1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it
11 under the terms of the GNU General Public License as published
12 by the Free Software Foundation; either version 2, or (at your
13 option) any later version.
15 GCC is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
23 Boston, MA 02110-1301, USA. */
27 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
38 #include "insn-attr.h"
49 #include "integrate.h"
52 #include "target-def.h"
54 #include "langhooks.h"
57 /* Forward definitions of types. */
58 typedef struct minipool_node Mnode;
59 typedef struct minipool_fixup Mfix;
61 const struct attribute_spec arm_attribute_table[];
63 /* Forward function declarations. */
64 static arm_stack_offsets *arm_get_frame_offsets (void);
65 static void arm_add_gc_roots (void);
66 static int arm_gen_constant (enum rtx_code, enum machine_mode, rtx,
67 HOST_WIDE_INT, rtx, rtx, int, int);
68 static unsigned bit_count (unsigned long);
69 static int arm_address_register_rtx_p (rtx, int);
70 static int arm_legitimate_index_p (enum machine_mode, rtx, RTX_CODE, int);
71 static int thumb2_legitimate_index_p (enum machine_mode, rtx, int);
72 static int thumb1_base_register_rtx_p (rtx, enum machine_mode, int);
73 inline static int thumb1_index_register_rtx_p (rtx, int);
74 static int thumb_far_jump_used_p (void);
75 static bool thumb_force_lr_save (void);
76 static unsigned long thumb1_compute_save_reg_mask (void);
77 static int const_ok_for_op (HOST_WIDE_INT, enum rtx_code);
78 static rtx emit_sfm (int, int);
79 static int arm_size_return_regs (void);
81 static bool arm_assemble_integer (rtx, unsigned int, int);
83 static const char *fp_const_from_val (REAL_VALUE_TYPE *);
84 static arm_cc get_arm_condition_code (rtx);
85 static HOST_WIDE_INT int_log2 (HOST_WIDE_INT);
86 static rtx is_jump_table (rtx);
87 static const char *output_multi_immediate (rtx *, const char *, const char *,
89 static const char *shift_op (rtx, HOST_WIDE_INT *);
90 static struct machine_function *arm_init_machine_status (void);
91 static void thumb_exit (FILE *, int);
92 static rtx is_jump_table (rtx);
93 static HOST_WIDE_INT get_jump_table_size (rtx);
94 static Mnode *move_minipool_fix_forward_ref (Mnode *, Mnode *, HOST_WIDE_INT);
95 static Mnode *add_minipool_forward_ref (Mfix *);
96 static Mnode *move_minipool_fix_backward_ref (Mnode *, Mnode *, HOST_WIDE_INT);
97 static Mnode *add_minipool_backward_ref (Mfix *);
98 static void assign_minipool_offsets (Mfix *);
99 static void arm_print_value (FILE *, rtx);
100 static void dump_minipool (rtx);
101 static int arm_barrier_cost (rtx);
102 static Mfix *create_fix_barrier (Mfix *, HOST_WIDE_INT);
103 static void push_minipool_barrier (rtx, HOST_WIDE_INT);
104 static void push_minipool_fix (rtx, HOST_WIDE_INT, rtx *, enum machine_mode,
106 static void arm_reorg (void);
107 static bool note_invalid_constants (rtx, HOST_WIDE_INT, int);
108 static unsigned long arm_compute_save_reg0_reg12_mask (void);
109 static unsigned long arm_compute_save_reg_mask (void);
110 static unsigned long arm_isr_value (tree);
111 static unsigned long arm_compute_func_type (void);
112 static tree arm_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
113 static tree arm_handle_isr_attribute (tree *, tree, tree, int, bool *);
114 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
115 static tree arm_handle_notshared_attribute (tree *, tree, tree, int, bool *);
117 static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT);
118 static void arm_output_function_prologue (FILE *, HOST_WIDE_INT);
119 static void thumb1_output_function_prologue (FILE *, HOST_WIDE_INT);
120 static int arm_comp_type_attributes (tree, tree);
121 static void arm_set_default_type_attributes (tree);
122 static int arm_adjust_cost (rtx, rtx, rtx, int);
123 static int count_insns_for_constant (HOST_WIDE_INT, int);
124 static int arm_get_strip_length (int);
125 static bool arm_function_ok_for_sibcall (tree, tree);
126 static void arm_internal_label (FILE *, const char *, unsigned long);
127 static void arm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
129 static int arm_rtx_costs_1 (rtx, enum rtx_code, enum rtx_code);
130 static bool arm_size_rtx_costs (rtx, int, int, int *);
131 static bool arm_slowmul_rtx_costs (rtx, int, int, int *);
132 static bool arm_fastmul_rtx_costs (rtx, int, int, int *);
133 static bool arm_xscale_rtx_costs (rtx, int, int, int *);
134 static bool arm_9e_rtx_costs (rtx, int, int, int *);
135 static int arm_address_cost (rtx);
136 static bool arm_memory_load_p (rtx);
137 static bool arm_cirrus_insn_p (rtx);
138 static void cirrus_reorg (rtx);
139 static void arm_init_builtins (void);
140 static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
141 static void arm_init_iwmmxt_builtins (void);
142 static rtx safe_vector_operand (rtx, enum machine_mode);
143 static rtx arm_expand_binop_builtin (enum insn_code, tree, rtx);
144 static rtx arm_expand_unop_builtin (enum insn_code, tree, rtx, int);
145 static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
146 static void emit_constant_insn (rtx cond, rtx pattern);
147 static rtx emit_set_insn (rtx, rtx);
148 static int arm_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
151 #ifdef OBJECT_FORMAT_ELF
152 static void arm_elf_asm_constructor (rtx, int) ATTRIBUTE_UNUSED;
153 static void arm_elf_asm_destructor (rtx, int) ATTRIBUTE_UNUSED;
156 static void arm_encode_section_info (tree, rtx, int);
159 static void arm_file_end (void);
160 static void arm_file_start (void);
163 static void aof_globalize_label (FILE *, const char *);
164 static void aof_dump_imports (FILE *);
165 static void aof_dump_pic_table (FILE *);
166 static void aof_file_start (void);
167 static void aof_file_end (void);
168 static void aof_asm_init_sections (void);
170 static void arm_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
172 static bool arm_pass_by_reference (CUMULATIVE_ARGS *,
173 enum machine_mode, tree, bool);
174 static bool arm_promote_prototypes (tree);
175 static bool arm_default_short_enums (void);
176 static bool arm_align_anon_bitfield (void);
177 static bool arm_return_in_msb (tree);
178 static bool arm_must_pass_in_stack (enum machine_mode, tree);
179 #ifdef TARGET_UNWIND_INFO
180 static void arm_unwind_emit (FILE *, rtx);
181 static bool arm_output_ttype (rtx);
183 static void arm_dwarf_handle_frame_unspec (const char *, rtx, int);
185 static tree arm_cxx_guard_type (void);
186 static bool arm_cxx_guard_mask_bit (void);
187 static tree arm_get_cookie_size (tree);
188 static bool arm_cookie_has_size (void);
189 static bool arm_cxx_cdtor_returns_this (void);
190 static bool arm_cxx_key_method_may_be_inline (void);
191 static void arm_cxx_determine_class_data_visibility (tree);
192 static bool arm_cxx_class_data_always_comdat (void);
193 static bool arm_cxx_use_aeabi_atexit (void);
194 static void arm_init_libfuncs (void);
195 static bool arm_handle_option (size_t, const char *, int);
196 static void arm_target_help (void);
197 static unsigned HOST_WIDE_INT arm_shift_truncation_mask (enum machine_mode);
198 static bool arm_cannot_copy_insn_p (rtx);
199 static bool arm_tls_symbol_p (rtx x);
200 static void arm_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
203 /* Initialize the GCC target structure. */
204 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
205 #undef TARGET_MERGE_DECL_ATTRIBUTES
206 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
209 #undef TARGET_ATTRIBUTE_TABLE
210 #define TARGET_ATTRIBUTE_TABLE arm_attribute_table
212 #undef TARGET_ASM_FILE_START
213 #define TARGET_ASM_FILE_START arm_file_start
214 #undef TARGET_ASM_FILE_END
215 #define TARGET_ASM_FILE_END arm_file_end
218 #undef TARGET_ASM_BYTE_OP
219 #define TARGET_ASM_BYTE_OP "\tDCB\t"
220 #undef TARGET_ASM_ALIGNED_HI_OP
221 #define TARGET_ASM_ALIGNED_HI_OP "\tDCW\t"
222 #undef TARGET_ASM_ALIGNED_SI_OP
223 #define TARGET_ASM_ALIGNED_SI_OP "\tDCD\t"
224 #undef TARGET_ASM_GLOBALIZE_LABEL
225 #define TARGET_ASM_GLOBALIZE_LABEL aof_globalize_label
226 #undef TARGET_ASM_FILE_START
227 #define TARGET_ASM_FILE_START aof_file_start
228 #undef TARGET_ASM_FILE_END
229 #define TARGET_ASM_FILE_END aof_file_end
231 #undef TARGET_ASM_ALIGNED_SI_OP
232 #define TARGET_ASM_ALIGNED_SI_OP NULL
233 #undef TARGET_ASM_INTEGER
234 #define TARGET_ASM_INTEGER arm_assemble_integer
237 #undef TARGET_ASM_FUNCTION_PROLOGUE
238 #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue
240 #undef TARGET_ASM_FUNCTION_EPILOGUE
241 #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue
243 #undef TARGET_DEFAULT_TARGET_FLAGS
244 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_SCHED_PROLOG)
245 #undef TARGET_HANDLE_OPTION
246 #define TARGET_HANDLE_OPTION arm_handle_option
248 #define TARGET_HELP arm_target_help
250 #undef TARGET_COMP_TYPE_ATTRIBUTES
251 #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes
253 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
254 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes
256 #undef TARGET_SCHED_ADJUST_COST
257 #define TARGET_SCHED_ADJUST_COST arm_adjust_cost
259 #undef TARGET_ENCODE_SECTION_INFO
261 #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info
263 #define TARGET_ENCODE_SECTION_INFO arm_encode_section_info
266 #undef TARGET_STRIP_NAME_ENCODING
267 #define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding
269 #undef TARGET_ASM_INTERNAL_LABEL
270 #define TARGET_ASM_INTERNAL_LABEL arm_internal_label
272 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
273 #define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall
275 #undef TARGET_ASM_OUTPUT_MI_THUNK
276 #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk
277 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
278 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
280 /* This will be overridden in arm_override_options. */
281 #undef TARGET_RTX_COSTS
282 #define TARGET_RTX_COSTS arm_slowmul_rtx_costs
283 #undef TARGET_ADDRESS_COST
284 #define TARGET_ADDRESS_COST arm_address_cost
286 #undef TARGET_SHIFT_TRUNCATION_MASK
287 #define TARGET_SHIFT_TRUNCATION_MASK arm_shift_truncation_mask
288 #undef TARGET_VECTOR_MODE_SUPPORTED_P
289 #define TARGET_VECTOR_MODE_SUPPORTED_P arm_vector_mode_supported_p
291 #undef TARGET_MACHINE_DEPENDENT_REORG
292 #define TARGET_MACHINE_DEPENDENT_REORG arm_reorg
294 #undef TARGET_INIT_BUILTINS
295 #define TARGET_INIT_BUILTINS arm_init_builtins
296 #undef TARGET_EXPAND_BUILTIN
297 #define TARGET_EXPAND_BUILTIN arm_expand_builtin
299 #undef TARGET_INIT_LIBFUNCS
300 #define TARGET_INIT_LIBFUNCS arm_init_libfuncs
302 #undef TARGET_PROMOTE_FUNCTION_ARGS
303 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
304 #undef TARGET_PROMOTE_FUNCTION_RETURN
305 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
306 #undef TARGET_PROMOTE_PROTOTYPES
307 #define TARGET_PROMOTE_PROTOTYPES arm_promote_prototypes
308 #undef TARGET_PASS_BY_REFERENCE
309 #define TARGET_PASS_BY_REFERENCE arm_pass_by_reference
310 #undef TARGET_ARG_PARTIAL_BYTES
311 #define TARGET_ARG_PARTIAL_BYTES arm_arg_partial_bytes
313 #undef TARGET_SETUP_INCOMING_VARARGS
314 #define TARGET_SETUP_INCOMING_VARARGS arm_setup_incoming_varargs
316 #undef TARGET_DEFAULT_SHORT_ENUMS
317 #define TARGET_DEFAULT_SHORT_ENUMS arm_default_short_enums
319 #undef TARGET_ALIGN_ANON_BITFIELD
320 #define TARGET_ALIGN_ANON_BITFIELD arm_align_anon_bitfield
322 #undef TARGET_NARROW_VOLATILE_BITFIELD
323 #define TARGET_NARROW_VOLATILE_BITFIELD hook_bool_void_false
325 #undef TARGET_CXX_GUARD_TYPE
326 #define TARGET_CXX_GUARD_TYPE arm_cxx_guard_type
328 #undef TARGET_CXX_GUARD_MASK_BIT
329 #define TARGET_CXX_GUARD_MASK_BIT arm_cxx_guard_mask_bit
331 #undef TARGET_CXX_GET_COOKIE_SIZE
332 #define TARGET_CXX_GET_COOKIE_SIZE arm_get_cookie_size
334 #undef TARGET_CXX_COOKIE_HAS_SIZE
335 #define TARGET_CXX_COOKIE_HAS_SIZE arm_cookie_has_size
337 #undef TARGET_CXX_CDTOR_RETURNS_THIS
338 #define TARGET_CXX_CDTOR_RETURNS_THIS arm_cxx_cdtor_returns_this
340 #undef TARGET_CXX_KEY_METHOD_MAY_BE_INLINE
341 #define TARGET_CXX_KEY_METHOD_MAY_BE_INLINE arm_cxx_key_method_may_be_inline
343 #undef TARGET_CXX_USE_AEABI_ATEXIT
344 #define TARGET_CXX_USE_AEABI_ATEXIT arm_cxx_use_aeabi_atexit
346 #undef TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY
347 #define TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY \
348 arm_cxx_determine_class_data_visibility
350 #undef TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT
351 #define TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT arm_cxx_class_data_always_comdat
353 #undef TARGET_RETURN_IN_MSB
354 #define TARGET_RETURN_IN_MSB arm_return_in_msb
356 #undef TARGET_MUST_PASS_IN_STACK
357 #define TARGET_MUST_PASS_IN_STACK arm_must_pass_in_stack
359 #ifdef TARGET_UNWIND_INFO
360 #undef TARGET_UNWIND_EMIT
361 #define TARGET_UNWIND_EMIT arm_unwind_emit
363 /* EABI unwinding tables use a different format for the typeinfo tables. */
364 #undef TARGET_ASM_TTYPE
365 #define TARGET_ASM_TTYPE arm_output_ttype
367 #undef TARGET_ARM_EABI_UNWINDER
368 #define TARGET_ARM_EABI_UNWINDER true
369 #endif /* TARGET_UNWIND_INFO */
371 #undef TARGET_DWARF_HANDLE_FRAME_UNSPEC
372 #define TARGET_DWARF_HANDLE_FRAME_UNSPEC arm_dwarf_handle_frame_unspec
374 #undef TARGET_CANNOT_COPY_INSN_P
375 #define TARGET_CANNOT_COPY_INSN_P arm_cannot_copy_insn_p
378 #undef TARGET_HAVE_TLS
379 #define TARGET_HAVE_TLS true
382 #undef TARGET_CANNOT_FORCE_CONST_MEM
383 #define TARGET_CANNOT_FORCE_CONST_MEM arm_tls_referenced_p
386 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
387 #define TARGET_ASM_OUTPUT_DWARF_DTPREL arm_output_dwarf_dtprel
390 struct gcc_target targetm = TARGET_INITIALIZER;
392 /* Obstack for minipool constant handling. */
393 static struct obstack minipool_obstack;
394 static char * minipool_startobj;
396 /* The maximum number of insns skipped which
397 will be conditionalised if possible. */
398 static int max_insns_skipped = 5;
400 extern FILE * asm_out_file;
402 /* True if we are currently building a constant table. */
403 int making_const_table;
405 /* Define the information needed to generate branch insns. This is
406 stored from the compare operation. */
407 rtx arm_compare_op0, arm_compare_op1;
409 /* The processor for which instructions should be scheduled. */
410 enum processor_type arm_tune = arm_none;
412 /* The default processor used if not overridden by commandline. */
413 static enum processor_type arm_default_cpu = arm_none;
415 /* Which floating point model to use. */
416 enum arm_fp_model arm_fp_model;
418 /* Which floating point hardware is available. */
419 enum fputype arm_fpu_arch;
421 /* Which floating point hardware to schedule for. */
422 enum fputype arm_fpu_tune;
424 /* Whether to use floating point hardware. */
425 enum float_abi_type arm_float_abi;
427 /* Which ABI to use. */
428 enum arm_abi_type arm_abi;
430 /* Which thread pointer model to use. */
431 enum arm_tp_type target_thread_pointer = TP_AUTO;
433 /* Used to parse -mstructure_size_boundary command line option. */
434 int arm_structure_size_boundary = DEFAULT_STRUCTURE_SIZE_BOUNDARY;
436 /* Used for Thumb call_via trampolines. */
437 rtx thumb_call_via_label[14];
438 static int thumb_call_reg_needed;
440 /* Bit values used to identify processor capabilities. */
441 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
442 #define FL_ARCH3M (1 << 1) /* Extended multiply */
443 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
444 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
445 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
446 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
447 #define FL_THUMB (1 << 6) /* Thumb aware */
448 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
449 #define FL_STRONG (1 << 8) /* StrongARM */
450 #define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */
451 #define FL_XSCALE (1 << 10) /* XScale */
452 #define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */
453 #define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds
454 media instructions. */
455 #define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */
456 #define FL_WBUF (1 << 14) /* Schedule for write buffer ops.
457 Note: ARM6 & 7 derivatives only. */
458 #define FL_ARCH6K (1 << 15) /* Architecture rel 6 K extensions. */
459 #define FL_THUMB2 (1 << 16) /* Thumb-2. */
460 #define FL_NOTM (1 << 17) /* Instructions not present in the 'M'
462 #define FL_DIV (1 << 18) /* Hardware divide. */
463 #define FL_VFPV3 (1 << 19) /* Vector Floating Point V3. */
465 #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
467 #define FL_FOR_ARCH2 FL_NOTM
468 #define FL_FOR_ARCH3 (FL_FOR_ARCH2 | FL_MODE32)
469 #define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M)
470 #define FL_FOR_ARCH4 (FL_FOR_ARCH3M | FL_ARCH4)
471 #define FL_FOR_ARCH4T (FL_FOR_ARCH4 | FL_THUMB)
472 #define FL_FOR_ARCH5 (FL_FOR_ARCH4 | FL_ARCH5)
473 #define FL_FOR_ARCH5T (FL_FOR_ARCH5 | FL_THUMB)
474 #define FL_FOR_ARCH5E (FL_FOR_ARCH5 | FL_ARCH5E)
475 #define FL_FOR_ARCH5TE (FL_FOR_ARCH5E | FL_THUMB)
476 #define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE
477 #define FL_FOR_ARCH6 (FL_FOR_ARCH5TE | FL_ARCH6)
478 #define FL_FOR_ARCH6J FL_FOR_ARCH6
479 #define FL_FOR_ARCH6K (FL_FOR_ARCH6 | FL_ARCH6K)
480 #define FL_FOR_ARCH6Z FL_FOR_ARCH6
481 #define FL_FOR_ARCH6ZK FL_FOR_ARCH6K
482 #define FL_FOR_ARCH6T2 (FL_FOR_ARCH6 | FL_THUMB2)
483 #define FL_FOR_ARCH7 (FL_FOR_ARCH6T2 &~ FL_NOTM)
484 #define FL_FOR_ARCH7A (FL_FOR_ARCH7 | FL_NOTM)
485 #define FL_FOR_ARCH7R (FL_FOR_ARCH7A | FL_DIV)
486 #define FL_FOR_ARCH7M (FL_FOR_ARCH7 | FL_DIV)
488 /* The bits in this mask specify which
489 instructions we are allowed to generate. */
490 static unsigned long insn_flags = 0;
492 /* The bits in this mask specify which instruction scheduling options should
494 static unsigned long tune_flags = 0;
496 /* The following are used in the arm.md file as equivalents to bits
497 in the above two flag variables. */
499 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
502 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
505 /* Nonzero if this chip supports the ARM Architecture 4t extensions. */
508 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
511 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
514 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
517 /* Nonzero if this chip supports the ARM 6K extensions. */
520 /* Nonzero if instructions not present in the 'M' profile can be used. */
521 int arm_arch_notm = 0;
523 /* Nonzero if this chip can benefit from load scheduling. */
524 int arm_ld_sched = 0;
526 /* Nonzero if this chip is a StrongARM. */
527 int arm_tune_strongarm = 0;
529 /* Nonzero if this chip is a Cirrus variant. */
530 int arm_arch_cirrus = 0;
532 /* Nonzero if this chip supports Intel Wireless MMX technology. */
533 int arm_arch_iwmmxt = 0;
535 /* Nonzero if this chip is an XScale. */
536 int arm_arch_xscale = 0;
538 /* Nonzero if tuning for XScale */
539 int arm_tune_xscale = 0;
541 /* Nonzero if we want to tune for stores that access the write-buffer.
542 This typically means an ARM6 or ARM7 with MMU or MPU. */
543 int arm_tune_wbuf = 0;
545 /* Nonzero if generating Thumb instructions. */
548 /* Nonzero if we should define __THUMB_INTERWORK__ in the
550 XXX This is a bit of a hack, it's intended to help work around
551 problems in GLD which doesn't understand that armv5t code is
552 interworking clean. */
553 int arm_cpp_interwork = 0;
555 /* Nonzero if chip supports Thumb 2. */
558 /* Nonzero if chip supports integer division instruction. */
561 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
562 must report the mode of the memory reference from PRINT_OPERAND to
563 PRINT_OPERAND_ADDRESS. */
564 enum machine_mode output_memory_reference_mode;
566 /* The register number to be used for the PIC offset register. */
567 unsigned arm_pic_register = INVALID_REGNUM;
569 /* Set to 1 when a return insn is output, this means that the epilogue
571 int return_used_this_function;
573 /* Set to 1 after arm_reorg has started. Reset to start at the start of
574 the next function. */
575 static int after_arm_reorg = 0;
577 /* The maximum number of insns to be used when loading a constant. */
578 static int arm_constant_limit = 3;
580 /* For an explanation of these variables, see final_prescan_insn below. */
582 /* arm_current_cc is also used for Thumb-2 cond_exec blocks. */
583 enum arm_cond_code arm_current_cc;
585 int arm_target_label;
586 /* The number of conditionally executed insns, including the current insn. */
587 int arm_condexec_count = 0;
588 /* A bitmask specifying the patterns for the IT block.
589 Zero means do not output an IT block before this insn. */
590 int arm_condexec_mask = 0;
591 /* The number of bits used in arm_condexec_mask. */
592 int arm_condexec_masklen = 0;
594 /* The condition codes of the ARM, and the inverse function. */
595 static const char * const arm_condition_codes[] =
597 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
598 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
601 #define ARM_LSL_NAME (TARGET_UNIFIED_ASM ? "lsl" : "asl")
602 #define streq(string1, string2) (strcmp (string1, string2) == 0)
604 #define THUMB2_WORK_REGS (0xff & ~( (1 << THUMB_HARD_FRAME_POINTER_REGNUM) \
605 | (1 << SP_REGNUM) | (1 << PC_REGNUM) \
606 | (1 << PIC_OFFSET_TABLE_REGNUM)))
608 /* Initialization code. */
612 const char *const name;
613 enum processor_type core;
615 const unsigned long flags;
616 bool (* rtx_costs) (rtx, int, int, int *);
619 /* Not all of these give usefully different compilation alternatives,
620 but there is no simple way of generalizing them. */
621 static const struct processors all_cores[] =
624 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \
625 {NAME, arm_none, #ARCH, FLAGS | FL_FOR_ARCH##ARCH, arm_##COSTS##_rtx_costs},
626 #include "arm-cores.def"
628 {NULL, arm_none, NULL, 0, NULL}
631 static const struct processors all_architectures[] =
633 /* ARM Architectures */
634 /* We don't specify rtx_costs here as it will be figured out
637 {"armv2", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL},
638 {"armv2a", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL},
639 {"armv3", arm6, "3", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3, NULL},
640 {"armv3m", arm7m, "3M", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3M, NULL},
641 {"armv4", arm7tdmi, "4", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH4, NULL},
642 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
643 implementations that support it, so we will leave it out for now. */
644 {"armv4t", arm7tdmi, "4T", FL_CO_PROC | FL_FOR_ARCH4T, NULL},
645 {"armv5", arm10tdmi, "5", FL_CO_PROC | FL_FOR_ARCH5, NULL},
646 {"armv5t", arm10tdmi, "5T", FL_CO_PROC | FL_FOR_ARCH5T, NULL},
647 {"armv5e", arm1026ejs, "5E", FL_CO_PROC | FL_FOR_ARCH5E, NULL},
648 {"armv5te", arm1026ejs, "5TE", FL_CO_PROC | FL_FOR_ARCH5TE, NULL},
649 {"armv6", arm1136js, "6", FL_CO_PROC | FL_FOR_ARCH6, NULL},
650 {"armv6j", arm1136js, "6J", FL_CO_PROC | FL_FOR_ARCH6J, NULL},
651 {"armv6k", mpcore, "6K", FL_CO_PROC | FL_FOR_ARCH6K, NULL},
652 {"armv6z", arm1176jzs, "6Z", FL_CO_PROC | FL_FOR_ARCH6Z, NULL},
653 {"armv6zk", arm1176jzs, "6ZK", FL_CO_PROC | FL_FOR_ARCH6ZK, NULL},
654 {"armv6t2", arm1156t2s, "6T2", FL_CO_PROC | FL_FOR_ARCH6T2, NULL},
655 {"armv7", cortexa8, "7", FL_CO_PROC | FL_FOR_ARCH7, NULL},
656 {"armv7-a", cortexa8, "7A", FL_CO_PROC | FL_FOR_ARCH7A, NULL},
657 {"armv7-r", cortexr4, "7R", FL_CO_PROC | FL_FOR_ARCH7R, NULL},
658 {"armv7-m", cortexm3, "7M", FL_CO_PROC | FL_FOR_ARCH7M, NULL},
659 {"ep9312", ep9312, "4T", FL_LDSCHED | FL_CIRRUS | FL_FOR_ARCH4, NULL},
660 {"iwmmxt", iwmmxt, "5TE", FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT , NULL},
661 {NULL, arm_none, NULL, 0 , NULL}
664 struct arm_cpu_select
668 const struct processors * processors;
671 /* This is a magic structure. The 'string' field is magically filled in
672 with a pointer to the value specified by the user on the command line
673 assuming that the user has specified such a value. */
675 static struct arm_cpu_select arm_select[] =
677 /* string name processors */
678 { NULL, "-mcpu=", all_cores },
679 { NULL, "-march=", all_architectures },
680 { NULL, "-mtune=", all_cores }
683 /* Defines representing the indexes into the above table. */
684 #define ARM_OPT_SET_CPU 0
685 #define ARM_OPT_SET_ARCH 1
686 #define ARM_OPT_SET_TUNE 2
688 /* The name of the preprocessor macro to define for this architecture. */
690 char arm_arch_name[] = "__ARM_ARCH_0UNK__";
699 /* Available values for -mfpu=. */
701 static const struct fpu_desc all_fpus[] =
703 {"fpa", FPUTYPE_FPA},
704 {"fpe2", FPUTYPE_FPA_EMU2},
705 {"fpe3", FPUTYPE_FPA_EMU2},
706 {"maverick", FPUTYPE_MAVERICK},
707 {"vfp", FPUTYPE_VFP},
708 {"vfp3", FPUTYPE_VFP3},
712 /* Floating point models used by the different hardware.
713 See fputype in arm.h. */
715 static const enum fputype fp_model_for_fpu[] =
717 /* No FP hardware. */
718 ARM_FP_MODEL_UNKNOWN, /* FPUTYPE_NONE */
719 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA */
720 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA_EMU2 */
721 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA_EMU3 */
722 ARM_FP_MODEL_MAVERICK, /* FPUTYPE_MAVERICK */
723 ARM_FP_MODEL_VFP, /* FPUTYPE_VFP */
724 ARM_FP_MODEL_VFP /* FPUTYPE_VFP3 */
731 enum float_abi_type abi_type;
735 /* Available values for -mfloat-abi=. */
737 static const struct float_abi all_float_abis[] =
739 {"soft", ARM_FLOAT_ABI_SOFT},
740 {"softfp", ARM_FLOAT_ABI_SOFTFP},
741 {"hard", ARM_FLOAT_ABI_HARD}
748 enum arm_abi_type abi_type;
752 /* Available values for -mabi=. */
754 static const struct abi_name arm_all_abis[] =
756 {"apcs-gnu", ARM_ABI_APCS},
757 {"atpcs", ARM_ABI_ATPCS},
758 {"aapcs", ARM_ABI_AAPCS},
759 {"iwmmxt", ARM_ABI_IWMMXT},
760 {"aapcs-linux", ARM_ABI_AAPCS_LINUX}
763 /* Supported TLS relocations. */
773 /* Emit an insn that's a simple single-set. Both the operands must be known
776 emit_set_insn (rtx x, rtx y)
778 return emit_insn (gen_rtx_SET (VOIDmode, x, y));
781 /* Return the number of bits set in VALUE. */
783 bit_count (unsigned long value)
785 unsigned long count = 0;
790 value &= value - 1; /* Clear the least-significant set bit. */
796 /* Set up library functions unique to ARM. */
799 arm_init_libfuncs (void)
801 /* There are no special library functions unless we are using the
806 /* The functions below are described in Section 4 of the "Run-Time
807 ABI for the ARM architecture", Version 1.0. */
809 /* Double-precision floating-point arithmetic. Table 2. */
810 set_optab_libfunc (add_optab, DFmode, "__aeabi_dadd");
811 set_optab_libfunc (sdiv_optab, DFmode, "__aeabi_ddiv");
812 set_optab_libfunc (smul_optab, DFmode, "__aeabi_dmul");
813 set_optab_libfunc (neg_optab, DFmode, "__aeabi_dneg");
814 set_optab_libfunc (sub_optab, DFmode, "__aeabi_dsub");
816 /* Double-precision comparisons. Table 3. */
817 set_optab_libfunc (eq_optab, DFmode, "__aeabi_dcmpeq");
818 set_optab_libfunc (ne_optab, DFmode, NULL);
819 set_optab_libfunc (lt_optab, DFmode, "__aeabi_dcmplt");
820 set_optab_libfunc (le_optab, DFmode, "__aeabi_dcmple");
821 set_optab_libfunc (ge_optab, DFmode, "__aeabi_dcmpge");
822 set_optab_libfunc (gt_optab, DFmode, "__aeabi_dcmpgt");
823 set_optab_libfunc (unord_optab, DFmode, "__aeabi_dcmpun");
825 /* Single-precision floating-point arithmetic. Table 4. */
826 set_optab_libfunc (add_optab, SFmode, "__aeabi_fadd");
827 set_optab_libfunc (sdiv_optab, SFmode, "__aeabi_fdiv");
828 set_optab_libfunc (smul_optab, SFmode, "__aeabi_fmul");
829 set_optab_libfunc (neg_optab, SFmode, "__aeabi_fneg");
830 set_optab_libfunc (sub_optab, SFmode, "__aeabi_fsub");
832 /* Single-precision comparisons. Table 5. */
833 set_optab_libfunc (eq_optab, SFmode, "__aeabi_fcmpeq");
834 set_optab_libfunc (ne_optab, SFmode, NULL);
835 set_optab_libfunc (lt_optab, SFmode, "__aeabi_fcmplt");
836 set_optab_libfunc (le_optab, SFmode, "__aeabi_fcmple");
837 set_optab_libfunc (ge_optab, SFmode, "__aeabi_fcmpge");
838 set_optab_libfunc (gt_optab, SFmode, "__aeabi_fcmpgt");
839 set_optab_libfunc (unord_optab, SFmode, "__aeabi_fcmpun");
841 /* Floating-point to integer conversions. Table 6. */
842 set_conv_libfunc (sfix_optab, SImode, DFmode, "__aeabi_d2iz");
843 set_conv_libfunc (ufix_optab, SImode, DFmode, "__aeabi_d2uiz");
844 set_conv_libfunc (sfix_optab, DImode, DFmode, "__aeabi_d2lz");
845 set_conv_libfunc (ufix_optab, DImode, DFmode, "__aeabi_d2ulz");
846 set_conv_libfunc (sfix_optab, SImode, SFmode, "__aeabi_f2iz");
847 set_conv_libfunc (ufix_optab, SImode, SFmode, "__aeabi_f2uiz");
848 set_conv_libfunc (sfix_optab, DImode, SFmode, "__aeabi_f2lz");
849 set_conv_libfunc (ufix_optab, DImode, SFmode, "__aeabi_f2ulz");
851 /* Conversions between floating types. Table 7. */
852 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__aeabi_d2f");
853 set_conv_libfunc (sext_optab, DFmode, SFmode, "__aeabi_f2d");
855 /* Integer to floating-point conversions. Table 8. */
856 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__aeabi_i2d");
857 set_conv_libfunc (ufloat_optab, DFmode, SImode, "__aeabi_ui2d");
858 set_conv_libfunc (sfloat_optab, DFmode, DImode, "__aeabi_l2d");
859 set_conv_libfunc (ufloat_optab, DFmode, DImode, "__aeabi_ul2d");
860 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__aeabi_i2f");
861 set_conv_libfunc (ufloat_optab, SFmode, SImode, "__aeabi_ui2f");
862 set_conv_libfunc (sfloat_optab, SFmode, DImode, "__aeabi_l2f");
863 set_conv_libfunc (ufloat_optab, SFmode, DImode, "__aeabi_ul2f");
865 /* Long long. Table 9. */
866 set_optab_libfunc (smul_optab, DImode, "__aeabi_lmul");
867 set_optab_libfunc (sdivmod_optab, DImode, "__aeabi_ldivmod");
868 set_optab_libfunc (udivmod_optab, DImode, "__aeabi_uldivmod");
869 set_optab_libfunc (ashl_optab, DImode, "__aeabi_llsl");
870 set_optab_libfunc (lshr_optab, DImode, "__aeabi_llsr");
871 set_optab_libfunc (ashr_optab, DImode, "__aeabi_lasr");
872 set_optab_libfunc (cmp_optab, DImode, "__aeabi_lcmp");
873 set_optab_libfunc (ucmp_optab, DImode, "__aeabi_ulcmp");
875 /* Integer (32/32->32) division. \S 4.3.1. */
876 set_optab_libfunc (sdivmod_optab, SImode, "__aeabi_idivmod");
877 set_optab_libfunc (udivmod_optab, SImode, "__aeabi_uidivmod");
879 /* The divmod functions are designed so that they can be used for
880 plain division, even though they return both the quotient and the
881 remainder. The quotient is returned in the usual location (i.e.,
882 r0 for SImode, {r0, r1} for DImode), just as would be expected
883 for an ordinary division routine. Because the AAPCS calling
884 conventions specify that all of { r0, r1, r2, r3 } are
885 callee-saved registers, there is no need to tell the compiler
886 explicitly that those registers are clobbered by these
888 set_optab_libfunc (sdiv_optab, DImode, "__aeabi_ldivmod");
889 set_optab_libfunc (udiv_optab, DImode, "__aeabi_uldivmod");
891 /* For SImode division the ABI provides div-without-mod routines,
893 set_optab_libfunc (sdiv_optab, SImode, "__aeabi_idiv");
894 set_optab_libfunc (udiv_optab, SImode, "__aeabi_uidiv");
896 /* We don't have mod libcalls. Fortunately gcc knows how to use the
897 divmod libcalls instead. */
898 set_optab_libfunc (smod_optab, DImode, NULL);
899 set_optab_libfunc (umod_optab, DImode, NULL);
900 set_optab_libfunc (smod_optab, SImode, NULL);
901 set_optab_libfunc (umod_optab, SImode, NULL);
904 /* Implement TARGET_HANDLE_OPTION. */
907 arm_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
912 arm_select[1].string = arg;
916 arm_select[0].string = arg;
919 case OPT_mhard_float:
920 target_float_abi_name = "hard";
923 case OPT_msoft_float:
924 target_float_abi_name = "soft";
928 arm_select[2].string = arg;
937 arm_target_help (void)
940 static int columns = 0;
943 /* If we have not done so already, obtain the desired maximum width of
944 the output. Note - this is a duplication of the code at the start of
945 gcc/opts.c:print_specific_help() - the two copies should probably be
946 replaced by a single function. */
951 GET_ENVIRONMENT (p, "COLUMNS");
954 int value = atoi (p);
961 /* Use a reasonable default. */
965 printf (" Known ARM CPUs (for use with the -mcpu= and -mtune= options):\n");
967 /* The - 2 is because we know that the last entry in the array is NULL. */
968 i = ARRAY_SIZE (all_cores) - 2;
970 printf (" %s", all_cores[i].name);
971 remaining = columns - (strlen (all_cores[i].name) + 4);
972 gcc_assert (remaining >= 0);
976 int len = strlen (all_cores[i].name);
978 if (remaining > len + 2)
980 printf (", %s", all_cores[i].name);
981 remaining -= len + 2;
987 printf ("\n %s", all_cores[i].name);
988 remaining = columns - (len + 4);
992 printf ("\n\n Known ARM architectures (for use with the -march= option):\n");
994 i = ARRAY_SIZE (all_architectures) - 2;
997 printf (" %s", all_architectures[i].name);
998 remaining = columns - (strlen (all_architectures[i].name) + 4);
999 gcc_assert (remaining >= 0);
1003 int len = strlen (all_architectures[i].name);
1005 if (remaining > len + 2)
1007 printf (", %s", all_architectures[i].name);
1008 remaining -= len + 2;
1014 printf ("\n %s", all_architectures[i].name);
1015 remaining = columns - (len + 4);
1022 /* Fix up any incompatible options that the user has specified.
1023 This has now turned into a maze. */
1025 arm_override_options (void)
1028 enum processor_type target_arch_cpu = arm_none;
1030 /* Set up the flags based on the cpu/architecture selected by the user. */
1031 for (i = ARRAY_SIZE (arm_select); i--;)
1033 struct arm_cpu_select * ptr = arm_select + i;
1035 if (ptr->string != NULL && ptr->string[0] != '\0')
1037 const struct processors * sel;
1039 for (sel = ptr->processors; sel->name != NULL; sel++)
1040 if (streq (ptr->string, sel->name))
1042 /* Set the architecture define. */
1043 if (i != ARM_OPT_SET_TUNE)
1044 sprintf (arm_arch_name, "__ARM_ARCH_%s__", sel->arch);
1046 /* Determine the processor core for which we should
1047 tune code-generation. */
1048 if (/* -mcpu= is a sensible default. */
1049 i == ARM_OPT_SET_CPU
1050 /* -mtune= overrides -mcpu= and -march=. */
1051 || i == ARM_OPT_SET_TUNE)
1052 arm_tune = (enum processor_type) (sel - ptr->processors);
1054 /* Remember the CPU associated with this architecture.
1055 If no other option is used to set the CPU type,
1056 we'll use this to guess the most suitable tuning
1058 if (i == ARM_OPT_SET_ARCH)
1059 target_arch_cpu = sel->core;
1061 if (i != ARM_OPT_SET_TUNE)
1063 /* If we have been given an architecture and a processor
1064 make sure that they are compatible. We only generate
1065 a warning though, and we prefer the CPU over the
1067 if (insn_flags != 0 && (insn_flags ^ sel->flags))
1068 warning (0, "switch -mcpu=%s conflicts with -march= switch",
1071 insn_flags = sel->flags;
1077 if (sel->name == NULL)
1078 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
1082 /* Guess the tuning options from the architecture if necessary. */
1083 if (arm_tune == arm_none)
1084 arm_tune = target_arch_cpu;
1086 /* If the user did not specify a processor, choose one for them. */
1087 if (insn_flags == 0)
1089 const struct processors * sel;
1090 unsigned int sought;
1091 enum processor_type cpu;
1093 cpu = TARGET_CPU_DEFAULT;
1094 if (cpu == arm_none)
1096 #ifdef SUBTARGET_CPU_DEFAULT
1097 /* Use the subtarget default CPU if none was specified by
1099 cpu = SUBTARGET_CPU_DEFAULT;
1101 /* Default to ARM6. */
1102 if (cpu == arm_none)
1105 sel = &all_cores[cpu];
1107 insn_flags = sel->flags;
1109 /* Now check to see if the user has specified some command line
1110 switch that require certain abilities from the cpu. */
1113 if (TARGET_INTERWORK || TARGET_THUMB)
1115 sought |= (FL_THUMB | FL_MODE32);
1117 /* There are no ARM processors that support both APCS-26 and
1118 interworking. Therefore we force FL_MODE26 to be removed
1119 from insn_flags here (if it was set), so that the search
1120 below will always be able to find a compatible processor. */
1121 insn_flags &= ~FL_MODE26;
1124 if (sought != 0 && ((sought & insn_flags) != sought))
1126 /* Try to locate a CPU type that supports all of the abilities
1127 of the default CPU, plus the extra abilities requested by
1129 for (sel = all_cores; sel->name != NULL; sel++)
1130 if ((sel->flags & sought) == (sought | insn_flags))
1133 if (sel->name == NULL)
1135 unsigned current_bit_count = 0;
1136 const struct processors * best_fit = NULL;
1138 /* Ideally we would like to issue an error message here
1139 saying that it was not possible to find a CPU compatible
1140 with the default CPU, but which also supports the command
1141 line options specified by the programmer, and so they
1142 ought to use the -mcpu=<name> command line option to
1143 override the default CPU type.
1145 If we cannot find a cpu that has both the
1146 characteristics of the default cpu and the given
1147 command line options we scan the array again looking
1148 for a best match. */
1149 for (sel = all_cores; sel->name != NULL; sel++)
1150 if ((sel->flags & sought) == sought)
1154 count = bit_count (sel->flags & insn_flags);
1156 if (count >= current_bit_count)
1159 current_bit_count = count;
1163 gcc_assert (best_fit);
1167 insn_flags = sel->flags;
1169 sprintf (arm_arch_name, "__ARM_ARCH_%s__", sel->arch);
1170 arm_default_cpu = (enum processor_type) (sel - all_cores);
1171 if (arm_tune == arm_none)
1172 arm_tune = arm_default_cpu;
1175 /* The processor for which we should tune should now have been
1177 gcc_assert (arm_tune != arm_none);
1179 tune_flags = all_cores[(int)arm_tune].flags;
1181 targetm.rtx_costs = arm_size_rtx_costs;
1183 targetm.rtx_costs = all_cores[(int)arm_tune].rtx_costs;
1185 /* Make sure that the processor choice does not conflict with any of the
1186 other command line choices. */
1187 if (TARGET_ARM && !(insn_flags & FL_NOTM))
1188 error ("target CPU does not support ARM mode");
1190 if (TARGET_INTERWORK && !(insn_flags & FL_THUMB))
1192 warning (0, "target CPU does not support interworking" );
1193 target_flags &= ~MASK_INTERWORK;
1196 if (TARGET_THUMB && !(insn_flags & FL_THUMB))
1198 warning (0, "target CPU does not support THUMB instructions");
1199 target_flags &= ~MASK_THUMB;
1202 if (TARGET_APCS_FRAME && TARGET_THUMB)
1204 /* warning (0, "ignoring -mapcs-frame because -mthumb was used"); */
1205 target_flags &= ~MASK_APCS_FRAME;
1208 /* Callee super interworking implies thumb interworking. Adding
1209 this to the flags here simplifies the logic elsewhere. */
1210 if (TARGET_THUMB && TARGET_CALLEE_INTERWORKING)
1211 target_flags |= MASK_INTERWORK;
1213 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
1214 from here where no function is being compiled currently. */
1215 if ((TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME) && TARGET_ARM)
1216 warning (0, "enabling backtrace support is only meaningful when compiling for the Thumb");
1218 if (TARGET_ARM && TARGET_CALLEE_INTERWORKING)
1219 warning (0, "enabling callee interworking support is only meaningful when compiling for the Thumb");
1221 if (TARGET_ARM && TARGET_CALLER_INTERWORKING)
1222 warning (0, "enabling caller interworking support is only meaningful when compiling for the Thumb");
1224 if (TARGET_APCS_STACK && !TARGET_APCS_FRAME)
1226 warning (0, "-mapcs-stack-check incompatible with -mno-apcs-frame");
1227 target_flags |= MASK_APCS_FRAME;
1230 if (TARGET_POKE_FUNCTION_NAME)
1231 target_flags |= MASK_APCS_FRAME;
1233 if (TARGET_APCS_REENT && flag_pic)
1234 error ("-fpic and -mapcs-reent are incompatible");
1236 if (TARGET_APCS_REENT)
1237 warning (0, "APCS reentrant code not supported. Ignored");
1239 /* If this target is normally configured to use APCS frames, warn if they
1240 are turned off and debugging is turned on. */
1242 && write_symbols != NO_DEBUG
1243 && !TARGET_APCS_FRAME
1244 && (TARGET_DEFAULT & MASK_APCS_FRAME))
1245 warning (0, "-g with -mno-apcs-frame may not give sensible debugging");
1247 if (TARGET_APCS_FLOAT)
1248 warning (0, "passing floating point arguments in fp regs not yet supported");
1250 /* Initialize boolean versions of the flags, for use in the arm.md file. */
1251 arm_arch3m = (insn_flags & FL_ARCH3M) != 0;
1252 arm_arch4 = (insn_flags & FL_ARCH4) != 0;
1253 arm_arch4t = arm_arch4 & ((insn_flags & FL_THUMB) != 0);
1254 arm_arch5 = (insn_flags & FL_ARCH5) != 0;
1255 arm_arch5e = (insn_flags & FL_ARCH5E) != 0;
1256 arm_arch6 = (insn_flags & FL_ARCH6) != 0;
1257 arm_arch6k = (insn_flags & FL_ARCH6K) != 0;
1258 arm_arch_notm = (insn_flags & FL_NOTM) != 0;
1259 arm_arch_thumb2 = (insn_flags & FL_THUMB2) != 0;
1260 arm_arch_xscale = (insn_flags & FL_XSCALE) != 0;
1261 arm_arch_cirrus = (insn_flags & FL_CIRRUS) != 0;
1263 arm_ld_sched = (tune_flags & FL_LDSCHED) != 0;
1264 arm_tune_strongarm = (tune_flags & FL_STRONG) != 0;
1265 thumb_code = (TARGET_ARM == 0);
1266 arm_tune_wbuf = (tune_flags & FL_WBUF) != 0;
1267 arm_tune_xscale = (tune_flags & FL_XSCALE) != 0;
1268 arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0;
1269 arm_arch_hwdiv = (insn_flags & FL_DIV) != 0;
1271 /* V5 code we generate is completely interworking capable, so we turn off
1272 TARGET_INTERWORK here to avoid many tests later on. */
1274 /* XXX However, we must pass the right pre-processor defines to CPP
1275 or GLD can get confused. This is a hack. */
1276 if (TARGET_INTERWORK)
1277 arm_cpp_interwork = 1;
1280 target_flags &= ~MASK_INTERWORK;
1282 if (target_abi_name)
1284 for (i = 0; i < ARRAY_SIZE (arm_all_abis); i++)
1286 if (streq (arm_all_abis[i].name, target_abi_name))
1288 arm_abi = arm_all_abis[i].abi_type;
1292 if (i == ARRAY_SIZE (arm_all_abis))
1293 error ("invalid ABI option: -mabi=%s", target_abi_name);
1296 arm_abi = ARM_DEFAULT_ABI;
1298 if (TARGET_IWMMXT && !ARM_DOUBLEWORD_ALIGN)
1299 error ("iwmmxt requires an AAPCS compatible ABI for proper operation");
1301 if (TARGET_IWMMXT_ABI && !TARGET_IWMMXT)
1302 error ("iwmmxt abi requires an iwmmxt capable cpu");
1304 arm_fp_model = ARM_FP_MODEL_UNKNOWN;
1305 if (target_fpu_name == NULL && target_fpe_name != NULL)
1307 if (streq (target_fpe_name, "2"))
1308 target_fpu_name = "fpe2";
1309 else if (streq (target_fpe_name, "3"))
1310 target_fpu_name = "fpe3";
1312 error ("invalid floating point emulation option: -mfpe=%s",
1315 if (target_fpu_name != NULL)
1317 /* The user specified a FPU. */
1318 for (i = 0; i < ARRAY_SIZE (all_fpus); i++)
1320 if (streq (all_fpus[i].name, target_fpu_name))
1322 arm_fpu_arch = all_fpus[i].fpu;
1323 arm_fpu_tune = arm_fpu_arch;
1324 arm_fp_model = fp_model_for_fpu[arm_fpu_arch];
1328 if (arm_fp_model == ARM_FP_MODEL_UNKNOWN)
1329 error ("invalid floating point option: -mfpu=%s", target_fpu_name);
1333 #ifdef FPUTYPE_DEFAULT
1334 /* Use the default if it is specified for this platform. */
1335 arm_fpu_arch = FPUTYPE_DEFAULT;
1336 arm_fpu_tune = FPUTYPE_DEFAULT;
1338 /* Pick one based on CPU type. */
1339 /* ??? Some targets assume FPA is the default.
1340 if ((insn_flags & FL_VFP) != 0)
1341 arm_fpu_arch = FPUTYPE_VFP;
1344 if (arm_arch_cirrus)
1345 arm_fpu_arch = FPUTYPE_MAVERICK;
1347 arm_fpu_arch = FPUTYPE_FPA_EMU2;
1349 if (tune_flags & FL_CO_PROC && arm_fpu_arch == FPUTYPE_FPA_EMU2)
1350 arm_fpu_tune = FPUTYPE_FPA;
1352 arm_fpu_tune = arm_fpu_arch;
1353 arm_fp_model = fp_model_for_fpu[arm_fpu_arch];
1354 gcc_assert (arm_fp_model != ARM_FP_MODEL_UNKNOWN);
1357 if (target_float_abi_name != NULL)
1359 /* The user specified a FP ABI. */
1360 for (i = 0; i < ARRAY_SIZE (all_float_abis); i++)
1362 if (streq (all_float_abis[i].name, target_float_abi_name))
1364 arm_float_abi = all_float_abis[i].abi_type;
1368 if (i == ARRAY_SIZE (all_float_abis))
1369 error ("invalid floating point abi: -mfloat-abi=%s",
1370 target_float_abi_name);
1373 arm_float_abi = TARGET_DEFAULT_FLOAT_ABI;
1375 if (arm_float_abi == ARM_FLOAT_ABI_HARD && TARGET_VFP)
1376 sorry ("-mfloat-abi=hard and VFP");
1378 /* FPA and iWMMXt are incompatible because the insn encodings overlap.
1379 VFP and iWMMXt can theoretically coexist, but it's unlikely such silicon
1380 will ever exist. GCC makes no attempt to support this combination. */
1381 if (TARGET_IWMMXT && !TARGET_SOFT_FLOAT)
1382 sorry ("iWMMXt and hardware floating point");
1384 /* ??? iWMMXt insn patterns need auditing for Thumb-2. */
1385 if (TARGET_THUMB2 && TARGET_IWMMXT)
1386 sorry ("Thumb-2 iWMMXt");
1388 /* If soft-float is specified then don't use FPU. */
1389 if (TARGET_SOFT_FLOAT)
1390 arm_fpu_arch = FPUTYPE_NONE;
1392 /* For arm2/3 there is no need to do any scheduling if there is only
1393 a floating point emulator, or we are doing software floating-point. */
1394 if ((TARGET_SOFT_FLOAT
1395 || arm_fpu_tune == FPUTYPE_FPA_EMU2
1396 || arm_fpu_tune == FPUTYPE_FPA_EMU3)
1397 && (tune_flags & FL_MODE32) == 0)
1398 flag_schedule_insns = flag_schedule_insns_after_reload = 0;
1400 if (target_thread_switch)
1402 if (strcmp (target_thread_switch, "soft") == 0)
1403 target_thread_pointer = TP_SOFT;
1404 else if (strcmp (target_thread_switch, "auto") == 0)
1405 target_thread_pointer = TP_AUTO;
1406 else if (strcmp (target_thread_switch, "cp15") == 0)
1407 target_thread_pointer = TP_CP15;
1409 error ("invalid thread pointer option: -mtp=%s", target_thread_switch);
1412 /* Use the cp15 method if it is available. */
1413 if (target_thread_pointer == TP_AUTO)
1415 if (arm_arch6k && !TARGET_THUMB)
1416 target_thread_pointer = TP_CP15;
1418 target_thread_pointer = TP_SOFT;
1421 if (TARGET_HARD_TP && TARGET_THUMB1)
1422 error ("can not use -mtp=cp15 with 16-bit Thumb");
1424 /* Override the default structure alignment for AAPCS ABI. */
1425 if (TARGET_AAPCS_BASED)
1426 arm_structure_size_boundary = 8;
1428 if (structure_size_string != NULL)
1430 int size = strtol (structure_size_string, NULL, 0);
1432 if (size == 8 || size == 32
1433 || (ARM_DOUBLEWORD_ALIGN && size == 64))
1434 arm_structure_size_boundary = size;
1436 warning (0, "structure size boundary can only be set to %s",
1437 ARM_DOUBLEWORD_ALIGN ? "8, 32 or 64": "8 or 32");
1440 if (!TARGET_ARM && TARGET_VXWORKS_RTP && flag_pic)
1442 error ("RTP PIC is incompatible with Thumb");
1446 /* If stack checking is disabled, we can use r10 as the PIC register,
1447 which keeps r9 available. The EABI specifies r9 as the PIC register. */
1448 if (flag_pic && TARGET_SINGLE_PIC_BASE)
1450 if (TARGET_VXWORKS_RTP)
1451 warning (0, "RTP PIC is incompatible with -msingle-pic-base");
1452 arm_pic_register = (TARGET_APCS_STACK || TARGET_AAPCS_BASED) ? 9 : 10;
1455 if (flag_pic && TARGET_VXWORKS_RTP)
1456 arm_pic_register = 9;
1458 if (arm_pic_register_string != NULL)
1460 int pic_register = decode_reg_name (arm_pic_register_string);
1463 warning (0, "-mpic-register= is useless without -fpic");
1465 /* Prevent the user from choosing an obviously stupid PIC register. */
1466 else if (pic_register < 0 || call_used_regs[pic_register]
1467 || pic_register == HARD_FRAME_POINTER_REGNUM
1468 || pic_register == STACK_POINTER_REGNUM
1469 || pic_register >= PC_REGNUM
1470 || (TARGET_VXWORKS_RTP
1471 && (unsigned int) pic_register != arm_pic_register))
1472 error ("unable to use '%s' for PIC register", arm_pic_register_string);
1474 arm_pic_register = pic_register;
1477 /* ??? We might want scheduling for thumb2. */
1478 if (TARGET_THUMB && flag_schedule_insns)
1480 /* Don't warn since it's on by default in -O2. */
1481 flag_schedule_insns = 0;
1486 arm_constant_limit = 1;
1488 /* If optimizing for size, bump the number of instructions that we
1489 are prepared to conditionally execute (even on a StrongARM). */
1490 max_insns_skipped = 6;
1494 /* For processors with load scheduling, it never costs more than
1495 2 cycles to load a constant, and the load scheduler may well
1496 reduce that to 1. */
1498 arm_constant_limit = 1;
1500 /* On XScale the longer latency of a load makes it more difficult
1501 to achieve a good schedule, so it's faster to synthesize
1502 constants that can be done in two insns. */
1503 if (arm_tune_xscale)
1504 arm_constant_limit = 2;
1506 /* StrongARM has early execution of branches, so a sequence
1507 that is worth skipping is shorter. */
1508 if (arm_tune_strongarm)
1509 max_insns_skipped = 3;
1512 /* Register global variables with the garbage collector. */
1513 arm_add_gc_roots ();
1517 arm_add_gc_roots (void)
1519 gcc_obstack_init(&minipool_obstack);
1520 minipool_startobj = (char *) obstack_alloc (&minipool_obstack, 0);
1523 /* A table of known ARM exception types.
1524 For use with the interrupt function attribute. */
1528 const char *const arg;
1529 const unsigned long return_value;
1533 static const isr_attribute_arg isr_attribute_args [] =
1535 { "IRQ", ARM_FT_ISR },
1536 { "irq", ARM_FT_ISR },
1537 { "FIQ", ARM_FT_FIQ },
1538 { "fiq", ARM_FT_FIQ },
1539 { "ABORT", ARM_FT_ISR },
1540 { "abort", ARM_FT_ISR },
1541 { "ABORT", ARM_FT_ISR },
1542 { "abort", ARM_FT_ISR },
1543 { "UNDEF", ARM_FT_EXCEPTION },
1544 { "undef", ARM_FT_EXCEPTION },
1545 { "SWI", ARM_FT_EXCEPTION },
1546 { "swi", ARM_FT_EXCEPTION },
1547 { NULL, ARM_FT_NORMAL }
1550 /* Returns the (interrupt) function type of the current
1551 function, or ARM_FT_UNKNOWN if the type cannot be determined. */
1553 static unsigned long
1554 arm_isr_value (tree argument)
1556 const isr_attribute_arg * ptr;
1560 return ARM_FT_NORMAL | ARM_FT_STACKALIGN;
1562 /* No argument - default to IRQ. */
1563 if (argument == NULL_TREE)
1566 /* Get the value of the argument. */
1567 if (TREE_VALUE (argument) == NULL_TREE
1568 || TREE_CODE (TREE_VALUE (argument)) != STRING_CST)
1569 return ARM_FT_UNKNOWN;
1571 arg = TREE_STRING_POINTER (TREE_VALUE (argument));
1573 /* Check it against the list of known arguments. */
1574 for (ptr = isr_attribute_args; ptr->arg != NULL; ptr++)
1575 if (streq (arg, ptr->arg))
1576 return ptr->return_value;
1578 /* An unrecognized interrupt type. */
1579 return ARM_FT_UNKNOWN;
1582 /* Computes the type of the current function. */
1584 static unsigned long
1585 arm_compute_func_type (void)
1587 unsigned long type = ARM_FT_UNKNOWN;
1591 gcc_assert (TREE_CODE (current_function_decl) == FUNCTION_DECL);
1593 /* Decide if the current function is volatile. Such functions
1594 never return, and many memory cycles can be saved by not storing
1595 register values that will never be needed again. This optimization
1596 was added to speed up context switching in a kernel application. */
1598 && (TREE_NOTHROW (current_function_decl)
1599 || !(flag_unwind_tables
1600 || (flag_exceptions && !USING_SJLJ_EXCEPTIONS)))
1601 && TREE_THIS_VOLATILE (current_function_decl))
1602 type |= ARM_FT_VOLATILE;
1604 if (cfun->static_chain_decl != NULL)
1605 type |= ARM_FT_NESTED;
1607 attr = DECL_ATTRIBUTES (current_function_decl);
1609 a = lookup_attribute ("naked", attr);
1611 type |= ARM_FT_NAKED;
1613 a = lookup_attribute ("isr", attr);
1615 a = lookup_attribute ("interrupt", attr);
1618 type |= TARGET_INTERWORK ? ARM_FT_INTERWORKED : ARM_FT_NORMAL;
1620 type |= arm_isr_value (TREE_VALUE (a));
1625 /* Returns the type of the current function. */
1628 arm_current_func_type (void)
1630 if (ARM_FUNC_TYPE (cfun->machine->func_type) == ARM_FT_UNKNOWN)
1631 cfun->machine->func_type = arm_compute_func_type ();
1633 return cfun->machine->func_type;
1636 /* Return 1 if it is possible to return using a single instruction.
1637 If SIBLING is non-null, this is a test for a return before a sibling
1638 call. SIBLING is the call insn, so we can examine its register usage. */
1641 use_return_insn (int iscond, rtx sibling)
1644 unsigned int func_type;
1645 unsigned long saved_int_regs;
1646 unsigned HOST_WIDE_INT stack_adjust;
1647 arm_stack_offsets *offsets;
1649 /* Never use a return instruction before reload has run. */
1650 if (!reload_completed)
1653 func_type = arm_current_func_type ();
1655 /* Naked, volatile and stack alignment functions need special
1657 if (func_type & (ARM_FT_VOLATILE | ARM_FT_NAKED | ARM_FT_STACKALIGN))
1660 /* So do interrupt functions that use the frame pointer and Thumb
1661 interrupt functions. */
1662 if (IS_INTERRUPT (func_type) && (frame_pointer_needed || TARGET_THUMB))
1665 offsets = arm_get_frame_offsets ();
1666 stack_adjust = offsets->outgoing_args - offsets->saved_regs;
1668 /* As do variadic functions. */
1669 if (current_function_pretend_args_size
1670 || cfun->machine->uses_anonymous_args
1671 /* Or if the function calls __builtin_eh_return () */
1672 || current_function_calls_eh_return
1673 /* Or if the function calls alloca */
1674 || current_function_calls_alloca
1675 /* Or if there is a stack adjustment. However, if the stack pointer
1676 is saved on the stack, we can use a pre-incrementing stack load. */
1677 || !(stack_adjust == 0 || (frame_pointer_needed && stack_adjust == 4)))
1680 saved_int_regs = arm_compute_save_reg_mask ();
1682 /* Unfortunately, the insn
1684 ldmib sp, {..., sp, ...}
1686 triggers a bug on most SA-110 based devices, such that the stack
1687 pointer won't be correctly restored if the instruction takes a
1688 page fault. We work around this problem by popping r3 along with
1689 the other registers, since that is never slower than executing
1690 another instruction.
1692 We test for !arm_arch5 here, because code for any architecture
1693 less than this could potentially be run on one of the buggy
1695 if (stack_adjust == 4 && !arm_arch5 && TARGET_ARM)
1697 /* Validate that r3 is a call-clobbered register (always true in
1698 the default abi) ... */
1699 if (!call_used_regs[3])
1702 /* ... that it isn't being used for a return value ... */
1703 if (arm_size_return_regs () >= (4 * UNITS_PER_WORD))
1706 /* ... or for a tail-call argument ... */
1709 gcc_assert (GET_CODE (sibling) == CALL_INSN);
1711 if (find_regno_fusage (sibling, USE, 3))
1715 /* ... and that there are no call-saved registers in r0-r2
1716 (always true in the default ABI). */
1717 if (saved_int_regs & 0x7)
1721 /* Can't be done if interworking with Thumb, and any registers have been
1723 if (TARGET_INTERWORK && saved_int_regs != 0 && !IS_INTERRUPT(func_type))
1726 /* On StrongARM, conditional returns are expensive if they aren't
1727 taken and multiple registers have been stacked. */
1728 if (iscond && arm_tune_strongarm)
1730 /* Conditional return when just the LR is stored is a simple
1731 conditional-load instruction, that's not expensive. */
1732 if (saved_int_regs != 0 && saved_int_regs != (1 << LR_REGNUM))
1736 && arm_pic_register != INVALID_REGNUM
1737 && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
1741 /* If there are saved registers but the LR isn't saved, then we need
1742 two instructions for the return. */
1743 if (saved_int_regs && !(saved_int_regs & (1 << LR_REGNUM)))
1746 /* Can't be done if any of the FPA regs are pushed,
1747 since this also requires an insn. */
1748 if (TARGET_HARD_FLOAT && TARGET_FPA)
1749 for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++)
1750 if (df_regs_ever_live_p (regno) && !call_used_regs[regno])
1753 /* Likewise VFP regs. */
1754 if (TARGET_HARD_FLOAT && TARGET_VFP)
1755 for (regno = FIRST_VFP_REGNUM; regno <= LAST_VFP_REGNUM; regno++)
1756 if (df_regs_ever_live_p (regno) && !call_used_regs[regno])
1759 if (TARGET_REALLY_IWMMXT)
1760 for (regno = FIRST_IWMMXT_REGNUM; regno <= LAST_IWMMXT_REGNUM; regno++)
1761 if (df_regs_ever_live_p (regno) && ! call_used_regs[regno])
1767 /* Return TRUE if int I is a valid immediate ARM constant. */
1770 const_ok_for_arm (HOST_WIDE_INT i)
1774 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
1775 be all zero, or all one. */
1776 if ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0
1777 && ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff)
1778 != ((~(unsigned HOST_WIDE_INT) 0)
1779 & ~(unsigned HOST_WIDE_INT) 0xffffffff)))
1782 i &= (unsigned HOST_WIDE_INT) 0xffffffff;
1784 /* Fast return for 0 and small values. We must do this for zero, since
1785 the code below can't handle that one case. */
1786 if ((i & ~(unsigned HOST_WIDE_INT) 0xff) == 0)
1789 /* Get the number of trailing zeros. */
1790 lowbit = ffs((int) i) - 1;
1792 /* Only even shifts are allowed in ARM mode so round down to the
1793 nearest even number. */
1797 if ((i & ~(((unsigned HOST_WIDE_INT) 0xff) << lowbit)) == 0)
1802 /* Allow rotated constants in ARM mode. */
1804 && ((i & ~0xc000003f) == 0
1805 || (i & ~0xf000000f) == 0
1806 || (i & ~0xfc000003) == 0))
1813 /* Allow repeated pattern. */
1816 if (i == v || i == (v | (v << 8)))
1823 /* Return true if I is a valid constant for the operation CODE. */
1825 const_ok_for_op (HOST_WIDE_INT i, enum rtx_code code)
1827 if (const_ok_for_arm (i))
1833 return const_ok_for_arm (ARM_SIGN_EXTEND (-i));
1835 case MINUS: /* Should only occur with (MINUS I reg) => rsb */
1841 return const_ok_for_arm (ARM_SIGN_EXTEND (~i));
1848 /* Emit a sequence of insns to handle a large constant.
1849 CODE is the code of the operation required, it can be any of SET, PLUS,
1850 IOR, AND, XOR, MINUS;
1851 MODE is the mode in which the operation is being performed;
1852 VAL is the integer to operate on;
1853 SOURCE is the other operand (a register, or a null-pointer for SET);
1854 SUBTARGETS means it is safe to create scratch registers if that will
1855 either produce a simpler sequence, or we will want to cse the values.
1856 Return value is the number of insns emitted. */
1858 /* ??? Tweak this for thumb2. */
1860 arm_split_constant (enum rtx_code code, enum machine_mode mode, rtx insn,
1861 HOST_WIDE_INT val, rtx target, rtx source, int subtargets)
1865 if (insn && GET_CODE (PATTERN (insn)) == COND_EXEC)
1866 cond = COND_EXEC_TEST (PATTERN (insn));
1870 if (subtargets || code == SET
1871 || (GET_CODE (target) == REG && GET_CODE (source) == REG
1872 && REGNO (target) != REGNO (source)))
1874 /* After arm_reorg has been called, we can't fix up expensive
1875 constants by pushing them into memory so we must synthesize
1876 them in-line, regardless of the cost. This is only likely to
1877 be more costly on chips that have load delay slots and we are
1878 compiling without running the scheduler (so no splitting
1879 occurred before the final instruction emission).
1881 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
1883 if (!after_arm_reorg
1885 && (arm_gen_constant (code, mode, NULL_RTX, val, target, source,
1887 > arm_constant_limit + (code != SET)))
1891 /* Currently SET is the only monadic value for CODE, all
1892 the rest are diadic. */
1893 emit_set_insn (target, GEN_INT (val));
1898 rtx temp = subtargets ? gen_reg_rtx (mode) : target;
1900 emit_set_insn (temp, GEN_INT (val));
1901 /* For MINUS, the value is subtracted from, since we never
1902 have subtraction of a constant. */
1904 emit_set_insn (target, gen_rtx_MINUS (mode, temp, source));
1906 emit_set_insn (target,
1907 gen_rtx_fmt_ee (code, mode, source, temp));
1913 return arm_gen_constant (code, mode, cond, val, target, source, subtargets,
1917 /* Return the number of ARM instructions required to synthesize the given
1920 count_insns_for_constant (HOST_WIDE_INT remainder, int i)
1922 HOST_WIDE_INT temp1;
1930 if (remainder & (3 << (i - 2)))
1935 temp1 = remainder & ((0x0ff << end)
1936 | ((i < end) ? (0xff >> (32 - end)) : 0));
1937 remainder &= ~temp1;
1942 } while (remainder);
1946 /* Emit an instruction with the indicated PATTERN. If COND is
1947 non-NULL, conditionalize the execution of the instruction on COND
1951 emit_constant_insn (rtx cond, rtx pattern)
1954 pattern = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (cond), pattern);
1955 emit_insn (pattern);
1958 /* As above, but extra parameter GENERATE which, if clear, suppresses
1960 /* ??? This needs more work for thumb2. */
1963 arm_gen_constant (enum rtx_code code, enum machine_mode mode, rtx cond,
1964 HOST_WIDE_INT val, rtx target, rtx source, int subtargets,
1969 int can_negate_initial = 0;
1972 int num_bits_set = 0;
1973 int set_sign_bit_copies = 0;
1974 int clear_sign_bit_copies = 0;
1975 int clear_zero_bit_copies = 0;
1976 int set_zero_bit_copies = 0;
1978 unsigned HOST_WIDE_INT temp1, temp2;
1979 unsigned HOST_WIDE_INT remainder = val & 0xffffffff;
1981 /* Find out which operations are safe for a given CODE. Also do a quick
1982 check for degenerate cases; these can occur when DImode operations
1994 can_negate_initial = 1;
1998 if (remainder == 0xffffffff)
2001 emit_constant_insn (cond,
2002 gen_rtx_SET (VOIDmode, target,
2003 GEN_INT (ARM_SIGN_EXTEND (val))));
2008 if (reload_completed && rtx_equal_p (target, source))
2011 emit_constant_insn (cond,
2012 gen_rtx_SET (VOIDmode, target, source));
2021 emit_constant_insn (cond,
2022 gen_rtx_SET (VOIDmode, target, const0_rtx));
2025 if (remainder == 0xffffffff)
2027 if (reload_completed && rtx_equal_p (target, source))
2030 emit_constant_insn (cond,
2031 gen_rtx_SET (VOIDmode, target, source));
2040 if (reload_completed && rtx_equal_p (target, source))
2043 emit_constant_insn (cond,
2044 gen_rtx_SET (VOIDmode, target, source));
2048 /* We don't know how to handle other cases yet. */
2049 gcc_assert (remainder == 0xffffffff);
2052 emit_constant_insn (cond,
2053 gen_rtx_SET (VOIDmode, target,
2054 gen_rtx_NOT (mode, source)));
2058 /* We treat MINUS as (val - source), since (source - val) is always
2059 passed as (source + (-val)). */
2063 emit_constant_insn (cond,
2064 gen_rtx_SET (VOIDmode, target,
2065 gen_rtx_NEG (mode, source)));
2068 if (const_ok_for_arm (val))
2071 emit_constant_insn (cond,
2072 gen_rtx_SET (VOIDmode, target,
2073 gen_rtx_MINUS (mode, GEN_INT (val),
2085 /* If we can do it in one insn get out quickly. */
2086 if (const_ok_for_arm (val)
2087 || (can_negate_initial && const_ok_for_arm (-val))
2088 || (can_invert && const_ok_for_arm (~val)))
2091 emit_constant_insn (cond,
2092 gen_rtx_SET (VOIDmode, target,
2094 ? gen_rtx_fmt_ee (code, mode, source,
2100 /* Calculate a few attributes that may be useful for specific
2102 for (i = 31; i >= 0; i--)
2104 if ((remainder & (1 << i)) == 0)
2105 clear_sign_bit_copies++;
2110 for (i = 31; i >= 0; i--)
2112 if ((remainder & (1 << i)) != 0)
2113 set_sign_bit_copies++;
2118 for (i = 0; i <= 31; i++)
2120 if ((remainder & (1 << i)) == 0)
2121 clear_zero_bit_copies++;
2126 for (i = 0; i <= 31; i++)
2128 if ((remainder & (1 << i)) != 0)
2129 set_zero_bit_copies++;
2137 /* See if we can use movw. */
2138 if (arm_arch_thumb2 && (remainder & 0xffff0000) == 0)
2141 emit_constant_insn (cond, gen_rtx_SET (VOIDmode, target,
2146 /* See if we can do this by sign_extending a constant that is known
2147 to be negative. This is a good, way of doing it, since the shift
2148 may well merge into a subsequent insn. */
2149 if (set_sign_bit_copies > 1)
2151 if (const_ok_for_arm
2152 (temp1 = ARM_SIGN_EXTEND (remainder
2153 << (set_sign_bit_copies - 1))))
2157 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2158 emit_constant_insn (cond,
2159 gen_rtx_SET (VOIDmode, new_src,
2161 emit_constant_insn (cond,
2162 gen_ashrsi3 (target, new_src,
2163 GEN_INT (set_sign_bit_copies - 1)));
2167 /* For an inverted constant, we will need to set the low bits,
2168 these will be shifted out of harm's way. */
2169 temp1 |= (1 << (set_sign_bit_copies - 1)) - 1;
2170 if (const_ok_for_arm (~temp1))
2174 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2175 emit_constant_insn (cond,
2176 gen_rtx_SET (VOIDmode, new_src,
2178 emit_constant_insn (cond,
2179 gen_ashrsi3 (target, new_src,
2180 GEN_INT (set_sign_bit_copies - 1)));
2186 /* See if we can calculate the value as the difference between two
2187 valid immediates. */
2188 if (clear_sign_bit_copies + clear_zero_bit_copies <= 16)
2190 int topshift = clear_sign_bit_copies & ~1;
2192 temp1 = ARM_SIGN_EXTEND ((remainder + (0x00800000 >> topshift))
2193 & (0xff000000 >> topshift));
2195 /* If temp1 is zero, then that means the 9 most significant
2196 bits of remainder were 1 and we've caused it to overflow.
2197 When topshift is 0 we don't need to do anything since we
2198 can borrow from 'bit 32'. */
2199 if (temp1 == 0 && topshift != 0)
2200 temp1 = 0x80000000 >> (topshift - 1);
2202 temp2 = ARM_SIGN_EXTEND (temp1 - remainder);
2204 if (const_ok_for_arm (temp2))
2208 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2209 emit_constant_insn (cond,
2210 gen_rtx_SET (VOIDmode, new_src,
2212 emit_constant_insn (cond,
2213 gen_addsi3 (target, new_src,
2221 /* See if we can generate this by setting the bottom (or the top)
2222 16 bits, and then shifting these into the other half of the
2223 word. We only look for the simplest cases, to do more would cost
2224 too much. Be careful, however, not to generate this when the
2225 alternative would take fewer insns. */
2226 if (val & 0xffff0000)
2228 temp1 = remainder & 0xffff0000;
2229 temp2 = remainder & 0x0000ffff;
2231 /* Overlaps outside this range are best done using other methods. */
2232 for (i = 9; i < 24; i++)
2234 if ((((temp2 | (temp2 << i)) & 0xffffffff) == remainder)
2235 && !const_ok_for_arm (temp2))
2237 rtx new_src = (subtargets
2238 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
2240 insns = arm_gen_constant (code, mode, cond, temp2, new_src,
2241 source, subtargets, generate);
2249 gen_rtx_ASHIFT (mode, source,
2256 /* Don't duplicate cases already considered. */
2257 for (i = 17; i < 24; i++)
2259 if (((temp1 | (temp1 >> i)) == remainder)
2260 && !const_ok_for_arm (temp1))
2262 rtx new_src = (subtargets
2263 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
2265 insns = arm_gen_constant (code, mode, cond, temp1, new_src,
2266 source, subtargets, generate);
2271 gen_rtx_SET (VOIDmode, target,
2274 gen_rtx_LSHIFTRT (mode, source,
2285 /* If we have IOR or XOR, and the constant can be loaded in a
2286 single instruction, and we can find a temporary to put it in,
2287 then this can be done in two instructions instead of 3-4. */
2289 /* TARGET can't be NULL if SUBTARGETS is 0 */
2290 || (reload_completed && !reg_mentioned_p (target, source)))
2292 if (const_ok_for_arm (ARM_SIGN_EXTEND (~val)))
2296 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
2298 emit_constant_insn (cond,
2299 gen_rtx_SET (VOIDmode, sub,
2301 emit_constant_insn (cond,
2302 gen_rtx_SET (VOIDmode, target,
2303 gen_rtx_fmt_ee (code, mode,
2313 if (set_sign_bit_copies > 8
2314 && (val & (-1 << (32 - set_sign_bit_copies))) == val)
2318 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
2319 rtx shift = GEN_INT (set_sign_bit_copies);
2323 gen_rtx_SET (VOIDmode, sub,
2325 gen_rtx_ASHIFT (mode,
2330 gen_rtx_SET (VOIDmode, target,
2332 gen_rtx_LSHIFTRT (mode, sub,
2338 if (set_zero_bit_copies > 8
2339 && (remainder & ((1 << set_zero_bit_copies) - 1)) == remainder)
2343 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
2344 rtx shift = GEN_INT (set_zero_bit_copies);
2348 gen_rtx_SET (VOIDmode, sub,
2350 gen_rtx_LSHIFTRT (mode,
2355 gen_rtx_SET (VOIDmode, target,
2357 gen_rtx_ASHIFT (mode, sub,
2363 if (const_ok_for_arm (temp1 = ARM_SIGN_EXTEND (~val)))
2367 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
2368 emit_constant_insn (cond,
2369 gen_rtx_SET (VOIDmode, sub,
2370 gen_rtx_NOT (mode, source)));
2373 sub = gen_reg_rtx (mode);
2374 emit_constant_insn (cond,
2375 gen_rtx_SET (VOIDmode, sub,
2376 gen_rtx_AND (mode, source,
2378 emit_constant_insn (cond,
2379 gen_rtx_SET (VOIDmode, target,
2380 gen_rtx_NOT (mode, sub)));
2387 /* See if two shifts will do 2 or more insn's worth of work. */
2388 if (clear_sign_bit_copies >= 16 && clear_sign_bit_copies < 24)
2390 HOST_WIDE_INT shift_mask = ((0xffffffff
2391 << (32 - clear_sign_bit_copies))
2394 if ((remainder | shift_mask) != 0xffffffff)
2398 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2399 insns = arm_gen_constant (AND, mode, cond,
2400 remainder | shift_mask,
2401 new_src, source, subtargets, 1);
2406 rtx targ = subtargets ? NULL_RTX : target;
2407 insns = arm_gen_constant (AND, mode, cond,
2408 remainder | shift_mask,
2409 targ, source, subtargets, 0);
2415 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2416 rtx shift = GEN_INT (clear_sign_bit_copies);
2418 emit_insn (gen_ashlsi3 (new_src, source, shift));
2419 emit_insn (gen_lshrsi3 (target, new_src, shift));
2425 if (clear_zero_bit_copies >= 16 && clear_zero_bit_copies < 24)
2427 HOST_WIDE_INT shift_mask = (1 << clear_zero_bit_copies) - 1;
2429 if ((remainder | shift_mask) != 0xffffffff)
2433 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2435 insns = arm_gen_constant (AND, mode, cond,
2436 remainder | shift_mask,
2437 new_src, source, subtargets, 1);
2442 rtx targ = subtargets ? NULL_RTX : target;
2444 insns = arm_gen_constant (AND, mode, cond,
2445 remainder | shift_mask,
2446 targ, source, subtargets, 0);
2452 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2453 rtx shift = GEN_INT (clear_zero_bit_copies);
2455 emit_insn (gen_lshrsi3 (new_src, source, shift));
2456 emit_insn (gen_ashlsi3 (target, new_src, shift));
2468 for (i = 0; i < 32; i++)
2469 if (remainder & (1 << i))
2472 if (code == AND || (can_invert && num_bits_set > 16))
2473 remainder = (~remainder) & 0xffffffff;
2474 else if (code == PLUS && num_bits_set > 16)
2475 remainder = (-remainder) & 0xffffffff;
2482 /* Now try and find a way of doing the job in either two or three
2484 We start by looking for the largest block of zeros that are aligned on
2485 a 2-bit boundary, we then fill up the temps, wrapping around to the
2486 top of the word when we drop off the bottom.
2487 In the worst case this code should produce no more than four insns.
2488 Thumb-2 constants are shifted, not rotated, so the MSB is always the
2489 best place to start. */
2491 /* ??? Use thumb2 replicated constants when the high and low halfwords are
2497 int best_consecutive_zeros = 0;
2499 for (i = 0; i < 32; i += 2)
2501 int consecutive_zeros = 0;
2503 if (!(remainder & (3 << i)))
2505 while ((i < 32) && !(remainder & (3 << i)))
2507 consecutive_zeros += 2;
2510 if (consecutive_zeros > best_consecutive_zeros)
2512 best_consecutive_zeros = consecutive_zeros;
2513 best_start = i - consecutive_zeros;
2519 /* So long as it won't require any more insns to do so, it's
2520 desirable to emit a small constant (in bits 0...9) in the last
2521 insn. This way there is more chance that it can be combined with
2522 a later addressing insn to form a pre-indexed load or store
2523 operation. Consider:
2525 *((volatile int *)0xe0000100) = 1;
2526 *((volatile int *)0xe0000110) = 2;
2528 We want this to wind up as:
2532 str rB, [rA, #0x100]
2534 str rB, [rA, #0x110]
2536 rather than having to synthesize both large constants from scratch.
2538 Therefore, we calculate how many insns would be required to emit
2539 the constant starting from `best_start', and also starting from
2540 zero (i.e. with bit 31 first to be output). If `best_start' doesn't
2541 yield a shorter sequence, we may as well use zero. */
2543 && ((((unsigned HOST_WIDE_INT) 1) << best_start) < remainder)
2544 && (count_insns_for_constant (remainder, 0) <=
2545 count_insns_for_constant (remainder, best_start)))
2549 /* Now start emitting the insns. */
2557 if (remainder & (3 << (i - 2)))
2562 temp1 = remainder & ((0x0ff << end)
2563 | ((i < end) ? (0xff >> (32 - end)) : 0));
2564 remainder &= ~temp1;
2568 rtx new_src, temp1_rtx;
2570 if (code == SET || code == MINUS)
2572 new_src = (subtargets ? gen_reg_rtx (mode) : target);
2573 if (can_invert && code != MINUS)
2578 if (remainder && subtargets)
2579 new_src = gen_reg_rtx (mode);
2584 else if (can_negate)
2588 temp1 = trunc_int_for_mode (temp1, mode);
2589 temp1_rtx = GEN_INT (temp1);
2593 else if (code == MINUS)
2594 temp1_rtx = gen_rtx_MINUS (mode, temp1_rtx, source);
2596 temp1_rtx = gen_rtx_fmt_ee (code, mode, source, temp1_rtx);
2598 emit_constant_insn (cond,
2599 gen_rtx_SET (VOIDmode, new_src,
2609 else if (code == MINUS)
2618 /* Arm allows rotates by a multiple of two. Thumb-2 allows arbitrary
2631 /* Canonicalize a comparison so that we are more likely to recognize it.
2632 This can be done for a few constant compares, where we can make the
2633 immediate value easier to load. */
2636 arm_canonicalize_comparison (enum rtx_code code, enum machine_mode mode,
2639 unsigned HOST_WIDE_INT i = INTVAL (*op1);
2640 unsigned HOST_WIDE_INT maxval;
2641 maxval = (((unsigned HOST_WIDE_INT) 1) << (GET_MODE_BITSIZE(mode) - 1)) - 1;
2652 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
2654 *op1 = GEN_INT (i + 1);
2655 return code == GT ? GE : LT;
2662 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
2664 *op1 = GEN_INT (i - 1);
2665 return code == GE ? GT : LE;
2671 if (i != ~((unsigned HOST_WIDE_INT) 0)
2672 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
2674 *op1 = GEN_INT (i + 1);
2675 return code == GTU ? GEU : LTU;
2682 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
2684 *op1 = GEN_INT (i - 1);
2685 return code == GEU ? GTU : LEU;
2697 /* Define how to find the value returned by a function. */
2700 arm_function_value(tree type, tree func ATTRIBUTE_UNUSED)
2702 enum machine_mode mode;
2703 int unsignedp ATTRIBUTE_UNUSED;
2704 rtx r ATTRIBUTE_UNUSED;
2706 mode = TYPE_MODE (type);
2707 /* Promote integer types. */
2708 if (INTEGRAL_TYPE_P (type))
2709 PROMOTE_FUNCTION_MODE (mode, unsignedp, type);
2711 /* Promotes small structs returned in a register to full-word size
2712 for big-endian AAPCS. */
2713 if (arm_return_in_msb (type))
2715 HOST_WIDE_INT size = int_size_in_bytes (type);
2716 if (size % UNITS_PER_WORD != 0)
2718 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
2719 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
2723 return LIBCALL_VALUE(mode);
2726 /* Determine the amount of memory needed to store the possible return
2727 registers of an untyped call. */
2729 arm_apply_result_size (void)
2735 if (TARGET_HARD_FLOAT_ABI)
2739 if (TARGET_MAVERICK)
2742 if (TARGET_IWMMXT_ABI)
2749 /* Decide whether a type should be returned in memory (true)
2750 or in a register (false). This is called by the macro
2751 RETURN_IN_MEMORY. */
2753 arm_return_in_memory (tree type)
2757 if (!AGGREGATE_TYPE_P (type) &&
2758 (TREE_CODE (type) != VECTOR_TYPE) &&
2759 !(TARGET_AAPCS_BASED && TREE_CODE (type) == COMPLEX_TYPE))
2760 /* All simple types are returned in registers.
2761 For AAPCS, complex types are treated the same as aggregates. */
2764 size = int_size_in_bytes (type);
2766 if (arm_abi != ARM_ABI_APCS)
2768 /* ATPCS and later return aggregate types in memory only if they are
2769 larger than a word (or are variable size). */
2770 return (size < 0 || size > UNITS_PER_WORD);
2773 /* To maximize backwards compatibility with previous versions of gcc,
2774 return vectors up to 4 words in registers. */
2775 if (TREE_CODE (type) == VECTOR_TYPE)
2776 return (size < 0 || size > (4 * UNITS_PER_WORD));
2778 /* For the arm-wince targets we choose to be compatible with Microsoft's
2779 ARM and Thumb compilers, which always return aggregates in memory. */
2781 /* All structures/unions bigger than one word are returned in memory.
2782 Also catch the case where int_size_in_bytes returns -1. In this case
2783 the aggregate is either huge or of variable size, and in either case
2784 we will want to return it via memory and not in a register. */
2785 if (size < 0 || size > UNITS_PER_WORD)
2788 if (TREE_CODE (type) == RECORD_TYPE)
2792 /* For a struct the APCS says that we only return in a register
2793 if the type is 'integer like' and every addressable element
2794 has an offset of zero. For practical purposes this means
2795 that the structure can have at most one non bit-field element
2796 and that this element must be the first one in the structure. */
2798 /* Find the first field, ignoring non FIELD_DECL things which will
2799 have been created by C++. */
2800 for (field = TYPE_FIELDS (type);
2801 field && TREE_CODE (field) != FIELD_DECL;
2802 field = TREE_CHAIN (field))
2806 return 0; /* An empty structure. Allowed by an extension to ANSI C. */
2808 /* Check that the first field is valid for returning in a register. */
2810 /* ... Floats are not allowed */
2811 if (FLOAT_TYPE_P (TREE_TYPE (field)))
2814 /* ... Aggregates that are not themselves valid for returning in
2815 a register are not allowed. */
2816 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
2819 /* Now check the remaining fields, if any. Only bitfields are allowed,
2820 since they are not addressable. */
2821 for (field = TREE_CHAIN (field);
2823 field = TREE_CHAIN (field))
2825 if (TREE_CODE (field) != FIELD_DECL)
2828 if (!DECL_BIT_FIELD_TYPE (field))
2835 if (TREE_CODE (type) == UNION_TYPE)
2839 /* Unions can be returned in registers if every element is
2840 integral, or can be returned in an integer register. */
2841 for (field = TYPE_FIELDS (type);
2843 field = TREE_CHAIN (field))
2845 if (TREE_CODE (field) != FIELD_DECL)
2848 if (FLOAT_TYPE_P (TREE_TYPE (field)))
2851 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
2857 #endif /* not ARM_WINCE */
2859 /* Return all other types in memory. */
2863 /* Indicate whether or not words of a double are in big-endian order. */
2866 arm_float_words_big_endian (void)
2868 if (TARGET_MAVERICK)
2871 /* For FPA, float words are always big-endian. For VFP, floats words
2872 follow the memory system mode. */
2880 return (TARGET_BIG_END ? 1 : 0);
2885 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2886 for a call to a function whose data type is FNTYPE.
2887 For a library call, FNTYPE is NULL. */
2889 arm_init_cumulative_args (CUMULATIVE_ARGS *pcum, tree fntype,
2890 rtx libname ATTRIBUTE_UNUSED,
2891 tree fndecl ATTRIBUTE_UNUSED)
2893 /* On the ARM, the offset starts at 0. */
2895 pcum->iwmmxt_nregs = 0;
2896 pcum->can_split = true;
2898 /* Varargs vectors are treated the same as long long.
2899 named_count avoids having to change the way arm handles 'named' */
2900 pcum->named_count = 0;
2903 if (TARGET_REALLY_IWMMXT && fntype)
2907 for (fn_arg = TYPE_ARG_TYPES (fntype);
2909 fn_arg = TREE_CHAIN (fn_arg))
2910 pcum->named_count += 1;
2912 if (! pcum->named_count)
2913 pcum->named_count = INT_MAX;
2918 /* Return true if mode/type need doubleword alignment. */
2920 arm_needs_doubleword_align (enum machine_mode mode, tree type)
2922 return (GET_MODE_ALIGNMENT (mode) > PARM_BOUNDARY
2923 || (type && TYPE_ALIGN (type) > PARM_BOUNDARY));
2927 /* Determine where to put an argument to a function.
2928 Value is zero to push the argument on the stack,
2929 or a hard register in which to store the argument.
2931 MODE is the argument's machine mode.
2932 TYPE is the data type of the argument (as a tree).
2933 This is null for libcalls where that information may
2935 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2936 the preceding args and about the function being called.
2937 NAMED is nonzero if this argument is a named parameter
2938 (otherwise it is an extra parameter matching an ellipsis). */
2941 arm_function_arg (CUMULATIVE_ARGS *pcum, enum machine_mode mode,
2942 tree type, int named)
2946 /* Varargs vectors are treated the same as long long.
2947 named_count avoids having to change the way arm handles 'named' */
2948 if (TARGET_IWMMXT_ABI
2949 && arm_vector_mode_supported_p (mode)
2950 && pcum->named_count > pcum->nargs + 1)
2952 if (pcum->iwmmxt_nregs <= 9)
2953 return gen_rtx_REG (mode, pcum->iwmmxt_nregs + FIRST_IWMMXT_REGNUM);
2956 pcum->can_split = false;
2961 /* Put doubleword aligned quantities in even register pairs. */
2963 && ARM_DOUBLEWORD_ALIGN
2964 && arm_needs_doubleword_align (mode, type))
2967 if (mode == VOIDmode)
2968 /* Pick an arbitrary value for operand 2 of the call insn. */
2971 /* Only allow splitting an arg between regs and memory if all preceding
2972 args were allocated to regs. For args passed by reference we only count
2973 the reference pointer. */
2974 if (pcum->can_split)
2977 nregs = ARM_NUM_REGS2 (mode, type);
2979 if (!named || pcum->nregs + nregs > NUM_ARG_REGS)
2982 return gen_rtx_REG (mode, pcum->nregs);
2986 arm_arg_partial_bytes (CUMULATIVE_ARGS *pcum, enum machine_mode mode,
2987 tree type, bool named ATTRIBUTE_UNUSED)
2989 int nregs = pcum->nregs;
2991 if (arm_vector_mode_supported_p (mode))
2994 if (NUM_ARG_REGS > nregs
2995 && (NUM_ARG_REGS < nregs + ARM_NUM_REGS2 (mode, type))
2997 return (NUM_ARG_REGS - nregs) * UNITS_PER_WORD;
3002 /* Variable sized types are passed by reference. This is a GCC
3003 extension to the ARM ABI. */
3006 arm_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
3007 enum machine_mode mode ATTRIBUTE_UNUSED,
3008 tree type, bool named ATTRIBUTE_UNUSED)
3010 return type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST;
3013 /* Encode the current state of the #pragma [no_]long_calls. */
3016 OFF, /* No #pragma [no_]long_calls is in effect. */
3017 LONG, /* #pragma long_calls is in effect. */
3018 SHORT /* #pragma no_long_calls is in effect. */
3021 static arm_pragma_enum arm_pragma_long_calls = OFF;
3024 arm_pr_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
3026 arm_pragma_long_calls = LONG;
3030 arm_pr_no_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
3032 arm_pragma_long_calls = SHORT;
3036 arm_pr_long_calls_off (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
3038 arm_pragma_long_calls = OFF;
3041 /* Table of machine attributes. */
3042 const struct attribute_spec arm_attribute_table[] =
3044 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
3045 /* Function calls made to this symbol must be done indirectly, because
3046 it may lie outside of the 26 bit addressing range of a normal function
3048 { "long_call", 0, 0, false, true, true, NULL },
3049 /* Whereas these functions are always known to reside within the 26 bit
3050 addressing range. */
3051 { "short_call", 0, 0, false, true, true, NULL },
3052 /* Interrupt Service Routines have special prologue and epilogue requirements. */
3053 { "isr", 0, 1, false, false, false, arm_handle_isr_attribute },
3054 { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute },
3055 { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute },
3057 /* ARM/PE has three new attributes:
3059 dllexport - for exporting a function/variable that will live in a dll
3060 dllimport - for importing a function/variable from a dll
3062 Microsoft allows multiple declspecs in one __declspec, separating
3063 them with spaces. We do NOT support this. Instead, use __declspec
3066 { "dllimport", 0, 0, true, false, false, NULL },
3067 { "dllexport", 0, 0, true, false, false, NULL },
3068 { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute },
3069 #elif TARGET_DLLIMPORT_DECL_ATTRIBUTES
3070 { "dllimport", 0, 0, false, false, false, handle_dll_attribute },
3071 { "dllexport", 0, 0, false, false, false, handle_dll_attribute },
3072 { "notshared", 0, 0, false, true, false, arm_handle_notshared_attribute },
3074 { NULL, 0, 0, false, false, false, NULL }
3077 /* Handle an attribute requiring a FUNCTION_DECL;
3078 arguments as in struct attribute_spec.handler. */
3080 arm_handle_fndecl_attribute (tree *node, tree name, tree args ATTRIBUTE_UNUSED,
3081 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
3083 if (TREE_CODE (*node) != FUNCTION_DECL)
3085 warning (OPT_Wattributes, "%qs attribute only applies to functions",
3086 IDENTIFIER_POINTER (name));
3087 *no_add_attrs = true;
3093 /* Handle an "interrupt" or "isr" attribute;
3094 arguments as in struct attribute_spec.handler. */
3096 arm_handle_isr_attribute (tree *node, tree name, tree args, int flags,
3101 if (TREE_CODE (*node) != FUNCTION_DECL)
3103 warning (OPT_Wattributes, "%qs attribute only applies to functions",
3104 IDENTIFIER_POINTER (name));
3105 *no_add_attrs = true;
3107 /* FIXME: the argument if any is checked for type attributes;
3108 should it be checked for decl ones? */
3112 if (TREE_CODE (*node) == FUNCTION_TYPE
3113 || TREE_CODE (*node) == METHOD_TYPE)
3115 if (arm_isr_value (args) == ARM_FT_UNKNOWN)
3117 warning (OPT_Wattributes, "%qs attribute ignored",
3118 IDENTIFIER_POINTER (name));
3119 *no_add_attrs = true;
3122 else if (TREE_CODE (*node) == POINTER_TYPE
3123 && (TREE_CODE (TREE_TYPE (*node)) == FUNCTION_TYPE
3124 || TREE_CODE (TREE_TYPE (*node)) == METHOD_TYPE)
3125 && arm_isr_value (args) != ARM_FT_UNKNOWN)
3127 *node = build_variant_type_copy (*node);
3128 TREE_TYPE (*node) = build_type_attribute_variant
3130 tree_cons (name, args, TYPE_ATTRIBUTES (TREE_TYPE (*node))));
3131 *no_add_attrs = true;
3135 /* Possibly pass this attribute on from the type to a decl. */
3136 if (flags & ((int) ATTR_FLAG_DECL_NEXT
3137 | (int) ATTR_FLAG_FUNCTION_NEXT
3138 | (int) ATTR_FLAG_ARRAY_NEXT))
3140 *no_add_attrs = true;
3141 return tree_cons (name, args, NULL_TREE);
3145 warning (OPT_Wattributes, "%qs attribute ignored",
3146 IDENTIFIER_POINTER (name));
3154 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
3155 /* Handle the "notshared" attribute. This attribute is another way of
3156 requesting hidden visibility. ARM's compiler supports
3157 "__declspec(notshared)"; we support the same thing via an
3161 arm_handle_notshared_attribute (tree *node,
3162 tree name ATTRIBUTE_UNUSED,
3163 tree args ATTRIBUTE_UNUSED,
3164 int flags ATTRIBUTE_UNUSED,
3167 tree decl = TYPE_NAME (*node);
3171 DECL_VISIBILITY (decl) = VISIBILITY_HIDDEN;
3172 DECL_VISIBILITY_SPECIFIED (decl) = 1;
3173 *no_add_attrs = false;
3179 /* Return 0 if the attributes for two types are incompatible, 1 if they
3180 are compatible, and 2 if they are nearly compatible (which causes a
3181 warning to be generated). */
3183 arm_comp_type_attributes (tree type1, tree type2)
3187 /* Check for mismatch of non-default calling convention. */
3188 if (TREE_CODE (type1) != FUNCTION_TYPE)
3191 /* Check for mismatched call attributes. */
3192 l1 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1)) != NULL;
3193 l2 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2)) != NULL;
3194 s1 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1)) != NULL;
3195 s2 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2)) != NULL;
3197 /* Only bother to check if an attribute is defined. */
3198 if (l1 | l2 | s1 | s2)
3200 /* If one type has an attribute, the other must have the same attribute. */
3201 if ((l1 != l2) || (s1 != s2))
3204 /* Disallow mixed attributes. */
3205 if ((l1 & s2) || (l2 & s1))
3209 /* Check for mismatched ISR attribute. */
3210 l1 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type1)) != NULL;
3212 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1)) != NULL;
3213 l2 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type2)) != NULL;
3215 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2)) != NULL;
3222 /* Assigns default attributes to newly defined type. This is used to
3223 set short_call/long_call attributes for function types of
3224 functions defined inside corresponding #pragma scopes. */
3226 arm_set_default_type_attributes (tree type)
3228 /* Add __attribute__ ((long_call)) to all functions, when
3229 inside #pragma long_calls or __attribute__ ((short_call)),
3230 when inside #pragma no_long_calls. */
3231 if (TREE_CODE (type) == FUNCTION_TYPE || TREE_CODE (type) == METHOD_TYPE)
3233 tree type_attr_list, attr_name;
3234 type_attr_list = TYPE_ATTRIBUTES (type);
3236 if (arm_pragma_long_calls == LONG)
3237 attr_name = get_identifier ("long_call");
3238 else if (arm_pragma_long_calls == SHORT)
3239 attr_name = get_identifier ("short_call");
3243 type_attr_list = tree_cons (attr_name, NULL_TREE, type_attr_list);
3244 TYPE_ATTRIBUTES (type) = type_attr_list;
3248 /* Return true if DECL is known to be linked into section SECTION. */
3251 arm_function_in_section_p (tree decl, section *section)
3253 /* We can only be certain about functions defined in the same
3254 compilation unit. */
3255 if (!TREE_STATIC (decl))
3258 /* Make sure that SYMBOL always binds to the definition in this
3259 compilation unit. */
3260 if (!targetm.binds_local_p (decl))
3263 /* If DECL_SECTION_NAME is set, assume it is trustworthy. */
3264 if (!DECL_SECTION_NAME (decl))
3266 /* Only cater for unit-at-a-time mode, where we know that the user
3267 cannot later specify a section for DECL. */
3268 if (!flag_unit_at_a_time)
3271 /* Make sure that we will not create a unique section for DECL. */
3272 if (flag_function_sections || DECL_ONE_ONLY (decl))
3276 return function_section (decl) == section;
3279 /* Return nonzero if a 32-bit "long_call" should be generated for
3280 a call from the current function to DECL. We generate a long_call
3283 a. has an __attribute__((long call))
3284 or b. is within the scope of a #pragma long_calls
3285 or c. the -mlong-calls command line switch has been specified
3287 However we do not generate a long call if the function:
3289 d. has an __attribute__ ((short_call))
3290 or e. is inside the scope of a #pragma no_long_calls
3291 or f. is defined in the same section as the current function. */
3294 arm_is_long_call_p (tree decl)
3299 return TARGET_LONG_CALLS;
3301 attrs = TYPE_ATTRIBUTES (TREE_TYPE (decl));
3302 if (lookup_attribute ("short_call", attrs))
3305 /* For "f", be conservative, and only cater for cases in which the
3306 whole of the current function is placed in the same section. */
3307 if (!flag_reorder_blocks_and_partition
3308 && arm_function_in_section_p (decl, current_function_section ()))
3311 if (lookup_attribute ("long_call", attrs))
3314 return TARGET_LONG_CALLS;
3317 /* Return nonzero if it is ok to make a tail-call to DECL. */
3319 arm_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
3321 unsigned long func_type;
3323 if (cfun->machine->sibcall_blocked)
3326 /* Never tailcall something for which we have no decl, or if we
3327 are in Thumb mode. */
3328 if (decl == NULL || TARGET_THUMB)
3331 /* The PIC register is live on entry to VxWorks PLT entries, so we
3332 must make the call before restoring the PIC register. */
3333 if (TARGET_VXWORKS_RTP && flag_pic && !targetm.binds_local_p (decl))
3336 /* Cannot tail-call to long calls, since these are out of range of
3337 a branch instruction. */
3338 if (arm_is_long_call_p (decl))
3341 /* If we are interworking and the function is not declared static
3342 then we can't tail-call it unless we know that it exists in this
3343 compilation unit (since it might be a Thumb routine). */
3344 if (TARGET_INTERWORK && TREE_PUBLIC (decl) && !TREE_ASM_WRITTEN (decl))
3347 func_type = arm_current_func_type ();
3348 /* Never tailcall from an ISR routine - it needs a special exit sequence. */
3349 if (IS_INTERRUPT (func_type))
3352 /* Never tailcall if function may be called with a misaligned SP. */
3353 if (IS_STACKALIGN (func_type))
3356 /* Everything else is ok. */
3361 /* Addressing mode support functions. */
3363 /* Return nonzero if X is a legitimate immediate operand when compiling
3364 for PIC. We know that X satisfies CONSTANT_P and flag_pic is true. */
3366 legitimate_pic_operand_p (rtx x)
3368 if (GET_CODE (x) == SYMBOL_REF
3369 || (GET_CODE (x) == CONST
3370 && GET_CODE (XEXP (x, 0)) == PLUS
3371 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF))
3377 /* Record that the current function needs a PIC register. Initialize
3378 cfun->machine->pic_reg if we have not already done so. */
3381 require_pic_register (void)
3383 /* A lot of the logic here is made obscure by the fact that this
3384 routine gets called as part of the rtx cost estimation process.
3385 We don't want those calls to affect any assumptions about the real
3386 function; and further, we can't call entry_of_function() until we
3387 start the real expansion process. */
3388 if (!current_function_uses_pic_offset_table)
3390 gcc_assert (!no_new_pseudos);
3391 if (arm_pic_register != INVALID_REGNUM)
3393 cfun->machine->pic_reg = gen_rtx_REG (Pmode, arm_pic_register);
3395 /* Play games to avoid marking the function as needing pic
3396 if we are being called as part of the cost-estimation
3398 if (current_ir_type () != IR_GIMPLE)
3399 current_function_uses_pic_offset_table = 1;
3405 cfun->machine->pic_reg = gen_reg_rtx (Pmode);
3407 /* Play games to avoid marking the function as needing pic
3408 if we are being called as part of the cost-estimation
3410 if (current_ir_type () != IR_GIMPLE)
3412 current_function_uses_pic_offset_table = 1;
3415 arm_load_pic_register (0UL);
3419 emit_insn_after (seq, entry_of_function ());
3426 legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg)
3428 if (GET_CODE (orig) == SYMBOL_REF
3429 || GET_CODE (orig) == LABEL_REF)
3431 #ifndef AOF_ASSEMBLER
3432 rtx pic_ref, address;
3437 /* If this function doesn't have a pic register, create one now. */
3438 require_pic_register ();
3442 gcc_assert (!no_new_pseudos);
3443 reg = gen_reg_rtx (Pmode);
3448 #ifdef AOF_ASSEMBLER
3449 /* The AOF assembler can generate relocations for these directly, and
3450 understands that the PIC register has to be added into the offset. */
3451 insn = emit_insn (gen_pic_load_addr_based (reg, orig));
3454 address = gen_reg_rtx (Pmode);
3459 emit_insn (gen_pic_load_addr_arm (address, orig));
3460 else if (TARGET_THUMB2)
3461 emit_insn (gen_pic_load_addr_thumb2 (address, orig));
3462 else /* TARGET_THUMB1 */
3463 emit_insn (gen_pic_load_addr_thumb1 (address, orig));
3465 /* VxWorks does not impose a fixed gap between segments; the run-time
3466 gap can be different from the object-file gap. We therefore can't
3467 use GOTOFF unless we are absolutely sure that the symbol is in the
3468 same segment as the GOT. Unfortunately, the flexibility of linker
3469 scripts means that we can't be sure of that in general, so assume
3470 that GOTOFF is never valid on VxWorks. */
3471 if ((GET_CODE (orig) == LABEL_REF
3472 || (GET_CODE (orig) == SYMBOL_REF &&
3473 SYMBOL_REF_LOCAL_P (orig)))
3475 && !TARGET_VXWORKS_RTP)
3476 pic_ref = gen_rtx_PLUS (Pmode, cfun->machine->pic_reg, address);
3479 pic_ref = gen_const_mem (Pmode,
3480 gen_rtx_PLUS (Pmode, cfun->machine->pic_reg,
3484 insn = emit_move_insn (reg, pic_ref);
3486 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3488 set_unique_reg_note (insn, REG_EQUAL, orig);
3492 else if (GET_CODE (orig) == CONST)
3496 if (GET_CODE (XEXP (orig, 0)) == PLUS
3497 && XEXP (XEXP (orig, 0), 0) == cfun->machine->pic_reg)
3500 if (GET_CODE (XEXP (orig, 0)) == UNSPEC
3501 && XINT (XEXP (orig, 0), 1) == UNSPEC_TLS)
3506 gcc_assert (!no_new_pseudos);
3507 reg = gen_reg_rtx (Pmode);
3510 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
3512 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
3513 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
3514 base == reg ? 0 : reg);
3516 if (GET_CODE (offset) == CONST_INT)
3518 /* The base register doesn't really matter, we only want to
3519 test the index for the appropriate mode. */
3520 if (!arm_legitimate_index_p (mode, offset, SET, 0))
3522 gcc_assert (!no_new_pseudos);
3523 offset = force_reg (Pmode, offset);
3526 if (GET_CODE (offset) == CONST_INT)
3527 return plus_constant (base, INTVAL (offset));
3530 if (GET_MODE_SIZE (mode) > 4
3531 && (GET_MODE_CLASS (mode) == MODE_INT
3532 || TARGET_SOFT_FLOAT))
3534 emit_insn (gen_addsi3 (reg, base, offset));
3538 return gen_rtx_PLUS (Pmode, base, offset);
3545 /* Find a spare register to use during the prolog of a function. */
3548 thumb_find_work_register (unsigned long pushed_regs_mask)
3552 /* Check the argument registers first as these are call-used. The
3553 register allocation order means that sometimes r3 might be used
3554 but earlier argument registers might not, so check them all. */
3555 for (reg = LAST_ARG_REGNUM; reg >= 0; reg --)
3556 if (!df_regs_ever_live_p (reg))
3559 /* Before going on to check the call-saved registers we can try a couple
3560 more ways of deducing that r3 is available. The first is when we are
3561 pushing anonymous arguments onto the stack and we have less than 4
3562 registers worth of fixed arguments(*). In this case r3 will be part of
3563 the variable argument list and so we can be sure that it will be
3564 pushed right at the start of the function. Hence it will be available
3565 for the rest of the prologue.
3566 (*): ie current_function_pretend_args_size is greater than 0. */
3567 if (cfun->machine->uses_anonymous_args
3568 && current_function_pretend_args_size > 0)
3569 return LAST_ARG_REGNUM;
3571 /* The other case is when we have fixed arguments but less than 4 registers
3572 worth. In this case r3 might be used in the body of the function, but
3573 it is not being used to convey an argument into the function. In theory
3574 we could just check current_function_args_size to see how many bytes are
3575 being passed in argument registers, but it seems that it is unreliable.
3576 Sometimes it will have the value 0 when in fact arguments are being
3577 passed. (See testcase execute/20021111-1.c for an example). So we also
3578 check the args_info.nregs field as well. The problem with this field is
3579 that it makes no allowances for arguments that are passed to the
3580 function but which are not used. Hence we could miss an opportunity
3581 when a function has an unused argument in r3. But it is better to be
3582 safe than to be sorry. */
3583 if (! cfun->machine->uses_anonymous_args
3584 && current_function_args_size >= 0
3585 && current_function_args_size <= (LAST_ARG_REGNUM * UNITS_PER_WORD)
3586 && cfun->args_info.nregs < 4)
3587 return LAST_ARG_REGNUM;
3589 /* Otherwise look for a call-saved register that is going to be pushed. */
3590 for (reg = LAST_LO_REGNUM; reg > LAST_ARG_REGNUM; reg --)
3591 if (pushed_regs_mask & (1 << reg))
3596 /* Thumb-2 can use high regs. */
3597 for (reg = FIRST_HI_REGNUM; reg < 15; reg ++)
3598 if (pushed_regs_mask & (1 << reg))
3601 /* Something went wrong - thumb_compute_save_reg_mask()
3602 should have arranged for a suitable register to be pushed. */
3606 static GTY(()) int pic_labelno;
3608 /* Generate code to load the PIC register. In thumb mode SCRATCH is a
3612 arm_load_pic_register (unsigned long saved_regs ATTRIBUTE_UNUSED)
3614 #ifndef AOF_ASSEMBLER
3615 rtx l1, labelno, pic_tmp, pic_tmp2, pic_rtx, pic_reg;
3616 rtx global_offset_table;
3618 if (current_function_uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE)
3621 gcc_assert (flag_pic);
3623 pic_reg = cfun->machine->pic_reg;
3624 if (TARGET_VXWORKS_RTP)
3626 pic_rtx = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_BASE);
3627 pic_rtx = gen_rtx_CONST (Pmode, pic_rtx);
3628 emit_insn (gen_pic_load_addr_arm (pic_reg, pic_rtx));
3630 emit_insn (gen_rtx_SET (Pmode, pic_reg, gen_rtx_MEM (Pmode, pic_reg)));
3632 pic_tmp = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_INDEX);
3633 emit_insn (gen_pic_offset_arm (pic_reg, pic_reg, pic_tmp));
3637 /* We use an UNSPEC rather than a LABEL_REF because this label
3638 never appears in the code stream. */
3640 labelno = GEN_INT (pic_labelno++);
3641 l1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL);
3642 l1 = gen_rtx_CONST (VOIDmode, l1);
3645 = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3646 /* On the ARM the PC register contains 'dot + 8' at the time of the
3647 addition, on the Thumb it is 'dot + 4'. */
3648 pic_tmp = plus_constant (l1, TARGET_ARM ? 8 : 4);
3651 pic_tmp2 = gen_rtx_PLUS (Pmode, global_offset_table, pc_rtx);
3652 pic_tmp2 = gen_rtx_CONST (VOIDmode, pic_tmp2);
3655 pic_tmp2 = gen_rtx_CONST (VOIDmode, global_offset_table);
3657 pic_rtx = gen_rtx_MINUS (Pmode, pic_tmp2, pic_tmp);
3658 pic_rtx = gen_rtx_CONST (Pmode, pic_rtx);
3662 emit_insn (gen_pic_load_addr_arm (pic_reg, pic_rtx));
3663 emit_insn (gen_pic_add_dot_plus_eight (pic_reg, pic_reg, labelno));
3665 else if (TARGET_THUMB2)
3667 /* Thumb-2 only allows very limited access to the PC. Calculate the
3668 address in a temporary register. */
3669 if (arm_pic_register != INVALID_REGNUM)
3671 pic_tmp = gen_rtx_REG (SImode,
3672 thumb_find_work_register (saved_regs));
3676 gcc_assert (!no_new_pseudos);
3677 pic_tmp = gen_reg_rtx (Pmode);
3680 emit_insn (gen_pic_load_addr_thumb2 (pic_reg, pic_rtx));
3681 emit_insn (gen_pic_load_dot_plus_four (pic_tmp, labelno));
3682 emit_insn (gen_addsi3 (pic_reg, pic_reg, pic_tmp));
3684 else /* TARGET_THUMB1 */
3686 if (arm_pic_register != INVALID_REGNUM
3687 && REGNO (pic_reg) > LAST_LO_REGNUM)
3689 /* We will have pushed the pic register, so we should always be
3690 able to find a work register. */
3691 pic_tmp = gen_rtx_REG (SImode,
3692 thumb_find_work_register (saved_regs));
3693 emit_insn (gen_pic_load_addr_thumb1 (pic_tmp, pic_rtx));
3694 emit_insn (gen_movsi (pic_offset_table_rtx, pic_tmp));
3697 emit_insn (gen_pic_load_addr_thumb1 (pic_reg, pic_rtx));
3698 emit_insn (gen_pic_add_dot_plus_four (pic_reg, pic_reg, labelno));
3702 /* Need to emit this whether or not we obey regdecls,
3703 since setjmp/longjmp can cause life info to screw up. */
3704 emit_insn (gen_rtx_USE (VOIDmode, pic_reg));
3705 #endif /* AOF_ASSEMBLER */
3709 /* Return nonzero if X is valid as an ARM state addressing register. */
3711 arm_address_register_rtx_p (rtx x, int strict_p)
3715 if (GET_CODE (x) != REG)
3721 return ARM_REGNO_OK_FOR_BASE_P (regno);
3723 return (regno <= LAST_ARM_REGNUM
3724 || regno >= FIRST_PSEUDO_REGISTER
3725 || regno == FRAME_POINTER_REGNUM
3726 || regno == ARG_POINTER_REGNUM);
3729 /* Return TRUE if this rtx is the difference of a symbol and a label,
3730 and will reduce to a PC-relative relocation in the object file.
3731 Expressions like this can be left alone when generating PIC, rather
3732 than forced through the GOT. */
3734 pcrel_constant_p (rtx x)
3736 if (GET_CODE (x) == MINUS)
3737 return symbol_mentioned_p (XEXP (x, 0)) && label_mentioned_p (XEXP (x, 1));
3742 /* Return nonzero if X is a valid ARM state address operand. */
3744 arm_legitimate_address_p (enum machine_mode mode, rtx x, RTX_CODE outer,
3748 enum rtx_code code = GET_CODE (x);
3750 if (arm_address_register_rtx_p (x, strict_p))
3753 use_ldrd = (TARGET_LDRD
3755 || (mode == DFmode && (TARGET_SOFT_FLOAT || TARGET_VFP))));
3757 if (code == POST_INC || code == PRE_DEC
3758 || ((code == PRE_INC || code == POST_DEC)
3759 && (use_ldrd || GET_MODE_SIZE (mode) <= 4)))
3760 return arm_address_register_rtx_p (XEXP (x, 0), strict_p);
3762 else if ((code == POST_MODIFY || code == PRE_MODIFY)
3763 && arm_address_register_rtx_p (XEXP (x, 0), strict_p)
3764 && GET_CODE (XEXP (x, 1)) == PLUS
3765 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
3767 rtx addend = XEXP (XEXP (x, 1), 1);
3769 /* Don't allow ldrd post increment by register because it's hard
3770 to fixup invalid register choices. */
3772 && GET_CODE (x) == POST_MODIFY
3773 && GET_CODE (addend) == REG)
3776 return ((use_ldrd || GET_MODE_SIZE (mode) <= 4)
3777 && arm_legitimate_index_p (mode, addend, outer, strict_p));
3780 /* After reload constants split into minipools will have addresses
3781 from a LABEL_REF. */
3782 else if (reload_completed
3783 && (code == LABEL_REF
3785 && GET_CODE (XEXP (x, 0)) == PLUS
3786 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
3787 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
3790 else if (mode == TImode)
3793 else if (code == PLUS)
3795 rtx xop0 = XEXP (x, 0);
3796 rtx xop1 = XEXP (x, 1);
3798 return ((arm_address_register_rtx_p (xop0, strict_p)
3799 && arm_legitimate_index_p (mode, xop1, outer, strict_p))
3800 || (arm_address_register_rtx_p (xop1, strict_p)
3801 && arm_legitimate_index_p (mode, xop0, outer, strict_p)));
3805 /* Reload currently can't handle MINUS, so disable this for now */
3806 else if (GET_CODE (x) == MINUS)
3808 rtx xop0 = XEXP (x, 0);
3809 rtx xop1 = XEXP (x, 1);
3811 return (arm_address_register_rtx_p (xop0, strict_p)
3812 && arm_legitimate_index_p (mode, xop1, outer, strict_p));
3816 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
3817 && code == SYMBOL_REF
3818 && CONSTANT_POOL_ADDRESS_P (x)
3820 && symbol_mentioned_p (get_pool_constant (x))
3821 && ! pcrel_constant_p (get_pool_constant (x))))
3827 /* Return nonzero if X is a valid Thumb-2 address operand. */
3829 thumb2_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p)
3832 enum rtx_code code = GET_CODE (x);
3834 if (arm_address_register_rtx_p (x, strict_p))
3837 use_ldrd = (TARGET_LDRD
3839 || (mode == DFmode && (TARGET_SOFT_FLOAT || TARGET_VFP))));
3841 if (code == POST_INC || code == PRE_DEC
3842 || ((code == PRE_INC || code == POST_DEC)
3843 && (use_ldrd || GET_MODE_SIZE (mode) <= 4)))
3844 return arm_address_register_rtx_p (XEXP (x, 0), strict_p);
3846 else if ((code == POST_MODIFY || code == PRE_MODIFY)
3847 && arm_address_register_rtx_p (XEXP (x, 0), strict_p)
3848 && GET_CODE (XEXP (x, 1)) == PLUS
3849 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
3851 /* Thumb-2 only has autoincrement by constant. */
3852 rtx addend = XEXP (XEXP (x, 1), 1);
3853 HOST_WIDE_INT offset;
3855 if (GET_CODE (addend) != CONST_INT)
3858 offset = INTVAL(addend);
3859 if (GET_MODE_SIZE (mode) <= 4)
3860 return (offset > -256 && offset < 256);
3862 return (use_ldrd && offset > -1024 && offset < 1024
3863 && (offset & 3) == 0);
3866 /* After reload constants split into minipools will have addresses
3867 from a LABEL_REF. */
3868 else if (reload_completed
3869 && (code == LABEL_REF
3871 && GET_CODE (XEXP (x, 0)) == PLUS
3872 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
3873 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
3876 else if (mode == TImode)
3879 else if (code == PLUS)
3881 rtx xop0 = XEXP (x, 0);
3882 rtx xop1 = XEXP (x, 1);
3884 return ((arm_address_register_rtx_p (xop0, strict_p)
3885 && thumb2_legitimate_index_p (mode, xop1, strict_p))
3886 || (arm_address_register_rtx_p (xop1, strict_p)
3887 && thumb2_legitimate_index_p (mode, xop0, strict_p)));
3890 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
3891 && code == SYMBOL_REF
3892 && CONSTANT_POOL_ADDRESS_P (x)
3894 && symbol_mentioned_p (get_pool_constant (x))
3895 && ! pcrel_constant_p (get_pool_constant (x))))
3901 /* Return nonzero if INDEX is valid for an address index operand in
3904 arm_legitimate_index_p (enum machine_mode mode, rtx index, RTX_CODE outer,
3907 HOST_WIDE_INT range;
3908 enum rtx_code code = GET_CODE (index);
3910 /* Standard coprocessor addressing modes. */
3911 if (TARGET_HARD_FLOAT
3912 && (TARGET_FPA || TARGET_MAVERICK)
3913 && (GET_MODE_CLASS (mode) == MODE_FLOAT
3914 || (TARGET_MAVERICK && mode == DImode)))
3915 return (code == CONST_INT && INTVAL (index) < 1024
3916 && INTVAL (index) > -1024
3917 && (INTVAL (index) & 3) == 0);
3919 if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))
3920 return (code == CONST_INT
3921 && INTVAL (index) < 1024
3922 && INTVAL (index) > -1024
3923 && (INTVAL (index) & 3) == 0);
3925 if (arm_address_register_rtx_p (index, strict_p)
3926 && (GET_MODE_SIZE (mode) <= 4))
3929 if (mode == DImode || mode == DFmode)
3931 if (code == CONST_INT)
3933 HOST_WIDE_INT val = INTVAL (index);
3936 return val > -256 && val < 256;
3938 return val > -4096 && val < 4092;
3941 return TARGET_LDRD && arm_address_register_rtx_p (index, strict_p);
3944 if (GET_MODE_SIZE (mode) <= 4
3947 || (mode == QImode && outer == SIGN_EXTEND))))
3951 rtx xiop0 = XEXP (index, 0);
3952 rtx xiop1 = XEXP (index, 1);
3954 return ((arm_address_register_rtx_p (xiop0, strict_p)
3955 && power_of_two_operand (xiop1, SImode))
3956 || (arm_address_register_rtx_p (xiop1, strict_p)
3957 && power_of_two_operand (xiop0, SImode)));
3959 else if (code == LSHIFTRT || code == ASHIFTRT
3960 || code == ASHIFT || code == ROTATERT)
3962 rtx op = XEXP (index, 1);
3964 return (arm_address_register_rtx_p (XEXP (index, 0), strict_p)
3965 && GET_CODE (op) == CONST_INT
3967 && INTVAL (op) <= 31);
3971 /* For ARM v4 we may be doing a sign-extend operation during the
3975 if (mode == HImode || (outer == SIGN_EXTEND && mode == QImode))
3981 range = (mode == HImode) ? 4095 : 4096;
3983 return (code == CONST_INT
3984 && INTVAL (index) < range
3985 && INTVAL (index) > -range);
3988 /* Return true if OP is a valid index scaling factor for Thumb-2 address
3989 index operand. i.e. 1, 2, 4 or 8. */
3991 thumb2_index_mul_operand (rtx op)
3995 if (GET_CODE(op) != CONST_INT)
3999 return (val == 1 || val == 2 || val == 4 || val == 8);
4002 /* Return nonzero if INDEX is a valid Thumb-2 address index operand. */
4004 thumb2_legitimate_index_p (enum machine_mode mode, rtx index, int strict_p)
4006 enum rtx_code code = GET_CODE (index);
4008 /* ??? Combine arm and thumb2 coprocessor addressing modes. */
4009 /* Standard coprocessor addressing modes. */
4010 if (TARGET_HARD_FLOAT
4011 && (TARGET_FPA || TARGET_MAVERICK)
4012 && (GET_MODE_CLASS (mode) == MODE_FLOAT
4013 || (TARGET_MAVERICK && mode == DImode)))
4014 return (code == CONST_INT && INTVAL (index) < 1024
4015 && INTVAL (index) > -1024
4016 && (INTVAL (index) & 3) == 0);
4018 if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))
4020 /* For DImode assume values will usually live in core regs
4021 and only allow LDRD addressing modes. */
4022 if (!TARGET_LDRD || mode != DImode)
4023 return (code == CONST_INT
4024 && INTVAL (index) < 1024
4025 && INTVAL (index) > -1024
4026 && (INTVAL (index) & 3) == 0);
4029 if (arm_address_register_rtx_p (index, strict_p)
4030 && (GET_MODE_SIZE (mode) <= 4))
4033 if (mode == DImode || mode == DFmode)
4035 HOST_WIDE_INT val = INTVAL (index);
4036 /* ??? Can we assume ldrd for thumb2? */
4037 /* Thumb-2 ldrd only has reg+const addressing modes. */
4038 if (code != CONST_INT)
4041 /* ldrd supports offsets of +-1020.
4042 However the ldr fallback does not. */
4043 return val > -256 && val < 256 && (val & 3) == 0;
4048 rtx xiop0 = XEXP (index, 0);
4049 rtx xiop1 = XEXP (index, 1);
4051 return ((arm_address_register_rtx_p (xiop0, strict_p)
4052 && thumb2_index_mul_operand (xiop1))
4053 || (arm_address_register_rtx_p (xiop1, strict_p)
4054 && thumb2_index_mul_operand (xiop0)));
4056 else if (code == ASHIFT)
4058 rtx op = XEXP (index, 1);
4060 return (arm_address_register_rtx_p (XEXP (index, 0), strict_p)
4061 && GET_CODE (op) == CONST_INT
4063 && INTVAL (op) <= 3);
4066 return (code == CONST_INT
4067 && INTVAL (index) < 4096
4068 && INTVAL (index) > -256);
4071 /* Return nonzero if X is valid as a 16-bit Thumb state base register. */
4073 thumb1_base_register_rtx_p (rtx x, enum machine_mode mode, int strict_p)
4077 if (GET_CODE (x) != REG)
4083 return THUMB1_REGNO_MODE_OK_FOR_BASE_P (regno, mode);
4085 return (regno <= LAST_LO_REGNUM
4086 || regno > LAST_VIRTUAL_REGISTER
4087 || regno == FRAME_POINTER_REGNUM
4088 || (GET_MODE_SIZE (mode) >= 4
4089 && (regno == STACK_POINTER_REGNUM
4090 || regno >= FIRST_PSEUDO_REGISTER
4091 || x == hard_frame_pointer_rtx
4092 || x == arg_pointer_rtx)));
4095 /* Return nonzero if x is a legitimate index register. This is the case
4096 for any base register that can access a QImode object. */
4098 thumb1_index_register_rtx_p (rtx x, int strict_p)
4100 return thumb1_base_register_rtx_p (x, QImode, strict_p);
4103 /* Return nonzero if x is a legitimate 16-bit Thumb-state address.
4105 The AP may be eliminated to either the SP or the FP, so we use the
4106 least common denominator, e.g. SImode, and offsets from 0 to 64.
4108 ??? Verify whether the above is the right approach.
4110 ??? Also, the FP may be eliminated to the SP, so perhaps that
4111 needs special handling also.
4113 ??? Look at how the mips16 port solves this problem. It probably uses
4114 better ways to solve some of these problems.
4116 Although it is not incorrect, we don't accept QImode and HImode
4117 addresses based on the frame pointer or arg pointer until the
4118 reload pass starts. This is so that eliminating such addresses
4119 into stack based ones won't produce impossible code. */
4121 thumb1_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p)
4123 /* ??? Not clear if this is right. Experiment. */
4124 if (GET_MODE_SIZE (mode) < 4
4125 && !(reload_in_progress || reload_completed)
4126 && (reg_mentioned_p (frame_pointer_rtx, x)
4127 || reg_mentioned_p (arg_pointer_rtx, x)
4128 || reg_mentioned_p (virtual_incoming_args_rtx, x)
4129 || reg_mentioned_p (virtual_outgoing_args_rtx, x)
4130 || reg_mentioned_p (virtual_stack_dynamic_rtx, x)
4131 || reg_mentioned_p (virtual_stack_vars_rtx, x)))
4134 /* Accept any base register. SP only in SImode or larger. */
4135 else if (thumb1_base_register_rtx_p (x, mode, strict_p))
4138 /* This is PC relative data before arm_reorg runs. */
4139 else if (GET_MODE_SIZE (mode) >= 4 && CONSTANT_P (x)
4140 && GET_CODE (x) == SYMBOL_REF
4141 && CONSTANT_POOL_ADDRESS_P (x) && !flag_pic)
4144 /* This is PC relative data after arm_reorg runs. */
4145 else if (GET_MODE_SIZE (mode) >= 4 && reload_completed
4146 && (GET_CODE (x) == LABEL_REF
4147 || (GET_CODE (x) == CONST
4148 && GET_CODE (XEXP (x, 0)) == PLUS
4149 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
4150 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
4153 /* Post-inc indexing only supported for SImode and larger. */
4154 else if (GET_CODE (x) == POST_INC && GET_MODE_SIZE (mode) >= 4
4155 && thumb1_index_register_rtx_p (XEXP (x, 0), strict_p))
4158 else if (GET_CODE (x) == PLUS)
4160 /* REG+REG address can be any two index registers. */
4161 /* We disallow FRAME+REG addressing since we know that FRAME
4162 will be replaced with STACK, and SP relative addressing only
4163 permits SP+OFFSET. */
4164 if (GET_MODE_SIZE (mode) <= 4
4165 && XEXP (x, 0) != frame_pointer_rtx
4166 && XEXP (x, 1) != frame_pointer_rtx
4167 && thumb1_index_register_rtx_p (XEXP (x, 0), strict_p)
4168 && thumb1_index_register_rtx_p (XEXP (x, 1), strict_p))
4171 /* REG+const has 5-7 bit offset for non-SP registers. */
4172 else if ((thumb1_index_register_rtx_p (XEXP (x, 0), strict_p)
4173 || XEXP (x, 0) == arg_pointer_rtx)
4174 && GET_CODE (XEXP (x, 1)) == CONST_INT
4175 && thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1))))
4178 /* REG+const has 10-bit offset for SP, but only SImode and
4179 larger is supported. */
4180 /* ??? Should probably check for DI/DFmode overflow here
4181 just like GO_IF_LEGITIMATE_OFFSET does. */
4182 else if (GET_CODE (XEXP (x, 0)) == REG
4183 && REGNO (XEXP (x, 0)) == STACK_POINTER_REGNUM
4184 && GET_MODE_SIZE (mode) >= 4
4185 && GET_CODE (XEXP (x, 1)) == CONST_INT
4186 && INTVAL (XEXP (x, 1)) >= 0
4187 && INTVAL (XEXP (x, 1)) + GET_MODE_SIZE (mode) <= 1024
4188 && (INTVAL (XEXP (x, 1)) & 3) == 0)
4191 else if (GET_CODE (XEXP (x, 0)) == REG
4192 && (REGNO (XEXP (x, 0)) == FRAME_POINTER_REGNUM
4193 || REGNO (XEXP (x, 0)) == ARG_POINTER_REGNUM
4194 || (REGNO (XEXP (x, 0)) >= FIRST_VIRTUAL_REGISTER
4195 && REGNO (XEXP (x, 0)) <= LAST_VIRTUAL_REGISTER))
4196 && GET_MODE_SIZE (mode) >= 4
4197 && GET_CODE (XEXP (x, 1)) == CONST_INT
4198 && (INTVAL (XEXP (x, 1)) & 3) == 0)
4202 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
4203 && GET_MODE_SIZE (mode) == 4
4204 && GET_CODE (x) == SYMBOL_REF
4205 && CONSTANT_POOL_ADDRESS_P (x)
4207 && symbol_mentioned_p (get_pool_constant (x))
4208 && ! pcrel_constant_p (get_pool_constant (x))))
4214 /* Return nonzero if VAL can be used as an offset in a Thumb-state address
4215 instruction of mode MODE. */
4217 thumb_legitimate_offset_p (enum machine_mode mode, HOST_WIDE_INT val)
4219 switch (GET_MODE_SIZE (mode))
4222 return val >= 0 && val < 32;
4225 return val >= 0 && val < 64 && (val & 1) == 0;
4229 && (val + GET_MODE_SIZE (mode)) <= 128
4234 /* Build the SYMBOL_REF for __tls_get_addr. */
4236 static GTY(()) rtx tls_get_addr_libfunc;
4239 get_tls_get_addr (void)
4241 if (!tls_get_addr_libfunc)
4242 tls_get_addr_libfunc = init_one_libfunc ("__tls_get_addr");
4243 return tls_get_addr_libfunc;
4247 arm_load_tp (rtx target)
4250 target = gen_reg_rtx (SImode);
4254 /* Can return in any reg. */
4255 emit_insn (gen_load_tp_hard (target));
4259 /* Always returned in r0. Immediately copy the result into a pseudo,
4260 otherwise other uses of r0 (e.g. setting up function arguments) may
4261 clobber the value. */
4265 emit_insn (gen_load_tp_soft ());
4267 tmp = gen_rtx_REG (SImode, 0);
4268 emit_move_insn (target, tmp);
4274 load_tls_operand (rtx x, rtx reg)
4278 if (reg == NULL_RTX)
4279 reg = gen_reg_rtx (SImode);
4281 tmp = gen_rtx_CONST (SImode, x);
4283 emit_move_insn (reg, tmp);
4289 arm_call_tls_get_addr (rtx x, rtx reg, rtx *valuep, int reloc)
4291 rtx insns, label, labelno, sum;
4295 labelno = GEN_INT (pic_labelno++);
4296 label = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL);
4297 label = gen_rtx_CONST (VOIDmode, label);
4299 sum = gen_rtx_UNSPEC (Pmode,
4300 gen_rtvec (4, x, GEN_INT (reloc), label,
4301 GEN_INT (TARGET_ARM ? 8 : 4)),
4303 reg = load_tls_operand (sum, reg);
4306 emit_insn (gen_pic_add_dot_plus_eight (reg, reg, labelno));
4307 else if (TARGET_THUMB2)
4310 /* Thumb-2 only allows very limited access to the PC. Calculate
4311 the address in a temporary register. */
4312 tmp = gen_reg_rtx (SImode);
4313 emit_insn (gen_pic_load_dot_plus_four (tmp, labelno));
4314 emit_insn (gen_addsi3(reg, reg, tmp));
4316 else /* TARGET_THUMB1 */
4317 emit_insn (gen_pic_add_dot_plus_four (reg, reg, labelno));
4319 *valuep = emit_library_call_value (get_tls_get_addr (), NULL_RTX, LCT_PURE, /* LCT_CONST? */
4320 Pmode, 1, reg, Pmode);
4322 insns = get_insns ();
4329 legitimize_tls_address (rtx x, rtx reg)
4331 rtx dest, tp, label, labelno, sum, insns, ret, eqv, addend;
4332 unsigned int model = SYMBOL_REF_TLS_MODEL (x);
4336 case TLS_MODEL_GLOBAL_DYNAMIC:
4337 insns = arm_call_tls_get_addr (x, reg, &ret, TLS_GD32);
4338 dest = gen_reg_rtx (Pmode);
4339 emit_libcall_block (insns, dest, ret, x);
4342 case TLS_MODEL_LOCAL_DYNAMIC:
4343 insns = arm_call_tls_get_addr (x, reg, &ret, TLS_LDM32);
4345 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
4346 share the LDM result with other LD model accesses. */
4347 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const1_rtx),
4349 dest = gen_reg_rtx (Pmode);
4350 emit_libcall_block (insns, dest, ret, eqv);
4352 /* Load the addend. */
4353 addend = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, x, GEN_INT (TLS_LDO32)),
4355 addend = force_reg (SImode, gen_rtx_CONST (SImode, addend));
4356 return gen_rtx_PLUS (Pmode, dest, addend);
4358 case TLS_MODEL_INITIAL_EXEC:
4359 labelno = GEN_INT (pic_labelno++);
4360 label = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL);
4361 label = gen_rtx_CONST (VOIDmode, label);
4362 sum = gen_rtx_UNSPEC (Pmode,
4363 gen_rtvec (4, x, GEN_INT (TLS_IE32), label,
4364 GEN_INT (TARGET_ARM ? 8 : 4)),
4366 reg = load_tls_operand (sum, reg);
4369 emit_insn (gen_tls_load_dot_plus_eight (reg, reg, labelno));
4370 else if (TARGET_THUMB2)
4373 /* Thumb-2 only allows very limited access to the PC. Calculate
4374 the address in a temporary register. */
4375 tmp = gen_reg_rtx (SImode);
4376 emit_insn (gen_pic_load_dot_plus_four (tmp, labelno));
4377 emit_insn (gen_addsi3(reg, reg, tmp));
4378 emit_move_insn (reg, gen_const_mem (SImode, reg));
4382 emit_insn (gen_pic_add_dot_plus_four (reg, reg, labelno));
4383 emit_move_insn (reg, gen_const_mem (SImode, reg));
4386 tp = arm_load_tp (NULL_RTX);
4388 return gen_rtx_PLUS (Pmode, tp, reg);
4390 case TLS_MODEL_LOCAL_EXEC:
4391 tp = arm_load_tp (NULL_RTX);
4393 reg = gen_rtx_UNSPEC (Pmode,
4394 gen_rtvec (2, x, GEN_INT (TLS_LE32)),
4396 reg = force_reg (SImode, gen_rtx_CONST (SImode, reg));
4398 return gen_rtx_PLUS (Pmode, tp, reg);
4405 /* Try machine-dependent ways of modifying an illegitimate address
4406 to be legitimate. If we find one, return the new, valid address. */
4408 arm_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)
4410 if (arm_tls_symbol_p (x))
4411 return legitimize_tls_address (x, NULL_RTX);
4413 if (GET_CODE (x) == PLUS)
4415 rtx xop0 = XEXP (x, 0);
4416 rtx xop1 = XEXP (x, 1);
4418 if (CONSTANT_P (xop0) && !symbol_mentioned_p (xop0))
4419 xop0 = force_reg (SImode, xop0);
4421 if (CONSTANT_P (xop1) && !symbol_mentioned_p (xop1))
4422 xop1 = force_reg (SImode, xop1);
4424 if (ARM_BASE_REGISTER_RTX_P (xop0)
4425 && GET_CODE (xop1) == CONST_INT)
4427 HOST_WIDE_INT n, low_n;
4431 /* VFP addressing modes actually allow greater offsets, but for
4432 now we just stick with the lowest common denominator. */
4434 || ((TARGET_SOFT_FLOAT || TARGET_VFP) && mode == DFmode))
4446 low_n = ((mode) == TImode ? 0
4447 : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff));
4451 base_reg = gen_reg_rtx (SImode);
4452 val = force_operand (plus_constant (xop0, n), NULL_RTX);
4453 emit_move_insn (base_reg, val);
4454 x = plus_constant (base_reg, low_n);
4456 else if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1))
4457 x = gen_rtx_PLUS (SImode, xop0, xop1);
4460 /* XXX We don't allow MINUS any more -- see comment in
4461 arm_legitimate_address_p (). */
4462 else if (GET_CODE (x) == MINUS)
4464 rtx xop0 = XEXP (x, 0);
4465 rtx xop1 = XEXP (x, 1);
4467 if (CONSTANT_P (xop0))
4468 xop0 = force_reg (SImode, xop0);
4470 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1))
4471 xop1 = force_reg (SImode, xop1);
4473 if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1))
4474 x = gen_rtx_MINUS (SImode, xop0, xop1);
4477 /* Make sure to take full advantage of the pre-indexed addressing mode
4478 with absolute addresses which often allows for the base register to
4479 be factorized for multiple adjacent memory references, and it might
4480 even allows for the mini pool to be avoided entirely. */
4481 else if (GET_CODE (x) == CONST_INT && optimize > 0)
4484 HOST_WIDE_INT mask, base, index;
4487 /* ldr and ldrb can use a 12-bit index, ldrsb and the rest can only
4488 use a 8-bit index. So let's use a 12-bit index for SImode only and
4489 hope that arm_gen_constant will enable ldrb to use more bits. */
4490 bits = (mode == SImode) ? 12 : 8;
4491 mask = (1 << bits) - 1;
4492 base = INTVAL (x) & ~mask;
4493 index = INTVAL (x) & mask;
4494 if (bit_count (base & 0xffffffff) > (32 - bits)/2)
4496 /* It'll most probably be more efficient to generate the base
4497 with more bits set and use a negative index instead. */
4501 base_reg = force_reg (SImode, GEN_INT (base));
4502 x = plus_constant (base_reg, index);
4507 /* We need to find and carefully transform any SYMBOL and LABEL
4508 references; so go back to the original address expression. */
4509 rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX);
4511 if (new_x != orig_x)
4519 /* Try machine-dependent ways of modifying an illegitimate Thumb address
4520 to be legitimate. If we find one, return the new, valid address. */
4522 thumb_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)
4524 if (arm_tls_symbol_p (x))
4525 return legitimize_tls_address (x, NULL_RTX);
4527 if (GET_CODE (x) == PLUS
4528 && GET_CODE (XEXP (x, 1)) == CONST_INT
4529 && (INTVAL (XEXP (x, 1)) >= 32 * GET_MODE_SIZE (mode)
4530 || INTVAL (XEXP (x, 1)) < 0))
4532 rtx xop0 = XEXP (x, 0);
4533 rtx xop1 = XEXP (x, 1);
4534 HOST_WIDE_INT offset = INTVAL (xop1);
4536 /* Try and fold the offset into a biasing of the base register and
4537 then offsetting that. Don't do this when optimizing for space
4538 since it can cause too many CSEs. */
4539 if (optimize_size && offset >= 0
4540 && offset < 256 + 31 * GET_MODE_SIZE (mode))
4542 HOST_WIDE_INT delta;
4545 delta = offset - (256 - GET_MODE_SIZE (mode));
4546 else if (offset < 32 * GET_MODE_SIZE (mode) + 8)
4547 delta = 31 * GET_MODE_SIZE (mode);
4549 delta = offset & (~31 * GET_MODE_SIZE (mode));
4551 xop0 = force_operand (plus_constant (xop0, offset - delta),
4553 x = plus_constant (xop0, delta);
4555 else if (offset < 0 && offset > -256)
4556 /* Small negative offsets are best done with a subtract before the
4557 dereference, forcing these into a register normally takes two
4559 x = force_operand (x, NULL_RTX);
4562 /* For the remaining cases, force the constant into a register. */
4563 xop1 = force_reg (SImode, xop1);
4564 x = gen_rtx_PLUS (SImode, xop0, xop1);
4567 else if (GET_CODE (x) == PLUS
4568 && s_register_operand (XEXP (x, 1), SImode)
4569 && !s_register_operand (XEXP (x, 0), SImode))
4571 rtx xop0 = force_operand (XEXP (x, 0), NULL_RTX);
4573 x = gen_rtx_PLUS (SImode, xop0, XEXP (x, 1));
4578 /* We need to find and carefully transform any SYMBOL and LABEL
4579 references; so go back to the original address expression. */
4580 rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX);
4582 if (new_x != orig_x)
4590 thumb_legitimize_reload_address (rtx *x_p,
4591 enum machine_mode mode,
4592 int opnum, int type,
4593 int ind_levels ATTRIBUTE_UNUSED)
4597 if (GET_CODE (x) == PLUS
4598 && GET_MODE_SIZE (mode) < 4
4599 && REG_P (XEXP (x, 0))
4600 && XEXP (x, 0) == stack_pointer_rtx
4601 && GET_CODE (XEXP (x, 1)) == CONST_INT
4602 && !thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1))))
4607 push_reload (orig_x, NULL_RTX, x_p, NULL, MODE_BASE_REG_CLASS (mode),
4608 Pmode, VOIDmode, 0, 0, opnum, type);
4612 /* If both registers are hi-regs, then it's better to reload the
4613 entire expression rather than each register individually. That
4614 only requires one reload register rather than two. */
4615 if (GET_CODE (x) == PLUS
4616 && REG_P (XEXP (x, 0))
4617 && REG_P (XEXP (x, 1))
4618 && !REG_MODE_OK_FOR_REG_BASE_P (XEXP (x, 0), mode)
4619 && !REG_MODE_OK_FOR_REG_BASE_P (XEXP (x, 1), mode))
4624 push_reload (orig_x, NULL_RTX, x_p, NULL, MODE_BASE_REG_CLASS (mode),
4625 Pmode, VOIDmode, 0, 0, opnum, type);
4632 /* Test for various thread-local symbols. */
4634 /* Return TRUE if X is a thread-local symbol. */
4637 arm_tls_symbol_p (rtx x)
4639 if (! TARGET_HAVE_TLS)
4642 if (GET_CODE (x) != SYMBOL_REF)
4645 return SYMBOL_REF_TLS_MODEL (x) != 0;
4648 /* Helper for arm_tls_referenced_p. */
4651 arm_tls_operand_p_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
4653 if (GET_CODE (*x) == SYMBOL_REF)
4654 return SYMBOL_REF_TLS_MODEL (*x) != 0;
4656 /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are
4657 TLS offsets, not real symbol references. */
4658 if (GET_CODE (*x) == UNSPEC
4659 && XINT (*x, 1) == UNSPEC_TLS)
4665 /* Return TRUE if X contains any TLS symbol references. */
4668 arm_tls_referenced_p (rtx x)
4670 if (! TARGET_HAVE_TLS)
4673 return for_each_rtx (&x, arm_tls_operand_p_1, NULL);
4676 #define REG_OR_SUBREG_REG(X) \
4677 (GET_CODE (X) == REG \
4678 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
4680 #define REG_OR_SUBREG_RTX(X) \
4681 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
4683 #ifndef COSTS_N_INSNS
4684 #define COSTS_N_INSNS(N) ((N) * 4 - 2)
4687 thumb1_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer)
4689 enum machine_mode mode = GET_MODE (x);
4702 return COSTS_N_INSNS (1);
4705 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4708 unsigned HOST_WIDE_INT i = INTVAL (XEXP (x, 1));
4715 return COSTS_N_INSNS (2) + cycles;
4717 return COSTS_N_INSNS (1) + 16;
4720 return (COSTS_N_INSNS (1)
4721 + 4 * ((GET_CODE (SET_SRC (x)) == MEM)
4722 + GET_CODE (SET_DEST (x)) == MEM));
4727 if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256)
4729 if (thumb_shiftable_const (INTVAL (x)))
4730 return COSTS_N_INSNS (2);
4731 return COSTS_N_INSNS (3);
4733 else if ((outer == PLUS || outer == COMPARE)
4734 && INTVAL (x) < 256 && INTVAL (x) > -256)
4736 else if (outer == AND
4737 && INTVAL (x) < 256 && INTVAL (x) >= -256)
4738 return COSTS_N_INSNS (1);
4739 else if (outer == ASHIFT || outer == ASHIFTRT
4740 || outer == LSHIFTRT)
4742 return COSTS_N_INSNS (2);
4748 return COSTS_N_INSNS (3);
4766 /* XXX another guess. */
4767 /* Memory costs quite a lot for the first word, but subsequent words
4768 load at the equivalent of a single insn each. */
4769 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
4770 + ((GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
4775 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
4780 /* XXX still guessing. */
4781 switch (GET_MODE (XEXP (x, 0)))
4784 return (1 + (mode == DImode ? 4 : 0)
4785 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
4788 return (4 + (mode == DImode ? 4 : 0)
4789 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
4792 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
4804 /* Worker routine for arm_rtx_costs. */
4805 /* ??? This needs updating for thumb2. */
4807 arm_rtx_costs_1 (rtx x, enum rtx_code code, enum rtx_code outer)
4809 enum machine_mode mode = GET_MODE (x);
4810 enum rtx_code subcode;
4816 /* Memory costs quite a lot for the first word, but subsequent words
4817 load at the equivalent of a single insn each. */
4818 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
4819 + (GET_CODE (x) == SYMBOL_REF
4820 && CONSTANT_POOL_ADDRESS_P (x) ? 4 : 0));
4826 return optimize_size ? COSTS_N_INSNS (2) : 100;
4829 if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG)
4836 case ASHIFT: case LSHIFTRT: case ASHIFTRT:
4838 return (8 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : 8)
4839 + ((GET_CODE (XEXP (x, 0)) == REG
4840 || (GET_CODE (XEXP (x, 0)) == SUBREG
4841 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
4843 return (1 + ((GET_CODE (XEXP (x, 0)) == REG
4844 || (GET_CODE (XEXP (x, 0)) == SUBREG
4845 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
4847 + ((GET_CODE (XEXP (x, 1)) == REG
4848 || (GET_CODE (XEXP (x, 1)) == SUBREG
4849 && GET_CODE (SUBREG_REG (XEXP (x, 1))) == REG)
4850 || (GET_CODE (XEXP (x, 1)) == CONST_INT))
4854 if (GET_CODE (XEXP (x, 1)) == MULT && mode == SImode && arm_arch_thumb2)
4856 extra_cost = rtx_cost (XEXP (x, 1), code);
4857 if (!REG_OR_SUBREG_REG (XEXP (x, 0)))
4858 extra_cost += 4 * ARM_NUM_REGS (mode);
4863 return (4 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 8)
4864 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
4865 || (GET_CODE (XEXP (x, 0)) == CONST_INT
4866 && const_ok_for_arm (INTVAL (XEXP (x, 0)))))
4869 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
4870 return (2 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
4871 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
4872 && arm_const_double_rtx (XEXP (x, 1))))
4874 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
4875 || (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE
4876 && arm_const_double_rtx (XEXP (x, 0))))
4879 if (((GET_CODE (XEXP (x, 0)) == CONST_INT
4880 && const_ok_for_arm (INTVAL (XEXP (x, 0)))
4881 && REG_OR_SUBREG_REG (XEXP (x, 1))))
4882 || (((subcode = GET_CODE (XEXP (x, 1))) == ASHIFT
4883 || subcode == ASHIFTRT || subcode == LSHIFTRT
4884 || subcode == ROTATE || subcode == ROTATERT
4886 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4887 && ((INTVAL (XEXP (XEXP (x, 1), 1)) &
4888 (INTVAL (XEXP (XEXP (x, 1), 1)) - 1)) == 0)))
4889 && REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 0))
4890 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 1))
4891 || GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT)
4892 && REG_OR_SUBREG_REG (XEXP (x, 0))))
4897 if (GET_CODE (XEXP (x, 0)) == MULT)
4899 extra_cost = rtx_cost (XEXP (x, 0), code);
4900 if (!REG_OR_SUBREG_REG (XEXP (x, 1)))
4901 extra_cost += 4 * ARM_NUM_REGS (mode);
4905 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
4906 return (2 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
4907 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
4908 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
4909 && arm_const_double_rtx (XEXP (x, 1))))
4913 case AND: case XOR: case IOR:
4916 /* Normally the frame registers will be spilt into reg+const during
4917 reload, so it is a bad idea to combine them with other instructions,
4918 since then they might not be moved outside of loops. As a compromise
4919 we allow integration with ops that have a constant as their second
4921 if ((REG_OR_SUBREG_REG (XEXP (x, 0))
4922 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))
4923 && GET_CODE (XEXP (x, 1)) != CONST_INT)
4924 || (REG_OR_SUBREG_REG (XEXP (x, 0))
4925 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))))
4929 return (4 + extra_cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
4930 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
4931 || (GET_CODE (XEXP (x, 1)) == CONST_INT
4932 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
4935 if (REG_OR_SUBREG_REG (XEXP (x, 0)))
4936 return (1 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : extra_cost)
4937 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
4938 || (GET_CODE (XEXP (x, 1)) == CONST_INT
4939 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
4942 else if (REG_OR_SUBREG_REG (XEXP (x, 1)))
4943 return (1 + extra_cost
4944 + ((((subcode = GET_CODE (XEXP (x, 0))) == ASHIFT
4945 || subcode == LSHIFTRT || subcode == ASHIFTRT
4946 || subcode == ROTATE || subcode == ROTATERT
4948 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4949 && ((INTVAL (XEXP (XEXP (x, 0), 1)) &
4950 (INTVAL (XEXP (XEXP (x, 0), 1)) - 1)) == 0)))
4951 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 0)))
4952 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 1)))
4953 || GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))
4959 /* This should have been handled by the CPU specific routines. */
4963 if (arm_arch3m && mode == SImode
4964 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
4965 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
4966 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0))
4967 == GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)))
4968 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ZERO_EXTEND
4969 || GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SIGN_EXTEND))
4974 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
4975 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 6);
4979 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
4981 return 1 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
4984 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
4992 return 4 + (mode == DImode ? 4 : 0);
4995 /* ??? value extensions are cheaper on armv6. */
4996 if (GET_MODE (XEXP (x, 0)) == QImode)
4997 return (4 + (mode == DImode ? 4 : 0)
4998 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
5001 switch (GET_MODE (XEXP (x, 0)))
5004 return (1 + (mode == DImode ? 4 : 0)
5005 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
5008 return (4 + (mode == DImode ? 4 : 0)
5009 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
5012 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
5027 if (const_ok_for_arm (INTVAL (x)))
5028 return outer == SET ? 2 : -1;
5029 else if (outer == AND
5030 && const_ok_for_arm (~INTVAL (x)))
5032 else if ((outer == COMPARE
5033 || outer == PLUS || outer == MINUS)
5034 && const_ok_for_arm (-INTVAL (x)))
5045 if (arm_const_double_rtx (x) || vfp3_const_double_rtx (x))
5046 return outer == SET ? 2 : -1;
5047 else if ((outer == COMPARE || outer == PLUS)
5048 && neg_const_double_rtx_ok_for_fpa (x))
5057 /* RTX costs when optimizing for size. */
5059 arm_size_rtx_costs (rtx x, int code, int outer_code, int *total)
5061 enum machine_mode mode = GET_MODE (x);
5065 /* XXX TBD. For now, use the standard costs. */
5066 *total = thumb1_rtx_costs (x, code, outer_code);
5073 /* A memory access costs 1 insn if the mode is small, or the address is
5074 a single register, otherwise it costs one insn per word. */
5075 if (REG_P (XEXP (x, 0)))
5076 *total = COSTS_N_INSNS (1);
5078 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
5085 /* Needs a libcall, so it costs about this. */
5086 *total = COSTS_N_INSNS (2);
5090 if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG)
5092 *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), code);
5100 if (mode == DImode && GET_CODE (XEXP (x, 1)) == CONST_INT)
5102 *total = COSTS_N_INSNS (3) + rtx_cost (XEXP (x, 0), code);
5105 else if (mode == SImode)
5107 *total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 0), code);
5108 /* Slightly disparage register shifts, but not by much. */
5109 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
5110 *total += 1 + rtx_cost (XEXP (x, 1), code);
5114 /* Needs a libcall. */
5115 *total = COSTS_N_INSNS (2);
5119 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
5121 *total = COSTS_N_INSNS (1);
5127 enum rtx_code subcode0 = GET_CODE (XEXP (x, 0));
5128 enum rtx_code subcode1 = GET_CODE (XEXP (x, 1));
5130 if (subcode0 == ROTATE || subcode0 == ROTATERT || subcode0 == ASHIFT
5131 || subcode0 == LSHIFTRT || subcode0 == ASHIFTRT
5132 || subcode1 == ROTATE || subcode1 == ROTATERT
5133 || subcode1 == ASHIFT || subcode1 == LSHIFTRT
5134 || subcode1 == ASHIFTRT)
5136 /* It's just the cost of the two operands. */
5141 *total = COSTS_N_INSNS (1);
5145 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
5149 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
5151 *total = COSTS_N_INSNS (1);
5156 case AND: case XOR: case IOR:
5159 enum rtx_code subcode = GET_CODE (XEXP (x, 0));
5161 if (subcode == ROTATE || subcode == ROTATERT || subcode == ASHIFT
5162 || subcode == LSHIFTRT || subcode == ASHIFTRT
5163 || (code == AND && subcode == NOT))
5165 /* It's just the cost of the two operands. */
5171 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
5175 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
5179 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
5180 *total = COSTS_N_INSNS (1);
5183 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
5192 if (cc_register (XEXP (x, 0), VOIDmode))
5195 *total = COSTS_N_INSNS (1);
5199 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
5200 *total = COSTS_N_INSNS (1);
5202 *total = COSTS_N_INSNS (1 + ARM_NUM_REGS (mode));
5207 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) < 4)
5209 if (!(arm_arch4 && MEM_P (XEXP (x, 0))))
5210 *total += COSTS_N_INSNS (arm_arch6 ? 1 : 2);
5213 *total += COSTS_N_INSNS (1);
5218 if (!(arm_arch4 && MEM_P (XEXP (x, 0))))
5220 switch (GET_MODE (XEXP (x, 0)))
5223 *total += COSTS_N_INSNS (1);
5227 *total += COSTS_N_INSNS (arm_arch6 ? 1 : 2);
5233 *total += COSTS_N_INSNS (2);
5238 *total += COSTS_N_INSNS (1);
5243 if (const_ok_for_arm (INTVAL (x)))
5244 *total = COSTS_N_INSNS (outer_code == SET ? 1 : 0);
5245 else if (const_ok_for_arm (~INTVAL (x)))
5246 *total = COSTS_N_INSNS (outer_code == AND ? 0 : 1);
5247 else if (const_ok_for_arm (-INTVAL (x)))
5249 if (outer_code == COMPARE || outer_code == PLUS
5250 || outer_code == MINUS)
5253 *total = COSTS_N_INSNS (1);
5256 *total = COSTS_N_INSNS (2);
5262 *total = COSTS_N_INSNS (2);
5266 *total = COSTS_N_INSNS (4);
5270 if (mode != VOIDmode)
5271 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
5273 *total = COSTS_N_INSNS (4); /* How knows? */
5278 /* RTX costs for cores with a slow MUL implementation. Thumb-2 is not
5279 supported on any "slowmul" cores, so it can be ignored. */
5282 arm_slowmul_rtx_costs (rtx x, int code, int outer_code, int *total)
5284 enum machine_mode mode = GET_MODE (x);
5288 *total = thumb1_rtx_costs (x, code, outer_code);
5295 if (GET_MODE_CLASS (mode) == MODE_FLOAT
5302 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
5304 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
5305 & (unsigned HOST_WIDE_INT) 0xffffffff);
5306 int cost, const_ok = const_ok_for_arm (i);
5307 int j, booth_unit_size;
5309 /* Tune as appropriate. */
5310 cost = const_ok ? 4 : 8;
5311 booth_unit_size = 2;
5312 for (j = 0; i && j < 32; j += booth_unit_size)
5314 i >>= booth_unit_size;
5322 *total = 30 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
5323 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
5327 *total = arm_rtx_costs_1 (x, code, outer_code);
5333 /* RTX cost for cores with a fast multiply unit (M variants). */
5336 arm_fastmul_rtx_costs (rtx x, int code, int outer_code, int *total)
5338 enum machine_mode mode = GET_MODE (x);
5342 *total = thumb1_rtx_costs (x, code, outer_code);
5346 /* ??? should thumb2 use different costs? */
5350 /* There is no point basing this on the tuning, since it is always the
5351 fast variant if it exists at all. */
5353 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
5354 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
5355 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
5362 if (GET_MODE_CLASS (mode) == MODE_FLOAT
5369 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
5371 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
5372 & (unsigned HOST_WIDE_INT) 0xffffffff);
5373 int cost, const_ok = const_ok_for_arm (i);
5374 int j, booth_unit_size;
5376 /* Tune as appropriate. */
5377 cost = const_ok ? 4 : 8;
5378 booth_unit_size = 8;
5379 for (j = 0; i && j < 32; j += booth_unit_size)
5381 i >>= booth_unit_size;
5389 *total = 8 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
5390 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
5394 *total = arm_rtx_costs_1 (x, code, outer_code);
5400 /* RTX cost for XScale CPUs. Thumb-2 is not supported on any xscale cores,
5401 so it can be ignored. */
5404 arm_xscale_rtx_costs (rtx x, int code, int outer_code, int *total)
5406 enum machine_mode mode = GET_MODE (x);
5410 *total = thumb1_rtx_costs (x, code, outer_code);
5417 /* There is no point basing this on the tuning, since it is always the
5418 fast variant if it exists at all. */
5420 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
5421 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
5422 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
5429 if (GET_MODE_CLASS (mode) == MODE_FLOAT
5436 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
5438 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
5439 & (unsigned HOST_WIDE_INT) 0xffffffff);
5440 int cost, const_ok = const_ok_for_arm (i);
5441 unsigned HOST_WIDE_INT masked_const;
5443 /* The cost will be related to two insns.
5444 First a load of the constant (MOV or LDR), then a multiply. */
5447 cost += 1; /* LDR is probably more expensive because
5448 of longer result latency. */
5449 masked_const = i & 0xffff8000;
5450 if (masked_const != 0 && masked_const != 0xffff8000)
5452 masked_const = i & 0xf8000000;
5453 if (masked_const == 0 || masked_const == 0xf8000000)
5462 *total = 8 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
5463 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
5467 /* A COMPARE of a MULT is slow on XScale; the muls instruction
5468 will stall until the multiplication is complete. */
5469 if (GET_CODE (XEXP (x, 0)) == MULT)
5470 *total = 4 + rtx_cost (XEXP (x, 0), code);
5472 *total = arm_rtx_costs_1 (x, code, outer_code);
5476 *total = arm_rtx_costs_1 (x, code, outer_code);
5482 /* RTX costs for 9e (and later) cores. */
5485 arm_9e_rtx_costs (rtx x, int code, int outer_code, int *total)
5487 enum machine_mode mode = GET_MODE (x);
5496 *total = COSTS_N_INSNS (3);
5500 *total = thumb1_rtx_costs (x, code, outer_code);
5508 /* There is no point basing this on the tuning, since it is always the
5509 fast variant if it exists at all. */
5511 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
5512 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
5513 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
5520 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
5537 *total = cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : nonreg_cost)
5538 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : nonreg_cost);
5542 *total = arm_rtx_costs_1 (x, code, outer_code);
5546 /* All address computations that can be done are free, but rtx cost returns
5547 the same for practically all of them. So we weight the different types
5548 of address here in the order (most pref first):
5549 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
5551 arm_arm_address_cost (rtx x)
5553 enum rtx_code c = GET_CODE (x);
5555 if (c == PRE_INC || c == PRE_DEC || c == POST_INC || c == POST_DEC)
5557 if (c == MEM || c == LABEL_REF || c == SYMBOL_REF)
5560 if (c == PLUS || c == MINUS)
5562 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5565 if (ARITHMETIC_P (XEXP (x, 0)) || ARITHMETIC_P (XEXP (x, 1)))
5575 arm_thumb_address_cost (rtx x)
5577 enum rtx_code c = GET_CODE (x);
5582 && GET_CODE (XEXP (x, 0)) == REG
5583 && GET_CODE (XEXP (x, 1)) == CONST_INT)
5590 arm_address_cost (rtx x)
5592 return TARGET_32BIT ? arm_arm_address_cost (x) : arm_thumb_address_cost (x);
5596 arm_adjust_cost (rtx insn, rtx link, rtx dep, int cost)
5600 /* Some true dependencies can have a higher cost depending
5601 on precisely how certain input operands are used. */
5603 && REG_NOTE_KIND (link) == 0
5604 && recog_memoized (insn) >= 0
5605 && recog_memoized (dep) >= 0)
5607 int shift_opnum = get_attr_shift (insn);
5608 enum attr_type attr_type = get_attr_type (dep);
5610 /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted
5611 operand for INSN. If we have a shifted input operand and the
5612 instruction we depend on is another ALU instruction, then we may
5613 have to account for an additional stall. */
5614 if (shift_opnum != 0
5615 && (attr_type == TYPE_ALU_SHIFT || attr_type == TYPE_ALU_SHIFT_REG))
5617 rtx shifted_operand;
5620 /* Get the shifted operand. */
5621 extract_insn (insn);
5622 shifted_operand = recog_data.operand[shift_opnum];
5624 /* Iterate over all the operands in DEP. If we write an operand
5625 that overlaps with SHIFTED_OPERAND, then we have increase the
5626 cost of this dependency. */
5628 preprocess_constraints ();
5629 for (opno = 0; opno < recog_data.n_operands; opno++)
5631 /* We can ignore strict inputs. */
5632 if (recog_data.operand_type[opno] == OP_IN)
5635 if (reg_overlap_mentioned_p (recog_data.operand[opno],
5642 /* XXX This is not strictly true for the FPA. */
5643 if (REG_NOTE_KIND (link) == REG_DEP_ANTI
5644 || REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
5647 /* Call insns don't incur a stall, even if they follow a load. */
5648 if (REG_NOTE_KIND (link) == 0
5649 && GET_CODE (insn) == CALL_INSN)
5652 if ((i_pat = single_set (insn)) != NULL
5653 && GET_CODE (SET_SRC (i_pat)) == MEM
5654 && (d_pat = single_set (dep)) != NULL
5655 && GET_CODE (SET_DEST (d_pat)) == MEM)
5657 rtx src_mem = XEXP (SET_SRC (i_pat), 0);
5658 /* This is a load after a store, there is no conflict if the load reads
5659 from a cached area. Assume that loads from the stack, and from the
5660 constant pool are cached, and that others will miss. This is a
5663 if ((GET_CODE (src_mem) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (src_mem))
5664 || reg_mentioned_p (stack_pointer_rtx, src_mem)
5665 || reg_mentioned_p (frame_pointer_rtx, src_mem)
5666 || reg_mentioned_p (hard_frame_pointer_rtx, src_mem))
5673 static int fp_consts_inited = 0;
5675 /* Only zero is valid for VFP. Other values are also valid for FPA. */
5676 static const char * const strings_fp[8] =
5679 "4", "5", "0.5", "10"
5682 static REAL_VALUE_TYPE values_fp[8];
5685 init_fp_table (void)
5691 fp_consts_inited = 1;
5693 fp_consts_inited = 8;
5695 for (i = 0; i < fp_consts_inited; i++)
5697 r = REAL_VALUE_ATOF (strings_fp[i], DFmode);
5702 /* Return TRUE if rtx X is a valid immediate FP constant. */
5704 arm_const_double_rtx (rtx x)
5709 if (!fp_consts_inited)
5712 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
5713 if (REAL_VALUE_MINUS_ZERO (r))
5716 for (i = 0; i < fp_consts_inited; i++)
5717 if (REAL_VALUES_EQUAL (r, values_fp[i]))
5723 /* Return TRUE if rtx X is a valid immediate FPA constant. */
5725 neg_const_double_rtx_ok_for_fpa (rtx x)
5730 if (!fp_consts_inited)
5733 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
5734 r = REAL_VALUE_NEGATE (r);
5735 if (REAL_VALUE_MINUS_ZERO (r))
5738 for (i = 0; i < 8; i++)
5739 if (REAL_VALUES_EQUAL (r, values_fp[i]))
5746 /* VFPv3 has a fairly wide range of representable immediates, formed from
5747 "quarter-precision" floating-point values. These can be evaluated using this
5748 formula (with ^ for exponentiation):
5752 Where 's' is a sign bit (0/1), 'n' and 'r' are integers such that
5753 16 <= n <= 31 and 0 <= r <= 7.
5755 These values are mapped onto an 8-bit integer ABCDEFGH s.t.
5757 - A (most-significant) is the sign bit.
5758 - BCD are the exponent (encoded as r XOR 3).
5759 - EFGH are the mantissa (encoded as n - 16).
5762 /* Return an integer index for a VFPv3 immediate operand X suitable for the
5763 fconst[sd] instruction, or -1 if X isn't suitable. */
5765 vfp3_const_double_index (rtx x)
5767 REAL_VALUE_TYPE r, m;
5769 unsigned HOST_WIDE_INT mantissa, mant_hi;
5770 unsigned HOST_WIDE_INT mask;
5771 HOST_WIDE_INT m1, m2;
5772 int point_pos = 2 * HOST_BITS_PER_WIDE_INT - 1;
5774 if (!TARGET_VFP3 || GET_CODE (x) != CONST_DOUBLE)
5777 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
5779 /* We can't represent these things, so detect them first. */
5780 if (REAL_VALUE_ISINF (r) || REAL_VALUE_ISNAN (r) || REAL_VALUE_MINUS_ZERO (r))
5783 /* Extract sign, exponent and mantissa. */
5784 sign = REAL_VALUE_NEGATIVE (r) ? 1 : 0;
5785 r = REAL_VALUE_ABS (r);
5786 exponent = REAL_EXP (&r);
5787 /* For the mantissa, we expand into two HOST_WIDE_INTS, apart from the
5788 highest (sign) bit, with a fixed binary point at bit point_pos.
5789 WARNING: If there's ever a VFP version which uses more than 2 * H_W_I - 1
5790 bits for the mantissa, this may fail (low bits would be lost). */
5791 real_ldexp (&m, &r, point_pos - exponent);
5792 REAL_VALUE_TO_INT (&m1, &m2, m);
5796 /* If there are bits set in the low part of the mantissa, we can't
5797 represent this value. */
5801 /* Now make it so that mantissa contains the most-significant bits, and move
5802 the point_pos to indicate that the least-significant bits have been
5804 point_pos -= HOST_BITS_PER_WIDE_INT;
5807 /* We can permit four significant bits of mantissa only, plus a high bit
5808 which is always 1. */
5809 mask = ((unsigned HOST_WIDE_INT)1 << (point_pos - 5)) - 1;
5810 if ((mantissa & mask) != 0)
5813 /* Now we know the mantissa is in range, chop off the unneeded bits. */
5814 mantissa >>= point_pos - 5;
5816 /* The mantissa may be zero. Disallow that case. (It's possible to load the
5817 floating-point immediate zero with Neon using an integer-zero load, but
5818 that case is handled elsewhere.) */
5822 gcc_assert (mantissa >= 16 && mantissa <= 31);
5824 /* The value of 5 here would be 4 if GCC used IEEE754-like encoding (where
5825 normalized significands are in the range [1, 2). (Our mantissa is shifted
5826 left 4 places at this point relative to normalized IEEE754 values). GCC
5827 internally uses [0.5, 1) (see real.c), so the exponent returned from
5828 REAL_EXP must be altered. */
5829 exponent = 5 - exponent;
5831 if (exponent < 0 || exponent > 7)
5834 /* Sign, mantissa and exponent are now in the correct form to plug into the
5835 formulae described in the comment above. */
5836 return (sign << 7) | ((exponent ^ 3) << 4) | (mantissa - 16);
5839 /* Return TRUE if rtx X is a valid immediate VFPv3 constant. */
5841 vfp3_const_double_rtx (rtx x)
5846 return vfp3_const_double_index (x) != -1;
5850 /* Predicates for `match_operand' and `match_operator'. */
5852 /* Return nonzero if OP is a valid Cirrus memory address pattern. */
5854 cirrus_memory_offset (rtx op)
5856 /* Reject eliminable registers. */
5857 if (! (reload_in_progress || reload_completed)
5858 && ( reg_mentioned_p (frame_pointer_rtx, op)
5859 || reg_mentioned_p (arg_pointer_rtx, op)
5860 || reg_mentioned_p (virtual_incoming_args_rtx, op)
5861 || reg_mentioned_p (virtual_outgoing_args_rtx, op)
5862 || reg_mentioned_p (virtual_stack_dynamic_rtx, op)
5863 || reg_mentioned_p (virtual_stack_vars_rtx, op)))
5866 if (GET_CODE (op) == MEM)
5872 /* Match: (mem (reg)). */
5873 if (GET_CODE (ind) == REG)
5879 if (GET_CODE (ind) == PLUS
5880 && GET_CODE (XEXP (ind, 0)) == REG
5881 && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode)
5882 && GET_CODE (XEXP (ind, 1)) == CONST_INT)
5889 /* Return TRUE if OP is a valid coprocessor memory address pattern.
5890 WB is true if full writeback address modes are allowed and is false
5891 if limited writeback address modes (POST_INC and PRE_DEC) are
5895 arm_coproc_mem_operand (rtx op, bool wb)
5899 /* Reject eliminable registers. */
5900 if (! (reload_in_progress || reload_completed)
5901 && ( reg_mentioned_p (frame_pointer_rtx, op)
5902 || reg_mentioned_p (arg_pointer_rtx, op)
5903 || reg_mentioned_p (virtual_incoming_args_rtx, op)
5904 || reg_mentioned_p (virtual_outgoing_args_rtx, op)
5905 || reg_mentioned_p (virtual_stack_dynamic_rtx, op)
5906 || reg_mentioned_p (virtual_stack_vars_rtx, op)))
5909 /* Constants are converted into offsets from labels. */
5910 if (GET_CODE (op) != MEM)
5915 if (reload_completed
5916 && (GET_CODE (ind) == LABEL_REF
5917 || (GET_CODE (ind) == CONST
5918 && GET_CODE (XEXP (ind, 0)) == PLUS
5919 && GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF
5920 && GET_CODE (XEXP (XEXP (ind, 0), 1)) == CONST_INT)))
5923 /* Match: (mem (reg)). */
5924 if (GET_CODE (ind) == REG)
5925 return arm_address_register_rtx_p (ind, 0);
5927 /* Autoincremment addressing modes. POST_INC and PRE_DEC are
5928 acceptable in any case (subject to verification by
5929 arm_address_register_rtx_p). We need WB to be true to accept
5930 PRE_INC and POST_DEC. */
5931 if (GET_CODE (ind) == POST_INC
5932 || GET_CODE (ind) == PRE_DEC
5934 && (GET_CODE (ind) == PRE_INC
5935 || GET_CODE (ind) == POST_DEC)))
5936 return arm_address_register_rtx_p (XEXP (ind, 0), 0);
5939 && (GET_CODE (ind) == POST_MODIFY || GET_CODE (ind) == PRE_MODIFY)
5940 && arm_address_register_rtx_p (XEXP (ind, 0), 0)
5941 && GET_CODE (XEXP (ind, 1)) == PLUS
5942 && rtx_equal_p (XEXP (XEXP (ind, 1), 0), XEXP (ind, 0)))
5943 ind = XEXP (ind, 1);
5948 if (GET_CODE (ind) == PLUS
5949 && GET_CODE (XEXP (ind, 0)) == REG
5950 && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode)
5951 && GET_CODE (XEXP (ind, 1)) == CONST_INT
5952 && INTVAL (XEXP (ind, 1)) > -1024
5953 && INTVAL (XEXP (ind, 1)) < 1024
5954 && (INTVAL (XEXP (ind, 1)) & 3) == 0)
5960 /* Return true if X is a register that will be eliminated later on. */
5962 arm_eliminable_register (rtx x)
5964 return REG_P (x) && (REGNO (x) == FRAME_POINTER_REGNUM
5965 || REGNO (x) == ARG_POINTER_REGNUM
5966 || (REGNO (x) >= FIRST_VIRTUAL_REGISTER
5967 && REGNO (x) <= LAST_VIRTUAL_REGISTER));
5970 /* Return GENERAL_REGS if a scratch register required to reload x to/from
5971 coprocessor registers. Otherwise return NO_REGS. */
5974 coproc_secondary_reload_class (enum machine_mode mode, rtx x, bool wb)
5976 if (arm_coproc_mem_operand (x, wb) || s_register_operand (x, mode))
5979 return GENERAL_REGS;
5982 /* Values which must be returned in the most-significant end of the return
5986 arm_return_in_msb (tree valtype)
5988 return (TARGET_AAPCS_BASED
5990 && (AGGREGATE_TYPE_P (valtype)
5991 || TREE_CODE (valtype) == COMPLEX_TYPE));
5994 /* Returns TRUE if INSN is an "LDR REG, ADDR" instruction.
5995 Use by the Cirrus Maverick code which has to workaround
5996 a hardware bug triggered by such instructions. */
5998 arm_memory_load_p (rtx insn)
6000 rtx body, lhs, rhs;;
6002 if (insn == NULL_RTX || GET_CODE (insn) != INSN)
6005 body = PATTERN (insn);
6007 if (GET_CODE (body) != SET)
6010 lhs = XEXP (body, 0);
6011 rhs = XEXP (body, 1);
6013 lhs = REG_OR_SUBREG_RTX (lhs);
6015 /* If the destination is not a general purpose
6016 register we do not have to worry. */
6017 if (GET_CODE (lhs) != REG
6018 || REGNO_REG_CLASS (REGNO (lhs)) != GENERAL_REGS)
6021 /* As well as loads from memory we also have to react
6022 to loads of invalid constants which will be turned
6023 into loads from the minipool. */
6024 return (GET_CODE (rhs) == MEM
6025 || GET_CODE (rhs) == SYMBOL_REF
6026 || note_invalid_constants (insn, -1, false));
6029 /* Return TRUE if INSN is a Cirrus instruction. */
6031 arm_cirrus_insn_p (rtx insn)
6033 enum attr_cirrus attr;
6035 /* get_attr cannot accept USE or CLOBBER. */
6037 || GET_CODE (insn) != INSN
6038 || GET_CODE (PATTERN (insn)) == USE
6039 || GET_CODE (PATTERN (insn)) == CLOBBER)
6042 attr = get_attr_cirrus (insn);
6044 return attr != CIRRUS_NOT;
6047 /* Cirrus reorg for invalid instruction combinations. */
6049 cirrus_reorg (rtx first)
6051 enum attr_cirrus attr;
6052 rtx body = PATTERN (first);
6056 /* Any branch must be followed by 2 non Cirrus instructions. */
6057 if (GET_CODE (first) == JUMP_INSN && GET_CODE (body) != RETURN)
6060 t = next_nonnote_insn (first);
6062 if (arm_cirrus_insn_p (t))
6065 if (arm_cirrus_insn_p (next_nonnote_insn (t)))
6069 emit_insn_after (gen_nop (), first);
6074 /* (float (blah)) is in parallel with a clobber. */
6075 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
6076 body = XVECEXP (body, 0, 0);
6078 if (GET_CODE (body) == SET)
6080 rtx lhs = XEXP (body, 0), rhs = XEXP (body, 1);
6082 /* cfldrd, cfldr64, cfstrd, cfstr64 must
6083 be followed by a non Cirrus insn. */
6084 if (get_attr_cirrus (first) == CIRRUS_DOUBLE)
6086 if (arm_cirrus_insn_p (next_nonnote_insn (first)))
6087 emit_insn_after (gen_nop (), first);
6091 else if (arm_memory_load_p (first))
6093 unsigned int arm_regno;
6095 /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr,
6096 ldr/cfmv64hr combination where the Rd field is the same
6097 in both instructions must be split with a non Cirrus
6104 /* Get Arm register number for ldr insn. */
6105 if (GET_CODE (lhs) == REG)
6106 arm_regno = REGNO (lhs);
6109 gcc_assert (GET_CODE (rhs) == REG);
6110 arm_regno = REGNO (rhs);
6114 first = next_nonnote_insn (first);
6116 if (! arm_cirrus_insn_p (first))
6119 body = PATTERN (first);
6121 /* (float (blah)) is in parallel with a clobber. */
6122 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0))
6123 body = XVECEXP (body, 0, 0);
6125 if (GET_CODE (body) == FLOAT)
6126 body = XEXP (body, 0);
6128 if (get_attr_cirrus (first) == CIRRUS_MOVE
6129 && GET_CODE (XEXP (body, 1)) == REG
6130 && arm_regno == REGNO (XEXP (body, 1)))
6131 emit_insn_after (gen_nop (), first);
6137 /* get_attr cannot accept USE or CLOBBER. */
6139 || GET_CODE (first) != INSN
6140 || GET_CODE (PATTERN (first)) == USE
6141 || GET_CODE (PATTERN (first)) == CLOBBER)
6144 attr = get_attr_cirrus (first);
6146 /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...)
6147 must be followed by a non-coprocessor instruction. */
6148 if (attr == CIRRUS_COMPARE)
6152 t = next_nonnote_insn (first);
6154 if (arm_cirrus_insn_p (t))
6157 if (arm_cirrus_insn_p (next_nonnote_insn (t)))
6161 emit_insn_after (gen_nop (), first);
6167 /* Return TRUE if X references a SYMBOL_REF. */
6169 symbol_mentioned_p (rtx x)
6174 if (GET_CODE (x) == SYMBOL_REF)
6177 /* UNSPEC_TLS entries for a symbol include the SYMBOL_REF, but they
6178 are constant offsets, not symbols. */
6179 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLS)
6182 fmt = GET_RTX_FORMAT (GET_CODE (x));
6184 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
6190 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
6191 if (symbol_mentioned_p (XVECEXP (x, i, j)))
6194 else if (fmt[i] == 'e' && symbol_mentioned_p (XEXP (x, i)))
6201 /* Return TRUE if X references a LABEL_REF. */
6203 label_mentioned_p (rtx x)
6208 if (GET_CODE (x) == LABEL_REF)
6211 /* UNSPEC_TLS entries for a symbol include a LABEL_REF for the referencing
6212 instruction, but they are constant offsets, not symbols. */
6213 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLS)
6216 fmt = GET_RTX_FORMAT (GET_CODE (x));
6217 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
6223 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
6224 if (label_mentioned_p (XVECEXP (x, i, j)))
6227 else if (fmt[i] == 'e' && label_mentioned_p (XEXP (x, i)))
6235 tls_mentioned_p (rtx x)
6237 switch (GET_CODE (x))
6240 return tls_mentioned_p (XEXP (x, 0));
6243 if (XINT (x, 1) == UNSPEC_TLS)
6251 /* Must not copy a SET whose source operand is PC-relative. */
6254 arm_cannot_copy_insn_p (rtx insn)
6256 rtx pat = PATTERN (insn);
6258 if (GET_CODE (pat) == SET)
6260 rtx rhs = SET_SRC (pat);
6262 if (GET_CODE (rhs) == UNSPEC
6263 && XINT (rhs, 1) == UNSPEC_PIC_BASE)
6266 if (GET_CODE (rhs) == MEM
6267 && GET_CODE (XEXP (rhs, 0)) == UNSPEC
6268 && XINT (XEXP (rhs, 0), 1) == UNSPEC_PIC_BASE)
6278 enum rtx_code code = GET_CODE (x);
6295 /* Return 1 if memory locations are adjacent. */
6297 adjacent_mem_locations (rtx a, rtx b)
6299 /* We don't guarantee to preserve the order of these memory refs. */
6300 if (volatile_refs_p (a) || volatile_refs_p (b))
6303 if ((GET_CODE (XEXP (a, 0)) == REG
6304 || (GET_CODE (XEXP (a, 0)) == PLUS
6305 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
6306 && (GET_CODE (XEXP (b, 0)) == REG
6307 || (GET_CODE (XEXP (b, 0)) == PLUS
6308 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
6310 HOST_WIDE_INT val0 = 0, val1 = 0;
6314 if (GET_CODE (XEXP (a, 0)) == PLUS)
6316 reg0 = XEXP (XEXP (a, 0), 0);
6317 val0 = INTVAL (XEXP (XEXP (a, 0), 1));
6322 if (GET_CODE (XEXP (b, 0)) == PLUS)
6324 reg1 = XEXP (XEXP (b, 0), 0);
6325 val1 = INTVAL (XEXP (XEXP (b, 0), 1));
6330 /* Don't accept any offset that will require multiple
6331 instructions to handle, since this would cause the
6332 arith_adjacentmem pattern to output an overlong sequence. */
6333 if (!const_ok_for_op (PLUS, val0) || !const_ok_for_op (PLUS, val1))
6336 /* Don't allow an eliminable register: register elimination can make
6337 the offset too large. */
6338 if (arm_eliminable_register (reg0))
6341 val_diff = val1 - val0;
6345 /* If the target has load delay slots, then there's no benefit
6346 to using an ldm instruction unless the offset is zero and
6347 we are optimizing for size. */
6348 return (optimize_size && (REGNO (reg0) == REGNO (reg1))
6349 && (val0 == 0 || val1 == 0 || val0 == 4 || val1 == 4)
6350 && (val_diff == 4 || val_diff == -4));
6353 return ((REGNO (reg0) == REGNO (reg1))
6354 && (val_diff == 4 || val_diff == -4));
6361 load_multiple_sequence (rtx *operands, int nops, int *regs, int *base,
6362 HOST_WIDE_INT *load_offset)
6364 int unsorted_regs[4];
6365 HOST_WIDE_INT unsorted_offsets[4];
6370 /* Can only handle 2, 3, or 4 insns at present,
6371 though could be easily extended if required. */
6372 gcc_assert (nops >= 2 && nops <= 4);
6374 /* Loop over the operands and check that the memory references are
6375 suitable (i.e. immediate offsets from the same base register). At
6376 the same time, extract the target register, and the memory
6378 for (i = 0; i < nops; i++)
6383 /* Convert a subreg of a mem into the mem itself. */
6384 if (GET_CODE (operands[nops + i]) == SUBREG)
6385 operands[nops + i] = alter_subreg (operands + (nops + i));
6387 gcc_assert (GET_CODE (operands[nops + i]) == MEM);
6389 /* Don't reorder volatile memory references; it doesn't seem worth
6390 looking for the case where the order is ok anyway. */
6391 if (MEM_VOLATILE_P (operands[nops + i]))
6394 offset = const0_rtx;
6396 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
6397 || (GET_CODE (reg) == SUBREG
6398 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
6399 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
6400 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
6402 || (GET_CODE (reg) == SUBREG
6403 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
6404 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
6409 base_reg = REGNO (reg);
6410 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
6411 ? REGNO (operands[i])
6412 : REGNO (SUBREG_REG (operands[i])));
6417 if (base_reg != (int) REGNO (reg))
6418 /* Not addressed from the same base register. */
6421 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
6422 ? REGNO (operands[i])
6423 : REGNO (SUBREG_REG (operands[i])));
6424 if (unsorted_regs[i] < unsorted_regs[order[0]])
6428 /* If it isn't an integer register, or if it overwrites the
6429 base register but isn't the last insn in the list, then
6430 we can't do this. */
6431 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14
6432 || (i != nops - 1 && unsorted_regs[i] == base_reg))
6435 unsorted_offsets[i] = INTVAL (offset);
6438 /* Not a suitable memory address. */
6442 /* All the useful information has now been extracted from the
6443 operands into unsorted_regs and unsorted_offsets; additionally,
6444 order[0] has been set to the lowest numbered register in the
6445 list. Sort the registers into order, and check that the memory
6446 offsets are ascending and adjacent. */
6448 for (i = 1; i < nops; i++)
6452 order[i] = order[i - 1];
6453 for (j = 0; j < nops; j++)
6454 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
6455 && (order[i] == order[i - 1]
6456 || unsorted_regs[j] < unsorted_regs[order[i]]))
6459 /* Have we found a suitable register? if not, one must be used more
6461 if (order[i] == order[i - 1])
6464 /* Is the memory address adjacent and ascending? */
6465 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
6473 for (i = 0; i < nops; i++)
6474 regs[i] = unsorted_regs[order[i]];
6476 *load_offset = unsorted_offsets[order[0]];
6479 if (unsorted_offsets[order[0]] == 0)
6480 return 1; /* ldmia */
6482 if (TARGET_ARM && unsorted_offsets[order[0]] == 4)
6483 return 2; /* ldmib */
6485 if (TARGET_ARM && unsorted_offsets[order[nops - 1]] == 0)
6486 return 3; /* ldmda */
6488 if (unsorted_offsets[order[nops - 1]] == -4)
6489 return 4; /* ldmdb */
6491 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
6492 if the offset isn't small enough. The reason 2 ldrs are faster
6493 is because these ARMs are able to do more than one cache access
6494 in a single cycle. The ARM9 and StrongARM have Harvard caches,
6495 whilst the ARM8 has a double bandwidth cache. This means that
6496 these cores can do both an instruction fetch and a data fetch in
6497 a single cycle, so the trick of calculating the address into a
6498 scratch register (one of the result regs) and then doing a load
6499 multiple actually becomes slower (and no smaller in code size).
6500 That is the transformation
6502 ldr rd1, [rbase + offset]
6503 ldr rd2, [rbase + offset + 4]
6507 add rd1, rbase, offset
6508 ldmia rd1, {rd1, rd2}
6510 produces worse code -- '3 cycles + any stalls on rd2' instead of
6511 '2 cycles + any stalls on rd2'. On ARMs with only one cache
6512 access per cycle, the first sequence could never complete in less
6513 than 6 cycles, whereas the ldm sequence would only take 5 and
6514 would make better use of sequential accesses if not hitting the
6517 We cheat here and test 'arm_ld_sched' which we currently know to
6518 only be true for the ARM8, ARM9 and StrongARM. If this ever
6519 changes, then the test below needs to be reworked. */
6520 if (nops == 2 && arm_ld_sched)
6523 /* Can't do it without setting up the offset, only do this if it takes
6524 no more than one insn. */
6525 return (const_ok_for_arm (unsorted_offsets[order[0]])
6526 || const_ok_for_arm (-unsorted_offsets[order[0]])) ? 5 : 0;
6530 emit_ldm_seq (rtx *operands, int nops)
6534 HOST_WIDE_INT offset;
6538 switch (load_multiple_sequence (operands, nops, regs, &base_reg, &offset))
6541 strcpy (buf, "ldm%(ia%)\t");
6545 strcpy (buf, "ldm%(ib%)\t");
6549 strcpy (buf, "ldm%(da%)\t");
6553 strcpy (buf, "ldm%(db%)\t");
6558 sprintf (buf, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
6559 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
6562 sprintf (buf, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
6563 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
6565 output_asm_insn (buf, operands);
6567 strcpy (buf, "ldm%(ia%)\t");
6574 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
6575 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
6577 for (i = 1; i < nops; i++)
6578 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
6579 reg_names[regs[i]]);
6581 strcat (buf, "}\t%@ phole ldm");
6583 output_asm_insn (buf, operands);
6588 store_multiple_sequence (rtx *operands, int nops, int *regs, int *base,
6589 HOST_WIDE_INT * load_offset)
6591 int unsorted_regs[4];
6592 HOST_WIDE_INT unsorted_offsets[4];
6597 /* Can only handle 2, 3, or 4 insns at present, though could be easily
6598 extended if required. */
6599 gcc_assert (nops >= 2 && nops <= 4);
6601 /* Loop over the operands and check that the memory references are
6602 suitable (i.e. immediate offsets from the same base register). At
6603 the same time, extract the target register, and the memory
6605 for (i = 0; i < nops; i++)
6610 /* Convert a subreg of a mem into the mem itself. */
6611 if (GET_CODE (operands[nops + i]) == SUBREG)
6612 operands[nops + i] = alter_subreg (operands + (nops + i));
6614 gcc_assert (GET_CODE (operands[nops + i]) == MEM);
6616 /* Don't reorder volatile memory references; it doesn't seem worth
6617 looking for the case where the order is ok anyway. */
6618 if (MEM_VOLATILE_P (operands[nops + i]))
6621 offset = const0_rtx;
6623 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
6624 || (GET_CODE (reg) == SUBREG
6625 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
6626 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
6627 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
6629 || (GET_CODE (reg) == SUBREG
6630 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
6631 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
6636 base_reg = REGNO (reg);
6637 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
6638 ? REGNO (operands[i])
6639 : REGNO (SUBREG_REG (operands[i])));
6644 if (base_reg != (int) REGNO (reg))
6645 /* Not addressed from the same base register. */
6648 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
6649 ? REGNO (operands[i])
6650 : REGNO (SUBREG_REG (operands[i])));
6651 if (unsorted_regs[i] < unsorted_regs[order[0]])
6655 /* If it isn't an integer register, then we can't do this. */
6656 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14)
6659 unsorted_offsets[i] = INTVAL (offset);
6662 /* Not a suitable memory address. */
6666 /* All the useful information has now been extracted from the
6667 operands into unsorted_regs and unsorted_offsets; additionally,
6668 order[0] has been set to the lowest numbered register in the
6669 list. Sort the registers into order, and check that the memory
6670 offsets are ascending and adjacent. */
6672 for (i = 1; i < nops; i++)
6676 order[i] = order[i - 1];
6677 for (j = 0; j < nops; j++)
6678 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
6679 && (order[i] == order[i - 1]
6680 || unsorted_regs[j] < unsorted_regs[order[i]]))
6683 /* Have we found a suitable register? if not, one must be used more
6685 if (order[i] == order[i - 1])
6688 /* Is the memory address adjacent and ascending? */
6689 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
6697 for (i = 0; i < nops; i++)
6698 regs[i] = unsorted_regs[order[i]];
6700 *load_offset = unsorted_offsets[order[0]];
6703 if (unsorted_offsets[order[0]] == 0)
6704 return 1; /* stmia */
6706 if (unsorted_offsets[order[0]] == 4)
6707 return 2; /* stmib */
6709 if (unsorted_offsets[order[nops - 1]] == 0)
6710 return 3; /* stmda */
6712 if (unsorted_offsets[order[nops - 1]] == -4)
6713 return 4; /* stmdb */
6719 emit_stm_seq (rtx *operands, int nops)
6723 HOST_WIDE_INT offset;
6727 switch (store_multiple_sequence (operands, nops, regs, &base_reg, &offset))
6730 strcpy (buf, "stm%(ia%)\t");
6734 strcpy (buf, "stm%(ib%)\t");
6738 strcpy (buf, "stm%(da%)\t");
6742 strcpy (buf, "stm%(db%)\t");
6749 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
6750 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
6752 for (i = 1; i < nops; i++)
6753 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
6754 reg_names[regs[i]]);
6756 strcat (buf, "}\t%@ phole stm");
6758 output_asm_insn (buf, operands);
6762 /* Routines for use in generating RTL. */
6765 arm_gen_load_multiple (int base_regno, int count, rtx from, int up,
6766 int write_back, rtx basemem, HOST_WIDE_INT *offsetp)
6768 HOST_WIDE_INT offset = *offsetp;
6771 int sign = up ? 1 : -1;
6774 /* XScale has load-store double instructions, but they have stricter
6775 alignment requirements than load-store multiple, so we cannot
6778 For XScale ldm requires 2 + NREGS cycles to complete and blocks
6779 the pipeline until completion.
6787 An ldr instruction takes 1-3 cycles, but does not block the
6796 Best case ldr will always win. However, the more ldr instructions
6797 we issue, the less likely we are to be able to schedule them well.
6798 Using ldr instructions also increases code size.
6800 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
6801 for counts of 3 or 4 regs. */
6802 if (arm_tune_xscale && count <= 2 && ! optimize_size)
6808 for (i = 0; i < count; i++)
6810 addr = plus_constant (from, i * 4 * sign);
6811 mem = adjust_automodify_address (basemem, SImode, addr, offset);
6812 emit_move_insn (gen_rtx_REG (SImode, base_regno + i), mem);
6818 emit_move_insn (from, plus_constant (from, count * 4 * sign));
6828 result = gen_rtx_PARALLEL (VOIDmode,
6829 rtvec_alloc (count + (write_back ? 1 : 0)));
6832 XVECEXP (result, 0, 0)
6833 = gen_rtx_SET (VOIDmode, from, plus_constant (from, count * 4 * sign));
6838 for (j = 0; i < count; i++, j++)
6840 addr = plus_constant (from, j * 4 * sign);
6841 mem = adjust_automodify_address_nv (basemem, SImode, addr, offset);
6842 XVECEXP (result, 0, i)
6843 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, base_regno + j), mem);
6854 arm_gen_store_multiple (int base_regno, int count, rtx to, int up,
6855 int write_back, rtx basemem, HOST_WIDE_INT *offsetp)
6857 HOST_WIDE_INT offset = *offsetp;
6860 int sign = up ? 1 : -1;
6863 /* See arm_gen_load_multiple for discussion of
6864 the pros/cons of ldm/stm usage for XScale. */
6865 if (arm_tune_xscale && count <= 2 && ! optimize_size)
6871 for (i = 0; i < count; i++)
6873 addr = plus_constant (to, i * 4 * sign);
6874 mem = adjust_automodify_address (basemem, SImode, addr, offset);
6875 emit_move_insn (mem, gen_rtx_REG (SImode, base_regno + i));
6881 emit_move_insn (to, plus_constant (to, count * 4 * sign));
6891 result = gen_rtx_PARALLEL (VOIDmode,
6892 rtvec_alloc (count + (write_back ? 1 : 0)));
6895 XVECEXP (result, 0, 0)
6896 = gen_rtx_SET (VOIDmode, to,
6897 plus_constant (to, count * 4 * sign));
6902 for (j = 0; i < count; i++, j++)
6904 addr = plus_constant (to, j * 4 * sign);
6905 mem = adjust_automodify_address_nv (basemem, SImode, addr, offset);
6906 XVECEXP (result, 0, i)
6907 = gen_rtx_SET (VOIDmode, mem, gen_rtx_REG (SImode, base_regno + j));
6918 arm_gen_movmemqi (rtx *operands)
6920 HOST_WIDE_INT in_words_to_go, out_words_to_go, last_bytes;
6921 HOST_WIDE_INT srcoffset, dstoffset;
6923 rtx src, dst, srcbase, dstbase;
6924 rtx part_bytes_reg = NULL;
6927 if (GET_CODE (operands[2]) != CONST_INT
6928 || GET_CODE (operands[3]) != CONST_INT
6929 || INTVAL (operands[2]) > 64
6930 || INTVAL (operands[3]) & 3)
6933 dstbase = operands[0];
6934 srcbase = operands[1];
6936 dst = copy_to_mode_reg (SImode, XEXP (dstbase, 0));
6937 src = copy_to_mode_reg (SImode, XEXP (srcbase, 0));
6939 in_words_to_go = ARM_NUM_INTS (INTVAL (operands[2]));
6940 out_words_to_go = INTVAL (operands[2]) / 4;
6941 last_bytes = INTVAL (operands[2]) & 3;
6942 dstoffset = srcoffset = 0;
6944 if (out_words_to_go != in_words_to_go && ((in_words_to_go - 1) & 3) != 0)
6945 part_bytes_reg = gen_rtx_REG (SImode, (in_words_to_go - 1) & 3);
6947 for (i = 0; in_words_to_go >= 2; i+=4)
6949 if (in_words_to_go > 4)
6950 emit_insn (arm_gen_load_multiple (0, 4, src, TRUE, TRUE,
6951 srcbase, &srcoffset));
6953 emit_insn (arm_gen_load_multiple (0, in_words_to_go, src, TRUE,
6954 FALSE, srcbase, &srcoffset));
6956 if (out_words_to_go)
6958 if (out_words_to_go > 4)
6959 emit_insn (arm_gen_store_multiple (0, 4, dst, TRUE, TRUE,
6960 dstbase, &dstoffset));
6961 else if (out_words_to_go != 1)
6962 emit_insn (arm_gen_store_multiple (0, out_words_to_go,
6966 dstbase, &dstoffset));
6969 mem = adjust_automodify_address (dstbase, SImode, dst, dstoffset);
6970 emit_move_insn (mem, gen_rtx_REG (SImode, 0));
6971 if (last_bytes != 0)
6973 emit_insn (gen_addsi3 (dst, dst, GEN_INT (4)));
6979 in_words_to_go -= in_words_to_go < 4 ? in_words_to_go : 4;
6980 out_words_to_go -= out_words_to_go < 4 ? out_words_to_go : 4;
6983 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
6984 if (out_words_to_go)
6988 mem = adjust_automodify_address (srcbase, SImode, src, srcoffset);
6989 sreg = copy_to_reg (mem);
6991 mem = adjust_automodify_address (dstbase, SImode, dst, dstoffset);
6992 emit_move_insn (mem, sreg);
6995 gcc_assert (!in_words_to_go); /* Sanity check */
7000 gcc_assert (in_words_to_go > 0);
7002 mem = adjust_automodify_address (srcbase, SImode, src, srcoffset);
7003 part_bytes_reg = copy_to_mode_reg (SImode, mem);
7006 gcc_assert (!last_bytes || part_bytes_reg);
7008 if (BYTES_BIG_ENDIAN && last_bytes)
7010 rtx tmp = gen_reg_rtx (SImode);
7012 /* The bytes we want are in the top end of the word. */
7013 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg,
7014 GEN_INT (8 * (4 - last_bytes))));
7015 part_bytes_reg = tmp;
7019 mem = adjust_automodify_address (dstbase, QImode,
7020 plus_constant (dst, last_bytes - 1),
7021 dstoffset + last_bytes - 1);
7022 emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
7026 tmp = gen_reg_rtx (SImode);
7027 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8)));
7028 part_bytes_reg = tmp;
7037 mem = adjust_automodify_address (dstbase, HImode, dst, dstoffset);
7038 emit_move_insn (mem, gen_lowpart (HImode, part_bytes_reg));
7042 rtx tmp = gen_reg_rtx (SImode);
7043 emit_insn (gen_addsi3 (dst, dst, const2_rtx));
7044 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (16)));
7045 part_bytes_reg = tmp;
7052 mem = adjust_automodify_address (dstbase, QImode, dst, dstoffset);
7053 emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
7060 /* Select a dominance comparison mode if possible for a test of the general
7061 form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms.
7062 COND_OR == DOM_CC_X_AND_Y => (X && Y)
7063 COND_OR == DOM_CC_NX_OR_Y => ((! X) || Y)
7064 COND_OR == DOM_CC_X_OR_Y => (X || Y)
7065 In all cases OP will be either EQ or NE, but we don't need to know which
7066 here. If we are unable to support a dominance comparison we return
7067 CC mode. This will then fail to match for the RTL expressions that
7068 generate this call. */
7070 arm_select_dominance_cc_mode (rtx x, rtx y, HOST_WIDE_INT cond_or)
7072 enum rtx_code cond1, cond2;
7075 /* Currently we will probably get the wrong result if the individual
7076 comparisons are not simple. This also ensures that it is safe to
7077 reverse a comparison if necessary. */
7078 if ((arm_select_cc_mode (cond1 = GET_CODE (x), XEXP (x, 0), XEXP (x, 1))
7080 || (arm_select_cc_mode (cond2 = GET_CODE (y), XEXP (y, 0), XEXP (y, 1))
7084 /* The if_then_else variant of this tests the second condition if the
7085 first passes, but is true if the first fails. Reverse the first
7086 condition to get a true "inclusive-or" expression. */
7087 if (cond_or == DOM_CC_NX_OR_Y)
7088 cond1 = reverse_condition (cond1);
7090 /* If the comparisons are not equal, and one doesn't dominate the other,
7091 then we can't do this. */
7093 && !comparison_dominates_p (cond1, cond2)
7094 && (swapped = 1, !comparison_dominates_p (cond2, cond1)))
7099 enum rtx_code temp = cond1;
7107 if (cond_or == DOM_CC_X_AND_Y)
7112 case EQ: return CC_DEQmode;
7113 case LE: return CC_DLEmode;
7114 case LEU: return CC_DLEUmode;
7115 case GE: return CC_DGEmode;
7116 case GEU: return CC_DGEUmode;
7117 default: gcc_unreachable ();
7121 if (cond_or == DOM_CC_X_AND_Y)
7137 if (cond_or == DOM_CC_X_AND_Y)
7153 if (cond_or == DOM_CC_X_AND_Y)
7169 if (cond_or == DOM_CC_X_AND_Y)
7184 /* The remaining cases only occur when both comparisons are the
7187 gcc_assert (cond1 == cond2);
7191 gcc_assert (cond1 == cond2);
7195 gcc_assert (cond1 == cond2);
7199 gcc_assert (cond1 == cond2);
7203 gcc_assert (cond1 == cond2);
7212 arm_select_cc_mode (enum rtx_code op, rtx x, rtx y)
7214 /* All floating point compares return CCFP if it is an equality
7215 comparison, and CCFPE otherwise. */
7216 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
7236 if (TARGET_HARD_FLOAT && TARGET_MAVERICK)
7245 /* A compare with a shifted operand. Because of canonicalization, the
7246 comparison will have to be swapped when we emit the assembler. */
7247 if (GET_MODE (y) == SImode && GET_CODE (y) == REG
7248 && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
7249 || GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE
7250 || GET_CODE (x) == ROTATERT))
7253 /* This operation is performed swapped, but since we only rely on the Z
7254 flag we don't need an additional mode. */
7255 if (GET_MODE (y) == SImode && REG_P (y)
7256 && GET_CODE (x) == NEG
7257 && (op == EQ || op == NE))
7260 /* This is a special case that is used by combine to allow a
7261 comparison of a shifted byte load to be split into a zero-extend
7262 followed by a comparison of the shifted integer (only valid for
7263 equalities and unsigned inequalities). */
7264 if (GET_MODE (x) == SImode
7265 && GET_CODE (x) == ASHIFT
7266 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 24
7267 && GET_CODE (XEXP (x, 0)) == SUBREG
7268 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == MEM
7269 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == QImode
7270 && (op == EQ || op == NE
7271 || op == GEU || op == GTU || op == LTU || op == LEU)
7272 && GET_CODE (y) == CONST_INT)
7275 /* A construct for a conditional compare, if the false arm contains
7276 0, then both conditions must be true, otherwise either condition
7277 must be true. Not all conditions are possible, so CCmode is
7278 returned if it can't be done. */
7279 if (GET_CODE (x) == IF_THEN_ELSE
7280 && (XEXP (x, 2) == const0_rtx
7281 || XEXP (x, 2) == const1_rtx)
7282 && COMPARISON_P (XEXP (x, 0))
7283 && COMPARISON_P (XEXP (x, 1)))
7284 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
7285 INTVAL (XEXP (x, 2)));
7287 /* Alternate canonicalizations of the above. These are somewhat cleaner. */
7288 if (GET_CODE (x) == AND
7289 && COMPARISON_P (XEXP (x, 0))
7290 && COMPARISON_P (XEXP (x, 1)))
7291 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
7294 if (GET_CODE (x) == IOR
7295 && COMPARISON_P (XEXP (x, 0))
7296 && COMPARISON_P (XEXP (x, 1)))
7297 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
7300 /* An operation (on Thumb) where we want to test for a single bit.
7301 This is done by shifting that bit up into the top bit of a
7302 scratch register; we can then branch on the sign bit. */
7304 && GET_MODE (x) == SImode
7305 && (op == EQ || op == NE)
7306 && GET_CODE (x) == ZERO_EXTRACT
7307 && XEXP (x, 1) == const1_rtx)
7310 /* An operation that sets the condition codes as a side-effect, the
7311 V flag is not set correctly, so we can only use comparisons where
7312 this doesn't matter. (For LT and GE we can use "mi" and "pl"
7314 /* ??? Does the ZERO_EXTRACT case really apply to thumb2? */
7315 if (GET_MODE (x) == SImode
7317 && (op == EQ || op == NE || op == LT || op == GE)
7318 && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
7319 || GET_CODE (x) == AND || GET_CODE (x) == IOR
7320 || GET_CODE (x) == XOR || GET_CODE (x) == MULT
7321 || GET_CODE (x) == NOT || GET_CODE (x) == NEG
7322 || GET_CODE (x) == LSHIFTRT
7323 || GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
7324 || GET_CODE (x) == ROTATERT
7325 || (TARGET_32BIT && GET_CODE (x) == ZERO_EXTRACT)))
7328 if (GET_MODE (x) == QImode && (op == EQ || op == NE))
7331 if (GET_MODE (x) == SImode && (op == LTU || op == GEU)
7332 && GET_CODE (x) == PLUS
7333 && (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y)))
7339 /* X and Y are two things to compare using CODE. Emit the compare insn and
7340 return the rtx for register 0 in the proper mode. FP means this is a
7341 floating point compare: I don't think that it is needed on the arm. */
7343 arm_gen_compare_reg (enum rtx_code code, rtx x, rtx y)
7345 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
7346 rtx cc_reg = gen_rtx_REG (mode, CC_REGNUM);
7348 emit_set_insn (cc_reg, gen_rtx_COMPARE (mode, x, y));
7353 /* Generate a sequence of insns that will generate the correct return
7354 address mask depending on the physical architecture that the program
7357 arm_gen_return_addr_mask (void)
7359 rtx reg = gen_reg_rtx (Pmode);
7361 emit_insn (gen_return_addr_mask (reg));
7366 arm_reload_in_hi (rtx *operands)
7368 rtx ref = operands[1];
7370 HOST_WIDE_INT offset = 0;
7372 if (GET_CODE (ref) == SUBREG)
7374 offset = SUBREG_BYTE (ref);
7375 ref = SUBREG_REG (ref);
7378 if (GET_CODE (ref) == REG)
7380 /* We have a pseudo which has been spilt onto the stack; there
7381 are two cases here: the first where there is a simple
7382 stack-slot replacement and a second where the stack-slot is
7383 out of range, or is used as a subreg. */
7384 if (reg_equiv_mem[REGNO (ref)])
7386 ref = reg_equiv_mem[REGNO (ref)];
7387 base = find_replacement (&XEXP (ref, 0));
7390 /* The slot is out of range, or was dressed up in a SUBREG. */
7391 base = reg_equiv_address[REGNO (ref)];
7394 base = find_replacement (&XEXP (ref, 0));
7396 /* Handle the case where the address is too complex to be offset by 1. */
7397 if (GET_CODE (base) == MINUS
7398 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
7400 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
7402 emit_set_insn (base_plus, base);
7405 else if (GET_CODE (base) == PLUS)
7407 /* The addend must be CONST_INT, or we would have dealt with it above. */
7408 HOST_WIDE_INT hi, lo;
7410 offset += INTVAL (XEXP (base, 1));
7411 base = XEXP (base, 0);
7413 /* Rework the address into a legal sequence of insns. */
7414 /* Valid range for lo is -4095 -> 4095 */
7417 : -((-offset) & 0xfff));
7419 /* Corner case, if lo is the max offset then we would be out of range
7420 once we have added the additional 1 below, so bump the msb into the
7421 pre-loading insn(s). */
7425 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff)
7426 ^ (HOST_WIDE_INT) 0x80000000)
7427 - (HOST_WIDE_INT) 0x80000000);
7429 gcc_assert (hi + lo == offset);
7433 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
7435 /* Get the base address; addsi3 knows how to handle constants
7436 that require more than one insn. */
7437 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
7443 /* Operands[2] may overlap operands[0] (though it won't overlap
7444 operands[1]), that's why we asked for a DImode reg -- so we can
7445 use the bit that does not overlap. */
7446 if (REGNO (operands[2]) == REGNO (operands[0]))
7447 scratch = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
7449 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
7451 emit_insn (gen_zero_extendqisi2 (scratch,
7452 gen_rtx_MEM (QImode,
7453 plus_constant (base,
7455 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode, operands[0], 0),
7456 gen_rtx_MEM (QImode,
7457 plus_constant (base,
7459 if (!BYTES_BIG_ENDIAN)
7460 emit_set_insn (gen_rtx_SUBREG (SImode, operands[0], 0),
7461 gen_rtx_IOR (SImode,
7464 gen_rtx_SUBREG (SImode, operands[0], 0),
7468 emit_set_insn (gen_rtx_SUBREG (SImode, operands[0], 0),
7469 gen_rtx_IOR (SImode,
7470 gen_rtx_ASHIFT (SImode, scratch,
7472 gen_rtx_SUBREG (SImode, operands[0], 0)));
7475 /* Handle storing a half-word to memory during reload by synthesizing as two
7476 byte stores. Take care not to clobber the input values until after we
7477 have moved them somewhere safe. This code assumes that if the DImode
7478 scratch in operands[2] overlaps either the input value or output address
7479 in some way, then that value must die in this insn (we absolutely need
7480 two scratch registers for some corner cases). */
7482 arm_reload_out_hi (rtx *operands)
7484 rtx ref = operands[0];
7485 rtx outval = operands[1];
7487 HOST_WIDE_INT offset = 0;
7489 if (GET_CODE (ref) == SUBREG)
7491 offset = SUBREG_BYTE (ref);
7492 ref = SUBREG_REG (ref);
7495 if (GET_CODE (ref) == REG)
7497 /* We have a pseudo which has been spilt onto the stack; there
7498 are two cases here: the first where there is a simple
7499 stack-slot replacement and a second where the stack-slot is
7500 out of range, or is used as a subreg. */
7501 if (reg_equiv_mem[REGNO (ref)])
7503 ref = reg_equiv_mem[REGNO (ref)];
7504 base = find_replacement (&XEXP (ref, 0));
7507 /* The slot is out of range, or was dressed up in a SUBREG. */
7508 base = reg_equiv_address[REGNO (ref)];
7511 base = find_replacement (&XEXP (ref, 0));
7513 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
7515 /* Handle the case where the address is too complex to be offset by 1. */
7516 if (GET_CODE (base) == MINUS
7517 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
7519 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
7521 /* Be careful not to destroy OUTVAL. */
7522 if (reg_overlap_mentioned_p (base_plus, outval))
7524 /* Updating base_plus might destroy outval, see if we can
7525 swap the scratch and base_plus. */
7526 if (!reg_overlap_mentioned_p (scratch, outval))
7529 scratch = base_plus;
7534 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
7536 /* Be conservative and copy OUTVAL into the scratch now,
7537 this should only be necessary if outval is a subreg
7538 of something larger than a word. */
7539 /* XXX Might this clobber base? I can't see how it can,
7540 since scratch is known to overlap with OUTVAL, and
7541 must be wider than a word. */
7542 emit_insn (gen_movhi (scratch_hi, outval));
7543 outval = scratch_hi;
7547 emit_set_insn (base_plus, base);
7550 else if (GET_CODE (base) == PLUS)
7552 /* The addend must be CONST_INT, or we would have dealt with it above. */
7553 HOST_WIDE_INT hi, lo;
7555 offset += INTVAL (XEXP (base, 1));
7556 base = XEXP (base, 0);
7558 /* Rework the address into a legal sequence of insns. */
7559 /* Valid range for lo is -4095 -> 4095 */
7562 : -((-offset) & 0xfff));
7564 /* Corner case, if lo is the max offset then we would be out of range
7565 once we have added the additional 1 below, so bump the msb into the
7566 pre-loading insn(s). */
7570 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff)
7571 ^ (HOST_WIDE_INT) 0x80000000)
7572 - (HOST_WIDE_INT) 0x80000000);
7574 gcc_assert (hi + lo == offset);
7578 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
7580 /* Be careful not to destroy OUTVAL. */
7581 if (reg_overlap_mentioned_p (base_plus, outval))
7583 /* Updating base_plus might destroy outval, see if we
7584 can swap the scratch and base_plus. */
7585 if (!reg_overlap_mentioned_p (scratch, outval))
7588 scratch = base_plus;
7593 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
7595 /* Be conservative and copy outval into scratch now,
7596 this should only be necessary if outval is a
7597 subreg of something larger than a word. */
7598 /* XXX Might this clobber base? I can't see how it
7599 can, since scratch is known to overlap with
7601 emit_insn (gen_movhi (scratch_hi, outval));
7602 outval = scratch_hi;
7606 /* Get the base address; addsi3 knows how to handle constants
7607 that require more than one insn. */
7608 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
7614 if (BYTES_BIG_ENDIAN)
7616 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
7617 plus_constant (base, offset + 1)),
7618 gen_lowpart (QImode, outval)));
7619 emit_insn (gen_lshrsi3 (scratch,
7620 gen_rtx_SUBREG (SImode, outval, 0),
7622 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
7623 gen_lowpart (QImode, scratch)));
7627 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
7628 gen_lowpart (QImode, outval)));
7629 emit_insn (gen_lshrsi3 (scratch,
7630 gen_rtx_SUBREG (SImode, outval, 0),
7632 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
7633 plus_constant (base, offset + 1)),
7634 gen_lowpart (QImode, scratch)));
7638 /* Return true if a type must be passed in memory. For AAPCS, small aggregates
7639 (padded to the size of a word) should be passed in a register. */
7642 arm_must_pass_in_stack (enum machine_mode mode, tree type)
7644 if (TARGET_AAPCS_BASED)
7645 return must_pass_in_stack_var_size (mode, type);
7647 return must_pass_in_stack_var_size_or_pad (mode, type);
7651 /* For use by FUNCTION_ARG_PADDING (MODE, TYPE).
7652 Return true if an argument passed on the stack should be padded upwards,
7653 i.e. if the least-significant byte has useful data.
7654 For legacy APCS ABIs we use the default. For AAPCS based ABIs small
7655 aggregate types are placed in the lowest memory address. */
7658 arm_pad_arg_upward (enum machine_mode mode, tree type)
7660 if (!TARGET_AAPCS_BASED)
7661 return DEFAULT_FUNCTION_ARG_PADDING(mode, type) == upward;
7663 if (type && BYTES_BIG_ENDIAN && INTEGRAL_TYPE_P (type))
7670 /* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST).
7671 For non-AAPCS, return !BYTES_BIG_ENDIAN if the least significant
7672 byte of the register has useful data, and return the opposite if the
7673 most significant byte does.
7674 For AAPCS, small aggregates and small complex types are always padded
7678 arm_pad_reg_upward (enum machine_mode mode ATTRIBUTE_UNUSED,
7679 tree type, int first ATTRIBUTE_UNUSED)
7681 if (TARGET_AAPCS_BASED
7683 && (AGGREGATE_TYPE_P (type) || TREE_CODE (type) == COMPLEX_TYPE)
7684 && int_size_in_bytes (type) <= 4)
7687 /* Otherwise, use default padding. */
7688 return !BYTES_BIG_ENDIAN;
7692 /* Print a symbolic form of X to the debug file, F. */
7694 arm_print_value (FILE *f, rtx x)
7696 switch (GET_CODE (x))
7699 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (x));
7703 fprintf (f, "<0x%lx,0x%lx>", (long)XWINT (x, 2), (long)XWINT (x, 3));
7711 for (i = 0; i < CONST_VECTOR_NUNITS (x); i++)
7713 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (CONST_VECTOR_ELT (x, i)));
7714 if (i < (CONST_VECTOR_NUNITS (x) - 1))
7722 fprintf (f, "\"%s\"", XSTR (x, 0));
7726 fprintf (f, "`%s'", XSTR (x, 0));
7730 fprintf (f, "L%d", INSN_UID (XEXP (x, 0)));
7734 arm_print_value (f, XEXP (x, 0));
7738 arm_print_value (f, XEXP (x, 0));
7740 arm_print_value (f, XEXP (x, 1));
7748 fprintf (f, "????");
7753 /* Routines for manipulation of the constant pool. */
7755 /* Arm instructions cannot load a large constant directly into a
7756 register; they have to come from a pc relative load. The constant
7757 must therefore be placed in the addressable range of the pc
7758 relative load. Depending on the precise pc relative load
7759 instruction the range is somewhere between 256 bytes and 4k. This
7760 means that we often have to dump a constant inside a function, and
7761 generate code to branch around it.
7763 It is important to minimize this, since the branches will slow
7764 things down and make the code larger.
7766 Normally we can hide the table after an existing unconditional
7767 branch so that there is no interruption of the flow, but in the
7768 worst case the code looks like this:
7786 We fix this by performing a scan after scheduling, which notices
7787 which instructions need to have their operands fetched from the
7788 constant table and builds the table.
7790 The algorithm starts by building a table of all the constants that
7791 need fixing up and all the natural barriers in the function (places
7792 where a constant table can be dropped without breaking the flow).
7793 For each fixup we note how far the pc-relative replacement will be
7794 able to reach and the offset of the instruction into the function.
7796 Having built the table we then group the fixes together to form
7797 tables that are as large as possible (subject to addressing
7798 constraints) and emit each table of constants after the last
7799 barrier that is within range of all the instructions in the group.
7800 If a group does not contain a barrier, then we forcibly create one
7801 by inserting a jump instruction into the flow. Once the table has
7802 been inserted, the insns are then modified to reference the
7803 relevant entry in the pool.
7805 Possible enhancements to the algorithm (not implemented) are:
7807 1) For some processors and object formats, there may be benefit in
7808 aligning the pools to the start of cache lines; this alignment
7809 would need to be taken into account when calculating addressability
7812 /* These typedefs are located at the start of this file, so that
7813 they can be used in the prototypes there. This comment is to
7814 remind readers of that fact so that the following structures
7815 can be understood more easily.
7817 typedef struct minipool_node Mnode;
7818 typedef struct minipool_fixup Mfix; */
7820 struct minipool_node
7822 /* Doubly linked chain of entries. */
7825 /* The maximum offset into the code that this entry can be placed. While
7826 pushing fixes for forward references, all entries are sorted in order
7827 of increasing max_address. */
7828 HOST_WIDE_INT max_address;
7829 /* Similarly for an entry inserted for a backwards ref. */
7830 HOST_WIDE_INT min_address;
7831 /* The number of fixes referencing this entry. This can become zero
7832 if we "unpush" an entry. In this case we ignore the entry when we
7833 come to emit the code. */
7835 /* The offset from the start of the minipool. */
7836 HOST_WIDE_INT offset;
7837 /* The value in table. */
7839 /* The mode of value. */
7840 enum machine_mode mode;
7841 /* The size of the value. With iWMMXt enabled
7842 sizes > 4 also imply an alignment of 8-bytes. */
7846 struct minipool_fixup
7850 HOST_WIDE_INT address;
7852 enum machine_mode mode;
7856 HOST_WIDE_INT forwards;
7857 HOST_WIDE_INT backwards;
7860 /* Fixes less than a word need padding out to a word boundary. */
7861 #define MINIPOOL_FIX_SIZE(mode) \
7862 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4)
7864 static Mnode * minipool_vector_head;
7865 static Mnode * minipool_vector_tail;
7866 static rtx minipool_vector_label;
7867 static int minipool_pad;
7869 /* The linked list of all minipool fixes required for this function. */
7870 Mfix * minipool_fix_head;
7871 Mfix * minipool_fix_tail;
7872 /* The fix entry for the current minipool, once it has been placed. */
7873 Mfix * minipool_barrier;
7875 /* Determines if INSN is the start of a jump table. Returns the end
7876 of the TABLE or NULL_RTX. */
7878 is_jump_table (rtx insn)
7882 if (GET_CODE (insn) == JUMP_INSN
7883 && JUMP_LABEL (insn) != NULL
7884 && ((table = next_real_insn (JUMP_LABEL (insn)))
7885 == next_real_insn (insn))
7887 && GET_CODE (table) == JUMP_INSN
7888 && (GET_CODE (PATTERN (table)) == ADDR_VEC
7889 || GET_CODE (PATTERN (table)) == ADDR_DIFF_VEC))
7895 #ifndef JUMP_TABLES_IN_TEXT_SECTION
7896 #define JUMP_TABLES_IN_TEXT_SECTION 0
7899 static HOST_WIDE_INT
7900 get_jump_table_size (rtx insn)
7902 /* ADDR_VECs only take room if read-only data does into the text
7904 if (JUMP_TABLES_IN_TEXT_SECTION || readonly_data_section == text_section)
7906 rtx body = PATTERN (insn);
7907 int elt = GET_CODE (body) == ADDR_DIFF_VEC ? 1 : 0;
7909 HOST_WIDE_INT modesize;
7911 modesize = GET_MODE_SIZE (GET_MODE (body));
7912 size = modesize * XVECLEN (body, elt);
7916 /* Round up size of TBB table to a halfword boundary. */
7917 size = (size + 1) & ~(HOST_WIDE_INT)1;
7920 /* No padding necessary for TBH. */
7923 /* Add two bytes for alignment on Thumb. */
7936 /* Move a minipool fix MP from its current location to before MAX_MP.
7937 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
7938 constraints may need updating. */
7940 move_minipool_fix_forward_ref (Mnode *mp, Mnode *max_mp,
7941 HOST_WIDE_INT max_address)
7943 /* The code below assumes these are different. */
7944 gcc_assert (mp != max_mp);
7948 if (max_address < mp->max_address)
7949 mp->max_address = max_address;
7953 if (max_address > max_mp->max_address - mp->fix_size)
7954 mp->max_address = max_mp->max_address - mp->fix_size;
7956 mp->max_address = max_address;
7958 /* Unlink MP from its current position. Since max_mp is non-null,
7959 mp->prev must be non-null. */
7960 mp->prev->next = mp->next;
7961 if (mp->next != NULL)
7962 mp->next->prev = mp->prev;
7964 minipool_vector_tail = mp->prev;
7966 /* Re-insert it before MAX_MP. */
7968 mp->prev = max_mp->prev;
7971 if (mp->prev != NULL)
7972 mp->prev->next = mp;
7974 minipool_vector_head = mp;
7977 /* Save the new entry. */
7980 /* Scan over the preceding entries and adjust their addresses as
7982 while (mp->prev != NULL
7983 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
7985 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
7992 /* Add a constant to the minipool for a forward reference. Returns the
7993 node added or NULL if the constant will not fit in this pool. */
7995 add_minipool_forward_ref (Mfix *fix)
7997 /* If set, max_mp is the first pool_entry that has a lower
7998 constraint than the one we are trying to add. */
7999 Mnode * max_mp = NULL;
8000 HOST_WIDE_INT max_address = fix->address + fix->forwards - minipool_pad;
8003 /* If the minipool starts before the end of FIX->INSN then this FIX
8004 can not be placed into the current pool. Furthermore, adding the
8005 new constant pool entry may cause the pool to start FIX_SIZE bytes
8007 if (minipool_vector_head &&
8008 (fix->address + get_attr_length (fix->insn)
8009 >= minipool_vector_head->max_address - fix->fix_size))
8012 /* Scan the pool to see if a constant with the same value has
8013 already been added. While we are doing this, also note the
8014 location where we must insert the constant if it doesn't already
8016 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
8018 if (GET_CODE (fix->value) == GET_CODE (mp->value)
8019 && fix->mode == mp->mode
8020 && (GET_CODE (fix->value) != CODE_LABEL
8021 || (CODE_LABEL_NUMBER (fix->value)
8022 == CODE_LABEL_NUMBER (mp->value)))
8023 && rtx_equal_p (fix->value, mp->value))
8025 /* More than one fix references this entry. */
8027 return move_minipool_fix_forward_ref (mp, max_mp, max_address);
8030 /* Note the insertion point if necessary. */
8032 && mp->max_address > max_address)
8035 /* If we are inserting an 8-bytes aligned quantity and
8036 we have not already found an insertion point, then
8037 make sure that all such 8-byte aligned quantities are
8038 placed at the start of the pool. */
8039 if (ARM_DOUBLEWORD_ALIGN
8041 && fix->fix_size == 8
8042 && mp->fix_size != 8)
8045 max_address = mp->max_address;
8049 /* The value is not currently in the minipool, so we need to create
8050 a new entry for it. If MAX_MP is NULL, the entry will be put on
8051 the end of the list since the placement is less constrained than
8052 any existing entry. Otherwise, we insert the new fix before
8053 MAX_MP and, if necessary, adjust the constraints on the other
8056 mp->fix_size = fix->fix_size;
8057 mp->mode = fix->mode;
8058 mp->value = fix->value;
8060 /* Not yet required for a backwards ref. */
8061 mp->min_address = -65536;
8065 mp->max_address = max_address;
8067 mp->prev = minipool_vector_tail;
8069 if (mp->prev == NULL)
8071 minipool_vector_head = mp;
8072 minipool_vector_label = gen_label_rtx ();
8075 mp->prev->next = mp;
8077 minipool_vector_tail = mp;
8081 if (max_address > max_mp->max_address - mp->fix_size)
8082 mp->max_address = max_mp->max_address - mp->fix_size;
8084 mp->max_address = max_address;
8087 mp->prev = max_mp->prev;
8089 if (mp->prev != NULL)
8090 mp->prev->next = mp;
8092 minipool_vector_head = mp;
8095 /* Save the new entry. */
8098 /* Scan over the preceding entries and adjust their addresses as
8100 while (mp->prev != NULL
8101 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
8103 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
8111 move_minipool_fix_backward_ref (Mnode *mp, Mnode *min_mp,
8112 HOST_WIDE_INT min_address)
8114 HOST_WIDE_INT offset;
8116 /* The code below assumes these are different. */
8117 gcc_assert (mp != min_mp);
8121 if (min_address > mp->min_address)
8122 mp->min_address = min_address;
8126 /* We will adjust this below if it is too loose. */
8127 mp->min_address = min_address;
8129 /* Unlink MP from its current position. Since min_mp is non-null,
8130 mp->next must be non-null. */
8131 mp->next->prev = mp->prev;
8132 if (mp->prev != NULL)
8133 mp->prev->next = mp->next;
8135 minipool_vector_head = mp->next;
8137 /* Reinsert it after MIN_MP. */
8139 mp->next = min_mp->next;
8141 if (mp->next != NULL)
8142 mp->next->prev = mp;
8144 minipool_vector_tail = mp;
8150 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
8152 mp->offset = offset;
8153 if (mp->refcount > 0)
8154 offset += mp->fix_size;
8156 if (mp->next && mp->next->min_address < mp->min_address + mp->fix_size)
8157 mp->next->min_address = mp->min_address + mp->fix_size;
8163 /* Add a constant to the minipool for a backward reference. Returns the
8164 node added or NULL if the constant will not fit in this pool.
8166 Note that the code for insertion for a backwards reference can be
8167 somewhat confusing because the calculated offsets for each fix do
8168 not take into account the size of the pool (which is still under
8171 add_minipool_backward_ref (Mfix *fix)
8173 /* If set, min_mp is the last pool_entry that has a lower constraint
8174 than the one we are trying to add. */
8175 Mnode *min_mp = NULL;
8176 /* This can be negative, since it is only a constraint. */
8177 HOST_WIDE_INT min_address = fix->address - fix->backwards;
8180 /* If we can't reach the current pool from this insn, or if we can't
8181 insert this entry at the end of the pool without pushing other
8182 fixes out of range, then we don't try. This ensures that we
8183 can't fail later on. */
8184 if (min_address >= minipool_barrier->address
8185 || (minipool_vector_tail->min_address + fix->fix_size
8186 >= minipool_barrier->address))
8189 /* Scan the pool to see if a constant with the same value has
8190 already been added. While we are doing this, also note the
8191 location where we must insert the constant if it doesn't already
8193 for (mp = minipool_vector_tail; mp != NULL; mp = mp->prev)
8195 if (GET_CODE (fix->value) == GET_CODE (mp->value)
8196 && fix->mode == mp->mode
8197 && (GET_CODE (fix->value) != CODE_LABEL
8198 || (CODE_LABEL_NUMBER (fix->value)
8199 == CODE_LABEL_NUMBER (mp->value)))
8200 && rtx_equal_p (fix->value, mp->value)
8201 /* Check that there is enough slack to move this entry to the
8202 end of the table (this is conservative). */
8204 > (minipool_barrier->address
8205 + minipool_vector_tail->offset
8206 + minipool_vector_tail->fix_size)))
8209 return move_minipool_fix_backward_ref (mp, min_mp, min_address);
8213 mp->min_address += fix->fix_size;
8216 /* Note the insertion point if necessary. */
8217 if (mp->min_address < min_address)
8219 /* For now, we do not allow the insertion of 8-byte alignment
8220 requiring nodes anywhere but at the start of the pool. */
8221 if (ARM_DOUBLEWORD_ALIGN
8222 && fix->fix_size == 8 && mp->fix_size != 8)
8227 else if (mp->max_address
8228 < minipool_barrier->address + mp->offset + fix->fix_size)
8230 /* Inserting before this entry would push the fix beyond
8231 its maximum address (which can happen if we have
8232 re-located a forwards fix); force the new fix to come
8235 min_address = mp->min_address + fix->fix_size;
8237 /* If we are inserting an 8-bytes aligned quantity and
8238 we have not already found an insertion point, then
8239 make sure that all such 8-byte aligned quantities are
8240 placed at the start of the pool. */
8241 else if (ARM_DOUBLEWORD_ALIGN
8243 && fix->fix_size == 8
8244 && mp->fix_size < 8)
8247 min_address = mp->min_address + fix->fix_size;
8252 /* We need to create a new entry. */
8254 mp->fix_size = fix->fix_size;
8255 mp->mode = fix->mode;
8256 mp->value = fix->value;
8258 mp->max_address = minipool_barrier->address + 65536;
8260 mp->min_address = min_address;
8265 mp->next = minipool_vector_head;
8267 if (mp->next == NULL)
8269 minipool_vector_tail = mp;
8270 minipool_vector_label = gen_label_rtx ();
8273 mp->next->prev = mp;
8275 minipool_vector_head = mp;
8279 mp->next = min_mp->next;
8283 if (mp->next != NULL)
8284 mp->next->prev = mp;
8286 minipool_vector_tail = mp;
8289 /* Save the new entry. */
8297 /* Scan over the following entries and adjust their offsets. */
8298 while (mp->next != NULL)
8300 if (mp->next->min_address < mp->min_address + mp->fix_size)
8301 mp->next->min_address = mp->min_address + mp->fix_size;
8304 mp->next->offset = mp->offset + mp->fix_size;
8306 mp->next->offset = mp->offset;
8315 assign_minipool_offsets (Mfix *barrier)
8317 HOST_WIDE_INT offset = 0;
8320 minipool_barrier = barrier;
8322 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
8324 mp->offset = offset;
8326 if (mp->refcount > 0)
8327 offset += mp->fix_size;
8331 /* Output the literal table */
8333 dump_minipool (rtx scan)
8339 if (ARM_DOUBLEWORD_ALIGN)
8340 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
8341 if (mp->refcount > 0 && mp->fix_size == 8)
8349 ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n",
8350 INSN_UID (scan), (unsigned long) minipool_barrier->address, align64 ? 8 : 4);
8352 scan = emit_label_after (gen_label_rtx (), scan);
8353 scan = emit_insn_after (align64 ? gen_align_8 () : gen_align_4 (), scan);
8354 scan = emit_label_after (minipool_vector_label, scan);
8356 for (mp = minipool_vector_head; mp != NULL; mp = nmp)
8358 if (mp->refcount > 0)
8363 ";; Offset %u, min %ld, max %ld ",
8364 (unsigned) mp->offset, (unsigned long) mp->min_address,
8365 (unsigned long) mp->max_address);
8366 arm_print_value (dump_file, mp->value);
8367 fputc ('\n', dump_file);
8370 switch (mp->fix_size)
8372 #ifdef HAVE_consttable_1
8374 scan = emit_insn_after (gen_consttable_1 (mp->value), scan);
8378 #ifdef HAVE_consttable_2
8380 scan = emit_insn_after (gen_consttable_2 (mp->value), scan);
8384 #ifdef HAVE_consttable_4
8386 scan = emit_insn_after (gen_consttable_4 (mp->value), scan);
8390 #ifdef HAVE_consttable_8
8392 scan = emit_insn_after (gen_consttable_8 (mp->value), scan);
8405 minipool_vector_head = minipool_vector_tail = NULL;
8406 scan = emit_insn_after (gen_consttable_end (), scan);
8407 scan = emit_barrier_after (scan);
8410 /* Return the cost of forcibly inserting a barrier after INSN. */
8412 arm_barrier_cost (rtx insn)
8414 /* Basing the location of the pool on the loop depth is preferable,
8415 but at the moment, the basic block information seems to be
8416 corrupt by this stage of the compilation. */
8418 rtx next = next_nonnote_insn (insn);
8420 if (next != NULL && GET_CODE (next) == CODE_LABEL)
8423 switch (GET_CODE (insn))
8426 /* It will always be better to place the table before the label, rather
8435 return base_cost - 10;
8438 return base_cost + 10;
8442 /* Find the best place in the insn stream in the range
8443 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
8444 Create the barrier by inserting a jump and add a new fix entry for
8447 create_fix_barrier (Mfix *fix, HOST_WIDE_INT max_address)
8449 HOST_WIDE_INT count = 0;
8451 rtx from = fix->insn;
8452 /* The instruction after which we will insert the jump. */
8453 rtx selected = NULL;
8455 /* The address at which the jump instruction will be placed. */
8456 HOST_WIDE_INT selected_address;
8458 HOST_WIDE_INT max_count = max_address - fix->address;
8459 rtx label = gen_label_rtx ();
8461 selected_cost = arm_barrier_cost (from);
8462 selected_address = fix->address;
8464 while (from && count < max_count)
8469 /* This code shouldn't have been called if there was a natural barrier
8471 gcc_assert (GET_CODE (from) != BARRIER);
8473 /* Count the length of this insn. */
8474 count += get_attr_length (from);
8476 /* If there is a jump table, add its length. */
8477 tmp = is_jump_table (from);
8480 count += get_jump_table_size (tmp);
8482 /* Jump tables aren't in a basic block, so base the cost on
8483 the dispatch insn. If we select this location, we will
8484 still put the pool after the table. */
8485 new_cost = arm_barrier_cost (from);
8487 if (count < max_count
8488 && (!selected || new_cost <= selected_cost))
8491 selected_cost = new_cost;
8492 selected_address = fix->address + count;
8495 /* Continue after the dispatch table. */
8496 from = NEXT_INSN (tmp);
8500 new_cost = arm_barrier_cost (from);
8502 if (count < max_count
8503 && (!selected || new_cost <= selected_cost))
8506 selected_cost = new_cost;
8507 selected_address = fix->address + count;
8510 from = NEXT_INSN (from);
8513 /* Make sure that we found a place to insert the jump. */
8514 gcc_assert (selected);
8516 /* Create a new JUMP_INSN that branches around a barrier. */
8517 from = emit_jump_insn_after (gen_jump (label), selected);
8518 JUMP_LABEL (from) = label;
8519 barrier = emit_barrier_after (from);
8520 emit_label_after (label, barrier);
8522 /* Create a minipool barrier entry for the new barrier. */
8523 new_fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* new_fix));
8524 new_fix->insn = barrier;
8525 new_fix->address = selected_address;
8526 new_fix->next = fix->next;
8527 fix->next = new_fix;
8532 /* Record that there is a natural barrier in the insn stream at
8535 push_minipool_barrier (rtx insn, HOST_WIDE_INT address)
8537 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
8540 fix->address = address;
8543 if (minipool_fix_head != NULL)
8544 minipool_fix_tail->next = fix;
8546 minipool_fix_head = fix;
8548 minipool_fix_tail = fix;
8551 /* Record INSN, which will need fixing up to load a value from the
8552 minipool. ADDRESS is the offset of the insn since the start of the
8553 function; LOC is a pointer to the part of the insn which requires
8554 fixing; VALUE is the constant that must be loaded, which is of type
8557 push_minipool_fix (rtx insn, HOST_WIDE_INT address, rtx *loc,
8558 enum machine_mode mode, rtx value)
8560 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
8562 #ifdef AOF_ASSEMBLER
8563 /* PIC symbol references need to be converted into offsets into the
8565 /* XXX This shouldn't be done here. */
8566 if (flag_pic && GET_CODE (value) == SYMBOL_REF)
8567 value = aof_pic_entry (value);
8568 #endif /* AOF_ASSEMBLER */
8571 fix->address = address;
8574 fix->fix_size = MINIPOOL_FIX_SIZE (mode);
8576 fix->forwards = get_attr_pool_range (insn);
8577 fix->backwards = get_attr_neg_pool_range (insn);
8578 fix->minipool = NULL;
8580 /* If an insn doesn't have a range defined for it, then it isn't
8581 expecting to be reworked by this code. Better to stop now than
8582 to generate duff assembly code. */
8583 gcc_assert (fix->forwards || fix->backwards);
8585 /* If an entry requires 8-byte alignment then assume all constant pools
8586 require 4 bytes of padding. Trying to do this later on a per-pool
8587 basis is awkward because existing pool entries have to be modified. */
8588 if (ARM_DOUBLEWORD_ALIGN && fix->fix_size == 8)
8594 ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ",
8595 GET_MODE_NAME (mode),
8596 INSN_UID (insn), (unsigned long) address,
8597 -1 * (long)fix->backwards, (long)fix->forwards);
8598 arm_print_value (dump_file, fix->value);
8599 fprintf (dump_file, "\n");
8602 /* Add it to the chain of fixes. */
8605 if (minipool_fix_head != NULL)
8606 minipool_fix_tail->next = fix;
8608 minipool_fix_head = fix;
8610 minipool_fix_tail = fix;
8613 /* Return the cost of synthesizing a 64-bit constant VAL inline.
8614 Returns the number of insns needed, or 99 if we don't know how to
8617 arm_const_double_inline_cost (rtx val)
8619 rtx lowpart, highpart;
8620 enum machine_mode mode;
8622 mode = GET_MODE (val);
8624 if (mode == VOIDmode)
8627 gcc_assert (GET_MODE_SIZE (mode) == 8);
8629 lowpart = gen_lowpart (SImode, val);
8630 highpart = gen_highpart_mode (SImode, mode, val);
8632 gcc_assert (GET_CODE (lowpart) == CONST_INT);
8633 gcc_assert (GET_CODE (highpart) == CONST_INT);
8635 return (arm_gen_constant (SET, SImode, NULL_RTX, INTVAL (lowpart),
8636 NULL_RTX, NULL_RTX, 0, 0)
8637 + arm_gen_constant (SET, SImode, NULL_RTX, INTVAL (highpart),
8638 NULL_RTX, NULL_RTX, 0, 0));
8641 /* Return true if it is worthwhile to split a 64-bit constant into two
8642 32-bit operations. This is the case if optimizing for size, or
8643 if we have load delay slots, or if one 32-bit part can be done with
8644 a single data operation. */
8646 arm_const_double_by_parts (rtx val)
8648 enum machine_mode mode = GET_MODE (val);
8651 if (optimize_size || arm_ld_sched)
8654 if (mode == VOIDmode)
8657 part = gen_highpart_mode (SImode, mode, val);
8659 gcc_assert (GET_CODE (part) == CONST_INT);
8661 if (const_ok_for_arm (INTVAL (part))
8662 || const_ok_for_arm (~INTVAL (part)))
8665 part = gen_lowpart (SImode, val);
8667 gcc_assert (GET_CODE (part) == CONST_INT);
8669 if (const_ok_for_arm (INTVAL (part))
8670 || const_ok_for_arm (~INTVAL (part)))
8676 /* Scan INSN and note any of its operands that need fixing.
8677 If DO_PUSHES is false we do not actually push any of the fixups
8678 needed. The function returns TRUE if any fixups were needed/pushed.
8679 This is used by arm_memory_load_p() which needs to know about loads
8680 of constants that will be converted into minipool loads. */
8682 note_invalid_constants (rtx insn, HOST_WIDE_INT address, int do_pushes)
8684 bool result = false;
8687 extract_insn (insn);
8689 if (!constrain_operands (1))
8690 fatal_insn_not_found (insn);
8692 if (recog_data.n_alternatives == 0)
8695 /* Fill in recog_op_alt with information about the constraints of
8697 preprocess_constraints ();
8699 for (opno = 0; opno < recog_data.n_operands; opno++)
8701 /* Things we need to fix can only occur in inputs. */
8702 if (recog_data.operand_type[opno] != OP_IN)
8705 /* If this alternative is a memory reference, then any mention
8706 of constants in this alternative is really to fool reload
8707 into allowing us to accept one there. We need to fix them up
8708 now so that we output the right code. */
8709 if (recog_op_alt[opno][which_alternative].memory_ok)
8711 rtx op = recog_data.operand[opno];
8713 if (CONSTANT_P (op))
8716 push_minipool_fix (insn, address, recog_data.operand_loc[opno],
8717 recog_data.operand_mode[opno], op);
8720 else if (GET_CODE (op) == MEM
8721 && GET_CODE (XEXP (op, 0)) == SYMBOL_REF
8722 && CONSTANT_POOL_ADDRESS_P (XEXP (op, 0)))
8726 rtx cop = avoid_constant_pool_reference (op);
8728 /* Casting the address of something to a mode narrower
8729 than a word can cause avoid_constant_pool_reference()
8730 to return the pool reference itself. That's no good to
8731 us here. Lets just hope that we can use the
8732 constant pool value directly. */
8734 cop = get_pool_constant (XEXP (op, 0));
8736 push_minipool_fix (insn, address,
8737 recog_data.operand_loc[opno],
8738 recog_data.operand_mode[opno], cop);
8749 /* Gcc puts the pool in the wrong place for ARM, since we can only
8750 load addresses a limited distance around the pc. We do some
8751 special munging to move the constant pool values to the correct
8752 point in the code. */
8757 HOST_WIDE_INT address = 0;
8760 minipool_fix_head = minipool_fix_tail = NULL;
8762 /* The first insn must always be a note, or the code below won't
8763 scan it properly. */
8764 insn = get_insns ();
8765 gcc_assert (GET_CODE (insn) == NOTE);
8768 /* Scan all the insns and record the operands that will need fixing. */
8769 for (insn = next_nonnote_insn (insn); insn; insn = next_nonnote_insn (insn))
8771 if (TARGET_CIRRUS_FIX_INVALID_INSNS
8772 && (arm_cirrus_insn_p (insn)
8773 || GET_CODE (insn) == JUMP_INSN
8774 || arm_memory_load_p (insn)))
8775 cirrus_reorg (insn);
8777 if (GET_CODE (insn) == BARRIER)
8778 push_minipool_barrier (insn, address);
8779 else if (INSN_P (insn))
8783 note_invalid_constants (insn, address, true);
8784 address += get_attr_length (insn);
8786 /* If the insn is a vector jump, add the size of the table
8787 and skip the table. */
8788 if ((table = is_jump_table (insn)) != NULL)
8790 address += get_jump_table_size (table);
8796 fix = minipool_fix_head;
8798 /* Now scan the fixups and perform the required changes. */
8803 Mfix * last_added_fix;
8804 Mfix * last_barrier = NULL;
8807 /* Skip any further barriers before the next fix. */
8808 while (fix && GET_CODE (fix->insn) == BARRIER)
8811 /* No more fixes. */
8815 last_added_fix = NULL;
8817 for (ftmp = fix; ftmp; ftmp = ftmp->next)
8819 if (GET_CODE (ftmp->insn) == BARRIER)
8821 if (ftmp->address >= minipool_vector_head->max_address)
8824 last_barrier = ftmp;
8826 else if ((ftmp->minipool = add_minipool_forward_ref (ftmp)) == NULL)
8829 last_added_fix = ftmp; /* Keep track of the last fix added. */
8832 /* If we found a barrier, drop back to that; any fixes that we
8833 could have reached but come after the barrier will now go in
8834 the next mini-pool. */
8835 if (last_barrier != NULL)
8837 /* Reduce the refcount for those fixes that won't go into this
8839 for (fdel = last_barrier->next;
8840 fdel && fdel != ftmp;
8843 fdel->minipool->refcount--;
8844 fdel->minipool = NULL;
8847 ftmp = last_barrier;
8851 /* ftmp is first fix that we can't fit into this pool and
8852 there no natural barriers that we could use. Insert a
8853 new barrier in the code somewhere between the previous
8854 fix and this one, and arrange to jump around it. */
8855 HOST_WIDE_INT max_address;
8857 /* The last item on the list of fixes must be a barrier, so
8858 we can never run off the end of the list of fixes without
8859 last_barrier being set. */
8862 max_address = minipool_vector_head->max_address;
8863 /* Check that there isn't another fix that is in range that
8864 we couldn't fit into this pool because the pool was
8865 already too large: we need to put the pool before such an
8866 instruction. The pool itself may come just after the
8867 fix because create_fix_barrier also allows space for a
8868 jump instruction. */
8869 if (ftmp->address < max_address)
8870 max_address = ftmp->address + 1;
8872 last_barrier = create_fix_barrier (last_added_fix, max_address);
8875 assign_minipool_offsets (last_barrier);
8879 if (GET_CODE (ftmp->insn) != BARRIER
8880 && ((ftmp->minipool = add_minipool_backward_ref (ftmp))
8887 /* Scan over the fixes we have identified for this pool, fixing them
8888 up and adding the constants to the pool itself. */
8889 for (this_fix = fix; this_fix && ftmp != this_fix;
8890 this_fix = this_fix->next)
8891 if (GET_CODE (this_fix->insn) != BARRIER)
8894 = plus_constant (gen_rtx_LABEL_REF (VOIDmode,
8895 minipool_vector_label),
8896 this_fix->minipool->offset);
8897 *this_fix->loc = gen_rtx_MEM (this_fix->mode, addr);
8900 dump_minipool (last_barrier->insn);
8904 /* From now on we must synthesize any constants that we can't handle
8905 directly. This can happen if the RTL gets split during final
8906 instruction generation. */
8907 after_arm_reorg = 1;
8909 /* Free the minipool memory. */
8910 obstack_free (&minipool_obstack, minipool_startobj);
8913 /* Routines to output assembly language. */
8915 /* If the rtx is the correct value then return the string of the number.
8916 In this way we can ensure that valid double constants are generated even
8917 when cross compiling. */
8919 fp_immediate_constant (rtx x)
8924 if (!fp_consts_inited)
8927 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
8928 for (i = 0; i < 8; i++)
8929 if (REAL_VALUES_EQUAL (r, values_fp[i]))
8930 return strings_fp[i];
8935 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
8937 fp_const_from_val (REAL_VALUE_TYPE *r)
8941 if (!fp_consts_inited)
8944 for (i = 0; i < 8; i++)
8945 if (REAL_VALUES_EQUAL (*r, values_fp[i]))
8946 return strings_fp[i];
8951 /* Output the operands of a LDM/STM instruction to STREAM.
8952 MASK is the ARM register set mask of which only bits 0-15 are important.
8953 REG is the base register, either the frame pointer or the stack pointer,
8954 INSTR is the possibly suffixed load or store instruction.
8955 RFE is nonzero if the instruction should also copy spsr to cpsr. */
8958 print_multi_reg (FILE *stream, const char *instr, unsigned reg,
8959 unsigned long mask, int rfe)
8962 bool not_first = FALSE;
8964 gcc_assert (!rfe || (mask & (1 << PC_REGNUM)));
8965 fputc ('\t', stream);
8966 asm_fprintf (stream, instr, reg);
8967 fputc ('{', stream);
8969 for (i = 0; i <= LAST_ARM_REGNUM; i++)
8970 if (mask & (1 << i))
8973 fprintf (stream, ", ");
8975 asm_fprintf (stream, "%r", i);
8980 fprintf (stream, "}^\n");
8982 fprintf (stream, "}\n");
8986 /* Output a FLDMD instruction to STREAM.
8987 BASE if the register containing the address.
8988 REG and COUNT specify the register range.
8989 Extra registers may be added to avoid hardware bugs.
8991 We output FLDMD even for ARMv5 VFP implementations. Although
8992 FLDMD is technically not supported until ARMv6, it is believed
8993 that all VFP implementations support its use in this context. */
8996 vfp_output_fldmd (FILE * stream, unsigned int base, int reg, int count)
9000 /* Workaround ARM10 VFPr1 bug. */
9001 if (count == 2 && !arm_arch6)
9008 /* FLDMD may not load more than 16 doubleword registers at a time. Split the
9009 load into multiple parts if we have to handle more than 16 registers. */
9012 vfp_output_fldmd (stream, base, reg, 16);
9013 vfp_output_fldmd (stream, base, reg + 16, count - 16);
9017 fputc ('\t', stream);
9018 asm_fprintf (stream, "fldmfdd\t%r!, {", base);
9020 for (i = reg; i < reg + count; i++)
9023 fputs (", ", stream);
9024 asm_fprintf (stream, "d%d", i);
9026 fputs ("}\n", stream);
9031 /* Output the assembly for a store multiple. */
9034 vfp_output_fstmd (rtx * operands)
9041 strcpy (pattern, "fstmfdd\t%m0!, {%P1");
9042 p = strlen (pattern);
9044 gcc_assert (GET_CODE (operands[1]) == REG);
9046 base = (REGNO (operands[1]) - FIRST_VFP_REGNUM) / 2;
9047 for (i = 1; i < XVECLEN (operands[2], 0); i++)
9049 p += sprintf (&pattern[p], ", d%d", base + i);
9051 strcpy (&pattern[p], "}");
9053 output_asm_insn (pattern, operands);
9058 /* Emit RTL to save block of VFP register pairs to the stack. Returns the
9059 number of bytes pushed. */
9062 vfp_emit_fstmd (int base_reg, int count)
9069 /* Workaround ARM10 VFPr1 bug. Data corruption can occur when exactly two
9070 register pairs are stored by a store multiple insn. We avoid this
9071 by pushing an extra pair. */
9072 if (count == 2 && !arm_arch6)
9074 if (base_reg == LAST_VFP_REGNUM - 3)
9079 /* FSTMD may not store more than 16 doubleword registers at once. Split
9080 larger stores into multiple parts (up to a maximum of two, in
9085 /* NOTE: base_reg is an internal register number, so each D register
9087 saved = vfp_emit_fstmd (base_reg + 32, count - 16);
9088 saved += vfp_emit_fstmd (base_reg, 16);
9092 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
9093 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (count + 1));
9095 reg = gen_rtx_REG (DFmode, base_reg);
9099 = gen_rtx_SET (VOIDmode,
9100 gen_frame_mem (BLKmode,
9101 gen_rtx_PRE_DEC (BLKmode,
9102 stack_pointer_rtx)),
9103 gen_rtx_UNSPEC (BLKmode,
9107 tmp = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
9108 plus_constant (stack_pointer_rtx, -(count * 8)));
9109 RTX_FRAME_RELATED_P (tmp) = 1;
9110 XVECEXP (dwarf, 0, 0) = tmp;
9112 tmp = gen_rtx_SET (VOIDmode,
9113 gen_frame_mem (DFmode, stack_pointer_rtx),
9115 RTX_FRAME_RELATED_P (tmp) = 1;
9116 XVECEXP (dwarf, 0, 1) = tmp;
9118 for (i = 1; i < count; i++)
9120 reg = gen_rtx_REG (DFmode, base_reg);
9122 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
9124 tmp = gen_rtx_SET (VOIDmode,
9125 gen_frame_mem (DFmode,
9126 plus_constant (stack_pointer_rtx,
9129 RTX_FRAME_RELATED_P (tmp) = 1;
9130 XVECEXP (dwarf, 0, i + 1) = tmp;
9133 par = emit_insn (par);
9134 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
9136 RTX_FRAME_RELATED_P (par) = 1;
9141 /* Emit a call instruction with pattern PAT. ADDR is the address of
9145 arm_emit_call_insn (rtx pat, rtx addr)
9149 insn = emit_call_insn (pat);
9151 /* The PIC register is live on entry to VxWorks PIC PLT entries.
9152 If the call might use such an entry, add a use of the PIC register
9153 to the instruction's CALL_INSN_FUNCTION_USAGE. */
9154 if (TARGET_VXWORKS_RTP
9156 && GET_CODE (addr) == SYMBOL_REF
9157 && (SYMBOL_REF_DECL (addr)
9158 ? !targetm.binds_local_p (SYMBOL_REF_DECL (addr))
9159 : !SYMBOL_REF_LOCAL_P (addr)))
9161 require_pic_register ();
9162 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), cfun->machine->pic_reg);
9166 /* Output a 'call' insn. */
9168 output_call (rtx *operands)
9170 gcc_assert (!arm_arch5); /* Patterns should call blx <reg> directly. */
9172 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
9173 if (REGNO (operands[0]) == LR_REGNUM)
9175 operands[0] = gen_rtx_REG (SImode, IP_REGNUM);
9176 output_asm_insn ("mov%?\t%0, %|lr", operands);
9179 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
9181 if (TARGET_INTERWORK || arm_arch4t)
9182 output_asm_insn ("bx%?\t%0", operands);
9184 output_asm_insn ("mov%?\t%|pc, %0", operands);
9189 /* Output a 'call' insn that is a reference in memory. */
9191 output_call_mem (rtx *operands)
9193 if (TARGET_INTERWORK && !arm_arch5)
9195 output_asm_insn ("ldr%?\t%|ip, %0", operands);
9196 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
9197 output_asm_insn ("bx%?\t%|ip", operands);
9199 else if (regno_use_in (LR_REGNUM, operands[0]))
9201 /* LR is used in the memory address. We load the address in the
9202 first instruction. It's safe to use IP as the target of the
9203 load since the call will kill it anyway. */
9204 output_asm_insn ("ldr%?\t%|ip, %0", operands);
9206 output_asm_insn ("blx%?\t%|ip", operands);
9209 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
9211 output_asm_insn ("bx%?\t%|ip", operands);
9213 output_asm_insn ("mov%?\t%|pc, %|ip", operands);
9218 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
9219 output_asm_insn ("ldr%?\t%|pc, %0", operands);
9226 /* Output a move from arm registers to an fpa registers.
9227 OPERANDS[0] is an fpa register.
9228 OPERANDS[1] is the first registers of an arm register pair. */
9230 output_mov_long_double_fpa_from_arm (rtx *operands)
9232 int arm_reg0 = REGNO (operands[1]);
9235 gcc_assert (arm_reg0 != IP_REGNUM);
9237 ops[0] = gen_rtx_REG (SImode, arm_reg0);
9238 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
9239 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
9241 output_asm_insn ("stm%(fd%)\t%|sp!, {%0, %1, %2}", ops);
9242 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands);
9247 /* Output a move from an fpa register to arm registers.
9248 OPERANDS[0] is the first registers of an arm register pair.
9249 OPERANDS[1] is an fpa register. */
9251 output_mov_long_double_arm_from_fpa (rtx *operands)
9253 int arm_reg0 = REGNO (operands[0]);
9256 gcc_assert (arm_reg0 != IP_REGNUM);
9258 ops[0] = gen_rtx_REG (SImode, arm_reg0);
9259 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
9260 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
9262 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands);
9263 output_asm_insn ("ldm%(fd%)\t%|sp!, {%0, %1, %2}", ops);
9267 /* Output a move from arm registers to arm registers of a long double
9268 OPERANDS[0] is the destination.
9269 OPERANDS[1] is the source. */
9271 output_mov_long_double_arm_from_arm (rtx *operands)
9273 /* We have to be careful here because the two might overlap. */
9274 int dest_start = REGNO (operands[0]);
9275 int src_start = REGNO (operands[1]);
9279 if (dest_start < src_start)
9281 for (i = 0; i < 3; i++)
9283 ops[0] = gen_rtx_REG (SImode, dest_start + i);
9284 ops[1] = gen_rtx_REG (SImode, src_start + i);
9285 output_asm_insn ("mov%?\t%0, %1", ops);
9290 for (i = 2; i >= 0; i--)
9292 ops[0] = gen_rtx_REG (SImode, dest_start + i);
9293 ops[1] = gen_rtx_REG (SImode, src_start + i);
9294 output_asm_insn ("mov%?\t%0, %1", ops);
9302 /* Output a move from arm registers to an fpa registers.
9303 OPERANDS[0] is an fpa register.
9304 OPERANDS[1] is the first registers of an arm register pair. */
9306 output_mov_double_fpa_from_arm (rtx *operands)
9308 int arm_reg0 = REGNO (operands[1]);
9311 gcc_assert (arm_reg0 != IP_REGNUM);
9313 ops[0] = gen_rtx_REG (SImode, arm_reg0);
9314 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
9315 output_asm_insn ("stm%(fd%)\t%|sp!, {%0, %1}", ops);
9316 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands);
9320 /* Output a move from an fpa register to arm registers.
9321 OPERANDS[0] is the first registers of an arm register pair.
9322 OPERANDS[1] is an fpa register. */
9324 output_mov_double_arm_from_fpa (rtx *operands)
9326 int arm_reg0 = REGNO (operands[0]);
9329 gcc_assert (arm_reg0 != IP_REGNUM);
9331 ops[0] = gen_rtx_REG (SImode, arm_reg0);
9332 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
9333 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands);
9334 output_asm_insn ("ldm%(fd%)\t%|sp!, {%0, %1}", ops);
9338 /* Output a move between double words.
9339 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
9340 or MEM<-REG and all MEMs must be offsettable addresses. */
9342 output_move_double (rtx *operands)
9344 enum rtx_code code0 = GET_CODE (operands[0]);
9345 enum rtx_code code1 = GET_CODE (operands[1]);
9350 int reg0 = REGNO (operands[0]);
9352 otherops[0] = gen_rtx_REG (SImode, 1 + reg0);
9354 gcc_assert (code1 == MEM); /* Constraints should ensure this. */
9356 switch (GET_CODE (XEXP (operands[1], 0)))
9359 output_asm_insn ("ldm%(ia%)\t%m1, %M0", operands);
9363 gcc_assert (TARGET_LDRD);
9364 output_asm_insn ("ldr%(d%)\t%0, [%m1, #8]!", operands);
9369 output_asm_insn ("ldr%(d%)\t%0, [%m1, #-8]!", operands);
9371 output_asm_insn ("ldm%(db%)\t%m1!, %M0", operands);
9375 output_asm_insn ("ldm%(ia%)\t%m1!, %M0", operands);
9379 gcc_assert (TARGET_LDRD);
9380 output_asm_insn ("ldr%(d%)\t%0, [%m1], #-8", operands);
9385 otherops[0] = operands[0];
9386 otherops[1] = XEXP (XEXP (XEXP (operands[1], 0), 1), 0);
9387 otherops[2] = XEXP (XEXP (XEXP (operands[1], 0), 1), 1);
9389 if (GET_CODE (XEXP (operands[1], 0)) == PRE_MODIFY)
9391 if (reg_overlap_mentioned_p (otherops[0], otherops[2]))
9393 /* Registers overlap so split out the increment. */
9394 output_asm_insn ("add%?\t%1, %1, %2", otherops);
9395 output_asm_insn ("ldr%(d%)\t%0, [%1] @split", otherops);
9399 /* IWMMXT allows offsets larger than ldrd can handle,
9400 fix these up with a pair of ldr. */
9401 if (GET_CODE (otherops[2]) == CONST_INT
9402 && (INTVAL(otherops[2]) <= -256
9403 || INTVAL(otherops[2]) >= 256))
9405 output_asm_insn ("ldr%?\t%0, [%1, %2]!", otherops);
9406 otherops[0] = gen_rtx_REG (SImode, 1 + reg0);
9407 output_asm_insn ("ldr%?\t%0, [%1, #4]", otherops);
9410 output_asm_insn ("ldr%(d%)\t%0, [%1, %2]!", otherops);
9415 /* IWMMXT allows offsets larger than ldrd can handle,
9416 fix these up with a pair of ldr. */
9417 if (GET_CODE (otherops[2]) == CONST_INT
9418 && (INTVAL(otherops[2]) <= -256
9419 || INTVAL(otherops[2]) >= 256))
9421 otherops[0] = gen_rtx_REG (SImode, 1 + reg0);
9422 output_asm_insn ("ldr%?\t%0, [%1, #4]", otherops);
9423 otherops[0] = operands[0];
9424 output_asm_insn ("ldr%?\t%0, [%1], %2", otherops);
9427 /* We only allow constant increments, so this is safe. */
9428 output_asm_insn ("ldr%(d%)\t%0, [%1], %2", otherops);
9434 output_asm_insn ("adr%?\t%0, %1", operands);
9435 output_asm_insn ("ldm%(ia%)\t%0, %M0", operands);
9438 /* ??? This needs checking for thumb2. */
9440 if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1),
9441 GET_MODE (XEXP (XEXP (operands[1], 0), 1))))
9443 otherops[0] = operands[0];
9444 otherops[1] = XEXP (XEXP (operands[1], 0), 0);
9445 otherops[2] = XEXP (XEXP (operands[1], 0), 1);
9447 if (GET_CODE (XEXP (operands[1], 0)) == PLUS)
9449 if (GET_CODE (otherops[2]) == CONST_INT)
9451 switch ((int) INTVAL (otherops[2]))
9454 output_asm_insn ("ldm%(db%)\t%1, %M0", otherops);
9459 output_asm_insn ("ldm%(da%)\t%1, %M0", otherops);
9464 output_asm_insn ("ldm%(ib%)\t%1, %M0", otherops);
9469 && (GET_CODE (otherops[2]) == REG
9470 || (GET_CODE (otherops[2]) == CONST_INT
9471 && INTVAL (otherops[2]) > -256
9472 && INTVAL (otherops[2]) < 256)))
9474 if (reg_overlap_mentioned_p (otherops[0],
9477 /* Swap base and index registers over to
9478 avoid a conflict. */
9479 otherops[1] = XEXP (XEXP (operands[1], 0), 1);
9480 otherops[2] = XEXP (XEXP (operands[1], 0), 0);
9482 /* If both registers conflict, it will usually
9483 have been fixed by a splitter. */
9484 if (reg_overlap_mentioned_p (otherops[0], otherops[2]))
9486 output_asm_insn ("add%?\t%1, %1, %2", otherops);
9487 output_asm_insn ("ldr%(d%)\t%0, [%1]",
9491 output_asm_insn ("ldr%(d%)\t%0, [%1, %2]", otherops);
9495 if (GET_CODE (otherops[2]) == CONST_INT)
9497 if (!(const_ok_for_arm (INTVAL (otherops[2]))))
9498 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops);
9500 output_asm_insn ("add%?\t%0, %1, %2", otherops);
9503 output_asm_insn ("add%?\t%0, %1, %2", otherops);
9506 output_asm_insn ("sub%?\t%0, %1, %2", otherops);
9508 return "ldm%(ia%)\t%0, %M0";
9512 otherops[1] = adjust_address (operands[1], SImode, 4);
9513 /* Take care of overlapping base/data reg. */
9514 if (reg_mentioned_p (operands[0], operands[1]))
9516 output_asm_insn ("ldr%?\t%0, %1", otherops);
9517 output_asm_insn ("ldr%?\t%0, %1", operands);
9521 output_asm_insn ("ldr%?\t%0, %1", operands);
9522 output_asm_insn ("ldr%?\t%0, %1", otherops);
9529 /* Constraints should ensure this. */
9530 gcc_assert (code0 == MEM && code1 == REG);
9531 gcc_assert (REGNO (operands[1]) != IP_REGNUM);
9533 switch (GET_CODE (XEXP (operands[0], 0)))
9536 output_asm_insn ("stm%(ia%)\t%m0, %M1", operands);
9540 gcc_assert (TARGET_LDRD);
9541 output_asm_insn ("str%(d%)\t%1, [%m0, #8]!", operands);
9546 output_asm_insn ("str%(d%)\t%1, [%m0, #-8]!", operands);
9548 output_asm_insn ("stm%(db%)\t%m0!, %M1", operands);
9552 output_asm_insn ("stm%(ia%)\t%m0!, %M1", operands);
9556 gcc_assert (TARGET_LDRD);
9557 output_asm_insn ("str%(d%)\t%1, [%m0], #-8", operands);
9562 otherops[0] = operands[1];
9563 otherops[1] = XEXP (XEXP (XEXP (operands[0], 0), 1), 0);
9564 otherops[2] = XEXP (XEXP (XEXP (operands[0], 0), 1), 1);
9566 /* IWMMXT allows offsets larger than ldrd can handle,
9567 fix these up with a pair of ldr. */
9568 if (GET_CODE (otherops[2]) == CONST_INT
9569 && (INTVAL(otherops[2]) <= -256
9570 || INTVAL(otherops[2]) >= 256))
9573 reg1 = gen_rtx_REG (SImode, 1 + REGNO (operands[1]));
9574 if (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY)
9576 output_asm_insn ("ldr%?\t%0, [%1, %2]!", otherops);
9578 output_asm_insn ("ldr%?\t%0, [%1, #4]", otherops);
9583 output_asm_insn ("ldr%?\t%0, [%1, #4]", otherops);
9584 otherops[0] = operands[1];
9585 output_asm_insn ("ldr%?\t%0, [%1], %2", otherops);
9588 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY)
9589 output_asm_insn ("str%(d%)\t%0, [%1, %2]!", otherops);
9591 output_asm_insn ("str%(d%)\t%0, [%1], %2", otherops);
9595 otherops[2] = XEXP (XEXP (operands[0], 0), 1);
9596 if (GET_CODE (otherops[2]) == CONST_INT)
9598 switch ((int) INTVAL (XEXP (XEXP (operands[0], 0), 1)))
9601 output_asm_insn ("stm%(db%)\t%m0, %M1", operands);
9607 output_asm_insn ("stm%(da%)\t%m0, %M1", operands);
9613 output_asm_insn ("stm%(ib%)\t%m0, %M1", operands);
9618 && (GET_CODE (otherops[2]) == REG
9619 || (GET_CODE (otherops[2]) == CONST_INT
9620 && INTVAL (otherops[2]) > -256
9621 && INTVAL (otherops[2]) < 256)))
9623 otherops[0] = operands[1];
9624 otherops[1] = XEXP (XEXP (operands[0], 0), 0);
9625 output_asm_insn ("str%(d%)\t%0, [%1, %2]", otherops);
9631 otherops[0] = adjust_address (operands[0], SImode, 4);
9632 otherops[1] = gen_rtx_REG (SImode, 1 + REGNO (operands[1]));
9633 output_asm_insn ("str%?\t%1, %0", operands);
9634 output_asm_insn ("str%?\t%1, %0", otherops);
9641 /* Output a VFP load or store instruction. */
9644 output_move_vfp (rtx *operands)
9646 rtx reg, mem, addr, ops[2];
9647 int load = REG_P (operands[0]);
9648 int dp = GET_MODE_SIZE (GET_MODE (operands[0])) == 8;
9649 int integer_p = GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT;
9650 const char *template;
9653 reg = operands[!load];
9654 mem = operands[load];
9656 gcc_assert (REG_P (reg));
9657 gcc_assert (IS_VFP_REGNUM (REGNO (reg)));
9658 gcc_assert (GET_MODE (reg) == SFmode
9659 || GET_MODE (reg) == DFmode
9660 || GET_MODE (reg) == SImode
9661 || GET_MODE (reg) == DImode);
9662 gcc_assert (MEM_P (mem));
9664 addr = XEXP (mem, 0);
9666 switch (GET_CODE (addr))
9669 template = "f%smdb%c%%?\t%%0!, {%%%s1}%s";
9670 ops[0] = XEXP (addr, 0);
9675 template = "f%smia%c%%?\t%%0!, {%%%s1}%s";
9676 ops[0] = XEXP (addr, 0);
9681 template = "f%s%c%%?\t%%%s0, %%1%s";
9687 sprintf (buff, template,
9691 integer_p ? "\t%@ int" : "");
9692 output_asm_insn (buff, ops);
9697 /* Output an ADD r, s, #n where n may be too big for one instruction.
9698 If adding zero to one register, output nothing. */
9700 output_add_immediate (rtx *operands)
9702 HOST_WIDE_INT n = INTVAL (operands[2]);
9704 if (n != 0 || REGNO (operands[0]) != REGNO (operands[1]))
9707 output_multi_immediate (operands,
9708 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
9711 output_multi_immediate (operands,
9712 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
9719 /* Output a multiple immediate operation.
9720 OPERANDS is the vector of operands referred to in the output patterns.
9721 INSTR1 is the output pattern to use for the first constant.
9722 INSTR2 is the output pattern to use for subsequent constants.
9723 IMMED_OP is the index of the constant slot in OPERANDS.
9724 N is the constant value. */
9726 output_multi_immediate (rtx *operands, const char *instr1, const char *instr2,
9727 int immed_op, HOST_WIDE_INT n)
9729 #if HOST_BITS_PER_WIDE_INT > 32
9735 /* Quick and easy output. */
9736 operands[immed_op] = const0_rtx;
9737 output_asm_insn (instr1, operands);
9742 const char * instr = instr1;
9744 /* Note that n is never zero here (which would give no output). */
9745 for (i = 0; i < 32; i += 2)
9749 operands[immed_op] = GEN_INT (n & (255 << i));
9750 output_asm_insn (instr, operands);
9760 /* Return the name of a shifter operation. */
9762 arm_shift_nmem(enum rtx_code code)
9767 return ARM_LSL_NAME;
9783 /* Return the appropriate ARM instruction for the operation code.
9784 The returned result should not be overwritten. OP is the rtx of the
9785 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
9788 arithmetic_instr (rtx op, int shift_first_arg)
9790 switch (GET_CODE (op))
9796 return shift_first_arg ? "rsb" : "sub";
9811 return arm_shift_nmem(GET_CODE(op));
9818 /* Ensure valid constant shifts and return the appropriate shift mnemonic
9819 for the operation code. The returned result should not be overwritten.
9820 OP is the rtx code of the shift.
9821 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
9824 shift_op (rtx op, HOST_WIDE_INT *amountp)
9827 enum rtx_code code = GET_CODE (op);
9829 switch (GET_CODE (XEXP (op, 1)))
9837 *amountp = INTVAL (XEXP (op, 1));
9847 gcc_assert (*amountp != -1);
9848 *amountp = 32 - *amountp;
9857 mnem = arm_shift_nmem(code);
9861 /* We never have to worry about the amount being other than a
9862 power of 2, since this case can never be reloaded from a reg. */
9863 gcc_assert (*amountp != -1);
9864 *amountp = int_log2 (*amountp);
9865 return ARM_LSL_NAME;
9873 /* This is not 100% correct, but follows from the desire to merge
9874 multiplication by a power of 2 with the recognizer for a
9875 shift. >=32 is not a valid shift for "lsl", so we must try and
9876 output a shift that produces the correct arithmetical result.
9877 Using lsr #32 is identical except for the fact that the carry bit
9878 is not set correctly if we set the flags; but we never use the
9879 carry bit from such an operation, so we can ignore that. */
9880 if (code == ROTATERT)
9881 /* Rotate is just modulo 32. */
9883 else if (*amountp != (*amountp & 31))
9890 /* Shifts of 0 are no-ops. */
9898 /* Obtain the shift from the POWER of two. */
9900 static HOST_WIDE_INT
9901 int_log2 (HOST_WIDE_INT power)
9903 HOST_WIDE_INT shift = 0;
9905 while ((((HOST_WIDE_INT) 1 << shift) & power) == 0)
9907 gcc_assert (shift <= 31);
9914 /* Output a .ascii pseudo-op, keeping track of lengths. This is
9915 because /bin/as is horribly restrictive. The judgement about
9916 whether or not each character is 'printable' (and can be output as
9917 is) or not (and must be printed with an octal escape) must be made
9918 with reference to the *host* character set -- the situation is
9919 similar to that discussed in the comments above pp_c_char in
9920 c-pretty-print.c. */
9922 #define MAX_ASCII_LEN 51
9925 output_ascii_pseudo_op (FILE *stream, const unsigned char *p, int len)
9930 fputs ("\t.ascii\t\"", stream);
9932 for (i = 0; i < len; i++)
9936 if (len_so_far >= MAX_ASCII_LEN)
9938 fputs ("\"\n\t.ascii\t\"", stream);
9944 if (c == '\\' || c == '\"')
9946 putc ('\\', stream);
9954 fprintf (stream, "\\%03o", c);
9959 fputs ("\"\n", stream);
9962 /* Compute the register save mask for registers 0 through 12
9963 inclusive. This code is used by arm_compute_save_reg_mask. */
9965 static unsigned long
9966 arm_compute_save_reg0_reg12_mask (void)
9968 unsigned long func_type = arm_current_func_type ();
9969 unsigned long save_reg_mask = 0;
9972 if (IS_INTERRUPT (func_type))
9974 unsigned int max_reg;
9975 /* Interrupt functions must not corrupt any registers,
9976 even call clobbered ones. If this is a leaf function
9977 we can just examine the registers used by the RTL, but
9978 otherwise we have to assume that whatever function is
9979 called might clobber anything, and so we have to save
9980 all the call-clobbered registers as well. */
9981 if (ARM_FUNC_TYPE (func_type) == ARM_FT_FIQ)
9982 /* FIQ handlers have registers r8 - r12 banked, so
9983 we only need to check r0 - r7, Normal ISRs only
9984 bank r14 and r15, so we must check up to r12.
9985 r13 is the stack pointer which is always preserved,
9986 so we do not need to consider it here. */
9991 for (reg = 0; reg <= max_reg; reg++)
9992 if (df_regs_ever_live_p (reg)
9993 || (! current_function_is_leaf && call_used_regs[reg]))
9994 save_reg_mask |= (1 << reg);
9996 /* Also save the pic base register if necessary. */
9998 && !TARGET_SINGLE_PIC_BASE
9999 && arm_pic_register != INVALID_REGNUM
10000 && current_function_uses_pic_offset_table)
10001 save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
10005 /* In arm mode we handle r11 (FP) as a special case. */
10006 unsigned last_reg = TARGET_ARM ? 10 : 11;
10008 /* In the normal case we only need to save those registers
10009 which are call saved and which are used by this function. */
10010 for (reg = 0; reg <= last_reg; reg++)
10011 if (df_regs_ever_live_p (reg) && ! call_used_regs[reg])
10012 save_reg_mask |= (1 << reg);
10014 /* Handle the frame pointer as a special case. */
10015 if (! TARGET_APCS_FRAME
10016 && ! frame_pointer_needed
10017 && df_regs_ever_live_p (HARD_FRAME_POINTER_REGNUM)
10018 && ! call_used_regs[HARD_FRAME_POINTER_REGNUM])
10019 save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM;
10020 else if (! TARGET_APCS_FRAME
10021 && ! frame_pointer_needed
10022 && df_regs_ever_live_p (HARD_FRAME_POINTER_REGNUM)
10023 && ! call_used_regs[HARD_FRAME_POINTER_REGNUM])
10024 save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM;
10026 /* If we aren't loading the PIC register,
10027 don't stack it even though it may be live. */
10029 && !TARGET_SINGLE_PIC_BASE
10030 && arm_pic_register != INVALID_REGNUM
10031 && (df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM)
10032 || current_function_uses_pic_offset_table))
10033 save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
10035 /* The prologue will copy SP into R0, so save it. */
10036 if (IS_STACKALIGN (func_type))
10037 save_reg_mask |= 1;
10040 /* Save registers so the exception handler can modify them. */
10041 if (current_function_calls_eh_return)
10047 reg = EH_RETURN_DATA_REGNO (i);
10048 if (reg == INVALID_REGNUM)
10050 save_reg_mask |= 1 << reg;
10054 return save_reg_mask;
10058 /* Compute a bit mask of which registers need to be
10059 saved on the stack for the current function. */
10061 static unsigned long
10062 arm_compute_save_reg_mask (void)
10064 unsigned int save_reg_mask = 0;
10065 unsigned long func_type = arm_current_func_type ();
10068 if (IS_NAKED (func_type))
10069 /* This should never really happen. */
10072 /* If we are creating a stack frame, then we must save the frame pointer,
10073 IP (which will hold the old stack pointer), LR and the PC. */
10074 if (frame_pointer_needed && TARGET_ARM)
10076 (1 << ARM_HARD_FRAME_POINTER_REGNUM)
10079 | (1 << PC_REGNUM);
10081 /* Volatile functions do not return, so there
10082 is no need to save any other registers. */
10083 if (IS_VOLATILE (func_type))
10084 return save_reg_mask;
10086 save_reg_mask |= arm_compute_save_reg0_reg12_mask ();
10088 /* Decide if we need to save the link register.
10089 Interrupt routines have their own banked link register,
10090 so they never need to save it.
10091 Otherwise if we do not use the link register we do not need to save
10092 it. If we are pushing other registers onto the stack however, we
10093 can save an instruction in the epilogue by pushing the link register
10094 now and then popping it back into the PC. This incurs extra memory
10095 accesses though, so we only do it when optimizing for size, and only
10096 if we know that we will not need a fancy return sequence. */
10097 if (df_regs_ever_live_p (LR_REGNUM)
10100 && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
10101 && !current_function_calls_eh_return))
10102 save_reg_mask |= 1 << LR_REGNUM;
10104 if (cfun->machine->lr_save_eliminated)
10105 save_reg_mask &= ~ (1 << LR_REGNUM);
10107 if (TARGET_REALLY_IWMMXT
10108 && ((bit_count (save_reg_mask)
10109 + ARM_NUM_INTS (current_function_pretend_args_size)) % 2) != 0)
10111 /* The total number of registers that are going to be pushed
10112 onto the stack is odd. We need to ensure that the stack
10113 is 64-bit aligned before we start to save iWMMXt registers,
10114 and also before we start to create locals. (A local variable
10115 might be a double or long long which we will load/store using
10116 an iWMMXt instruction). Therefore we need to push another
10117 ARM register, so that the stack will be 64-bit aligned. We
10118 try to avoid using the arg registers (r0 -r3) as they might be
10119 used to pass values in a tail call. */
10120 for (reg = 4; reg <= 12; reg++)
10121 if ((save_reg_mask & (1 << reg)) == 0)
10125 save_reg_mask |= (1 << reg);
10128 cfun->machine->sibcall_blocked = 1;
10129 save_reg_mask |= (1 << 3);
10133 /* We may need to push an additional register for use initializing the
10134 PIC base register. */
10135 if (TARGET_THUMB2 && IS_NESTED (func_type) && flag_pic
10136 && (save_reg_mask & THUMB2_WORK_REGS) == 0)
10138 reg = thumb_find_work_register (1 << 4);
10139 if (!call_used_regs[reg])
10140 save_reg_mask |= (1 << reg);
10143 return save_reg_mask;
10147 /* Compute a bit mask of which registers need to be
10148 saved on the stack for the current function. */
10149 static unsigned long
10150 thumb1_compute_save_reg_mask (void)
10152 unsigned long mask;
10156 for (reg = 0; reg < 12; reg ++)
10157 if (df_regs_ever_live_p (reg) && !call_used_regs[reg])
10161 && !TARGET_SINGLE_PIC_BASE
10162 && arm_pic_register != INVALID_REGNUM
10163 && current_function_uses_pic_offset_table)
10164 mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
10166 /* See if we might need r11 for calls to _interwork_r11_call_via_rN(). */
10167 if (!frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > 0)
10168 mask |= 1 << ARM_HARD_FRAME_POINTER_REGNUM;
10170 /* LR will also be pushed if any lo regs are pushed. */
10171 if (mask & 0xff || thumb_force_lr_save ())
10172 mask |= (1 << LR_REGNUM);
10174 /* Make sure we have a low work register if we need one.
10175 We will need one if we are going to push a high register,
10176 but we are not currently intending to push a low register. */
10177 if ((mask & 0xff) == 0
10178 && ((mask & 0x0f00) || TARGET_BACKTRACE))
10180 /* Use thumb_find_work_register to choose which register
10181 we will use. If the register is live then we will
10182 have to push it. Use LAST_LO_REGNUM as our fallback
10183 choice for the register to select. */
10184 reg = thumb_find_work_register (1 << LAST_LO_REGNUM);
10186 if (! call_used_regs[reg])
10194 /* Return the number of bytes required to save VFP registers. */
10196 arm_get_vfp_saved_size (void)
10198 unsigned int regno;
10203 /* Space for saved VFP registers. */
10204 if (TARGET_HARD_FLOAT && TARGET_VFP)
10207 for (regno = FIRST_VFP_REGNUM;
10208 regno < LAST_VFP_REGNUM;
10211 if ((!df_regs_ever_live_p (regno) || call_used_regs[regno])
10212 && (!df_regs_ever_live_p (regno + 1) || call_used_regs[regno + 1]))
10216 /* Workaround ARM10 VFPr1 bug. */
10217 if (count == 2 && !arm_arch6)
10219 saved += count * 8;
10228 if (count == 2 && !arm_arch6)
10230 saved += count * 8;
10237 /* Generate a function exit sequence. If REALLY_RETURN is false, then do
10238 everything bar the final return instruction. */
10240 output_return_instruction (rtx operand, int really_return, int reverse)
10242 char conditional[10];
10245 unsigned long live_regs_mask;
10246 unsigned long func_type;
10247 arm_stack_offsets *offsets;
10249 func_type = arm_current_func_type ();
10251 if (IS_NAKED (func_type))
10254 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
10256 /* If this function was declared non-returning, and we have
10257 found a tail call, then we have to trust that the called
10258 function won't return. */
10263 /* Otherwise, trap an attempted return by aborting. */
10265 ops[1] = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)"
10267 assemble_external_libcall (ops[1]);
10268 output_asm_insn (reverse ? "bl%D0\t%a1" : "bl%d0\t%a1", ops);
10274 gcc_assert (!current_function_calls_alloca || really_return);
10276 sprintf (conditional, "%%?%%%c0", reverse ? 'D' : 'd');
10278 return_used_this_function = 1;
10280 live_regs_mask = arm_compute_save_reg_mask ();
10282 if (live_regs_mask)
10284 const char * return_reg;
10286 /* If we do not have any special requirements for function exit
10287 (e.g. interworking) then we can load the return address
10288 directly into the PC. Otherwise we must load it into LR. */
10290 && (IS_INTERRUPT (func_type) || !TARGET_INTERWORK))
10291 return_reg = reg_names[PC_REGNUM];
10293 return_reg = reg_names[LR_REGNUM];
10295 if ((live_regs_mask & (1 << IP_REGNUM)) == (1 << IP_REGNUM))
10297 /* There are three possible reasons for the IP register
10298 being saved. 1) a stack frame was created, in which case
10299 IP contains the old stack pointer, or 2) an ISR routine
10300 corrupted it, or 3) it was saved to align the stack on
10301 iWMMXt. In case 1, restore IP into SP, otherwise just
10303 if (frame_pointer_needed)
10305 live_regs_mask &= ~ (1 << IP_REGNUM);
10306 live_regs_mask |= (1 << SP_REGNUM);
10309 gcc_assert (IS_INTERRUPT (func_type) || TARGET_REALLY_IWMMXT);
10312 /* On some ARM architectures it is faster to use LDR rather than
10313 LDM to load a single register. On other architectures, the
10314 cost is the same. In 26 bit mode, or for exception handlers,
10315 we have to use LDM to load the PC so that the CPSR is also
10317 for (reg = 0; reg <= LAST_ARM_REGNUM; reg++)
10318 if (live_regs_mask == (1U << reg))
10321 if (reg <= LAST_ARM_REGNUM
10322 && (reg != LR_REGNUM
10324 || ! IS_INTERRUPT (func_type)))
10326 sprintf (instr, "ldr%s\t%%|%s, [%%|sp], #4", conditional,
10327 (reg == LR_REGNUM) ? return_reg : reg_names[reg]);
10334 /* Generate the load multiple instruction to restore the
10335 registers. Note we can get here, even if
10336 frame_pointer_needed is true, but only if sp already
10337 points to the base of the saved core registers. */
10338 if (live_regs_mask & (1 << SP_REGNUM))
10340 unsigned HOST_WIDE_INT stack_adjust;
10342 offsets = arm_get_frame_offsets ();
10343 stack_adjust = offsets->outgoing_args - offsets->saved_regs;
10344 gcc_assert (stack_adjust == 0 || stack_adjust == 4);
10346 if (stack_adjust && arm_arch5 && TARGET_ARM)
10347 sprintf (instr, "ldm%sib\t%%|sp, {", conditional);
10350 /* If we can't use ldmib (SA110 bug),
10351 then try to pop r3 instead. */
10353 live_regs_mask |= 1 << 3;
10354 sprintf (instr, "ldm%sfd\t%%|sp, {", conditional);
10358 sprintf (instr, "ldm%sfd\t%%|sp!, {", conditional);
10360 p = instr + strlen (instr);
10362 for (reg = 0; reg <= SP_REGNUM; reg++)
10363 if (live_regs_mask & (1 << reg))
10365 int l = strlen (reg_names[reg]);
10371 memcpy (p, ", ", 2);
10375 memcpy (p, "%|", 2);
10376 memcpy (p + 2, reg_names[reg], l);
10380 if (live_regs_mask & (1 << LR_REGNUM))
10382 sprintf (p, "%s%%|%s}", first ? "" : ", ", return_reg);
10383 /* If returning from an interrupt, restore the CPSR. */
10384 if (IS_INTERRUPT (func_type))
10391 output_asm_insn (instr, & operand);
10393 /* See if we need to generate an extra instruction to
10394 perform the actual function return. */
10396 && func_type != ARM_FT_INTERWORKED
10397 && (live_regs_mask & (1 << LR_REGNUM)) != 0)
10399 /* The return has already been handled
10400 by loading the LR into the PC. */
10407 switch ((int) ARM_FUNC_TYPE (func_type))
10411 /* ??? This is wrong for unified assembly syntax. */
10412 sprintf (instr, "sub%ss\t%%|pc, %%|lr, #4", conditional);
10415 case ARM_FT_INTERWORKED:
10416 sprintf (instr, "bx%s\t%%|lr", conditional);
10419 case ARM_FT_EXCEPTION:
10420 /* ??? This is wrong for unified assembly syntax. */
10421 sprintf (instr, "mov%ss\t%%|pc, %%|lr", conditional);
10425 /* Use bx if it's available. */
10426 if (arm_arch5 || arm_arch4t)
10427 sprintf (instr, "bx%s\t%%|lr", conditional);
10429 sprintf (instr, "mov%s\t%%|pc, %%|lr", conditional);
10433 output_asm_insn (instr, & operand);
10439 /* Write the function name into the code section, directly preceding
10440 the function prologue.
10442 Code will be output similar to this:
10444 .ascii "arm_poke_function_name", 0
10447 .word 0xff000000 + (t1 - t0)
10448 arm_poke_function_name
10450 stmfd sp!, {fp, ip, lr, pc}
10453 When performing a stack backtrace, code can inspect the value
10454 of 'pc' stored at 'fp' + 0. If the trace function then looks
10455 at location pc - 12 and the top 8 bits are set, then we know
10456 that there is a function name embedded immediately preceding this
10457 location and has length ((pc[-3]) & 0xff000000).
10459 We assume that pc is declared as a pointer to an unsigned long.
10461 It is of no benefit to output the function name if we are assembling
10462 a leaf function. These function types will not contain a stack
10463 backtrace structure, therefore it is not possible to determine the
10466 arm_poke_function_name (FILE *stream, const char *name)
10468 unsigned long alignlength;
10469 unsigned long length;
10472 length = strlen (name) + 1;
10473 alignlength = ROUND_UP_WORD (length);
10475 ASM_OUTPUT_ASCII (stream, name, length);
10476 ASM_OUTPUT_ALIGN (stream, 2);
10477 x = GEN_INT ((unsigned HOST_WIDE_INT) 0xff000000 + alignlength);
10478 assemble_aligned_integer (UNITS_PER_WORD, x);
10481 /* Place some comments into the assembler stream
10482 describing the current function. */
10484 arm_output_function_prologue (FILE *f, HOST_WIDE_INT frame_size)
10486 unsigned long func_type;
10490 thumb1_output_function_prologue (f, frame_size);
10494 /* Sanity check. */
10495 gcc_assert (!arm_ccfsm_state && !arm_target_insn);
10497 func_type = arm_current_func_type ();
10499 switch ((int) ARM_FUNC_TYPE (func_type))
10502 case ARM_FT_NORMAL:
10504 case ARM_FT_INTERWORKED:
10505 asm_fprintf (f, "\t%@ Function supports interworking.\n");
10508 asm_fprintf (f, "\t%@ Interrupt Service Routine.\n");
10511 asm_fprintf (f, "\t%@ Fast Interrupt Service Routine.\n");
10513 case ARM_FT_EXCEPTION:
10514 asm_fprintf (f, "\t%@ ARM Exception Handler.\n");
10518 if (IS_NAKED (func_type))
10519 asm_fprintf (f, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n");
10521 if (IS_VOLATILE (func_type))
10522 asm_fprintf (f, "\t%@ Volatile: function does not return.\n");
10524 if (IS_NESTED (func_type))
10525 asm_fprintf (f, "\t%@ Nested: function declared inside another function.\n");
10526 if (IS_STACKALIGN (func_type))
10527 asm_fprintf (f, "\t%@ Stack Align: May be called with mis-aligned SP.\n");
10529 asm_fprintf (f, "\t%@ args = %d, pretend = %d, frame = %wd\n",
10530 current_function_args_size,
10531 current_function_pretend_args_size, frame_size);
10533 asm_fprintf (f, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n",
10534 frame_pointer_needed,
10535 cfun->machine->uses_anonymous_args);
10537 if (cfun->machine->lr_save_eliminated)
10538 asm_fprintf (f, "\t%@ link register save eliminated.\n");
10540 if (current_function_calls_eh_return)
10541 asm_fprintf (f, "\t@ Calls __builtin_eh_return.\n");
10543 #ifdef AOF_ASSEMBLER
10545 asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, PIC_OFFSET_TABLE_REGNUM);
10548 return_used_this_function = 0;
10552 arm_output_epilogue (rtx sibling)
10555 unsigned long saved_regs_mask;
10556 unsigned long func_type;
10557 /* Floats_offset is the offset from the "virtual" frame. In an APCS
10558 frame that is $fp + 4 for a non-variadic function. */
10559 int floats_offset = 0;
10561 FILE * f = asm_out_file;
10562 unsigned int lrm_count = 0;
10563 int really_return = (sibling == NULL);
10565 arm_stack_offsets *offsets;
10567 /* If we have already generated the return instruction
10568 then it is futile to generate anything else. */
10569 if (use_return_insn (FALSE, sibling) && return_used_this_function)
10572 func_type = arm_current_func_type ();
10574 if (IS_NAKED (func_type))
10575 /* Naked functions don't have epilogues. */
10578 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
10582 /* A volatile function should never return. Call abort. */
10583 op = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" : "abort");
10584 assemble_external_libcall (op);
10585 output_asm_insn ("bl\t%a0", &op);
10590 /* If we are throwing an exception, then we really must be doing a
10591 return, so we can't tail-call. */
10592 gcc_assert (!current_function_calls_eh_return || really_return);
10594 offsets = arm_get_frame_offsets ();
10595 saved_regs_mask = arm_compute_save_reg_mask ();
10598 lrm_count = bit_count (saved_regs_mask);
10600 floats_offset = offsets->saved_args;
10601 /* Compute how far away the floats will be. */
10602 for (reg = 0; reg <= LAST_ARM_REGNUM; reg++)
10603 if (saved_regs_mask & (1 << reg))
10604 floats_offset += 4;
10606 if (frame_pointer_needed && TARGET_ARM)
10608 /* This variable is for the Virtual Frame Pointer, not VFP regs. */
10609 int vfp_offset = offsets->frame;
10611 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
10613 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
10614 if (df_regs_ever_live_p (reg) && !call_used_regs[reg])
10616 floats_offset += 12;
10617 asm_fprintf (f, "\tldfe\t%r, [%r, #-%d]\n",
10618 reg, FP_REGNUM, floats_offset - vfp_offset);
10623 start_reg = LAST_FPA_REGNUM;
10625 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
10627 if (df_regs_ever_live_p (reg) && !call_used_regs[reg])
10629 floats_offset += 12;
10631 /* We can't unstack more than four registers at once. */
10632 if (start_reg - reg == 3)
10634 asm_fprintf (f, "\tlfm\t%r, 4, [%r, #-%d]\n",
10635 reg, FP_REGNUM, floats_offset - vfp_offset);
10636 start_reg = reg - 1;
10641 if (reg != start_reg)
10642 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
10643 reg + 1, start_reg - reg,
10644 FP_REGNUM, floats_offset - vfp_offset);
10645 start_reg = reg - 1;
10649 /* Just in case the last register checked also needs unstacking. */
10650 if (reg != start_reg)
10651 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
10652 reg + 1, start_reg - reg,
10653 FP_REGNUM, floats_offset - vfp_offset);
10656 if (TARGET_HARD_FLOAT && TARGET_VFP)
10660 /* The fldmd insns do not have base+offset addressing
10661 modes, so we use IP to hold the address. */
10662 saved_size = arm_get_vfp_saved_size ();
10664 if (saved_size > 0)
10666 floats_offset += saved_size;
10667 asm_fprintf (f, "\tsub\t%r, %r, #%d\n", IP_REGNUM,
10668 FP_REGNUM, floats_offset - vfp_offset);
10670 start_reg = FIRST_VFP_REGNUM;
10671 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
10673 if ((!df_regs_ever_live_p (reg) || call_used_regs[reg])
10674 && (!df_regs_ever_live_p (reg + 1) || call_used_regs[reg + 1]))
10676 if (start_reg != reg)
10677 vfp_output_fldmd (f, IP_REGNUM,
10678 (start_reg - FIRST_VFP_REGNUM) / 2,
10679 (reg - start_reg) / 2);
10680 start_reg = reg + 2;
10683 if (start_reg != reg)
10684 vfp_output_fldmd (f, IP_REGNUM,
10685 (start_reg - FIRST_VFP_REGNUM) / 2,
10686 (reg - start_reg) / 2);
10691 /* The frame pointer is guaranteed to be non-double-word aligned.
10692 This is because it is set to (old_stack_pointer - 4) and the
10693 old_stack_pointer was double word aligned. Thus the offset to
10694 the iWMMXt registers to be loaded must also be non-double-word
10695 sized, so that the resultant address *is* double-word aligned.
10696 We can ignore floats_offset since that was already included in
10697 the live_regs_mask. */
10698 lrm_count += (lrm_count % 2 ? 2 : 1);
10700 for (reg = LAST_IWMMXT_REGNUM; reg >= FIRST_IWMMXT_REGNUM; reg--)
10701 if (df_regs_ever_live_p (reg) && !call_used_regs[reg])
10703 asm_fprintf (f, "\twldrd\t%r, [%r, #-%d]\n",
10704 reg, FP_REGNUM, lrm_count * 4);
10709 /* saved_regs_mask should contain the IP, which at the time of stack
10710 frame generation actually contains the old stack pointer. So a
10711 quick way to unwind the stack is just pop the IP register directly
10712 into the stack pointer. */
10713 gcc_assert (saved_regs_mask & (1 << IP_REGNUM));
10714 saved_regs_mask &= ~ (1 << IP_REGNUM);
10715 saved_regs_mask |= (1 << SP_REGNUM);
10717 /* There are two registers left in saved_regs_mask - LR and PC. We
10718 only need to restore the LR register (the return address), but to
10719 save time we can load it directly into the PC, unless we need a
10720 special function exit sequence, or we are not really returning. */
10722 && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
10723 && !current_function_calls_eh_return)
10724 /* Delete the LR from the register mask, so that the LR on
10725 the stack is loaded into the PC in the register mask. */
10726 saved_regs_mask &= ~ (1 << LR_REGNUM);
10728 saved_regs_mask &= ~ (1 << PC_REGNUM);
10730 /* We must use SP as the base register, because SP is one of the
10731 registers being restored. If an interrupt or page fault
10732 happens in the ldm instruction, the SP might or might not
10733 have been restored. That would be bad, as then SP will no
10734 longer indicate the safe area of stack, and we can get stack
10735 corruption. Using SP as the base register means that it will
10736 be reset correctly to the original value, should an interrupt
10737 occur. If the stack pointer already points at the right
10738 place, then omit the subtraction. */
10739 if (offsets->outgoing_args != (1 + (int) bit_count (saved_regs_mask))
10740 || current_function_calls_alloca)
10741 asm_fprintf (f, "\tsub\t%r, %r, #%d\n", SP_REGNUM, FP_REGNUM,
10742 4 * bit_count (saved_regs_mask));
10743 print_multi_reg (f, "ldmfd\t%r, ", SP_REGNUM, saved_regs_mask, 0);
10745 if (IS_INTERRUPT (func_type))
10746 /* Interrupt handlers will have pushed the
10747 IP onto the stack, so restore it now. */
10748 print_multi_reg (f, "ldmfd\t%r!, ", SP_REGNUM, 1 << IP_REGNUM, 0);
10752 HOST_WIDE_INT amount;
10754 /* Restore stack pointer if necessary. */
10755 if (frame_pointer_needed)
10757 /* For Thumb-2 restore sp from the frame pointer.
10758 Operand restrictions mean we have to increment FP, then copy
10760 amount = offsets->locals_base - offsets->saved_regs;
10761 operands[0] = hard_frame_pointer_rtx;
10765 operands[0] = stack_pointer_rtx;
10766 amount = offsets->outgoing_args - offsets->saved_regs;
10771 operands[1] = operands[0];
10772 operands[2] = GEN_INT (amount);
10773 output_add_immediate (operands);
10775 if (frame_pointer_needed)
10776 asm_fprintf (f, "\tmov\t%r, %r\n",
10777 SP_REGNUM, HARD_FRAME_POINTER_REGNUM);
10779 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
10781 for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++)
10782 if (df_regs_ever_live_p (reg) && !call_used_regs[reg])
10783 asm_fprintf (f, "\tldfe\t%r, [%r], #12\n",
10788 start_reg = FIRST_FPA_REGNUM;
10790 for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++)
10792 if (df_regs_ever_live_p (reg) && !call_used_regs[reg])
10794 if (reg - start_reg == 3)
10796 asm_fprintf (f, "\tlfmfd\t%r, 4, [%r]!\n",
10797 start_reg, SP_REGNUM);
10798 start_reg = reg + 1;
10803 if (reg != start_reg)
10804 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
10805 start_reg, reg - start_reg,
10808 start_reg = reg + 1;
10812 /* Just in case the last register checked also needs unstacking. */
10813 if (reg != start_reg)
10814 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
10815 start_reg, reg - start_reg, SP_REGNUM);
10818 if (TARGET_HARD_FLOAT && TARGET_VFP)
10820 start_reg = FIRST_VFP_REGNUM;
10821 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
10823 if ((!df_regs_ever_live_p (reg) || call_used_regs[reg])
10824 && (!df_regs_ever_live_p (reg + 1) || call_used_regs[reg + 1]))
10826 if (start_reg != reg)
10827 vfp_output_fldmd (f, SP_REGNUM,
10828 (start_reg - FIRST_VFP_REGNUM) / 2,
10829 (reg - start_reg) / 2);
10830 start_reg = reg + 2;
10833 if (start_reg != reg)
10834 vfp_output_fldmd (f, SP_REGNUM,
10835 (start_reg - FIRST_VFP_REGNUM) / 2,
10836 (reg - start_reg) / 2);
10839 for (reg = FIRST_IWMMXT_REGNUM; reg <= LAST_IWMMXT_REGNUM; reg++)
10840 if (df_regs_ever_live_p (reg) && !call_used_regs[reg])
10841 asm_fprintf (f, "\twldrd\t%r, [%r], #8\n", reg, SP_REGNUM);
10843 /* If we can, restore the LR into the PC. */
10844 if (ARM_FUNC_TYPE (func_type) != ARM_FT_INTERWORKED
10845 && (TARGET_ARM || ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL)
10846 && !IS_STACKALIGN (func_type)
10848 && current_function_pretend_args_size == 0
10849 && saved_regs_mask & (1 << LR_REGNUM)
10850 && !current_function_calls_eh_return)
10852 saved_regs_mask &= ~ (1 << LR_REGNUM);
10853 saved_regs_mask |= (1 << PC_REGNUM);
10854 rfe = IS_INTERRUPT (func_type);
10859 /* Load the registers off the stack. If we only have one register
10860 to load use the LDR instruction - it is faster. For Thumb-2
10861 always use pop and the assembler will pick the best instruction.*/
10862 if (TARGET_ARM && saved_regs_mask == (1 << LR_REGNUM)
10863 && !IS_INTERRUPT(func_type))
10865 asm_fprintf (f, "\tldr\t%r, [%r], #4\n", LR_REGNUM, SP_REGNUM);
10867 else if (saved_regs_mask)
10869 if (saved_regs_mask & (1 << SP_REGNUM))
10870 /* Note - write back to the stack register is not enabled
10871 (i.e. "ldmfd sp!..."). We know that the stack pointer is
10872 in the list of registers and if we add writeback the
10873 instruction becomes UNPREDICTABLE. */
10874 print_multi_reg (f, "ldmfd\t%r, ", SP_REGNUM, saved_regs_mask,
10876 else if (TARGET_ARM)
10877 print_multi_reg (f, "ldmfd\t%r!, ", SP_REGNUM, saved_regs_mask,
10880 print_multi_reg (f, "pop\t", SP_REGNUM, saved_regs_mask, 0);
10883 if (current_function_pretend_args_size)
10885 /* Unwind the pre-pushed regs. */
10886 operands[0] = operands[1] = stack_pointer_rtx;
10887 operands[2] = GEN_INT (current_function_pretend_args_size);
10888 output_add_immediate (operands);
10892 /* We may have already restored PC directly from the stack. */
10893 if (!really_return || saved_regs_mask & (1 << PC_REGNUM))
10896 /* Stack adjustment for exception handler. */
10897 if (current_function_calls_eh_return)
10898 asm_fprintf (f, "\tadd\t%r, %r, %r\n", SP_REGNUM, SP_REGNUM,
10899 ARM_EH_STACKADJ_REGNUM);
10901 /* Generate the return instruction. */
10902 switch ((int) ARM_FUNC_TYPE (func_type))
10906 asm_fprintf (f, "\tsubs\t%r, %r, #4\n", PC_REGNUM, LR_REGNUM);
10909 case ARM_FT_EXCEPTION:
10910 asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM);
10913 case ARM_FT_INTERWORKED:
10914 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
10918 if (IS_STACKALIGN (func_type))
10920 /* See comment in arm_expand_prologue. */
10921 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, 0);
10923 if (arm_arch5 || arm_arch4t)
10924 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
10926 asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, LR_REGNUM);
10934 arm_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
10935 HOST_WIDE_INT frame_size ATTRIBUTE_UNUSED)
10937 arm_stack_offsets *offsets;
10943 /* Emit any call-via-reg trampolines that are needed for v4t support
10944 of call_reg and call_value_reg type insns. */
10945 for (regno = 0; regno < LR_REGNUM; regno++)
10947 rtx label = cfun->machine->call_via[regno];
10951 switch_to_section (function_section (current_function_decl));
10952 targetm.asm_out.internal_label (asm_out_file, "L",
10953 CODE_LABEL_NUMBER (label));
10954 asm_fprintf (asm_out_file, "\tbx\t%r\n", regno);
10958 /* ??? Probably not safe to set this here, since it assumes that a
10959 function will be emitted as assembly immediately after we generate
10960 RTL for it. This does not happen for inline functions. */
10961 return_used_this_function = 0;
10963 else /* TARGET_32BIT */
10965 /* We need to take into account any stack-frame rounding. */
10966 offsets = arm_get_frame_offsets ();
10968 gcc_assert (!use_return_insn (FALSE, NULL)
10969 || !return_used_this_function
10970 || offsets->saved_regs == offsets->outgoing_args
10971 || frame_pointer_needed);
10973 /* Reset the ARM-specific per-function variables. */
10974 after_arm_reorg = 0;
10978 /* Generate and emit an insn that we will recognize as a push_multi.
10979 Unfortunately, since this insn does not reflect very well the actual
10980 semantics of the operation, we need to annotate the insn for the benefit
10981 of DWARF2 frame unwind information. */
10983 emit_multi_reg_push (unsigned long mask)
10986 int num_dwarf_regs;
10990 int dwarf_par_index;
10993 for (i = 0; i <= LAST_ARM_REGNUM; i++)
10994 if (mask & (1 << i))
10997 gcc_assert (num_regs && num_regs <= 16);
10999 /* We don't record the PC in the dwarf frame information. */
11000 num_dwarf_regs = num_regs;
11001 if (mask & (1 << PC_REGNUM))
11004 /* For the body of the insn we are going to generate an UNSPEC in
11005 parallel with several USEs. This allows the insn to be recognized
11006 by the push_multi pattern in the arm.md file. The insn looks
11007 something like this:
11010 (set (mem:BLK (pre_dec:BLK (reg:SI sp)))
11011 (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT))
11012 (use (reg:SI 11 fp))
11013 (use (reg:SI 12 ip))
11014 (use (reg:SI 14 lr))
11015 (use (reg:SI 15 pc))
11018 For the frame note however, we try to be more explicit and actually
11019 show each register being stored into the stack frame, plus a (single)
11020 decrement of the stack pointer. We do it this way in order to be
11021 friendly to the stack unwinding code, which only wants to see a single
11022 stack decrement per instruction. The RTL we generate for the note looks
11023 something like this:
11026 (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20)))
11027 (set (mem:SI (reg:SI sp)) (reg:SI r4))
11028 (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp))
11029 (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip))
11030 (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr))
11033 This sequence is used both by the code to support stack unwinding for
11034 exceptions handlers and the code to generate dwarf2 frame debugging. */
11036 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_regs));
11037 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (num_dwarf_regs + 1));
11038 dwarf_par_index = 1;
11040 for (i = 0; i <= LAST_ARM_REGNUM; i++)
11042 if (mask & (1 << i))
11044 reg = gen_rtx_REG (SImode, i);
11046 XVECEXP (par, 0, 0)
11047 = gen_rtx_SET (VOIDmode,
11048 gen_frame_mem (BLKmode,
11049 gen_rtx_PRE_DEC (BLKmode,
11050 stack_pointer_rtx)),
11051 gen_rtx_UNSPEC (BLKmode,
11052 gen_rtvec (1, reg),
11053 UNSPEC_PUSH_MULT));
11055 if (i != PC_REGNUM)
11057 tmp = gen_rtx_SET (VOIDmode,
11058 gen_frame_mem (SImode, stack_pointer_rtx),
11060 RTX_FRAME_RELATED_P (tmp) = 1;
11061 XVECEXP (dwarf, 0, dwarf_par_index) = tmp;
11069 for (j = 1, i++; j < num_regs; i++)
11071 if (mask & (1 << i))
11073 reg = gen_rtx_REG (SImode, i);
11075 XVECEXP (par, 0, j) = gen_rtx_USE (VOIDmode, reg);
11077 if (i != PC_REGNUM)
11080 = gen_rtx_SET (VOIDmode,
11081 gen_frame_mem (SImode,
11082 plus_constant (stack_pointer_rtx,
11085 RTX_FRAME_RELATED_P (tmp) = 1;
11086 XVECEXP (dwarf, 0, dwarf_par_index++) = tmp;
11093 par = emit_insn (par);
11095 tmp = gen_rtx_SET (VOIDmode,
11097 plus_constant (stack_pointer_rtx, -4 * num_regs));
11098 RTX_FRAME_RELATED_P (tmp) = 1;
11099 XVECEXP (dwarf, 0, 0) = tmp;
11101 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
11106 /* Calculate the size of the return value that is passed in registers. */
11108 arm_size_return_regs (void)
11110 enum machine_mode mode;
11112 if (current_function_return_rtx != 0)
11113 mode = GET_MODE (current_function_return_rtx);
11115 mode = DECL_MODE (DECL_RESULT (current_function_decl));
11117 return GET_MODE_SIZE (mode);
11121 emit_sfm (int base_reg, int count)
11128 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
11129 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (count + 1));
11131 reg = gen_rtx_REG (XFmode, base_reg++);
11133 XVECEXP (par, 0, 0)
11134 = gen_rtx_SET (VOIDmode,
11135 gen_frame_mem (BLKmode,
11136 gen_rtx_PRE_DEC (BLKmode,
11137 stack_pointer_rtx)),
11138 gen_rtx_UNSPEC (BLKmode,
11139 gen_rtvec (1, reg),
11140 UNSPEC_PUSH_MULT));
11141 tmp = gen_rtx_SET (VOIDmode,
11142 gen_frame_mem (XFmode, stack_pointer_rtx), reg);
11143 RTX_FRAME_RELATED_P (tmp) = 1;
11144 XVECEXP (dwarf, 0, 1) = tmp;
11146 for (i = 1; i < count; i++)
11148 reg = gen_rtx_REG (XFmode, base_reg++);
11149 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
11151 tmp = gen_rtx_SET (VOIDmode,
11152 gen_frame_mem (XFmode,
11153 plus_constant (stack_pointer_rtx,
11156 RTX_FRAME_RELATED_P (tmp) = 1;
11157 XVECEXP (dwarf, 0, i + 1) = tmp;
11160 tmp = gen_rtx_SET (VOIDmode,
11162 plus_constant (stack_pointer_rtx, -12 * count));
11164 RTX_FRAME_RELATED_P (tmp) = 1;
11165 XVECEXP (dwarf, 0, 0) = tmp;
11167 par = emit_insn (par);
11168 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
11174 /* Return true if the current function needs to save/restore LR. */
11177 thumb_force_lr_save (void)
11179 return !cfun->machine->lr_save_eliminated
11180 && (!leaf_function_p ()
11181 || thumb_far_jump_used_p ()
11182 || df_regs_ever_live_p (LR_REGNUM));
11186 /* Compute the distance from register FROM to register TO.
11187 These can be the arg pointer (26), the soft frame pointer (25),
11188 the stack pointer (13) or the hard frame pointer (11).
11189 In thumb mode r7 is used as the soft frame pointer, if needed.
11190 Typical stack layout looks like this:
11192 old stack pointer -> | |
11195 | | saved arguments for
11196 | | vararg functions
11199 hard FP & arg pointer -> | | \
11207 soft frame pointer -> | | /
11212 locals base pointer -> | | /
11217 current stack pointer -> | | /
11220 For a given function some or all of these stack components
11221 may not be needed, giving rise to the possibility of
11222 eliminating some of the registers.
11224 The values returned by this function must reflect the behavior
11225 of arm_expand_prologue() and arm_compute_save_reg_mask().
11227 The sign of the number returned reflects the direction of stack
11228 growth, so the values are positive for all eliminations except
11229 from the soft frame pointer to the hard frame pointer.
11231 SFP may point just inside the local variables block to ensure correct
11235 /* Calculate stack offsets. These are used to calculate register elimination
11236 offsets and in prologue/epilogue code. */
11238 static arm_stack_offsets *
11239 arm_get_frame_offsets (void)
11241 struct arm_stack_offsets *offsets;
11242 unsigned long func_type;
11245 HOST_WIDE_INT frame_size;
11247 offsets = &cfun->machine->stack_offsets;
11249 /* We need to know if we are a leaf function. Unfortunately, it
11250 is possible to be called after start_sequence has been called,
11251 which causes get_insns to return the insns for the sequence,
11252 not the function, which will cause leaf_function_p to return
11253 the incorrect result.
11255 to know about leaf functions once reload has completed, and the
11256 frame size cannot be changed after that time, so we can safely
11257 use the cached value. */
11259 if (reload_completed)
11262 /* Initially this is the size of the local variables. It will translated
11263 into an offset once we have determined the size of preceding data. */
11264 frame_size = ROUND_UP_WORD (get_frame_size ());
11266 leaf = leaf_function_p ();
11268 /* Space for variadic functions. */
11269 offsets->saved_args = current_function_pretend_args_size;
11271 /* In Thumb mode this is incorrect, but never used. */
11272 offsets->frame = offsets->saved_args + (frame_pointer_needed ? 4 : 0);
11276 unsigned int regno;
11278 saved = bit_count (arm_compute_save_reg_mask ()) * 4;
11280 /* We know that SP will be doubleword aligned on entry, and we must
11281 preserve that condition at any subroutine call. We also require the
11282 soft frame pointer to be doubleword aligned. */
11284 if (TARGET_REALLY_IWMMXT)
11286 /* Check for the call-saved iWMMXt registers. */
11287 for (regno = FIRST_IWMMXT_REGNUM;
11288 regno <= LAST_IWMMXT_REGNUM;
11290 if (df_regs_ever_live_p (regno) && ! call_used_regs[regno])
11294 func_type = arm_current_func_type ();
11295 if (! IS_VOLATILE (func_type))
11297 /* Space for saved FPA registers. */
11298 for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++)
11299 if (df_regs_ever_live_p (regno) && ! call_used_regs[regno])
11302 /* Space for saved VFP registers. */
11303 if (TARGET_HARD_FLOAT && TARGET_VFP)
11304 saved += arm_get_vfp_saved_size ();
11307 else /* TARGET_THUMB1 */
11309 saved = bit_count (thumb1_compute_save_reg_mask ()) * 4;
11310 if (TARGET_BACKTRACE)
11314 /* Saved registers include the stack frame. */
11315 offsets->saved_regs = offsets->saved_args + saved;
11316 offsets->soft_frame = offsets->saved_regs + CALLER_INTERWORKING_SLOT_SIZE;
11317 /* A leaf function does not need any stack alignment if it has nothing
11319 if (leaf && frame_size == 0)
11321 offsets->outgoing_args = offsets->soft_frame;
11322 offsets->locals_base = offsets->soft_frame;
11326 /* Ensure SFP has the correct alignment. */
11327 if (ARM_DOUBLEWORD_ALIGN
11328 && (offsets->soft_frame & 7))
11329 offsets->soft_frame += 4;
11331 offsets->locals_base = offsets->soft_frame + frame_size;
11332 offsets->outgoing_args = (offsets->locals_base
11333 + current_function_outgoing_args_size);
11335 if (ARM_DOUBLEWORD_ALIGN)
11337 /* Ensure SP remains doubleword aligned. */
11338 if (offsets->outgoing_args & 7)
11339 offsets->outgoing_args += 4;
11340 gcc_assert (!(offsets->outgoing_args & 7));
11347 /* Calculate the relative offsets for the different stack pointers. Positive
11348 offsets are in the direction of stack growth. */
11351 arm_compute_initial_elimination_offset (unsigned int from, unsigned int to)
11353 arm_stack_offsets *offsets;
11355 offsets = arm_get_frame_offsets ();
11357 /* OK, now we have enough information to compute the distances.
11358 There must be an entry in these switch tables for each pair
11359 of registers in ELIMINABLE_REGS, even if some of the entries
11360 seem to be redundant or useless. */
11363 case ARG_POINTER_REGNUM:
11366 case THUMB_HARD_FRAME_POINTER_REGNUM:
11369 case FRAME_POINTER_REGNUM:
11370 /* This is the reverse of the soft frame pointer
11371 to hard frame pointer elimination below. */
11372 return offsets->soft_frame - offsets->saved_args;
11374 case ARM_HARD_FRAME_POINTER_REGNUM:
11375 /* If there is no stack frame then the hard
11376 frame pointer and the arg pointer coincide. */
11377 if (offsets->frame == offsets->saved_regs)
11379 /* FIXME: Not sure about this. Maybe we should always return 0 ? */
11380 return (frame_pointer_needed
11381 && cfun->static_chain_decl != NULL
11382 && ! cfun->machine->uses_anonymous_args) ? 4 : 0;
11384 case STACK_POINTER_REGNUM:
11385 /* If nothing has been pushed on the stack at all
11386 then this will return -4. This *is* correct! */
11387 return offsets->outgoing_args - (offsets->saved_args + 4);
11390 gcc_unreachable ();
11392 gcc_unreachable ();
11394 case FRAME_POINTER_REGNUM:
11397 case THUMB_HARD_FRAME_POINTER_REGNUM:
11400 case ARM_HARD_FRAME_POINTER_REGNUM:
11401 /* The hard frame pointer points to the top entry in the
11402 stack frame. The soft frame pointer to the bottom entry
11403 in the stack frame. If there is no stack frame at all,
11404 then they are identical. */
11406 return offsets->frame - offsets->soft_frame;
11408 case STACK_POINTER_REGNUM:
11409 return offsets->outgoing_args - offsets->soft_frame;
11412 gcc_unreachable ();
11414 gcc_unreachable ();
11417 /* You cannot eliminate from the stack pointer.
11418 In theory you could eliminate from the hard frame
11419 pointer to the stack pointer, but this will never
11420 happen, since if a stack frame is not needed the
11421 hard frame pointer will never be used. */
11422 gcc_unreachable ();
11427 /* Emit RTL to save coprocessor registers on function entry. Returns the
11428 number of bytes pushed. */
11431 arm_save_coproc_regs(void)
11433 int saved_size = 0;
11435 unsigned start_reg;
11438 for (reg = LAST_IWMMXT_REGNUM; reg >= FIRST_IWMMXT_REGNUM; reg--)
11439 if (df_regs_ever_live_p (reg) && ! call_used_regs[reg])
11441 insn = gen_rtx_PRE_DEC (V2SImode, stack_pointer_rtx);
11442 insn = gen_rtx_MEM (V2SImode, insn);
11443 insn = emit_set_insn (insn, gen_rtx_REG (V2SImode, reg));
11444 RTX_FRAME_RELATED_P (insn) = 1;
11448 /* Save any floating point call-saved registers used by this
11450 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
11452 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
11453 if (df_regs_ever_live_p (reg) && !call_used_regs[reg])
11455 insn = gen_rtx_PRE_DEC (XFmode, stack_pointer_rtx);
11456 insn = gen_rtx_MEM (XFmode, insn);
11457 insn = emit_set_insn (insn, gen_rtx_REG (XFmode, reg));
11458 RTX_FRAME_RELATED_P (insn) = 1;
11464 start_reg = LAST_FPA_REGNUM;
11466 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
11468 if (df_regs_ever_live_p (reg) && !call_used_regs[reg])
11470 if (start_reg - reg == 3)
11472 insn = emit_sfm (reg, 4);
11473 RTX_FRAME_RELATED_P (insn) = 1;
11475 start_reg = reg - 1;
11480 if (start_reg != reg)
11482 insn = emit_sfm (reg + 1, start_reg - reg);
11483 RTX_FRAME_RELATED_P (insn) = 1;
11484 saved_size += (start_reg - reg) * 12;
11486 start_reg = reg - 1;
11490 if (start_reg != reg)
11492 insn = emit_sfm (reg + 1, start_reg - reg);
11493 saved_size += (start_reg - reg) * 12;
11494 RTX_FRAME_RELATED_P (insn) = 1;
11497 if (TARGET_HARD_FLOAT && TARGET_VFP)
11499 start_reg = FIRST_VFP_REGNUM;
11501 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
11503 if ((!df_regs_ever_live_p (reg) || call_used_regs[reg])
11504 && (!df_regs_ever_live_p (reg + 1) || call_used_regs[reg + 1]))
11506 if (start_reg != reg)
11507 saved_size += vfp_emit_fstmd (start_reg,
11508 (reg - start_reg) / 2);
11509 start_reg = reg + 2;
11512 if (start_reg != reg)
11513 saved_size += vfp_emit_fstmd (start_reg,
11514 (reg - start_reg) / 2);
11520 /* Set the Thumb frame pointer from the stack pointer. */
11523 thumb_set_frame_pointer (arm_stack_offsets *offsets)
11525 HOST_WIDE_INT amount;
11528 amount = offsets->outgoing_args - offsets->locals_base;
11530 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
11531 stack_pointer_rtx, GEN_INT (amount)));
11534 emit_insn (gen_movsi (hard_frame_pointer_rtx, GEN_INT (amount)));
11535 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
11536 hard_frame_pointer_rtx,
11537 stack_pointer_rtx));
11538 dwarf = gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
11539 plus_constant (stack_pointer_rtx, amount));
11540 RTX_FRAME_RELATED_P (dwarf) = 1;
11541 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
11545 RTX_FRAME_RELATED_P (insn) = 1;
11548 /* Generate the prologue instructions for entry into an ARM or Thumb-2
11551 arm_expand_prologue (void)
11556 unsigned long live_regs_mask;
11557 unsigned long func_type;
11559 int saved_pretend_args = 0;
11560 int saved_regs = 0;
11561 unsigned HOST_WIDE_INT args_to_push;
11562 arm_stack_offsets *offsets;
11564 func_type = arm_current_func_type ();
11566 /* Naked functions don't have prologues. */
11567 if (IS_NAKED (func_type))
11570 /* Make a copy of c_f_p_a_s as we may need to modify it locally. */
11571 args_to_push = current_function_pretend_args_size;
11573 /* Compute which register we will have to save onto the stack. */
11574 live_regs_mask = arm_compute_save_reg_mask ();
11576 ip_rtx = gen_rtx_REG (SImode, IP_REGNUM);
11578 if (IS_STACKALIGN (func_type))
11583 /* Handle a word-aligned stack pointer. We generate the following:
11588 <save and restore r0 in normal prologue/epilogue>
11592 The unwinder doesn't need to know about the stack realignment.
11593 Just tell it we saved SP in r0. */
11594 gcc_assert (TARGET_THUMB2 && !arm_arch_notm && args_to_push == 0);
11596 r0 = gen_rtx_REG (SImode, 0);
11597 r1 = gen_rtx_REG (SImode, 1);
11598 dwarf = gen_rtx_UNSPEC (SImode, NULL_RTVEC, UNSPEC_STACK_ALIGN);
11599 dwarf = gen_rtx_SET (VOIDmode, r0, dwarf);
11600 insn = gen_movsi (r0, stack_pointer_rtx);
11601 RTX_FRAME_RELATED_P (insn) = 1;
11602 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
11603 dwarf, REG_NOTES (insn));
11605 emit_insn (gen_andsi3 (r1, r0, GEN_INT (~(HOST_WIDE_INT)7)));
11606 emit_insn (gen_movsi (stack_pointer_rtx, r1));
11609 if (frame_pointer_needed && TARGET_ARM)
11611 if (IS_INTERRUPT (func_type))
11613 /* Interrupt functions must not corrupt any registers.
11614 Creating a frame pointer however, corrupts the IP
11615 register, so we must push it first. */
11616 insn = emit_multi_reg_push (1 << IP_REGNUM);
11618 /* Do not set RTX_FRAME_RELATED_P on this insn.
11619 The dwarf stack unwinding code only wants to see one
11620 stack decrement per function, and this is not it. If
11621 this instruction is labeled as being part of the frame
11622 creation sequence then dwarf2out_frame_debug_expr will
11623 die when it encounters the assignment of IP to FP
11624 later on, since the use of SP here establishes SP as
11625 the CFA register and not IP.
11627 Anyway this instruction is not really part of the stack
11628 frame creation although it is part of the prologue. */
11630 else if (IS_NESTED (func_type))
11632 /* The Static chain register is the same as the IP register
11633 used as a scratch register during stack frame creation.
11634 To get around this need to find somewhere to store IP
11635 whilst the frame is being created. We try the following
11638 1. The last argument register.
11639 2. A slot on the stack above the frame. (This only
11640 works if the function is not a varargs function).
11641 3. Register r3, after pushing the argument registers
11644 Note - we only need to tell the dwarf2 backend about the SP
11645 adjustment in the second variant; the static chain register
11646 doesn't need to be unwound, as it doesn't contain a value
11647 inherited from the caller. */
11649 if (df_regs_ever_live_p (3) == false)
11650 insn = emit_set_insn (gen_rtx_REG (SImode, 3), ip_rtx);
11651 else if (args_to_push == 0)
11655 insn = gen_rtx_PRE_DEC (SImode, stack_pointer_rtx);
11656 insn = emit_set_insn (gen_frame_mem (SImode, insn), ip_rtx);
11659 /* Just tell the dwarf backend that we adjusted SP. */
11660 dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
11661 plus_constant (stack_pointer_rtx,
11663 RTX_FRAME_RELATED_P (insn) = 1;
11664 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
11665 dwarf, REG_NOTES (insn));
11669 /* Store the args on the stack. */
11670 if (cfun->machine->uses_anonymous_args)
11671 insn = emit_multi_reg_push
11672 ((0xf0 >> (args_to_push / 4)) & 0xf);
11675 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
11676 GEN_INT (- args_to_push)));
11678 RTX_FRAME_RELATED_P (insn) = 1;
11680 saved_pretend_args = 1;
11681 fp_offset = args_to_push;
11684 /* Now reuse r3 to preserve IP. */
11685 emit_set_insn (gen_rtx_REG (SImode, 3), ip_rtx);
11689 insn = emit_set_insn (ip_rtx,
11690 plus_constant (stack_pointer_rtx, fp_offset));
11691 RTX_FRAME_RELATED_P (insn) = 1;
11696 /* Push the argument registers, or reserve space for them. */
11697 if (cfun->machine->uses_anonymous_args)
11698 insn = emit_multi_reg_push
11699 ((0xf0 >> (args_to_push / 4)) & 0xf);
11702 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
11703 GEN_INT (- args_to_push)));
11704 RTX_FRAME_RELATED_P (insn) = 1;
11707 /* If this is an interrupt service routine, and the link register
11708 is going to be pushed, and we are not creating a stack frame,
11709 (which would involve an extra push of IP and a pop in the epilogue)
11710 subtracting four from LR now will mean that the function return
11711 can be done with a single instruction. */
11712 if ((func_type == ARM_FT_ISR || func_type == ARM_FT_FIQ)
11713 && (live_regs_mask & (1 << LR_REGNUM)) != 0
11714 && ! frame_pointer_needed
11717 rtx lr = gen_rtx_REG (SImode, LR_REGNUM);
11719 emit_set_insn (lr, plus_constant (lr, -4));
11722 if (live_regs_mask)
11724 insn = emit_multi_reg_push (live_regs_mask);
11725 saved_regs += bit_count (live_regs_mask) * 4;
11726 RTX_FRAME_RELATED_P (insn) = 1;
11729 if (! IS_VOLATILE (func_type))
11730 saved_regs += arm_save_coproc_regs ();
11732 if (frame_pointer_needed && TARGET_ARM)
11734 /* Create the new frame pointer. */
11736 insn = GEN_INT (-(4 + args_to_push + fp_offset));
11737 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, ip_rtx, insn));
11738 RTX_FRAME_RELATED_P (insn) = 1;
11740 if (IS_NESTED (func_type))
11742 /* Recover the static chain register. */
11743 if (!df_regs_ever_live_p (3)
11744 || saved_pretend_args)
11745 insn = gen_rtx_REG (SImode, 3);
11746 else /* if (current_function_pretend_args_size == 0) */
11748 insn = plus_constant (hard_frame_pointer_rtx, 4);
11749 insn = gen_frame_mem (SImode, insn);
11751 emit_set_insn (ip_rtx, insn);
11752 /* Add a USE to stop propagate_one_insn() from barfing. */
11753 emit_insn (gen_prologue_use (ip_rtx));
11758 offsets = arm_get_frame_offsets ();
11759 if (offsets->outgoing_args != offsets->saved_args + saved_regs)
11761 /* This add can produce multiple insns for a large constant, so we
11762 need to get tricky. */
11763 rtx last = get_last_insn ();
11765 amount = GEN_INT (offsets->saved_args + saved_regs
11766 - offsets->outgoing_args);
11768 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
11772 last = last ? NEXT_INSN (last) : get_insns ();
11773 RTX_FRAME_RELATED_P (last) = 1;
11775 while (last != insn);
11777 /* If the frame pointer is needed, emit a special barrier that
11778 will prevent the scheduler from moving stores to the frame
11779 before the stack adjustment. */
11780 if (frame_pointer_needed)
11781 insn = emit_insn (gen_stack_tie (stack_pointer_rtx,
11782 hard_frame_pointer_rtx));
11786 if (frame_pointer_needed && TARGET_THUMB2)
11787 thumb_set_frame_pointer (offsets);
11789 if (flag_pic && arm_pic_register != INVALID_REGNUM)
11791 unsigned long mask;
11793 mask = live_regs_mask;
11794 mask &= THUMB2_WORK_REGS;
11795 if (!IS_NESTED (func_type))
11796 mask |= (1 << IP_REGNUM);
11797 arm_load_pic_register (mask);
11800 /* If we are profiling, make sure no instructions are scheduled before
11801 the call to mcount. Similarly if the user has requested no
11802 scheduling in the prolog. Similarly if we want non-call exceptions
11803 using the EABI unwinder, to prevent faulting instructions from being
11804 swapped with a stack adjustment. */
11805 if (current_function_profile || !TARGET_SCHED_PROLOG
11806 || (ARM_EABI_UNWIND_TABLES && flag_non_call_exceptions))
11807 emit_insn (gen_blockage ());
11809 /* If the link register is being kept alive, with the return address in it,
11810 then make sure that it does not get reused by the ce2 pass. */
11811 if ((live_regs_mask & (1 << LR_REGNUM)) == 0)
11812 cfun->machine->lr_save_eliminated = 1;
11815 /* Print condition code to STREAM. Helper function for arm_print_operand. */
11817 arm_print_condition (FILE *stream)
11819 if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4)
11821 /* Branch conversion is not implemented for Thumb-2. */
11824 output_operand_lossage ("predicated Thumb instruction");
11827 if (current_insn_predicate != NULL)
11829 output_operand_lossage
11830 ("predicated instruction in conditional sequence");
11834 fputs (arm_condition_codes[arm_current_cc], stream);
11836 else if (current_insn_predicate)
11838 enum arm_cond_code code;
11842 output_operand_lossage ("predicated Thumb instruction");
11846 code = get_arm_condition_code (current_insn_predicate);
11847 fputs (arm_condition_codes[code], stream);
11852 /* If CODE is 'd', then the X is a condition operand and the instruction
11853 should only be executed if the condition is true.
11854 if CODE is 'D', then the X is a condition operand and the instruction
11855 should only be executed if the condition is false: however, if the mode
11856 of the comparison is CCFPEmode, then always execute the instruction -- we
11857 do this because in these circumstances !GE does not necessarily imply LT;
11858 in these cases the instruction pattern will take care to make sure that
11859 an instruction containing %d will follow, thereby undoing the effects of
11860 doing this instruction unconditionally.
11861 If CODE is 'N' then X is a floating point operand that must be negated
11863 If CODE is 'B' then output a bitwise inverted value of X (a const int).
11864 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
11866 arm_print_operand (FILE *stream, rtx x, int code)
11871 fputs (ASM_COMMENT_START, stream);
11875 fputs (user_label_prefix, stream);
11879 fputs (REGISTER_PREFIX, stream);
11883 arm_print_condition (stream);
11887 /* Nothing in unified syntax, otherwise the current condition code. */
11888 if (!TARGET_UNIFIED_ASM)
11889 arm_print_condition (stream);
11893 /* The current condition code in unified syntax, otherwise nothing. */
11894 if (TARGET_UNIFIED_ASM)
11895 arm_print_condition (stream);
11899 /* The current condition code for a condition code setting instruction.
11900 Preceded by 's' in unified syntax, otherwise followed by 's'. */
11901 if (TARGET_UNIFIED_ASM)
11903 fputc('s', stream);
11904 arm_print_condition (stream);
11908 arm_print_condition (stream);
11909 fputc('s', stream);
11914 /* If the instruction is conditionally executed then print
11915 the current condition code, otherwise print 's'. */
11916 gcc_assert (TARGET_THUMB2 && TARGET_UNIFIED_ASM);
11917 if (current_insn_predicate)
11918 arm_print_condition (stream);
11920 fputc('s', stream);
11926 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
11927 r = REAL_VALUE_NEGATE (r);
11928 fprintf (stream, "%s", fp_const_from_val (&r));
11933 if (GET_CODE (x) == CONST_INT)
11936 val = ARM_SIGN_EXTEND (~INTVAL (x));
11937 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val);
11941 putc ('~', stream);
11942 output_addr_const (stream, x);
11947 /* The low 16 bits of an immediate constant. */
11948 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL(x) & 0xffff);
11952 fprintf (stream, "%s", arithmetic_instr (x, 1));
11955 /* Truncate Cirrus shift counts. */
11957 if (GET_CODE (x) == CONST_INT)
11959 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0x3f);
11962 arm_print_operand (stream, x, 0);
11966 fprintf (stream, "%s", arithmetic_instr (x, 0));
11974 if (!shift_operator (x, SImode))
11976 output_operand_lossage ("invalid shift operand");
11980 shift = shift_op (x, &val);
11984 fprintf (stream, ", %s ", shift);
11986 arm_print_operand (stream, XEXP (x, 1), 0);
11988 fprintf (stream, "#" HOST_WIDE_INT_PRINT_DEC, val);
11993 /* An explanation of the 'Q', 'R' and 'H' register operands:
11995 In a pair of registers containing a DI or DF value the 'Q'
11996 operand returns the register number of the register containing
11997 the least significant part of the value. The 'R' operand returns
11998 the register number of the register containing the most
11999 significant part of the value.
12001 The 'H' operand returns the higher of the two register numbers.
12002 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
12003 same as the 'Q' operand, since the most significant part of the
12004 value is held in the lower number register. The reverse is true
12005 on systems where WORDS_BIG_ENDIAN is false.
12007 The purpose of these operands is to distinguish between cases
12008 where the endian-ness of the values is important (for example
12009 when they are added together), and cases where the endian-ness
12010 is irrelevant, but the order of register operations is important.
12011 For example when loading a value from memory into a register
12012 pair, the endian-ness does not matter. Provided that the value
12013 from the lower memory address is put into the lower numbered
12014 register, and the value from the higher address is put into the
12015 higher numbered register, the load will work regardless of whether
12016 the value being loaded is big-wordian or little-wordian. The
12017 order of the two register loads can matter however, if the address
12018 of the memory location is actually held in one of the registers
12019 being overwritten by the load. */
12021 if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM)
12023 output_operand_lossage ("invalid operand for code '%c'", code);
12027 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0));
12031 if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM)
12033 output_operand_lossage ("invalid operand for code '%c'", code);
12037 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1));
12041 if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM)
12043 output_operand_lossage ("invalid operand for code '%c'", code);
12047 asm_fprintf (stream, "%r", REGNO (x) + 1);
12051 asm_fprintf (stream, "%r",
12052 GET_CODE (XEXP (x, 0)) == REG
12053 ? REGNO (XEXP (x, 0)) : REGNO (XEXP (XEXP (x, 0), 0)));
12057 asm_fprintf (stream, "{%r-%r}",
12059 REGNO (x) + ARM_NUM_REGS (GET_MODE (x)) - 1);
12063 /* CONST_TRUE_RTX means always -- that's the default. */
12064 if (x == const_true_rtx)
12067 if (!COMPARISON_P (x))
12069 output_operand_lossage ("invalid operand for code '%c'", code);
12073 fputs (arm_condition_codes[get_arm_condition_code (x)],
12078 /* CONST_TRUE_RTX means not always -- i.e. never. We shouldn't ever
12079 want to do that. */
12080 if (x == const_true_rtx)
12082 output_operand_lossage ("instruction never executed");
12085 if (!COMPARISON_P (x))
12087 output_operand_lossage ("invalid operand for code '%c'", code);
12091 fputs (arm_condition_codes[ARM_INVERSE_CONDITION_CODE
12092 (get_arm_condition_code (x))],
12096 /* Cirrus registers can be accessed in a variety of ways:
12097 single floating point (f)
12098 double floating point (d)
12100 64bit integer (dx). */
12101 case 'W': /* Cirrus register in F mode. */
12102 case 'X': /* Cirrus register in D mode. */
12103 case 'Y': /* Cirrus register in FX mode. */
12104 case 'Z': /* Cirrus register in DX mode. */
12105 gcc_assert (GET_CODE (x) == REG
12106 && REGNO_REG_CLASS (REGNO (x)) == CIRRUS_REGS);
12108 fprintf (stream, "mv%s%s",
12110 : code == 'X' ? "d"
12111 : code == 'Y' ? "fx" : "dx", reg_names[REGNO (x)] + 2);
12115 /* Print cirrus register in the mode specified by the register's mode. */
12118 int mode = GET_MODE (x);
12120 if (GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) != CIRRUS_REGS)
12122 output_operand_lossage ("invalid operand for code '%c'", code);
12126 fprintf (stream, "mv%s%s",
12127 mode == DFmode ? "d"
12128 : mode == SImode ? "fx"
12129 : mode == DImode ? "dx"
12130 : "f", reg_names[REGNO (x)] + 2);
12136 if (GET_CODE (x) != REG
12137 || REGNO (x) < FIRST_IWMMXT_GR_REGNUM
12138 || REGNO (x) > LAST_IWMMXT_GR_REGNUM)
12139 /* Bad value for wCG register number. */
12141 output_operand_lossage ("invalid operand for code '%c'", code);
12146 fprintf (stream, "%d", REGNO (x) - FIRST_IWMMXT_GR_REGNUM);
12149 /* Print an iWMMXt control register name. */
12151 if (GET_CODE (x) != CONST_INT
12153 || INTVAL (x) >= 16)
12154 /* Bad value for wC register number. */
12156 output_operand_lossage ("invalid operand for code '%c'", code);
12162 static const char * wc_reg_names [16] =
12164 "wCID", "wCon", "wCSSF", "wCASF",
12165 "wC4", "wC5", "wC6", "wC7",
12166 "wCGR0", "wCGR1", "wCGR2", "wCGR3",
12167 "wC12", "wC13", "wC14", "wC15"
12170 fprintf (stream, wc_reg_names [INTVAL (x)]);
12174 /* Print a VFP double precision register name. */
12177 int mode = GET_MODE (x);
12180 if (mode != DImode && mode != DFmode)
12182 output_operand_lossage ("invalid operand for code '%c'", code);
12186 if (GET_CODE (x) != REG
12187 || !IS_VFP_REGNUM (REGNO (x)))
12189 output_operand_lossage ("invalid operand for code '%c'", code);
12193 num = REGNO(x) - FIRST_VFP_REGNUM;
12196 output_operand_lossage ("invalid operand for code '%c'", code);
12200 fprintf (stream, "d%d", num >> 1);
12204 /* Print a VFPv3 floating-point constant, represented as an integer
12208 int index = vfp3_const_double_index (x);
12209 gcc_assert (index != -1);
12210 fprintf (stream, "%d", index);
12217 output_operand_lossage ("missing operand");
12221 switch (GET_CODE (x))
12224 asm_fprintf (stream, "%r", REGNO (x));
12228 output_memory_reference_mode = GET_MODE (x);
12229 output_address (XEXP (x, 0));
12233 fprintf (stream, "#%s", fp_immediate_constant (x));
12237 gcc_assert (GET_CODE (x) != NEG);
12238 fputc ('#', stream);
12239 output_addr_const (stream, x);
12245 #ifndef AOF_ASSEMBLER
12246 /* Target hook for assembling integer objects. The ARM version needs to
12247 handle word-sized values specially. */
12249 arm_assemble_integer (rtx x, unsigned int size, int aligned_p)
12251 if (size == UNITS_PER_WORD && aligned_p)
12253 fputs ("\t.word\t", asm_out_file);
12254 output_addr_const (asm_out_file, x);
12256 /* Mark symbols as position independent. We only do this in the
12257 .text segment, not in the .data segment. */
12258 if (NEED_GOT_RELOC && flag_pic && making_const_table &&
12259 (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF))
12261 /* See legitimize_pic_address for an explanation of the
12262 TARGET_VXWORKS_RTP check. */
12263 if (TARGET_VXWORKS_RTP
12264 || (GET_CODE (x) == SYMBOL_REF && !SYMBOL_REF_LOCAL_P (x)))
12265 fputs ("(GOT)", asm_out_file);
12267 fputs ("(GOTOFF)", asm_out_file);
12269 fputc ('\n', asm_out_file);
12273 if (arm_vector_mode_supported_p (GET_MODE (x)))
12277 gcc_assert (GET_CODE (x) == CONST_VECTOR);
12279 units = CONST_VECTOR_NUNITS (x);
12281 switch (GET_MODE (x))
12283 case V2SImode: size = 4; break;
12284 case V4HImode: size = 2; break;
12285 case V8QImode: size = 1; break;
12287 gcc_unreachable ();
12290 for (i = 0; i < units; i++)
12294 elt = CONST_VECTOR_ELT (x, i);
12296 (elt, size, i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT, 1);
12302 return default_assemble_integer (x, size, aligned_p);
12306 arm_elf_asm_cdtor (rtx symbol, int priority, bool is_ctor)
12310 if (!TARGET_AAPCS_BASED)
12313 default_named_section_asm_out_constructor
12314 : default_named_section_asm_out_destructor) (symbol, priority);
12318 /* Put these in the .init_array section, using a special relocation. */
12319 if (priority != DEFAULT_INIT_PRIORITY)
12322 sprintf (buf, "%s.%.5u",
12323 is_ctor ? ".init_array" : ".fini_array",
12325 s = get_section (buf, SECTION_WRITE, NULL_TREE);
12332 switch_to_section (s);
12333 assemble_align (POINTER_SIZE);
12334 fputs ("\t.word\t", asm_out_file);
12335 output_addr_const (asm_out_file, symbol);
12336 fputs ("(target1)\n", asm_out_file);
12339 /* Add a function to the list of static constructors. */
12342 arm_elf_asm_constructor (rtx symbol, int priority)
12344 arm_elf_asm_cdtor (symbol, priority, /*is_ctor=*/true);
12347 /* Add a function to the list of static destructors. */
12350 arm_elf_asm_destructor (rtx symbol, int priority)
12352 arm_elf_asm_cdtor (symbol, priority, /*is_ctor=*/false);
12356 /* A finite state machine takes care of noticing whether or not instructions
12357 can be conditionally executed, and thus decrease execution time and code
12358 size by deleting branch instructions. The fsm is controlled by
12359 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
12361 /* The state of the fsm controlling condition codes are:
12362 0: normal, do nothing special
12363 1: make ASM_OUTPUT_OPCODE not output this instruction
12364 2: make ASM_OUTPUT_OPCODE not output this instruction
12365 3: make instructions conditional
12366 4: make instructions conditional
12368 State transitions (state->state by whom under condition):
12369 0 -> 1 final_prescan_insn if the `target' is a label
12370 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
12371 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
12372 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
12373 3 -> 0 (*targetm.asm_out.internal_label) if the `target' label is reached
12374 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
12375 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
12376 (the target insn is arm_target_insn).
12378 If the jump clobbers the conditions then we use states 2 and 4.
12380 A similar thing can be done with conditional return insns.
12382 XXX In case the `target' is an unconditional branch, this conditionalising
12383 of the instructions always reduces code size, but not always execution
12384 time. But then, I want to reduce the code size to somewhere near what
12385 /bin/cc produces. */
12387 /* In addition to this, state is maintained for Thumb-2 COND_EXEC
12388 instructions. When a COND_EXEC instruction is seen the subsequent
12389 instructions are scanned so that multiple conditional instructions can be
12390 combined into a single IT block. arm_condexec_count and arm_condexec_mask
12391 specify the length and true/false mask for the IT block. These will be
12392 decremented/zeroed by arm_asm_output_opcode as the insns are output. */
12394 /* Returns the index of the ARM condition code string in
12395 `arm_condition_codes'. COMPARISON should be an rtx like
12396 `(eq (...) (...))'. */
12397 static enum arm_cond_code
12398 get_arm_condition_code (rtx comparison)
12400 enum machine_mode mode = GET_MODE (XEXP (comparison, 0));
12402 enum rtx_code comp_code = GET_CODE (comparison);
12404 if (GET_MODE_CLASS (mode) != MODE_CC)
12405 mode = SELECT_CC_MODE (comp_code, XEXP (comparison, 0),
12406 XEXP (comparison, 1));
12410 case CC_DNEmode: code = ARM_NE; goto dominance;
12411 case CC_DEQmode: code = ARM_EQ; goto dominance;
12412 case CC_DGEmode: code = ARM_GE; goto dominance;
12413 case CC_DGTmode: code = ARM_GT; goto dominance;
12414 case CC_DLEmode: code = ARM_LE; goto dominance;
12415 case CC_DLTmode: code = ARM_LT; goto dominance;
12416 case CC_DGEUmode: code = ARM_CS; goto dominance;
12417 case CC_DGTUmode: code = ARM_HI; goto dominance;
12418 case CC_DLEUmode: code = ARM_LS; goto dominance;
12419 case CC_DLTUmode: code = ARM_CC;
12422 gcc_assert (comp_code == EQ || comp_code == NE);
12424 if (comp_code == EQ)
12425 return ARM_INVERSE_CONDITION_CODE (code);
12431 case NE: return ARM_NE;
12432 case EQ: return ARM_EQ;
12433 case GE: return ARM_PL;
12434 case LT: return ARM_MI;
12435 default: gcc_unreachable ();
12441 case NE: return ARM_NE;
12442 case EQ: return ARM_EQ;
12443 default: gcc_unreachable ();
12449 case NE: return ARM_MI;
12450 case EQ: return ARM_PL;
12451 default: gcc_unreachable ();
12456 /* These encodings assume that AC=1 in the FPA system control
12457 byte. This allows us to handle all cases except UNEQ and
12461 case GE: return ARM_GE;
12462 case GT: return ARM_GT;
12463 case LE: return ARM_LS;
12464 case LT: return ARM_MI;
12465 case NE: return ARM_NE;
12466 case EQ: return ARM_EQ;
12467 case ORDERED: return ARM_VC;
12468 case UNORDERED: return ARM_VS;
12469 case UNLT: return ARM_LT;
12470 case UNLE: return ARM_LE;
12471 case UNGT: return ARM_HI;
12472 case UNGE: return ARM_PL;
12473 /* UNEQ and LTGT do not have a representation. */
12474 case UNEQ: /* Fall through. */
12475 case LTGT: /* Fall through. */
12476 default: gcc_unreachable ();
12482 case NE: return ARM_NE;
12483 case EQ: return ARM_EQ;
12484 case GE: return ARM_LE;
12485 case GT: return ARM_LT;
12486 case LE: return ARM_GE;
12487 case LT: return ARM_GT;
12488 case GEU: return ARM_LS;
12489 case GTU: return ARM_CC;
12490 case LEU: return ARM_CS;
12491 case LTU: return ARM_HI;
12492 default: gcc_unreachable ();
12498 case LTU: return ARM_CS;
12499 case GEU: return ARM_CC;
12500 default: gcc_unreachable ();
12506 case NE: return ARM_NE;
12507 case EQ: return ARM_EQ;
12508 case GE: return ARM_GE;
12509 case GT: return ARM_GT;
12510 case LE: return ARM_LE;
12511 case LT: return ARM_LT;
12512 case GEU: return ARM_CS;
12513 case GTU: return ARM_HI;
12514 case LEU: return ARM_LS;
12515 case LTU: return ARM_CC;
12516 default: gcc_unreachable ();
12519 default: gcc_unreachable ();
12523 /* Tell arm_asm_output_opcode to output IT blocks for conditionally executed
12526 thumb2_final_prescan_insn (rtx insn)
12528 rtx first_insn = insn;
12529 rtx body = PATTERN (insn);
12531 enum arm_cond_code code;
12535 /* Remove the previous insn from the count of insns to be output. */
12536 if (arm_condexec_count)
12537 arm_condexec_count--;
12539 /* Nothing to do if we are already inside a conditional block. */
12540 if (arm_condexec_count)
12543 if (GET_CODE (body) != COND_EXEC)
12546 /* Conditional jumps are implemented directly. */
12547 if (GET_CODE (insn) == JUMP_INSN)
12550 predicate = COND_EXEC_TEST (body);
12551 arm_current_cc = get_arm_condition_code (predicate);
12553 n = get_attr_ce_count (insn);
12554 arm_condexec_count = 1;
12555 arm_condexec_mask = (1 << n) - 1;
12556 arm_condexec_masklen = n;
12557 /* See if subsequent instructions can be combined into the same block. */
12560 insn = next_nonnote_insn (insn);
12562 /* Jumping into the middle of an IT block is illegal, so a label or
12563 barrier terminates the block. */
12564 if (GET_CODE (insn) != INSN && GET_CODE(insn) != JUMP_INSN)
12567 body = PATTERN (insn);
12568 /* USE and CLOBBER aren't really insns, so just skip them. */
12569 if (GET_CODE (body) == USE
12570 || GET_CODE (body) == CLOBBER)
12573 /* ??? Recognize conditional jumps, and combine them with IT blocks. */
12574 if (GET_CODE (body) != COND_EXEC)
12576 /* Allow up to 4 conditionally executed instructions in a block. */
12577 n = get_attr_ce_count (insn);
12578 if (arm_condexec_masklen + n > 4)
12581 predicate = COND_EXEC_TEST (body);
12582 code = get_arm_condition_code (predicate);
12583 mask = (1 << n) - 1;
12584 if (arm_current_cc == code)
12585 arm_condexec_mask |= (mask << arm_condexec_masklen);
12586 else if (arm_current_cc != ARM_INVERSE_CONDITION_CODE(code))
12589 arm_condexec_count++;
12590 arm_condexec_masklen += n;
12592 /* A jump must be the last instruction in a conditional block. */
12593 if (GET_CODE(insn) == JUMP_INSN)
12596 /* Restore recog_data (getting the attributes of other insns can
12597 destroy this array, but final.c assumes that it remains intact
12598 across this call). */
12599 extract_constrain_insn_cached (first_insn);
12603 arm_final_prescan_insn (rtx insn)
12605 /* BODY will hold the body of INSN. */
12606 rtx body = PATTERN (insn);
12608 /* This will be 1 if trying to repeat the trick, and things need to be
12609 reversed if it appears to fail. */
12612 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
12613 taken are clobbered, even if the rtl suggests otherwise. It also
12614 means that we have to grub around within the jump expression to find
12615 out what the conditions are when the jump isn't taken. */
12616 int jump_clobbers = 0;
12618 /* If we start with a return insn, we only succeed if we find another one. */
12619 int seeking_return = 0;
12621 /* START_INSN will hold the insn from where we start looking. This is the
12622 first insn after the following code_label if REVERSE is true. */
12623 rtx start_insn = insn;
12625 /* If in state 4, check if the target branch is reached, in order to
12626 change back to state 0. */
12627 if (arm_ccfsm_state == 4)
12629 if (insn == arm_target_insn)
12631 arm_target_insn = NULL;
12632 arm_ccfsm_state = 0;
12637 /* If in state 3, it is possible to repeat the trick, if this insn is an
12638 unconditional branch to a label, and immediately following this branch
12639 is the previous target label which is only used once, and the label this
12640 branch jumps to is not too far off. */
12641 if (arm_ccfsm_state == 3)
12643 if (simplejump_p (insn))
12645 start_insn = next_nonnote_insn (start_insn);
12646 if (GET_CODE (start_insn) == BARRIER)
12648 /* XXX Isn't this always a barrier? */
12649 start_insn = next_nonnote_insn (start_insn);
12651 if (GET_CODE (start_insn) == CODE_LABEL
12652 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
12653 && LABEL_NUSES (start_insn) == 1)
12658 else if (GET_CODE (body) == RETURN)
12660 start_insn = next_nonnote_insn (start_insn);
12661 if (GET_CODE (start_insn) == BARRIER)
12662 start_insn = next_nonnote_insn (start_insn);
12663 if (GET_CODE (start_insn) == CODE_LABEL
12664 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
12665 && LABEL_NUSES (start_insn) == 1)
12668 seeking_return = 1;
12677 gcc_assert (!arm_ccfsm_state || reverse);
12678 if (GET_CODE (insn) != JUMP_INSN)
12681 /* This jump might be paralleled with a clobber of the condition codes
12682 the jump should always come first */
12683 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
12684 body = XVECEXP (body, 0, 0);
12687 || (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
12688 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE))
12691 int fail = FALSE, succeed = FALSE;
12692 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
12693 int then_not_else = TRUE;
12694 rtx this_insn = start_insn, label = 0;
12696 /* If the jump cannot be done with one instruction, we cannot
12697 conditionally execute the instruction in the inverse case. */
12698 if (get_attr_conds (insn) == CONDS_JUMP_CLOB)
12704 /* Register the insn jumped to. */
12707 if (!seeking_return)
12708 label = XEXP (SET_SRC (body), 0);
12710 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == LABEL_REF)
12711 label = XEXP (XEXP (SET_SRC (body), 1), 0);
12712 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == LABEL_REF)
12714 label = XEXP (XEXP (SET_SRC (body), 2), 0);
12715 then_not_else = FALSE;
12717 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN)
12718 seeking_return = 1;
12719 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN)
12721 seeking_return = 1;
12722 then_not_else = FALSE;
12725 gcc_unreachable ();
12727 /* See how many insns this branch skips, and what kind of insns. If all
12728 insns are okay, and the label or unconditional branch to the same
12729 label is not too far away, succeed. */
12730 for (insns_skipped = 0;
12731 !fail && !succeed && insns_skipped++ < max_insns_skipped;)
12735 this_insn = next_nonnote_insn (this_insn);
12739 switch (GET_CODE (this_insn))
12742 /* Succeed if it is the target label, otherwise fail since
12743 control falls in from somewhere else. */
12744 if (this_insn == label)
12748 arm_ccfsm_state = 2;
12749 this_insn = next_nonnote_insn (this_insn);
12752 arm_ccfsm_state = 1;
12760 /* Succeed if the following insn is the target label.
12762 If return insns are used then the last insn in a function
12763 will be a barrier. */
12764 this_insn = next_nonnote_insn (this_insn);
12765 if (this_insn && this_insn == label)
12769 arm_ccfsm_state = 2;
12770 this_insn = next_nonnote_insn (this_insn);
12773 arm_ccfsm_state = 1;
12781 /* The AAPCS says that conditional calls should not be
12782 used since they make interworking inefficient (the
12783 linker can't transform BL<cond> into BLX). That's
12784 only a problem if the machine has BLX. */
12791 /* Succeed if the following insn is the target label, or
12792 if the following two insns are a barrier and the
12794 this_insn = next_nonnote_insn (this_insn);
12795 if (this_insn && GET_CODE (this_insn) == BARRIER)
12796 this_insn = next_nonnote_insn (this_insn);
12798 if (this_insn && this_insn == label
12799 && insns_skipped < max_insns_skipped)
12803 arm_ccfsm_state = 2;
12804 this_insn = next_nonnote_insn (this_insn);
12807 arm_ccfsm_state = 1;
12815 /* If this is an unconditional branch to the same label, succeed.
12816 If it is to another label, do nothing. If it is conditional,
12818 /* XXX Probably, the tests for SET and the PC are
12821 scanbody = PATTERN (this_insn);
12822 if (GET_CODE (scanbody) == SET
12823 && GET_CODE (SET_DEST (scanbody)) == PC)
12825 if (GET_CODE (SET_SRC (scanbody)) == LABEL_REF
12826 && XEXP (SET_SRC (scanbody), 0) == label && !reverse)
12828 arm_ccfsm_state = 2;
12831 else if (GET_CODE (SET_SRC (scanbody)) == IF_THEN_ELSE)
12834 /* Fail if a conditional return is undesirable (e.g. on a
12835 StrongARM), but still allow this if optimizing for size. */
12836 else if (GET_CODE (scanbody) == RETURN
12837 && !use_return_insn (TRUE, NULL)
12840 else if (GET_CODE (scanbody) == RETURN
12843 arm_ccfsm_state = 2;
12846 else if (GET_CODE (scanbody) == PARALLEL)
12848 switch (get_attr_conds (this_insn))
12858 fail = TRUE; /* Unrecognized jump (e.g. epilogue). */
12863 /* Instructions using or affecting the condition codes make it
12865 scanbody = PATTERN (this_insn);
12866 if (!(GET_CODE (scanbody) == SET
12867 || GET_CODE (scanbody) == PARALLEL)
12868 || get_attr_conds (this_insn) != CONDS_NOCOND)
12871 /* A conditional cirrus instruction must be followed by
12872 a non Cirrus instruction. However, since we
12873 conditionalize instructions in this function and by
12874 the time we get here we can't add instructions
12875 (nops), because shorten_branches() has already been
12876 called, we will disable conditionalizing Cirrus
12877 instructions to be safe. */
12878 if (GET_CODE (scanbody) != USE
12879 && GET_CODE (scanbody) != CLOBBER
12880 && get_attr_cirrus (this_insn) != CIRRUS_NOT)
12890 if ((!seeking_return) && (arm_ccfsm_state == 1 || reverse))
12891 arm_target_label = CODE_LABEL_NUMBER (label);
12894 gcc_assert (seeking_return || arm_ccfsm_state == 2);
12896 while (this_insn && GET_CODE (PATTERN (this_insn)) == USE)
12898 this_insn = next_nonnote_insn (this_insn);
12899 gcc_assert (!this_insn
12900 || (GET_CODE (this_insn) != BARRIER
12901 && GET_CODE (this_insn) != CODE_LABEL));
12905 /* Oh, dear! we ran off the end.. give up. */
12906 extract_constrain_insn_cached (insn);
12907 arm_ccfsm_state = 0;
12908 arm_target_insn = NULL;
12911 arm_target_insn = this_insn;
12915 gcc_assert (!reverse);
12917 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body),
12919 if (GET_CODE (XEXP (XEXP (SET_SRC (body), 0), 0)) == AND)
12920 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
12921 if (GET_CODE (XEXP (SET_SRC (body), 0)) == NE)
12922 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
12926 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
12929 arm_current_cc = get_arm_condition_code (XEXP (SET_SRC (body),
12933 if (reverse || then_not_else)
12934 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
12937 /* Restore recog_data (getting the attributes of other insns can
12938 destroy this array, but final.c assumes that it remains intact
12939 across this call. */
12940 extract_constrain_insn_cached (insn);
12944 /* Output IT instructions. */
12946 thumb2_asm_output_opcode (FILE * stream)
12951 if (arm_condexec_mask)
12953 for (n = 0; n < arm_condexec_masklen; n++)
12954 buff[n] = (arm_condexec_mask & (1 << n)) ? 't' : 'e';
12956 asm_fprintf(stream, "i%s\t%s\n\t", buff,
12957 arm_condition_codes[arm_current_cc]);
12958 arm_condexec_mask = 0;
12962 /* Returns true if REGNO is a valid register
12963 for holding a quantity of type MODE. */
12965 arm_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
12967 if (GET_MODE_CLASS (mode) == MODE_CC)
12968 return (regno == CC_REGNUM
12969 || (TARGET_HARD_FLOAT && TARGET_VFP
12970 && regno == VFPCC_REGNUM));
12973 /* For the Thumb we only allow values bigger than SImode in
12974 registers 0 - 6, so that there is always a second low
12975 register available to hold the upper part of the value.
12976 We probably we ought to ensure that the register is the
12977 start of an even numbered register pair. */
12978 return (ARM_NUM_REGS (mode) < 2) || (regno < LAST_LO_REGNUM);
12980 if (TARGET_HARD_FLOAT && TARGET_MAVERICK
12981 && IS_CIRRUS_REGNUM (regno))
12982 /* We have outlawed SI values in Cirrus registers because they
12983 reside in the lower 32 bits, but SF values reside in the
12984 upper 32 bits. This causes gcc all sorts of grief. We can't
12985 even split the registers into pairs because Cirrus SI values
12986 get sign extended to 64bits-- aldyh. */
12987 return (GET_MODE_CLASS (mode) == MODE_FLOAT) || (mode == DImode);
12989 if (TARGET_HARD_FLOAT && TARGET_VFP
12990 && IS_VFP_REGNUM (regno))
12992 if (mode == SFmode || mode == SImode)
12993 return VFP_REGNO_OK_FOR_SINGLE (regno);
12995 if (mode == DFmode)
12996 return VFP_REGNO_OK_FOR_DOUBLE (regno);
13000 if (TARGET_REALLY_IWMMXT)
13002 if (IS_IWMMXT_GR_REGNUM (regno))
13003 return mode == SImode;
13005 if (IS_IWMMXT_REGNUM (regno))
13006 return VALID_IWMMXT_REG_MODE (mode);
13009 /* We allow any value to be stored in the general registers.
13010 Restrict doubleword quantities to even register pairs so that we can
13012 if (regno <= LAST_ARM_REGNUM)
13013 return !(TARGET_LDRD && GET_MODE_SIZE (mode) > 4 && (regno & 1) != 0);
13015 if (regno == FRAME_POINTER_REGNUM
13016 || regno == ARG_POINTER_REGNUM)
13017 /* We only allow integers in the fake hard registers. */
13018 return GET_MODE_CLASS (mode) == MODE_INT;
13020 /* The only registers left are the FPA registers
13021 which we only allow to hold FP values. */
13022 return (TARGET_HARD_FLOAT && TARGET_FPA
13023 && GET_MODE_CLASS (mode) == MODE_FLOAT
13024 && regno >= FIRST_FPA_REGNUM
13025 && regno <= LAST_FPA_REGNUM);
13028 /* For efficiency and historical reasons LO_REGS, HI_REGS and CC_REGS are
13029 not used in arm mode. */
13031 arm_regno_class (int regno)
13035 if (regno == STACK_POINTER_REGNUM)
13037 if (regno == CC_REGNUM)
13044 if (TARGET_THUMB2 && regno < 8)
13047 if ( regno <= LAST_ARM_REGNUM
13048 || regno == FRAME_POINTER_REGNUM
13049 || regno == ARG_POINTER_REGNUM)
13050 return TARGET_THUMB2 ? HI_REGS : GENERAL_REGS;
13052 if (regno == CC_REGNUM || regno == VFPCC_REGNUM)
13053 return TARGET_THUMB2 ? CC_REG : NO_REGS;
13055 if (IS_CIRRUS_REGNUM (regno))
13056 return CIRRUS_REGS;
13058 if (IS_VFP_REGNUM (regno))
13060 if (regno <= D7_VFP_REGNUM)
13061 return VFP_D0_D7_REGS;
13062 else if (regno <= LAST_LO_VFP_REGNUM)
13063 return VFP_LO_REGS;
13065 return VFP_HI_REGS;
13068 if (IS_IWMMXT_REGNUM (regno))
13069 return IWMMXT_REGS;
13071 if (IS_IWMMXT_GR_REGNUM (regno))
13072 return IWMMXT_GR_REGS;
13077 /* Handle a special case when computing the offset
13078 of an argument from the frame pointer. */
13080 arm_debugger_arg_offset (int value, rtx addr)
13084 /* We are only interested if dbxout_parms() failed to compute the offset. */
13088 /* We can only cope with the case where the address is held in a register. */
13089 if (GET_CODE (addr) != REG)
13092 /* If we are using the frame pointer to point at the argument, then
13093 an offset of 0 is correct. */
13094 if (REGNO (addr) == (unsigned) HARD_FRAME_POINTER_REGNUM)
13097 /* If we are using the stack pointer to point at the
13098 argument, then an offset of 0 is correct. */
13099 /* ??? Check this is consistent with thumb2 frame layout. */
13100 if ((TARGET_THUMB || !frame_pointer_needed)
13101 && REGNO (addr) == SP_REGNUM)
13104 /* Oh dear. The argument is pointed to by a register rather
13105 than being held in a register, or being stored at a known
13106 offset from the frame pointer. Since GDB only understands
13107 those two kinds of argument we must translate the address
13108 held in the register into an offset from the frame pointer.
13109 We do this by searching through the insns for the function
13110 looking to see where this register gets its value. If the
13111 register is initialized from the frame pointer plus an offset
13112 then we are in luck and we can continue, otherwise we give up.
13114 This code is exercised by producing debugging information
13115 for a function with arguments like this:
13117 double func (double a, double b, int c, double d) {return d;}
13119 Without this code the stab for parameter 'd' will be set to
13120 an offset of 0 from the frame pointer, rather than 8. */
13122 /* The if() statement says:
13124 If the insn is a normal instruction
13125 and if the insn is setting the value in a register
13126 and if the register being set is the register holding the address of the argument
13127 and if the address is computing by an addition
13128 that involves adding to a register
13129 which is the frame pointer
13134 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
13136 if ( GET_CODE (insn) == INSN
13137 && GET_CODE (PATTERN (insn)) == SET
13138 && REGNO (XEXP (PATTERN (insn), 0)) == REGNO (addr)
13139 && GET_CODE (XEXP (PATTERN (insn), 1)) == PLUS
13140 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 0)) == REG
13141 && REGNO (XEXP (XEXP (PATTERN (insn), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
13142 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 1)) == CONST_INT
13145 value = INTVAL (XEXP (XEXP (PATTERN (insn), 1), 1));
13154 warning (0, "unable to compute real location of stacked parameter");
13155 value = 8; /* XXX magic hack */
13161 #define def_mbuiltin(MASK, NAME, TYPE, CODE) \
13164 if ((MASK) & insn_flags) \
13165 add_builtin_function ((NAME), (TYPE), (CODE), \
13166 BUILT_IN_MD, NULL, NULL_TREE); \
13170 struct builtin_description
13172 const unsigned int mask;
13173 const enum insn_code icode;
13174 const char * const name;
13175 const enum arm_builtins code;
13176 const enum rtx_code comparison;
13177 const unsigned int flag;
13180 static const struct builtin_description bdesc_2arg[] =
13182 #define IWMMXT_BUILTIN(code, string, builtin) \
13183 { FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \
13184 ARM_BUILTIN_##builtin, 0, 0 },
13186 IWMMXT_BUILTIN (addv8qi3, "waddb", WADDB)
13187 IWMMXT_BUILTIN (addv4hi3, "waddh", WADDH)
13188 IWMMXT_BUILTIN (addv2si3, "waddw", WADDW)
13189 IWMMXT_BUILTIN (subv8qi3, "wsubb", WSUBB)
13190 IWMMXT_BUILTIN (subv4hi3, "wsubh", WSUBH)
13191 IWMMXT_BUILTIN (subv2si3, "wsubw", WSUBW)
13192 IWMMXT_BUILTIN (ssaddv8qi3, "waddbss", WADDSSB)
13193 IWMMXT_BUILTIN (ssaddv4hi3, "waddhss", WADDSSH)
13194 IWMMXT_BUILTIN (ssaddv2si3, "waddwss", WADDSSW)
13195 IWMMXT_BUILTIN (sssubv8qi3, "wsubbss", WSUBSSB)
13196 IWMMXT_BUILTIN (sssubv4hi3, "wsubhss", WSUBSSH)
13197 IWMMXT_BUILTIN (sssubv2si3, "wsubwss", WSUBSSW)
13198 IWMMXT_BUILTIN (usaddv8qi3, "waddbus", WADDUSB)
13199 IWMMXT_BUILTIN (usaddv4hi3, "waddhus", WADDUSH)
13200 IWMMXT_BUILTIN (usaddv2si3, "waddwus", WADDUSW)
13201 IWMMXT_BUILTIN (ussubv8qi3, "wsubbus", WSUBUSB)
13202 IWMMXT_BUILTIN (ussubv4hi3, "wsubhus", WSUBUSH)
13203 IWMMXT_BUILTIN (ussubv2si3, "wsubwus", WSUBUSW)
13204 IWMMXT_BUILTIN (mulv4hi3, "wmulul", WMULUL)
13205 IWMMXT_BUILTIN (smulv4hi3_highpart, "wmulsm", WMULSM)
13206 IWMMXT_BUILTIN (umulv4hi3_highpart, "wmulum", WMULUM)
13207 IWMMXT_BUILTIN (eqv8qi3, "wcmpeqb", WCMPEQB)
13208 IWMMXT_BUILTIN (eqv4hi3, "wcmpeqh", WCMPEQH)
13209 IWMMXT_BUILTIN (eqv2si3, "wcmpeqw", WCMPEQW)
13210 IWMMXT_BUILTIN (gtuv8qi3, "wcmpgtub", WCMPGTUB)
13211 IWMMXT_BUILTIN (gtuv4hi3, "wcmpgtuh", WCMPGTUH)
13212 IWMMXT_BUILTIN (gtuv2si3, "wcmpgtuw", WCMPGTUW)
13213 IWMMXT_BUILTIN (gtv8qi3, "wcmpgtsb", WCMPGTSB)
13214 IWMMXT_BUILTIN (gtv4hi3, "wcmpgtsh", WCMPGTSH)
13215 IWMMXT_BUILTIN (gtv2si3, "wcmpgtsw", WCMPGTSW)
13216 IWMMXT_BUILTIN (umaxv8qi3, "wmaxub", WMAXUB)
13217 IWMMXT_BUILTIN (smaxv8qi3, "wmaxsb", WMAXSB)
13218 IWMMXT_BUILTIN (umaxv4hi3, "wmaxuh", WMAXUH)
13219 IWMMXT_BUILTIN (smaxv4hi3, "wmaxsh", WMAXSH)
13220 IWMMXT_BUILTIN (umaxv2si3, "wmaxuw", WMAXUW)
13221 IWMMXT_BUILTIN (smaxv2si3, "wmaxsw", WMAXSW)
13222 IWMMXT_BUILTIN (uminv8qi3, "wminub", WMINUB)
13223 IWMMXT_BUILTIN (sminv8qi3, "wminsb", WMINSB)
13224 IWMMXT_BUILTIN (uminv4hi3, "wminuh", WMINUH)
13225 IWMMXT_BUILTIN (sminv4hi3, "wminsh", WMINSH)
13226 IWMMXT_BUILTIN (uminv2si3, "wminuw", WMINUW)
13227 IWMMXT_BUILTIN (sminv2si3, "wminsw", WMINSW)
13228 IWMMXT_BUILTIN (iwmmxt_anddi3, "wand", WAND)
13229 IWMMXT_BUILTIN (iwmmxt_nanddi3, "wandn", WANDN)
13230 IWMMXT_BUILTIN (iwmmxt_iordi3, "wor", WOR)
13231 IWMMXT_BUILTIN (iwmmxt_xordi3, "wxor", WXOR)
13232 IWMMXT_BUILTIN (iwmmxt_uavgv8qi3, "wavg2b", WAVG2B)
13233 IWMMXT_BUILTIN (iwmmxt_uavgv4hi3, "wavg2h", WAVG2H)
13234 IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3, "wavg2br", WAVG2BR)
13235 IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3, "wavg2hr", WAVG2HR)
13236 IWMMXT_BUILTIN (iwmmxt_wunpckilb, "wunpckilb", WUNPCKILB)
13237 IWMMXT_BUILTIN (iwmmxt_wunpckilh, "wunpckilh", WUNPCKILH)
13238 IWMMXT_BUILTIN (iwmmxt_wunpckilw, "wunpckilw", WUNPCKILW)
13239 IWMMXT_BUILTIN (iwmmxt_wunpckihb, "wunpckihb", WUNPCKIHB)
13240 IWMMXT_BUILTIN (iwmmxt_wunpckihh, "wunpckihh", WUNPCKIHH)
13241 IWMMXT_BUILTIN (iwmmxt_wunpckihw, "wunpckihw", WUNPCKIHW)
13242 IWMMXT_BUILTIN (iwmmxt_wmadds, "wmadds", WMADDS)
13243 IWMMXT_BUILTIN (iwmmxt_wmaddu, "wmaddu", WMADDU)
13245 #define IWMMXT_BUILTIN2(code, builtin) \
13246 { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, 0, 0 },
13248 IWMMXT_BUILTIN2 (iwmmxt_wpackhss, WPACKHSS)
13249 IWMMXT_BUILTIN2 (iwmmxt_wpackwss, WPACKWSS)
13250 IWMMXT_BUILTIN2 (iwmmxt_wpackdss, WPACKDSS)
13251 IWMMXT_BUILTIN2 (iwmmxt_wpackhus, WPACKHUS)
13252 IWMMXT_BUILTIN2 (iwmmxt_wpackwus, WPACKWUS)
13253 IWMMXT_BUILTIN2 (iwmmxt_wpackdus, WPACKDUS)
13254 IWMMXT_BUILTIN2 (ashlv4hi3_di, WSLLH)
13255 IWMMXT_BUILTIN2 (ashlv4hi3, WSLLHI)
13256 IWMMXT_BUILTIN2 (ashlv2si3_di, WSLLW)
13257 IWMMXT_BUILTIN2 (ashlv2si3, WSLLWI)
13258 IWMMXT_BUILTIN2 (ashldi3_di, WSLLD)
13259 IWMMXT_BUILTIN2 (ashldi3_iwmmxt, WSLLDI)
13260 IWMMXT_BUILTIN2 (lshrv4hi3_di, WSRLH)
13261 IWMMXT_BUILTIN2 (lshrv4hi3, WSRLHI)
13262 IWMMXT_BUILTIN2 (lshrv2si3_di, WSRLW)
13263 IWMMXT_BUILTIN2 (lshrv2si3, WSRLWI)
13264 IWMMXT_BUILTIN2 (lshrdi3_di, WSRLD)
13265 IWMMXT_BUILTIN2 (lshrdi3_iwmmxt, WSRLDI)
13266 IWMMXT_BUILTIN2 (ashrv4hi3_di, WSRAH)
13267 IWMMXT_BUILTIN2 (ashrv4hi3, WSRAHI)
13268 IWMMXT_BUILTIN2 (ashrv2si3_di, WSRAW)
13269 IWMMXT_BUILTIN2 (ashrv2si3, WSRAWI)
13270 IWMMXT_BUILTIN2 (ashrdi3_di, WSRAD)
13271 IWMMXT_BUILTIN2 (ashrdi3_iwmmxt, WSRADI)
13272 IWMMXT_BUILTIN2 (rorv4hi3_di, WRORH)
13273 IWMMXT_BUILTIN2 (rorv4hi3, WRORHI)
13274 IWMMXT_BUILTIN2 (rorv2si3_di, WRORW)
13275 IWMMXT_BUILTIN2 (rorv2si3, WRORWI)
13276 IWMMXT_BUILTIN2 (rordi3_di, WRORD)
13277 IWMMXT_BUILTIN2 (rordi3, WRORDI)
13278 IWMMXT_BUILTIN2 (iwmmxt_wmacuz, WMACUZ)
13279 IWMMXT_BUILTIN2 (iwmmxt_wmacsz, WMACSZ)
13282 static const struct builtin_description bdesc_1arg[] =
13284 IWMMXT_BUILTIN (iwmmxt_tmovmskb, "tmovmskb", TMOVMSKB)
13285 IWMMXT_BUILTIN (iwmmxt_tmovmskh, "tmovmskh", TMOVMSKH)
13286 IWMMXT_BUILTIN (iwmmxt_tmovmskw, "tmovmskw", TMOVMSKW)
13287 IWMMXT_BUILTIN (iwmmxt_waccb, "waccb", WACCB)
13288 IWMMXT_BUILTIN (iwmmxt_wacch, "wacch", WACCH)
13289 IWMMXT_BUILTIN (iwmmxt_waccw, "waccw", WACCW)
13290 IWMMXT_BUILTIN (iwmmxt_wunpckehub, "wunpckehub", WUNPCKEHUB)
13291 IWMMXT_BUILTIN (iwmmxt_wunpckehuh, "wunpckehuh", WUNPCKEHUH)
13292 IWMMXT_BUILTIN (iwmmxt_wunpckehuw, "wunpckehuw", WUNPCKEHUW)
13293 IWMMXT_BUILTIN (iwmmxt_wunpckehsb, "wunpckehsb", WUNPCKEHSB)
13294 IWMMXT_BUILTIN (iwmmxt_wunpckehsh, "wunpckehsh", WUNPCKEHSH)
13295 IWMMXT_BUILTIN (iwmmxt_wunpckehsw, "wunpckehsw", WUNPCKEHSW)
13296 IWMMXT_BUILTIN (iwmmxt_wunpckelub, "wunpckelub", WUNPCKELUB)
13297 IWMMXT_BUILTIN (iwmmxt_wunpckeluh, "wunpckeluh", WUNPCKELUH)
13298 IWMMXT_BUILTIN (iwmmxt_wunpckeluw, "wunpckeluw", WUNPCKELUW)
13299 IWMMXT_BUILTIN (iwmmxt_wunpckelsb, "wunpckelsb", WUNPCKELSB)
13300 IWMMXT_BUILTIN (iwmmxt_wunpckelsh, "wunpckelsh", WUNPCKELSH)
13301 IWMMXT_BUILTIN (iwmmxt_wunpckelsw, "wunpckelsw", WUNPCKELSW)
13304 /* Set up all the iWMMXt builtins. This is
13305 not called if TARGET_IWMMXT is zero. */
13308 arm_init_iwmmxt_builtins (void)
13310 const struct builtin_description * d;
13312 tree endlink = void_list_node;
13314 tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
13315 tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
13316 tree V8QI_type_node = build_vector_type_for_mode (intQI_type_node, V8QImode);
13319 = build_function_type (integer_type_node,
13320 tree_cons (NULL_TREE, integer_type_node, endlink));
13321 tree v8qi_ftype_v8qi_v8qi_int
13322 = build_function_type (V8QI_type_node,
13323 tree_cons (NULL_TREE, V8QI_type_node,
13324 tree_cons (NULL_TREE, V8QI_type_node,
13325 tree_cons (NULL_TREE,
13328 tree v4hi_ftype_v4hi_int
13329 = build_function_type (V4HI_type_node,
13330 tree_cons (NULL_TREE, V4HI_type_node,
13331 tree_cons (NULL_TREE, integer_type_node,
13333 tree v2si_ftype_v2si_int
13334 = build_function_type (V2SI_type_node,
13335 tree_cons (NULL_TREE, V2SI_type_node,
13336 tree_cons (NULL_TREE, integer_type_node,
13338 tree v2si_ftype_di_di
13339 = build_function_type (V2SI_type_node,
13340 tree_cons (NULL_TREE, long_long_integer_type_node,
13341 tree_cons (NULL_TREE, long_long_integer_type_node,
13343 tree di_ftype_di_int
13344 = build_function_type (long_long_integer_type_node,
13345 tree_cons (NULL_TREE, long_long_integer_type_node,
13346 tree_cons (NULL_TREE, integer_type_node,
13348 tree di_ftype_di_int_int
13349 = build_function_type (long_long_integer_type_node,
13350 tree_cons (NULL_TREE, long_long_integer_type_node,
13351 tree_cons (NULL_TREE, integer_type_node,
13352 tree_cons (NULL_TREE,
13355 tree int_ftype_v8qi
13356 = build_function_type (integer_type_node,
13357 tree_cons (NULL_TREE, V8QI_type_node,
13359 tree int_ftype_v4hi
13360 = build_function_type (integer_type_node,
13361 tree_cons (NULL_TREE, V4HI_type_node,
13363 tree int_ftype_v2si
13364 = build_function_type (integer_type_node,
13365 tree_cons (NULL_TREE, V2SI_type_node,
13367 tree int_ftype_v8qi_int
13368 = build_function_type (integer_type_node,
13369 tree_cons (NULL_TREE, V8QI_type_node,
13370 tree_cons (NULL_TREE, integer_type_node,
13372 tree int_ftype_v4hi_int
13373 = build_function_type (integer_type_node,
13374 tree_cons (NULL_TREE, V4HI_type_node,
13375 tree_cons (NULL_TREE, integer_type_node,
13377 tree int_ftype_v2si_int
13378 = build_function_type (integer_type_node,
13379 tree_cons (NULL_TREE, V2SI_type_node,
13380 tree_cons (NULL_TREE, integer_type_node,
13382 tree v8qi_ftype_v8qi_int_int
13383 = build_function_type (V8QI_type_node,
13384 tree_cons (NULL_TREE, V8QI_type_node,
13385 tree_cons (NULL_TREE, integer_type_node,
13386 tree_cons (NULL_TREE,
13389 tree v4hi_ftype_v4hi_int_int
13390 = build_function_type (V4HI_type_node,
13391 tree_cons (NULL_TREE, V4HI_type_node,
13392 tree_cons (NULL_TREE, integer_type_node,
13393 tree_cons (NULL_TREE,
13396 tree v2si_ftype_v2si_int_int
13397 = build_function_type (V2SI_type_node,
13398 tree_cons (NULL_TREE, V2SI_type_node,
13399 tree_cons (NULL_TREE, integer_type_node,
13400 tree_cons (NULL_TREE,
13403 /* Miscellaneous. */
13404 tree v8qi_ftype_v4hi_v4hi
13405 = build_function_type (V8QI_type_node,
13406 tree_cons (NULL_TREE, V4HI_type_node,
13407 tree_cons (NULL_TREE, V4HI_type_node,
13409 tree v4hi_ftype_v2si_v2si
13410 = build_function_type (V4HI_type_node,
13411 tree_cons (NULL_TREE, V2SI_type_node,
13412 tree_cons (NULL_TREE, V2SI_type_node,
13414 tree v2si_ftype_v4hi_v4hi
13415 = build_function_type (V2SI_type_node,
13416 tree_cons (NULL_TREE, V4HI_type_node,
13417 tree_cons (NULL_TREE, V4HI_type_node,
13419 tree v2si_ftype_v8qi_v8qi
13420 = build_function_type (V2SI_type_node,
13421 tree_cons (NULL_TREE, V8QI_type_node,
13422 tree_cons (NULL_TREE, V8QI_type_node,
13424 tree v4hi_ftype_v4hi_di
13425 = build_function_type (V4HI_type_node,
13426 tree_cons (NULL_TREE, V4HI_type_node,
13427 tree_cons (NULL_TREE,
13428 long_long_integer_type_node,
13430 tree v2si_ftype_v2si_di
13431 = build_function_type (V2SI_type_node,
13432 tree_cons (NULL_TREE, V2SI_type_node,
13433 tree_cons (NULL_TREE,
13434 long_long_integer_type_node,
13436 tree void_ftype_int_int
13437 = build_function_type (void_type_node,
13438 tree_cons (NULL_TREE, integer_type_node,
13439 tree_cons (NULL_TREE, integer_type_node,
13442 = build_function_type (long_long_unsigned_type_node, endlink);
13444 = build_function_type (long_long_integer_type_node,
13445 tree_cons (NULL_TREE, V8QI_type_node,
13448 = build_function_type (long_long_integer_type_node,
13449 tree_cons (NULL_TREE, V4HI_type_node,
13452 = build_function_type (long_long_integer_type_node,
13453 tree_cons (NULL_TREE, V2SI_type_node,
13455 tree v2si_ftype_v4hi
13456 = build_function_type (V2SI_type_node,
13457 tree_cons (NULL_TREE, V4HI_type_node,
13459 tree v4hi_ftype_v8qi
13460 = build_function_type (V4HI_type_node,
13461 tree_cons (NULL_TREE, V8QI_type_node,
13464 tree di_ftype_di_v4hi_v4hi
13465 = build_function_type (long_long_unsigned_type_node,
13466 tree_cons (NULL_TREE,
13467 long_long_unsigned_type_node,
13468 tree_cons (NULL_TREE, V4HI_type_node,
13469 tree_cons (NULL_TREE,
13473 tree di_ftype_v4hi_v4hi
13474 = build_function_type (long_long_unsigned_type_node,
13475 tree_cons (NULL_TREE, V4HI_type_node,
13476 tree_cons (NULL_TREE, V4HI_type_node,
13479 /* Normal vector binops. */
13480 tree v8qi_ftype_v8qi_v8qi
13481 = build_function_type (V8QI_type_node,
13482 tree_cons (NULL_TREE, V8QI_type_node,
13483 tree_cons (NULL_TREE, V8QI_type_node,
13485 tree v4hi_ftype_v4hi_v4hi
13486 = build_function_type (V4HI_type_node,
13487 tree_cons (NULL_TREE, V4HI_type_node,
13488 tree_cons (NULL_TREE, V4HI_type_node,
13490 tree v2si_ftype_v2si_v2si
13491 = build_function_type (V2SI_type_node,
13492 tree_cons (NULL_TREE, V2SI_type_node,
13493 tree_cons (NULL_TREE, V2SI_type_node,
13495 tree di_ftype_di_di
13496 = build_function_type (long_long_unsigned_type_node,
13497 tree_cons (NULL_TREE, long_long_unsigned_type_node,
13498 tree_cons (NULL_TREE,
13499 long_long_unsigned_type_node,
13502 /* Add all builtins that are more or less simple operations on two
13504 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
13506 /* Use one of the operands; the target can have a different mode for
13507 mask-generating compares. */
13508 enum machine_mode mode;
13514 mode = insn_data[d->icode].operand[1].mode;
13519 type = v8qi_ftype_v8qi_v8qi;
13522 type = v4hi_ftype_v4hi_v4hi;
13525 type = v2si_ftype_v2si_v2si;
13528 type = di_ftype_di_di;
13532 gcc_unreachable ();
13535 def_mbuiltin (d->mask, d->name, type, d->code);
13538 /* Add the remaining MMX insns with somewhat more complicated types. */
13539 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wzero", di_ftype_void, ARM_BUILTIN_WZERO);
13540 def_mbuiltin (FL_IWMMXT, "__builtin_arm_setwcx", void_ftype_int_int, ARM_BUILTIN_SETWCX);
13541 def_mbuiltin (FL_IWMMXT, "__builtin_arm_getwcx", int_ftype_int, ARM_BUILTIN_GETWCX);
13543 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSLLH);
13544 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllw", v2si_ftype_v2si_di, ARM_BUILTIN_WSLLW);
13545 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslld", di_ftype_di_di, ARM_BUILTIN_WSLLD);
13546 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSLLHI);
13547 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSLLWI);
13548 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslldi", di_ftype_di_int, ARM_BUILTIN_WSLLDI);
13550 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRLH);
13551 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRLW);
13552 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrld", di_ftype_di_di, ARM_BUILTIN_WSRLD);
13553 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRLHI);
13554 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRLWI);
13555 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrldi", di_ftype_di_int, ARM_BUILTIN_WSRLDI);
13557 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrah", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRAH);
13558 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsraw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRAW);
13559 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrad", di_ftype_di_di, ARM_BUILTIN_WSRAD);
13560 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrahi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRAHI);
13561 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrawi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRAWI);
13562 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsradi", di_ftype_di_int, ARM_BUILTIN_WSRADI);
13564 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WRORH);
13565 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorw", v2si_ftype_v2si_di, ARM_BUILTIN_WRORW);
13566 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrord", di_ftype_di_di, ARM_BUILTIN_WRORD);
13567 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WRORHI);
13568 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorwi", v2si_ftype_v2si_int, ARM_BUILTIN_WRORWI);
13569 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrordi", di_ftype_di_int, ARM_BUILTIN_WRORDI);
13571 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wshufh", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSHUFH);
13573 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadb", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADB);
13574 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadh", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADH);
13575 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadbz", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADBZ);
13576 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadhz", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADHZ);
13578 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsb", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMSB);
13579 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMSH);
13580 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMSW);
13581 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmub", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMUB);
13582 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMUH);
13583 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMUW);
13584 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrb", v8qi_ftype_v8qi_int_int, ARM_BUILTIN_TINSRB);
13585 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrh", v4hi_ftype_v4hi_int_int, ARM_BUILTIN_TINSRH);
13586 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrw", v2si_ftype_v2si_int_int, ARM_BUILTIN_TINSRW);
13588 def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccb", di_ftype_v8qi, ARM_BUILTIN_WACCB);
13589 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wacch", di_ftype_v4hi, ARM_BUILTIN_WACCH);
13590 def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccw", di_ftype_v2si, ARM_BUILTIN_WACCW);
13592 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskb", int_ftype_v8qi, ARM_BUILTIN_TMOVMSKB);
13593 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskh", int_ftype_v4hi, ARM_BUILTIN_TMOVMSKH);
13594 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskw", int_ftype_v2si, ARM_BUILTIN_TMOVMSKW);
13596 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhss", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHSS);
13597 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhus", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHUS);
13598 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwus", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWUS);
13599 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwss", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWSS);
13600 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdus", v2si_ftype_di_di, ARM_BUILTIN_WPACKDUS);
13601 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdss", v2si_ftype_di_di, ARM_BUILTIN_WPACKDSS);
13603 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHUB);
13604 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHUH);
13605 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHUW);
13606 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHSB);
13607 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHSH);
13608 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHSW);
13609 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELUB);
13610 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELUH);
13611 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELUW);
13612 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELSB);
13613 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELSH);
13614 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELSW);
13616 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacs", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACS);
13617 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacsz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACSZ);
13618 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacu", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACU);
13619 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacuz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACUZ);
13621 def_mbuiltin (FL_IWMMXT, "__builtin_arm_walign", v8qi_ftype_v8qi_v8qi_int, ARM_BUILTIN_WALIGN);
13622 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmia", di_ftype_di_int_int, ARM_BUILTIN_TMIA);
13623 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiaph", di_ftype_di_int_int, ARM_BUILTIN_TMIAPH);
13624 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabb", di_ftype_di_int_int, ARM_BUILTIN_TMIABB);
13625 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabt", di_ftype_di_int_int, ARM_BUILTIN_TMIABT);
13626 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatb", di_ftype_di_int_int, ARM_BUILTIN_TMIATB);
13627 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatt", di_ftype_di_int_int, ARM_BUILTIN_TMIATT);
13631 arm_init_tls_builtins (void)
13634 tree nothrow = tree_cons (get_identifier ("nothrow"), NULL, NULL);
13635 tree const_nothrow = tree_cons (get_identifier ("const"), NULL, nothrow);
13637 ftype = build_function_type (ptr_type_node, void_list_node);
13638 add_builtin_function ("__builtin_thread_pointer", ftype,
13639 ARM_BUILTIN_THREAD_POINTER, BUILT_IN_MD,
13640 NULL, const_nothrow);
13644 arm_init_builtins (void)
13646 arm_init_tls_builtins ();
13648 if (TARGET_REALLY_IWMMXT)
13649 arm_init_iwmmxt_builtins ();
13652 /* Errors in the source file can cause expand_expr to return const0_rtx
13653 where we expect a vector. To avoid crashing, use one of the vector
13654 clear instructions. */
13657 safe_vector_operand (rtx x, enum machine_mode mode)
13659 if (x != const0_rtx)
13661 x = gen_reg_rtx (mode);
13663 emit_insn (gen_iwmmxt_clrdi (mode == DImode ? x
13664 : gen_rtx_SUBREG (DImode, x, 0)));
13668 /* Subroutine of arm_expand_builtin to take care of binop insns. */
13671 arm_expand_binop_builtin (enum insn_code icode,
13672 tree exp, rtx target)
13675 tree arg0 = CALL_EXPR_ARG (exp, 0);
13676 tree arg1 = CALL_EXPR_ARG (exp, 1);
13677 rtx op0 = expand_normal (arg0);
13678 rtx op1 = expand_normal (arg1);
13679 enum machine_mode tmode = insn_data[icode].operand[0].mode;
13680 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
13681 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
13683 if (VECTOR_MODE_P (mode0))
13684 op0 = safe_vector_operand (op0, mode0);
13685 if (VECTOR_MODE_P (mode1))
13686 op1 = safe_vector_operand (op1, mode1);
13689 || GET_MODE (target) != tmode
13690 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13691 target = gen_reg_rtx (tmode);
13693 gcc_assert (GET_MODE (op0) == mode0 && GET_MODE (op1) == mode1);
13695 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
13696 op0 = copy_to_mode_reg (mode0, op0);
13697 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
13698 op1 = copy_to_mode_reg (mode1, op1);
13700 pat = GEN_FCN (icode) (target, op0, op1);
13707 /* Subroutine of arm_expand_builtin to take care of unop insns. */
13710 arm_expand_unop_builtin (enum insn_code icode,
13711 tree exp, rtx target, int do_load)
13714 tree arg0 = CALL_EXPR_ARG (exp, 0);
13715 rtx op0 = expand_normal (arg0);
13716 enum machine_mode tmode = insn_data[icode].operand[0].mode;
13717 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
13720 || GET_MODE (target) != tmode
13721 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13722 target = gen_reg_rtx (tmode);
13724 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
13727 if (VECTOR_MODE_P (mode0))
13728 op0 = safe_vector_operand (op0, mode0);
13730 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
13731 op0 = copy_to_mode_reg (mode0, op0);
13734 pat = GEN_FCN (icode) (target, op0);
13741 /* Expand an expression EXP that calls a built-in function,
13742 with result going to TARGET if that's convenient
13743 (and in mode MODE if that's convenient).
13744 SUBTARGET may be used as the target for computing one of EXP's operands.
13745 IGNORE is nonzero if the value is to be ignored. */
13748 arm_expand_builtin (tree exp,
13750 rtx subtarget ATTRIBUTE_UNUSED,
13751 enum machine_mode mode ATTRIBUTE_UNUSED,
13752 int ignore ATTRIBUTE_UNUSED)
13754 const struct builtin_description * d;
13755 enum insn_code icode;
13756 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
13764 int fcode = DECL_FUNCTION_CODE (fndecl);
13766 enum machine_mode tmode;
13767 enum machine_mode mode0;
13768 enum machine_mode mode1;
13769 enum machine_mode mode2;
13773 case ARM_BUILTIN_TEXTRMSB:
13774 case ARM_BUILTIN_TEXTRMUB:
13775 case ARM_BUILTIN_TEXTRMSH:
13776 case ARM_BUILTIN_TEXTRMUH:
13777 case ARM_BUILTIN_TEXTRMSW:
13778 case ARM_BUILTIN_TEXTRMUW:
13779 icode = (fcode == ARM_BUILTIN_TEXTRMSB ? CODE_FOR_iwmmxt_textrmsb
13780 : fcode == ARM_BUILTIN_TEXTRMUB ? CODE_FOR_iwmmxt_textrmub
13781 : fcode == ARM_BUILTIN_TEXTRMSH ? CODE_FOR_iwmmxt_textrmsh
13782 : fcode == ARM_BUILTIN_TEXTRMUH ? CODE_FOR_iwmmxt_textrmuh
13783 : CODE_FOR_iwmmxt_textrmw);
13785 arg0 = CALL_EXPR_ARG (exp, 0);
13786 arg1 = CALL_EXPR_ARG (exp, 1);
13787 op0 = expand_normal (arg0);
13788 op1 = expand_normal (arg1);
13789 tmode = insn_data[icode].operand[0].mode;
13790 mode0 = insn_data[icode].operand[1].mode;
13791 mode1 = insn_data[icode].operand[2].mode;
13793 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
13794 op0 = copy_to_mode_reg (mode0, op0);
13795 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
13797 /* @@@ better error message */
13798 error ("selector must be an immediate");
13799 return gen_reg_rtx (tmode);
13802 || GET_MODE (target) != tmode
13803 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13804 target = gen_reg_rtx (tmode);
13805 pat = GEN_FCN (icode) (target, op0, op1);
13811 case ARM_BUILTIN_TINSRB:
13812 case ARM_BUILTIN_TINSRH:
13813 case ARM_BUILTIN_TINSRW:
13814 icode = (fcode == ARM_BUILTIN_TINSRB ? CODE_FOR_iwmmxt_tinsrb
13815 : fcode == ARM_BUILTIN_TINSRH ? CODE_FOR_iwmmxt_tinsrh
13816 : CODE_FOR_iwmmxt_tinsrw);
13817 arg0 = CALL_EXPR_ARG (exp, 0);
13818 arg1 = CALL_EXPR_ARG (exp, 1);
13819 arg2 = CALL_EXPR_ARG (exp, 2);
13820 op0 = expand_normal (arg0);
13821 op1 = expand_normal (arg1);
13822 op2 = expand_normal (arg2);
13823 tmode = insn_data[icode].operand[0].mode;
13824 mode0 = insn_data[icode].operand[1].mode;
13825 mode1 = insn_data[icode].operand[2].mode;
13826 mode2 = insn_data[icode].operand[3].mode;
13828 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
13829 op0 = copy_to_mode_reg (mode0, op0);
13830 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
13831 op1 = copy_to_mode_reg (mode1, op1);
13832 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
13834 /* @@@ better error message */
13835 error ("selector must be an immediate");
13839 || GET_MODE (target) != tmode
13840 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13841 target = gen_reg_rtx (tmode);
13842 pat = GEN_FCN (icode) (target, op0, op1, op2);
13848 case ARM_BUILTIN_SETWCX:
13849 arg0 = CALL_EXPR_ARG (exp, 0);
13850 arg1 = CALL_EXPR_ARG (exp, 1);
13851 op0 = force_reg (SImode, expand_normal (arg0));
13852 op1 = expand_normal (arg1);
13853 emit_insn (gen_iwmmxt_tmcr (op1, op0));
13856 case ARM_BUILTIN_GETWCX:
13857 arg0 = CALL_EXPR_ARG (exp, 0);
13858 op0 = expand_normal (arg0);
13859 target = gen_reg_rtx (SImode);
13860 emit_insn (gen_iwmmxt_tmrc (target, op0));
13863 case ARM_BUILTIN_WSHUFH:
13864 icode = CODE_FOR_iwmmxt_wshufh;
13865 arg0 = CALL_EXPR_ARG (exp, 0);
13866 arg1 = CALL_EXPR_ARG (exp, 1);
13867 op0 = expand_normal (arg0);
13868 op1 = expand_normal (arg1);
13869 tmode = insn_data[icode].operand[0].mode;
13870 mode1 = insn_data[icode].operand[1].mode;
13871 mode2 = insn_data[icode].operand[2].mode;
13873 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
13874 op0 = copy_to_mode_reg (mode1, op0);
13875 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
13877 /* @@@ better error message */
13878 error ("mask must be an immediate");
13882 || GET_MODE (target) != tmode
13883 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13884 target = gen_reg_rtx (tmode);
13885 pat = GEN_FCN (icode) (target, op0, op1);
13891 case ARM_BUILTIN_WSADB:
13892 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadb, exp, target);
13893 case ARM_BUILTIN_WSADH:
13894 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadh, exp, target);
13895 case ARM_BUILTIN_WSADBZ:
13896 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadbz, exp, target);
13897 case ARM_BUILTIN_WSADHZ:
13898 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadhz, exp, target);
13900 /* Several three-argument builtins. */
13901 case ARM_BUILTIN_WMACS:
13902 case ARM_BUILTIN_WMACU:
13903 case ARM_BUILTIN_WALIGN:
13904 case ARM_BUILTIN_TMIA:
13905 case ARM_BUILTIN_TMIAPH:
13906 case ARM_BUILTIN_TMIATT:
13907 case ARM_BUILTIN_TMIATB:
13908 case ARM_BUILTIN_TMIABT:
13909 case ARM_BUILTIN_TMIABB:
13910 icode = (fcode == ARM_BUILTIN_WMACS ? CODE_FOR_iwmmxt_wmacs
13911 : fcode == ARM_BUILTIN_WMACU ? CODE_FOR_iwmmxt_wmacu
13912 : fcode == ARM_BUILTIN_TMIA ? CODE_FOR_iwmmxt_tmia
13913 : fcode == ARM_BUILTIN_TMIAPH ? CODE_FOR_iwmmxt_tmiaph
13914 : fcode == ARM_BUILTIN_TMIABB ? CODE_FOR_iwmmxt_tmiabb
13915 : fcode == ARM_BUILTIN_TMIABT ? CODE_FOR_iwmmxt_tmiabt
13916 : fcode == ARM_BUILTIN_TMIATB ? CODE_FOR_iwmmxt_tmiatb
13917 : fcode == ARM_BUILTIN_TMIATT ? CODE_FOR_iwmmxt_tmiatt
13918 : CODE_FOR_iwmmxt_walign);
13919 arg0 = CALL_EXPR_ARG (exp, 0);
13920 arg1 = CALL_EXPR_ARG (exp, 1);
13921 arg2 = CALL_EXPR_ARG (exp, 2);
13922 op0 = expand_normal (arg0);
13923 op1 = expand_normal (arg1);
13924 op2 = expand_normal (arg2);
13925 tmode = insn_data[icode].operand[0].mode;
13926 mode0 = insn_data[icode].operand[1].mode;
13927 mode1 = insn_data[icode].operand[2].mode;
13928 mode2 = insn_data[icode].operand[3].mode;
13930 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
13931 op0 = copy_to_mode_reg (mode0, op0);
13932 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
13933 op1 = copy_to_mode_reg (mode1, op1);
13934 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
13935 op2 = copy_to_mode_reg (mode2, op2);
13937 || GET_MODE (target) != tmode
13938 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13939 target = gen_reg_rtx (tmode);
13940 pat = GEN_FCN (icode) (target, op0, op1, op2);
13946 case ARM_BUILTIN_WZERO:
13947 target = gen_reg_rtx (DImode);
13948 emit_insn (gen_iwmmxt_clrdi (target));
13951 case ARM_BUILTIN_THREAD_POINTER:
13952 return arm_load_tp (target);
13958 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
13959 if (d->code == (const enum arm_builtins) fcode)
13960 return arm_expand_binop_builtin (d->icode, exp, target);
13962 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
13963 if (d->code == (const enum arm_builtins) fcode)
13964 return arm_expand_unop_builtin (d->icode, exp, target, 0);
13966 /* @@@ Should really do something sensible here. */
13970 /* Return the number (counting from 0) of
13971 the least significant set bit in MASK. */
13974 number_of_first_bit_set (unsigned mask)
13979 (mask & (1 << bit)) == 0;
13986 /* Emit code to push or pop registers to or from the stack. F is the
13987 assembly file. MASK is the registers to push or pop. PUSH is
13988 nonzero if we should push, and zero if we should pop. For debugging
13989 output, if pushing, adjust CFA_OFFSET by the amount of space added
13990 to the stack. REAL_REGS should have the same number of bits set as
13991 MASK, and will be used instead (in the same order) to describe which
13992 registers were saved - this is used to mark the save slots when we
13993 push high registers after moving them to low registers. */
13995 thumb_pushpop (FILE *f, unsigned long mask, int push, int *cfa_offset,
13996 unsigned long real_regs)
13999 int lo_mask = mask & 0xFF;
14000 int pushed_words = 0;
14004 if (lo_mask == 0 && !push && (mask & (1 << PC_REGNUM)))
14006 /* Special case. Do not generate a POP PC statement here, do it in
14008 thumb_exit (f, -1);
14012 if (ARM_EABI_UNWIND_TABLES && push)
14014 fprintf (f, "\t.save\t{");
14015 for (regno = 0; regno < 15; regno++)
14017 if (real_regs & (1 << regno))
14019 if (real_regs & ((1 << regno) -1))
14021 asm_fprintf (f, "%r", regno);
14024 fprintf (f, "}\n");
14027 fprintf (f, "\t%s\t{", push ? "push" : "pop");
14029 /* Look at the low registers first. */
14030 for (regno = 0; regno <= LAST_LO_REGNUM; regno++, lo_mask >>= 1)
14034 asm_fprintf (f, "%r", regno);
14036 if ((lo_mask & ~1) != 0)
14043 if (push && (mask & (1 << LR_REGNUM)))
14045 /* Catch pushing the LR. */
14049 asm_fprintf (f, "%r", LR_REGNUM);
14053 else if (!push && (mask & (1 << PC_REGNUM)))
14055 /* Catch popping the PC. */
14056 if (TARGET_INTERWORK || TARGET_BACKTRACE
14057 || current_function_calls_eh_return)
14059 /* The PC is never poped directly, instead
14060 it is popped into r3 and then BX is used. */
14061 fprintf (f, "}\n");
14063 thumb_exit (f, -1);
14072 asm_fprintf (f, "%r", PC_REGNUM);
14076 fprintf (f, "}\n");
14078 if (push && pushed_words && dwarf2out_do_frame ())
14080 char *l = dwarf2out_cfi_label ();
14081 int pushed_mask = real_regs;
14083 *cfa_offset += pushed_words * 4;
14084 dwarf2out_def_cfa (l, SP_REGNUM, *cfa_offset);
14087 pushed_mask = real_regs;
14088 for (regno = 0; regno <= 14; regno++, pushed_mask >>= 1)
14090 if (pushed_mask & 1)
14091 dwarf2out_reg_save (l, regno, 4 * pushed_words++ - *cfa_offset);
14096 /* Generate code to return from a thumb function.
14097 If 'reg_containing_return_addr' is -1, then the return address is
14098 actually on the stack, at the stack pointer. */
14100 thumb_exit (FILE *f, int reg_containing_return_addr)
14102 unsigned regs_available_for_popping;
14103 unsigned regs_to_pop;
14105 unsigned available;
14109 int restore_a4 = FALSE;
14111 /* Compute the registers we need to pop. */
14115 if (reg_containing_return_addr == -1)
14117 regs_to_pop |= 1 << LR_REGNUM;
14121 if (TARGET_BACKTRACE)
14123 /* Restore the (ARM) frame pointer and stack pointer. */
14124 regs_to_pop |= (1 << ARM_HARD_FRAME_POINTER_REGNUM) | (1 << SP_REGNUM);
14128 /* If there is nothing to pop then just emit the BX instruction and
14130 if (pops_needed == 0)
14132 if (current_function_calls_eh_return)
14133 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, ARM_EH_STACKADJ_REGNUM);
14135 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
14138 /* Otherwise if we are not supporting interworking and we have not created
14139 a backtrace structure and the function was not entered in ARM mode then
14140 just pop the return address straight into the PC. */
14141 else if (!TARGET_INTERWORK
14142 && !TARGET_BACKTRACE
14143 && !is_called_in_ARM_mode (current_function_decl)
14144 && !current_function_calls_eh_return)
14146 asm_fprintf (f, "\tpop\t{%r}\n", PC_REGNUM);
14150 /* Find out how many of the (return) argument registers we can corrupt. */
14151 regs_available_for_popping = 0;
14153 /* If returning via __builtin_eh_return, the bottom three registers
14154 all contain information needed for the return. */
14155 if (current_function_calls_eh_return)
14159 /* If we can deduce the registers used from the function's
14160 return value. This is more reliable that examining
14161 df_regs_ever_live_p () because that will be set if the register is
14162 ever used in the function, not just if the register is used
14163 to hold a return value. */
14165 if (current_function_return_rtx != 0)
14166 mode = GET_MODE (current_function_return_rtx);
14168 mode = DECL_MODE (DECL_RESULT (current_function_decl));
14170 size = GET_MODE_SIZE (mode);
14174 /* In a void function we can use any argument register.
14175 In a function that returns a structure on the stack
14176 we can use the second and third argument registers. */
14177 if (mode == VOIDmode)
14178 regs_available_for_popping =
14179 (1 << ARG_REGISTER (1))
14180 | (1 << ARG_REGISTER (2))
14181 | (1 << ARG_REGISTER (3));
14183 regs_available_for_popping =
14184 (1 << ARG_REGISTER (2))
14185 | (1 << ARG_REGISTER (3));
14187 else if (size <= 4)
14188 regs_available_for_popping =
14189 (1 << ARG_REGISTER (2))
14190 | (1 << ARG_REGISTER (3));
14191 else if (size <= 8)
14192 regs_available_for_popping =
14193 (1 << ARG_REGISTER (3));
14196 /* Match registers to be popped with registers into which we pop them. */
14197 for (available = regs_available_for_popping,
14198 required = regs_to_pop;
14199 required != 0 && available != 0;
14200 available &= ~(available & - available),
14201 required &= ~(required & - required))
14204 /* If we have any popping registers left over, remove them. */
14206 regs_available_for_popping &= ~available;
14208 /* Otherwise if we need another popping register we can use
14209 the fourth argument register. */
14210 else if (pops_needed)
14212 /* If we have not found any free argument registers and
14213 reg a4 contains the return address, we must move it. */
14214 if (regs_available_for_popping == 0
14215 && reg_containing_return_addr == LAST_ARG_REGNUM)
14217 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
14218 reg_containing_return_addr = LR_REGNUM;
14220 else if (size > 12)
14222 /* Register a4 is being used to hold part of the return value,
14223 but we have dire need of a free, low register. */
14226 asm_fprintf (f, "\tmov\t%r, %r\n",IP_REGNUM, LAST_ARG_REGNUM);
14229 if (reg_containing_return_addr != LAST_ARG_REGNUM)
14231 /* The fourth argument register is available. */
14232 regs_available_for_popping |= 1 << LAST_ARG_REGNUM;
14238 /* Pop as many registers as we can. */
14239 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
14240 regs_available_for_popping);
14242 /* Process the registers we popped. */
14243 if (reg_containing_return_addr == -1)
14245 /* The return address was popped into the lowest numbered register. */
14246 regs_to_pop &= ~(1 << LR_REGNUM);
14248 reg_containing_return_addr =
14249 number_of_first_bit_set (regs_available_for_popping);
14251 /* Remove this register for the mask of available registers, so that
14252 the return address will not be corrupted by further pops. */
14253 regs_available_for_popping &= ~(1 << reg_containing_return_addr);
14256 /* If we popped other registers then handle them here. */
14257 if (regs_available_for_popping)
14261 /* Work out which register currently contains the frame pointer. */
14262 frame_pointer = number_of_first_bit_set (regs_available_for_popping);
14264 /* Move it into the correct place. */
14265 asm_fprintf (f, "\tmov\t%r, %r\n",
14266 ARM_HARD_FRAME_POINTER_REGNUM, frame_pointer);
14268 /* (Temporarily) remove it from the mask of popped registers. */
14269 regs_available_for_popping &= ~(1 << frame_pointer);
14270 regs_to_pop &= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM);
14272 if (regs_available_for_popping)
14276 /* We popped the stack pointer as well,
14277 find the register that contains it. */
14278 stack_pointer = number_of_first_bit_set (regs_available_for_popping);
14280 /* Move it into the stack register. */
14281 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, stack_pointer);
14283 /* At this point we have popped all necessary registers, so
14284 do not worry about restoring regs_available_for_popping
14285 to its correct value:
14287 assert (pops_needed == 0)
14288 assert (regs_available_for_popping == (1 << frame_pointer))
14289 assert (regs_to_pop == (1 << STACK_POINTER)) */
14293 /* Since we have just move the popped value into the frame
14294 pointer, the popping register is available for reuse, and
14295 we know that we still have the stack pointer left to pop. */
14296 regs_available_for_popping |= (1 << frame_pointer);
14300 /* If we still have registers left on the stack, but we no longer have
14301 any registers into which we can pop them, then we must move the return
14302 address into the link register and make available the register that
14304 if (regs_available_for_popping == 0 && pops_needed > 0)
14306 regs_available_for_popping |= 1 << reg_containing_return_addr;
14308 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM,
14309 reg_containing_return_addr);
14311 reg_containing_return_addr = LR_REGNUM;
14314 /* If we have registers left on the stack then pop some more.
14315 We know that at most we will want to pop FP and SP. */
14316 if (pops_needed > 0)
14321 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
14322 regs_available_for_popping);
14324 /* We have popped either FP or SP.
14325 Move whichever one it is into the correct register. */
14326 popped_into = number_of_first_bit_set (regs_available_for_popping);
14327 move_to = number_of_first_bit_set (regs_to_pop);
14329 asm_fprintf (f, "\tmov\t%r, %r\n", move_to, popped_into);
14331 regs_to_pop &= ~(1 << move_to);
14336 /* If we still have not popped everything then we must have only
14337 had one register available to us and we are now popping the SP. */
14338 if (pops_needed > 0)
14342 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
14343 regs_available_for_popping);
14345 popped_into = number_of_first_bit_set (regs_available_for_popping);
14347 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, popped_into);
14349 assert (regs_to_pop == (1 << STACK_POINTER))
14350 assert (pops_needed == 1)
14354 /* If necessary restore the a4 register. */
14357 if (reg_containing_return_addr != LR_REGNUM)
14359 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
14360 reg_containing_return_addr = LR_REGNUM;
14363 asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM);
14366 if (current_function_calls_eh_return)
14367 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, ARM_EH_STACKADJ_REGNUM);
14369 /* Return to caller. */
14370 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
14375 thumb1_final_prescan_insn (rtx insn)
14377 if (flag_print_asm_name)
14378 asm_fprintf (asm_out_file, "%@ 0x%04x\n",
14379 INSN_ADDRESSES (INSN_UID (insn)));
14383 thumb_shiftable_const (unsigned HOST_WIDE_INT val)
14385 unsigned HOST_WIDE_INT mask = 0xff;
14388 if (val == 0) /* XXX */
14391 for (i = 0; i < 25; i++)
14392 if ((val & (mask << i)) == val)
14398 /* Returns nonzero if the current function contains,
14399 or might contain a far jump. */
14401 thumb_far_jump_used_p (void)
14405 /* This test is only important for leaf functions. */
14406 /* assert (!leaf_function_p ()); */
14408 /* If we have already decided that far jumps may be used,
14409 do not bother checking again, and always return true even if
14410 it turns out that they are not being used. Once we have made
14411 the decision that far jumps are present (and that hence the link
14412 register will be pushed onto the stack) we cannot go back on it. */
14413 if (cfun->machine->far_jump_used)
14416 /* If this function is not being called from the prologue/epilogue
14417 generation code then it must be being called from the
14418 INITIAL_ELIMINATION_OFFSET macro. */
14419 if (!(ARM_DOUBLEWORD_ALIGN || reload_completed))
14421 /* In this case we know that we are being asked about the elimination
14422 of the arg pointer register. If that register is not being used,
14423 then there are no arguments on the stack, and we do not have to
14424 worry that a far jump might force the prologue to push the link
14425 register, changing the stack offsets. In this case we can just
14426 return false, since the presence of far jumps in the function will
14427 not affect stack offsets.
14429 If the arg pointer is live (or if it was live, but has now been
14430 eliminated and so set to dead) then we do have to test to see if
14431 the function might contain a far jump. This test can lead to some
14432 false negatives, since before reload is completed, then length of
14433 branch instructions is not known, so gcc defaults to returning their
14434 longest length, which in turn sets the far jump attribute to true.
14436 A false negative will not result in bad code being generated, but it
14437 will result in a needless push and pop of the link register. We
14438 hope that this does not occur too often.
14440 If we need doubleword stack alignment this could affect the other
14441 elimination offsets so we can't risk getting it wrong. */
14442 if (df_regs_ever_live_p (ARG_POINTER_REGNUM))
14443 cfun->machine->arg_pointer_live = 1;
14444 else if (!cfun->machine->arg_pointer_live)
14448 /* Check to see if the function contains a branch
14449 insn with the far jump attribute set. */
14450 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
14452 if (GET_CODE (insn) == JUMP_INSN
14453 /* Ignore tablejump patterns. */
14454 && GET_CODE (PATTERN (insn)) != ADDR_VEC
14455 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
14456 && get_attr_far_jump (insn) == FAR_JUMP_YES
14459 /* Record the fact that we have decided that
14460 the function does use far jumps. */
14461 cfun->machine->far_jump_used = 1;
14469 /* Return nonzero if FUNC must be entered in ARM mode. */
14471 is_called_in_ARM_mode (tree func)
14473 gcc_assert (TREE_CODE (func) == FUNCTION_DECL);
14475 /* Ignore the problem about functions whose address is taken. */
14476 if (TARGET_CALLEE_INTERWORKING && TREE_PUBLIC (func))
14480 return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func)) != NULL_TREE;
14486 /* The bits which aren't usefully expanded as rtl. */
14488 thumb_unexpanded_epilogue (void)
14491 unsigned long live_regs_mask = 0;
14492 int high_regs_pushed = 0;
14493 int had_to_push_lr;
14496 if (return_used_this_function)
14499 if (IS_NAKED (arm_current_func_type ()))
14502 live_regs_mask = thumb1_compute_save_reg_mask ();
14503 high_regs_pushed = bit_count (live_regs_mask & 0x0f00);
14505 /* If we can deduce the registers used from the function's return value.
14506 This is more reliable that examining df_regs_ever_live_p () because that
14507 will be set if the register is ever used in the function, not just if
14508 the register is used to hold a return value. */
14509 size = arm_size_return_regs ();
14511 /* The prolog may have pushed some high registers to use as
14512 work registers. e.g. the testsuite file:
14513 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
14514 compiles to produce:
14515 push {r4, r5, r6, r7, lr}
14519 as part of the prolog. We have to undo that pushing here. */
14521 if (high_regs_pushed)
14523 unsigned long mask = live_regs_mask & 0xff;
14526 /* The available low registers depend on the size of the value we are
14534 /* Oh dear! We have no low registers into which we can pop
14537 ("no low registers available for popping high registers");
14539 for (next_hi_reg = 8; next_hi_reg < 13; next_hi_reg++)
14540 if (live_regs_mask & (1 << next_hi_reg))
14543 while (high_regs_pushed)
14545 /* Find lo register(s) into which the high register(s) can
14547 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
14549 if (mask & (1 << regno))
14550 high_regs_pushed--;
14551 if (high_regs_pushed == 0)
14555 mask &= (2 << regno) - 1; /* A noop if regno == 8 */
14557 /* Pop the values into the low register(s). */
14558 thumb_pushpop (asm_out_file, mask, 0, NULL, mask);
14560 /* Move the value(s) into the high registers. */
14561 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
14563 if (mask & (1 << regno))
14565 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", next_hi_reg,
14568 for (next_hi_reg++; next_hi_reg < 13; next_hi_reg++)
14569 if (live_regs_mask & (1 << next_hi_reg))
14574 live_regs_mask &= ~0x0f00;
14577 had_to_push_lr = (live_regs_mask & (1 << LR_REGNUM)) != 0;
14578 live_regs_mask &= 0xff;
14580 if (current_function_pretend_args_size == 0 || TARGET_BACKTRACE)
14582 /* Pop the return address into the PC. */
14583 if (had_to_push_lr)
14584 live_regs_mask |= 1 << PC_REGNUM;
14586 /* Either no argument registers were pushed or a backtrace
14587 structure was created which includes an adjusted stack
14588 pointer, so just pop everything. */
14589 if (live_regs_mask)
14590 thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL,
14593 /* We have either just popped the return address into the
14594 PC or it is was kept in LR for the entire function. */
14595 if (!had_to_push_lr)
14596 thumb_exit (asm_out_file, LR_REGNUM);
14600 /* Pop everything but the return address. */
14601 if (live_regs_mask)
14602 thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL,
14605 if (had_to_push_lr)
14609 /* We have no free low regs, so save one. */
14610 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", IP_REGNUM,
14614 /* Get the return address into a temporary register. */
14615 thumb_pushpop (asm_out_file, 1 << LAST_ARG_REGNUM, 0, NULL,
14616 1 << LAST_ARG_REGNUM);
14620 /* Move the return address to lr. */
14621 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", LR_REGNUM,
14623 /* Restore the low register. */
14624 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", LAST_ARG_REGNUM,
14629 regno = LAST_ARG_REGNUM;
14634 /* Remove the argument registers that were pushed onto the stack. */
14635 asm_fprintf (asm_out_file, "\tadd\t%r, %r, #%d\n",
14636 SP_REGNUM, SP_REGNUM,
14637 current_function_pretend_args_size);
14639 thumb_exit (asm_out_file, regno);
14645 /* Functions to save and restore machine-specific function data. */
14646 static struct machine_function *
14647 arm_init_machine_status (void)
14649 struct machine_function *machine;
14650 machine = (machine_function *) ggc_alloc_cleared (sizeof (machine_function));
14652 #if ARM_FT_UNKNOWN != 0
14653 machine->func_type = ARM_FT_UNKNOWN;
14658 /* Return an RTX indicating where the return address to the
14659 calling function can be found. */
14661 arm_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
14666 return get_hard_reg_initial_val (Pmode, LR_REGNUM);
14669 /* Do anything needed before RTL is emitted for each function. */
14671 arm_init_expanders (void)
14673 /* Arrange to initialize and mark the machine per-function status. */
14674 init_machine_status = arm_init_machine_status;
14676 /* This is to stop the combine pass optimizing away the alignment
14677 adjustment of va_arg. */
14678 /* ??? It is claimed that this should not be necessary. */
14680 mark_reg_pointer (arg_pointer_rtx, PARM_BOUNDARY);
14684 /* Like arm_compute_initial_elimination offset. Simpler because there
14685 isn't an ABI specified frame pointer for Thumb. Instead, we set it
14686 to point at the base of the local variables after static stack
14687 space for a function has been allocated. */
14690 thumb_compute_initial_elimination_offset (unsigned int from, unsigned int to)
14692 arm_stack_offsets *offsets;
14694 offsets = arm_get_frame_offsets ();
14698 case ARG_POINTER_REGNUM:
14701 case STACK_POINTER_REGNUM:
14702 return offsets->outgoing_args - offsets->saved_args;
14704 case FRAME_POINTER_REGNUM:
14705 return offsets->soft_frame - offsets->saved_args;
14707 case ARM_HARD_FRAME_POINTER_REGNUM:
14708 return offsets->saved_regs - offsets->saved_args;
14710 case THUMB_HARD_FRAME_POINTER_REGNUM:
14711 return offsets->locals_base - offsets->saved_args;
14714 gcc_unreachable ();
14718 case FRAME_POINTER_REGNUM:
14721 case STACK_POINTER_REGNUM:
14722 return offsets->outgoing_args - offsets->soft_frame;
14724 case ARM_HARD_FRAME_POINTER_REGNUM:
14725 return offsets->saved_regs - offsets->soft_frame;
14727 case THUMB_HARD_FRAME_POINTER_REGNUM:
14728 return offsets->locals_base - offsets->soft_frame;
14731 gcc_unreachable ();
14736 gcc_unreachable ();
14740 /* Generate the rest of a function's prologue. */
14742 thumb1_expand_prologue (void)
14746 HOST_WIDE_INT amount;
14747 arm_stack_offsets *offsets;
14748 unsigned long func_type;
14750 unsigned long live_regs_mask;
14752 func_type = arm_current_func_type ();
14754 /* Naked functions don't have prologues. */
14755 if (IS_NAKED (func_type))
14758 if (IS_INTERRUPT (func_type))
14760 error ("interrupt Service Routines cannot be coded in Thumb mode");
14764 live_regs_mask = thumb1_compute_save_reg_mask ();
14765 /* Load the pic register before setting the frame pointer,
14766 so we can use r7 as a temporary work register. */
14767 if (flag_pic && arm_pic_register != INVALID_REGNUM)
14768 arm_load_pic_register (live_regs_mask);
14770 if (!frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > 0)
14771 emit_move_insn (gen_rtx_REG (Pmode, ARM_HARD_FRAME_POINTER_REGNUM),
14772 stack_pointer_rtx);
14774 offsets = arm_get_frame_offsets ();
14775 amount = offsets->outgoing_args - offsets->saved_regs;
14780 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
14781 GEN_INT (- amount)));
14782 RTX_FRAME_RELATED_P (insn) = 1;
14788 /* The stack decrement is too big for an immediate value in a single
14789 insn. In theory we could issue multiple subtracts, but after
14790 three of them it becomes more space efficient to place the full
14791 value in the constant pool and load into a register. (Also the
14792 ARM debugger really likes to see only one stack decrement per
14793 function). So instead we look for a scratch register into which
14794 we can load the decrement, and then we subtract this from the
14795 stack pointer. Unfortunately on the thumb the only available
14796 scratch registers are the argument registers, and we cannot use
14797 these as they may hold arguments to the function. Instead we
14798 attempt to locate a call preserved register which is used by this
14799 function. If we can find one, then we know that it will have
14800 been pushed at the start of the prologue and so we can corrupt
14802 for (regno = LAST_ARG_REGNUM + 1; regno <= LAST_LO_REGNUM; regno++)
14803 if (live_regs_mask & (1 << regno)
14804 && !(frame_pointer_needed
14805 && (regno == THUMB_HARD_FRAME_POINTER_REGNUM)))
14808 if (regno > LAST_LO_REGNUM) /* Very unlikely. */
14810 rtx spare = gen_rtx_REG (SImode, IP_REGNUM);
14812 /* Choose an arbitrary, non-argument low register. */
14813 reg = gen_rtx_REG (SImode, LAST_LO_REGNUM);
14815 /* Save it by copying it into a high, scratch register. */
14816 emit_insn (gen_movsi (spare, reg));
14817 /* Add a USE to stop propagate_one_insn() from barfing. */
14818 emit_insn (gen_prologue_use (spare));
14820 /* Decrement the stack. */
14821 emit_insn (gen_movsi (reg, GEN_INT (- amount)));
14822 insn = emit_insn (gen_addsi3 (stack_pointer_rtx,
14823 stack_pointer_rtx, reg));
14824 RTX_FRAME_RELATED_P (insn) = 1;
14825 dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
14826 plus_constant (stack_pointer_rtx,
14828 RTX_FRAME_RELATED_P (dwarf) = 1;
14830 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
14833 /* Restore the low register's original value. */
14834 emit_insn (gen_movsi (reg, spare));
14836 /* Emit a USE of the restored scratch register, so that flow
14837 analysis will not consider the restore redundant. The
14838 register won't be used again in this function and isn't
14839 restored by the epilogue. */
14840 emit_insn (gen_prologue_use (reg));
14844 reg = gen_rtx_REG (SImode, regno);
14846 emit_insn (gen_movsi (reg, GEN_INT (- amount)));
14848 insn = emit_insn (gen_addsi3 (stack_pointer_rtx,
14849 stack_pointer_rtx, reg));
14850 RTX_FRAME_RELATED_P (insn) = 1;
14851 dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
14852 plus_constant (stack_pointer_rtx,
14854 RTX_FRAME_RELATED_P (dwarf) = 1;
14856 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
14862 if (frame_pointer_needed)
14863 thumb_set_frame_pointer (offsets);
14865 /* If we are profiling, make sure no instructions are scheduled before
14866 the call to mcount. Similarly if the user has requested no
14867 scheduling in the prolog. Similarly if we want non-call exceptions
14868 using the EABI unwinder, to prevent faulting instructions from being
14869 swapped with a stack adjustment. */
14870 if (current_function_profile || !TARGET_SCHED_PROLOG
14871 || (ARM_EABI_UNWIND_TABLES && flag_non_call_exceptions))
14872 emit_insn (gen_blockage ());
14874 cfun->machine->lr_save_eliminated = !thumb_force_lr_save ();
14875 if (live_regs_mask & 0xff)
14876 cfun->machine->lr_save_eliminated = 0;
14881 thumb1_expand_epilogue (void)
14883 HOST_WIDE_INT amount;
14884 arm_stack_offsets *offsets;
14887 /* Naked functions don't have prologues. */
14888 if (IS_NAKED (arm_current_func_type ()))
14891 offsets = arm_get_frame_offsets ();
14892 amount = offsets->outgoing_args - offsets->saved_regs;
14894 if (frame_pointer_needed)
14896 emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx));
14897 amount = offsets->locals_base - offsets->saved_regs;
14900 gcc_assert (amount >= 0);
14904 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
14905 GEN_INT (amount)));
14908 /* r3 is always free in the epilogue. */
14909 rtx reg = gen_rtx_REG (SImode, LAST_ARG_REGNUM);
14911 emit_insn (gen_movsi (reg, GEN_INT (amount)));
14912 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, reg));
14916 /* Emit a USE (stack_pointer_rtx), so that
14917 the stack adjustment will not be deleted. */
14918 emit_insn (gen_prologue_use (stack_pointer_rtx));
14920 if (current_function_profile || !TARGET_SCHED_PROLOG)
14921 emit_insn (gen_blockage ());
14923 /* Emit a clobber for each insn that will be restored in the epilogue,
14924 so that flow2 will get register lifetimes correct. */
14925 for (regno = 0; regno < 13; regno++)
14926 if (df_regs_ever_live_p (regno) && !call_used_regs[regno])
14927 emit_insn (gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, regno)));
14929 if (! df_regs_ever_live_p (LR_REGNUM))
14930 emit_insn (gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, LR_REGNUM)));
14934 thumb1_output_function_prologue (FILE *f, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
14936 unsigned long live_regs_mask = 0;
14937 unsigned long l_mask;
14938 unsigned high_regs_pushed = 0;
14939 int cfa_offset = 0;
14942 if (IS_NAKED (arm_current_func_type ()))
14945 if (is_called_in_ARM_mode (current_function_decl))
14949 gcc_assert (GET_CODE (DECL_RTL (current_function_decl)) == MEM);
14950 gcc_assert (GET_CODE (XEXP (DECL_RTL (current_function_decl), 0))
14952 name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
14954 /* Generate code sequence to switch us into Thumb mode. */
14955 /* The .code 32 directive has already been emitted by
14956 ASM_DECLARE_FUNCTION_NAME. */
14957 asm_fprintf (f, "\torr\t%r, %r, #1\n", IP_REGNUM, PC_REGNUM);
14958 asm_fprintf (f, "\tbx\t%r\n", IP_REGNUM);
14960 /* Generate a label, so that the debugger will notice the
14961 change in instruction sets. This label is also used by
14962 the assembler to bypass the ARM code when this function
14963 is called from a Thumb encoded function elsewhere in the
14964 same file. Hence the definition of STUB_NAME here must
14965 agree with the definition in gas/config/tc-arm.c. */
14967 #define STUB_NAME ".real_start_of"
14969 fprintf (f, "\t.code\t16\n");
14971 if (arm_dllexport_name_p (name))
14972 name = arm_strip_name_encoding (name);
14974 asm_fprintf (f, "\t.globl %s%U%s\n", STUB_NAME, name);
14975 fprintf (f, "\t.thumb_func\n");
14976 asm_fprintf (f, "%s%U%s:\n", STUB_NAME, name);
14979 if (current_function_pretend_args_size)
14981 /* Output unwind directive for the stack adjustment. */
14982 if (ARM_EABI_UNWIND_TABLES)
14983 fprintf (f, "\t.pad #%d\n",
14984 current_function_pretend_args_size);
14986 if (cfun->machine->uses_anonymous_args)
14990 fprintf (f, "\tpush\t{");
14992 num_pushes = ARM_NUM_INTS (current_function_pretend_args_size);
14994 for (regno = LAST_ARG_REGNUM + 1 - num_pushes;
14995 regno <= LAST_ARG_REGNUM;
14997 asm_fprintf (f, "%r%s", regno,
14998 regno == LAST_ARG_REGNUM ? "" : ", ");
15000 fprintf (f, "}\n");
15003 asm_fprintf (f, "\tsub\t%r, %r, #%d\n",
15004 SP_REGNUM, SP_REGNUM,
15005 current_function_pretend_args_size);
15007 /* We don't need to record the stores for unwinding (would it
15008 help the debugger any if we did?), but record the change in
15009 the stack pointer. */
15010 if (dwarf2out_do_frame ())
15012 char *l = dwarf2out_cfi_label ();
15014 cfa_offset = cfa_offset + current_function_pretend_args_size;
15015 dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset);
15019 /* Get the registers we are going to push. */
15020 live_regs_mask = thumb1_compute_save_reg_mask ();
15021 /* Extract a mask of the ones we can give to the Thumb's push instruction. */
15022 l_mask = live_regs_mask & 0x40ff;
15023 /* Then count how many other high registers will need to be pushed. */
15024 high_regs_pushed = bit_count (live_regs_mask & 0x0f00);
15026 if (TARGET_BACKTRACE)
15029 unsigned work_register;
15031 /* We have been asked to create a stack backtrace structure.
15032 The code looks like this:
15036 0 sub SP, #16 Reserve space for 4 registers.
15037 2 push {R7} Push low registers.
15038 4 add R7, SP, #20 Get the stack pointer before the push.
15039 6 str R7, [SP, #8] Store the stack pointer (before reserving the space).
15040 8 mov R7, PC Get hold of the start of this code plus 12.
15041 10 str R7, [SP, #16] Store it.
15042 12 mov R7, FP Get hold of the current frame pointer.
15043 14 str R7, [SP, #4] Store it.
15044 16 mov R7, LR Get hold of the current return address.
15045 18 str R7, [SP, #12] Store it.
15046 20 add R7, SP, #16 Point at the start of the backtrace structure.
15047 22 mov FP, R7 Put this value into the frame pointer. */
15049 work_register = thumb_find_work_register (live_regs_mask);
15051 if (ARM_EABI_UNWIND_TABLES)
15052 asm_fprintf (f, "\t.pad #16\n");
15055 (f, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n",
15056 SP_REGNUM, SP_REGNUM);
15058 if (dwarf2out_do_frame ())
15060 char *l = dwarf2out_cfi_label ();
15062 cfa_offset = cfa_offset + 16;
15063 dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset);
15068 thumb_pushpop (f, l_mask, 1, &cfa_offset, l_mask);
15069 offset = bit_count (l_mask) * UNITS_PER_WORD;
15074 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
15075 offset + 16 + current_function_pretend_args_size);
15077 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
15080 /* Make sure that the instruction fetching the PC is in the right place
15081 to calculate "start of backtrace creation code + 12". */
15084 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
15085 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
15087 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
15088 ARM_HARD_FRAME_POINTER_REGNUM);
15089 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
15094 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
15095 ARM_HARD_FRAME_POINTER_REGNUM);
15096 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
15098 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
15099 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
15103 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, LR_REGNUM);
15104 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
15106 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
15108 asm_fprintf (f, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n",
15109 ARM_HARD_FRAME_POINTER_REGNUM, work_register);
15111 /* Optimization: If we are not pushing any low registers but we are going
15112 to push some high registers then delay our first push. This will just
15113 be a push of LR and we can combine it with the push of the first high
15115 else if ((l_mask & 0xff) != 0
15116 || (high_regs_pushed == 0 && l_mask))
15117 thumb_pushpop (f, l_mask, 1, &cfa_offset, l_mask);
15119 if (high_regs_pushed)
15121 unsigned pushable_regs;
15122 unsigned next_hi_reg;
15124 for (next_hi_reg = 12; next_hi_reg > LAST_LO_REGNUM; next_hi_reg--)
15125 if (live_regs_mask & (1 << next_hi_reg))
15128 pushable_regs = l_mask & 0xff;
15130 if (pushable_regs == 0)
15131 pushable_regs = 1 << thumb_find_work_register (live_regs_mask);
15133 while (high_regs_pushed > 0)
15135 unsigned long real_regs_mask = 0;
15137 for (regno = LAST_LO_REGNUM; regno >= 0; regno --)
15139 if (pushable_regs & (1 << regno))
15141 asm_fprintf (f, "\tmov\t%r, %r\n", regno, next_hi_reg);
15143 high_regs_pushed --;
15144 real_regs_mask |= (1 << next_hi_reg);
15146 if (high_regs_pushed)
15148 for (next_hi_reg --; next_hi_reg > LAST_LO_REGNUM;
15150 if (live_regs_mask & (1 << next_hi_reg))
15155 pushable_regs &= ~((1 << regno) - 1);
15161 /* If we had to find a work register and we have not yet
15162 saved the LR then add it to the list of regs to push. */
15163 if (l_mask == (1 << LR_REGNUM))
15165 thumb_pushpop (f, pushable_regs | (1 << LR_REGNUM),
15167 real_regs_mask | (1 << LR_REGNUM));
15171 thumb_pushpop (f, pushable_regs, 1, &cfa_offset, real_regs_mask);
15176 /* Handle the case of a double word load into a low register from
15177 a computed memory address. The computed address may involve a
15178 register which is overwritten by the load. */
15180 thumb_load_double_from_address (rtx *operands)
15188 gcc_assert (GET_CODE (operands[0]) == REG);
15189 gcc_assert (GET_CODE (operands[1]) == MEM);
15191 /* Get the memory address. */
15192 addr = XEXP (operands[1], 0);
15194 /* Work out how the memory address is computed. */
15195 switch (GET_CODE (addr))
15198 operands[2] = adjust_address (operands[1], SImode, 4);
15200 if (REGNO (operands[0]) == REGNO (addr))
15202 output_asm_insn ("ldr\t%H0, %2", operands);
15203 output_asm_insn ("ldr\t%0, %1", operands);
15207 output_asm_insn ("ldr\t%0, %1", operands);
15208 output_asm_insn ("ldr\t%H0, %2", operands);
15213 /* Compute <address> + 4 for the high order load. */
15214 operands[2] = adjust_address (operands[1], SImode, 4);
15216 output_asm_insn ("ldr\t%0, %1", operands);
15217 output_asm_insn ("ldr\t%H0, %2", operands);
15221 arg1 = XEXP (addr, 0);
15222 arg2 = XEXP (addr, 1);
15224 if (CONSTANT_P (arg1))
15225 base = arg2, offset = arg1;
15227 base = arg1, offset = arg2;
15229 gcc_assert (GET_CODE (base) == REG);
15231 /* Catch the case of <address> = <reg> + <reg> */
15232 if (GET_CODE (offset) == REG)
15234 int reg_offset = REGNO (offset);
15235 int reg_base = REGNO (base);
15236 int reg_dest = REGNO (operands[0]);
15238 /* Add the base and offset registers together into the
15239 higher destination register. */
15240 asm_fprintf (asm_out_file, "\tadd\t%r, %r, %r",
15241 reg_dest + 1, reg_base, reg_offset);
15243 /* Load the lower destination register from the address in
15244 the higher destination register. */
15245 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #0]",
15246 reg_dest, reg_dest + 1);
15248 /* Load the higher destination register from its own address
15250 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #4]",
15251 reg_dest + 1, reg_dest + 1);
15255 /* Compute <address> + 4 for the high order load. */
15256 operands[2] = adjust_address (operands[1], SImode, 4);
15258 /* If the computed address is held in the low order register
15259 then load the high order register first, otherwise always
15260 load the low order register first. */
15261 if (REGNO (operands[0]) == REGNO (base))
15263 output_asm_insn ("ldr\t%H0, %2", operands);
15264 output_asm_insn ("ldr\t%0, %1", operands);
15268 output_asm_insn ("ldr\t%0, %1", operands);
15269 output_asm_insn ("ldr\t%H0, %2", operands);
15275 /* With no registers to worry about we can just load the value
15277 operands[2] = adjust_address (operands[1], SImode, 4);
15279 output_asm_insn ("ldr\t%H0, %2", operands);
15280 output_asm_insn ("ldr\t%0, %1", operands);
15284 gcc_unreachable ();
15291 thumb_output_move_mem_multiple (int n, rtx *operands)
15298 if (REGNO (operands[4]) > REGNO (operands[5]))
15301 operands[4] = operands[5];
15304 output_asm_insn ("ldmia\t%1!, {%4, %5}", operands);
15305 output_asm_insn ("stmia\t%0!, {%4, %5}", operands);
15309 if (REGNO (operands[4]) > REGNO (operands[5]))
15312 operands[4] = operands[5];
15315 if (REGNO (operands[5]) > REGNO (operands[6]))
15318 operands[5] = operands[6];
15321 if (REGNO (operands[4]) > REGNO (operands[5]))
15324 operands[4] = operands[5];
15328 output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands);
15329 output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands);
15333 gcc_unreachable ();
15339 /* Output a call-via instruction for thumb state. */
15341 thumb_call_via_reg (rtx reg)
15343 int regno = REGNO (reg);
15346 gcc_assert (regno < LR_REGNUM);
15348 /* If we are in the normal text section we can use a single instance
15349 per compilation unit. If we are doing function sections, then we need
15350 an entry per section, since we can't rely on reachability. */
15351 if (in_section == text_section)
15353 thumb_call_reg_needed = 1;
15355 if (thumb_call_via_label[regno] == NULL)
15356 thumb_call_via_label[regno] = gen_label_rtx ();
15357 labelp = thumb_call_via_label + regno;
15361 if (cfun->machine->call_via[regno] == NULL)
15362 cfun->machine->call_via[regno] = gen_label_rtx ();
15363 labelp = cfun->machine->call_via + regno;
15366 output_asm_insn ("bl\t%a0", labelp);
15370 /* Routines for generating rtl. */
15372 thumb_expand_movmemqi (rtx *operands)
15374 rtx out = copy_to_mode_reg (SImode, XEXP (operands[0], 0));
15375 rtx in = copy_to_mode_reg (SImode, XEXP (operands[1], 0));
15376 HOST_WIDE_INT len = INTVAL (operands[2]);
15377 HOST_WIDE_INT offset = 0;
15381 emit_insn (gen_movmem12b (out, in, out, in));
15387 emit_insn (gen_movmem8b (out, in, out, in));
15393 rtx reg = gen_reg_rtx (SImode);
15394 emit_insn (gen_movsi (reg, gen_rtx_MEM (SImode, in)));
15395 emit_insn (gen_movsi (gen_rtx_MEM (SImode, out), reg));
15402 rtx reg = gen_reg_rtx (HImode);
15403 emit_insn (gen_movhi (reg, gen_rtx_MEM (HImode,
15404 plus_constant (in, offset))));
15405 emit_insn (gen_movhi (gen_rtx_MEM (HImode, plus_constant (out, offset)),
15413 rtx reg = gen_reg_rtx (QImode);
15414 emit_insn (gen_movqi (reg, gen_rtx_MEM (QImode,
15415 plus_constant (in, offset))));
15416 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (out, offset)),
15422 thumb_reload_out_hi (rtx *operands)
15424 emit_insn (gen_thumb_movhi_clobber (operands[0], operands[1], operands[2]));
15427 /* Handle reading a half-word from memory during reload. */
15429 thumb_reload_in_hi (rtx *operands ATTRIBUTE_UNUSED)
15431 gcc_unreachable ();
15434 /* Return the length of a function name prefix
15435 that starts with the character 'c'. */
15437 arm_get_strip_length (int c)
15441 ARM_NAME_ENCODING_LENGTHS
15446 /* Return a pointer to a function's name with any
15447 and all prefix encodings stripped from it. */
15449 arm_strip_name_encoding (const char *name)
15453 while ((skip = arm_get_strip_length (* name)))
15459 /* If there is a '*' anywhere in the name's prefix, then
15460 emit the stripped name verbatim, otherwise prepend an
15461 underscore if leading underscores are being used. */
15463 arm_asm_output_labelref (FILE *stream, const char *name)
15468 while ((skip = arm_get_strip_length (* name)))
15470 verbatim |= (*name == '*');
15475 fputs (name, stream);
15477 asm_fprintf (stream, "%U%s", name);
15481 arm_file_start (void)
15485 if (TARGET_UNIFIED_ASM)
15486 asm_fprintf (asm_out_file, "\t.syntax unified\n");
15490 const char *fpu_name;
15491 if (arm_select[0].string)
15492 asm_fprintf (asm_out_file, "\t.cpu %s\n", arm_select[0].string);
15493 else if (arm_select[1].string)
15494 asm_fprintf (asm_out_file, "\t.arch %s\n", arm_select[1].string);
15496 asm_fprintf (asm_out_file, "\t.cpu %s\n",
15497 all_cores[arm_default_cpu].name);
15499 if (TARGET_SOFT_FLOAT)
15502 fpu_name = "softvfp";
15504 fpu_name = "softfpa";
15508 int set_float_abi_attributes = 0;
15509 switch (arm_fpu_arch)
15514 case FPUTYPE_FPA_EMU2:
15517 case FPUTYPE_FPA_EMU3:
15520 case FPUTYPE_MAVERICK:
15521 fpu_name = "maverick";
15525 set_float_abi_attributes = 1;
15529 set_float_abi_attributes = 1;
15534 if (set_float_abi_attributes)
15536 if (TARGET_HARD_FLOAT)
15537 asm_fprintf (asm_out_file, "\t.eabi_attribute 27, 3\n");
15538 if (TARGET_HARD_FLOAT_ABI)
15539 asm_fprintf (asm_out_file, "\t.eabi_attribute 28, 1\n");
15542 asm_fprintf (asm_out_file, "\t.fpu %s\n", fpu_name);
15544 /* Some of these attributes only apply when the corresponding features
15545 are used. However we don't have any easy way of figuring this out.
15546 Conservatively record the setting that would have been used. */
15548 /* Tag_ABI_PCS_wchar_t. */
15549 asm_fprintf (asm_out_file, "\t.eabi_attribute 18, %d\n",
15550 (int)WCHAR_TYPE_SIZE / BITS_PER_UNIT);
15552 /* Tag_ABI_FP_rounding. */
15553 if (flag_rounding_math)
15554 asm_fprintf (asm_out_file, "\t.eabi_attribute 19, 1\n");
15555 if (!flag_unsafe_math_optimizations)
15557 /* Tag_ABI_FP_denomal. */
15558 asm_fprintf (asm_out_file, "\t.eabi_attribute 20, 1\n");
15559 /* Tag_ABI_FP_exceptions. */
15560 asm_fprintf (asm_out_file, "\t.eabi_attribute 21, 1\n");
15562 /* Tag_ABI_FP_user_exceptions. */
15563 if (flag_signaling_nans)
15564 asm_fprintf (asm_out_file, "\t.eabi_attribute 22, 1\n");
15565 /* Tag_ABI_FP_number_model. */
15566 asm_fprintf (asm_out_file, "\t.eabi_attribute 23, %d\n",
15567 flag_finite_math_only ? 1 : 3);
15569 /* Tag_ABI_align8_needed. */
15570 asm_fprintf (asm_out_file, "\t.eabi_attribute 24, 1\n");
15571 /* Tag_ABI_align8_preserved. */
15572 asm_fprintf (asm_out_file, "\t.eabi_attribute 25, 1\n");
15573 /* Tag_ABI_enum_size. */
15574 asm_fprintf (asm_out_file, "\t.eabi_attribute 26, %d\n",
15575 flag_short_enums ? 1 : 2);
15577 /* Tag_ABI_optimization_goals. */
15580 else if (optimize >= 2)
15586 asm_fprintf (asm_out_file, "\t.eabi_attribute 30, %d\n", val);
15588 default_file_start();
15592 arm_file_end (void)
15596 if (NEED_INDICATE_EXEC_STACK)
15597 /* Add .note.GNU-stack. */
15598 file_end_indicate_exec_stack ();
15600 if (! thumb_call_reg_needed)
15603 switch_to_section (text_section);
15604 asm_fprintf (asm_out_file, "\t.code 16\n");
15605 ASM_OUTPUT_ALIGN (asm_out_file, 1);
15607 for (regno = 0; regno < LR_REGNUM; regno++)
15609 rtx label = thumb_call_via_label[regno];
15613 targetm.asm_out.internal_label (asm_out_file, "L",
15614 CODE_LABEL_NUMBER (label));
15615 asm_fprintf (asm_out_file, "\tbx\t%r\n", regno);
15622 #ifdef AOF_ASSEMBLER
15623 /* Special functions only needed when producing AOF syntax assembler. */
15627 struct pic_chain * next;
15628 const char * symname;
15631 static struct pic_chain * aof_pic_chain = NULL;
15634 aof_pic_entry (rtx x)
15636 struct pic_chain ** chainp;
15639 if (aof_pic_label == NULL_RTX)
15641 aof_pic_label = gen_rtx_SYMBOL_REF (Pmode, "x$adcons");
15644 for (offset = 0, chainp = &aof_pic_chain; *chainp;
15645 offset += 4, chainp = &(*chainp)->next)
15646 if ((*chainp)->symname == XSTR (x, 0))
15647 return plus_constant (aof_pic_label, offset);
15649 *chainp = (struct pic_chain *) xmalloc (sizeof (struct pic_chain));
15650 (*chainp)->next = NULL;
15651 (*chainp)->symname = XSTR (x, 0);
15652 return plus_constant (aof_pic_label, offset);
15656 aof_dump_pic_table (FILE *f)
15658 struct pic_chain * chain;
15660 if (aof_pic_chain == NULL)
15663 asm_fprintf (f, "\tAREA |%r$$adcons|, BASED %r\n",
15664 PIC_OFFSET_TABLE_REGNUM,
15665 PIC_OFFSET_TABLE_REGNUM);
15666 fputs ("|x$adcons|\n", f);
15668 for (chain = aof_pic_chain; chain; chain = chain->next)
15670 fputs ("\tDCD\t", f);
15671 assemble_name (f, chain->symname);
15676 int arm_text_section_count = 1;
15678 /* A get_unnamed_section callback for switching to the text section. */
15681 aof_output_text_section_asm_op (const void *data ATTRIBUTE_UNUSED)
15683 fprintf (asm_out_file, "\tAREA |C$$code%d|, CODE, READONLY",
15684 arm_text_section_count++);
15686 fprintf (asm_out_file, ", PIC, REENTRANT");
15687 fprintf (asm_out_file, "\n");
15690 static int arm_data_section_count = 1;
15692 /* A get_unnamed_section callback for switching to the data section. */
15695 aof_output_data_section_asm_op (const void *data ATTRIBUTE_UNUSED)
15697 fprintf (asm_out_file, "\tAREA |C$$data%d|, DATA\n",
15698 arm_data_section_count++);
15701 /* Implement TARGET_ASM_INIT_SECTIONS.
15703 AOF Assembler syntax is a nightmare when it comes to areas, since once
15704 we change from one area to another, we can't go back again. Instead,
15705 we must create a new area with the same attributes and add the new output
15706 to that. Unfortunately, there is nothing we can do here to guarantee that
15707 two areas with the same attributes will be linked adjacently in the
15708 resulting executable, so we have to be careful not to do pc-relative
15709 addressing across such boundaries. */
15712 aof_asm_init_sections (void)
15714 text_section = get_unnamed_section (SECTION_CODE,
15715 aof_output_text_section_asm_op, NULL);
15716 data_section = get_unnamed_section (SECTION_WRITE,
15717 aof_output_data_section_asm_op, NULL);
15718 readonly_data_section = text_section;
15722 zero_init_section (void)
15724 static int zero_init_count = 1;
15726 fprintf (asm_out_file, "\tAREA |C$$zidata%d|,NOINIT\n", zero_init_count++);
15730 /* The AOF assembler is religiously strict about declarations of
15731 imported and exported symbols, so that it is impossible to declare
15732 a function as imported near the beginning of the file, and then to
15733 export it later on. It is, however, possible to delay the decision
15734 until all the functions in the file have been compiled. To get
15735 around this, we maintain a list of the imports and exports, and
15736 delete from it any that are subsequently defined. At the end of
15737 compilation we spit the remainder of the list out before the END
15742 struct import * next;
15746 static struct import * imports_list = NULL;
15749 aof_add_import (const char *name)
15751 struct import * new;
15753 for (new = imports_list; new; new = new->next)
15754 if (new->name == name)
15757 new = (struct import *) xmalloc (sizeof (struct import));
15758 new->next = imports_list;
15759 imports_list = new;
15764 aof_delete_import (const char *name)
15766 struct import ** old;
15768 for (old = &imports_list; *old; old = & (*old)->next)
15770 if ((*old)->name == name)
15772 *old = (*old)->next;
15778 int arm_main_function = 0;
15781 aof_dump_imports (FILE *f)
15783 /* The AOF assembler needs this to cause the startup code to be extracted
15784 from the library. Brining in __main causes the whole thing to work
15786 if (arm_main_function)
15788 switch_to_section (text_section);
15789 fputs ("\tIMPORT __main\n", f);
15790 fputs ("\tDCD __main\n", f);
15793 /* Now dump the remaining imports. */
15794 while (imports_list)
15796 fprintf (f, "\tIMPORT\t");
15797 assemble_name (f, imports_list->name);
15799 imports_list = imports_list->next;
15804 aof_globalize_label (FILE *stream, const char *name)
15806 default_globalize_label (stream, name);
15807 if (! strcmp (name, "main"))
15808 arm_main_function = 1;
15812 aof_file_start (void)
15814 fputs ("__r0\tRN\t0\n", asm_out_file);
15815 fputs ("__a1\tRN\t0\n", asm_out_file);
15816 fputs ("__a2\tRN\t1\n", asm_out_file);
15817 fputs ("__a3\tRN\t2\n", asm_out_file);
15818 fputs ("__a4\tRN\t3\n", asm_out_file);
15819 fputs ("__v1\tRN\t4\n", asm_out_file);
15820 fputs ("__v2\tRN\t5\n", asm_out_file);
15821 fputs ("__v3\tRN\t6\n", asm_out_file);
15822 fputs ("__v4\tRN\t7\n", asm_out_file);
15823 fputs ("__v5\tRN\t8\n", asm_out_file);
15824 fputs ("__v6\tRN\t9\n", asm_out_file);
15825 fputs ("__sl\tRN\t10\n", asm_out_file);
15826 fputs ("__fp\tRN\t11\n", asm_out_file);
15827 fputs ("__ip\tRN\t12\n", asm_out_file);
15828 fputs ("__sp\tRN\t13\n", asm_out_file);
15829 fputs ("__lr\tRN\t14\n", asm_out_file);
15830 fputs ("__pc\tRN\t15\n", asm_out_file);
15831 fputs ("__f0\tFN\t0\n", asm_out_file);
15832 fputs ("__f1\tFN\t1\n", asm_out_file);
15833 fputs ("__f2\tFN\t2\n", asm_out_file);
15834 fputs ("__f3\tFN\t3\n", asm_out_file);
15835 fputs ("__f4\tFN\t4\n", asm_out_file);
15836 fputs ("__f5\tFN\t5\n", asm_out_file);
15837 fputs ("__f6\tFN\t6\n", asm_out_file);
15838 fputs ("__f7\tFN\t7\n", asm_out_file);
15839 switch_to_section (text_section);
15843 aof_file_end (void)
15846 aof_dump_pic_table (asm_out_file);
15848 aof_dump_imports (asm_out_file);
15849 fputs ("\tEND\n", asm_out_file);
15851 #endif /* AOF_ASSEMBLER */
15854 /* Symbols in the text segment can be accessed without indirecting via the
15855 constant pool; it may take an extra binary operation, but this is still
15856 faster than indirecting via memory. Don't do this when not optimizing,
15857 since we won't be calculating al of the offsets necessary to do this
15861 arm_encode_section_info (tree decl, rtx rtl, int first)
15863 /* This doesn't work with AOF syntax, since the string table may be in
15864 a different AREA. */
15865 #ifndef AOF_ASSEMBLER
15866 if (optimize > 0 && TREE_CONSTANT (decl))
15867 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;
15870 default_encode_section_info (decl, rtl, first);
15872 #endif /* !ARM_PE */
15875 arm_internal_label (FILE *stream, const char *prefix, unsigned long labelno)
15877 if (arm_ccfsm_state == 3 && (unsigned) arm_target_label == labelno
15878 && !strcmp (prefix, "L"))
15880 arm_ccfsm_state = 0;
15881 arm_target_insn = NULL;
15883 default_internal_label (stream, prefix, labelno);
15886 /* Output code to add DELTA to the first argument, and then jump
15887 to FUNCTION. Used for C++ multiple inheritance. */
15889 arm_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
15890 HOST_WIDE_INT delta,
15891 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
15894 static int thunk_label = 0;
15897 int mi_delta = delta;
15898 const char *const mi_op = mi_delta < 0 ? "sub" : "add";
15900 int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)
15903 mi_delta = - mi_delta;
15904 /* When generating 16-bit thumb code, thunks are entered in arm mode. */
15907 int labelno = thunk_label++;
15908 ASM_GENERATE_INTERNAL_LABEL (label, "LTHUMBFUNC", labelno);
15909 fputs ("\tldr\tr12, ", file);
15910 assemble_name (file, label);
15911 fputc ('\n', file);
15914 /* If we are generating PIC, the ldr instruction below loads
15915 "(target - 7) - .LTHUNKPCn" into r12. The pc reads as
15916 the address of the add + 8, so we have:
15918 r12 = (target - 7) - .LTHUNKPCn + (.LTHUNKPCn + 8)
15921 Note that we have "+ 1" because some versions of GNU ld
15922 don't set the low bit of the result for R_ARM_REL32
15923 relocations against thumb function symbols. */
15924 ASM_GENERATE_INTERNAL_LABEL (labelpc, "LTHUNKPC", labelno);
15925 assemble_name (file, labelpc);
15926 fputs (":\n", file);
15927 fputs ("\tadd\tr12, pc, r12\n", file);
15930 /* TODO: Use movw/movt for large constants when available. */
15931 while (mi_delta != 0)
15933 if ((mi_delta & (3 << shift)) == 0)
15937 asm_fprintf (file, "\t%s\t%r, %r, #%d\n",
15938 mi_op, this_regno, this_regno,
15939 mi_delta & (0xff << shift));
15940 mi_delta &= ~(0xff << shift);
15946 fprintf (file, "\tbx\tr12\n");
15947 ASM_OUTPUT_ALIGN (file, 2);
15948 assemble_name (file, label);
15949 fputs (":\n", file);
15952 /* Output ".word .LTHUNKn-7-.LTHUNKPCn". */
15953 rtx tem = XEXP (DECL_RTL (function), 0);
15954 tem = gen_rtx_PLUS (GET_MODE (tem), tem, GEN_INT (-7));
15955 tem = gen_rtx_MINUS (GET_MODE (tem),
15957 gen_rtx_SYMBOL_REF (Pmode,
15958 ggc_strdup (labelpc)));
15959 assemble_integer (tem, 4, BITS_PER_WORD, 1);
15962 /* Output ".word .LTHUNKn". */
15963 assemble_integer (XEXP (DECL_RTL (function), 0), 4, BITS_PER_WORD, 1);
15967 fputs ("\tb\t", file);
15968 assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0));
15969 if (NEED_PLT_RELOC)
15970 fputs ("(PLT)", file);
15971 fputc ('\n', file);
15976 arm_emit_vector_const (FILE *file, rtx x)
15979 const char * pattern;
15981 gcc_assert (GET_CODE (x) == CONST_VECTOR);
15983 switch (GET_MODE (x))
15985 case V2SImode: pattern = "%08x"; break;
15986 case V4HImode: pattern = "%04x"; break;
15987 case V8QImode: pattern = "%02x"; break;
15988 default: gcc_unreachable ();
15991 fprintf (file, "0x");
15992 for (i = CONST_VECTOR_NUNITS (x); i--;)
15996 element = CONST_VECTOR_ELT (x, i);
15997 fprintf (file, pattern, INTVAL (element));
16004 arm_output_load_gr (rtx *operands)
16011 if (GET_CODE (operands [1]) != MEM
16012 || GET_CODE (sum = XEXP (operands [1], 0)) != PLUS
16013 || GET_CODE (reg = XEXP (sum, 0)) != REG
16014 || GET_CODE (offset = XEXP (sum, 1)) != CONST_INT
16015 || ((INTVAL (offset) < 1024) && (INTVAL (offset) > -1024)))
16016 return "wldrw%?\t%0, %1";
16018 /* Fix up an out-of-range load of a GR register. */
16019 output_asm_insn ("str%?\t%0, [sp, #-4]!\t@ Start of GR load expansion", & reg);
16020 wcgr = operands[0];
16022 output_asm_insn ("ldr%?\t%0, %1", operands);
16024 operands[0] = wcgr;
16026 output_asm_insn ("tmcr%?\t%0, %1", operands);
16027 output_asm_insn ("ldr%?\t%0, [sp], #4\t@ End of GR load expansion", & reg);
16032 /* Worker function for TARGET_SETUP_INCOMING_VARARGS.
16034 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
16035 named arg and all anonymous args onto the stack.
16036 XXX I know the prologue shouldn't be pushing registers, but it is faster
16040 arm_setup_incoming_varargs (CUMULATIVE_ARGS *cum,
16041 enum machine_mode mode ATTRIBUTE_UNUSED,
16042 tree type ATTRIBUTE_UNUSED,
16044 int second_time ATTRIBUTE_UNUSED)
16046 cfun->machine->uses_anonymous_args = 1;
16047 if (cum->nregs < NUM_ARG_REGS)
16048 *pretend_size = (NUM_ARG_REGS - cum->nregs) * UNITS_PER_WORD;
16051 /* Return nonzero if the CONSUMER instruction (a store) does not need
16052 PRODUCER's value to calculate the address. */
16055 arm_no_early_store_addr_dep (rtx producer, rtx consumer)
16057 rtx value = PATTERN (producer);
16058 rtx addr = PATTERN (consumer);
16060 if (GET_CODE (value) == COND_EXEC)
16061 value = COND_EXEC_CODE (value);
16062 if (GET_CODE (value) == PARALLEL)
16063 value = XVECEXP (value, 0, 0);
16064 value = XEXP (value, 0);
16065 if (GET_CODE (addr) == COND_EXEC)
16066 addr = COND_EXEC_CODE (addr);
16067 if (GET_CODE (addr) == PARALLEL)
16068 addr = XVECEXP (addr, 0, 0);
16069 addr = XEXP (addr, 0);
16071 return !reg_overlap_mentioned_p (value, addr);
16074 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
16075 have an early register shift value or amount dependency on the
16076 result of PRODUCER. */
16079 arm_no_early_alu_shift_dep (rtx producer, rtx consumer)
16081 rtx value = PATTERN (producer);
16082 rtx op = PATTERN (consumer);
16085 if (GET_CODE (value) == COND_EXEC)
16086 value = COND_EXEC_CODE (value);
16087 if (GET_CODE (value) == PARALLEL)
16088 value = XVECEXP (value, 0, 0);
16089 value = XEXP (value, 0);
16090 if (GET_CODE (op) == COND_EXEC)
16091 op = COND_EXEC_CODE (op);
16092 if (GET_CODE (op) == PARALLEL)
16093 op = XVECEXP (op, 0, 0);
16096 early_op = XEXP (op, 0);
16097 /* This is either an actual independent shift, or a shift applied to
16098 the first operand of another operation. We want the whole shift
16100 if (GET_CODE (early_op) == REG)
16103 return !reg_overlap_mentioned_p (value, early_op);
16106 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
16107 have an early register shift value dependency on the result of
16111 arm_no_early_alu_shift_value_dep (rtx producer, rtx consumer)
16113 rtx value = PATTERN (producer);
16114 rtx op = PATTERN (consumer);
16117 if (GET_CODE (value) == COND_EXEC)
16118 value = COND_EXEC_CODE (value);
16119 if (GET_CODE (value) == PARALLEL)
16120 value = XVECEXP (value, 0, 0);
16121 value = XEXP (value, 0);
16122 if (GET_CODE (op) == COND_EXEC)
16123 op = COND_EXEC_CODE (op);
16124 if (GET_CODE (op) == PARALLEL)
16125 op = XVECEXP (op, 0, 0);
16128 early_op = XEXP (op, 0);
16130 /* This is either an actual independent shift, or a shift applied to
16131 the first operand of another operation. We want the value being
16132 shifted, in either case. */
16133 if (GET_CODE (early_op) != REG)
16134 early_op = XEXP (early_op, 0);
16136 return !reg_overlap_mentioned_p (value, early_op);
16139 /* Return nonzero if the CONSUMER (a mul or mac op) does not
16140 have an early register mult dependency on the result of
16144 arm_no_early_mul_dep (rtx producer, rtx consumer)
16146 rtx value = PATTERN (producer);
16147 rtx op = PATTERN (consumer);
16149 if (GET_CODE (value) == COND_EXEC)
16150 value = COND_EXEC_CODE (value);
16151 if (GET_CODE (value) == PARALLEL)
16152 value = XVECEXP (value, 0, 0);
16153 value = XEXP (value, 0);
16154 if (GET_CODE (op) == COND_EXEC)
16155 op = COND_EXEC_CODE (op);
16156 if (GET_CODE (op) == PARALLEL)
16157 op = XVECEXP (op, 0, 0);
16160 return (GET_CODE (op) == PLUS
16161 && !reg_overlap_mentioned_p (value, XEXP (op, 0)));
16165 /* We can't rely on the caller doing the proper promotion when
16166 using APCS or ATPCS. */
16169 arm_promote_prototypes (tree t ATTRIBUTE_UNUSED)
16171 return !TARGET_AAPCS_BASED;
16175 /* AAPCS based ABIs use short enums by default. */
16178 arm_default_short_enums (void)
16180 return TARGET_AAPCS_BASED && arm_abi != ARM_ABI_AAPCS_LINUX;
16184 /* AAPCS requires that anonymous bitfields affect structure alignment. */
16187 arm_align_anon_bitfield (void)
16189 return TARGET_AAPCS_BASED;
16193 /* The generic C++ ABI says 64-bit (long long). The EABI says 32-bit. */
16196 arm_cxx_guard_type (void)
16198 return TARGET_AAPCS_BASED ? integer_type_node : long_long_integer_type_node;
16202 /* The EABI says test the least significant bit of a guard variable. */
16205 arm_cxx_guard_mask_bit (void)
16207 return TARGET_AAPCS_BASED;
16211 /* The EABI specifies that all array cookies are 8 bytes long. */
16214 arm_get_cookie_size (tree type)
16218 if (!TARGET_AAPCS_BASED)
16219 return default_cxx_get_cookie_size (type);
16221 size = build_int_cst (sizetype, 8);
16226 /* The EABI says that array cookies should also contain the element size. */
16229 arm_cookie_has_size (void)
16231 return TARGET_AAPCS_BASED;
16235 /* The EABI says constructors and destructors should return a pointer to
16236 the object constructed/destroyed. */
16239 arm_cxx_cdtor_returns_this (void)
16241 return TARGET_AAPCS_BASED;
16244 /* The EABI says that an inline function may never be the key
16248 arm_cxx_key_method_may_be_inline (void)
16250 return !TARGET_AAPCS_BASED;
16254 arm_cxx_determine_class_data_visibility (tree decl)
16256 if (!TARGET_AAPCS_BASED)
16259 /* In general, \S 3.2.5.5 of the ARM EABI requires that class data
16260 is exported. However, on systems without dynamic vague linkage,
16261 \S 3.2.5.6 says that COMDAT class data has hidden linkage. */
16262 if (!TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P && DECL_COMDAT (decl))
16263 DECL_VISIBILITY (decl) = VISIBILITY_HIDDEN;
16265 DECL_VISIBILITY (decl) = VISIBILITY_DEFAULT;
16266 DECL_VISIBILITY_SPECIFIED (decl) = 1;
16270 arm_cxx_class_data_always_comdat (void)
16272 /* \S 3.2.5.4 of the ARM C++ ABI says that class data only have
16273 vague linkage if the class has no key function. */
16274 return !TARGET_AAPCS_BASED;
16278 /* The EABI says __aeabi_atexit should be used to register static
16282 arm_cxx_use_aeabi_atexit (void)
16284 return TARGET_AAPCS_BASED;
16289 arm_set_return_address (rtx source, rtx scratch)
16291 arm_stack_offsets *offsets;
16292 HOST_WIDE_INT delta;
16294 unsigned long saved_regs;
16296 saved_regs = arm_compute_save_reg_mask ();
16298 if ((saved_regs & (1 << LR_REGNUM)) == 0)
16299 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNUM), source);
16302 if (frame_pointer_needed)
16303 addr = plus_constant(hard_frame_pointer_rtx, -4);
16306 /* LR will be the first saved register. */
16307 offsets = arm_get_frame_offsets ();
16308 delta = offsets->outgoing_args - (offsets->frame + 4);
16313 emit_insn (gen_addsi3 (scratch, stack_pointer_rtx,
16314 GEN_INT (delta & ~4095)));
16319 addr = stack_pointer_rtx;
16321 addr = plus_constant (addr, delta);
16323 emit_move_insn (gen_frame_mem (Pmode, addr), source);
16329 thumb_set_return_address (rtx source, rtx scratch)
16331 arm_stack_offsets *offsets;
16332 HOST_WIDE_INT delta;
16333 HOST_WIDE_INT limit;
16336 unsigned long mask;
16338 emit_insn (gen_rtx_USE (VOIDmode, source));
16340 mask = thumb1_compute_save_reg_mask ();
16341 if (mask & (1 << LR_REGNUM))
16343 offsets = arm_get_frame_offsets ();
16346 /* Find the saved regs. */
16347 if (frame_pointer_needed)
16349 delta = offsets->soft_frame - offsets->saved_args;
16350 reg = THUMB_HARD_FRAME_POINTER_REGNUM;
16356 delta = offsets->outgoing_args - offsets->saved_args;
16359 /* Allow for the stack frame. */
16360 if (TARGET_THUMB1 && TARGET_BACKTRACE)
16362 /* The link register is always the first saved register. */
16365 /* Construct the address. */
16366 addr = gen_rtx_REG (SImode, reg);
16369 emit_insn (gen_movsi (scratch, GEN_INT (delta)));
16370 emit_insn (gen_addsi3 (scratch, scratch, stack_pointer_rtx));
16374 addr = plus_constant (addr, delta);
16376 emit_move_insn (gen_frame_mem (Pmode, addr), source);
16379 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNUM), source);
16382 /* Implements target hook vector_mode_supported_p. */
16384 arm_vector_mode_supported_p (enum machine_mode mode)
16386 if ((mode == V2SImode)
16387 || (mode == V4HImode)
16388 || (mode == V8QImode))
16394 /* Implement TARGET_SHIFT_TRUNCATION_MASK. SImode shifts use normal
16395 ARM insns and therefore guarantee that the shift count is modulo 256.
16396 DImode shifts (those implemented by lib1funcs.asm or by optabs.c)
16397 guarantee no particular behavior for out-of-range counts. */
16399 static unsigned HOST_WIDE_INT
16400 arm_shift_truncation_mask (enum machine_mode mode)
16402 return mode == SImode ? 255 : 0;
16406 /* Map internal gcc register numbers to DWARF2 register numbers. */
16409 arm_dbx_register_number (unsigned int regno)
16414 /* TODO: Legacy targets output FPA regs as registers 16-23 for backwards
16415 compatibility. The EABI defines them as registers 96-103. */
16416 if (IS_FPA_REGNUM (regno))
16417 return (TARGET_AAPCS_BASED ? 96 : 16) + regno - FIRST_FPA_REGNUM;
16419 /* FIXME: VFPv3 register numbering. */
16420 if (IS_VFP_REGNUM (regno))
16421 return 64 + regno - FIRST_VFP_REGNUM;
16423 if (IS_IWMMXT_GR_REGNUM (regno))
16424 return 104 + regno - FIRST_IWMMXT_GR_REGNUM;
16426 if (IS_IWMMXT_REGNUM (regno))
16427 return 112 + regno - FIRST_IWMMXT_REGNUM;
16429 gcc_unreachable ();
16433 #ifdef TARGET_UNWIND_INFO
16434 /* Emit unwind directives for a store-multiple instruction or stack pointer
16435 push during alignment.
16436 These should only ever be generated by the function prologue code, so
16437 expect them to have a particular form. */
16440 arm_unwind_emit_sequence (FILE * asm_out_file, rtx p)
16443 HOST_WIDE_INT offset;
16444 HOST_WIDE_INT nregs;
16450 e = XVECEXP (p, 0, 0);
16451 if (GET_CODE (e) != SET)
16454 /* First insn will adjust the stack pointer. */
16455 if (GET_CODE (e) != SET
16456 || GET_CODE (XEXP (e, 0)) != REG
16457 || REGNO (XEXP (e, 0)) != SP_REGNUM
16458 || GET_CODE (XEXP (e, 1)) != PLUS)
16461 offset = -INTVAL (XEXP (XEXP (e, 1), 1));
16462 nregs = XVECLEN (p, 0) - 1;
16464 reg = REGNO (XEXP (XVECEXP (p, 0, 1), 1));
16467 /* The function prologue may also push pc, but not annotate it as it is
16468 never restored. We turn this into a stack pointer adjustment. */
16469 if (nregs * 4 == offset - 4)
16471 fprintf (asm_out_file, "\t.pad #4\n");
16475 fprintf (asm_out_file, "\t.save {");
16477 else if (IS_VFP_REGNUM (reg))
16480 fprintf (asm_out_file, "\t.vsave {");
16482 else if (reg >= FIRST_FPA_REGNUM && reg <= LAST_FPA_REGNUM)
16484 /* FPA registers are done differently. */
16485 asm_fprintf (asm_out_file, "\t.save %r, %wd\n", reg, nregs);
16489 /* Unknown register type. */
16492 /* If the stack increment doesn't match the size of the saved registers,
16493 something has gone horribly wrong. */
16494 if (offset != nregs * reg_size)
16499 /* The remaining insns will describe the stores. */
16500 for (i = 1; i <= nregs; i++)
16502 /* Expect (set (mem <addr>) (reg)).
16503 Where <addr> is (reg:SP) or (plus (reg:SP) (const_int)). */
16504 e = XVECEXP (p, 0, i);
16505 if (GET_CODE (e) != SET
16506 || GET_CODE (XEXP (e, 0)) != MEM
16507 || GET_CODE (XEXP (e, 1)) != REG)
16510 reg = REGNO (XEXP (e, 1));
16515 fprintf (asm_out_file, ", ");
16516 /* We can't use %r for vfp because we need to use the
16517 double precision register names. */
16518 if (IS_VFP_REGNUM (reg))
16519 asm_fprintf (asm_out_file, "d%d", (reg - FIRST_VFP_REGNUM) / 2);
16521 asm_fprintf (asm_out_file, "%r", reg);
16523 #ifdef ENABLE_CHECKING
16524 /* Check that the addresses are consecutive. */
16525 e = XEXP (XEXP (e, 0), 0);
16526 if (GET_CODE (e) == PLUS)
16528 offset += reg_size;
16529 if (GET_CODE (XEXP (e, 0)) != REG
16530 || REGNO (XEXP (e, 0)) != SP_REGNUM
16531 || GET_CODE (XEXP (e, 1)) != CONST_INT
16532 || offset != INTVAL (XEXP (e, 1)))
16536 || GET_CODE (e) != REG
16537 || REGNO (e) != SP_REGNUM)
16541 fprintf (asm_out_file, "}\n");
16544 /* Emit unwind directives for a SET. */
16547 arm_unwind_emit_set (FILE * asm_out_file, rtx p)
16555 switch (GET_CODE (e0))
16558 /* Pushing a single register. */
16559 if (GET_CODE (XEXP (e0, 0)) != PRE_DEC
16560 || GET_CODE (XEXP (XEXP (e0, 0), 0)) != REG
16561 || REGNO (XEXP (XEXP (e0, 0), 0)) != SP_REGNUM)
16564 asm_fprintf (asm_out_file, "\t.save ");
16565 if (IS_VFP_REGNUM (REGNO (e1)))
16566 asm_fprintf(asm_out_file, "{d%d}\n",
16567 (REGNO (e1) - FIRST_VFP_REGNUM) / 2);
16569 asm_fprintf(asm_out_file, "{%r}\n", REGNO (e1));
16573 if (REGNO (e0) == SP_REGNUM)
16575 /* A stack increment. */
16576 if (GET_CODE (e1) != PLUS
16577 || GET_CODE (XEXP (e1, 0)) != REG
16578 || REGNO (XEXP (e1, 0)) != SP_REGNUM
16579 || GET_CODE (XEXP (e1, 1)) != CONST_INT)
16582 asm_fprintf (asm_out_file, "\t.pad #%wd\n",
16583 -INTVAL (XEXP (e1, 1)));
16585 else if (REGNO (e0) == HARD_FRAME_POINTER_REGNUM)
16587 HOST_WIDE_INT offset;
16589 if (GET_CODE (e1) == PLUS)
16591 if (GET_CODE (XEXP (e1, 0)) != REG
16592 || GET_CODE (XEXP (e1, 1)) != CONST_INT)
16594 reg = REGNO (XEXP (e1, 0));
16595 offset = INTVAL (XEXP (e1, 1));
16596 asm_fprintf (asm_out_file, "\t.setfp %r, %r, #%wd\n",
16597 HARD_FRAME_POINTER_REGNUM, reg,
16598 INTVAL (XEXP (e1, 1)));
16600 else if (GET_CODE (e1) == REG)
16603 asm_fprintf (asm_out_file, "\t.setfp %r, %r\n",
16604 HARD_FRAME_POINTER_REGNUM, reg);
16609 else if (GET_CODE (e1) == REG && REGNO (e1) == SP_REGNUM)
16611 /* Move from sp to reg. */
16612 asm_fprintf (asm_out_file, "\t.movsp %r\n", REGNO (e0));
16614 else if (GET_CODE (e1) == PLUS
16615 && GET_CODE (XEXP (e1, 0)) == REG
16616 && REGNO (XEXP (e1, 0)) == SP_REGNUM
16617 && GET_CODE (XEXP (e1, 1)) == CONST_INT)
16619 /* Set reg to offset from sp. */
16620 asm_fprintf (asm_out_file, "\t.movsp %r, #%d\n",
16621 REGNO (e0), (int)INTVAL(XEXP (e1, 1)));
16623 else if (GET_CODE (e1) == UNSPEC && XINT (e1, 1) == UNSPEC_STACK_ALIGN)
16625 /* Stack pointer save before alignment. */
16627 asm_fprintf (asm_out_file, "\t.unwind_raw 0, 0x%x @ vsp = r%d\n",
16640 /* Emit unwind directives for the given insn. */
16643 arm_unwind_emit (FILE * asm_out_file, rtx insn)
16647 if (!ARM_EABI_UNWIND_TABLES)
16650 if (GET_CODE (insn) == NOTE || !RTX_FRAME_RELATED_P (insn))
16653 pat = find_reg_note (insn, REG_FRAME_RELATED_EXPR, NULL_RTX);
16655 pat = XEXP (pat, 0);
16657 pat = PATTERN (insn);
16659 switch (GET_CODE (pat))
16662 arm_unwind_emit_set (asm_out_file, pat);
16666 /* Store multiple. */
16667 arm_unwind_emit_sequence (asm_out_file, pat);
16676 /* Output a reference from a function exception table to the type_info
16677 object X. The EABI specifies that the symbol should be relocated by
16678 an R_ARM_TARGET2 relocation. */
16681 arm_output_ttype (rtx x)
16683 fputs ("\t.word\t", asm_out_file);
16684 output_addr_const (asm_out_file, x);
16685 /* Use special relocations for symbol references. */
16686 if (GET_CODE (x) != CONST_INT)
16687 fputs ("(TARGET2)", asm_out_file);
16688 fputc ('\n', asm_out_file);
16692 #endif /* TARGET_UNWIND_INFO */
16695 /* Handle UNSPEC DWARF call frame instructions. These are needed for dynamic
16696 stack alignment. */
16699 arm_dwarf_handle_frame_unspec (const char *label, rtx pattern, int index)
16701 rtx unspec = SET_SRC (pattern);
16702 gcc_assert (GET_CODE (unspec) == UNSPEC);
16706 case UNSPEC_STACK_ALIGN:
16707 /* ??? We should set the CFA = (SP & ~7). At this point we haven't
16708 put anything on the stack, so hopefully it won't matter.
16709 CFA = SP will be correct after alignment. */
16710 dwarf2out_reg_save_reg (label, stack_pointer_rtx,
16711 SET_DEST (pattern));
16714 gcc_unreachable ();
16719 /* Output unwind directives for the start/end of a function. */
16722 arm_output_fn_unwind (FILE * f, bool prologue)
16724 if (!ARM_EABI_UNWIND_TABLES)
16728 fputs ("\t.fnstart\n", f);
16730 fputs ("\t.fnend\n", f);
16734 arm_emit_tls_decoration (FILE *fp, rtx x)
16736 enum tls_reloc reloc;
16739 val = XVECEXP (x, 0, 0);
16740 reloc = INTVAL (XVECEXP (x, 0, 1));
16742 output_addr_const (fp, val);
16747 fputs ("(tlsgd)", fp);
16750 fputs ("(tlsldm)", fp);
16753 fputs ("(tlsldo)", fp);
16756 fputs ("(gottpoff)", fp);
16759 fputs ("(tpoff)", fp);
16762 gcc_unreachable ();
16770 fputs (" + (. - ", fp);
16771 output_addr_const (fp, XVECEXP (x, 0, 2));
16773 output_addr_const (fp, XVECEXP (x, 0, 3));
16783 /* ARM implementation of TARGET_ASM_OUTPUT_DWARF_DTPREL. */
16786 arm_output_dwarf_dtprel (FILE *file, int size, rtx x)
16788 gcc_assert (size == 4);
16789 fputs ("\t.word\t", file);
16790 output_addr_const (file, x);
16791 fputs ("(tlsldo)", file);
16795 arm_output_addr_const_extra (FILE *fp, rtx x)
16797 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLS)
16798 return arm_emit_tls_decoration (fp, x);
16799 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_PIC_LABEL)
16802 int labelno = INTVAL (XVECEXP (x, 0, 0));
16804 ASM_GENERATE_INTERNAL_LABEL (label, "LPIC", labelno);
16805 assemble_name_raw (fp, label);
16809 else if (GET_CODE (x) == CONST_VECTOR)
16810 return arm_emit_vector_const (fp, x);
16815 /* Output assembly for a shift instruction.
16816 SET_FLAGS determines how the instruction modifies the condition codes.
16817 0 - Do not set condition codes.
16818 1 - Set condition codes.
16819 2 - Use smallest instruction. */
16821 arm_output_shift(rtx * operands, int set_flags)
16824 static const char flag_chars[3] = {'?', '.', '!'};
16829 c = flag_chars[set_flags];
16830 if (TARGET_UNIFIED_ASM)
16832 shift = shift_op(operands[3], &val);
16836 operands[2] = GEN_INT(val);
16837 sprintf (pattern, "%s%%%c\t%%0, %%1, %%2", shift, c);
16840 sprintf (pattern, "mov%%%c\t%%0, %%1", c);
16843 sprintf (pattern, "mov%%%c\t%%0, %%1%%S3", c);
16844 output_asm_insn (pattern, operands);
16848 /* Output a Thumb-2 casesi instruction. */
16850 thumb2_output_casesi (rtx *operands)
16852 rtx diff_vec = PATTERN (next_real_insn (operands[2]));
16854 gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC);
16856 output_asm_insn ("cmp\t%0, %1", operands);
16857 output_asm_insn ("bhi\t%l3", operands);
16858 switch (GET_MODE(diff_vec))
16861 return "tbb\t[%|pc, %0]";
16863 return "tbh\t[%|pc, %0, lsl #1]";
16867 output_asm_insn ("adr\t%4, %l2", operands);
16868 output_asm_insn ("ldr\t%5, [%4, %0, lsl #2]", operands);
16869 output_asm_insn ("add\t%4, %4, %5", operands);
16874 output_asm_insn ("adr\t%4, %l2", operands);
16875 return "ldr\t%|pc, [%4, %0, lsl #2]";
16878 gcc_unreachable ();
16882 #include "gt-arm.h"