1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
3 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it
11 under the terms of the GNU General Public License as published
12 by the Free Software Foundation; either version 2, or (at your
13 option) any later version.
15 GCC is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
27 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
38 #include "insn-attr.h"
49 #include "integrate.h"
52 #include "target-def.h"
54 /* Forward definitions of types. */
55 typedef struct minipool_node Mnode;
56 typedef struct minipool_fixup Mfix;
58 const struct attribute_spec arm_attribute_table[];
60 /* Forward function declarations. */
61 static void arm_add_gc_roots (void);
62 static int arm_gen_constant (enum rtx_code, enum machine_mode, HOST_WIDE_INT,
64 static unsigned bit_count (unsigned long);
65 static int arm_address_register_rtx_p (rtx, int);
66 static int arm_legitimate_index_p (enum machine_mode, rtx, int);
67 static int thumb_base_register_rtx_p (rtx, enum machine_mode, int);
68 inline static int thumb_index_register_rtx_p (rtx, int);
69 static int const_ok_for_op (HOST_WIDE_INT, enum rtx_code);
70 static rtx emit_multi_reg_push (int);
71 static rtx emit_sfm (int, int);
73 static bool arm_assemble_integer (rtx, unsigned int, int);
75 static const char *fp_const_from_val (REAL_VALUE_TYPE *);
76 static arm_cc get_arm_condition_code (rtx);
77 static void init_fpa_table (void);
78 static HOST_WIDE_INT int_log2 (HOST_WIDE_INT);
79 static rtx is_jump_table (rtx);
80 static const char *output_multi_immediate (rtx *, const char *, const char *,
82 static void print_multi_reg (FILE *, const char *, int, int);
83 static const char *shift_op (rtx, HOST_WIDE_INT *);
84 static struct machine_function *arm_init_machine_status (void);
85 static int number_of_first_bit_set (int);
86 static void replace_symbols_in_block (tree, rtx, rtx);
87 static void thumb_exit (FILE *, int, rtx);
88 static void thumb_pushpop (FILE *, int, int);
89 static rtx is_jump_table (rtx);
90 static HOST_WIDE_INT get_jump_table_size (rtx);
91 static Mnode *move_minipool_fix_forward_ref (Mnode *, Mnode *, HOST_WIDE_INT);
92 static Mnode *add_minipool_forward_ref (Mfix *);
93 static Mnode *move_minipool_fix_backward_ref (Mnode *, Mnode *, HOST_WIDE_INT);
94 static Mnode *add_minipool_backward_ref (Mfix *);
95 static void assign_minipool_offsets (Mfix *);
96 static void arm_print_value (FILE *, rtx);
97 static void dump_minipool (rtx);
98 static int arm_barrier_cost (rtx);
99 static Mfix *create_fix_barrier (Mfix *, HOST_WIDE_INT);
100 static void push_minipool_barrier (rtx, HOST_WIDE_INT);
101 static void push_minipool_fix (rtx, HOST_WIDE_INT, rtx *, enum machine_mode,
103 static void arm_reorg (void);
104 static bool note_invalid_constants (rtx, HOST_WIDE_INT, int);
105 static int current_file_function_operand (rtx);
106 static unsigned long arm_compute_save_reg0_reg12_mask (void);
107 static unsigned long arm_compute_save_reg_mask (void);
108 static unsigned long arm_isr_value (tree);
109 static unsigned long arm_compute_func_type (void);
110 static tree arm_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
111 static tree arm_handle_isr_attribute (tree *, tree, tree, int, bool *);
112 static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT);
113 static void arm_output_function_prologue (FILE *, HOST_WIDE_INT);
114 static void thumb_output_function_prologue (FILE *, HOST_WIDE_INT);
115 static int arm_comp_type_attributes (tree, tree);
116 static void arm_set_default_type_attributes (tree);
117 static int arm_adjust_cost (rtx, rtx, rtx, int);
118 static int arm_use_dfa_pipeline_interface (void);
119 static int count_insns_for_constant (HOST_WIDE_INT, int);
120 static int arm_get_strip_length (int);
121 static bool arm_function_ok_for_sibcall (tree, tree);
122 static void arm_internal_label (FILE *, const char *, unsigned long);
123 static void arm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
125 static int arm_rtx_costs_1 (rtx, enum rtx_code, enum rtx_code);
126 static bool arm_rtx_costs (rtx, int, int, int *);
127 static int arm_address_cost (rtx);
128 static bool arm_memory_load_p (rtx);
129 static bool arm_cirrus_insn_p (rtx);
130 static void cirrus_reorg (rtx);
131 static void arm_init_builtins (void);
132 static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
133 static void arm_init_iwmmxt_builtins (void);
134 static rtx safe_vector_operand (rtx, enum machine_mode);
135 static rtx arm_expand_binop_builtin (enum insn_code, tree, rtx);
136 static rtx arm_expand_unop_builtin (enum insn_code, tree, rtx, int);
137 static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
139 #ifdef OBJECT_FORMAT_ELF
140 static void arm_elf_asm_named_section (const char *, unsigned int);
143 static void arm_encode_section_info (tree, rtx, int);
146 static void aof_globalize_label (FILE *, const char *);
147 static void aof_dump_imports (FILE *);
148 static void aof_dump_pic_table (FILE *);
149 static void aof_file_start (void);
150 static void aof_file_end (void);
154 /* Initialize the GCC target structure. */
155 #ifdef TARGET_DLLIMPORT_DECL_ATTRIBUTES
156 #undef TARGET_MERGE_DECL_ATTRIBUTES
157 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
160 #undef TARGET_ATTRIBUTE_TABLE
161 #define TARGET_ATTRIBUTE_TABLE arm_attribute_table
164 #undef TARGET_ASM_BYTE_OP
165 #define TARGET_ASM_BYTE_OP "\tDCB\t"
166 #undef TARGET_ASM_ALIGNED_HI_OP
167 #define TARGET_ASM_ALIGNED_HI_OP "\tDCW\t"
168 #undef TARGET_ASM_ALIGNED_SI_OP
169 #define TARGET_ASM_ALIGNED_SI_OP "\tDCD\t"
170 #undef TARGET_ASM_GLOBALIZE_LABEL
171 #define TARGET_ASM_GLOBALIZE_LABEL aof_globalize_label
172 #undef TARGET_ASM_FILE_START
173 #define TARGET_ASM_FILE_START aof_file_start
174 #undef TARGET_ASM_FILE_END
175 #define TARGET_ASM_FILE_END aof_file_end
177 #undef TARGET_ASM_ALIGNED_SI_OP
178 #define TARGET_ASM_ALIGNED_SI_OP NULL
179 #undef TARGET_ASM_INTEGER
180 #define TARGET_ASM_INTEGER arm_assemble_integer
183 #undef TARGET_ASM_FUNCTION_PROLOGUE
184 #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue
186 #undef TARGET_ASM_FUNCTION_EPILOGUE
187 #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue
189 #undef TARGET_COMP_TYPE_ATTRIBUTES
190 #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes
192 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
193 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes
195 #undef TARGET_SCHED_ADJUST_COST
196 #define TARGET_SCHED_ADJUST_COST arm_adjust_cost
198 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
199 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE arm_use_dfa_pipeline_interface
201 #undef TARGET_ENCODE_SECTION_INFO
203 #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info
205 #define TARGET_ENCODE_SECTION_INFO arm_encode_section_info
208 #undef TARGET_STRIP_NAME_ENCODING
209 #define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding
211 #undef TARGET_ASM_INTERNAL_LABEL
212 #define TARGET_ASM_INTERNAL_LABEL arm_internal_label
214 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
215 #define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall
217 #undef TARGET_ASM_OUTPUT_MI_THUNK
218 #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk
219 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
220 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
222 #undef TARGET_RTX_COSTS
223 #define TARGET_RTX_COSTS arm_rtx_costs
224 #undef TARGET_ADDRESS_COST
225 #define TARGET_ADDRESS_COST arm_address_cost
227 #undef TARGET_MACHINE_DEPENDENT_REORG
228 #define TARGET_MACHINE_DEPENDENT_REORG arm_reorg
230 #undef TARGET_INIT_BUILTINS
231 #define TARGET_INIT_BUILTINS arm_init_builtins
232 #undef TARGET_EXPAND_BUILTIN
233 #define TARGET_EXPAND_BUILTIN arm_expand_builtin
235 struct gcc_target targetm = TARGET_INITIALIZER;
237 /* Obstack for minipool constant handling. */
238 static struct obstack minipool_obstack;
239 static char * minipool_startobj;
241 /* The maximum number of insns skipped which
242 will be conditionalised if possible. */
243 static int max_insns_skipped = 5;
245 extern FILE * asm_out_file;
247 /* True if we are currently building a constant table. */
248 int making_const_table;
250 /* Define the information needed to generate branch insns. This is
251 stored from the compare operation. */
252 rtx arm_compare_op0, arm_compare_op1;
254 /* What type of floating point are we tuning for? */
255 enum fputype arm_fpu_tune;
257 /* What type of floating point instructions are available? */
258 enum fputype arm_fpu_arch;
260 /* What program mode is the cpu running in? 26-bit mode or 32-bit mode. */
261 enum prog_mode_type arm_prgmode;
263 /* Set by the -mfp=... option. */
264 const char * target_fp_name = NULL;
266 /* Used to parse -mstructure_size_boundary command line option. */
267 const char * structure_size_string = NULL;
268 int arm_structure_size_boundary = DEFAULT_STRUCTURE_SIZE_BOUNDARY;
270 /* Bit values used to identify processor capabilities. */
271 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
272 #define FL_FAST_MULT (1 << 1) /* Fast multiply */
273 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
274 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
275 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
276 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
277 #define FL_THUMB (1 << 6) /* Thumb aware */
278 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
279 #define FL_STRONG (1 << 8) /* StrongARM */
280 #define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */
281 #define FL_XSCALE (1 << 10) /* XScale */
282 #define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */
283 #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
284 #define FL_ARCH6J (1 << 12) /* Architecture rel 6. Adds
285 media instructions. */
286 #define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */
288 /* The bits in this mask specify which
289 instructions we are allowed to generate. */
290 static unsigned long insn_flags = 0;
292 /* The bits in this mask specify which instruction scheduling options should
293 be used. Note - there is an overlap with the FL_FAST_MULT. For some
294 hardware we want to be able to generate the multiply instructions, but to
295 tune as if they were not present in the architecture. */
296 static unsigned long tune_flags = 0;
298 /* The following are used in the arm.md file as equivalents to bits
299 in the above two flag variables. */
301 /* Nonzero if this is an "M" variant of the processor. */
302 int arm_fast_multiply = 0;
304 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
307 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
310 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
313 /* Nonzero if this chip can benefit from load scheduling. */
314 int arm_ld_sched = 0;
316 /* Nonzero if this chip is a StrongARM. */
317 int arm_is_strong = 0;
319 /* Nonzero if this chip supports Intel Wireless MMX technology. */
320 int arm_arch_iwmmxt = 0;
322 /* Nonzero if this chip is an XScale. */
323 int arm_arch_xscale = 0;
325 /* Nonzero if tuning for XScale */
326 int arm_tune_xscale = 0;
328 /* Nonzero if this chip is an ARM6 or an ARM7. */
329 int arm_is_6_or_7 = 0;
331 /* Nonzero if this chip is a Cirrus/DSP. */
332 int arm_is_cirrus = 0;
334 /* Nonzero if generating Thumb instructions. */
337 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
338 must report the mode of the memory reference from PRINT_OPERAND to
339 PRINT_OPERAND_ADDRESS. */
340 enum machine_mode output_memory_reference_mode;
342 /* The register number to be used for the PIC offset register. */
343 const char * arm_pic_register_string = NULL;
344 int arm_pic_register = INVALID_REGNUM;
346 /* Set to 1 when a return insn is output, this means that the epilogue
348 int return_used_this_function;
350 /* Set to 1 after arm_reorg has started. Reset to start at the start of
351 the next function. */
352 static int after_arm_reorg = 0;
354 /* The maximum number of insns to be used when loading a constant. */
355 static int arm_constant_limit = 3;
357 /* For an explanation of these variables, see final_prescan_insn below. */
359 enum arm_cond_code arm_current_cc;
361 int arm_target_label;
363 /* The condition codes of the ARM, and the inverse function. */
364 static const char * const arm_condition_codes[] =
366 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
367 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
370 #define streq(string1, string2) (strcmp (string1, string2) == 0)
372 /* Initialization code. */
376 const char *const name;
377 const unsigned long flags;
380 /* Not all of these give usefully different compilation alternatives,
381 but there is no simple way of generalizing them. */
382 static const struct processors all_cores[] =
386 {"arm2", FL_CO_PROC | FL_MODE26 },
387 {"arm250", FL_CO_PROC | FL_MODE26 },
388 {"arm3", FL_CO_PROC | FL_MODE26 },
389 {"arm6", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
390 {"arm60", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
391 {"arm600", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
392 {"arm610", FL_MODE26 | FL_MODE32 },
393 {"arm620", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
394 {"arm7", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
395 /* arm7m doesn't exist on its own, but only with D, (and I), but
396 those don't alter the code, so arm7m is sometimes used. */
397 {"arm7m", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
398 {"arm7d", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
399 {"arm7dm", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
400 {"arm7di", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
401 {"arm7dmi", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
402 {"arm70", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
403 {"arm700", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
404 {"arm700i", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
405 {"arm710", FL_MODE26 | FL_MODE32 },
406 {"arm720", FL_MODE26 | FL_MODE32 },
407 {"arm710c", FL_MODE26 | FL_MODE32 },
408 {"arm7100", FL_MODE26 | FL_MODE32 },
409 {"arm7500", FL_MODE26 | FL_MODE32 },
410 /* Doesn't have an external co-proc, but does have embedded fpa. */
411 {"arm7500fe", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
412 /* V4 Architecture Processors */
413 {"arm7tdmi", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB },
414 {"arm710t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB },
415 {"arm720t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB },
416 {"arm740t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB },
417 {"arm8", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED },
418 {"arm810", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED },
419 {"arm9", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED },
420 {"arm920", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED },
421 {"arm920t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED },
422 {"arm940t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED },
423 {"arm9tdmi", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED },
424 {"arm9e", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED },
425 {"ep9312", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_CIRRUS },
426 {"strongarm", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG },
427 {"strongarm110", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG },
428 {"strongarm1100", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG },
429 {"strongarm1110", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG },
430 /* V5 Architecture Processors */
431 {"arm10tdmi", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_ARCH5 },
432 {"arm1020t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_ARCH5 },
433 {"arm926ejs", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E },
434 {"arm1026ejs", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E },
435 {"xscale", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_STRONG | FL_ARCH5 | FL_ARCH5E | FL_XSCALE },
436 {"iwmmxt", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_STRONG | FL_ARCH5 | FL_ARCH5E | FL_XSCALE | FL_IWMMXT },
437 /* V6 Architecture Processors */
438 {"arm1136js", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E | FL_ARCH6J },
439 {"arm1136jfs", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E | FL_ARCH6J | FL_VFPV2 },
443 static const struct processors all_architectures[] =
445 /* ARM Architectures */
447 { "armv2", FL_CO_PROC | FL_MODE26 },
448 { "armv2a", FL_CO_PROC | FL_MODE26 },
449 { "armv3", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
450 { "armv3m", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
451 { "armv4", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 },
452 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
453 implementations that support it, so we will leave it out for now. */
454 { "armv4t", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB },
455 { "armv5", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 },
456 { "armv5t", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 },
457 { "armv5te", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E },
458 { "armv6j", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E | FL_ARCH6J },
459 { "ep9312", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_CIRRUS },
460 {"iwmmxt", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_STRONG | FL_ARCH5 | FL_ARCH5E | FL_XSCALE | FL_IWMMXT },
464 /* This is a magic structure. The 'string' field is magically filled in
465 with a pointer to the value specified by the user on the command line
466 assuming that the user has specified such a value. */
468 struct arm_cpu_select arm_select[] =
470 /* string name processors */
471 { NULL, "-mcpu=", all_cores },
472 { NULL, "-march=", all_architectures },
473 { NULL, "-mtune=", all_cores }
476 /* Return the number of bits set in VALUE. */
478 bit_count (unsigned long value)
480 unsigned long count = 0;
485 value &= value - 1; /* Clear the least-significant set bit. */
491 /* Fix up any incompatible options that the user has specified.
492 This has now turned into a maze. */
494 arm_override_options (void)
498 /* Set up the flags based on the cpu/architecture selected by the user. */
499 for (i = ARRAY_SIZE (arm_select); i--;)
501 struct arm_cpu_select * ptr = arm_select + i;
503 if (ptr->string != NULL && ptr->string[0] != '\0')
505 const struct processors * sel;
507 for (sel = ptr->processors; sel->name != NULL; sel++)
508 if (streq (ptr->string, sel->name))
511 tune_flags = sel->flags;
514 /* If we have been given an architecture and a processor
515 make sure that they are compatible. We only generate
516 a warning though, and we prefer the CPU over the
518 if (insn_flags != 0 && (insn_flags ^ sel->flags))
519 warning ("switch -mcpu=%s conflicts with -march= switch",
522 insn_flags = sel->flags;
528 if (sel->name == NULL)
529 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
533 /* If the user did not specify a processor, choose one for them. */
536 const struct processors * sel;
538 static const struct cpu_default
541 const char *const name;
545 { TARGET_CPU_arm2, "arm2" },
546 { TARGET_CPU_arm6, "arm6" },
547 { TARGET_CPU_arm610, "arm610" },
548 { TARGET_CPU_arm710, "arm710" },
549 { TARGET_CPU_arm7m, "arm7m" },
550 { TARGET_CPU_arm7500fe, "arm7500fe" },
551 { TARGET_CPU_arm7tdmi, "arm7tdmi" },
552 { TARGET_CPU_arm8, "arm8" },
553 { TARGET_CPU_arm810, "arm810" },
554 { TARGET_CPU_arm9, "arm9" },
555 { TARGET_CPU_strongarm, "strongarm" },
556 { TARGET_CPU_xscale, "xscale" },
557 { TARGET_CPU_ep9312, "ep9312" },
558 { TARGET_CPU_iwmmxt, "iwmmxt" },
559 { TARGET_CPU_arm926ej_s, "arm926ej-s" },
560 { TARGET_CPU_arm1026ej_s, "arm1026ej-s" },
561 { TARGET_CPU_arm1136j_s, "arm1136j_s" },
562 { TARGET_CPU_arm1136jf_s, "arm1136jf_s" },
563 { TARGET_CPU_generic, "arm" },
566 const struct cpu_default * def;
568 /* Find the default. */
569 for (def = cpu_defaults; def->name; def++)
570 if (def->cpu == TARGET_CPU_DEFAULT)
573 /* Make sure we found the default CPU. */
574 if (def->name == NULL)
577 /* Find the default CPU's flags. */
578 for (sel = all_cores; sel->name != NULL; sel++)
579 if (streq (def->name, sel->name))
582 if (sel->name == NULL)
585 insn_flags = sel->flags;
587 /* Now check to see if the user has specified some command line
588 switch that require certain abilities from the cpu. */
591 if (TARGET_INTERWORK || TARGET_THUMB)
593 sought |= (FL_THUMB | FL_MODE32);
595 /* Force apcs-32 to be used for interworking. */
596 target_flags |= ARM_FLAG_APCS_32;
598 /* There are no ARM processors that support both APCS-26 and
599 interworking. Therefore we force FL_MODE26 to be removed
600 from insn_flags here (if it was set), so that the search
601 below will always be able to find a compatible processor. */
602 insn_flags &= ~FL_MODE26;
604 else if (!TARGET_APCS_32)
607 if (sought != 0 && ((sought & insn_flags) != sought))
609 /* Try to locate a CPU type that supports all of the abilities
610 of the default CPU, plus the extra abilities requested by
612 for (sel = all_cores; sel->name != NULL; sel++)
613 if ((sel->flags & sought) == (sought | insn_flags))
616 if (sel->name == NULL)
618 unsigned current_bit_count = 0;
619 const struct processors * best_fit = NULL;
621 /* Ideally we would like to issue an error message here
622 saying that it was not possible to find a CPU compatible
623 with the default CPU, but which also supports the command
624 line options specified by the programmer, and so they
625 ought to use the -mcpu=<name> command line option to
626 override the default CPU type.
628 Unfortunately this does not work with multilibing. We
629 need to be able to support multilibs for -mapcs-26 and for
630 -mthumb-interwork and there is no CPU that can support both
631 options. Instead if we cannot find a cpu that has both the
632 characteristics of the default cpu and the given command line
633 options we scan the array again looking for a best match. */
634 for (sel = all_cores; sel->name != NULL; sel++)
635 if ((sel->flags & sought) == sought)
639 count = bit_count (sel->flags & insn_flags);
641 if (count >= current_bit_count)
644 current_bit_count = count;
648 if (best_fit == NULL)
654 insn_flags = sel->flags;
658 /* If tuning has not been specified, tune for whichever processor or
659 architecture has been selected. */
661 tune_flags = insn_flags;
663 /* Make sure that the processor choice does not conflict with any of the
664 other command line choices. */
665 if (TARGET_APCS_32 && !(insn_flags & FL_MODE32))
667 /* If APCS-32 was not the default then it must have been set by the
668 user, so issue a warning message. If the user has specified
669 "-mapcs-32 -mcpu=arm2" then we loose here. */
670 if ((TARGET_DEFAULT & ARM_FLAG_APCS_32) == 0)
671 warning ("target CPU does not support APCS-32" );
672 target_flags &= ~ARM_FLAG_APCS_32;
674 else if (!TARGET_APCS_32 && !(insn_flags & FL_MODE26))
676 warning ("target CPU does not support APCS-26" );
677 target_flags |= ARM_FLAG_APCS_32;
680 if (TARGET_INTERWORK && !(insn_flags & FL_THUMB))
682 warning ("target CPU does not support interworking" );
683 target_flags &= ~ARM_FLAG_INTERWORK;
686 if (TARGET_THUMB && !(insn_flags & FL_THUMB))
688 warning ("target CPU does not support THUMB instructions");
689 target_flags &= ~ARM_FLAG_THUMB;
692 if (TARGET_APCS_FRAME && TARGET_THUMB)
694 /* warning ("ignoring -mapcs-frame because -mthumb was used"); */
695 target_flags &= ~ARM_FLAG_APCS_FRAME;
698 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
699 from here where no function is being compiled currently. */
700 if ((target_flags & (THUMB_FLAG_LEAF_BACKTRACE | THUMB_FLAG_BACKTRACE))
702 warning ("enabling backtrace support is only meaningful when compiling for the Thumb");
704 if (TARGET_ARM && TARGET_CALLEE_INTERWORKING)
705 warning ("enabling callee interworking support is only meaningful when compiling for the Thumb");
707 if (TARGET_ARM && TARGET_CALLER_INTERWORKING)
708 warning ("enabling caller interworking support is only meaningful when compiling for the Thumb");
710 /* If interworking is enabled then APCS-32 must be selected as well. */
711 if (TARGET_INTERWORK)
714 warning ("interworking forces APCS-32 to be used" );
715 target_flags |= ARM_FLAG_APCS_32;
718 if (TARGET_APCS_STACK && !TARGET_APCS_FRAME)
720 warning ("-mapcs-stack-check incompatible with -mno-apcs-frame");
721 target_flags |= ARM_FLAG_APCS_FRAME;
724 if (TARGET_POKE_FUNCTION_NAME)
725 target_flags |= ARM_FLAG_APCS_FRAME;
727 if (TARGET_APCS_REENT && flag_pic)
728 error ("-fpic and -mapcs-reent are incompatible");
730 if (TARGET_APCS_REENT)
731 warning ("APCS reentrant code not supported. Ignored");
733 /* If this target is normally configured to use APCS frames, warn if they
734 are turned off and debugging is turned on. */
736 && write_symbols != NO_DEBUG
737 && !TARGET_APCS_FRAME
738 && (TARGET_DEFAULT & ARM_FLAG_APCS_FRAME))
739 warning ("-g with -mno-apcs-frame may not give sensible debugging");
741 /* If stack checking is disabled, we can use r10 as the PIC register,
742 which keeps r9 available. */
744 arm_pic_register = TARGET_APCS_STACK ? 9 : 10;
746 if (TARGET_APCS_FLOAT)
747 warning ("passing floating point arguments in fp regs not yet supported");
749 /* Initialize boolean versions of the flags, for use in the arm.md file. */
750 arm_fast_multiply = (insn_flags & FL_FAST_MULT) != 0;
751 arm_arch4 = (insn_flags & FL_ARCH4) != 0;
752 arm_arch5 = (insn_flags & FL_ARCH5) != 0;
753 arm_arch5e = (insn_flags & FL_ARCH5E) != 0;
754 arm_arch_xscale = (insn_flags & FL_XSCALE) != 0;
756 arm_ld_sched = (tune_flags & FL_LDSCHED) != 0;
757 arm_is_strong = (tune_flags & FL_STRONG) != 0;
758 thumb_code = (TARGET_ARM == 0);
759 arm_is_6_or_7 = (((tune_flags & (FL_MODE26 | FL_MODE32))
760 && !(tune_flags & FL_ARCH4))) != 0;
761 arm_tune_xscale = (tune_flags & FL_XSCALE) != 0;
762 arm_is_cirrus = (tune_flags & FL_CIRRUS) != 0;
763 arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0;
765 if (TARGET_IWMMXT && (! TARGET_ATPCS))
766 target_flags |= ARM_FLAG_ATPCS;
770 arm_fpu_tune = FPUTYPE_MAVERICK;
772 /* Ignore -mhard-float if -mcpu=ep9312. */
773 if (TARGET_HARD_FLOAT)
774 target_flags ^= ARM_FLAG_SOFT_FLOAT;
777 /* Default value for floating point code... if no co-processor
778 bus, then schedule for emulated floating point. Otherwise,
779 assume the user has an FPA.
780 Note: this does not prevent use of floating point instructions,
781 -msoft-float does that. */
782 arm_fpu_tune = (tune_flags & FL_CO_PROC) ? FPUTYPE_FPA : FPUTYPE_FPA_EMU3;
786 if (streq (target_fp_name, "2"))
787 arm_fpu_arch = FPUTYPE_FPA_EMU2;
788 else if (streq (target_fp_name, "3"))
789 arm_fpu_arch = FPUTYPE_FPA_EMU3;
791 error ("invalid floating point emulation option: -mfpe-%s",
795 arm_fpu_arch = FPUTYPE_DEFAULT;
799 if (arm_fpu_tune == FPUTYPE_FPA_EMU3)
800 arm_fpu_tune = FPUTYPE_FPA_EMU2;
801 else if (arm_fpu_tune == FPUTYPE_MAVERICK)
802 warning ("-mfpe switch not supported by ep9312 target cpu - ignored.");
803 else if (arm_fpu_tune != FPUTYPE_FPA)
804 arm_fpu_tune = FPUTYPE_FPA_EMU2;
807 /* For arm2/3 there is no need to do any scheduling if there is only
808 a floating point emulator, or we are doing software floating-point. */
809 if ((TARGET_SOFT_FLOAT || arm_fpu_tune != FPUTYPE_FPA)
810 && (tune_flags & FL_MODE32) == 0)
811 flag_schedule_insns = flag_schedule_insns_after_reload = 0;
813 arm_prgmode = TARGET_APCS_32 ? PROG_MODE_PROG32 : PROG_MODE_PROG26;
815 if (structure_size_string != NULL)
817 int size = strtol (structure_size_string, NULL, 0);
819 if (size == 8 || size == 32)
820 arm_structure_size_boundary = size;
822 warning ("structure size boundary can only be set to 8 or 32");
825 if (arm_pic_register_string != NULL)
827 int pic_register = decode_reg_name (arm_pic_register_string);
830 warning ("-mpic-register= is useless without -fpic");
832 /* Prevent the user from choosing an obviously stupid PIC register. */
833 else if (pic_register < 0 || call_used_regs[pic_register]
834 || pic_register == HARD_FRAME_POINTER_REGNUM
835 || pic_register == STACK_POINTER_REGNUM
836 || pic_register >= PC_REGNUM)
837 error ("unable to use '%s' for PIC register", arm_pic_register_string);
839 arm_pic_register = pic_register;
842 if (TARGET_THUMB && flag_schedule_insns)
844 /* Don't warn since it's on by default in -O2. */
845 flag_schedule_insns = 0;
850 /* There's some dispute as to whether this should be 1 or 2. However,
851 experiments seem to show that in pathological cases a setting of
852 1 degrades less severly than a setting of 2. This could change if
853 other parts of the compiler change their behavior. */
854 arm_constant_limit = 1;
856 /* If optimizing for size, bump the number of instructions that we
857 are prepared to conditionally execute (even on a StrongARM). */
858 max_insns_skipped = 6;
862 /* For processors with load scheduling, it never costs more than
863 2 cycles to load a constant, and the load scheduler may well
865 if (tune_flags & FL_LDSCHED)
866 arm_constant_limit = 1;
868 /* On XScale the longer latency of a load makes it more difficult
869 to achieve a good schedule, so it's faster to synthesize
870 constants that can be done in two insns. */
872 arm_constant_limit = 2;
874 /* StrongARM has early execution of branches, so a sequence
875 that is worth skipping is shorter. */
877 max_insns_skipped = 3;
880 /* Register global variables with the garbage collector. */
885 arm_add_gc_roots (void)
887 gcc_obstack_init(&minipool_obstack);
888 minipool_startobj = (char *) obstack_alloc (&minipool_obstack, 0);
891 /* A table of known ARM exception types.
892 For use with the interrupt function attribute. */
896 const char *const arg;
897 const unsigned long return_value;
901 static const isr_attribute_arg isr_attribute_args [] =
903 { "IRQ", ARM_FT_ISR },
904 { "irq", ARM_FT_ISR },
905 { "FIQ", ARM_FT_FIQ },
906 { "fiq", ARM_FT_FIQ },
907 { "ABORT", ARM_FT_ISR },
908 { "abort", ARM_FT_ISR },
909 { "ABORT", ARM_FT_ISR },
910 { "abort", ARM_FT_ISR },
911 { "UNDEF", ARM_FT_EXCEPTION },
912 { "undef", ARM_FT_EXCEPTION },
913 { "SWI", ARM_FT_EXCEPTION },
914 { "swi", ARM_FT_EXCEPTION },
915 { NULL, ARM_FT_NORMAL }
918 /* Returns the (interrupt) function type of the current
919 function, or ARM_FT_UNKNOWN if the type cannot be determined. */
922 arm_isr_value (tree argument)
924 const isr_attribute_arg * ptr;
927 /* No argument - default to IRQ. */
928 if (argument == NULL_TREE)
931 /* Get the value of the argument. */
932 if (TREE_VALUE (argument) == NULL_TREE
933 || TREE_CODE (TREE_VALUE (argument)) != STRING_CST)
934 return ARM_FT_UNKNOWN;
936 arg = TREE_STRING_POINTER (TREE_VALUE (argument));
938 /* Check it against the list of known arguments. */
939 for (ptr = isr_attribute_args; ptr->arg != NULL; ptr++)
940 if (streq (arg, ptr->arg))
941 return ptr->return_value;
943 /* An unrecognized interrupt type. */
944 return ARM_FT_UNKNOWN;
947 /* Computes the type of the current function. */
950 arm_compute_func_type (void)
952 unsigned long type = ARM_FT_UNKNOWN;
956 if (TREE_CODE (current_function_decl) != FUNCTION_DECL)
959 /* Decide if the current function is volatile. Such functions
960 never return, and many memory cycles can be saved by not storing
961 register values that will never be needed again. This optimization
962 was added to speed up context switching in a kernel application. */
964 && current_function_nothrow
965 && TREE_THIS_VOLATILE (current_function_decl))
966 type |= ARM_FT_VOLATILE;
968 if (current_function_needs_context)
969 type |= ARM_FT_NESTED;
971 attr = DECL_ATTRIBUTES (current_function_decl);
973 a = lookup_attribute ("naked", attr);
975 type |= ARM_FT_NAKED;
977 if (cfun->machine->eh_epilogue_sp_ofs != NULL_RTX)
978 type |= ARM_FT_EXCEPTION_HANDLER;
981 a = lookup_attribute ("isr", attr);
983 a = lookup_attribute ("interrupt", attr);
986 type |= TARGET_INTERWORK ? ARM_FT_INTERWORKED : ARM_FT_NORMAL;
988 type |= arm_isr_value (TREE_VALUE (a));
994 /* Returns the type of the current function. */
997 arm_current_func_type (void)
999 if (ARM_FUNC_TYPE (cfun->machine->func_type) == ARM_FT_UNKNOWN)
1000 cfun->machine->func_type = arm_compute_func_type ();
1002 return cfun->machine->func_type;
1005 /* Return 1 if it is possible to return using a single instruction. */
1008 use_return_insn (int iscond)
1011 unsigned int func_type;
1012 unsigned long saved_int_regs;
1014 /* Never use a return instruction before reload has run. */
1015 if (!reload_completed)
1018 func_type = arm_current_func_type ();
1020 /* Naked functions and volatile functions need special
1022 if (func_type & (ARM_FT_VOLATILE | ARM_FT_NAKED))
1025 /* So do interrupt functions that use the frame pointer. */
1026 if (IS_INTERRUPT (func_type) && frame_pointer_needed)
1029 /* As do variadic functions. */
1030 if (current_function_pretend_args_size
1031 || cfun->machine->uses_anonymous_args
1032 /* Or if the function calls __builtin_eh_return () */
1033 || ARM_FUNC_TYPE (func_type) == ARM_FT_EXCEPTION_HANDLER
1034 /* Or if the function calls alloca */
1035 || current_function_calls_alloca
1036 /* Or if there is a stack adjustment. */
1037 || (arm_get_frame_size () + current_function_outgoing_args_size != 0))
1040 saved_int_regs = arm_compute_save_reg_mask ();
1042 /* Can't be done if interworking with Thumb, and any registers have been
1044 if (TARGET_INTERWORK && saved_int_regs != 0)
1047 /* On StrongARM, conditional returns are expensive if they aren't
1048 taken and multiple registers have been stacked. */
1049 if (iscond && arm_is_strong)
1051 /* Conditional return when just the LR is stored is a simple
1052 conditional-load instruction, that's not expensive. */
1053 if (saved_int_regs != 0 && saved_int_regs != (1 << LR_REGNUM))
1056 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
1060 /* If there are saved registers but the LR isn't saved, then we need
1061 two instructions for the return. */
1062 if (saved_int_regs && !(saved_int_regs & (1 << LR_REGNUM)))
1065 /* Can't be done if any of the FPA regs are pushed,
1066 since this also requires an insn. */
1067 if (TARGET_HARD_FLOAT)
1068 for (regno = FIRST_ARM_FP_REGNUM; regno <= LAST_ARM_FP_REGNUM; regno++)
1069 if (regs_ever_live[regno] && !call_used_regs[regno])
1072 if (TARGET_REALLY_IWMMXT)
1073 for (regno = FIRST_IWMMXT_REGNUM; regno <= LAST_IWMMXT_REGNUM; regno++)
1074 if (regs_ever_live[regno] && ! call_used_regs [regno])
1080 /* Return TRUE if int I is a valid immediate ARM constant. */
1083 const_ok_for_arm (HOST_WIDE_INT i)
1085 unsigned HOST_WIDE_INT mask = ~(unsigned HOST_WIDE_INT)0xFF;
1087 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
1088 be all zero, or all one. */
1089 if ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0
1090 && ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff)
1091 != ((~(unsigned HOST_WIDE_INT) 0)
1092 & ~(unsigned HOST_WIDE_INT) 0xffffffff)))
1095 /* Fast return for 0 and powers of 2 */
1096 if ((i & (i - 1)) == 0)
1101 if ((i & mask & (unsigned HOST_WIDE_INT) 0xffffffff) == 0)
1104 (mask << 2) | ((mask & (unsigned HOST_WIDE_INT) 0xffffffff)
1105 >> (32 - 2)) | ~(unsigned HOST_WIDE_INT) 0xffffffff;
1107 while (mask != ~(unsigned HOST_WIDE_INT) 0xFF);
1112 /* Return true if I is a valid constant for the operation CODE. */
1114 const_ok_for_op (HOST_WIDE_INT i, enum rtx_code code)
1116 if (const_ok_for_arm (i))
1122 return const_ok_for_arm (ARM_SIGN_EXTEND (-i));
1124 case MINUS: /* Should only occur with (MINUS I reg) => rsb */
1130 return const_ok_for_arm (ARM_SIGN_EXTEND (~i));
1137 /* Emit a sequence of insns to handle a large constant.
1138 CODE is the code of the operation required, it can be any of SET, PLUS,
1139 IOR, AND, XOR, MINUS;
1140 MODE is the mode in which the operation is being performed;
1141 VAL is the integer to operate on;
1142 SOURCE is the other operand (a register, or a null-pointer for SET);
1143 SUBTARGETS means it is safe to create scratch registers if that will
1144 either produce a simpler sequence, or we will want to cse the values.
1145 Return value is the number of insns emitted. */
1148 arm_split_constant (enum rtx_code code, enum machine_mode mode,
1149 HOST_WIDE_INT val, rtx target, rtx source, int subtargets)
1151 if (subtargets || code == SET
1152 || (GET_CODE (target) == REG && GET_CODE (source) == REG
1153 && REGNO (target) != REGNO (source)))
1155 /* After arm_reorg has been called, we can't fix up expensive
1156 constants by pushing them into memory so we must synthesize
1157 them in-line, regardless of the cost. This is only likely to
1158 be more costly on chips that have load delay slots and we are
1159 compiling without running the scheduler (so no splitting
1160 occurred before the final instruction emission).
1162 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
1164 if (!after_arm_reorg
1165 && (arm_gen_constant (code, mode, val, target, source, 1, 0)
1166 > arm_constant_limit + (code != SET)))
1170 /* Currently SET is the only monadic value for CODE, all
1171 the rest are diadic. */
1172 emit_insn (gen_rtx_SET (VOIDmode, target, GEN_INT (val)));
1177 rtx temp = subtargets ? gen_reg_rtx (mode) : target;
1179 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (val)));
1180 /* For MINUS, the value is subtracted from, since we never
1181 have subtraction of a constant. */
1183 emit_insn (gen_rtx_SET (VOIDmode, target,
1184 gen_rtx_MINUS (mode, temp, source)));
1186 emit_insn (gen_rtx_SET (VOIDmode, target,
1187 gen_rtx (code, mode, source, temp)));
1193 return arm_gen_constant (code, mode, val, target, source, subtargets, 1);
1197 count_insns_for_constant (HOST_WIDE_INT remainder, int i)
1199 HOST_WIDE_INT temp1;
1207 if (remainder & (3 << (i - 2)))
1212 temp1 = remainder & ((0x0ff << end)
1213 | ((i < end) ? (0xff >> (32 - end)) : 0));
1214 remainder &= ~temp1;
1219 } while (remainder);
1223 /* As above, but extra parameter GENERATE which, if clear, suppresses
1227 arm_gen_constant (enum rtx_code code, enum machine_mode mode,
1228 HOST_WIDE_INT val, rtx target, rtx source, int subtargets,
1233 int can_negate_initial = 0;
1236 int num_bits_set = 0;
1237 int set_sign_bit_copies = 0;
1238 int clear_sign_bit_copies = 0;
1239 int clear_zero_bit_copies = 0;
1240 int set_zero_bit_copies = 0;
1242 unsigned HOST_WIDE_INT temp1, temp2;
1243 unsigned HOST_WIDE_INT remainder = val & 0xffffffff;
1245 /* Find out which operations are safe for a given CODE. Also do a quick
1246 check for degenerate cases; these can occur when DImode operations
1258 can_negate_initial = 1;
1262 if (remainder == 0xffffffff)
1265 emit_insn (gen_rtx_SET (VOIDmode, target,
1266 GEN_INT (ARM_SIGN_EXTEND (val))));
1271 if (reload_completed && rtx_equal_p (target, source))
1274 emit_insn (gen_rtx_SET (VOIDmode, target, source));
1283 emit_insn (gen_rtx_SET (VOIDmode, target, const0_rtx));
1286 if (remainder == 0xffffffff)
1288 if (reload_completed && rtx_equal_p (target, source))
1291 emit_insn (gen_rtx_SET (VOIDmode, target, source));
1300 if (reload_completed && rtx_equal_p (target, source))
1303 emit_insn (gen_rtx_SET (VOIDmode, target, source));
1306 if (remainder == 0xffffffff)
1309 emit_insn (gen_rtx_SET (VOIDmode, target,
1310 gen_rtx_NOT (mode, source)));
1314 /* We don't know how to handle this yet below. */
1318 /* We treat MINUS as (val - source), since (source - val) is always
1319 passed as (source + (-val)). */
1323 emit_insn (gen_rtx_SET (VOIDmode, target,
1324 gen_rtx_NEG (mode, source)));
1327 if (const_ok_for_arm (val))
1330 emit_insn (gen_rtx_SET (VOIDmode, target,
1331 gen_rtx_MINUS (mode, GEN_INT (val),
1343 /* If we can do it in one insn get out quickly. */
1344 if (const_ok_for_arm (val)
1345 || (can_negate_initial && const_ok_for_arm (-val))
1346 || (can_invert && const_ok_for_arm (~val)))
1349 emit_insn (gen_rtx_SET (VOIDmode, target,
1350 (source ? gen_rtx (code, mode, source,
1356 /* Calculate a few attributes that may be useful for specific
1358 for (i = 31; i >= 0; i--)
1360 if ((remainder & (1 << i)) == 0)
1361 clear_sign_bit_copies++;
1366 for (i = 31; i >= 0; i--)
1368 if ((remainder & (1 << i)) != 0)
1369 set_sign_bit_copies++;
1374 for (i = 0; i <= 31; i++)
1376 if ((remainder & (1 << i)) == 0)
1377 clear_zero_bit_copies++;
1382 for (i = 0; i <= 31; i++)
1384 if ((remainder & (1 << i)) != 0)
1385 set_zero_bit_copies++;
1393 /* See if we can do this by sign_extending a constant that is known
1394 to be negative. This is a good, way of doing it, since the shift
1395 may well merge into a subsequent insn. */
1396 if (set_sign_bit_copies > 1)
1398 if (const_ok_for_arm
1399 (temp1 = ARM_SIGN_EXTEND (remainder
1400 << (set_sign_bit_copies - 1))))
1404 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1405 emit_insn (gen_rtx_SET (VOIDmode, new_src,
1407 emit_insn (gen_ashrsi3 (target, new_src,
1408 GEN_INT (set_sign_bit_copies - 1)));
1412 /* For an inverted constant, we will need to set the low bits,
1413 these will be shifted out of harm's way. */
1414 temp1 |= (1 << (set_sign_bit_copies - 1)) - 1;
1415 if (const_ok_for_arm (~temp1))
1419 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1420 emit_insn (gen_rtx_SET (VOIDmode, new_src,
1422 emit_insn (gen_ashrsi3 (target, new_src,
1423 GEN_INT (set_sign_bit_copies - 1)));
1429 /* See if we can generate this by setting the bottom (or the top)
1430 16 bits, and then shifting these into the other half of the
1431 word. We only look for the simplest cases, to do more would cost
1432 too much. Be careful, however, not to generate this when the
1433 alternative would take fewer insns. */
1434 if (val & 0xffff0000)
1436 temp1 = remainder & 0xffff0000;
1437 temp2 = remainder & 0x0000ffff;
1439 /* Overlaps outside this range are best done using other methods. */
1440 for (i = 9; i < 24; i++)
1442 if ((((temp2 | (temp2 << i)) & 0xffffffff) == remainder)
1443 && !const_ok_for_arm (temp2))
1445 rtx new_src = (subtargets
1446 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
1448 insns = arm_gen_constant (code, mode, temp2, new_src,
1449 source, subtargets, generate);
1452 emit_insn (gen_rtx_SET
1455 gen_rtx_ASHIFT (mode, source,
1462 /* Don't duplicate cases already considered. */
1463 for (i = 17; i < 24; i++)
1465 if (((temp1 | (temp1 >> i)) == remainder)
1466 && !const_ok_for_arm (temp1))
1468 rtx new_src = (subtargets
1469 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
1471 insns = arm_gen_constant (code, mode, temp1, new_src,
1472 source, subtargets, generate);
1476 (gen_rtx_SET (VOIDmode, target,
1479 gen_rtx_LSHIFTRT (mode, source,
1490 /* If we have IOR or XOR, and the constant can be loaded in a
1491 single instruction, and we can find a temporary to put it in,
1492 then this can be done in two instructions instead of 3-4. */
1494 /* TARGET can't be NULL if SUBTARGETS is 0 */
1495 || (reload_completed && !reg_mentioned_p (target, source)))
1497 if (const_ok_for_arm (ARM_SIGN_EXTEND (~val)))
1501 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1503 emit_insn (gen_rtx_SET (VOIDmode, sub, GEN_INT (val)));
1504 emit_insn (gen_rtx_SET (VOIDmode, target,
1505 gen_rtx (code, mode, source, sub)));
1514 if (set_sign_bit_copies > 8
1515 && (val & (-1 << (32 - set_sign_bit_copies))) == val)
1519 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1520 rtx shift = GEN_INT (set_sign_bit_copies);
1522 emit_insn (gen_rtx_SET (VOIDmode, sub,
1524 gen_rtx_ASHIFT (mode,
1527 emit_insn (gen_rtx_SET (VOIDmode, target,
1529 gen_rtx_LSHIFTRT (mode, sub,
1535 if (set_zero_bit_copies > 8
1536 && (remainder & ((1 << set_zero_bit_copies) - 1)) == remainder)
1540 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1541 rtx shift = GEN_INT (set_zero_bit_copies);
1543 emit_insn (gen_rtx_SET (VOIDmode, sub,
1545 gen_rtx_LSHIFTRT (mode,
1548 emit_insn (gen_rtx_SET (VOIDmode, target,
1550 gen_rtx_ASHIFT (mode, sub,
1556 if (const_ok_for_arm (temp1 = ARM_SIGN_EXTEND (~val)))
1560 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1561 emit_insn (gen_rtx_SET (VOIDmode, sub,
1562 gen_rtx_NOT (mode, source)));
1565 sub = gen_reg_rtx (mode);
1566 emit_insn (gen_rtx_SET (VOIDmode, sub,
1567 gen_rtx_AND (mode, source,
1569 emit_insn (gen_rtx_SET (VOIDmode, target,
1570 gen_rtx_NOT (mode, sub)));
1577 /* See if two shifts will do 2 or more insn's worth of work. */
1578 if (clear_sign_bit_copies >= 16 && clear_sign_bit_copies < 24)
1580 HOST_WIDE_INT shift_mask = ((0xffffffff
1581 << (32 - clear_sign_bit_copies))
1584 if ((remainder | shift_mask) != 0xffffffff)
1588 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1589 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1590 new_src, source, subtargets, 1);
1595 rtx targ = subtargets ? NULL_RTX : target;
1596 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1597 targ, source, subtargets, 0);
1603 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1604 rtx shift = GEN_INT (clear_sign_bit_copies);
1606 emit_insn (gen_ashlsi3 (new_src, source, shift));
1607 emit_insn (gen_lshrsi3 (target, new_src, shift));
1613 if (clear_zero_bit_copies >= 16 && clear_zero_bit_copies < 24)
1615 HOST_WIDE_INT shift_mask = (1 << clear_zero_bit_copies) - 1;
1617 if ((remainder | shift_mask) != 0xffffffff)
1621 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1623 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1624 new_src, source, subtargets, 1);
1629 rtx targ = subtargets ? NULL_RTX : target;
1631 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1632 targ, source, subtargets, 0);
1638 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1639 rtx shift = GEN_INT (clear_zero_bit_copies);
1641 emit_insn (gen_lshrsi3 (new_src, source, shift));
1642 emit_insn (gen_ashlsi3 (target, new_src, shift));
1654 for (i = 0; i < 32; i++)
1655 if (remainder & (1 << i))
1658 if (code == AND || (can_invert && num_bits_set > 16))
1659 remainder = (~remainder) & 0xffffffff;
1660 else if (code == PLUS && num_bits_set > 16)
1661 remainder = (-remainder) & 0xffffffff;
1668 /* Now try and find a way of doing the job in either two or three
1670 We start by looking for the largest block of zeros that are aligned on
1671 a 2-bit boundary, we then fill up the temps, wrapping around to the
1672 top of the word when we drop off the bottom.
1673 In the worst case this code should produce no more than four insns. */
1676 int best_consecutive_zeros = 0;
1678 for (i = 0; i < 32; i += 2)
1680 int consecutive_zeros = 0;
1682 if (!(remainder & (3 << i)))
1684 while ((i < 32) && !(remainder & (3 << i)))
1686 consecutive_zeros += 2;
1689 if (consecutive_zeros > best_consecutive_zeros)
1691 best_consecutive_zeros = consecutive_zeros;
1692 best_start = i - consecutive_zeros;
1698 /* So long as it won't require any more insns to do so, it's
1699 desirable to emit a small constant (in bits 0...9) in the last
1700 insn. This way there is more chance that it can be combined with
1701 a later addressing insn to form a pre-indexed load or store
1702 operation. Consider:
1704 *((volatile int *)0xe0000100) = 1;
1705 *((volatile int *)0xe0000110) = 2;
1707 We want this to wind up as:
1711 str rB, [rA, #0x100]
1713 str rB, [rA, #0x110]
1715 rather than having to synthesize both large constants from scratch.
1717 Therefore, we calculate how many insns would be required to emit
1718 the constant starting from `best_start', and also starting from
1719 zero (ie with bit 31 first to be output). If `best_start' doesn't
1720 yield a shorter sequence, we may as well use zero. */
1722 && ((((unsigned HOST_WIDE_INT) 1) << best_start) < remainder)
1723 && (count_insns_for_constant (remainder, 0) <=
1724 count_insns_for_constant (remainder, best_start)))
1727 /* Now start emitting the insns. */
1735 if (remainder & (3 << (i - 2)))
1740 temp1 = remainder & ((0x0ff << end)
1741 | ((i < end) ? (0xff >> (32 - end)) : 0));
1742 remainder &= ~temp1;
1746 rtx new_src, temp1_rtx;
1748 if (code == SET || code == MINUS)
1750 new_src = (subtargets ? gen_reg_rtx (mode) : target);
1751 if (can_invert && code != MINUS)
1756 if (remainder && subtargets)
1757 new_src = gen_reg_rtx (mode);
1762 else if (can_negate)
1766 temp1 = trunc_int_for_mode (temp1, mode);
1767 temp1_rtx = GEN_INT (temp1);
1771 else if (code == MINUS)
1772 temp1_rtx = gen_rtx_MINUS (mode, temp1_rtx, source);
1774 temp1_rtx = gen_rtx_fmt_ee (code, mode, source, temp1_rtx);
1776 emit_insn (gen_rtx_SET (VOIDmode, new_src, temp1_rtx));
1785 else if (code == MINUS)
1799 /* Canonicalize a comparison so that we are more likely to recognize it.
1800 This can be done for a few constant compares, where we can make the
1801 immediate value easier to load. */
1804 arm_canonicalize_comparison (enum rtx_code code, rtx * op1)
1806 unsigned HOST_WIDE_INT i = INTVAL (*op1);
1816 if (i != ((((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1)) - 1)
1817 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
1819 *op1 = GEN_INT (i + 1);
1820 return code == GT ? GE : LT;
1826 if (i != (((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1))
1827 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
1829 *op1 = GEN_INT (i - 1);
1830 return code == GE ? GT : LE;
1836 if (i != ~((unsigned HOST_WIDE_INT) 0)
1837 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
1839 *op1 = GEN_INT (i + 1);
1840 return code == GTU ? GEU : LTU;
1847 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
1849 *op1 = GEN_INT (i - 1);
1850 return code == GEU ? GTU : LEU;
1861 /* Decide whether a type should be returned in memory (true)
1862 or in a register (false). This is called by the macro
1863 RETURN_IN_MEMORY. */
1865 arm_return_in_memory (tree type)
1869 if (!AGGREGATE_TYPE_P (type))
1870 /* All simple types are returned in registers. */
1873 size = int_size_in_bytes (type);
1877 /* ATPCS returns aggregate types in memory only if they are
1878 larger than a word (or are variable size). */
1879 return (size < 0 || size > UNITS_PER_WORD);
1882 /* For the arm-wince targets we choose to be compatible with Microsoft's
1883 ARM and Thumb compilers, which always return aggregates in memory. */
1885 /* All structures/unions bigger than one word are returned in memory.
1886 Also catch the case where int_size_in_bytes returns -1. In this case
1887 the aggregate is either huge or of variable size, and in either case
1888 we will want to return it via memory and not in a register. */
1889 if (size < 0 || size > UNITS_PER_WORD)
1892 if (TREE_CODE (type) == RECORD_TYPE)
1896 /* For a struct the APCS says that we only return in a register
1897 if the type is 'integer like' and every addressable element
1898 has an offset of zero. For practical purposes this means
1899 that the structure can have at most one non bit-field element
1900 and that this element must be the first one in the structure. */
1902 /* Find the first field, ignoring non FIELD_DECL things which will
1903 have been created by C++. */
1904 for (field = TYPE_FIELDS (type);
1905 field && TREE_CODE (field) != FIELD_DECL;
1906 field = TREE_CHAIN (field))
1910 return 0; /* An empty structure. Allowed by an extension to ANSI C. */
1912 /* Check that the first field is valid for returning in a register. */
1914 /* ... Floats are not allowed */
1915 if (FLOAT_TYPE_P (TREE_TYPE (field)))
1918 /* ... Aggregates that are not themselves valid for returning in
1919 a register are not allowed. */
1920 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
1923 /* Now check the remaining fields, if any. Only bitfields are allowed,
1924 since they are not addressable. */
1925 for (field = TREE_CHAIN (field);
1927 field = TREE_CHAIN (field))
1929 if (TREE_CODE (field) != FIELD_DECL)
1932 if (!DECL_BIT_FIELD_TYPE (field))
1939 if (TREE_CODE (type) == UNION_TYPE)
1943 /* Unions can be returned in registers if every element is
1944 integral, or can be returned in an integer register. */
1945 for (field = TYPE_FIELDS (type);
1947 field = TREE_CHAIN (field))
1949 if (TREE_CODE (field) != FIELD_DECL)
1952 if (FLOAT_TYPE_P (TREE_TYPE (field)))
1955 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
1961 #endif /* not ARM_WINCE */
1963 /* Return all other types in memory. */
1967 /* Indicate whether or not words of a double are in big-endian order. */
1970 arm_float_words_big_endian (void)
1975 /* For FPA, float words are always big-endian. For VFP, floats words
1976 follow the memory system mode. */
1978 if (TARGET_HARD_FLOAT)
1980 /* FIXME: TARGET_HARD_FLOAT currently implies FPA. */
1985 return (TARGET_BIG_END ? 1 : 0);
1990 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1991 for a call to a function whose data type is FNTYPE.
1992 For a library call, FNTYPE is NULL. */
1994 arm_init_cumulative_args (CUMULATIVE_ARGS *pcum, tree fntype,
1995 rtx libname ATTRIBUTE_UNUSED,
1996 tree fndecl ATTRIBUTE_UNUSED)
1998 /* On the ARM, the offset starts at 0. */
1999 pcum->nregs = ((fntype && aggregate_value_p (TREE_TYPE (fntype), fntype)) ? 1 : 0);
2000 pcum->iwmmxt_nregs = 0;
2002 pcum->call_cookie = CALL_NORMAL;
2004 if (TARGET_LONG_CALLS)
2005 pcum->call_cookie = CALL_LONG;
2007 /* Check for long call/short call attributes. The attributes
2008 override any command line option. */
2011 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (fntype)))
2012 pcum->call_cookie = CALL_SHORT;
2013 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (fntype)))
2014 pcum->call_cookie = CALL_LONG;
2017 /* Varargs vectors are treated the same as long long.
2018 named_count avoids having to change the way arm handles 'named' */
2019 pcum->named_count = 0;
2022 if (TARGET_REALLY_IWMMXT && fntype)
2026 for (fn_arg = TYPE_ARG_TYPES (fntype);
2028 fn_arg = TREE_CHAIN (fn_arg))
2029 pcum->named_count += 1;
2031 if (! pcum->named_count)
2032 pcum->named_count = INT_MAX;
2036 /* Determine where to put an argument to a function.
2037 Value is zero to push the argument on the stack,
2038 or a hard register in which to store the argument.
2040 MODE is the argument's machine mode.
2041 TYPE is the data type of the argument (as a tree).
2042 This is null for libcalls where that information may
2044 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2045 the preceding args and about the function being called.
2046 NAMED is nonzero if this argument is a named parameter
2047 (otherwise it is an extra parameter matching an ellipsis). */
2050 arm_function_arg (CUMULATIVE_ARGS *pcum, enum machine_mode mode,
2051 tree type ATTRIBUTE_UNUSED, int named)
2053 if (TARGET_REALLY_IWMMXT)
2055 if (VECTOR_MODE_SUPPORTED_P (mode))
2057 /* varargs vectors are treated the same as long long.
2058 named_count avoids having to change the way arm handles 'named' */
2059 if (pcum->named_count <= pcum->nargs + 1)
2061 if (pcum->nregs == 1)
2063 if (pcum->nregs <= 2)
2064 return gen_rtx_REG (mode, pcum->nregs);
2068 else if (pcum->iwmmxt_nregs <= 9)
2069 return gen_rtx_REG (mode, pcum->iwmmxt_nregs + FIRST_IWMMXT_REGNUM);
2073 else if ((mode == DImode || mode == DFmode) && pcum->nregs & 1)
2077 if (mode == VOIDmode)
2078 /* Compute operand 2 of the call insn. */
2079 return GEN_INT (pcum->call_cookie);
2081 if (!named || pcum->nregs >= NUM_ARG_REGS)
2084 return gen_rtx_REG (mode, pcum->nregs);
2087 /* Variable sized types are passed by reference. This is a GCC
2088 extension to the ARM ABI. */
2091 arm_function_arg_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
2092 enum machine_mode mode ATTRIBUTE_UNUSED,
2093 tree type, int named ATTRIBUTE_UNUSED)
2095 return type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST;
2098 /* Implement va_arg. */
2101 arm_va_arg (tree valist, tree type)
2103 /* Variable sized types are passed by reference. */
2104 if (TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
2106 rtx addr = std_expand_builtin_va_arg (valist, build_pointer_type (type));
2107 return gen_rtx_MEM (ptr_mode, force_reg (Pmode, addr));
2110 if (FUNCTION_ARG_BOUNDARY (TYPE_MODE (type), NULL) == IWMMXT_ALIGNMENT)
2115 /* Maintain 64-bit alignment of the valist pointer by
2116 constructing: valist = ((valist + (8 - 1)) & -8). */
2117 minus_eight = build_int_2 (- (IWMMXT_ALIGNMENT / BITS_PER_UNIT), -1);
2118 t = build_int_2 ((IWMMXT_ALIGNMENT / BITS_PER_UNIT) - 1, 0);
2119 t = build (PLUS_EXPR, TREE_TYPE (valist), valist, t);
2120 t = build (BIT_AND_EXPR, TREE_TYPE (t), t, minus_eight);
2121 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
2122 TREE_SIDE_EFFECTS (t) = 1;
2123 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2125 /* This is to stop the combine pass optimizing
2126 away the alignment adjustment. */
2127 mark_reg_pointer (arg_pointer_rtx, PARM_BOUNDARY);
2130 return std_expand_builtin_va_arg (valist, type);
2133 /* Encode the current state of the #pragma [no_]long_calls. */
2136 OFF, /* No #pramgma [no_]long_calls is in effect. */
2137 LONG, /* #pragma long_calls is in effect. */
2138 SHORT /* #pragma no_long_calls is in effect. */
2141 static arm_pragma_enum arm_pragma_long_calls = OFF;
2144 arm_pr_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2146 arm_pragma_long_calls = LONG;
2150 arm_pr_no_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2152 arm_pragma_long_calls = SHORT;
2156 arm_pr_long_calls_off (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2158 arm_pragma_long_calls = OFF;
2161 /* Table of machine attributes. */
2162 const struct attribute_spec arm_attribute_table[] =
2164 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
2165 /* Function calls made to this symbol must be done indirectly, because
2166 it may lie outside of the 26 bit addressing range of a normal function
2168 { "long_call", 0, 0, false, true, true, NULL },
2169 /* Whereas these functions are always known to reside within the 26 bit
2170 addressing range. */
2171 { "short_call", 0, 0, false, true, true, NULL },
2172 /* Interrupt Service Routines have special prologue and epilogue requirements. */
2173 { "isr", 0, 1, false, false, false, arm_handle_isr_attribute },
2174 { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute },
2175 { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute },
2177 /* ARM/PE has three new attributes:
2179 dllexport - for exporting a function/variable that will live in a dll
2180 dllimport - for importing a function/variable from a dll
2182 Microsoft allows multiple declspecs in one __declspec, separating
2183 them with spaces. We do NOT support this. Instead, use __declspec
2186 { "dllimport", 0, 0, true, false, false, NULL },
2187 { "dllexport", 0, 0, true, false, false, NULL },
2188 { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute },
2190 { NULL, 0, 0, false, false, false, NULL }
2193 /* Handle an attribute requiring a FUNCTION_DECL;
2194 arguments as in struct attribute_spec.handler. */
2196 arm_handle_fndecl_attribute (tree *node, tree name, tree args ATTRIBUTE_UNUSED,
2197 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
2199 if (TREE_CODE (*node) != FUNCTION_DECL)
2201 warning ("`%s' attribute only applies to functions",
2202 IDENTIFIER_POINTER (name));
2203 *no_add_attrs = true;
2209 /* Handle an "interrupt" or "isr" attribute;
2210 arguments as in struct attribute_spec.handler. */
2212 arm_handle_isr_attribute (tree *node, tree name, tree args, int flags,
2217 if (TREE_CODE (*node) != FUNCTION_DECL)
2219 warning ("`%s' attribute only applies to functions",
2220 IDENTIFIER_POINTER (name));
2221 *no_add_attrs = true;
2223 /* FIXME: the argument if any is checked for type attributes;
2224 should it be checked for decl ones? */
2228 if (TREE_CODE (*node) == FUNCTION_TYPE
2229 || TREE_CODE (*node) == METHOD_TYPE)
2231 if (arm_isr_value (args) == ARM_FT_UNKNOWN)
2233 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
2234 *no_add_attrs = true;
2237 else if (TREE_CODE (*node) == POINTER_TYPE
2238 && (TREE_CODE (TREE_TYPE (*node)) == FUNCTION_TYPE
2239 || TREE_CODE (TREE_TYPE (*node)) == METHOD_TYPE)
2240 && arm_isr_value (args) != ARM_FT_UNKNOWN)
2242 *node = build_type_copy (*node);
2243 TREE_TYPE (*node) = build_type_attribute_variant
2245 tree_cons (name, args, TYPE_ATTRIBUTES (TREE_TYPE (*node))));
2246 *no_add_attrs = true;
2250 /* Possibly pass this attribute on from the type to a decl. */
2251 if (flags & ((int) ATTR_FLAG_DECL_NEXT
2252 | (int) ATTR_FLAG_FUNCTION_NEXT
2253 | (int) ATTR_FLAG_ARRAY_NEXT))
2255 *no_add_attrs = true;
2256 return tree_cons (name, args, NULL_TREE);
2260 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
2268 /* Return 0 if the attributes for two types are incompatible, 1 if they
2269 are compatible, and 2 if they are nearly compatible (which causes a
2270 warning to be generated). */
2272 arm_comp_type_attributes (tree type1, tree type2)
2276 /* Check for mismatch of non-default calling convention. */
2277 if (TREE_CODE (type1) != FUNCTION_TYPE)
2280 /* Check for mismatched call attributes. */
2281 l1 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1)) != NULL;
2282 l2 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2)) != NULL;
2283 s1 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1)) != NULL;
2284 s2 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2)) != NULL;
2286 /* Only bother to check if an attribute is defined. */
2287 if (l1 | l2 | s1 | s2)
2289 /* If one type has an attribute, the other must have the same attribute. */
2290 if ((l1 != l2) || (s1 != s2))
2293 /* Disallow mixed attributes. */
2294 if ((l1 & s2) || (l2 & s1))
2298 /* Check for mismatched ISR attribute. */
2299 l1 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type1)) != NULL;
2301 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1)) != NULL;
2302 l2 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type2)) != NULL;
2304 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2)) != NULL;
2311 /* Encode long_call or short_call attribute by prefixing
2312 symbol name in DECL with a special character FLAG. */
2314 arm_encode_call_attribute (tree decl, int flag)
2316 const char * str = XSTR (XEXP (DECL_RTL (decl), 0), 0);
2317 int len = strlen (str);
2320 /* Do not allow weak functions to be treated as short call. */
2321 if (DECL_WEAK (decl) && flag == SHORT_CALL_FLAG_CHAR)
2324 newstr = alloca (len + 2);
2326 strcpy (newstr + 1, str);
2328 newstr = (char *) ggc_alloc_string (newstr, len + 1);
2329 XSTR (XEXP (DECL_RTL (decl), 0), 0) = newstr;
2332 /* Assigns default attributes to newly defined type. This is used to
2333 set short_call/long_call attributes for function types of
2334 functions defined inside corresponding #pragma scopes. */
2336 arm_set_default_type_attributes (tree type)
2338 /* Add __attribute__ ((long_call)) to all functions, when
2339 inside #pragma long_calls or __attribute__ ((short_call)),
2340 when inside #pragma no_long_calls. */
2341 if (TREE_CODE (type) == FUNCTION_TYPE || TREE_CODE (type) == METHOD_TYPE)
2343 tree type_attr_list, attr_name;
2344 type_attr_list = TYPE_ATTRIBUTES (type);
2346 if (arm_pragma_long_calls == LONG)
2347 attr_name = get_identifier ("long_call");
2348 else if (arm_pragma_long_calls == SHORT)
2349 attr_name = get_identifier ("short_call");
2353 type_attr_list = tree_cons (attr_name, NULL_TREE, type_attr_list);
2354 TYPE_ATTRIBUTES (type) = type_attr_list;
2358 /* Return 1 if the operand is a SYMBOL_REF for a function known to be
2359 defined within the current compilation unit. If this cannot be
2360 determined, then 0 is returned. */
2362 current_file_function_operand (rtx sym_ref)
2364 /* This is a bit of a fib. A function will have a short call flag
2365 applied to its name if it has the short call attribute, or it has
2366 already been defined within the current compilation unit. */
2367 if (ENCODED_SHORT_CALL_ATTR_P (XSTR (sym_ref, 0)))
2370 /* The current function is always defined within the current compilation
2371 unit. if it s a weak definition however, then this may not be the real
2372 definition of the function, and so we have to say no. */
2373 if (sym_ref == XEXP (DECL_RTL (current_function_decl), 0)
2374 && !DECL_WEAK (current_function_decl))
2377 /* We cannot make the determination - default to returning 0. */
2381 /* Return nonzero if a 32 bit "long_call" should be generated for
2382 this call. We generate a long_call if the function:
2384 a. has an __attribute__((long call))
2385 or b. is within the scope of a #pragma long_calls
2386 or c. the -mlong-calls command line switch has been specified
2388 However we do not generate a long call if the function:
2390 d. has an __attribute__ ((short_call))
2391 or e. is inside the scope of a #pragma no_long_calls
2392 or f. has an __attribute__ ((section))
2393 or g. is defined within the current compilation unit.
2395 This function will be called by C fragments contained in the machine
2396 description file. CALL_REF and CALL_COOKIE correspond to the matched
2397 rtl operands. CALL_SYMBOL is used to distinguish between
2398 two different callers of the function. It is set to 1 in the
2399 "call_symbol" and "call_symbol_value" patterns and to 0 in the "call"
2400 and "call_value" patterns. This is because of the difference in the
2401 SYM_REFs passed by these patterns. */
2403 arm_is_longcall_p (rtx sym_ref, int call_cookie, int call_symbol)
2407 if (GET_CODE (sym_ref) != MEM)
2410 sym_ref = XEXP (sym_ref, 0);
2413 if (GET_CODE (sym_ref) != SYMBOL_REF)
2416 if (call_cookie & CALL_SHORT)
2419 if (TARGET_LONG_CALLS && flag_function_sections)
2422 if (current_file_function_operand (sym_ref))
2425 return (call_cookie & CALL_LONG)
2426 || ENCODED_LONG_CALL_ATTR_P (XSTR (sym_ref, 0))
2427 || TARGET_LONG_CALLS;
2430 /* Return nonzero if it is ok to make a tail-call to DECL. */
2432 arm_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
2434 int call_type = TARGET_LONG_CALLS ? CALL_LONG : CALL_NORMAL;
2436 if (cfun->machine->sibcall_blocked)
2439 /* Never tailcall something for which we have no decl, or if we
2440 are in Thumb mode. */
2441 if (decl == NULL || TARGET_THUMB)
2444 /* Get the calling method. */
2445 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
2446 call_type = CALL_SHORT;
2447 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
2448 call_type = CALL_LONG;
2450 /* Cannot tail-call to long calls, since these are out of range of
2451 a branch instruction. However, if not compiling PIC, we know
2452 we can reach the symbol if it is in this compilation unit. */
2453 if (call_type == CALL_LONG && (flag_pic || !TREE_ASM_WRITTEN (decl)))
2456 /* If we are interworking and the function is not declared static
2457 then we can't tail-call it unless we know that it exists in this
2458 compilation unit (since it might be a Thumb routine). */
2459 if (TARGET_INTERWORK && TREE_PUBLIC (decl) && !TREE_ASM_WRITTEN (decl))
2462 /* Never tailcall from an ISR routine - it needs a special exit sequence. */
2463 if (IS_INTERRUPT (arm_current_func_type ()))
2466 /* Everything else is ok. */
2471 /* Addressing mode support functions. */
2473 /* Return nonzero if X is a legitimate immediate operand when compiling
2476 legitimate_pic_operand_p (rtx x)
2480 && (GET_CODE (x) == SYMBOL_REF
2481 || (GET_CODE (x) == CONST
2482 && GET_CODE (XEXP (x, 0)) == PLUS
2483 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)))
2490 legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg)
2492 if (GET_CODE (orig) == SYMBOL_REF
2493 || GET_CODE (orig) == LABEL_REF)
2495 #ifndef AOF_ASSEMBLER
2496 rtx pic_ref, address;
2506 reg = gen_reg_rtx (Pmode);
2511 #ifdef AOF_ASSEMBLER
2512 /* The AOF assembler can generate relocations for these directly, and
2513 understands that the PIC register has to be added into the offset. */
2514 insn = emit_insn (gen_pic_load_addr_based (reg, orig));
2517 address = gen_reg_rtx (Pmode);
2522 emit_insn (gen_pic_load_addr_arm (address, orig));
2524 emit_insn (gen_pic_load_addr_thumb (address, orig));
2526 if ((GET_CODE (orig) == LABEL_REF
2527 || (GET_CODE (orig) == SYMBOL_REF &&
2528 SYMBOL_REF_LOCAL_P (orig)))
2530 pic_ref = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, address);
2533 pic_ref = gen_rtx_MEM (Pmode,
2534 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
2536 RTX_UNCHANGING_P (pic_ref) = 1;
2539 insn = emit_move_insn (reg, pic_ref);
2541 current_function_uses_pic_offset_table = 1;
2542 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2544 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
2548 else if (GET_CODE (orig) == CONST)
2552 if (GET_CODE (XEXP (orig, 0)) == PLUS
2553 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
2561 reg = gen_reg_rtx (Pmode);
2564 if (GET_CODE (XEXP (orig, 0)) == PLUS)
2566 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
2567 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
2568 base == reg ? 0 : reg);
2573 if (GET_CODE (offset) == CONST_INT)
2575 /* The base register doesn't really matter, we only want to
2576 test the index for the appropriate mode. */
2577 if (!arm_legitimate_index_p (mode, offset, 0))
2579 if (!no_new_pseudos)
2580 offset = force_reg (Pmode, offset);
2585 if (GET_CODE (offset) == CONST_INT)
2586 return plus_constant (base, INTVAL (offset));
2589 if (GET_MODE_SIZE (mode) > 4
2590 && (GET_MODE_CLASS (mode) == MODE_INT
2591 || TARGET_SOFT_FLOAT))
2593 emit_insn (gen_addsi3 (reg, base, offset));
2597 return gen_rtx_PLUS (Pmode, base, offset);
2603 /* Generate code to load the PIC register. PROLOGUE is true if
2604 called from arm_expand_prologue (in which case we want the
2605 generated insns at the start of the function); false if called
2606 by an exception receiver that needs the PIC register reloaded
2607 (in which case the insns are just dumped at the current location). */
2609 arm_finalize_pic (int prologue ATTRIBUTE_UNUSED)
2611 #ifndef AOF_ASSEMBLER
2612 rtx l1, pic_tmp, pic_tmp2, seq, pic_rtx;
2613 rtx global_offset_table;
2615 if (current_function_uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE)
2622 l1 = gen_label_rtx ();
2624 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
2625 /* On the ARM the PC register contains 'dot + 8' at the time of the
2626 addition, on the Thumb it is 'dot + 4'. */
2627 pic_tmp = plus_constant (gen_rtx_LABEL_REF (Pmode, l1), TARGET_ARM ? 8 : 4);
2629 pic_tmp2 = gen_rtx_CONST (VOIDmode,
2630 gen_rtx_PLUS (Pmode, global_offset_table, pc_rtx));
2632 pic_tmp2 = gen_rtx_CONST (VOIDmode, global_offset_table);
2634 pic_rtx = gen_rtx_CONST (Pmode, gen_rtx_MINUS (Pmode, pic_tmp2, pic_tmp));
2638 emit_insn (gen_pic_load_addr_arm (pic_offset_table_rtx, pic_rtx));
2639 emit_insn (gen_pic_add_dot_plus_eight (pic_offset_table_rtx, l1));
2643 emit_insn (gen_pic_load_addr_thumb (pic_offset_table_rtx, pic_rtx));
2644 emit_insn (gen_pic_add_dot_plus_four (pic_offset_table_rtx, l1));
2650 emit_insn_after (seq, get_insns ());
2654 /* Need to emit this whether or not we obey regdecls,
2655 since setjmp/longjmp can cause life info to screw up. */
2656 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
2657 #endif /* AOF_ASSEMBLER */
2660 /* Return nonzero if X is valid as an ARM state addressing register. */
2662 arm_address_register_rtx_p (rtx x, int strict_p)
2666 if (GET_CODE (x) != REG)
2672 return ARM_REGNO_OK_FOR_BASE_P (regno);
2674 return (regno <= LAST_ARM_REGNUM
2675 || regno >= FIRST_PSEUDO_REGISTER
2676 || regno == FRAME_POINTER_REGNUM
2677 || regno == ARG_POINTER_REGNUM);
2680 /* Return nonzero if X is a valid ARM state address operand. */
2682 arm_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p)
2684 if (arm_address_register_rtx_p (x, strict_p))
2687 else if (GET_CODE (x) == POST_INC || GET_CODE (x) == PRE_DEC)
2688 return arm_address_register_rtx_p (XEXP (x, 0), strict_p);
2690 else if ((GET_CODE (x) == POST_MODIFY || GET_CODE (x) == PRE_MODIFY)
2691 && GET_MODE_SIZE (mode) <= 4
2692 && arm_address_register_rtx_p (XEXP (x, 0), strict_p)
2693 && GET_CODE (XEXP (x, 1)) == PLUS
2694 && XEXP (XEXP (x, 1), 0) == XEXP (x, 0))
2695 return arm_legitimate_index_p (mode, XEXP (XEXP (x, 1), 1), strict_p);
2697 /* After reload constants split into minipools will have addresses
2698 from a LABEL_REF. */
2699 else if (GET_MODE_SIZE (mode) >= 4 && reload_completed
2700 && (GET_CODE (x) == LABEL_REF
2701 || (GET_CODE (x) == CONST
2702 && GET_CODE (XEXP (x, 0)) == PLUS
2703 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
2704 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
2707 else if (mode == TImode)
2710 else if (mode == DImode || (TARGET_SOFT_FLOAT && mode == DFmode))
2712 if (GET_CODE (x) == PLUS
2713 && arm_address_register_rtx_p (XEXP (x, 0), strict_p)
2714 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2716 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
2718 if (val == 4 || val == -4 || val == -8)
2723 else if (GET_CODE (x) == PLUS)
2725 rtx xop0 = XEXP (x, 0);
2726 rtx xop1 = XEXP (x, 1);
2728 return ((arm_address_register_rtx_p (xop0, strict_p)
2729 && arm_legitimate_index_p (mode, xop1, strict_p))
2730 || (arm_address_register_rtx_p (xop1, strict_p)
2731 && arm_legitimate_index_p (mode, xop0, strict_p)));
2735 /* Reload currently can't handle MINUS, so disable this for now */
2736 else if (GET_CODE (x) == MINUS)
2738 rtx xop0 = XEXP (x, 0);
2739 rtx xop1 = XEXP (x, 1);
2741 return (arm_address_register_rtx_p (xop0, strict_p)
2742 && arm_legitimate_index_p (mode, xop1, strict_p));
2746 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
2747 && GET_CODE (x) == SYMBOL_REF
2748 && CONSTANT_POOL_ADDRESS_P (x)
2750 && symbol_mentioned_p (get_pool_constant (x))))
2753 else if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == POST_DEC)
2754 && (GET_MODE_SIZE (mode) <= 4)
2755 && arm_address_register_rtx_p (XEXP (x, 0), strict_p))
2761 /* Return nonzero if INDEX is valid for an address index operand in
2764 arm_legitimate_index_p (enum machine_mode mode, rtx index, int strict_p)
2766 HOST_WIDE_INT range;
2767 enum rtx_code code = GET_CODE (index);
2769 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
2770 return (code == CONST_INT && INTVAL (index) < 1024
2771 && INTVAL (index) > -1024
2772 && (INTVAL (index) & 3) == 0);
2775 && (GET_MODE_CLASS (mode) == MODE_FLOAT || mode == DImode))
2776 return (code == CONST_INT
2777 && INTVAL (index) < 255
2778 && INTVAL (index) > -255);
2780 if (arm_address_register_rtx_p (index, strict_p)
2781 && GET_MODE_SIZE (mode) <= 4)
2784 if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))
2785 return (code == CONST_INT
2786 && INTVAL (index) < 256
2787 && INTVAL (index) > -256);
2789 /* XXX What about ldrsb? */
2790 if (GET_MODE_SIZE (mode) <= 4 && code == MULT
2791 && (!arm_arch4 || (mode) != HImode))
2793 rtx xiop0 = XEXP (index, 0);
2794 rtx xiop1 = XEXP (index, 1);
2796 return ((arm_address_register_rtx_p (xiop0, strict_p)
2797 && power_of_two_operand (xiop1, SImode))
2798 || (arm_address_register_rtx_p (xiop1, strict_p)
2799 && power_of_two_operand (xiop0, SImode)));
2802 if (GET_MODE_SIZE (mode) <= 4
2803 && (code == LSHIFTRT || code == ASHIFTRT
2804 || code == ASHIFT || code == ROTATERT)
2805 && (!arm_arch4 || (mode) != HImode))
2807 rtx op = XEXP (index, 1);
2809 return (arm_address_register_rtx_p (XEXP (index, 0), strict_p)
2810 && GET_CODE (op) == CONST_INT
2812 && INTVAL (op) <= 31);
2815 /* XXX For ARM v4 we may be doing a sign-extend operation during the
2816 load, but that has a restricted addressing range and we are unable
2817 to tell here whether that is the case. To be safe we restrict all
2818 loads to that range. */
2819 range = ((mode) == HImode || (mode) == QImode)
2820 ? (arm_arch4 ? 256 : 4095) : 4096;
2822 return (code == CONST_INT
2823 && INTVAL (index) < range
2824 && INTVAL (index) > -range);
2827 /* Return nonzero if X is valid as an ARM state addressing register. */
2829 thumb_base_register_rtx_p (rtx x, enum machine_mode mode, int strict_p)
2833 if (GET_CODE (x) != REG)
2839 return THUMB_REGNO_MODE_OK_FOR_BASE_P (regno, mode);
2841 return (regno <= LAST_LO_REGNUM
2842 || regno >= FIRST_PSEUDO_REGISTER
2843 || regno == FRAME_POINTER_REGNUM
2844 || (GET_MODE_SIZE (mode) >= 4
2845 && (regno == STACK_POINTER_REGNUM
2846 || x == hard_frame_pointer_rtx
2847 || x == arg_pointer_rtx)));
2850 /* Return nonzero if x is a legitimate index register. This is the case
2851 for any base register that can access a QImode object. */
2853 thumb_index_register_rtx_p (rtx x, int strict_p)
2855 return thumb_base_register_rtx_p (x, QImode, strict_p);
2858 /* Return nonzero if x is a legitimate Thumb-state address.
2860 The AP may be eliminated to either the SP or the FP, so we use the
2861 least common denominator, e.g. SImode, and offsets from 0 to 64.
2863 ??? Verify whether the above is the right approach.
2865 ??? Also, the FP may be eliminated to the SP, so perhaps that
2866 needs special handling also.
2868 ??? Look at how the mips16 port solves this problem. It probably uses
2869 better ways to solve some of these problems.
2871 Although it is not incorrect, we don't accept QImode and HImode
2872 addresses based on the frame pointer or arg pointer until the
2873 reload pass starts. This is so that eliminating such addresses
2874 into stack based ones won't produce impossible code. */
2876 thumb_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p)
2878 /* ??? Not clear if this is right. Experiment. */
2879 if (GET_MODE_SIZE (mode) < 4
2880 && !(reload_in_progress || reload_completed)
2881 && (reg_mentioned_p (frame_pointer_rtx, x)
2882 || reg_mentioned_p (arg_pointer_rtx, x)
2883 || reg_mentioned_p (virtual_incoming_args_rtx, x)
2884 || reg_mentioned_p (virtual_outgoing_args_rtx, x)
2885 || reg_mentioned_p (virtual_stack_dynamic_rtx, x)
2886 || reg_mentioned_p (virtual_stack_vars_rtx, x)))
2889 /* Accept any base register. SP only in SImode or larger. */
2890 else if (thumb_base_register_rtx_p (x, mode, strict_p))
2893 /* This is PC relative data before arm_reorg runs. */
2894 else if (GET_MODE_SIZE (mode) >= 4 && CONSTANT_P (x)
2895 && GET_CODE (x) == SYMBOL_REF
2896 && CONSTANT_POOL_ADDRESS_P (x) && ! flag_pic)
2899 /* This is PC relative data after arm_reorg runs. */
2900 else if (GET_MODE_SIZE (mode) >= 4 && reload_completed
2901 && (GET_CODE (x) == LABEL_REF
2902 || (GET_CODE (x) == CONST
2903 && GET_CODE (XEXP (x, 0)) == PLUS
2904 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
2905 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
2908 /* Post-inc indexing only supported for SImode and larger. */
2909 else if (GET_CODE (x) == POST_INC && GET_MODE_SIZE (mode) >= 4
2910 && thumb_index_register_rtx_p (XEXP (x, 0), strict_p))
2913 else if (GET_CODE (x) == PLUS)
2915 /* REG+REG address can be any two index registers. */
2916 /* We disallow FRAME+REG addressing since we know that FRAME
2917 will be replaced with STACK, and SP relative addressing only
2918 permits SP+OFFSET. */
2919 if (GET_MODE_SIZE (mode) <= 4
2920 && XEXP (x, 0) != frame_pointer_rtx
2921 && XEXP (x, 1) != frame_pointer_rtx
2922 && XEXP (x, 0) != virtual_stack_vars_rtx
2923 && XEXP (x, 1) != virtual_stack_vars_rtx
2924 && thumb_index_register_rtx_p (XEXP (x, 0), strict_p)
2925 && thumb_index_register_rtx_p (XEXP (x, 1), strict_p))
2928 /* REG+const has 5-7 bit offset for non-SP registers. */
2929 else if ((thumb_index_register_rtx_p (XEXP (x, 0), strict_p)
2930 || XEXP (x, 0) == arg_pointer_rtx)
2931 && GET_CODE (XEXP (x, 1)) == CONST_INT
2932 && thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1))))
2935 /* REG+const has 10 bit offset for SP, but only SImode and
2936 larger is supported. */
2937 /* ??? Should probably check for DI/DFmode overflow here
2938 just like GO_IF_LEGITIMATE_OFFSET does. */
2939 else if (GET_CODE (XEXP (x, 0)) == REG
2940 && REGNO (XEXP (x, 0)) == STACK_POINTER_REGNUM
2941 && GET_MODE_SIZE (mode) >= 4
2942 && GET_CODE (XEXP (x, 1)) == CONST_INT
2943 && INTVAL (XEXP (x, 1)) >= 0
2944 && INTVAL (XEXP (x, 1)) + GET_MODE_SIZE (mode) <= 1024
2945 && (INTVAL (XEXP (x, 1)) & 3) == 0)
2948 else if (GET_CODE (XEXP (x, 0)) == REG
2949 && REGNO (XEXP (x, 0)) == FRAME_POINTER_REGNUM
2950 && GET_MODE_SIZE (mode) >= 4
2951 && GET_CODE (XEXP (x, 1)) == CONST_INT
2952 && (INTVAL (XEXP (x, 1)) & 3) == 0)
2956 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
2957 && GET_CODE (x) == SYMBOL_REF
2958 && CONSTANT_POOL_ADDRESS_P (x)
2960 && symbol_mentioned_p (get_pool_constant (x))))
2966 /* Return nonzero if VAL can be used as an offset in a Thumb-state address
2967 instruction of mode MODE. */
2969 thumb_legitimate_offset_p (enum machine_mode mode, HOST_WIDE_INT val)
2971 switch (GET_MODE_SIZE (mode))
2974 return val >= 0 && val < 32;
2977 return val >= 0 && val < 64 && (val & 1) == 0;
2981 && (val + GET_MODE_SIZE (mode)) <= 128
2986 /* Try machine-dependent ways of modifying an illegitimate address
2987 to be legitimate. If we find one, return the new, valid address. */
2989 arm_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)
2991 if (GET_CODE (x) == PLUS)
2993 rtx xop0 = XEXP (x, 0);
2994 rtx xop1 = XEXP (x, 1);
2996 if (CONSTANT_P (xop0) && !symbol_mentioned_p (xop0))
2997 xop0 = force_reg (SImode, xop0);
2999 if (CONSTANT_P (xop1) && !symbol_mentioned_p (xop1))
3000 xop1 = force_reg (SImode, xop1);
3002 if (ARM_BASE_REGISTER_RTX_P (xop0)
3003 && GET_CODE (xop1) == CONST_INT)
3005 HOST_WIDE_INT n, low_n;
3009 if (mode == DImode || (TARGET_SOFT_FLOAT && mode == DFmode))
3021 low_n = ((mode) == TImode ? 0
3022 : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff));
3026 base_reg = gen_reg_rtx (SImode);
3027 val = force_operand (gen_rtx_PLUS (SImode, xop0,
3028 GEN_INT (n)), NULL_RTX);
3029 emit_move_insn (base_reg, val);
3030 x = (low_n == 0 ? base_reg
3031 : gen_rtx_PLUS (SImode, base_reg, GEN_INT (low_n)));
3033 else if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1))
3034 x = gen_rtx_PLUS (SImode, xop0, xop1);
3037 /* XXX We don't allow MINUS any more -- see comment in
3038 arm_legitimate_address_p (). */
3039 else if (GET_CODE (x) == MINUS)
3041 rtx xop0 = XEXP (x, 0);
3042 rtx xop1 = XEXP (x, 1);
3044 if (CONSTANT_P (xop0))
3045 xop0 = force_reg (SImode, xop0);
3047 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1))
3048 xop1 = force_reg (SImode, xop1);
3050 if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1))
3051 x = gen_rtx_MINUS (SImode, xop0, xop1);
3056 /* We need to find and carefully transform any SYMBOL and LABEL
3057 references; so go back to the original address expression. */
3058 rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX);
3060 if (new_x != orig_x)
3069 #define REG_OR_SUBREG_REG(X) \
3070 (GET_CODE (X) == REG \
3071 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
3073 #define REG_OR_SUBREG_RTX(X) \
3074 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
3076 #ifndef COSTS_N_INSNS
3077 #define COSTS_N_INSNS(N) ((N) * 4 - 2)
3079 /* Worker routine for arm_rtx_costs. */
3081 arm_rtx_costs_1 (rtx x, enum rtx_code code, enum rtx_code outer)
3083 enum machine_mode mode = GET_MODE (x);
3084 enum rtx_code subcode;
3100 return COSTS_N_INSNS (1);
3103 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
3106 unsigned HOST_WIDE_INT i = INTVAL (XEXP (x, 1));
3113 return COSTS_N_INSNS (2) + cycles;
3115 return COSTS_N_INSNS (1) + 16;
3118 return (COSTS_N_INSNS (1)
3119 + 4 * ((GET_CODE (SET_SRC (x)) == MEM)
3120 + GET_CODE (SET_DEST (x)) == MEM));
3125 if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256)
3127 if (thumb_shiftable_const (INTVAL (x)))
3128 return COSTS_N_INSNS (2);
3129 return COSTS_N_INSNS (3);
3131 else if ((outer == PLUS || outer == COMPARE)
3132 && INTVAL (x) < 256 && INTVAL (x) > -256)
3134 else if (outer == AND
3135 && INTVAL (x) < 256 && INTVAL (x) >= -256)
3136 return COSTS_N_INSNS (1);
3137 else if (outer == ASHIFT || outer == ASHIFTRT
3138 || outer == LSHIFTRT)
3140 return COSTS_N_INSNS (2);
3146 return COSTS_N_INSNS (3);
3165 /* XXX another guess. */
3166 /* Memory costs quite a lot for the first word, but subsequent words
3167 load at the equivalent of a single insn each. */
3168 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
3169 + ((GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
3174 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
3179 /* XXX still guessing. */
3180 switch (GET_MODE (XEXP (x, 0)))
3183 return (1 + (mode == DImode ? 4 : 0)
3184 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3187 return (4 + (mode == DImode ? 4 : 0)
3188 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3191 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3205 /* Memory costs quite a lot for the first word, but subsequent words
3206 load at the equivalent of a single insn each. */
3207 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
3208 + (GET_CODE (x) == SYMBOL_REF
3209 && CONSTANT_POOL_ADDRESS_P (x) ? 4 : 0));
3215 return optimize_size ? COSTS_N_INSNS (2) : 100;
3218 if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG)
3225 case ASHIFT: case LSHIFTRT: case ASHIFTRT:
3227 return (8 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : 8)
3228 + ((GET_CODE (XEXP (x, 0)) == REG
3229 || (GET_CODE (XEXP (x, 0)) == SUBREG
3230 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
3232 return (1 + ((GET_CODE (XEXP (x, 0)) == REG
3233 || (GET_CODE (XEXP (x, 0)) == SUBREG
3234 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
3236 + ((GET_CODE (XEXP (x, 1)) == REG
3237 || (GET_CODE (XEXP (x, 1)) == SUBREG
3238 && GET_CODE (SUBREG_REG (XEXP (x, 1))) == REG)
3239 || (GET_CODE (XEXP (x, 1)) == CONST_INT))
3244 return (4 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 8)
3245 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
3246 || (GET_CODE (XEXP (x, 0)) == CONST_INT
3247 && const_ok_for_arm (INTVAL (XEXP (x, 0)))))
3250 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
3251 return (2 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
3252 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
3253 && const_double_rtx_ok_for_fpa (XEXP (x, 1))))
3255 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
3256 || (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE
3257 && const_double_rtx_ok_for_fpa (XEXP (x, 0))))
3260 if (((GET_CODE (XEXP (x, 0)) == CONST_INT
3261 && const_ok_for_arm (INTVAL (XEXP (x, 0)))
3262 && REG_OR_SUBREG_REG (XEXP (x, 1))))
3263 || (((subcode = GET_CODE (XEXP (x, 1))) == ASHIFT
3264 || subcode == ASHIFTRT || subcode == LSHIFTRT
3265 || subcode == ROTATE || subcode == ROTATERT
3267 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
3268 && ((INTVAL (XEXP (XEXP (x, 1), 1)) &
3269 (INTVAL (XEXP (XEXP (x, 1), 1)) - 1)) == 0)))
3270 && REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 0))
3271 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 1))
3272 || GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT)
3273 && REG_OR_SUBREG_REG (XEXP (x, 0))))
3278 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
3279 return (2 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
3280 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
3281 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
3282 && const_double_rtx_ok_for_fpa (XEXP (x, 1))))
3286 case AND: case XOR: case IOR:
3289 /* Normally the frame registers will be spilt into reg+const during
3290 reload, so it is a bad idea to combine them with other instructions,
3291 since then they might not be moved outside of loops. As a compromise
3292 we allow integration with ops that have a constant as their second
3294 if ((REG_OR_SUBREG_REG (XEXP (x, 0))
3295 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))
3296 && GET_CODE (XEXP (x, 1)) != CONST_INT)
3297 || (REG_OR_SUBREG_REG (XEXP (x, 0))
3298 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))))
3302 return (4 + extra_cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
3303 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
3304 || (GET_CODE (XEXP (x, 1)) == CONST_INT
3305 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
3308 if (REG_OR_SUBREG_REG (XEXP (x, 0)))
3309 return (1 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : extra_cost)
3310 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
3311 || (GET_CODE (XEXP (x, 1)) == CONST_INT
3312 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
3315 else if (REG_OR_SUBREG_REG (XEXP (x, 1)))
3316 return (1 + extra_cost
3317 + ((((subcode = GET_CODE (XEXP (x, 0))) == ASHIFT
3318 || subcode == LSHIFTRT || subcode == ASHIFTRT
3319 || subcode == ROTATE || subcode == ROTATERT
3321 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3322 && ((INTVAL (XEXP (XEXP (x, 0), 1)) &
3323 (INTVAL (XEXP (XEXP (x, 0), 1)) - 1)) == 0)))
3324 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 0)))
3325 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 1)))
3326 || GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))
3332 /* There is no point basing this on the tuning, since it is always the
3333 fast variant if it exists at all. */
3334 if (arm_fast_multiply && mode == DImode
3335 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
3336 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
3337 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
3340 if (GET_MODE_CLASS (mode) == MODE_FLOAT
3344 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
3346 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
3347 & (unsigned HOST_WIDE_INT) 0xffffffff);
3348 int add_cost = const_ok_for_arm (i) ? 4 : 8;
3351 /* Tune as appropriate. */
3352 int booth_unit_size = ((tune_flags & FL_FAST_MULT) ? 8 : 2);
3354 for (j = 0; i && j < 32; j += booth_unit_size)
3356 i >>= booth_unit_size;
3363 return (((tune_flags & FL_FAST_MULT) ? 8 : 30)
3364 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
3365 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4));
3368 if (arm_fast_multiply && mode == SImode
3369 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
3370 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
3371 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0))
3372 == GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)))
3373 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ZERO_EXTEND
3374 || GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SIGN_EXTEND))
3379 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
3380 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 6);
3384 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
3386 return 1 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
3389 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
3397 return 4 + (mode == DImode ? 4 : 0);
3400 if (GET_MODE (XEXP (x, 0)) == QImode)
3401 return (4 + (mode == DImode ? 4 : 0)
3402 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3405 switch (GET_MODE (XEXP (x, 0)))
3408 return (1 + (mode == DImode ? 4 : 0)
3409 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3412 return (4 + (mode == DImode ? 4 : 0)
3413 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3416 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3431 if (const_ok_for_arm (INTVAL (x)))
3432 return outer == SET ? 2 : -1;
3433 else if (outer == AND
3434 && const_ok_for_arm (~INTVAL (x)))
3436 else if ((outer == COMPARE
3437 || outer == PLUS || outer == MINUS)
3438 && const_ok_for_arm (-INTVAL (x)))
3449 if (const_double_rtx_ok_for_fpa (x))
3450 return outer == SET ? 2 : -1;
3451 else if ((outer == COMPARE || outer == PLUS)
3452 && neg_const_double_rtx_ok_for_fpa (x))
3462 arm_rtx_costs (rtx x, int code, int outer_code, int *total)
3464 *total = arm_rtx_costs_1 (x, code, outer_code);
3468 /* All address computations that can be done are free, but rtx cost returns
3469 the same for practically all of them. So we weight the different types
3470 of address here in the order (most pref first):
3471 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
3473 arm_address_cost (rtx x)
3475 #define ARM_ADDRESS_COST(X) \
3476 (10 - ((GET_CODE (X) == MEM || GET_CODE (X) == LABEL_REF \
3477 || GET_CODE (X) == SYMBOL_REF) \
3479 : ((GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC \
3480 || GET_CODE (X) == POST_INC || GET_CODE (X) == POST_DEC) \
3482 : (((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS) \
3483 ? 6 + (GET_CODE (XEXP (X, 1)) == CONST_INT ? 2 \
3484 : ((GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == '2' \
3485 || GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == 'c' \
3486 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == '2' \
3487 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == 'c') \
3491 #define THUMB_ADDRESS_COST(X) \
3492 ((GET_CODE (X) == REG \
3493 || (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG \
3494 && GET_CODE (XEXP (X, 1)) == CONST_INT)) \
3497 return (TARGET_ARM ? ARM_ADDRESS_COST (x) : THUMB_ADDRESS_COST (x));
3501 arm_use_dfa_pipeline_interface (void)
3507 arm_adjust_cost (rtx insn, rtx link, rtx dep, int cost)
3511 /* Some true dependencies can have a higher cost depending
3512 on precisely how certain input operands are used. */
3514 && REG_NOTE_KIND (link) == 0
3515 && recog_memoized (insn) >= 0
3516 && recog_memoized (dep) >= 0)
3518 int shift_opnum = get_attr_shift (insn);
3519 enum attr_type attr_type = get_attr_type (dep);
3521 /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted
3522 operand for INSN. If we have a shifted input operand and the
3523 instruction we depend on is another ALU instruction, then we may
3524 have to account for an additional stall. */
3525 if (shift_opnum != 0 && attr_type == TYPE_NORMAL)
3527 rtx shifted_operand;
3530 /* Get the shifted operand. */
3531 extract_insn (insn);
3532 shifted_operand = recog_data.operand[shift_opnum];
3534 /* Iterate over all the operands in DEP. If we write an operand
3535 that overlaps with SHIFTED_OPERAND, then we have increase the
3536 cost of this dependency. */
3538 preprocess_constraints ();
3539 for (opno = 0; opno < recog_data.n_operands; opno++)
3541 /* We can ignore strict inputs. */
3542 if (recog_data.operand_type[opno] == OP_IN)
3545 if (reg_overlap_mentioned_p (recog_data.operand[opno],
3552 /* XXX This is not strictly true for the FPA. */
3553 if (REG_NOTE_KIND (link) == REG_DEP_ANTI
3554 || REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
3557 /* Call insns don't incur a stall, even if they follow a load. */
3558 if (REG_NOTE_KIND (link) == 0
3559 && GET_CODE (insn) == CALL_INSN)
3562 if ((i_pat = single_set (insn)) != NULL
3563 && GET_CODE (SET_SRC (i_pat)) == MEM
3564 && (d_pat = single_set (dep)) != NULL
3565 && GET_CODE (SET_DEST (d_pat)) == MEM)
3567 rtx src_mem = XEXP (SET_SRC (i_pat), 0);
3568 /* This is a load after a store, there is no conflict if the load reads
3569 from a cached area. Assume that loads from the stack, and from the
3570 constant pool are cached, and that others will miss. This is a
3573 if ((GET_CODE (src_mem) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (src_mem))
3574 || reg_mentioned_p (stack_pointer_rtx, src_mem)
3575 || reg_mentioned_p (frame_pointer_rtx, src_mem)
3576 || reg_mentioned_p (hard_frame_pointer_rtx, src_mem))
3583 static int fpa_consts_inited = 0;
3585 static const char * const strings_fpa[8] =
3588 "4", "5", "0.5", "10"
3591 static REAL_VALUE_TYPE values_fpa[8];
3594 init_fpa_table (void)
3599 for (i = 0; i < 8; i++)
3601 r = REAL_VALUE_ATOF (strings_fpa[i], DFmode);
3605 fpa_consts_inited = 1;
3608 /* Return TRUE if rtx X is a valid immediate FPA constant. */
3610 const_double_rtx_ok_for_fpa (rtx x)
3615 if (!fpa_consts_inited)
3618 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
3619 if (REAL_VALUE_MINUS_ZERO (r))
3622 for (i = 0; i < 8; i++)
3623 if (REAL_VALUES_EQUAL (r, values_fpa[i]))
3629 /* Return TRUE if rtx X is a valid immediate FPA constant. */
3631 neg_const_double_rtx_ok_for_fpa (rtx x)
3636 if (!fpa_consts_inited)
3639 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
3640 r = REAL_VALUE_NEGATE (r);
3641 if (REAL_VALUE_MINUS_ZERO (r))
3644 for (i = 0; i < 8; i++)
3645 if (REAL_VALUES_EQUAL (r, values_fpa[i]))
3651 /* Predicates for `match_operand' and `match_operator'. */
3653 /* s_register_operand is the same as register_operand, but it doesn't accept
3656 This function exists because at the time it was put in it led to better
3657 code. SUBREG(MEM) always needs a reload in the places where
3658 s_register_operand is used, and this seemed to lead to excessive
3661 s_register_operand (rtx op, enum machine_mode mode)
3663 if (GET_MODE (op) != mode && mode != VOIDmode)
3666 if (GET_CODE (op) == SUBREG)
3667 op = SUBREG_REG (op);
3669 /* We don't consider registers whose class is NO_REGS
3670 to be a register operand. */
3671 /* XXX might have to check for lo regs only for thumb ??? */
3672 return (GET_CODE (op) == REG
3673 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
3674 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
3677 /* A hard register operand (even before reload. */
3679 arm_hard_register_operand (rtx op, enum machine_mode mode)
3681 if (GET_MODE (op) != mode && mode != VOIDmode)
3684 return (GET_CODE (op) == REG
3685 && REGNO (op) < FIRST_PSEUDO_REGISTER);
3688 /* Only accept reg, subreg(reg), const_int. */
3690 reg_or_int_operand (rtx op, enum machine_mode mode)
3692 if (GET_CODE (op) == CONST_INT)
3695 if (GET_MODE (op) != mode && mode != VOIDmode)
3698 if (GET_CODE (op) == SUBREG)
3699 op = SUBREG_REG (op);
3701 /* We don't consider registers whose class is NO_REGS
3702 to be a register operand. */
3703 return (GET_CODE (op) == REG
3704 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
3705 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
3708 /* Return 1 if OP is an item in memory, given that we are in reload. */
3710 arm_reload_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3712 int regno = true_regnum (op);
3714 return (!CONSTANT_P (op)
3716 || (GET_CODE (op) == REG
3717 && REGNO (op) >= FIRST_PSEUDO_REGISTER)));
3720 /* Return 1 if OP is a valid memory address, but not valid for a signed byte
3721 memory access (architecture V4).
3722 MODE is QImode if called when computing constraints, or VOIDmode when
3723 emitting patterns. In this latter case we cannot use memory_operand()
3724 because it will fail on badly formed MEMs, which is precisely what we are
3727 bad_signed_byte_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3729 if (GET_CODE (op) != MEM)
3734 /* A sum of anything more complex than reg + reg or reg + const is bad. */
3735 if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS)
3736 && (!s_register_operand (XEXP (op, 0), VOIDmode)
3737 || (!s_register_operand (XEXP (op, 1), VOIDmode)
3738 && GET_CODE (XEXP (op, 1)) != CONST_INT)))
3741 /* Big constants are also bad. */
3742 if (GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT
3743 && (INTVAL (XEXP (op, 1)) > 0xff
3744 || -INTVAL (XEXP (op, 1)) > 0xff))
3747 /* Everything else is good, or can will automatically be made so. */
3751 /* Return TRUE for valid operands for the rhs of an ARM instruction. */
3753 arm_rhs_operand (rtx op, enum machine_mode mode)
3755 return (s_register_operand (op, mode)
3756 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op))));
3759 /* Return TRUE for valid operands for the
3760 rhs of an ARM instruction, or a load. */
3762 arm_rhsm_operand (rtx op, enum machine_mode mode)
3764 return (s_register_operand (op, mode)
3765 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op)))
3766 || memory_operand (op, mode));
3769 /* Return TRUE for valid operands for the rhs of an ARM instruction, or if a
3770 constant that is valid when negated. */
3772 arm_add_operand (rtx op, enum machine_mode mode)
3775 return thumb_cmp_operand (op, mode);
3777 return (s_register_operand (op, mode)
3778 || (GET_CODE (op) == CONST_INT
3779 && (const_ok_for_arm (INTVAL (op))
3780 || const_ok_for_arm (-INTVAL (op)))));
3783 /* Return TRUE for valid ARM constants (or when valid if negated). */
3785 arm_addimm_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3787 return (GET_CODE (op) == CONST_INT
3788 && (const_ok_for_arm (INTVAL (op))
3789 || const_ok_for_arm (-INTVAL (op))));
3793 arm_not_operand (rtx op, enum machine_mode mode)
3795 return (s_register_operand (op, mode)
3796 || (GET_CODE (op) == CONST_INT
3797 && (const_ok_for_arm (INTVAL (op))
3798 || const_ok_for_arm (~INTVAL (op)))));
3801 /* Return TRUE if the operand is a memory reference which contains an
3802 offsettable address. */
3804 offsettable_memory_operand (rtx op, enum machine_mode mode)
3806 if (mode == VOIDmode)
3807 mode = GET_MODE (op);
3809 return (mode == GET_MODE (op)
3810 && GET_CODE (op) == MEM
3811 && offsettable_address_p (reload_completed | reload_in_progress,
3812 mode, XEXP (op, 0)));
3815 /* Return TRUE if the operand is a memory reference which is, or can be
3816 made word aligned by adjusting the offset. */
3818 alignable_memory_operand (rtx op, enum machine_mode mode)
3822 if (mode == VOIDmode)
3823 mode = GET_MODE (op);
3825 if (mode != GET_MODE (op) || GET_CODE (op) != MEM)
3830 return ((GET_CODE (reg = op) == REG
3831 || (GET_CODE (op) == SUBREG
3832 && GET_CODE (reg = SUBREG_REG (op)) == REG)
3833 || (GET_CODE (op) == PLUS
3834 && GET_CODE (XEXP (op, 1)) == CONST_INT
3835 && (GET_CODE (reg = XEXP (op, 0)) == REG
3836 || (GET_CODE (XEXP (op, 0)) == SUBREG
3837 && GET_CODE (reg = SUBREG_REG (XEXP (op, 0))) == REG))))
3838 && REGNO_POINTER_ALIGN (REGNO (reg)) >= 32);
3841 /* Similar to s_register_operand, but does not allow hard integer
3844 f_register_operand (rtx op, enum machine_mode mode)
3846 if (GET_MODE (op) != mode && mode != VOIDmode)
3849 if (GET_CODE (op) == SUBREG)
3850 op = SUBREG_REG (op);
3852 /* We don't consider registers whose class is NO_REGS
3853 to be a register operand. */
3854 return (GET_CODE (op) == REG
3855 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
3856 || REGNO_REG_CLASS (REGNO (op)) == FPA_REGS));
3859 /* Return TRUE for valid operands for the rhs of an FPA instruction. */
3861 fpa_rhs_operand (rtx op, enum machine_mode mode)
3863 if (s_register_operand (op, mode))
3866 if (GET_MODE (op) != mode && mode != VOIDmode)
3869 if (GET_CODE (op) == CONST_DOUBLE)
3870 return const_double_rtx_ok_for_fpa (op);
3876 fpa_add_operand (rtx op, enum machine_mode mode)
3878 if (s_register_operand (op, mode))
3881 if (GET_MODE (op) != mode && mode != VOIDmode)
3884 if (GET_CODE (op) == CONST_DOUBLE)
3885 return (const_double_rtx_ok_for_fpa (op)
3886 || neg_const_double_rtx_ok_for_fpa (op));
3891 /* Return nonzero if OP is a valid Cirrus memory address pattern. */
3893 cirrus_memory_offset (rtx op)
3895 /* Reject eliminable registers. */
3896 if (! (reload_in_progress || reload_completed)
3897 && ( reg_mentioned_p (frame_pointer_rtx, op)
3898 || reg_mentioned_p (arg_pointer_rtx, op)
3899 || reg_mentioned_p (virtual_incoming_args_rtx, op)
3900 || reg_mentioned_p (virtual_outgoing_args_rtx, op)
3901 || reg_mentioned_p (virtual_stack_dynamic_rtx, op)
3902 || reg_mentioned_p (virtual_stack_vars_rtx, op)))
3905 if (GET_CODE (op) == MEM)
3911 /* Match: (mem (reg)). */
3912 if (GET_CODE (ind) == REG)
3918 if (GET_CODE (ind) == PLUS
3919 && GET_CODE (XEXP (ind, 0)) == REG
3920 && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode)
3921 && GET_CODE (XEXP (ind, 1)) == CONST_INT)
3928 /* Return nonzero if OP is a Cirrus or general register. */
3930 cirrus_register_operand (rtx op, enum machine_mode mode)
3932 if (GET_MODE (op) != mode && mode != VOIDmode)
3935 if (GET_CODE (op) == SUBREG)
3936 op = SUBREG_REG (op);
3938 return (GET_CODE (op) == REG
3939 && (REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS
3940 || REGNO_REG_CLASS (REGNO (op)) == GENERAL_REGS));
3943 /* Return nonzero if OP is a cirrus FP register. */
3945 cirrus_fp_register (rtx op, enum machine_mode mode)
3947 if (GET_MODE (op) != mode && mode != VOIDmode)
3950 if (GET_CODE (op) == SUBREG)
3951 op = SUBREG_REG (op);
3953 return (GET_CODE (op) == REG
3954 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
3955 || REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS));
3958 /* Return nonzero if OP is a 6bit constant (0..63). */
3960 cirrus_shift_const (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3962 return (GET_CODE (op) == CONST_INT
3964 && INTVAL (op) < 64);
3967 /* Returns TRUE if INSN is an "LDR REG, ADDR" instruction.
3968 Use by the Cirrus Maverick code which has to workaround
3969 a hardware bug triggered by such instructions. */
3971 arm_memory_load_p (rtx insn)
3973 rtx body, lhs, rhs;;
3975 if (insn == NULL_RTX || GET_CODE (insn) != INSN)
3978 body = PATTERN (insn);
3980 if (GET_CODE (body) != SET)
3983 lhs = XEXP (body, 0);
3984 rhs = XEXP (body, 1);
3986 lhs = REG_OR_SUBREG_RTX (lhs);
3988 /* If the destination is not a general purpose
3989 register we do not have to worry. */
3990 if (GET_CODE (lhs) != REG
3991 || REGNO_REG_CLASS (REGNO (lhs)) != GENERAL_REGS)
3994 /* As well as loads from memory we also have to react
3995 to loads of invalid constants which will be turned
3996 into loads from the minipool. */
3997 return (GET_CODE (rhs) == MEM
3998 || GET_CODE (rhs) == SYMBOL_REF
3999 || note_invalid_constants (insn, -1, false));
4002 /* Return TRUE if INSN is a Cirrus instruction. */
4004 arm_cirrus_insn_p (rtx insn)
4006 enum attr_cirrus attr;
4008 /* get_attr aborts on USE and CLOBBER. */
4010 || GET_CODE (insn) != INSN
4011 || GET_CODE (PATTERN (insn)) == USE
4012 || GET_CODE (PATTERN (insn)) == CLOBBER)
4015 attr = get_attr_cirrus (insn);
4017 return attr != CIRRUS_NOT;
4020 /* Cirrus reorg for invalid instruction combinations. */
4022 cirrus_reorg (rtx first)
4024 enum attr_cirrus attr;
4025 rtx body = PATTERN (first);
4029 /* Any branch must be followed by 2 non Cirrus instructions. */
4030 if (GET_CODE (first) == JUMP_INSN && GET_CODE (body) != RETURN)
4033 t = next_nonnote_insn (first);
4035 if (arm_cirrus_insn_p (t))
4038 if (arm_cirrus_insn_p (next_nonnote_insn (t)))
4042 emit_insn_after (gen_nop (), first);
4047 /* (float (blah)) is in parallel with a clobber. */
4048 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
4049 body = XVECEXP (body, 0, 0);
4051 if (GET_CODE (body) == SET)
4053 rtx lhs = XEXP (body, 0), rhs = XEXP (body, 1);
4055 /* cfldrd, cfldr64, cfstrd, cfstr64 must
4056 be followed by a non Cirrus insn. */
4057 if (get_attr_cirrus (first) == CIRRUS_DOUBLE)
4059 if (arm_cirrus_insn_p (next_nonnote_insn (first)))
4060 emit_insn_after (gen_nop (), first);
4064 else if (arm_memory_load_p (first))
4066 unsigned int arm_regno;
4068 /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr,
4069 ldr/cfmv64hr combination where the Rd field is the same
4070 in both instructions must be split with a non Cirrus
4077 /* Get Arm register number for ldr insn. */
4078 if (GET_CODE (lhs) == REG)
4079 arm_regno = REGNO (lhs);
4080 else if (GET_CODE (rhs) == REG)
4081 arm_regno = REGNO (rhs);
4086 first = next_nonnote_insn (first);
4088 if (! arm_cirrus_insn_p (first))
4091 body = PATTERN (first);
4093 /* (float (blah)) is in parallel with a clobber. */
4094 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0))
4095 body = XVECEXP (body, 0, 0);
4097 if (GET_CODE (body) == FLOAT)
4098 body = XEXP (body, 0);
4100 if (get_attr_cirrus (first) == CIRRUS_MOVE
4101 && GET_CODE (XEXP (body, 1)) == REG
4102 && arm_regno == REGNO (XEXP (body, 1)))
4103 emit_insn_after (gen_nop (), first);
4109 /* get_attr aborts on USE and CLOBBER. */
4111 || GET_CODE (first) != INSN
4112 || GET_CODE (PATTERN (first)) == USE
4113 || GET_CODE (PATTERN (first)) == CLOBBER)
4116 attr = get_attr_cirrus (first);
4118 /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...)
4119 must be followed by a non-coprocessor instruction. */
4120 if (attr == CIRRUS_COMPARE)
4124 t = next_nonnote_insn (first);
4126 if (arm_cirrus_insn_p (t))
4129 if (arm_cirrus_insn_p (next_nonnote_insn (t)))
4133 emit_insn_after (gen_nop (), first);
4139 /* Return nonzero if OP is a constant power of two. */
4141 power_of_two_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4143 if (GET_CODE (op) == CONST_INT)
4145 HOST_WIDE_INT value = INTVAL (op);
4147 return value != 0 && (value & (value - 1)) == 0;
4153 /* Return TRUE for a valid operand of a DImode operation.
4154 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
4155 Note that this disallows MEM(REG+REG), but allows
4156 MEM(PRE/POST_INC/DEC(REG)). */
4158 di_operand (rtx op, enum machine_mode mode)
4160 if (s_register_operand (op, mode))
4163 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && GET_MODE (op) != DImode)
4166 if (GET_CODE (op) == SUBREG)
4167 op = SUBREG_REG (op);
4169 switch (GET_CODE (op))
4176 return memory_address_p (DImode, XEXP (op, 0));
4183 /* Like di_operand, but don't accept constants. */
4185 nonimmediate_di_operand (rtx op, enum machine_mode mode)
4187 if (s_register_operand (op, mode))
4190 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && GET_MODE (op) != DImode)
4193 if (GET_CODE (op) == SUBREG)
4194 op = SUBREG_REG (op);
4196 if (GET_CODE (op) == MEM)
4197 return memory_address_p (DImode, XEXP (op, 0));
4202 /* Return TRUE for a valid operand of a DFmode operation when -msoft-float.
4203 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
4204 Note that this disallows MEM(REG+REG), but allows
4205 MEM(PRE/POST_INC/DEC(REG)). */
4207 soft_df_operand (rtx op, enum machine_mode mode)
4209 if (s_register_operand (op, mode))
4212 if (mode != VOIDmode && GET_MODE (op) != mode)
4215 if (GET_CODE (op) == SUBREG && CONSTANT_P (SUBREG_REG (op)))
4218 if (GET_CODE (op) == SUBREG)
4219 op = SUBREG_REG (op);
4221 switch (GET_CODE (op))
4227 return memory_address_p (DFmode, XEXP (op, 0));
4234 /* Like soft_df_operand, but don't accept constants. */
4236 nonimmediate_soft_df_operand (rtx op, enum machine_mode mode)
4238 if (s_register_operand (op, mode))
4241 if (mode != VOIDmode && GET_MODE (op) != mode)
4244 if (GET_CODE (op) == SUBREG)
4245 op = SUBREG_REG (op);
4247 if (GET_CODE (op) == MEM)
4248 return memory_address_p (DFmode, XEXP (op, 0));
4252 /* Return TRUE for valid index operands. */
4254 index_operand (rtx op, enum machine_mode mode)
4256 return (s_register_operand (op, mode)
4257 || (immediate_operand (op, mode)
4258 && (GET_CODE (op) != CONST_INT
4259 || (INTVAL (op) < 4096 && INTVAL (op) > -4096))));
4262 /* Return TRUE for valid shifts by a constant. This also accepts any
4263 power of two on the (somewhat overly relaxed) assumption that the
4264 shift operator in this case was a mult. */
4266 const_shift_operand (rtx op, enum machine_mode mode)
4268 return (power_of_two_operand (op, mode)
4269 || (immediate_operand (op, mode)
4270 && (GET_CODE (op) != CONST_INT
4271 || (INTVAL (op) < 32 && INTVAL (op) > 0))));
4274 /* Return TRUE for arithmetic operators which can be combined with a multiply
4277 shiftable_operator (rtx x, enum machine_mode mode)
4281 if (GET_MODE (x) != mode)
4284 code = GET_CODE (x);
4286 return (code == PLUS || code == MINUS
4287 || code == IOR || code == XOR || code == AND);
4290 /* Return TRUE for binary logical operators. */
4292 logical_binary_operator (rtx x, enum machine_mode mode)
4296 if (GET_MODE (x) != mode)
4299 code = GET_CODE (x);
4301 return (code == IOR || code == XOR || code == AND);
4304 /* Return TRUE for shift operators. */
4306 shift_operator (rtx x,enum machine_mode mode)
4310 if (GET_MODE (x) != mode)
4313 code = GET_CODE (x);
4316 return power_of_two_operand (XEXP (x, 1), mode);
4318 return (code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT
4319 || code == ROTATERT);
4322 /* Return TRUE if x is EQ or NE. */
4324 equality_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
4326 return GET_CODE (x) == EQ || GET_CODE (x) == NE;
4329 /* Return TRUE if x is a comparison operator other than LTGT or UNEQ. */
4331 arm_comparison_operator (rtx x, enum machine_mode mode)
4333 return (comparison_operator (x, mode)
4334 && GET_CODE (x) != LTGT
4335 && GET_CODE (x) != UNEQ);
4338 /* Return TRUE for SMIN SMAX UMIN UMAX operators. */
4340 minmax_operator (rtx x, enum machine_mode mode)
4342 enum rtx_code code = GET_CODE (x);
4344 if (GET_MODE (x) != mode)
4347 return code == SMIN || code == SMAX || code == UMIN || code == UMAX;
4350 /* Return TRUE if this is the condition code register, if we aren't given
4351 a mode, accept any class CCmode register. */
4353 cc_register (rtx x, enum machine_mode mode)
4355 if (mode == VOIDmode)
4357 mode = GET_MODE (x);
4359 if (GET_MODE_CLASS (mode) != MODE_CC)
4363 if ( GET_MODE (x) == mode
4364 && GET_CODE (x) == REG
4365 && REGNO (x) == CC_REGNUM)
4371 /* Return TRUE if this is the condition code register, if we aren't given
4372 a mode, accept any class CCmode register which indicates a dominance
4375 dominant_cc_register (rtx x, enum machine_mode mode)
4377 if (mode == VOIDmode)
4379 mode = GET_MODE (x);
4381 if (GET_MODE_CLASS (mode) != MODE_CC)
4385 if (mode != CC_DNEmode && mode != CC_DEQmode
4386 && mode != CC_DLEmode && mode != CC_DLTmode
4387 && mode != CC_DGEmode && mode != CC_DGTmode
4388 && mode != CC_DLEUmode && mode != CC_DLTUmode
4389 && mode != CC_DGEUmode && mode != CC_DGTUmode)
4392 return cc_register (x, mode);
4395 /* Return TRUE if X references a SYMBOL_REF. */
4397 symbol_mentioned_p (rtx x)
4402 if (GET_CODE (x) == SYMBOL_REF)
4405 fmt = GET_RTX_FORMAT (GET_CODE (x));
4407 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
4413 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4414 if (symbol_mentioned_p (XVECEXP (x, i, j)))
4417 else if (fmt[i] == 'e' && symbol_mentioned_p (XEXP (x, i)))
4424 /* Return TRUE if X references a LABEL_REF. */
4426 label_mentioned_p (rtx x)
4431 if (GET_CODE (x) == LABEL_REF)
4434 fmt = GET_RTX_FORMAT (GET_CODE (x));
4435 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
4441 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4442 if (label_mentioned_p (XVECEXP (x, i, j)))
4445 else if (fmt[i] == 'e' && label_mentioned_p (XEXP (x, i)))
4455 enum rtx_code code = GET_CODE (x);
4459 else if (code == SMIN)
4461 else if (code == UMIN)
4463 else if (code == UMAX)
4469 /* Return 1 if memory locations are adjacent. */
4471 adjacent_mem_locations (rtx a, rtx b)
4473 if ((GET_CODE (XEXP (a, 0)) == REG
4474 || (GET_CODE (XEXP (a, 0)) == PLUS
4475 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
4476 && (GET_CODE (XEXP (b, 0)) == REG
4477 || (GET_CODE (XEXP (b, 0)) == PLUS
4478 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
4480 int val0 = 0, val1 = 0;
4483 if (GET_CODE (XEXP (a, 0)) == PLUS)
4485 reg0 = REGNO (XEXP (XEXP (a, 0), 0));
4486 val0 = INTVAL (XEXP (XEXP (a, 0), 1));
4489 reg0 = REGNO (XEXP (a, 0));
4491 if (GET_CODE (XEXP (b, 0)) == PLUS)
4493 reg1 = REGNO (XEXP (XEXP (b, 0), 0));
4494 val1 = INTVAL (XEXP (XEXP (b, 0), 1));
4497 reg1 = REGNO (XEXP (b, 0));
4499 /* Don't accept any offset that will require multiple
4500 instructions to handle, since this would cause the
4501 arith_adjacentmem pattern to output an overlong sequence. */
4502 if (!const_ok_for_op (PLUS, val0) || !const_ok_for_op (PLUS, val1))
4505 return (reg0 == reg1) && ((val1 - val0) == 4 || (val0 - val1) == 4);
4510 /* Return 1 if OP is a load multiple operation. It is known to be
4511 parallel and the first section will be tested. */
4513 load_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4515 HOST_WIDE_INT count = XVECLEN (op, 0);
4518 HOST_WIDE_INT i = 1, base = 0;
4522 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
4525 /* Check to see if this might be a write-back. */
4526 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
4531 /* Now check it more carefully. */
4532 if (GET_CODE (SET_DEST (elt)) != REG
4533 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
4534 || REGNO (XEXP (SET_SRC (elt), 0)) != REGNO (SET_DEST (elt))
4535 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
4536 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4)
4540 /* Perform a quick check so we don't blow up below. */
4542 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
4543 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != REG
4544 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != MEM)
4547 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, i - 1)));
4548 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, i - 1)), 0);
4550 for (; i < count; i++)
4552 elt = XVECEXP (op, 0, i);
4554 if (GET_CODE (elt) != SET
4555 || GET_CODE (SET_DEST (elt)) != REG
4556 || GET_MODE (SET_DEST (elt)) != SImode
4557 || REGNO (SET_DEST (elt)) != (unsigned int)(dest_regno + i - base)
4558 || GET_CODE (SET_SRC (elt)) != MEM
4559 || GET_MODE (SET_SRC (elt)) != SImode
4560 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
4561 || !rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
4562 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
4563 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != (i - base) * 4)
4570 /* Return 1 if OP is a store multiple operation. It is known to be
4571 parallel and the first section will be tested. */
4573 store_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4575 HOST_WIDE_INT count = XVECLEN (op, 0);
4578 HOST_WIDE_INT i = 1, base = 0;
4582 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
4585 /* Check to see if this might be a write-back. */
4586 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
4591 /* Now check it more carefully. */
4592 if (GET_CODE (SET_DEST (elt)) != REG
4593 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
4594 || REGNO (XEXP (SET_SRC (elt), 0)) != REGNO (SET_DEST (elt))
4595 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
4596 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4)
4600 /* Perform a quick check so we don't blow up below. */
4602 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
4603 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != MEM
4604 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != REG)
4607 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, i - 1)));
4608 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, i - 1)), 0);
4610 for (; i < count; i++)
4612 elt = XVECEXP (op, 0, i);
4614 if (GET_CODE (elt) != SET
4615 || GET_CODE (SET_SRC (elt)) != REG
4616 || GET_MODE (SET_SRC (elt)) != SImode
4617 || REGNO (SET_SRC (elt)) != (unsigned int)(src_regno + i - base)
4618 || GET_CODE (SET_DEST (elt)) != MEM
4619 || GET_MODE (SET_DEST (elt)) != SImode
4620 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
4621 || !rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
4622 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
4623 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != (i - base) * 4)
4631 load_multiple_sequence (rtx *operands, int nops, int *regs, int *base,
4632 HOST_WIDE_INT *load_offset)
4634 int unsorted_regs[4];
4635 HOST_WIDE_INT unsorted_offsets[4];
4640 /* Can only handle 2, 3, or 4 insns at present,
4641 though could be easily extended if required. */
4642 if (nops < 2 || nops > 4)
4645 /* Loop over the operands and check that the memory references are
4646 suitable (ie immediate offsets from the same base register). At
4647 the same time, extract the target register, and the memory
4649 for (i = 0; i < nops; i++)
4654 /* Convert a subreg of a mem into the mem itself. */
4655 if (GET_CODE (operands[nops + i]) == SUBREG)
4656 operands[nops + i] = alter_subreg (operands + (nops + i));
4658 if (GET_CODE (operands[nops + i]) != MEM)
4661 /* Don't reorder volatile memory references; it doesn't seem worth
4662 looking for the case where the order is ok anyway. */
4663 if (MEM_VOLATILE_P (operands[nops + i]))
4666 offset = const0_rtx;
4668 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
4669 || (GET_CODE (reg) == SUBREG
4670 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
4671 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
4672 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
4674 || (GET_CODE (reg) == SUBREG
4675 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
4676 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
4681 base_reg = REGNO (reg);
4682 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
4683 ? REGNO (operands[i])
4684 : REGNO (SUBREG_REG (operands[i])));
4689 if (base_reg != (int) REGNO (reg))
4690 /* Not addressed from the same base register. */
4693 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
4694 ? REGNO (operands[i])
4695 : REGNO (SUBREG_REG (operands[i])));
4696 if (unsorted_regs[i] < unsorted_regs[order[0]])
4700 /* If it isn't an integer register, or if it overwrites the
4701 base register but isn't the last insn in the list, then
4702 we can't do this. */
4703 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14
4704 || (i != nops - 1 && unsorted_regs[i] == base_reg))
4707 unsorted_offsets[i] = INTVAL (offset);
4710 /* Not a suitable memory address. */
4714 /* All the useful information has now been extracted from the
4715 operands into unsorted_regs and unsorted_offsets; additionally,
4716 order[0] has been set to the lowest numbered register in the
4717 list. Sort the registers into order, and check that the memory
4718 offsets are ascending and adjacent. */
4720 for (i = 1; i < nops; i++)
4724 order[i] = order[i - 1];
4725 for (j = 0; j < nops; j++)
4726 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
4727 && (order[i] == order[i - 1]
4728 || unsorted_regs[j] < unsorted_regs[order[i]]))
4731 /* Have we found a suitable register? if not, one must be used more
4733 if (order[i] == order[i - 1])
4736 /* Is the memory address adjacent and ascending? */
4737 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
4745 for (i = 0; i < nops; i++)
4746 regs[i] = unsorted_regs[order[i]];
4748 *load_offset = unsorted_offsets[order[0]];
4751 if (unsorted_offsets[order[0]] == 0)
4752 return 1; /* ldmia */
4754 if (unsorted_offsets[order[0]] == 4)
4755 return 2; /* ldmib */
4757 if (unsorted_offsets[order[nops - 1]] == 0)
4758 return 3; /* ldmda */
4760 if (unsorted_offsets[order[nops - 1]] == -4)
4761 return 4; /* ldmdb */
4763 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
4764 if the offset isn't small enough. The reason 2 ldrs are faster
4765 is because these ARMs are able to do more than one cache access
4766 in a single cycle. The ARM9 and StrongARM have Harvard caches,
4767 whilst the ARM8 has a double bandwidth cache. This means that
4768 these cores can do both an instruction fetch and a data fetch in
4769 a single cycle, so the trick of calculating the address into a
4770 scratch register (one of the result regs) and then doing a load
4771 multiple actually becomes slower (and no smaller in code size).
4772 That is the transformation
4774 ldr rd1, [rbase + offset]
4775 ldr rd2, [rbase + offset + 4]
4779 add rd1, rbase, offset
4780 ldmia rd1, {rd1, rd2}
4782 produces worse code -- '3 cycles + any stalls on rd2' instead of
4783 '2 cycles + any stalls on rd2'. On ARMs with only one cache
4784 access per cycle, the first sequence could never complete in less
4785 than 6 cycles, whereas the ldm sequence would only take 5 and
4786 would make better use of sequential accesses if not hitting the
4789 We cheat here and test 'arm_ld_sched' which we currently know to
4790 only be true for the ARM8, ARM9 and StrongARM. If this ever
4791 changes, then the test below needs to be reworked. */
4792 if (nops == 2 && arm_ld_sched)
4795 /* Can't do it without setting up the offset, only do this if it takes
4796 no more than one insn. */
4797 return (const_ok_for_arm (unsorted_offsets[order[0]])
4798 || const_ok_for_arm (-unsorted_offsets[order[0]])) ? 5 : 0;
4802 emit_ldm_seq (rtx *operands, int nops)
4806 HOST_WIDE_INT offset;
4810 switch (load_multiple_sequence (operands, nops, regs, &base_reg, &offset))
4813 strcpy (buf, "ldm%?ia\t");
4817 strcpy (buf, "ldm%?ib\t");
4821 strcpy (buf, "ldm%?da\t");
4825 strcpy (buf, "ldm%?db\t");
4830 sprintf (buf, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
4831 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
4834 sprintf (buf, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
4835 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
4837 output_asm_insn (buf, operands);
4839 strcpy (buf, "ldm%?ia\t");
4846 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
4847 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
4849 for (i = 1; i < nops; i++)
4850 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
4851 reg_names[regs[i]]);
4853 strcat (buf, "}\t%@ phole ldm");
4855 output_asm_insn (buf, operands);
4860 store_multiple_sequence (rtx *operands, int nops, int *regs, int *base,
4861 HOST_WIDE_INT * load_offset)
4863 int unsorted_regs[4];
4864 HOST_WIDE_INT unsorted_offsets[4];
4869 /* Can only handle 2, 3, or 4 insns at present, though could be easily
4870 extended if required. */
4871 if (nops < 2 || nops > 4)
4874 /* Loop over the operands and check that the memory references are
4875 suitable (ie immediate offsets from the same base register). At
4876 the same time, extract the target register, and the memory
4878 for (i = 0; i < nops; i++)
4883 /* Convert a subreg of a mem into the mem itself. */
4884 if (GET_CODE (operands[nops + i]) == SUBREG)
4885 operands[nops + i] = alter_subreg (operands + (nops + i));
4887 if (GET_CODE (operands[nops + i]) != MEM)
4890 /* Don't reorder volatile memory references; it doesn't seem worth
4891 looking for the case where the order is ok anyway. */
4892 if (MEM_VOLATILE_P (operands[nops + i]))
4895 offset = const0_rtx;
4897 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
4898 || (GET_CODE (reg) == SUBREG
4899 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
4900 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
4901 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
4903 || (GET_CODE (reg) == SUBREG
4904 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
4905 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
4910 base_reg = REGNO (reg);
4911 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
4912 ? REGNO (operands[i])
4913 : REGNO (SUBREG_REG (operands[i])));
4918 if (base_reg != (int) REGNO (reg))
4919 /* Not addressed from the same base register. */
4922 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
4923 ? REGNO (operands[i])
4924 : REGNO (SUBREG_REG (operands[i])));
4925 if (unsorted_regs[i] < unsorted_regs[order[0]])
4929 /* If it isn't an integer register, then we can't do this. */
4930 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14)
4933 unsorted_offsets[i] = INTVAL (offset);
4936 /* Not a suitable memory address. */
4940 /* All the useful information has now been extracted from the
4941 operands into unsorted_regs and unsorted_offsets; additionally,
4942 order[0] has been set to the lowest numbered register in the
4943 list. Sort the registers into order, and check that the memory
4944 offsets are ascending and adjacent. */
4946 for (i = 1; i < nops; i++)
4950 order[i] = order[i - 1];
4951 for (j = 0; j < nops; j++)
4952 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
4953 && (order[i] == order[i - 1]
4954 || unsorted_regs[j] < unsorted_regs[order[i]]))
4957 /* Have we found a suitable register? if not, one must be used more
4959 if (order[i] == order[i - 1])
4962 /* Is the memory address adjacent and ascending? */
4963 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
4971 for (i = 0; i < nops; i++)
4972 regs[i] = unsorted_regs[order[i]];
4974 *load_offset = unsorted_offsets[order[0]];
4977 if (unsorted_offsets[order[0]] == 0)
4978 return 1; /* stmia */
4980 if (unsorted_offsets[order[0]] == 4)
4981 return 2; /* stmib */
4983 if (unsorted_offsets[order[nops - 1]] == 0)
4984 return 3; /* stmda */
4986 if (unsorted_offsets[order[nops - 1]] == -4)
4987 return 4; /* stmdb */
4993 emit_stm_seq (rtx *operands, int nops)
4997 HOST_WIDE_INT offset;
5001 switch (store_multiple_sequence (operands, nops, regs, &base_reg, &offset))
5004 strcpy (buf, "stm%?ia\t");
5008 strcpy (buf, "stm%?ib\t");
5012 strcpy (buf, "stm%?da\t");
5016 strcpy (buf, "stm%?db\t");
5023 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
5024 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
5026 for (i = 1; i < nops; i++)
5027 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
5028 reg_names[regs[i]]);
5030 strcat (buf, "}\t%@ phole stm");
5032 output_asm_insn (buf, operands);
5037 multi_register_push (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
5039 if (GET_CODE (op) != PARALLEL
5040 || (GET_CODE (XVECEXP (op, 0, 0)) != SET)
5041 || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC)
5042 || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPEC_PUSH_MULT))
5048 /* Routines for use in generating RTL. */
5051 arm_gen_load_multiple (int base_regno, int count, rtx from, int up,
5052 int write_back, int unchanging_p, int in_struct_p,
5057 int sign = up ? 1 : -1;
5060 /* XScale has load-store double instructions, but they have stricter
5061 alignment requirements than load-store multiple, so we can not
5064 For XScale ldm requires 2 + NREGS cycles to complete and blocks
5065 the pipeline until completion.
5073 An ldr instruction takes 1-3 cycles, but does not block the
5082 Best case ldr will always win. However, the more ldr instructions
5083 we issue, the less likely we are to be able to schedule them well.
5084 Using ldr instructions also increases code size.
5086 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
5087 for counts of 3 or 4 regs. */
5088 if (arm_tune_xscale && count <= 2 && ! optimize_size)
5094 for (i = 0; i < count; i++)
5096 mem = gen_rtx_MEM (SImode, plus_constant (from, i * 4 * sign));
5097 RTX_UNCHANGING_P (mem) = unchanging_p;
5098 MEM_IN_STRUCT_P (mem) = in_struct_p;
5099 MEM_SCALAR_P (mem) = scalar_p;
5100 emit_move_insn (gen_rtx_REG (SImode, base_regno + i), mem);
5104 emit_move_insn (from, plus_constant (from, count * 4 * sign));
5112 result = gen_rtx_PARALLEL (VOIDmode,
5113 rtvec_alloc (count + (write_back ? 1 : 0)));
5116 XVECEXP (result, 0, 0)
5117 = gen_rtx_SET (GET_MODE (from), from,
5118 plus_constant (from, count * 4 * sign));
5123 for (j = 0; i < count; i++, j++)
5125 mem = gen_rtx_MEM (SImode, plus_constant (from, j * 4 * sign));
5126 RTX_UNCHANGING_P (mem) = unchanging_p;
5127 MEM_IN_STRUCT_P (mem) = in_struct_p;
5128 MEM_SCALAR_P (mem) = scalar_p;
5129 XVECEXP (result, 0, i)
5130 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, base_regno + j), mem);
5137 arm_gen_store_multiple (int base_regno, int count, rtx to, int up,
5138 int write_back, int unchanging_p, int in_struct_p,
5143 int sign = up ? 1 : -1;
5146 /* See arm_gen_load_multiple for discussion of
5147 the pros/cons of ldm/stm usage for XScale. */
5148 if (arm_tune_xscale && count <= 2 && ! optimize_size)
5154 for (i = 0; i < count; i++)
5156 mem = gen_rtx_MEM (SImode, plus_constant (to, i * 4 * sign));
5157 RTX_UNCHANGING_P (mem) = unchanging_p;
5158 MEM_IN_STRUCT_P (mem) = in_struct_p;
5159 MEM_SCALAR_P (mem) = scalar_p;
5160 emit_move_insn (mem, gen_rtx_REG (SImode, base_regno + i));
5164 emit_move_insn (to, plus_constant (to, count * 4 * sign));
5172 result = gen_rtx_PARALLEL (VOIDmode,
5173 rtvec_alloc (count + (write_back ? 1 : 0)));
5176 XVECEXP (result, 0, 0)
5177 = gen_rtx_SET (GET_MODE (to), to,
5178 plus_constant (to, count * 4 * sign));
5183 for (j = 0; i < count; i++, j++)
5185 mem = gen_rtx_MEM (SImode, plus_constant (to, j * 4 * sign));
5186 RTX_UNCHANGING_P (mem) = unchanging_p;
5187 MEM_IN_STRUCT_P (mem) = in_struct_p;
5188 MEM_SCALAR_P (mem) = scalar_p;
5190 XVECEXP (result, 0, i)
5191 = gen_rtx_SET (VOIDmode, mem, gen_rtx_REG (SImode, base_regno + j));
5198 arm_gen_movstrqi (rtx *operands)
5200 HOST_WIDE_INT in_words_to_go, out_words_to_go, last_bytes;
5203 rtx st_src, st_dst, fin_src, fin_dst;
5204 rtx part_bytes_reg = NULL;
5206 int dst_unchanging_p, dst_in_struct_p, src_unchanging_p, src_in_struct_p;
5207 int dst_scalar_p, src_scalar_p;
5209 if (GET_CODE (operands[2]) != CONST_INT
5210 || GET_CODE (operands[3]) != CONST_INT
5211 || INTVAL (operands[2]) > 64
5212 || INTVAL (operands[3]) & 3)
5215 st_dst = XEXP (operands[0], 0);
5216 st_src = XEXP (operands[1], 0);
5218 dst_unchanging_p = RTX_UNCHANGING_P (operands[0]);
5219 dst_in_struct_p = MEM_IN_STRUCT_P (operands[0]);
5220 dst_scalar_p = MEM_SCALAR_P (operands[0]);
5221 src_unchanging_p = RTX_UNCHANGING_P (operands[1]);
5222 src_in_struct_p = MEM_IN_STRUCT_P (operands[1]);
5223 src_scalar_p = MEM_SCALAR_P (operands[1]);
5225 fin_dst = dst = copy_to_mode_reg (SImode, st_dst);
5226 fin_src = src = copy_to_mode_reg (SImode, st_src);
5228 in_words_to_go = ARM_NUM_INTS (INTVAL (operands[2]));
5229 out_words_to_go = INTVAL (operands[2]) / 4;
5230 last_bytes = INTVAL (operands[2]) & 3;
5232 if (out_words_to_go != in_words_to_go && ((in_words_to_go - 1) & 3) != 0)
5233 part_bytes_reg = gen_rtx_REG (SImode, (in_words_to_go - 1) & 3);
5235 for (i = 0; in_words_to_go >= 2; i+=4)
5237 if (in_words_to_go > 4)
5238 emit_insn (arm_gen_load_multiple (0, 4, src, TRUE, TRUE,
5243 emit_insn (arm_gen_load_multiple (0, in_words_to_go, src, TRUE,
5244 FALSE, src_unchanging_p,
5245 src_in_struct_p, src_scalar_p));
5247 if (out_words_to_go)
5249 if (out_words_to_go > 4)
5250 emit_insn (arm_gen_store_multiple (0, 4, dst, TRUE, TRUE,
5254 else if (out_words_to_go != 1)
5255 emit_insn (arm_gen_store_multiple (0, out_words_to_go,
5264 mem = gen_rtx_MEM (SImode, dst);
5265 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
5266 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
5267 MEM_SCALAR_P (mem) = dst_scalar_p;
5268 emit_move_insn (mem, gen_rtx_REG (SImode, 0));
5269 if (last_bytes != 0)
5270 emit_insn (gen_addsi3 (dst, dst, GEN_INT (4)));
5274 in_words_to_go -= in_words_to_go < 4 ? in_words_to_go : 4;
5275 out_words_to_go -= out_words_to_go < 4 ? out_words_to_go : 4;
5278 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
5279 if (out_words_to_go)
5283 mem = gen_rtx_MEM (SImode, src);
5284 RTX_UNCHANGING_P (mem) = src_unchanging_p;
5285 MEM_IN_STRUCT_P (mem) = src_in_struct_p;
5286 MEM_SCALAR_P (mem) = src_scalar_p;
5287 emit_move_insn (sreg = gen_reg_rtx (SImode), mem);
5288 emit_move_insn (fin_src = gen_reg_rtx (SImode), plus_constant (src, 4));
5290 mem = gen_rtx_MEM (SImode, dst);
5291 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
5292 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
5293 MEM_SCALAR_P (mem) = dst_scalar_p;
5294 emit_move_insn (mem, sreg);
5295 emit_move_insn (fin_dst = gen_reg_rtx (SImode), plus_constant (dst, 4));
5298 if (in_words_to_go) /* Sanity check */
5304 if (in_words_to_go < 0)
5307 mem = gen_rtx_MEM (SImode, src);
5308 RTX_UNCHANGING_P (mem) = src_unchanging_p;
5309 MEM_IN_STRUCT_P (mem) = src_in_struct_p;
5310 MEM_SCALAR_P (mem) = src_scalar_p;
5311 part_bytes_reg = copy_to_mode_reg (SImode, mem);
5314 if (last_bytes && part_bytes_reg == NULL)
5317 if (BYTES_BIG_ENDIAN && last_bytes)
5319 rtx tmp = gen_reg_rtx (SImode);
5321 /* The bytes we want are in the top end of the word. */
5322 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg,
5323 GEN_INT (8 * (4 - last_bytes))));
5324 part_bytes_reg = tmp;
5328 mem = gen_rtx_MEM (QImode, plus_constant (dst, last_bytes - 1));
5329 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
5330 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
5331 MEM_SCALAR_P (mem) = dst_scalar_p;
5332 emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
5336 tmp = gen_reg_rtx (SImode);
5337 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8)));
5338 part_bytes_reg = tmp;
5347 mem = gen_rtx_MEM (HImode, dst);
5348 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
5349 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
5350 MEM_SCALAR_P (mem) = dst_scalar_p;
5351 emit_move_insn (mem, gen_lowpart (HImode, part_bytes_reg));
5355 rtx tmp = gen_reg_rtx (SImode);
5357 emit_insn (gen_addsi3 (dst, dst, GEN_INT (2)));
5358 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (16)));
5359 part_bytes_reg = tmp;
5365 mem = gen_rtx_MEM (QImode, dst);
5366 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
5367 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
5368 MEM_SCALAR_P (mem) = dst_scalar_p;
5369 emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
5376 /* Generate a memory reference for a half word, such that it will be loaded
5377 into the top 16 bits of the word. We can assume that the address is
5378 known to be alignable and of the form reg, or plus (reg, const). */
5381 arm_gen_rotated_half_load (rtx memref)
5383 HOST_WIDE_INT offset = 0;
5384 rtx base = XEXP (memref, 0);
5386 if (GET_CODE (base) == PLUS)
5388 offset = INTVAL (XEXP (base, 1));
5389 base = XEXP (base, 0);
5392 /* If we aren't allowed to generate unaligned addresses, then fail. */
5393 if (TARGET_MMU_TRAPS
5394 && ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 0)))
5397 base = gen_rtx_MEM (SImode, plus_constant (base, offset & ~2));
5399 if ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 2))
5402 return gen_rtx_ROTATE (SImode, base, GEN_INT (16));
5405 /* Select a dominance comparison mode if possible for a test of the general
5406 form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms.
5407 COND_OR == DOM_CC_X_AND_Y => (X && Y)
5408 COND_OR == DOM_CC_NX_OR_Y => ((! X) || Y)
5409 COND_OR == DOM_CC_X_OR_Y => (X || Y)
5410 In all cases OP will be either EQ or NE, but we don't need to know which
5411 here. If we are unable to support a dominance comparison we return
5412 CC mode. This will then fail to match for the RTL expressions that
5413 generate this call. */
5415 arm_select_dominance_cc_mode (rtx x, rtx y, HOST_WIDE_INT cond_or)
5417 enum rtx_code cond1, cond2;
5420 /* Currently we will probably get the wrong result if the individual
5421 comparisons are not simple. This also ensures that it is safe to
5422 reverse a comparison if necessary. */
5423 if ((arm_select_cc_mode (cond1 = GET_CODE (x), XEXP (x, 0), XEXP (x, 1))
5425 || (arm_select_cc_mode (cond2 = GET_CODE (y), XEXP (y, 0), XEXP (y, 1))
5429 /* The if_then_else variant of this tests the second condition if the
5430 first passes, but is true if the first fails. Reverse the first
5431 condition to get a true "inclusive-or" expression. */
5432 if (cond_or == DOM_CC_NX_OR_Y)
5433 cond1 = reverse_condition (cond1);
5435 /* If the comparisons are not equal, and one doesn't dominate the other,
5436 then we can't do this. */
5438 && !comparison_dominates_p (cond1, cond2)
5439 && (swapped = 1, !comparison_dominates_p (cond2, cond1)))
5444 enum rtx_code temp = cond1;
5452 if (cond2 == EQ || cond_or == DOM_CC_X_AND_Y)
5457 case LE: return CC_DLEmode;
5458 case LEU: return CC_DLEUmode;
5459 case GE: return CC_DGEmode;
5460 case GEU: return CC_DGEUmode;
5467 if (cond2 == LT || cond_or == DOM_CC_X_AND_Y)
5476 if (cond2 == GT || cond_or == DOM_CC_X_AND_Y)
5485 if (cond2 == LTU || cond_or == DOM_CC_X_AND_Y)
5494 if (cond2 == GTU || cond_or == DOM_CC_X_AND_Y)
5502 /* The remaining cases only occur when both comparisons are the
5527 arm_select_cc_mode (enum rtx_code op, rtx x, rtx y)
5529 /* All floating point compares return CCFP if it is an equality
5530 comparison, and CCFPE otherwise. */
5531 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
5560 /* A compare with a shifted operand. Because of canonicalization, the
5561 comparison will have to be swapped when we emit the assembler. */
5562 if (GET_MODE (y) == SImode && GET_CODE (y) == REG
5563 && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
5564 || GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE
5565 || GET_CODE (x) == ROTATERT))
5568 /* This is a special case that is used by combine to allow a
5569 comparison of a shifted byte load to be split into a zero-extend
5570 followed by a comparison of the shifted integer (only valid for
5571 equalities and unsigned inequalities). */
5572 if (GET_MODE (x) == SImode
5573 && GET_CODE (x) == ASHIFT
5574 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 24
5575 && GET_CODE (XEXP (x, 0)) == SUBREG
5576 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == MEM
5577 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == QImode
5578 && (op == EQ || op == NE
5579 || op == GEU || op == GTU || op == LTU || op == LEU)
5580 && GET_CODE (y) == CONST_INT)
5583 /* A construct for a conditional compare, if the false arm contains
5584 0, then both conditions must be true, otherwise either condition
5585 must be true. Not all conditions are possible, so CCmode is
5586 returned if it can't be done. */
5587 if (GET_CODE (x) == IF_THEN_ELSE
5588 && (XEXP (x, 2) == const0_rtx
5589 || XEXP (x, 2) == const1_rtx)
5590 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
5591 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<')
5592 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
5593 INTVAL (XEXP (x, 2)));
5595 /* Alternate canonicalizations of the above. These are somewhat cleaner. */
5596 if (GET_CODE (x) == AND
5597 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
5598 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<')
5599 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
5602 if (GET_CODE (x) == IOR
5603 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
5604 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<')
5605 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
5608 /* An operation (on Thumb) where we want to test for a single bit.
5609 This is done by shifting that bit up into the top bit of a
5610 scratch register; we can then branch on the sign bit. */
5612 && GET_MODE (x) == SImode
5613 && (op == EQ || op == NE)
5614 && (GET_CODE (x) == ZERO_EXTRACT))
5617 /* An operation that sets the condition codes as a side-effect, the
5618 V flag is not set correctly, so we can only use comparisons where
5619 this doesn't matter. (For LT and GE we can use "mi" and "pl"
5621 if (GET_MODE (x) == SImode
5623 && (op == EQ || op == NE || op == LT || op == GE)
5624 && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
5625 || GET_CODE (x) == AND || GET_CODE (x) == IOR
5626 || GET_CODE (x) == XOR || GET_CODE (x) == MULT
5627 || GET_CODE (x) == NOT || GET_CODE (x) == NEG
5628 || GET_CODE (x) == LSHIFTRT
5629 || GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
5630 || GET_CODE (x) == ROTATERT
5631 || (TARGET_ARM && GET_CODE (x) == ZERO_EXTRACT)))
5634 if (GET_MODE (x) == QImode && (op == EQ || op == NE))
5637 if (GET_MODE (x) == SImode && (op == LTU || op == GEU)
5638 && GET_CODE (x) == PLUS
5639 && (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y)))
5645 /* X and Y are two things to compare using CODE. Emit the compare insn and
5646 return the rtx for register 0 in the proper mode. FP means this is a
5647 floating point compare: I don't think that it is needed on the arm. */
5649 arm_gen_compare_reg (enum rtx_code code, rtx x, rtx y)
5651 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
5652 rtx cc_reg = gen_rtx_REG (mode, CC_REGNUM);
5654 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
5655 gen_rtx_COMPARE (mode, x, y)));
5660 /* Generate a sequence of insns that will generate the correct return
5661 address mask depending on the physical architecture that the program
5664 arm_gen_return_addr_mask (void)
5666 rtx reg = gen_reg_rtx (Pmode);
5668 emit_insn (gen_return_addr_mask (reg));
5673 arm_reload_in_hi (rtx *operands)
5675 rtx ref = operands[1];
5677 HOST_WIDE_INT offset = 0;
5679 if (GET_CODE (ref) == SUBREG)
5681 offset = SUBREG_BYTE (ref);
5682 ref = SUBREG_REG (ref);
5685 if (GET_CODE (ref) == REG)
5687 /* We have a pseudo which has been spilt onto the stack; there
5688 are two cases here: the first where there is a simple
5689 stack-slot replacement and a second where the stack-slot is
5690 out of range, or is used as a subreg. */
5691 if (reg_equiv_mem[REGNO (ref)])
5693 ref = reg_equiv_mem[REGNO (ref)];
5694 base = find_replacement (&XEXP (ref, 0));
5697 /* The slot is out of range, or was dressed up in a SUBREG. */
5698 base = reg_equiv_address[REGNO (ref)];
5701 base = find_replacement (&XEXP (ref, 0));
5703 /* Handle the case where the address is too complex to be offset by 1. */
5704 if (GET_CODE (base) == MINUS
5705 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
5707 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
5709 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
5712 else if (GET_CODE (base) == PLUS)
5714 /* The addend must be CONST_INT, or we would have dealt with it above. */
5715 HOST_WIDE_INT hi, lo;
5717 offset += INTVAL (XEXP (base, 1));
5718 base = XEXP (base, 0);
5720 /* Rework the address into a legal sequence of insns. */
5721 /* Valid range for lo is -4095 -> 4095 */
5724 : -((-offset) & 0xfff));
5726 /* Corner case, if lo is the max offset then we would be out of range
5727 once we have added the additional 1 below, so bump the msb into the
5728 pre-loading insn(s). */
5732 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff)
5733 ^ (HOST_WIDE_INT) 0x80000000)
5734 - (HOST_WIDE_INT) 0x80000000);
5736 if (hi + lo != offset)
5741 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
5743 /* Get the base address; addsi3 knows how to handle constants
5744 that require more than one insn. */
5745 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
5751 /* Operands[2] may overlap operands[0] (though it won't overlap
5752 operands[1]), that's why we asked for a DImode reg -- so we can
5753 use the bit that does not overlap. */
5754 if (REGNO (operands[2]) == REGNO (operands[0]))
5755 scratch = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
5757 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
5759 emit_insn (gen_zero_extendqisi2 (scratch,
5760 gen_rtx_MEM (QImode,
5761 plus_constant (base,
5763 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode, operands[0], 0),
5764 gen_rtx_MEM (QImode,
5765 plus_constant (base,
5767 if (!BYTES_BIG_ENDIAN)
5768 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
5769 gen_rtx_IOR (SImode,
5772 gen_rtx_SUBREG (SImode, operands[0], 0),
5776 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
5777 gen_rtx_IOR (SImode,
5778 gen_rtx_ASHIFT (SImode, scratch,
5780 gen_rtx_SUBREG (SImode, operands[0],
5784 /* Handle storing a half-word to memory during reload by synthesizing as two
5785 byte stores. Take care not to clobber the input values until after we
5786 have moved them somewhere safe. This code assumes that if the DImode
5787 scratch in operands[2] overlaps either the input value or output address
5788 in some way, then that value must die in this insn (we absolutely need
5789 two scratch registers for some corner cases). */
5791 arm_reload_out_hi (rtx *operands)
5793 rtx ref = operands[0];
5794 rtx outval = operands[1];
5796 HOST_WIDE_INT offset = 0;
5798 if (GET_CODE (ref) == SUBREG)
5800 offset = SUBREG_BYTE (ref);
5801 ref = SUBREG_REG (ref);
5804 if (GET_CODE (ref) == REG)
5806 /* We have a pseudo which has been spilt onto the stack; there
5807 are two cases here: the first where there is a simple
5808 stack-slot replacement and a second where the stack-slot is
5809 out of range, or is used as a subreg. */
5810 if (reg_equiv_mem[REGNO (ref)])
5812 ref = reg_equiv_mem[REGNO (ref)];
5813 base = find_replacement (&XEXP (ref, 0));
5816 /* The slot is out of range, or was dressed up in a SUBREG. */
5817 base = reg_equiv_address[REGNO (ref)];
5820 base = find_replacement (&XEXP (ref, 0));
5822 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
5824 /* Handle the case where the address is too complex to be offset by 1. */
5825 if (GET_CODE (base) == MINUS
5826 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
5828 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
5830 /* Be careful not to destroy OUTVAL. */
5831 if (reg_overlap_mentioned_p (base_plus, outval))
5833 /* Updating base_plus might destroy outval, see if we can
5834 swap the scratch and base_plus. */
5835 if (!reg_overlap_mentioned_p (scratch, outval))
5838 scratch = base_plus;
5843 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
5845 /* Be conservative and copy OUTVAL into the scratch now,
5846 this should only be necessary if outval is a subreg
5847 of something larger than a word. */
5848 /* XXX Might this clobber base? I can't see how it can,
5849 since scratch is known to overlap with OUTVAL, and
5850 must be wider than a word. */
5851 emit_insn (gen_movhi (scratch_hi, outval));
5852 outval = scratch_hi;
5856 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
5859 else if (GET_CODE (base) == PLUS)
5861 /* The addend must be CONST_INT, or we would have dealt with it above. */
5862 HOST_WIDE_INT hi, lo;
5864 offset += INTVAL (XEXP (base, 1));
5865 base = XEXP (base, 0);
5867 /* Rework the address into a legal sequence of insns. */
5868 /* Valid range for lo is -4095 -> 4095 */
5871 : -((-offset) & 0xfff));
5873 /* Corner case, if lo is the max offset then we would be out of range
5874 once we have added the additional 1 below, so bump the msb into the
5875 pre-loading insn(s). */
5879 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff)
5880 ^ (HOST_WIDE_INT) 0x80000000)
5881 - (HOST_WIDE_INT) 0x80000000);
5883 if (hi + lo != offset)
5888 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
5890 /* Be careful not to destroy OUTVAL. */
5891 if (reg_overlap_mentioned_p (base_plus, outval))
5893 /* Updating base_plus might destroy outval, see if we
5894 can swap the scratch and base_plus. */
5895 if (!reg_overlap_mentioned_p (scratch, outval))
5898 scratch = base_plus;
5903 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
5905 /* Be conservative and copy outval into scratch now,
5906 this should only be necessary if outval is a
5907 subreg of something larger than a word. */
5908 /* XXX Might this clobber base? I can't see how it
5909 can, since scratch is known to overlap with
5911 emit_insn (gen_movhi (scratch_hi, outval));
5912 outval = scratch_hi;
5916 /* Get the base address; addsi3 knows how to handle constants
5917 that require more than one insn. */
5918 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
5924 if (BYTES_BIG_ENDIAN)
5926 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
5927 plus_constant (base, offset + 1)),
5928 gen_lowpart (QImode, outval)));
5929 emit_insn (gen_lshrsi3 (scratch,
5930 gen_rtx_SUBREG (SImode, outval, 0),
5932 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
5933 gen_lowpart (QImode, scratch)));
5937 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
5938 gen_lowpart (QImode, outval)));
5939 emit_insn (gen_lshrsi3 (scratch,
5940 gen_rtx_SUBREG (SImode, outval, 0),
5942 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
5943 plus_constant (base, offset + 1)),
5944 gen_lowpart (QImode, scratch)));
5948 /* Print a symbolic form of X to the debug file, F. */
5950 arm_print_value (FILE *f, rtx x)
5952 switch (GET_CODE (x))
5955 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (x));
5959 fprintf (f, "<0x%lx,0x%lx>", (long)XWINT (x, 2), (long)XWINT (x, 3));
5967 for (i = 0; i < CONST_VECTOR_NUNITS (x); i++)
5969 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (CONST_VECTOR_ELT (x, i)));
5970 if (i < (CONST_VECTOR_NUNITS (x) - 1))
5978 fprintf (f, "\"%s\"", XSTR (x, 0));
5982 fprintf (f, "`%s'", XSTR (x, 0));
5986 fprintf (f, "L%d", INSN_UID (XEXP (x, 0)));
5990 arm_print_value (f, XEXP (x, 0));
5994 arm_print_value (f, XEXP (x, 0));
5996 arm_print_value (f, XEXP (x, 1));
6004 fprintf (f, "????");
6009 /* Routines for manipulation of the constant pool. */
6011 /* Arm instructions cannot load a large constant directly into a
6012 register; they have to come from a pc relative load. The constant
6013 must therefore be placed in the addressable range of the pc
6014 relative load. Depending on the precise pc relative load
6015 instruction the range is somewhere between 256 bytes and 4k. This
6016 means that we often have to dump a constant inside a function, and
6017 generate code to branch around it.
6019 It is important to minimize this, since the branches will slow
6020 things down and make the code larger.
6022 Normally we can hide the table after an existing unconditional
6023 branch so that there is no interruption of the flow, but in the
6024 worst case the code looks like this:
6042 We fix this by performing a scan after scheduling, which notices
6043 which instructions need to have their operands fetched from the
6044 constant table and builds the table.
6046 The algorithm starts by building a table of all the constants that
6047 need fixing up and all the natural barriers in the function (places
6048 where a constant table can be dropped without breaking the flow).
6049 For each fixup we note how far the pc-relative replacement will be
6050 able to reach and the offset of the instruction into the function.
6052 Having built the table we then group the fixes together to form
6053 tables that are as large as possible (subject to addressing
6054 constraints) and emit each table of constants after the last
6055 barrier that is within range of all the instructions in the group.
6056 If a group does not contain a barrier, then we forcibly create one
6057 by inserting a jump instruction into the flow. Once the table has
6058 been inserted, the insns are then modified to reference the
6059 relevant entry in the pool.
6061 Possible enhancements to the algorithm (not implemented) are:
6063 1) For some processors and object formats, there may be benefit in
6064 aligning the pools to the start of cache lines; this alignment
6065 would need to be taken into account when calculating addressability
6068 /* These typedefs are located at the start of this file, so that
6069 they can be used in the prototypes there. This comment is to
6070 remind readers of that fact so that the following structures
6071 can be understood more easily.
6073 typedef struct minipool_node Mnode;
6074 typedef struct minipool_fixup Mfix; */
6076 struct minipool_node
6078 /* Doubly linked chain of entries. */
6081 /* The maximum offset into the code that this entry can be placed. While
6082 pushing fixes for forward references, all entries are sorted in order
6083 of increasing max_address. */
6084 HOST_WIDE_INT max_address;
6085 /* Similarly for an entry inserted for a backwards ref. */
6086 HOST_WIDE_INT min_address;
6087 /* The number of fixes referencing this entry. This can become zero
6088 if we "unpush" an entry. In this case we ignore the entry when we
6089 come to emit the code. */
6091 /* The offset from the start of the minipool. */
6092 HOST_WIDE_INT offset;
6093 /* The value in table. */
6095 /* The mode of value. */
6096 enum machine_mode mode;
6097 /* The size of the value. With iWMMXt enabled
6098 sizes > 4 also imply an alignment of 8-bytes. */
6102 struct minipool_fixup
6106 HOST_WIDE_INT address;
6108 enum machine_mode mode;
6112 HOST_WIDE_INT forwards;
6113 HOST_WIDE_INT backwards;
6116 /* Fixes less than a word need padding out to a word boundary. */
6117 #define MINIPOOL_FIX_SIZE(mode) \
6118 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4)
6120 static Mnode * minipool_vector_head;
6121 static Mnode * minipool_vector_tail;
6122 static rtx minipool_vector_label;
6124 /* The linked list of all minipool fixes required for this function. */
6125 Mfix * minipool_fix_head;
6126 Mfix * minipool_fix_tail;
6127 /* The fix entry for the current minipool, once it has been placed. */
6128 Mfix * minipool_barrier;
6130 /* Determines if INSN is the start of a jump table. Returns the end
6131 of the TABLE or NULL_RTX. */
6133 is_jump_table (rtx insn)
6137 if (GET_CODE (insn) == JUMP_INSN
6138 && JUMP_LABEL (insn) != NULL
6139 && ((table = next_real_insn (JUMP_LABEL (insn)))
6140 == next_real_insn (insn))
6142 && GET_CODE (table) == JUMP_INSN
6143 && (GET_CODE (PATTERN (table)) == ADDR_VEC
6144 || GET_CODE (PATTERN (table)) == ADDR_DIFF_VEC))
6150 #ifndef JUMP_TABLES_IN_TEXT_SECTION
6151 #define JUMP_TABLES_IN_TEXT_SECTION 0
6154 static HOST_WIDE_INT
6155 get_jump_table_size (rtx insn)
6157 /* ADDR_VECs only take room if read-only data does into the text
6159 if (JUMP_TABLES_IN_TEXT_SECTION
6160 #if !defined(READONLY_DATA_SECTION) && !defined(READONLY_DATA_SECTION_ASM_OP)
6165 rtx body = PATTERN (insn);
6166 int elt = GET_CODE (body) == ADDR_DIFF_VEC ? 1 : 0;
6168 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, elt);
6174 /* Move a minipool fix MP from its current location to before MAX_MP.
6175 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
6176 constraints may need updating. */
6178 move_minipool_fix_forward_ref (Mnode *mp, Mnode *max_mp,
6179 HOST_WIDE_INT max_address)
6181 /* This should never be true and the code below assumes these are
6188 if (max_address < mp->max_address)
6189 mp->max_address = max_address;
6193 if (max_address > max_mp->max_address - mp->fix_size)
6194 mp->max_address = max_mp->max_address - mp->fix_size;
6196 mp->max_address = max_address;
6198 /* Unlink MP from its current position. Since max_mp is non-null,
6199 mp->prev must be non-null. */
6200 mp->prev->next = mp->next;
6201 if (mp->next != NULL)
6202 mp->next->prev = mp->prev;
6204 minipool_vector_tail = mp->prev;
6206 /* Re-insert it before MAX_MP. */
6208 mp->prev = max_mp->prev;
6211 if (mp->prev != NULL)
6212 mp->prev->next = mp;
6214 minipool_vector_head = mp;
6217 /* Save the new entry. */
6220 /* Scan over the preceding entries and adjust their addresses as
6222 while (mp->prev != NULL
6223 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
6225 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
6232 /* Add a constant to the minipool for a forward reference. Returns the
6233 node added or NULL if the constant will not fit in this pool. */
6235 add_minipool_forward_ref (Mfix *fix)
6237 /* If set, max_mp is the first pool_entry that has a lower
6238 constraint than the one we are trying to add. */
6239 Mnode * max_mp = NULL;
6240 HOST_WIDE_INT max_address = fix->address + fix->forwards;
6243 /* If this fix's address is greater than the address of the first
6244 entry, then we can't put the fix in this pool. We subtract the
6245 size of the current fix to ensure that if the table is fully
6246 packed we still have enough room to insert this value by suffling
6247 the other fixes forwards. */
6248 if (minipool_vector_head &&
6249 fix->address >= minipool_vector_head->max_address - fix->fix_size)
6252 /* Scan the pool to see if a constant with the same value has
6253 already been added. While we are doing this, also note the
6254 location where we must insert the constant if it doesn't already
6256 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
6258 if (GET_CODE (fix->value) == GET_CODE (mp->value)
6259 && fix->mode == mp->mode
6260 && (GET_CODE (fix->value) != CODE_LABEL
6261 || (CODE_LABEL_NUMBER (fix->value)
6262 == CODE_LABEL_NUMBER (mp->value)))
6263 && rtx_equal_p (fix->value, mp->value))
6265 /* More than one fix references this entry. */
6267 return move_minipool_fix_forward_ref (mp, max_mp, max_address);
6270 /* Note the insertion point if necessary. */
6272 && mp->max_address > max_address)
6275 /* If we are inserting an 8-bytes aligned quantity and
6276 we have not already found an insertion point, then
6277 make sure that all such 8-byte aligned quantities are
6278 placed at the start of the pool. */
6279 if (TARGET_REALLY_IWMMXT
6281 && fix->fix_size == 8
6282 && mp->fix_size != 8)
6285 max_address = mp->max_address;
6289 /* The value is not currently in the minipool, so we need to create
6290 a new entry for it. If MAX_MP is NULL, the entry will be put on
6291 the end of the list since the placement is less constrained than
6292 any existing entry. Otherwise, we insert the new fix before
6293 MAX_MP and, if necessary, adjust the constraints on the other
6295 mp = xmalloc (sizeof (* mp));
6296 mp->fix_size = fix->fix_size;
6297 mp->mode = fix->mode;
6298 mp->value = fix->value;
6300 /* Not yet required for a backwards ref. */
6301 mp->min_address = -65536;
6305 mp->max_address = max_address;
6307 mp->prev = minipool_vector_tail;
6309 if (mp->prev == NULL)
6311 minipool_vector_head = mp;
6312 minipool_vector_label = gen_label_rtx ();
6315 mp->prev->next = mp;
6317 minipool_vector_tail = mp;
6321 if (max_address > max_mp->max_address - mp->fix_size)
6322 mp->max_address = max_mp->max_address - mp->fix_size;
6324 mp->max_address = max_address;
6327 mp->prev = max_mp->prev;
6329 if (mp->prev != NULL)
6330 mp->prev->next = mp;
6332 minipool_vector_head = mp;
6335 /* Save the new entry. */
6338 /* Scan over the preceding entries and adjust their addresses as
6340 while (mp->prev != NULL
6341 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
6343 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
6351 move_minipool_fix_backward_ref (Mnode *mp, Mnode *min_mp,
6352 HOST_WIDE_INT min_address)
6354 HOST_WIDE_INT offset;
6356 /* This should never be true, and the code below assumes these are
6363 if (min_address > mp->min_address)
6364 mp->min_address = min_address;
6368 /* We will adjust this below if it is too loose. */
6369 mp->min_address = min_address;
6371 /* Unlink MP from its current position. Since min_mp is non-null,
6372 mp->next must be non-null. */
6373 mp->next->prev = mp->prev;
6374 if (mp->prev != NULL)
6375 mp->prev->next = mp->next;
6377 minipool_vector_head = mp->next;
6379 /* Reinsert it after MIN_MP. */
6381 mp->next = min_mp->next;
6383 if (mp->next != NULL)
6384 mp->next->prev = mp;
6386 minipool_vector_tail = mp;
6392 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
6394 mp->offset = offset;
6395 if (mp->refcount > 0)
6396 offset += mp->fix_size;
6398 if (mp->next && mp->next->min_address < mp->min_address + mp->fix_size)
6399 mp->next->min_address = mp->min_address + mp->fix_size;
6405 /* Add a constant to the minipool for a backward reference. Returns the
6406 node added or NULL if the constant will not fit in this pool.
6408 Note that the code for insertion for a backwards reference can be
6409 somewhat confusing because the calculated offsets for each fix do
6410 not take into account the size of the pool (which is still under
6413 add_minipool_backward_ref (Mfix *fix)
6415 /* If set, min_mp is the last pool_entry that has a lower constraint
6416 than the one we are trying to add. */
6417 Mnode *min_mp = NULL;
6418 /* This can be negative, since it is only a constraint. */
6419 HOST_WIDE_INT min_address = fix->address - fix->backwards;
6422 /* If we can't reach the current pool from this insn, or if we can't
6423 insert this entry at the end of the pool without pushing other
6424 fixes out of range, then we don't try. This ensures that we
6425 can't fail later on. */
6426 if (min_address >= minipool_barrier->address
6427 || (minipool_vector_tail->min_address + fix->fix_size
6428 >= minipool_barrier->address))
6431 /* Scan the pool to see if a constant with the same value has
6432 already been added. While we are doing this, also note the
6433 location where we must insert the constant if it doesn't already
6435 for (mp = minipool_vector_tail; mp != NULL; mp = mp->prev)
6437 if (GET_CODE (fix->value) == GET_CODE (mp->value)
6438 && fix->mode == mp->mode
6439 && (GET_CODE (fix->value) != CODE_LABEL
6440 || (CODE_LABEL_NUMBER (fix->value)
6441 == CODE_LABEL_NUMBER (mp->value)))
6442 && rtx_equal_p (fix->value, mp->value)
6443 /* Check that there is enough slack to move this entry to the
6444 end of the table (this is conservative). */
6446 > (minipool_barrier->address
6447 + minipool_vector_tail->offset
6448 + minipool_vector_tail->fix_size)))
6451 return move_minipool_fix_backward_ref (mp, min_mp, min_address);
6455 mp->min_address += fix->fix_size;
6458 /* Note the insertion point if necessary. */
6459 if (mp->min_address < min_address)
6461 /* For now, we do not allow the insertion of 8-byte alignment
6462 requiring nodes anywhere but at the start of the pool. */
6463 if (TARGET_REALLY_IWMMXT && fix->fix_size == 8 && mp->fix_size != 8)
6468 else if (mp->max_address
6469 < minipool_barrier->address + mp->offset + fix->fix_size)
6471 /* Inserting before this entry would push the fix beyond
6472 its maximum address (which can happen if we have
6473 re-located a forwards fix); force the new fix to come
6476 min_address = mp->min_address + fix->fix_size;
6478 /* If we are inserting an 8-bytes aligned quantity and
6479 we have not already found an insertion point, then
6480 make sure that all such 8-byte aligned quantities are
6481 placed at the start of the pool. */
6482 else if (TARGET_REALLY_IWMMXT
6484 && fix->fix_size == 8
6485 && mp->fix_size < 8)
6488 min_address = mp->min_address + fix->fix_size;
6493 /* We need to create a new entry. */
6494 mp = xmalloc (sizeof (* mp));
6495 mp->fix_size = fix->fix_size;
6496 mp->mode = fix->mode;
6497 mp->value = fix->value;
6499 mp->max_address = minipool_barrier->address + 65536;
6501 mp->min_address = min_address;
6506 mp->next = minipool_vector_head;
6508 if (mp->next == NULL)
6510 minipool_vector_tail = mp;
6511 minipool_vector_label = gen_label_rtx ();
6514 mp->next->prev = mp;
6516 minipool_vector_head = mp;
6520 mp->next = min_mp->next;
6524 if (mp->next != NULL)
6525 mp->next->prev = mp;
6527 minipool_vector_tail = mp;
6530 /* Save the new entry. */
6538 /* Scan over the following entries and adjust their offsets. */
6539 while (mp->next != NULL)
6541 if (mp->next->min_address < mp->min_address + mp->fix_size)
6542 mp->next->min_address = mp->min_address + mp->fix_size;
6545 mp->next->offset = mp->offset + mp->fix_size;
6547 mp->next->offset = mp->offset;
6556 assign_minipool_offsets (Mfix *barrier)
6558 HOST_WIDE_INT offset = 0;
6561 minipool_barrier = barrier;
6563 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
6565 mp->offset = offset;
6567 if (mp->refcount > 0)
6568 offset += mp->fix_size;
6572 /* Output the literal table */
6574 dump_minipool (rtx scan)
6580 if (TARGET_REALLY_IWMMXT)
6581 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
6582 if (mp->refcount > 0 && mp->fix_size == 8)
6589 fprintf (rtl_dump_file,
6590 ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n",
6591 INSN_UID (scan), (unsigned long) minipool_barrier->address, align64 ? 8 : 4);
6593 scan = emit_label_after (gen_label_rtx (), scan);
6594 scan = emit_insn_after (align64 ? gen_align_8 () : gen_align_4 (), scan);
6595 scan = emit_label_after (minipool_vector_label, scan);
6597 for (mp = minipool_vector_head; mp != NULL; mp = nmp)
6599 if (mp->refcount > 0)
6603 fprintf (rtl_dump_file,
6604 ";; Offset %u, min %ld, max %ld ",
6605 (unsigned) mp->offset, (unsigned long) mp->min_address,
6606 (unsigned long) mp->max_address);
6607 arm_print_value (rtl_dump_file, mp->value);
6608 fputc ('\n', rtl_dump_file);
6611 switch (mp->fix_size)
6613 #ifdef HAVE_consttable_1
6615 scan = emit_insn_after (gen_consttable_1 (mp->value), scan);
6619 #ifdef HAVE_consttable_2
6621 scan = emit_insn_after (gen_consttable_2 (mp->value), scan);
6625 #ifdef HAVE_consttable_4
6627 scan = emit_insn_after (gen_consttable_4 (mp->value), scan);
6631 #ifdef HAVE_consttable_8
6633 scan = emit_insn_after (gen_consttable_8 (mp->value), scan);
6647 minipool_vector_head = minipool_vector_tail = NULL;
6648 scan = emit_insn_after (gen_consttable_end (), scan);
6649 scan = emit_barrier_after (scan);
6652 /* Return the cost of forcibly inserting a barrier after INSN. */
6654 arm_barrier_cost (rtx insn)
6656 /* Basing the location of the pool on the loop depth is preferable,
6657 but at the moment, the basic block information seems to be
6658 corrupt by this stage of the compilation. */
6660 rtx next = next_nonnote_insn (insn);
6662 if (next != NULL && GET_CODE (next) == CODE_LABEL)
6665 switch (GET_CODE (insn))
6668 /* It will always be better to place the table before the label, rather
6677 return base_cost - 10;
6680 return base_cost + 10;
6684 /* Find the best place in the insn stream in the range
6685 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
6686 Create the barrier by inserting a jump and add a new fix entry for
6689 create_fix_barrier (Mfix *fix, HOST_WIDE_INT max_address)
6691 HOST_WIDE_INT count = 0;
6693 rtx from = fix->insn;
6694 rtx selected = from;
6696 HOST_WIDE_INT selected_address;
6698 HOST_WIDE_INT max_count = max_address - fix->address;
6699 rtx label = gen_label_rtx ();
6701 selected_cost = arm_barrier_cost (from);
6702 selected_address = fix->address;
6704 while (from && count < max_count)
6709 /* This code shouldn't have been called if there was a natural barrier
6711 if (GET_CODE (from) == BARRIER)
6714 /* Count the length of this insn. */
6715 count += get_attr_length (from);
6717 /* If there is a jump table, add its length. */
6718 tmp = is_jump_table (from);
6721 count += get_jump_table_size (tmp);
6723 /* Jump tables aren't in a basic block, so base the cost on
6724 the dispatch insn. If we select this location, we will
6725 still put the pool after the table. */
6726 new_cost = arm_barrier_cost (from);
6728 if (count < max_count && new_cost <= selected_cost)
6731 selected_cost = new_cost;
6732 selected_address = fix->address + count;
6735 /* Continue after the dispatch table. */
6736 from = NEXT_INSN (tmp);
6740 new_cost = arm_barrier_cost (from);
6742 if (count < max_count && new_cost <= selected_cost)
6745 selected_cost = new_cost;
6746 selected_address = fix->address + count;
6749 from = NEXT_INSN (from);
6752 /* Create a new JUMP_INSN that branches around a barrier. */
6753 from = emit_jump_insn_after (gen_jump (label), selected);
6754 JUMP_LABEL (from) = label;
6755 barrier = emit_barrier_after (from);
6756 emit_label_after (label, barrier);
6758 /* Create a minipool barrier entry for the new barrier. */
6759 new_fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* new_fix));
6760 new_fix->insn = barrier;
6761 new_fix->address = selected_address;
6762 new_fix->next = fix->next;
6763 fix->next = new_fix;
6768 /* Record that there is a natural barrier in the insn stream at
6771 push_minipool_barrier (rtx insn, HOST_WIDE_INT address)
6773 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
6776 fix->address = address;
6779 if (minipool_fix_head != NULL)
6780 minipool_fix_tail->next = fix;
6782 minipool_fix_head = fix;
6784 minipool_fix_tail = fix;
6787 /* Record INSN, which will need fixing up to load a value from the
6788 minipool. ADDRESS is the offset of the insn since the start of the
6789 function; LOC is a pointer to the part of the insn which requires
6790 fixing; VALUE is the constant that must be loaded, which is of type
6793 push_minipool_fix (rtx insn, HOST_WIDE_INT address, rtx *loc,
6794 enum machine_mode mode, rtx value)
6796 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
6798 #ifdef AOF_ASSEMBLER
6799 /* PIC symbol references need to be converted into offsets into the
6801 /* XXX This shouldn't be done here. */
6802 if (flag_pic && GET_CODE (value) == SYMBOL_REF)
6803 value = aof_pic_entry (value);
6804 #endif /* AOF_ASSEMBLER */
6807 fix->address = address;
6810 fix->fix_size = MINIPOOL_FIX_SIZE (mode);
6812 fix->forwards = get_attr_pool_range (insn);
6813 fix->backwards = get_attr_neg_pool_range (insn);
6814 fix->minipool = NULL;
6816 /* If an insn doesn't have a range defined for it, then it isn't
6817 expecting to be reworked by this code. Better to abort now than
6818 to generate duff assembly code. */
6819 if (fix->forwards == 0 && fix->backwards == 0)
6822 /* With iWMMXt enabled, the pool is aligned to an 8-byte boundary.
6823 So there might be an empty word before the start of the pool.
6824 Hence we reduce the forward range by 4 to allow for this
6826 if (TARGET_REALLY_IWMMXT && fix->fix_size == 8)
6831 fprintf (rtl_dump_file,
6832 ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ",
6833 GET_MODE_NAME (mode),
6834 INSN_UID (insn), (unsigned long) address,
6835 -1 * (long)fix->backwards, (long)fix->forwards);
6836 arm_print_value (rtl_dump_file, fix->value);
6837 fprintf (rtl_dump_file, "\n");
6840 /* Add it to the chain of fixes. */
6843 if (minipool_fix_head != NULL)
6844 minipool_fix_tail->next = fix;
6846 minipool_fix_head = fix;
6848 minipool_fix_tail = fix;
6851 /* Scan INSN and note any of its operands that need fixing.
6852 If DO_PUSHES is false we do not actually push any of the fixups
6853 needed. The function returns TRUE is any fixups were needed/pushed.
6854 This is used by arm_memory_load_p() which needs to know about loads
6855 of constants that will be converted into minipool loads. */
6857 note_invalid_constants (rtx insn, HOST_WIDE_INT address, int do_pushes)
6859 bool result = false;
6862 extract_insn (insn);
6864 if (!constrain_operands (1))
6865 fatal_insn_not_found (insn);
6867 /* Fill in recog_op_alt with information about the constraints of this insn. */
6868 preprocess_constraints ();
6870 for (opno = 0; opno < recog_data.n_operands; opno++)
6872 /* Things we need to fix can only occur in inputs. */
6873 if (recog_data.operand_type[opno] != OP_IN)
6876 /* If this alternative is a memory reference, then any mention
6877 of constants in this alternative is really to fool reload
6878 into allowing us to accept one there. We need to fix them up
6879 now so that we output the right code. */
6880 if (recog_op_alt[opno][which_alternative].memory_ok)
6882 rtx op = recog_data.operand[opno];
6884 if (CONSTANT_P (op))
6887 push_minipool_fix (insn, address, recog_data.operand_loc[opno],
6888 recog_data.operand_mode[opno], op);
6891 else if (GET_CODE (op) == MEM
6892 && GET_CODE (XEXP (op, 0)) == SYMBOL_REF
6893 && CONSTANT_POOL_ADDRESS_P (XEXP (op, 0)))
6897 rtx cop = avoid_constant_pool_reference (op);
6899 /* Casting the address of something to a mode narrower
6900 than a word can cause avoid_constant_pool_reference()
6901 to return the pool reference itself. That's no good to
6902 us here. Lets just hope that we can use the
6903 constant pool value directly. */
6905 cop = get_pool_constant (XEXP (op, 0));
6907 push_minipool_fix (insn, address,
6908 recog_data.operand_loc[opno],
6909 recog_data.operand_mode[opno], cop);
6920 /* Gcc puts the pool in the wrong place for ARM, since we can only
6921 load addresses a limited distance around the pc. We do some
6922 special munging to move the constant pool values to the correct
6923 point in the code. */
6928 HOST_WIDE_INT address = 0;
6931 minipool_fix_head = minipool_fix_tail = NULL;
6933 /* The first insn must always be a note, or the code below won't
6934 scan it properly. */
6935 insn = get_insns ();
6936 if (GET_CODE (insn) != NOTE)
6939 /* Scan all the insns and record the operands that will need fixing. */
6940 for (insn = next_nonnote_insn (insn); insn; insn = next_nonnote_insn (insn))
6942 if (TARGET_CIRRUS_FIX_INVALID_INSNS
6943 && (arm_cirrus_insn_p (insn)
6944 || GET_CODE (insn) == JUMP_INSN
6945 || arm_memory_load_p (insn)))
6946 cirrus_reorg (insn);
6948 if (GET_CODE (insn) == BARRIER)
6949 push_minipool_barrier (insn, address);
6950 else if (INSN_P (insn))
6954 note_invalid_constants (insn, address, true);
6955 address += get_attr_length (insn);
6957 /* If the insn is a vector jump, add the size of the table
6958 and skip the table. */
6959 if ((table = is_jump_table (insn)) != NULL)
6961 address += get_jump_table_size (table);
6967 fix = minipool_fix_head;
6969 /* Now scan the fixups and perform the required changes. */
6974 Mfix * last_added_fix;
6975 Mfix * last_barrier = NULL;
6978 /* Skip any further barriers before the next fix. */
6979 while (fix && GET_CODE (fix->insn) == BARRIER)
6982 /* No more fixes. */
6986 last_added_fix = NULL;
6988 for (ftmp = fix; ftmp; ftmp = ftmp->next)
6990 if (GET_CODE (ftmp->insn) == BARRIER)
6992 if (ftmp->address >= minipool_vector_head->max_address)
6995 last_barrier = ftmp;
6997 else if ((ftmp->minipool = add_minipool_forward_ref (ftmp)) == NULL)
7000 last_added_fix = ftmp; /* Keep track of the last fix added. */
7003 /* If we found a barrier, drop back to that; any fixes that we
7004 could have reached but come after the barrier will now go in
7005 the next mini-pool. */
7006 if (last_barrier != NULL)
7008 /* Reduce the refcount for those fixes that won't go into this
7010 for (fdel = last_barrier->next;
7011 fdel && fdel != ftmp;
7014 fdel->minipool->refcount--;
7015 fdel->minipool = NULL;
7018 ftmp = last_barrier;
7022 /* ftmp is first fix that we can't fit into this pool and
7023 there no natural barriers that we could use. Insert a
7024 new barrier in the code somewhere between the previous
7025 fix and this one, and arrange to jump around it. */
7026 HOST_WIDE_INT max_address;
7028 /* The last item on the list of fixes must be a barrier, so
7029 we can never run off the end of the list of fixes without
7030 last_barrier being set. */
7034 max_address = minipool_vector_head->max_address;
7035 /* Check that there isn't another fix that is in range that
7036 we couldn't fit into this pool because the pool was
7037 already too large: we need to put the pool before such an
7039 if (ftmp->address < max_address)
7040 max_address = ftmp->address;
7042 last_barrier = create_fix_barrier (last_added_fix, max_address);
7045 assign_minipool_offsets (last_barrier);
7049 if (GET_CODE (ftmp->insn) != BARRIER
7050 && ((ftmp->minipool = add_minipool_backward_ref (ftmp))
7057 /* Scan over the fixes we have identified for this pool, fixing them
7058 up and adding the constants to the pool itself. */
7059 for (this_fix = fix; this_fix && ftmp != this_fix;
7060 this_fix = this_fix->next)
7061 if (GET_CODE (this_fix->insn) != BARRIER)
7064 = plus_constant (gen_rtx_LABEL_REF (VOIDmode,
7065 minipool_vector_label),
7066 this_fix->minipool->offset);
7067 *this_fix->loc = gen_rtx_MEM (this_fix->mode, addr);
7070 dump_minipool (last_barrier->insn);
7074 /* From now on we must synthesize any constants that we can't handle
7075 directly. This can happen if the RTL gets split during final
7076 instruction generation. */
7077 after_arm_reorg = 1;
7079 /* Free the minipool memory. */
7080 obstack_free (&minipool_obstack, minipool_startobj);
7083 /* Routines to output assembly language. */
7085 /* If the rtx is the correct value then return the string of the number.
7086 In this way we can ensure that valid double constants are generated even
7087 when cross compiling. */
7089 fp_immediate_constant (rtx x)
7094 if (!fpa_consts_inited)
7097 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
7098 for (i = 0; i < 8; i++)
7099 if (REAL_VALUES_EQUAL (r, values_fpa[i]))
7100 return strings_fpa[i];
7105 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
7107 fp_const_from_val (REAL_VALUE_TYPE *r)
7111 if (!fpa_consts_inited)
7114 for (i = 0; i < 8; i++)
7115 if (REAL_VALUES_EQUAL (*r, values_fpa[i]))
7116 return strings_fpa[i];
7121 /* Output the operands of a LDM/STM instruction to STREAM.
7122 MASK is the ARM register set mask of which only bits 0-15 are important.
7123 REG is the base register, either the frame pointer or the stack pointer,
7124 INSTR is the possibly suffixed load or store instruction. */
7126 print_multi_reg (FILE *stream, const char *instr, int reg, int mask)
7129 int not_first = FALSE;
7131 fputc ('\t', stream);
7132 asm_fprintf (stream, instr, reg);
7133 fputs (", {", stream);
7135 for (i = 0; i <= LAST_ARM_REGNUM; i++)
7136 if (mask & (1 << i))
7139 fprintf (stream, ", ");
7141 asm_fprintf (stream, "%r", i);
7145 fprintf (stream, "}");
7147 /* Add a ^ character for the 26-bit ABI, but only if we were loading
7148 the PC. Otherwise we would generate an UNPREDICTABLE instruction.
7149 Strictly speaking the instruction would be unpredicatble only if
7150 we were writing back the base register as well, but since we never
7151 want to generate an LDM type 2 instruction (register bank switching)
7152 which is what you get if the PC is not being loaded, we do not need
7153 to check for writeback. */
7154 if (! TARGET_APCS_32
7155 && ((mask & (1 << PC_REGNUM)) != 0))
7156 fprintf (stream, "^");
7158 fprintf (stream, "\n");
7161 /* Output a 'call' insn. */
7163 output_call (rtx *operands)
7165 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
7167 if (REGNO (operands[0]) == LR_REGNUM)
7169 operands[0] = gen_rtx_REG (SImode, IP_REGNUM);
7170 output_asm_insn ("mov%?\t%0, %|lr", operands);
7173 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
7175 if (TARGET_INTERWORK)
7176 output_asm_insn ("bx%?\t%0", operands);
7178 output_asm_insn ("mov%?\t%|pc, %0", operands);
7183 /* Output a 'call' insn that is a reference in memory. */
7185 output_call_mem (rtx *operands)
7187 if (TARGET_INTERWORK)
7189 output_asm_insn ("ldr%?\t%|ip, %0", operands);
7190 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
7191 output_asm_insn ("bx%?\t%|ip", operands);
7193 else if (regno_use_in (LR_REGNUM, operands[0]))
7195 /* LR is used in the memory address. We load the address in the
7196 first instruction. It's safe to use IP as the target of the
7197 load since the call will kill it anyway. */
7198 output_asm_insn ("ldr%?\t%|ip, %0", operands);
7199 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
7200 output_asm_insn ("mov%?\t%|pc, %|ip", operands);
7204 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
7205 output_asm_insn ("ldr%?\t%|pc, %0", operands);
7212 /* Output a move from arm registers to an fpa registers.
7213 OPERANDS[0] is an fpa register.
7214 OPERANDS[1] is the first registers of an arm register pair. */
7216 output_mov_long_double_fpa_from_arm (rtx *operands)
7218 int arm_reg0 = REGNO (operands[1]);
7221 if (arm_reg0 == IP_REGNUM)
7224 ops[0] = gen_rtx_REG (SImode, arm_reg0);
7225 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
7226 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
7228 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops);
7229 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands);
7234 /* Output a move from an fpa register to arm registers.
7235 OPERANDS[0] is the first registers of an arm register pair.
7236 OPERANDS[1] is an fpa register. */
7238 output_mov_long_double_arm_from_fpa (rtx *operands)
7240 int arm_reg0 = REGNO (operands[0]);
7243 if (arm_reg0 == IP_REGNUM)
7246 ops[0] = gen_rtx_REG (SImode, arm_reg0);
7247 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
7248 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
7250 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands);
7251 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops);
7255 /* Output a move from arm registers to arm registers of a long double
7256 OPERANDS[0] is the destination.
7257 OPERANDS[1] is the source. */
7259 output_mov_long_double_arm_from_arm (rtx *operands)
7261 /* We have to be careful here because the two might overlap. */
7262 int dest_start = REGNO (operands[0]);
7263 int src_start = REGNO (operands[1]);
7267 if (dest_start < src_start)
7269 for (i = 0; i < 3; i++)
7271 ops[0] = gen_rtx_REG (SImode, dest_start + i);
7272 ops[1] = gen_rtx_REG (SImode, src_start + i);
7273 output_asm_insn ("mov%?\t%0, %1", ops);
7278 for (i = 2; i >= 0; i--)
7280 ops[0] = gen_rtx_REG (SImode, dest_start + i);
7281 ops[1] = gen_rtx_REG (SImode, src_start + i);
7282 output_asm_insn ("mov%?\t%0, %1", ops);
7290 /* Output a move from arm registers to an fpa registers.
7291 OPERANDS[0] is an fpa register.
7292 OPERANDS[1] is the first registers of an arm register pair. */
7294 output_mov_double_fpa_from_arm (rtx *operands)
7296 int arm_reg0 = REGNO (operands[1]);
7299 if (arm_reg0 == IP_REGNUM)
7302 ops[0] = gen_rtx_REG (SImode, arm_reg0);
7303 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
7304 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops);
7305 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands);
7309 /* Output a move from an fpa register to arm registers.
7310 OPERANDS[0] is the first registers of an arm register pair.
7311 OPERANDS[1] is an fpa register. */
7313 output_mov_double_arm_from_fpa (rtx *operands)
7315 int arm_reg0 = REGNO (operands[0]);
7318 if (arm_reg0 == IP_REGNUM)
7321 ops[0] = gen_rtx_REG (SImode, arm_reg0);
7322 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
7323 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands);
7324 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops);
7328 /* Output a move between double words.
7329 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
7330 or MEM<-REG and all MEMs must be offsettable addresses. */
7332 output_move_double (rtx *operands)
7334 enum rtx_code code0 = GET_CODE (operands[0]);
7335 enum rtx_code code1 = GET_CODE (operands[1]);
7340 int reg0 = REGNO (operands[0]);
7342 otherops[0] = gen_rtx_REG (SImode, 1 + reg0);
7346 int reg1 = REGNO (operands[1]);
7347 if (reg1 == IP_REGNUM)
7350 /* Ensure the second source is not overwritten. */
7351 if (reg1 == reg0 + (WORDS_BIG_ENDIAN ? -1 : 1))
7352 output_asm_insn ("mov%?\t%Q0, %Q1\n\tmov%?\t%R0, %R1", operands);
7354 output_asm_insn ("mov%?\t%R0, %R1\n\tmov%?\t%Q0, %Q1", operands);
7356 else if (code1 == CONST_VECTOR)
7358 HOST_WIDE_INT hint = 0;
7360 switch (GET_MODE (operands[1]))
7363 otherops[1] = GEN_INT (INTVAL (CONST_VECTOR_ELT (operands[1], 1)));
7364 operands[1] = GEN_INT (INTVAL (CONST_VECTOR_ELT (operands[1], 0)));
7368 if (BYTES_BIG_ENDIAN)
7370 hint = INTVAL (CONST_VECTOR_ELT (operands[1], 2));
7372 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 3));
7376 hint = INTVAL (CONST_VECTOR_ELT (operands[1], 3));
7378 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 2));
7381 otherops[1] = GEN_INT (hint);
7384 if (BYTES_BIG_ENDIAN)
7386 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0));
7388 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1));
7392 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1));
7394 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0));
7397 operands[1] = GEN_INT (hint);
7401 if (BYTES_BIG_ENDIAN)
7403 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 4));
7405 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 5));
7407 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 6));
7409 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 7));
7413 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 7));
7415 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 6));
7417 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 5));
7419 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 4));
7422 otherops[1] = GEN_INT (hint);
7425 if (BYTES_BIG_ENDIAN)
7427 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0));
7429 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1));
7431 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 2));
7433 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 3));
7437 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 3));
7439 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 2));
7441 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1));
7443 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0));
7446 operands[1] = GEN_INT (hint);
7452 output_mov_immediate (operands);
7453 output_mov_immediate (otherops);
7455 else if (code1 == CONST_DOUBLE)
7457 if (GET_MODE (operands[1]) == DFmode)
7462 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
7463 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
7464 otherops[1] = GEN_INT (l[1]);
7465 operands[1] = GEN_INT (l[0]);
7467 else if (GET_MODE (operands[1]) != VOIDmode)
7469 else if (WORDS_BIG_ENDIAN)
7471 otherops[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
7472 operands[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
7476 otherops[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
7477 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
7480 output_mov_immediate (operands);
7481 output_mov_immediate (otherops);
7483 else if (code1 == CONST_INT)
7485 #if HOST_BITS_PER_WIDE_INT > 32
7486 /* If HOST_WIDE_INT is more than 32 bits, the intval tells us
7487 what the upper word is. */
7488 if (WORDS_BIG_ENDIAN)
7490 otherops[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1])));
7491 operands[1] = GEN_INT (INTVAL (operands[1]) >> 32);
7495 otherops[1] = GEN_INT (INTVAL (operands[1]) >> 32);
7496 operands[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1])));
7499 /* Sign extend the intval into the high-order word. */
7500 if (WORDS_BIG_ENDIAN)
7502 otherops[1] = operands[1];
7503 operands[1] = (INTVAL (operands[1]) < 0
7504 ? constm1_rtx : const0_rtx);
7507 otherops[1] = INTVAL (operands[1]) < 0 ? constm1_rtx : const0_rtx;
7509 output_mov_immediate (otherops);
7510 output_mov_immediate (operands);
7512 else if (code1 == MEM)
7514 switch (GET_CODE (XEXP (operands[1], 0)))
7517 output_asm_insn ("ldm%?ia\t%m1, %M0", operands);
7521 abort (); /* Should never happen now. */
7525 output_asm_insn ("ldm%?db\t%m1!, %M0", operands);
7529 output_asm_insn ("ldm%?ia\t%m1!, %M0", operands);
7533 abort (); /* Should never happen now. */
7538 output_asm_insn ("adr%?\t%0, %1", operands);
7539 output_asm_insn ("ldm%?ia\t%0, %M0", operands);
7543 if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1),
7544 GET_MODE (XEXP (XEXP (operands[1], 0), 1))))
7546 otherops[0] = operands[0];
7547 otherops[1] = XEXP (XEXP (operands[1], 0), 0);
7548 otherops[2] = XEXP (XEXP (operands[1], 0), 1);
7550 if (GET_CODE (XEXP (operands[1], 0)) == PLUS)
7552 if (GET_CODE (otherops[2]) == CONST_INT)
7554 switch ((int) INTVAL (otherops[2]))
7557 output_asm_insn ("ldm%?db\t%1, %M0", otherops);
7560 output_asm_insn ("ldm%?da\t%1, %M0", otherops);
7563 output_asm_insn ("ldm%?ib\t%1, %M0", otherops);
7567 if (!(const_ok_for_arm (INTVAL (otherops[2]))))
7568 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops);
7570 output_asm_insn ("add%?\t%0, %1, %2", otherops);
7573 output_asm_insn ("add%?\t%0, %1, %2", otherops);
7576 output_asm_insn ("sub%?\t%0, %1, %2", otherops);
7578 return "ldm%?ia\t%0, %M0";
7582 otherops[1] = adjust_address (operands[1], SImode, 4);
7583 /* Take care of overlapping base/data reg. */
7584 if (reg_mentioned_p (operands[0], operands[1]))
7586 output_asm_insn ("ldr%?\t%0, %1", otherops);
7587 output_asm_insn ("ldr%?\t%0, %1", operands);
7591 output_asm_insn ("ldr%?\t%0, %1", operands);
7592 output_asm_insn ("ldr%?\t%0, %1", otherops);
7598 abort (); /* Constraints should prevent this. */
7600 else if (code0 == MEM && code1 == REG)
7602 if (REGNO (operands[1]) == IP_REGNUM)
7605 switch (GET_CODE (XEXP (operands[0], 0)))
7608 output_asm_insn ("stm%?ia\t%m0, %M1", operands);
7612 abort (); /* Should never happen now. */
7616 output_asm_insn ("stm%?db\t%m0!, %M1", operands);
7620 output_asm_insn ("stm%?ia\t%m0!, %M1", operands);
7624 abort (); /* Should never happen now. */
7628 if (GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
7630 switch ((int) INTVAL (XEXP (XEXP (operands[0], 0), 1)))
7633 output_asm_insn ("stm%?db\t%m0, %M1", operands);
7637 output_asm_insn ("stm%?da\t%m0, %M1", operands);
7641 output_asm_insn ("stm%?ib\t%m0, %M1", operands);
7648 otherops[0] = adjust_address (operands[0], SImode, 4);
7649 otherops[1] = gen_rtx_REG (SImode, 1 + REGNO (operands[1]));
7650 output_asm_insn ("str%?\t%1, %0", operands);
7651 output_asm_insn ("str%?\t%1, %0", otherops);
7655 /* Constraints should prevent this. */
7662 /* Output an arbitrary MOV reg, #n.
7663 OPERANDS[0] is a register. OPERANDS[1] is a const_int. */
7665 output_mov_immediate (rtx *operands)
7667 HOST_WIDE_INT n = INTVAL (operands[1]);
7669 /* Try to use one MOV. */
7670 if (const_ok_for_arm (n))
7671 output_asm_insn ("mov%?\t%0, %1", operands);
7673 /* Try to use one MVN. */
7674 else if (const_ok_for_arm (~n))
7676 operands[1] = GEN_INT (~n);
7677 output_asm_insn ("mvn%?\t%0, %1", operands);
7684 /* If all else fails, make it out of ORRs or BICs as appropriate. */
7685 for (i = 0; i < 32; i++)
7689 if (n_ones > 16) /* Shorter to use MVN with BIC in this case. */
7690 output_multi_immediate (operands, "mvn%?\t%0, %1", "bic%?\t%0, %0, %1", 1, ~ n);
7692 output_multi_immediate (operands, "mov%?\t%0, %1", "orr%?\t%0, %0, %1", 1, n);
7698 /* Output an ADD r, s, #n where n may be too big for one instruction.
7699 If adding zero to one register, output nothing. */
7701 output_add_immediate (rtx *operands)
7703 HOST_WIDE_INT n = INTVAL (operands[2]);
7705 if (n != 0 || REGNO (operands[0]) != REGNO (operands[1]))
7708 output_multi_immediate (operands,
7709 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
7712 output_multi_immediate (operands,
7713 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
7720 /* Output a multiple immediate operation.
7721 OPERANDS is the vector of operands referred to in the output patterns.
7722 INSTR1 is the output pattern to use for the first constant.
7723 INSTR2 is the output pattern to use for subsequent constants.
7724 IMMED_OP is the index of the constant slot in OPERANDS.
7725 N is the constant value. */
7727 output_multi_immediate (rtx *operands, const char *instr1, const char *instr2,
7728 int immed_op, HOST_WIDE_INT n)
7730 #if HOST_BITS_PER_WIDE_INT > 32
7736 /* Quick and easy output. */
7737 operands[immed_op] = const0_rtx;
7738 output_asm_insn (instr1, operands);
7743 const char * instr = instr1;
7745 /* Note that n is never zero here (which would give no output). */
7746 for (i = 0; i < 32; i += 2)
7750 operands[immed_op] = GEN_INT (n & (255 << i));
7751 output_asm_insn (instr, operands);
7761 /* Return the appropriate ARM instruction for the operation code.
7762 The returned result should not be overwritten. OP is the rtx of the
7763 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
7766 arithmetic_instr (rtx op, int shift_first_arg)
7768 switch (GET_CODE (op))
7774 return shift_first_arg ? "rsb" : "sub";
7790 /* Ensure valid constant shifts and return the appropriate shift mnemonic
7791 for the operation code. The returned result should not be overwritten.
7792 OP is the rtx code of the shift.
7793 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
7796 shift_op (rtx op, HOST_WIDE_INT *amountp)
7799 enum rtx_code code = GET_CODE (op);
7801 if (GET_CODE (XEXP (op, 1)) == REG || GET_CODE (XEXP (op, 1)) == SUBREG)
7803 else if (GET_CODE (XEXP (op, 1)) == CONST_INT)
7804 *amountp = INTVAL (XEXP (op, 1));
7827 /* We never have to worry about the amount being other than a
7828 power of 2, since this case can never be reloaded from a reg. */
7830 *amountp = int_log2 (*amountp);
7841 /* This is not 100% correct, but follows from the desire to merge
7842 multiplication by a power of 2 with the recognizer for a
7843 shift. >=32 is not a valid shift for "asl", so we must try and
7844 output a shift that produces the correct arithmetical result.
7845 Using lsr #32 is identical except for the fact that the carry bit
7846 is not set correctly if we set the flags; but we never use the
7847 carry bit from such an operation, so we can ignore that. */
7848 if (code == ROTATERT)
7849 /* Rotate is just modulo 32. */
7851 else if (*amountp != (*amountp & 31))
7858 /* Shifts of 0 are no-ops. */
7866 /* Obtain the shift from the POWER of two. */
7868 static HOST_WIDE_INT
7869 int_log2 (HOST_WIDE_INT power)
7871 HOST_WIDE_INT shift = 0;
7873 while ((((HOST_WIDE_INT) 1 << shift) & power) == 0)
7883 /* Output a .ascii pseudo-op, keeping track of lengths. This is because
7884 /bin/as is horribly restrictive. */
7885 #define MAX_ASCII_LEN 51
7888 output_ascii_pseudo_op (FILE *stream, const unsigned char *p, int len)
7893 fputs ("\t.ascii\t\"", stream);
7895 for (i = 0; i < len; i++)
7899 if (len_so_far >= MAX_ASCII_LEN)
7901 fputs ("\"\n\t.ascii\t\"", stream);
7908 fputs ("\\t", stream);
7913 fputs ("\\f", stream);
7918 fputs ("\\b", stream);
7923 fputs ("\\r", stream);
7927 case TARGET_NEWLINE:
7928 fputs ("\\n", stream);
7930 if ((c >= ' ' && c <= '~')
7932 /* This is a good place for a line break. */
7933 len_so_far = MAX_ASCII_LEN;
7940 putc ('\\', stream);
7945 if (c >= ' ' && c <= '~')
7952 fprintf (stream, "\\%03o", c);
7959 fputs ("\"\n", stream);
7962 /* Compute the register sabe mask for registers 0 through 12
7963 inclusive. This code is used by both arm_compute_save_reg_mask
7964 and arm_compute_initial_elimination_offset. */
7965 static unsigned long
7966 arm_compute_save_reg0_reg12_mask (void)
7968 unsigned long func_type = arm_current_func_type ();
7969 unsigned int save_reg_mask = 0;
7972 if (IS_INTERRUPT (func_type))
7974 unsigned int max_reg;
7975 /* Interrupt functions must not corrupt any registers,
7976 even call clobbered ones. If this is a leaf function
7977 we can just examine the registers used by the RTL, but
7978 otherwise we have to assume that whatever function is
7979 called might clobber anything, and so we have to save
7980 all the call-clobbered registers as well. */
7981 if (ARM_FUNC_TYPE (func_type) == ARM_FT_FIQ)
7982 /* FIQ handlers have registers r8 - r12 banked, so
7983 we only need to check r0 - r7, Normal ISRs only
7984 bank r14 and r15, so we must check up to r12.
7985 r13 is the stack pointer which is always preserved,
7986 so we do not need to consider it here. */
7991 for (reg = 0; reg <= max_reg; reg++)
7992 if (regs_ever_live[reg]
7993 || (! current_function_is_leaf && call_used_regs [reg]))
7994 save_reg_mask |= (1 << reg);
7998 /* In the normal case we only need to save those registers
7999 which are call saved and which are used by this function. */
8000 for (reg = 0; reg <= 10; reg++)
8001 if (regs_ever_live[reg] && ! call_used_regs [reg])
8002 save_reg_mask |= (1 << reg);
8004 /* Handle the frame pointer as a special case. */
8005 if (! TARGET_APCS_FRAME
8006 && ! frame_pointer_needed
8007 && regs_ever_live[HARD_FRAME_POINTER_REGNUM]
8008 && ! call_used_regs[HARD_FRAME_POINTER_REGNUM])
8009 save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM;
8011 /* If we aren't loading the PIC register,
8012 don't stack it even though it may be live. */
8014 && ! TARGET_SINGLE_PIC_BASE
8015 && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
8016 save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
8019 return save_reg_mask;
8022 /* Compute a bit mask of which registers need to be
8023 saved on the stack for the current function. */
8025 static unsigned long
8026 arm_compute_save_reg_mask (void)
8028 unsigned int save_reg_mask = 0;
8029 unsigned long func_type = arm_current_func_type ();
8031 if (IS_NAKED (func_type))
8032 /* This should never really happen. */
8035 /* If we are creating a stack frame, then we must save the frame pointer,
8036 IP (which will hold the old stack pointer), LR and the PC. */
8037 if (frame_pointer_needed)
8039 (1 << ARM_HARD_FRAME_POINTER_REGNUM)
8044 /* Volatile functions do not return, so there
8045 is no need to save any other registers. */
8046 if (IS_VOLATILE (func_type))
8047 return save_reg_mask;
8049 save_reg_mask |= arm_compute_save_reg0_reg12_mask ();
8051 /* Decide if we need to save the link register.
8052 Interrupt routines have their own banked link register,
8053 so they never need to save it.
8054 Otherwise if we do not use the link register we do not need to save
8055 it. If we are pushing other registers onto the stack however, we
8056 can save an instruction in the epilogue by pushing the link register
8057 now and then popping it back into the PC. This incurs extra memory
8058 accesses though, so we only do it when optimizing for size, and only
8059 if we know that we will not need a fancy return sequence. */
8060 if (regs_ever_live [LR_REGNUM]
8063 && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL))
8064 save_reg_mask |= 1 << LR_REGNUM;
8066 if (cfun->machine->lr_save_eliminated)
8067 save_reg_mask &= ~ (1 << LR_REGNUM);
8069 if (TARGET_REALLY_IWMMXT
8070 && ((bit_count (save_reg_mask)
8071 + ARM_NUM_INTS (current_function_pretend_args_size)) % 2) != 0)
8075 /* The total number of registers that are going to be pushed
8076 onto the stack is odd. We need to ensure that the stack
8077 is 64-bit aligned before we start to save iWMMXt registers,
8078 and also before we start to create locals. (A local variable
8079 might be a double or long long which we will load/store using
8080 an iWMMXt instruction). Therefore we need to push another
8081 ARM register, so that the stack will be 64-bit aligned. We
8082 try to avoid using the arg registers (r0 -r3) as they might be
8083 used to pass values in a tail call. */
8084 for (reg = 4; reg <= 12; reg++)
8085 if ((save_reg_mask & (1 << reg)) == 0)
8089 save_reg_mask |= (1 << reg);
8092 cfun->machine->sibcall_blocked = 1;
8093 save_reg_mask |= (1 << 3);
8097 return save_reg_mask;
8100 /* Generate a function exit sequence. If REALLY_RETURN is false, then do
8101 everything bar the final return instruction. */
8103 output_return_instruction (rtx operand, int really_return, int reverse)
8105 char conditional[10];
8108 unsigned long live_regs_mask;
8109 unsigned long func_type;
8111 func_type = arm_current_func_type ();
8113 if (IS_NAKED (func_type))
8116 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
8118 /* If this function was declared non-returning, and we have
8119 found a tail call, then we have to trust that the called
8120 function won't return. */
8125 /* Otherwise, trap an attempted return by aborting. */
8127 ops[1] = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)"
8129 assemble_external_libcall (ops[1]);
8130 output_asm_insn (reverse ? "bl%D0\t%a1" : "bl%d0\t%a1", ops);
8136 if (current_function_calls_alloca && !really_return)
8139 sprintf (conditional, "%%?%%%c0", reverse ? 'D' : 'd');
8141 return_used_this_function = 1;
8143 live_regs_mask = arm_compute_save_reg_mask ();
8147 const char * return_reg;
8149 /* If we do not have any special requirements for function exit
8150 (eg interworking, or ISR) then we can load the return address
8151 directly into the PC. Otherwise we must load it into LR. */
8153 && ! TARGET_INTERWORK)
8154 return_reg = reg_names[PC_REGNUM];
8156 return_reg = reg_names[LR_REGNUM];
8158 if ((live_regs_mask & (1 << IP_REGNUM)) == (1 << IP_REGNUM))
8159 /* There are two possible reasons for the IP register being saved.
8160 Either a stack frame was created, in which case IP contains the
8161 old stack pointer, or an ISR routine corrupted it. If this in an
8162 ISR routine then just restore IP, otherwise restore IP into SP. */
8163 if (! IS_INTERRUPT (func_type))
8165 live_regs_mask &= ~ (1 << IP_REGNUM);
8166 live_regs_mask |= (1 << SP_REGNUM);
8169 /* On some ARM architectures it is faster to use LDR rather than
8170 LDM to load a single register. On other architectures, the
8171 cost is the same. In 26 bit mode, or for exception handlers,
8172 we have to use LDM to load the PC so that the CPSR is also
8174 for (reg = 0; reg <= LAST_ARM_REGNUM; reg++)
8176 if (live_regs_mask == (unsigned int)(1 << reg))
8179 if (reg <= LAST_ARM_REGNUM
8180 && (reg != LR_REGNUM
8182 || (TARGET_APCS_32 && ! IS_INTERRUPT (func_type))))
8184 sprintf (instr, "ldr%s\t%%|%s, [%%|sp], #4", conditional,
8185 (reg == LR_REGNUM) ? return_reg : reg_names[reg]);
8192 /* Generate the load multiple instruction to restore the
8193 registers. Note we can get here, even if
8194 frame_pointer_needed is true, but only if sp already
8195 points to the base of the saved core registers. */
8196 if (live_regs_mask & (1 << SP_REGNUM))
8197 sprintf (instr, "ldm%sfd\t%%|sp, {", conditional);
8199 sprintf (instr, "ldm%sfd\t%%|sp!, {", conditional);
8201 p = instr + strlen (instr);
8203 for (reg = 0; reg <= SP_REGNUM; reg++)
8204 if (live_regs_mask & (1 << reg))
8206 int l = strlen (reg_names[reg]);
8212 memcpy (p, ", ", 2);
8216 memcpy (p, "%|", 2);
8217 memcpy (p + 2, reg_names[reg], l);
8221 if (live_regs_mask & (1 << LR_REGNUM))
8223 sprintf (p, "%s%%|%s}", first ? "" : ", ", return_reg);
8224 /* Decide if we need to add the ^ symbol to the end of the
8225 register list. This causes the saved condition codes
8226 register to be copied into the current condition codes
8227 register. We do the copy if we are conforming to the 32-bit
8228 ABI and this is an interrupt function, or if we are
8229 conforming to the 26-bit ABI. There is a special case for
8230 the 26-bit ABI however, which is if we are writing back the
8231 stack pointer but not loading the PC. In this case adding
8232 the ^ symbol would create a type 2 LDM instruction, where
8233 writeback is UNPREDICTABLE. We are safe in leaving the ^
8234 character off in this case however, since the actual return
8235 instruction will be a MOVS which will restore the CPSR. */
8236 if ((TARGET_APCS_32 && IS_INTERRUPT (func_type))
8237 || (! TARGET_APCS_32 && really_return))
8244 output_asm_insn (instr, & operand);
8246 /* See if we need to generate an extra instruction to
8247 perform the actual function return. */
8249 && func_type != ARM_FT_INTERWORKED
8250 && (live_regs_mask & (1 << LR_REGNUM)) != 0)
8252 /* The return has already been handled
8253 by loading the LR into the PC. */
8260 switch ((int) ARM_FUNC_TYPE (func_type))
8264 sprintf (instr, "sub%ss\t%%|pc, %%|lr, #4", conditional);
8267 case ARM_FT_INTERWORKED:
8268 sprintf (instr, "bx%s\t%%|lr", conditional);
8271 case ARM_FT_EXCEPTION:
8272 sprintf (instr, "mov%ss\t%%|pc, %%|lr", conditional);
8276 /* ARMv5 implementations always provide BX, so interworking
8277 is the default unless APCS-26 is in use. */
8278 if ((insn_flags & FL_ARCH5) != 0 && TARGET_APCS_32)
8279 sprintf (instr, "bx%s\t%%|lr", conditional);
8281 sprintf (instr, "mov%s%s\t%%|pc, %%|lr",
8282 conditional, TARGET_APCS_32 ? "" : "s");
8286 output_asm_insn (instr, & operand);
8292 /* Write the function name into the code section, directly preceding
8293 the function prologue.
8295 Code will be output similar to this:
8297 .ascii "arm_poke_function_name", 0
8300 .word 0xff000000 + (t1 - t0)
8301 arm_poke_function_name
8303 stmfd sp!, {fp, ip, lr, pc}
8306 When performing a stack backtrace, code can inspect the value
8307 of 'pc' stored at 'fp' + 0. If the trace function then looks
8308 at location pc - 12 and the top 8 bits are set, then we know
8309 that there is a function name embedded immediately preceding this
8310 location and has length ((pc[-3]) & 0xff000000).
8312 We assume that pc is declared as a pointer to an unsigned long.
8314 It is of no benefit to output the function name if we are assembling
8315 a leaf function. These function types will not contain a stack
8316 backtrace structure, therefore it is not possible to determine the
8319 arm_poke_function_name (FILE *stream, const char *name)
8321 unsigned long alignlength;
8322 unsigned long length;
8325 length = strlen (name) + 1;
8326 alignlength = ROUND_UP_WORD (length);
8328 ASM_OUTPUT_ASCII (stream, name, length);
8329 ASM_OUTPUT_ALIGN (stream, 2);
8330 x = GEN_INT ((unsigned HOST_WIDE_INT) 0xff000000 + alignlength);
8331 assemble_aligned_integer (UNITS_PER_WORD, x);
8334 /* Place some comments into the assembler stream
8335 describing the current function. */
8337 arm_output_function_prologue (FILE *f, HOST_WIDE_INT frame_size)
8339 unsigned long func_type;
8343 thumb_output_function_prologue (f, frame_size);
8348 if (arm_ccfsm_state || arm_target_insn)
8351 func_type = arm_current_func_type ();
8353 switch ((int) ARM_FUNC_TYPE (func_type))
8358 case ARM_FT_INTERWORKED:
8359 asm_fprintf (f, "\t%@ Function supports interworking.\n");
8361 case ARM_FT_EXCEPTION_HANDLER:
8362 asm_fprintf (f, "\t%@ C++ Exception Handler.\n");
8365 asm_fprintf (f, "\t%@ Interrupt Service Routine.\n");
8368 asm_fprintf (f, "\t%@ Fast Interrupt Service Routine.\n");
8370 case ARM_FT_EXCEPTION:
8371 asm_fprintf (f, "\t%@ ARM Exception Handler.\n");
8375 if (IS_NAKED (func_type))
8376 asm_fprintf (f, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n");
8378 if (IS_VOLATILE (func_type))
8379 asm_fprintf (f, "\t%@ Volatile: function does not return.\n");
8381 if (IS_NESTED (func_type))
8382 asm_fprintf (f, "\t%@ Nested: function declared inside another function.\n");
8384 asm_fprintf (f, "\t%@ args = %d, pretend = %d, frame = %wd\n",
8385 current_function_args_size,
8386 current_function_pretend_args_size, frame_size);
8388 asm_fprintf (f, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n",
8389 frame_pointer_needed,
8390 cfun->machine->uses_anonymous_args);
8392 if (cfun->machine->lr_save_eliminated)
8393 asm_fprintf (f, "\t%@ link register save eliminated.\n");
8395 #ifdef AOF_ASSEMBLER
8397 asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, PIC_OFFSET_TABLE_REGNUM);
8400 return_used_this_function = 0;
8404 arm_output_epilogue (int really_return)
8407 unsigned long saved_regs_mask;
8408 unsigned long func_type;
8409 /* Floats_offset is the offset from the "virtual" frame. In an APCS
8410 frame that is $fp + 4 for a non-variadic function. */
8411 int floats_offset = 0;
8413 int frame_size = arm_get_frame_size ();
8414 FILE * f = asm_out_file;
8415 rtx eh_ofs = cfun->machine->eh_epilogue_sp_ofs;
8416 unsigned int lrm_count = 0;
8418 /* If we have already generated the return instruction
8419 then it is futile to generate anything else. */
8420 if (use_return_insn (FALSE) && return_used_this_function)
8423 func_type = arm_current_func_type ();
8425 if (IS_NAKED (func_type))
8426 /* Naked functions don't have epilogues. */
8429 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
8433 /* A volatile function should never return. Call abort. */
8434 op = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" : "abort");
8435 assemble_external_libcall (op);
8436 output_asm_insn ("bl\t%a0", &op);
8441 if (ARM_FUNC_TYPE (func_type) == ARM_FT_EXCEPTION_HANDLER
8443 /* If we are throwing an exception, then we really must
8444 be doing a return, so we can't tail-call. */
8447 saved_regs_mask = arm_compute_save_reg_mask ();
8450 lrm_count = bit_count (saved_regs_mask);
8452 /* XXX We should adjust floats_offset for any anonymous args, and then
8453 re-adjust vfp_offset below to compensate. */
8455 /* Compute how far away the floats will be. */
8456 for (reg = 0; reg <= LAST_ARM_REGNUM; reg++)
8457 if (saved_regs_mask & (1 << reg))
8460 if (frame_pointer_needed)
8464 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
8466 for (reg = LAST_ARM_FP_REGNUM; reg >= FIRST_ARM_FP_REGNUM; reg--)
8467 if (regs_ever_live[reg] && !call_used_regs[reg])
8469 floats_offset += 12;
8470 asm_fprintf (f, "\tldfe\t%r, [%r, #-%d]\n",
8471 reg, FP_REGNUM, floats_offset - vfp_offset);
8476 int start_reg = LAST_ARM_FP_REGNUM;
8478 for (reg = LAST_ARM_FP_REGNUM; reg >= FIRST_ARM_FP_REGNUM; reg--)
8480 if (regs_ever_live[reg] && !call_used_regs[reg])
8482 floats_offset += 12;
8484 /* We can't unstack more than four registers at once. */
8485 if (start_reg - reg == 3)
8487 asm_fprintf (f, "\tlfm\t%r, 4, [%r, #-%d]\n",
8488 reg, FP_REGNUM, floats_offset - vfp_offset);
8489 start_reg = reg - 1;
8494 if (reg != start_reg)
8495 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
8496 reg + 1, start_reg - reg,
8497 FP_REGNUM, floats_offset - vfp_offset);
8498 start_reg = reg - 1;
8502 /* Just in case the last register checked also needs unstacking. */
8503 if (reg != start_reg)
8504 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
8505 reg + 1, start_reg - reg,
8506 FP_REGNUM, floats_offset - vfp_offset);
8511 /* The frame pointer is guaranteed to be non-double-word aligned.
8512 This is because it is set to (old_stack_pointer - 4) and the
8513 old_stack_pointer was double word aligned. Thus the offset to
8514 the iWMMXt registers to be loaded must also be non-double-word
8515 sized, so that the resultant address *is* double-word aligned.
8516 We can ignore floats_offset since that was already included in
8517 the live_regs_mask. */
8518 lrm_count += (lrm_count % 2 ? 2 : 1);
8520 for (reg = FIRST_IWMMXT_REGNUM; reg <= LAST_IWMMXT_REGNUM; reg++)
8521 if (regs_ever_live[reg] && !call_used_regs[reg])
8523 asm_fprintf (f, "\twldrd\t%r, [%r, #-%d]\n",
8524 reg, FP_REGNUM, lrm_count * 4);
8529 /* saved_regs_mask should contain the IP, which at the time of stack
8530 frame generation actually contains the old stack pointer. So a
8531 quick way to unwind the stack is just pop the IP register directly
8532 into the stack pointer. */
8533 if ((saved_regs_mask & (1 << IP_REGNUM)) == 0)
8535 saved_regs_mask &= ~ (1 << IP_REGNUM);
8536 saved_regs_mask |= (1 << SP_REGNUM);
8538 /* There are two registers left in saved_regs_mask - LR and PC. We
8539 only need to restore the LR register (the return address), but to
8540 save time we can load it directly into the PC, unless we need a
8541 special function exit sequence, or we are not really returning. */
8542 if (really_return && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL)
8543 /* Delete the LR from the register mask, so that the LR on
8544 the stack is loaded into the PC in the register mask. */
8545 saved_regs_mask &= ~ (1 << LR_REGNUM);
8547 saved_regs_mask &= ~ (1 << PC_REGNUM);
8549 /* We must use SP as the base register, because SP is one of the
8550 registers being restored. If an interrupt or page fault
8551 happens in the ldm instruction, the SP might or might not
8552 have been restored. That would be bad, as then SP will no
8553 longer indicate the safe area of stack, and we can get stack
8554 corruption. Using SP as the base register means that it will
8555 be reset correctly to the original value, should an interrupt
8556 occur. If the stack pointer already points at the right
8557 place, then omit the subtraction. */
8558 if (((frame_size + current_function_outgoing_args_size + floats_offset)
8559 != 4 * (1 + (int) bit_count (saved_regs_mask)))
8560 || current_function_calls_alloca)
8561 asm_fprintf (f, "\tsub\t%r, %r, #%d\n", SP_REGNUM, FP_REGNUM,
8562 4 * bit_count (saved_regs_mask));
8563 print_multi_reg (f, "ldmfd\t%r", SP_REGNUM, saved_regs_mask);
8565 if (IS_INTERRUPT (func_type))
8566 /* Interrupt handlers will have pushed the
8567 IP onto the stack, so restore it now. */
8568 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, 1 << IP_REGNUM);
8572 /* Restore stack pointer if necessary. */
8573 if (frame_size + current_function_outgoing_args_size != 0)
8575 operands[0] = operands[1] = stack_pointer_rtx;
8576 operands[2] = GEN_INT (frame_size
8577 + current_function_outgoing_args_size);
8578 output_add_immediate (operands);
8581 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
8583 for (reg = FIRST_ARM_FP_REGNUM; reg <= LAST_ARM_FP_REGNUM; reg++)
8584 if (regs_ever_live[reg] && !call_used_regs[reg])
8585 asm_fprintf (f, "\tldfe\t%r, [%r], #12\n",
8590 int start_reg = FIRST_ARM_FP_REGNUM;
8592 for (reg = FIRST_ARM_FP_REGNUM; reg <= LAST_ARM_FP_REGNUM; reg++)
8594 if (regs_ever_live[reg] && !call_used_regs[reg])
8596 if (reg - start_reg == 3)
8598 asm_fprintf (f, "\tlfmfd\t%r, 4, [%r]!\n",
8599 start_reg, SP_REGNUM);
8600 start_reg = reg + 1;
8605 if (reg != start_reg)
8606 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
8607 start_reg, reg - start_reg,
8610 start_reg = reg + 1;
8614 /* Just in case the last register checked also needs unstacking. */
8615 if (reg != start_reg)
8616 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
8617 start_reg, reg - start_reg, SP_REGNUM);
8621 for (reg = FIRST_IWMMXT_REGNUM; reg <= LAST_IWMMXT_REGNUM; reg++)
8622 if (regs_ever_live[reg] && !call_used_regs[reg])
8623 asm_fprintf (f, "\twldrd\t%r, [%r, #+8]!\n", reg, SP_REGNUM);
8625 /* If we can, restore the LR into the PC. */
8626 if (ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
8628 && current_function_pretend_args_size == 0
8629 && saved_regs_mask & (1 << LR_REGNUM))
8631 saved_regs_mask &= ~ (1 << LR_REGNUM);
8632 saved_regs_mask |= (1 << PC_REGNUM);
8635 /* Load the registers off the stack. If we only have one register
8636 to load use the LDR instruction - it is faster. */
8637 if (saved_regs_mask == (1 << LR_REGNUM))
8639 /* The exception handler ignores the LR, so we do
8640 not really need to load it off the stack. */
8642 asm_fprintf (f, "\tadd\t%r, %r, #4\n", SP_REGNUM, SP_REGNUM);
8644 asm_fprintf (f, "\tldr\t%r, [%r], #4\n", LR_REGNUM, SP_REGNUM);
8646 else if (saved_regs_mask)
8648 if (saved_regs_mask & (1 << SP_REGNUM))
8649 /* Note - write back to the stack register is not enabled
8650 (ie "ldmfd sp!..."). We know that the stack pointer is
8651 in the list of registers and if we add writeback the
8652 instruction becomes UNPREDICTABLE. */
8653 print_multi_reg (f, "ldmfd\t%r", SP_REGNUM, saved_regs_mask);
8655 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, saved_regs_mask);
8658 if (current_function_pretend_args_size)
8660 /* Unwind the pre-pushed regs. */
8661 operands[0] = operands[1] = stack_pointer_rtx;
8662 operands[2] = GEN_INT (current_function_pretend_args_size);
8663 output_add_immediate (operands);
8668 || (ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
8669 && current_function_pretend_args_size == 0
8670 && saved_regs_mask & (1 << PC_REGNUM)))
8673 /* Generate the return instruction. */
8674 switch ((int) ARM_FUNC_TYPE (func_type))
8676 case ARM_FT_EXCEPTION_HANDLER:
8677 /* Even in 26-bit mode we do a mov (rather than a movs)
8678 because we don't have the PSR bits set in the address. */
8679 asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, EXCEPTION_LR_REGNUM);
8684 asm_fprintf (f, "\tsubs\t%r, %r, #4\n", PC_REGNUM, LR_REGNUM);
8687 case ARM_FT_EXCEPTION:
8688 asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM);
8691 case ARM_FT_INTERWORKED:
8692 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
8696 if (frame_pointer_needed)
8697 /* If we used the frame pointer then the return address
8698 will have been loaded off the stack directly into the
8699 PC, so there is no need to issue a MOV instruction
8702 else if (current_function_pretend_args_size == 0
8703 && (saved_regs_mask & (1 << LR_REGNUM)))
8704 /* Similarly we may have been able to load LR into the PC
8705 even if we did not create a stack frame. */
8707 else if (TARGET_APCS_32)
8708 asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, LR_REGNUM);
8710 asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM);
8718 arm_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
8719 HOST_WIDE_INT frame_size)
8723 /* ??? Probably not safe to set this here, since it assumes that a
8724 function will be emitted as assembly immediately after we generate
8725 RTL for it. This does not happen for inline functions. */
8726 return_used_this_function = 0;
8730 /* We need to take into account any stack-frame rounding. */
8731 frame_size = arm_get_frame_size ();
8733 if (use_return_insn (FALSE)
8734 && return_used_this_function
8735 && (frame_size + current_function_outgoing_args_size) != 0
8736 && !frame_pointer_needed)
8739 /* Reset the ARM-specific per-function variables. */
8740 after_arm_reorg = 0;
8744 /* Generate and emit an insn that we will recognize as a push_multi.
8745 Unfortunately, since this insn does not reflect very well the actual
8746 semantics of the operation, we need to annotate the insn for the benefit
8747 of DWARF2 frame unwind information. */
8749 emit_multi_reg_push (int mask)
8756 int dwarf_par_index;
8759 for (i = 0; i <= LAST_ARM_REGNUM; i++)
8760 if (mask & (1 << i))
8763 if (num_regs == 0 || num_regs > 16)
8766 /* We don't record the PC in the dwarf frame information. */
8767 num_dwarf_regs = num_regs;
8768 if (mask & (1 << PC_REGNUM))
8771 /* For the body of the insn we are going to generate an UNSPEC in
8772 parallel with several USEs. This allows the insn to be recognized
8773 by the push_multi pattern in the arm.md file. The insn looks
8774 something like this:
8777 (set (mem:BLK (pre_dec:BLK (reg:SI sp)))
8778 (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT))
8779 (use (reg:SI 11 fp))
8780 (use (reg:SI 12 ip))
8781 (use (reg:SI 14 lr))
8782 (use (reg:SI 15 pc))
8785 For the frame note however, we try to be more explicit and actually
8786 show each register being stored into the stack frame, plus a (single)
8787 decrement of the stack pointer. We do it this way in order to be
8788 friendly to the stack unwinding code, which only wants to see a single
8789 stack decrement per instruction. The RTL we generate for the note looks
8790 something like this:
8793 (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20)))
8794 (set (mem:SI (reg:SI sp)) (reg:SI r4))
8795 (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp))
8796 (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip))
8797 (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr))
8800 This sequence is used both by the code to support stack unwinding for
8801 exceptions handlers and the code to generate dwarf2 frame debugging. */
8803 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_regs));
8804 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (num_dwarf_regs + 1));
8805 dwarf_par_index = 1;
8807 for (i = 0; i <= LAST_ARM_REGNUM; i++)
8809 if (mask & (1 << i))
8811 reg = gen_rtx_REG (SImode, i);
8814 = gen_rtx_SET (VOIDmode,
8815 gen_rtx_MEM (BLKmode,
8816 gen_rtx_PRE_DEC (BLKmode,
8817 stack_pointer_rtx)),
8818 gen_rtx_UNSPEC (BLKmode,
8824 tmp = gen_rtx_SET (VOIDmode,
8825 gen_rtx_MEM (SImode, stack_pointer_rtx),
8827 RTX_FRAME_RELATED_P (tmp) = 1;
8828 XVECEXP (dwarf, 0, dwarf_par_index) = tmp;
8836 for (j = 1, i++; j < num_regs; i++)
8838 if (mask & (1 << i))
8840 reg = gen_rtx_REG (SImode, i);
8842 XVECEXP (par, 0, j) = gen_rtx_USE (VOIDmode, reg);
8846 tmp = gen_rtx_SET (VOIDmode,
8847 gen_rtx_MEM (SImode,
8848 plus_constant (stack_pointer_rtx,
8851 RTX_FRAME_RELATED_P (tmp) = 1;
8852 XVECEXP (dwarf, 0, dwarf_par_index++) = tmp;
8859 par = emit_insn (par);
8861 tmp = gen_rtx_SET (SImode,
8863 gen_rtx_PLUS (SImode,
8865 GEN_INT (-4 * num_regs)));
8866 RTX_FRAME_RELATED_P (tmp) = 1;
8867 XVECEXP (dwarf, 0, 0) = tmp;
8869 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
8875 emit_sfm (int base_reg, int count)
8882 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
8883 dwarf = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
8885 reg = gen_rtx_REG (XFmode, base_reg++);
8888 = gen_rtx_SET (VOIDmode,
8889 gen_rtx_MEM (BLKmode,
8890 gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
8891 gen_rtx_UNSPEC (BLKmode,
8895 = gen_rtx_SET (VOIDmode,
8896 gen_rtx_MEM (XFmode,
8897 gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
8899 RTX_FRAME_RELATED_P (tmp) = 1;
8900 XVECEXP (dwarf, 0, count - 1) = tmp;
8902 for (i = 1; i < count; i++)
8904 reg = gen_rtx_REG (XFmode, base_reg++);
8905 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
8907 tmp = gen_rtx_SET (VOIDmode,
8908 gen_rtx_MEM (XFmode,
8909 gen_rtx_PRE_DEC (BLKmode,
8910 stack_pointer_rtx)),
8912 RTX_FRAME_RELATED_P (tmp) = 1;
8913 XVECEXP (dwarf, 0, count - i - 1) = tmp;
8916 par = emit_insn (par);
8917 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
8922 /* Compute the distance from register FROM to register TO.
8923 These can be the arg pointer (26), the soft frame pointer (25),
8924 the stack pointer (13) or the hard frame pointer (11).
8925 Typical stack layout looks like this:
8927 old stack pointer -> | |
8930 | | saved arguments for
8931 | | vararg functions
8934 hard FP & arg pointer -> | | \
8942 soft frame pointer -> | | /
8952 current stack pointer -> | | /
8955 For a given function some or all of these stack components
8956 may not be needed, giving rise to the possibility of
8957 eliminating some of the registers.
8959 The values returned by this function must reflect the behavior
8960 of arm_expand_prologue() and arm_compute_save_reg_mask().
8962 The sign of the number returned reflects the direction of stack
8963 growth, so the values are positive for all eliminations except
8964 from the soft frame pointer to the hard frame pointer. */
8966 arm_compute_initial_elimination_offset (unsigned int from, unsigned int to)
8968 unsigned int local_vars = arm_get_frame_size ();
8969 unsigned int outgoing_args = current_function_outgoing_args_size;
8970 unsigned int stack_frame;
8971 unsigned int call_saved_registers;
8972 unsigned long func_type;
8974 func_type = arm_current_func_type ();
8976 /* Volatile functions never return, so there is
8977 no need to save call saved registers. */
8978 call_saved_registers = 0;
8979 if (! IS_VOLATILE (func_type))
8981 unsigned int reg_mask;
8984 /* Make sure that we compute which registers will be saved
8985 on the stack using the same algorithm that is used by
8986 the prologue creation code. */
8987 reg_mask = arm_compute_save_reg_mask ();
8989 /* Now count the number of bits set in save_reg_mask.
8990 If we have already counted the registers in the stack
8991 frame, do not count them again. Non call-saved registers
8992 might be saved in the call-save area of the stack, if
8993 doing so will preserve the stack's alignment. Hence we
8994 must count them here. For each set bit we need 4 bytes
8996 if (frame_pointer_needed)
8998 call_saved_registers += 4 * bit_count (reg_mask);
9000 /* If the hard floating point registers are going to be
9001 used then they must be saved on the stack as well.
9002 Each register occupies 12 bytes of stack space. */
9003 for (reg = FIRST_ARM_FP_REGNUM; reg <= LAST_ARM_FP_REGNUM; reg++)
9004 if (regs_ever_live[reg] && ! call_used_regs[reg])
9005 call_saved_registers += 12;
9007 if (TARGET_REALLY_IWMMXT)
9008 /* Check for the call-saved iWMMXt registers. */
9009 for (reg = FIRST_IWMMXT_REGNUM; reg <= LAST_IWMMXT_REGNUM; reg++)
9010 if (regs_ever_live[reg] && ! call_used_regs [reg])
9011 call_saved_registers += 8;
9014 /* The stack frame contains 4 registers - the old frame pointer,
9015 the old stack pointer, the return address and PC of the start
9017 stack_frame = frame_pointer_needed ? 16 : 0;
9019 /* OK, now we have enough information to compute the distances.
9020 There must be an entry in these switch tables for each pair
9021 of registers in ELIMINABLE_REGS, even if some of the entries
9022 seem to be redundant or useless. */
9025 case ARG_POINTER_REGNUM:
9028 case THUMB_HARD_FRAME_POINTER_REGNUM:
9031 case FRAME_POINTER_REGNUM:
9032 /* This is the reverse of the soft frame pointer
9033 to hard frame pointer elimination below. */
9034 if (call_saved_registers == 0 && stack_frame == 0)
9036 return (call_saved_registers + stack_frame - 4);
9038 case ARM_HARD_FRAME_POINTER_REGNUM:
9039 /* If there is no stack frame then the hard
9040 frame pointer and the arg pointer coincide. */
9041 if (stack_frame == 0 && call_saved_registers != 0)
9043 /* FIXME: Not sure about this. Maybe we should always return 0 ? */
9044 return (frame_pointer_needed
9045 && current_function_needs_context
9046 && ! cfun->machine->uses_anonymous_args) ? 4 : 0;
9048 case STACK_POINTER_REGNUM:
9049 /* If nothing has been pushed on the stack at all
9050 then this will return -4. This *is* correct! */
9051 return call_saved_registers + stack_frame + local_vars + outgoing_args - 4;
9058 case FRAME_POINTER_REGNUM:
9061 case THUMB_HARD_FRAME_POINTER_REGNUM:
9064 case ARM_HARD_FRAME_POINTER_REGNUM:
9065 /* The hard frame pointer points to the top entry in the
9066 stack frame. The soft frame pointer to the bottom entry
9067 in the stack frame. If there is no stack frame at all,
9068 then they are identical. */
9069 if (call_saved_registers == 0 && stack_frame == 0)
9071 return - (call_saved_registers + stack_frame - 4);
9073 case STACK_POINTER_REGNUM:
9074 return local_vars + outgoing_args;
9082 /* You cannot eliminate from the stack pointer.
9083 In theory you could eliminate from the hard frame
9084 pointer to the stack pointer, but this will never
9085 happen, since if a stack frame is not needed the
9086 hard frame pointer will never be used. */
9091 /* Calculate the size of the stack frame, taking into account any
9092 padding that is required to ensure stack-alignment. */
9094 arm_get_frame_size (void)
9098 int base_size = ROUND_UP_WORD (get_frame_size ());
9100 unsigned long func_type = arm_current_func_type ();
9109 /* We need to know if we are a leaf function. Unfortunately, it
9110 is possible to be called after start_sequence has been called,
9111 which causes get_insns to return the insns for the sequence,
9112 not the function, which will cause leaf_function_p to return
9113 the incorrect result.
9115 To work around this, we cache the computed frame size. This
9116 works because we will only be calling RTL expanders that need
9117 to know about leaf functions once reload has completed, and the
9118 frame size cannot be changed after that time, so we can safely
9119 use the cached value. */
9121 if (reload_completed)
9122 return cfun->machine->frame_size;
9124 leaf = leaf_function_p ();
9126 /* A leaf function does not need any stack alignment if it has nothing
9128 if (leaf && base_size == 0)
9130 cfun->machine->frame_size = 0;
9134 /* We know that SP will be word aligned on entry, and we must
9135 preserve that condition at any subroutine call. But those are
9136 the only constraints. */
9138 /* Space for variadic functions. */
9139 if (current_function_pretend_args_size)
9140 entry_size += current_function_pretend_args_size;
9142 /* Space for saved registers. */
9143 entry_size += bit_count (arm_compute_save_reg_mask ()) * 4;
9145 /* Space for saved FPA registers. */
9146 if (! IS_VOLATILE (func_type))
9148 for (regno = FIRST_ARM_FP_REGNUM; regno <= LAST_ARM_FP_REGNUM; regno++)
9149 if (regs_ever_live[regno] && ! call_used_regs[regno])
9153 if (TARGET_REALLY_IWMMXT)
9155 /* Check for the call-saved iWMMXt registers. */
9156 for (regno = FIRST_IWMMXT_REGNUM; regno <= LAST_IWMMXT_REGNUM; regno++)
9157 if (regs_ever_live [regno] && ! call_used_regs [regno])
9161 if ((entry_size + base_size + current_function_outgoing_args_size) & 7)
9163 if ((entry_size + base_size + current_function_outgoing_args_size) & 7)
9166 cfun->machine->frame_size = base_size;
9171 /* Generate the prologue instructions for entry into an ARM function. */
9173 arm_expand_prologue (void)
9179 unsigned long live_regs_mask;
9180 unsigned long func_type;
9182 int saved_pretend_args = 0;
9183 unsigned int args_to_push;
9185 func_type = arm_current_func_type ();
9187 /* Naked functions don't have prologues. */
9188 if (IS_NAKED (func_type))
9191 /* Make a copy of c_f_p_a_s as we may need to modify it locally. */
9192 args_to_push = current_function_pretend_args_size;
9194 /* Compute which register we will have to save onto the stack. */
9195 live_regs_mask = arm_compute_save_reg_mask ();
9197 ip_rtx = gen_rtx_REG (SImode, IP_REGNUM);
9199 if (frame_pointer_needed)
9201 if (IS_INTERRUPT (func_type))
9203 /* Interrupt functions must not corrupt any registers.
9204 Creating a frame pointer however, corrupts the IP
9205 register, so we must push it first. */
9206 insn = emit_multi_reg_push (1 << IP_REGNUM);
9208 /* Do not set RTX_FRAME_RELATED_P on this insn.
9209 The dwarf stack unwinding code only wants to see one
9210 stack decrement per function, and this is not it. If
9211 this instruction is labeled as being part of the frame
9212 creation sequence then dwarf2out_frame_debug_expr will
9213 abort when it encounters the assignment of IP to FP
9214 later on, since the use of SP here establishes SP as
9215 the CFA register and not IP.
9217 Anyway this instruction is not really part of the stack
9218 frame creation although it is part of the prologue. */
9220 else if (IS_NESTED (func_type))
9222 /* The Static chain register is the same as the IP register
9223 used as a scratch register during stack frame creation.
9224 To get around this need to find somewhere to store IP
9225 whilst the frame is being created. We try the following
9228 1. The last argument register.
9229 2. A slot on the stack above the frame. (This only
9230 works if the function is not a varargs function).
9231 3. Register r3, after pushing the argument registers
9234 Note - we only need to tell the dwarf2 backend about the SP
9235 adjustment in the second variant; the static chain register
9236 doesn't need to be unwound, as it doesn't contain a value
9237 inherited from the caller. */
9239 if (regs_ever_live[3] == 0)
9241 insn = gen_rtx_REG (SImode, 3);
9242 insn = gen_rtx_SET (SImode, insn, ip_rtx);
9243 insn = emit_insn (insn);
9245 else if (args_to_push == 0)
9248 insn = gen_rtx_PRE_DEC (SImode, stack_pointer_rtx);
9249 insn = gen_rtx_MEM (SImode, insn);
9250 insn = gen_rtx_SET (VOIDmode, insn, ip_rtx);
9251 insn = emit_insn (insn);
9255 /* Just tell the dwarf backend that we adjusted SP. */
9256 dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
9257 gen_rtx_PLUS (SImode, stack_pointer_rtx,
9258 GEN_INT (-fp_offset)));
9259 RTX_FRAME_RELATED_P (insn) = 1;
9260 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
9261 dwarf, REG_NOTES (insn));
9265 /* Store the args on the stack. */
9266 if (cfun->machine->uses_anonymous_args)
9267 insn = emit_multi_reg_push
9268 ((0xf0 >> (args_to_push / 4)) & 0xf);
9271 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
9272 GEN_INT (- args_to_push)));
9274 RTX_FRAME_RELATED_P (insn) = 1;
9276 saved_pretend_args = 1;
9277 fp_offset = args_to_push;
9280 /* Now reuse r3 to preserve IP. */
9281 insn = gen_rtx_REG (SImode, 3);
9282 insn = gen_rtx_SET (SImode, insn, ip_rtx);
9283 (void) emit_insn (insn);
9289 insn = gen_rtx_PLUS (SImode, stack_pointer_rtx, GEN_INT (fp_offset));
9290 insn = gen_rtx_SET (SImode, ip_rtx, insn);
9293 insn = gen_movsi (ip_rtx, stack_pointer_rtx);
9295 insn = emit_insn (insn);
9296 RTX_FRAME_RELATED_P (insn) = 1;
9301 /* Push the argument registers, or reserve space for them. */
9302 if (cfun->machine->uses_anonymous_args)
9303 insn = emit_multi_reg_push
9304 ((0xf0 >> (args_to_push / 4)) & 0xf);
9307 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
9308 GEN_INT (- args_to_push)));
9309 RTX_FRAME_RELATED_P (insn) = 1;
9312 /* If this is an interrupt service routine, and the link register
9313 is going to be pushed, and we are not creating a stack frame,
9314 (which would involve an extra push of IP and a pop in the epilogue)
9315 subtracting four from LR now will mean that the function return
9316 can be done with a single instruction. */
9317 if ((func_type == ARM_FT_ISR || func_type == ARM_FT_FIQ)
9318 && (live_regs_mask & (1 << LR_REGNUM)) != 0
9319 && ! frame_pointer_needed)
9320 emit_insn (gen_rtx_SET (SImode,
9321 gen_rtx_REG (SImode, LR_REGNUM),
9322 gen_rtx_PLUS (SImode,
9323 gen_rtx_REG (SImode, LR_REGNUM),
9328 insn = emit_multi_reg_push (live_regs_mask);
9329 RTX_FRAME_RELATED_P (insn) = 1;
9333 for (reg = FIRST_IWMMXT_REGNUM; reg <= LAST_IWMMXT_REGNUM; reg++)
9334 if (regs_ever_live[reg] && ! call_used_regs [reg])
9336 insn = gen_rtx_PRE_DEC (V2SImode, stack_pointer_rtx);
9337 insn = gen_rtx_MEM (V2SImode, insn);
9338 insn = emit_insn (gen_rtx_SET (VOIDmode, insn,
9339 gen_rtx_REG (V2SImode, reg)));
9340 RTX_FRAME_RELATED_P (insn) = 1;
9343 if (! IS_VOLATILE (func_type))
9345 /* Save any floating point call-saved registers used by this
9347 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
9349 for (reg = LAST_ARM_FP_REGNUM; reg >= FIRST_ARM_FP_REGNUM; reg--)
9350 if (regs_ever_live[reg] && !call_used_regs[reg])
9352 insn = gen_rtx_PRE_DEC (XFmode, stack_pointer_rtx);
9353 insn = gen_rtx_MEM (XFmode, insn);
9354 insn = emit_insn (gen_rtx_SET (VOIDmode, insn,
9355 gen_rtx_REG (XFmode, reg)));
9356 RTX_FRAME_RELATED_P (insn) = 1;
9361 int start_reg = LAST_ARM_FP_REGNUM;
9363 for (reg = LAST_ARM_FP_REGNUM; reg >= FIRST_ARM_FP_REGNUM; reg--)
9365 if (regs_ever_live[reg] && !call_used_regs[reg])
9367 if (start_reg - reg == 3)
9369 insn = emit_sfm (reg, 4);
9370 RTX_FRAME_RELATED_P (insn) = 1;
9371 start_reg = reg - 1;
9376 if (start_reg != reg)
9378 insn = emit_sfm (reg + 1, start_reg - reg);
9379 RTX_FRAME_RELATED_P (insn) = 1;
9381 start_reg = reg - 1;
9385 if (start_reg != reg)
9387 insn = emit_sfm (reg + 1, start_reg - reg);
9388 RTX_FRAME_RELATED_P (insn) = 1;
9393 if (frame_pointer_needed)
9395 /* Create the new frame pointer. */
9396 insn = GEN_INT (-(4 + args_to_push + fp_offset));
9397 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, ip_rtx, insn));
9398 RTX_FRAME_RELATED_P (insn) = 1;
9400 if (IS_NESTED (func_type))
9402 /* Recover the static chain register. */
9403 if (regs_ever_live [3] == 0
9404 || saved_pretend_args)
9405 insn = gen_rtx_REG (SImode, 3);
9406 else /* if (current_function_pretend_args_size == 0) */
9408 insn = gen_rtx_PLUS (SImode, hard_frame_pointer_rtx,
9410 insn = gen_rtx_MEM (SImode, insn);
9413 emit_insn (gen_rtx_SET (SImode, ip_rtx, insn));
9414 /* Add a USE to stop propagate_one_insn() from barfing. */
9415 emit_insn (gen_prologue_use (ip_rtx));
9419 amount = GEN_INT (-(arm_get_frame_size ()
9420 + current_function_outgoing_args_size));
9422 if (amount != const0_rtx)
9424 /* This add can produce multiple insns for a large constant, so we
9425 need to get tricky. */
9426 rtx last = get_last_insn ();
9427 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
9431 last = last ? NEXT_INSN (last) : get_insns ();
9432 RTX_FRAME_RELATED_P (last) = 1;
9434 while (last != insn);
9436 /* If the frame pointer is needed, emit a special barrier that
9437 will prevent the scheduler from moving stores to the frame
9438 before the stack adjustment. */
9439 if (frame_pointer_needed)
9440 insn = emit_insn (gen_stack_tie (stack_pointer_rtx,
9441 hard_frame_pointer_rtx));
9444 /* If we are profiling, make sure no instructions are scheduled before
9445 the call to mcount. Similarly if the user has requested no
9446 scheduling in the prolog. */
9447 if (current_function_profile || TARGET_NO_SCHED_PRO)
9448 emit_insn (gen_blockage ());
9450 /* If the link register is being kept alive, with the return address in it,
9451 then make sure that it does not get reused by the ce2 pass. */
9452 if ((live_regs_mask & (1 << LR_REGNUM)) == 0)
9454 emit_insn (gen_prologue_use (gen_rtx_REG (SImode, LR_REGNUM)));
9455 cfun->machine->lr_save_eliminated = 1;
9459 /* If CODE is 'd', then the X is a condition operand and the instruction
9460 should only be executed if the condition is true.
9461 if CODE is 'D', then the X is a condition operand and the instruction
9462 should only be executed if the condition is false: however, if the mode
9463 of the comparison is CCFPEmode, then always execute the instruction -- we
9464 do this because in these circumstances !GE does not necessarily imply LT;
9465 in these cases the instruction pattern will take care to make sure that
9466 an instruction containing %d will follow, thereby undoing the effects of
9467 doing this instruction unconditionally.
9468 If CODE is 'N' then X is a floating point operand that must be negated
9470 If CODE is 'B' then output a bitwise inverted value of X (a const int).
9471 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
9473 arm_print_operand (FILE *stream, rtx x, int code)
9478 fputs (ASM_COMMENT_START, stream);
9482 fputs (user_label_prefix, stream);
9486 fputs (REGISTER_PREFIX, stream);
9490 if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4)
9492 if (TARGET_THUMB || current_insn_predicate != NULL)
9495 fputs (arm_condition_codes[arm_current_cc], stream);
9497 else if (current_insn_predicate)
9499 enum arm_cond_code code;
9504 code = get_arm_condition_code (current_insn_predicate);
9505 fputs (arm_condition_codes[code], stream);
9512 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
9513 r = REAL_VALUE_NEGATE (r);
9514 fprintf (stream, "%s", fp_const_from_val (&r));
9519 if (GET_CODE (x) == CONST_INT)
9522 val = ARM_SIGN_EXTEND (~INTVAL (x));
9523 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val);
9528 output_addr_const (stream, x);
9533 fprintf (stream, "%s", arithmetic_instr (x, 1));
9536 /* Truncate Cirrus shift counts. */
9538 if (GET_CODE (x) == CONST_INT)
9540 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0x3f);
9543 arm_print_operand (stream, x, 0);
9547 fprintf (stream, "%s", arithmetic_instr (x, 0));
9553 const char * shift = shift_op (x, &val);
9557 fprintf (stream, ", %s ", shift_op (x, &val));
9559 arm_print_operand (stream, XEXP (x, 1), 0);
9561 fprintf (stream, "#" HOST_WIDE_INT_PRINT_DEC, val);
9566 /* An explanation of the 'Q', 'R' and 'H' register operands:
9568 In a pair of registers containing a DI or DF value the 'Q'
9569 operand returns the register number of the register containing
9570 the least significant part of the value. The 'R' operand returns
9571 the register number of the register containing the most
9572 significant part of the value.
9574 The 'H' operand returns the higher of the two register numbers.
9575 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
9576 same as the 'Q' operand, since the most significant part of the
9577 value is held in the lower number register. The reverse is true
9578 on systems where WORDS_BIG_ENDIAN is false.
9580 The purpose of these operands is to distinguish between cases
9581 where the endian-ness of the values is important (for example
9582 when they are added together), and cases where the endian-ness
9583 is irrelevant, but the order of register operations is important.
9584 For example when loading a value from memory into a register
9585 pair, the endian-ness does not matter. Provided that the value
9586 from the lower memory address is put into the lower numbered
9587 register, and the value from the higher address is put into the
9588 higher numbered register, the load will work regardless of whether
9589 the value being loaded is big-wordian or little-wordian. The
9590 order of the two register loads can matter however, if the address
9591 of the memory location is actually held in one of the registers
9592 being overwritten by the load. */
9594 if (REGNO (x) > LAST_ARM_REGNUM)
9596 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0));
9600 if (REGNO (x) > LAST_ARM_REGNUM)
9602 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1));
9606 if (REGNO (x) > LAST_ARM_REGNUM)
9608 asm_fprintf (stream, "%r", REGNO (x) + 1);
9612 asm_fprintf (stream, "%r",
9613 GET_CODE (XEXP (x, 0)) == REG
9614 ? REGNO (XEXP (x, 0)) : REGNO (XEXP (XEXP (x, 0), 0)));
9618 asm_fprintf (stream, "{%r-%r}",
9620 REGNO (x) + ARM_NUM_REGS (GET_MODE (x)) - 1);
9624 /* CONST_TRUE_RTX means always -- that's the default. */
9625 if (x == const_true_rtx)
9628 fputs (arm_condition_codes[get_arm_condition_code (x)],
9633 /* CONST_TRUE_RTX means not always -- ie never. We shouldn't ever
9635 if (x == const_true_rtx)
9638 fputs (arm_condition_codes[ARM_INVERSE_CONDITION_CODE
9639 (get_arm_condition_code (x))],
9643 /* Cirrus registers can be accessed in a variety of ways:
9644 single floating point (f)
9645 double floating point (d)
9647 64bit integer (dx). */
9648 case 'W': /* Cirrus register in F mode. */
9649 case 'X': /* Cirrus register in D mode. */
9650 case 'Y': /* Cirrus register in FX mode. */
9651 case 'Z': /* Cirrus register in DX mode. */
9652 if (GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) != CIRRUS_REGS)
9655 fprintf (stream, "mv%s%s",
9658 : code == 'Y' ? "fx" : "dx", reg_names[REGNO (x)] + 2);
9662 /* Print cirrus register in the mode specified by the register's mode. */
9665 int mode = GET_MODE (x);
9667 if (GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) != CIRRUS_REGS)
9670 fprintf (stream, "mv%s%s",
9671 mode == DFmode ? "d"
9672 : mode == SImode ? "fx"
9673 : mode == DImode ? "dx"
9674 : "f", reg_names[REGNO (x)] + 2);
9680 if (GET_CODE (x) != REG
9681 || REGNO (x) < FIRST_IWMMXT_GR_REGNUM
9682 || REGNO (x) > LAST_IWMMXT_GR_REGNUM)
9683 /* Bad value for wCG register number. */
9686 fprintf (stream, "%d", REGNO (x) - FIRST_IWMMXT_GR_REGNUM);
9689 /* Print an iWMMXt control register name. */
9691 if (GET_CODE (x) != CONST_INT
9693 || INTVAL (x) >= 16)
9694 /* Bad value for wC register number. */
9698 static const char * wc_reg_names [16] =
9700 "wCID", "wCon", "wCSSF", "wCASF",
9701 "wC4", "wC5", "wC6", "wC7",
9702 "wCGR0", "wCGR1", "wCGR2", "wCGR3",
9703 "wC12", "wC13", "wC14", "wC15"
9706 fprintf (stream, wc_reg_names [INTVAL (x)]);
9714 if (GET_CODE (x) == REG)
9715 asm_fprintf (stream, "%r", REGNO (x));
9716 else if (GET_CODE (x) == MEM)
9718 output_memory_reference_mode = GET_MODE (x);
9719 output_address (XEXP (x, 0));
9721 else if (GET_CODE (x) == CONST_DOUBLE)
9722 fprintf (stream, "#%s", fp_immediate_constant (x));
9723 else if (GET_CODE (x) == NEG)
9724 abort (); /* This should never happen now. */
9727 fputc ('#', stream);
9728 output_addr_const (stream, x);
9733 #ifndef AOF_ASSEMBLER
9734 /* Target hook for assembling integer objects. The ARM version needs to
9735 handle word-sized values specially. */
9737 arm_assemble_integer (rtx x, unsigned int size, int aligned_p)
9739 if (size == UNITS_PER_WORD && aligned_p)
9741 fputs ("\t.word\t", asm_out_file);
9742 output_addr_const (asm_out_file, x);
9744 /* Mark symbols as position independent. We only do this in the
9745 .text segment, not in the .data segment. */
9746 if (NEED_GOT_RELOC && flag_pic && making_const_table &&
9747 (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF))
9749 if (GET_CODE (x) == SYMBOL_REF
9750 && (CONSTANT_POOL_ADDRESS_P (x)
9751 || SYMBOL_REF_LOCAL_P (x)))
9752 fputs ("(GOTOFF)", asm_out_file);
9753 else if (GET_CODE (x) == LABEL_REF)
9754 fputs ("(GOTOFF)", asm_out_file);
9756 fputs ("(GOT)", asm_out_file);
9758 fputc ('\n', asm_out_file);
9762 if (VECTOR_MODE_SUPPORTED_P (GET_MODE (x)))
9766 if (GET_CODE (x) != CONST_VECTOR)
9769 units = CONST_VECTOR_NUNITS (x);
9771 switch (GET_MODE (x))
9773 case V2SImode: size = 4; break;
9774 case V4HImode: size = 2; break;
9775 case V8QImode: size = 1; break;
9780 for (i = 0; i < units; i++)
9784 elt = CONST_VECTOR_ELT (x, i);
9786 (elt, size, i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT, 1);
9792 return default_assemble_integer (x, size, aligned_p);
9796 /* A finite state machine takes care of noticing whether or not instructions
9797 can be conditionally executed, and thus decrease execution time and code
9798 size by deleting branch instructions. The fsm is controlled by
9799 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
9801 /* The state of the fsm controlling condition codes are:
9802 0: normal, do nothing special
9803 1: make ASM_OUTPUT_OPCODE not output this instruction
9804 2: make ASM_OUTPUT_OPCODE not output this instruction
9805 3: make instructions conditional
9806 4: make instructions conditional
9808 State transitions (state->state by whom under condition):
9809 0 -> 1 final_prescan_insn if the `target' is a label
9810 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
9811 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
9812 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
9813 3 -> 0 (*targetm.asm_out.internal_label) if the `target' label is reached
9814 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
9815 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
9816 (the target insn is arm_target_insn).
9818 If the jump clobbers the conditions then we use states 2 and 4.
9820 A similar thing can be done with conditional return insns.
9822 XXX In case the `target' is an unconditional branch, this conditionalising
9823 of the instructions always reduces code size, but not always execution
9824 time. But then, I want to reduce the code size to somewhere near what
9825 /bin/cc produces. */
9827 /* Returns the index of the ARM condition code string in
9828 `arm_condition_codes'. COMPARISON should be an rtx like
9829 `(eq (...) (...))'. */
9830 static enum arm_cond_code
9831 get_arm_condition_code (rtx comparison)
9833 enum machine_mode mode = GET_MODE (XEXP (comparison, 0));
9835 enum rtx_code comp_code = GET_CODE (comparison);
9837 if (GET_MODE_CLASS (mode) != MODE_CC)
9838 mode = SELECT_CC_MODE (comp_code, XEXP (comparison, 0),
9839 XEXP (comparison, 1));
9843 case CC_DNEmode: code = ARM_NE; goto dominance;
9844 case CC_DEQmode: code = ARM_EQ; goto dominance;
9845 case CC_DGEmode: code = ARM_GE; goto dominance;
9846 case CC_DGTmode: code = ARM_GT; goto dominance;
9847 case CC_DLEmode: code = ARM_LE; goto dominance;
9848 case CC_DLTmode: code = ARM_LT; goto dominance;
9849 case CC_DGEUmode: code = ARM_CS; goto dominance;
9850 case CC_DGTUmode: code = ARM_HI; goto dominance;
9851 case CC_DLEUmode: code = ARM_LS; goto dominance;
9852 case CC_DLTUmode: code = ARM_CC;
9855 if (comp_code != EQ && comp_code != NE)
9858 if (comp_code == EQ)
9859 return ARM_INVERSE_CONDITION_CODE (code);
9865 case NE: return ARM_NE;
9866 case EQ: return ARM_EQ;
9867 case GE: return ARM_PL;
9868 case LT: return ARM_MI;
9875 case NE: return ARM_NE;
9876 case EQ: return ARM_EQ;
9883 case NE: return ARM_MI;
9884 case EQ: return ARM_PL;
9890 /* These encodings assume that AC=1 in the FPA system control
9891 byte. This allows us to handle all cases except UNEQ and
9895 case GE: return ARM_GE;
9896 case GT: return ARM_GT;
9897 case LE: return ARM_LS;
9898 case LT: return ARM_MI;
9899 case NE: return ARM_NE;
9900 case EQ: return ARM_EQ;
9901 case ORDERED: return ARM_VC;
9902 case UNORDERED: return ARM_VS;
9903 case UNLT: return ARM_LT;
9904 case UNLE: return ARM_LE;
9905 case UNGT: return ARM_HI;
9906 case UNGE: return ARM_PL;
9907 /* UNEQ and LTGT do not have a representation. */
9908 case UNEQ: /* Fall through. */
9909 case LTGT: /* Fall through. */
9916 case NE: return ARM_NE;
9917 case EQ: return ARM_EQ;
9918 case GE: return ARM_LE;
9919 case GT: return ARM_LT;
9920 case LE: return ARM_GE;
9921 case LT: return ARM_GT;
9922 case GEU: return ARM_LS;
9923 case GTU: return ARM_CC;
9924 case LEU: return ARM_CS;
9925 case LTU: return ARM_HI;
9932 case LTU: return ARM_CS;
9933 case GEU: return ARM_CC;
9940 case NE: return ARM_NE;
9941 case EQ: return ARM_EQ;
9942 case GE: return ARM_GE;
9943 case GT: return ARM_GT;
9944 case LE: return ARM_LE;
9945 case LT: return ARM_LT;
9946 case GEU: return ARM_CS;
9947 case GTU: return ARM_HI;
9948 case LEU: return ARM_LS;
9949 case LTU: return ARM_CC;
9960 arm_final_prescan_insn (rtx insn)
9962 /* BODY will hold the body of INSN. */
9963 rtx body = PATTERN (insn);
9965 /* This will be 1 if trying to repeat the trick, and things need to be
9966 reversed if it appears to fail. */
9969 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
9970 taken are clobbered, even if the rtl suggests otherwise. It also
9971 means that we have to grub around within the jump expression to find
9972 out what the conditions are when the jump isn't taken. */
9973 int jump_clobbers = 0;
9975 /* If we start with a return insn, we only succeed if we find another one. */
9976 int seeking_return = 0;
9978 /* START_INSN will hold the insn from where we start looking. This is the
9979 first insn after the following code_label if REVERSE is true. */
9980 rtx start_insn = insn;
9982 /* If in state 4, check if the target branch is reached, in order to
9983 change back to state 0. */
9984 if (arm_ccfsm_state == 4)
9986 if (insn == arm_target_insn)
9988 arm_target_insn = NULL;
9989 arm_ccfsm_state = 0;
9994 /* If in state 3, it is possible to repeat the trick, if this insn is an
9995 unconditional branch to a label, and immediately following this branch
9996 is the previous target label which is only used once, and the label this
9997 branch jumps to is not too far off. */
9998 if (arm_ccfsm_state == 3)
10000 if (simplejump_p (insn))
10002 start_insn = next_nonnote_insn (start_insn);
10003 if (GET_CODE (start_insn) == BARRIER)
10005 /* XXX Isn't this always a barrier? */
10006 start_insn = next_nonnote_insn (start_insn);
10008 if (GET_CODE (start_insn) == CODE_LABEL
10009 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
10010 && LABEL_NUSES (start_insn) == 1)
10015 else if (GET_CODE (body) == RETURN)
10017 start_insn = next_nonnote_insn (start_insn);
10018 if (GET_CODE (start_insn) == BARRIER)
10019 start_insn = next_nonnote_insn (start_insn);
10020 if (GET_CODE (start_insn) == CODE_LABEL
10021 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
10022 && LABEL_NUSES (start_insn) == 1)
10025 seeking_return = 1;
10034 if (arm_ccfsm_state != 0 && !reverse)
10036 if (GET_CODE (insn) != JUMP_INSN)
10039 /* This jump might be paralleled with a clobber of the condition codes
10040 the jump should always come first */
10041 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
10042 body = XVECEXP (body, 0, 0);
10045 || (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
10046 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE))
10049 int fail = FALSE, succeed = FALSE;
10050 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
10051 int then_not_else = TRUE;
10052 rtx this_insn = start_insn, label = 0;
10054 /* If the jump cannot be done with one instruction, we cannot
10055 conditionally execute the instruction in the inverse case. */
10056 if (get_attr_conds (insn) == CONDS_JUMP_CLOB)
10062 /* Register the insn jumped to. */
10065 if (!seeking_return)
10066 label = XEXP (SET_SRC (body), 0);
10068 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == LABEL_REF)
10069 label = XEXP (XEXP (SET_SRC (body), 1), 0);
10070 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == LABEL_REF)
10072 label = XEXP (XEXP (SET_SRC (body), 2), 0);
10073 then_not_else = FALSE;
10075 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN)
10076 seeking_return = 1;
10077 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN)
10079 seeking_return = 1;
10080 then_not_else = FALSE;
10085 /* See how many insns this branch skips, and what kind of insns. If all
10086 insns are okay, and the label or unconditional branch to the same
10087 label is not too far away, succeed. */
10088 for (insns_skipped = 0;
10089 !fail && !succeed && insns_skipped++ < max_insns_skipped;)
10093 this_insn = next_nonnote_insn (this_insn);
10097 switch (GET_CODE (this_insn))
10100 /* Succeed if it is the target label, otherwise fail since
10101 control falls in from somewhere else. */
10102 if (this_insn == label)
10106 arm_ccfsm_state = 2;
10107 this_insn = next_nonnote_insn (this_insn);
10110 arm_ccfsm_state = 1;
10118 /* Succeed if the following insn is the target label.
10120 If return insns are used then the last insn in a function
10121 will be a barrier. */
10122 this_insn = next_nonnote_insn (this_insn);
10123 if (this_insn && this_insn == label)
10127 arm_ccfsm_state = 2;
10128 this_insn = next_nonnote_insn (this_insn);
10131 arm_ccfsm_state = 1;
10139 /* If using 32-bit addresses the cc is not preserved over
10141 if (TARGET_APCS_32)
10143 /* Succeed if the following insn is the target label,
10144 or if the following two insns are a barrier and
10145 the target label. */
10146 this_insn = next_nonnote_insn (this_insn);
10147 if (this_insn && GET_CODE (this_insn) == BARRIER)
10148 this_insn = next_nonnote_insn (this_insn);
10150 if (this_insn && this_insn == label
10151 && insns_skipped < max_insns_skipped)
10155 arm_ccfsm_state = 2;
10156 this_insn = next_nonnote_insn (this_insn);
10159 arm_ccfsm_state = 1;
10168 /* If this is an unconditional branch to the same label, succeed.
10169 If it is to another label, do nothing. If it is conditional,
10171 /* XXX Probably, the tests for SET and the PC are
10174 scanbody = PATTERN (this_insn);
10175 if (GET_CODE (scanbody) == SET
10176 && GET_CODE (SET_DEST (scanbody)) == PC)
10178 if (GET_CODE (SET_SRC (scanbody)) == LABEL_REF
10179 && XEXP (SET_SRC (scanbody), 0) == label && !reverse)
10181 arm_ccfsm_state = 2;
10184 else if (GET_CODE (SET_SRC (scanbody)) == IF_THEN_ELSE)
10187 /* Fail if a conditional return is undesirable (eg on a
10188 StrongARM), but still allow this if optimizing for size. */
10189 else if (GET_CODE (scanbody) == RETURN
10190 && !use_return_insn (TRUE)
10193 else if (GET_CODE (scanbody) == RETURN
10196 arm_ccfsm_state = 2;
10199 else if (GET_CODE (scanbody) == PARALLEL)
10201 switch (get_attr_conds (this_insn))
10211 fail = TRUE; /* Unrecognized jump (eg epilogue). */
10216 /* Instructions using or affecting the condition codes make it
10218 scanbody = PATTERN (this_insn);
10219 if (!(GET_CODE (scanbody) == SET
10220 || GET_CODE (scanbody) == PARALLEL)
10221 || get_attr_conds (this_insn) != CONDS_NOCOND)
10224 /* A conditional cirrus instruction must be followed by
10225 a non Cirrus instruction. However, since we
10226 conditionalize instructions in this function and by
10227 the time we get here we can't add instructions
10228 (nops), because shorten_branches() has already been
10229 called, we will disable conditionalizing Cirrus
10230 instructions to be safe. */
10231 if (GET_CODE (scanbody) != USE
10232 && GET_CODE (scanbody) != CLOBBER
10233 && get_attr_cirrus (this_insn) != CIRRUS_NOT)
10243 if ((!seeking_return) && (arm_ccfsm_state == 1 || reverse))
10244 arm_target_label = CODE_LABEL_NUMBER (label);
10245 else if (seeking_return || arm_ccfsm_state == 2)
10247 while (this_insn && GET_CODE (PATTERN (this_insn)) == USE)
10249 this_insn = next_nonnote_insn (this_insn);
10250 if (this_insn && (GET_CODE (this_insn) == BARRIER
10251 || GET_CODE (this_insn) == CODE_LABEL))
10256 /* Oh, dear! we ran off the end.. give up */
10257 recog (PATTERN (insn), insn, NULL);
10258 arm_ccfsm_state = 0;
10259 arm_target_insn = NULL;
10262 arm_target_insn = this_insn;
10271 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body),
10273 if (GET_CODE (XEXP (XEXP (SET_SRC (body), 0), 0)) == AND)
10274 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
10275 if (GET_CODE (XEXP (SET_SRC (body), 0)) == NE)
10276 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
10280 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
10283 arm_current_cc = get_arm_condition_code (XEXP (SET_SRC (body),
10287 if (reverse || then_not_else)
10288 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
10291 /* Restore recog_data (getting the attributes of other insns can
10292 destroy this array, but final.c assumes that it remains intact
10293 across this call; since the insn has been recognized already we
10294 call recog direct). */
10295 recog (PATTERN (insn), insn, NULL);
10299 /* Returns true if REGNO is a valid register
10300 for holding a quantity of tyoe MODE. */
10302 arm_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
10304 if (GET_MODE_CLASS (mode) == MODE_CC)
10305 return regno == CC_REGNUM;
10308 /* For the Thumb we only allow values bigger than SImode in
10309 registers 0 - 6, so that there is always a second low
10310 register available to hold the upper part of the value.
10311 We probably we ought to ensure that the register is the
10312 start of an even numbered register pair. */
10313 return (ARM_NUM_REGS (mode) < 2) || (regno < LAST_LO_REGNUM);
10315 if (IS_CIRRUS_REGNUM (regno))
10316 /* We have outlawed SI values in Cirrus registers because they
10317 reside in the lower 32 bits, but SF values reside in the
10318 upper 32 bits. This causes gcc all sorts of grief. We can't
10319 even split the registers into pairs because Cirrus SI values
10320 get sign extended to 64bits-- aldyh. */
10321 return (GET_MODE_CLASS (mode) == MODE_FLOAT) || (mode == DImode);
10323 if (IS_IWMMXT_GR_REGNUM (regno))
10324 return mode == SImode;
10326 if (IS_IWMMXT_REGNUM (regno))
10327 return VALID_IWMMXT_REG_MODE (mode);
10329 if (regno <= LAST_ARM_REGNUM)
10330 /* We allow any value to be stored in the general registers. */
10333 if ( regno == FRAME_POINTER_REGNUM
10334 || regno == ARG_POINTER_REGNUM)
10335 /* We only allow integers in the fake hard registers. */
10336 return GET_MODE_CLASS (mode) == MODE_INT;
10338 /* The only registers left are the FPA registers
10339 which we only allow to hold FP values. */
10340 return GET_MODE_CLASS (mode) == MODE_FLOAT
10341 && regno >= FIRST_ARM_FP_REGNUM
10342 && regno <= LAST_ARM_FP_REGNUM;
10346 arm_regno_class (int regno)
10350 if (regno == STACK_POINTER_REGNUM)
10352 if (regno == CC_REGNUM)
10359 if ( regno <= LAST_ARM_REGNUM
10360 || regno == FRAME_POINTER_REGNUM
10361 || regno == ARG_POINTER_REGNUM)
10362 return GENERAL_REGS;
10364 if (regno == CC_REGNUM)
10367 if (IS_CIRRUS_REGNUM (regno))
10368 return CIRRUS_REGS;
10370 if (IS_IWMMXT_REGNUM (regno))
10371 return IWMMXT_REGS;
10373 if (IS_IWMMXT_GR_REGNUM (regno))
10374 return IWMMXT_GR_REGS;
10379 /* Handle a special case when computing the offset
10380 of an argument from the frame pointer. */
10382 arm_debugger_arg_offset (int value, rtx addr)
10386 /* We are only interested if dbxout_parms() failed to compute the offset. */
10390 /* We can only cope with the case where the address is held in a register. */
10391 if (GET_CODE (addr) != REG)
10394 /* If we are using the frame pointer to point at the argument, then
10395 an offset of 0 is correct. */
10396 if (REGNO (addr) == (unsigned) HARD_FRAME_POINTER_REGNUM)
10399 /* If we are using the stack pointer to point at the
10400 argument, then an offset of 0 is correct. */
10401 if ((TARGET_THUMB || !frame_pointer_needed)
10402 && REGNO (addr) == SP_REGNUM)
10405 /* Oh dear. The argument is pointed to by a register rather
10406 than being held in a register, or being stored at a known
10407 offset from the frame pointer. Since GDB only understands
10408 those two kinds of argument we must translate the address
10409 held in the register into an offset from the frame pointer.
10410 We do this by searching through the insns for the function
10411 looking to see where this register gets its value. If the
10412 register is initialized from the frame pointer plus an offset
10413 then we are in luck and we can continue, otherwise we give up.
10415 This code is exercised by producing debugging information
10416 for a function with arguments like this:
10418 double func (double a, double b, int c, double d) {return d;}
10420 Without this code the stab for parameter 'd' will be set to
10421 an offset of 0 from the frame pointer, rather than 8. */
10423 /* The if() statement says:
10425 If the insn is a normal instruction
10426 and if the insn is setting the value in a register
10427 and if the register being set is the register holding the address of the argument
10428 and if the address is computing by an addition
10429 that involves adding to a register
10430 which is the frame pointer
10435 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
10437 if ( GET_CODE (insn) == INSN
10438 && GET_CODE (PATTERN (insn)) == SET
10439 && REGNO (XEXP (PATTERN (insn), 0)) == REGNO (addr)
10440 && GET_CODE (XEXP (PATTERN (insn), 1)) == PLUS
10441 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 0)) == REG
10442 && REGNO (XEXP (XEXP (PATTERN (insn), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
10443 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 1)) == CONST_INT
10446 value = INTVAL (XEXP (XEXP (PATTERN (insn), 1), 1));
10455 warning ("unable to compute real location of stacked parameter");
10456 value = 8; /* XXX magic hack */
10462 #define def_mbuiltin(MASK, NAME, TYPE, CODE) \
10465 if ((MASK) & insn_flags) \
10466 builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, NULL, NULL_TREE); \
10470 struct builtin_description
10472 const unsigned int mask;
10473 const enum insn_code icode;
10474 const char * const name;
10475 const enum arm_builtins code;
10476 const enum rtx_code comparison;
10477 const unsigned int flag;
10480 static const struct builtin_description bdesc_2arg[] =
10482 #define IWMMXT_BUILTIN(code, string, builtin) \
10483 { FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \
10484 ARM_BUILTIN_##builtin, 0, 0 },
10486 IWMMXT_BUILTIN (addv8qi3, "waddb", WADDB)
10487 IWMMXT_BUILTIN (addv4hi3, "waddh", WADDH)
10488 IWMMXT_BUILTIN (addv2si3, "waddw", WADDW)
10489 IWMMXT_BUILTIN (subv8qi3, "wsubb", WSUBB)
10490 IWMMXT_BUILTIN (subv4hi3, "wsubh", WSUBH)
10491 IWMMXT_BUILTIN (subv2si3, "wsubw", WSUBW)
10492 IWMMXT_BUILTIN (ssaddv8qi3, "waddbss", WADDSSB)
10493 IWMMXT_BUILTIN (ssaddv4hi3, "waddhss", WADDSSH)
10494 IWMMXT_BUILTIN (ssaddv2si3, "waddwss", WADDSSW)
10495 IWMMXT_BUILTIN (sssubv8qi3, "wsubbss", WSUBSSB)
10496 IWMMXT_BUILTIN (sssubv4hi3, "wsubhss", WSUBSSH)
10497 IWMMXT_BUILTIN (sssubv2si3, "wsubwss", WSUBSSW)
10498 IWMMXT_BUILTIN (usaddv8qi3, "waddbus", WADDUSB)
10499 IWMMXT_BUILTIN (usaddv4hi3, "waddhus", WADDUSH)
10500 IWMMXT_BUILTIN (usaddv2si3, "waddwus", WADDUSW)
10501 IWMMXT_BUILTIN (ussubv8qi3, "wsubbus", WSUBUSB)
10502 IWMMXT_BUILTIN (ussubv4hi3, "wsubhus", WSUBUSH)
10503 IWMMXT_BUILTIN (ussubv2si3, "wsubwus", WSUBUSW)
10504 IWMMXT_BUILTIN (mulv4hi3, "wmulul", WMULUL)
10505 IWMMXT_BUILTIN (smulv4hi3_highpart, "wmulsh", WMULSH)
10506 IWMMXT_BUILTIN (umulv4hi3_highpart, "wmuluh", WMULUH)
10507 IWMMXT_BUILTIN (eqv8qi3, "wcmpeqb", WCMPEQB)
10508 IWMMXT_BUILTIN (eqv4hi3, "wcmpeqh", WCMPEQH)
10509 IWMMXT_BUILTIN (eqv2si3, "wcmpeqw", WCMPEQW)
10510 IWMMXT_BUILTIN (gtuv8qi3, "wcmpgtub", WCMPGTUB)
10511 IWMMXT_BUILTIN (gtuv4hi3, "wcmpgtuh", WCMPGTUH)
10512 IWMMXT_BUILTIN (gtuv2si3, "wcmpgtuw", WCMPGTUW)
10513 IWMMXT_BUILTIN (gtv8qi3, "wcmpgtsb", WCMPGTSB)
10514 IWMMXT_BUILTIN (gtv4hi3, "wcmpgtsh", WCMPGTSH)
10515 IWMMXT_BUILTIN (gtv2si3, "wcmpgtsw", WCMPGTSW)
10516 IWMMXT_BUILTIN (umaxv8qi3, "wmaxub", WMAXUB)
10517 IWMMXT_BUILTIN (smaxv8qi3, "wmaxsb", WMAXSB)
10518 IWMMXT_BUILTIN (umaxv4hi3, "wmaxuh", WMAXUH)
10519 IWMMXT_BUILTIN (smaxv4hi3, "wmaxsh", WMAXSH)
10520 IWMMXT_BUILTIN (umaxv2si3, "wmaxuw", WMAXUW)
10521 IWMMXT_BUILTIN (smaxv2si3, "wmaxsw", WMAXSW)
10522 IWMMXT_BUILTIN (uminv8qi3, "wminub", WMINUB)
10523 IWMMXT_BUILTIN (sminv8qi3, "wminsb", WMINSB)
10524 IWMMXT_BUILTIN (uminv4hi3, "wminuh", WMINUH)
10525 IWMMXT_BUILTIN (sminv4hi3, "wminsh", WMINSH)
10526 IWMMXT_BUILTIN (uminv2si3, "wminuw", WMINUW)
10527 IWMMXT_BUILTIN (sminv2si3, "wminsw", WMINSW)
10528 IWMMXT_BUILTIN (iwmmxt_anddi3, "wand", WAND)
10529 IWMMXT_BUILTIN (iwmmxt_nanddi3, "wandn", WANDN)
10530 IWMMXT_BUILTIN (iwmmxt_iordi3, "wor", WOR)
10531 IWMMXT_BUILTIN (iwmmxt_xordi3, "wxor", WXOR)
10532 IWMMXT_BUILTIN (iwmmxt_uavgv8qi3, "wavg2b", WAVG2B)
10533 IWMMXT_BUILTIN (iwmmxt_uavgv4hi3, "wavg2h", WAVG2H)
10534 IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3, "wavg2br", WAVG2BR)
10535 IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3, "wavg2hr", WAVG2HR)
10536 IWMMXT_BUILTIN (iwmmxt_wunpckilb, "wunpckilb", WUNPCKILB)
10537 IWMMXT_BUILTIN (iwmmxt_wunpckilh, "wunpckilh", WUNPCKILH)
10538 IWMMXT_BUILTIN (iwmmxt_wunpckilw, "wunpckilw", WUNPCKILW)
10539 IWMMXT_BUILTIN (iwmmxt_wunpckihb, "wunpckihb", WUNPCKIHB)
10540 IWMMXT_BUILTIN (iwmmxt_wunpckihh, "wunpckihh", WUNPCKIHH)
10541 IWMMXT_BUILTIN (iwmmxt_wunpckihw, "wunpckihw", WUNPCKIHW)
10542 IWMMXT_BUILTIN (iwmmxt_wmadds, "wmadds", WMADDS)
10543 IWMMXT_BUILTIN (iwmmxt_wmaddu, "wmaddu", WMADDU)
10545 #define IWMMXT_BUILTIN2(code, builtin) \
10546 { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, 0, 0 },
10548 IWMMXT_BUILTIN2 (iwmmxt_wpackhss, WPACKHSS)
10549 IWMMXT_BUILTIN2 (iwmmxt_wpackwss, WPACKWSS)
10550 IWMMXT_BUILTIN2 (iwmmxt_wpackdss, WPACKDSS)
10551 IWMMXT_BUILTIN2 (iwmmxt_wpackhus, WPACKHUS)
10552 IWMMXT_BUILTIN2 (iwmmxt_wpackwus, WPACKWUS)
10553 IWMMXT_BUILTIN2 (iwmmxt_wpackdus, WPACKDUS)
10554 IWMMXT_BUILTIN2 (ashlv4hi3_di, WSLLH)
10555 IWMMXT_BUILTIN2 (ashlv4hi3, WSLLHI)
10556 IWMMXT_BUILTIN2 (ashlv2si3_di, WSLLW)
10557 IWMMXT_BUILTIN2 (ashlv2si3, WSLLWI)
10558 IWMMXT_BUILTIN2 (ashldi3_di, WSLLD)
10559 IWMMXT_BUILTIN2 (ashldi3_iwmmxt, WSLLDI)
10560 IWMMXT_BUILTIN2 (lshrv4hi3_di, WSRLH)
10561 IWMMXT_BUILTIN2 (lshrv4hi3, WSRLHI)
10562 IWMMXT_BUILTIN2 (lshrv2si3_di, WSRLW)
10563 IWMMXT_BUILTIN2 (lshrv2si3, WSRLWI)
10564 IWMMXT_BUILTIN2 (lshrdi3_di, WSRLD)
10565 IWMMXT_BUILTIN2 (lshrdi3, WSRLDI)
10566 IWMMXT_BUILTIN2 (ashrv4hi3_di, WSRAH)
10567 IWMMXT_BUILTIN2 (ashrv4hi3, WSRAHI)
10568 IWMMXT_BUILTIN2 (ashrv2si3_di, WSRAW)
10569 IWMMXT_BUILTIN2 (ashrv2si3, WSRAWI)
10570 IWMMXT_BUILTIN2 (ashrdi3_di, WSRAD)
10571 IWMMXT_BUILTIN2 (ashrdi3, WSRADI)
10572 IWMMXT_BUILTIN2 (rorv4hi3_di, WRORH)
10573 IWMMXT_BUILTIN2 (rorv4hi3, WRORHI)
10574 IWMMXT_BUILTIN2 (rorv2si3_di, WRORW)
10575 IWMMXT_BUILTIN2 (rorv2si3, WRORWI)
10576 IWMMXT_BUILTIN2 (rordi3_di, WRORD)
10577 IWMMXT_BUILTIN2 (rordi3, WRORDI)
10578 IWMMXT_BUILTIN2 (iwmmxt_wmacuz, WMACUZ)
10579 IWMMXT_BUILTIN2 (iwmmxt_wmacsz, WMACSZ)
10582 static const struct builtin_description bdesc_1arg[] =
10584 IWMMXT_BUILTIN (iwmmxt_tmovmskb, "tmovmskb", TMOVMSKB)
10585 IWMMXT_BUILTIN (iwmmxt_tmovmskh, "tmovmskh", TMOVMSKH)
10586 IWMMXT_BUILTIN (iwmmxt_tmovmskw, "tmovmskw", TMOVMSKW)
10587 IWMMXT_BUILTIN (iwmmxt_waccb, "waccb", WACCB)
10588 IWMMXT_BUILTIN (iwmmxt_wacch, "wacch", WACCH)
10589 IWMMXT_BUILTIN (iwmmxt_waccw, "waccw", WACCW)
10590 IWMMXT_BUILTIN (iwmmxt_wunpckehub, "wunpckehub", WUNPCKEHUB)
10591 IWMMXT_BUILTIN (iwmmxt_wunpckehuh, "wunpckehuh", WUNPCKEHUH)
10592 IWMMXT_BUILTIN (iwmmxt_wunpckehuw, "wunpckehuw", WUNPCKEHUW)
10593 IWMMXT_BUILTIN (iwmmxt_wunpckehsb, "wunpckehsb", WUNPCKEHSB)
10594 IWMMXT_BUILTIN (iwmmxt_wunpckehsh, "wunpckehsh", WUNPCKEHSH)
10595 IWMMXT_BUILTIN (iwmmxt_wunpckehsw, "wunpckehsw", WUNPCKEHSW)
10596 IWMMXT_BUILTIN (iwmmxt_wunpckelub, "wunpckelub", WUNPCKELUB)
10597 IWMMXT_BUILTIN (iwmmxt_wunpckeluh, "wunpckeluh", WUNPCKELUH)
10598 IWMMXT_BUILTIN (iwmmxt_wunpckeluw, "wunpckeluw", WUNPCKELUW)
10599 IWMMXT_BUILTIN (iwmmxt_wunpckelsb, "wunpckelsb", WUNPCKELSB)
10600 IWMMXT_BUILTIN (iwmmxt_wunpckelsh, "wunpckelsh", WUNPCKELSH)
10601 IWMMXT_BUILTIN (iwmmxt_wunpckelsw, "wunpckelsw", WUNPCKELSW)
10604 /* Set up all the iWMMXt builtins. This is
10605 not called if TARGET_IWMMXT is zero. */
10608 arm_init_iwmmxt_builtins (void)
10610 const struct builtin_description * d;
10612 tree endlink = void_list_node;
10615 = build_function_type (integer_type_node,
10616 tree_cons (NULL_TREE, integer_type_node, endlink));
10617 tree v8qi_ftype_v8qi_v8qi_int
10618 = build_function_type (V8QI_type_node,
10619 tree_cons (NULL_TREE, V8QI_type_node,
10620 tree_cons (NULL_TREE, V8QI_type_node,
10621 tree_cons (NULL_TREE,
10624 tree v4hi_ftype_v4hi_int
10625 = build_function_type (V4HI_type_node,
10626 tree_cons (NULL_TREE, V4HI_type_node,
10627 tree_cons (NULL_TREE, integer_type_node,
10629 tree v2si_ftype_v2si_int
10630 = build_function_type (V2SI_type_node,
10631 tree_cons (NULL_TREE, V2SI_type_node,
10632 tree_cons (NULL_TREE, integer_type_node,
10634 tree v2si_ftype_di_di
10635 = build_function_type (V2SI_type_node,
10636 tree_cons (NULL_TREE, long_long_integer_type_node,
10637 tree_cons (NULL_TREE, long_long_integer_type_node,
10639 tree di_ftype_di_int
10640 = build_function_type (long_long_integer_type_node,
10641 tree_cons (NULL_TREE, long_long_integer_type_node,
10642 tree_cons (NULL_TREE, integer_type_node,
10644 tree di_ftype_di_int_int
10645 = build_function_type (long_long_integer_type_node,
10646 tree_cons (NULL_TREE, long_long_integer_type_node,
10647 tree_cons (NULL_TREE, integer_type_node,
10648 tree_cons (NULL_TREE,
10651 tree int_ftype_v8qi
10652 = build_function_type (integer_type_node,
10653 tree_cons (NULL_TREE, V8QI_type_node,
10655 tree int_ftype_v4hi
10656 = build_function_type (integer_type_node,
10657 tree_cons (NULL_TREE, V4HI_type_node,
10659 tree int_ftype_v2si
10660 = build_function_type (integer_type_node,
10661 tree_cons (NULL_TREE, V2SI_type_node,
10663 tree int_ftype_v8qi_int
10664 = build_function_type (integer_type_node,
10665 tree_cons (NULL_TREE, V8QI_type_node,
10666 tree_cons (NULL_TREE, integer_type_node,
10668 tree int_ftype_v4hi_int
10669 = build_function_type (integer_type_node,
10670 tree_cons (NULL_TREE, V4HI_type_node,
10671 tree_cons (NULL_TREE, integer_type_node,
10673 tree int_ftype_v2si_int
10674 = build_function_type (integer_type_node,
10675 tree_cons (NULL_TREE, V2SI_type_node,
10676 tree_cons (NULL_TREE, integer_type_node,
10678 tree v8qi_ftype_v8qi_int_int
10679 = build_function_type (V8QI_type_node,
10680 tree_cons (NULL_TREE, V8QI_type_node,
10681 tree_cons (NULL_TREE, integer_type_node,
10682 tree_cons (NULL_TREE,
10685 tree v4hi_ftype_v4hi_int_int
10686 = build_function_type (V4HI_type_node,
10687 tree_cons (NULL_TREE, V4HI_type_node,
10688 tree_cons (NULL_TREE, integer_type_node,
10689 tree_cons (NULL_TREE,
10692 tree v2si_ftype_v2si_int_int
10693 = build_function_type (V2SI_type_node,
10694 tree_cons (NULL_TREE, V2SI_type_node,
10695 tree_cons (NULL_TREE, integer_type_node,
10696 tree_cons (NULL_TREE,
10699 /* Miscellaneous. */
10700 tree v8qi_ftype_v4hi_v4hi
10701 = build_function_type (V8QI_type_node,
10702 tree_cons (NULL_TREE, V4HI_type_node,
10703 tree_cons (NULL_TREE, V4HI_type_node,
10705 tree v4hi_ftype_v2si_v2si
10706 = build_function_type (V4HI_type_node,
10707 tree_cons (NULL_TREE, V2SI_type_node,
10708 tree_cons (NULL_TREE, V2SI_type_node,
10710 tree v2si_ftype_v4hi_v4hi
10711 = build_function_type (V2SI_type_node,
10712 tree_cons (NULL_TREE, V4HI_type_node,
10713 tree_cons (NULL_TREE, V4HI_type_node,
10715 tree v2si_ftype_v8qi_v8qi
10716 = build_function_type (V2SI_type_node,
10717 tree_cons (NULL_TREE, V8QI_type_node,
10718 tree_cons (NULL_TREE, V8QI_type_node,
10720 tree v4hi_ftype_v4hi_di
10721 = build_function_type (V4HI_type_node,
10722 tree_cons (NULL_TREE, V4HI_type_node,
10723 tree_cons (NULL_TREE,
10724 long_long_integer_type_node,
10726 tree v2si_ftype_v2si_di
10727 = build_function_type (V2SI_type_node,
10728 tree_cons (NULL_TREE, V2SI_type_node,
10729 tree_cons (NULL_TREE,
10730 long_long_integer_type_node,
10732 tree void_ftype_int_int
10733 = build_function_type (void_type_node,
10734 tree_cons (NULL_TREE, integer_type_node,
10735 tree_cons (NULL_TREE, integer_type_node,
10738 = build_function_type (long_long_unsigned_type_node, endlink);
10740 = build_function_type (long_long_integer_type_node,
10741 tree_cons (NULL_TREE, V8QI_type_node,
10744 = build_function_type (long_long_integer_type_node,
10745 tree_cons (NULL_TREE, V4HI_type_node,
10748 = build_function_type (long_long_integer_type_node,
10749 tree_cons (NULL_TREE, V2SI_type_node,
10751 tree v2si_ftype_v4hi
10752 = build_function_type (V2SI_type_node,
10753 tree_cons (NULL_TREE, V4HI_type_node,
10755 tree v4hi_ftype_v8qi
10756 = build_function_type (V4HI_type_node,
10757 tree_cons (NULL_TREE, V8QI_type_node,
10760 tree di_ftype_di_v4hi_v4hi
10761 = build_function_type (long_long_unsigned_type_node,
10762 tree_cons (NULL_TREE,
10763 long_long_unsigned_type_node,
10764 tree_cons (NULL_TREE, V4HI_type_node,
10765 tree_cons (NULL_TREE,
10769 tree di_ftype_v4hi_v4hi
10770 = build_function_type (long_long_unsigned_type_node,
10771 tree_cons (NULL_TREE, V4HI_type_node,
10772 tree_cons (NULL_TREE, V4HI_type_node,
10775 /* Normal vector binops. */
10776 tree v8qi_ftype_v8qi_v8qi
10777 = build_function_type (V8QI_type_node,
10778 tree_cons (NULL_TREE, V8QI_type_node,
10779 tree_cons (NULL_TREE, V8QI_type_node,
10781 tree v4hi_ftype_v4hi_v4hi
10782 = build_function_type (V4HI_type_node,
10783 tree_cons (NULL_TREE, V4HI_type_node,
10784 tree_cons (NULL_TREE, V4HI_type_node,
10786 tree v2si_ftype_v2si_v2si
10787 = build_function_type (V2SI_type_node,
10788 tree_cons (NULL_TREE, V2SI_type_node,
10789 tree_cons (NULL_TREE, V2SI_type_node,
10791 tree di_ftype_di_di
10792 = build_function_type (long_long_unsigned_type_node,
10793 tree_cons (NULL_TREE, long_long_unsigned_type_node,
10794 tree_cons (NULL_TREE,
10795 long_long_unsigned_type_node,
10798 /* Add all builtins that are more or less simple operations on two
10800 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
10802 /* Use one of the operands; the target can have a different mode for
10803 mask-generating compares. */
10804 enum machine_mode mode;
10810 mode = insn_data[d->icode].operand[1].mode;
10815 type = v8qi_ftype_v8qi_v8qi;
10818 type = v4hi_ftype_v4hi_v4hi;
10821 type = v2si_ftype_v2si_v2si;
10824 type = di_ftype_di_di;
10831 def_mbuiltin (d->mask, d->name, type, d->code);
10834 /* Add the remaining MMX insns with somewhat more complicated types. */
10835 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wzero", di_ftype_void, ARM_BUILTIN_WZERO);
10836 def_mbuiltin (FL_IWMMXT, "__builtin_arm_setwcx", void_ftype_int_int, ARM_BUILTIN_SETWCX);
10837 def_mbuiltin (FL_IWMMXT, "__builtin_arm_getwcx", int_ftype_int, ARM_BUILTIN_GETWCX);
10839 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSLLH);
10840 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllw", v2si_ftype_v2si_di, ARM_BUILTIN_WSLLW);
10841 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslld", di_ftype_di_di, ARM_BUILTIN_WSLLD);
10842 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSLLHI);
10843 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSLLWI);
10844 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslldi", di_ftype_di_int, ARM_BUILTIN_WSLLDI);
10846 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRLH);
10847 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRLW);
10848 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrld", di_ftype_di_di, ARM_BUILTIN_WSRLD);
10849 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRLHI);
10850 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRLWI);
10851 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrldi", di_ftype_di_int, ARM_BUILTIN_WSRLDI);
10853 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrah", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRAH);
10854 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsraw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRAW);
10855 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrad", di_ftype_di_di, ARM_BUILTIN_WSRAD);
10856 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrahi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRAHI);
10857 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrawi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRAWI);
10858 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsradi", di_ftype_di_int, ARM_BUILTIN_WSRADI);
10860 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WRORH);
10861 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorw", v2si_ftype_v2si_di, ARM_BUILTIN_WRORW);
10862 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrord", di_ftype_di_di, ARM_BUILTIN_WRORD);
10863 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WRORHI);
10864 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorwi", v2si_ftype_v2si_int, ARM_BUILTIN_WRORWI);
10865 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrordi", di_ftype_di_int, ARM_BUILTIN_WRORDI);
10867 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wshufh", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSHUFH);
10869 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadb", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADB);
10870 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadh", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADH);
10871 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadbz", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADBZ);
10872 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadhz", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADHZ);
10874 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsb", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMSB);
10875 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMSH);
10876 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMSW);
10877 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmub", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMUB);
10878 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMUH);
10879 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMUW);
10880 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrb", v8qi_ftype_v8qi_int_int, ARM_BUILTIN_TINSRB);
10881 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrh", v4hi_ftype_v4hi_int_int, ARM_BUILTIN_TINSRH);
10882 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrw", v2si_ftype_v2si_int_int, ARM_BUILTIN_TINSRW);
10884 def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccb", di_ftype_v8qi, ARM_BUILTIN_WACCB);
10885 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wacch", di_ftype_v4hi, ARM_BUILTIN_WACCH);
10886 def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccw", di_ftype_v2si, ARM_BUILTIN_WACCW);
10888 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskb", int_ftype_v8qi, ARM_BUILTIN_TMOVMSKB);
10889 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskh", int_ftype_v4hi, ARM_BUILTIN_TMOVMSKH);
10890 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskw", int_ftype_v2si, ARM_BUILTIN_TMOVMSKW);
10892 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhss", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHSS);
10893 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhus", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHUS);
10894 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwus", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWUS);
10895 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwss", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWSS);
10896 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdus", v2si_ftype_di_di, ARM_BUILTIN_WPACKDUS);
10897 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdss", v2si_ftype_di_di, ARM_BUILTIN_WPACKDSS);
10899 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHUB);
10900 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHUH);
10901 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHUW);
10902 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHSB);
10903 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHSH);
10904 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHSW);
10905 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELUB);
10906 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELUH);
10907 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELUW);
10908 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELSB);
10909 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELSH);
10910 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELSW);
10912 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacs", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACS);
10913 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacsz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACSZ);
10914 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacu", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACU);
10915 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacuz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACUZ);
10917 def_mbuiltin (FL_IWMMXT, "__builtin_arm_walign", v8qi_ftype_v8qi_v8qi_int, ARM_BUILTIN_WALIGN);
10918 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmia", di_ftype_di_int_int, ARM_BUILTIN_TMIA);
10919 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiaph", di_ftype_di_int_int, ARM_BUILTIN_TMIAPH);
10920 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabb", di_ftype_di_int_int, ARM_BUILTIN_TMIABB);
10921 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabt", di_ftype_di_int_int, ARM_BUILTIN_TMIABT);
10922 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatb", di_ftype_di_int_int, ARM_BUILTIN_TMIATB);
10923 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatt", di_ftype_di_int_int, ARM_BUILTIN_TMIATT);
10927 arm_init_builtins (void)
10929 if (TARGET_REALLY_IWMMXT)
10930 arm_init_iwmmxt_builtins ();
10933 /* Errors in the source file can cause expand_expr to return const0_rtx
10934 where we expect a vector. To avoid crashing, use one of the vector
10935 clear instructions. */
10938 safe_vector_operand (rtx x, enum machine_mode mode)
10940 if (x != const0_rtx)
10942 x = gen_reg_rtx (mode);
10944 emit_insn (gen_iwmmxt_clrdi (mode == DImode ? x
10945 : gen_rtx_SUBREG (DImode, x, 0)));
10949 /* Subroutine of arm_expand_builtin to take care of binop insns. */
10952 arm_expand_binop_builtin (enum insn_code icode,
10953 tree arglist, rtx target)
10956 tree arg0 = TREE_VALUE (arglist);
10957 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
10958 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
10959 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
10960 enum machine_mode tmode = insn_data[icode].operand[0].mode;
10961 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
10962 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
10964 if (VECTOR_MODE_P (mode0))
10965 op0 = safe_vector_operand (op0, mode0);
10966 if (VECTOR_MODE_P (mode1))
10967 op1 = safe_vector_operand (op1, mode1);
10970 || GET_MODE (target) != tmode
10971 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
10972 target = gen_reg_rtx (tmode);
10974 /* In case the insn wants input operands in modes different from
10975 the result, abort. */
10976 if (GET_MODE (op0) != mode0 || GET_MODE (op1) != mode1)
10979 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
10980 op0 = copy_to_mode_reg (mode0, op0);
10981 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
10982 op1 = copy_to_mode_reg (mode1, op1);
10984 pat = GEN_FCN (icode) (target, op0, op1);
10991 /* Subroutine of arm_expand_builtin to take care of unop insns. */
10994 arm_expand_unop_builtin (enum insn_code icode,
10995 tree arglist, rtx target, int do_load)
10998 tree arg0 = TREE_VALUE (arglist);
10999 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
11000 enum machine_mode tmode = insn_data[icode].operand[0].mode;
11001 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
11004 || GET_MODE (target) != tmode
11005 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
11006 target = gen_reg_rtx (tmode);
11008 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
11011 if (VECTOR_MODE_P (mode0))
11012 op0 = safe_vector_operand (op0, mode0);
11014 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
11015 op0 = copy_to_mode_reg (mode0, op0);
11018 pat = GEN_FCN (icode) (target, op0);
11025 /* Expand an expression EXP that calls a built-in function,
11026 with result going to TARGET if that's convenient
11027 (and in mode MODE if that's convenient).
11028 SUBTARGET may be used as the target for computing one of EXP's operands.
11029 IGNORE is nonzero if the value is to be ignored. */
11032 arm_expand_builtin (tree exp,
11034 rtx subtarget ATTRIBUTE_UNUSED,
11035 enum machine_mode mode ATTRIBUTE_UNUSED,
11036 int ignore ATTRIBUTE_UNUSED)
11038 const struct builtin_description * d;
11039 enum insn_code icode;
11040 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
11041 tree arglist = TREE_OPERAND (exp, 1);
11049 int fcode = DECL_FUNCTION_CODE (fndecl);
11051 enum machine_mode tmode;
11052 enum machine_mode mode0;
11053 enum machine_mode mode1;
11054 enum machine_mode mode2;
11058 case ARM_BUILTIN_TEXTRMSB:
11059 case ARM_BUILTIN_TEXTRMUB:
11060 case ARM_BUILTIN_TEXTRMSH:
11061 case ARM_BUILTIN_TEXTRMUH:
11062 case ARM_BUILTIN_TEXTRMSW:
11063 case ARM_BUILTIN_TEXTRMUW:
11064 icode = (fcode == ARM_BUILTIN_TEXTRMSB ? CODE_FOR_iwmmxt_textrmsb
11065 : fcode == ARM_BUILTIN_TEXTRMUB ? CODE_FOR_iwmmxt_textrmub
11066 : fcode == ARM_BUILTIN_TEXTRMSH ? CODE_FOR_iwmmxt_textrmsh
11067 : fcode == ARM_BUILTIN_TEXTRMUH ? CODE_FOR_iwmmxt_textrmuh
11068 : CODE_FOR_iwmmxt_textrmw);
11070 arg0 = TREE_VALUE (arglist);
11071 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
11072 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
11073 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
11074 tmode = insn_data[icode].operand[0].mode;
11075 mode0 = insn_data[icode].operand[1].mode;
11076 mode1 = insn_data[icode].operand[2].mode;
11078 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
11079 op0 = copy_to_mode_reg (mode0, op0);
11080 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
11082 /* @@@ better error message */
11083 error ("selector must be an immediate");
11084 return gen_reg_rtx (tmode);
11087 || GET_MODE (target) != tmode
11088 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
11089 target = gen_reg_rtx (tmode);
11090 pat = GEN_FCN (icode) (target, op0, op1);
11096 case ARM_BUILTIN_TINSRB:
11097 case ARM_BUILTIN_TINSRH:
11098 case ARM_BUILTIN_TINSRW:
11099 icode = (fcode == ARM_BUILTIN_TINSRB ? CODE_FOR_iwmmxt_tinsrb
11100 : fcode == ARM_BUILTIN_TINSRH ? CODE_FOR_iwmmxt_tinsrh
11101 : CODE_FOR_iwmmxt_tinsrw);
11102 arg0 = TREE_VALUE (arglist);
11103 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
11104 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
11105 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
11106 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
11107 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
11108 tmode = insn_data[icode].operand[0].mode;
11109 mode0 = insn_data[icode].operand[1].mode;
11110 mode1 = insn_data[icode].operand[2].mode;
11111 mode2 = insn_data[icode].operand[3].mode;
11113 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
11114 op0 = copy_to_mode_reg (mode0, op0);
11115 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
11116 op1 = copy_to_mode_reg (mode1, op1);
11117 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
11119 /* @@@ better error message */
11120 error ("selector must be an immediate");
11124 || GET_MODE (target) != tmode
11125 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
11126 target = gen_reg_rtx (tmode);
11127 pat = GEN_FCN (icode) (target, op0, op1, op2);
11133 case ARM_BUILTIN_SETWCX:
11134 arg0 = TREE_VALUE (arglist);
11135 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
11136 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
11137 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
11138 emit_insn (gen_iwmmxt_tmcr (op0, op1));
11141 case ARM_BUILTIN_GETWCX:
11142 arg0 = TREE_VALUE (arglist);
11143 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
11144 target = gen_reg_rtx (SImode);
11145 emit_insn (gen_iwmmxt_tmrc (target, op0));
11148 case ARM_BUILTIN_WSHUFH:
11149 icode = CODE_FOR_iwmmxt_wshufh;
11150 arg0 = TREE_VALUE (arglist);
11151 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
11152 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
11153 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
11154 tmode = insn_data[icode].operand[0].mode;
11155 mode1 = insn_data[icode].operand[1].mode;
11156 mode2 = insn_data[icode].operand[2].mode;
11158 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
11159 op0 = copy_to_mode_reg (mode1, op0);
11160 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
11162 /* @@@ better error message */
11163 error ("mask must be an immediate");
11167 || GET_MODE (target) != tmode
11168 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
11169 target = gen_reg_rtx (tmode);
11170 pat = GEN_FCN (icode) (target, op0, op1);
11176 case ARM_BUILTIN_WSADB:
11177 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadb, arglist, target);
11178 case ARM_BUILTIN_WSADH:
11179 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadh, arglist, target);
11180 case ARM_BUILTIN_WSADBZ:
11181 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadbz, arglist, target);
11182 case ARM_BUILTIN_WSADHZ:
11183 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadhz, arglist, target);
11185 /* Several three-argument builtins. */
11186 case ARM_BUILTIN_WMACS:
11187 case ARM_BUILTIN_WMACU:
11188 case ARM_BUILTIN_WALIGN:
11189 case ARM_BUILTIN_TMIA:
11190 case ARM_BUILTIN_TMIAPH:
11191 case ARM_BUILTIN_TMIATT:
11192 case ARM_BUILTIN_TMIATB:
11193 case ARM_BUILTIN_TMIABT:
11194 case ARM_BUILTIN_TMIABB:
11195 icode = (fcode == ARM_BUILTIN_WMACS ? CODE_FOR_iwmmxt_wmacs
11196 : fcode == ARM_BUILTIN_WMACU ? CODE_FOR_iwmmxt_wmacu
11197 : fcode == ARM_BUILTIN_TMIA ? CODE_FOR_iwmmxt_tmia
11198 : fcode == ARM_BUILTIN_TMIAPH ? CODE_FOR_iwmmxt_tmiaph
11199 : fcode == ARM_BUILTIN_TMIABB ? CODE_FOR_iwmmxt_tmiabb
11200 : fcode == ARM_BUILTIN_TMIABT ? CODE_FOR_iwmmxt_tmiabt
11201 : fcode == ARM_BUILTIN_TMIATB ? CODE_FOR_iwmmxt_tmiatb
11202 : fcode == ARM_BUILTIN_TMIATT ? CODE_FOR_iwmmxt_tmiatt
11203 : CODE_FOR_iwmmxt_walign);
11204 arg0 = TREE_VALUE (arglist);
11205 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
11206 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
11207 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
11208 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
11209 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
11210 tmode = insn_data[icode].operand[0].mode;
11211 mode0 = insn_data[icode].operand[1].mode;
11212 mode1 = insn_data[icode].operand[2].mode;
11213 mode2 = insn_data[icode].operand[3].mode;
11215 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
11216 op0 = copy_to_mode_reg (mode0, op0);
11217 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
11218 op1 = copy_to_mode_reg (mode1, op1);
11219 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
11220 op2 = copy_to_mode_reg (mode2, op2);
11222 || GET_MODE (target) != tmode
11223 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
11224 target = gen_reg_rtx (tmode);
11225 pat = GEN_FCN (icode) (target, op0, op1, op2);
11231 case ARM_BUILTIN_WZERO:
11232 target = gen_reg_rtx (DImode);
11233 emit_insn (gen_iwmmxt_clrdi (target));
11240 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
11241 if (d->code == (const enum arm_builtins) fcode)
11242 return arm_expand_binop_builtin (d->icode, arglist, target);
11244 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
11245 if (d->code == (const enum arm_builtins) fcode)
11246 return arm_expand_unop_builtin (d->icode, arglist, target, 0);
11248 /* @@@ Should really do something sensible here. */
11252 /* Recursively search through all of the blocks in a function
11253 checking to see if any of the variables created in that
11254 function match the RTX called 'orig'. If they do then
11255 replace them with the RTX called 'new'. */
11257 replace_symbols_in_block (tree block, rtx orig, rtx new)
11259 for (; block; block = BLOCK_CHAIN (block))
11263 if (!TREE_USED (block))
11266 for (sym = BLOCK_VARS (block); sym; sym = TREE_CHAIN (sym))
11268 if ( (DECL_NAME (sym) == 0 && TREE_CODE (sym) != TYPE_DECL)
11269 || DECL_IGNORED_P (sym)
11270 || TREE_CODE (sym) != VAR_DECL
11271 || DECL_EXTERNAL (sym)
11272 || !rtx_equal_p (DECL_RTL (sym), orig)
11276 SET_DECL_RTL (sym, new);
11279 replace_symbols_in_block (BLOCK_SUBBLOCKS (block), orig, new);
11283 /* Return the number (counting from 0) of
11284 the least significant set bit in MASK. */
11287 number_of_first_bit_set (int mask)
11292 (mask & (1 << bit)) == 0;
11299 /* Generate code to return from a thumb function.
11300 If 'reg_containing_return_addr' is -1, then the return address is
11301 actually on the stack, at the stack pointer. */
11303 thumb_exit (FILE *f, int reg_containing_return_addr, rtx eh_ofs)
11305 unsigned regs_available_for_popping;
11306 unsigned regs_to_pop;
11308 unsigned available;
11312 int restore_a4 = FALSE;
11314 /* Compute the registers we need to pop. */
11318 /* There is an assumption here, that if eh_ofs is not NULL, the
11319 normal return address will have been pushed. */
11320 if (reg_containing_return_addr == -1 || eh_ofs)
11322 /* When we are generating a return for __builtin_eh_return,
11323 reg_containing_return_addr must specify the return regno. */
11324 if (eh_ofs && reg_containing_return_addr == -1)
11327 regs_to_pop |= 1 << LR_REGNUM;
11331 if (TARGET_BACKTRACE)
11333 /* Restore the (ARM) frame pointer and stack pointer. */
11334 regs_to_pop |= (1 << ARM_HARD_FRAME_POINTER_REGNUM) | (1 << SP_REGNUM);
11338 /* If there is nothing to pop then just emit the BX instruction and
11340 if (pops_needed == 0)
11343 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs));
11345 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
11348 /* Otherwise if we are not supporting interworking and we have not created
11349 a backtrace structure and the function was not entered in ARM mode then
11350 just pop the return address straight into the PC. */
11351 else if (!TARGET_INTERWORK
11352 && !TARGET_BACKTRACE
11353 && !is_called_in_ARM_mode (current_function_decl))
11357 asm_fprintf (f, "\tadd\t%r, #4\n", SP_REGNUM);
11358 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs));
11359 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
11362 asm_fprintf (f, "\tpop\t{%r}\n", PC_REGNUM);
11367 /* Find out how many of the (return) argument registers we can corrupt. */
11368 regs_available_for_popping = 0;
11370 /* If returning via __builtin_eh_return, the bottom three registers
11371 all contain information needed for the return. */
11377 /* If we can deduce the registers used from the function's
11378 return value. This is more reliable that examining
11379 regs_ever_live[] because that will be set if the register is
11380 ever used in the function, not just if the register is used
11381 to hold a return value. */
11383 if (current_function_return_rtx != 0)
11384 mode = GET_MODE (current_function_return_rtx);
11387 mode = DECL_MODE (DECL_RESULT (current_function_decl));
11389 size = GET_MODE_SIZE (mode);
11393 /* In a void function we can use any argument register.
11394 In a function that returns a structure on the stack
11395 we can use the second and third argument registers. */
11396 if (mode == VOIDmode)
11397 regs_available_for_popping =
11398 (1 << ARG_REGISTER (1))
11399 | (1 << ARG_REGISTER (2))
11400 | (1 << ARG_REGISTER (3));
11402 regs_available_for_popping =
11403 (1 << ARG_REGISTER (2))
11404 | (1 << ARG_REGISTER (3));
11406 else if (size <= 4)
11407 regs_available_for_popping =
11408 (1 << ARG_REGISTER (2))
11409 | (1 << ARG_REGISTER (3));
11410 else if (size <= 8)
11411 regs_available_for_popping =
11412 (1 << ARG_REGISTER (3));
11415 /* Match registers to be popped with registers into which we pop them. */
11416 for (available = regs_available_for_popping,
11417 required = regs_to_pop;
11418 required != 0 && available != 0;
11419 available &= ~(available & - available),
11420 required &= ~(required & - required))
11423 /* If we have any popping registers left over, remove them. */
11425 regs_available_for_popping &= ~available;
11427 /* Otherwise if we need another popping register we can use
11428 the fourth argument register. */
11429 else if (pops_needed)
11431 /* If we have not found any free argument registers and
11432 reg a4 contains the return address, we must move it. */
11433 if (regs_available_for_popping == 0
11434 && reg_containing_return_addr == LAST_ARG_REGNUM)
11436 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
11437 reg_containing_return_addr = LR_REGNUM;
11439 else if (size > 12)
11441 /* Register a4 is being used to hold part of the return value,
11442 but we have dire need of a free, low register. */
11445 asm_fprintf (f, "\tmov\t%r, %r\n",IP_REGNUM, LAST_ARG_REGNUM);
11448 if (reg_containing_return_addr != LAST_ARG_REGNUM)
11450 /* The fourth argument register is available. */
11451 regs_available_for_popping |= 1 << LAST_ARG_REGNUM;
11457 /* Pop as many registers as we can. */
11458 thumb_pushpop (f, regs_available_for_popping, FALSE);
11460 /* Process the registers we popped. */
11461 if (reg_containing_return_addr == -1)
11463 /* The return address was popped into the lowest numbered register. */
11464 regs_to_pop &= ~(1 << LR_REGNUM);
11466 reg_containing_return_addr =
11467 number_of_first_bit_set (regs_available_for_popping);
11469 /* Remove this register for the mask of available registers, so that
11470 the return address will not be corrupted by further pops. */
11471 regs_available_for_popping &= ~(1 << reg_containing_return_addr);
11474 /* If we popped other registers then handle them here. */
11475 if (regs_available_for_popping)
11479 /* Work out which register currently contains the frame pointer. */
11480 frame_pointer = number_of_first_bit_set (regs_available_for_popping);
11482 /* Move it into the correct place. */
11483 asm_fprintf (f, "\tmov\t%r, %r\n",
11484 ARM_HARD_FRAME_POINTER_REGNUM, frame_pointer);
11486 /* (Temporarily) remove it from the mask of popped registers. */
11487 regs_available_for_popping &= ~(1 << frame_pointer);
11488 regs_to_pop &= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM);
11490 if (regs_available_for_popping)
11494 /* We popped the stack pointer as well,
11495 find the register that contains it. */
11496 stack_pointer = number_of_first_bit_set (regs_available_for_popping);
11498 /* Move it into the stack register. */
11499 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, stack_pointer);
11501 /* At this point we have popped all necessary registers, so
11502 do not worry about restoring regs_available_for_popping
11503 to its correct value:
11505 assert (pops_needed == 0)
11506 assert (regs_available_for_popping == (1 << frame_pointer))
11507 assert (regs_to_pop == (1 << STACK_POINTER)) */
11511 /* Since we have just move the popped value into the frame
11512 pointer, the popping register is available for reuse, and
11513 we know that we still have the stack pointer left to pop. */
11514 regs_available_for_popping |= (1 << frame_pointer);
11518 /* If we still have registers left on the stack, but we no longer have
11519 any registers into which we can pop them, then we must move the return
11520 address into the link register and make available the register that
11522 if (regs_available_for_popping == 0 && pops_needed > 0)
11524 regs_available_for_popping |= 1 << reg_containing_return_addr;
11526 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM,
11527 reg_containing_return_addr);
11529 reg_containing_return_addr = LR_REGNUM;
11532 /* If we have registers left on the stack then pop some more.
11533 We know that at most we will want to pop FP and SP. */
11534 if (pops_needed > 0)
11539 thumb_pushpop (f, regs_available_for_popping, FALSE);
11541 /* We have popped either FP or SP.
11542 Move whichever one it is into the correct register. */
11543 popped_into = number_of_first_bit_set (regs_available_for_popping);
11544 move_to = number_of_first_bit_set (regs_to_pop);
11546 asm_fprintf (f, "\tmov\t%r, %r\n", move_to, popped_into);
11548 regs_to_pop &= ~(1 << move_to);
11553 /* If we still have not popped everything then we must have only
11554 had one register available to us and we are now popping the SP. */
11555 if (pops_needed > 0)
11559 thumb_pushpop (f, regs_available_for_popping, FALSE);
11561 popped_into = number_of_first_bit_set (regs_available_for_popping);
11563 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, popped_into);
11565 assert (regs_to_pop == (1 << STACK_POINTER))
11566 assert (pops_needed == 1)
11570 /* If necessary restore the a4 register. */
11573 if (reg_containing_return_addr != LR_REGNUM)
11575 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
11576 reg_containing_return_addr = LR_REGNUM;
11579 asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM);
11583 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs));
11585 /* Return to caller. */
11586 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
11589 /* Emit code to push or pop registers to or from the stack. */
11591 thumb_pushpop (FILE *f, int mask, int push)
11594 int lo_mask = mask & 0xFF;
11596 if (lo_mask == 0 && !push && (mask & (1 << 15)))
11598 /* Special case. Do not generate a POP PC statement here, do it in
11600 thumb_exit (f, -1, NULL_RTX);
11604 fprintf (f, "\t%s\t{", push ? "push" : "pop");
11606 /* Look at the low registers first. */
11607 for (regno = 0; regno <= LAST_LO_REGNUM; regno++, lo_mask >>= 1)
11611 asm_fprintf (f, "%r", regno);
11613 if ((lo_mask & ~1) != 0)
11618 if (push && (mask & (1 << LR_REGNUM)))
11620 /* Catch pushing the LR. */
11624 asm_fprintf (f, "%r", LR_REGNUM);
11626 else if (!push && (mask & (1 << PC_REGNUM)))
11628 /* Catch popping the PC. */
11629 if (TARGET_INTERWORK || TARGET_BACKTRACE)
11631 /* The PC is never poped directly, instead
11632 it is popped into r3 and then BX is used. */
11633 fprintf (f, "}\n");
11635 thumb_exit (f, -1, NULL_RTX);
11644 asm_fprintf (f, "%r", PC_REGNUM);
11648 fprintf (f, "}\n");
11652 thumb_final_prescan_insn (rtx insn)
11654 if (flag_print_asm_name)
11655 asm_fprintf (asm_out_file, "%@ 0x%04x\n",
11656 INSN_ADDRESSES (INSN_UID (insn)));
11660 thumb_shiftable_const (unsigned HOST_WIDE_INT val)
11662 unsigned HOST_WIDE_INT mask = 0xff;
11665 if (val == 0) /* XXX */
11668 for (i = 0; i < 25; i++)
11669 if ((val & (mask << i)) == val)
11675 /* Returns nonzero if the current function contains,
11676 or might contain a far jump. */
11678 thumb_far_jump_used_p (int in_prologue)
11682 /* This test is only important for leaf functions. */
11683 /* assert (!leaf_function_p ()); */
11685 /* If we have already decided that far jumps may be used,
11686 do not bother checking again, and always return true even if
11687 it turns out that they are not being used. Once we have made
11688 the decision that far jumps are present (and that hence the link
11689 register will be pushed onto the stack) we cannot go back on it. */
11690 if (cfun->machine->far_jump_used)
11693 /* If this function is not being called from the prologue/epilogue
11694 generation code then it must be being called from the
11695 INITIAL_ELIMINATION_OFFSET macro. */
11698 /* In this case we know that we are being asked about the elimination
11699 of the arg pointer register. If that register is not being used,
11700 then there are no arguments on the stack, and we do not have to
11701 worry that a far jump might force the prologue to push the link
11702 register, changing the stack offsets. In this case we can just
11703 return false, since the presence of far jumps in the function will
11704 not affect stack offsets.
11706 If the arg pointer is live (or if it was live, but has now been
11707 eliminated and so set to dead) then we do have to test to see if
11708 the function might contain a far jump. This test can lead to some
11709 false negatives, since before reload is completed, then length of
11710 branch instructions is not known, so gcc defaults to returning their
11711 longest length, which in turn sets the far jump attribute to true.
11713 A false negative will not result in bad code being generated, but it
11714 will result in a needless push and pop of the link register. We
11715 hope that this does not occur too often. */
11716 if (regs_ever_live [ARG_POINTER_REGNUM])
11717 cfun->machine->arg_pointer_live = 1;
11718 else if (!cfun->machine->arg_pointer_live)
11722 /* Check to see if the function contains a branch
11723 insn with the far jump attribute set. */
11724 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
11726 if (GET_CODE (insn) == JUMP_INSN
11727 /* Ignore tablejump patterns. */
11728 && GET_CODE (PATTERN (insn)) != ADDR_VEC
11729 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
11730 && get_attr_far_jump (insn) == FAR_JUMP_YES
11733 /* Record the fact that we have decided that
11734 the function does use far jumps. */
11735 cfun->machine->far_jump_used = 1;
11743 /* Return nonzero if FUNC must be entered in ARM mode. */
11745 is_called_in_ARM_mode (tree func)
11747 if (TREE_CODE (func) != FUNCTION_DECL)
11750 /* Ignore the problem about functions whoes address is taken. */
11751 if (TARGET_CALLEE_INTERWORKING && TREE_PUBLIC (func))
11755 return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func)) != NULL_TREE;
11761 /* The bits which aren't usefully expanded as rtl. */
11763 thumb_unexpanded_epilogue (void)
11766 int live_regs_mask = 0;
11767 int high_regs_pushed = 0;
11768 int leaf_function = leaf_function_p ();
11769 int had_to_push_lr;
11770 rtx eh_ofs = cfun->machine->eh_epilogue_sp_ofs;
11772 if (return_used_this_function)
11775 if (IS_NAKED (arm_current_func_type ()))
11778 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
11779 if (THUMB_REG_PUSHED_P (regno))
11780 live_regs_mask |= 1 << regno;
11782 for (regno = 8; regno < 13; regno++)
11783 if (THUMB_REG_PUSHED_P (regno))
11784 high_regs_pushed++;
11786 /* The prolog may have pushed some high registers to use as
11787 work registers. eg the testsuite file:
11788 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
11789 compiles to produce:
11790 push {r4, r5, r6, r7, lr}
11794 as part of the prolog. We have to undo that pushing here. */
11796 if (high_regs_pushed)
11798 int mask = live_regs_mask;
11804 /* If we can deduce the registers used from the function's return value.
11805 This is more reliable that examining regs_ever_live[] because that
11806 will be set if the register is ever used in the function, not just if
11807 the register is used to hold a return value. */
11809 if (current_function_return_rtx != 0)
11810 mode = GET_MODE (current_function_return_rtx);
11813 mode = DECL_MODE (DECL_RESULT (current_function_decl));
11815 size = GET_MODE_SIZE (mode);
11817 /* Unless we are returning a type of size > 12 register r3 is
11823 /* Oh dear! We have no low registers into which we can pop
11826 ("no low registers available for popping high registers");
11828 for (next_hi_reg = 8; next_hi_reg < 13; next_hi_reg++)
11829 if (THUMB_REG_PUSHED_P (next_hi_reg))
11832 while (high_regs_pushed)
11834 /* Find lo register(s) into which the high register(s) can
11836 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
11838 if (mask & (1 << regno))
11839 high_regs_pushed--;
11840 if (high_regs_pushed == 0)
11844 mask &= (2 << regno) - 1; /* A noop if regno == 8 */
11846 /* Pop the values into the low register(s). */
11847 thumb_pushpop (asm_out_file, mask, 0);
11849 /* Move the value(s) into the high registers. */
11850 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
11852 if (mask & (1 << regno))
11854 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", next_hi_reg,
11857 for (next_hi_reg++; next_hi_reg < 13; next_hi_reg++)
11858 if (THUMB_REG_PUSHED_P (next_hi_reg))
11865 had_to_push_lr = (live_regs_mask || !leaf_function
11866 || thumb_far_jump_used_p (1));
11868 if (TARGET_BACKTRACE
11869 && ((live_regs_mask & 0xFF) == 0)
11870 && regs_ever_live [LAST_ARG_REGNUM] != 0)
11872 /* The stack backtrace structure creation code had to
11873 push R7 in order to get a work register, so we pop
11875 live_regs_mask |= (1 << LAST_LO_REGNUM);
11878 if (current_function_pretend_args_size == 0 || TARGET_BACKTRACE)
11881 && !is_called_in_ARM_mode (current_function_decl)
11883 live_regs_mask |= 1 << PC_REGNUM;
11885 /* Either no argument registers were pushed or a backtrace
11886 structure was created which includes an adjusted stack
11887 pointer, so just pop everything. */
11888 if (live_regs_mask)
11889 thumb_pushpop (asm_out_file, live_regs_mask, FALSE);
11892 thumb_exit (asm_out_file, 2, eh_ofs);
11893 /* We have either just popped the return address into the
11894 PC or it is was kept in LR for the entire function or
11895 it is still on the stack because we do not want to
11896 return by doing a pop {pc}. */
11897 else if ((live_regs_mask & (1 << PC_REGNUM)) == 0)
11898 thumb_exit (asm_out_file,
11900 && is_called_in_ARM_mode (current_function_decl)) ?
11901 -1 : LR_REGNUM, NULL_RTX);
11905 /* Pop everything but the return address. */
11906 live_regs_mask &= ~(1 << PC_REGNUM);
11908 if (live_regs_mask)
11909 thumb_pushpop (asm_out_file, live_regs_mask, FALSE);
11911 if (had_to_push_lr)
11912 /* Get the return address into a temporary register. */
11913 thumb_pushpop (asm_out_file, 1 << LAST_ARG_REGNUM, 0);
11915 /* Remove the argument registers that were pushed onto the stack. */
11916 asm_fprintf (asm_out_file, "\tadd\t%r, %r, #%d\n",
11917 SP_REGNUM, SP_REGNUM,
11918 current_function_pretend_args_size);
11921 thumb_exit (asm_out_file, 2, eh_ofs);
11923 thumb_exit (asm_out_file,
11924 had_to_push_lr ? LAST_ARG_REGNUM : LR_REGNUM, NULL_RTX);
11930 /* Functions to save and restore machine-specific function data. */
11931 static struct machine_function *
11932 arm_init_machine_status (void)
11934 struct machine_function *machine;
11935 machine = (machine_function *) ggc_alloc_cleared (sizeof (machine_function));
11937 #if ARM_FT_UNKNOWN != 0
11938 machine->func_type = ARM_FT_UNKNOWN;
11943 /* Return an RTX indicating where the return address to the
11944 calling function can be found. */
11946 arm_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
11951 if (TARGET_APCS_32)
11952 return get_hard_reg_initial_val (Pmode, LR_REGNUM);
11955 rtx lr = gen_rtx_AND (Pmode, gen_rtx_REG (Pmode, LR_REGNUM),
11956 GEN_INT (RETURN_ADDR_MASK26));
11957 return get_func_hard_reg_initial_val (cfun, lr);
11961 /* Do anything needed before RTL is emitted for each function. */
11963 arm_init_expanders (void)
11965 /* Arrange to initialize and mark the machine per-function status. */
11966 init_machine_status = arm_init_machine_status;
11970 thumb_get_frame_size (void)
11974 int base_size = ROUND_UP_WORD (get_frame_size ());
11975 int count_regs = 0;
11976 int entry_size = 0;
11979 if (! TARGET_THUMB)
11982 if (! TARGET_ATPCS)
11985 /* We need to know if we are a leaf function. Unfortunately, it
11986 is possible to be called after start_sequence has been called,
11987 which causes get_insns to return the insns for the sequence,
11988 not the function, which will cause leaf_function_p to return
11989 the incorrect result.
11991 To work around this, we cache the computed frame size. This
11992 works because we will only be calling RTL expanders that need
11993 to know about leaf functions once reload has completed, and the
11994 frame size cannot be changed after that time, so we can safely
11995 use the cached value. */
11997 if (reload_completed)
11998 return cfun->machine->frame_size;
12000 leaf = leaf_function_p ();
12002 /* A leaf function does not need any stack alignment if it has nothing
12004 if (leaf && base_size == 0)
12006 cfun->machine->frame_size = 0;
12010 /* We know that SP will be word aligned on entry, and we must
12011 preserve that condition at any subroutine call. But those are
12012 the only constraints. */
12014 /* Space for variadic functions. */
12015 if (current_function_pretend_args_size)
12016 entry_size += current_function_pretend_args_size;
12018 /* Space for pushed lo registers. */
12019 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
12020 if (THUMB_REG_PUSHED_P (regno))
12023 /* Space for backtrace structure. */
12024 if (TARGET_BACKTRACE)
12026 if (count_regs == 0 && regs_ever_live[LAST_ARG_REGNUM] != 0)
12032 if (count_regs || !leaf || thumb_far_jump_used_p (1))
12033 count_regs++; /* LR */
12035 entry_size += count_regs * 4;
12038 /* Space for pushed hi regs. */
12039 for (regno = 8; regno < 13; regno++)
12040 if (THUMB_REG_PUSHED_P (regno))
12043 entry_size += count_regs * 4;
12045 if ((entry_size + base_size + current_function_outgoing_args_size) & 7)
12047 if ((entry_size + base_size + current_function_outgoing_args_size) & 7)
12050 cfun->machine->frame_size = base_size;
12055 /* Generate the rest of a function's prologue. */
12057 thumb_expand_prologue (void)
12059 HOST_WIDE_INT amount = (thumb_get_frame_size ()
12060 + current_function_outgoing_args_size);
12061 unsigned long func_type;
12063 func_type = arm_current_func_type ();
12065 /* Naked functions don't have prologues. */
12066 if (IS_NAKED (func_type))
12069 if (IS_INTERRUPT (func_type))
12071 error ("interrupt Service Routines cannot be coded in Thumb mode");
12075 if (frame_pointer_needed)
12076 emit_insn (gen_movsi (hard_frame_pointer_rtx, stack_pointer_rtx));
12080 amount = ROUND_UP_WORD (amount);
12083 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
12084 GEN_INT (- amount)));
12090 /* The stack decrement is too big for an immediate value in a single
12091 insn. In theory we could issue multiple subtracts, but after
12092 three of them it becomes more space efficient to place the full
12093 value in the constant pool and load into a register. (Also the
12094 ARM debugger really likes to see only one stack decrement per
12095 function). So instead we look for a scratch register into which
12096 we can load the decrement, and then we subtract this from the
12097 stack pointer. Unfortunately on the thumb the only available
12098 scratch registers are the argument registers, and we cannot use
12099 these as they may hold arguments to the function. Instead we
12100 attempt to locate a call preserved register which is used by this
12101 function. If we can find one, then we know that it will have
12102 been pushed at the start of the prologue and so we can corrupt
12104 for (regno = LAST_ARG_REGNUM + 1; regno <= LAST_LO_REGNUM; regno++)
12105 if (THUMB_REG_PUSHED_P (regno)
12106 && !(frame_pointer_needed
12107 && (regno == THUMB_HARD_FRAME_POINTER_REGNUM)))
12110 if (regno > LAST_LO_REGNUM) /* Very unlikely. */
12112 rtx spare = gen_rtx (REG, SImode, IP_REGNUM);
12114 /* Choose an arbitrary, non-argument low register. */
12115 reg = gen_rtx (REG, SImode, LAST_LO_REGNUM);
12117 /* Save it by copying it into a high, scratch register. */
12118 emit_insn (gen_movsi (spare, reg));
12119 /* Add a USE to stop propagate_one_insn() from barfing. */
12120 emit_insn (gen_prologue_use (spare));
12122 /* Decrement the stack. */
12123 emit_insn (gen_movsi (reg, GEN_INT (- amount)));
12124 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
12127 /* Restore the low register's original value. */
12128 emit_insn (gen_movsi (reg, spare));
12130 /* Emit a USE of the restored scratch register, so that flow
12131 analysis will not consider the restore redundant. The
12132 register won't be used again in this function and isn't
12133 restored by the epilogue. */
12134 emit_insn (gen_prologue_use (reg));
12138 reg = gen_rtx (REG, SImode, regno);
12140 emit_insn (gen_movsi (reg, GEN_INT (- amount)));
12141 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
12147 if (current_function_profile || TARGET_NO_SCHED_PRO)
12148 emit_insn (gen_blockage ());
12152 thumb_expand_epilogue (void)
12154 HOST_WIDE_INT amount = (thumb_get_frame_size ()
12155 + current_function_outgoing_args_size);
12158 /* Naked functions don't have prologues. */
12159 if (IS_NAKED (arm_current_func_type ()))
12162 if (frame_pointer_needed)
12163 emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx));
12166 amount = ROUND_UP_WORD (amount);
12169 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
12170 GEN_INT (amount)));
12173 /* r3 is always free in the epilogue. */
12174 rtx reg = gen_rtx (REG, SImode, LAST_ARG_REGNUM);
12176 emit_insn (gen_movsi (reg, GEN_INT (amount)));
12177 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, reg));
12181 /* Emit a USE (stack_pointer_rtx), so that
12182 the stack adjustment will not be deleted. */
12183 emit_insn (gen_prologue_use (stack_pointer_rtx));
12185 if (current_function_profile || TARGET_NO_SCHED_PRO)
12186 emit_insn (gen_blockage ());
12188 /* Emit a clobber for each insn that will be restored in the epilogue,
12189 so that flow2 will get register lifetimes correct. */
12190 for (regno = 0; regno < 13; regno++)
12191 if (regs_ever_live[regno] && !call_used_regs[regno])
12192 emit_insn (gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, regno)));
12194 if (! regs_ever_live[LR_REGNUM])
12195 emit_insn (gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, LR_REGNUM)));
12199 thumb_output_function_prologue (FILE *f, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
12201 int live_regs_mask = 0;
12202 int high_regs_pushed = 0;
12205 if (IS_NAKED (arm_current_func_type ()))
12208 if (is_called_in_ARM_mode (current_function_decl))
12212 if (GET_CODE (DECL_RTL (current_function_decl)) != MEM)
12214 if (GET_CODE (XEXP (DECL_RTL (current_function_decl), 0)) != SYMBOL_REF)
12216 name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
12218 /* Generate code sequence to switch us into Thumb mode. */
12219 /* The .code 32 directive has already been emitted by
12220 ASM_DECLARE_FUNCTION_NAME. */
12221 asm_fprintf (f, "\torr\t%r, %r, #1\n", IP_REGNUM, PC_REGNUM);
12222 asm_fprintf (f, "\tbx\t%r\n", IP_REGNUM);
12224 /* Generate a label, so that the debugger will notice the
12225 change in instruction sets. This label is also used by
12226 the assembler to bypass the ARM code when this function
12227 is called from a Thumb encoded function elsewhere in the
12228 same file. Hence the definition of STUB_NAME here must
12229 agree with the definition in gas/config/tc-arm.c */
12231 #define STUB_NAME ".real_start_of"
12233 fprintf (f, "\t.code\t16\n");
12235 if (arm_dllexport_name_p (name))
12236 name = arm_strip_name_encoding (name);
12238 asm_fprintf (f, "\t.globl %s%U%s\n", STUB_NAME, name);
12239 fprintf (f, "\t.thumb_func\n");
12240 asm_fprintf (f, "%s%U%s:\n", STUB_NAME, name);
12243 if (current_function_pretend_args_size)
12245 if (cfun->machine->uses_anonymous_args)
12249 fprintf (f, "\tpush\t{");
12251 num_pushes = ARM_NUM_INTS (current_function_pretend_args_size);
12253 for (regno = LAST_ARG_REGNUM + 1 - num_pushes;
12254 regno <= LAST_ARG_REGNUM;
12256 asm_fprintf (f, "%r%s", regno,
12257 regno == LAST_ARG_REGNUM ? "" : ", ");
12259 fprintf (f, "}\n");
12262 asm_fprintf (f, "\tsub\t%r, %r, #%d\n",
12263 SP_REGNUM, SP_REGNUM,
12264 current_function_pretend_args_size);
12267 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
12268 if (THUMB_REG_PUSHED_P (regno))
12269 live_regs_mask |= 1 << regno;
12271 if (live_regs_mask || !leaf_function_p () || thumb_far_jump_used_p (1))
12272 live_regs_mask |= 1 << LR_REGNUM;
12274 if (TARGET_BACKTRACE)
12277 int work_register = 0;
12280 /* We have been asked to create a stack backtrace structure.
12281 The code looks like this:
12285 0 sub SP, #16 Reserve space for 4 registers.
12286 2 push {R7} Get a work register.
12287 4 add R7, SP, #20 Get the stack pointer before the push.
12288 6 str R7, [SP, #8] Store the stack pointer (before reserving the space).
12289 8 mov R7, PC Get hold of the start of this code plus 12.
12290 10 str R7, [SP, #16] Store it.
12291 12 mov R7, FP Get hold of the current frame pointer.
12292 14 str R7, [SP, #4] Store it.
12293 16 mov R7, LR Get hold of the current return address.
12294 18 str R7, [SP, #12] Store it.
12295 20 add R7, SP, #16 Point at the start of the backtrace structure.
12296 22 mov FP, R7 Put this value into the frame pointer. */
12298 if ((live_regs_mask & 0xFF) == 0)
12300 /* See if the a4 register is free. */
12302 if (regs_ever_live [LAST_ARG_REGNUM] == 0)
12303 work_register = LAST_ARG_REGNUM;
12304 else /* We must push a register of our own */
12305 live_regs_mask |= (1 << LAST_LO_REGNUM);
12308 if (work_register == 0)
12310 /* Select a register from the list that will be pushed to
12311 use as our work register. */
12312 for (work_register = (LAST_LO_REGNUM + 1); work_register--;)
12313 if ((1 << work_register) & live_regs_mask)
12318 (f, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n",
12319 SP_REGNUM, SP_REGNUM);
12321 if (live_regs_mask)
12322 thumb_pushpop (f, live_regs_mask, 1);
12324 for (offset = 0, wr = 1 << 15; wr != 0; wr >>= 1)
12325 if (wr & live_regs_mask)
12328 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
12329 offset + 16 + current_function_pretend_args_size);
12331 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
12334 /* Make sure that the instruction fetching the PC is in the right place
12335 to calculate "start of backtrace creation code + 12". */
12336 if (live_regs_mask)
12338 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
12339 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
12341 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
12342 ARM_HARD_FRAME_POINTER_REGNUM);
12343 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
12348 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
12349 ARM_HARD_FRAME_POINTER_REGNUM);
12350 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
12352 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
12353 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
12357 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, LR_REGNUM);
12358 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
12360 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
12362 asm_fprintf (f, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n",
12363 ARM_HARD_FRAME_POINTER_REGNUM, work_register);
12365 else if (live_regs_mask)
12366 thumb_pushpop (f, live_regs_mask, 1);
12368 for (regno = 8; regno < 13; regno++)
12369 if (THUMB_REG_PUSHED_P (regno))
12370 high_regs_pushed++;
12372 if (high_regs_pushed)
12374 int pushable_regs = 0;
12375 int mask = live_regs_mask & 0xff;
12378 for (next_hi_reg = 12; next_hi_reg > LAST_LO_REGNUM; next_hi_reg--)
12379 if (THUMB_REG_PUSHED_P (next_hi_reg))
12382 pushable_regs = mask;
12384 if (pushable_regs == 0)
12386 /* Desperation time -- this probably will never happen. */
12387 if (THUMB_REG_PUSHED_P (LAST_ARG_REGNUM))
12388 asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, LAST_ARG_REGNUM);
12389 mask = 1 << LAST_ARG_REGNUM;
12392 while (high_regs_pushed > 0)
12394 for (regno = LAST_LO_REGNUM; regno >= 0; regno--)
12396 if (mask & (1 << regno))
12398 asm_fprintf (f, "\tmov\t%r, %r\n", regno, next_hi_reg);
12400 high_regs_pushed--;
12402 if (high_regs_pushed)
12404 for (next_hi_reg--; next_hi_reg > LAST_LO_REGNUM;
12406 if (THUMB_REG_PUSHED_P (next_hi_reg))
12411 mask &= ~((1 << regno) - 1);
12417 thumb_pushpop (f, mask, 1);
12420 if (pushable_regs == 0
12421 && (THUMB_REG_PUSHED_P (LAST_ARG_REGNUM)))
12422 asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM);
12426 /* Handle the case of a double word load into a low register from
12427 a computed memory address. The computed address may involve a
12428 register which is overwritten by the load. */
12430 thumb_load_double_from_address (rtx *operands)
12438 if (GET_CODE (operands[0]) != REG)
12441 if (GET_CODE (operands[1]) != MEM)
12444 /* Get the memory address. */
12445 addr = XEXP (operands[1], 0);
12447 /* Work out how the memory address is computed. */
12448 switch (GET_CODE (addr))
12451 operands[2] = gen_rtx (MEM, SImode,
12452 plus_constant (XEXP (operands[1], 0), 4));
12454 if (REGNO (operands[0]) == REGNO (addr))
12456 output_asm_insn ("ldr\t%H0, %2", operands);
12457 output_asm_insn ("ldr\t%0, %1", operands);
12461 output_asm_insn ("ldr\t%0, %1", operands);
12462 output_asm_insn ("ldr\t%H0, %2", operands);
12467 /* Compute <address> + 4 for the high order load. */
12468 operands[2] = gen_rtx (MEM, SImode,
12469 plus_constant (XEXP (operands[1], 0), 4));
12471 output_asm_insn ("ldr\t%0, %1", operands);
12472 output_asm_insn ("ldr\t%H0, %2", operands);
12476 arg1 = XEXP (addr, 0);
12477 arg2 = XEXP (addr, 1);
12479 if (CONSTANT_P (arg1))
12480 base = arg2, offset = arg1;
12482 base = arg1, offset = arg2;
12484 if (GET_CODE (base) != REG)
12487 /* Catch the case of <address> = <reg> + <reg> */
12488 if (GET_CODE (offset) == REG)
12490 int reg_offset = REGNO (offset);
12491 int reg_base = REGNO (base);
12492 int reg_dest = REGNO (operands[0]);
12494 /* Add the base and offset registers together into the
12495 higher destination register. */
12496 asm_fprintf (asm_out_file, "\tadd\t%r, %r, %r",
12497 reg_dest + 1, reg_base, reg_offset);
12499 /* Load the lower destination register from the address in
12500 the higher destination register. */
12501 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #0]",
12502 reg_dest, reg_dest + 1);
12504 /* Load the higher destination register from its own address
12506 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #4]",
12507 reg_dest + 1, reg_dest + 1);
12511 /* Compute <address> + 4 for the high order load. */
12512 operands[2] = gen_rtx (MEM, SImode,
12513 plus_constant (XEXP (operands[1], 0), 4));
12515 /* If the computed address is held in the low order register
12516 then load the high order register first, otherwise always
12517 load the low order register first. */
12518 if (REGNO (operands[0]) == REGNO (base))
12520 output_asm_insn ("ldr\t%H0, %2", operands);
12521 output_asm_insn ("ldr\t%0, %1", operands);
12525 output_asm_insn ("ldr\t%0, %1", operands);
12526 output_asm_insn ("ldr\t%H0, %2", operands);
12532 /* With no registers to worry about we can just load the value
12534 operands[2] = gen_rtx (MEM, SImode,
12535 plus_constant (XEXP (operands[1], 0), 4));
12537 output_asm_insn ("ldr\t%H0, %2", operands);
12538 output_asm_insn ("ldr\t%0, %1", operands);
12550 thumb_output_move_mem_multiple (int n, rtx *operands)
12557 if (REGNO (operands[4]) > REGNO (operands[5]))
12560 operands[4] = operands[5];
12563 output_asm_insn ("ldmia\t%1!, {%4, %5}", operands);
12564 output_asm_insn ("stmia\t%0!, {%4, %5}", operands);
12568 if (REGNO (operands[4]) > REGNO (operands[5]))
12571 operands[4] = operands[5];
12574 if (REGNO (operands[5]) > REGNO (operands[6]))
12577 operands[5] = operands[6];
12580 if (REGNO (operands[4]) > REGNO (operands[5]))
12583 operands[4] = operands[5];
12587 output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands);
12588 output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands);
12598 /* Routines for generating rtl. */
12600 thumb_expand_movstrqi (rtx *operands)
12602 rtx out = copy_to_mode_reg (SImode, XEXP (operands[0], 0));
12603 rtx in = copy_to_mode_reg (SImode, XEXP (operands[1], 0));
12604 HOST_WIDE_INT len = INTVAL (operands[2]);
12605 HOST_WIDE_INT offset = 0;
12609 emit_insn (gen_movmem12b (out, in, out, in));
12615 emit_insn (gen_movmem8b (out, in, out, in));
12621 rtx reg = gen_reg_rtx (SImode);
12622 emit_insn (gen_movsi (reg, gen_rtx (MEM, SImode, in)));
12623 emit_insn (gen_movsi (gen_rtx (MEM, SImode, out), reg));
12630 rtx reg = gen_reg_rtx (HImode);
12631 emit_insn (gen_movhi (reg, gen_rtx (MEM, HImode,
12632 plus_constant (in, offset))));
12633 emit_insn (gen_movhi (gen_rtx (MEM, HImode, plus_constant (out, offset)),
12641 rtx reg = gen_reg_rtx (QImode);
12642 emit_insn (gen_movqi (reg, gen_rtx (MEM, QImode,
12643 plus_constant (in, offset))));
12644 emit_insn (gen_movqi (gen_rtx (MEM, QImode, plus_constant (out, offset)),
12650 thumb_cmp_operand (rtx op, enum machine_mode mode)
12652 return ((GET_CODE (op) == CONST_INT
12653 && INTVAL (op) < 256
12654 && INTVAL (op) >= 0)
12655 || s_register_operand (op, mode));
12659 thumb_cmpneg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
12661 return (GET_CODE (op) == CONST_INT
12663 && INTVAL (op) > -256);
12666 /* Return TRUE if a result can be stored in OP without clobbering the
12667 condition code register. Prior to reload we only accept a
12668 register. After reload we have to be able to handle memory as
12669 well, since a pseudo may not get a hard reg and reload cannot
12670 handle output-reloads on jump insns.
12672 We could possibly handle mem before reload as well, but that might
12673 complicate things with the need to handle increment
12677 thumb_cbrch_target_operand (rtx op, enum machine_mode mode)
12679 return (s_register_operand (op, mode)
12680 || ((reload_in_progress || reload_completed)
12681 && memory_operand (op, mode)));
12684 /* Handle storing a half-word to memory during reload. */
12686 thumb_reload_out_hi (rtx *operands)
12688 emit_insn (gen_thumb_movhi_clobber (operands[0], operands[1], operands[2]));
12691 /* Handle reading a half-word from memory during reload. */
12693 thumb_reload_in_hi (rtx *operands ATTRIBUTE_UNUSED)
12698 /* Return the length of a function name prefix
12699 that starts with the character 'c'. */
12701 arm_get_strip_length (int c)
12705 ARM_NAME_ENCODING_LENGTHS
12710 /* Return a pointer to a function's name with any
12711 and all prefix encodings stripped from it. */
12713 arm_strip_name_encoding (const char *name)
12717 while ((skip = arm_get_strip_length (* name)))
12723 /* If there is a '*' anywhere in the name's prefix, then
12724 emit the stripped name verbatim, otherwise prepend an
12725 underscore if leading underscores are being used. */
12727 arm_asm_output_labelref (FILE *stream, const char *name)
12732 while ((skip = arm_get_strip_length (* name)))
12734 verbatim |= (*name == '*');
12739 fputs (name, stream);
12741 asm_fprintf (stream, "%U%s", name);
12746 #ifdef AOF_ASSEMBLER
12747 /* Special functions only needed when producing AOF syntax assembler. */
12751 struct pic_chain * next;
12752 const char * symname;
12755 static struct pic_chain * aof_pic_chain = NULL;
12758 aof_pic_entry (rtx x)
12760 struct pic_chain ** chainp;
12763 if (aof_pic_label == NULL_RTX)
12765 aof_pic_label = gen_rtx_SYMBOL_REF (Pmode, "x$adcons");
12768 for (offset = 0, chainp = &aof_pic_chain; *chainp;
12769 offset += 4, chainp = &(*chainp)->next)
12770 if ((*chainp)->symname == XSTR (x, 0))
12771 return plus_constant (aof_pic_label, offset);
12773 *chainp = (struct pic_chain *) xmalloc (sizeof (struct pic_chain));
12774 (*chainp)->next = NULL;
12775 (*chainp)->symname = XSTR (x, 0);
12776 return plus_constant (aof_pic_label, offset);
12780 aof_dump_pic_table (FILE *f)
12782 struct pic_chain * chain;
12784 if (aof_pic_chain == NULL)
12787 asm_fprintf (f, "\tAREA |%r$$adcons|, BASED %r\n",
12788 PIC_OFFSET_TABLE_REGNUM,
12789 PIC_OFFSET_TABLE_REGNUM);
12790 fputs ("|x$adcons|\n", f);
12792 for (chain = aof_pic_chain; chain; chain = chain->next)
12794 fputs ("\tDCD\t", f);
12795 assemble_name (f, chain->symname);
12800 int arm_text_section_count = 1;
12803 aof_text_section (void )
12805 static char buf[100];
12806 sprintf (buf, "\tAREA |C$$code%d|, CODE, READONLY",
12807 arm_text_section_count++);
12809 strcat (buf, ", PIC, REENTRANT");
12813 static int arm_data_section_count = 1;
12816 aof_data_section (void)
12818 static char buf[100];
12819 sprintf (buf, "\tAREA |C$$data%d|, DATA", arm_data_section_count++);
12823 /* The AOF assembler is religiously strict about declarations of
12824 imported and exported symbols, so that it is impossible to declare
12825 a function as imported near the beginning of the file, and then to
12826 export it later on. It is, however, possible to delay the decision
12827 until all the functions in the file have been compiled. To get
12828 around this, we maintain a list of the imports and exports, and
12829 delete from it any that are subsequently defined. At the end of
12830 compilation we spit the remainder of the list out before the END
12835 struct import * next;
12839 static struct import * imports_list = NULL;
12842 aof_add_import (const char *name)
12844 struct import * new;
12846 for (new = imports_list; new; new = new->next)
12847 if (new->name == name)
12850 new = (struct import *) xmalloc (sizeof (struct import));
12851 new->next = imports_list;
12852 imports_list = new;
12857 aof_delete_import (const char *name)
12859 struct import ** old;
12861 for (old = &imports_list; *old; old = & (*old)->next)
12863 if ((*old)->name == name)
12865 *old = (*old)->next;
12871 int arm_main_function = 0;
12874 aof_dump_imports (FILE *f)
12876 /* The AOF assembler needs this to cause the startup code to be extracted
12877 from the library. Brining in __main causes the whole thing to work
12879 if (arm_main_function)
12882 fputs ("\tIMPORT __main\n", f);
12883 fputs ("\tDCD __main\n", f);
12886 /* Now dump the remaining imports. */
12887 while (imports_list)
12889 fprintf (f, "\tIMPORT\t");
12890 assemble_name (f, imports_list->name);
12892 imports_list = imports_list->next;
12897 aof_globalize_label (FILE *stream, const char *name)
12899 default_globalize_label (stream, name);
12900 if (! strcmp (name, "main"))
12901 arm_main_function = 1;
12907 fputs ("__r0\tRN\t0\n", asm_out_file);
12908 fputs ("__a1\tRN\t0\n", asm_out_file);
12909 fputs ("__a2\tRN\t1\n", asm_out_file);
12910 fputs ("__a3\tRN\t2\n", asm_out_file);
12911 fputs ("__a4\tRN\t3\n", asm_out_file);
12912 fputs ("__v1\tRN\t4\n", asm_out_file);
12913 fputs ("__v2\tRN\t5\n", asm_out_file);
12914 fputs ("__v3\tRN\t6\n", asm_out_file);
12915 fputs ("__v4\tRN\t7\n", asm_out_file);
12916 fputs ("__v5\tRN\t8\n", asm_out_file);
12917 fputs ("__v6\tRN\t9\n", asm_out_file);
12918 fputs ("__sl\tRN\t10\n", asm_out_file);
12919 fputs ("__fp\tRN\t11\n", asm_out_file);
12920 fputs ("__ip\tRN\t12\n", asm_out_file);
12921 fputs ("__sp\tRN\t13\n", asm_out_file);
12922 fputs ("__lr\tRN\t14\n", asm_out_file);
12923 fputs ("__pc\tRN\t15\n", asm_out_file);
12924 fputs ("__f0\tFN\t0\n", asm_out_file);
12925 fputs ("__f1\tFN\t1\n", asm_out_file);
12926 fputs ("__f2\tFN\t2\n", asm_out_file);
12927 fputs ("__f3\tFN\t3\n", asm_out_file);
12928 fputs ("__f4\tFN\t4\n", asm_out_file);
12929 fputs ("__f5\tFN\t5\n", asm_out_file);
12930 fputs ("__f6\tFN\t6\n", asm_out_file);
12931 fputs ("__f7\tFN\t7\n", asm_out_file);
12936 aof_file_end (void)
12939 aof_dump_pic_table (asm_out_file);
12940 aof_dump_imports (asm_out_file);
12941 fputs ("\tEND\n", asm_out_file);
12943 #endif /* AOF_ASSEMBLER */
12945 #ifdef OBJECT_FORMAT_ELF
12946 /* Switch to an arbitrary section NAME with attributes as specified
12947 by FLAGS. ALIGN specifies any known alignment requirements for
12948 the section; 0 if the default should be used.
12950 Differs from the default elf version only in the prefix character
12951 used before the section type. */
12954 arm_elf_asm_named_section (const char *name, unsigned int flags)
12956 char flagchars[10], *f = flagchars;
12958 if (! named_section_first_declaration (name))
12960 fprintf (asm_out_file, "\t.section\t%s\n", name);
12964 if (!(flags & SECTION_DEBUG))
12966 if (flags & SECTION_WRITE)
12968 if (flags & SECTION_CODE)
12970 if (flags & SECTION_SMALL)
12972 if (flags & SECTION_MERGE)
12974 if (flags & SECTION_STRINGS)
12976 if (flags & SECTION_TLS)
12980 fprintf (asm_out_file, "\t.section\t%s,\"%s\"", name, flagchars);
12982 if (!(flags & SECTION_NOTYPE))
12986 if (flags & SECTION_BSS)
12991 fprintf (asm_out_file, ",%%%s", type);
12993 if (flags & SECTION_ENTSIZE)
12994 fprintf (asm_out_file, ",%d", flags & SECTION_ENTSIZE);
12997 putc ('\n', asm_out_file);
13002 /* Symbols in the text segment can be accessed without indirecting via the
13003 constant pool; it may take an extra binary operation, but this is still
13004 faster than indirecting via memory. Don't do this when not optimizing,
13005 since we won't be calculating al of the offsets necessary to do this
13009 arm_encode_section_info (tree decl, rtx rtl, int first)
13011 /* This doesn't work with AOF syntax, since the string table may be in
13012 a different AREA. */
13013 #ifndef AOF_ASSEMBLER
13014 if (optimize > 0 && TREE_CONSTANT (decl)
13015 && (!flag_writable_strings || TREE_CODE (decl) != STRING_CST))
13016 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;
13019 /* If we are referencing a function that is weak then encode a long call
13020 flag in the function name, otherwise if the function is static or
13021 or known to be defined in this file then encode a short call flag. */
13022 if (first && TREE_CODE_CLASS (TREE_CODE (decl)) == 'd')
13024 if (TREE_CODE (decl) == FUNCTION_DECL && DECL_WEAK (decl))
13025 arm_encode_call_attribute (decl, LONG_CALL_FLAG_CHAR);
13026 else if (! TREE_PUBLIC (decl))
13027 arm_encode_call_attribute (decl, SHORT_CALL_FLAG_CHAR);
13030 #endif /* !ARM_PE */
13033 arm_internal_label (FILE *stream, const char *prefix, unsigned long labelno)
13035 if (arm_ccfsm_state == 3 && (unsigned) arm_target_label == labelno
13036 && !strcmp (prefix, "L"))
13038 arm_ccfsm_state = 0;
13039 arm_target_insn = NULL;
13041 default_internal_label (stream, prefix, labelno);
13044 /* Output code to add DELTA to the first argument, and then jump
13045 to FUNCTION. Used for C++ multiple inheritance. */
13047 arm_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
13048 HOST_WIDE_INT delta,
13049 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
13052 int mi_delta = delta;
13053 const char *const mi_op = mi_delta < 0 ? "sub" : "add";
13055 int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)
13058 mi_delta = - mi_delta;
13059 while (mi_delta != 0)
13061 if ((mi_delta & (3 << shift)) == 0)
13065 asm_fprintf (file, "\t%s\t%r, %r, #%d\n",
13066 mi_op, this_regno, this_regno,
13067 mi_delta & (0xff << shift));
13068 mi_delta &= ~(0xff << shift);
13072 fputs ("\tb\t", file);
13073 assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0));
13074 if (NEED_PLT_RELOC)
13075 fputs ("(PLT)", file);
13076 fputc ('\n', file);
13080 arm_emit_vector_const (FILE *file, rtx x)
13083 const char * pattern;
13085 if (GET_CODE (x) != CONST_VECTOR)
13088 switch (GET_MODE (x))
13090 case V2SImode: pattern = "%08x"; break;
13091 case V4HImode: pattern = "%04x"; break;
13092 case V8QImode: pattern = "%02x"; break;
13096 fprintf (file, "0x");
13097 for (i = CONST_VECTOR_NUNITS (x); i--;)
13101 element = CONST_VECTOR_ELT (x, i);
13102 fprintf (file, pattern, INTVAL (element));
13109 arm_output_load_gr (rtx *operands)
13116 if (GET_CODE (operands [1]) != MEM
13117 || GET_CODE (sum = XEXP (operands [1], 0)) != PLUS
13118 || GET_CODE (reg = XEXP (sum, 0)) != REG
13119 || GET_CODE (offset = XEXP (sum, 1)) != CONST_INT
13120 || ((INTVAL (offset) < 1024) && (INTVAL (offset) > -1024)))
13121 return "wldrw%?\t%0, %1";
13123 /* Fix up an out-of-range load of a GR register. */
13124 output_asm_insn ("str%?\t%0, [sp, #-4]!\t@ Start of GR load expansion", & reg);
13125 wcgr = operands[0];
13127 output_asm_insn ("ldr%?\t%0, %1", operands);
13129 operands[0] = wcgr;
13131 output_asm_insn ("tmcr%?\t%0, %1", operands);
13132 output_asm_insn ("ldr%?\t%0, [sp], #4\t@ End of GR load expansion", & reg);