1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it
11 under the terms of the GNU General Public License as published
12 by the Free Software Foundation; either version 2, or (at your
13 option) any later version.
15 GCC is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
27 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
38 #include "insn-attr.h"
49 #include "integrate.h"
52 #include "target-def.h"
54 #include "langhooks.h"
56 /* Forward definitions of types. */
57 typedef struct minipool_node Mnode;
58 typedef struct minipool_fixup Mfix;
60 const struct attribute_spec arm_attribute_table[];
62 /* Forward function declarations. */
63 static arm_stack_offsets *arm_get_frame_offsets (void);
64 static void arm_add_gc_roots (void);
65 static int arm_gen_constant (enum rtx_code, enum machine_mode, rtx,
66 HOST_WIDE_INT, rtx, rtx, int, int);
67 static unsigned bit_count (unsigned long);
68 static int arm_address_register_rtx_p (rtx, int);
69 static int arm_legitimate_index_p (enum machine_mode, rtx, RTX_CODE, int);
70 static int thumb_base_register_rtx_p (rtx, enum machine_mode, int);
71 inline static int thumb_index_register_rtx_p (rtx, int);
72 static int thumb_far_jump_used_p (void);
73 static bool thumb_force_lr_save (void);
74 static unsigned long thumb_compute_save_reg_mask (void);
75 static int const_ok_for_op (HOST_WIDE_INT, enum rtx_code);
76 static rtx emit_multi_reg_push (int);
77 static rtx emit_sfm (int, int);
79 static bool arm_assemble_integer (rtx, unsigned int, int);
81 static const char *fp_const_from_val (REAL_VALUE_TYPE *);
82 static arm_cc get_arm_condition_code (rtx);
83 static HOST_WIDE_INT int_log2 (HOST_WIDE_INT);
84 static rtx is_jump_table (rtx);
85 static const char *output_multi_immediate (rtx *, const char *, const char *,
87 static void print_multi_reg (FILE *, const char *, int, int);
88 static const char *shift_op (rtx, HOST_WIDE_INT *);
89 static struct machine_function *arm_init_machine_status (void);
90 static int number_of_first_bit_set (int);
91 static void replace_symbols_in_block (tree, rtx, rtx);
92 static void thumb_exit (FILE *, int);
93 static void thumb_pushpop (FILE *, int, int, int *, int);
94 static rtx is_jump_table (rtx);
95 static HOST_WIDE_INT get_jump_table_size (rtx);
96 static Mnode *move_minipool_fix_forward_ref (Mnode *, Mnode *, HOST_WIDE_INT);
97 static Mnode *add_minipool_forward_ref (Mfix *);
98 static Mnode *move_minipool_fix_backward_ref (Mnode *, Mnode *, HOST_WIDE_INT);
99 static Mnode *add_minipool_backward_ref (Mfix *);
100 static void assign_minipool_offsets (Mfix *);
101 static void arm_print_value (FILE *, rtx);
102 static void dump_minipool (rtx);
103 static int arm_barrier_cost (rtx);
104 static Mfix *create_fix_barrier (Mfix *, HOST_WIDE_INT);
105 static void push_minipool_barrier (rtx, HOST_WIDE_INT);
106 static void push_minipool_fix (rtx, HOST_WIDE_INT, rtx *, enum machine_mode,
108 static void arm_reorg (void);
109 static bool note_invalid_constants (rtx, HOST_WIDE_INT, int);
110 static int current_file_function_operand (rtx);
111 static unsigned long arm_compute_save_reg0_reg12_mask (void);
112 static unsigned long arm_compute_save_reg_mask (void);
113 static unsigned long arm_isr_value (tree);
114 static unsigned long arm_compute_func_type (void);
115 static tree arm_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
116 static tree arm_handle_isr_attribute (tree *, tree, tree, int, bool *);
117 static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT);
118 static void arm_output_function_prologue (FILE *, HOST_WIDE_INT);
119 static void thumb_output_function_prologue (FILE *, HOST_WIDE_INT);
120 static int arm_comp_type_attributes (tree, tree);
121 static void arm_set_default_type_attributes (tree);
122 static int arm_adjust_cost (rtx, rtx, rtx, int);
123 static int count_insns_for_constant (HOST_WIDE_INT, int);
124 static int arm_get_strip_length (int);
125 static bool arm_function_ok_for_sibcall (tree, tree);
126 static void arm_internal_label (FILE *, const char *, unsigned long);
127 static void arm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
129 static int arm_rtx_costs_1 (rtx, enum rtx_code, enum rtx_code);
130 static bool arm_size_rtx_costs (rtx, int, int, int *);
131 static bool arm_slowmul_rtx_costs (rtx, int, int, int *);
132 static bool arm_fastmul_rtx_costs (rtx, int, int, int *);
133 static bool arm_xscale_rtx_costs (rtx, int, int, int *);
134 static bool arm_9e_rtx_costs (rtx, int, int, int *);
135 static int arm_address_cost (rtx);
136 static bool arm_memory_load_p (rtx);
137 static bool arm_cirrus_insn_p (rtx);
138 static void cirrus_reorg (rtx);
139 static void arm_init_builtins (void);
140 static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
141 static void arm_init_iwmmxt_builtins (void);
142 static rtx safe_vector_operand (rtx, enum machine_mode);
143 static rtx arm_expand_binop_builtin (enum insn_code, tree, rtx);
144 static rtx arm_expand_unop_builtin (enum insn_code, tree, rtx, int);
145 static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
146 static void emit_constant_insn (rtx cond, rtx pattern);
148 #ifdef OBJECT_FORMAT_ELF
149 static void arm_elf_asm_named_section (const char *, unsigned int);
152 static void arm_encode_section_info (tree, rtx, int);
155 static void aof_globalize_label (FILE *, const char *);
156 static void aof_dump_imports (FILE *);
157 static void aof_dump_pic_table (FILE *);
158 static void aof_file_start (void);
159 static void aof_file_end (void);
161 static rtx arm_struct_value_rtx (tree, int);
162 static void arm_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
164 static bool arm_pass_by_reference (CUMULATIVE_ARGS *,
165 enum machine_mode, tree, bool);
166 static bool arm_promote_prototypes (tree);
167 static bool arm_default_short_enums (void);
168 static bool arm_align_anon_bitfield (void);
170 static tree arm_cxx_guard_type (void);
171 static bool arm_cxx_guard_mask_bit (void);
172 static tree arm_get_cookie_size (tree);
173 static bool arm_cookie_has_size (void);
174 static bool arm_cxx_cdtor_returns_this (void);
175 static void arm_init_libfuncs (void);
178 /* Initialize the GCC target structure. */
179 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
180 #undef TARGET_MERGE_DECL_ATTRIBUTES
181 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
184 #undef TARGET_ATTRIBUTE_TABLE
185 #define TARGET_ATTRIBUTE_TABLE arm_attribute_table
188 #undef TARGET_ASM_BYTE_OP
189 #define TARGET_ASM_BYTE_OP "\tDCB\t"
190 #undef TARGET_ASM_ALIGNED_HI_OP
191 #define TARGET_ASM_ALIGNED_HI_OP "\tDCW\t"
192 #undef TARGET_ASM_ALIGNED_SI_OP
193 #define TARGET_ASM_ALIGNED_SI_OP "\tDCD\t"
194 #undef TARGET_ASM_GLOBALIZE_LABEL
195 #define TARGET_ASM_GLOBALIZE_LABEL aof_globalize_label
196 #undef TARGET_ASM_FILE_START
197 #define TARGET_ASM_FILE_START aof_file_start
198 #undef TARGET_ASM_FILE_END
199 #define TARGET_ASM_FILE_END aof_file_end
201 #undef TARGET_ASM_ALIGNED_SI_OP
202 #define TARGET_ASM_ALIGNED_SI_OP NULL
203 #undef TARGET_ASM_INTEGER
204 #define TARGET_ASM_INTEGER arm_assemble_integer
207 #undef TARGET_ASM_FUNCTION_PROLOGUE
208 #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue
210 #undef TARGET_ASM_FUNCTION_EPILOGUE
211 #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue
213 #undef TARGET_COMP_TYPE_ATTRIBUTES
214 #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes
216 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
217 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes
219 #undef TARGET_SCHED_ADJUST_COST
220 #define TARGET_SCHED_ADJUST_COST arm_adjust_cost
222 #undef TARGET_ENCODE_SECTION_INFO
224 #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info
226 #define TARGET_ENCODE_SECTION_INFO arm_encode_section_info
229 #undef TARGET_STRIP_NAME_ENCODING
230 #define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding
232 #undef TARGET_ASM_INTERNAL_LABEL
233 #define TARGET_ASM_INTERNAL_LABEL arm_internal_label
235 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
236 #define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall
238 #undef TARGET_ASM_OUTPUT_MI_THUNK
239 #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk
240 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
241 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
243 /* This will be overridden in arm_override_options. */
244 #undef TARGET_RTX_COSTS
245 #define TARGET_RTX_COSTS arm_slowmul_rtx_costs
246 #undef TARGET_ADDRESS_COST
247 #define TARGET_ADDRESS_COST arm_address_cost
249 #undef TARGET_MACHINE_DEPENDENT_REORG
250 #define TARGET_MACHINE_DEPENDENT_REORG arm_reorg
252 #undef TARGET_INIT_BUILTINS
253 #define TARGET_INIT_BUILTINS arm_init_builtins
254 #undef TARGET_EXPAND_BUILTIN
255 #define TARGET_EXPAND_BUILTIN arm_expand_builtin
257 #undef TARGET_INIT_LIBFUNCS
258 #define TARGET_INIT_LIBFUNCS arm_init_libfuncs
260 #undef TARGET_PROMOTE_FUNCTION_ARGS
261 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
262 #undef TARGET_PROMOTE_FUNCTION_RETURN
263 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
264 #undef TARGET_PROMOTE_PROTOTYPES
265 #define TARGET_PROMOTE_PROTOTYPES arm_promote_prototypes
266 #undef TARGET_PASS_BY_REFERENCE
267 #define TARGET_PASS_BY_REFERENCE arm_pass_by_reference
269 #undef TARGET_STRUCT_VALUE_RTX
270 #define TARGET_STRUCT_VALUE_RTX arm_struct_value_rtx
272 #undef TARGET_SETUP_INCOMING_VARARGS
273 #define TARGET_SETUP_INCOMING_VARARGS arm_setup_incoming_varargs
275 #undef TARGET_DEFAULT_SHORT_ENUMS
276 #define TARGET_DEFAULT_SHORT_ENUMS arm_default_short_enums
278 #undef TARGET_ALIGN_ANON_BITFIELD
279 #define TARGET_ALIGN_ANON_BITFIELD arm_align_anon_bitfield
281 #undef TARGET_CXX_GUARD_TYPE
282 #define TARGET_CXX_GUARD_TYPE arm_cxx_guard_type
284 #undef TARGET_CXX_GUARD_MASK_BIT
285 #define TARGET_CXX_GUARD_MASK_BIT arm_cxx_guard_mask_bit
287 #undef TARGET_CXX_GET_COOKIE_SIZE
288 #define TARGET_CXX_GET_COOKIE_SIZE arm_get_cookie_size
290 #undef TARGET_CXX_COOKIE_HAS_SIZE
291 #define TARGET_CXX_COOKIE_HAS_SIZE arm_cookie_has_size
293 #undef TARGET_CXX_CDTOR_RETURNS_THIS
294 #define TARGET_CXX_CDTOR_RETURNS_THIS arm_cxx_cdtor_returns_this
296 struct gcc_target targetm = TARGET_INITIALIZER;
298 /* Obstack for minipool constant handling. */
299 static struct obstack minipool_obstack;
300 static char * minipool_startobj;
302 /* The maximum number of insns skipped which
303 will be conditionalised if possible. */
304 static int max_insns_skipped = 5;
306 extern FILE * asm_out_file;
308 /* True if we are currently building a constant table. */
309 int making_const_table;
311 /* Define the information needed to generate branch insns. This is
312 stored from the compare operation. */
313 rtx arm_compare_op0, arm_compare_op1;
315 /* The processor for which instructions should be scheduled. */
316 enum processor_type arm_tune = arm_none;
318 /* Which floating point model to use. */
319 enum arm_fp_model arm_fp_model;
321 /* Which floating point hardware is available. */
322 enum fputype arm_fpu_arch;
324 /* Which floating point hardware to schedule for. */
325 enum fputype arm_fpu_tune;
327 /* Whether to use floating point hardware. */
328 enum float_abi_type arm_float_abi;
330 /* Which ABI to use. */
331 enum arm_abi_type arm_abi;
333 /* Set by the -mfpu=... option. */
334 const char * target_fpu_name = NULL;
336 /* Set by the -mfpe=... option. */
337 const char * target_fpe_name = NULL;
339 /* Set by the -mfloat-abi=... option. */
340 const char * target_float_abi_name = NULL;
342 /* Set by the -mabi=... option. */
343 const char * target_abi_name = NULL;
345 /* Used to parse -mstructure_size_boundary command line option. */
346 const char * structure_size_string = NULL;
347 int arm_structure_size_boundary = DEFAULT_STRUCTURE_SIZE_BOUNDARY;
349 /* Bit values used to identify processor capabilities. */
350 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
351 #define FL_ARCH3M (1 << 1) /* Extended multiply */
352 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
353 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
354 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
355 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
356 #define FL_THUMB (1 << 6) /* Thumb aware */
357 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
358 #define FL_STRONG (1 << 8) /* StrongARM */
359 #define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */
360 #define FL_XSCALE (1 << 10) /* XScale */
361 #define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */
362 #define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds
363 media instructions. */
364 #define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */
366 #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
368 #define FL_FOR_ARCH2 0
369 #define FL_FOR_ARCH3 FL_MODE32
370 #define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M)
371 #define FL_FOR_ARCH4 (FL_FOR_ARCH3M | FL_ARCH4)
372 #define FL_FOR_ARCH4T (FL_FOR_ARCH4 | FL_THUMB)
373 #define FL_FOR_ARCH5 (FL_FOR_ARCH4 | FL_ARCH5)
374 #define FL_FOR_ARCH5T (FL_FOR_ARCH5 | FL_THUMB)
375 #define FL_FOR_ARCH5E (FL_FOR_ARCH5 | FL_ARCH5E)
376 #define FL_FOR_ARCH5TE (FL_FOR_ARCH5E | FL_THUMB)
377 #define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE
378 #define FL_FOR_ARCH6 (FL_FOR_ARCH5TE | FL_ARCH6)
379 #define FL_FOR_ARCH6J FL_FOR_ARCH6
381 /* The bits in this mask specify which
382 instructions we are allowed to generate. */
383 static unsigned long insn_flags = 0;
385 /* The bits in this mask specify which instruction scheduling options should
387 static unsigned long tune_flags = 0;
389 /* The following are used in the arm.md file as equivalents to bits
390 in the above two flag variables. */
392 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
395 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
398 /* Nonzero if this chip supports the ARM Architecture 4t extensions. */
401 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
404 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
407 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
410 /* Nonzero if this chip can benefit from load scheduling. */
411 int arm_ld_sched = 0;
413 /* Nonzero if this chip is a StrongARM. */
414 int arm_is_strong = 0;
416 /* Nonzero if this chip is a Cirrus variant. */
417 int arm_arch_cirrus = 0;
419 /* Nonzero if this chip supports Intel Wireless MMX technology. */
420 int arm_arch_iwmmxt = 0;
422 /* Nonzero if this chip is an XScale. */
423 int arm_arch_xscale = 0;
425 /* Nonzero if tuning for XScale */
426 int arm_tune_xscale = 0;
428 /* Nonzero if this chip is an ARM6 or an ARM7. */
429 int arm_is_6_or_7 = 0;
431 /* Nonzero if generating Thumb instructions. */
434 /* Nonzero if we should define __THUMB_INTERWORK__ in the
436 XXX This is a bit of a hack, it's intended to help work around
437 problems in GLD which doesn't understand that armv5t code is
438 interworking clean. */
439 int arm_cpp_interwork = 0;
441 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
442 must report the mode of the memory reference from PRINT_OPERAND to
443 PRINT_OPERAND_ADDRESS. */
444 enum machine_mode output_memory_reference_mode;
446 /* The register number to be used for the PIC offset register. */
447 const char * arm_pic_register_string = NULL;
448 int arm_pic_register = INVALID_REGNUM;
450 /* Set to 1 when a return insn is output, this means that the epilogue
452 int return_used_this_function;
454 /* Set to 1 after arm_reorg has started. Reset to start at the start of
455 the next function. */
456 static int after_arm_reorg = 0;
458 /* The maximum number of insns to be used when loading a constant. */
459 static int arm_constant_limit = 3;
461 /* For an explanation of these variables, see final_prescan_insn below. */
463 enum arm_cond_code arm_current_cc;
465 int arm_target_label;
467 /* The condition codes of the ARM, and the inverse function. */
468 static const char * const arm_condition_codes[] =
470 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
471 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
474 #define streq(string1, string2) (strcmp (string1, string2) == 0)
476 /* Initialization code. */
480 const char *const name;
481 enum processor_type core;
483 const unsigned long flags;
484 bool (* rtx_costs) (rtx, int, int, int *);
487 /* Not all of these give usefully different compilation alternatives,
488 but there is no simple way of generalizing them. */
489 static const struct processors all_cores[] =
492 #define ARM_CORE(NAME, ARCH, FLAGS, COSTS) \
493 {#NAME, arm_none, #ARCH, FLAGS | FL_FOR_ARCH##ARCH, arm_##COSTS##_rtx_costs},
494 #include "arm-cores.def"
496 {NULL, arm_none, NULL, 0, NULL}
499 static const struct processors all_architectures[] =
501 /* ARM Architectures */
502 /* We don't specify rtx_costs here as it will be figured out
505 {"armv2", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL},
506 {"armv2a", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL},
507 {"armv3", arm6, "3", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3, NULL},
508 {"armv3m", arm7m, "3M", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3M, NULL},
509 {"armv4", arm7tdmi, "4", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH4, NULL},
510 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
511 implementations that support it, so we will leave it out for now. */
512 {"armv4t", arm7tdmi, "4T", FL_CO_PROC | FL_FOR_ARCH4T, NULL},
513 {"armv5", arm10tdmi, "5", FL_CO_PROC | FL_FOR_ARCH5, NULL},
514 {"armv5t", arm10tdmi, "5T", FL_CO_PROC | FL_FOR_ARCH5T, NULL},
515 {"armv5e", arm1026ejs, "5E", FL_CO_PROC | FL_FOR_ARCH5E, NULL},
516 {"armv5te", arm1026ejs, "5TE", FL_CO_PROC | FL_FOR_ARCH5TE, NULL},
517 {"armv6", arm1136js, "6", FL_CO_PROC | FL_FOR_ARCH6, NULL},
518 {"armv6j", arm1136js, "6J", FL_CO_PROC | FL_FOR_ARCH6J, NULL},
519 {"ep9312", ep9312, "4T", FL_LDSCHED | FL_CIRRUS | FL_FOR_ARCH4, NULL},
520 {"iwmmxt", iwmmxt, "5TE", FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT , NULL},
521 {NULL, arm_none, NULL, 0 , NULL}
524 /* This is a magic structure. The 'string' field is magically filled in
525 with a pointer to the value specified by the user on the command line
526 assuming that the user has specified such a value. */
528 struct arm_cpu_select arm_select[] =
530 /* string name processors */
531 { NULL, "-mcpu=", all_cores },
532 { NULL, "-march=", all_architectures },
533 { NULL, "-mtune=", all_cores }
537 /* The name of the proprocessor macro to define for this architecture. */
539 char arm_arch_name[] = "__ARM_ARCH_0UNK__";
548 /* Available values for for -mfpu=. */
550 static const struct fpu_desc all_fpus[] =
552 {"fpa", FPUTYPE_FPA},
553 {"fpe2", FPUTYPE_FPA_EMU2},
554 {"fpe3", FPUTYPE_FPA_EMU2},
555 {"maverick", FPUTYPE_MAVERICK},
560 /* Floating point models used by the different hardware.
561 See fputype in arm.h. */
563 static const enum fputype fp_model_for_fpu[] =
565 /* No FP hardware. */
566 ARM_FP_MODEL_UNKNOWN, /* FPUTYPE_NONE */
567 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA */
568 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA_EMU2 */
569 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA_EMU3 */
570 ARM_FP_MODEL_MAVERICK, /* FPUTYPE_MAVERICK */
571 ARM_FP_MODEL_VFP /* FPUTYPE_VFP */
578 enum float_abi_type abi_type;
582 /* Available values for -mfloat-abi=. */
584 static const struct float_abi all_float_abis[] =
586 {"soft", ARM_FLOAT_ABI_SOFT},
587 {"softfp", ARM_FLOAT_ABI_SOFTFP},
588 {"hard", ARM_FLOAT_ABI_HARD}
595 enum arm_abi_type abi_type;
599 /* Available values for -mabi=. */
601 static const struct abi_name arm_all_abis[] =
603 {"apcs-gnu", ARM_ABI_APCS},
604 {"atpcs", ARM_ABI_ATPCS},
605 {"aapcs", ARM_ABI_AAPCS},
606 {"iwmmxt", ARM_ABI_IWMMXT}
609 /* Return the number of bits set in VALUE. */
611 bit_count (unsigned long value)
613 unsigned long count = 0;
618 value &= value - 1; /* Clear the least-significant set bit. */
624 /* Set up library functions uqniue to ARM. */
627 arm_init_libfuncs (void)
629 /* There are no special library functions unless we are using the
634 /* The functions below are described in Section 4 of the "Run-Time
635 ABI for the ARM architecture", Version 1.0. */
637 /* Double-precision floating-point arithmetic. Table 2. */
638 set_optab_libfunc (add_optab, DFmode, "__aeabi_dadd");
639 set_optab_libfunc (sdiv_optab, DFmode, "__aeabi_ddiv");
640 set_optab_libfunc (smul_optab, DFmode, "__aeabi_dmul");
641 set_optab_libfunc (neg_optab, DFmode, "__aeabi_dneg");
642 set_optab_libfunc (sub_optab, DFmode, "__aeabi_dsub");
644 /* Double-precision comparisions. Table 3. */
645 set_optab_libfunc (eq_optab, DFmode, "__aeabi_dcmpeq");
646 set_optab_libfunc (ne_optab, DFmode, NULL);
647 set_optab_libfunc (lt_optab, DFmode, "__aeabi_dcmplt");
648 set_optab_libfunc (le_optab, DFmode, "__aeabi_dcmple");
649 set_optab_libfunc (ge_optab, DFmode, "__aeabi_dcmpge");
650 set_optab_libfunc (gt_optab, DFmode, "__aeabi_dcmpgt");
651 set_optab_libfunc (unord_optab, DFmode, "__aeabi_dcmpun");
653 /* Single-precision floating-point arithmetic. Table 4. */
654 set_optab_libfunc (add_optab, SFmode, "__aeabi_fadd");
655 set_optab_libfunc (sdiv_optab, SFmode, "__aeabi_fdiv");
656 set_optab_libfunc (smul_optab, SFmode, "__aeabi_fmul");
657 set_optab_libfunc (neg_optab, SFmode, "__aeabi_fneg");
658 set_optab_libfunc (sub_optab, SFmode, "__aeabi_fsub");
660 /* Single-precision comparisions. Table 5. */
661 set_optab_libfunc (eq_optab, SFmode, "__aeabi_fcmpeq");
662 set_optab_libfunc (ne_optab, SFmode, NULL);
663 set_optab_libfunc (lt_optab, SFmode, "__aeabi_fcmplt");
664 set_optab_libfunc (le_optab, SFmode, "__aeabi_fcmple");
665 set_optab_libfunc (ge_optab, SFmode, "__aeabi_fcmpge");
666 set_optab_libfunc (gt_optab, SFmode, "__aeabi_fcmpgt");
667 set_optab_libfunc (unord_optab, SFmode, "__aeabi_fcmpun");
669 /* Floating-point to integer conversions. Table 6. */
670 set_conv_libfunc (sfix_optab, SImode, DFmode, "__aeabi_d2iz");
671 set_conv_libfunc (ufix_optab, SImode, DFmode, "__aeabi_d2uiz");
672 set_conv_libfunc (sfix_optab, DImode, DFmode, "__aeabi_d2lz");
673 set_conv_libfunc (ufix_optab, DImode, DFmode, "__aeabi_d2ulz");
674 set_conv_libfunc (sfix_optab, SImode, SFmode, "__aeabi_f2iz");
675 set_conv_libfunc (ufix_optab, SImode, SFmode, "__aeabi_f2uiz");
676 set_conv_libfunc (sfix_optab, DImode, SFmode, "__aeabi_f2lz");
677 set_conv_libfunc (ufix_optab, DImode, SFmode, "__aeabi_f2ulz");
679 /* Conversions between floating types. Table 7. */
680 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__aeabi_d2f");
681 set_conv_libfunc (sext_optab, DFmode, SFmode, "__aeabi_f2d");
683 /* Integer to floating-point converisons. Table 8. */
684 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__aeabi_i2d");
685 set_conv_libfunc (ufloat_optab, DFmode, SImode, "__aeabi_ui2d");
686 set_conv_libfunc (sfloat_optab, DFmode, DImode, "__aeabi_l2d");
687 set_conv_libfunc (ufloat_optab, DFmode, DImode, "__aeabi_ul2d");
688 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__aeabi_i2f");
689 set_conv_libfunc (ufloat_optab, SFmode, SImode, "__aeabi_ui2f");
690 set_conv_libfunc (sfloat_optab, SFmode, DImode, "__aeabi_l2f");
691 set_conv_libfunc (ufloat_optab, SFmode, DImode, "__aeabi_ul2f");
693 /* Long long. Table 9. */
694 set_optab_libfunc (smul_optab, DImode, "__aeabi_lmul");
695 set_optab_libfunc (sdivmod_optab, DImode, "__aeabi_ldivmod");
696 set_optab_libfunc (udivmod_optab, DImode, "__aeabi_uldivmod");
697 set_optab_libfunc (ashl_optab, DImode, "__aeabi_llsl");
698 set_optab_libfunc (lshr_optab, DImode, "__aeabi_llsr");
699 set_optab_libfunc (ashr_optab, DImode, "__aeabi_lasr");
700 set_optab_libfunc (cmp_optab, DImode, "__aeabi_lcmp");
701 set_optab_libfunc (ucmp_optab, DImode, "__aeabi_ulcmp");
703 /* Integer (32/32->32) division. \S 4.3.1. */
704 set_optab_libfunc (sdivmod_optab, SImode, "__aeabi_idivmod");
705 set_optab_libfunc (udivmod_optab, SImode, "__aeabi_uidivmod");
707 /* The divmod functions are designed so that they can be used for
708 plain division, even though they return both the quotient and the
709 remainder. The quotient is returned in the usual location (i.e.,
710 r0 for SImode, {r0, r1} for DImode), just as would be expected
711 for an ordinary division routine. Because the AAPCS calling
712 conventions specify that all of { r0, r1, r2, r3 } are
713 callee-saved registers, there is no need to tell the compiler
714 explicitly that those registers are clobbered by these
716 set_optab_libfunc (sdiv_optab, DImode, "__aeabi_ldivmod");
717 set_optab_libfunc (udiv_optab, DImode, "__aeabi_uldivmod");
718 set_optab_libfunc (sdiv_optab, SImode, "__aeabi_idivmod");
719 set_optab_libfunc (udiv_optab, SImode, "__aeabi_uidivmod");
722 /* Fix up any incompatible options that the user has specified.
723 This has now turned into a maze. */
725 arm_override_options (void)
729 /* Set up the flags based on the cpu/architecture selected by the user. */
730 for (i = ARRAY_SIZE (arm_select); i--;)
732 struct arm_cpu_select * ptr = arm_select + i;
734 if (ptr->string != NULL && ptr->string[0] != '\0')
736 const struct processors * sel;
738 for (sel = ptr->processors; sel->name != NULL; sel++)
739 if (streq (ptr->string, sel->name))
741 /* Set the architecture define. */
743 sprintf (arm_arch_name, "__ARM_ARCH_%s__", sel->arch);
745 /* Determine the processor core for which we should
746 tune code-generation. */
747 if (/* -mcpu= is a sensible default. */
749 /* If -march= is used, and -mcpu= has not been used,
750 assume that we should tune for a representative
751 CPU from that architecture. */
753 /* -mtune= overrides -mcpu= and -march=. */
755 arm_tune = (enum processor_type) (sel - ptr->processors);
759 /* If we have been given an architecture and a processor
760 make sure that they are compatible. We only generate
761 a warning though, and we prefer the CPU over the
763 if (insn_flags != 0 && (insn_flags ^ sel->flags))
764 warning ("switch -mcpu=%s conflicts with -march= switch",
767 insn_flags = sel->flags;
773 if (sel->name == NULL)
774 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
778 /* If the user did not specify a processor, choose one for them. */
781 const struct processors * sel;
783 enum processor_type cpu;
785 cpu = TARGET_CPU_DEFAULT;
788 #ifdef SUBTARGET_CPU_DEFAULT
789 /* Use the subtarget default CPU if none was specified by
791 cpu = SUBTARGET_CPU_DEFAULT;
793 /* Default to ARM6. */
797 sel = &all_cores[cpu];
799 insn_flags = sel->flags;
801 /* Now check to see if the user has specified some command line
802 switch that require certain abilities from the cpu. */
805 if (TARGET_INTERWORK || TARGET_THUMB)
807 sought |= (FL_THUMB | FL_MODE32);
809 /* There are no ARM processors that support both APCS-26 and
810 interworking. Therefore we force FL_MODE26 to be removed
811 from insn_flags here (if it was set), so that the search
812 below will always be able to find a compatible processor. */
813 insn_flags &= ~FL_MODE26;
816 if (sought != 0 && ((sought & insn_flags) != sought))
818 /* Try to locate a CPU type that supports all of the abilities
819 of the default CPU, plus the extra abilities requested by
821 for (sel = all_cores; sel->name != NULL; sel++)
822 if ((sel->flags & sought) == (sought | insn_flags))
825 if (sel->name == NULL)
827 unsigned current_bit_count = 0;
828 const struct processors * best_fit = NULL;
830 /* Ideally we would like to issue an error message here
831 saying that it was not possible to find a CPU compatible
832 with the default CPU, but which also supports the command
833 line options specified by the programmer, and so they
834 ought to use the -mcpu=<name> command line option to
835 override the default CPU type.
837 If we cannot find a cpu that has both the
838 characteristics of the default cpu and the given
839 command line options we scan the array again looking
841 for (sel = all_cores; sel->name != NULL; sel++)
842 if ((sel->flags & sought) == sought)
846 count = bit_count (sel->flags & insn_flags);
848 if (count >= current_bit_count)
851 current_bit_count = count;
855 if (best_fit == NULL)
861 insn_flags = sel->flags;
863 sprintf (arm_arch_name, "__ARM_ARCH_%s__", sel->arch);
864 if (arm_tune == arm_none)
865 arm_tune = (enum processor_type) (sel - all_cores);
868 /* The processor for which we should tune should now have been
870 if (arm_tune == arm_none)
873 tune_flags = all_cores[(int)arm_tune].flags;
875 targetm.rtx_costs = arm_size_rtx_costs;
877 targetm.rtx_costs = all_cores[(int)arm_tune].rtx_costs;
879 /* Make sure that the processor choice does not conflict with any of the
880 other command line choices. */
881 if (TARGET_INTERWORK && !(insn_flags & FL_THUMB))
883 warning ("target CPU does not support interworking" );
884 target_flags &= ~ARM_FLAG_INTERWORK;
887 if (TARGET_THUMB && !(insn_flags & FL_THUMB))
889 warning ("target CPU does not support THUMB instructions");
890 target_flags &= ~ARM_FLAG_THUMB;
893 if (TARGET_APCS_FRAME && TARGET_THUMB)
895 /* warning ("ignoring -mapcs-frame because -mthumb was used"); */
896 target_flags &= ~ARM_FLAG_APCS_FRAME;
899 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
900 from here where no function is being compiled currently. */
901 if ((target_flags & (THUMB_FLAG_LEAF_BACKTRACE | THUMB_FLAG_BACKTRACE))
903 warning ("enabling backtrace support is only meaningful when compiling for the Thumb");
905 if (TARGET_ARM && TARGET_CALLEE_INTERWORKING)
906 warning ("enabling callee interworking support is only meaningful when compiling for the Thumb");
908 if (TARGET_ARM && TARGET_CALLER_INTERWORKING)
909 warning ("enabling caller interworking support is only meaningful when compiling for the Thumb");
911 if (TARGET_APCS_STACK && !TARGET_APCS_FRAME)
913 warning ("-mapcs-stack-check incompatible with -mno-apcs-frame");
914 target_flags |= ARM_FLAG_APCS_FRAME;
917 if (TARGET_POKE_FUNCTION_NAME)
918 target_flags |= ARM_FLAG_APCS_FRAME;
920 if (TARGET_APCS_REENT && flag_pic)
921 error ("-fpic and -mapcs-reent are incompatible");
923 if (TARGET_APCS_REENT)
924 warning ("APCS reentrant code not supported. Ignored");
926 /* If this target is normally configured to use APCS frames, warn if they
927 are turned off and debugging is turned on. */
929 && write_symbols != NO_DEBUG
930 && !TARGET_APCS_FRAME
931 && (TARGET_DEFAULT & ARM_FLAG_APCS_FRAME))
932 warning ("-g with -mno-apcs-frame may not give sensible debugging");
934 /* If stack checking is disabled, we can use r10 as the PIC register,
935 which keeps r9 available. */
937 arm_pic_register = TARGET_APCS_STACK ? 9 : 10;
939 if (TARGET_APCS_FLOAT)
940 warning ("passing floating point arguments in fp regs not yet supported");
942 /* Initialize boolean versions of the flags, for use in the arm.md file. */
943 arm_arch3m = (insn_flags & FL_ARCH3M) != 0;
944 arm_arch4 = (insn_flags & FL_ARCH4) != 0;
945 arm_arch4t = arm_arch4 & ((insn_flags & FL_THUMB) != 0);
946 arm_arch5 = (insn_flags & FL_ARCH5) != 0;
947 arm_arch5e = (insn_flags & FL_ARCH5E) != 0;
948 arm_arch6 = (insn_flags & FL_ARCH6) != 0;
949 arm_arch_xscale = (insn_flags & FL_XSCALE) != 0;
950 arm_arch_cirrus = (insn_flags & FL_CIRRUS) != 0;
952 arm_ld_sched = (tune_flags & FL_LDSCHED) != 0;
953 arm_is_strong = (tune_flags & FL_STRONG) != 0;
954 thumb_code = (TARGET_ARM == 0);
955 arm_is_6_or_7 = (((tune_flags & (FL_MODE26 | FL_MODE32))
956 && !(tune_flags & FL_ARCH4))) != 0;
957 arm_tune_xscale = (tune_flags & FL_XSCALE) != 0;
958 arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0;
960 /* V5 code we generate is completely interworking capable, so we turn off
961 TARGET_INTERWORK here to avoid many tests later on. */
963 /* XXX However, we must pass the right pre-processor defines to CPP
964 or GLD can get confused. This is a hack. */
965 if (TARGET_INTERWORK)
966 arm_cpp_interwork = 1;
969 target_flags &= ~ARM_FLAG_INTERWORK;
973 for (i = 0; i < ARRAY_SIZE (arm_all_abis); i++)
975 if (streq (arm_all_abis[i].name, target_abi_name))
977 arm_abi = arm_all_abis[i].abi_type;
981 if (i == ARRAY_SIZE (arm_all_abis))
982 error ("invalid ABI option: -mabi=%s", target_abi_name);
985 arm_abi = ARM_DEFAULT_ABI;
987 if (TARGET_IWMMXT && !ARM_DOUBLEWORD_ALIGN)
988 error ("iwmmxt requires an AAPCS compatible ABI for proper operation");
990 if (TARGET_IWMMXT_ABI && !TARGET_IWMMXT)
991 error ("iwmmxt abi requires an iwmmxt capable cpu");
993 arm_fp_model = ARM_FP_MODEL_UNKNOWN;
994 if (target_fpu_name == NULL && target_fpe_name != NULL)
996 if (streq (target_fpe_name, "2"))
997 target_fpu_name = "fpe2";
998 else if (streq (target_fpe_name, "3"))
999 target_fpu_name = "fpe3";
1001 error ("invalid floating point emulation option: -mfpe=%s",
1004 if (target_fpu_name != NULL)
1006 /* The user specified a FPU. */
1007 for (i = 0; i < ARRAY_SIZE (all_fpus); i++)
1009 if (streq (all_fpus[i].name, target_fpu_name))
1011 arm_fpu_arch = all_fpus[i].fpu;
1012 arm_fpu_tune = arm_fpu_arch;
1013 arm_fp_model = fp_model_for_fpu[arm_fpu_arch];
1017 if (arm_fp_model == ARM_FP_MODEL_UNKNOWN)
1018 error ("invalid floating point option: -mfpu=%s", target_fpu_name);
1022 #ifdef FPUTYPE_DEFAULT
1023 /* Use the default if it is specified for this platform. */
1024 arm_fpu_arch = FPUTYPE_DEFAULT;
1025 arm_fpu_tune = FPUTYPE_DEFAULT;
1027 /* Pick one based on CPU type. */
1028 /* ??? Some targets assume FPA is the default.
1029 if ((insn_flags & FL_VFP) != 0)
1030 arm_fpu_arch = FPUTYPE_VFP;
1033 if (arm_arch_cirrus)
1034 arm_fpu_arch = FPUTYPE_MAVERICK;
1036 arm_fpu_arch = FPUTYPE_FPA_EMU2;
1038 if (tune_flags & FL_CO_PROC && arm_fpu_arch == FPUTYPE_FPA_EMU2)
1039 arm_fpu_tune = FPUTYPE_FPA;
1041 arm_fpu_tune = arm_fpu_arch;
1042 arm_fp_model = fp_model_for_fpu[arm_fpu_arch];
1043 if (arm_fp_model == ARM_FP_MODEL_UNKNOWN)
1047 if (target_float_abi_name != NULL)
1049 /* The user specified a FP ABI. */
1050 for (i = 0; i < ARRAY_SIZE (all_float_abis); i++)
1052 if (streq (all_float_abis[i].name, target_float_abi_name))
1054 arm_float_abi = all_float_abis[i].abi_type;
1058 if (i == ARRAY_SIZE (all_float_abis))
1059 error ("invalid floating point abi: -mfloat-abi=%s",
1060 target_float_abi_name);
1064 /* Use soft-float target flag. */
1065 if (target_flags & ARM_FLAG_SOFT_FLOAT)
1066 arm_float_abi = ARM_FLOAT_ABI_SOFT;
1068 arm_float_abi = ARM_FLOAT_ABI_HARD;
1071 if (arm_float_abi == ARM_FLOAT_ABI_SOFTFP)
1072 sorry ("-mfloat-abi=softfp");
1073 /* If soft-float is specified then don't use FPU. */
1074 if (TARGET_SOFT_FLOAT)
1075 arm_fpu_arch = FPUTYPE_NONE;
1077 /* For arm2/3 there is no need to do any scheduling if there is only
1078 a floating point emulator, or we are doing software floating-point. */
1079 if ((TARGET_SOFT_FLOAT
1080 || arm_fpu_tune == FPUTYPE_FPA_EMU2
1081 || arm_fpu_tune == FPUTYPE_FPA_EMU3)
1082 && (tune_flags & FL_MODE32) == 0)
1083 flag_schedule_insns = flag_schedule_insns_after_reload = 0;
1085 /* Override the default structure alignment for AAPCS ABI. */
1086 if (arm_abi == ARM_ABI_AAPCS)
1087 arm_structure_size_boundary = 8;
1089 if (structure_size_string != NULL)
1091 int size = strtol (structure_size_string, NULL, 0);
1093 if (size == 8 || size == 32
1094 || (ARM_DOUBLEWORD_ALIGN && size == 64))
1095 arm_structure_size_boundary = size;
1097 warning ("structure size boundary can only be set to %s",
1098 ARM_DOUBLEWORD_ALIGN ? "8, 32 or 64": "8 or 32");
1101 if (arm_pic_register_string != NULL)
1103 int pic_register = decode_reg_name (arm_pic_register_string);
1106 warning ("-mpic-register= is useless without -fpic");
1108 /* Prevent the user from choosing an obviously stupid PIC register. */
1109 else if (pic_register < 0 || call_used_regs[pic_register]
1110 || pic_register == HARD_FRAME_POINTER_REGNUM
1111 || pic_register == STACK_POINTER_REGNUM
1112 || pic_register >= PC_REGNUM)
1113 error ("unable to use '%s' for PIC register", arm_pic_register_string);
1115 arm_pic_register = pic_register;
1118 if (TARGET_THUMB && flag_schedule_insns)
1120 /* Don't warn since it's on by default in -O2. */
1121 flag_schedule_insns = 0;
1126 /* There's some dispute as to whether this should be 1 or 2. However,
1127 experiments seem to show that in pathological cases a setting of
1128 1 degrades less severely than a setting of 2. This could change if
1129 other parts of the compiler change their behavior. */
1130 arm_constant_limit = 1;
1132 /* If optimizing for size, bump the number of instructions that we
1133 are prepared to conditionally execute (even on a StrongARM). */
1134 max_insns_skipped = 6;
1138 /* For processors with load scheduling, it never costs more than
1139 2 cycles to load a constant, and the load scheduler may well
1140 reduce that to 1. */
1141 if (tune_flags & FL_LDSCHED)
1142 arm_constant_limit = 1;
1144 /* On XScale the longer latency of a load makes it more difficult
1145 to achieve a good schedule, so it's faster to synthesize
1146 constants that can be done in two insns. */
1147 if (arm_tune_xscale)
1148 arm_constant_limit = 2;
1150 /* StrongARM has early execution of branches, so a sequence
1151 that is worth skipping is shorter. */
1153 max_insns_skipped = 3;
1156 /* Register global variables with the garbage collector. */
1157 arm_add_gc_roots ();
1161 arm_add_gc_roots (void)
1163 gcc_obstack_init(&minipool_obstack);
1164 minipool_startobj = (char *) obstack_alloc (&minipool_obstack, 0);
1167 /* A table of known ARM exception types.
1168 For use with the interrupt function attribute. */
1172 const char *const arg;
1173 const unsigned long return_value;
1177 static const isr_attribute_arg isr_attribute_args [] =
1179 { "IRQ", ARM_FT_ISR },
1180 { "irq", ARM_FT_ISR },
1181 { "FIQ", ARM_FT_FIQ },
1182 { "fiq", ARM_FT_FIQ },
1183 { "ABORT", ARM_FT_ISR },
1184 { "abort", ARM_FT_ISR },
1185 { "ABORT", ARM_FT_ISR },
1186 { "abort", ARM_FT_ISR },
1187 { "UNDEF", ARM_FT_EXCEPTION },
1188 { "undef", ARM_FT_EXCEPTION },
1189 { "SWI", ARM_FT_EXCEPTION },
1190 { "swi", ARM_FT_EXCEPTION },
1191 { NULL, ARM_FT_NORMAL }
1194 /* Returns the (interrupt) function type of the current
1195 function, or ARM_FT_UNKNOWN if the type cannot be determined. */
1197 static unsigned long
1198 arm_isr_value (tree argument)
1200 const isr_attribute_arg * ptr;
1203 /* No argument - default to IRQ. */
1204 if (argument == NULL_TREE)
1207 /* Get the value of the argument. */
1208 if (TREE_VALUE (argument) == NULL_TREE
1209 || TREE_CODE (TREE_VALUE (argument)) != STRING_CST)
1210 return ARM_FT_UNKNOWN;
1212 arg = TREE_STRING_POINTER (TREE_VALUE (argument));
1214 /* Check it against the list of known arguments. */
1215 for (ptr = isr_attribute_args; ptr->arg != NULL; ptr++)
1216 if (streq (arg, ptr->arg))
1217 return ptr->return_value;
1219 /* An unrecognized interrupt type. */
1220 return ARM_FT_UNKNOWN;
1223 /* Computes the type of the current function. */
1225 static unsigned long
1226 arm_compute_func_type (void)
1228 unsigned long type = ARM_FT_UNKNOWN;
1232 if (TREE_CODE (current_function_decl) != FUNCTION_DECL)
1235 /* Decide if the current function is volatile. Such functions
1236 never return, and many memory cycles can be saved by not storing
1237 register values that will never be needed again. This optimization
1238 was added to speed up context switching in a kernel application. */
1240 && TREE_NOTHROW (current_function_decl)
1241 && TREE_THIS_VOLATILE (current_function_decl))
1242 type |= ARM_FT_VOLATILE;
1244 if (cfun->static_chain_decl != NULL)
1245 type |= ARM_FT_NESTED;
1247 attr = DECL_ATTRIBUTES (current_function_decl);
1249 a = lookup_attribute ("naked", attr);
1251 type |= ARM_FT_NAKED;
1253 a = lookup_attribute ("isr", attr);
1255 a = lookup_attribute ("interrupt", attr);
1258 type |= TARGET_INTERWORK ? ARM_FT_INTERWORKED : ARM_FT_NORMAL;
1260 type |= arm_isr_value (TREE_VALUE (a));
1265 /* Returns the type of the current function. */
1268 arm_current_func_type (void)
1270 if (ARM_FUNC_TYPE (cfun->machine->func_type) == ARM_FT_UNKNOWN)
1271 cfun->machine->func_type = arm_compute_func_type ();
1273 return cfun->machine->func_type;
1276 /* Return 1 if it is possible to return using a single instruction.
1277 If SIBLING is non-null, this is a test for a return before a sibling
1278 call. SIBLING is the call insn, so we can examine its register usage. */
1281 use_return_insn (int iscond, rtx sibling)
1284 unsigned int func_type;
1285 unsigned long saved_int_regs;
1286 unsigned HOST_WIDE_INT stack_adjust;
1287 arm_stack_offsets *offsets;
1289 /* Never use a return instruction before reload has run. */
1290 if (!reload_completed)
1293 func_type = arm_current_func_type ();
1295 /* Naked functions and volatile functions need special
1297 if (func_type & (ARM_FT_VOLATILE | ARM_FT_NAKED))
1300 /* So do interrupt functions that use the frame pointer. */
1301 if (IS_INTERRUPT (func_type) && frame_pointer_needed)
1304 offsets = arm_get_frame_offsets ();
1305 stack_adjust = offsets->outgoing_args - offsets->saved_regs;
1307 /* As do variadic functions. */
1308 if (current_function_pretend_args_size
1309 || cfun->machine->uses_anonymous_args
1310 /* Or if the function calls __builtin_eh_return () */
1311 || current_function_calls_eh_return
1312 /* Or if the function calls alloca */
1313 || current_function_calls_alloca
1314 /* Or if there is a stack adjustment. However, if the stack pointer
1315 is saved on the stack, we can use a pre-incrementing stack load. */
1316 || !(stack_adjust == 0 || (frame_pointer_needed && stack_adjust == 4)))
1319 saved_int_regs = arm_compute_save_reg_mask ();
1321 /* Unfortunately, the insn
1323 ldmib sp, {..., sp, ...}
1325 triggers a bug on most SA-110 based devices, such that the stack
1326 pointer won't be correctly restored if the instruction takes a
1327 page fault. We work around this problem by popping r3 along with
1328 the other registers, since that is never slower than executing
1329 another instruction.
1331 We test for !arm_arch5 here, because code for any architecture
1332 less than this could potentially be run on one of the buggy
1334 if (stack_adjust == 4 && !arm_arch5)
1336 /* Validate that r3 is a call-clobbered register (always true in
1337 the default abi) ... */
1338 if (!call_used_regs[3])
1341 /* ... that it isn't being used for a return value (always true
1342 until we implement return-in-regs), or for a tail-call
1346 if (GET_CODE (sibling) != CALL_INSN)
1349 if (find_regno_fusage (sibling, USE, 3))
1353 /* ... and that there are no call-saved registers in r0-r2
1354 (always true in the default ABI). */
1355 if (saved_int_regs & 0x7)
1359 /* Can't be done if interworking with Thumb, and any registers have been
1361 if (TARGET_INTERWORK && saved_int_regs != 0)
1364 /* On StrongARM, conditional returns are expensive if they aren't
1365 taken and multiple registers have been stacked. */
1366 if (iscond && arm_is_strong)
1368 /* Conditional return when just the LR is stored is a simple
1369 conditional-load instruction, that's not expensive. */
1370 if (saved_int_regs != 0 && saved_int_regs != (1 << LR_REGNUM))
1373 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
1377 /* If there are saved registers but the LR isn't saved, then we need
1378 two instructions for the return. */
1379 if (saved_int_regs && !(saved_int_regs & (1 << LR_REGNUM)))
1382 /* Can't be done if any of the FPA regs are pushed,
1383 since this also requires an insn. */
1384 if (TARGET_HARD_FLOAT && TARGET_FPA)
1385 for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++)
1386 if (regs_ever_live[regno] && !call_used_regs[regno])
1389 /* Likewise VFP regs. */
1390 if (TARGET_HARD_FLOAT && TARGET_VFP)
1391 for (regno = FIRST_VFP_REGNUM; regno <= LAST_VFP_REGNUM; regno++)
1392 if (regs_ever_live[regno] && !call_used_regs[regno])
1395 if (TARGET_REALLY_IWMMXT)
1396 for (regno = FIRST_IWMMXT_REGNUM; regno <= LAST_IWMMXT_REGNUM; regno++)
1397 if (regs_ever_live[regno] && ! call_used_regs [regno])
1403 /* Return TRUE if int I is a valid immediate ARM constant. */
1406 const_ok_for_arm (HOST_WIDE_INT i)
1408 unsigned HOST_WIDE_INT mask = ~(unsigned HOST_WIDE_INT)0xFF;
1410 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
1411 be all zero, or all one. */
1412 if ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0
1413 && ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff)
1414 != ((~(unsigned HOST_WIDE_INT) 0)
1415 & ~(unsigned HOST_WIDE_INT) 0xffffffff)))
1418 /* Fast return for 0 and powers of 2 */
1419 if ((i & (i - 1)) == 0)
1424 if ((i & mask & (unsigned HOST_WIDE_INT) 0xffffffff) == 0)
1427 (mask << 2) | ((mask & (unsigned HOST_WIDE_INT) 0xffffffff)
1428 >> (32 - 2)) | ~(unsigned HOST_WIDE_INT) 0xffffffff;
1430 while (mask != ~(unsigned HOST_WIDE_INT) 0xFF);
1435 /* Return true if I is a valid constant for the operation CODE. */
1437 const_ok_for_op (HOST_WIDE_INT i, enum rtx_code code)
1439 if (const_ok_for_arm (i))
1445 return const_ok_for_arm (ARM_SIGN_EXTEND (-i));
1447 case MINUS: /* Should only occur with (MINUS I reg) => rsb */
1453 return const_ok_for_arm (ARM_SIGN_EXTEND (~i));
1460 /* Emit a sequence of insns to handle a large constant.
1461 CODE is the code of the operation required, it can be any of SET, PLUS,
1462 IOR, AND, XOR, MINUS;
1463 MODE is the mode in which the operation is being performed;
1464 VAL is the integer to operate on;
1465 SOURCE is the other operand (a register, or a null-pointer for SET);
1466 SUBTARGETS means it is safe to create scratch registers if that will
1467 either produce a simpler sequence, or we will want to cse the values.
1468 Return value is the number of insns emitted. */
1471 arm_split_constant (enum rtx_code code, enum machine_mode mode, rtx insn,
1472 HOST_WIDE_INT val, rtx target, rtx source, int subtargets)
1476 if (insn && GET_CODE (PATTERN (insn)) == COND_EXEC)
1477 cond = COND_EXEC_TEST (PATTERN (insn));
1481 if (subtargets || code == SET
1482 || (GET_CODE (target) == REG && GET_CODE (source) == REG
1483 && REGNO (target) != REGNO (source)))
1485 /* After arm_reorg has been called, we can't fix up expensive
1486 constants by pushing them into memory so we must synthesize
1487 them in-line, regardless of the cost. This is only likely to
1488 be more costly on chips that have load delay slots and we are
1489 compiling without running the scheduler (so no splitting
1490 occurred before the final instruction emission).
1492 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
1494 if (!after_arm_reorg
1496 && (arm_gen_constant (code, mode, NULL_RTX, val, target, source,
1498 > arm_constant_limit + (code != SET)))
1502 /* Currently SET is the only monadic value for CODE, all
1503 the rest are diadic. */
1504 emit_insn (gen_rtx_SET (VOIDmode, target, GEN_INT (val)));
1509 rtx temp = subtargets ? gen_reg_rtx (mode) : target;
1511 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (val)));
1512 /* For MINUS, the value is subtracted from, since we never
1513 have subtraction of a constant. */
1515 emit_insn (gen_rtx_SET (VOIDmode, target,
1516 gen_rtx_MINUS (mode, temp, source)));
1518 emit_insn (gen_rtx_SET (VOIDmode, target,
1519 gen_rtx_fmt_ee (code, mode, source, temp)));
1525 return arm_gen_constant (code, mode, cond, val, target, source, subtargets,
1530 count_insns_for_constant (HOST_WIDE_INT remainder, int i)
1532 HOST_WIDE_INT temp1;
1540 if (remainder & (3 << (i - 2)))
1545 temp1 = remainder & ((0x0ff << end)
1546 | ((i < end) ? (0xff >> (32 - end)) : 0));
1547 remainder &= ~temp1;
1552 } while (remainder);
1556 /* Emit an instruction with the indicated PATTERN. If COND is
1557 non-NULL, conditionalize the execution of the instruction on COND
1561 emit_constant_insn (rtx cond, rtx pattern)
1564 pattern = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (cond), pattern);
1565 emit_insn (pattern);
1568 /* As above, but extra parameter GENERATE which, if clear, suppresses
1572 arm_gen_constant (enum rtx_code code, enum machine_mode mode, rtx cond,
1573 HOST_WIDE_INT val, rtx target, rtx source, int subtargets,
1578 int can_negate_initial = 0;
1581 int num_bits_set = 0;
1582 int set_sign_bit_copies = 0;
1583 int clear_sign_bit_copies = 0;
1584 int clear_zero_bit_copies = 0;
1585 int set_zero_bit_copies = 0;
1587 unsigned HOST_WIDE_INT temp1, temp2;
1588 unsigned HOST_WIDE_INT remainder = val & 0xffffffff;
1590 /* Find out which operations are safe for a given CODE. Also do a quick
1591 check for degenerate cases; these can occur when DImode operations
1603 can_negate_initial = 1;
1607 if (remainder == 0xffffffff)
1610 emit_constant_insn (cond,
1611 gen_rtx_SET (VOIDmode, target,
1612 GEN_INT (ARM_SIGN_EXTEND (val))));
1617 if (reload_completed && rtx_equal_p (target, source))
1620 emit_constant_insn (cond,
1621 gen_rtx_SET (VOIDmode, target, source));
1630 emit_constant_insn (cond,
1631 gen_rtx_SET (VOIDmode, target, const0_rtx));
1634 if (remainder == 0xffffffff)
1636 if (reload_completed && rtx_equal_p (target, source))
1639 emit_constant_insn (cond,
1640 gen_rtx_SET (VOIDmode, target, source));
1649 if (reload_completed && rtx_equal_p (target, source))
1652 emit_constant_insn (cond,
1653 gen_rtx_SET (VOIDmode, target, source));
1656 if (remainder == 0xffffffff)
1659 emit_constant_insn (cond,
1660 gen_rtx_SET (VOIDmode, target,
1661 gen_rtx_NOT (mode, source)));
1665 /* We don't know how to handle this yet below. */
1669 /* We treat MINUS as (val - source), since (source - val) is always
1670 passed as (source + (-val)). */
1674 emit_constant_insn (cond,
1675 gen_rtx_SET (VOIDmode, target,
1676 gen_rtx_NEG (mode, source)));
1679 if (const_ok_for_arm (val))
1682 emit_constant_insn (cond,
1683 gen_rtx_SET (VOIDmode, target,
1684 gen_rtx_MINUS (mode, GEN_INT (val),
1696 /* If we can do it in one insn get out quickly. */
1697 if (const_ok_for_arm (val)
1698 || (can_negate_initial && const_ok_for_arm (-val))
1699 || (can_invert && const_ok_for_arm (~val)))
1702 emit_constant_insn (cond,
1703 gen_rtx_SET (VOIDmode, target,
1705 ? gen_rtx_fmt_ee (code, mode, source,
1711 /* Calculate a few attributes that may be useful for specific
1713 for (i = 31; i >= 0; i--)
1715 if ((remainder & (1 << i)) == 0)
1716 clear_sign_bit_copies++;
1721 for (i = 31; i >= 0; i--)
1723 if ((remainder & (1 << i)) != 0)
1724 set_sign_bit_copies++;
1729 for (i = 0; i <= 31; i++)
1731 if ((remainder & (1 << i)) == 0)
1732 clear_zero_bit_copies++;
1737 for (i = 0; i <= 31; i++)
1739 if ((remainder & (1 << i)) != 0)
1740 set_zero_bit_copies++;
1748 /* See if we can do this by sign_extending a constant that is known
1749 to be negative. This is a good, way of doing it, since the shift
1750 may well merge into a subsequent insn. */
1751 if (set_sign_bit_copies > 1)
1753 if (const_ok_for_arm
1754 (temp1 = ARM_SIGN_EXTEND (remainder
1755 << (set_sign_bit_copies - 1))))
1759 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1760 emit_constant_insn (cond,
1761 gen_rtx_SET (VOIDmode, new_src,
1763 emit_constant_insn (cond,
1764 gen_ashrsi3 (target, new_src,
1765 GEN_INT (set_sign_bit_copies - 1)));
1769 /* For an inverted constant, we will need to set the low bits,
1770 these will be shifted out of harm's way. */
1771 temp1 |= (1 << (set_sign_bit_copies - 1)) - 1;
1772 if (const_ok_for_arm (~temp1))
1776 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1777 emit_constant_insn (cond,
1778 gen_rtx_SET (VOIDmode, new_src,
1780 emit_constant_insn (cond,
1781 gen_ashrsi3 (target, new_src,
1782 GEN_INT (set_sign_bit_copies - 1)));
1788 /* See if we can generate this by setting the bottom (or the top)
1789 16 bits, and then shifting these into the other half of the
1790 word. We only look for the simplest cases, to do more would cost
1791 too much. Be careful, however, not to generate this when the
1792 alternative would take fewer insns. */
1793 if (val & 0xffff0000)
1795 temp1 = remainder & 0xffff0000;
1796 temp2 = remainder & 0x0000ffff;
1798 /* Overlaps outside this range are best done using other methods. */
1799 for (i = 9; i < 24; i++)
1801 if ((((temp2 | (temp2 << i)) & 0xffffffff) == remainder)
1802 && !const_ok_for_arm (temp2))
1804 rtx new_src = (subtargets
1805 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
1807 insns = arm_gen_constant (code, mode, cond, temp2, new_src,
1808 source, subtargets, generate);
1816 gen_rtx_ASHIFT (mode, source,
1823 /* Don't duplicate cases already considered. */
1824 for (i = 17; i < 24; i++)
1826 if (((temp1 | (temp1 >> i)) == remainder)
1827 && !const_ok_for_arm (temp1))
1829 rtx new_src = (subtargets
1830 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
1832 insns = arm_gen_constant (code, mode, cond, temp1, new_src,
1833 source, subtargets, generate);
1838 gen_rtx_SET (VOIDmode, target,
1841 gen_rtx_LSHIFTRT (mode, source,
1852 /* If we have IOR or XOR, and the constant can be loaded in a
1853 single instruction, and we can find a temporary to put it in,
1854 then this can be done in two instructions instead of 3-4. */
1856 /* TARGET can't be NULL if SUBTARGETS is 0 */
1857 || (reload_completed && !reg_mentioned_p (target, source)))
1859 if (const_ok_for_arm (ARM_SIGN_EXTEND (~val)))
1863 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1865 emit_constant_insn (cond,
1866 gen_rtx_SET (VOIDmode, sub,
1868 emit_constant_insn (cond,
1869 gen_rtx_SET (VOIDmode, target,
1870 gen_rtx_fmt_ee (code, mode,
1880 if (set_sign_bit_copies > 8
1881 && (val & (-1 << (32 - set_sign_bit_copies))) == val)
1885 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1886 rtx shift = GEN_INT (set_sign_bit_copies);
1890 gen_rtx_SET (VOIDmode, sub,
1892 gen_rtx_ASHIFT (mode,
1897 gen_rtx_SET (VOIDmode, target,
1899 gen_rtx_LSHIFTRT (mode, sub,
1905 if (set_zero_bit_copies > 8
1906 && (remainder & ((1 << set_zero_bit_copies) - 1)) == remainder)
1910 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1911 rtx shift = GEN_INT (set_zero_bit_copies);
1915 gen_rtx_SET (VOIDmode, sub,
1917 gen_rtx_LSHIFTRT (mode,
1922 gen_rtx_SET (VOIDmode, target,
1924 gen_rtx_ASHIFT (mode, sub,
1930 if (const_ok_for_arm (temp1 = ARM_SIGN_EXTEND (~val)))
1934 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1935 emit_constant_insn (cond,
1936 gen_rtx_SET (VOIDmode, sub,
1937 gen_rtx_NOT (mode, source)));
1940 sub = gen_reg_rtx (mode);
1941 emit_constant_insn (cond,
1942 gen_rtx_SET (VOIDmode, sub,
1943 gen_rtx_AND (mode, source,
1945 emit_constant_insn (cond,
1946 gen_rtx_SET (VOIDmode, target,
1947 gen_rtx_NOT (mode, sub)));
1954 /* See if two shifts will do 2 or more insn's worth of work. */
1955 if (clear_sign_bit_copies >= 16 && clear_sign_bit_copies < 24)
1957 HOST_WIDE_INT shift_mask = ((0xffffffff
1958 << (32 - clear_sign_bit_copies))
1961 if ((remainder | shift_mask) != 0xffffffff)
1965 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1966 insns = arm_gen_constant (AND, mode, cond,
1967 remainder | shift_mask,
1968 new_src, source, subtargets, 1);
1973 rtx targ = subtargets ? NULL_RTX : target;
1974 insns = arm_gen_constant (AND, mode, cond,
1975 remainder | shift_mask,
1976 targ, source, subtargets, 0);
1982 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1983 rtx shift = GEN_INT (clear_sign_bit_copies);
1985 emit_insn (gen_ashlsi3 (new_src, source, shift));
1986 emit_insn (gen_lshrsi3 (target, new_src, shift));
1992 if (clear_zero_bit_copies >= 16 && clear_zero_bit_copies < 24)
1994 HOST_WIDE_INT shift_mask = (1 << clear_zero_bit_copies) - 1;
1996 if ((remainder | shift_mask) != 0xffffffff)
2000 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2002 insns = arm_gen_constant (AND, mode, cond,
2003 remainder | shift_mask,
2004 new_src, source, subtargets, 1);
2009 rtx targ = subtargets ? NULL_RTX : target;
2011 insns = arm_gen_constant (AND, mode, cond,
2012 remainder | shift_mask,
2013 targ, source, subtargets, 0);
2019 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
2020 rtx shift = GEN_INT (clear_zero_bit_copies);
2022 emit_insn (gen_lshrsi3 (new_src, source, shift));
2023 emit_insn (gen_ashlsi3 (target, new_src, shift));
2035 for (i = 0; i < 32; i++)
2036 if (remainder & (1 << i))
2039 if (code == AND || (can_invert && num_bits_set > 16))
2040 remainder = (~remainder) & 0xffffffff;
2041 else if (code == PLUS && num_bits_set > 16)
2042 remainder = (-remainder) & 0xffffffff;
2049 /* Now try and find a way of doing the job in either two or three
2051 We start by looking for the largest block of zeros that are aligned on
2052 a 2-bit boundary, we then fill up the temps, wrapping around to the
2053 top of the word when we drop off the bottom.
2054 In the worst case this code should produce no more than four insns. */
2057 int best_consecutive_zeros = 0;
2059 for (i = 0; i < 32; i += 2)
2061 int consecutive_zeros = 0;
2063 if (!(remainder & (3 << i)))
2065 while ((i < 32) && !(remainder & (3 << i)))
2067 consecutive_zeros += 2;
2070 if (consecutive_zeros > best_consecutive_zeros)
2072 best_consecutive_zeros = consecutive_zeros;
2073 best_start = i - consecutive_zeros;
2079 /* So long as it won't require any more insns to do so, it's
2080 desirable to emit a small constant (in bits 0...9) in the last
2081 insn. This way there is more chance that it can be combined with
2082 a later addressing insn to form a pre-indexed load or store
2083 operation. Consider:
2085 *((volatile int *)0xe0000100) = 1;
2086 *((volatile int *)0xe0000110) = 2;
2088 We want this to wind up as:
2092 str rB, [rA, #0x100]
2094 str rB, [rA, #0x110]
2096 rather than having to synthesize both large constants from scratch.
2098 Therefore, we calculate how many insns would be required to emit
2099 the constant starting from `best_start', and also starting from
2100 zero (ie with bit 31 first to be output). If `best_start' doesn't
2101 yield a shorter sequence, we may as well use zero. */
2103 && ((((unsigned HOST_WIDE_INT) 1) << best_start) < remainder)
2104 && (count_insns_for_constant (remainder, 0) <=
2105 count_insns_for_constant (remainder, best_start)))
2108 /* Now start emitting the insns. */
2116 if (remainder & (3 << (i - 2)))
2121 temp1 = remainder & ((0x0ff << end)
2122 | ((i < end) ? (0xff >> (32 - end)) : 0));
2123 remainder &= ~temp1;
2127 rtx new_src, temp1_rtx;
2129 if (code == SET || code == MINUS)
2131 new_src = (subtargets ? gen_reg_rtx (mode) : target);
2132 if (can_invert && code != MINUS)
2137 if (remainder && subtargets)
2138 new_src = gen_reg_rtx (mode);
2143 else if (can_negate)
2147 temp1 = trunc_int_for_mode (temp1, mode);
2148 temp1_rtx = GEN_INT (temp1);
2152 else if (code == MINUS)
2153 temp1_rtx = gen_rtx_MINUS (mode, temp1_rtx, source);
2155 temp1_rtx = gen_rtx_fmt_ee (code, mode, source, temp1_rtx);
2157 emit_constant_insn (cond,
2158 gen_rtx_SET (VOIDmode, new_src,
2168 else if (code == MINUS)
2182 /* Canonicalize a comparison so that we are more likely to recognize it.
2183 This can be done for a few constant compares, where we can make the
2184 immediate value easier to load. */
2187 arm_canonicalize_comparison (enum rtx_code code, rtx * op1)
2189 unsigned HOST_WIDE_INT i = INTVAL (*op1);
2199 if (i != ((((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1)) - 1)
2200 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
2202 *op1 = GEN_INT (i + 1);
2203 return code == GT ? GE : LT;
2209 if (i != (((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1))
2210 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
2212 *op1 = GEN_INT (i - 1);
2213 return code == GE ? GT : LE;
2219 if (i != ~((unsigned HOST_WIDE_INT) 0)
2220 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
2222 *op1 = GEN_INT (i + 1);
2223 return code == GTU ? GEU : LTU;
2230 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
2232 *op1 = GEN_INT (i - 1);
2233 return code == GEU ? GTU : LEU;
2245 /* Define how to find the value returned by a function. */
2247 rtx arm_function_value(tree type, tree func ATTRIBUTE_UNUSED)
2249 enum machine_mode mode;
2250 int unsignedp ATTRIBUTE_UNUSED;
2251 rtx r ATTRIBUTE_UNUSED;
2254 mode = TYPE_MODE (type);
2255 /* Promote integer types. */
2256 if (INTEGRAL_TYPE_P (type))
2257 PROMOTE_FUNCTION_MODE (mode, unsignedp, type);
2258 return LIBCALL_VALUE(mode);
2262 /* Decide whether a type should be returned in memory (true)
2263 or in a register (false). This is called by the macro
2264 RETURN_IN_MEMORY. */
2266 arm_return_in_memory (tree type)
2270 if (!AGGREGATE_TYPE_P (type))
2271 /* All simple types are returned in registers. */
2274 size = int_size_in_bytes (type);
2276 if (arm_abi != ARM_ABI_APCS)
2278 /* ATPCS and later return aggregate types in memory only if they are
2279 larger than a word (or are variable size). */
2280 return (size < 0 || size > UNITS_PER_WORD);
2283 /* For the arm-wince targets we choose to be compatible with Microsoft's
2284 ARM and Thumb compilers, which always return aggregates in memory. */
2286 /* All structures/unions bigger than one word are returned in memory.
2287 Also catch the case where int_size_in_bytes returns -1. In this case
2288 the aggregate is either huge or of variable size, and in either case
2289 we will want to return it via memory and not in a register. */
2290 if (size < 0 || size > UNITS_PER_WORD)
2293 if (TREE_CODE (type) == RECORD_TYPE)
2297 /* For a struct the APCS says that we only return in a register
2298 if the type is 'integer like' and every addressable element
2299 has an offset of zero. For practical purposes this means
2300 that the structure can have at most one non bit-field element
2301 and that this element must be the first one in the structure. */
2303 /* Find the first field, ignoring non FIELD_DECL things which will
2304 have been created by C++. */
2305 for (field = TYPE_FIELDS (type);
2306 field && TREE_CODE (field) != FIELD_DECL;
2307 field = TREE_CHAIN (field))
2311 return 0; /* An empty structure. Allowed by an extension to ANSI C. */
2313 /* Check that the first field is valid for returning in a register. */
2315 /* ... Floats are not allowed */
2316 if (FLOAT_TYPE_P (TREE_TYPE (field)))
2319 /* ... Aggregates that are not themselves valid for returning in
2320 a register are not allowed. */
2321 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
2324 /* Now check the remaining fields, if any. Only bitfields are allowed,
2325 since they are not addressable. */
2326 for (field = TREE_CHAIN (field);
2328 field = TREE_CHAIN (field))
2330 if (TREE_CODE (field) != FIELD_DECL)
2333 if (!DECL_BIT_FIELD_TYPE (field))
2340 if (TREE_CODE (type) == UNION_TYPE)
2344 /* Unions can be returned in registers if every element is
2345 integral, or can be returned in an integer register. */
2346 for (field = TYPE_FIELDS (type);
2348 field = TREE_CHAIN (field))
2350 if (TREE_CODE (field) != FIELD_DECL)
2353 if (FLOAT_TYPE_P (TREE_TYPE (field)))
2356 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
2362 #endif /* not ARM_WINCE */
2364 /* Return all other types in memory. */
2368 /* Indicate whether or not words of a double are in big-endian order. */
2371 arm_float_words_big_endian (void)
2373 if (TARGET_MAVERICK)
2376 /* For FPA, float words are always big-endian. For VFP, floats words
2377 follow the memory system mode. */
2385 return (TARGET_BIG_END ? 1 : 0);
2390 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2391 for a call to a function whose data type is FNTYPE.
2392 For a library call, FNTYPE is NULL. */
2394 arm_init_cumulative_args (CUMULATIVE_ARGS *pcum, tree fntype,
2395 rtx libname ATTRIBUTE_UNUSED,
2396 tree fndecl ATTRIBUTE_UNUSED)
2398 /* On the ARM, the offset starts at 0. */
2399 pcum->nregs = ((fntype && aggregate_value_p (TREE_TYPE (fntype), fntype)) ? 1 : 0);
2400 pcum->iwmmxt_nregs = 0;
2401 pcum->can_split = true;
2403 pcum->call_cookie = CALL_NORMAL;
2405 if (TARGET_LONG_CALLS)
2406 pcum->call_cookie = CALL_LONG;
2408 /* Check for long call/short call attributes. The attributes
2409 override any command line option. */
2412 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (fntype)))
2413 pcum->call_cookie = CALL_SHORT;
2414 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (fntype)))
2415 pcum->call_cookie = CALL_LONG;
2418 /* Varargs vectors are treated the same as long long.
2419 named_count avoids having to change the way arm handles 'named' */
2420 pcum->named_count = 0;
2423 if (TARGET_REALLY_IWMMXT && fntype)
2427 for (fn_arg = TYPE_ARG_TYPES (fntype);
2429 fn_arg = TREE_CHAIN (fn_arg))
2430 pcum->named_count += 1;
2432 if (! pcum->named_count)
2433 pcum->named_count = INT_MAX;
2438 /* Return true if mode/type need doubleword alignment. */
2440 arm_needs_doubleword_align (enum machine_mode mode, tree type)
2442 return (GET_MODE_ALIGNMENT (mode) > PARM_BOUNDARY
2443 || (type && TYPE_ALIGN (type) > PARM_BOUNDARY));
2447 /* Determine where to put an argument to a function.
2448 Value is zero to push the argument on the stack,
2449 or a hard register in which to store the argument.
2451 MODE is the argument's machine mode.
2452 TYPE is the data type of the argument (as a tree).
2453 This is null for libcalls where that information may
2455 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2456 the preceding args and about the function being called.
2457 NAMED is nonzero if this argument is a named parameter
2458 (otherwise it is an extra parameter matching an ellipsis). */
2461 arm_function_arg (CUMULATIVE_ARGS *pcum, enum machine_mode mode,
2462 tree type, int named)
2466 /* Varargs vectors are treated the same as long long.
2467 named_count avoids having to change the way arm handles 'named' */
2468 if (TARGET_IWMMXT_ABI
2469 && VECTOR_MODE_SUPPORTED_P (mode)
2470 && pcum->named_count > pcum->nargs + 1)
2472 if (pcum->iwmmxt_nregs <= 9)
2473 return gen_rtx_REG (mode, pcum->iwmmxt_nregs + FIRST_IWMMXT_REGNUM);
2476 pcum->can_split = false;
2481 /* Put doubleword aligned quantities in even register pairs. */
2483 && ARM_DOUBLEWORD_ALIGN
2484 && arm_needs_doubleword_align (mode, type))
2487 if (mode == VOIDmode)
2488 /* Compute operand 2 of the call insn. */
2489 return GEN_INT (pcum->call_cookie);
2491 /* Only allow splitting an arg between regs and memory if all preceding
2492 args were allocated to regs. For args passed by reference we only count
2493 the reference pointer. */
2494 if (pcum->can_split)
2497 nregs = ARM_NUM_REGS2 (mode, type);
2499 if (!named || pcum->nregs + nregs > NUM_ARG_REGS)
2502 return gen_rtx_REG (mode, pcum->nregs);
2505 /* Variable sized types are passed by reference. This is a GCC
2506 extension to the ARM ABI. */
2509 arm_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
2510 enum machine_mode mode ATTRIBUTE_UNUSED,
2511 tree type, bool named ATTRIBUTE_UNUSED)
2513 return type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST;
2516 /* Encode the current state of the #pragma [no_]long_calls. */
2519 OFF, /* No #pramgma [no_]long_calls is in effect. */
2520 LONG, /* #pragma long_calls is in effect. */
2521 SHORT /* #pragma no_long_calls is in effect. */
2524 static arm_pragma_enum arm_pragma_long_calls = OFF;
2527 arm_pr_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2529 arm_pragma_long_calls = LONG;
2533 arm_pr_no_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2535 arm_pragma_long_calls = SHORT;
2539 arm_pr_long_calls_off (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2541 arm_pragma_long_calls = OFF;
2544 /* Table of machine attributes. */
2545 const struct attribute_spec arm_attribute_table[] =
2547 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
2548 /* Function calls made to this symbol must be done indirectly, because
2549 it may lie outside of the 26 bit addressing range of a normal function
2551 { "long_call", 0, 0, false, true, true, NULL },
2552 /* Whereas these functions are always known to reside within the 26 bit
2553 addressing range. */
2554 { "short_call", 0, 0, false, true, true, NULL },
2555 /* Interrupt Service Routines have special prologue and epilogue requirements. */
2556 { "isr", 0, 1, false, false, false, arm_handle_isr_attribute },
2557 { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute },
2558 { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute },
2560 /* ARM/PE has three new attributes:
2562 dllexport - for exporting a function/variable that will live in a dll
2563 dllimport - for importing a function/variable from a dll
2565 Microsoft allows multiple declspecs in one __declspec, separating
2566 them with spaces. We do NOT support this. Instead, use __declspec
2569 { "dllimport", 0, 0, true, false, false, NULL },
2570 { "dllexport", 0, 0, true, false, false, NULL },
2571 { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute },
2572 #elif TARGET_DLLIMPORT_DECL_ATTRIBUTES
2573 { "dllimport", 0, 0, false, false, false, handle_dll_attribute },
2574 { "dllexport", 0, 0, false, false, false, handle_dll_attribute },
2576 { NULL, 0, 0, false, false, false, NULL }
2579 /* Handle an attribute requiring a FUNCTION_DECL;
2580 arguments as in struct attribute_spec.handler. */
2582 arm_handle_fndecl_attribute (tree *node, tree name, tree args ATTRIBUTE_UNUSED,
2583 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
2585 if (TREE_CODE (*node) != FUNCTION_DECL)
2587 warning ("`%s' attribute only applies to functions",
2588 IDENTIFIER_POINTER (name));
2589 *no_add_attrs = true;
2595 /* Handle an "interrupt" or "isr" attribute;
2596 arguments as in struct attribute_spec.handler. */
2598 arm_handle_isr_attribute (tree *node, tree name, tree args, int flags,
2603 if (TREE_CODE (*node) != FUNCTION_DECL)
2605 warning ("`%s' attribute only applies to functions",
2606 IDENTIFIER_POINTER (name));
2607 *no_add_attrs = true;
2609 /* FIXME: the argument if any is checked for type attributes;
2610 should it be checked for decl ones? */
2614 if (TREE_CODE (*node) == FUNCTION_TYPE
2615 || TREE_CODE (*node) == METHOD_TYPE)
2617 if (arm_isr_value (args) == ARM_FT_UNKNOWN)
2619 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
2620 *no_add_attrs = true;
2623 else if (TREE_CODE (*node) == POINTER_TYPE
2624 && (TREE_CODE (TREE_TYPE (*node)) == FUNCTION_TYPE
2625 || TREE_CODE (TREE_TYPE (*node)) == METHOD_TYPE)
2626 && arm_isr_value (args) != ARM_FT_UNKNOWN)
2628 *node = build_variant_type_copy (*node);
2629 TREE_TYPE (*node) = build_type_attribute_variant
2631 tree_cons (name, args, TYPE_ATTRIBUTES (TREE_TYPE (*node))));
2632 *no_add_attrs = true;
2636 /* Possibly pass this attribute on from the type to a decl. */
2637 if (flags & ((int) ATTR_FLAG_DECL_NEXT
2638 | (int) ATTR_FLAG_FUNCTION_NEXT
2639 | (int) ATTR_FLAG_ARRAY_NEXT))
2641 *no_add_attrs = true;
2642 return tree_cons (name, args, NULL_TREE);
2646 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
2654 /* Return 0 if the attributes for two types are incompatible, 1 if they
2655 are compatible, and 2 if they are nearly compatible (which causes a
2656 warning to be generated). */
2658 arm_comp_type_attributes (tree type1, tree type2)
2662 /* Check for mismatch of non-default calling convention. */
2663 if (TREE_CODE (type1) != FUNCTION_TYPE)
2666 /* Check for mismatched call attributes. */
2667 l1 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1)) != NULL;
2668 l2 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2)) != NULL;
2669 s1 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1)) != NULL;
2670 s2 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2)) != NULL;
2672 /* Only bother to check if an attribute is defined. */
2673 if (l1 | l2 | s1 | s2)
2675 /* If one type has an attribute, the other must have the same attribute. */
2676 if ((l1 != l2) || (s1 != s2))
2679 /* Disallow mixed attributes. */
2680 if ((l1 & s2) || (l2 & s1))
2684 /* Check for mismatched ISR attribute. */
2685 l1 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type1)) != NULL;
2687 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1)) != NULL;
2688 l2 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type2)) != NULL;
2690 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2)) != NULL;
2697 /* Encode long_call or short_call attribute by prefixing
2698 symbol name in DECL with a special character FLAG. */
2700 arm_encode_call_attribute (tree decl, int flag)
2702 const char * str = XSTR (XEXP (DECL_RTL (decl), 0), 0);
2703 int len = strlen (str);
2706 /* Do not allow weak functions to be treated as short call. */
2707 if (DECL_WEAK (decl) && flag == SHORT_CALL_FLAG_CHAR)
2710 newstr = alloca (len + 2);
2712 strcpy (newstr + 1, str);
2714 newstr = (char *) ggc_alloc_string (newstr, len + 1);
2715 XSTR (XEXP (DECL_RTL (decl), 0), 0) = newstr;
2718 /* Assigns default attributes to newly defined type. This is used to
2719 set short_call/long_call attributes for function types of
2720 functions defined inside corresponding #pragma scopes. */
2722 arm_set_default_type_attributes (tree type)
2724 /* Add __attribute__ ((long_call)) to all functions, when
2725 inside #pragma long_calls or __attribute__ ((short_call)),
2726 when inside #pragma no_long_calls. */
2727 if (TREE_CODE (type) == FUNCTION_TYPE || TREE_CODE (type) == METHOD_TYPE)
2729 tree type_attr_list, attr_name;
2730 type_attr_list = TYPE_ATTRIBUTES (type);
2732 if (arm_pragma_long_calls == LONG)
2733 attr_name = get_identifier ("long_call");
2734 else if (arm_pragma_long_calls == SHORT)
2735 attr_name = get_identifier ("short_call");
2739 type_attr_list = tree_cons (attr_name, NULL_TREE, type_attr_list);
2740 TYPE_ATTRIBUTES (type) = type_attr_list;
2744 /* Return 1 if the operand is a SYMBOL_REF for a function known to be
2745 defined within the current compilation unit. If this cannot be
2746 determined, then 0 is returned. */
2748 current_file_function_operand (rtx sym_ref)
2750 /* This is a bit of a fib. A function will have a short call flag
2751 applied to its name if it has the short call attribute, or it has
2752 already been defined within the current compilation unit. */
2753 if (ENCODED_SHORT_CALL_ATTR_P (XSTR (sym_ref, 0)))
2756 /* The current function is always defined within the current compilation
2757 unit. If it s a weak definition however, then this may not be the real
2758 definition of the function, and so we have to say no. */
2759 if (sym_ref == XEXP (DECL_RTL (current_function_decl), 0)
2760 && !DECL_WEAK (current_function_decl))
2763 /* We cannot make the determination - default to returning 0. */
2767 /* Return nonzero if a 32 bit "long_call" should be generated for
2768 this call. We generate a long_call if the function:
2770 a. has an __attribute__((long call))
2771 or b. is within the scope of a #pragma long_calls
2772 or c. the -mlong-calls command line switch has been specified
2774 1. -ffunction-sections is in effect
2775 or 2. the current function has __attribute__ ((section))
2776 or 3. the target function has __attribute__ ((section))
2778 However we do not generate a long call if the function:
2780 d. has an __attribute__ ((short_call))
2781 or e. is inside the scope of a #pragma no_long_calls
2782 or f. is defined within the current compilation unit.
2784 This function will be called by C fragments contained in the machine
2785 description file. SYM_REF and CALL_COOKIE correspond to the matched
2786 rtl operands. CALL_SYMBOL is used to distinguish between
2787 two different callers of the function. It is set to 1 in the
2788 "call_symbol" and "call_symbol_value" patterns and to 0 in the "call"
2789 and "call_value" patterns. This is because of the difference in the
2790 SYM_REFs passed by these patterns. */
2792 arm_is_longcall_p (rtx sym_ref, int call_cookie, int call_symbol)
2796 if (GET_CODE (sym_ref) != MEM)
2799 sym_ref = XEXP (sym_ref, 0);
2802 if (GET_CODE (sym_ref) != SYMBOL_REF)
2805 if (call_cookie & CALL_SHORT)
2808 if (TARGET_LONG_CALLS)
2810 if (flag_function_sections
2811 || DECL_SECTION_NAME (current_function_decl))
2812 /* c.3 is handled by the defintion of the
2813 ARM_DECLARE_FUNCTION_SIZE macro. */
2817 if (current_file_function_operand (sym_ref))
2820 return (call_cookie & CALL_LONG)
2821 || ENCODED_LONG_CALL_ATTR_P (XSTR (sym_ref, 0))
2822 || TARGET_LONG_CALLS;
2825 /* Return nonzero if it is ok to make a tail-call to DECL. */
2827 arm_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
2829 int call_type = TARGET_LONG_CALLS ? CALL_LONG : CALL_NORMAL;
2831 if (cfun->machine->sibcall_blocked)
2834 /* Never tailcall something for which we have no decl, or if we
2835 are in Thumb mode. */
2836 if (decl == NULL || TARGET_THUMB)
2839 /* Get the calling method. */
2840 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
2841 call_type = CALL_SHORT;
2842 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
2843 call_type = CALL_LONG;
2845 /* Cannot tail-call to long calls, since these are out of range of
2846 a branch instruction. However, if not compiling PIC, we know
2847 we can reach the symbol if it is in this compilation unit. */
2848 if (call_type == CALL_LONG && (flag_pic || !TREE_ASM_WRITTEN (decl)))
2851 /* If we are interworking and the function is not declared static
2852 then we can't tail-call it unless we know that it exists in this
2853 compilation unit (since it might be a Thumb routine). */
2854 if (TARGET_INTERWORK && TREE_PUBLIC (decl) && !TREE_ASM_WRITTEN (decl))
2857 /* Never tailcall from an ISR routine - it needs a special exit sequence. */
2858 if (IS_INTERRUPT (arm_current_func_type ()))
2861 /* Everything else is ok. */
2866 /* Addressing mode support functions. */
2868 /* Return nonzero if X is a legitimate immediate operand when compiling
2871 legitimate_pic_operand_p (rtx x)
2875 && (GET_CODE (x) == SYMBOL_REF
2876 || (GET_CODE (x) == CONST
2877 && GET_CODE (XEXP (x, 0)) == PLUS
2878 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)))
2885 legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg)
2887 if (GET_CODE (orig) == SYMBOL_REF
2888 || GET_CODE (orig) == LABEL_REF)
2890 #ifndef AOF_ASSEMBLER
2891 rtx pic_ref, address;
2901 reg = gen_reg_rtx (Pmode);
2906 #ifdef AOF_ASSEMBLER
2907 /* The AOF assembler can generate relocations for these directly, and
2908 understands that the PIC register has to be added into the offset. */
2909 insn = emit_insn (gen_pic_load_addr_based (reg, orig));
2912 address = gen_reg_rtx (Pmode);
2917 emit_insn (gen_pic_load_addr_arm (address, orig));
2919 emit_insn (gen_pic_load_addr_thumb (address, orig));
2921 if ((GET_CODE (orig) == LABEL_REF
2922 || (GET_CODE (orig) == SYMBOL_REF &&
2923 SYMBOL_REF_LOCAL_P (orig)))
2925 pic_ref = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, address);
2928 pic_ref = gen_const_mem (Pmode,
2929 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
2933 insn = emit_move_insn (reg, pic_ref);
2935 current_function_uses_pic_offset_table = 1;
2936 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2938 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
2942 else if (GET_CODE (orig) == CONST)
2946 if (GET_CODE (XEXP (orig, 0)) == PLUS
2947 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
2955 reg = gen_reg_rtx (Pmode);
2958 if (GET_CODE (XEXP (orig, 0)) == PLUS)
2960 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
2961 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
2962 base == reg ? 0 : reg);
2967 if (GET_CODE (offset) == CONST_INT)
2969 /* The base register doesn't really matter, we only want to
2970 test the index for the appropriate mode. */
2971 if (!arm_legitimate_index_p (mode, offset, SET, 0))
2973 if (!no_new_pseudos)
2974 offset = force_reg (Pmode, offset);
2979 if (GET_CODE (offset) == CONST_INT)
2980 return plus_constant (base, INTVAL (offset));
2983 if (GET_MODE_SIZE (mode) > 4
2984 && (GET_MODE_CLASS (mode) == MODE_INT
2985 || TARGET_SOFT_FLOAT))
2987 emit_insn (gen_addsi3 (reg, base, offset));
2991 return gen_rtx_PLUS (Pmode, base, offset);
2998 /* Find a spare low register. */
3001 thumb_find_work_register (int live_regs_mask)
3005 /* Use a spare arg register. */
3006 if (!regs_ever_live[LAST_ARG_REGNUM])
3007 return LAST_ARG_REGNUM;
3009 /* Look for a pushed register. */
3010 for (reg = 0; reg < LAST_LO_REGNUM; reg++)
3011 if (live_regs_mask & (1 << reg))
3014 /* Something went wrong. */
3019 /* Generate code to load the PIC register. */
3022 arm_load_pic_register (void)
3024 #ifndef AOF_ASSEMBLER
3025 rtx l1, pic_tmp, pic_tmp2, pic_rtx;
3026 rtx global_offset_table;
3028 if (current_function_uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE)
3034 l1 = gen_label_rtx ();
3036 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3037 /* On the ARM the PC register contains 'dot + 8' at the time of the
3038 addition, on the Thumb it is 'dot + 4'. */
3039 pic_tmp = plus_constant (gen_rtx_LABEL_REF (Pmode, l1), TARGET_ARM ? 8 : 4);
3041 pic_tmp2 = gen_rtx_CONST (VOIDmode,
3042 gen_rtx_PLUS (Pmode, global_offset_table, pc_rtx));
3044 pic_tmp2 = gen_rtx_CONST (VOIDmode, global_offset_table);
3046 pic_rtx = gen_rtx_CONST (Pmode, gen_rtx_MINUS (Pmode, pic_tmp2, pic_tmp));
3050 emit_insn (gen_pic_load_addr_arm (pic_offset_table_rtx, pic_rtx));
3051 emit_insn (gen_pic_add_dot_plus_eight (pic_offset_table_rtx, l1));
3055 if (REGNO (pic_offset_table_rtx) > LAST_LO_REGNUM)
3059 /* We will have pushed the pic register, so should always be
3060 able to find a work register. */
3061 reg = thumb_find_work_register (thumb_compute_save_reg_mask ());
3062 pic_tmp = gen_rtx_REG (SImode, reg);
3063 emit_insn (gen_pic_load_addr_thumb (pic_tmp, pic_rtx));
3064 emit_insn (gen_movsi (pic_offset_table_rtx, pic_tmp));
3067 emit_insn (gen_pic_load_addr_thumb (pic_offset_table_rtx, pic_rtx));
3068 emit_insn (gen_pic_add_dot_plus_four (pic_offset_table_rtx, l1));
3071 /* Need to emit this whether or not we obey regdecls,
3072 since setjmp/longjmp can cause life info to screw up. */
3073 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
3074 #endif /* AOF_ASSEMBLER */
3078 /* Return nonzero if X is valid as an ARM state addressing register. */
3080 arm_address_register_rtx_p (rtx x, int strict_p)
3084 if (GET_CODE (x) != REG)
3090 return ARM_REGNO_OK_FOR_BASE_P (regno);
3092 return (regno <= LAST_ARM_REGNUM
3093 || regno >= FIRST_PSEUDO_REGISTER
3094 || regno == FRAME_POINTER_REGNUM
3095 || regno == ARG_POINTER_REGNUM);
3098 /* Return nonzero if X is a valid ARM state address operand. */
3100 arm_legitimate_address_p (enum machine_mode mode, rtx x, RTX_CODE outer,
3104 enum rtx_code code = GET_CODE (x);
3106 if (arm_address_register_rtx_p (x, strict_p))
3109 use_ldrd = (TARGET_LDRD
3111 || (mode == DFmode && (TARGET_SOFT_FLOAT || TARGET_VFP))));
3113 if (code == POST_INC || code == PRE_DEC
3114 || ((code == PRE_INC || code == POST_DEC)
3115 && (use_ldrd || GET_MODE_SIZE (mode) <= 4)))
3116 return arm_address_register_rtx_p (XEXP (x, 0), strict_p);
3118 else if ((code == POST_MODIFY || code == PRE_MODIFY)
3119 && arm_address_register_rtx_p (XEXP (x, 0), strict_p)
3120 && GET_CODE (XEXP (x, 1)) == PLUS
3121 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
3123 rtx addend = XEXP (XEXP (x, 1), 1);
3125 /* Don't allow ldrd post increment by register becuase it's hard
3126 to fixup invalid register choices. */
3128 && GET_CODE (x) == POST_MODIFY
3129 && GET_CODE (addend) == REG)
3132 return ((use_ldrd || GET_MODE_SIZE (mode) <= 4)
3133 && arm_legitimate_index_p (mode, addend, outer, strict_p));
3136 /* After reload constants split into minipools will have addresses
3137 from a LABEL_REF. */
3138 else if (reload_completed
3139 && (code == LABEL_REF
3141 && GET_CODE (XEXP (x, 0)) == PLUS
3142 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
3143 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
3146 else if (mode == TImode)
3149 else if (code == PLUS)
3151 rtx xop0 = XEXP (x, 0);
3152 rtx xop1 = XEXP (x, 1);
3154 return ((arm_address_register_rtx_p (xop0, strict_p)
3155 && arm_legitimate_index_p (mode, xop1, outer, strict_p))
3156 || (arm_address_register_rtx_p (xop1, strict_p)
3157 && arm_legitimate_index_p (mode, xop0, outer, strict_p)));
3161 /* Reload currently can't handle MINUS, so disable this for now */
3162 else if (GET_CODE (x) == MINUS)
3164 rtx xop0 = XEXP (x, 0);
3165 rtx xop1 = XEXP (x, 1);
3167 return (arm_address_register_rtx_p (xop0, strict_p)
3168 && arm_legitimate_index_p (mode, xop1, outer, strict_p));
3172 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
3173 && code == SYMBOL_REF
3174 && CONSTANT_POOL_ADDRESS_P (x)
3176 && symbol_mentioned_p (get_pool_constant (x))))
3182 /* Return nonzero if INDEX is valid for an address index operand in
3185 arm_legitimate_index_p (enum machine_mode mode, rtx index, RTX_CODE outer,
3188 HOST_WIDE_INT range;
3189 enum rtx_code code = GET_CODE (index);
3191 /* Standard coprocessor addressing modes. */
3192 if (TARGET_HARD_FLOAT
3193 && (TARGET_FPA || TARGET_MAVERICK)
3194 && (GET_MODE_CLASS (mode) == MODE_FLOAT
3195 || (TARGET_MAVERICK && mode == DImode)))
3196 return (code == CONST_INT && INTVAL (index) < 1024
3197 && INTVAL (index) > -1024
3198 && (INTVAL (index) & 3) == 0);
3200 if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))
3201 return (code == CONST_INT
3202 && INTVAL (index) < 1024
3203 && INTVAL (index) > -1024
3204 && (INTVAL (index) & 3) == 0);
3206 if (arm_address_register_rtx_p (index, strict_p)
3207 && (GET_MODE_SIZE (mode) <= 4))
3210 if (mode == DImode || mode == DFmode)
3212 if (code == CONST_INT)
3214 HOST_WIDE_INT val = INTVAL (index);
3217 return val > -256 && val < 256;
3219 return val > -4096 && val < 4092;
3222 return TARGET_LDRD && arm_address_register_rtx_p (index, strict_p);
3225 if (GET_MODE_SIZE (mode) <= 4
3228 || (mode == QImode && outer == SIGN_EXTEND))))
3232 rtx xiop0 = XEXP (index, 0);
3233 rtx xiop1 = XEXP (index, 1);
3235 return ((arm_address_register_rtx_p (xiop0, strict_p)
3236 && power_of_two_operand (xiop1, SImode))
3237 || (arm_address_register_rtx_p (xiop1, strict_p)
3238 && power_of_two_operand (xiop0, SImode)));
3240 else if (code == LSHIFTRT || code == ASHIFTRT
3241 || code == ASHIFT || code == ROTATERT)
3243 rtx op = XEXP (index, 1);
3245 return (arm_address_register_rtx_p (XEXP (index, 0), strict_p)
3246 && GET_CODE (op) == CONST_INT
3248 && INTVAL (op) <= 31);
3252 /* For ARM v4 we may be doing a sign-extend operation during the
3256 if (mode == HImode || (outer == SIGN_EXTEND && mode == QImode))
3262 range = (mode == HImode) ? 4095 : 4096;
3264 return (code == CONST_INT
3265 && INTVAL (index) < range
3266 && INTVAL (index) > -range);
3269 /* Return nonzero if X is valid as a Thumb state base register. */
3271 thumb_base_register_rtx_p (rtx x, enum machine_mode mode, int strict_p)
3275 if (GET_CODE (x) != REG)
3281 return THUMB_REGNO_MODE_OK_FOR_BASE_P (regno, mode);
3283 return (regno <= LAST_LO_REGNUM
3284 || regno > LAST_VIRTUAL_REGISTER
3285 || regno == FRAME_POINTER_REGNUM
3286 || (GET_MODE_SIZE (mode) >= 4
3287 && (regno == STACK_POINTER_REGNUM
3288 || regno >= FIRST_PSEUDO_REGISTER
3289 || x == hard_frame_pointer_rtx
3290 || x == arg_pointer_rtx)));
3293 /* Return nonzero if x is a legitimate index register. This is the case
3294 for any base register that can access a QImode object. */
3296 thumb_index_register_rtx_p (rtx x, int strict_p)
3298 return thumb_base_register_rtx_p (x, QImode, strict_p);
3301 /* Return nonzero if x is a legitimate Thumb-state address.
3303 The AP may be eliminated to either the SP or the FP, so we use the
3304 least common denominator, e.g. SImode, and offsets from 0 to 64.
3306 ??? Verify whether the above is the right approach.
3308 ??? Also, the FP may be eliminated to the SP, so perhaps that
3309 needs special handling also.
3311 ??? Look at how the mips16 port solves this problem. It probably uses
3312 better ways to solve some of these problems.
3314 Although it is not incorrect, we don't accept QImode and HImode
3315 addresses based on the frame pointer or arg pointer until the
3316 reload pass starts. This is so that eliminating such addresses
3317 into stack based ones won't produce impossible code. */
3319 thumb_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p)
3321 /* ??? Not clear if this is right. Experiment. */
3322 if (GET_MODE_SIZE (mode) < 4
3323 && !(reload_in_progress || reload_completed)
3324 && (reg_mentioned_p (frame_pointer_rtx, x)
3325 || reg_mentioned_p (arg_pointer_rtx, x)
3326 || reg_mentioned_p (virtual_incoming_args_rtx, x)
3327 || reg_mentioned_p (virtual_outgoing_args_rtx, x)
3328 || reg_mentioned_p (virtual_stack_dynamic_rtx, x)
3329 || reg_mentioned_p (virtual_stack_vars_rtx, x)))
3332 /* Accept any base register. SP only in SImode or larger. */
3333 else if (thumb_base_register_rtx_p (x, mode, strict_p))
3336 /* This is PC relative data before arm_reorg runs. */
3337 else if (GET_MODE_SIZE (mode) >= 4 && CONSTANT_P (x)
3338 && GET_CODE (x) == SYMBOL_REF
3339 && CONSTANT_POOL_ADDRESS_P (x) && ! flag_pic)
3342 /* This is PC relative data after arm_reorg runs. */
3343 else if (GET_MODE_SIZE (mode) >= 4 && reload_completed
3344 && (GET_CODE (x) == LABEL_REF
3345 || (GET_CODE (x) == CONST
3346 && GET_CODE (XEXP (x, 0)) == PLUS
3347 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
3348 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
3351 /* Post-inc indexing only supported for SImode and larger. */
3352 else if (GET_CODE (x) == POST_INC && GET_MODE_SIZE (mode) >= 4
3353 && thumb_index_register_rtx_p (XEXP (x, 0), strict_p))
3356 else if (GET_CODE (x) == PLUS)
3358 /* REG+REG address can be any two index registers. */
3359 /* We disallow FRAME+REG addressing since we know that FRAME
3360 will be replaced with STACK, and SP relative addressing only
3361 permits SP+OFFSET. */
3362 if (GET_MODE_SIZE (mode) <= 4
3363 && XEXP (x, 0) != frame_pointer_rtx
3364 && XEXP (x, 1) != frame_pointer_rtx
3365 && thumb_index_register_rtx_p (XEXP (x, 0), strict_p)
3366 && thumb_index_register_rtx_p (XEXP (x, 1), strict_p))
3369 /* REG+const has 5-7 bit offset for non-SP registers. */
3370 else if ((thumb_index_register_rtx_p (XEXP (x, 0), strict_p)
3371 || XEXP (x, 0) == arg_pointer_rtx)
3372 && GET_CODE (XEXP (x, 1)) == CONST_INT
3373 && thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1))))
3376 /* REG+const has 10 bit offset for SP, but only SImode and
3377 larger is supported. */
3378 /* ??? Should probably check for DI/DFmode overflow here
3379 just like GO_IF_LEGITIMATE_OFFSET does. */
3380 else if (GET_CODE (XEXP (x, 0)) == REG
3381 && REGNO (XEXP (x, 0)) == STACK_POINTER_REGNUM
3382 && GET_MODE_SIZE (mode) >= 4
3383 && GET_CODE (XEXP (x, 1)) == CONST_INT
3384 && INTVAL (XEXP (x, 1)) >= 0
3385 && INTVAL (XEXP (x, 1)) + GET_MODE_SIZE (mode) <= 1024
3386 && (INTVAL (XEXP (x, 1)) & 3) == 0)
3389 else if (GET_CODE (XEXP (x, 0)) == REG
3390 && REGNO (XEXP (x, 0)) == FRAME_POINTER_REGNUM
3391 && GET_MODE_SIZE (mode) >= 4
3392 && GET_CODE (XEXP (x, 1)) == CONST_INT
3393 && (INTVAL (XEXP (x, 1)) & 3) == 0)
3397 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
3398 && GET_MODE_SIZE (mode) == 4
3399 && GET_CODE (x) == SYMBOL_REF
3400 && CONSTANT_POOL_ADDRESS_P (x)
3402 && symbol_mentioned_p (get_pool_constant (x))))
3408 /* Return nonzero if VAL can be used as an offset in a Thumb-state address
3409 instruction of mode MODE. */
3411 thumb_legitimate_offset_p (enum machine_mode mode, HOST_WIDE_INT val)
3413 switch (GET_MODE_SIZE (mode))
3416 return val >= 0 && val < 32;
3419 return val >= 0 && val < 64 && (val & 1) == 0;
3423 && (val + GET_MODE_SIZE (mode)) <= 128
3428 /* Try machine-dependent ways of modifying an illegitimate address
3429 to be legitimate. If we find one, return the new, valid address. */
3431 arm_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)
3433 if (GET_CODE (x) == PLUS)
3435 rtx xop0 = XEXP (x, 0);
3436 rtx xop1 = XEXP (x, 1);
3438 if (CONSTANT_P (xop0) && !symbol_mentioned_p (xop0))
3439 xop0 = force_reg (SImode, xop0);
3441 if (CONSTANT_P (xop1) && !symbol_mentioned_p (xop1))
3442 xop1 = force_reg (SImode, xop1);
3444 if (ARM_BASE_REGISTER_RTX_P (xop0)
3445 && GET_CODE (xop1) == CONST_INT)
3447 HOST_WIDE_INT n, low_n;
3451 /* VFP addressing modes actually allow greater offsets, but for
3452 now we just stick with the lowest common denominator. */
3454 || ((TARGET_SOFT_FLOAT || TARGET_VFP) && mode == DFmode))
3466 low_n = ((mode) == TImode ? 0
3467 : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff));
3471 base_reg = gen_reg_rtx (SImode);
3472 val = force_operand (gen_rtx_PLUS (SImode, xop0,
3473 GEN_INT (n)), NULL_RTX);
3474 emit_move_insn (base_reg, val);
3475 x = (low_n == 0 ? base_reg
3476 : gen_rtx_PLUS (SImode, base_reg, GEN_INT (low_n)));
3478 else if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1))
3479 x = gen_rtx_PLUS (SImode, xop0, xop1);
3482 /* XXX We don't allow MINUS any more -- see comment in
3483 arm_legitimate_address_p (). */
3484 else if (GET_CODE (x) == MINUS)
3486 rtx xop0 = XEXP (x, 0);
3487 rtx xop1 = XEXP (x, 1);
3489 if (CONSTANT_P (xop0))
3490 xop0 = force_reg (SImode, xop0);
3492 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1))
3493 xop1 = force_reg (SImode, xop1);
3495 if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1))
3496 x = gen_rtx_MINUS (SImode, xop0, xop1);
3501 /* We need to find and carefully transform any SYMBOL and LABEL
3502 references; so go back to the original address expression. */
3503 rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX);
3505 if (new_x != orig_x)
3513 /* Try machine-dependent ways of modifying an illegitimate Thumb address
3514 to be legitimate. If we find one, return the new, valid address. */
3516 thumb_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)
3518 if (GET_CODE (x) == PLUS
3519 && GET_CODE (XEXP (x, 1)) == CONST_INT
3520 && (INTVAL (XEXP (x, 1)) >= 32 * GET_MODE_SIZE (mode)
3521 || INTVAL (XEXP (x, 1)) < 0))
3523 rtx xop0 = XEXP (x, 0);
3524 rtx xop1 = XEXP (x, 1);
3525 HOST_WIDE_INT offset = INTVAL (xop1);
3527 /* Try and fold the offset into a biasing of the base register and
3528 then offsetting that. Don't do this when optimizing for space
3529 since it can cause too many CSEs. */
3530 if (optimize_size && offset >= 0
3531 && offset < 256 + 31 * GET_MODE_SIZE (mode))
3533 HOST_WIDE_INT delta;
3536 delta = offset - (256 - GET_MODE_SIZE (mode));
3537 else if (offset < 32 * GET_MODE_SIZE (mode) + 8)
3538 delta = 31 * GET_MODE_SIZE (mode);
3540 delta = offset & (~31 * GET_MODE_SIZE (mode));
3542 xop0 = force_operand (plus_constant (xop0, offset - delta),
3544 x = plus_constant (xop0, delta);
3546 else if (offset < 0 && offset > -256)
3547 /* Small negative offsets are best done with a subtract before the
3548 dereference, forcing these into a register normally takes two
3550 x = force_operand (x, NULL_RTX);
3553 /* For the remaining cases, force the constant into a register. */
3554 xop1 = force_reg (SImode, xop1);
3555 x = gen_rtx_PLUS (SImode, xop0, xop1);
3558 else if (GET_CODE (x) == PLUS
3559 && s_register_operand (XEXP (x, 1), SImode)
3560 && !s_register_operand (XEXP (x, 0), SImode))
3562 rtx xop0 = force_operand (XEXP (x, 0), NULL_RTX);
3564 x = gen_rtx_PLUS (SImode, xop0, XEXP (x, 1));
3569 /* We need to find and carefully transform any SYMBOL and LABEL
3570 references; so go back to the original address expression. */
3571 rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX);
3573 if (new_x != orig_x)
3582 #define REG_OR_SUBREG_REG(X) \
3583 (GET_CODE (X) == REG \
3584 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
3586 #define REG_OR_SUBREG_RTX(X) \
3587 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
3589 #ifndef COSTS_N_INSNS
3590 #define COSTS_N_INSNS(N) ((N) * 4 - 2)
3593 thumb_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer)
3595 enum machine_mode mode = GET_MODE (x);
3608 return COSTS_N_INSNS (1);
3611 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
3614 unsigned HOST_WIDE_INT i = INTVAL (XEXP (x, 1));
3621 return COSTS_N_INSNS (2) + cycles;
3623 return COSTS_N_INSNS (1) + 16;
3626 return (COSTS_N_INSNS (1)
3627 + 4 * ((GET_CODE (SET_SRC (x)) == MEM)
3628 + GET_CODE (SET_DEST (x)) == MEM));
3633 if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256)
3635 if (thumb_shiftable_const (INTVAL (x)))
3636 return COSTS_N_INSNS (2);
3637 return COSTS_N_INSNS (3);
3639 else if ((outer == PLUS || outer == COMPARE)
3640 && INTVAL (x) < 256 && INTVAL (x) > -256)
3642 else if (outer == AND
3643 && INTVAL (x) < 256 && INTVAL (x) >= -256)
3644 return COSTS_N_INSNS (1);
3645 else if (outer == ASHIFT || outer == ASHIFTRT
3646 || outer == LSHIFTRT)
3648 return COSTS_N_INSNS (2);
3654 return COSTS_N_INSNS (3);
3672 /* XXX another guess. */
3673 /* Memory costs quite a lot for the first word, but subsequent words
3674 load at the equivalent of a single insn each. */
3675 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
3676 + ((GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
3681 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
3686 /* XXX still guessing. */
3687 switch (GET_MODE (XEXP (x, 0)))
3690 return (1 + (mode == DImode ? 4 : 0)
3691 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3694 return (4 + (mode == DImode ? 4 : 0)
3695 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3698 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3710 /* Worker routine for arm_rtx_costs. */
3712 arm_rtx_costs_1 (rtx x, enum rtx_code code, enum rtx_code outer)
3714 enum machine_mode mode = GET_MODE (x);
3715 enum rtx_code subcode;
3721 /* Memory costs quite a lot for the first word, but subsequent words
3722 load at the equivalent of a single insn each. */
3723 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
3724 + (GET_CODE (x) == SYMBOL_REF
3725 && CONSTANT_POOL_ADDRESS_P (x) ? 4 : 0));
3731 return optimize_size ? COSTS_N_INSNS (2) : 100;
3734 if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG)
3741 case ASHIFT: case LSHIFTRT: case ASHIFTRT:
3743 return (8 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : 8)
3744 + ((GET_CODE (XEXP (x, 0)) == REG
3745 || (GET_CODE (XEXP (x, 0)) == SUBREG
3746 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
3748 return (1 + ((GET_CODE (XEXP (x, 0)) == REG
3749 || (GET_CODE (XEXP (x, 0)) == SUBREG
3750 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
3752 + ((GET_CODE (XEXP (x, 1)) == REG
3753 || (GET_CODE (XEXP (x, 1)) == SUBREG
3754 && GET_CODE (SUBREG_REG (XEXP (x, 1))) == REG)
3755 || (GET_CODE (XEXP (x, 1)) == CONST_INT))
3760 return (4 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 8)
3761 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
3762 || (GET_CODE (XEXP (x, 0)) == CONST_INT
3763 && const_ok_for_arm (INTVAL (XEXP (x, 0)))))
3766 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
3767 return (2 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
3768 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
3769 && arm_const_double_rtx (XEXP (x, 1))))
3771 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
3772 || (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE
3773 && arm_const_double_rtx (XEXP (x, 0))))
3776 if (((GET_CODE (XEXP (x, 0)) == CONST_INT
3777 && const_ok_for_arm (INTVAL (XEXP (x, 0)))
3778 && REG_OR_SUBREG_REG (XEXP (x, 1))))
3779 || (((subcode = GET_CODE (XEXP (x, 1))) == ASHIFT
3780 || subcode == ASHIFTRT || subcode == LSHIFTRT
3781 || subcode == ROTATE || subcode == ROTATERT
3783 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
3784 && ((INTVAL (XEXP (XEXP (x, 1), 1)) &
3785 (INTVAL (XEXP (XEXP (x, 1), 1)) - 1)) == 0)))
3786 && REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 0))
3787 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 1))
3788 || GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT)
3789 && REG_OR_SUBREG_REG (XEXP (x, 0))))
3794 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
3795 return (2 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
3796 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
3797 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
3798 && arm_const_double_rtx (XEXP (x, 1))))
3802 case AND: case XOR: case IOR:
3805 /* Normally the frame registers will be spilt into reg+const during
3806 reload, so it is a bad idea to combine them with other instructions,
3807 since then they might not be moved outside of loops. As a compromise
3808 we allow integration with ops that have a constant as their second
3810 if ((REG_OR_SUBREG_REG (XEXP (x, 0))
3811 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))
3812 && GET_CODE (XEXP (x, 1)) != CONST_INT)
3813 || (REG_OR_SUBREG_REG (XEXP (x, 0))
3814 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))))
3818 return (4 + extra_cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
3819 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
3820 || (GET_CODE (XEXP (x, 1)) == CONST_INT
3821 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
3824 if (REG_OR_SUBREG_REG (XEXP (x, 0)))
3825 return (1 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : extra_cost)
3826 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
3827 || (GET_CODE (XEXP (x, 1)) == CONST_INT
3828 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
3831 else if (REG_OR_SUBREG_REG (XEXP (x, 1)))
3832 return (1 + extra_cost
3833 + ((((subcode = GET_CODE (XEXP (x, 0))) == ASHIFT
3834 || subcode == LSHIFTRT || subcode == ASHIFTRT
3835 || subcode == ROTATE || subcode == ROTATERT
3837 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3838 && ((INTVAL (XEXP (XEXP (x, 0), 1)) &
3839 (INTVAL (XEXP (XEXP (x, 0), 1)) - 1)) == 0)))
3840 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 0)))
3841 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 1)))
3842 || GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))
3848 /* This should have been handled by the CPU specific routines. */
3852 if (arm_arch3m && mode == SImode
3853 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
3854 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
3855 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0))
3856 == GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)))
3857 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ZERO_EXTEND
3858 || GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SIGN_EXTEND))
3863 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
3864 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 6);
3868 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
3870 return 1 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
3873 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
3881 return 4 + (mode == DImode ? 4 : 0);
3884 if (GET_MODE (XEXP (x, 0)) == QImode)
3885 return (4 + (mode == DImode ? 4 : 0)
3886 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3889 switch (GET_MODE (XEXP (x, 0)))
3892 return (1 + (mode == DImode ? 4 : 0)
3893 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3896 return (4 + (mode == DImode ? 4 : 0)
3897 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3900 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3915 if (const_ok_for_arm (INTVAL (x)))
3916 return outer == SET ? 2 : -1;
3917 else if (outer == AND
3918 && const_ok_for_arm (~INTVAL (x)))
3920 else if ((outer == COMPARE
3921 || outer == PLUS || outer == MINUS)
3922 && const_ok_for_arm (-INTVAL (x)))
3933 if (arm_const_double_rtx (x))
3934 return outer == SET ? 2 : -1;
3935 else if ((outer == COMPARE || outer == PLUS)
3936 && neg_const_double_rtx_ok_for_fpa (x))
3945 /* RTX costs when optimizing for size. */
3947 arm_size_rtx_costs (rtx x, int code, int outer_code, int *total)
3949 enum machine_mode mode = GET_MODE (x);
3953 /* XXX TBD. For now, use the standard costs. */
3954 *total = thumb_rtx_costs (x, code, outer_code);
3961 /* A memory access costs 1 insn if the mode is small, or the address is
3962 a single register, otherwise it costs one insn per word. */
3963 if (REG_P (XEXP (x, 0)))
3964 *total = COSTS_N_INSNS (1);
3966 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
3973 /* Needs a libcall, so it costs about this. */
3974 *total = COSTS_N_INSNS (2);
3978 if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG)
3980 *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), code);
3988 if (mode == DImode && GET_CODE (XEXP (x, 1)) == CONST_INT)
3990 *total = COSTS_N_INSNS (3) + rtx_cost (XEXP (x, 0), code);
3993 else if (mode == SImode)
3995 *total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 0), code);
3996 /* Slightly disparage register shifts, but not by much. */
3997 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
3998 *total += 1 + rtx_cost (XEXP (x, 1), code);
4002 /* Needs a libcall. */
4003 *total = COSTS_N_INSNS (2);
4007 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
4009 *total = COSTS_N_INSNS (1);
4015 enum rtx_code subcode0 = GET_CODE (XEXP (x, 0));
4016 enum rtx_code subcode1 = GET_CODE (XEXP (x, 1));
4018 if (subcode0 == ROTATE || subcode0 == ROTATERT || subcode0 == ASHIFT
4019 || subcode0 == LSHIFTRT || subcode0 == ASHIFTRT
4020 || subcode1 == ROTATE || subcode1 == ROTATERT
4021 || subcode1 == ASHIFT || subcode1 == LSHIFTRT
4022 || subcode1 == ASHIFTRT)
4024 /* It's just the cost of the two operands. */
4029 *total = COSTS_N_INSNS (1);
4033 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
4037 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
4039 *total = COSTS_N_INSNS (1);
4044 case AND: case XOR: case IOR:
4047 enum rtx_code subcode = GET_CODE (XEXP (x, 0));
4049 if (subcode == ROTATE || subcode == ROTATERT || subcode == ASHIFT
4050 || subcode == LSHIFTRT || subcode == ASHIFTRT
4051 || (code == AND && subcode == NOT))
4053 /* It's just the cost of the two operands. */
4059 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
4063 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
4067 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
4068 *total = COSTS_N_INSNS (1);
4071 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
4080 if (cc_register (XEXP (x, 0), VOIDmode))
4083 *total = COSTS_N_INSNS (1);
4087 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
4088 *total = COSTS_N_INSNS (1);
4090 *total = COSTS_N_INSNS (1 + ARM_NUM_REGS (mode));
4095 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) < 4)
4097 if (!(arm_arch4 && MEM_P (XEXP (x, 0))))
4098 *total += COSTS_N_INSNS (arm_arch6 ? 1 : 2);
4101 *total += COSTS_N_INSNS (1);
4106 if (!(arm_arch4 && MEM_P (XEXP (x, 0))))
4108 switch (GET_MODE (XEXP (x, 0)))
4111 *total += COSTS_N_INSNS (1);
4115 *total += COSTS_N_INSNS (arm_arch6 ? 1 : 2);
4121 *total += COSTS_N_INSNS (2);
4126 *total += COSTS_N_INSNS (1);
4131 if (const_ok_for_arm (INTVAL (x)))
4132 *total = COSTS_N_INSNS (outer_code == SET ? 1 : 0);
4133 else if (const_ok_for_arm (~INTVAL (x)))
4134 *total = COSTS_N_INSNS (outer_code == AND ? 0 : 1);
4135 else if (const_ok_for_arm (-INTVAL (x)))
4137 if (outer_code == COMPARE || outer_code == PLUS
4138 || outer_code == MINUS)
4141 *total = COSTS_N_INSNS (1);
4144 *total = COSTS_N_INSNS (2);
4150 *total = COSTS_N_INSNS (2);
4154 *total = COSTS_N_INSNS (4);
4158 if (mode != VOIDmode)
4159 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
4161 *total = COSTS_N_INSNS (4); /* How knows? */
4166 /* RTX costs for cores with a slow MUL implementation. */
4169 arm_slowmul_rtx_costs (rtx x, int code, int outer_code, int *total)
4171 enum machine_mode mode = GET_MODE (x);
4175 *total = thumb_rtx_costs (x, code, outer_code);
4182 if (GET_MODE_CLASS (mode) == MODE_FLOAT
4189 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4191 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
4192 & (unsigned HOST_WIDE_INT) 0xffffffff);
4193 int cost, const_ok = const_ok_for_arm (i);
4194 int j, booth_unit_size;
4196 /* Tune as appropriate. */
4197 cost = const_ok ? 4 : 8;
4198 booth_unit_size = 2;
4199 for (j = 0; i && j < 32; j += booth_unit_size)
4201 i >>= booth_unit_size;
4209 *total = 30 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
4210 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
4214 *total = arm_rtx_costs_1 (x, code, outer_code);
4220 /* RTX cost for cores with a fast multiply unit (M variants). */
4223 arm_fastmul_rtx_costs (rtx x, int code, int outer_code, int *total)
4225 enum machine_mode mode = GET_MODE (x);
4229 *total = thumb_rtx_costs (x, code, outer_code);
4236 /* There is no point basing this on the tuning, since it is always the
4237 fast variant if it exists at all. */
4239 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
4240 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
4241 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
4248 if (GET_MODE_CLASS (mode) == MODE_FLOAT
4255 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4257 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
4258 & (unsigned HOST_WIDE_INT) 0xffffffff);
4259 int cost, const_ok = const_ok_for_arm (i);
4260 int j, booth_unit_size;
4262 /* Tune as appropriate. */
4263 cost = const_ok ? 4 : 8;
4264 booth_unit_size = 8;
4265 for (j = 0; i && j < 32; j += booth_unit_size)
4267 i >>= booth_unit_size;
4275 *total = 8 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
4276 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
4280 *total = arm_rtx_costs_1 (x, code, outer_code);
4286 /* RTX cost for XScale CPUs. */
4289 arm_xscale_rtx_costs (rtx x, int code, int outer_code, int *total)
4291 enum machine_mode mode = GET_MODE (x);
4295 *total = thumb_rtx_costs (x, code, outer_code);
4302 /* There is no point basing this on the tuning, since it is always the
4303 fast variant if it exists at all. */
4305 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
4306 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
4307 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
4314 if (GET_MODE_CLASS (mode) == MODE_FLOAT
4321 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4323 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
4324 & (unsigned HOST_WIDE_INT) 0xffffffff);
4325 int cost, const_ok = const_ok_for_arm (i);
4326 unsigned HOST_WIDE_INT masked_const;
4328 /* The cost will be related to two insns.
4329 First a load of the constant (MOV or LDR), then a multiply. */
4332 cost += 1; /* LDR is probably more expensive because
4333 of longer result latency. */
4334 masked_const = i & 0xffff8000;
4335 if (masked_const != 0 && masked_const != 0xffff8000)
4337 masked_const = i & 0xf8000000;
4338 if (masked_const == 0 || masked_const == 0xf8000000)
4347 *total = 8 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
4348 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
4352 *total = arm_rtx_costs_1 (x, code, outer_code);
4358 /* RTX costs for 9e (and later) cores. */
4361 arm_9e_rtx_costs (rtx x, int code, int outer_code, int *total)
4363 enum machine_mode mode = GET_MODE (x);
4372 *total = COSTS_N_INSNS (3);
4376 *total = thumb_rtx_costs (x, code, outer_code);
4384 /* There is no point basing this on the tuning, since it is always the
4385 fast variant if it exists at all. */
4387 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
4388 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
4389 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
4396 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
4413 *total = cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : nonreg_cost)
4414 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : nonreg_cost);
4418 *total = arm_rtx_costs_1 (x, code, outer_code);
4422 /* All address computations that can be done are free, but rtx cost returns
4423 the same for practically all of them. So we weight the different types
4424 of address here in the order (most pref first):
4425 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
4427 arm_arm_address_cost (rtx x)
4429 enum rtx_code c = GET_CODE (x);
4431 if (c == PRE_INC || c == PRE_DEC || c == POST_INC || c == POST_DEC)
4433 if (c == MEM || c == LABEL_REF || c == SYMBOL_REF)
4436 if (c == PLUS || c == MINUS)
4438 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
4441 if (ARITHMETIC_P (XEXP (x, 0)) || ARITHMETIC_P (XEXP (x, 1)))
4451 arm_thumb_address_cost (rtx x)
4453 enum rtx_code c = GET_CODE (x);
4458 && GET_CODE (XEXP (x, 0)) == REG
4459 && GET_CODE (XEXP (x, 1)) == CONST_INT)
4466 arm_address_cost (rtx x)
4468 return TARGET_ARM ? arm_arm_address_cost (x) : arm_thumb_address_cost (x);
4472 arm_adjust_cost (rtx insn, rtx link, rtx dep, int cost)
4476 /* Some true dependencies can have a higher cost depending
4477 on precisely how certain input operands are used. */
4479 && REG_NOTE_KIND (link) == 0
4480 && recog_memoized (insn) >= 0
4481 && recog_memoized (dep) >= 0)
4483 int shift_opnum = get_attr_shift (insn);
4484 enum attr_type attr_type = get_attr_type (dep);
4486 /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted
4487 operand for INSN. If we have a shifted input operand and the
4488 instruction we depend on is another ALU instruction, then we may
4489 have to account for an additional stall. */
4490 if (shift_opnum != 0
4491 && (attr_type == TYPE_ALU_SHIFT || attr_type == TYPE_ALU_SHIFT_REG))
4493 rtx shifted_operand;
4496 /* Get the shifted operand. */
4497 extract_insn (insn);
4498 shifted_operand = recog_data.operand[shift_opnum];
4500 /* Iterate over all the operands in DEP. If we write an operand
4501 that overlaps with SHIFTED_OPERAND, then we have increase the
4502 cost of this dependency. */
4504 preprocess_constraints ();
4505 for (opno = 0; opno < recog_data.n_operands; opno++)
4507 /* We can ignore strict inputs. */
4508 if (recog_data.operand_type[opno] == OP_IN)
4511 if (reg_overlap_mentioned_p (recog_data.operand[opno],
4518 /* XXX This is not strictly true for the FPA. */
4519 if (REG_NOTE_KIND (link) == REG_DEP_ANTI
4520 || REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
4523 /* Call insns don't incur a stall, even if they follow a load. */
4524 if (REG_NOTE_KIND (link) == 0
4525 && GET_CODE (insn) == CALL_INSN)
4528 if ((i_pat = single_set (insn)) != NULL
4529 && GET_CODE (SET_SRC (i_pat)) == MEM
4530 && (d_pat = single_set (dep)) != NULL
4531 && GET_CODE (SET_DEST (d_pat)) == MEM)
4533 rtx src_mem = XEXP (SET_SRC (i_pat), 0);
4534 /* This is a load after a store, there is no conflict if the load reads
4535 from a cached area. Assume that loads from the stack, and from the
4536 constant pool are cached, and that others will miss. This is a
4539 if ((GET_CODE (src_mem) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (src_mem))
4540 || reg_mentioned_p (stack_pointer_rtx, src_mem)
4541 || reg_mentioned_p (frame_pointer_rtx, src_mem)
4542 || reg_mentioned_p (hard_frame_pointer_rtx, src_mem))
4549 static int fp_consts_inited = 0;
4551 /* Only zero is valid for VFP. Other values are also valid for FPA. */
4552 static const char * const strings_fp[8] =
4555 "4", "5", "0.5", "10"
4558 static REAL_VALUE_TYPE values_fp[8];
4561 init_fp_table (void)
4567 fp_consts_inited = 1;
4569 fp_consts_inited = 8;
4571 for (i = 0; i < fp_consts_inited; i++)
4573 r = REAL_VALUE_ATOF (strings_fp[i], DFmode);
4578 /* Return TRUE if rtx X is a valid immediate FP constant. */
4580 arm_const_double_rtx (rtx x)
4585 if (!fp_consts_inited)
4588 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
4589 if (REAL_VALUE_MINUS_ZERO (r))
4592 for (i = 0; i < fp_consts_inited; i++)
4593 if (REAL_VALUES_EQUAL (r, values_fp[i]))
4599 /* Return TRUE if rtx X is a valid immediate FPA constant. */
4601 neg_const_double_rtx_ok_for_fpa (rtx x)
4606 if (!fp_consts_inited)
4609 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
4610 r = REAL_VALUE_NEGATE (r);
4611 if (REAL_VALUE_MINUS_ZERO (r))
4614 for (i = 0; i < 8; i++)
4615 if (REAL_VALUES_EQUAL (r, values_fp[i]))
4621 /* Predicates for `match_operand' and `match_operator'. */
4623 /* s_register_operand is the same as register_operand, but it doesn't accept
4626 This function exists because at the time it was put in it led to better
4627 code. SUBREG(MEM) always needs a reload in the places where
4628 s_register_operand is used, and this seemed to lead to excessive
4631 s_register_operand (rtx op, enum machine_mode mode)
4633 if (GET_MODE (op) != mode && mode != VOIDmode)
4636 if (GET_CODE (op) == SUBREG)
4637 op = SUBREG_REG (op);
4639 /* We don't consider registers whose class is NO_REGS
4640 to be a register operand. */
4641 /* XXX might have to check for lo regs only for thumb ??? */
4642 return (GET_CODE (op) == REG
4643 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
4644 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
4647 /* A hard register operand (even before reload. */
4649 arm_hard_register_operand (rtx op, enum machine_mode mode)
4651 if (GET_MODE (op) != mode && mode != VOIDmode)
4654 return (GET_CODE (op) == REG
4655 && REGNO (op) < FIRST_PSEUDO_REGISTER);
4658 /* An arm register operand. */
4660 arm_general_register_operand (rtx op, enum machine_mode mode)
4662 if (GET_MODE (op) != mode && mode != VOIDmode)
4665 if (GET_CODE (op) == SUBREG)
4666 op = SUBREG_REG (op);
4668 return (GET_CODE (op) == REG
4669 && (REGNO (op) <= LAST_ARM_REGNUM
4670 || REGNO (op) >= FIRST_PSEUDO_REGISTER));
4673 /* Only accept reg, subreg(reg), const_int. */
4675 reg_or_int_operand (rtx op, enum machine_mode mode)
4677 if (GET_CODE (op) == CONST_INT)
4680 if (GET_MODE (op) != mode && mode != VOIDmode)
4683 if (GET_CODE (op) == SUBREG)
4684 op = SUBREG_REG (op);
4686 /* We don't consider registers whose class is NO_REGS
4687 to be a register operand. */
4688 return (GET_CODE (op) == REG
4689 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
4690 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
4693 /* Return 1 if OP is an item in memory, given that we are in reload. */
4695 arm_reload_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4697 int regno = true_regnum (op);
4699 return (!CONSTANT_P (op)
4701 || (GET_CODE (op) == REG
4702 && REGNO (op) >= FIRST_PSEUDO_REGISTER)));
4705 /* Return TRUE for valid operands for the rhs of an ARM instruction. */
4707 arm_rhs_operand (rtx op, enum machine_mode mode)
4709 return (s_register_operand (op, mode)
4710 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op))));
4713 /* Return TRUE for valid operands for the
4714 rhs of an ARM instruction, or a load. */
4716 arm_rhsm_operand (rtx op, enum machine_mode mode)
4718 return (s_register_operand (op, mode)
4719 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op)))
4720 || memory_operand (op, mode));
4723 /* Return TRUE for valid operands for the rhs of an ARM instruction, or if a
4724 constant that is valid when negated. */
4726 arm_add_operand (rtx op, enum machine_mode mode)
4729 return thumb_cmp_operand (op, mode);
4731 return (s_register_operand (op, mode)
4732 || (GET_CODE (op) == CONST_INT
4733 && (const_ok_for_arm (INTVAL (op))
4734 || const_ok_for_arm (-INTVAL (op)))));
4737 /* Return TRUE for valid ARM constants (or when valid if negated). */
4739 arm_addimm_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4741 return (GET_CODE (op) == CONST_INT
4742 && (const_ok_for_arm (INTVAL (op))
4743 || const_ok_for_arm (-INTVAL (op))));
4747 arm_not_operand (rtx op, enum machine_mode mode)
4749 return (s_register_operand (op, mode)
4750 || (GET_CODE (op) == CONST_INT
4751 && (const_ok_for_arm (INTVAL (op))
4752 || const_ok_for_arm (~INTVAL (op)))));
4755 /* Return TRUE if the operand is a memory reference which contains an
4756 offsettable address. */
4758 offsettable_memory_operand (rtx op, enum machine_mode mode)
4760 if (mode == VOIDmode)
4761 mode = GET_MODE (op);
4763 return (mode == GET_MODE (op)
4764 && GET_CODE (op) == MEM
4765 && offsettable_address_p (reload_completed | reload_in_progress,
4766 mode, XEXP (op, 0)));
4769 /* Return TRUE if the operand is a memory reference which is, or can be
4770 made word aligned by adjusting the offset. */
4772 alignable_memory_operand (rtx op, enum machine_mode mode)
4776 if (mode == VOIDmode)
4777 mode = GET_MODE (op);
4779 if (mode != GET_MODE (op) || GET_CODE (op) != MEM)
4784 return ((GET_CODE (reg = op) == REG
4785 || (GET_CODE (op) == SUBREG
4786 && GET_CODE (reg = SUBREG_REG (op)) == REG)
4787 || (GET_CODE (op) == PLUS
4788 && GET_CODE (XEXP (op, 1)) == CONST_INT
4789 && (GET_CODE (reg = XEXP (op, 0)) == REG
4790 || (GET_CODE (XEXP (op, 0)) == SUBREG
4791 && GET_CODE (reg = SUBREG_REG (XEXP (op, 0))) == REG))))
4792 && REGNO_POINTER_ALIGN (REGNO (reg)) >= 32);
4795 /* Similar to s_register_operand, but does not allow hard integer
4798 f_register_operand (rtx op, enum machine_mode mode)
4800 if (GET_MODE (op) != mode && mode != VOIDmode)
4803 if (GET_CODE (op) == SUBREG)
4804 op = SUBREG_REG (op);
4806 /* We don't consider registers whose class is NO_REGS
4807 to be a register operand. */
4808 return (GET_CODE (op) == REG
4809 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
4810 || REGNO_REG_CLASS (REGNO (op)) == FPA_REGS));
4813 /* Return TRUE for valid operands for the rhs of an floating point insns.
4814 Allows regs or certain consts on FPA, just regs for everything else. */
4816 arm_float_rhs_operand (rtx op, enum machine_mode mode)
4818 if (s_register_operand (op, mode))
4821 if (GET_MODE (op) != mode && mode != VOIDmode)
4824 if (TARGET_FPA && GET_CODE (op) == CONST_DOUBLE)
4825 return arm_const_double_rtx (op);
4831 arm_float_add_operand (rtx op, enum machine_mode mode)
4833 if (s_register_operand (op, mode))
4836 if (GET_MODE (op) != mode && mode != VOIDmode)
4839 if (TARGET_FPA && GET_CODE (op) == CONST_DOUBLE)
4840 return (arm_const_double_rtx (op)
4841 || neg_const_double_rtx_ok_for_fpa (op));
4847 /* Return TRUE if OP is suitable for the rhs of a floating point comparison.
4848 Depends which fpu we are targeting. */
4851 arm_float_compare_operand (rtx op, enum machine_mode mode)
4854 return vfp_compare_operand (op, mode);
4856 return arm_float_rhs_operand (op, mode);
4860 /* Return nonzero if OP is a valid Cirrus memory address pattern. */
4862 cirrus_memory_offset (rtx op)
4864 /* Reject eliminable registers. */
4865 if (! (reload_in_progress || reload_completed)
4866 && ( reg_mentioned_p (frame_pointer_rtx, op)
4867 || reg_mentioned_p (arg_pointer_rtx, op)
4868 || reg_mentioned_p (virtual_incoming_args_rtx, op)
4869 || reg_mentioned_p (virtual_outgoing_args_rtx, op)
4870 || reg_mentioned_p (virtual_stack_dynamic_rtx, op)
4871 || reg_mentioned_p (virtual_stack_vars_rtx, op)))
4874 if (GET_CODE (op) == MEM)
4880 /* Match: (mem (reg)). */
4881 if (GET_CODE (ind) == REG)
4887 if (GET_CODE (ind) == PLUS
4888 && GET_CODE (XEXP (ind, 0)) == REG
4889 && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode)
4890 && GET_CODE (XEXP (ind, 1)) == CONST_INT)
4898 arm_extendqisi_mem_op (rtx op, enum machine_mode mode)
4900 if (!memory_operand (op, mode))
4903 return arm_legitimate_address_p (mode, XEXP (op, 0), SIGN_EXTEND, 0);
4906 /* Return nonzero if OP is a Cirrus or general register. */
4908 cirrus_register_operand (rtx op, enum machine_mode mode)
4910 if (GET_MODE (op) != mode && mode != VOIDmode)
4913 if (GET_CODE (op) == SUBREG)
4914 op = SUBREG_REG (op);
4916 return (GET_CODE (op) == REG
4917 && (REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS
4918 || REGNO_REG_CLASS (REGNO (op)) == GENERAL_REGS));
4921 /* Return nonzero if OP is a cirrus FP register. */
4923 cirrus_fp_register (rtx op, enum machine_mode mode)
4925 if (GET_MODE (op) != mode && mode != VOIDmode)
4928 if (GET_CODE (op) == SUBREG)
4929 op = SUBREG_REG (op);
4931 return (GET_CODE (op) == REG
4932 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
4933 || REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS));
4936 /* Return nonzero if OP is a 6bit constant (0..63). */
4938 cirrus_shift_const (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4940 return (GET_CODE (op) == CONST_INT
4942 && INTVAL (op) < 64);
4946 /* Return TRUE if OP is a valid VFP memory address pattern.
4947 WB if true if writeback address modes are allowed. */
4950 arm_coproc_mem_operand (rtx op, bool wb)
4954 /* Reject eliminable registers. */
4955 if (! (reload_in_progress || reload_completed)
4956 && ( reg_mentioned_p (frame_pointer_rtx, op)
4957 || reg_mentioned_p (arg_pointer_rtx, op)
4958 || reg_mentioned_p (virtual_incoming_args_rtx, op)
4959 || reg_mentioned_p (virtual_outgoing_args_rtx, op)
4960 || reg_mentioned_p (virtual_stack_dynamic_rtx, op)
4961 || reg_mentioned_p (virtual_stack_vars_rtx, op)))
4964 /* Constants are converted into offsets from labels. */
4965 if (GET_CODE (op) != MEM)
4970 if (reload_completed
4971 && (GET_CODE (ind) == LABEL_REF
4972 || (GET_CODE (ind) == CONST
4973 && GET_CODE (XEXP (ind, 0)) == PLUS
4974 && GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF
4975 && GET_CODE (XEXP (XEXP (ind, 0), 1)) == CONST_INT)))
4978 /* Match: (mem (reg)). */
4979 if (GET_CODE (ind) == REG)
4980 return arm_address_register_rtx_p (ind, 0);
4982 /* Autoincremment addressing modes. */
4984 && (GET_CODE (ind) == PRE_INC
4985 || GET_CODE (ind) == POST_INC
4986 || GET_CODE (ind) == PRE_DEC
4987 || GET_CODE (ind) == POST_DEC))
4988 return arm_address_register_rtx_p (XEXP (ind, 0), 0);
4991 && (GET_CODE (ind) == POST_MODIFY || GET_CODE (ind) == PRE_MODIFY)
4992 && arm_address_register_rtx_p (XEXP (ind, 0), 0)
4993 && GET_CODE (XEXP (ind, 1)) == PLUS
4994 && rtx_equal_p (XEXP (XEXP (ind, 1), 0), XEXP (ind, 0)))
4995 ind = XEXP (ind, 1);
5000 if (GET_CODE (ind) == PLUS
5001 && GET_CODE (XEXP (ind, 0)) == REG
5002 && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode)
5003 && GET_CODE (XEXP (ind, 1)) == CONST_INT
5004 && INTVAL (XEXP (ind, 1)) > -1024
5005 && INTVAL (XEXP (ind, 1)) < 1024
5006 && (INTVAL (XEXP (ind, 1)) & 3) == 0)
5013 /* Return TRUE if OP is a REG or constant zero. */
5015 vfp_compare_operand (rtx op, enum machine_mode mode)
5017 if (s_register_operand (op, mode))
5020 return (GET_CODE (op) == CONST_DOUBLE
5021 && arm_const_double_rtx (op));
5025 /* Return GENERAL_REGS if a scratch register required to reload x to/from
5026 VFP registers. Otherwise return NO_REGS. */
5029 vfp_secondary_reload_class (enum machine_mode mode, rtx x)
5031 if (arm_coproc_mem_operand (x, FALSE) || s_register_operand (x, mode))
5034 return GENERAL_REGS;
5038 /* Returns TRUE if INSN is an "LDR REG, ADDR" instruction.
5039 Use by the Cirrus Maverick code which has to workaround
5040 a hardware bug triggered by such instructions. */
5042 arm_memory_load_p (rtx insn)
5044 rtx body, lhs, rhs;;
5046 if (insn == NULL_RTX || GET_CODE (insn) != INSN)
5049 body = PATTERN (insn);
5051 if (GET_CODE (body) != SET)
5054 lhs = XEXP (body, 0);
5055 rhs = XEXP (body, 1);
5057 lhs = REG_OR_SUBREG_RTX (lhs);
5059 /* If the destination is not a general purpose
5060 register we do not have to worry. */
5061 if (GET_CODE (lhs) != REG
5062 || REGNO_REG_CLASS (REGNO (lhs)) != GENERAL_REGS)
5065 /* As well as loads from memory we also have to react
5066 to loads of invalid constants which will be turned
5067 into loads from the minipool. */
5068 return (GET_CODE (rhs) == MEM
5069 || GET_CODE (rhs) == SYMBOL_REF
5070 || note_invalid_constants (insn, -1, false));
5073 /* Return TRUE if INSN is a Cirrus instruction. */
5075 arm_cirrus_insn_p (rtx insn)
5077 enum attr_cirrus attr;
5079 /* get_attr aborts on USE and CLOBBER. */
5081 || GET_CODE (insn) != INSN
5082 || GET_CODE (PATTERN (insn)) == USE
5083 || GET_CODE (PATTERN (insn)) == CLOBBER)
5086 attr = get_attr_cirrus (insn);
5088 return attr != CIRRUS_NOT;
5091 /* Cirrus reorg for invalid instruction combinations. */
5093 cirrus_reorg (rtx first)
5095 enum attr_cirrus attr;
5096 rtx body = PATTERN (first);
5100 /* Any branch must be followed by 2 non Cirrus instructions. */
5101 if (GET_CODE (first) == JUMP_INSN && GET_CODE (body) != RETURN)
5104 t = next_nonnote_insn (first);
5106 if (arm_cirrus_insn_p (t))
5109 if (arm_cirrus_insn_p (next_nonnote_insn (t)))
5113 emit_insn_after (gen_nop (), first);
5118 /* (float (blah)) is in parallel with a clobber. */
5119 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
5120 body = XVECEXP (body, 0, 0);
5122 if (GET_CODE (body) == SET)
5124 rtx lhs = XEXP (body, 0), rhs = XEXP (body, 1);
5126 /* cfldrd, cfldr64, cfstrd, cfstr64 must
5127 be followed by a non Cirrus insn. */
5128 if (get_attr_cirrus (first) == CIRRUS_DOUBLE)
5130 if (arm_cirrus_insn_p (next_nonnote_insn (first)))
5131 emit_insn_after (gen_nop (), first);
5135 else if (arm_memory_load_p (first))
5137 unsigned int arm_regno;
5139 /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr,
5140 ldr/cfmv64hr combination where the Rd field is the same
5141 in both instructions must be split with a non Cirrus
5148 /* Get Arm register number for ldr insn. */
5149 if (GET_CODE (lhs) == REG)
5150 arm_regno = REGNO (lhs);
5151 else if (GET_CODE (rhs) == REG)
5152 arm_regno = REGNO (rhs);
5157 first = next_nonnote_insn (first);
5159 if (! arm_cirrus_insn_p (first))
5162 body = PATTERN (first);
5164 /* (float (blah)) is in parallel with a clobber. */
5165 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0))
5166 body = XVECEXP (body, 0, 0);
5168 if (GET_CODE (body) == FLOAT)
5169 body = XEXP (body, 0);
5171 if (get_attr_cirrus (first) == CIRRUS_MOVE
5172 && GET_CODE (XEXP (body, 1)) == REG
5173 && arm_regno == REGNO (XEXP (body, 1)))
5174 emit_insn_after (gen_nop (), first);
5180 /* get_attr aborts on USE and CLOBBER. */
5182 || GET_CODE (first) != INSN
5183 || GET_CODE (PATTERN (first)) == USE
5184 || GET_CODE (PATTERN (first)) == CLOBBER)
5187 attr = get_attr_cirrus (first);
5189 /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...)
5190 must be followed by a non-coprocessor instruction. */
5191 if (attr == CIRRUS_COMPARE)
5195 t = next_nonnote_insn (first);
5197 if (arm_cirrus_insn_p (t))
5200 if (arm_cirrus_insn_p (next_nonnote_insn (t)))
5204 emit_insn_after (gen_nop (), first);
5210 /* Return nonzero if OP is a constant power of two. */
5212 power_of_two_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
5214 if (GET_CODE (op) == CONST_INT)
5216 HOST_WIDE_INT value = INTVAL (op);
5218 return value != 0 && (value & (value - 1)) == 0;
5224 /* Return TRUE for a valid operand of a DImode operation.
5225 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
5226 Note that this disallows MEM(REG+REG), but allows
5227 MEM(PRE/POST_INC/DEC(REG)). */
5229 di_operand (rtx op, enum machine_mode mode)
5231 if (s_register_operand (op, mode))
5234 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && GET_MODE (op) != DImode)
5237 if (GET_CODE (op) == SUBREG)
5238 op = SUBREG_REG (op);
5240 switch (GET_CODE (op))
5247 return memory_address_p (DImode, XEXP (op, 0));
5254 /* Like di_operand, but don't accept constants. */
5256 nonimmediate_di_operand (rtx op, enum machine_mode mode)
5258 if (s_register_operand (op, mode))
5261 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && GET_MODE (op) != DImode)
5264 if (GET_CODE (op) == SUBREG)
5265 op = SUBREG_REG (op);
5267 if (GET_CODE (op) == MEM)
5268 return memory_address_p (DImode, XEXP (op, 0));
5273 /* Return TRUE for a valid operand of a DFmode operation when soft-float.
5274 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
5275 Note that this disallows MEM(REG+REG), but allows
5276 MEM(PRE/POST_INC/DEC(REG)). */
5278 soft_df_operand (rtx op, enum machine_mode mode)
5280 if (s_register_operand (op, mode))
5283 if (mode != VOIDmode && GET_MODE (op) != mode)
5286 if (GET_CODE (op) == SUBREG && CONSTANT_P (SUBREG_REG (op)))
5289 if (GET_CODE (op) == SUBREG)
5290 op = SUBREG_REG (op);
5292 switch (GET_CODE (op))
5298 return memory_address_p (DFmode, XEXP (op, 0));
5305 /* Like soft_df_operand, but don't accept constants. */
5307 nonimmediate_soft_df_operand (rtx op, enum machine_mode mode)
5309 if (s_register_operand (op, mode))
5312 if (mode != VOIDmode && GET_MODE (op) != mode)
5315 if (GET_CODE (op) == SUBREG)
5316 op = SUBREG_REG (op);
5318 if (GET_CODE (op) == MEM)
5319 return memory_address_p (DFmode, XEXP (op, 0));
5323 /* Return TRUE for valid index operands. */
5325 index_operand (rtx op, enum machine_mode mode)
5327 return (s_register_operand (op, mode)
5328 || (immediate_operand (op, mode)
5329 && (GET_CODE (op) != CONST_INT
5330 || (INTVAL (op) < 4096 && INTVAL (op) > -4096))));
5333 /* Return TRUE for valid shifts by a constant. This also accepts any
5334 power of two on the (somewhat overly relaxed) assumption that the
5335 shift operator in this case was a mult. */
5337 const_shift_operand (rtx op, enum machine_mode mode)
5339 return (power_of_two_operand (op, mode)
5340 || (immediate_operand (op, mode)
5341 && (GET_CODE (op) != CONST_INT
5342 || (INTVAL (op) < 32 && INTVAL (op) > 0))));
5345 /* Return TRUE for arithmetic operators which can be combined with a multiply
5348 shiftable_operator (rtx x, enum machine_mode mode)
5352 if (GET_MODE (x) != mode)
5355 code = GET_CODE (x);
5357 return (code == PLUS || code == MINUS
5358 || code == IOR || code == XOR || code == AND);
5361 /* Return TRUE for binary logical operators. */
5363 logical_binary_operator (rtx x, enum machine_mode mode)
5367 if (GET_MODE (x) != mode)
5370 code = GET_CODE (x);
5372 return (code == IOR || code == XOR || code == AND);
5375 /* Return TRUE for shift operators. */
5377 shift_operator (rtx x,enum machine_mode mode)
5381 if (GET_MODE (x) != mode)
5384 code = GET_CODE (x);
5387 return power_of_two_operand (XEXP (x, 1), mode);
5389 return (code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT
5390 || code == ROTATERT);
5393 /* Return TRUE if x is EQ or NE. */
5395 equality_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
5397 return GET_CODE (x) == EQ || GET_CODE (x) == NE;
5400 /* Return TRUE if x is a comparison operator other than LTGT or UNEQ. */
5402 arm_comparison_operator (rtx x, enum machine_mode mode)
5404 return (comparison_operator (x, mode)
5405 && GET_CODE (x) != LTGT
5406 && GET_CODE (x) != UNEQ);
5409 /* Return TRUE for SMIN SMAX UMIN UMAX operators. */
5411 minmax_operator (rtx x, enum machine_mode mode)
5413 enum rtx_code code = GET_CODE (x);
5415 if (GET_MODE (x) != mode)
5418 return code == SMIN || code == SMAX || code == UMIN || code == UMAX;
5421 /* Return TRUE if this is the condition code register, if we aren't given
5422 a mode, accept any class CCmode register. */
5424 cc_register (rtx x, enum machine_mode mode)
5426 if (mode == VOIDmode)
5428 mode = GET_MODE (x);
5430 if (GET_MODE_CLASS (mode) != MODE_CC)
5434 if ( GET_MODE (x) == mode
5435 && GET_CODE (x) == REG
5436 && REGNO (x) == CC_REGNUM)
5442 /* Return TRUE if this is the condition code register, if we aren't given
5443 a mode, accept any class CCmode register which indicates a dominance
5446 dominant_cc_register (rtx x, enum machine_mode mode)
5448 if (mode == VOIDmode)
5450 mode = GET_MODE (x);
5452 if (GET_MODE_CLASS (mode) != MODE_CC)
5456 if (mode != CC_DNEmode && mode != CC_DEQmode
5457 && mode != CC_DLEmode && mode != CC_DLTmode
5458 && mode != CC_DGEmode && mode != CC_DGTmode
5459 && mode != CC_DLEUmode && mode != CC_DLTUmode
5460 && mode != CC_DGEUmode && mode != CC_DGTUmode)
5463 return cc_register (x, mode);
5466 /* Return TRUE if X references a SYMBOL_REF. */
5468 symbol_mentioned_p (rtx x)
5473 if (GET_CODE (x) == SYMBOL_REF)
5476 fmt = GET_RTX_FORMAT (GET_CODE (x));
5478 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5484 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5485 if (symbol_mentioned_p (XVECEXP (x, i, j)))
5488 else if (fmt[i] == 'e' && symbol_mentioned_p (XEXP (x, i)))
5495 /* Return TRUE if X references a LABEL_REF. */
5497 label_mentioned_p (rtx x)
5502 if (GET_CODE (x) == LABEL_REF)
5505 fmt = GET_RTX_FORMAT (GET_CODE (x));
5506 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5512 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5513 if (label_mentioned_p (XVECEXP (x, i, j)))
5516 else if (fmt[i] == 'e' && label_mentioned_p (XEXP (x, i)))
5526 enum rtx_code code = GET_CODE (x);
5530 else if (code == SMIN)
5532 else if (code == UMIN)
5534 else if (code == UMAX)
5540 /* Return 1 if memory locations are adjacent. */
5542 adjacent_mem_locations (rtx a, rtx b)
5544 if ((GET_CODE (XEXP (a, 0)) == REG
5545 || (GET_CODE (XEXP (a, 0)) == PLUS
5546 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
5547 && (GET_CODE (XEXP (b, 0)) == REG
5548 || (GET_CODE (XEXP (b, 0)) == PLUS
5549 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
5551 int val0 = 0, val1 = 0;
5554 if (GET_CODE (XEXP (a, 0)) == PLUS)
5556 reg0 = REGNO (XEXP (XEXP (a, 0), 0));
5557 val0 = INTVAL (XEXP (XEXP (a, 0), 1));
5560 reg0 = REGNO (XEXP (a, 0));
5562 if (GET_CODE (XEXP (b, 0)) == PLUS)
5564 reg1 = REGNO (XEXP (XEXP (b, 0), 0));
5565 val1 = INTVAL (XEXP (XEXP (b, 0), 1));
5568 reg1 = REGNO (XEXP (b, 0));
5570 /* Don't accept any offset that will require multiple
5571 instructions to handle, since this would cause the
5572 arith_adjacentmem pattern to output an overlong sequence. */
5573 if (!const_ok_for_op (PLUS, val0) || !const_ok_for_op (PLUS, val1))
5576 return (reg0 == reg1) && ((val1 - val0) == 4 || (val0 - val1) == 4);
5581 /* Return 1 if OP is a load multiple operation. It is known to be
5582 parallel and the first section will be tested. */
5584 load_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
5586 HOST_WIDE_INT count = XVECLEN (op, 0);
5589 HOST_WIDE_INT i = 1, base = 0;
5593 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
5596 /* Check to see if this might be a write-back. */
5597 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
5602 /* Now check it more carefully. */
5603 if (GET_CODE (SET_DEST (elt)) != REG
5604 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
5605 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
5606 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4)
5610 /* Perform a quick check so we don't blow up below. */
5612 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
5613 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != REG
5614 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != MEM)
5617 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, i - 1)));
5618 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, i - 1)), 0);
5620 for (; i < count; i++)
5622 elt = XVECEXP (op, 0, i);
5624 if (GET_CODE (elt) != SET
5625 || GET_CODE (SET_DEST (elt)) != REG
5626 || GET_MODE (SET_DEST (elt)) != SImode
5627 || REGNO (SET_DEST (elt)) != (unsigned int)(dest_regno + i - base)
5628 || GET_CODE (SET_SRC (elt)) != MEM
5629 || GET_MODE (SET_SRC (elt)) != SImode
5630 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
5631 || !rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
5632 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
5633 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != (i - base) * 4)
5640 /* Return 1 if OP is a store multiple operation. It is known to be
5641 parallel and the first section will be tested. */
5643 store_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
5645 HOST_WIDE_INT count = XVECLEN (op, 0);
5648 HOST_WIDE_INT i = 1, base = 0;
5652 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
5655 /* Check to see if this might be a write-back. */
5656 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
5661 /* Now check it more carefully. */
5662 if (GET_CODE (SET_DEST (elt)) != REG
5663 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
5664 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
5665 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4)
5669 /* Perform a quick check so we don't blow up below. */
5671 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
5672 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != MEM
5673 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != REG)
5676 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, i - 1)));
5677 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, i - 1)), 0);
5679 for (; i < count; i++)
5681 elt = XVECEXP (op, 0, i);
5683 if (GET_CODE (elt) != SET
5684 || GET_CODE (SET_SRC (elt)) != REG
5685 || GET_MODE (SET_SRC (elt)) != SImode
5686 || REGNO (SET_SRC (elt)) != (unsigned int)(src_regno + i - base)
5687 || GET_CODE (SET_DEST (elt)) != MEM
5688 || GET_MODE (SET_DEST (elt)) != SImode
5689 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
5690 || !rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
5691 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
5692 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != (i - base) * 4)
5700 load_multiple_sequence (rtx *operands, int nops, int *regs, int *base,
5701 HOST_WIDE_INT *load_offset)
5703 int unsorted_regs[4];
5704 HOST_WIDE_INT unsorted_offsets[4];
5709 /* Can only handle 2, 3, or 4 insns at present,
5710 though could be easily extended if required. */
5711 if (nops < 2 || nops > 4)
5714 /* Loop over the operands and check that the memory references are
5715 suitable (ie immediate offsets from the same base register). At
5716 the same time, extract the target register, and the memory
5718 for (i = 0; i < nops; i++)
5723 /* Convert a subreg of a mem into the mem itself. */
5724 if (GET_CODE (operands[nops + i]) == SUBREG)
5725 operands[nops + i] = alter_subreg (operands + (nops + i));
5727 if (GET_CODE (operands[nops + i]) != MEM)
5730 /* Don't reorder volatile memory references; it doesn't seem worth
5731 looking for the case where the order is ok anyway. */
5732 if (MEM_VOLATILE_P (operands[nops + i]))
5735 offset = const0_rtx;
5737 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
5738 || (GET_CODE (reg) == SUBREG
5739 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
5740 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
5741 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
5743 || (GET_CODE (reg) == SUBREG
5744 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
5745 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
5750 base_reg = REGNO (reg);
5751 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
5752 ? REGNO (operands[i])
5753 : REGNO (SUBREG_REG (operands[i])));
5758 if (base_reg != (int) REGNO (reg))
5759 /* Not addressed from the same base register. */
5762 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
5763 ? REGNO (operands[i])
5764 : REGNO (SUBREG_REG (operands[i])));
5765 if (unsorted_regs[i] < unsorted_regs[order[0]])
5769 /* If it isn't an integer register, or if it overwrites the
5770 base register but isn't the last insn in the list, then
5771 we can't do this. */
5772 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14
5773 || (i != nops - 1 && unsorted_regs[i] == base_reg))
5776 unsorted_offsets[i] = INTVAL (offset);
5779 /* Not a suitable memory address. */
5783 /* All the useful information has now been extracted from the
5784 operands into unsorted_regs and unsorted_offsets; additionally,
5785 order[0] has been set to the lowest numbered register in the
5786 list. Sort the registers into order, and check that the memory
5787 offsets are ascending and adjacent. */
5789 for (i = 1; i < nops; i++)
5793 order[i] = order[i - 1];
5794 for (j = 0; j < nops; j++)
5795 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
5796 && (order[i] == order[i - 1]
5797 || unsorted_regs[j] < unsorted_regs[order[i]]))
5800 /* Have we found a suitable register? if not, one must be used more
5802 if (order[i] == order[i - 1])
5805 /* Is the memory address adjacent and ascending? */
5806 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
5814 for (i = 0; i < nops; i++)
5815 regs[i] = unsorted_regs[order[i]];
5817 *load_offset = unsorted_offsets[order[0]];
5820 if (unsorted_offsets[order[0]] == 0)
5821 return 1; /* ldmia */
5823 if (unsorted_offsets[order[0]] == 4)
5824 return 2; /* ldmib */
5826 if (unsorted_offsets[order[nops - 1]] == 0)
5827 return 3; /* ldmda */
5829 if (unsorted_offsets[order[nops - 1]] == -4)
5830 return 4; /* ldmdb */
5832 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
5833 if the offset isn't small enough. The reason 2 ldrs are faster
5834 is because these ARMs are able to do more than one cache access
5835 in a single cycle. The ARM9 and StrongARM have Harvard caches,
5836 whilst the ARM8 has a double bandwidth cache. This means that
5837 these cores can do both an instruction fetch and a data fetch in
5838 a single cycle, so the trick of calculating the address into a
5839 scratch register (one of the result regs) and then doing a load
5840 multiple actually becomes slower (and no smaller in code size).
5841 That is the transformation
5843 ldr rd1, [rbase + offset]
5844 ldr rd2, [rbase + offset + 4]
5848 add rd1, rbase, offset
5849 ldmia rd1, {rd1, rd2}
5851 produces worse code -- '3 cycles + any stalls on rd2' instead of
5852 '2 cycles + any stalls on rd2'. On ARMs with only one cache
5853 access per cycle, the first sequence could never complete in less
5854 than 6 cycles, whereas the ldm sequence would only take 5 and
5855 would make better use of sequential accesses if not hitting the
5858 We cheat here and test 'arm_ld_sched' which we currently know to
5859 only be true for the ARM8, ARM9 and StrongARM. If this ever
5860 changes, then the test below needs to be reworked. */
5861 if (nops == 2 && arm_ld_sched)
5864 /* Can't do it without setting up the offset, only do this if it takes
5865 no more than one insn. */
5866 return (const_ok_for_arm (unsorted_offsets[order[0]])
5867 || const_ok_for_arm (-unsorted_offsets[order[0]])) ? 5 : 0;
5871 emit_ldm_seq (rtx *operands, int nops)
5875 HOST_WIDE_INT offset;
5879 switch (load_multiple_sequence (operands, nops, regs, &base_reg, &offset))
5882 strcpy (buf, "ldm%?ia\t");
5886 strcpy (buf, "ldm%?ib\t");
5890 strcpy (buf, "ldm%?da\t");
5894 strcpy (buf, "ldm%?db\t");
5899 sprintf (buf, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
5900 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
5903 sprintf (buf, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
5904 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
5906 output_asm_insn (buf, operands);
5908 strcpy (buf, "ldm%?ia\t");
5915 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
5916 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
5918 for (i = 1; i < nops; i++)
5919 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
5920 reg_names[regs[i]]);
5922 strcat (buf, "}\t%@ phole ldm");
5924 output_asm_insn (buf, operands);
5929 store_multiple_sequence (rtx *operands, int nops, int *regs, int *base,
5930 HOST_WIDE_INT * load_offset)
5932 int unsorted_regs[4];
5933 HOST_WIDE_INT unsorted_offsets[4];
5938 /* Can only handle 2, 3, or 4 insns at present, though could be easily
5939 extended if required. */
5940 if (nops < 2 || nops > 4)
5943 /* Loop over the operands and check that the memory references are
5944 suitable (ie immediate offsets from the same base register). At
5945 the same time, extract the target register, and the memory
5947 for (i = 0; i < nops; i++)
5952 /* Convert a subreg of a mem into the mem itself. */
5953 if (GET_CODE (operands[nops + i]) == SUBREG)
5954 operands[nops + i] = alter_subreg (operands + (nops + i));
5956 if (GET_CODE (operands[nops + i]) != MEM)
5959 /* Don't reorder volatile memory references; it doesn't seem worth
5960 looking for the case where the order is ok anyway. */
5961 if (MEM_VOLATILE_P (operands[nops + i]))
5964 offset = const0_rtx;
5966 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
5967 || (GET_CODE (reg) == SUBREG
5968 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
5969 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
5970 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
5972 || (GET_CODE (reg) == SUBREG
5973 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
5974 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
5979 base_reg = REGNO (reg);
5980 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
5981 ? REGNO (operands[i])
5982 : REGNO (SUBREG_REG (operands[i])));
5987 if (base_reg != (int) REGNO (reg))
5988 /* Not addressed from the same base register. */
5991 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
5992 ? REGNO (operands[i])
5993 : REGNO (SUBREG_REG (operands[i])));
5994 if (unsorted_regs[i] < unsorted_regs[order[0]])
5998 /* If it isn't an integer register, then we can't do this. */
5999 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14)
6002 unsorted_offsets[i] = INTVAL (offset);
6005 /* Not a suitable memory address. */
6009 /* All the useful information has now been extracted from the
6010 operands into unsorted_regs and unsorted_offsets; additionally,
6011 order[0] has been set to the lowest numbered register in the
6012 list. Sort the registers into order, and check that the memory
6013 offsets are ascending and adjacent. */
6015 for (i = 1; i < nops; i++)
6019 order[i] = order[i - 1];
6020 for (j = 0; j < nops; j++)
6021 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
6022 && (order[i] == order[i - 1]
6023 || unsorted_regs[j] < unsorted_regs[order[i]]))
6026 /* Have we found a suitable register? if not, one must be used more
6028 if (order[i] == order[i - 1])
6031 /* Is the memory address adjacent and ascending? */
6032 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
6040 for (i = 0; i < nops; i++)
6041 regs[i] = unsorted_regs[order[i]];
6043 *load_offset = unsorted_offsets[order[0]];
6046 if (unsorted_offsets[order[0]] == 0)
6047 return 1; /* stmia */
6049 if (unsorted_offsets[order[0]] == 4)
6050 return 2; /* stmib */
6052 if (unsorted_offsets[order[nops - 1]] == 0)
6053 return 3; /* stmda */
6055 if (unsorted_offsets[order[nops - 1]] == -4)
6056 return 4; /* stmdb */
6062 emit_stm_seq (rtx *operands, int nops)
6066 HOST_WIDE_INT offset;
6070 switch (store_multiple_sequence (operands, nops, regs, &base_reg, &offset))
6073 strcpy (buf, "stm%?ia\t");
6077 strcpy (buf, "stm%?ib\t");
6081 strcpy (buf, "stm%?da\t");
6085 strcpy (buf, "stm%?db\t");
6092 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
6093 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
6095 for (i = 1; i < nops; i++)
6096 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
6097 reg_names[regs[i]]);
6099 strcat (buf, "}\t%@ phole stm");
6101 output_asm_insn (buf, operands);
6106 multi_register_push (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
6108 if (GET_CODE (op) != PARALLEL
6109 || (GET_CODE (XVECEXP (op, 0, 0)) != SET)
6110 || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC)
6111 || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPEC_PUSH_MULT))
6117 /* Routines for use in generating RTL. */
6120 arm_gen_load_multiple (int base_regno, int count, rtx from, int up,
6121 int write_back, rtx basemem, HOST_WIDE_INT *offsetp)
6123 HOST_WIDE_INT offset = *offsetp;
6126 int sign = up ? 1 : -1;
6129 /* XScale has load-store double instructions, but they have stricter
6130 alignment requirements than load-store multiple, so we cannot
6133 For XScale ldm requires 2 + NREGS cycles to complete and blocks
6134 the pipeline until completion.
6142 An ldr instruction takes 1-3 cycles, but does not block the
6151 Best case ldr will always win. However, the more ldr instructions
6152 we issue, the less likely we are to be able to schedule them well.
6153 Using ldr instructions also increases code size.
6155 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
6156 for counts of 3 or 4 regs. */
6157 if (arm_tune_xscale && count <= 2 && ! optimize_size)
6163 for (i = 0; i < count; i++)
6165 addr = plus_constant (from, i * 4 * sign);
6166 mem = adjust_automodify_address (basemem, SImode, addr, offset);
6167 emit_move_insn (gen_rtx_REG (SImode, base_regno + i), mem);
6173 emit_move_insn (from, plus_constant (from, count * 4 * sign));
6183 result = gen_rtx_PARALLEL (VOIDmode,
6184 rtvec_alloc (count + (write_back ? 1 : 0)));
6187 XVECEXP (result, 0, 0)
6188 = gen_rtx_SET (GET_MODE (from), from,
6189 plus_constant (from, count * 4 * sign));
6194 for (j = 0; i < count; i++, j++)
6196 addr = plus_constant (from, j * 4 * sign);
6197 mem = adjust_automodify_address_nv (basemem, SImode, addr, offset);
6198 XVECEXP (result, 0, i)
6199 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, base_regno + j), mem);
6210 arm_gen_store_multiple (int base_regno, int count, rtx to, int up,
6211 int write_back, rtx basemem, HOST_WIDE_INT *offsetp)
6213 HOST_WIDE_INT offset = *offsetp;
6216 int sign = up ? 1 : -1;
6219 /* See arm_gen_load_multiple for discussion of
6220 the pros/cons of ldm/stm usage for XScale. */
6221 if (arm_tune_xscale && count <= 2 && ! optimize_size)
6227 for (i = 0; i < count; i++)
6229 addr = plus_constant (to, i * 4 * sign);
6230 mem = adjust_automodify_address (basemem, SImode, addr, offset);
6231 emit_move_insn (mem, gen_rtx_REG (SImode, base_regno + i));
6237 emit_move_insn (to, plus_constant (to, count * 4 * sign));
6247 result = gen_rtx_PARALLEL (VOIDmode,
6248 rtvec_alloc (count + (write_back ? 1 : 0)));
6251 XVECEXP (result, 0, 0)
6252 = gen_rtx_SET (GET_MODE (to), to,
6253 plus_constant (to, count * 4 * sign));
6258 for (j = 0; i < count; i++, j++)
6260 addr = plus_constant (to, j * 4 * sign);
6261 mem = adjust_automodify_address_nv (basemem, SImode, addr, offset);
6262 XVECEXP (result, 0, i)
6263 = gen_rtx_SET (VOIDmode, mem, gen_rtx_REG (SImode, base_regno + j));
6274 arm_gen_movmemqi (rtx *operands)
6276 HOST_WIDE_INT in_words_to_go, out_words_to_go, last_bytes;
6277 HOST_WIDE_INT srcoffset, dstoffset;
6279 rtx src, dst, srcbase, dstbase;
6280 rtx part_bytes_reg = NULL;
6283 if (GET_CODE (operands[2]) != CONST_INT
6284 || GET_CODE (operands[3]) != CONST_INT
6285 || INTVAL (operands[2]) > 64
6286 || INTVAL (operands[3]) & 3)
6289 dstbase = operands[0];
6290 srcbase = operands[1];
6292 dst = copy_to_mode_reg (SImode, XEXP (dstbase, 0));
6293 src = copy_to_mode_reg (SImode, XEXP (srcbase, 0));
6295 in_words_to_go = ARM_NUM_INTS (INTVAL (operands[2]));
6296 out_words_to_go = INTVAL (operands[2]) / 4;
6297 last_bytes = INTVAL (operands[2]) & 3;
6298 dstoffset = srcoffset = 0;
6300 if (out_words_to_go != in_words_to_go && ((in_words_to_go - 1) & 3) != 0)
6301 part_bytes_reg = gen_rtx_REG (SImode, (in_words_to_go - 1) & 3);
6303 for (i = 0; in_words_to_go >= 2; i+=4)
6305 if (in_words_to_go > 4)
6306 emit_insn (arm_gen_load_multiple (0, 4, src, TRUE, TRUE,
6307 srcbase, &srcoffset));
6309 emit_insn (arm_gen_load_multiple (0, in_words_to_go, src, TRUE,
6310 FALSE, srcbase, &srcoffset));
6312 if (out_words_to_go)
6314 if (out_words_to_go > 4)
6315 emit_insn (arm_gen_store_multiple (0, 4, dst, TRUE, TRUE,
6316 dstbase, &dstoffset));
6317 else if (out_words_to_go != 1)
6318 emit_insn (arm_gen_store_multiple (0, out_words_to_go,
6322 dstbase, &dstoffset));
6325 mem = adjust_automodify_address (dstbase, SImode, dst, dstoffset);
6326 emit_move_insn (mem, gen_rtx_REG (SImode, 0));
6327 if (last_bytes != 0)
6329 emit_insn (gen_addsi3 (dst, dst, GEN_INT (4)));
6335 in_words_to_go -= in_words_to_go < 4 ? in_words_to_go : 4;
6336 out_words_to_go -= out_words_to_go < 4 ? out_words_to_go : 4;
6339 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
6340 if (out_words_to_go)
6344 mem = adjust_automodify_address (srcbase, SImode, src, srcoffset);
6345 sreg = copy_to_reg (mem);
6347 mem = adjust_automodify_address (dstbase, SImode, dst, dstoffset);
6348 emit_move_insn (mem, sreg);
6351 if (in_words_to_go) /* Sanity check */
6357 if (in_words_to_go < 0)
6360 mem = adjust_automodify_address (srcbase, SImode, src, srcoffset);
6361 part_bytes_reg = copy_to_mode_reg (SImode, mem);
6364 if (last_bytes && part_bytes_reg == NULL)
6367 if (BYTES_BIG_ENDIAN && last_bytes)
6369 rtx tmp = gen_reg_rtx (SImode);
6371 /* The bytes we want are in the top end of the word. */
6372 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg,
6373 GEN_INT (8 * (4 - last_bytes))));
6374 part_bytes_reg = tmp;
6378 mem = adjust_automodify_address (dstbase, QImode,
6379 plus_constant (dst, last_bytes - 1),
6380 dstoffset + last_bytes - 1);
6381 emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
6385 tmp = gen_reg_rtx (SImode);
6386 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8)));
6387 part_bytes_reg = tmp;
6396 mem = adjust_automodify_address (dstbase, HImode, dst, dstoffset);
6397 emit_move_insn (mem, gen_lowpart (HImode, part_bytes_reg));
6401 rtx tmp = gen_reg_rtx (SImode);
6402 emit_insn (gen_addsi3 (dst, dst, const2_rtx));
6403 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (16)));
6404 part_bytes_reg = tmp;
6411 mem = adjust_automodify_address (dstbase, QImode, dst, dstoffset);
6412 emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
6419 /* Generate a memory reference for a half word, such that it will be loaded
6420 into the top 16 bits of the word. We can assume that the address is
6421 known to be alignable and of the form reg, or plus (reg, const). */
6424 arm_gen_rotated_half_load (rtx memref)
6426 HOST_WIDE_INT offset = 0;
6427 rtx base = XEXP (memref, 0);
6429 if (GET_CODE (base) == PLUS)
6431 offset = INTVAL (XEXP (base, 1));
6432 base = XEXP (base, 0);
6435 /* If we aren't allowed to generate unaligned addresses, then fail. */
6436 if ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 0))
6439 base = gen_rtx_MEM (SImode, plus_constant (base, offset & ~2));
6441 if ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 2))
6444 return gen_rtx_ROTATE (SImode, base, GEN_INT (16));
6447 /* Select a dominance comparison mode if possible for a test of the general
6448 form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms.
6449 COND_OR == DOM_CC_X_AND_Y => (X && Y)
6450 COND_OR == DOM_CC_NX_OR_Y => ((! X) || Y)
6451 COND_OR == DOM_CC_X_OR_Y => (X || Y)
6452 In all cases OP will be either EQ or NE, but we don't need to know which
6453 here. If we are unable to support a dominance comparison we return
6454 CC mode. This will then fail to match for the RTL expressions that
6455 generate this call. */
6457 arm_select_dominance_cc_mode (rtx x, rtx y, HOST_WIDE_INT cond_or)
6459 enum rtx_code cond1, cond2;
6462 /* Currently we will probably get the wrong result if the individual
6463 comparisons are not simple. This also ensures that it is safe to
6464 reverse a comparison if necessary. */
6465 if ((arm_select_cc_mode (cond1 = GET_CODE (x), XEXP (x, 0), XEXP (x, 1))
6467 || (arm_select_cc_mode (cond2 = GET_CODE (y), XEXP (y, 0), XEXP (y, 1))
6471 /* The if_then_else variant of this tests the second condition if the
6472 first passes, but is true if the first fails. Reverse the first
6473 condition to get a true "inclusive-or" expression. */
6474 if (cond_or == DOM_CC_NX_OR_Y)
6475 cond1 = reverse_condition (cond1);
6477 /* If the comparisons are not equal, and one doesn't dominate the other,
6478 then we can't do this. */
6480 && !comparison_dominates_p (cond1, cond2)
6481 && (swapped = 1, !comparison_dominates_p (cond2, cond1)))
6486 enum rtx_code temp = cond1;
6494 if (cond2 == EQ || cond_or == DOM_CC_X_AND_Y)
6499 case LE: return CC_DLEmode;
6500 case LEU: return CC_DLEUmode;
6501 case GE: return CC_DGEmode;
6502 case GEU: return CC_DGEUmode;
6509 if (cond2 == LT || cond_or == DOM_CC_X_AND_Y)
6518 if (cond2 == GT || cond_or == DOM_CC_X_AND_Y)
6527 if (cond2 == LTU || cond_or == DOM_CC_X_AND_Y)
6536 if (cond2 == GTU || cond_or == DOM_CC_X_AND_Y)
6544 /* The remaining cases only occur when both comparisons are the
6569 arm_select_cc_mode (enum rtx_code op, rtx x, rtx y)
6571 /* All floating point compares return CCFP if it is an equality
6572 comparison, and CCFPE otherwise. */
6573 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
6593 if (TARGET_HARD_FLOAT && TARGET_MAVERICK)
6602 /* A compare with a shifted operand. Because of canonicalization, the
6603 comparison will have to be swapped when we emit the assembler. */
6604 if (GET_MODE (y) == SImode && GET_CODE (y) == REG
6605 && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
6606 || GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE
6607 || GET_CODE (x) == ROTATERT))
6610 /* This is a special case that is used by combine to allow a
6611 comparison of a shifted byte load to be split into a zero-extend
6612 followed by a comparison of the shifted integer (only valid for
6613 equalities and unsigned inequalities). */
6614 if (GET_MODE (x) == SImode
6615 && GET_CODE (x) == ASHIFT
6616 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 24
6617 && GET_CODE (XEXP (x, 0)) == SUBREG
6618 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == MEM
6619 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == QImode
6620 && (op == EQ || op == NE
6621 || op == GEU || op == GTU || op == LTU || op == LEU)
6622 && GET_CODE (y) == CONST_INT)
6625 /* A construct for a conditional compare, if the false arm contains
6626 0, then both conditions must be true, otherwise either condition
6627 must be true. Not all conditions are possible, so CCmode is
6628 returned if it can't be done. */
6629 if (GET_CODE (x) == IF_THEN_ELSE
6630 && (XEXP (x, 2) == const0_rtx
6631 || XEXP (x, 2) == const1_rtx)
6632 && COMPARISON_P (XEXP (x, 0))
6633 && COMPARISON_P (XEXP (x, 1)))
6634 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
6635 INTVAL (XEXP (x, 2)));
6637 /* Alternate canonicalizations of the above. These are somewhat cleaner. */
6638 if (GET_CODE (x) == AND
6639 && COMPARISON_P (XEXP (x, 0))
6640 && COMPARISON_P (XEXP (x, 1)))
6641 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
6644 if (GET_CODE (x) == IOR
6645 && COMPARISON_P (XEXP (x, 0))
6646 && COMPARISON_P (XEXP (x, 1)))
6647 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
6650 /* An operation (on Thumb) where we want to test for a single bit.
6651 This is done by shifting that bit up into the top bit of a
6652 scratch register; we can then branch on the sign bit. */
6654 && GET_MODE (x) == SImode
6655 && (op == EQ || op == NE)
6656 && (GET_CODE (x) == ZERO_EXTRACT))
6659 /* An operation that sets the condition codes as a side-effect, the
6660 V flag is not set correctly, so we can only use comparisons where
6661 this doesn't matter. (For LT and GE we can use "mi" and "pl"
6663 if (GET_MODE (x) == SImode
6665 && (op == EQ || op == NE || op == LT || op == GE)
6666 && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
6667 || GET_CODE (x) == AND || GET_CODE (x) == IOR
6668 || GET_CODE (x) == XOR || GET_CODE (x) == MULT
6669 || GET_CODE (x) == NOT || GET_CODE (x) == NEG
6670 || GET_CODE (x) == LSHIFTRT
6671 || GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
6672 || GET_CODE (x) == ROTATERT
6673 || (TARGET_ARM && GET_CODE (x) == ZERO_EXTRACT)))
6676 if (GET_MODE (x) == QImode && (op == EQ || op == NE))
6679 if (GET_MODE (x) == SImode && (op == LTU || op == GEU)
6680 && GET_CODE (x) == PLUS
6681 && (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y)))
6687 /* X and Y are two things to compare using CODE. Emit the compare insn and
6688 return the rtx for register 0 in the proper mode. FP means this is a
6689 floating point compare: I don't think that it is needed on the arm. */
6691 arm_gen_compare_reg (enum rtx_code code, rtx x, rtx y)
6693 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
6694 rtx cc_reg = gen_rtx_REG (mode, CC_REGNUM);
6696 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
6697 gen_rtx_COMPARE (mode, x, y)));
6702 /* Generate a sequence of insns that will generate the correct return
6703 address mask depending on the physical architecture that the program
6706 arm_gen_return_addr_mask (void)
6708 rtx reg = gen_reg_rtx (Pmode);
6710 emit_insn (gen_return_addr_mask (reg));
6715 arm_reload_in_hi (rtx *operands)
6717 rtx ref = operands[1];
6719 HOST_WIDE_INT offset = 0;
6721 if (GET_CODE (ref) == SUBREG)
6723 offset = SUBREG_BYTE (ref);
6724 ref = SUBREG_REG (ref);
6727 if (GET_CODE (ref) == REG)
6729 /* We have a pseudo which has been spilt onto the stack; there
6730 are two cases here: the first where there is a simple
6731 stack-slot replacement and a second where the stack-slot is
6732 out of range, or is used as a subreg. */
6733 if (reg_equiv_mem[REGNO (ref)])
6735 ref = reg_equiv_mem[REGNO (ref)];
6736 base = find_replacement (&XEXP (ref, 0));
6739 /* The slot is out of range, or was dressed up in a SUBREG. */
6740 base = reg_equiv_address[REGNO (ref)];
6743 base = find_replacement (&XEXP (ref, 0));
6745 /* Handle the case where the address is too complex to be offset by 1. */
6746 if (GET_CODE (base) == MINUS
6747 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
6749 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6751 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
6754 else if (GET_CODE (base) == PLUS)
6756 /* The addend must be CONST_INT, or we would have dealt with it above. */
6757 HOST_WIDE_INT hi, lo;
6759 offset += INTVAL (XEXP (base, 1));
6760 base = XEXP (base, 0);
6762 /* Rework the address into a legal sequence of insns. */
6763 /* Valid range for lo is -4095 -> 4095 */
6766 : -((-offset) & 0xfff));
6768 /* Corner case, if lo is the max offset then we would be out of range
6769 once we have added the additional 1 below, so bump the msb into the
6770 pre-loading insn(s). */
6774 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff)
6775 ^ (HOST_WIDE_INT) 0x80000000)
6776 - (HOST_WIDE_INT) 0x80000000);
6778 if (hi + lo != offset)
6783 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6785 /* Get the base address; addsi3 knows how to handle constants
6786 that require more than one insn. */
6787 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
6793 /* Operands[2] may overlap operands[0] (though it won't overlap
6794 operands[1]), that's why we asked for a DImode reg -- so we can
6795 use the bit that does not overlap. */
6796 if (REGNO (operands[2]) == REGNO (operands[0]))
6797 scratch = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6799 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
6801 emit_insn (gen_zero_extendqisi2 (scratch,
6802 gen_rtx_MEM (QImode,
6803 plus_constant (base,
6805 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode, operands[0], 0),
6806 gen_rtx_MEM (QImode,
6807 plus_constant (base,
6809 if (!BYTES_BIG_ENDIAN)
6810 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
6811 gen_rtx_IOR (SImode,
6814 gen_rtx_SUBREG (SImode, operands[0], 0),
6818 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
6819 gen_rtx_IOR (SImode,
6820 gen_rtx_ASHIFT (SImode, scratch,
6822 gen_rtx_SUBREG (SImode, operands[0],
6826 /* Handle storing a half-word to memory during reload by synthesizing as two
6827 byte stores. Take care not to clobber the input values until after we
6828 have moved them somewhere safe. This code assumes that if the DImode
6829 scratch in operands[2] overlaps either the input value or output address
6830 in some way, then that value must die in this insn (we absolutely need
6831 two scratch registers for some corner cases). */
6833 arm_reload_out_hi (rtx *operands)
6835 rtx ref = operands[0];
6836 rtx outval = operands[1];
6838 HOST_WIDE_INT offset = 0;
6840 if (GET_CODE (ref) == SUBREG)
6842 offset = SUBREG_BYTE (ref);
6843 ref = SUBREG_REG (ref);
6846 if (GET_CODE (ref) == REG)
6848 /* We have a pseudo which has been spilt onto the stack; there
6849 are two cases here: the first where there is a simple
6850 stack-slot replacement and a second where the stack-slot is
6851 out of range, or is used as a subreg. */
6852 if (reg_equiv_mem[REGNO (ref)])
6854 ref = reg_equiv_mem[REGNO (ref)];
6855 base = find_replacement (&XEXP (ref, 0));
6858 /* The slot is out of range, or was dressed up in a SUBREG. */
6859 base = reg_equiv_address[REGNO (ref)];
6862 base = find_replacement (&XEXP (ref, 0));
6864 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
6866 /* Handle the case where the address is too complex to be offset by 1. */
6867 if (GET_CODE (base) == MINUS
6868 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
6870 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6872 /* Be careful not to destroy OUTVAL. */
6873 if (reg_overlap_mentioned_p (base_plus, outval))
6875 /* Updating base_plus might destroy outval, see if we can
6876 swap the scratch and base_plus. */
6877 if (!reg_overlap_mentioned_p (scratch, outval))
6880 scratch = base_plus;
6885 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
6887 /* Be conservative and copy OUTVAL into the scratch now,
6888 this should only be necessary if outval is a subreg
6889 of something larger than a word. */
6890 /* XXX Might this clobber base? I can't see how it can,
6891 since scratch is known to overlap with OUTVAL, and
6892 must be wider than a word. */
6893 emit_insn (gen_movhi (scratch_hi, outval));
6894 outval = scratch_hi;
6898 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
6901 else if (GET_CODE (base) == PLUS)
6903 /* The addend must be CONST_INT, or we would have dealt with it above. */
6904 HOST_WIDE_INT hi, lo;
6906 offset += INTVAL (XEXP (base, 1));
6907 base = XEXP (base, 0);
6909 /* Rework the address into a legal sequence of insns. */
6910 /* Valid range for lo is -4095 -> 4095 */
6913 : -((-offset) & 0xfff));
6915 /* Corner case, if lo is the max offset then we would be out of range
6916 once we have added the additional 1 below, so bump the msb into the
6917 pre-loading insn(s). */
6921 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff)
6922 ^ (HOST_WIDE_INT) 0x80000000)
6923 - (HOST_WIDE_INT) 0x80000000);
6925 if (hi + lo != offset)
6930 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6932 /* Be careful not to destroy OUTVAL. */
6933 if (reg_overlap_mentioned_p (base_plus, outval))
6935 /* Updating base_plus might destroy outval, see if we
6936 can swap the scratch and base_plus. */
6937 if (!reg_overlap_mentioned_p (scratch, outval))
6940 scratch = base_plus;
6945 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
6947 /* Be conservative and copy outval into scratch now,
6948 this should only be necessary if outval is a
6949 subreg of something larger than a word. */
6950 /* XXX Might this clobber base? I can't see how it
6951 can, since scratch is known to overlap with
6953 emit_insn (gen_movhi (scratch_hi, outval));
6954 outval = scratch_hi;
6958 /* Get the base address; addsi3 knows how to handle constants
6959 that require more than one insn. */
6960 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
6966 if (BYTES_BIG_ENDIAN)
6968 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
6969 plus_constant (base, offset + 1)),
6970 gen_lowpart (QImode, outval)));
6971 emit_insn (gen_lshrsi3 (scratch,
6972 gen_rtx_SUBREG (SImode, outval, 0),
6974 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
6975 gen_lowpart (QImode, scratch)));
6979 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
6980 gen_lowpart (QImode, outval)));
6981 emit_insn (gen_lshrsi3 (scratch,
6982 gen_rtx_SUBREG (SImode, outval, 0),
6984 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
6985 plus_constant (base, offset + 1)),
6986 gen_lowpart (QImode, scratch)));
6990 /* Print a symbolic form of X to the debug file, F. */
6992 arm_print_value (FILE *f, rtx x)
6994 switch (GET_CODE (x))
6997 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (x));
7001 fprintf (f, "<0x%lx,0x%lx>", (long)XWINT (x, 2), (long)XWINT (x, 3));
7009 for (i = 0; i < CONST_VECTOR_NUNITS (x); i++)
7011 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (CONST_VECTOR_ELT (x, i)));
7012 if (i < (CONST_VECTOR_NUNITS (x) - 1))
7020 fprintf (f, "\"%s\"", XSTR (x, 0));
7024 fprintf (f, "`%s'", XSTR (x, 0));
7028 fprintf (f, "L%d", INSN_UID (XEXP (x, 0)));
7032 arm_print_value (f, XEXP (x, 0));
7036 arm_print_value (f, XEXP (x, 0));
7038 arm_print_value (f, XEXP (x, 1));
7046 fprintf (f, "????");
7051 /* Routines for manipulation of the constant pool. */
7053 /* Arm instructions cannot load a large constant directly into a
7054 register; they have to come from a pc relative load. The constant
7055 must therefore be placed in the addressable range of the pc
7056 relative load. Depending on the precise pc relative load
7057 instruction the range is somewhere between 256 bytes and 4k. This
7058 means that we often have to dump a constant inside a function, and
7059 generate code to branch around it.
7061 It is important to minimize this, since the branches will slow
7062 things down and make the code larger.
7064 Normally we can hide the table after an existing unconditional
7065 branch so that there is no interruption of the flow, but in the
7066 worst case the code looks like this:
7084 We fix this by performing a scan after scheduling, which notices
7085 which instructions need to have their operands fetched from the
7086 constant table and builds the table.
7088 The algorithm starts by building a table of all the constants that
7089 need fixing up and all the natural barriers in the function (places
7090 where a constant table can be dropped without breaking the flow).
7091 For each fixup we note how far the pc-relative replacement will be
7092 able to reach and the offset of the instruction into the function.
7094 Having built the table we then group the fixes together to form
7095 tables that are as large as possible (subject to addressing
7096 constraints) and emit each table of constants after the last
7097 barrier that is within range of all the instructions in the group.
7098 If a group does not contain a barrier, then we forcibly create one
7099 by inserting a jump instruction into the flow. Once the table has
7100 been inserted, the insns are then modified to reference the
7101 relevant entry in the pool.
7103 Possible enhancements to the algorithm (not implemented) are:
7105 1) For some processors and object formats, there may be benefit in
7106 aligning the pools to the start of cache lines; this alignment
7107 would need to be taken into account when calculating addressability
7110 /* These typedefs are located at the start of this file, so that
7111 they can be used in the prototypes there. This comment is to
7112 remind readers of that fact so that the following structures
7113 can be understood more easily.
7115 typedef struct minipool_node Mnode;
7116 typedef struct minipool_fixup Mfix; */
7118 struct minipool_node
7120 /* Doubly linked chain of entries. */
7123 /* The maximum offset into the code that this entry can be placed. While
7124 pushing fixes for forward references, all entries are sorted in order
7125 of increasing max_address. */
7126 HOST_WIDE_INT max_address;
7127 /* Similarly for an entry inserted for a backwards ref. */
7128 HOST_WIDE_INT min_address;
7129 /* The number of fixes referencing this entry. This can become zero
7130 if we "unpush" an entry. In this case we ignore the entry when we
7131 come to emit the code. */
7133 /* The offset from the start of the minipool. */
7134 HOST_WIDE_INT offset;
7135 /* The value in table. */
7137 /* The mode of value. */
7138 enum machine_mode mode;
7139 /* The size of the value. With iWMMXt enabled
7140 sizes > 4 also imply an alignment of 8-bytes. */
7144 struct minipool_fixup
7148 HOST_WIDE_INT address;
7150 enum machine_mode mode;
7154 HOST_WIDE_INT forwards;
7155 HOST_WIDE_INT backwards;
7158 /* Fixes less than a word need padding out to a word boundary. */
7159 #define MINIPOOL_FIX_SIZE(mode) \
7160 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4)
7162 static Mnode * minipool_vector_head;
7163 static Mnode * minipool_vector_tail;
7164 static rtx minipool_vector_label;
7166 /* The linked list of all minipool fixes required for this function. */
7167 Mfix * minipool_fix_head;
7168 Mfix * minipool_fix_tail;
7169 /* The fix entry for the current minipool, once it has been placed. */
7170 Mfix * minipool_barrier;
7172 /* Determines if INSN is the start of a jump table. Returns the end
7173 of the TABLE or NULL_RTX. */
7175 is_jump_table (rtx insn)
7179 if (GET_CODE (insn) == JUMP_INSN
7180 && JUMP_LABEL (insn) != NULL
7181 && ((table = next_real_insn (JUMP_LABEL (insn)))
7182 == next_real_insn (insn))
7184 && GET_CODE (table) == JUMP_INSN
7185 && (GET_CODE (PATTERN (table)) == ADDR_VEC
7186 || GET_CODE (PATTERN (table)) == ADDR_DIFF_VEC))
7192 #ifndef JUMP_TABLES_IN_TEXT_SECTION
7193 #define JUMP_TABLES_IN_TEXT_SECTION 0
7196 static HOST_WIDE_INT
7197 get_jump_table_size (rtx insn)
7199 /* ADDR_VECs only take room if read-only data does into the text
7201 if (JUMP_TABLES_IN_TEXT_SECTION
7202 #if !defined(READONLY_DATA_SECTION) && !defined(READONLY_DATA_SECTION_ASM_OP)
7207 rtx body = PATTERN (insn);
7208 int elt = GET_CODE (body) == ADDR_DIFF_VEC ? 1 : 0;
7210 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, elt);
7216 /* Move a minipool fix MP from its current location to before MAX_MP.
7217 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
7218 constraints may need updating. */
7220 move_minipool_fix_forward_ref (Mnode *mp, Mnode *max_mp,
7221 HOST_WIDE_INT max_address)
7223 /* This should never be true and the code below assumes these are
7230 if (max_address < mp->max_address)
7231 mp->max_address = max_address;
7235 if (max_address > max_mp->max_address - mp->fix_size)
7236 mp->max_address = max_mp->max_address - mp->fix_size;
7238 mp->max_address = max_address;
7240 /* Unlink MP from its current position. Since max_mp is non-null,
7241 mp->prev must be non-null. */
7242 mp->prev->next = mp->next;
7243 if (mp->next != NULL)
7244 mp->next->prev = mp->prev;
7246 minipool_vector_tail = mp->prev;
7248 /* Re-insert it before MAX_MP. */
7250 mp->prev = max_mp->prev;
7253 if (mp->prev != NULL)
7254 mp->prev->next = mp;
7256 minipool_vector_head = mp;
7259 /* Save the new entry. */
7262 /* Scan over the preceding entries and adjust their addresses as
7264 while (mp->prev != NULL
7265 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
7267 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
7274 /* Add a constant to the minipool for a forward reference. Returns the
7275 node added or NULL if the constant will not fit in this pool. */
7277 add_minipool_forward_ref (Mfix *fix)
7279 /* If set, max_mp is the first pool_entry that has a lower
7280 constraint than the one we are trying to add. */
7281 Mnode * max_mp = NULL;
7282 HOST_WIDE_INT max_address = fix->address + fix->forwards;
7285 /* If this fix's address is greater than the address of the first
7286 entry, then we can't put the fix in this pool. We subtract the
7287 size of the current fix to ensure that if the table is fully
7288 packed we still have enough room to insert this value by suffling
7289 the other fixes forwards. */
7290 if (minipool_vector_head &&
7291 fix->address >= minipool_vector_head->max_address - fix->fix_size)
7294 /* Scan the pool to see if a constant with the same value has
7295 already been added. While we are doing this, also note the
7296 location where we must insert the constant if it doesn't already
7298 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
7300 if (GET_CODE (fix->value) == GET_CODE (mp->value)
7301 && fix->mode == mp->mode
7302 && (GET_CODE (fix->value) != CODE_LABEL
7303 || (CODE_LABEL_NUMBER (fix->value)
7304 == CODE_LABEL_NUMBER (mp->value)))
7305 && rtx_equal_p (fix->value, mp->value))
7307 /* More than one fix references this entry. */
7309 return move_minipool_fix_forward_ref (mp, max_mp, max_address);
7312 /* Note the insertion point if necessary. */
7314 && mp->max_address > max_address)
7317 /* If we are inserting an 8-bytes aligned quantity and
7318 we have not already found an insertion point, then
7319 make sure that all such 8-byte aligned quantities are
7320 placed at the start of the pool. */
7321 if (ARM_DOUBLEWORD_ALIGN
7323 && fix->fix_size == 8
7324 && mp->fix_size != 8)
7327 max_address = mp->max_address;
7331 /* The value is not currently in the minipool, so we need to create
7332 a new entry for it. If MAX_MP is NULL, the entry will be put on
7333 the end of the list since the placement is less constrained than
7334 any existing entry. Otherwise, we insert the new fix before
7335 MAX_MP and, if necessary, adjust the constraints on the other
7337 mp = xmalloc (sizeof (* mp));
7338 mp->fix_size = fix->fix_size;
7339 mp->mode = fix->mode;
7340 mp->value = fix->value;
7342 /* Not yet required for a backwards ref. */
7343 mp->min_address = -65536;
7347 mp->max_address = max_address;
7349 mp->prev = minipool_vector_tail;
7351 if (mp->prev == NULL)
7353 minipool_vector_head = mp;
7354 minipool_vector_label = gen_label_rtx ();
7357 mp->prev->next = mp;
7359 minipool_vector_tail = mp;
7363 if (max_address > max_mp->max_address - mp->fix_size)
7364 mp->max_address = max_mp->max_address - mp->fix_size;
7366 mp->max_address = max_address;
7369 mp->prev = max_mp->prev;
7371 if (mp->prev != NULL)
7372 mp->prev->next = mp;
7374 minipool_vector_head = mp;
7377 /* Save the new entry. */
7380 /* Scan over the preceding entries and adjust their addresses as
7382 while (mp->prev != NULL
7383 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
7385 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
7393 move_minipool_fix_backward_ref (Mnode *mp, Mnode *min_mp,
7394 HOST_WIDE_INT min_address)
7396 HOST_WIDE_INT offset;
7398 /* This should never be true, and the code below assumes these are
7405 if (min_address > mp->min_address)
7406 mp->min_address = min_address;
7410 /* We will adjust this below if it is too loose. */
7411 mp->min_address = min_address;
7413 /* Unlink MP from its current position. Since min_mp is non-null,
7414 mp->next must be non-null. */
7415 mp->next->prev = mp->prev;
7416 if (mp->prev != NULL)
7417 mp->prev->next = mp->next;
7419 minipool_vector_head = mp->next;
7421 /* Reinsert it after MIN_MP. */
7423 mp->next = min_mp->next;
7425 if (mp->next != NULL)
7426 mp->next->prev = mp;
7428 minipool_vector_tail = mp;
7434 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
7436 mp->offset = offset;
7437 if (mp->refcount > 0)
7438 offset += mp->fix_size;
7440 if (mp->next && mp->next->min_address < mp->min_address + mp->fix_size)
7441 mp->next->min_address = mp->min_address + mp->fix_size;
7447 /* Add a constant to the minipool for a backward reference. Returns the
7448 node added or NULL if the constant will not fit in this pool.
7450 Note that the code for insertion for a backwards reference can be
7451 somewhat confusing because the calculated offsets for each fix do
7452 not take into account the size of the pool (which is still under
7455 add_minipool_backward_ref (Mfix *fix)
7457 /* If set, min_mp is the last pool_entry that has a lower constraint
7458 than the one we are trying to add. */
7459 Mnode *min_mp = NULL;
7460 /* This can be negative, since it is only a constraint. */
7461 HOST_WIDE_INT min_address = fix->address - fix->backwards;
7464 /* If we can't reach the current pool from this insn, or if we can't
7465 insert this entry at the end of the pool without pushing other
7466 fixes out of range, then we don't try. This ensures that we
7467 can't fail later on. */
7468 if (min_address >= minipool_barrier->address
7469 || (minipool_vector_tail->min_address + fix->fix_size
7470 >= minipool_barrier->address))
7473 /* Scan the pool to see if a constant with the same value has
7474 already been added. While we are doing this, also note the
7475 location where we must insert the constant if it doesn't already
7477 for (mp = minipool_vector_tail; mp != NULL; mp = mp->prev)
7479 if (GET_CODE (fix->value) == GET_CODE (mp->value)
7480 && fix->mode == mp->mode
7481 && (GET_CODE (fix->value) != CODE_LABEL
7482 || (CODE_LABEL_NUMBER (fix->value)
7483 == CODE_LABEL_NUMBER (mp->value)))
7484 && rtx_equal_p (fix->value, mp->value)
7485 /* Check that there is enough slack to move this entry to the
7486 end of the table (this is conservative). */
7488 > (minipool_barrier->address
7489 + minipool_vector_tail->offset
7490 + minipool_vector_tail->fix_size)))
7493 return move_minipool_fix_backward_ref (mp, min_mp, min_address);
7497 mp->min_address += fix->fix_size;
7500 /* Note the insertion point if necessary. */
7501 if (mp->min_address < min_address)
7503 /* For now, we do not allow the insertion of 8-byte alignment
7504 requiring nodes anywhere but at the start of the pool. */
7505 if (ARM_DOUBLEWORD_ALIGN
7506 && fix->fix_size == 8 && mp->fix_size != 8)
7511 else if (mp->max_address
7512 < minipool_barrier->address + mp->offset + fix->fix_size)
7514 /* Inserting before this entry would push the fix beyond
7515 its maximum address (which can happen if we have
7516 re-located a forwards fix); force the new fix to come
7519 min_address = mp->min_address + fix->fix_size;
7521 /* If we are inserting an 8-bytes aligned quantity and
7522 we have not already found an insertion point, then
7523 make sure that all such 8-byte aligned quantities are
7524 placed at the start of the pool. */
7525 else if (ARM_DOUBLEWORD_ALIGN
7527 && fix->fix_size == 8
7528 && mp->fix_size < 8)
7531 min_address = mp->min_address + fix->fix_size;
7536 /* We need to create a new entry. */
7537 mp = xmalloc (sizeof (* mp));
7538 mp->fix_size = fix->fix_size;
7539 mp->mode = fix->mode;
7540 mp->value = fix->value;
7542 mp->max_address = minipool_barrier->address + 65536;
7544 mp->min_address = min_address;
7549 mp->next = minipool_vector_head;
7551 if (mp->next == NULL)
7553 minipool_vector_tail = mp;
7554 minipool_vector_label = gen_label_rtx ();
7557 mp->next->prev = mp;
7559 minipool_vector_head = mp;
7563 mp->next = min_mp->next;
7567 if (mp->next != NULL)
7568 mp->next->prev = mp;
7570 minipool_vector_tail = mp;
7573 /* Save the new entry. */
7581 /* Scan over the following entries and adjust their offsets. */
7582 while (mp->next != NULL)
7584 if (mp->next->min_address < mp->min_address + mp->fix_size)
7585 mp->next->min_address = mp->min_address + mp->fix_size;
7588 mp->next->offset = mp->offset + mp->fix_size;
7590 mp->next->offset = mp->offset;
7599 assign_minipool_offsets (Mfix *barrier)
7601 HOST_WIDE_INT offset = 0;
7604 minipool_barrier = barrier;
7606 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
7608 mp->offset = offset;
7610 if (mp->refcount > 0)
7611 offset += mp->fix_size;
7615 /* Output the literal table */
7617 dump_minipool (rtx scan)
7623 if (ARM_DOUBLEWORD_ALIGN)
7624 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
7625 if (mp->refcount > 0 && mp->fix_size == 8)
7633 ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n",
7634 INSN_UID (scan), (unsigned long) minipool_barrier->address, align64 ? 8 : 4);
7636 scan = emit_label_after (gen_label_rtx (), scan);
7637 scan = emit_insn_after (align64 ? gen_align_8 () : gen_align_4 (), scan);
7638 scan = emit_label_after (minipool_vector_label, scan);
7640 for (mp = minipool_vector_head; mp != NULL; mp = nmp)
7642 if (mp->refcount > 0)
7647 ";; Offset %u, min %ld, max %ld ",
7648 (unsigned) mp->offset, (unsigned long) mp->min_address,
7649 (unsigned long) mp->max_address);
7650 arm_print_value (dump_file, mp->value);
7651 fputc ('\n', dump_file);
7654 switch (mp->fix_size)
7656 #ifdef HAVE_consttable_1
7658 scan = emit_insn_after (gen_consttable_1 (mp->value), scan);
7662 #ifdef HAVE_consttable_2
7664 scan = emit_insn_after (gen_consttable_2 (mp->value), scan);
7668 #ifdef HAVE_consttable_4
7670 scan = emit_insn_after (gen_consttable_4 (mp->value), scan);
7674 #ifdef HAVE_consttable_8
7676 scan = emit_insn_after (gen_consttable_8 (mp->value), scan);
7690 minipool_vector_head = minipool_vector_tail = NULL;
7691 scan = emit_insn_after (gen_consttable_end (), scan);
7692 scan = emit_barrier_after (scan);
7695 /* Return the cost of forcibly inserting a barrier after INSN. */
7697 arm_barrier_cost (rtx insn)
7699 /* Basing the location of the pool on the loop depth is preferable,
7700 but at the moment, the basic block information seems to be
7701 corrupt by this stage of the compilation. */
7703 rtx next = next_nonnote_insn (insn);
7705 if (next != NULL && GET_CODE (next) == CODE_LABEL)
7708 switch (GET_CODE (insn))
7711 /* It will always be better to place the table before the label, rather
7720 return base_cost - 10;
7723 return base_cost + 10;
7727 /* Find the best place in the insn stream in the range
7728 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
7729 Create the barrier by inserting a jump and add a new fix entry for
7732 create_fix_barrier (Mfix *fix, HOST_WIDE_INT max_address)
7734 HOST_WIDE_INT count = 0;
7736 rtx from = fix->insn;
7737 rtx selected = from;
7739 HOST_WIDE_INT selected_address;
7741 HOST_WIDE_INT max_count = max_address - fix->address;
7742 rtx label = gen_label_rtx ();
7744 selected_cost = arm_barrier_cost (from);
7745 selected_address = fix->address;
7747 while (from && count < max_count)
7752 /* This code shouldn't have been called if there was a natural barrier
7754 if (GET_CODE (from) == BARRIER)
7757 /* Count the length of this insn. */
7758 count += get_attr_length (from);
7760 /* If there is a jump table, add its length. */
7761 tmp = is_jump_table (from);
7764 count += get_jump_table_size (tmp);
7766 /* Jump tables aren't in a basic block, so base the cost on
7767 the dispatch insn. If we select this location, we will
7768 still put the pool after the table. */
7769 new_cost = arm_barrier_cost (from);
7771 if (count < max_count && new_cost <= selected_cost)
7774 selected_cost = new_cost;
7775 selected_address = fix->address + count;
7778 /* Continue after the dispatch table. */
7779 from = NEXT_INSN (tmp);
7783 new_cost = arm_barrier_cost (from);
7785 if (count < max_count && new_cost <= selected_cost)
7788 selected_cost = new_cost;
7789 selected_address = fix->address + count;
7792 from = NEXT_INSN (from);
7795 /* Create a new JUMP_INSN that branches around a barrier. */
7796 from = emit_jump_insn_after (gen_jump (label), selected);
7797 JUMP_LABEL (from) = label;
7798 barrier = emit_barrier_after (from);
7799 emit_label_after (label, barrier);
7801 /* Create a minipool barrier entry for the new barrier. */
7802 new_fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* new_fix));
7803 new_fix->insn = barrier;
7804 new_fix->address = selected_address;
7805 new_fix->next = fix->next;
7806 fix->next = new_fix;
7811 /* Record that there is a natural barrier in the insn stream at
7814 push_minipool_barrier (rtx insn, HOST_WIDE_INT address)
7816 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
7819 fix->address = address;
7822 if (minipool_fix_head != NULL)
7823 minipool_fix_tail->next = fix;
7825 minipool_fix_head = fix;
7827 minipool_fix_tail = fix;
7830 /* Record INSN, which will need fixing up to load a value from the
7831 minipool. ADDRESS is the offset of the insn since the start of the
7832 function; LOC is a pointer to the part of the insn which requires
7833 fixing; VALUE is the constant that must be loaded, which is of type
7836 push_minipool_fix (rtx insn, HOST_WIDE_INT address, rtx *loc,
7837 enum machine_mode mode, rtx value)
7839 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
7841 #ifdef AOF_ASSEMBLER
7842 /* PIC symbol references need to be converted into offsets into the
7844 /* XXX This shouldn't be done here. */
7845 if (flag_pic && GET_CODE (value) == SYMBOL_REF)
7846 value = aof_pic_entry (value);
7847 #endif /* AOF_ASSEMBLER */
7850 fix->address = address;
7853 fix->fix_size = MINIPOOL_FIX_SIZE (mode);
7855 fix->forwards = get_attr_pool_range (insn);
7856 fix->backwards = get_attr_neg_pool_range (insn);
7857 fix->minipool = NULL;
7859 /* If an insn doesn't have a range defined for it, then it isn't
7860 expecting to be reworked by this code. Better to abort now than
7861 to generate duff assembly code. */
7862 if (fix->forwards == 0 && fix->backwards == 0)
7865 /* With AAPCS/iWMMXt enabled, the pool is aligned to an 8-byte boundary.
7866 So there might be an empty word before the start of the pool.
7867 Hence we reduce the forward range by 4 to allow for this
7869 if (ARM_DOUBLEWORD_ALIGN && fix->fix_size == 8)
7875 ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ",
7876 GET_MODE_NAME (mode),
7877 INSN_UID (insn), (unsigned long) address,
7878 -1 * (long)fix->backwards, (long)fix->forwards);
7879 arm_print_value (dump_file, fix->value);
7880 fprintf (dump_file, "\n");
7883 /* Add it to the chain of fixes. */
7886 if (minipool_fix_head != NULL)
7887 minipool_fix_tail->next = fix;
7889 minipool_fix_head = fix;
7891 minipool_fix_tail = fix;
7894 /* Scan INSN and note any of its operands that need fixing.
7895 If DO_PUSHES is false we do not actually push any of the fixups
7896 needed. The function returns TRUE is any fixups were needed/pushed.
7897 This is used by arm_memory_load_p() which needs to know about loads
7898 of constants that will be converted into minipool loads. */
7900 note_invalid_constants (rtx insn, HOST_WIDE_INT address, int do_pushes)
7902 bool result = false;
7905 extract_insn (insn);
7907 if (!constrain_operands (1))
7908 fatal_insn_not_found (insn);
7910 if (recog_data.n_alternatives == 0)
7913 /* Fill in recog_op_alt with information about the constraints of this insn. */
7914 preprocess_constraints ();
7916 for (opno = 0; opno < recog_data.n_operands; opno++)
7918 /* Things we need to fix can only occur in inputs. */
7919 if (recog_data.operand_type[opno] != OP_IN)
7922 /* If this alternative is a memory reference, then any mention
7923 of constants in this alternative is really to fool reload
7924 into allowing us to accept one there. We need to fix them up
7925 now so that we output the right code. */
7926 if (recog_op_alt[opno][which_alternative].memory_ok)
7928 rtx op = recog_data.operand[opno];
7930 if (CONSTANT_P (op))
7933 push_minipool_fix (insn, address, recog_data.operand_loc[opno],
7934 recog_data.operand_mode[opno], op);
7937 else if (GET_CODE (op) == MEM
7938 && GET_CODE (XEXP (op, 0)) == SYMBOL_REF
7939 && CONSTANT_POOL_ADDRESS_P (XEXP (op, 0)))
7943 rtx cop = avoid_constant_pool_reference (op);
7945 /* Casting the address of something to a mode narrower
7946 than a word can cause avoid_constant_pool_reference()
7947 to return the pool reference itself. That's no good to
7948 us here. Lets just hope that we can use the
7949 constant pool value directly. */
7951 cop = get_pool_constant (XEXP (op, 0));
7953 push_minipool_fix (insn, address,
7954 recog_data.operand_loc[opno],
7955 recog_data.operand_mode[opno], cop);
7966 /* Gcc puts the pool in the wrong place for ARM, since we can only
7967 load addresses a limited distance around the pc. We do some
7968 special munging to move the constant pool values to the correct
7969 point in the code. */
7974 HOST_WIDE_INT address = 0;
7977 minipool_fix_head = minipool_fix_tail = NULL;
7979 /* The first insn must always be a note, or the code below won't
7980 scan it properly. */
7981 insn = get_insns ();
7982 if (GET_CODE (insn) != NOTE)
7985 /* Scan all the insns and record the operands that will need fixing. */
7986 for (insn = next_nonnote_insn (insn); insn; insn = next_nonnote_insn (insn))
7988 if (TARGET_CIRRUS_FIX_INVALID_INSNS
7989 && (arm_cirrus_insn_p (insn)
7990 || GET_CODE (insn) == JUMP_INSN
7991 || arm_memory_load_p (insn)))
7992 cirrus_reorg (insn);
7994 if (GET_CODE (insn) == BARRIER)
7995 push_minipool_barrier (insn, address);
7996 else if (INSN_P (insn))
8000 note_invalid_constants (insn, address, true);
8001 address += get_attr_length (insn);
8003 /* If the insn is a vector jump, add the size of the table
8004 and skip the table. */
8005 if ((table = is_jump_table (insn)) != NULL)
8007 address += get_jump_table_size (table);
8013 fix = minipool_fix_head;
8015 /* Now scan the fixups and perform the required changes. */
8020 Mfix * last_added_fix;
8021 Mfix * last_barrier = NULL;
8024 /* Skip any further barriers before the next fix. */
8025 while (fix && GET_CODE (fix->insn) == BARRIER)
8028 /* No more fixes. */
8032 last_added_fix = NULL;
8034 for (ftmp = fix; ftmp; ftmp = ftmp->next)
8036 if (GET_CODE (ftmp->insn) == BARRIER)
8038 if (ftmp->address >= minipool_vector_head->max_address)
8041 last_barrier = ftmp;
8043 else if ((ftmp->minipool = add_minipool_forward_ref (ftmp)) == NULL)
8046 last_added_fix = ftmp; /* Keep track of the last fix added. */
8049 /* If we found a barrier, drop back to that; any fixes that we
8050 could have reached but come after the barrier will now go in
8051 the next mini-pool. */
8052 if (last_barrier != NULL)
8054 /* Reduce the refcount for those fixes that won't go into this
8056 for (fdel = last_barrier->next;
8057 fdel && fdel != ftmp;
8060 fdel->minipool->refcount--;
8061 fdel->minipool = NULL;
8064 ftmp = last_barrier;
8068 /* ftmp is first fix that we can't fit into this pool and
8069 there no natural barriers that we could use. Insert a
8070 new barrier in the code somewhere between the previous
8071 fix and this one, and arrange to jump around it. */
8072 HOST_WIDE_INT max_address;
8074 /* The last item on the list of fixes must be a barrier, so
8075 we can never run off the end of the list of fixes without
8076 last_barrier being set. */
8080 max_address = minipool_vector_head->max_address;
8081 /* Check that there isn't another fix that is in range that
8082 we couldn't fit into this pool because the pool was
8083 already too large: we need to put the pool before such an
8085 if (ftmp->address < max_address)
8086 max_address = ftmp->address;
8088 last_barrier = create_fix_barrier (last_added_fix, max_address);
8091 assign_minipool_offsets (last_barrier);
8095 if (GET_CODE (ftmp->insn) != BARRIER
8096 && ((ftmp->minipool = add_minipool_backward_ref (ftmp))
8103 /* Scan over the fixes we have identified for this pool, fixing them
8104 up and adding the constants to the pool itself. */
8105 for (this_fix = fix; this_fix && ftmp != this_fix;
8106 this_fix = this_fix->next)
8107 if (GET_CODE (this_fix->insn) != BARRIER)
8110 = plus_constant (gen_rtx_LABEL_REF (VOIDmode,
8111 minipool_vector_label),
8112 this_fix->minipool->offset);
8113 *this_fix->loc = gen_rtx_MEM (this_fix->mode, addr);
8116 dump_minipool (last_barrier->insn);
8120 /* From now on we must synthesize any constants that we can't handle
8121 directly. This can happen if the RTL gets split during final
8122 instruction generation. */
8123 after_arm_reorg = 1;
8125 /* Free the minipool memory. */
8126 obstack_free (&minipool_obstack, minipool_startobj);
8129 /* Routines to output assembly language. */
8131 /* If the rtx is the correct value then return the string of the number.
8132 In this way we can ensure that valid double constants are generated even
8133 when cross compiling. */
8135 fp_immediate_constant (rtx x)
8140 if (!fp_consts_inited)
8143 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
8144 for (i = 0; i < 8; i++)
8145 if (REAL_VALUES_EQUAL (r, values_fp[i]))
8146 return strings_fp[i];
8151 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
8153 fp_const_from_val (REAL_VALUE_TYPE *r)
8157 if (!fp_consts_inited)
8160 for (i = 0; i < 8; i++)
8161 if (REAL_VALUES_EQUAL (*r, values_fp[i]))
8162 return strings_fp[i];
8167 /* Output the operands of a LDM/STM instruction to STREAM.
8168 MASK is the ARM register set mask of which only bits 0-15 are important.
8169 REG is the base register, either the frame pointer or the stack pointer,
8170 INSTR is the possibly suffixed load or store instruction. */
8172 print_multi_reg (FILE *stream, const char *instr, int reg, int mask)
8175 int not_first = FALSE;
8177 fputc ('\t', stream);
8178 asm_fprintf (stream, instr, reg);
8179 fputs (", {", stream);
8181 for (i = 0; i <= LAST_ARM_REGNUM; i++)
8182 if (mask & (1 << i))
8185 fprintf (stream, ", ");
8187 asm_fprintf (stream, "%r", i);
8191 fprintf (stream, "}\n");
8195 /* Output a FLDMX instruction to STREAM.
8196 BASE if the register containing the address.
8197 REG and COUNT specify the register range.
8198 Extra registers may be added to avoid hardware bugs. */
8201 arm_output_fldmx (FILE * stream, unsigned int base, int reg, int count)
8205 /* Workaround ARM10 VFPr1 bug. */
8206 if (count == 2 && !arm_arch6)
8213 fputc ('\t', stream);
8214 asm_fprintf (stream, "fldmfdx\t%r!, {", base);
8216 for (i = reg; i < reg + count; i++)
8219 fputs (", ", stream);
8220 asm_fprintf (stream, "d%d", i);
8222 fputs ("}\n", stream);
8227 /* Output the assembly for a store multiple. */
8230 vfp_output_fstmx (rtx * operands)
8237 strcpy (pattern, "fstmfdx\t%m0!, {%P1");
8238 p = strlen (pattern);
8240 if (GET_CODE (operands[1]) != REG)
8243 base = (REGNO (operands[1]) - FIRST_VFP_REGNUM) / 2;
8244 for (i = 1; i < XVECLEN (operands[2], 0); i++)
8246 p += sprintf (&pattern[p], ", d%d", base + i);
8248 strcpy (&pattern[p], "}");
8250 output_asm_insn (pattern, operands);
8255 /* Emit RTL to save block of VFP register pairs to the stack. Returns the
8256 number of bytes pushed. */
8259 vfp_emit_fstmx (int base_reg, int count)
8266 /* Workaround ARM10 VFPr1 bug. Data corruption can occur when exactly two
8267 register pairs are stored by a store multiple insn. We avoid this
8268 by pushing an extra pair. */
8269 if (count == 2 && !arm_arch6)
8271 if (base_reg == LAST_VFP_REGNUM - 3)
8276 /* ??? The frame layout is implementation defined. We describe
8277 standard format 1 (equivalent to a FSTMD insn and unused pad word).
8278 We really need some way of representing the whole block so that the
8279 unwinder can figure it out at runtime. */
8280 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
8281 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (count + 1));
8283 reg = gen_rtx_REG (DFmode, base_reg);
8287 = gen_rtx_SET (VOIDmode,
8288 gen_rtx_MEM (BLKmode,
8289 gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
8290 gen_rtx_UNSPEC (BLKmode,
8294 tmp = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8295 gen_rtx_PLUS (SImode, stack_pointer_rtx,
8296 GEN_INT (-(count * 8 + 4))));
8297 RTX_FRAME_RELATED_P (tmp) = 1;
8298 XVECEXP (dwarf, 0, 0) = tmp;
8300 tmp = gen_rtx_SET (VOIDmode,
8301 gen_rtx_MEM (DFmode, stack_pointer_rtx),
8303 RTX_FRAME_RELATED_P (tmp) = 1;
8304 XVECEXP (dwarf, 0, 1) = tmp;
8306 for (i = 1; i < count; i++)
8308 reg = gen_rtx_REG (DFmode, base_reg);
8310 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
8312 tmp = gen_rtx_SET (VOIDmode,
8313 gen_rtx_MEM (DFmode,
8314 gen_rtx_PLUS (SImode,
8318 RTX_FRAME_RELATED_P (tmp) = 1;
8319 XVECEXP (dwarf, 0, i + 1) = tmp;
8322 par = emit_insn (par);
8323 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
8325 RTX_FRAME_RELATED_P (par) = 1;
8327 return count * 8 + 4;
8331 /* Output a 'call' insn. */
8333 output_call (rtx *operands)
8336 abort (); /* Patterns should call blx <reg> directly. */
8338 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
8339 if (REGNO (operands[0]) == LR_REGNUM)
8341 operands[0] = gen_rtx_REG (SImode, IP_REGNUM);
8342 output_asm_insn ("mov%?\t%0, %|lr", operands);
8345 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
8347 if (TARGET_INTERWORK || arm_arch4t)
8348 output_asm_insn ("bx%?\t%0", operands);
8350 output_asm_insn ("mov%?\t%|pc, %0", operands);
8355 /* Output a 'call' insn that is a reference in memory. */
8357 output_call_mem (rtx *operands)
8359 if (TARGET_INTERWORK && !arm_arch5)
8361 output_asm_insn ("ldr%?\t%|ip, %0", operands);
8362 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
8363 output_asm_insn ("bx%?\t%|ip", operands);
8365 else if (regno_use_in (LR_REGNUM, operands[0]))
8367 /* LR is used in the memory address. We load the address in the
8368 first instruction. It's safe to use IP as the target of the
8369 load since the call will kill it anyway. */
8370 output_asm_insn ("ldr%?\t%|ip, %0", operands);
8372 output_asm_insn ("blx%?%|ip", operands);
8375 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
8377 output_asm_insn ("bx%?\t%|ip", operands);
8379 output_asm_insn ("mov%?\t%|pc, %|ip", operands);
8384 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
8385 output_asm_insn ("ldr%?\t%|pc, %0", operands);
8392 /* Output a move from arm registers to an fpa registers.
8393 OPERANDS[0] is an fpa register.
8394 OPERANDS[1] is the first registers of an arm register pair. */
8396 output_mov_long_double_fpa_from_arm (rtx *operands)
8398 int arm_reg0 = REGNO (operands[1]);
8401 if (arm_reg0 == IP_REGNUM)
8404 ops[0] = gen_rtx_REG (SImode, arm_reg0);
8405 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
8406 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
8408 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops);
8409 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands);
8414 /* Output a move from an fpa register to arm registers.
8415 OPERANDS[0] is the first registers of an arm register pair.
8416 OPERANDS[1] is an fpa register. */
8418 output_mov_long_double_arm_from_fpa (rtx *operands)
8420 int arm_reg0 = REGNO (operands[0]);
8423 if (arm_reg0 == IP_REGNUM)
8426 ops[0] = gen_rtx_REG (SImode, arm_reg0);
8427 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
8428 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
8430 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands);
8431 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops);
8435 /* Output a move from arm registers to arm registers of a long double
8436 OPERANDS[0] is the destination.
8437 OPERANDS[1] is the source. */
8439 output_mov_long_double_arm_from_arm (rtx *operands)
8441 /* We have to be careful here because the two might overlap. */
8442 int dest_start = REGNO (operands[0]);
8443 int src_start = REGNO (operands[1]);
8447 if (dest_start < src_start)
8449 for (i = 0; i < 3; i++)
8451 ops[0] = gen_rtx_REG (SImode, dest_start + i);
8452 ops[1] = gen_rtx_REG (SImode, src_start + i);
8453 output_asm_insn ("mov%?\t%0, %1", ops);
8458 for (i = 2; i >= 0; i--)
8460 ops[0] = gen_rtx_REG (SImode, dest_start + i);
8461 ops[1] = gen_rtx_REG (SImode, src_start + i);
8462 output_asm_insn ("mov%?\t%0, %1", ops);
8470 /* Output a move from arm registers to an fpa registers.
8471 OPERANDS[0] is an fpa register.
8472 OPERANDS[1] is the first registers of an arm register pair. */
8474 output_mov_double_fpa_from_arm (rtx *operands)
8476 int arm_reg0 = REGNO (operands[1]);
8479 if (arm_reg0 == IP_REGNUM)
8482 ops[0] = gen_rtx_REG (SImode, arm_reg0);
8483 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
8484 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops);
8485 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands);
8489 /* Output a move from an fpa register to arm registers.
8490 OPERANDS[0] is the first registers of an arm register pair.
8491 OPERANDS[1] is an fpa register. */
8493 output_mov_double_arm_from_fpa (rtx *operands)
8495 int arm_reg0 = REGNO (operands[0]);
8498 if (arm_reg0 == IP_REGNUM)
8501 ops[0] = gen_rtx_REG (SImode, arm_reg0);
8502 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
8503 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands);
8504 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops);
8508 /* Output a move between double words.
8509 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
8510 or MEM<-REG and all MEMs must be offsettable addresses. */
8512 output_move_double (rtx *operands)
8514 enum rtx_code code0 = GET_CODE (operands[0]);
8515 enum rtx_code code1 = GET_CODE (operands[1]);
8520 int reg0 = REGNO (operands[0]);
8522 otherops[0] = gen_rtx_REG (SImode, 1 + reg0);
8526 int reg1 = REGNO (operands[1]);
8527 if (reg1 == IP_REGNUM)
8530 /* Ensure the second source is not overwritten. */
8531 if (reg1 == reg0 + (WORDS_BIG_ENDIAN ? -1 : 1))
8532 output_asm_insn ("mov%?\t%Q0, %Q1\n\tmov%?\t%R0, %R1", operands);
8534 output_asm_insn ("mov%?\t%R0, %R1\n\tmov%?\t%Q0, %Q1", operands);
8536 else if (code1 == CONST_VECTOR)
8538 HOST_WIDE_INT hint = 0;
8540 switch (GET_MODE (operands[1]))
8543 otherops[1] = GEN_INT (INTVAL (CONST_VECTOR_ELT (operands[1], 1)));
8544 operands[1] = GEN_INT (INTVAL (CONST_VECTOR_ELT (operands[1], 0)));
8548 if (BYTES_BIG_ENDIAN)
8550 hint = INTVAL (CONST_VECTOR_ELT (operands[1], 2));
8552 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 3));
8556 hint = INTVAL (CONST_VECTOR_ELT (operands[1], 3));
8558 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 2));
8561 otherops[1] = GEN_INT (hint);
8564 if (BYTES_BIG_ENDIAN)
8566 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0));
8568 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1));
8572 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1));
8574 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0));
8577 operands[1] = GEN_INT (hint);
8581 if (BYTES_BIG_ENDIAN)
8583 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 4));
8585 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 5));
8587 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 6));
8589 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 7));
8593 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 7));
8595 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 6));
8597 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 5));
8599 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 4));
8602 otherops[1] = GEN_INT (hint);
8605 if (BYTES_BIG_ENDIAN)
8607 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0));
8609 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1));
8611 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 2));
8613 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 3));
8617 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 3));
8619 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 2));
8621 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1));
8623 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0));
8626 operands[1] = GEN_INT (hint);
8632 output_mov_immediate (operands);
8633 output_mov_immediate (otherops);
8635 else if (code1 == CONST_DOUBLE)
8637 if (GET_MODE (operands[1]) == DFmode)
8642 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
8643 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
8644 otherops[1] = GEN_INT (l[1]);
8645 operands[1] = GEN_INT (l[0]);
8647 else if (GET_MODE (operands[1]) != VOIDmode)
8649 else if (WORDS_BIG_ENDIAN)
8651 otherops[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
8652 operands[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
8656 otherops[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
8657 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
8660 output_mov_immediate (operands);
8661 output_mov_immediate (otherops);
8663 else if (code1 == CONST_INT)
8665 #if HOST_BITS_PER_WIDE_INT > 32
8666 /* If HOST_WIDE_INT is more than 32 bits, the intval tells us
8667 what the upper word is. */
8668 if (WORDS_BIG_ENDIAN)
8670 otherops[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1])));
8671 operands[1] = GEN_INT (INTVAL (operands[1]) >> 32);
8675 otherops[1] = GEN_INT (INTVAL (operands[1]) >> 32);
8676 operands[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1])));
8679 /* Sign extend the intval into the high-order word. */
8680 if (WORDS_BIG_ENDIAN)
8682 otherops[1] = operands[1];
8683 operands[1] = (INTVAL (operands[1]) < 0
8684 ? constm1_rtx : const0_rtx);
8687 otherops[1] = INTVAL (operands[1]) < 0 ? constm1_rtx : const0_rtx;
8689 output_mov_immediate (otherops);
8690 output_mov_immediate (operands);
8692 else if (code1 == MEM)
8694 switch (GET_CODE (XEXP (operands[1], 0)))
8697 output_asm_insn ("ldm%?ia\t%m1, %M0", operands);
8702 abort (); /* Should never happen now. */
8703 output_asm_insn ("ldr%?d\t%0, [%m1, #8]!", operands);
8707 output_asm_insn ("ldm%?db\t%m1!, %M0", operands);
8711 output_asm_insn ("ldm%?ia\t%m1!, %M0", operands);
8716 abort (); /* Should never happen now. */
8717 output_asm_insn ("ldr%?d\t%0, [%m1], #-8", operands);
8722 otherops[0] = operands[0];
8723 otherops[1] = XEXP (XEXP (XEXP (operands[1], 0), 1), 0);
8724 otherops[2] = XEXP (XEXP (XEXP (operands[1], 0), 1), 1);
8726 if (GET_CODE (XEXP (operands[1], 0)) == PRE_MODIFY)
8728 if (reg_overlap_mentioned_p (otherops[0], otherops[2]))
8730 /* Registers overlap so split out the increment. */
8731 output_asm_insn ("add%?\t%1, %1, %2", otherops);
8732 output_asm_insn ("ldr%?d\t%0, [%1] @split", otherops);
8735 output_asm_insn ("ldr%?d\t%0, [%1, %2]!", otherops);
8739 /* We only allow constant increments, so this is safe. */
8740 output_asm_insn ("ldr%?d\t%0, [%1], %2", otherops);
8746 output_asm_insn ("adr%?\t%0, %1", operands);
8747 output_asm_insn ("ldm%?ia\t%0, %M0", operands);
8751 if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1),
8752 GET_MODE (XEXP (XEXP (operands[1], 0), 1))))
8754 otherops[0] = operands[0];
8755 otherops[1] = XEXP (XEXP (operands[1], 0), 0);
8756 otherops[2] = XEXP (XEXP (operands[1], 0), 1);
8758 if (GET_CODE (XEXP (operands[1], 0)) == PLUS)
8760 if (GET_CODE (otherops[2]) == CONST_INT)
8762 switch ((int) INTVAL (otherops[2]))
8765 output_asm_insn ("ldm%?db\t%1, %M0", otherops);
8768 output_asm_insn ("ldm%?da\t%1, %M0", otherops);
8771 output_asm_insn ("ldm%?ib\t%1, %M0", otherops);
8776 && (GET_CODE (otherops[2]) == REG
8777 || (GET_CODE (otherops[2]) == CONST_INT
8778 && INTVAL (otherops[2]) > -256
8779 && INTVAL (otherops[2]) < 256)))
8781 if (reg_overlap_mentioned_p (otherops[0],
8784 /* Swap base and index registers over to
8785 avoid a conflict. */
8786 otherops[1] = XEXP (XEXP (operands[1], 0), 1);
8787 otherops[2] = XEXP (XEXP (operands[1], 0), 0);
8790 /* If both registers conflict, it will usually
8791 have been fixed by a splitter. */
8792 if (reg_overlap_mentioned_p (otherops[0],
8795 output_asm_insn ("add%?\t%1, %1, %2", otherops);
8796 output_asm_insn ("ldr%?d\t%0, [%1]",
8802 output_asm_insn ("ldr%?d\t%0, [%1, %2]",
8807 if (GET_CODE (otherops[2]) == CONST_INT)
8809 if (!(const_ok_for_arm (INTVAL (otherops[2]))))
8810 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops);
8812 output_asm_insn ("add%?\t%0, %1, %2", otherops);
8815 output_asm_insn ("add%?\t%0, %1, %2", otherops);
8818 output_asm_insn ("sub%?\t%0, %1, %2", otherops);
8820 return "ldm%?ia\t%0, %M0";
8824 otherops[1] = adjust_address (operands[1], SImode, 4);
8825 /* Take care of overlapping base/data reg. */
8826 if (reg_mentioned_p (operands[0], operands[1]))
8828 output_asm_insn ("ldr%?\t%0, %1", otherops);
8829 output_asm_insn ("ldr%?\t%0, %1", operands);
8833 output_asm_insn ("ldr%?\t%0, %1", operands);
8834 output_asm_insn ("ldr%?\t%0, %1", otherops);
8840 abort (); /* Constraints should prevent this. */
8842 else if (code0 == MEM && code1 == REG)
8844 if (REGNO (operands[1]) == IP_REGNUM)
8847 switch (GET_CODE (XEXP (operands[0], 0)))
8850 output_asm_insn ("stm%?ia\t%m0, %M1", operands);
8855 abort (); /* Should never happen now. */
8856 output_asm_insn ("str%?d\t%1, [%m0, #8]!", operands);
8860 output_asm_insn ("stm%?db\t%m0!, %M1", operands);
8864 output_asm_insn ("stm%?ia\t%m0!, %M1", operands);
8869 abort (); /* Should never happen now. */
8870 output_asm_insn ("str%?d\t%1, [%m0], #-8", operands);
8875 otherops[0] = operands[1];
8876 otherops[1] = XEXP (XEXP (XEXP (operands[0], 0), 1), 0);
8877 otherops[2] = XEXP (XEXP (XEXP (operands[0], 0), 1), 1);
8879 if (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY)
8880 output_asm_insn ("str%?d\t%0, [%1, %2]!", otherops);
8882 output_asm_insn ("str%?d\t%0, [%1], %2", otherops);
8886 otherops[2] = XEXP (XEXP (operands[0], 0), 1);
8887 if (GET_CODE (otherops[2]) == CONST_INT)
8889 switch ((int) INTVAL (XEXP (XEXP (operands[0], 0), 1)))
8892 output_asm_insn ("stm%?db\t%m0, %M1", operands);
8896 output_asm_insn ("stm%?da\t%m0, %M1", operands);
8900 output_asm_insn ("stm%?ib\t%m0, %M1", operands);
8905 && (GET_CODE (otherops[2]) == REG
8906 || (GET_CODE (otherops[2]) == CONST_INT
8907 && INTVAL (otherops[2]) > -256
8908 && INTVAL (otherops[2]) < 256)))
8910 otherops[0] = operands[1];
8911 otherops[1] = XEXP (XEXP (operands[0], 0), 0);
8912 output_asm_insn ("str%?d\t%0, [%1, %2]", otherops);
8918 otherops[0] = adjust_address (operands[0], SImode, 4);
8919 otherops[1] = gen_rtx_REG (SImode, 1 + REGNO (operands[1]));
8920 output_asm_insn ("str%?\t%1, %0", operands);
8921 output_asm_insn ("str%?\t%1, %0", otherops);
8925 /* Constraints should prevent this. */
8932 /* Output an arbitrary MOV reg, #n.
8933 OPERANDS[0] is a register. OPERANDS[1] is a const_int. */
8935 output_mov_immediate (rtx *operands)
8937 HOST_WIDE_INT n = INTVAL (operands[1]);
8939 /* Try to use one MOV. */
8940 if (const_ok_for_arm (n))
8941 output_asm_insn ("mov%?\t%0, %1", operands);
8943 /* Try to use one MVN. */
8944 else if (const_ok_for_arm (~n))
8946 operands[1] = GEN_INT (~n);
8947 output_asm_insn ("mvn%?\t%0, %1", operands);
8954 /* If all else fails, make it out of ORRs or BICs as appropriate. */
8955 for (i = 0; i < 32; i++)
8959 if (n_ones > 16) /* Shorter to use MVN with BIC in this case. */
8960 output_multi_immediate (operands, "mvn%?\t%0, %1", "bic%?\t%0, %0, %1", 1, ~ n);
8962 output_multi_immediate (operands, "mov%?\t%0, %1", "orr%?\t%0, %0, %1", 1, n);
8968 /* Output an ADD r, s, #n where n may be too big for one instruction.
8969 If adding zero to one register, output nothing. */
8971 output_add_immediate (rtx *operands)
8973 HOST_WIDE_INT n = INTVAL (operands[2]);
8975 if (n != 0 || REGNO (operands[0]) != REGNO (operands[1]))
8978 output_multi_immediate (operands,
8979 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
8982 output_multi_immediate (operands,
8983 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
8990 /* Output a multiple immediate operation.
8991 OPERANDS is the vector of operands referred to in the output patterns.
8992 INSTR1 is the output pattern to use for the first constant.
8993 INSTR2 is the output pattern to use for subsequent constants.
8994 IMMED_OP is the index of the constant slot in OPERANDS.
8995 N is the constant value. */
8997 output_multi_immediate (rtx *operands, const char *instr1, const char *instr2,
8998 int immed_op, HOST_WIDE_INT n)
9000 #if HOST_BITS_PER_WIDE_INT > 32
9006 /* Quick and easy output. */
9007 operands[immed_op] = const0_rtx;
9008 output_asm_insn (instr1, operands);
9013 const char * instr = instr1;
9015 /* Note that n is never zero here (which would give no output). */
9016 for (i = 0; i < 32; i += 2)
9020 operands[immed_op] = GEN_INT (n & (255 << i));
9021 output_asm_insn (instr, operands);
9031 /* Return the appropriate ARM instruction for the operation code.
9032 The returned result should not be overwritten. OP is the rtx of the
9033 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
9036 arithmetic_instr (rtx op, int shift_first_arg)
9038 switch (GET_CODE (op))
9044 return shift_first_arg ? "rsb" : "sub";
9060 /* Ensure valid constant shifts and return the appropriate shift mnemonic
9061 for the operation code. The returned result should not be overwritten.
9062 OP is the rtx code of the shift.
9063 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
9066 shift_op (rtx op, HOST_WIDE_INT *amountp)
9069 enum rtx_code code = GET_CODE (op);
9071 if (GET_CODE (XEXP (op, 1)) == REG || GET_CODE (XEXP (op, 1)) == SUBREG)
9073 else if (GET_CODE (XEXP (op, 1)) == CONST_INT)
9074 *amountp = INTVAL (XEXP (op, 1));
9097 /* We never have to worry about the amount being other than a
9098 power of 2, since this case can never be reloaded from a reg. */
9100 *amountp = int_log2 (*amountp);
9111 /* This is not 100% correct, but follows from the desire to merge
9112 multiplication by a power of 2 with the recognizer for a
9113 shift. >=32 is not a valid shift for "asl", so we must try and
9114 output a shift that produces the correct arithmetical result.
9115 Using lsr #32 is identical except for the fact that the carry bit
9116 is not set correctly if we set the flags; but we never use the
9117 carry bit from such an operation, so we can ignore that. */
9118 if (code == ROTATERT)
9119 /* Rotate is just modulo 32. */
9121 else if (*amountp != (*amountp & 31))
9128 /* Shifts of 0 are no-ops. */
9136 /* Obtain the shift from the POWER of two. */
9138 static HOST_WIDE_INT
9139 int_log2 (HOST_WIDE_INT power)
9141 HOST_WIDE_INT shift = 0;
9143 while ((((HOST_WIDE_INT) 1 << shift) & power) == 0)
9153 /* Output a .ascii pseudo-op, keeping track of lengths. This is because
9154 /bin/as is horribly restrictive. */
9155 #define MAX_ASCII_LEN 51
9158 output_ascii_pseudo_op (FILE *stream, const unsigned char *p, int len)
9163 fputs ("\t.ascii\t\"", stream);
9165 for (i = 0; i < len; i++)
9169 if (len_so_far >= MAX_ASCII_LEN)
9171 fputs ("\"\n\t.ascii\t\"", stream);
9178 fputs ("\\t", stream);
9183 fputs ("\\f", stream);
9188 fputs ("\\b", stream);
9193 fputs ("\\r", stream);
9197 case TARGET_NEWLINE:
9198 fputs ("\\n", stream);
9200 if ((c >= ' ' && c <= '~')
9202 /* This is a good place for a line break. */
9203 len_so_far = MAX_ASCII_LEN;
9210 putc ('\\', stream);
9215 if (c >= ' ' && c <= '~')
9222 fprintf (stream, "\\%03o", c);
9229 fputs ("\"\n", stream);
9232 /* Compute the register save mask for registers 0 through 12
9233 inclusive. This code is used by arm_compute_save_reg_mask. */
9234 static unsigned long
9235 arm_compute_save_reg0_reg12_mask (void)
9237 unsigned long func_type = arm_current_func_type ();
9238 unsigned int save_reg_mask = 0;
9241 if (IS_INTERRUPT (func_type))
9243 unsigned int max_reg;
9244 /* Interrupt functions must not corrupt any registers,
9245 even call clobbered ones. If this is a leaf function
9246 we can just examine the registers used by the RTL, but
9247 otherwise we have to assume that whatever function is
9248 called might clobber anything, and so we have to save
9249 all the call-clobbered registers as well. */
9250 if (ARM_FUNC_TYPE (func_type) == ARM_FT_FIQ)
9251 /* FIQ handlers have registers r8 - r12 banked, so
9252 we only need to check r0 - r7, Normal ISRs only
9253 bank r14 and r15, so we must check up to r12.
9254 r13 is the stack pointer which is always preserved,
9255 so we do not need to consider it here. */
9260 for (reg = 0; reg <= max_reg; reg++)
9261 if (regs_ever_live[reg]
9262 || (! current_function_is_leaf && call_used_regs [reg]))
9263 save_reg_mask |= (1 << reg);
9267 /* In the normal case we only need to save those registers
9268 which are call saved and which are used by this function. */
9269 for (reg = 0; reg <= 10; reg++)
9270 if (regs_ever_live[reg] && ! call_used_regs [reg])
9271 save_reg_mask |= (1 << reg);
9273 /* Handle the frame pointer as a special case. */
9274 if (! TARGET_APCS_FRAME
9275 && ! frame_pointer_needed
9276 && regs_ever_live[HARD_FRAME_POINTER_REGNUM]
9277 && ! call_used_regs[HARD_FRAME_POINTER_REGNUM])
9278 save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM;
9280 /* If we aren't loading the PIC register,
9281 don't stack it even though it may be live. */
9283 && ! TARGET_SINGLE_PIC_BASE
9284 && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
9285 save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
9288 /* Save registers so the exception handler can modify them. */
9289 if (current_function_calls_eh_return)
9295 reg = EH_RETURN_DATA_REGNO (i);
9296 if (reg == INVALID_REGNUM)
9298 save_reg_mask |= 1 << reg;
9302 return save_reg_mask;
9305 /* Compute a bit mask of which registers need to be
9306 saved on the stack for the current function. */
9308 static unsigned long
9309 arm_compute_save_reg_mask (void)
9311 unsigned int save_reg_mask = 0;
9312 unsigned long func_type = arm_current_func_type ();
9314 if (IS_NAKED (func_type))
9315 /* This should never really happen. */
9318 /* If we are creating a stack frame, then we must save the frame pointer,
9319 IP (which will hold the old stack pointer), LR and the PC. */
9320 if (frame_pointer_needed)
9322 (1 << ARM_HARD_FRAME_POINTER_REGNUM)
9327 /* Volatile functions do not return, so there
9328 is no need to save any other registers. */
9329 if (IS_VOLATILE (func_type))
9330 return save_reg_mask;
9332 save_reg_mask |= arm_compute_save_reg0_reg12_mask ();
9334 /* Decide if we need to save the link register.
9335 Interrupt routines have their own banked link register,
9336 so they never need to save it.
9337 Otherwise if we do not use the link register we do not need to save
9338 it. If we are pushing other registers onto the stack however, we
9339 can save an instruction in the epilogue by pushing the link register
9340 now and then popping it back into the PC. This incurs extra memory
9341 accesses though, so we only do it when optimizing for size, and only
9342 if we know that we will not need a fancy return sequence. */
9343 if (regs_ever_live [LR_REGNUM]
9346 && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
9347 && !current_function_calls_eh_return))
9348 save_reg_mask |= 1 << LR_REGNUM;
9350 if (cfun->machine->lr_save_eliminated)
9351 save_reg_mask &= ~ (1 << LR_REGNUM);
9353 if (TARGET_REALLY_IWMMXT
9354 && ((bit_count (save_reg_mask)
9355 + ARM_NUM_INTS (current_function_pretend_args_size)) % 2) != 0)
9359 /* The total number of registers that are going to be pushed
9360 onto the stack is odd. We need to ensure that the stack
9361 is 64-bit aligned before we start to save iWMMXt registers,
9362 and also before we start to create locals. (A local variable
9363 might be a double or long long which we will load/store using
9364 an iWMMXt instruction). Therefore we need to push another
9365 ARM register, so that the stack will be 64-bit aligned. We
9366 try to avoid using the arg registers (r0 -r3) as they might be
9367 used to pass values in a tail call. */
9368 for (reg = 4; reg <= 12; reg++)
9369 if ((save_reg_mask & (1 << reg)) == 0)
9373 save_reg_mask |= (1 << reg);
9376 cfun->machine->sibcall_blocked = 1;
9377 save_reg_mask |= (1 << 3);
9381 return save_reg_mask;
9385 /* Compute a bit mask of which registers need to be
9386 saved on the stack for the current function. */
9387 static unsigned long
9388 thumb_compute_save_reg_mask (void)
9394 for (reg = 0; reg < 12; reg ++)
9396 if (regs_ever_live[reg] && !call_used_regs[reg])
9400 if (flag_pic && !TARGET_SINGLE_PIC_BASE)
9401 mask |= PIC_OFFSET_TABLE_REGNUM;
9402 if (TARGET_SINGLE_PIC_BASE)
9403 mask &= ~(1 << arm_pic_register);
9405 /* lr will also be pushed if any lo regs are pushed. */
9406 if (mask & 0xff || thumb_force_lr_save ())
9407 mask |= (1 << LR_REGNUM);
9409 /* Make sure we have a low work register if we need one. */
9410 if (((mask & 0xff) == 0 && regs_ever_live[LAST_ARG_REGNUM])
9411 && ((mask & 0x0f00) || TARGET_BACKTRACE))
9412 mask |= 1 << LAST_LO_REGNUM;
9418 /* Return the number of bytes required to save VFP registers. */
9420 arm_get_vfp_saved_size (void)
9427 /* Space for saved VFP registers. */
9428 if (TARGET_HARD_FLOAT && TARGET_VFP)
9431 for (regno = FIRST_VFP_REGNUM;
9432 regno < LAST_VFP_REGNUM;
9435 if ((!regs_ever_live[regno] || call_used_regs[regno])
9436 && (!regs_ever_live[regno + 1] || call_used_regs[regno + 1]))
9440 /* Workaround ARM10 VFPr1 bug. */
9441 if (count == 2 && !arm_arch6)
9443 saved += count * 8 + 4;
9452 if (count == 2 && !arm_arch6)
9454 saved += count * 8 + 4;
9461 /* Generate a function exit sequence. If REALLY_RETURN is false, then do
9462 everything bar the final return instruction. */
9464 output_return_instruction (rtx operand, int really_return, int reverse)
9466 char conditional[10];
9469 unsigned long live_regs_mask;
9470 unsigned long func_type;
9471 arm_stack_offsets *offsets;
9473 func_type = arm_current_func_type ();
9475 if (IS_NAKED (func_type))
9478 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
9480 /* If this function was declared non-returning, and we have
9481 found a tail call, then we have to trust that the called
9482 function won't return. */
9487 /* Otherwise, trap an attempted return by aborting. */
9489 ops[1] = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)"
9491 assemble_external_libcall (ops[1]);
9492 output_asm_insn (reverse ? "bl%D0\t%a1" : "bl%d0\t%a1", ops);
9498 if (current_function_calls_alloca && !really_return)
9501 sprintf (conditional, "%%?%%%c0", reverse ? 'D' : 'd');
9503 return_used_this_function = 1;
9505 live_regs_mask = arm_compute_save_reg_mask ();
9509 const char * return_reg;
9511 /* If we do not have any special requirements for function exit
9512 (eg interworking, or ISR) then we can load the return address
9513 directly into the PC. Otherwise we must load it into LR. */
9515 && ! TARGET_INTERWORK)
9516 return_reg = reg_names[PC_REGNUM];
9518 return_reg = reg_names[LR_REGNUM];
9520 if ((live_regs_mask & (1 << IP_REGNUM)) == (1 << IP_REGNUM))
9522 /* There are three possible reasons for the IP register
9523 being saved. 1) a stack frame was created, in which case
9524 IP contains the old stack pointer, or 2) an ISR routine
9525 corrupted it, or 3) it was saved to align the stack on
9526 iWMMXt. In case 1, restore IP into SP, otherwise just
9528 if (frame_pointer_needed)
9530 live_regs_mask &= ~ (1 << IP_REGNUM);
9531 live_regs_mask |= (1 << SP_REGNUM);
9535 if (! IS_INTERRUPT (func_type)
9536 && ! TARGET_REALLY_IWMMXT)
9541 /* On some ARM architectures it is faster to use LDR rather than
9542 LDM to load a single register. On other architectures, the
9543 cost is the same. In 26 bit mode, or for exception handlers,
9544 we have to use LDM to load the PC so that the CPSR is also
9546 for (reg = 0; reg <= LAST_ARM_REGNUM; reg++)
9548 if (live_regs_mask == (unsigned int)(1 << reg))
9551 if (reg <= LAST_ARM_REGNUM
9552 && (reg != LR_REGNUM
9554 || ! IS_INTERRUPT (func_type)))
9556 sprintf (instr, "ldr%s\t%%|%s, [%%|sp], #4", conditional,
9557 (reg == LR_REGNUM) ? return_reg : reg_names[reg]);
9564 /* Generate the load multiple instruction to restore the
9565 registers. Note we can get here, even if
9566 frame_pointer_needed is true, but only if sp already
9567 points to the base of the saved core registers. */
9568 if (live_regs_mask & (1 << SP_REGNUM))
9570 unsigned HOST_WIDE_INT stack_adjust;
9572 offsets = arm_get_frame_offsets ();
9573 stack_adjust = offsets->outgoing_args - offsets->saved_regs;
9574 if (stack_adjust != 0 && stack_adjust != 4)
9577 if (stack_adjust && arm_arch5)
9578 sprintf (instr, "ldm%sib\t%%|sp, {", conditional);
9581 /* If we can't use ldmib (SA110 bug), then try to pop r3
9584 live_regs_mask |= 1 << 3;
9585 sprintf (instr, "ldm%sfd\t%%|sp, {", conditional);
9589 sprintf (instr, "ldm%sfd\t%%|sp!, {", conditional);
9591 p = instr + strlen (instr);
9593 for (reg = 0; reg <= SP_REGNUM; reg++)
9594 if (live_regs_mask & (1 << reg))
9596 int l = strlen (reg_names[reg]);
9602 memcpy (p, ", ", 2);
9606 memcpy (p, "%|", 2);
9607 memcpy (p + 2, reg_names[reg], l);
9611 if (live_regs_mask & (1 << LR_REGNUM))
9613 sprintf (p, "%s%%|%s}", first ? "" : ", ", return_reg);
9614 /* If returning from an interrupt, restore the CPSR. */
9615 if (IS_INTERRUPT (func_type))
9622 output_asm_insn (instr, & operand);
9624 /* See if we need to generate an extra instruction to
9625 perform the actual function return. */
9627 && func_type != ARM_FT_INTERWORKED
9628 && (live_regs_mask & (1 << LR_REGNUM)) != 0)
9630 /* The return has already been handled
9631 by loading the LR into the PC. */
9638 switch ((int) ARM_FUNC_TYPE (func_type))
9642 sprintf (instr, "sub%ss\t%%|pc, %%|lr, #4", conditional);
9645 case ARM_FT_INTERWORKED:
9646 sprintf (instr, "bx%s\t%%|lr", conditional);
9649 case ARM_FT_EXCEPTION:
9650 sprintf (instr, "mov%ss\t%%|pc, %%|lr", conditional);
9654 /* Use bx if it's available. */
9655 if (arm_arch5 || arm_arch4t)
9656 sprintf (instr, "bx%s\t%%|lr", conditional);
9658 sprintf (instr, "mov%s\t%%|pc, %%|lr", conditional);
9662 output_asm_insn (instr, & operand);
9668 /* Write the function name into the code section, directly preceding
9669 the function prologue.
9671 Code will be output similar to this:
9673 .ascii "arm_poke_function_name", 0
9676 .word 0xff000000 + (t1 - t0)
9677 arm_poke_function_name
9679 stmfd sp!, {fp, ip, lr, pc}
9682 When performing a stack backtrace, code can inspect the value
9683 of 'pc' stored at 'fp' + 0. If the trace function then looks
9684 at location pc - 12 and the top 8 bits are set, then we know
9685 that there is a function name embedded immediately preceding this
9686 location and has length ((pc[-3]) & 0xff000000).
9688 We assume that pc is declared as a pointer to an unsigned long.
9690 It is of no benefit to output the function name if we are assembling
9691 a leaf function. These function types will not contain a stack
9692 backtrace structure, therefore it is not possible to determine the
9695 arm_poke_function_name (FILE *stream, const char *name)
9697 unsigned long alignlength;
9698 unsigned long length;
9701 length = strlen (name) + 1;
9702 alignlength = ROUND_UP_WORD (length);
9704 ASM_OUTPUT_ASCII (stream, name, length);
9705 ASM_OUTPUT_ALIGN (stream, 2);
9706 x = GEN_INT ((unsigned HOST_WIDE_INT) 0xff000000 + alignlength);
9707 assemble_aligned_integer (UNITS_PER_WORD, x);
9710 /* Place some comments into the assembler stream
9711 describing the current function. */
9713 arm_output_function_prologue (FILE *f, HOST_WIDE_INT frame_size)
9715 unsigned long func_type;
9719 thumb_output_function_prologue (f, frame_size);
9724 if (arm_ccfsm_state || arm_target_insn)
9727 func_type = arm_current_func_type ();
9729 switch ((int) ARM_FUNC_TYPE (func_type))
9734 case ARM_FT_INTERWORKED:
9735 asm_fprintf (f, "\t%@ Function supports interworking.\n");
9738 asm_fprintf (f, "\t%@ Interrupt Service Routine.\n");
9741 asm_fprintf (f, "\t%@ Fast Interrupt Service Routine.\n");
9743 case ARM_FT_EXCEPTION:
9744 asm_fprintf (f, "\t%@ ARM Exception Handler.\n");
9748 if (IS_NAKED (func_type))
9749 asm_fprintf (f, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n");
9751 if (IS_VOLATILE (func_type))
9752 asm_fprintf (f, "\t%@ Volatile: function does not return.\n");
9754 if (IS_NESTED (func_type))
9755 asm_fprintf (f, "\t%@ Nested: function declared inside another function.\n");
9757 asm_fprintf (f, "\t%@ args = %d, pretend = %d, frame = %wd\n",
9758 current_function_args_size,
9759 current_function_pretend_args_size, frame_size);
9761 asm_fprintf (f, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n",
9762 frame_pointer_needed,
9763 cfun->machine->uses_anonymous_args);
9765 if (cfun->machine->lr_save_eliminated)
9766 asm_fprintf (f, "\t%@ link register save eliminated.\n");
9768 if (current_function_calls_eh_return)
9769 asm_fprintf (f, "\t@ Calls __builtin_eh_return.\n");
9771 #ifdef AOF_ASSEMBLER
9773 asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, PIC_OFFSET_TABLE_REGNUM);
9776 return_used_this_function = 0;
9780 arm_output_epilogue (rtx sibling)
9783 unsigned long saved_regs_mask;
9784 unsigned long func_type;
9785 /* Floats_offset is the offset from the "virtual" frame. In an APCS
9786 frame that is $fp + 4 for a non-variadic function. */
9787 int floats_offset = 0;
9789 FILE * f = asm_out_file;
9790 unsigned int lrm_count = 0;
9791 int really_return = (sibling == NULL);
9793 arm_stack_offsets *offsets;
9795 /* If we have already generated the return instruction
9796 then it is futile to generate anything else. */
9797 if (use_return_insn (FALSE, sibling) && return_used_this_function)
9800 func_type = arm_current_func_type ();
9802 if (IS_NAKED (func_type))
9803 /* Naked functions don't have epilogues. */
9806 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
9810 /* A volatile function should never return. Call abort. */
9811 op = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" : "abort");
9812 assemble_external_libcall (op);
9813 output_asm_insn ("bl\t%a0", &op);
9818 if (current_function_calls_eh_return
9820 /* If we are throwing an exception, then we really must
9821 be doing a return, so we can't tail-call. */
9824 offsets = arm_get_frame_offsets ();
9825 saved_regs_mask = arm_compute_save_reg_mask ();
9828 lrm_count = bit_count (saved_regs_mask);
9830 floats_offset = offsets->saved_args;
9831 /* Compute how far away the floats will be. */
9832 for (reg = 0; reg <= LAST_ARM_REGNUM; reg++)
9833 if (saved_regs_mask & (1 << reg))
9836 if (frame_pointer_needed)
9838 /* This variable is for the Virtual Frame Pointer, not VFP regs. */
9839 int vfp_offset = offsets->frame;
9841 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
9843 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
9844 if (regs_ever_live[reg] && !call_used_regs[reg])
9846 floats_offset += 12;
9847 asm_fprintf (f, "\tldfe\t%r, [%r, #-%d]\n",
9848 reg, FP_REGNUM, floats_offset - vfp_offset);
9853 start_reg = LAST_FPA_REGNUM;
9855 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
9857 if (regs_ever_live[reg] && !call_used_regs[reg])
9859 floats_offset += 12;
9861 /* We can't unstack more than four registers at once. */
9862 if (start_reg - reg == 3)
9864 asm_fprintf (f, "\tlfm\t%r, 4, [%r, #-%d]\n",
9865 reg, FP_REGNUM, floats_offset - vfp_offset);
9866 start_reg = reg - 1;
9871 if (reg != start_reg)
9872 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
9873 reg + 1, start_reg - reg,
9874 FP_REGNUM, floats_offset - vfp_offset);
9875 start_reg = reg - 1;
9879 /* Just in case the last register checked also needs unstacking. */
9880 if (reg != start_reg)
9881 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
9882 reg + 1, start_reg - reg,
9883 FP_REGNUM, floats_offset - vfp_offset);
9886 if (TARGET_HARD_FLOAT && TARGET_VFP)
9890 /* The fldmx insn does not have base+offset addressing modes,
9891 so we use IP to hold the address. */
9892 saved_size = arm_get_vfp_saved_size ();
9896 floats_offset += saved_size;
9897 asm_fprintf (f, "\tsub\t%r, %r, #%d\n", IP_REGNUM,
9898 FP_REGNUM, floats_offset - vfp_offset);
9900 start_reg = FIRST_VFP_REGNUM;
9901 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
9903 if ((!regs_ever_live[reg] || call_used_regs[reg])
9904 && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1]))
9906 if (start_reg != reg)
9907 arm_output_fldmx (f, IP_REGNUM,
9908 (start_reg - FIRST_VFP_REGNUM) / 2,
9909 (reg - start_reg) / 2);
9910 start_reg = reg + 2;
9913 if (start_reg != reg)
9914 arm_output_fldmx (f, IP_REGNUM,
9915 (start_reg - FIRST_VFP_REGNUM) / 2,
9916 (reg - start_reg) / 2);
9921 /* The frame pointer is guaranteed to be non-double-word aligned.
9922 This is because it is set to (old_stack_pointer - 4) and the
9923 old_stack_pointer was double word aligned. Thus the offset to
9924 the iWMMXt registers to be loaded must also be non-double-word
9925 sized, so that the resultant address *is* double-word aligned.
9926 We can ignore floats_offset since that was already included in
9927 the live_regs_mask. */
9928 lrm_count += (lrm_count % 2 ? 2 : 1);
9930 for (reg = LAST_IWMMXT_REGNUM; reg >= FIRST_IWMMXT_REGNUM; reg--)
9931 if (regs_ever_live[reg] && !call_used_regs[reg])
9933 asm_fprintf (f, "\twldrd\t%r, [%r, #-%d]\n",
9934 reg, FP_REGNUM, lrm_count * 4);
9939 /* saved_regs_mask should contain the IP, which at the time of stack
9940 frame generation actually contains the old stack pointer. So a
9941 quick way to unwind the stack is just pop the IP register directly
9942 into the stack pointer. */
9943 if ((saved_regs_mask & (1 << IP_REGNUM)) == 0)
9945 saved_regs_mask &= ~ (1 << IP_REGNUM);
9946 saved_regs_mask |= (1 << SP_REGNUM);
9948 /* There are two registers left in saved_regs_mask - LR and PC. We
9949 only need to restore the LR register (the return address), but to
9950 save time we can load it directly into the PC, unless we need a
9951 special function exit sequence, or we are not really returning. */
9953 && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
9954 && !current_function_calls_eh_return)
9955 /* Delete the LR from the register mask, so that the LR on
9956 the stack is loaded into the PC in the register mask. */
9957 saved_regs_mask &= ~ (1 << LR_REGNUM);
9959 saved_regs_mask &= ~ (1 << PC_REGNUM);
9961 /* We must use SP as the base register, because SP is one of the
9962 registers being restored. If an interrupt or page fault
9963 happens in the ldm instruction, the SP might or might not
9964 have been restored. That would be bad, as then SP will no
9965 longer indicate the safe area of stack, and we can get stack
9966 corruption. Using SP as the base register means that it will
9967 be reset correctly to the original value, should an interrupt
9968 occur. If the stack pointer already points at the right
9969 place, then omit the subtraction. */
9970 if (offsets->outgoing_args != (1 + (int) bit_count (saved_regs_mask))
9971 || current_function_calls_alloca)
9972 asm_fprintf (f, "\tsub\t%r, %r, #%d\n", SP_REGNUM, FP_REGNUM,
9973 4 * bit_count (saved_regs_mask));
9974 print_multi_reg (f, "ldmfd\t%r", SP_REGNUM, saved_regs_mask);
9976 if (IS_INTERRUPT (func_type))
9977 /* Interrupt handlers will have pushed the
9978 IP onto the stack, so restore it now. */
9979 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, 1 << IP_REGNUM);
9983 /* Restore stack pointer if necessary. */
9984 if (offsets->outgoing_args != offsets->saved_regs)
9986 operands[0] = operands[1] = stack_pointer_rtx;
9987 operands[2] = GEN_INT (offsets->outgoing_args - offsets->saved_regs);
9988 output_add_immediate (operands);
9991 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
9993 for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++)
9994 if (regs_ever_live[reg] && !call_used_regs[reg])
9995 asm_fprintf (f, "\tldfe\t%r, [%r], #12\n",
10000 start_reg = FIRST_FPA_REGNUM;
10002 for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++)
10004 if (regs_ever_live[reg] && !call_used_regs[reg])
10006 if (reg - start_reg == 3)
10008 asm_fprintf (f, "\tlfmfd\t%r, 4, [%r]!\n",
10009 start_reg, SP_REGNUM);
10010 start_reg = reg + 1;
10015 if (reg != start_reg)
10016 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
10017 start_reg, reg - start_reg,
10020 start_reg = reg + 1;
10024 /* Just in case the last register checked also needs unstacking. */
10025 if (reg != start_reg)
10026 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
10027 start_reg, reg - start_reg, SP_REGNUM);
10030 if (TARGET_HARD_FLOAT && TARGET_VFP)
10032 start_reg = FIRST_VFP_REGNUM;
10033 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
10035 if ((!regs_ever_live[reg] || call_used_regs[reg])
10036 && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1]))
10038 if (start_reg != reg)
10039 arm_output_fldmx (f, SP_REGNUM,
10040 (start_reg - FIRST_VFP_REGNUM) / 2,
10041 (reg - start_reg) / 2);
10042 start_reg = reg + 2;
10045 if (start_reg != reg)
10046 arm_output_fldmx (f, SP_REGNUM,
10047 (start_reg - FIRST_VFP_REGNUM) / 2,
10048 (reg - start_reg) / 2);
10051 for (reg = FIRST_IWMMXT_REGNUM; reg <= LAST_IWMMXT_REGNUM; reg++)
10052 if (regs_ever_live[reg] && !call_used_regs[reg])
10053 asm_fprintf (f, "\twldrd\t%r, [%r], #8\n", reg, SP_REGNUM);
10055 /* If we can, restore the LR into the PC. */
10056 if (ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
10058 && current_function_pretend_args_size == 0
10059 && saved_regs_mask & (1 << LR_REGNUM)
10060 && !current_function_calls_eh_return)
10062 saved_regs_mask &= ~ (1 << LR_REGNUM);
10063 saved_regs_mask |= (1 << PC_REGNUM);
10066 /* Load the registers off the stack. If we only have one register
10067 to load use the LDR instruction - it is faster. */
10068 if (saved_regs_mask == (1 << LR_REGNUM))
10070 asm_fprintf (f, "\tldr\t%r, [%r], #4\n", LR_REGNUM, SP_REGNUM);
10072 else if (saved_regs_mask)
10074 if (saved_regs_mask & (1 << SP_REGNUM))
10075 /* Note - write back to the stack register is not enabled
10076 (ie "ldmfd sp!..."). We know that the stack pointer is
10077 in the list of registers and if we add writeback the
10078 instruction becomes UNPREDICTABLE. */
10079 print_multi_reg (f, "ldmfd\t%r", SP_REGNUM, saved_regs_mask);
10081 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, saved_regs_mask);
10084 if (current_function_pretend_args_size)
10086 /* Unwind the pre-pushed regs. */
10087 operands[0] = operands[1] = stack_pointer_rtx;
10088 operands[2] = GEN_INT (current_function_pretend_args_size);
10089 output_add_immediate (operands);
10093 /* We may have already restored PC directly from the stack. */
10094 if (!really_return || saved_regs_mask & (1 << PC_REGNUM))
10097 /* Stack adjustment for exception handler. */
10098 if (current_function_calls_eh_return)
10099 asm_fprintf (f, "\tadd\t%r, %r, %r\n", SP_REGNUM, SP_REGNUM,
10100 ARM_EH_STACKADJ_REGNUM);
10102 /* Generate the return instruction. */
10103 switch ((int) ARM_FUNC_TYPE (func_type))
10107 asm_fprintf (f, "\tsubs\t%r, %r, #4\n", PC_REGNUM, LR_REGNUM);
10110 case ARM_FT_EXCEPTION:
10111 asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM);
10114 case ARM_FT_INTERWORKED:
10115 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
10119 if (arm_arch5 || arm_arch4t)
10120 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
10122 asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, LR_REGNUM);
10130 arm_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
10131 HOST_WIDE_INT frame_size ATTRIBUTE_UNUSED)
10133 arm_stack_offsets *offsets;
10137 /* ??? Probably not safe to set this here, since it assumes that a
10138 function will be emitted as assembly immediately after we generate
10139 RTL for it. This does not happen for inline functions. */
10140 return_used_this_function = 0;
10144 /* We need to take into account any stack-frame rounding. */
10145 offsets = arm_get_frame_offsets ();
10147 if (use_return_insn (FALSE, NULL)
10148 && return_used_this_function
10149 && offsets->saved_regs != offsets->outgoing_args
10150 && !frame_pointer_needed)
10153 /* Reset the ARM-specific per-function variables. */
10154 after_arm_reorg = 0;
10158 /* Generate and emit an insn that we will recognize as a push_multi.
10159 Unfortunately, since this insn does not reflect very well the actual
10160 semantics of the operation, we need to annotate the insn for the benefit
10161 of DWARF2 frame unwind information. */
10163 emit_multi_reg_push (int mask)
10166 int num_dwarf_regs;
10170 int dwarf_par_index;
10173 for (i = 0; i <= LAST_ARM_REGNUM; i++)
10174 if (mask & (1 << i))
10177 if (num_regs == 0 || num_regs > 16)
10180 /* We don't record the PC in the dwarf frame information. */
10181 num_dwarf_regs = num_regs;
10182 if (mask & (1 << PC_REGNUM))
10185 /* For the body of the insn we are going to generate an UNSPEC in
10186 parallel with several USEs. This allows the insn to be recognized
10187 by the push_multi pattern in the arm.md file. The insn looks
10188 something like this:
10191 (set (mem:BLK (pre_dec:BLK (reg:SI sp)))
10192 (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT))
10193 (use (reg:SI 11 fp))
10194 (use (reg:SI 12 ip))
10195 (use (reg:SI 14 lr))
10196 (use (reg:SI 15 pc))
10199 For the frame note however, we try to be more explicit and actually
10200 show each register being stored into the stack frame, plus a (single)
10201 decrement of the stack pointer. We do it this way in order to be
10202 friendly to the stack unwinding code, which only wants to see a single
10203 stack decrement per instruction. The RTL we generate for the note looks
10204 something like this:
10207 (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20)))
10208 (set (mem:SI (reg:SI sp)) (reg:SI r4))
10209 (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp))
10210 (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip))
10211 (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr))
10214 This sequence is used both by the code to support stack unwinding for
10215 exceptions handlers and the code to generate dwarf2 frame debugging. */
10217 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_regs));
10218 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (num_dwarf_regs + 1));
10219 dwarf_par_index = 1;
10221 for (i = 0; i <= LAST_ARM_REGNUM; i++)
10223 if (mask & (1 << i))
10225 reg = gen_rtx_REG (SImode, i);
10227 XVECEXP (par, 0, 0)
10228 = gen_rtx_SET (VOIDmode,
10229 gen_rtx_MEM (BLKmode,
10230 gen_rtx_PRE_DEC (BLKmode,
10231 stack_pointer_rtx)),
10232 gen_rtx_UNSPEC (BLKmode,
10233 gen_rtvec (1, reg),
10234 UNSPEC_PUSH_MULT));
10236 if (i != PC_REGNUM)
10238 tmp = gen_rtx_SET (VOIDmode,
10239 gen_rtx_MEM (SImode, stack_pointer_rtx),
10241 RTX_FRAME_RELATED_P (tmp) = 1;
10242 XVECEXP (dwarf, 0, dwarf_par_index) = tmp;
10250 for (j = 1, i++; j < num_regs; i++)
10252 if (mask & (1 << i))
10254 reg = gen_rtx_REG (SImode, i);
10256 XVECEXP (par, 0, j) = gen_rtx_USE (VOIDmode, reg);
10258 if (i != PC_REGNUM)
10260 tmp = gen_rtx_SET (VOIDmode,
10261 gen_rtx_MEM (SImode,
10262 plus_constant (stack_pointer_rtx,
10265 RTX_FRAME_RELATED_P (tmp) = 1;
10266 XVECEXP (dwarf, 0, dwarf_par_index++) = tmp;
10273 par = emit_insn (par);
10275 tmp = gen_rtx_SET (SImode,
10277 gen_rtx_PLUS (SImode,
10279 GEN_INT (-4 * num_regs)));
10280 RTX_FRAME_RELATED_P (tmp) = 1;
10281 XVECEXP (dwarf, 0, 0) = tmp;
10283 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
10289 emit_sfm (int base_reg, int count)
10296 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
10297 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (count + 1));
10299 reg = gen_rtx_REG (XFmode, base_reg++);
10301 XVECEXP (par, 0, 0)
10302 = gen_rtx_SET (VOIDmode,
10303 gen_rtx_MEM (BLKmode,
10304 gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
10305 gen_rtx_UNSPEC (BLKmode,
10306 gen_rtvec (1, reg),
10307 UNSPEC_PUSH_MULT));
10308 tmp = gen_rtx_SET (VOIDmode,
10309 gen_rtx_MEM (XFmode, stack_pointer_rtx), reg);
10310 RTX_FRAME_RELATED_P (tmp) = 1;
10311 XVECEXP (dwarf, 0, 1) = tmp;
10313 for (i = 1; i < count; i++)
10315 reg = gen_rtx_REG (XFmode, base_reg++);
10316 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
10318 tmp = gen_rtx_SET (VOIDmode,
10319 gen_rtx_MEM (XFmode,
10320 plus_constant (stack_pointer_rtx,
10323 RTX_FRAME_RELATED_P (tmp) = 1;
10324 XVECEXP (dwarf, 0, i + 1) = tmp;
10327 tmp = gen_rtx_SET (VOIDmode,
10329 gen_rtx_PLUS (SImode,
10331 GEN_INT (-12 * count)));
10332 RTX_FRAME_RELATED_P (tmp) = 1;
10333 XVECEXP (dwarf, 0, 0) = tmp;
10335 par = emit_insn (par);
10336 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
10342 /* Return true if the current function needs to save/restore LR. */
10345 thumb_force_lr_save (void)
10347 return !cfun->machine->lr_save_eliminated
10348 && (!leaf_function_p ()
10349 || thumb_far_jump_used_p ()
10350 || regs_ever_live [LR_REGNUM]);
10354 /* Compute the distance from register FROM to register TO.
10355 These can be the arg pointer (26), the soft frame pointer (25),
10356 the stack pointer (13) or the hard frame pointer (11).
10357 In thumb mode r7 is used as the soft frame pointer, if needed.
10358 Typical stack layout looks like this:
10360 old stack pointer -> | |
10363 | | saved arguments for
10364 | | vararg functions
10367 hard FP & arg pointer -> | | \
10375 soft frame pointer -> | | /
10385 current stack pointer -> | | /
10388 For a given function some or all of these stack components
10389 may not be needed, giving rise to the possibility of
10390 eliminating some of the registers.
10392 The values returned by this function must reflect the behavior
10393 of arm_expand_prologue() and arm_compute_save_reg_mask().
10395 The sign of the number returned reflects the direction of stack
10396 growth, so the values are positive for all eliminations except
10397 from the soft frame pointer to the hard frame pointer.
10399 SFP may point just inside the local variables block to ensure correct
10403 /* Calculate stack offsets. These are used to calculate register elimination
10404 offsets and in prologue/epilogue code. */
10406 static arm_stack_offsets *
10407 arm_get_frame_offsets (void)
10409 struct arm_stack_offsets *offsets;
10410 unsigned long func_type;
10413 HOST_WIDE_INT frame_size;
10415 offsets = &cfun->machine->stack_offsets;
10417 /* We need to know if we are a leaf function. Unfortunately, it
10418 is possible to be called after start_sequence has been called,
10419 which causes get_insns to return the insns for the sequence,
10420 not the function, which will cause leaf_function_p to return
10421 the incorrect result.
10423 to know about leaf functions once reload has completed, and the
10424 frame size cannot be changed after that time, so we can safely
10425 use the cached value. */
10427 if (reload_completed)
10430 /* Initially this is the size of the local variables. It will translated
10431 into an offset once we have determined the size of preceding data. */
10432 frame_size = ROUND_UP_WORD (get_frame_size ());
10434 leaf = leaf_function_p ();
10436 /* Space for variadic functions. */
10437 offsets->saved_args = current_function_pretend_args_size;
10439 offsets->frame = offsets->saved_args + (frame_pointer_needed ? 4 : 0);
10443 unsigned int regno;
10445 saved = bit_count (arm_compute_save_reg_mask ()) * 4;
10447 /* We know that SP will be doubleword aligned on entry, and we must
10448 preserve that condition at any subroutine call. We also require the
10449 soft frame pointer to be doubleword aligned. */
10451 if (TARGET_REALLY_IWMMXT)
10453 /* Check for the call-saved iWMMXt registers. */
10454 for (regno = FIRST_IWMMXT_REGNUM;
10455 regno <= LAST_IWMMXT_REGNUM;
10457 if (regs_ever_live [regno] && ! call_used_regs [regno])
10461 func_type = arm_current_func_type ();
10462 if (! IS_VOLATILE (func_type))
10464 /* Space for saved FPA registers. */
10465 for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++)
10466 if (regs_ever_live[regno] && ! call_used_regs[regno])
10469 /* Space for saved VFP registers. */
10470 if (TARGET_HARD_FLOAT && TARGET_VFP)
10471 saved += arm_get_vfp_saved_size ();
10474 else /* TARGET_THUMB */
10476 saved = bit_count (thumb_compute_save_reg_mask ()) * 4;
10477 if (TARGET_BACKTRACE)
10481 /* Saved registers include the stack frame. */
10482 offsets->saved_regs = offsets->saved_args + saved;
10483 offsets->soft_frame = offsets->saved_regs;
10484 /* A leaf function does not need any stack alignment if it has nothing
10486 if (leaf && frame_size == 0)
10488 offsets->outgoing_args = offsets->soft_frame;
10492 /* Ensure SFP has the correct alignment. */
10493 if (ARM_DOUBLEWORD_ALIGN
10494 && (offsets->soft_frame & 7))
10495 offsets->soft_frame += 4;
10497 offsets->outgoing_args = offsets->soft_frame + frame_size
10498 + current_function_outgoing_args_size;
10500 if (ARM_DOUBLEWORD_ALIGN)
10502 /* Ensure SP remains doubleword aligned. */
10503 if (offsets->outgoing_args & 7)
10504 offsets->outgoing_args += 4;
10505 if (offsets->outgoing_args & 7)
10513 /* Calculate the relative offsets for the different stack pointers. Positive
10514 offsets are in the direction of stack growth. */
10517 arm_compute_initial_elimination_offset (unsigned int from, unsigned int to)
10519 arm_stack_offsets *offsets;
10521 offsets = arm_get_frame_offsets ();
10523 /* OK, now we have enough information to compute the distances.
10524 There must be an entry in these switch tables for each pair
10525 of registers in ELIMINABLE_REGS, even if some of the entries
10526 seem to be redundant or useless. */
10529 case ARG_POINTER_REGNUM:
10532 case THUMB_HARD_FRAME_POINTER_REGNUM:
10535 case FRAME_POINTER_REGNUM:
10536 /* This is the reverse of the soft frame pointer
10537 to hard frame pointer elimination below. */
10538 return offsets->soft_frame - offsets->saved_args;
10540 case ARM_HARD_FRAME_POINTER_REGNUM:
10541 /* If there is no stack frame then the hard
10542 frame pointer and the arg pointer coincide. */
10543 if (offsets->frame == offsets->saved_regs)
10545 /* FIXME: Not sure about this. Maybe we should always return 0 ? */
10546 return (frame_pointer_needed
10547 && cfun->static_chain_decl != NULL
10548 && ! cfun->machine->uses_anonymous_args) ? 4 : 0;
10550 case STACK_POINTER_REGNUM:
10551 /* If nothing has been pushed on the stack at all
10552 then this will return -4. This *is* correct! */
10553 return offsets->outgoing_args - (offsets->saved_args + 4);
10560 case FRAME_POINTER_REGNUM:
10563 case THUMB_HARD_FRAME_POINTER_REGNUM:
10566 case ARM_HARD_FRAME_POINTER_REGNUM:
10567 /* The hard frame pointer points to the top entry in the
10568 stack frame. The soft frame pointer to the bottom entry
10569 in the stack frame. If there is no stack frame at all,
10570 then they are identical. */
10572 return offsets->frame - offsets->soft_frame;
10574 case STACK_POINTER_REGNUM:
10575 return offsets->outgoing_args - offsets->soft_frame;
10583 /* You cannot eliminate from the stack pointer.
10584 In theory you could eliminate from the hard frame
10585 pointer to the stack pointer, but this will never
10586 happen, since if a stack frame is not needed the
10587 hard frame pointer will never be used. */
10593 /* Generate the prologue instructions for entry into an ARM function. */
10595 arm_expand_prologue (void)
10601 unsigned long live_regs_mask;
10602 unsigned long func_type;
10604 int saved_pretend_args = 0;
10605 int saved_regs = 0;
10606 unsigned int args_to_push;
10607 arm_stack_offsets *offsets;
10609 func_type = arm_current_func_type ();
10611 /* Naked functions don't have prologues. */
10612 if (IS_NAKED (func_type))
10615 /* Make a copy of c_f_p_a_s as we may need to modify it locally. */
10616 args_to_push = current_function_pretend_args_size;
10618 /* Compute which register we will have to save onto the stack. */
10619 live_regs_mask = arm_compute_save_reg_mask ();
10621 ip_rtx = gen_rtx_REG (SImode, IP_REGNUM);
10623 if (frame_pointer_needed)
10625 if (IS_INTERRUPT (func_type))
10627 /* Interrupt functions must not corrupt any registers.
10628 Creating a frame pointer however, corrupts the IP
10629 register, so we must push it first. */
10630 insn = emit_multi_reg_push (1 << IP_REGNUM);
10632 /* Do not set RTX_FRAME_RELATED_P on this insn.
10633 The dwarf stack unwinding code only wants to see one
10634 stack decrement per function, and this is not it. If
10635 this instruction is labeled as being part of the frame
10636 creation sequence then dwarf2out_frame_debug_expr will
10637 abort when it encounters the assignment of IP to FP
10638 later on, since the use of SP here establishes SP as
10639 the CFA register and not IP.
10641 Anyway this instruction is not really part of the stack
10642 frame creation although it is part of the prologue. */
10644 else if (IS_NESTED (func_type))
10646 /* The Static chain register is the same as the IP register
10647 used as a scratch register during stack frame creation.
10648 To get around this need to find somewhere to store IP
10649 whilst the frame is being created. We try the following
10652 1. The last argument register.
10653 2. A slot on the stack above the frame. (This only
10654 works if the function is not a varargs function).
10655 3. Register r3, after pushing the argument registers
10658 Note - we only need to tell the dwarf2 backend about the SP
10659 adjustment in the second variant; the static chain register
10660 doesn't need to be unwound, as it doesn't contain a value
10661 inherited from the caller. */
10663 if (regs_ever_live[3] == 0)
10665 insn = gen_rtx_REG (SImode, 3);
10666 insn = gen_rtx_SET (SImode, insn, ip_rtx);
10667 insn = emit_insn (insn);
10669 else if (args_to_push == 0)
10672 insn = gen_rtx_PRE_DEC (SImode, stack_pointer_rtx);
10673 insn = gen_rtx_MEM (SImode, insn);
10674 insn = gen_rtx_SET (VOIDmode, insn, ip_rtx);
10675 insn = emit_insn (insn);
10679 /* Just tell the dwarf backend that we adjusted SP. */
10680 dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
10681 gen_rtx_PLUS (SImode, stack_pointer_rtx,
10682 GEN_INT (-fp_offset)));
10683 RTX_FRAME_RELATED_P (insn) = 1;
10684 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
10685 dwarf, REG_NOTES (insn));
10689 /* Store the args on the stack. */
10690 if (cfun->machine->uses_anonymous_args)
10691 insn = emit_multi_reg_push
10692 ((0xf0 >> (args_to_push / 4)) & 0xf);
10695 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
10696 GEN_INT (- args_to_push)));
10698 RTX_FRAME_RELATED_P (insn) = 1;
10700 saved_pretend_args = 1;
10701 fp_offset = args_to_push;
10704 /* Now reuse r3 to preserve IP. */
10705 insn = gen_rtx_REG (SImode, 3);
10706 insn = gen_rtx_SET (SImode, insn, ip_rtx);
10707 (void) emit_insn (insn);
10713 insn = gen_rtx_PLUS (SImode, stack_pointer_rtx, GEN_INT (fp_offset));
10714 insn = gen_rtx_SET (SImode, ip_rtx, insn);
10717 insn = gen_movsi (ip_rtx, stack_pointer_rtx);
10719 insn = emit_insn (insn);
10720 RTX_FRAME_RELATED_P (insn) = 1;
10725 /* Push the argument registers, or reserve space for them. */
10726 if (cfun->machine->uses_anonymous_args)
10727 insn = emit_multi_reg_push
10728 ((0xf0 >> (args_to_push / 4)) & 0xf);
10731 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
10732 GEN_INT (- args_to_push)));
10733 RTX_FRAME_RELATED_P (insn) = 1;
10736 /* If this is an interrupt service routine, and the link register
10737 is going to be pushed, and we are not creating a stack frame,
10738 (which would involve an extra push of IP and a pop in the epilogue)
10739 subtracting four from LR now will mean that the function return
10740 can be done with a single instruction. */
10741 if ((func_type == ARM_FT_ISR || func_type == ARM_FT_FIQ)
10742 && (live_regs_mask & (1 << LR_REGNUM)) != 0
10743 && ! frame_pointer_needed)
10744 emit_insn (gen_rtx_SET (SImode,
10745 gen_rtx_REG (SImode, LR_REGNUM),
10746 gen_rtx_PLUS (SImode,
10747 gen_rtx_REG (SImode, LR_REGNUM),
10750 if (live_regs_mask)
10752 insn = emit_multi_reg_push (live_regs_mask);
10753 saved_regs += bit_count (live_regs_mask) * 4;
10754 RTX_FRAME_RELATED_P (insn) = 1;
10758 for (reg = LAST_IWMMXT_REGNUM; reg >= FIRST_IWMMXT_REGNUM; reg--)
10759 if (regs_ever_live[reg] && ! call_used_regs [reg])
10761 insn = gen_rtx_PRE_DEC (V2SImode, stack_pointer_rtx);
10762 insn = gen_rtx_MEM (V2SImode, insn);
10763 insn = emit_insn (gen_rtx_SET (VOIDmode, insn,
10764 gen_rtx_REG (V2SImode, reg)));
10765 RTX_FRAME_RELATED_P (insn) = 1;
10769 if (! IS_VOLATILE (func_type))
10773 /* Save any floating point call-saved registers used by this
10775 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
10777 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
10778 if (regs_ever_live[reg] && !call_used_regs[reg])
10780 insn = gen_rtx_PRE_DEC (XFmode, stack_pointer_rtx);
10781 insn = gen_rtx_MEM (XFmode, insn);
10782 insn = emit_insn (gen_rtx_SET (VOIDmode, insn,
10783 gen_rtx_REG (XFmode, reg)));
10784 RTX_FRAME_RELATED_P (insn) = 1;
10790 start_reg = LAST_FPA_REGNUM;
10792 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
10794 if (regs_ever_live[reg] && !call_used_regs[reg])
10796 if (start_reg - reg == 3)
10798 insn = emit_sfm (reg, 4);
10799 RTX_FRAME_RELATED_P (insn) = 1;
10801 start_reg = reg - 1;
10806 if (start_reg != reg)
10808 insn = emit_sfm (reg + 1, start_reg - reg);
10809 RTX_FRAME_RELATED_P (insn) = 1;
10810 saved_regs += (start_reg - reg) * 12;
10812 start_reg = reg - 1;
10816 if (start_reg != reg)
10818 insn = emit_sfm (reg + 1, start_reg - reg);
10819 saved_regs += (start_reg - reg) * 12;
10820 RTX_FRAME_RELATED_P (insn) = 1;
10823 if (TARGET_HARD_FLOAT && TARGET_VFP)
10825 start_reg = FIRST_VFP_REGNUM;
10827 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
10829 if ((!regs_ever_live[reg] || call_used_regs[reg])
10830 && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1]))
10832 if (start_reg != reg)
10833 saved_regs += vfp_emit_fstmx (start_reg,
10834 (reg - start_reg) / 2);
10835 start_reg = reg + 2;
10838 if (start_reg != reg)
10839 saved_regs += vfp_emit_fstmx (start_reg,
10840 (reg - start_reg) / 2);
10844 if (frame_pointer_needed)
10846 /* Create the new frame pointer. */
10847 insn = GEN_INT (-(4 + args_to_push + fp_offset));
10848 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, ip_rtx, insn));
10849 RTX_FRAME_RELATED_P (insn) = 1;
10851 if (IS_NESTED (func_type))
10853 /* Recover the static chain register. */
10854 if (regs_ever_live [3] == 0
10855 || saved_pretend_args)
10856 insn = gen_rtx_REG (SImode, 3);
10857 else /* if (current_function_pretend_args_size == 0) */
10859 insn = gen_rtx_PLUS (SImode, hard_frame_pointer_rtx,
10861 insn = gen_rtx_MEM (SImode, insn);
10864 emit_insn (gen_rtx_SET (SImode, ip_rtx, insn));
10865 /* Add a USE to stop propagate_one_insn() from barfing. */
10866 emit_insn (gen_prologue_use (ip_rtx));
10870 offsets = arm_get_frame_offsets ();
10871 if (offsets->outgoing_args != offsets->saved_args + saved_regs)
10873 /* This add can produce multiple insns for a large constant, so we
10874 need to get tricky. */
10875 rtx last = get_last_insn ();
10877 amount = GEN_INT (offsets->saved_args + saved_regs
10878 - offsets->outgoing_args);
10880 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
10884 last = last ? NEXT_INSN (last) : get_insns ();
10885 RTX_FRAME_RELATED_P (last) = 1;
10887 while (last != insn);
10889 /* If the frame pointer is needed, emit a special barrier that
10890 will prevent the scheduler from moving stores to the frame
10891 before the stack adjustment. */
10892 if (frame_pointer_needed)
10893 insn = emit_insn (gen_stack_tie (stack_pointer_rtx,
10894 hard_frame_pointer_rtx));
10899 arm_load_pic_register ();
10901 /* If we are profiling, make sure no instructions are scheduled before
10902 the call to mcount. Similarly if the user has requested no
10903 scheduling in the prolog. */
10904 if (current_function_profile || TARGET_NO_SCHED_PRO)
10905 emit_insn (gen_blockage ());
10907 /* If the link register is being kept alive, with the return address in it,
10908 then make sure that it does not get reused by the ce2 pass. */
10909 if ((live_regs_mask & (1 << LR_REGNUM)) == 0)
10911 emit_insn (gen_prologue_use (gen_rtx_REG (SImode, LR_REGNUM)));
10912 cfun->machine->lr_save_eliminated = 1;
10916 /* If CODE is 'd', then the X is a condition operand and the instruction
10917 should only be executed if the condition is true.
10918 if CODE is 'D', then the X is a condition operand and the instruction
10919 should only be executed if the condition is false: however, if the mode
10920 of the comparison is CCFPEmode, then always execute the instruction -- we
10921 do this because in these circumstances !GE does not necessarily imply LT;
10922 in these cases the instruction pattern will take care to make sure that
10923 an instruction containing %d will follow, thereby undoing the effects of
10924 doing this instruction unconditionally.
10925 If CODE is 'N' then X is a floating point operand that must be negated
10927 If CODE is 'B' then output a bitwise inverted value of X (a const int).
10928 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
10930 arm_print_operand (FILE *stream, rtx x, int code)
10935 fputs (ASM_COMMENT_START, stream);
10939 fputs (user_label_prefix, stream);
10943 fputs (REGISTER_PREFIX, stream);
10947 if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4)
10949 if (TARGET_THUMB || current_insn_predicate != NULL)
10952 fputs (arm_condition_codes[arm_current_cc], stream);
10954 else if (current_insn_predicate)
10956 enum arm_cond_code code;
10961 code = get_arm_condition_code (current_insn_predicate);
10962 fputs (arm_condition_codes[code], stream);
10969 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
10970 r = REAL_VALUE_NEGATE (r);
10971 fprintf (stream, "%s", fp_const_from_val (&r));
10976 if (GET_CODE (x) == CONST_INT)
10979 val = ARM_SIGN_EXTEND (~INTVAL (x));
10980 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val);
10984 putc ('~', stream);
10985 output_addr_const (stream, x);
10990 fprintf (stream, "%s", arithmetic_instr (x, 1));
10993 /* Truncate Cirrus shift counts. */
10995 if (GET_CODE (x) == CONST_INT)
10997 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0x3f);
11000 arm_print_operand (stream, x, 0);
11004 fprintf (stream, "%s", arithmetic_instr (x, 0));
11010 const char * shift = shift_op (x, &val);
11014 fprintf (stream, ", %s ", shift_op (x, &val));
11016 arm_print_operand (stream, XEXP (x, 1), 0);
11018 fprintf (stream, "#" HOST_WIDE_INT_PRINT_DEC, val);
11023 /* An explanation of the 'Q', 'R' and 'H' register operands:
11025 In a pair of registers containing a DI or DF value the 'Q'
11026 operand returns the register number of the register containing
11027 the least significant part of the value. The 'R' operand returns
11028 the register number of the register containing the most
11029 significant part of the value.
11031 The 'H' operand returns the higher of the two register numbers.
11032 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
11033 same as the 'Q' operand, since the most significant part of the
11034 value is held in the lower number register. The reverse is true
11035 on systems where WORDS_BIG_ENDIAN is false.
11037 The purpose of these operands is to distinguish between cases
11038 where the endian-ness of the values is important (for example
11039 when they are added together), and cases where the endian-ness
11040 is irrelevant, but the order of register operations is important.
11041 For example when loading a value from memory into a register
11042 pair, the endian-ness does not matter. Provided that the value
11043 from the lower memory address is put into the lower numbered
11044 register, and the value from the higher address is put into the
11045 higher numbered register, the load will work regardless of whether
11046 the value being loaded is big-wordian or little-wordian. The
11047 order of the two register loads can matter however, if the address
11048 of the memory location is actually held in one of the registers
11049 being overwritten by the load. */
11051 if (REGNO (x) > LAST_ARM_REGNUM)
11053 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0));
11057 if (REGNO (x) > LAST_ARM_REGNUM)
11059 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1));
11063 if (REGNO (x) > LAST_ARM_REGNUM)
11065 asm_fprintf (stream, "%r", REGNO (x) + 1);
11069 asm_fprintf (stream, "%r",
11070 GET_CODE (XEXP (x, 0)) == REG
11071 ? REGNO (XEXP (x, 0)) : REGNO (XEXP (XEXP (x, 0), 0)));
11075 asm_fprintf (stream, "{%r-%r}",
11077 REGNO (x) + ARM_NUM_REGS (GET_MODE (x)) - 1);
11081 /* CONST_TRUE_RTX means always -- that's the default. */
11082 if (x == const_true_rtx)
11085 fputs (arm_condition_codes[get_arm_condition_code (x)],
11090 /* CONST_TRUE_RTX means not always -- ie never. We shouldn't ever
11091 want to do that. */
11092 if (x == const_true_rtx)
11095 fputs (arm_condition_codes[ARM_INVERSE_CONDITION_CODE
11096 (get_arm_condition_code (x))],
11100 /* Cirrus registers can be accessed in a variety of ways:
11101 single floating point (f)
11102 double floating point (d)
11104 64bit integer (dx). */
11105 case 'W': /* Cirrus register in F mode. */
11106 case 'X': /* Cirrus register in D mode. */
11107 case 'Y': /* Cirrus register in FX mode. */
11108 case 'Z': /* Cirrus register in DX mode. */
11109 if (GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) != CIRRUS_REGS)
11112 fprintf (stream, "mv%s%s",
11114 : code == 'X' ? "d"
11115 : code == 'Y' ? "fx" : "dx", reg_names[REGNO (x)] + 2);
11119 /* Print cirrus register in the mode specified by the register's mode. */
11122 int mode = GET_MODE (x);
11124 if (GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) != CIRRUS_REGS)
11127 fprintf (stream, "mv%s%s",
11128 mode == DFmode ? "d"
11129 : mode == SImode ? "fx"
11130 : mode == DImode ? "dx"
11131 : "f", reg_names[REGNO (x)] + 2);
11137 if (GET_CODE (x) != REG
11138 || REGNO (x) < FIRST_IWMMXT_GR_REGNUM
11139 || REGNO (x) > LAST_IWMMXT_GR_REGNUM)
11140 /* Bad value for wCG register number. */
11143 fprintf (stream, "%d", REGNO (x) - FIRST_IWMMXT_GR_REGNUM);
11146 /* Print an iWMMXt control register name. */
11148 if (GET_CODE (x) != CONST_INT
11150 || INTVAL (x) >= 16)
11151 /* Bad value for wC register number. */
11155 static const char * wc_reg_names [16] =
11157 "wCID", "wCon", "wCSSF", "wCASF",
11158 "wC4", "wC5", "wC6", "wC7",
11159 "wCGR0", "wCGR1", "wCGR2", "wCGR3",
11160 "wC12", "wC13", "wC14", "wC15"
11163 fprintf (stream, wc_reg_names [INTVAL (x)]);
11167 /* Print a VFP double precision register name. */
11170 int mode = GET_MODE (x);
11173 if (mode != DImode && mode != DFmode)
11176 if (GET_CODE (x) != REG
11177 || !IS_VFP_REGNUM (REGNO (x)))
11180 num = REGNO(x) - FIRST_VFP_REGNUM;
11184 fprintf (stream, "d%d", num >> 1);
11192 if (GET_CODE (x) == REG)
11193 asm_fprintf (stream, "%r", REGNO (x));
11194 else if (GET_CODE (x) == MEM)
11196 output_memory_reference_mode = GET_MODE (x);
11197 output_address (XEXP (x, 0));
11199 else if (GET_CODE (x) == CONST_DOUBLE)
11200 fprintf (stream, "#%s", fp_immediate_constant (x));
11201 else if (GET_CODE (x) == NEG)
11202 abort (); /* This should never happen now. */
11205 fputc ('#', stream);
11206 output_addr_const (stream, x);
11211 #ifndef AOF_ASSEMBLER
11212 /* Target hook for assembling integer objects. The ARM version needs to
11213 handle word-sized values specially. */
11215 arm_assemble_integer (rtx x, unsigned int size, int aligned_p)
11217 if (size == UNITS_PER_WORD && aligned_p)
11219 fputs ("\t.word\t", asm_out_file);
11220 output_addr_const (asm_out_file, x);
11222 /* Mark symbols as position independent. We only do this in the
11223 .text segment, not in the .data segment. */
11224 if (NEED_GOT_RELOC && flag_pic && making_const_table &&
11225 (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF))
11227 if (GET_CODE (x) == SYMBOL_REF
11228 && (CONSTANT_POOL_ADDRESS_P (x)
11229 || SYMBOL_REF_LOCAL_P (x)))
11230 fputs ("(GOTOFF)", asm_out_file);
11231 else if (GET_CODE (x) == LABEL_REF)
11232 fputs ("(GOTOFF)", asm_out_file);
11234 fputs ("(GOT)", asm_out_file);
11236 fputc ('\n', asm_out_file);
11240 if (VECTOR_MODE_SUPPORTED_P (GET_MODE (x)))
11244 if (GET_CODE (x) != CONST_VECTOR)
11247 units = CONST_VECTOR_NUNITS (x);
11249 switch (GET_MODE (x))
11251 case V2SImode: size = 4; break;
11252 case V4HImode: size = 2; break;
11253 case V8QImode: size = 1; break;
11258 for (i = 0; i < units; i++)
11262 elt = CONST_VECTOR_ELT (x, i);
11264 (elt, size, i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT, 1);
11270 return default_assemble_integer (x, size, aligned_p);
11274 /* A finite state machine takes care of noticing whether or not instructions
11275 can be conditionally executed, and thus decrease execution time and code
11276 size by deleting branch instructions. The fsm is controlled by
11277 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
11279 /* The state of the fsm controlling condition codes are:
11280 0: normal, do nothing special
11281 1: make ASM_OUTPUT_OPCODE not output this instruction
11282 2: make ASM_OUTPUT_OPCODE not output this instruction
11283 3: make instructions conditional
11284 4: make instructions conditional
11286 State transitions (state->state by whom under condition):
11287 0 -> 1 final_prescan_insn if the `target' is a label
11288 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
11289 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
11290 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
11291 3 -> 0 (*targetm.asm_out.internal_label) if the `target' label is reached
11292 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
11293 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
11294 (the target insn is arm_target_insn).
11296 If the jump clobbers the conditions then we use states 2 and 4.
11298 A similar thing can be done with conditional return insns.
11300 XXX In case the `target' is an unconditional branch, this conditionalising
11301 of the instructions always reduces code size, but not always execution
11302 time. But then, I want to reduce the code size to somewhere near what
11303 /bin/cc produces. */
11305 /* Returns the index of the ARM condition code string in
11306 `arm_condition_codes'. COMPARISON should be an rtx like
11307 `(eq (...) (...))'. */
11308 static enum arm_cond_code
11309 get_arm_condition_code (rtx comparison)
11311 enum machine_mode mode = GET_MODE (XEXP (comparison, 0));
11313 enum rtx_code comp_code = GET_CODE (comparison);
11315 if (GET_MODE_CLASS (mode) != MODE_CC)
11316 mode = SELECT_CC_MODE (comp_code, XEXP (comparison, 0),
11317 XEXP (comparison, 1));
11321 case CC_DNEmode: code = ARM_NE; goto dominance;
11322 case CC_DEQmode: code = ARM_EQ; goto dominance;
11323 case CC_DGEmode: code = ARM_GE; goto dominance;
11324 case CC_DGTmode: code = ARM_GT; goto dominance;
11325 case CC_DLEmode: code = ARM_LE; goto dominance;
11326 case CC_DLTmode: code = ARM_LT; goto dominance;
11327 case CC_DGEUmode: code = ARM_CS; goto dominance;
11328 case CC_DGTUmode: code = ARM_HI; goto dominance;
11329 case CC_DLEUmode: code = ARM_LS; goto dominance;
11330 case CC_DLTUmode: code = ARM_CC;
11333 if (comp_code != EQ && comp_code != NE)
11336 if (comp_code == EQ)
11337 return ARM_INVERSE_CONDITION_CODE (code);
11343 case NE: return ARM_NE;
11344 case EQ: return ARM_EQ;
11345 case GE: return ARM_PL;
11346 case LT: return ARM_MI;
11353 case NE: return ARM_NE;
11354 case EQ: return ARM_EQ;
11361 case NE: return ARM_MI;
11362 case EQ: return ARM_PL;
11368 /* These encodings assume that AC=1 in the FPA system control
11369 byte. This allows us to handle all cases except UNEQ and
11373 case GE: return ARM_GE;
11374 case GT: return ARM_GT;
11375 case LE: return ARM_LS;
11376 case LT: return ARM_MI;
11377 case NE: return ARM_NE;
11378 case EQ: return ARM_EQ;
11379 case ORDERED: return ARM_VC;
11380 case UNORDERED: return ARM_VS;
11381 case UNLT: return ARM_LT;
11382 case UNLE: return ARM_LE;
11383 case UNGT: return ARM_HI;
11384 case UNGE: return ARM_PL;
11385 /* UNEQ and LTGT do not have a representation. */
11386 case UNEQ: /* Fall through. */
11387 case LTGT: /* Fall through. */
11394 case NE: return ARM_NE;
11395 case EQ: return ARM_EQ;
11396 case GE: return ARM_LE;
11397 case GT: return ARM_LT;
11398 case LE: return ARM_GE;
11399 case LT: return ARM_GT;
11400 case GEU: return ARM_LS;
11401 case GTU: return ARM_CC;
11402 case LEU: return ARM_CS;
11403 case LTU: return ARM_HI;
11410 case LTU: return ARM_CS;
11411 case GEU: return ARM_CC;
11418 case NE: return ARM_NE;
11419 case EQ: return ARM_EQ;
11420 case GE: return ARM_GE;
11421 case GT: return ARM_GT;
11422 case LE: return ARM_LE;
11423 case LT: return ARM_LT;
11424 case GEU: return ARM_CS;
11425 case GTU: return ARM_HI;
11426 case LEU: return ARM_LS;
11427 case LTU: return ARM_CC;
11438 arm_final_prescan_insn (rtx insn)
11440 /* BODY will hold the body of INSN. */
11441 rtx body = PATTERN (insn);
11443 /* This will be 1 if trying to repeat the trick, and things need to be
11444 reversed if it appears to fail. */
11447 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
11448 taken are clobbered, even if the rtl suggests otherwise. It also
11449 means that we have to grub around within the jump expression to find
11450 out what the conditions are when the jump isn't taken. */
11451 int jump_clobbers = 0;
11453 /* If we start with a return insn, we only succeed if we find another one. */
11454 int seeking_return = 0;
11456 /* START_INSN will hold the insn from where we start looking. This is the
11457 first insn after the following code_label if REVERSE is true. */
11458 rtx start_insn = insn;
11460 /* If in state 4, check if the target branch is reached, in order to
11461 change back to state 0. */
11462 if (arm_ccfsm_state == 4)
11464 if (insn == arm_target_insn)
11466 arm_target_insn = NULL;
11467 arm_ccfsm_state = 0;
11472 /* If in state 3, it is possible to repeat the trick, if this insn is an
11473 unconditional branch to a label, and immediately following this branch
11474 is the previous target label which is only used once, and the label this
11475 branch jumps to is not too far off. */
11476 if (arm_ccfsm_state == 3)
11478 if (simplejump_p (insn))
11480 start_insn = next_nonnote_insn (start_insn);
11481 if (GET_CODE (start_insn) == BARRIER)
11483 /* XXX Isn't this always a barrier? */
11484 start_insn = next_nonnote_insn (start_insn);
11486 if (GET_CODE (start_insn) == CODE_LABEL
11487 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
11488 && LABEL_NUSES (start_insn) == 1)
11493 else if (GET_CODE (body) == RETURN)
11495 start_insn = next_nonnote_insn (start_insn);
11496 if (GET_CODE (start_insn) == BARRIER)
11497 start_insn = next_nonnote_insn (start_insn);
11498 if (GET_CODE (start_insn) == CODE_LABEL
11499 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
11500 && LABEL_NUSES (start_insn) == 1)
11503 seeking_return = 1;
11512 if (arm_ccfsm_state != 0 && !reverse)
11514 if (GET_CODE (insn) != JUMP_INSN)
11517 /* This jump might be paralleled with a clobber of the condition codes
11518 the jump should always come first */
11519 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
11520 body = XVECEXP (body, 0, 0);
11523 || (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
11524 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE))
11527 int fail = FALSE, succeed = FALSE;
11528 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
11529 int then_not_else = TRUE;
11530 rtx this_insn = start_insn, label = 0;
11532 /* If the jump cannot be done with one instruction, we cannot
11533 conditionally execute the instruction in the inverse case. */
11534 if (get_attr_conds (insn) == CONDS_JUMP_CLOB)
11540 /* Register the insn jumped to. */
11543 if (!seeking_return)
11544 label = XEXP (SET_SRC (body), 0);
11546 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == LABEL_REF)
11547 label = XEXP (XEXP (SET_SRC (body), 1), 0);
11548 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == LABEL_REF)
11550 label = XEXP (XEXP (SET_SRC (body), 2), 0);
11551 then_not_else = FALSE;
11553 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN)
11554 seeking_return = 1;
11555 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN)
11557 seeking_return = 1;
11558 then_not_else = FALSE;
11563 /* See how many insns this branch skips, and what kind of insns. If all
11564 insns are okay, and the label or unconditional branch to the same
11565 label is not too far away, succeed. */
11566 for (insns_skipped = 0;
11567 !fail && !succeed && insns_skipped++ < max_insns_skipped;)
11571 this_insn = next_nonnote_insn (this_insn);
11575 switch (GET_CODE (this_insn))
11578 /* Succeed if it is the target label, otherwise fail since
11579 control falls in from somewhere else. */
11580 if (this_insn == label)
11584 arm_ccfsm_state = 2;
11585 this_insn = next_nonnote_insn (this_insn);
11588 arm_ccfsm_state = 1;
11596 /* Succeed if the following insn is the target label.
11598 If return insns are used then the last insn in a function
11599 will be a barrier. */
11600 this_insn = next_nonnote_insn (this_insn);
11601 if (this_insn && this_insn == label)
11605 arm_ccfsm_state = 2;
11606 this_insn = next_nonnote_insn (this_insn);
11609 arm_ccfsm_state = 1;
11617 /* The AAPCS says that conditional calls should not be
11618 used since they make interworking inefficient (the
11619 linker can't transform BL<cond> into BLX). That's
11620 only a problem if the machine has BLX. */
11627 /* Succeed if the following insn is the target label, or
11628 if the following two insns are a barrier and the
11630 this_insn = next_nonnote_insn (this_insn);
11631 if (this_insn && GET_CODE (this_insn) == BARRIER)
11632 this_insn = next_nonnote_insn (this_insn);
11634 if (this_insn && this_insn == label
11635 && insns_skipped < max_insns_skipped)
11639 arm_ccfsm_state = 2;
11640 this_insn = next_nonnote_insn (this_insn);
11643 arm_ccfsm_state = 1;
11651 /* If this is an unconditional branch to the same label, succeed.
11652 If it is to another label, do nothing. If it is conditional,
11654 /* XXX Probably, the tests for SET and the PC are
11657 scanbody = PATTERN (this_insn);
11658 if (GET_CODE (scanbody) == SET
11659 && GET_CODE (SET_DEST (scanbody)) == PC)
11661 if (GET_CODE (SET_SRC (scanbody)) == LABEL_REF
11662 && XEXP (SET_SRC (scanbody), 0) == label && !reverse)
11664 arm_ccfsm_state = 2;
11667 else if (GET_CODE (SET_SRC (scanbody)) == IF_THEN_ELSE)
11670 /* Fail if a conditional return is undesirable (eg on a
11671 StrongARM), but still allow this if optimizing for size. */
11672 else if (GET_CODE (scanbody) == RETURN
11673 && !use_return_insn (TRUE, NULL)
11676 else if (GET_CODE (scanbody) == RETURN
11679 arm_ccfsm_state = 2;
11682 else if (GET_CODE (scanbody) == PARALLEL)
11684 switch (get_attr_conds (this_insn))
11694 fail = TRUE; /* Unrecognized jump (eg epilogue). */
11699 /* Instructions using or affecting the condition codes make it
11701 scanbody = PATTERN (this_insn);
11702 if (!(GET_CODE (scanbody) == SET
11703 || GET_CODE (scanbody) == PARALLEL)
11704 || get_attr_conds (this_insn) != CONDS_NOCOND)
11707 /* A conditional cirrus instruction must be followed by
11708 a non Cirrus instruction. However, since we
11709 conditionalize instructions in this function and by
11710 the time we get here we can't add instructions
11711 (nops), because shorten_branches() has already been
11712 called, we will disable conditionalizing Cirrus
11713 instructions to be safe. */
11714 if (GET_CODE (scanbody) != USE
11715 && GET_CODE (scanbody) != CLOBBER
11716 && get_attr_cirrus (this_insn) != CIRRUS_NOT)
11726 if ((!seeking_return) && (arm_ccfsm_state == 1 || reverse))
11727 arm_target_label = CODE_LABEL_NUMBER (label);
11728 else if (seeking_return || arm_ccfsm_state == 2)
11730 while (this_insn && GET_CODE (PATTERN (this_insn)) == USE)
11732 this_insn = next_nonnote_insn (this_insn);
11733 if (this_insn && (GET_CODE (this_insn) == BARRIER
11734 || GET_CODE (this_insn) == CODE_LABEL))
11739 /* Oh, dear! we ran off the end.. give up. */
11740 recog (PATTERN (insn), insn, NULL);
11741 arm_ccfsm_state = 0;
11742 arm_target_insn = NULL;
11745 arm_target_insn = this_insn;
11754 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body),
11756 if (GET_CODE (XEXP (XEXP (SET_SRC (body), 0), 0)) == AND)
11757 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
11758 if (GET_CODE (XEXP (SET_SRC (body), 0)) == NE)
11759 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
11763 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
11766 arm_current_cc = get_arm_condition_code (XEXP (SET_SRC (body),
11770 if (reverse || then_not_else)
11771 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
11774 /* Restore recog_data (getting the attributes of other insns can
11775 destroy this array, but final.c assumes that it remains intact
11776 across this call; since the insn has been recognized already we
11777 call recog direct). */
11778 recog (PATTERN (insn), insn, NULL);
11782 /* Returns true if REGNO is a valid register
11783 for holding a quantity of type MODE. */
11785 arm_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
11787 if (GET_MODE_CLASS (mode) == MODE_CC)
11788 return regno == CC_REGNUM || regno == VFPCC_REGNUM;
11791 /* For the Thumb we only allow values bigger than SImode in
11792 registers 0 - 6, so that there is always a second low
11793 register available to hold the upper part of the value.
11794 We probably we ought to ensure that the register is the
11795 start of an even numbered register pair. */
11796 return (ARM_NUM_REGS (mode) < 2) || (regno < LAST_LO_REGNUM);
11798 if (IS_CIRRUS_REGNUM (regno))
11799 /* We have outlawed SI values in Cirrus registers because they
11800 reside in the lower 32 bits, but SF values reside in the
11801 upper 32 bits. This causes gcc all sorts of grief. We can't
11802 even split the registers into pairs because Cirrus SI values
11803 get sign extended to 64bits-- aldyh. */
11804 return (GET_MODE_CLASS (mode) == MODE_FLOAT) || (mode == DImode);
11806 if (IS_VFP_REGNUM (regno))
11808 if (mode == SFmode || mode == SImode)
11811 /* DFmode values are only valid in even register pairs. */
11812 if (mode == DFmode)
11813 return ((regno - FIRST_VFP_REGNUM) & 1) == 0;
11817 if (IS_IWMMXT_GR_REGNUM (regno))
11818 return mode == SImode;
11820 if (IS_IWMMXT_REGNUM (regno))
11821 return VALID_IWMMXT_REG_MODE (mode);
11823 /* We allow any value to be stored in the general registers.
11824 Restrict doubleword quantities to even register pairs so that we can
11826 if (regno <= LAST_ARM_REGNUM)
11827 return !(TARGET_LDRD && GET_MODE_SIZE (mode) > 4 && (regno & 1) != 0);
11829 if ( regno == FRAME_POINTER_REGNUM
11830 || regno == ARG_POINTER_REGNUM)
11831 /* We only allow integers in the fake hard registers. */
11832 return GET_MODE_CLASS (mode) == MODE_INT;
11834 /* The only registers left are the FPA registers
11835 which we only allow to hold FP values. */
11836 return GET_MODE_CLASS (mode) == MODE_FLOAT
11837 && regno >= FIRST_FPA_REGNUM
11838 && regno <= LAST_FPA_REGNUM;
11842 arm_regno_class (int regno)
11846 if (regno == STACK_POINTER_REGNUM)
11848 if (regno == CC_REGNUM)
11855 if ( regno <= LAST_ARM_REGNUM
11856 || regno == FRAME_POINTER_REGNUM
11857 || regno == ARG_POINTER_REGNUM)
11858 return GENERAL_REGS;
11860 if (regno == CC_REGNUM || regno == VFPCC_REGNUM)
11863 if (IS_CIRRUS_REGNUM (regno))
11864 return CIRRUS_REGS;
11866 if (IS_VFP_REGNUM (regno))
11869 if (IS_IWMMXT_REGNUM (regno))
11870 return IWMMXT_REGS;
11872 if (IS_IWMMXT_GR_REGNUM (regno))
11873 return IWMMXT_GR_REGS;
11878 /* Handle a special case when computing the offset
11879 of an argument from the frame pointer. */
11881 arm_debugger_arg_offset (int value, rtx addr)
11885 /* We are only interested if dbxout_parms() failed to compute the offset. */
11889 /* We can only cope with the case where the address is held in a register. */
11890 if (GET_CODE (addr) != REG)
11893 /* If we are using the frame pointer to point at the argument, then
11894 an offset of 0 is correct. */
11895 if (REGNO (addr) == (unsigned) HARD_FRAME_POINTER_REGNUM)
11898 /* If we are using the stack pointer to point at the
11899 argument, then an offset of 0 is correct. */
11900 if ((TARGET_THUMB || !frame_pointer_needed)
11901 && REGNO (addr) == SP_REGNUM)
11904 /* Oh dear. The argument is pointed to by a register rather
11905 than being held in a register, or being stored at a known
11906 offset from the frame pointer. Since GDB only understands
11907 those two kinds of argument we must translate the address
11908 held in the register into an offset from the frame pointer.
11909 We do this by searching through the insns for the function
11910 looking to see where this register gets its value. If the
11911 register is initialized from the frame pointer plus an offset
11912 then we are in luck and we can continue, otherwise we give up.
11914 This code is exercised by producing debugging information
11915 for a function with arguments like this:
11917 double func (double a, double b, int c, double d) {return d;}
11919 Without this code the stab for parameter 'd' will be set to
11920 an offset of 0 from the frame pointer, rather than 8. */
11922 /* The if() statement says:
11924 If the insn is a normal instruction
11925 and if the insn is setting the value in a register
11926 and if the register being set is the register holding the address of the argument
11927 and if the address is computing by an addition
11928 that involves adding to a register
11929 which is the frame pointer
11934 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
11936 if ( GET_CODE (insn) == INSN
11937 && GET_CODE (PATTERN (insn)) == SET
11938 && REGNO (XEXP (PATTERN (insn), 0)) == REGNO (addr)
11939 && GET_CODE (XEXP (PATTERN (insn), 1)) == PLUS
11940 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 0)) == REG
11941 && REGNO (XEXP (XEXP (PATTERN (insn), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
11942 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 1)) == CONST_INT
11945 value = INTVAL (XEXP (XEXP (PATTERN (insn), 1), 1));
11954 warning ("unable to compute real location of stacked parameter");
11955 value = 8; /* XXX magic hack */
11961 #define def_mbuiltin(MASK, NAME, TYPE, CODE) \
11964 if ((MASK) & insn_flags) \
11965 lang_hooks.builtin_function ((NAME), (TYPE), (CODE), \
11966 BUILT_IN_MD, NULL, NULL_TREE); \
11970 struct builtin_description
11972 const unsigned int mask;
11973 const enum insn_code icode;
11974 const char * const name;
11975 const enum arm_builtins code;
11976 const enum rtx_code comparison;
11977 const unsigned int flag;
11980 static const struct builtin_description bdesc_2arg[] =
11982 #define IWMMXT_BUILTIN(code, string, builtin) \
11983 { FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \
11984 ARM_BUILTIN_##builtin, 0, 0 },
11986 IWMMXT_BUILTIN (addv8qi3, "waddb", WADDB)
11987 IWMMXT_BUILTIN (addv4hi3, "waddh", WADDH)
11988 IWMMXT_BUILTIN (addv2si3, "waddw", WADDW)
11989 IWMMXT_BUILTIN (subv8qi3, "wsubb", WSUBB)
11990 IWMMXT_BUILTIN (subv4hi3, "wsubh", WSUBH)
11991 IWMMXT_BUILTIN (subv2si3, "wsubw", WSUBW)
11992 IWMMXT_BUILTIN (ssaddv8qi3, "waddbss", WADDSSB)
11993 IWMMXT_BUILTIN (ssaddv4hi3, "waddhss", WADDSSH)
11994 IWMMXT_BUILTIN (ssaddv2si3, "waddwss", WADDSSW)
11995 IWMMXT_BUILTIN (sssubv8qi3, "wsubbss", WSUBSSB)
11996 IWMMXT_BUILTIN (sssubv4hi3, "wsubhss", WSUBSSH)
11997 IWMMXT_BUILTIN (sssubv2si3, "wsubwss", WSUBSSW)
11998 IWMMXT_BUILTIN (usaddv8qi3, "waddbus", WADDUSB)
11999 IWMMXT_BUILTIN (usaddv4hi3, "waddhus", WADDUSH)
12000 IWMMXT_BUILTIN (usaddv2si3, "waddwus", WADDUSW)
12001 IWMMXT_BUILTIN (ussubv8qi3, "wsubbus", WSUBUSB)
12002 IWMMXT_BUILTIN (ussubv4hi3, "wsubhus", WSUBUSH)
12003 IWMMXT_BUILTIN (ussubv2si3, "wsubwus", WSUBUSW)
12004 IWMMXT_BUILTIN (mulv4hi3, "wmulul", WMULUL)
12005 IWMMXT_BUILTIN (smulv4hi3_highpart, "wmulsm", WMULSM)
12006 IWMMXT_BUILTIN (umulv4hi3_highpart, "wmulum", WMULUM)
12007 IWMMXT_BUILTIN (eqv8qi3, "wcmpeqb", WCMPEQB)
12008 IWMMXT_BUILTIN (eqv4hi3, "wcmpeqh", WCMPEQH)
12009 IWMMXT_BUILTIN (eqv2si3, "wcmpeqw", WCMPEQW)
12010 IWMMXT_BUILTIN (gtuv8qi3, "wcmpgtub", WCMPGTUB)
12011 IWMMXT_BUILTIN (gtuv4hi3, "wcmpgtuh", WCMPGTUH)
12012 IWMMXT_BUILTIN (gtuv2si3, "wcmpgtuw", WCMPGTUW)
12013 IWMMXT_BUILTIN (gtv8qi3, "wcmpgtsb", WCMPGTSB)
12014 IWMMXT_BUILTIN (gtv4hi3, "wcmpgtsh", WCMPGTSH)
12015 IWMMXT_BUILTIN (gtv2si3, "wcmpgtsw", WCMPGTSW)
12016 IWMMXT_BUILTIN (umaxv8qi3, "wmaxub", WMAXUB)
12017 IWMMXT_BUILTIN (smaxv8qi3, "wmaxsb", WMAXSB)
12018 IWMMXT_BUILTIN (umaxv4hi3, "wmaxuh", WMAXUH)
12019 IWMMXT_BUILTIN (smaxv4hi3, "wmaxsh", WMAXSH)
12020 IWMMXT_BUILTIN (umaxv2si3, "wmaxuw", WMAXUW)
12021 IWMMXT_BUILTIN (smaxv2si3, "wmaxsw", WMAXSW)
12022 IWMMXT_BUILTIN (uminv8qi3, "wminub", WMINUB)
12023 IWMMXT_BUILTIN (sminv8qi3, "wminsb", WMINSB)
12024 IWMMXT_BUILTIN (uminv4hi3, "wminuh", WMINUH)
12025 IWMMXT_BUILTIN (sminv4hi3, "wminsh", WMINSH)
12026 IWMMXT_BUILTIN (uminv2si3, "wminuw", WMINUW)
12027 IWMMXT_BUILTIN (sminv2si3, "wminsw", WMINSW)
12028 IWMMXT_BUILTIN (iwmmxt_anddi3, "wand", WAND)
12029 IWMMXT_BUILTIN (iwmmxt_nanddi3, "wandn", WANDN)
12030 IWMMXT_BUILTIN (iwmmxt_iordi3, "wor", WOR)
12031 IWMMXT_BUILTIN (iwmmxt_xordi3, "wxor", WXOR)
12032 IWMMXT_BUILTIN (iwmmxt_uavgv8qi3, "wavg2b", WAVG2B)
12033 IWMMXT_BUILTIN (iwmmxt_uavgv4hi3, "wavg2h", WAVG2H)
12034 IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3, "wavg2br", WAVG2BR)
12035 IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3, "wavg2hr", WAVG2HR)
12036 IWMMXT_BUILTIN (iwmmxt_wunpckilb, "wunpckilb", WUNPCKILB)
12037 IWMMXT_BUILTIN (iwmmxt_wunpckilh, "wunpckilh", WUNPCKILH)
12038 IWMMXT_BUILTIN (iwmmxt_wunpckilw, "wunpckilw", WUNPCKILW)
12039 IWMMXT_BUILTIN (iwmmxt_wunpckihb, "wunpckihb", WUNPCKIHB)
12040 IWMMXT_BUILTIN (iwmmxt_wunpckihh, "wunpckihh", WUNPCKIHH)
12041 IWMMXT_BUILTIN (iwmmxt_wunpckihw, "wunpckihw", WUNPCKIHW)
12042 IWMMXT_BUILTIN (iwmmxt_wmadds, "wmadds", WMADDS)
12043 IWMMXT_BUILTIN (iwmmxt_wmaddu, "wmaddu", WMADDU)
12045 #define IWMMXT_BUILTIN2(code, builtin) \
12046 { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, 0, 0 },
12048 IWMMXT_BUILTIN2 (iwmmxt_wpackhss, WPACKHSS)
12049 IWMMXT_BUILTIN2 (iwmmxt_wpackwss, WPACKWSS)
12050 IWMMXT_BUILTIN2 (iwmmxt_wpackdss, WPACKDSS)
12051 IWMMXT_BUILTIN2 (iwmmxt_wpackhus, WPACKHUS)
12052 IWMMXT_BUILTIN2 (iwmmxt_wpackwus, WPACKWUS)
12053 IWMMXT_BUILTIN2 (iwmmxt_wpackdus, WPACKDUS)
12054 IWMMXT_BUILTIN2 (ashlv4hi3_di, WSLLH)
12055 IWMMXT_BUILTIN2 (ashlv4hi3, WSLLHI)
12056 IWMMXT_BUILTIN2 (ashlv2si3_di, WSLLW)
12057 IWMMXT_BUILTIN2 (ashlv2si3, WSLLWI)
12058 IWMMXT_BUILTIN2 (ashldi3_di, WSLLD)
12059 IWMMXT_BUILTIN2 (ashldi3_iwmmxt, WSLLDI)
12060 IWMMXT_BUILTIN2 (lshrv4hi3_di, WSRLH)
12061 IWMMXT_BUILTIN2 (lshrv4hi3, WSRLHI)
12062 IWMMXT_BUILTIN2 (lshrv2si3_di, WSRLW)
12063 IWMMXT_BUILTIN2 (lshrv2si3, WSRLWI)
12064 IWMMXT_BUILTIN2 (lshrdi3_di, WSRLD)
12065 IWMMXT_BUILTIN2 (lshrdi3_iwmmxt, WSRLDI)
12066 IWMMXT_BUILTIN2 (ashrv4hi3_di, WSRAH)
12067 IWMMXT_BUILTIN2 (ashrv4hi3, WSRAHI)
12068 IWMMXT_BUILTIN2 (ashrv2si3_di, WSRAW)
12069 IWMMXT_BUILTIN2 (ashrv2si3, WSRAWI)
12070 IWMMXT_BUILTIN2 (ashrdi3_di, WSRAD)
12071 IWMMXT_BUILTIN2 (ashrdi3_iwmmxt, WSRADI)
12072 IWMMXT_BUILTIN2 (rorv4hi3_di, WRORH)
12073 IWMMXT_BUILTIN2 (rorv4hi3, WRORHI)
12074 IWMMXT_BUILTIN2 (rorv2si3_di, WRORW)
12075 IWMMXT_BUILTIN2 (rorv2si3, WRORWI)
12076 IWMMXT_BUILTIN2 (rordi3_di, WRORD)
12077 IWMMXT_BUILTIN2 (rordi3, WRORDI)
12078 IWMMXT_BUILTIN2 (iwmmxt_wmacuz, WMACUZ)
12079 IWMMXT_BUILTIN2 (iwmmxt_wmacsz, WMACSZ)
12082 static const struct builtin_description bdesc_1arg[] =
12084 IWMMXT_BUILTIN (iwmmxt_tmovmskb, "tmovmskb", TMOVMSKB)
12085 IWMMXT_BUILTIN (iwmmxt_tmovmskh, "tmovmskh", TMOVMSKH)
12086 IWMMXT_BUILTIN (iwmmxt_tmovmskw, "tmovmskw", TMOVMSKW)
12087 IWMMXT_BUILTIN (iwmmxt_waccb, "waccb", WACCB)
12088 IWMMXT_BUILTIN (iwmmxt_wacch, "wacch", WACCH)
12089 IWMMXT_BUILTIN (iwmmxt_waccw, "waccw", WACCW)
12090 IWMMXT_BUILTIN (iwmmxt_wunpckehub, "wunpckehub", WUNPCKEHUB)
12091 IWMMXT_BUILTIN (iwmmxt_wunpckehuh, "wunpckehuh", WUNPCKEHUH)
12092 IWMMXT_BUILTIN (iwmmxt_wunpckehuw, "wunpckehuw", WUNPCKEHUW)
12093 IWMMXT_BUILTIN (iwmmxt_wunpckehsb, "wunpckehsb", WUNPCKEHSB)
12094 IWMMXT_BUILTIN (iwmmxt_wunpckehsh, "wunpckehsh", WUNPCKEHSH)
12095 IWMMXT_BUILTIN (iwmmxt_wunpckehsw, "wunpckehsw", WUNPCKEHSW)
12096 IWMMXT_BUILTIN (iwmmxt_wunpckelub, "wunpckelub", WUNPCKELUB)
12097 IWMMXT_BUILTIN (iwmmxt_wunpckeluh, "wunpckeluh", WUNPCKELUH)
12098 IWMMXT_BUILTIN (iwmmxt_wunpckeluw, "wunpckeluw", WUNPCKELUW)
12099 IWMMXT_BUILTIN (iwmmxt_wunpckelsb, "wunpckelsb", WUNPCKELSB)
12100 IWMMXT_BUILTIN (iwmmxt_wunpckelsh, "wunpckelsh", WUNPCKELSH)
12101 IWMMXT_BUILTIN (iwmmxt_wunpckelsw, "wunpckelsw", WUNPCKELSW)
12104 /* Set up all the iWMMXt builtins. This is
12105 not called if TARGET_IWMMXT is zero. */
12108 arm_init_iwmmxt_builtins (void)
12110 const struct builtin_description * d;
12112 tree endlink = void_list_node;
12114 tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
12115 tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
12116 tree V8QI_type_node = build_vector_type_for_mode (intQI_type_node, V8QImode);
12119 = build_function_type (integer_type_node,
12120 tree_cons (NULL_TREE, integer_type_node, endlink));
12121 tree v8qi_ftype_v8qi_v8qi_int
12122 = build_function_type (V8QI_type_node,
12123 tree_cons (NULL_TREE, V8QI_type_node,
12124 tree_cons (NULL_TREE, V8QI_type_node,
12125 tree_cons (NULL_TREE,
12128 tree v4hi_ftype_v4hi_int
12129 = build_function_type (V4HI_type_node,
12130 tree_cons (NULL_TREE, V4HI_type_node,
12131 tree_cons (NULL_TREE, integer_type_node,
12133 tree v2si_ftype_v2si_int
12134 = build_function_type (V2SI_type_node,
12135 tree_cons (NULL_TREE, V2SI_type_node,
12136 tree_cons (NULL_TREE, integer_type_node,
12138 tree v2si_ftype_di_di
12139 = build_function_type (V2SI_type_node,
12140 tree_cons (NULL_TREE, long_long_integer_type_node,
12141 tree_cons (NULL_TREE, long_long_integer_type_node,
12143 tree di_ftype_di_int
12144 = build_function_type (long_long_integer_type_node,
12145 tree_cons (NULL_TREE, long_long_integer_type_node,
12146 tree_cons (NULL_TREE, integer_type_node,
12148 tree di_ftype_di_int_int
12149 = build_function_type (long_long_integer_type_node,
12150 tree_cons (NULL_TREE, long_long_integer_type_node,
12151 tree_cons (NULL_TREE, integer_type_node,
12152 tree_cons (NULL_TREE,
12155 tree int_ftype_v8qi
12156 = build_function_type (integer_type_node,
12157 tree_cons (NULL_TREE, V8QI_type_node,
12159 tree int_ftype_v4hi
12160 = build_function_type (integer_type_node,
12161 tree_cons (NULL_TREE, V4HI_type_node,
12163 tree int_ftype_v2si
12164 = build_function_type (integer_type_node,
12165 tree_cons (NULL_TREE, V2SI_type_node,
12167 tree int_ftype_v8qi_int
12168 = build_function_type (integer_type_node,
12169 tree_cons (NULL_TREE, V8QI_type_node,
12170 tree_cons (NULL_TREE, integer_type_node,
12172 tree int_ftype_v4hi_int
12173 = build_function_type (integer_type_node,
12174 tree_cons (NULL_TREE, V4HI_type_node,
12175 tree_cons (NULL_TREE, integer_type_node,
12177 tree int_ftype_v2si_int
12178 = build_function_type (integer_type_node,
12179 tree_cons (NULL_TREE, V2SI_type_node,
12180 tree_cons (NULL_TREE, integer_type_node,
12182 tree v8qi_ftype_v8qi_int_int
12183 = build_function_type (V8QI_type_node,
12184 tree_cons (NULL_TREE, V8QI_type_node,
12185 tree_cons (NULL_TREE, integer_type_node,
12186 tree_cons (NULL_TREE,
12189 tree v4hi_ftype_v4hi_int_int
12190 = build_function_type (V4HI_type_node,
12191 tree_cons (NULL_TREE, V4HI_type_node,
12192 tree_cons (NULL_TREE, integer_type_node,
12193 tree_cons (NULL_TREE,
12196 tree v2si_ftype_v2si_int_int
12197 = build_function_type (V2SI_type_node,
12198 tree_cons (NULL_TREE, V2SI_type_node,
12199 tree_cons (NULL_TREE, integer_type_node,
12200 tree_cons (NULL_TREE,
12203 /* Miscellaneous. */
12204 tree v8qi_ftype_v4hi_v4hi
12205 = build_function_type (V8QI_type_node,
12206 tree_cons (NULL_TREE, V4HI_type_node,
12207 tree_cons (NULL_TREE, V4HI_type_node,
12209 tree v4hi_ftype_v2si_v2si
12210 = build_function_type (V4HI_type_node,
12211 tree_cons (NULL_TREE, V2SI_type_node,
12212 tree_cons (NULL_TREE, V2SI_type_node,
12214 tree v2si_ftype_v4hi_v4hi
12215 = build_function_type (V2SI_type_node,
12216 tree_cons (NULL_TREE, V4HI_type_node,
12217 tree_cons (NULL_TREE, V4HI_type_node,
12219 tree v2si_ftype_v8qi_v8qi
12220 = build_function_type (V2SI_type_node,
12221 tree_cons (NULL_TREE, V8QI_type_node,
12222 tree_cons (NULL_TREE, V8QI_type_node,
12224 tree v4hi_ftype_v4hi_di
12225 = build_function_type (V4HI_type_node,
12226 tree_cons (NULL_TREE, V4HI_type_node,
12227 tree_cons (NULL_TREE,
12228 long_long_integer_type_node,
12230 tree v2si_ftype_v2si_di
12231 = build_function_type (V2SI_type_node,
12232 tree_cons (NULL_TREE, V2SI_type_node,
12233 tree_cons (NULL_TREE,
12234 long_long_integer_type_node,
12236 tree void_ftype_int_int
12237 = build_function_type (void_type_node,
12238 tree_cons (NULL_TREE, integer_type_node,
12239 tree_cons (NULL_TREE, integer_type_node,
12242 = build_function_type (long_long_unsigned_type_node, endlink);
12244 = build_function_type (long_long_integer_type_node,
12245 tree_cons (NULL_TREE, V8QI_type_node,
12248 = build_function_type (long_long_integer_type_node,
12249 tree_cons (NULL_TREE, V4HI_type_node,
12252 = build_function_type (long_long_integer_type_node,
12253 tree_cons (NULL_TREE, V2SI_type_node,
12255 tree v2si_ftype_v4hi
12256 = build_function_type (V2SI_type_node,
12257 tree_cons (NULL_TREE, V4HI_type_node,
12259 tree v4hi_ftype_v8qi
12260 = build_function_type (V4HI_type_node,
12261 tree_cons (NULL_TREE, V8QI_type_node,
12264 tree di_ftype_di_v4hi_v4hi
12265 = build_function_type (long_long_unsigned_type_node,
12266 tree_cons (NULL_TREE,
12267 long_long_unsigned_type_node,
12268 tree_cons (NULL_TREE, V4HI_type_node,
12269 tree_cons (NULL_TREE,
12273 tree di_ftype_v4hi_v4hi
12274 = build_function_type (long_long_unsigned_type_node,
12275 tree_cons (NULL_TREE, V4HI_type_node,
12276 tree_cons (NULL_TREE, V4HI_type_node,
12279 /* Normal vector binops. */
12280 tree v8qi_ftype_v8qi_v8qi
12281 = build_function_type (V8QI_type_node,
12282 tree_cons (NULL_TREE, V8QI_type_node,
12283 tree_cons (NULL_TREE, V8QI_type_node,
12285 tree v4hi_ftype_v4hi_v4hi
12286 = build_function_type (V4HI_type_node,
12287 tree_cons (NULL_TREE, V4HI_type_node,
12288 tree_cons (NULL_TREE, V4HI_type_node,
12290 tree v2si_ftype_v2si_v2si
12291 = build_function_type (V2SI_type_node,
12292 tree_cons (NULL_TREE, V2SI_type_node,
12293 tree_cons (NULL_TREE, V2SI_type_node,
12295 tree di_ftype_di_di
12296 = build_function_type (long_long_unsigned_type_node,
12297 tree_cons (NULL_TREE, long_long_unsigned_type_node,
12298 tree_cons (NULL_TREE,
12299 long_long_unsigned_type_node,
12302 /* Add all builtins that are more or less simple operations on two
12304 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
12306 /* Use one of the operands; the target can have a different mode for
12307 mask-generating compares. */
12308 enum machine_mode mode;
12314 mode = insn_data[d->icode].operand[1].mode;
12319 type = v8qi_ftype_v8qi_v8qi;
12322 type = v4hi_ftype_v4hi_v4hi;
12325 type = v2si_ftype_v2si_v2si;
12328 type = di_ftype_di_di;
12335 def_mbuiltin (d->mask, d->name, type, d->code);
12338 /* Add the remaining MMX insns with somewhat more complicated types. */
12339 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wzero", di_ftype_void, ARM_BUILTIN_WZERO);
12340 def_mbuiltin (FL_IWMMXT, "__builtin_arm_setwcx", void_ftype_int_int, ARM_BUILTIN_SETWCX);
12341 def_mbuiltin (FL_IWMMXT, "__builtin_arm_getwcx", int_ftype_int, ARM_BUILTIN_GETWCX);
12343 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSLLH);
12344 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllw", v2si_ftype_v2si_di, ARM_BUILTIN_WSLLW);
12345 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslld", di_ftype_di_di, ARM_BUILTIN_WSLLD);
12346 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSLLHI);
12347 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSLLWI);
12348 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslldi", di_ftype_di_int, ARM_BUILTIN_WSLLDI);
12350 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRLH);
12351 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRLW);
12352 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrld", di_ftype_di_di, ARM_BUILTIN_WSRLD);
12353 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRLHI);
12354 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRLWI);
12355 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrldi", di_ftype_di_int, ARM_BUILTIN_WSRLDI);
12357 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrah", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRAH);
12358 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsraw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRAW);
12359 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrad", di_ftype_di_di, ARM_BUILTIN_WSRAD);
12360 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrahi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRAHI);
12361 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrawi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRAWI);
12362 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsradi", di_ftype_di_int, ARM_BUILTIN_WSRADI);
12364 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WRORH);
12365 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorw", v2si_ftype_v2si_di, ARM_BUILTIN_WRORW);
12366 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrord", di_ftype_di_di, ARM_BUILTIN_WRORD);
12367 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WRORHI);
12368 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorwi", v2si_ftype_v2si_int, ARM_BUILTIN_WRORWI);
12369 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrordi", di_ftype_di_int, ARM_BUILTIN_WRORDI);
12371 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wshufh", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSHUFH);
12373 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadb", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADB);
12374 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadh", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADH);
12375 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadbz", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADBZ);
12376 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadhz", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADHZ);
12378 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsb", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMSB);
12379 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMSH);
12380 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMSW);
12381 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmub", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMUB);
12382 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMUH);
12383 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMUW);
12384 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrb", v8qi_ftype_v8qi_int_int, ARM_BUILTIN_TINSRB);
12385 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrh", v4hi_ftype_v4hi_int_int, ARM_BUILTIN_TINSRH);
12386 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrw", v2si_ftype_v2si_int_int, ARM_BUILTIN_TINSRW);
12388 def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccb", di_ftype_v8qi, ARM_BUILTIN_WACCB);
12389 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wacch", di_ftype_v4hi, ARM_BUILTIN_WACCH);
12390 def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccw", di_ftype_v2si, ARM_BUILTIN_WACCW);
12392 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskb", int_ftype_v8qi, ARM_BUILTIN_TMOVMSKB);
12393 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskh", int_ftype_v4hi, ARM_BUILTIN_TMOVMSKH);
12394 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskw", int_ftype_v2si, ARM_BUILTIN_TMOVMSKW);
12396 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhss", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHSS);
12397 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhus", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHUS);
12398 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwus", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWUS);
12399 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwss", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWSS);
12400 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdus", v2si_ftype_di_di, ARM_BUILTIN_WPACKDUS);
12401 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdss", v2si_ftype_di_di, ARM_BUILTIN_WPACKDSS);
12403 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHUB);
12404 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHUH);
12405 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHUW);
12406 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHSB);
12407 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHSH);
12408 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHSW);
12409 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELUB);
12410 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELUH);
12411 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELUW);
12412 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELSB);
12413 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELSH);
12414 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELSW);
12416 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacs", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACS);
12417 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacsz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACSZ);
12418 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacu", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACU);
12419 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacuz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACUZ);
12421 def_mbuiltin (FL_IWMMXT, "__builtin_arm_walign", v8qi_ftype_v8qi_v8qi_int, ARM_BUILTIN_WALIGN);
12422 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmia", di_ftype_di_int_int, ARM_BUILTIN_TMIA);
12423 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiaph", di_ftype_di_int_int, ARM_BUILTIN_TMIAPH);
12424 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabb", di_ftype_di_int_int, ARM_BUILTIN_TMIABB);
12425 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabt", di_ftype_di_int_int, ARM_BUILTIN_TMIABT);
12426 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatb", di_ftype_di_int_int, ARM_BUILTIN_TMIATB);
12427 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatt", di_ftype_di_int_int, ARM_BUILTIN_TMIATT);
12431 arm_init_builtins (void)
12433 if (TARGET_REALLY_IWMMXT)
12434 arm_init_iwmmxt_builtins ();
12437 /* Errors in the source file can cause expand_expr to return const0_rtx
12438 where we expect a vector. To avoid crashing, use one of the vector
12439 clear instructions. */
12442 safe_vector_operand (rtx x, enum machine_mode mode)
12444 if (x != const0_rtx)
12446 x = gen_reg_rtx (mode);
12448 emit_insn (gen_iwmmxt_clrdi (mode == DImode ? x
12449 : gen_rtx_SUBREG (DImode, x, 0)));
12453 /* Subroutine of arm_expand_builtin to take care of binop insns. */
12456 arm_expand_binop_builtin (enum insn_code icode,
12457 tree arglist, rtx target)
12460 tree arg0 = TREE_VALUE (arglist);
12461 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12462 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12463 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12464 enum machine_mode tmode = insn_data[icode].operand[0].mode;
12465 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
12466 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
12468 if (VECTOR_MODE_P (mode0))
12469 op0 = safe_vector_operand (op0, mode0);
12470 if (VECTOR_MODE_P (mode1))
12471 op1 = safe_vector_operand (op1, mode1);
12474 || GET_MODE (target) != tmode
12475 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12476 target = gen_reg_rtx (tmode);
12478 /* In case the insn wants input operands in modes different from
12479 the result, abort. */
12480 if (GET_MODE (op0) != mode0 || GET_MODE (op1) != mode1)
12483 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12484 op0 = copy_to_mode_reg (mode0, op0);
12485 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
12486 op1 = copy_to_mode_reg (mode1, op1);
12488 pat = GEN_FCN (icode) (target, op0, op1);
12495 /* Subroutine of arm_expand_builtin to take care of unop insns. */
12498 arm_expand_unop_builtin (enum insn_code icode,
12499 tree arglist, rtx target, int do_load)
12502 tree arg0 = TREE_VALUE (arglist);
12503 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12504 enum machine_mode tmode = insn_data[icode].operand[0].mode;
12505 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
12508 || GET_MODE (target) != tmode
12509 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12510 target = gen_reg_rtx (tmode);
12512 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
12515 if (VECTOR_MODE_P (mode0))
12516 op0 = safe_vector_operand (op0, mode0);
12518 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12519 op0 = copy_to_mode_reg (mode0, op0);
12522 pat = GEN_FCN (icode) (target, op0);
12529 /* Expand an expression EXP that calls a built-in function,
12530 with result going to TARGET if that's convenient
12531 (and in mode MODE if that's convenient).
12532 SUBTARGET may be used as the target for computing one of EXP's operands.
12533 IGNORE is nonzero if the value is to be ignored. */
12536 arm_expand_builtin (tree exp,
12538 rtx subtarget ATTRIBUTE_UNUSED,
12539 enum machine_mode mode ATTRIBUTE_UNUSED,
12540 int ignore ATTRIBUTE_UNUSED)
12542 const struct builtin_description * d;
12543 enum insn_code icode;
12544 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
12545 tree arglist = TREE_OPERAND (exp, 1);
12553 int fcode = DECL_FUNCTION_CODE (fndecl);
12555 enum machine_mode tmode;
12556 enum machine_mode mode0;
12557 enum machine_mode mode1;
12558 enum machine_mode mode2;
12562 case ARM_BUILTIN_TEXTRMSB:
12563 case ARM_BUILTIN_TEXTRMUB:
12564 case ARM_BUILTIN_TEXTRMSH:
12565 case ARM_BUILTIN_TEXTRMUH:
12566 case ARM_BUILTIN_TEXTRMSW:
12567 case ARM_BUILTIN_TEXTRMUW:
12568 icode = (fcode == ARM_BUILTIN_TEXTRMSB ? CODE_FOR_iwmmxt_textrmsb
12569 : fcode == ARM_BUILTIN_TEXTRMUB ? CODE_FOR_iwmmxt_textrmub
12570 : fcode == ARM_BUILTIN_TEXTRMSH ? CODE_FOR_iwmmxt_textrmsh
12571 : fcode == ARM_BUILTIN_TEXTRMUH ? CODE_FOR_iwmmxt_textrmuh
12572 : CODE_FOR_iwmmxt_textrmw);
12574 arg0 = TREE_VALUE (arglist);
12575 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12576 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12577 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12578 tmode = insn_data[icode].operand[0].mode;
12579 mode0 = insn_data[icode].operand[1].mode;
12580 mode1 = insn_data[icode].operand[2].mode;
12582 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12583 op0 = copy_to_mode_reg (mode0, op0);
12584 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
12586 /* @@@ better error message */
12587 error ("selector must be an immediate");
12588 return gen_reg_rtx (tmode);
12591 || GET_MODE (target) != tmode
12592 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12593 target = gen_reg_rtx (tmode);
12594 pat = GEN_FCN (icode) (target, op0, op1);
12600 case ARM_BUILTIN_TINSRB:
12601 case ARM_BUILTIN_TINSRH:
12602 case ARM_BUILTIN_TINSRW:
12603 icode = (fcode == ARM_BUILTIN_TINSRB ? CODE_FOR_iwmmxt_tinsrb
12604 : fcode == ARM_BUILTIN_TINSRH ? CODE_FOR_iwmmxt_tinsrh
12605 : CODE_FOR_iwmmxt_tinsrw);
12606 arg0 = TREE_VALUE (arglist);
12607 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12608 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
12609 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12610 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12611 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
12612 tmode = insn_data[icode].operand[0].mode;
12613 mode0 = insn_data[icode].operand[1].mode;
12614 mode1 = insn_data[icode].operand[2].mode;
12615 mode2 = insn_data[icode].operand[3].mode;
12617 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12618 op0 = copy_to_mode_reg (mode0, op0);
12619 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
12620 op1 = copy_to_mode_reg (mode1, op1);
12621 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
12623 /* @@@ better error message */
12624 error ("selector must be an immediate");
12628 || GET_MODE (target) != tmode
12629 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12630 target = gen_reg_rtx (tmode);
12631 pat = GEN_FCN (icode) (target, op0, op1, op2);
12637 case ARM_BUILTIN_SETWCX:
12638 arg0 = TREE_VALUE (arglist);
12639 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12640 op0 = force_reg (SImode, expand_expr (arg0, NULL_RTX, VOIDmode, 0));
12641 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12642 emit_insn (gen_iwmmxt_tmcr (op1, op0));
12645 case ARM_BUILTIN_GETWCX:
12646 arg0 = TREE_VALUE (arglist);
12647 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12648 target = gen_reg_rtx (SImode);
12649 emit_insn (gen_iwmmxt_tmrc (target, op0));
12652 case ARM_BUILTIN_WSHUFH:
12653 icode = CODE_FOR_iwmmxt_wshufh;
12654 arg0 = TREE_VALUE (arglist);
12655 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12656 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12657 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12658 tmode = insn_data[icode].operand[0].mode;
12659 mode1 = insn_data[icode].operand[1].mode;
12660 mode2 = insn_data[icode].operand[2].mode;
12662 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
12663 op0 = copy_to_mode_reg (mode1, op0);
12664 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
12666 /* @@@ better error message */
12667 error ("mask must be an immediate");
12671 || GET_MODE (target) != tmode
12672 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12673 target = gen_reg_rtx (tmode);
12674 pat = GEN_FCN (icode) (target, op0, op1);
12680 case ARM_BUILTIN_WSADB:
12681 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadb, arglist, target);
12682 case ARM_BUILTIN_WSADH:
12683 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadh, arglist, target);
12684 case ARM_BUILTIN_WSADBZ:
12685 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadbz, arglist, target);
12686 case ARM_BUILTIN_WSADHZ:
12687 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadhz, arglist, target);
12689 /* Several three-argument builtins. */
12690 case ARM_BUILTIN_WMACS:
12691 case ARM_BUILTIN_WMACU:
12692 case ARM_BUILTIN_WALIGN:
12693 case ARM_BUILTIN_TMIA:
12694 case ARM_BUILTIN_TMIAPH:
12695 case ARM_BUILTIN_TMIATT:
12696 case ARM_BUILTIN_TMIATB:
12697 case ARM_BUILTIN_TMIABT:
12698 case ARM_BUILTIN_TMIABB:
12699 icode = (fcode == ARM_BUILTIN_WMACS ? CODE_FOR_iwmmxt_wmacs
12700 : fcode == ARM_BUILTIN_WMACU ? CODE_FOR_iwmmxt_wmacu
12701 : fcode == ARM_BUILTIN_TMIA ? CODE_FOR_iwmmxt_tmia
12702 : fcode == ARM_BUILTIN_TMIAPH ? CODE_FOR_iwmmxt_tmiaph
12703 : fcode == ARM_BUILTIN_TMIABB ? CODE_FOR_iwmmxt_tmiabb
12704 : fcode == ARM_BUILTIN_TMIABT ? CODE_FOR_iwmmxt_tmiabt
12705 : fcode == ARM_BUILTIN_TMIATB ? CODE_FOR_iwmmxt_tmiatb
12706 : fcode == ARM_BUILTIN_TMIATT ? CODE_FOR_iwmmxt_tmiatt
12707 : CODE_FOR_iwmmxt_walign);
12708 arg0 = TREE_VALUE (arglist);
12709 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12710 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
12711 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12712 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12713 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
12714 tmode = insn_data[icode].operand[0].mode;
12715 mode0 = insn_data[icode].operand[1].mode;
12716 mode1 = insn_data[icode].operand[2].mode;
12717 mode2 = insn_data[icode].operand[3].mode;
12719 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12720 op0 = copy_to_mode_reg (mode0, op0);
12721 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
12722 op1 = copy_to_mode_reg (mode1, op1);
12723 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
12724 op2 = copy_to_mode_reg (mode2, op2);
12726 || GET_MODE (target) != tmode
12727 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12728 target = gen_reg_rtx (tmode);
12729 pat = GEN_FCN (icode) (target, op0, op1, op2);
12735 case ARM_BUILTIN_WZERO:
12736 target = gen_reg_rtx (DImode);
12737 emit_insn (gen_iwmmxt_clrdi (target));
12744 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
12745 if (d->code == (const enum arm_builtins) fcode)
12746 return arm_expand_binop_builtin (d->icode, arglist, target);
12748 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
12749 if (d->code == (const enum arm_builtins) fcode)
12750 return arm_expand_unop_builtin (d->icode, arglist, target, 0);
12752 /* @@@ Should really do something sensible here. */
12756 /* Recursively search through all of the blocks in a function
12757 checking to see if any of the variables created in that
12758 function match the RTX called 'orig'. If they do then
12759 replace them with the RTX called 'new'. */
12761 replace_symbols_in_block (tree block, rtx orig, rtx new)
12763 for (; block; block = BLOCK_CHAIN (block))
12767 if (!TREE_USED (block))
12770 for (sym = BLOCK_VARS (block); sym; sym = TREE_CHAIN (sym))
12772 if ( (DECL_NAME (sym) == 0 && TREE_CODE (sym) != TYPE_DECL)
12773 || DECL_IGNORED_P (sym)
12774 || TREE_CODE (sym) != VAR_DECL
12775 || DECL_EXTERNAL (sym)
12776 || !rtx_equal_p (DECL_RTL (sym), orig)
12780 SET_DECL_RTL (sym, new);
12783 replace_symbols_in_block (BLOCK_SUBBLOCKS (block), orig, new);
12787 /* Return the number (counting from 0) of
12788 the least significant set bit in MASK. */
12791 number_of_first_bit_set (int mask)
12796 (mask & (1 << bit)) == 0;
12803 /* Generate code to return from a thumb function.
12804 If 'reg_containing_return_addr' is -1, then the return address is
12805 actually on the stack, at the stack pointer. */
12807 thumb_exit (FILE *f, int reg_containing_return_addr)
12809 unsigned regs_available_for_popping;
12810 unsigned regs_to_pop;
12812 unsigned available;
12816 int restore_a4 = FALSE;
12818 /* Compute the registers we need to pop. */
12822 if (reg_containing_return_addr == -1)
12824 regs_to_pop |= 1 << LR_REGNUM;
12828 if (TARGET_BACKTRACE)
12830 /* Restore the (ARM) frame pointer and stack pointer. */
12831 regs_to_pop |= (1 << ARM_HARD_FRAME_POINTER_REGNUM) | (1 << SP_REGNUM);
12835 /* If there is nothing to pop then just emit the BX instruction and
12837 if (pops_needed == 0)
12839 if (current_function_calls_eh_return)
12840 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, ARM_EH_STACKADJ_REGNUM);
12842 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
12845 /* Otherwise if we are not supporting interworking and we have not created
12846 a backtrace structure and the function was not entered in ARM mode then
12847 just pop the return address straight into the PC. */
12848 else if (!TARGET_INTERWORK
12849 && !TARGET_BACKTRACE
12850 && !is_called_in_ARM_mode (current_function_decl)
12851 && !current_function_calls_eh_return)
12853 asm_fprintf (f, "\tpop\t{%r}\n", PC_REGNUM);
12857 /* Find out how many of the (return) argument registers we can corrupt. */
12858 regs_available_for_popping = 0;
12860 /* If returning via __builtin_eh_return, the bottom three registers
12861 all contain information needed for the return. */
12862 if (current_function_calls_eh_return)
12866 /* If we can deduce the registers used from the function's
12867 return value. This is more reliable that examining
12868 regs_ever_live[] because that will be set if the register is
12869 ever used in the function, not just if the register is used
12870 to hold a return value. */
12872 if (current_function_return_rtx != 0)
12873 mode = GET_MODE (current_function_return_rtx);
12875 mode = DECL_MODE (DECL_RESULT (current_function_decl));
12877 size = GET_MODE_SIZE (mode);
12881 /* In a void function we can use any argument register.
12882 In a function that returns a structure on the stack
12883 we can use the second and third argument registers. */
12884 if (mode == VOIDmode)
12885 regs_available_for_popping =
12886 (1 << ARG_REGISTER (1))
12887 | (1 << ARG_REGISTER (2))
12888 | (1 << ARG_REGISTER (3));
12890 regs_available_for_popping =
12891 (1 << ARG_REGISTER (2))
12892 | (1 << ARG_REGISTER (3));
12894 else if (size <= 4)
12895 regs_available_for_popping =
12896 (1 << ARG_REGISTER (2))
12897 | (1 << ARG_REGISTER (3));
12898 else if (size <= 8)
12899 regs_available_for_popping =
12900 (1 << ARG_REGISTER (3));
12903 /* Match registers to be popped with registers into which we pop them. */
12904 for (available = regs_available_for_popping,
12905 required = regs_to_pop;
12906 required != 0 && available != 0;
12907 available &= ~(available & - available),
12908 required &= ~(required & - required))
12911 /* If we have any popping registers left over, remove them. */
12913 regs_available_for_popping &= ~available;
12915 /* Otherwise if we need another popping register we can use
12916 the fourth argument register. */
12917 else if (pops_needed)
12919 /* If we have not found any free argument registers and
12920 reg a4 contains the return address, we must move it. */
12921 if (regs_available_for_popping == 0
12922 && reg_containing_return_addr == LAST_ARG_REGNUM)
12924 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
12925 reg_containing_return_addr = LR_REGNUM;
12927 else if (size > 12)
12929 /* Register a4 is being used to hold part of the return value,
12930 but we have dire need of a free, low register. */
12933 asm_fprintf (f, "\tmov\t%r, %r\n",IP_REGNUM, LAST_ARG_REGNUM);
12936 if (reg_containing_return_addr != LAST_ARG_REGNUM)
12938 /* The fourth argument register is available. */
12939 regs_available_for_popping |= 1 << LAST_ARG_REGNUM;
12945 /* Pop as many registers as we can. */
12946 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
12947 regs_available_for_popping);
12949 /* Process the registers we popped. */
12950 if (reg_containing_return_addr == -1)
12952 /* The return address was popped into the lowest numbered register. */
12953 regs_to_pop &= ~(1 << LR_REGNUM);
12955 reg_containing_return_addr =
12956 number_of_first_bit_set (regs_available_for_popping);
12958 /* Remove this register for the mask of available registers, so that
12959 the return address will not be corrupted by further pops. */
12960 regs_available_for_popping &= ~(1 << reg_containing_return_addr);
12963 /* If we popped other registers then handle them here. */
12964 if (regs_available_for_popping)
12968 /* Work out which register currently contains the frame pointer. */
12969 frame_pointer = number_of_first_bit_set (regs_available_for_popping);
12971 /* Move it into the correct place. */
12972 asm_fprintf (f, "\tmov\t%r, %r\n",
12973 ARM_HARD_FRAME_POINTER_REGNUM, frame_pointer);
12975 /* (Temporarily) remove it from the mask of popped registers. */
12976 regs_available_for_popping &= ~(1 << frame_pointer);
12977 regs_to_pop &= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM);
12979 if (regs_available_for_popping)
12983 /* We popped the stack pointer as well,
12984 find the register that contains it. */
12985 stack_pointer = number_of_first_bit_set (regs_available_for_popping);
12987 /* Move it into the stack register. */
12988 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, stack_pointer);
12990 /* At this point we have popped all necessary registers, so
12991 do not worry about restoring regs_available_for_popping
12992 to its correct value:
12994 assert (pops_needed == 0)
12995 assert (regs_available_for_popping == (1 << frame_pointer))
12996 assert (regs_to_pop == (1 << STACK_POINTER)) */
13000 /* Since we have just move the popped value into the frame
13001 pointer, the popping register is available for reuse, and
13002 we know that we still have the stack pointer left to pop. */
13003 regs_available_for_popping |= (1 << frame_pointer);
13007 /* If we still have registers left on the stack, but we no longer have
13008 any registers into which we can pop them, then we must move the return
13009 address into the link register and make available the register that
13011 if (regs_available_for_popping == 0 && pops_needed > 0)
13013 regs_available_for_popping |= 1 << reg_containing_return_addr;
13015 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM,
13016 reg_containing_return_addr);
13018 reg_containing_return_addr = LR_REGNUM;
13021 /* If we have registers left on the stack then pop some more.
13022 We know that at most we will want to pop FP and SP. */
13023 if (pops_needed > 0)
13028 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
13029 regs_available_for_popping);
13031 /* We have popped either FP or SP.
13032 Move whichever one it is into the correct register. */
13033 popped_into = number_of_first_bit_set (regs_available_for_popping);
13034 move_to = number_of_first_bit_set (regs_to_pop);
13036 asm_fprintf (f, "\tmov\t%r, %r\n", move_to, popped_into);
13038 regs_to_pop &= ~(1 << move_to);
13043 /* If we still have not popped everything then we must have only
13044 had one register available to us and we are now popping the SP. */
13045 if (pops_needed > 0)
13049 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
13050 regs_available_for_popping);
13052 popped_into = number_of_first_bit_set (regs_available_for_popping);
13054 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, popped_into);
13056 assert (regs_to_pop == (1 << STACK_POINTER))
13057 assert (pops_needed == 1)
13061 /* If necessary restore the a4 register. */
13064 if (reg_containing_return_addr != LR_REGNUM)
13066 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
13067 reg_containing_return_addr = LR_REGNUM;
13070 asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM);
13073 if (current_function_calls_eh_return)
13074 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, ARM_EH_STACKADJ_REGNUM);
13076 /* Return to caller. */
13077 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
13080 /* Emit code to push or pop registers to or from the stack. F is the
13081 assembly file. MASK is the registers to push or pop. PUSH is
13082 nonzero if we should push, and zero if we should pop. For debugging
13083 output, if pushing, adjust CFA_OFFSET by the amount of space added
13084 to the stack. REAL_REGS should have the same number of bits set as
13085 MASK, and will be used instead (in the same order) to describe which
13086 registers were saved - this is used to mark the save slots when we
13087 push high registers after moving them to low registers. */
13089 thumb_pushpop (FILE *f, int mask, int push, int *cfa_offset, int real_regs)
13092 int lo_mask = mask & 0xFF;
13093 int pushed_words = 0;
13095 if (lo_mask == 0 && !push && (mask & (1 << PC_REGNUM)))
13097 /* Special case. Do not generate a POP PC statement here, do it in
13099 thumb_exit (f, -1);
13103 fprintf (f, "\t%s\t{", push ? "push" : "pop");
13105 /* Look at the low registers first. */
13106 for (regno = 0; regno <= LAST_LO_REGNUM; regno++, lo_mask >>= 1)
13110 asm_fprintf (f, "%r", regno);
13112 if ((lo_mask & ~1) != 0)
13119 if (push && (mask & (1 << LR_REGNUM)))
13121 /* Catch pushing the LR. */
13125 asm_fprintf (f, "%r", LR_REGNUM);
13129 else if (!push && (mask & (1 << PC_REGNUM)))
13131 /* Catch popping the PC. */
13132 if (TARGET_INTERWORK || TARGET_BACKTRACE
13133 || current_function_calls_eh_return)
13135 /* The PC is never poped directly, instead
13136 it is popped into r3 and then BX is used. */
13137 fprintf (f, "}\n");
13139 thumb_exit (f, -1);
13148 asm_fprintf (f, "%r", PC_REGNUM);
13152 fprintf (f, "}\n");
13154 if (push && pushed_words && dwarf2out_do_frame ())
13156 char *l = dwarf2out_cfi_label ();
13157 int pushed_mask = real_regs;
13159 *cfa_offset += pushed_words * 4;
13160 dwarf2out_def_cfa (l, SP_REGNUM, *cfa_offset);
13163 pushed_mask = real_regs;
13164 for (regno = 0; regno <= 14; regno++, pushed_mask >>= 1)
13166 if (pushed_mask & 1)
13167 dwarf2out_reg_save (l, regno, 4 * pushed_words++ - *cfa_offset);
13173 thumb_final_prescan_insn (rtx insn)
13175 if (flag_print_asm_name)
13176 asm_fprintf (asm_out_file, "%@ 0x%04x\n",
13177 INSN_ADDRESSES (INSN_UID (insn)));
13181 thumb_shiftable_const (unsigned HOST_WIDE_INT val)
13183 unsigned HOST_WIDE_INT mask = 0xff;
13186 if (val == 0) /* XXX */
13189 for (i = 0; i < 25; i++)
13190 if ((val & (mask << i)) == val)
13196 /* Returns nonzero if the current function contains,
13197 or might contain a far jump. */
13199 thumb_far_jump_used_p (void)
13203 /* This test is only important for leaf functions. */
13204 /* assert (!leaf_function_p ()); */
13206 /* If we have already decided that far jumps may be used,
13207 do not bother checking again, and always return true even if
13208 it turns out that they are not being used. Once we have made
13209 the decision that far jumps are present (and that hence the link
13210 register will be pushed onto the stack) we cannot go back on it. */
13211 if (cfun->machine->far_jump_used)
13214 /* If this function is not being called from the prologue/epilogue
13215 generation code then it must be being called from the
13216 INITIAL_ELIMINATION_OFFSET macro. */
13217 if (!(ARM_DOUBLEWORD_ALIGN || reload_completed))
13219 /* In this case we know that we are being asked about the elimination
13220 of the arg pointer register. If that register is not being used,
13221 then there are no arguments on the stack, and we do not have to
13222 worry that a far jump might force the prologue to push the link
13223 register, changing the stack offsets. In this case we can just
13224 return false, since the presence of far jumps in the function will
13225 not affect stack offsets.
13227 If the arg pointer is live (or if it was live, but has now been
13228 eliminated and so set to dead) then we do have to test to see if
13229 the function might contain a far jump. This test can lead to some
13230 false negatives, since before reload is completed, then length of
13231 branch instructions is not known, so gcc defaults to returning their
13232 longest length, which in turn sets the far jump attribute to true.
13234 A false negative will not result in bad code being generated, but it
13235 will result in a needless push and pop of the link register. We
13236 hope that this does not occur too often.
13238 If we need doubleword stack alignment this could affect the other
13239 elimination offsets so we can't risk getting it wrong. */
13240 if (regs_ever_live [ARG_POINTER_REGNUM])
13241 cfun->machine->arg_pointer_live = 1;
13242 else if (!cfun->machine->arg_pointer_live)
13246 /* Check to see if the function contains a branch
13247 insn with the far jump attribute set. */
13248 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
13250 if (GET_CODE (insn) == JUMP_INSN
13251 /* Ignore tablejump patterns. */
13252 && GET_CODE (PATTERN (insn)) != ADDR_VEC
13253 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
13254 && get_attr_far_jump (insn) == FAR_JUMP_YES
13257 /* Record the fact that we have decided that
13258 the function does use far jumps. */
13259 cfun->machine->far_jump_used = 1;
13267 /* Return nonzero if FUNC must be entered in ARM mode. */
13269 is_called_in_ARM_mode (tree func)
13271 if (TREE_CODE (func) != FUNCTION_DECL)
13274 /* Ignore the problem about functions whoes address is taken. */
13275 if (TARGET_CALLEE_INTERWORKING && TREE_PUBLIC (func))
13279 return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func)) != NULL_TREE;
13285 /* The bits which aren't usefully expanded as rtl. */
13287 thumb_unexpanded_epilogue (void)
13290 int live_regs_mask = 0;
13291 int high_regs_pushed = 0;
13292 int had_to_push_lr;
13296 if (return_used_this_function)
13299 if (IS_NAKED (arm_current_func_type ()))
13302 live_regs_mask = thumb_compute_save_reg_mask ();
13303 high_regs_pushed = bit_count (live_regs_mask & 0x0f00);
13305 /* If we can deduce the registers used from the function's return value.
13306 This is more reliable that examining regs_ever_live[] because that
13307 will be set if the register is ever used in the function, not just if
13308 the register is used to hold a return value. */
13310 if (current_function_return_rtx != 0)
13311 mode = GET_MODE (current_function_return_rtx);
13313 mode = DECL_MODE (DECL_RESULT (current_function_decl));
13315 size = GET_MODE_SIZE (mode);
13317 /* The prolog may have pushed some high registers to use as
13318 work registers. eg the testsuite file:
13319 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
13320 compiles to produce:
13321 push {r4, r5, r6, r7, lr}
13325 as part of the prolog. We have to undo that pushing here. */
13327 if (high_regs_pushed)
13329 int mask = live_regs_mask & 0xff;
13332 /* The available low registers depend on the size of the value we are
13340 /* Oh dear! We have no low registers into which we can pop
13343 ("no low registers available for popping high registers");
13345 for (next_hi_reg = 8; next_hi_reg < 13; next_hi_reg++)
13346 if (live_regs_mask & (1 << next_hi_reg))
13349 while (high_regs_pushed)
13351 /* Find lo register(s) into which the high register(s) can
13353 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
13355 if (mask & (1 << regno))
13356 high_regs_pushed--;
13357 if (high_regs_pushed == 0)
13361 mask &= (2 << regno) - 1; /* A noop if regno == 8 */
13363 /* Pop the values into the low register(s). */
13364 thumb_pushpop (asm_out_file, mask, 0, NULL, mask);
13366 /* Move the value(s) into the high registers. */
13367 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
13369 if (mask & (1 << regno))
13371 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", next_hi_reg,
13374 for (next_hi_reg++; next_hi_reg < 13; next_hi_reg++)
13375 if (live_regs_mask & (1 << next_hi_reg))
13380 live_regs_mask &= ~0x0f00;
13383 had_to_push_lr = (live_regs_mask & (1 << LR_REGNUM)) != 0;
13384 live_regs_mask &= 0xff;
13386 if (current_function_pretend_args_size == 0 || TARGET_BACKTRACE)
13388 /* Pop the return address into the PC. */
13389 if (had_to_push_lr)
13390 live_regs_mask |= 1 << PC_REGNUM;
13392 /* Either no argument registers were pushed or a backtrace
13393 structure was created which includes an adjusted stack
13394 pointer, so just pop everything. */
13395 if (live_regs_mask)
13396 thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL,
13399 /* We have either just popped the return address into the
13400 PC or it is was kept in LR for the entire function. */
13401 if (!had_to_push_lr)
13402 thumb_exit (asm_out_file, LR_REGNUM);
13406 /* Pop everything but the return address. */
13407 if (live_regs_mask)
13408 thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL,
13411 if (had_to_push_lr)
13415 /* We have no free low regs, so save one. */
13416 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", IP_REGNUM,
13420 /* Get the return address into a temporary register. */
13421 thumb_pushpop (asm_out_file, 1 << LAST_ARG_REGNUM, 0, NULL,
13422 1 << LAST_ARG_REGNUM);
13426 /* Move the return address to lr. */
13427 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", LR_REGNUM,
13429 /* Restore the low register. */
13430 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", LAST_ARG_REGNUM,
13435 regno = LAST_ARG_REGNUM;
13440 /* Remove the argument registers that were pushed onto the stack. */
13441 asm_fprintf (asm_out_file, "\tadd\t%r, %r, #%d\n",
13442 SP_REGNUM, SP_REGNUM,
13443 current_function_pretend_args_size);
13445 thumb_exit (asm_out_file, regno);
13451 /* Functions to save and restore machine-specific function data. */
13452 static struct machine_function *
13453 arm_init_machine_status (void)
13455 struct machine_function *machine;
13456 machine = (machine_function *) ggc_alloc_cleared (sizeof (machine_function));
13458 #if ARM_FT_UNKNOWN != 0
13459 machine->func_type = ARM_FT_UNKNOWN;
13464 /* Return an RTX indicating where the return address to the
13465 calling function can be found. */
13467 arm_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
13472 return get_hard_reg_initial_val (Pmode, LR_REGNUM);
13475 /* Do anything needed before RTL is emitted for each function. */
13477 arm_init_expanders (void)
13479 /* Arrange to initialize and mark the machine per-function status. */
13480 init_machine_status = arm_init_machine_status;
13482 /* This is to stop the combine pass optimizing away the alignment
13483 adjustment of va_arg. */
13484 /* ??? It is claimed that this should not be necessary. */
13486 mark_reg_pointer (arg_pointer_rtx, PARM_BOUNDARY);
13490 /* Like arm_compute_initial_elimination offset. Simpler because
13491 THUMB_HARD_FRAME_POINTER isn't actually the ABI specified frame pointer. */
13494 thumb_compute_initial_elimination_offset (unsigned int from, unsigned int to)
13496 arm_stack_offsets *offsets;
13498 offsets = arm_get_frame_offsets ();
13502 case ARG_POINTER_REGNUM:
13505 case STACK_POINTER_REGNUM:
13506 return offsets->outgoing_args - offsets->saved_args;
13508 case FRAME_POINTER_REGNUM:
13509 return offsets->soft_frame - offsets->saved_args;
13511 case THUMB_HARD_FRAME_POINTER_REGNUM:
13512 case ARM_HARD_FRAME_POINTER_REGNUM:
13513 return offsets->saved_regs - offsets->saved_args;
13520 case FRAME_POINTER_REGNUM:
13523 case STACK_POINTER_REGNUM:
13524 return offsets->outgoing_args - offsets->soft_frame;
13526 case THUMB_HARD_FRAME_POINTER_REGNUM:
13527 case ARM_HARD_FRAME_POINTER_REGNUM:
13528 return offsets->saved_regs - offsets->soft_frame;
13541 /* Generate the rest of a function's prologue. */
13543 thumb_expand_prologue (void)
13547 HOST_WIDE_INT amount;
13548 arm_stack_offsets *offsets;
13549 unsigned long func_type;
13551 unsigned long live_regs_mask;
13553 func_type = arm_current_func_type ();
13555 /* Naked functions don't have prologues. */
13556 if (IS_NAKED (func_type))
13559 if (IS_INTERRUPT (func_type))
13561 error ("interrupt Service Routines cannot be coded in Thumb mode");
13565 /* Load the pic recister before setting the frame pointer, so we can use r7
13566 as a temporary work register. */
13568 arm_load_pic_register ();
13570 offsets = arm_get_frame_offsets ();
13572 if (frame_pointer_needed)
13574 insn = emit_insn (gen_movsi (hard_frame_pointer_rtx,
13575 stack_pointer_rtx));
13576 RTX_FRAME_RELATED_P (insn) = 1;
13579 live_regs_mask = thumb_compute_save_reg_mask ();
13580 amount = offsets->outgoing_args - offsets->saved_regs;
13585 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
13586 GEN_INT (- amount)));
13587 RTX_FRAME_RELATED_P (insn) = 1;
13593 /* The stack decrement is too big for an immediate value in a single
13594 insn. In theory we could issue multiple subtracts, but after
13595 three of them it becomes more space efficient to place the full
13596 value in the constant pool and load into a register. (Also the
13597 ARM debugger really likes to see only one stack decrement per
13598 function). So instead we look for a scratch register into which
13599 we can load the decrement, and then we subtract this from the
13600 stack pointer. Unfortunately on the thumb the only available
13601 scratch registers are the argument registers, and we cannot use
13602 these as they may hold arguments to the function. Instead we
13603 attempt to locate a call preserved register which is used by this
13604 function. If we can find one, then we know that it will have
13605 been pushed at the start of the prologue and so we can corrupt
13607 for (regno = LAST_ARG_REGNUM + 1; regno <= LAST_LO_REGNUM; regno++)
13608 if (live_regs_mask & (1 << regno)
13609 && !(frame_pointer_needed
13610 && (regno == THUMB_HARD_FRAME_POINTER_REGNUM)))
13613 if (regno > LAST_LO_REGNUM) /* Very unlikely. */
13615 rtx spare = gen_rtx_REG (SImode, IP_REGNUM);
13617 /* Choose an arbitrary, non-argument low register. */
13618 reg = gen_rtx_REG (SImode, LAST_LO_REGNUM);
13620 /* Save it by copying it into a high, scratch register. */
13621 emit_insn (gen_movsi (spare, reg));
13622 /* Add a USE to stop propagate_one_insn() from barfing. */
13623 emit_insn (gen_prologue_use (spare));
13625 /* Decrement the stack. */
13626 emit_insn (gen_movsi (reg, GEN_INT (- amount)));
13627 insn = emit_insn (gen_addsi3 (stack_pointer_rtx,
13628 stack_pointer_rtx, reg));
13629 RTX_FRAME_RELATED_P (insn) = 1;
13630 dwarf = gen_rtx_SET (SImode, stack_pointer_rtx,
13631 plus_constant (stack_pointer_rtx,
13633 RTX_FRAME_RELATED_P (dwarf) = 1;
13635 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
13638 /* Restore the low register's original value. */
13639 emit_insn (gen_movsi (reg, spare));
13641 /* Emit a USE of the restored scratch register, so that flow
13642 analysis will not consider the restore redundant. The
13643 register won't be used again in this function and isn't
13644 restored by the epilogue. */
13645 emit_insn (gen_prologue_use (reg));
13649 reg = gen_rtx_REG (SImode, regno);
13651 emit_insn (gen_movsi (reg, GEN_INT (- amount)));
13653 insn = emit_insn (gen_addsi3 (stack_pointer_rtx,
13654 stack_pointer_rtx, reg));
13655 RTX_FRAME_RELATED_P (insn) = 1;
13656 dwarf = gen_rtx_SET (SImode, stack_pointer_rtx,
13657 plus_constant (stack_pointer_rtx,
13659 RTX_FRAME_RELATED_P (dwarf) = 1;
13661 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
13665 /* If the frame pointer is needed, emit a special barrier that
13666 will prevent the scheduler from moving stores to the frame
13667 before the stack adjustment. */
13668 if (frame_pointer_needed)
13669 emit_insn (gen_stack_tie (stack_pointer_rtx,
13670 hard_frame_pointer_rtx));
13673 if (current_function_profile || TARGET_NO_SCHED_PRO)
13674 emit_insn (gen_blockage ());
13676 cfun->machine->lr_save_eliminated = !thumb_force_lr_save ();
13677 if (live_regs_mask & 0xff)
13678 cfun->machine->lr_save_eliminated = 0;
13680 /* If the link register is being kept alive, with the return address in it,
13681 then make sure that it does not get reused by the ce2 pass. */
13682 if (cfun->machine->lr_save_eliminated)
13683 emit_insn (gen_prologue_use (gen_rtx_REG (SImode, LR_REGNUM)));
13688 thumb_expand_epilogue (void)
13690 HOST_WIDE_INT amount;
13691 arm_stack_offsets *offsets;
13694 /* Naked functions don't have prologues. */
13695 if (IS_NAKED (arm_current_func_type ()))
13698 offsets = arm_get_frame_offsets ();
13699 amount = offsets->outgoing_args - offsets->saved_regs;
13701 if (frame_pointer_needed)
13702 emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx));
13706 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
13707 GEN_INT (amount)));
13710 /* r3 is always free in the epilogue. */
13711 rtx reg = gen_rtx_REG (SImode, LAST_ARG_REGNUM);
13713 emit_insn (gen_movsi (reg, GEN_INT (amount)));
13714 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, reg));
13718 /* Emit a USE (stack_pointer_rtx), so that
13719 the stack adjustment will not be deleted. */
13720 emit_insn (gen_prologue_use (stack_pointer_rtx));
13722 if (current_function_profile || TARGET_NO_SCHED_PRO)
13723 emit_insn (gen_blockage ());
13725 /* Emit a clobber for each insn that will be restored in the epilogue,
13726 so that flow2 will get register lifetimes correct. */
13727 for (regno = 0; regno < 13; regno++)
13728 if (regs_ever_live[regno] && !call_used_regs[regno])
13729 emit_insn (gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, regno)));
13731 if (! regs_ever_live[LR_REGNUM])
13732 emit_insn (gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, LR_REGNUM)));
13736 thumb_output_function_prologue (FILE *f, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
13738 int live_regs_mask = 0;
13740 int high_regs_pushed = 0;
13741 int cfa_offset = 0;
13744 if (IS_NAKED (arm_current_func_type ()))
13747 if (is_called_in_ARM_mode (current_function_decl))
13751 if (GET_CODE (DECL_RTL (current_function_decl)) != MEM)
13753 if (GET_CODE (XEXP (DECL_RTL (current_function_decl), 0)) != SYMBOL_REF)
13755 name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
13757 /* Generate code sequence to switch us into Thumb mode. */
13758 /* The .code 32 directive has already been emitted by
13759 ASM_DECLARE_FUNCTION_NAME. */
13760 asm_fprintf (f, "\torr\t%r, %r, #1\n", IP_REGNUM, PC_REGNUM);
13761 asm_fprintf (f, "\tbx\t%r\n", IP_REGNUM);
13763 /* Generate a label, so that the debugger will notice the
13764 change in instruction sets. This label is also used by
13765 the assembler to bypass the ARM code when this function
13766 is called from a Thumb encoded function elsewhere in the
13767 same file. Hence the definition of STUB_NAME here must
13768 agree with the definition in gas/config/tc-arm.c. */
13770 #define STUB_NAME ".real_start_of"
13772 fprintf (f, "\t.code\t16\n");
13774 if (arm_dllexport_name_p (name))
13775 name = arm_strip_name_encoding (name);
13777 asm_fprintf (f, "\t.globl %s%U%s\n", STUB_NAME, name);
13778 fprintf (f, "\t.thumb_func\n");
13779 asm_fprintf (f, "%s%U%s:\n", STUB_NAME, name);
13782 if (current_function_pretend_args_size)
13784 if (cfun->machine->uses_anonymous_args)
13788 fprintf (f, "\tpush\t{");
13790 num_pushes = ARM_NUM_INTS (current_function_pretend_args_size);
13792 for (regno = LAST_ARG_REGNUM + 1 - num_pushes;
13793 regno <= LAST_ARG_REGNUM;
13795 asm_fprintf (f, "%r%s", regno,
13796 regno == LAST_ARG_REGNUM ? "" : ", ");
13798 fprintf (f, "}\n");
13801 asm_fprintf (f, "\tsub\t%r, %r, #%d\n",
13802 SP_REGNUM, SP_REGNUM,
13803 current_function_pretend_args_size);
13805 /* We don't need to record the stores for unwinding (would it
13806 help the debugger any if we did?), but record the change in
13807 the stack pointer. */
13808 if (dwarf2out_do_frame ())
13810 char *l = dwarf2out_cfi_label ();
13811 cfa_offset = cfa_offset + current_function_pretend_args_size;
13812 dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset);
13816 live_regs_mask = thumb_compute_save_reg_mask ();
13817 /* Just low regs and lr. */
13818 l_mask = live_regs_mask & 0x40ff;
13820 if (TARGET_BACKTRACE)
13825 /* We have been asked to create a stack backtrace structure.
13826 The code looks like this:
13830 0 sub SP, #16 Reserve space for 4 registers.
13831 2 push {R7} Push low registers.
13832 4 add R7, SP, #20 Get the stack pointer before the push.
13833 6 str R7, [SP, #8] Store the stack pointer (before reserving the space).
13834 8 mov R7, PC Get hold of the start of this code plus 12.
13835 10 str R7, [SP, #16] Store it.
13836 12 mov R7, FP Get hold of the current frame pointer.
13837 14 str R7, [SP, #4] Store it.
13838 16 mov R7, LR Get hold of the current return address.
13839 18 str R7, [SP, #12] Store it.
13840 20 add R7, SP, #16 Point at the start of the backtrace structure.
13841 22 mov FP, R7 Put this value into the frame pointer. */
13843 work_register = thumb_find_work_register (live_regs_mask);
13846 (f, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n",
13847 SP_REGNUM, SP_REGNUM);
13849 if (dwarf2out_do_frame ())
13851 char *l = dwarf2out_cfi_label ();
13852 cfa_offset = cfa_offset + 16;
13853 dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset);
13858 thumb_pushpop (f, l_mask, 1, &cfa_offset, l_mask);
13859 offset = bit_count (l_mask);
13864 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
13865 offset + 16 + current_function_pretend_args_size);
13867 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13870 /* Make sure that the instruction fetching the PC is in the right place
13871 to calculate "start of backtrace creation code + 12". */
13874 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
13875 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13877 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
13878 ARM_HARD_FRAME_POINTER_REGNUM);
13879 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13884 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
13885 ARM_HARD_FRAME_POINTER_REGNUM);
13886 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13888 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
13889 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13893 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, LR_REGNUM);
13894 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13896 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
13898 asm_fprintf (f, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n",
13899 ARM_HARD_FRAME_POINTER_REGNUM, work_register);
13902 thumb_pushpop (f, l_mask, 1, &cfa_offset, l_mask);
13904 high_regs_pushed = bit_count (live_regs_mask & 0x0f00);
13906 if (high_regs_pushed)
13908 int pushable_regs = 0;
13911 for (next_hi_reg = 12; next_hi_reg > LAST_LO_REGNUM; next_hi_reg--)
13912 if (live_regs_mask & (1 << next_hi_reg))
13915 pushable_regs = l_mask & 0xff;
13917 if (pushable_regs == 0)
13918 pushable_regs = 1 << thumb_find_work_register (live_regs_mask);
13920 while (high_regs_pushed > 0)
13922 int real_regs_mask = 0;
13924 for (regno = LAST_LO_REGNUM; regno >= 0; regno--)
13926 if (pushable_regs & (1 << regno))
13928 asm_fprintf (f, "\tmov\t%r, %r\n", regno, next_hi_reg);
13930 high_regs_pushed--;
13931 real_regs_mask |= (1 << next_hi_reg);
13933 if (high_regs_pushed)
13935 for (next_hi_reg--; next_hi_reg > LAST_LO_REGNUM;
13937 if (live_regs_mask & (1 << next_hi_reg))
13942 pushable_regs &= ~((1 << regno) - 1);
13948 thumb_pushpop (f, pushable_regs, 1, &cfa_offset, real_regs_mask);
13953 /* Handle the case of a double word load into a low register from
13954 a computed memory address. The computed address may involve a
13955 register which is overwritten by the load. */
13957 thumb_load_double_from_address (rtx *operands)
13965 if (GET_CODE (operands[0]) != REG)
13968 if (GET_CODE (operands[1]) != MEM)
13971 /* Get the memory address. */
13972 addr = XEXP (operands[1], 0);
13974 /* Work out how the memory address is computed. */
13975 switch (GET_CODE (addr))
13978 operands[2] = gen_rtx_MEM (SImode,
13979 plus_constant (XEXP (operands[1], 0), 4));
13981 if (REGNO (operands[0]) == REGNO (addr))
13983 output_asm_insn ("ldr\t%H0, %2", operands);
13984 output_asm_insn ("ldr\t%0, %1", operands);
13988 output_asm_insn ("ldr\t%0, %1", operands);
13989 output_asm_insn ("ldr\t%H0, %2", operands);
13994 /* Compute <address> + 4 for the high order load. */
13995 operands[2] = gen_rtx_MEM (SImode,
13996 plus_constant (XEXP (operands[1], 0), 4));
13998 output_asm_insn ("ldr\t%0, %1", operands);
13999 output_asm_insn ("ldr\t%H0, %2", operands);
14003 arg1 = XEXP (addr, 0);
14004 arg2 = XEXP (addr, 1);
14006 if (CONSTANT_P (arg1))
14007 base = arg2, offset = arg1;
14009 base = arg1, offset = arg2;
14011 if (GET_CODE (base) != REG)
14014 /* Catch the case of <address> = <reg> + <reg> */
14015 if (GET_CODE (offset) == REG)
14017 int reg_offset = REGNO (offset);
14018 int reg_base = REGNO (base);
14019 int reg_dest = REGNO (operands[0]);
14021 /* Add the base and offset registers together into the
14022 higher destination register. */
14023 asm_fprintf (asm_out_file, "\tadd\t%r, %r, %r",
14024 reg_dest + 1, reg_base, reg_offset);
14026 /* Load the lower destination register from the address in
14027 the higher destination register. */
14028 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #0]",
14029 reg_dest, reg_dest + 1);
14031 /* Load the higher destination register from its own address
14033 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #4]",
14034 reg_dest + 1, reg_dest + 1);
14038 /* Compute <address> + 4 for the high order load. */
14039 operands[2] = gen_rtx_MEM (SImode,
14040 plus_constant (XEXP (operands[1], 0), 4));
14042 /* If the computed address is held in the low order register
14043 then load the high order register first, otherwise always
14044 load the low order register first. */
14045 if (REGNO (operands[0]) == REGNO (base))
14047 output_asm_insn ("ldr\t%H0, %2", operands);
14048 output_asm_insn ("ldr\t%0, %1", operands);
14052 output_asm_insn ("ldr\t%0, %1", operands);
14053 output_asm_insn ("ldr\t%H0, %2", operands);
14059 /* With no registers to worry about we can just load the value
14061 operands[2] = gen_rtx_MEM (SImode,
14062 plus_constant (XEXP (operands[1], 0), 4));
14064 output_asm_insn ("ldr\t%H0, %2", operands);
14065 output_asm_insn ("ldr\t%0, %1", operands);
14077 thumb_output_move_mem_multiple (int n, rtx *operands)
14084 if (REGNO (operands[4]) > REGNO (operands[5]))
14087 operands[4] = operands[5];
14090 output_asm_insn ("ldmia\t%1!, {%4, %5}", operands);
14091 output_asm_insn ("stmia\t%0!, {%4, %5}", operands);
14095 if (REGNO (operands[4]) > REGNO (operands[5]))
14098 operands[4] = operands[5];
14101 if (REGNO (operands[5]) > REGNO (operands[6]))
14104 operands[5] = operands[6];
14107 if (REGNO (operands[4]) > REGNO (operands[5]))
14110 operands[4] = operands[5];
14114 output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands);
14115 output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands);
14125 /* Routines for generating rtl. */
14127 thumb_expand_movmemqi (rtx *operands)
14129 rtx out = copy_to_mode_reg (SImode, XEXP (operands[0], 0));
14130 rtx in = copy_to_mode_reg (SImode, XEXP (operands[1], 0));
14131 HOST_WIDE_INT len = INTVAL (operands[2]);
14132 HOST_WIDE_INT offset = 0;
14136 emit_insn (gen_movmem12b (out, in, out, in));
14142 emit_insn (gen_movmem8b (out, in, out, in));
14148 rtx reg = gen_reg_rtx (SImode);
14149 emit_insn (gen_movsi (reg, gen_rtx_MEM (SImode, in)));
14150 emit_insn (gen_movsi (gen_rtx_MEM (SImode, out), reg));
14157 rtx reg = gen_reg_rtx (HImode);
14158 emit_insn (gen_movhi (reg, gen_rtx_MEM (HImode,
14159 plus_constant (in, offset))));
14160 emit_insn (gen_movhi (gen_rtx_MEM (HImode, plus_constant (out, offset)),
14168 rtx reg = gen_reg_rtx (QImode);
14169 emit_insn (gen_movqi (reg, gen_rtx_MEM (QImode,
14170 plus_constant (in, offset))));
14171 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (out, offset)),
14177 thumb_cmp_operand (rtx op, enum machine_mode mode)
14179 return ((GET_CODE (op) == CONST_INT
14180 && INTVAL (op) < 256
14181 && INTVAL (op) >= 0)
14182 || s_register_operand (op, mode));
14186 thumb_cmpneg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
14188 return (GET_CODE (op) == CONST_INT
14190 && INTVAL (op) > -256);
14193 /* Return TRUE if a result can be stored in OP without clobbering the
14194 condition code register. Prior to reload we only accept a
14195 register. After reload we have to be able to handle memory as
14196 well, since a pseudo may not get a hard reg and reload cannot
14197 handle output-reloads on jump insns.
14199 We could possibly handle mem before reload as well, but that might
14200 complicate things with the need to handle increment
14204 thumb_cbrch_target_operand (rtx op, enum machine_mode mode)
14206 return (s_register_operand (op, mode)
14207 || ((reload_in_progress || reload_completed)
14208 && memory_operand (op, mode)));
14211 /* Handle storing a half-word to memory during reload. */
14213 thumb_reload_out_hi (rtx *operands)
14215 emit_insn (gen_thumb_movhi_clobber (operands[0], operands[1], operands[2]));
14218 /* Handle reading a half-word from memory during reload. */
14220 thumb_reload_in_hi (rtx *operands ATTRIBUTE_UNUSED)
14225 /* Return the length of a function name prefix
14226 that starts with the character 'c'. */
14228 arm_get_strip_length (int c)
14232 ARM_NAME_ENCODING_LENGTHS
14237 /* Return a pointer to a function's name with any
14238 and all prefix encodings stripped from it. */
14240 arm_strip_name_encoding (const char *name)
14244 while ((skip = arm_get_strip_length (* name)))
14250 /* If there is a '*' anywhere in the name's prefix, then
14251 emit the stripped name verbatim, otherwise prepend an
14252 underscore if leading underscores are being used. */
14254 arm_asm_output_labelref (FILE *stream, const char *name)
14259 while ((skip = arm_get_strip_length (* name)))
14261 verbatim |= (*name == '*');
14266 fputs (name, stream);
14268 asm_fprintf (stream, "%U%s", name);
14273 #ifdef AOF_ASSEMBLER
14274 /* Special functions only needed when producing AOF syntax assembler. */
14278 struct pic_chain * next;
14279 const char * symname;
14282 static struct pic_chain * aof_pic_chain = NULL;
14285 aof_pic_entry (rtx x)
14287 struct pic_chain ** chainp;
14290 if (aof_pic_label == NULL_RTX)
14292 aof_pic_label = gen_rtx_SYMBOL_REF (Pmode, "x$adcons");
14295 for (offset = 0, chainp = &aof_pic_chain; *chainp;
14296 offset += 4, chainp = &(*chainp)->next)
14297 if ((*chainp)->symname == XSTR (x, 0))
14298 return plus_constant (aof_pic_label, offset);
14300 *chainp = (struct pic_chain *) xmalloc (sizeof (struct pic_chain));
14301 (*chainp)->next = NULL;
14302 (*chainp)->symname = XSTR (x, 0);
14303 return plus_constant (aof_pic_label, offset);
14307 aof_dump_pic_table (FILE *f)
14309 struct pic_chain * chain;
14311 if (aof_pic_chain == NULL)
14314 asm_fprintf (f, "\tAREA |%r$$adcons|, BASED %r\n",
14315 PIC_OFFSET_TABLE_REGNUM,
14316 PIC_OFFSET_TABLE_REGNUM);
14317 fputs ("|x$adcons|\n", f);
14319 for (chain = aof_pic_chain; chain; chain = chain->next)
14321 fputs ("\tDCD\t", f);
14322 assemble_name (f, chain->symname);
14327 int arm_text_section_count = 1;
14330 aof_text_section (void )
14332 static char buf[100];
14333 sprintf (buf, "\tAREA |C$$code%d|, CODE, READONLY",
14334 arm_text_section_count++);
14336 strcat (buf, ", PIC, REENTRANT");
14340 static int arm_data_section_count = 1;
14343 aof_data_section (void)
14345 static char buf[100];
14346 sprintf (buf, "\tAREA |C$$data%d|, DATA", arm_data_section_count++);
14350 /* The AOF assembler is religiously strict about declarations of
14351 imported and exported symbols, so that it is impossible to declare
14352 a function as imported near the beginning of the file, and then to
14353 export it later on. It is, however, possible to delay the decision
14354 until all the functions in the file have been compiled. To get
14355 around this, we maintain a list of the imports and exports, and
14356 delete from it any that are subsequently defined. At the end of
14357 compilation we spit the remainder of the list out before the END
14362 struct import * next;
14366 static struct import * imports_list = NULL;
14369 aof_add_import (const char *name)
14371 struct import * new;
14373 for (new = imports_list; new; new = new->next)
14374 if (new->name == name)
14377 new = (struct import *) xmalloc (sizeof (struct import));
14378 new->next = imports_list;
14379 imports_list = new;
14384 aof_delete_import (const char *name)
14386 struct import ** old;
14388 for (old = &imports_list; *old; old = & (*old)->next)
14390 if ((*old)->name == name)
14392 *old = (*old)->next;
14398 int arm_main_function = 0;
14401 aof_dump_imports (FILE *f)
14403 /* The AOF assembler needs this to cause the startup code to be extracted
14404 from the library. Brining in __main causes the whole thing to work
14406 if (arm_main_function)
14409 fputs ("\tIMPORT __main\n", f);
14410 fputs ("\tDCD __main\n", f);
14413 /* Now dump the remaining imports. */
14414 while (imports_list)
14416 fprintf (f, "\tIMPORT\t");
14417 assemble_name (f, imports_list->name);
14419 imports_list = imports_list->next;
14424 aof_globalize_label (FILE *stream, const char *name)
14426 default_globalize_label (stream, name);
14427 if (! strcmp (name, "main"))
14428 arm_main_function = 1;
14432 aof_file_start (void)
14434 fputs ("__r0\tRN\t0\n", asm_out_file);
14435 fputs ("__a1\tRN\t0\n", asm_out_file);
14436 fputs ("__a2\tRN\t1\n", asm_out_file);
14437 fputs ("__a3\tRN\t2\n", asm_out_file);
14438 fputs ("__a4\tRN\t3\n", asm_out_file);
14439 fputs ("__v1\tRN\t4\n", asm_out_file);
14440 fputs ("__v2\tRN\t5\n", asm_out_file);
14441 fputs ("__v3\tRN\t6\n", asm_out_file);
14442 fputs ("__v4\tRN\t7\n", asm_out_file);
14443 fputs ("__v5\tRN\t8\n", asm_out_file);
14444 fputs ("__v6\tRN\t9\n", asm_out_file);
14445 fputs ("__sl\tRN\t10\n", asm_out_file);
14446 fputs ("__fp\tRN\t11\n", asm_out_file);
14447 fputs ("__ip\tRN\t12\n", asm_out_file);
14448 fputs ("__sp\tRN\t13\n", asm_out_file);
14449 fputs ("__lr\tRN\t14\n", asm_out_file);
14450 fputs ("__pc\tRN\t15\n", asm_out_file);
14451 fputs ("__f0\tFN\t0\n", asm_out_file);
14452 fputs ("__f1\tFN\t1\n", asm_out_file);
14453 fputs ("__f2\tFN\t2\n", asm_out_file);
14454 fputs ("__f3\tFN\t3\n", asm_out_file);
14455 fputs ("__f4\tFN\t4\n", asm_out_file);
14456 fputs ("__f5\tFN\t5\n", asm_out_file);
14457 fputs ("__f6\tFN\t6\n", asm_out_file);
14458 fputs ("__f7\tFN\t7\n", asm_out_file);
14463 aof_file_end (void)
14466 aof_dump_pic_table (asm_out_file);
14467 aof_dump_imports (asm_out_file);
14468 fputs ("\tEND\n", asm_out_file);
14470 #endif /* AOF_ASSEMBLER */
14472 #ifdef OBJECT_FORMAT_ELF
14473 /* Switch to an arbitrary section NAME with attributes as specified
14474 by FLAGS. ALIGN specifies any known alignment requirements for
14475 the section; 0 if the default should be used.
14477 Differs from the default elf version only in the prefix character
14478 used before the section type. */
14481 arm_elf_asm_named_section (const char *name, unsigned int flags)
14483 char flagchars[10], *f = flagchars;
14485 if (! named_section_first_declaration (name))
14487 fprintf (asm_out_file, "\t.section\t%s\n", name);
14491 if (!(flags & SECTION_DEBUG))
14493 if (flags & SECTION_WRITE)
14495 if (flags & SECTION_CODE)
14497 if (flags & SECTION_SMALL)
14499 if (flags & SECTION_MERGE)
14501 if (flags & SECTION_STRINGS)
14503 if (flags & SECTION_TLS)
14507 fprintf (asm_out_file, "\t.section\t%s,\"%s\"", name, flagchars);
14509 if (!(flags & SECTION_NOTYPE))
14513 if (flags & SECTION_BSS)
14518 fprintf (asm_out_file, ",%%%s", type);
14520 if (flags & SECTION_ENTSIZE)
14521 fprintf (asm_out_file, ",%d", flags & SECTION_ENTSIZE);
14524 putc ('\n', asm_out_file);
14529 /* Symbols in the text segment can be accessed without indirecting via the
14530 constant pool; it may take an extra binary operation, but this is still
14531 faster than indirecting via memory. Don't do this when not optimizing,
14532 since we won't be calculating al of the offsets necessary to do this
14536 arm_encode_section_info (tree decl, rtx rtl, int first)
14538 /* This doesn't work with AOF syntax, since the string table may be in
14539 a different AREA. */
14540 #ifndef AOF_ASSEMBLER
14541 if (optimize > 0 && TREE_CONSTANT (decl))
14542 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;
14545 /* If we are referencing a function that is weak then encode a long call
14546 flag in the function name, otherwise if the function is static or
14547 or known to be defined in this file then encode a short call flag. */
14548 if (first && TREE_CODE_CLASS (TREE_CODE (decl)) == 'd')
14550 if (TREE_CODE (decl) == FUNCTION_DECL && DECL_WEAK (decl))
14551 arm_encode_call_attribute (decl, LONG_CALL_FLAG_CHAR);
14552 else if (! TREE_PUBLIC (decl))
14553 arm_encode_call_attribute (decl, SHORT_CALL_FLAG_CHAR);
14556 #endif /* !ARM_PE */
14559 arm_internal_label (FILE *stream, const char *prefix, unsigned long labelno)
14561 if (arm_ccfsm_state == 3 && (unsigned) arm_target_label == labelno
14562 && !strcmp (prefix, "L"))
14564 arm_ccfsm_state = 0;
14565 arm_target_insn = NULL;
14567 default_internal_label (stream, prefix, labelno);
14570 /* Output code to add DELTA to the first argument, and then jump
14571 to FUNCTION. Used for C++ multiple inheritance. */
14573 arm_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
14574 HOST_WIDE_INT delta,
14575 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
14578 static int thunk_label = 0;
14580 int mi_delta = delta;
14581 const char *const mi_op = mi_delta < 0 ? "sub" : "add";
14583 int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)
14586 mi_delta = - mi_delta;
14589 int labelno = thunk_label++;
14590 ASM_GENERATE_INTERNAL_LABEL (label, "LTHUMBFUNC", labelno);
14591 fputs ("\tldr\tr12, ", file);
14592 assemble_name (file, label);
14593 fputc ('\n', file);
14595 while (mi_delta != 0)
14597 if ((mi_delta & (3 << shift)) == 0)
14601 asm_fprintf (file, "\t%s\t%r, %r, #%d\n",
14602 mi_op, this_regno, this_regno,
14603 mi_delta & (0xff << shift));
14604 mi_delta &= ~(0xff << shift);
14610 fprintf (file, "\tbx\tr12\n");
14611 ASM_OUTPUT_ALIGN (file, 2);
14612 assemble_name (file, label);
14613 fputs (":\n", file);
14614 assemble_integer (XEXP (DECL_RTL (function), 0), 4, BITS_PER_WORD, 1);
14618 fputs ("\tb\t", file);
14619 assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0));
14620 if (NEED_PLT_RELOC)
14621 fputs ("(PLT)", file);
14622 fputc ('\n', file);
14627 arm_emit_vector_const (FILE *file, rtx x)
14630 const char * pattern;
14632 if (GET_CODE (x) != CONST_VECTOR)
14635 switch (GET_MODE (x))
14637 case V2SImode: pattern = "%08x"; break;
14638 case V4HImode: pattern = "%04x"; break;
14639 case V8QImode: pattern = "%02x"; break;
14643 fprintf (file, "0x");
14644 for (i = CONST_VECTOR_NUNITS (x); i--;)
14648 element = CONST_VECTOR_ELT (x, i);
14649 fprintf (file, pattern, INTVAL (element));
14656 arm_output_load_gr (rtx *operands)
14663 if (GET_CODE (operands [1]) != MEM
14664 || GET_CODE (sum = XEXP (operands [1], 0)) != PLUS
14665 || GET_CODE (reg = XEXP (sum, 0)) != REG
14666 || GET_CODE (offset = XEXP (sum, 1)) != CONST_INT
14667 || ((INTVAL (offset) < 1024) && (INTVAL (offset) > -1024)))
14668 return "wldrw%?\t%0, %1";
14670 /* Fix up an out-of-range load of a GR register. */
14671 output_asm_insn ("str%?\t%0, [sp, #-4]!\t@ Start of GR load expansion", & reg);
14672 wcgr = operands[0];
14674 output_asm_insn ("ldr%?\t%0, %1", operands);
14676 operands[0] = wcgr;
14678 output_asm_insn ("tmcr%?\t%0, %1", operands);
14679 output_asm_insn ("ldr%?\t%0, [sp], #4\t@ End of GR load expansion", & reg);
14685 arm_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
14686 int incoming ATTRIBUTE_UNUSED)
14689 /* FIXME: The ARM backend has special code to handle structure
14690 returns, and will reserve its own hidden first argument. So
14691 if this macro is enabled a *second* hidden argument will be
14692 reserved, which will break binary compatibility with old
14693 toolchains and also thunk handling. One day this should be
14697 /* Register in which address to store a structure value
14698 is passed to a function. */
14699 return gen_rtx_REG (Pmode, ARG_REGISTER (1));
14703 /* Worker function for TARGET_SETUP_INCOMING_VARARGS.
14705 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
14706 named arg and all anonymous args onto the stack.
14707 XXX I know the prologue shouldn't be pushing registers, but it is faster
14711 arm_setup_incoming_varargs (CUMULATIVE_ARGS *cum,
14712 enum machine_mode mode ATTRIBUTE_UNUSED,
14713 tree type ATTRIBUTE_UNUSED,
14715 int second_time ATTRIBUTE_UNUSED)
14717 cfun->machine->uses_anonymous_args = 1;
14718 if (cum->nregs < NUM_ARG_REGS)
14719 *pretend_size = (NUM_ARG_REGS - cum->nregs) * UNITS_PER_WORD;
14722 /* Return nonzero if the CONSUMER instruction (a store) does not need
14723 PRODUCER's value to calculate the address. */
14726 arm_no_early_store_addr_dep (rtx producer, rtx consumer)
14728 rtx value = PATTERN (producer);
14729 rtx addr = PATTERN (consumer);
14731 if (GET_CODE (value) == COND_EXEC)
14732 value = COND_EXEC_CODE (value);
14733 if (GET_CODE (value) == PARALLEL)
14734 value = XVECEXP (value, 0, 0);
14735 value = XEXP (value, 0);
14736 if (GET_CODE (addr) == COND_EXEC)
14737 addr = COND_EXEC_CODE (addr);
14738 if (GET_CODE (addr) == PARALLEL)
14739 addr = XVECEXP (addr, 0, 0);
14740 addr = XEXP (addr, 0);
14742 return !reg_overlap_mentioned_p (value, addr);
14745 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
14746 have an early register shift value or amount dependency on the
14747 result of PRODUCER. */
14750 arm_no_early_alu_shift_dep (rtx producer, rtx consumer)
14752 rtx value = PATTERN (producer);
14753 rtx op = PATTERN (consumer);
14756 if (GET_CODE (value) == COND_EXEC)
14757 value = COND_EXEC_CODE (value);
14758 if (GET_CODE (value) == PARALLEL)
14759 value = XVECEXP (value, 0, 0);
14760 value = XEXP (value, 0);
14761 if (GET_CODE (op) == COND_EXEC)
14762 op = COND_EXEC_CODE (op);
14763 if (GET_CODE (op) == PARALLEL)
14764 op = XVECEXP (op, 0, 0);
14767 early_op = XEXP (op, 0);
14768 /* This is either an actual independent shift, or a shift applied to
14769 the first operand of another operation. We want the whole shift
14771 if (GET_CODE (early_op) == REG)
14774 return !reg_overlap_mentioned_p (value, early_op);
14777 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
14778 have an early register shift value dependency on the result of
14782 arm_no_early_alu_shift_value_dep (rtx producer, rtx consumer)
14784 rtx value = PATTERN (producer);
14785 rtx op = PATTERN (consumer);
14788 if (GET_CODE (value) == COND_EXEC)
14789 value = COND_EXEC_CODE (value);
14790 if (GET_CODE (value) == PARALLEL)
14791 value = XVECEXP (value, 0, 0);
14792 value = XEXP (value, 0);
14793 if (GET_CODE (op) == COND_EXEC)
14794 op = COND_EXEC_CODE (op);
14795 if (GET_CODE (op) == PARALLEL)
14796 op = XVECEXP (op, 0, 0);
14799 early_op = XEXP (op, 0);
14801 /* This is either an actual independent shift, or a shift applied to
14802 the first operand of another operation. We want the value being
14803 shifted, in either case. */
14804 if (GET_CODE (early_op) != REG)
14805 early_op = XEXP (early_op, 0);
14807 return !reg_overlap_mentioned_p (value, early_op);
14810 /* Return nonzero if the CONSUMER (a mul or mac op) does not
14811 have an early register mult dependency on the result of
14815 arm_no_early_mul_dep (rtx producer, rtx consumer)
14817 rtx value = PATTERN (producer);
14818 rtx op = PATTERN (consumer);
14820 if (GET_CODE (value) == COND_EXEC)
14821 value = COND_EXEC_CODE (value);
14822 if (GET_CODE (value) == PARALLEL)
14823 value = XVECEXP (value, 0, 0);
14824 value = XEXP (value, 0);
14825 if (GET_CODE (op) == COND_EXEC)
14826 op = COND_EXEC_CODE (op);
14827 if (GET_CODE (op) == PARALLEL)
14828 op = XVECEXP (op, 0, 0);
14831 return (GET_CODE (op) == PLUS
14832 && !reg_overlap_mentioned_p (value, XEXP (op, 0)));
14836 /* We can't rely on the caller doing the proper promotion when
14837 using APCS or ATPCS. */
14840 arm_promote_prototypes (tree t ATTRIBUTE_UNUSED)
14842 return !TARGET_AAPCS_BASED;
14846 /* AAPCS based ABIs use short enums by default. */
14849 arm_default_short_enums (void)
14851 return TARGET_AAPCS_BASED;
14855 /* AAPCS requires that anonymous bitfields affect structure alignment. */
14858 arm_align_anon_bitfield (void)
14860 return TARGET_AAPCS_BASED;
14864 /* The generic C++ ABI says 64-bit (long long). The EABI says 32-bit. */
14867 arm_cxx_guard_type (void)
14869 return TARGET_AAPCS_BASED ? integer_type_node : long_long_integer_type_node;
14873 /* The EABI says test the least significan bit of a guard variable. */
14876 arm_cxx_guard_mask_bit (void)
14878 return TARGET_AAPCS_BASED;
14882 /* The EABI specifies that all array cookies are 8 bytes long. */
14885 arm_get_cookie_size (tree type)
14889 if (!TARGET_AAPCS_BASED)
14890 return default_cxx_get_cookie_size (type);
14892 size = build_int_cst (sizetype, 8, 0);
14897 /* The EABI says that array cookies should also contain the element size. */
14900 arm_cookie_has_size (void)
14902 return TARGET_AAPCS_BASED;
14906 /* The EABI says constructors and destructors should return a pointer to
14907 the object constructed/destroyed. */
14910 arm_cxx_cdtor_returns_this (void)
14912 return TARGET_AAPCS_BASED;
14917 arm_set_return_address (rtx source, rtx scratch)
14919 arm_stack_offsets *offsets;
14920 HOST_WIDE_INT delta;
14922 unsigned long saved_regs;
14924 saved_regs = arm_compute_save_reg_mask ();
14926 if ((saved_regs & (1 << LR_REGNUM)) == 0)
14927 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNUM), source);
14930 if (frame_pointer_needed)
14931 addr = plus_constant(hard_frame_pointer_rtx, -4);
14934 /* LR will be the first saved register. */
14935 offsets = arm_get_frame_offsets ();
14936 delta = offsets->outgoing_args - (offsets->frame + 4);
14941 emit_insn (gen_addsi3 (scratch, stack_pointer_rtx,
14942 GEN_INT (delta & ~4095)));
14947 addr = stack_pointer_rtx;
14949 addr = plus_constant (addr, delta);
14951 emit_move_insn (gen_rtx_MEM (Pmode, addr), source);
14957 thumb_set_return_address (rtx source, rtx scratch)
14959 arm_stack_offsets *offsets;
14960 HOST_WIDE_INT delta;
14963 unsigned long mask;
14965 emit_insn (gen_rtx_USE (VOIDmode, source));
14967 mask = thumb_compute_save_reg_mask ();
14968 if (mask & (1 << LR_REGNUM))
14970 offsets = arm_get_frame_offsets ();
14972 /* Find the saved regs. */
14973 if (frame_pointer_needed)
14975 delta = offsets->soft_frame - offsets->saved_args;
14976 reg = THUMB_HARD_FRAME_POINTER_REGNUM;
14980 delta = offsets->outgoing_args - offsets->saved_args;
14983 /* Allow for the stack frame. */
14984 if (TARGET_BACKTRACE)
14986 /* The link register is always the first saved register. */
14989 /* Construct the address. */
14990 addr = gen_rtx_REG (SImode, reg);
14991 if ((reg != SP_REGNUM && delta >= 128)
14994 emit_insn (gen_movsi (scratch, GEN_INT (delta)));
14995 emit_insn (gen_addsi3 (scratch, scratch, stack_pointer_rtx));
14999 addr = plus_constant (addr, delta);
15001 emit_move_insn (gen_rtx_MEM (Pmode, addr), source);
15004 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNUM), source);