1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
3 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com).
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
47 #include "integrate.h"
50 #include "target-def.h"
52 /* Forward definitions of types. */
53 typedef struct minipool_node Mnode;
54 typedef struct minipool_fixup Mfix;
56 /* In order to improve the layout of the prototypes below
57 some short type abbreviations are defined here. */
58 #define Hint HOST_WIDE_INT
59 #define Mmode enum machine_mode
60 #define Ulong unsigned long
61 #define Ccstar const char *
63 /* Forward function declarations. */
64 static void arm_add_gc_roots PARAMS ((void));
65 static int arm_gen_constant PARAMS ((enum rtx_code, Mmode, Hint, rtx, rtx, int, int));
66 static Ulong bit_count PARAMS ((signed int));
67 static int const_ok_for_op PARAMS ((Hint, enum rtx_code));
68 static int eliminate_lr2ip PARAMS ((rtx *));
69 static rtx emit_multi_reg_push PARAMS ((int));
70 static rtx emit_sfm PARAMS ((int, int));
71 static Ccstar fp_const_from_val PARAMS ((REAL_VALUE_TYPE *));
72 static arm_cc get_arm_condition_code PARAMS ((rtx));
73 static void init_fpa_table PARAMS ((void));
74 static Hint int_log2 PARAMS ((Hint));
75 static rtx is_jump_table PARAMS ((rtx));
76 static Ccstar output_multi_immediate PARAMS ((rtx *, Ccstar, Ccstar, int, Hint));
77 static void print_multi_reg PARAMS ((FILE *, Ccstar, int, int));
78 static Mmode select_dominance_cc_mode PARAMS ((rtx, rtx, Hint));
79 static Ccstar shift_op PARAMS ((rtx, Hint *));
80 static void arm_init_machine_status PARAMS ((struct function *));
81 static void arm_mark_machine_status PARAMS ((struct function *));
82 static void arm_free_machine_status PARAMS ((struct function *));
83 static int number_of_first_bit_set PARAMS ((int));
84 static void replace_symbols_in_block PARAMS ((tree, rtx, rtx));
85 static void thumb_exit PARAMS ((FILE *, int, rtx));
86 static void thumb_pushpop PARAMS ((FILE *, int, int));
87 static Ccstar thumb_condition_code PARAMS ((rtx, int));
88 static rtx is_jump_table PARAMS ((rtx));
89 static Hint get_jump_table_size PARAMS ((rtx));
90 static Mnode * move_minipool_fix_forward_ref PARAMS ((Mnode *, Mnode *, Hint));
91 static Mnode * add_minipool_forward_ref PARAMS ((Mfix *));
92 static Mnode * move_minipool_fix_backward_ref PARAMS ((Mnode *, Mnode *, Hint));
93 static Mnode * add_minipool_backward_ref PARAMS ((Mfix *));
94 static void assign_minipool_offsets PARAMS ((Mfix *));
95 static void arm_print_value PARAMS ((FILE *, rtx));
96 static void dump_minipool PARAMS ((rtx));
97 static int arm_barrier_cost PARAMS ((rtx));
98 static Mfix * create_fix_barrier PARAMS ((Mfix *, Hint));
99 static void push_minipool_barrier PARAMS ((rtx, Hint));
100 static void push_minipool_fix PARAMS ((rtx, Hint, rtx *, Mmode, rtx));
101 static void note_invalid_constants PARAMS ((rtx, Hint));
102 static int current_file_function_operand PARAMS ((rtx));
103 static Ulong arm_compute_save_reg_mask PARAMS ((void));
104 static Ulong arm_isr_value PARAMS ((tree));
105 static Ulong arm_compute_func_type PARAMS ((void));
106 static tree arm_handle_fndecl_attribute PARAMS ((tree *, tree, tree, int, bool *));
107 static tree arm_handle_isr_attribute PARAMS ((tree *, tree, tree, int, bool *));
108 const struct attribute_spec arm_attribute_table[];
109 static void arm_output_function_epilogue PARAMS ((FILE *,
111 static void arm_output_function_prologue PARAMS ((FILE *,
113 static void thumb_output_function_prologue PARAMS ((FILE *,
115 static int arm_comp_type_attributes PARAMS ((tree, tree));
116 static void arm_set_default_type_attributes PARAMS ((tree));
117 #ifdef OBJECT_FORMAT_ELF
118 static void arm_elf_asm_named_section PARAMS ((const char *,
121 static int arm_adjust_cost PARAMS ((rtx, rtx, rtx, int));
128 /* Initialize the GCC target structure. */
129 #ifdef TARGET_DLLIMPORT_DECL_ATTRIBUTES
130 #undef TARGET_MERGE_DECL_ATTRIBUTES
131 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
134 #undef TARGET_ATTRIBUTE_TABLE
135 #define TARGET_ATTRIBUTE_TABLE arm_attribute_table
137 #undef TARGET_ASM_FUNCTION_PROLOGUE
138 #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue
140 #undef TARGET_ASM_FUNCTION_EPILOGUE
141 #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue
143 #undef TARGET_COMP_TYPE_ATTRIBUTES
144 #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes
146 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
147 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes
149 #undef TARGET_INIT_BUILTINS
150 #define TARGET_INIT_BUILTINS arm_init_builtins
152 #undef TARGET_EXPAND_BUILTIN
153 #define TARGET_EXPAND_BUILTIN arm_expand_builtin
155 #undef TARGET_SCHED_ADJUST_COST
156 #define TARGET_SCHED_ADJUST_COST arm_adjust_cost
158 struct gcc_target targetm = TARGET_INITIALIZER;
160 /* Obstack for minipool constant handling. */
161 static struct obstack minipool_obstack;
162 static char *minipool_startobj;
164 #define obstack_chunk_alloc xmalloc
165 #define obstack_chunk_free free
167 /* The maximum number of insns skipped which will be conditionalised if
169 static int max_insns_skipped = 5;
171 extern FILE * asm_out_file;
173 /* True if we are currently building a constant table. */
174 int making_const_table;
176 /* Define the information needed to generate branch insns. This is
177 stored from the compare operation. */
178 rtx arm_compare_op0, arm_compare_op1;
180 /* What type of floating point are we tuning for? */
181 enum floating_point_type arm_fpu;
183 /* What type of floating point instructions are available? */
184 enum floating_point_type arm_fpu_arch;
186 /* What program mode is the cpu running in? 26-bit mode or 32-bit mode. */
187 enum prog_mode_type arm_prgmode;
189 /* Set by the -mfp=... option. */
190 const char * target_fp_name = NULL;
192 /* Used to parse -mstructure_size_boundary command line option. */
193 const char * structure_size_string = NULL;
194 int arm_structure_size_boundary = DEFAULT_STRUCTURE_SIZE_BOUNDARY;
196 /* Bit values used to identify processor capabilities. */
197 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
198 #define FL_FAST_MULT (1 << 1) /* Fast multiply */
199 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
200 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
201 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
202 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
203 #define FL_THUMB (1 << 6) /* Thumb aware */
204 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
205 #define FL_STRONG (1 << 8) /* StrongARM */
206 #define FL_ARCH5E (1 << 9) /* DSP extenstions to v5 */
207 #define FL_XSCALE (1 << 10) /* XScale */
209 /* The bits in this mask specify which instructions we are
210 allowed to generate. */
211 static int insn_flags = 0;
213 /* The bits in this mask specify which instruction scheduling options should
214 be used. Note - there is an overlap with the FL_FAST_MULT. For some
215 hardware we want to be able to generate the multiply instructions, but to
216 tune as if they were not present in the architecture. */
217 static int tune_flags = 0;
219 /* The following are used in the arm.md file as equivalents to bits
220 in the above two flag variables. */
222 /* Nonzero if this is an "M" variant of the processor. */
223 int arm_fast_multiply = 0;
225 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
228 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
231 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
234 /* Nonzero if this chip can benefit from load scheduling. */
235 int arm_ld_sched = 0;
237 /* Nonzero if this chip is a StrongARM. */
238 int arm_is_strong = 0;
240 /* Nonzero if this chip is an XScale. */
241 int arm_is_xscale = 0;
243 /* Nonzero if this chip is an ARM6 or an ARM7. */
244 int arm_is_6_or_7 = 0;
246 /* Nonzero if generating Thumb instructions. */
249 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
250 must report the mode of the memory reference from PRINT_OPERAND to
251 PRINT_OPERAND_ADDRESS. */
252 enum machine_mode output_memory_reference_mode;
254 /* Nonzero if the prologue must setup `fp'. */
255 int current_function_anonymous_args;
257 /* The register number to be used for the PIC offset register. */
258 const char * arm_pic_register_string = NULL;
259 int arm_pic_register = 9;
261 /* Set to 1 when a return insn is output, this means that the epilogue
263 int return_used_this_function;
265 /* Set to 1 after arm_reorg has started. Reset to start at the start of
266 the next function. */
267 static int after_arm_reorg = 0;
269 /* The maximum number of insns to be used when loading a constant. */
270 static int arm_constant_limit = 3;
272 /* For an explanation of these variables, see final_prescan_insn below. */
274 enum arm_cond_code arm_current_cc;
276 int arm_target_label;
278 /* The condition codes of the ARM, and the inverse function. */
279 static const char *const arm_condition_codes[] =
281 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
282 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
285 #define streq(string1, string2) (strcmp (string1, string2) == 0)
287 /* Initialization code. */
291 const char *const name;
292 const unsigned int flags;
295 /* Not all of these give usefully different compilation alternatives,
296 but there is no simple way of generalizing them. */
297 static const struct processors all_cores[] =
301 {"arm2", FL_CO_PROC | FL_MODE26 },
302 {"arm250", FL_CO_PROC | FL_MODE26 },
303 {"arm3", FL_CO_PROC | FL_MODE26 },
304 {"arm6", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
305 {"arm60", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
306 {"arm600", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
307 {"arm610", FL_MODE26 | FL_MODE32 },
308 {"arm620", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
309 {"arm7", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
310 /* arm7m doesn't exist on its own, but only with D, (and I), but
311 those don't alter the code, so arm7m is sometimes used. */
312 {"arm7m", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
313 {"arm7d", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
314 {"arm7dm", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
315 {"arm7di", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
316 {"arm7dmi", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
317 {"arm70", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
318 {"arm700", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
319 {"arm700i", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
320 {"arm710", FL_MODE26 | FL_MODE32 },
321 {"arm710t", FL_MODE26 | FL_MODE32 | FL_THUMB },
322 {"arm720", FL_MODE26 | FL_MODE32 },
323 {"arm720t", FL_MODE26 | FL_MODE32 | FL_THUMB },
324 {"arm740t", FL_MODE26 | FL_MODE32 | FL_THUMB },
325 {"arm710c", FL_MODE26 | FL_MODE32 },
326 {"arm7100", FL_MODE26 | FL_MODE32 },
327 {"arm7500", FL_MODE26 | FL_MODE32 },
328 /* Doesn't have an external co-proc, but does have embedded fpu. */
329 {"arm7500fe", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
330 {"arm7tdmi", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB },
331 {"arm8", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED },
332 {"arm810", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED },
333 {"arm9", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED },
334 {"arm920", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED },
335 {"arm920t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED },
336 {"arm940t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED },
337 {"arm9tdmi", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED },
338 {"arm9e", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED },
339 {"strongarm", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG },
340 {"strongarm110", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG },
341 {"strongarm1100", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG },
342 {"strongarm1110", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG },
343 {"arm10tdmi", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_ARCH5 },
344 {"arm1020t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_ARCH5 },
345 {"xscale", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_STRONG | FL_ARCH5 | FL_ARCH5E | FL_XSCALE },
350 static const struct processors all_architectures[] =
352 /* ARM Architectures */
354 { "armv2", FL_CO_PROC | FL_MODE26 },
355 { "armv2a", FL_CO_PROC | FL_MODE26 },
356 { "armv3", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
357 { "armv3m", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
358 { "armv4", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 },
359 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
360 implementations that support it, so we will leave it out for now. */
361 { "armv4t", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB },
362 { "armv5", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 },
363 { "armv5t", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 },
364 { "armv5te", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E },
368 /* This is a magic stucture. The 'string' field is magically filled in
369 with a pointer to the value specified by the user on the command line
370 assuming that the user has specified such a value. */
372 struct arm_cpu_select arm_select[] =
374 /* string name processors */
375 { NULL, "-mcpu=", all_cores },
376 { NULL, "-march=", all_architectures },
377 { NULL, "-mtune=", all_cores }
380 /* Return the number of bits set in value' */
385 unsigned long count = 0;
389 value &= ~(value & -value);
396 /* Fix up any incompatible options that the user has specified.
397 This has now turned into a maze. */
399 arm_override_options ()
403 /* Set up the flags based on the cpu/architecture selected by the user. */
404 for (i = ARRAY_SIZE (arm_select); i--;)
406 struct arm_cpu_select * ptr = arm_select + i;
408 if (ptr->string != NULL && ptr->string[0] != '\0')
410 const struct processors * sel;
412 for (sel = ptr->processors; sel->name != NULL; sel++)
413 if (streq (ptr->string, sel->name))
416 tune_flags = sel->flags;
419 /* If we have been given an architecture and a processor
420 make sure that they are compatible. We only generate
421 a warning though, and we prefer the CPU over the
423 if (insn_flags != 0 && (insn_flags ^ sel->flags))
424 warning ("switch -mcpu=%s conflicts with -march= switch",
427 insn_flags = sel->flags;
433 if (sel->name == NULL)
434 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
438 /* If the user did not specify a processor, choose one for them. */
441 const struct processors * sel;
443 static const struct cpu_default
446 const char *const name;
450 { TARGET_CPU_arm2, "arm2" },
451 { TARGET_CPU_arm6, "arm6" },
452 { TARGET_CPU_arm610, "arm610" },
453 { TARGET_CPU_arm710, "arm710" },
454 { TARGET_CPU_arm7m, "arm7m" },
455 { TARGET_CPU_arm7500fe, "arm7500fe" },
456 { TARGET_CPU_arm7tdmi, "arm7tdmi" },
457 { TARGET_CPU_arm8, "arm8" },
458 { TARGET_CPU_arm810, "arm810" },
459 { TARGET_CPU_arm9, "arm9" },
460 { TARGET_CPU_strongarm, "strongarm" },
461 { TARGET_CPU_xscale, "xscale" },
462 { TARGET_CPU_generic, "arm" },
465 const struct cpu_default * def;
467 /* Find the default. */
468 for (def = cpu_defaults; def->name; def++)
469 if (def->cpu == TARGET_CPU_DEFAULT)
472 /* Make sure we found the default CPU. */
473 if (def->name == NULL)
476 /* Find the default CPU's flags. */
477 for (sel = all_cores; sel->name != NULL; sel++)
478 if (streq (def->name, sel->name))
481 if (sel->name == NULL)
484 insn_flags = sel->flags;
486 /* Now check to see if the user has specified some command line
487 switch that require certain abilities from the cpu. */
490 if (TARGET_INTERWORK || TARGET_THUMB)
492 sought |= (FL_THUMB | FL_MODE32);
494 /* Force apcs-32 to be used for interworking. */
495 target_flags |= ARM_FLAG_APCS_32;
497 /* There are no ARM processors that support both APCS-26 and
498 interworking. Therefore we force FL_MODE26 to be removed
499 from insn_flags here (if it was set), so that the search
500 below will always be able to find a compatible processor. */
501 insn_flags &= ~FL_MODE26;
503 else if (!TARGET_APCS_32)
506 if (sought != 0 && ((sought & insn_flags) != sought))
508 /* Try to locate a CPU type that supports all of the abilities
509 of the default CPU, plus the extra abilities requested by
511 for (sel = all_cores; sel->name != NULL; sel++)
512 if ((sel->flags & sought) == (sought | insn_flags))
515 if (sel->name == NULL)
517 unsigned int current_bit_count = 0;
518 const struct processors * best_fit = NULL;
520 /* Ideally we would like to issue an error message here
521 saying that it was not possible to find a CPU compatible
522 with the default CPU, but which also supports the command
523 line options specified by the programmer, and so they
524 ought to use the -mcpu=<name> command line option to
525 override the default CPU type.
527 Unfortunately this does not work with multilibing. We
528 need to be able to support multilibs for -mapcs-26 and for
529 -mthumb-interwork and there is no CPU that can support both
530 options. Instead if we cannot find a cpu that has both the
531 characteristics of the default cpu and the given command line
532 options we scan the array again looking for a best match. */
533 for (sel = all_cores; sel->name != NULL; sel++)
534 if ((sel->flags & sought) == sought)
538 count = bit_count (sel->flags & insn_flags);
540 if (count >= current_bit_count)
543 current_bit_count = count;
547 if (best_fit == NULL)
553 insn_flags = sel->flags;
557 /* If tuning has not been specified, tune for whichever processor or
558 architecture has been selected. */
560 tune_flags = insn_flags;
562 /* Make sure that the processor choice does not conflict with any of the
563 other command line choices. */
564 if (TARGET_APCS_32 && !(insn_flags & FL_MODE32))
566 /* If APCS-32 was not the default then it must have been set by the
567 user, so issue a warning message. If the user has specified
568 "-mapcs-32 -mcpu=arm2" then we loose here. */
569 if ((TARGET_DEFAULT & ARM_FLAG_APCS_32) == 0)
570 warning ("target CPU does not support APCS-32" );
571 target_flags &= ~ARM_FLAG_APCS_32;
573 else if (!TARGET_APCS_32 && !(insn_flags & FL_MODE26))
575 warning ("target CPU does not support APCS-26" );
576 target_flags |= ARM_FLAG_APCS_32;
579 if (TARGET_INTERWORK && !(insn_flags & FL_THUMB))
581 warning ("target CPU does not support interworking" );
582 target_flags &= ~ARM_FLAG_INTERWORK;
585 if (TARGET_THUMB && !(insn_flags & FL_THUMB))
587 warning ("target CPU does not support THUMB instructions");
588 target_flags &= ~ARM_FLAG_THUMB;
591 if (TARGET_APCS_FRAME && TARGET_THUMB)
593 /* warning ("ignoring -mapcs-frame because -mthumb was used"); */
594 target_flags &= ~ARM_FLAG_APCS_FRAME;
597 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
598 from here where no function is being compiled currently. */
599 if ((target_flags & (THUMB_FLAG_LEAF_BACKTRACE | THUMB_FLAG_BACKTRACE))
601 warning ("enabling backtrace support is only meaningful when compiling for the Thumb");
603 if (TARGET_ARM && TARGET_CALLEE_INTERWORKING)
604 warning ("enabling callee interworking support is only meaningful when compiling for the Thumb");
606 if (TARGET_ARM && TARGET_CALLER_INTERWORKING)
607 warning ("enabling caller interworking support is only meaningful when compiling for the Thumb");
609 /* If interworking is enabled then APCS-32 must be selected as well. */
610 if (TARGET_INTERWORK)
613 warning ("interworking forces APCS-32 to be used" );
614 target_flags |= ARM_FLAG_APCS_32;
617 if (TARGET_APCS_STACK && !TARGET_APCS_FRAME)
619 warning ("-mapcs-stack-check incompatible with -mno-apcs-frame");
620 target_flags |= ARM_FLAG_APCS_FRAME;
623 if (TARGET_POKE_FUNCTION_NAME)
624 target_flags |= ARM_FLAG_APCS_FRAME;
626 if (TARGET_APCS_REENT && flag_pic)
627 error ("-fpic and -mapcs-reent are incompatible");
629 if (TARGET_APCS_REENT)
630 warning ("APCS reentrant code not supported. Ignored");
632 /* If this target is normally configured to use APCS frames, warn if they
633 are turned off and debugging is turned on. */
635 && write_symbols != NO_DEBUG
636 && !TARGET_APCS_FRAME
637 && (TARGET_DEFAULT & ARM_FLAG_APCS_FRAME))
638 warning ("-g with -mno-apcs-frame may not give sensible debugging");
640 /* If stack checking is disabled, we can use r10 as the PIC register,
641 which keeps r9 available. */
642 if (flag_pic && !TARGET_APCS_STACK)
643 arm_pic_register = 10;
645 if (TARGET_APCS_FLOAT)
646 warning ("passing floating point arguments in fp regs not yet supported");
648 /* Initialise boolean versions of the flags, for use in the arm.md file. */
649 arm_fast_multiply = (insn_flags & FL_FAST_MULT) != 0;
650 arm_arch4 = (insn_flags & FL_ARCH4) != 0;
651 arm_arch5 = (insn_flags & FL_ARCH5) != 0;
652 arm_arch5e = (insn_flags & FL_ARCH5E) != 0;
653 arm_is_xscale = (insn_flags & FL_XSCALE) != 0;
655 arm_ld_sched = (tune_flags & FL_LDSCHED) != 0;
656 arm_is_strong = (tune_flags & FL_STRONG) != 0;
657 thumb_code = (TARGET_ARM == 0);
658 arm_is_6_or_7 = (((tune_flags & (FL_MODE26 | FL_MODE32))
659 && !(tune_flags & FL_ARCH4))) != 0;
661 /* Default value for floating point code... if no co-processor
662 bus, then schedule for emulated floating point. Otherwise,
663 assume the user has an FPA.
664 Note: this does not prevent use of floating point instructions,
665 -msoft-float does that. */
666 arm_fpu = (tune_flags & FL_CO_PROC) ? FP_HARD : FP_SOFT3;
670 if (streq (target_fp_name, "2"))
671 arm_fpu_arch = FP_SOFT2;
672 else if (streq (target_fp_name, "3"))
673 arm_fpu_arch = FP_SOFT3;
675 error ("invalid floating point emulation option: -mfpe-%s",
679 arm_fpu_arch = FP_DEFAULT;
681 if (TARGET_FPE && arm_fpu != FP_HARD)
684 /* For arm2/3 there is no need to do any scheduling if there is only
685 a floating point emulator, or we are doing software floating-point. */
686 if ((TARGET_SOFT_FLOAT || arm_fpu != FP_HARD)
687 && (tune_flags & FL_MODE32) == 0)
688 flag_schedule_insns = flag_schedule_insns_after_reload = 0;
690 arm_prgmode = TARGET_APCS_32 ? PROG_MODE_PROG32 : PROG_MODE_PROG26;
692 if (structure_size_string != NULL)
694 int size = strtol (structure_size_string, NULL, 0);
696 if (size == 8 || size == 32)
697 arm_structure_size_boundary = size;
699 warning ("structure size boundary can only be set to 8 or 32");
702 if (arm_pic_register_string != NULL)
707 warning ("-mpic-register= is useless without -fpic");
709 pic_register = decode_reg_name (arm_pic_register_string);
711 /* Prevent the user from choosing an obviously stupid PIC register. */
712 if (pic_register < 0 || call_used_regs[pic_register]
713 || pic_register == HARD_FRAME_POINTER_REGNUM
714 || pic_register == STACK_POINTER_REGNUM
715 || pic_register >= PC_REGNUM)
716 error ("unable to use '%s' for PIC register", arm_pic_register_string);
718 arm_pic_register = pic_register;
721 if (TARGET_THUMB && flag_schedule_insns)
723 /* Don't warn since it's on by default in -O2. */
724 flag_schedule_insns = 0;
727 /* If optimizing for space, don't synthesize constants.
728 For processors with load scheduling, it never costs more than 2 cycles
729 to load a constant, and the load scheduler may well reduce that to 1. */
730 if (optimize_size || (tune_flags & FL_LDSCHED))
731 arm_constant_limit = 1;
734 arm_constant_limit = 2;
736 /* If optimizing for size, bump the number of instructions that we
737 are prepared to conditionally execute (even on a StrongARM).
738 Otherwise for the StrongARM, which has early execution of branches,
739 a sequence that is worth skipping is shorter. */
741 max_insns_skipped = 6;
742 else if (arm_is_strong)
743 max_insns_skipped = 3;
745 /* Register global variables with the garbage collector. */
752 ggc_add_rtx_root (&arm_compare_op0, 1);
753 ggc_add_rtx_root (&arm_compare_op1, 1);
754 ggc_add_rtx_root (&arm_target_insn, 1); /* Not sure this is really a root. */
756 gcc_obstack_init(&minipool_obstack);
757 minipool_startobj = (char *) obstack_alloc (&minipool_obstack, 0);
760 /* A table of known ARM exception types.
761 For use with the interrupt function attribute. */
765 const char *const arg;
766 const unsigned long return_value;
770 static const isr_attribute_arg isr_attribute_args [] =
772 { "IRQ", ARM_FT_ISR },
773 { "irq", ARM_FT_ISR },
774 { "FIQ", ARM_FT_FIQ },
775 { "fiq", ARM_FT_FIQ },
776 { "ABORT", ARM_FT_ISR },
777 { "abort", ARM_FT_ISR },
778 { "ABORT", ARM_FT_ISR },
779 { "abort", ARM_FT_ISR },
780 { "UNDEF", ARM_FT_EXCEPTION },
781 { "undef", ARM_FT_EXCEPTION },
782 { "SWI", ARM_FT_EXCEPTION },
783 { "swi", ARM_FT_EXCEPTION },
784 { NULL, ARM_FT_NORMAL }
787 /* Returns the (interrupt) function type of the current
788 function, or ARM_FT_UNKNOWN if the type cannot be determined. */
791 arm_isr_value (argument)
794 const isr_attribute_arg * ptr;
797 /* No argument - default to IRQ. */
798 if (argument == NULL_TREE)
801 /* Get the value of the argument. */
802 if (TREE_VALUE (argument) == NULL_TREE
803 || TREE_CODE (TREE_VALUE (argument)) != STRING_CST)
804 return ARM_FT_UNKNOWN;
806 arg = TREE_STRING_POINTER (TREE_VALUE (argument));
808 /* Check it against the list of known arguments. */
809 for (ptr = isr_attribute_args; ptr->arg != NULL; ptr ++)
810 if (strcmp (arg, ptr->arg) == 0)
811 return ptr->return_value;
813 /* An unrecognised interrupt type. */
814 return ARM_FT_UNKNOWN;
817 /* Computes the type of the current function. */
820 arm_compute_func_type ()
822 unsigned long type = ARM_FT_UNKNOWN;
826 if (TREE_CODE (current_function_decl) != FUNCTION_DECL)
829 /* Decide if the current function is volatile. Such functions
830 never return, and many memory cycles can be saved by not storing
831 register values that will never be needed again. This optimization
832 was added to speed up context switching in a kernel application. */
834 && current_function_nothrow
835 && TREE_THIS_VOLATILE (current_function_decl))
836 type |= ARM_FT_VOLATILE;
838 if (current_function_needs_context)
839 type |= ARM_FT_NESTED;
841 attr = DECL_ATTRIBUTES (current_function_decl);
843 a = lookup_attribute ("naked", attr);
845 type |= ARM_FT_NAKED;
847 if (cfun->machine->eh_epilogue_sp_ofs != NULL_RTX)
848 type |= ARM_FT_EXCEPTION_HANDLER;
851 a = lookup_attribute ("isr", attr);
853 a = lookup_attribute ("interrupt", attr);
856 type |= TARGET_INTERWORK ? ARM_FT_INTERWORKED : ARM_FT_NORMAL;
858 type |= arm_isr_value (TREE_VALUE (a));
864 /* Returns the type of the current function. */
867 arm_current_func_type ()
869 if (ARM_FUNC_TYPE (cfun->machine->func_type) == ARM_FT_UNKNOWN)
870 cfun->machine->func_type = arm_compute_func_type ();
872 return cfun->machine->func_type;
875 /* Return 1 if it is possible to return using a single instruction. */
878 use_return_insn (iscond)
882 unsigned int func_type;
884 /* Never use a return instruction before reload has run. */
885 if (!reload_completed)
888 func_type = arm_current_func_type ();
890 /* Naked functions, volatile functiond and interrupt
891 functions all need special consideration. */
892 if (func_type & (ARM_FT_INTERRUPT | ARM_FT_VOLATILE | ARM_FT_NAKED))
895 /* As do variadic functions. */
896 if (current_function_pretend_args_size
897 || current_function_anonymous_args
898 /* Of if the function calls __builtin_eh_return () */
899 || ARM_FUNC_TYPE (func_type) == ARM_FT_EXCEPTION_HANDLER
900 /* Or if there is no frame pointer and there is a stack adjustment. */
901 || ((get_frame_size () + current_function_outgoing_args_size != 0)
902 && !frame_pointer_needed))
905 /* Can't be done if interworking with Thumb, and any registers have been
906 stacked. Similarly, on StrongARM, conditional returns are expensive
907 if they aren't taken and registers have been stacked. */
908 if (iscond && arm_is_strong && frame_pointer_needed)
911 if ((iscond && arm_is_strong)
914 for (regno = 0; regno <= LAST_ARM_REGNUM; regno++)
915 if (regs_ever_live[regno] && !call_used_regs[regno])
918 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
922 /* Can't be done if any of the FPU regs are pushed,
923 since this also requires an insn. */
924 if (TARGET_HARD_FLOAT)
925 for (regno = FIRST_ARM_FP_REGNUM; regno <= LAST_ARM_FP_REGNUM; regno++)
926 if (regs_ever_live[regno] && !call_used_regs[regno])
932 /* Return TRUE if int I is a valid immediate ARM constant. */
938 unsigned HOST_WIDE_INT mask = ~(unsigned HOST_WIDE_INT)0xFF;
940 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
941 be all zero, or all one. */
942 if ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0
943 && ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff)
944 != ((~(unsigned HOST_WIDE_INT) 0)
945 & ~(unsigned HOST_WIDE_INT) 0xffffffff)))
948 /* Fast return for 0 and powers of 2 */
949 if ((i & (i - 1)) == 0)
954 if ((i & mask & (unsigned HOST_WIDE_INT) 0xffffffff) == 0)
957 (mask << 2) | ((mask & (unsigned HOST_WIDE_INT) 0xffffffff)
958 >> (32 - 2)) | ~(unsigned HOST_WIDE_INT) 0xffffffff;
960 while (mask != ~(unsigned HOST_WIDE_INT) 0xFF);
965 /* Return true if I is a valid constant for the operation CODE. */
967 const_ok_for_op (i, code)
971 if (const_ok_for_arm (i))
977 return const_ok_for_arm (ARM_SIGN_EXTEND (-i));
979 case MINUS: /* Should only occur with (MINUS I reg) => rsb */
985 return const_ok_for_arm (ARM_SIGN_EXTEND (~i));
992 /* Emit a sequence of insns to handle a large constant.
993 CODE is the code of the operation required, it can be any of SET, PLUS,
994 IOR, AND, XOR, MINUS;
995 MODE is the mode in which the operation is being performed;
996 VAL is the integer to operate on;
997 SOURCE is the other operand (a register, or a null-pointer for SET);
998 SUBTARGETS means it is safe to create scratch registers if that will
999 either produce a simpler sequence, or we will want to cse the values.
1000 Return value is the number of insns emitted. */
1003 arm_split_constant (code, mode, val, target, source, subtargets)
1005 enum machine_mode mode;
1011 if (subtargets || code == SET
1012 || (GET_CODE (target) == REG && GET_CODE (source) == REG
1013 && REGNO (target) != REGNO (source)))
1015 /* After arm_reorg has been called, we can't fix up expensive
1016 constants by pushing them into memory so we must synthesise
1017 them in-line, regardless of the cost. This is only likely to
1018 be more costly on chips that have load delay slots and we are
1019 compiling without running the scheduler (so no splitting
1020 occurred before the final instruction emission).
1022 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
1024 if (!after_arm_reorg
1025 && (arm_gen_constant (code, mode, val, target, source, 1, 0)
1026 > arm_constant_limit + (code != SET)))
1030 /* Currently SET is the only monadic value for CODE, all
1031 the rest are diadic. */
1032 emit_insn (gen_rtx_SET (VOIDmode, target, GEN_INT (val)));
1037 rtx temp = subtargets ? gen_reg_rtx (mode) : target;
1039 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (val)));
1040 /* For MINUS, the value is subtracted from, since we never
1041 have subtraction of a constant. */
1043 emit_insn (gen_rtx_SET (VOIDmode, target,
1044 gen_rtx_MINUS (mode, temp, source)));
1046 emit_insn (gen_rtx_SET (VOIDmode, target,
1047 gen_rtx (code, mode, source, temp)));
1053 return arm_gen_constant (code, mode, val, target, source, subtargets, 1);
1057 count_insns_for_constant (HOST_WIDE_INT remainder, int i)
1059 HOST_WIDE_INT temp1;
1067 if (remainder & (3 << (i - 2)))
1072 temp1 = remainder & ((0x0ff << end)
1073 | ((i < end) ? (0xff >> (32 - end)) : 0));
1074 remainder &= ~temp1;
1079 } while (remainder);
1083 /* As above, but extra parameter GENERATE which, if clear, suppresses
1086 arm_gen_constant (code, mode, val, target, source, subtargets, generate)
1088 enum machine_mode mode;
1097 int can_negate_initial = 0;
1100 int num_bits_set = 0;
1101 int set_sign_bit_copies = 0;
1102 int clear_sign_bit_copies = 0;
1103 int clear_zero_bit_copies = 0;
1104 int set_zero_bit_copies = 0;
1106 unsigned HOST_WIDE_INT temp1, temp2;
1107 unsigned HOST_WIDE_INT remainder = val & 0xffffffff;
1109 /* Find out which operations are safe for a given CODE. Also do a quick
1110 check for degenerate cases; these can occur when DImode operations
1122 can_negate_initial = 1;
1126 if (remainder == 0xffffffff)
1129 emit_insn (gen_rtx_SET (VOIDmode, target,
1130 GEN_INT (ARM_SIGN_EXTEND (val))));
1135 if (reload_completed && rtx_equal_p (target, source))
1138 emit_insn (gen_rtx_SET (VOIDmode, target, source));
1147 emit_insn (gen_rtx_SET (VOIDmode, target, const0_rtx));
1150 if (remainder == 0xffffffff)
1152 if (reload_completed && rtx_equal_p (target, source))
1155 emit_insn (gen_rtx_SET (VOIDmode, target, source));
1164 if (reload_completed && rtx_equal_p (target, source))
1167 emit_insn (gen_rtx_SET (VOIDmode, target, source));
1170 if (remainder == 0xffffffff)
1173 emit_insn (gen_rtx_SET (VOIDmode, target,
1174 gen_rtx_NOT (mode, source)));
1178 /* We don't know how to handle this yet below. */
1182 /* We treat MINUS as (val - source), since (source - val) is always
1183 passed as (source + (-val)). */
1187 emit_insn (gen_rtx_SET (VOIDmode, target,
1188 gen_rtx_NEG (mode, source)));
1191 if (const_ok_for_arm (val))
1194 emit_insn (gen_rtx_SET (VOIDmode, target,
1195 gen_rtx_MINUS (mode, GEN_INT (val),
1207 /* If we can do it in one insn get out quickly. */
1208 if (const_ok_for_arm (val)
1209 || (can_negate_initial && const_ok_for_arm (-val))
1210 || (can_invert && const_ok_for_arm (~val)))
1213 emit_insn (gen_rtx_SET (VOIDmode, target,
1214 (source ? gen_rtx (code, mode, source,
1220 /* Calculate a few attributes that may be useful for specific
1222 for (i = 31; i >= 0; i--)
1224 if ((remainder & (1 << i)) == 0)
1225 clear_sign_bit_copies++;
1230 for (i = 31; i >= 0; i--)
1232 if ((remainder & (1 << i)) != 0)
1233 set_sign_bit_copies++;
1238 for (i = 0; i <= 31; i++)
1240 if ((remainder & (1 << i)) == 0)
1241 clear_zero_bit_copies++;
1246 for (i = 0; i <= 31; i++)
1248 if ((remainder & (1 << i)) != 0)
1249 set_zero_bit_copies++;
1257 /* See if we can do this by sign_extending a constant that is known
1258 to be negative. This is a good, way of doing it, since the shift
1259 may well merge into a subsequent insn. */
1260 if (set_sign_bit_copies > 1)
1262 if (const_ok_for_arm
1263 (temp1 = ARM_SIGN_EXTEND (remainder
1264 << (set_sign_bit_copies - 1))))
1268 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1269 emit_insn (gen_rtx_SET (VOIDmode, new_src,
1271 emit_insn (gen_ashrsi3 (target, new_src,
1272 GEN_INT (set_sign_bit_copies - 1)));
1276 /* For an inverted constant, we will need to set the low bits,
1277 these will be shifted out of harm's way. */
1278 temp1 |= (1 << (set_sign_bit_copies - 1)) - 1;
1279 if (const_ok_for_arm (~temp1))
1283 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1284 emit_insn (gen_rtx_SET (VOIDmode, new_src,
1286 emit_insn (gen_ashrsi3 (target, new_src,
1287 GEN_INT (set_sign_bit_copies - 1)));
1293 /* See if we can generate this by setting the bottom (or the top)
1294 16 bits, and then shifting these into the other half of the
1295 word. We only look for the simplest cases, to do more would cost
1296 too much. Be careful, however, not to generate this when the
1297 alternative would take fewer insns. */
1298 if (val & 0xffff0000)
1300 temp1 = remainder & 0xffff0000;
1301 temp2 = remainder & 0x0000ffff;
1303 /* Overlaps outside this range are best done using other methods. */
1304 for (i = 9; i < 24; i++)
1306 if ((((temp2 | (temp2 << i)) & 0xffffffff) == remainder)
1307 && !const_ok_for_arm (temp2))
1309 rtx new_src = (subtargets
1310 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
1312 insns = arm_gen_constant (code, mode, temp2, new_src,
1313 source, subtargets, generate);
1316 emit_insn (gen_rtx_SET
1319 gen_rtx_ASHIFT (mode, source,
1326 /* Don't duplicate cases already considered. */
1327 for (i = 17; i < 24; i++)
1329 if (((temp1 | (temp1 >> i)) == remainder)
1330 && !const_ok_for_arm (temp1))
1332 rtx new_src = (subtargets
1333 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
1335 insns = arm_gen_constant (code, mode, temp1, new_src,
1336 source, subtargets, generate);
1340 (gen_rtx_SET (VOIDmode, target,
1343 gen_rtx_LSHIFTRT (mode, source,
1354 /* If we have IOR or XOR, and the constant can be loaded in a
1355 single instruction, and we can find a temporary to put it in,
1356 then this can be done in two instructions instead of 3-4. */
1358 /* TARGET can't be NULL if SUBTARGETS is 0 */
1359 || (reload_completed && !reg_mentioned_p (target, source)))
1361 if (const_ok_for_arm (ARM_SIGN_EXTEND (~val)))
1365 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1367 emit_insn (gen_rtx_SET (VOIDmode, sub, GEN_INT (val)));
1368 emit_insn (gen_rtx_SET (VOIDmode, target,
1369 gen_rtx (code, mode, source, sub)));
1378 if (set_sign_bit_copies > 8
1379 && (val & (-1 << (32 - set_sign_bit_copies))) == val)
1383 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1384 rtx shift = GEN_INT (set_sign_bit_copies);
1386 emit_insn (gen_rtx_SET (VOIDmode, sub,
1388 gen_rtx_ASHIFT (mode,
1391 emit_insn (gen_rtx_SET (VOIDmode, target,
1393 gen_rtx_LSHIFTRT (mode, sub,
1399 if (set_zero_bit_copies > 8
1400 && (remainder & ((1 << set_zero_bit_copies) - 1)) == remainder)
1404 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1405 rtx shift = GEN_INT (set_zero_bit_copies);
1407 emit_insn (gen_rtx_SET (VOIDmode, sub,
1409 gen_rtx_LSHIFTRT (mode,
1412 emit_insn (gen_rtx_SET (VOIDmode, target,
1414 gen_rtx_ASHIFT (mode, sub,
1420 if (const_ok_for_arm (temp1 = ARM_SIGN_EXTEND (~val)))
1424 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1425 emit_insn (gen_rtx_SET (VOIDmode, sub,
1426 gen_rtx_NOT (mode, source)));
1429 sub = gen_reg_rtx (mode);
1430 emit_insn (gen_rtx_SET (VOIDmode, sub,
1431 gen_rtx_AND (mode, source,
1433 emit_insn (gen_rtx_SET (VOIDmode, target,
1434 gen_rtx_NOT (mode, sub)));
1441 /* See if two shifts will do 2 or more insn's worth of work. */
1442 if (clear_sign_bit_copies >= 16 && clear_sign_bit_copies < 24)
1444 HOST_WIDE_INT shift_mask = ((0xffffffff
1445 << (32 - clear_sign_bit_copies))
1448 if ((remainder | shift_mask) != 0xffffffff)
1452 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1453 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1454 new_src, source, subtargets, 1);
1459 rtx targ = subtargets ? NULL_RTX : target;
1460 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1461 targ, source, subtargets, 0);
1467 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1468 rtx shift = GEN_INT (clear_sign_bit_copies);
1470 emit_insn (gen_ashlsi3 (new_src, source, shift));
1471 emit_insn (gen_lshrsi3 (target, new_src, shift));
1477 if (clear_zero_bit_copies >= 16 && clear_zero_bit_copies < 24)
1479 HOST_WIDE_INT shift_mask = (1 << clear_zero_bit_copies) - 1;
1481 if ((remainder | shift_mask) != 0xffffffff)
1485 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1487 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1488 new_src, source, subtargets, 1);
1493 rtx targ = subtargets ? NULL_RTX : target;
1495 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1496 targ, source, subtargets, 0);
1502 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1503 rtx shift = GEN_INT (clear_zero_bit_copies);
1505 emit_insn (gen_lshrsi3 (new_src, source, shift));
1506 emit_insn (gen_ashlsi3 (target, new_src, shift));
1518 for (i = 0; i < 32; i++)
1519 if (remainder & (1 << i))
1522 if (code == AND || (can_invert && num_bits_set > 16))
1523 remainder = (~remainder) & 0xffffffff;
1524 else if (code == PLUS && num_bits_set > 16)
1525 remainder = (-remainder) & 0xffffffff;
1532 /* Now try and find a way of doing the job in either two or three
1534 We start by looking for the largest block of zeros that are aligned on
1535 a 2-bit boundary, we then fill up the temps, wrapping around to the
1536 top of the word when we drop off the bottom.
1537 In the worst case this code should produce no more than four insns. */
1540 int best_consecutive_zeros = 0;
1542 for (i = 0; i < 32; i += 2)
1544 int consecutive_zeros = 0;
1546 if (!(remainder & (3 << i)))
1548 while ((i < 32) && !(remainder & (3 << i)))
1550 consecutive_zeros += 2;
1553 if (consecutive_zeros > best_consecutive_zeros)
1555 best_consecutive_zeros = consecutive_zeros;
1556 best_start = i - consecutive_zeros;
1562 /* So long as it won't require any more insns to do so, it's
1563 desirable to emit a small constant (in bits 0...9) in the last
1564 insn. This way there is more chance that it can be combined with
1565 a later addressing insn to form a pre-indexed load or store
1566 operation. Consider:
1568 *((volatile int *)0xe0000100) = 1;
1569 *((volatile int *)0xe0000110) = 2;
1571 We want this to wind up as:
1575 str rB, [rA, #0x100]
1577 str rB, [rA, #0x110]
1579 rather than having to synthesize both large constants from scratch.
1581 Therefore, we calculate how many insns would be required to emit
1582 the constant starting from `best_start', and also starting from
1583 zero (ie with bit 31 first to be output). If `best_start' doesn't
1584 yield a shorter sequence, we may as well use zero. */
1586 && ((((unsigned HOST_WIDE_INT) 1) << best_start) < remainder)
1587 && (count_insns_for_constant (remainder, 0) <=
1588 count_insns_for_constant (remainder, best_start)))
1591 /* Now start emitting the insns. */
1599 if (remainder & (3 << (i - 2)))
1604 temp1 = remainder & ((0x0ff << end)
1605 | ((i < end) ? (0xff >> (32 - end)) : 0));
1606 remainder &= ~temp1;
1613 emit_insn (gen_rtx_SET (VOIDmode,
1614 new_src = (subtargets
1615 ? gen_reg_rtx (mode)
1618 ? ~temp1 : temp1)));
1619 else if (code == MINUS)
1620 emit_insn (gen_rtx_SET (VOIDmode,
1621 new_src = (subtargets
1622 ? gen_reg_rtx (mode)
1624 gen_rtx (code, mode, GEN_INT (temp1),
1627 emit_insn (gen_rtx_SET (VOIDmode,
1628 new_src = (remainder
1630 ? gen_reg_rtx (mode)
1633 gen_rtx (code, mode, source,
1634 GEN_INT (can_invert ? ~temp1
1646 else if (code == MINUS)
1653 } while (remainder);
1658 /* Canonicalize a comparison so that we are more likely to recognize it.
1659 This can be done for a few constant compares, where we can make the
1660 immediate value easier to load. */
1662 arm_canonicalize_comparison (code, op1)
1666 unsigned HOST_WIDE_INT i = INTVAL (*op1);
1676 if (i != ((((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1)) - 1)
1677 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
1679 *op1 = GEN_INT (i + 1);
1680 return code == GT ? GE : LT;
1686 if (i != (((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1))
1687 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
1689 *op1 = GEN_INT (i - 1);
1690 return code == GE ? GT : LE;
1696 if (i != ~((unsigned HOST_WIDE_INT) 0)
1697 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
1699 *op1 = GEN_INT (i + 1);
1700 return code == GTU ? GEU : LTU;
1707 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
1709 *op1 = GEN_INT (i - 1);
1710 return code == GEU ? GTU : LEU;
1721 /* Decide whether a type should be returned in memory (true)
1722 or in a register (false). This is called by the macro
1723 RETURN_IN_MEMORY. */
1725 arm_return_in_memory (type)
1728 if (!AGGREGATE_TYPE_P (type))
1729 /* All simple types are returned in registers. */
1732 /* For the arm-wince targets we choose to be compitable with Microsoft's
1733 ARM and Thumb compilers, which always return aggregates in memory. */
1735 /* All structures/unions bigger than one word are returned in memory.
1736 Also catch the case where int_size_in_bytes returns -1. In this case
1737 the aggregate is either huge or of varaible size, and in either case
1738 we will want to return it via memory and not in a register. */
1739 if (((unsigned int) int_size_in_bytes (type)) > UNITS_PER_WORD)
1742 if (TREE_CODE (type) == RECORD_TYPE)
1746 /* For a struct the APCS says that we only return in a register
1747 if the type is 'integer like' and every addressable element
1748 has an offset of zero. For practical purposes this means
1749 that the structure can have at most one non bit-field element
1750 and that this element must be the first one in the structure. */
1752 /* Find the first field, ignoring non FIELD_DECL things which will
1753 have been created by C++. */
1754 for (field = TYPE_FIELDS (type);
1755 field && TREE_CODE (field) != FIELD_DECL;
1756 field = TREE_CHAIN (field))
1760 return 0; /* An empty structure. Allowed by an extension to ANSI C. */
1762 /* Check that the first field is valid for returning in a register. */
1764 /* ... Floats are not allowed */
1765 if (FLOAT_TYPE_P (TREE_TYPE (field)))
1768 /* ... Aggregates that are not themselves valid for returning in
1769 a register are not allowed. */
1770 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
1773 /* Now check the remaining fields, if any. Only bitfields are allowed,
1774 since they are not addressable. */
1775 for (field = TREE_CHAIN (field);
1777 field = TREE_CHAIN (field))
1779 if (TREE_CODE (field) != FIELD_DECL)
1782 if (!DECL_BIT_FIELD_TYPE (field))
1789 if (TREE_CODE (type) == UNION_TYPE)
1793 /* Unions can be returned in registers if every element is
1794 integral, or can be returned in an integer register. */
1795 for (field = TYPE_FIELDS (type);
1797 field = TREE_CHAIN (field))
1799 if (TREE_CODE (field) != FIELD_DECL)
1802 if (FLOAT_TYPE_P (TREE_TYPE (field)))
1805 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
1811 #endif /* not ARM_WINCE */
1813 /* Return all other types in memory. */
1817 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1818 for a call to a function whose data type is FNTYPE.
1819 For a library call, FNTYPE is NULL. */
1821 arm_init_cumulative_args (pcum, fntype, libname, indirect)
1822 CUMULATIVE_ARGS * pcum;
1824 rtx libname ATTRIBUTE_UNUSED;
1825 int indirect ATTRIBUTE_UNUSED;
1827 /* On the ARM, the offset starts at 0. */
1828 pcum->nregs = ((fntype && aggregate_value_p (TREE_TYPE (fntype))) ? 1 : 0);
1830 pcum->call_cookie = CALL_NORMAL;
1832 if (TARGET_LONG_CALLS)
1833 pcum->call_cookie = CALL_LONG;
1835 /* Check for long call/short call attributes. The attributes
1836 override any command line option. */
1839 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (fntype)))
1840 pcum->call_cookie = CALL_SHORT;
1841 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (fntype)))
1842 pcum->call_cookie = CALL_LONG;
1846 /* Determine where to put an argument to a function.
1847 Value is zero to push the argument on the stack,
1848 or a hard register in which to store the argument.
1850 MODE is the argument's machine mode.
1851 TYPE is the data type of the argument (as a tree).
1852 This is null for libcalls where that information may
1854 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1855 the preceding args and about the function being called.
1856 NAMED is nonzero if this argument is a named parameter
1857 (otherwise it is an extra parameter matching an ellipsis). */
1859 arm_function_arg (pcum, mode, type, named)
1860 CUMULATIVE_ARGS * pcum;
1861 enum machine_mode mode;
1862 tree type ATTRIBUTE_UNUSED;
1865 if (mode == VOIDmode)
1866 /* Compute operand 2 of the call insn. */
1867 return GEN_INT (pcum->call_cookie);
1869 if (!named || pcum->nregs >= NUM_ARG_REGS)
1872 return gen_rtx_REG (mode, pcum->nregs);
1875 /* Encode the current state of the #pragma [no_]long_calls. */
1878 OFF, /* No #pramgma [no_]long_calls is in effect. */
1879 LONG, /* #pragma long_calls is in effect. */
1880 SHORT /* #pragma no_long_calls is in effect. */
1883 static arm_pragma_enum arm_pragma_long_calls = OFF;
1886 arm_pr_long_calls (pfile)
1887 cpp_reader *pfile ATTRIBUTE_UNUSED;
1889 arm_pragma_long_calls = LONG;
1893 arm_pr_no_long_calls (pfile)
1894 cpp_reader *pfile ATTRIBUTE_UNUSED;
1896 arm_pragma_long_calls = SHORT;
1900 arm_pr_long_calls_off (pfile)
1901 cpp_reader *pfile ATTRIBUTE_UNUSED;
1903 arm_pragma_long_calls = OFF;
1907 /* Table of machine attributes. */
1908 const struct attribute_spec arm_attribute_table[] =
1910 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
1911 /* Function calls made to this symbol must be done indirectly, because
1912 it may lie outside of the 26 bit addressing range of a normal function
1914 { "long_call", 0, 0, false, true, true, NULL },
1915 /* Whereas these functions are always known to reside within the 26 bit
1916 addressing range. */
1917 { "short_call", 0, 0, false, true, true, NULL },
1918 /* Interrupt Service Routines have special prologue and epilogue requirements. */
1919 { "isr", 0, 1, false, false, false, arm_handle_isr_attribute },
1920 { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute },
1921 { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute },
1923 /* ARM/PE has three new attributes:
1925 dllexport - for exporting a function/variable that will live in a dll
1926 dllimport - for importing a function/variable from a dll
1928 Microsoft allows multiple declspecs in one __declspec, separating
1929 them with spaces. We do NOT support this. Instead, use __declspec
1932 { "dllimport", 0, 0, true, false, false, NULL },
1933 { "dllexport", 0, 0, true, false, false, NULL },
1934 { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute },
1936 { NULL, 0, 0, false, false, false, NULL }
1939 /* Handle an attribute requiring a FUNCTION_DECL;
1940 arguments as in struct attribute_spec.handler. */
1942 arm_handle_fndecl_attribute (node, name, args, flags, no_add_attrs)
1945 tree args ATTRIBUTE_UNUSED;
1946 int flags ATTRIBUTE_UNUSED;
1949 if (TREE_CODE (*node) != FUNCTION_DECL)
1951 warning ("`%s' attribute only applies to functions",
1952 IDENTIFIER_POINTER (name));
1953 *no_add_attrs = true;
1959 /* Handle an "interrupt" or "isr" attribute;
1960 arguments as in struct attribute_spec.handler. */
1962 arm_handle_isr_attribute (node, name, args, flags, no_add_attrs)
1971 if (TREE_CODE (*node) != FUNCTION_DECL)
1973 warning ("`%s' attribute only applies to functions",
1974 IDENTIFIER_POINTER (name));
1975 *no_add_attrs = true;
1977 /* FIXME: the argument if any is checked for type attributes;
1978 should it be checked for decl ones? */
1982 if (TREE_CODE (*node) == FUNCTION_TYPE
1983 || TREE_CODE (*node) == METHOD_TYPE)
1985 if (arm_isr_value (args) == ARM_FT_UNKNOWN)
1987 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
1988 *no_add_attrs = true;
1991 else if (TREE_CODE (*node) == POINTER_TYPE
1992 && (TREE_CODE (TREE_TYPE (*node)) == FUNCTION_TYPE
1993 || TREE_CODE (TREE_TYPE (*node)) == METHOD_TYPE)
1994 && arm_isr_value (args) != ARM_FT_UNKNOWN)
1996 *node = build_type_copy (*node);
1997 TREE_TYPE (*node) = build_type_attribute_variant (TREE_TYPE (*node),
2000 TYPE_ATTRIBUTES (TREE_TYPE (*node))));
2001 *no_add_attrs = true;
2005 /* Possibly pass this attribute on from the type to a decl. */
2006 if (flags & ((int) ATTR_FLAG_DECL_NEXT
2007 | (int) ATTR_FLAG_FUNCTION_NEXT
2008 | (int) ATTR_FLAG_ARRAY_NEXT))
2010 *no_add_attrs = true;
2011 return tree_cons (name, args, NULL_TREE);
2015 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
2023 /* Return 0 if the attributes for two types are incompatible, 1 if they
2024 are compatible, and 2 if they are nearly compatible (which causes a
2025 warning to be generated). */
2027 arm_comp_type_attributes (type1, type2)
2033 /* Check for mismatch of non-default calling convention. */
2034 if (TREE_CODE (type1) != FUNCTION_TYPE)
2037 /* Check for mismatched call attributes. */
2038 l1 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1)) != NULL;
2039 l2 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2)) != NULL;
2040 s1 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1)) != NULL;
2041 s2 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2)) != NULL;
2043 /* Only bother to check if an attribute is defined. */
2044 if (l1 | l2 | s1 | s2)
2046 /* If one type has an attribute, the other must have the same attribute. */
2047 if ((l1 != l2) || (s1 != s2))
2050 /* Disallow mixed attributes. */
2051 if ((l1 & s2) || (l2 & s1))
2055 /* Check for mismatched ISR attribute. */
2056 l1 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type1)) != NULL;
2058 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1)) != NULL;
2059 l2 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type2)) != NULL;
2061 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2)) != NULL;
2068 /* Encode long_call or short_call attribute by prefixing
2069 symbol name in DECL with a special character FLAG. */
2071 arm_encode_call_attribute (decl, flag)
2075 const char * str = XSTR (XEXP (DECL_RTL (decl), 0), 0);
2076 int len = strlen (str);
2079 if (TREE_CODE (decl) != FUNCTION_DECL)
2082 /* Do not allow weak functions to be treated as short call. */
2083 if (DECL_WEAK (decl) && flag == SHORT_CALL_FLAG_CHAR)
2086 newstr = alloca (len + 2);
2088 strcpy (newstr + 1, str);
2090 newstr = (char *) ggc_alloc_string (newstr, len + 1);
2091 XSTR (XEXP (DECL_RTL (decl), 0), 0) = newstr;
2094 /* Assigns default attributes to newly defined type. This is used to
2095 set short_call/long_call attributes for function types of
2096 functions defined inside corresponding #pragma scopes. */
2098 arm_set_default_type_attributes (type)
2101 /* Add __attribute__ ((long_call)) to all functions, when
2102 inside #pragma long_calls or __attribute__ ((short_call)),
2103 when inside #pragma no_long_calls. */
2104 if (TREE_CODE (type) == FUNCTION_TYPE || TREE_CODE (type) == METHOD_TYPE)
2106 tree type_attr_list, attr_name;
2107 type_attr_list = TYPE_ATTRIBUTES (type);
2109 if (arm_pragma_long_calls == LONG)
2110 attr_name = get_identifier ("long_call");
2111 else if (arm_pragma_long_calls == SHORT)
2112 attr_name = get_identifier ("short_call");
2116 type_attr_list = tree_cons (attr_name, NULL_TREE, type_attr_list);
2117 TYPE_ATTRIBUTES (type) = type_attr_list;
2121 /* Return 1 if the operand is a SYMBOL_REF for a function known to be
2122 defined within the current compilation unit. If this caanot be
2123 determined, then 0 is returned. */
2125 current_file_function_operand (sym_ref)
2128 /* This is a bit of a fib. A function will have a short call flag
2129 applied to its name if it has the short call attribute, or it has
2130 already been defined within the current compilation unit. */
2131 if (ENCODED_SHORT_CALL_ATTR_P (XSTR (sym_ref, 0)))
2134 /* The current function is always defined within the current compilation
2135 unit. if it s a weak definition however, then this may not be the real
2136 definition of the function, and so we have to say no. */
2137 if (sym_ref == XEXP (DECL_RTL (current_function_decl), 0)
2138 && !DECL_WEAK (current_function_decl))
2141 /* We cannot make the determination - default to returning 0. */
2145 /* Return non-zero if a 32 bit "long_call" should be generated for
2146 this call. We generate a long_call if the function:
2148 a. has an __attribute__((long call))
2149 or b. is within the scope of a #pragma long_calls
2150 or c. the -mlong-calls command line switch has been specified
2152 However we do not generate a long call if the function:
2154 d. has an __attribute__ ((short_call))
2155 or e. is inside the scope of a #pragma no_long_calls
2156 or f. has an __attribute__ ((section))
2157 or g. is defined within the current compilation unit.
2159 This function will be called by C fragments contained in the machine
2160 description file. CALL_REF and CALL_COOKIE correspond to the matched
2161 rtl operands. CALL_SYMBOL is used to distinguish between
2162 two different callers of the function. It is set to 1 in the
2163 "call_symbol" and "call_symbol_value" patterns and to 0 in the "call"
2164 and "call_value" patterns. This is because of the difference in the
2165 SYM_REFs passed by these patterns. */
2167 arm_is_longcall_p (sym_ref, call_cookie, call_symbol)
2174 if (GET_CODE (sym_ref) != MEM)
2177 sym_ref = XEXP (sym_ref, 0);
2180 if (GET_CODE (sym_ref) != SYMBOL_REF)
2183 if (call_cookie & CALL_SHORT)
2186 if (TARGET_LONG_CALLS && flag_function_sections)
2189 if (current_file_function_operand (sym_ref))
2192 return (call_cookie & CALL_LONG)
2193 || ENCODED_LONG_CALL_ATTR_P (XSTR (sym_ref, 0))
2194 || TARGET_LONG_CALLS;
2197 /* Return non-zero if it is ok to make a tail-call to DECL. */
2199 arm_function_ok_for_sibcall (decl)
2202 int call_type = TARGET_LONG_CALLS ? CALL_LONG : CALL_NORMAL;
2204 /* Never tailcall something for which we have no decl, or if we
2205 are in Thumb mode. */
2206 if (decl == NULL || TARGET_THUMB)
2209 /* Get the calling method. */
2210 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
2211 call_type = CALL_SHORT;
2212 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
2213 call_type = CALL_LONG;
2215 /* Cannot tail-call to long calls, since these are out of range of
2216 a branch instruction. However, if not compiling PIC, we know
2217 we can reach the symbol if it is in this compilation unit. */
2218 if (call_type == CALL_LONG && (flag_pic || !TREE_ASM_WRITTEN (decl)))
2221 /* If we are interworking and the function is not declared static
2222 then we can't tail-call it unless we know that it exists in this
2223 compilation unit (since it might be a Thumb routine). */
2224 if (TARGET_INTERWORK && TREE_PUBLIC (decl) && !TREE_ASM_WRITTEN (decl))
2227 /* Never tailcall from an ISR routine - it needs a special exit sequence. */
2228 if (IS_INTERRUPT (arm_current_func_type ()))
2231 /* Everything else is ok. */
2237 legitimate_pic_operand_p (x)
2242 && (GET_CODE (x) == SYMBOL_REF
2243 || (GET_CODE (x) == CONST
2244 && GET_CODE (XEXP (x, 0)) == PLUS
2245 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)))
2252 legitimize_pic_address (orig, mode, reg)
2254 enum machine_mode mode;
2257 if (GET_CODE (orig) == SYMBOL_REF
2258 || GET_CODE (orig) == LABEL_REF)
2260 #ifndef AOF_ASSEMBLER
2261 rtx pic_ref, address;
2271 reg = gen_reg_rtx (Pmode);
2276 #ifdef AOF_ASSEMBLER
2277 /* The AOF assembler can generate relocations for these directly, and
2278 understands that the PIC register has to be added into the offset. */
2279 insn = emit_insn (gen_pic_load_addr_based (reg, orig));
2282 address = gen_reg_rtx (Pmode);
2287 emit_insn (gen_pic_load_addr_arm (address, orig));
2289 emit_insn (gen_pic_load_addr_thumb (address, orig));
2291 if (GET_CODE (orig) == LABEL_REF && NEED_GOT_RELOC)
2292 pic_ref = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, address);
2295 pic_ref = gen_rtx_MEM (Pmode,
2296 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
2298 RTX_UNCHANGING_P (pic_ref) = 1;
2301 insn = emit_move_insn (reg, pic_ref);
2303 current_function_uses_pic_offset_table = 1;
2304 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2306 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
2310 else if (GET_CODE (orig) == CONST)
2314 if (GET_CODE (XEXP (orig, 0)) == PLUS
2315 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
2323 reg = gen_reg_rtx (Pmode);
2326 if (GET_CODE (XEXP (orig, 0)) == PLUS)
2328 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
2329 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
2330 base == reg ? 0 : reg);
2335 if (GET_CODE (offset) == CONST_INT)
2337 /* The base register doesn't really matter, we only want to
2338 test the index for the appropriate mode. */
2339 ARM_GO_IF_LEGITIMATE_INDEX (mode, 0, offset, win);
2341 if (!no_new_pseudos)
2342 offset = force_reg (Pmode, offset);
2347 if (GET_CODE (offset) == CONST_INT)
2348 return plus_constant (base, INTVAL (offset));
2351 if (GET_MODE_SIZE (mode) > 4
2352 && (GET_MODE_CLASS (mode) == MODE_INT
2353 || TARGET_SOFT_FLOAT))
2355 emit_insn (gen_addsi3 (reg, base, offset));
2359 return gen_rtx_PLUS (Pmode, base, offset);
2365 /* Generate code to load the PIC register. PROLOGUE is true if
2366 called from arm_expand_prologue (in which case we want the
2367 generated insns at the start of the function); false if called
2368 by an exception receiver that needs the PIC register reloaded
2369 (in which case the insns are just dumped at the current location). */
2372 arm_finalize_pic (prologue)
2373 int prologue ATTRIBUTE_UNUSED;
2375 #ifndef AOF_ASSEMBLER
2376 rtx l1, pic_tmp, pic_tmp2, seq, pic_rtx;
2377 rtx global_offset_table;
2379 if (current_function_uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE)
2386 l1 = gen_label_rtx ();
2388 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
2389 /* On the ARM the PC register contains 'dot + 8' at the time of the
2390 addition, on the Thumb it is 'dot + 4'. */
2391 pic_tmp = plus_constant (gen_rtx_LABEL_REF (Pmode, l1), TARGET_ARM ? 8 : 4);
2393 pic_tmp2 = gen_rtx_CONST (VOIDmode,
2394 gen_rtx_PLUS (Pmode, global_offset_table, pc_rtx));
2396 pic_tmp2 = gen_rtx_CONST (VOIDmode, global_offset_table);
2398 pic_rtx = gen_rtx_CONST (Pmode, gen_rtx_MINUS (Pmode, pic_tmp2, pic_tmp));
2402 emit_insn (gen_pic_load_addr_arm (pic_offset_table_rtx, pic_rtx));
2403 emit_insn (gen_pic_add_dot_plus_eight (pic_offset_table_rtx, l1));
2407 emit_insn (gen_pic_load_addr_thumb (pic_offset_table_rtx, pic_rtx));
2408 emit_insn (gen_pic_add_dot_plus_four (pic_offset_table_rtx, l1));
2411 seq = gen_sequence ();
2414 emit_insn_after (seq, get_insns ());
2418 /* Need to emit this whether or not we obey regdecls,
2419 since setjmp/longjmp can cause life info to screw up. */
2420 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
2421 #endif /* AOF_ASSEMBLER */
2424 #define REG_OR_SUBREG_REG(X) \
2425 (GET_CODE (X) == REG \
2426 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
2428 #define REG_OR_SUBREG_RTX(X) \
2429 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
2431 #ifndef COSTS_N_INSNS
2432 #define COSTS_N_INSNS(N) ((N) * 4 - 2)
2436 arm_rtx_costs (x, code, outer)
2439 enum rtx_code outer;
2441 enum machine_mode mode = GET_MODE (x);
2442 enum rtx_code subcode;
2458 return COSTS_N_INSNS (1);
2461 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
2464 unsigned HOST_WIDE_INT i = INTVAL (XEXP (x, 1));
2471 return COSTS_N_INSNS (2) + cycles;
2473 return COSTS_N_INSNS (1) + 16;
2476 return (COSTS_N_INSNS (1)
2477 + 4 * ((GET_CODE (SET_SRC (x)) == MEM)
2478 + GET_CODE (SET_DEST (x)) == MEM));
2483 if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256)
2485 if (thumb_shiftable_const (INTVAL (x)))
2486 return COSTS_N_INSNS (2);
2487 return COSTS_N_INSNS (3);
2489 else if (outer == PLUS
2490 && INTVAL (x) < 256 && INTVAL (x) > -256)
2492 else if (outer == COMPARE
2493 && (unsigned HOST_WIDE_INT) INTVAL (x) < 256)
2495 else if (outer == ASHIFT || outer == ASHIFTRT
2496 || outer == LSHIFTRT)
2498 return COSTS_N_INSNS (2);
2504 return COSTS_N_INSNS (3);
2523 /* XXX another guess. */
2524 /* Memory costs quite a lot for the first word, but subsequent words
2525 load at the equivalent of a single insn each. */
2526 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
2527 + (CONSTANT_POOL_ADDRESS_P (x) ? 4 : 0));
2531 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
2536 /* XXX still guessing. */
2537 switch (GET_MODE (XEXP (x, 0)))
2540 return (1 + (mode == DImode ? 4 : 0)
2541 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
2544 return (4 + (mode == DImode ? 4 : 0)
2545 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
2548 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
2562 fprintf (stderr, "unexpected code for thumb in rtx_costs: %s\n",
2572 /* Memory costs quite a lot for the first word, but subsequent words
2573 load at the equivalent of a single insn each. */
2574 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
2575 + (CONSTANT_POOL_ADDRESS_P (x) ? 4 : 0));
2582 if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG)
2589 case ASHIFT: case LSHIFTRT: case ASHIFTRT:
2591 return (8 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : 8)
2592 + ((GET_CODE (XEXP (x, 0)) == REG
2593 || (GET_CODE (XEXP (x, 0)) == SUBREG
2594 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
2596 return (1 + ((GET_CODE (XEXP (x, 0)) == REG
2597 || (GET_CODE (XEXP (x, 0)) == SUBREG
2598 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
2600 + ((GET_CODE (XEXP (x, 1)) == REG
2601 || (GET_CODE (XEXP (x, 1)) == SUBREG
2602 && GET_CODE (SUBREG_REG (XEXP (x, 1))) == REG)
2603 || (GET_CODE (XEXP (x, 1)) == CONST_INT))
2608 return (4 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 8)
2609 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
2610 || (GET_CODE (XEXP (x, 0)) == CONST_INT
2611 && const_ok_for_arm (INTVAL (XEXP (x, 0)))))
2614 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
2615 return (2 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
2616 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
2617 && const_double_rtx_ok_for_fpu (XEXP (x, 1))))
2619 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
2620 || (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE
2621 && const_double_rtx_ok_for_fpu (XEXP (x, 0))))
2624 if (((GET_CODE (XEXP (x, 0)) == CONST_INT
2625 && const_ok_for_arm (INTVAL (XEXP (x, 0)))
2626 && REG_OR_SUBREG_REG (XEXP (x, 1))))
2627 || (((subcode = GET_CODE (XEXP (x, 1))) == ASHIFT
2628 || subcode == ASHIFTRT || subcode == LSHIFTRT
2629 || subcode == ROTATE || subcode == ROTATERT
2631 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
2632 && ((INTVAL (XEXP (XEXP (x, 1), 1)) &
2633 (INTVAL (XEXP (XEXP (x, 1), 1)) - 1)) == 0)))
2634 && REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 0))
2635 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 1))
2636 || GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT)
2637 && REG_OR_SUBREG_REG (XEXP (x, 0))))
2642 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
2643 return (2 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
2644 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
2645 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
2646 && const_double_rtx_ok_for_fpu (XEXP (x, 1))))
2650 case AND: case XOR: case IOR:
2653 /* Normally the frame registers will be spilt into reg+const during
2654 reload, so it is a bad idea to combine them with other instructions,
2655 since then they might not be moved outside of loops. As a compromise
2656 we allow integration with ops that have a constant as their second
2658 if ((REG_OR_SUBREG_REG (XEXP (x, 0))
2659 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))
2660 && GET_CODE (XEXP (x, 1)) != CONST_INT)
2661 || (REG_OR_SUBREG_REG (XEXP (x, 0))
2662 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))))
2666 return (4 + extra_cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
2667 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
2668 || (GET_CODE (XEXP (x, 1)) == CONST_INT
2669 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
2672 if (REG_OR_SUBREG_REG (XEXP (x, 0)))
2673 return (1 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : extra_cost)
2674 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
2675 || (GET_CODE (XEXP (x, 1)) == CONST_INT
2676 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
2679 else if (REG_OR_SUBREG_REG (XEXP (x, 1)))
2680 return (1 + extra_cost
2681 + ((((subcode = GET_CODE (XEXP (x, 0))) == ASHIFT
2682 || subcode == LSHIFTRT || subcode == ASHIFTRT
2683 || subcode == ROTATE || subcode == ROTATERT
2685 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2686 && ((INTVAL (XEXP (XEXP (x, 0), 1)) &
2687 (INTVAL (XEXP (XEXP (x, 0), 1)) - 1)) == 0)))
2688 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 0)))
2689 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 1)))
2690 || GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))
2696 /* There is no point basing this on the tuning, since it is always the
2697 fast variant if it exists at all. */
2698 if (arm_fast_multiply && mode == DImode
2699 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
2700 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
2701 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
2704 if (GET_MODE_CLASS (mode) == MODE_FLOAT
2708 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
2710 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
2711 & (unsigned HOST_WIDE_INT) 0xffffffff);
2712 int add_cost = const_ok_for_arm (i) ? 4 : 8;
2715 /* Tune as appropriate. */
2716 int booth_unit_size = ((tune_flags & FL_FAST_MULT) ? 8 : 2);
2718 for (j = 0; i && j < 32; j += booth_unit_size)
2720 i >>= booth_unit_size;
2727 return (((tune_flags & FL_FAST_MULT) ? 8 : 30)
2728 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
2729 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4));
2732 if (arm_fast_multiply && mode == SImode
2733 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
2734 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
2735 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0))
2736 == GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)))
2737 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ZERO_EXTEND
2738 || GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SIGN_EXTEND))
2743 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
2744 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 6);
2748 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
2750 return 1 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
2753 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
2761 return 4 + (mode == DImode ? 4 : 0);
2764 if (GET_MODE (XEXP (x, 0)) == QImode)
2765 return (4 + (mode == DImode ? 4 : 0)
2766 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
2769 switch (GET_MODE (XEXP (x, 0)))
2772 return (1 + (mode == DImode ? 4 : 0)
2773 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
2776 return (4 + (mode == DImode ? 4 : 0)
2777 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
2780 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
2788 if (const_ok_for_arm (INTVAL (x)))
2789 return outer == SET ? 2 : -1;
2790 else if (outer == AND
2791 && const_ok_for_arm (~INTVAL (x)))
2793 else if ((outer == COMPARE
2794 || outer == PLUS || outer == MINUS)
2795 && const_ok_for_arm (-INTVAL (x)))
2806 if (const_double_rtx_ok_for_fpu (x))
2807 return outer == SET ? 2 : -1;
2808 else if ((outer == COMPARE || outer == PLUS)
2809 && neg_const_double_rtx_ok_for_fpu (x))
2819 arm_adjust_cost (insn, link, dep, cost)
2827 /* Some true dependencies can have a higher cost depending
2828 on precisely how certain input operands are used. */
2830 && REG_NOTE_KIND (link) == 0
2831 && recog_memoized (insn) < 0
2832 && recog_memoized (dep) < 0)
2834 int shift_opnum = get_attr_shift (insn);
2835 enum attr_type attr_type = get_attr_type (dep);
2837 /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted
2838 operand for INSN. If we have a shifted input operand and the
2839 instruction we depend on is another ALU instruction, then we may
2840 have to account for an additional stall. */
2841 if (shift_opnum != 0 && attr_type == TYPE_NORMAL)
2843 rtx shifted_operand;
2846 /* Get the shifted operand. */
2847 extract_insn (insn);
2848 shifted_operand = recog_data.operand[shift_opnum];
2850 /* Iterate over all the operands in DEP. If we write an operand
2851 that overlaps with SHIFTED_OPERAND, then we have increase the
2852 cost of this dependency. */
2854 preprocess_constraints ();
2855 for (opno = 0; opno < recog_data.n_operands; opno++)
2857 /* We can ignore strict inputs. */
2858 if (recog_data.operand_type[opno] == OP_IN)
2861 if (reg_overlap_mentioned_p (recog_data.operand[opno],
2868 /* XXX This is not strictly true for the FPA. */
2869 if (REG_NOTE_KIND (link) == REG_DEP_ANTI
2870 || REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
2873 /* Call insns don't incur a stall, even if they follow a load. */
2874 if (REG_NOTE_KIND (link) == 0
2875 && GET_CODE (insn) == CALL_INSN)
2878 if ((i_pat = single_set (insn)) != NULL
2879 && GET_CODE (SET_SRC (i_pat)) == MEM
2880 && (d_pat = single_set (dep)) != NULL
2881 && GET_CODE (SET_DEST (d_pat)) == MEM)
2883 /* This is a load after a store, there is no conflict if the load reads
2884 from a cached area. Assume that loads from the stack, and from the
2885 constant pool are cached, and that others will miss. This is a
2888 if (CONSTANT_POOL_ADDRESS_P (XEXP (SET_SRC (i_pat), 0))
2889 || reg_mentioned_p (stack_pointer_rtx, XEXP (SET_SRC (i_pat), 0))
2890 || reg_mentioned_p (frame_pointer_rtx, XEXP (SET_SRC (i_pat), 0))
2891 || reg_mentioned_p (hard_frame_pointer_rtx,
2892 XEXP (SET_SRC (i_pat), 0)))
2899 /* This code has been fixed for cross compilation. */
2901 static int fpa_consts_inited = 0;
2903 static const char *const strings_fpa[8] =
2906 "4", "5", "0.5", "10"
2909 static REAL_VALUE_TYPE values_fpa[8];
2917 for (i = 0; i < 8; i++)
2919 r = REAL_VALUE_ATOF (strings_fpa[i], DFmode);
2923 fpa_consts_inited = 1;
2926 /* Return TRUE if rtx X is a valid immediate FPU constant. */
2929 const_double_rtx_ok_for_fpu (x)
2935 if (!fpa_consts_inited)
2938 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
2939 if (REAL_VALUE_MINUS_ZERO (r))
2942 for (i = 0; i < 8; i++)
2943 if (REAL_VALUES_EQUAL (r, values_fpa[i]))
2949 /* Return TRUE if rtx X is a valid immediate FPU constant. */
2952 neg_const_double_rtx_ok_for_fpu (x)
2958 if (!fpa_consts_inited)
2961 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
2962 r = REAL_VALUE_NEGATE (r);
2963 if (REAL_VALUE_MINUS_ZERO (r))
2966 for (i = 0; i < 8; i++)
2967 if (REAL_VALUES_EQUAL (r, values_fpa[i]))
2973 /* Predicates for `match_operand' and `match_operator'. */
2975 /* s_register_operand is the same as register_operand, but it doesn't accept
2978 This function exists because at the time it was put in it led to better
2979 code. SUBREG(MEM) always needs a reload in the places where
2980 s_register_operand is used, and this seemed to lead to excessive
2984 s_register_operand (op, mode)
2986 enum machine_mode mode;
2988 if (GET_MODE (op) != mode && mode != VOIDmode)
2991 if (GET_CODE (op) == SUBREG)
2992 op = SUBREG_REG (op);
2994 /* We don't consider registers whose class is NO_REGS
2995 to be a register operand. */
2996 /* XXX might have to check for lo regs only for thumb ??? */
2997 return (GET_CODE (op) == REG
2998 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
2999 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
3002 /* A hard register operand (even before reload. */
3004 arm_hard_register_operand (op, mode)
3006 enum machine_mode mode;
3008 if (GET_MODE (op) != mode && mode != VOIDmode)
3011 return (GET_CODE (op) == REG
3012 && REGNO (op) < FIRST_PSEUDO_REGISTER);
3015 /* Only accept reg, subreg(reg), const_int. */
3018 reg_or_int_operand (op, mode)
3020 enum machine_mode mode;
3022 if (GET_CODE (op) == CONST_INT)
3025 if (GET_MODE (op) != mode && mode != VOIDmode)
3028 if (GET_CODE (op) == SUBREG)
3029 op = SUBREG_REG (op);
3031 /* We don't consider registers whose class is NO_REGS
3032 to be a register operand. */
3033 return (GET_CODE (op) == REG
3034 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
3035 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
3038 /* Return 1 if OP is an item in memory, given that we are in reload. */
3041 arm_reload_memory_operand (op, mode)
3043 enum machine_mode mode ATTRIBUTE_UNUSED;
3045 int regno = true_regnum (op);
3047 return (!CONSTANT_P (op)
3049 || (GET_CODE (op) == REG
3050 && REGNO (op) >= FIRST_PSEUDO_REGISTER)));
3053 /* Return 1 if OP is a valid memory address, but not valid for a signed byte
3054 memory access (architecture V4).
3055 MODE is QImode if called when computing constraints, or VOIDmode when
3056 emitting patterns. In this latter case we cannot use memory_operand()
3057 because it will fail on badly formed MEMs, which is precisly what we are
3060 bad_signed_byte_operand (op, mode)
3062 enum machine_mode mode ATTRIBUTE_UNUSED;
3065 if ((mode == QImode && !memory_operand (op, mode)) || GET_CODE (op) != MEM)
3068 if (GET_CODE (op) != MEM)
3073 /* A sum of anything more complex than reg + reg or reg + const is bad. */
3074 if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS)
3075 && (!s_register_operand (XEXP (op, 0), VOIDmode)
3076 || (!s_register_operand (XEXP (op, 1), VOIDmode)
3077 && GET_CODE (XEXP (op, 1)) != CONST_INT)))
3080 /* Big constants are also bad. */
3081 if (GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT
3082 && (INTVAL (XEXP (op, 1)) > 0xff
3083 || -INTVAL (XEXP (op, 1)) > 0xff))
3086 /* Everything else is good, or can will automatically be made so. */
3090 /* Return TRUE for valid operands for the rhs of an ARM instruction. */
3093 arm_rhs_operand (op, mode)
3095 enum machine_mode mode;
3097 return (s_register_operand (op, mode)
3098 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op))));
3101 /* Return TRUE for valid operands for the rhs of an ARM instruction, or a load.
3105 arm_rhsm_operand (op, mode)
3107 enum machine_mode mode;
3109 return (s_register_operand (op, mode)
3110 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op)))
3111 || memory_operand (op, mode));
3114 /* Return TRUE for valid operands for the rhs of an ARM instruction, or if a
3115 constant that is valid when negated. */
3118 arm_add_operand (op, mode)
3120 enum machine_mode mode;
3123 return thumb_cmp_operand (op, mode);
3125 return (s_register_operand (op, mode)
3126 || (GET_CODE (op) == CONST_INT
3127 && (const_ok_for_arm (INTVAL (op))
3128 || const_ok_for_arm (-INTVAL (op)))));
3132 arm_not_operand (op, mode)
3134 enum machine_mode mode;
3136 return (s_register_operand (op, mode)
3137 || (GET_CODE (op) == CONST_INT
3138 && (const_ok_for_arm (INTVAL (op))
3139 || const_ok_for_arm (~INTVAL (op)))));
3142 /* Return TRUE if the operand is a memory reference which contains an
3143 offsettable address. */
3145 offsettable_memory_operand (op, mode)
3147 enum machine_mode mode;
3149 if (mode == VOIDmode)
3150 mode = GET_MODE (op);
3152 return (mode == GET_MODE (op)
3153 && GET_CODE (op) == MEM
3154 && offsettable_address_p (reload_completed | reload_in_progress,
3155 mode, XEXP (op, 0)));
3158 /* Return TRUE if the operand is a memory reference which is, or can be
3159 made word aligned by adjusting the offset. */
3161 alignable_memory_operand (op, mode)
3163 enum machine_mode mode;
3167 if (mode == VOIDmode)
3168 mode = GET_MODE (op);
3170 if (mode != GET_MODE (op) || GET_CODE (op) != MEM)
3175 return ((GET_CODE (reg = op) == REG
3176 || (GET_CODE (op) == SUBREG
3177 && GET_CODE (reg = SUBREG_REG (op)) == REG)
3178 || (GET_CODE (op) == PLUS
3179 && GET_CODE (XEXP (op, 1)) == CONST_INT
3180 && (GET_CODE (reg = XEXP (op, 0)) == REG
3181 || (GET_CODE (XEXP (op, 0)) == SUBREG
3182 && GET_CODE (reg = SUBREG_REG (XEXP (op, 0))) == REG))))
3183 && REGNO_POINTER_ALIGN (REGNO (reg)) >= 32);
3186 /* Similar to s_register_operand, but does not allow hard integer
3189 f_register_operand (op, mode)
3191 enum machine_mode mode;
3193 if (GET_MODE (op) != mode && mode != VOIDmode)
3196 if (GET_CODE (op) == SUBREG)
3197 op = SUBREG_REG (op);
3199 /* We don't consider registers whose class is NO_REGS
3200 to be a register operand. */
3201 return (GET_CODE (op) == REG
3202 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
3203 || REGNO_REG_CLASS (REGNO (op)) == FPU_REGS));
3206 /* Return TRUE for valid operands for the rhs of an FPU instruction. */
3209 fpu_rhs_operand (op, mode)
3211 enum machine_mode mode;
3213 if (s_register_operand (op, mode))
3216 if (GET_MODE (op) != mode && mode != VOIDmode)
3219 if (GET_CODE (op) == CONST_DOUBLE)
3220 return const_double_rtx_ok_for_fpu (op);
3226 fpu_add_operand (op, mode)
3228 enum machine_mode mode;
3230 if (s_register_operand (op, mode))
3233 if (GET_MODE (op) != mode && mode != VOIDmode)
3236 if (GET_CODE (op) == CONST_DOUBLE)
3237 return (const_double_rtx_ok_for_fpu (op)
3238 || neg_const_double_rtx_ok_for_fpu (op));
3243 /* Return nonzero if OP is a constant power of two. */
3246 power_of_two_operand (op, mode)
3248 enum machine_mode mode ATTRIBUTE_UNUSED;
3250 if (GET_CODE (op) == CONST_INT)
3252 HOST_WIDE_INT value = INTVAL (op);
3253 return value != 0 && (value & (value - 1)) == 0;
3258 /* Return TRUE for a valid operand of a DImode operation.
3259 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
3260 Note that this disallows MEM(REG+REG), but allows
3261 MEM(PRE/POST_INC/DEC(REG)). */
3264 di_operand (op, mode)
3266 enum machine_mode mode;
3268 if (s_register_operand (op, mode))
3271 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && GET_MODE (op) != DImode)
3274 if (GET_CODE (op) == SUBREG)
3275 op = SUBREG_REG (op);
3277 switch (GET_CODE (op))
3284 return memory_address_p (DImode, XEXP (op, 0));
3291 /* Like di_operand, but don't accept constants. */
3293 nonimmediate_di_operand (op, mode)
3295 enum machine_mode mode;
3297 if (s_register_operand (op, mode))
3300 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && GET_MODE (op) != DImode)
3303 if (GET_CODE (op) == SUBREG)
3304 op = SUBREG_REG (op);
3306 if (GET_CODE (op) == MEM)
3307 return memory_address_p (DImode, XEXP (op, 0));
3312 /* Return TRUE for a valid operand of a DFmode operation when -msoft-float.
3313 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
3314 Note that this disallows MEM(REG+REG), but allows
3315 MEM(PRE/POST_INC/DEC(REG)). */
3318 soft_df_operand (op, mode)
3320 enum machine_mode mode;
3322 if (s_register_operand (op, mode))
3325 if (mode != VOIDmode && GET_MODE (op) != mode)
3328 if (GET_CODE (op) == SUBREG && CONSTANT_P (SUBREG_REG (op)))
3331 if (GET_CODE (op) == SUBREG)
3332 op = SUBREG_REG (op);
3334 switch (GET_CODE (op))
3340 return memory_address_p (DFmode, XEXP (op, 0));
3347 /* Like soft_df_operand, but don't accept constants. */
3349 nonimmediate_soft_df_operand (op, mode)
3351 enum machine_mode mode;
3353 if (s_register_operand (op, mode))
3356 if (mode != VOIDmode && GET_MODE (op) != mode)
3359 if (GET_CODE (op) == SUBREG)
3360 op = SUBREG_REG (op);
3362 if (GET_CODE (op) == MEM)
3363 return memory_address_p (DFmode, XEXP (op, 0));
3367 /* Return TRUE for valid index operands. */
3369 index_operand (op, mode)
3371 enum machine_mode mode;
3373 return (s_register_operand (op, mode)
3374 || (immediate_operand (op, mode)
3375 && (GET_CODE (op) != CONST_INT
3376 || (INTVAL (op) < 4096 && INTVAL (op) > -4096))));
3379 /* Return TRUE for valid shifts by a constant. This also accepts any
3380 power of two on the (somewhat overly relaxed) assumption that the
3381 shift operator in this case was a mult. */
3384 const_shift_operand (op, mode)
3386 enum machine_mode mode;
3388 return (power_of_two_operand (op, mode)
3389 || (immediate_operand (op, mode)
3390 && (GET_CODE (op) != CONST_INT
3391 || (INTVAL (op) < 32 && INTVAL (op) > 0))));
3394 /* Return TRUE for arithmetic operators which can be combined with a multiply
3398 shiftable_operator (x, mode)
3400 enum machine_mode mode;
3402 if (GET_MODE (x) != mode)
3406 enum rtx_code code = GET_CODE (x);
3408 return (code == PLUS || code == MINUS
3409 || code == IOR || code == XOR || code == AND);
3413 /* Return TRUE for binary logical operators. */
3416 logical_binary_operator (x, mode)
3418 enum machine_mode mode;
3420 if (GET_MODE (x) != mode)
3424 enum rtx_code code = GET_CODE (x);
3426 return (code == IOR || code == XOR || code == AND);
3430 /* Return TRUE for shift operators. */
3433 shift_operator (x, mode)
3435 enum machine_mode mode;
3437 if (GET_MODE (x) != mode)
3441 enum rtx_code code = GET_CODE (x);
3444 return power_of_two_operand (XEXP (x, 1), mode);
3446 return (code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT
3447 || code == ROTATERT);
3451 /* Return TRUE if x is EQ or NE. */
3453 equality_operator (x, mode)
3455 enum machine_mode mode ATTRIBUTE_UNUSED;
3457 return GET_CODE (x) == EQ || GET_CODE (x) == NE;
3460 /* Return TRUE if x is a comparison operator other than LTGT or UNEQ. */
3462 arm_comparison_operator (x, mode)
3464 enum machine_mode mode;
3466 return (comparison_operator (x, mode)
3467 && GET_CODE (x) != LTGT
3468 && GET_CODE (x) != UNEQ);
3471 /* Return TRUE for SMIN SMAX UMIN UMAX operators. */
3473 minmax_operator (x, mode)
3475 enum machine_mode mode;
3477 enum rtx_code code = GET_CODE (x);
3479 if (GET_MODE (x) != mode)
3482 return code == SMIN || code == SMAX || code == UMIN || code == UMAX;
3485 /* Return TRUE if this is the condition code register, if we aren't given
3486 a mode, accept any class CCmode register. */
3488 cc_register (x, mode)
3490 enum machine_mode mode;
3492 if (mode == VOIDmode)
3494 mode = GET_MODE (x);
3496 if (GET_MODE_CLASS (mode) != MODE_CC)
3500 if ( GET_MODE (x) == mode
3501 && GET_CODE (x) == REG
3502 && REGNO (x) == CC_REGNUM)
3508 /* Return TRUE if this is the condition code register, if we aren't given
3509 a mode, accept any class CCmode register which indicates a dominance
3512 dominant_cc_register (x, mode)
3514 enum machine_mode mode;
3516 if (mode == VOIDmode)
3518 mode = GET_MODE (x);
3520 if (GET_MODE_CLASS (mode) != MODE_CC)
3524 if ( mode != CC_DNEmode && mode != CC_DEQmode
3525 && mode != CC_DLEmode && mode != CC_DLTmode
3526 && mode != CC_DGEmode && mode != CC_DGTmode
3527 && mode != CC_DLEUmode && mode != CC_DLTUmode
3528 && mode != CC_DGEUmode && mode != CC_DGTUmode)
3531 return cc_register (x, mode);
3534 /* Return TRUE if X references a SYMBOL_REF. */
3536 symbol_mentioned_p (x)
3539 register const char * fmt;
3542 if (GET_CODE (x) == SYMBOL_REF)
3545 fmt = GET_RTX_FORMAT (GET_CODE (x));
3547 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
3553 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3554 if (symbol_mentioned_p (XVECEXP (x, i, j)))
3557 else if (fmt[i] == 'e' && symbol_mentioned_p (XEXP (x, i)))
3564 /* Return TRUE if X references a LABEL_REF. */
3566 label_mentioned_p (x)
3569 register const char * fmt;
3572 if (GET_CODE (x) == LABEL_REF)
3575 fmt = GET_RTX_FORMAT (GET_CODE (x));
3576 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
3582 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3583 if (label_mentioned_p (XVECEXP (x, i, j)))
3586 else if (fmt[i] == 'e' && label_mentioned_p (XEXP (x, i)))
3597 enum rtx_code code = GET_CODE (x);
3601 else if (code == SMIN)
3603 else if (code == UMIN)
3605 else if (code == UMAX)
3611 /* Return 1 if memory locations are adjacent. */
3613 adjacent_mem_locations (a, b)
3616 int val0 = 0, val1 = 0;
3619 if ((GET_CODE (XEXP (a, 0)) == REG
3620 || (GET_CODE (XEXP (a, 0)) == PLUS
3621 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
3622 && (GET_CODE (XEXP (b, 0)) == REG
3623 || (GET_CODE (XEXP (b, 0)) == PLUS
3624 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
3626 if (GET_CODE (XEXP (a, 0)) == PLUS)
3628 reg0 = REGNO (XEXP (XEXP (a, 0), 0));
3629 val0 = INTVAL (XEXP (XEXP (a, 0), 1));
3632 reg0 = REGNO (XEXP (a, 0));
3633 if (GET_CODE (XEXP (b, 0)) == PLUS)
3635 reg1 = REGNO (XEXP (XEXP (b, 0), 0));
3636 val1 = INTVAL (XEXP (XEXP (b, 0), 1));
3639 reg1 = REGNO (XEXP (b, 0));
3640 return (reg0 == reg1) && ((val1 - val0) == 4 || (val0 - val1) == 4);
3645 /* Return 1 if OP is a load multiple operation. It is known to be
3646 parallel and the first section will be tested. */
3648 load_multiple_operation (op, mode)
3650 enum machine_mode mode ATTRIBUTE_UNUSED;
3652 HOST_WIDE_INT count = XVECLEN (op, 0);
3655 HOST_WIDE_INT i = 1, base = 0;
3659 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
3662 /* Check to see if this might be a write-back. */
3663 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
3668 /* Now check it more carefully. */
3669 if (GET_CODE (SET_DEST (elt)) != REG
3670 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
3671 || REGNO (XEXP (SET_SRC (elt), 0)) != REGNO (SET_DEST (elt))
3672 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
3673 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4)
3677 /* Perform a quick check so we don't blow up below. */
3679 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
3680 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != REG
3681 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != MEM)
3684 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, i - 1)));
3685 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, i - 1)), 0);
3687 for (; i < count; i++)
3689 elt = XVECEXP (op, 0, i);
3691 if (GET_CODE (elt) != SET
3692 || GET_CODE (SET_DEST (elt)) != REG
3693 || GET_MODE (SET_DEST (elt)) != SImode
3694 || REGNO (SET_DEST (elt)) != (unsigned int)(dest_regno + i - base)
3695 || GET_CODE (SET_SRC (elt)) != MEM
3696 || GET_MODE (SET_SRC (elt)) != SImode
3697 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
3698 || !rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
3699 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
3700 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != (i - base) * 4)
3707 /* Return 1 if OP is a store multiple operation. It is known to be
3708 parallel and the first section will be tested. */
3710 store_multiple_operation (op, mode)
3712 enum machine_mode mode ATTRIBUTE_UNUSED;
3714 HOST_WIDE_INT count = XVECLEN (op, 0);
3717 HOST_WIDE_INT i = 1, base = 0;
3721 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
3724 /* Check to see if this might be a write-back. */
3725 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
3730 /* Now check it more carefully. */
3731 if (GET_CODE (SET_DEST (elt)) != REG
3732 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
3733 || REGNO (XEXP (SET_SRC (elt), 0)) != REGNO (SET_DEST (elt))
3734 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
3735 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4)
3739 /* Perform a quick check so we don't blow up below. */
3741 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
3742 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != MEM
3743 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != REG)
3746 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, i - 1)));
3747 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, i - 1)), 0);
3749 for (; i < count; i++)
3751 elt = XVECEXP (op, 0, i);
3753 if (GET_CODE (elt) != SET
3754 || GET_CODE (SET_SRC (elt)) != REG
3755 || GET_MODE (SET_SRC (elt)) != SImode
3756 || REGNO (SET_SRC (elt)) != (unsigned int)(src_regno + i - base)
3757 || GET_CODE (SET_DEST (elt)) != MEM
3758 || GET_MODE (SET_DEST (elt)) != SImode
3759 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
3760 || !rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
3761 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
3762 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != (i - base) * 4)
3770 load_multiple_sequence (operands, nops, regs, base, load_offset)
3775 HOST_WIDE_INT * load_offset;
3777 int unsorted_regs[4];
3778 HOST_WIDE_INT unsorted_offsets[4];
3783 /* Can only handle 2, 3, or 4 insns at present, though could be easily
3784 extended if required. */
3785 if (nops < 2 || nops > 4)
3788 /* Loop over the operands and check that the memory references are
3789 suitable (ie immediate offsets from the same base register). At
3790 the same time, extract the target register, and the memory
3792 for (i = 0; i < nops; i++)
3797 /* Convert a subreg of a mem into the mem itself. */
3798 if (GET_CODE (operands[nops + i]) == SUBREG)
3799 operands[nops + i] = alter_subreg (operands + (nops + i));
3801 if (GET_CODE (operands[nops + i]) != MEM)
3804 /* Don't reorder volatile memory references; it doesn't seem worth
3805 looking for the case where the order is ok anyway. */
3806 if (MEM_VOLATILE_P (operands[nops + i]))
3809 offset = const0_rtx;
3811 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
3812 || (GET_CODE (reg) == SUBREG
3813 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
3814 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
3815 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
3817 || (GET_CODE (reg) == SUBREG
3818 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
3819 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
3824 base_reg = REGNO (reg);
3825 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
3826 ? REGNO (operands[i])
3827 : REGNO (SUBREG_REG (operands[i])));
3832 if (base_reg != (int) REGNO (reg))
3833 /* Not addressed from the same base register. */
3836 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
3837 ? REGNO (operands[i])
3838 : REGNO (SUBREG_REG (operands[i])));
3839 if (unsorted_regs[i] < unsorted_regs[order[0]])
3843 /* If it isn't an integer register, or if it overwrites the
3844 base register but isn't the last insn in the list, then
3845 we can't do this. */
3846 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14
3847 || (i != nops - 1 && unsorted_regs[i] == base_reg))
3850 unsorted_offsets[i] = INTVAL (offset);
3853 /* Not a suitable memory address. */
3857 /* All the useful information has now been extracted from the
3858 operands into unsorted_regs and unsorted_offsets; additionally,
3859 order[0] has been set to the lowest numbered register in the
3860 list. Sort the registers into order, and check that the memory
3861 offsets are ascending and adjacent. */
3863 for (i = 1; i < nops; i++)
3867 order[i] = order[i - 1];
3868 for (j = 0; j < nops; j++)
3869 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
3870 && (order[i] == order[i - 1]
3871 || unsorted_regs[j] < unsorted_regs[order[i]]))
3874 /* Have we found a suitable register? if not, one must be used more
3876 if (order[i] == order[i - 1])
3879 /* Is the memory address adjacent and ascending? */
3880 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
3888 for (i = 0; i < nops; i++)
3889 regs[i] = unsorted_regs[order[i]];
3891 *load_offset = unsorted_offsets[order[0]];
3894 if (unsorted_offsets[order[0]] == 0)
3895 return 1; /* ldmia */
3897 if (unsorted_offsets[order[0]] == 4)
3898 return 2; /* ldmib */
3900 if (unsorted_offsets[order[nops - 1]] == 0)
3901 return 3; /* ldmda */
3903 if (unsorted_offsets[order[nops - 1]] == -4)
3904 return 4; /* ldmdb */
3906 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
3907 if the offset isn't small enough. The reason 2 ldrs are faster
3908 is because these ARMs are able to do more than one cache access
3909 in a single cycle. The ARM9 and StrongARM have Harvard caches,
3910 whilst the ARM8 has a double bandwidth cache. This means that
3911 these cores can do both an instruction fetch and a data fetch in
3912 a single cycle, so the trick of calculating the address into a
3913 scratch register (one of the result regs) and then doing a load
3914 multiple actually becomes slower (and no smaller in code size).
3915 That is the transformation
3917 ldr rd1, [rbase + offset]
3918 ldr rd2, [rbase + offset + 4]
3922 add rd1, rbase, offset
3923 ldmia rd1, {rd1, rd2}
3925 produces worse code -- '3 cycles + any stalls on rd2' instead of
3926 '2 cycles + any stalls on rd2'. On ARMs with only one cache
3927 access per cycle, the first sequence could never complete in less
3928 than 6 cycles, whereas the ldm sequence would only take 5 and
3929 would make better use of sequential accesses if not hitting the
3932 We cheat here and test 'arm_ld_sched' which we currently know to
3933 only be true for the ARM8, ARM9 and StrongARM. If this ever
3934 changes, then the test below needs to be reworked. */
3935 if (nops == 2 && arm_ld_sched)
3938 /* Can't do it without setting up the offset, only do this if it takes
3939 no more than one insn. */
3940 return (const_ok_for_arm (unsorted_offsets[order[0]])
3941 || const_ok_for_arm (-unsorted_offsets[order[0]])) ? 5 : 0;
3945 emit_ldm_seq (operands, nops)
3951 HOST_WIDE_INT offset;
3955 switch (load_multiple_sequence (operands, nops, regs, &base_reg, &offset))
3958 strcpy (buf, "ldm%?ia\t");
3962 strcpy (buf, "ldm%?ib\t");
3966 strcpy (buf, "ldm%?da\t");
3970 strcpy (buf, "ldm%?db\t");
3975 sprintf (buf, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
3976 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
3979 sprintf (buf, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
3980 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
3982 output_asm_insn (buf, operands);
3984 strcpy (buf, "ldm%?ia\t");
3991 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
3992 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
3994 for (i = 1; i < nops; i++)
3995 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
3996 reg_names[regs[i]]);
3998 strcat (buf, "}\t%@ phole ldm");
4000 output_asm_insn (buf, operands);
4005 store_multiple_sequence (operands, nops, regs, base, load_offset)
4010 HOST_WIDE_INT * load_offset;
4012 int unsorted_regs[4];
4013 HOST_WIDE_INT unsorted_offsets[4];
4018 /* Can only handle 2, 3, or 4 insns at present, though could be easily
4019 extended if required. */
4020 if (nops < 2 || nops > 4)
4023 /* Loop over the operands and check that the memory references are
4024 suitable (ie immediate offsets from the same base register). At
4025 the same time, extract the target register, and the memory
4027 for (i = 0; i < nops; i++)
4032 /* Convert a subreg of a mem into the mem itself. */
4033 if (GET_CODE (operands[nops + i]) == SUBREG)
4034 operands[nops + i] = alter_subreg (operands + (nops + i));
4036 if (GET_CODE (operands[nops + i]) != MEM)
4039 /* Don't reorder volatile memory references; it doesn't seem worth
4040 looking for the case where the order is ok anyway. */
4041 if (MEM_VOLATILE_P (operands[nops + i]))
4044 offset = const0_rtx;
4046 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
4047 || (GET_CODE (reg) == SUBREG
4048 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
4049 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
4050 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
4052 || (GET_CODE (reg) == SUBREG
4053 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
4054 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
4059 base_reg = REGNO (reg);
4060 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
4061 ? REGNO (operands[i])
4062 : REGNO (SUBREG_REG (operands[i])));
4067 if (base_reg != (int) REGNO (reg))
4068 /* Not addressed from the same base register. */
4071 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
4072 ? REGNO (operands[i])
4073 : REGNO (SUBREG_REG (operands[i])));
4074 if (unsorted_regs[i] < unsorted_regs[order[0]])
4078 /* If it isn't an integer register, then we can't do this. */
4079 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14)
4082 unsorted_offsets[i] = INTVAL (offset);
4085 /* Not a suitable memory address. */
4089 /* All the useful information has now been extracted from the
4090 operands into unsorted_regs and unsorted_offsets; additionally,
4091 order[0] has been set to the lowest numbered register in the
4092 list. Sort the registers into order, and check that the memory
4093 offsets are ascending and adjacent. */
4095 for (i = 1; i < nops; i++)
4099 order[i] = order[i - 1];
4100 for (j = 0; j < nops; j++)
4101 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
4102 && (order[i] == order[i - 1]
4103 || unsorted_regs[j] < unsorted_regs[order[i]]))
4106 /* Have we found a suitable register? if not, one must be used more
4108 if (order[i] == order[i - 1])
4111 /* Is the memory address adjacent and ascending? */
4112 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
4120 for (i = 0; i < nops; i++)
4121 regs[i] = unsorted_regs[order[i]];
4123 *load_offset = unsorted_offsets[order[0]];
4126 if (unsorted_offsets[order[0]] == 0)
4127 return 1; /* stmia */
4129 if (unsorted_offsets[order[0]] == 4)
4130 return 2; /* stmib */
4132 if (unsorted_offsets[order[nops - 1]] == 0)
4133 return 3; /* stmda */
4135 if (unsorted_offsets[order[nops - 1]] == -4)
4136 return 4; /* stmdb */
4142 emit_stm_seq (operands, nops)
4148 HOST_WIDE_INT offset;
4152 switch (store_multiple_sequence (operands, nops, regs, &base_reg, &offset))
4155 strcpy (buf, "stm%?ia\t");
4159 strcpy (buf, "stm%?ib\t");
4163 strcpy (buf, "stm%?da\t");
4167 strcpy (buf, "stm%?db\t");
4174 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
4175 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
4177 for (i = 1; i < nops; i++)
4178 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
4179 reg_names[regs[i]]);
4181 strcat (buf, "}\t%@ phole stm");
4183 output_asm_insn (buf, operands);
4188 multi_register_push (op, mode)
4190 enum machine_mode mode ATTRIBUTE_UNUSED;
4192 if (GET_CODE (op) != PARALLEL
4193 || (GET_CODE (XVECEXP (op, 0, 0)) != SET)
4194 || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC)
4195 || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPEC_PUSH_MULT))
4201 /* Routines for use in generating RTL. */
4203 arm_gen_load_multiple (base_regno, count, from, up, write_back, unchanging_p,
4204 in_struct_p, scalar_p)
4216 int sign = up ? 1 : -1;
4219 /* XScale has load-store double instructions, but they have stricter
4220 alignment requirements than load-store multiple, so we can not
4223 For XScale ldm requires 2 + NREGS cycles to complete and blocks
4224 the pipeline until completion.
4232 An ldr instruction takes 1-3 cycles, but does not block the
4241 Best case ldr will always win. However, the more ldr instructions
4242 we issue, the less likely we are to be able to schedule them well.
4243 Using ldr instructions also increases code size.
4245 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
4246 for counts of 3 or 4 regs. */
4247 if (arm_is_xscale && count <= 2 && ! optimize_size)
4253 for (i = 0; i < count; i++)
4255 mem = gen_rtx_MEM (SImode, plus_constant (from, i * 4 * sign));
4256 RTX_UNCHANGING_P (mem) = unchanging_p;
4257 MEM_IN_STRUCT_P (mem) = in_struct_p;
4258 MEM_SCALAR_P (mem) = scalar_p;
4259 emit_move_insn (gen_rtx_REG (SImode, base_regno + i), mem);
4263 emit_move_insn (from, plus_constant (from, count * 4 * sign));
4265 seq = gen_sequence ();
4271 result = gen_rtx_PARALLEL (VOIDmode,
4272 rtvec_alloc (count + (write_back ? 1 : 0)));
4275 XVECEXP (result, 0, 0)
4276 = gen_rtx_SET (GET_MODE (from), from,
4277 plus_constant (from, count * 4 * sign));
4282 for (j = 0; i < count; i++, j++)
4284 mem = gen_rtx_MEM (SImode, plus_constant (from, j * 4 * sign));
4285 RTX_UNCHANGING_P (mem) = unchanging_p;
4286 MEM_IN_STRUCT_P (mem) = in_struct_p;
4287 MEM_SCALAR_P (mem) = scalar_p;
4288 XVECEXP (result, 0, i)
4289 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, base_regno + j), mem);
4296 arm_gen_store_multiple (base_regno, count, to, up, write_back, unchanging_p,
4297 in_struct_p, scalar_p)
4309 int sign = up ? 1 : -1;
4312 /* See arm_gen_load_multiple for discussion of
4313 the pros/cons of ldm/stm usage for XScale. */
4314 if (arm_is_xscale && count <= 2 && ! optimize_size)
4320 for (i = 0; i < count; i++)
4322 mem = gen_rtx_MEM (SImode, plus_constant (to, i * 4 * sign));
4323 RTX_UNCHANGING_P (mem) = unchanging_p;
4324 MEM_IN_STRUCT_P (mem) = in_struct_p;
4325 MEM_SCALAR_P (mem) = scalar_p;
4326 emit_move_insn (mem, gen_rtx_REG (SImode, base_regno + i));
4330 emit_move_insn (to, plus_constant (to, count * 4 * sign));
4332 seq = gen_sequence ();
4338 result = gen_rtx_PARALLEL (VOIDmode,
4339 rtvec_alloc (count + (write_back ? 1 : 0)));
4342 XVECEXP (result, 0, 0)
4343 = gen_rtx_SET (GET_MODE (to), to,
4344 plus_constant (to, count * 4 * sign));
4349 for (j = 0; i < count; i++, j++)
4351 mem = gen_rtx_MEM (SImode, plus_constant (to, j * 4 * sign));
4352 RTX_UNCHANGING_P (mem) = unchanging_p;
4353 MEM_IN_STRUCT_P (mem) = in_struct_p;
4354 MEM_SCALAR_P (mem) = scalar_p;
4356 XVECEXP (result, 0, i)
4357 = gen_rtx_SET (VOIDmode, mem, gen_rtx_REG (SImode, base_regno + j));
4364 arm_gen_movstrqi (operands)
4367 HOST_WIDE_INT in_words_to_go, out_words_to_go, last_bytes;
4370 rtx st_src, st_dst, fin_src, fin_dst;
4371 rtx part_bytes_reg = NULL;
4373 int dst_unchanging_p, dst_in_struct_p, src_unchanging_p, src_in_struct_p;
4374 int dst_scalar_p, src_scalar_p;
4376 if (GET_CODE (operands[2]) != CONST_INT
4377 || GET_CODE (operands[3]) != CONST_INT
4378 || INTVAL (operands[2]) > 64
4379 || INTVAL (operands[3]) & 3)
4382 st_dst = XEXP (operands[0], 0);
4383 st_src = XEXP (operands[1], 0);
4385 dst_unchanging_p = RTX_UNCHANGING_P (operands[0]);
4386 dst_in_struct_p = MEM_IN_STRUCT_P (operands[0]);
4387 dst_scalar_p = MEM_SCALAR_P (operands[0]);
4388 src_unchanging_p = RTX_UNCHANGING_P (operands[1]);
4389 src_in_struct_p = MEM_IN_STRUCT_P (operands[1]);
4390 src_scalar_p = MEM_SCALAR_P (operands[1]);
4392 fin_dst = dst = copy_to_mode_reg (SImode, st_dst);
4393 fin_src = src = copy_to_mode_reg (SImode, st_src);
4395 in_words_to_go = NUM_INTS (INTVAL (operands[2]));
4396 out_words_to_go = INTVAL (operands[2]) / 4;
4397 last_bytes = INTVAL (operands[2]) & 3;
4399 if (out_words_to_go != in_words_to_go && ((in_words_to_go - 1) & 3) != 0)
4400 part_bytes_reg = gen_rtx_REG (SImode, (in_words_to_go - 1) & 3);
4402 for (i = 0; in_words_to_go >= 2; i+=4)
4404 if (in_words_to_go > 4)
4405 emit_insn (arm_gen_load_multiple (0, 4, src, TRUE, TRUE,
4410 emit_insn (arm_gen_load_multiple (0, in_words_to_go, src, TRUE,
4411 FALSE, src_unchanging_p,
4412 src_in_struct_p, src_scalar_p));
4414 if (out_words_to_go)
4416 if (out_words_to_go > 4)
4417 emit_insn (arm_gen_store_multiple (0, 4, dst, TRUE, TRUE,
4421 else if (out_words_to_go != 1)
4422 emit_insn (arm_gen_store_multiple (0, out_words_to_go,
4431 mem = gen_rtx_MEM (SImode, dst);
4432 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
4433 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
4434 MEM_SCALAR_P (mem) = dst_scalar_p;
4435 emit_move_insn (mem, gen_rtx_REG (SImode, 0));
4436 if (last_bytes != 0)
4437 emit_insn (gen_addsi3 (dst, dst, GEN_INT (4)));
4441 in_words_to_go -= in_words_to_go < 4 ? in_words_to_go : 4;
4442 out_words_to_go -= out_words_to_go < 4 ? out_words_to_go : 4;
4445 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
4446 if (out_words_to_go)
4450 mem = gen_rtx_MEM (SImode, src);
4451 RTX_UNCHANGING_P (mem) = src_unchanging_p;
4452 MEM_IN_STRUCT_P (mem) = src_in_struct_p;
4453 MEM_SCALAR_P (mem) = src_scalar_p;
4454 emit_move_insn (sreg = gen_reg_rtx (SImode), mem);
4455 emit_move_insn (fin_src = gen_reg_rtx (SImode), plus_constant (src, 4));
4457 mem = gen_rtx_MEM (SImode, dst);
4458 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
4459 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
4460 MEM_SCALAR_P (mem) = dst_scalar_p;
4461 emit_move_insn (mem, sreg);
4462 emit_move_insn (fin_dst = gen_reg_rtx (SImode), plus_constant (dst, 4));
4465 if (in_words_to_go) /* Sanity check */
4471 if (in_words_to_go < 0)
4474 mem = gen_rtx_MEM (SImode, src);
4475 RTX_UNCHANGING_P (mem) = src_unchanging_p;
4476 MEM_IN_STRUCT_P (mem) = src_in_struct_p;
4477 MEM_SCALAR_P (mem) = src_scalar_p;
4478 part_bytes_reg = copy_to_mode_reg (SImode, mem);
4481 if (last_bytes && part_bytes_reg == NULL)
4484 if (BYTES_BIG_ENDIAN && last_bytes)
4486 rtx tmp = gen_reg_rtx (SImode);
4488 /* The bytes we want are in the top end of the word. */
4489 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg,
4490 GEN_INT (8 * (4 - last_bytes))));
4491 part_bytes_reg = tmp;
4495 mem = gen_rtx_MEM (QImode, plus_constant (dst, last_bytes - 1));
4496 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
4497 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
4498 MEM_SCALAR_P (mem) = dst_scalar_p;
4499 emit_move_insn (mem, gen_rtx_SUBREG (QImode, part_bytes_reg, 0));
4503 tmp = gen_reg_rtx (SImode);
4504 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8)));
4505 part_bytes_reg = tmp;
4514 mem = gen_rtx_MEM (HImode, dst);
4515 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
4516 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
4517 MEM_SCALAR_P (mem) = dst_scalar_p;
4518 emit_move_insn (mem, gen_rtx_SUBREG (HImode, part_bytes_reg, 0));
4522 rtx tmp = gen_reg_rtx (SImode);
4524 emit_insn (gen_addsi3 (dst, dst, GEN_INT (2)));
4525 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (16)));
4526 part_bytes_reg = tmp;
4532 mem = gen_rtx_MEM (QImode, dst);
4533 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
4534 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
4535 MEM_SCALAR_P (mem) = dst_scalar_p;
4536 emit_move_insn (mem, gen_rtx_SUBREG (QImode, part_bytes_reg, 0));
4543 /* Generate a memory reference for a half word, such that it will be loaded
4544 into the top 16 bits of the word. We can assume that the address is
4545 known to be alignable and of the form reg, or plus (reg, const). */
4547 arm_gen_rotated_half_load (memref)
4550 HOST_WIDE_INT offset = 0;
4551 rtx base = XEXP (memref, 0);
4553 if (GET_CODE (base) == PLUS)
4555 offset = INTVAL (XEXP (base, 1));
4556 base = XEXP (base, 0);
4559 /* If we aren't allowed to generate unaligned addresses, then fail. */
4560 if (TARGET_MMU_TRAPS
4561 && ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 0)))
4564 base = gen_rtx_MEM (SImode, plus_constant (base, offset & ~2));
4566 if ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 2))
4569 return gen_rtx_ROTATE (SImode, base, GEN_INT (16));
4572 /* Select a dominance comparison mode if possible. We support three forms.
4573 COND_OR == 0 => (X && Y)
4574 COND_OR == 1 => ((! X( || Y)
4575 COND_OR == 2 => (X || Y)
4576 If we are unable to support a dominance comparsison we return CC mode.
4577 This will then fail to match for the RTL expressions that generate this
4580 static enum machine_mode
4581 select_dominance_cc_mode (x, y, cond_or)
4584 HOST_WIDE_INT cond_or;
4586 enum rtx_code cond1, cond2;
4589 /* Currently we will probably get the wrong result if the individual
4590 comparisons are not simple. This also ensures that it is safe to
4591 reverse a comparison if necessary. */
4592 if ((arm_select_cc_mode (cond1 = GET_CODE (x), XEXP (x, 0), XEXP (x, 1))
4594 || (arm_select_cc_mode (cond2 = GET_CODE (y), XEXP (y, 0), XEXP (y, 1))
4598 /* The if_then_else variant of this tests the second condition if the
4599 first passes, but is true if the first fails. Reverse the first
4600 condition to get a true "inclusive-or" expression. */
4602 cond1 = reverse_condition (cond1);
4604 /* If the comparisons are not equal, and one doesn't dominate the other,
4605 then we can't do this. */
4607 && !comparison_dominates_p (cond1, cond2)
4608 && (swapped = 1, !comparison_dominates_p (cond2, cond1)))
4613 enum rtx_code temp = cond1;
4621 if (cond2 == EQ || !cond_or)
4626 case LE: return CC_DLEmode;
4627 case LEU: return CC_DLEUmode;
4628 case GE: return CC_DGEmode;
4629 case GEU: return CC_DGEUmode;
4636 if (cond2 == LT || !cond_or)
4645 if (cond2 == GT || !cond_or)
4654 if (cond2 == LTU || !cond_or)
4663 if (cond2 == GTU || !cond_or)
4671 /* The remaining cases only occur when both comparisons are the
4696 arm_select_cc_mode (op, x, y)
4701 /* All floating point compares return CCFP if it is an equality
4702 comparison, and CCFPE otherwise. */
4703 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
4730 /* A compare with a shifted operand. Because of canonicalization, the
4731 comparison will have to be swapped when we emit the assembler. */
4732 if (GET_MODE (y) == SImode && GET_CODE (y) == REG
4733 && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
4734 || GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE
4735 || GET_CODE (x) == ROTATERT))
4738 /* This is a special case that is used by combine to allow a
4739 comparison of a shifted byte load to be split into a zero-extend
4740 followed by a comparison of the shifted integer (only valid for
4741 equalities and unsigned inequalities). */
4742 if (GET_MODE (x) == SImode
4743 && GET_CODE (x) == ASHIFT
4744 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 24
4745 && GET_CODE (XEXP (x, 0)) == SUBREG
4746 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == MEM
4747 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == QImode
4748 && (op == EQ || op == NE
4749 || op == GEU || op == GTU || op == LTU || op == LEU)
4750 && GET_CODE (y) == CONST_INT)
4753 /* A construct for a conditional compare, if the false arm contains
4754 0, then both conditions must be true, otherwise either condition
4755 must be true. Not all conditions are possible, so CCmode is
4756 returned if it can't be done. */
4757 if (GET_CODE (x) == IF_THEN_ELSE
4758 && (XEXP (x, 2) == const0_rtx
4759 || XEXP (x, 2) == const1_rtx)
4760 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4761 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<')
4762 return select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
4763 INTVAL (XEXP (x, 2)));
4765 /* Alternate canonicalizations of the above. These are somewhat cleaner. */
4766 if (GET_CODE (x) == AND
4767 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4768 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<')
4769 return select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1), 0);
4771 if (GET_CODE (x) == IOR
4772 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4773 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<')
4774 return select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1), 2);
4776 /* An operation that sets the condition codes as a side-effect, the
4777 V flag is not set correctly, so we can only use comparisons where
4778 this doesn't matter. (For LT and GE we can use "mi" and "pl"
4780 if (GET_MODE (x) == SImode
4782 && (op == EQ || op == NE || op == LT || op == GE)
4783 && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
4784 || GET_CODE (x) == AND || GET_CODE (x) == IOR
4785 || GET_CODE (x) == XOR || GET_CODE (x) == MULT
4786 || GET_CODE (x) == NOT || GET_CODE (x) == NEG
4787 || GET_CODE (x) == LSHIFTRT
4788 || GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
4789 || GET_CODE (x) == ROTATERT || GET_CODE (x) == ZERO_EXTRACT))
4792 if (GET_MODE (x) == QImode && (op == EQ || op == NE))
4795 if (GET_MODE (x) == SImode && (op == LTU || op == GEU)
4796 && GET_CODE (x) == PLUS
4797 && (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y)))
4803 /* X and Y are two things to compare using CODE. Emit the compare insn and
4804 return the rtx for register 0 in the proper mode. FP means this is a
4805 floating point compare: I don't think that it is needed on the arm. */
4808 arm_gen_compare_reg (code, x, y)
4812 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
4813 rtx cc_reg = gen_rtx_REG (mode, CC_REGNUM);
4815 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
4816 gen_rtx_COMPARE (mode, x, y)));
4822 arm_reload_in_hi (operands)
4825 rtx ref = operands[1];
4827 HOST_WIDE_INT offset = 0;
4829 if (GET_CODE (ref) == SUBREG)
4831 offset = SUBREG_BYTE (ref);
4832 ref = SUBREG_REG (ref);
4835 if (GET_CODE (ref) == REG)
4837 /* We have a pseudo which has been spilt onto the stack; there
4838 are two cases here: the first where there is a simple
4839 stack-slot replacement and a second where the stack-slot is
4840 out of range, or is used as a subreg. */
4841 if (reg_equiv_mem[REGNO (ref)])
4843 ref = reg_equiv_mem[REGNO (ref)];
4844 base = find_replacement (&XEXP (ref, 0));
4847 /* The slot is out of range, or was dressed up in a SUBREG. */
4848 base = reg_equiv_address[REGNO (ref)];
4851 base = find_replacement (&XEXP (ref, 0));
4853 /* Handle the case where the address is too complex to be offset by 1. */
4854 if (GET_CODE (base) == MINUS
4855 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
4857 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
4859 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
4862 else if (GET_CODE (base) == PLUS)
4864 /* The addend must be CONST_INT, or we would have dealt with it above. */
4865 HOST_WIDE_INT hi, lo;
4867 offset += INTVAL (XEXP (base, 1));
4868 base = XEXP (base, 0);
4870 /* Rework the address into a legal sequence of insns. */
4871 /* Valid range for lo is -4095 -> 4095 */
4874 : -((-offset) & 0xfff));
4876 /* Corner case, if lo is the max offset then we would be out of range
4877 once we have added the additional 1 below, so bump the msb into the
4878 pre-loading insn(s). */
4882 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff)
4883 ^ (HOST_WIDE_INT) 0x80000000)
4884 - (HOST_WIDE_INT) 0x80000000);
4886 if (hi + lo != offset)
4891 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
4893 /* Get the base address; addsi3 knows how to handle constants
4894 that require more than one insn. */
4895 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
4901 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
4902 emit_insn (gen_zero_extendqisi2 (scratch,
4903 gen_rtx_MEM (QImode,
4904 plus_constant (base,
4906 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode, operands[0], 0),
4907 gen_rtx_MEM (QImode,
4908 plus_constant (base,
4910 if (!BYTES_BIG_ENDIAN)
4911 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
4912 gen_rtx_IOR (SImode,
4915 gen_rtx_SUBREG (SImode, operands[0], 0),
4919 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
4920 gen_rtx_IOR (SImode,
4921 gen_rtx_ASHIFT (SImode, scratch,
4923 gen_rtx_SUBREG (SImode, operands[0],
4927 /* Handle storing a half-word to memory during reload by synthesising as two
4928 byte stores. Take care not to clobber the input values until after we
4929 have moved them somewhere safe. This code assumes that if the DImode
4930 scratch in operands[2] overlaps either the input value or output address
4931 in some way, then that value must die in this insn (we absolutely need
4932 two scratch registers for some corner cases). */
4934 arm_reload_out_hi (operands)
4937 rtx ref = operands[0];
4938 rtx outval = operands[1];
4940 HOST_WIDE_INT offset = 0;
4942 if (GET_CODE (ref) == SUBREG)
4944 offset = SUBREG_BYTE (ref);
4945 ref = SUBREG_REG (ref);
4949 if (GET_CODE (ref) == REG)
4951 /* We have a pseudo which has been spilt onto the stack; there
4952 are two cases here: the first where there is a simple
4953 stack-slot replacement and a second where the stack-slot is
4954 out of range, or is used as a subreg. */
4955 if (reg_equiv_mem[REGNO (ref)])
4957 ref = reg_equiv_mem[REGNO (ref)];
4958 base = find_replacement (&XEXP (ref, 0));
4961 /* The slot is out of range, or was dressed up in a SUBREG. */
4962 base = reg_equiv_address[REGNO (ref)];
4965 base = find_replacement (&XEXP (ref, 0));
4967 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
4969 /* Handle the case where the address is too complex to be offset by 1. */
4970 if (GET_CODE (base) == MINUS
4971 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
4973 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
4975 /* Be careful not to destroy OUTVAL. */
4976 if (reg_overlap_mentioned_p (base_plus, outval))
4978 /* Updating base_plus might destroy outval, see if we can
4979 swap the scratch and base_plus. */
4980 if (!reg_overlap_mentioned_p (scratch, outval))
4983 scratch = base_plus;
4988 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
4990 /* Be conservative and copy OUTVAL into the scratch now,
4991 this should only be necessary if outval is a subreg
4992 of something larger than a word. */
4993 /* XXX Might this clobber base? I can't see how it can,
4994 since scratch is known to overlap with OUTVAL, and
4995 must be wider than a word. */
4996 emit_insn (gen_movhi (scratch_hi, outval));
4997 outval = scratch_hi;
5001 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
5004 else if (GET_CODE (base) == PLUS)
5006 /* The addend must be CONST_INT, or we would have dealt with it above. */
5007 HOST_WIDE_INT hi, lo;
5009 offset += INTVAL (XEXP (base, 1));
5010 base = XEXP (base, 0);
5012 /* Rework the address into a legal sequence of insns. */
5013 /* Valid range for lo is -4095 -> 4095 */
5016 : -((-offset) & 0xfff));
5018 /* Corner case, if lo is the max offset then we would be out of range
5019 once we have added the additional 1 below, so bump the msb into the
5020 pre-loading insn(s). */
5024 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff)
5025 ^ (HOST_WIDE_INT) 0x80000000)
5026 - (HOST_WIDE_INT) 0x80000000);
5028 if (hi + lo != offset)
5033 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
5035 /* Be careful not to destroy OUTVAL. */
5036 if (reg_overlap_mentioned_p (base_plus, outval))
5038 /* Updating base_plus might destroy outval, see if we
5039 can swap the scratch and base_plus. */
5040 if (!reg_overlap_mentioned_p (scratch, outval))
5043 scratch = base_plus;
5048 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
5050 /* Be conservative and copy outval into scratch now,
5051 this should only be necessary if outval is a
5052 subreg of something larger than a word. */
5053 /* XXX Might this clobber base? I can't see how it
5054 can, since scratch is known to overlap with
5056 emit_insn (gen_movhi (scratch_hi, outval));
5057 outval = scratch_hi;
5061 /* Get the base address; addsi3 knows how to handle constants
5062 that require more than one insn. */
5063 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
5069 if (BYTES_BIG_ENDIAN)
5071 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
5072 plus_constant (base, offset + 1)),
5073 gen_rtx_SUBREG (QImode, outval, 0)));
5074 emit_insn (gen_lshrsi3 (scratch,
5075 gen_rtx_SUBREG (SImode, outval, 0),
5077 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
5078 gen_rtx_SUBREG (QImode, scratch, 0)));
5082 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
5083 gen_rtx_SUBREG (QImode, outval, 0)));
5084 emit_insn (gen_lshrsi3 (scratch,
5085 gen_rtx_SUBREG (SImode, outval, 0),
5087 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
5088 plus_constant (base, offset + 1)),
5089 gen_rtx_SUBREG (QImode, scratch, 0)));
5093 /* Print a symbolic form of X to the debug file, F. */
5095 arm_print_value (f, x)
5099 switch (GET_CODE (x))
5102 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (x));
5106 fprintf (f, "<0x%lx,0x%lx>", (long)XWINT (x, 2), (long)XWINT (x, 3));
5110 fprintf (f, "\"%s\"", XSTR (x, 0));
5114 fprintf (f, "`%s'", XSTR (x, 0));
5118 fprintf (f, "L%d", INSN_UID (XEXP (x, 0)));
5122 arm_print_value (f, XEXP (x, 0));
5126 arm_print_value (f, XEXP (x, 0));
5128 arm_print_value (f, XEXP (x, 1));
5136 fprintf (f, "????");
5141 /* Routines for manipulation of the constant pool. */
5143 /* Arm instructions cannot load a large constant directly into a
5144 register; they have to come from a pc relative load. The constant
5145 must therefore be placed in the addressable range of the pc
5146 relative load. Depending on the precise pc relative load
5147 instruction the range is somewhere between 256 bytes and 4k. This
5148 means that we often have to dump a constant inside a function, and
5149 generate code to branch around it.
5151 It is important to minimize this, since the branches will slow
5152 things down and make the code larger.
5154 Normally we can hide the table after an existing unconditional
5155 branch so that there is no interruption of the flow, but in the
5156 worst case the code looks like this:
5174 We fix this by performing a scan after scheduling, which notices
5175 which instructions need to have their operands fetched from the
5176 constant table and builds the table.
5178 The algorithm starts by building a table of all the constants that
5179 need fixing up and all the natural barriers in the function (places
5180 where a constant table can be dropped without breaking the flow).
5181 For each fixup we note how far the pc-relative replacement will be
5182 able to reach and the offset of the instruction into the function.
5184 Having built the table we then group the fixes together to form
5185 tables that are as large as possible (subject to addressing
5186 constraints) and emit each table of constants after the last
5187 barrier that is within range of all the instructions in the group.
5188 If a group does not contain a barrier, then we forcibly create one
5189 by inserting a jump instruction into the flow. Once the table has
5190 been inserted, the insns are then modified to reference the
5191 relevant entry in the pool.
5193 Possible enhancements to the algorithm (not implemented) are:
5195 1) For some processors and object formats, there may be benefit in
5196 aligning the pools to the start of cache lines; this alignment
5197 would need to be taken into account when calculating addressability
5200 /* These typedefs are located at the start of this file, so that
5201 they can be used in the prototypes there. This comment is to
5202 remind readers of that fact so that the following structures
5203 can be understood more easily.
5205 typedef struct minipool_node Mnode;
5206 typedef struct minipool_fixup Mfix; */
5208 struct minipool_node
5210 /* Doubly linked chain of entries. */
5213 /* The maximum offset into the code that this entry can be placed. While
5214 pushing fixes for forward references, all entries are sorted in order
5215 of increasing max_address. */
5216 HOST_WIDE_INT max_address;
5217 /* Similarly for an entry inserted for a backwards ref. */
5218 HOST_WIDE_INT min_address;
5219 /* The number of fixes referencing this entry. This can become zero
5220 if we "unpush" an entry. In this case we ignore the entry when we
5221 come to emit the code. */
5223 /* The offset from the start of the minipool. */
5224 HOST_WIDE_INT offset;
5225 /* The value in table. */
5227 /* The mode of value. */
5228 enum machine_mode mode;
5232 struct minipool_fixup
5236 HOST_WIDE_INT address;
5238 enum machine_mode mode;
5242 HOST_WIDE_INT forwards;
5243 HOST_WIDE_INT backwards;
5246 /* Fixes less than a word need padding out to a word boundary. */
5247 #define MINIPOOL_FIX_SIZE(mode) \
5248 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4)
5250 static Mnode * minipool_vector_head;
5251 static Mnode * minipool_vector_tail;
5252 static rtx minipool_vector_label;
5254 /* The linked list of all minipool fixes required for this function. */
5255 Mfix * minipool_fix_head;
5256 Mfix * minipool_fix_tail;
5257 /* The fix entry for the current minipool, once it has been placed. */
5258 Mfix * minipool_barrier;
5260 /* Determines if INSN is the start of a jump table. Returns the end
5261 of the TABLE or NULL_RTX. */
5263 is_jump_table (insn)
5268 if (GET_CODE (insn) == JUMP_INSN
5269 && JUMP_LABEL (insn) != NULL
5270 && ((table = next_real_insn (JUMP_LABEL (insn)))
5271 == next_real_insn (insn))
5273 && GET_CODE (table) == JUMP_INSN
5274 && (GET_CODE (PATTERN (table)) == ADDR_VEC
5275 || GET_CODE (PATTERN (table)) == ADDR_DIFF_VEC))
5281 static HOST_WIDE_INT
5282 get_jump_table_size (insn)
5285 rtx body = PATTERN (insn);
5286 int elt = GET_CODE (body) == ADDR_DIFF_VEC ? 1 : 0;
5288 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, elt);
5291 /* Move a minipool fix MP from its current location to before MAX_MP.
5292 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
5293 contrains may need updating. */
5295 move_minipool_fix_forward_ref (mp, max_mp, max_address)
5298 HOST_WIDE_INT max_address;
5300 /* This should never be true and the code below assumes these are
5307 if (max_address < mp->max_address)
5308 mp->max_address = max_address;
5312 if (max_address > max_mp->max_address - mp->fix_size)
5313 mp->max_address = max_mp->max_address - mp->fix_size;
5315 mp->max_address = max_address;
5317 /* Unlink MP from its current position. Since max_mp is non-null,
5318 mp->prev must be non-null. */
5319 mp->prev->next = mp->next;
5320 if (mp->next != NULL)
5321 mp->next->prev = mp->prev;
5323 minipool_vector_tail = mp->prev;
5325 /* Re-insert it before MAX_MP. */
5327 mp->prev = max_mp->prev;
5330 if (mp->prev != NULL)
5331 mp->prev->next = mp;
5333 minipool_vector_head = mp;
5336 /* Save the new entry. */
5339 /* Scan over the preceding entries and adjust their addresses as
5341 while (mp->prev != NULL
5342 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
5344 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
5351 /* Add a constant to the minipool for a forward reference. Returns the
5352 node added or NULL if the constant will not fit in this pool. */
5354 add_minipool_forward_ref (fix)
5357 /* If set, max_mp is the first pool_entry that has a lower
5358 constraint than the one we are trying to add. */
5359 Mnode * max_mp = NULL;
5360 HOST_WIDE_INT max_address = fix->address + fix->forwards;
5363 /* If this fix's address is greater than the address of the first
5364 entry, then we can't put the fix in this pool. We subtract the
5365 size of the current fix to ensure that if the table is fully
5366 packed we still have enough room to insert this value by suffling
5367 the other fixes forwards. */
5368 if (minipool_vector_head &&
5369 fix->address >= minipool_vector_head->max_address - fix->fix_size)
5372 /* Scan the pool to see if a constant with the same value has
5373 already been added. While we are doing this, also note the
5374 location where we must insert the constant if it doesn't already
5376 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
5378 if (GET_CODE (fix->value) == GET_CODE (mp->value)
5379 && fix->mode == mp->mode
5380 && (GET_CODE (fix->value) != CODE_LABEL
5381 || (CODE_LABEL_NUMBER (fix->value)
5382 == CODE_LABEL_NUMBER (mp->value)))
5383 && rtx_equal_p (fix->value, mp->value))
5385 /* More than one fix references this entry. */
5387 return move_minipool_fix_forward_ref (mp, max_mp, max_address);
5390 /* Note the insertion point if necessary. */
5392 && mp->max_address > max_address)
5396 /* The value is not currently in the minipool, so we need to create
5397 a new entry for it. If MAX_MP is NULL, the entry will be put on
5398 the end of the list since the placement is less constrained than
5399 any existing entry. Otherwise, we insert the new fix before
5400 MAX_MP and, if neceesary, adjust the constraints on the other
5402 mp = xmalloc (sizeof (* mp));
5403 mp->fix_size = fix->fix_size;
5404 mp->mode = fix->mode;
5405 mp->value = fix->value;
5407 /* Not yet required for a backwards ref. */
5408 mp->min_address = -65536;
5412 mp->max_address = max_address;
5414 mp->prev = minipool_vector_tail;
5416 if (mp->prev == NULL)
5418 minipool_vector_head = mp;
5419 minipool_vector_label = gen_label_rtx ();
5422 mp->prev->next = mp;
5424 minipool_vector_tail = mp;
5428 if (max_address > max_mp->max_address - mp->fix_size)
5429 mp->max_address = max_mp->max_address - mp->fix_size;
5431 mp->max_address = max_address;
5434 mp->prev = max_mp->prev;
5436 if (mp->prev != NULL)
5437 mp->prev->next = mp;
5439 minipool_vector_head = mp;
5442 /* Save the new entry. */
5445 /* Scan over the preceding entries and adjust their addresses as
5447 while (mp->prev != NULL
5448 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
5450 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
5458 move_minipool_fix_backward_ref (mp, min_mp, min_address)
5461 HOST_WIDE_INT min_address;
5463 HOST_WIDE_INT offset;
5465 /* This should never be true, and the code below assumes these are
5472 if (min_address > mp->min_address)
5473 mp->min_address = min_address;
5477 /* We will adjust this below if it is too loose. */
5478 mp->min_address = min_address;
5480 /* Unlink MP from its current position. Since min_mp is non-null,
5481 mp->next must be non-null. */
5482 mp->next->prev = mp->prev;
5483 if (mp->prev != NULL)
5484 mp->prev->next = mp->next;
5486 minipool_vector_head = mp->next;
5488 /* Reinsert it after MIN_MP. */
5490 mp->next = min_mp->next;
5492 if (mp->next != NULL)
5493 mp->next->prev = mp;
5495 minipool_vector_tail = mp;
5501 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
5503 mp->offset = offset;
5504 if (mp->refcount > 0)
5505 offset += mp->fix_size;
5507 if (mp->next && mp->next->min_address < mp->min_address + mp->fix_size)
5508 mp->next->min_address = mp->min_address + mp->fix_size;
5514 /* Add a constant to the minipool for a backward reference. Returns the
5515 node added or NULL if the constant will not fit in this pool.
5517 Note that the code for insertion for a backwards reference can be
5518 somewhat confusing because the calculated offsets for each fix do
5519 not take into account the size of the pool (which is still under
5522 add_minipool_backward_ref (fix)
5525 /* If set, min_mp is the last pool_entry that has a lower constraint
5526 than the one we are trying to add. */
5527 Mnode * min_mp = NULL;
5528 /* This can be negative, since it is only a constraint. */
5529 HOST_WIDE_INT min_address = fix->address - fix->backwards;
5532 /* If we can't reach the current pool from this insn, or if we can't
5533 insert this entry at the end of the pool without pushing other
5534 fixes out of range, then we don't try. This ensures that we
5535 can't fail later on. */
5536 if (min_address >= minipool_barrier->address
5537 || (minipool_vector_tail->min_address + fix->fix_size
5538 >= minipool_barrier->address))
5541 /* Scan the pool to see if a constant with the same value has
5542 already been added. While we are doing this, also note the
5543 location where we must insert the constant if it doesn't already
5545 for (mp = minipool_vector_tail; mp != NULL; mp = mp->prev)
5547 if (GET_CODE (fix->value) == GET_CODE (mp->value)
5548 && fix->mode == mp->mode
5549 && (GET_CODE (fix->value) != CODE_LABEL
5550 || (CODE_LABEL_NUMBER (fix->value)
5551 == CODE_LABEL_NUMBER (mp->value)))
5552 && rtx_equal_p (fix->value, mp->value)
5553 /* Check that there is enough slack to move this entry to the
5554 end of the table (this is conservative). */
5556 > (minipool_barrier->address
5557 + minipool_vector_tail->offset
5558 + minipool_vector_tail->fix_size)))
5561 return move_minipool_fix_backward_ref (mp, min_mp, min_address);
5565 mp->min_address += fix->fix_size;
5568 /* Note the insertion point if necessary. */
5569 if (mp->min_address < min_address)
5571 else if (mp->max_address
5572 < minipool_barrier->address + mp->offset + fix->fix_size)
5574 /* Inserting before this entry would push the fix beyond
5575 its maximum address (which can happen if we have
5576 re-located a forwards fix); force the new fix to come
5579 min_address = mp->min_address + fix->fix_size;
5584 /* We need to create a new entry. */
5585 mp = xmalloc (sizeof (* mp));
5586 mp->fix_size = fix->fix_size;
5587 mp->mode = fix->mode;
5588 mp->value = fix->value;
5590 mp->max_address = minipool_barrier->address + 65536;
5592 mp->min_address = min_address;
5597 mp->next = minipool_vector_head;
5599 if (mp->next == NULL)
5601 minipool_vector_tail = mp;
5602 minipool_vector_label = gen_label_rtx ();
5605 mp->next->prev = mp;
5607 minipool_vector_head = mp;
5611 mp->next = min_mp->next;
5615 if (mp->next != NULL)
5616 mp->next->prev = mp;
5618 minipool_vector_tail = mp;
5621 /* Save the new entry. */
5629 /* Scan over the following entries and adjust their offsets. */
5630 while (mp->next != NULL)
5632 if (mp->next->min_address < mp->min_address + mp->fix_size)
5633 mp->next->min_address = mp->min_address + mp->fix_size;
5636 mp->next->offset = mp->offset + mp->fix_size;
5638 mp->next->offset = mp->offset;
5647 assign_minipool_offsets (barrier)
5650 HOST_WIDE_INT offset = 0;
5653 minipool_barrier = barrier;
5655 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
5657 mp->offset = offset;
5659 if (mp->refcount > 0)
5660 offset += mp->fix_size;
5664 /* Output the literal table */
5666 dump_minipool (scan)
5673 fprintf (rtl_dump_file,
5674 ";; Emitting minipool after insn %u; address %ld\n",
5675 INSN_UID (scan), (unsigned long) minipool_barrier->address);
5677 scan = emit_label_after (gen_label_rtx (), scan);
5678 scan = emit_insn_after (gen_align_4 (), scan);
5679 scan = emit_label_after (minipool_vector_label, scan);
5681 for (mp = minipool_vector_head; mp != NULL; mp = nmp)
5683 if (mp->refcount > 0)
5687 fprintf (rtl_dump_file,
5688 ";; Offset %u, min %ld, max %ld ",
5689 (unsigned) mp->offset, (unsigned long) mp->min_address,
5690 (unsigned long) mp->max_address);
5691 arm_print_value (rtl_dump_file, mp->value);
5692 fputc ('\n', rtl_dump_file);
5695 switch (mp->fix_size)
5697 #ifdef HAVE_consttable_1
5699 scan = emit_insn_after (gen_consttable_1 (mp->value), scan);
5703 #ifdef HAVE_consttable_2
5705 scan = emit_insn_after (gen_consttable_2 (mp->value), scan);
5709 #ifdef HAVE_consttable_4
5711 scan = emit_insn_after (gen_consttable_4 (mp->value), scan);
5715 #ifdef HAVE_consttable_8
5717 scan = emit_insn_after (gen_consttable_8 (mp->value), scan);
5731 minipool_vector_head = minipool_vector_tail = NULL;
5732 scan = emit_insn_after (gen_consttable_end (), scan);
5733 scan = emit_barrier_after (scan);
5736 /* Return the cost of forcibly inserting a barrier after INSN. */
5738 arm_barrier_cost (insn)
5741 /* Basing the location of the pool on the loop depth is preferable,
5742 but at the moment, the basic block information seems to be
5743 corrupt by this stage of the compilation. */
5745 rtx next = next_nonnote_insn (insn);
5747 if (next != NULL && GET_CODE (next) == CODE_LABEL)
5750 switch (GET_CODE (insn))
5753 /* It will always be better to place the table before the label, rather
5762 return base_cost - 10;
5765 return base_cost + 10;
5769 /* Find the best place in the insn stream in the range
5770 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
5771 Create the barrier by inserting a jump and add a new fix entry for
5774 create_fix_barrier (fix, max_address)
5776 HOST_WIDE_INT max_address;
5778 HOST_WIDE_INT count = 0;
5780 rtx from = fix->insn;
5781 rtx selected = from;
5783 HOST_WIDE_INT selected_address;
5785 HOST_WIDE_INT max_count = max_address - fix->address;
5786 rtx label = gen_label_rtx ();
5788 selected_cost = arm_barrier_cost (from);
5789 selected_address = fix->address;
5791 while (from && count < max_count)
5796 /* This code shouldn't have been called if there was a natural barrier
5798 if (GET_CODE (from) == BARRIER)
5801 /* Count the length of this insn. */
5802 count += get_attr_length (from);
5804 /* If there is a jump table, add its length. */
5805 tmp = is_jump_table (from);
5808 count += get_jump_table_size (tmp);
5810 /* Jump tables aren't in a basic block, so base the cost on
5811 the dispatch insn. If we select this location, we will
5812 still put the pool after the table. */
5813 new_cost = arm_barrier_cost (from);
5815 if (count < max_count && new_cost <= selected_cost)
5818 selected_cost = new_cost;
5819 selected_address = fix->address + count;
5822 /* Continue after the dispatch table. */
5823 from = NEXT_INSN (tmp);
5827 new_cost = arm_barrier_cost (from);
5829 if (count < max_count && new_cost <= selected_cost)
5832 selected_cost = new_cost;
5833 selected_address = fix->address + count;
5836 from = NEXT_INSN (from);
5839 /* Create a new JUMP_INSN that branches around a barrier. */
5840 from = emit_jump_insn_after (gen_jump (label), selected);
5841 JUMP_LABEL (from) = label;
5842 barrier = emit_barrier_after (from);
5843 emit_label_after (label, barrier);
5845 /* Create a minipool barrier entry for the new barrier. */
5846 new_fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* new_fix));
5847 new_fix->insn = barrier;
5848 new_fix->address = selected_address;
5849 new_fix->next = fix->next;
5850 fix->next = new_fix;
5855 /* Record that there is a natural barrier in the insn stream at
5858 push_minipool_barrier (insn, address)
5860 HOST_WIDE_INT address;
5862 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
5865 fix->address = address;
5868 if (minipool_fix_head != NULL)
5869 minipool_fix_tail->next = fix;
5871 minipool_fix_head = fix;
5873 minipool_fix_tail = fix;
5876 /* Record INSN, which will need fixing up to load a value from the
5877 minipool. ADDRESS is the offset of the insn since the start of the
5878 function; LOC is a pointer to the part of the insn which requires
5879 fixing; VALUE is the constant that must be loaded, which is of type
5882 push_minipool_fix (insn, address, loc, mode, value)
5884 HOST_WIDE_INT address;
5886 enum machine_mode mode;
5889 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
5891 #ifdef AOF_ASSEMBLER
5892 /* PIC symbol refereneces need to be converted into offsets into the
5894 /* XXX This shouldn't be done here. */
5895 if (flag_pic && GET_CODE (value) == SYMBOL_REF)
5896 value = aof_pic_entry (value);
5897 #endif /* AOF_ASSEMBLER */
5900 fix->address = address;
5903 fix->fix_size = MINIPOOL_FIX_SIZE (mode);
5905 fix->forwards = get_attr_pool_range (insn);
5906 fix->backwards = get_attr_neg_pool_range (insn);
5907 fix->minipool = NULL;
5909 /* If an insn doesn't have a range defined for it, then it isn't
5910 expecting to be reworked by this code. Better to abort now than
5911 to generate duff assembly code. */
5912 if (fix->forwards == 0 && fix->backwards == 0)
5917 fprintf (rtl_dump_file,
5918 ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ",
5919 GET_MODE_NAME (mode),
5920 INSN_UID (insn), (unsigned long) address,
5921 -1 * (long)fix->backwards, (long)fix->forwards);
5922 arm_print_value (rtl_dump_file, fix->value);
5923 fprintf (rtl_dump_file, "\n");
5926 /* Add it to the chain of fixes. */
5929 if (minipool_fix_head != NULL)
5930 minipool_fix_tail->next = fix;
5932 minipool_fix_head = fix;
5934 minipool_fix_tail = fix;
5937 /* Scan INSN and note any of its operands that need fixing. */
5939 note_invalid_constants (insn, address)
5941 HOST_WIDE_INT address;
5945 extract_insn (insn);
5947 if (!constrain_operands (1))
5948 fatal_insn_not_found (insn);
5950 /* Fill in recog_op_alt with information about the constraints of this
5952 preprocess_constraints ();
5954 for (opno = 0; opno < recog_data.n_operands; opno++)
5956 /* Things we need to fix can only occur in inputs. */
5957 if (recog_data.operand_type[opno] != OP_IN)
5960 /* If this alternative is a memory reference, then any mention
5961 of constants in this alternative is really to fool reload
5962 into allowing us to accept one there. We need to fix them up
5963 now so that we output the right code. */
5964 if (recog_op_alt[opno][which_alternative].memory_ok)
5966 rtx op = recog_data.operand[opno];
5968 if (CONSTANT_P (op))
5969 push_minipool_fix (insn, address, recog_data.operand_loc[opno],
5970 recog_data.operand_mode[opno], op);
5972 /* RWE: Now we look correctly at the operands for the insn,
5973 this shouldn't be needed any more. */
5974 #ifndef AOF_ASSEMBLER
5975 /* XXX Is this still needed? */
5976 else if (GET_CODE (op) == UNSPEC && XINT (op, 1) == UNSPEC_PIC_SYM)
5977 push_minipool_fix (insn, address, recog_data.operand_loc[opno],
5978 recog_data.operand_mode[opno],
5979 XVECEXP (op, 0, 0));
5982 else if (GET_CODE (op) == MEM
5983 && GET_CODE (XEXP (op, 0)) == SYMBOL_REF
5984 && CONSTANT_POOL_ADDRESS_P (XEXP (op, 0)))
5985 push_minipool_fix (insn, address, recog_data.operand_loc[opno],
5986 recog_data.operand_mode[opno],
5987 get_pool_constant (XEXP (op, 0)));
5997 HOST_WIDE_INT address = 0;
6000 minipool_fix_head = minipool_fix_tail = NULL;
6002 /* The first insn must always be a note, or the code below won't
6003 scan it properly. */
6004 if (GET_CODE (first) != NOTE)
6007 /* Scan all the insns and record the operands that will need fixing. */
6008 for (insn = next_nonnote_insn (first); insn; insn = next_nonnote_insn (insn))
6010 if (GET_CODE (insn) == BARRIER)
6011 push_minipool_barrier (insn, address);
6012 else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN
6013 || GET_CODE (insn) == JUMP_INSN)
6017 note_invalid_constants (insn, address);
6018 address += get_attr_length (insn);
6020 /* If the insn is a vector jump, add the size of the table
6021 and skip the table. */
6022 if ((table = is_jump_table (insn)) != NULL)
6024 address += get_jump_table_size (table);
6030 fix = minipool_fix_head;
6032 /* Now scan the fixups and perform the required changes. */
6037 Mfix * last_added_fix;
6038 Mfix * last_barrier = NULL;
6041 /* Skip any further barriers before the next fix. */
6042 while (fix && GET_CODE (fix->insn) == BARRIER)
6045 /* No more fixes. */
6049 last_added_fix = NULL;
6051 for (ftmp = fix; ftmp; ftmp = ftmp->next)
6053 if (GET_CODE (ftmp->insn) == BARRIER)
6055 if (ftmp->address >= minipool_vector_head->max_address)
6058 last_barrier = ftmp;
6060 else if ((ftmp->minipool = add_minipool_forward_ref (ftmp)) == NULL)
6063 last_added_fix = ftmp; /* Keep track of the last fix added. */
6066 /* If we found a barrier, drop back to that; any fixes that we
6067 could have reached but come after the barrier will now go in
6068 the next mini-pool. */
6069 if (last_barrier != NULL)
6071 /* Reduce the refcount for those fixes that won't go into this
6073 for (fdel = last_barrier->next;
6074 fdel && fdel != ftmp;
6077 fdel->minipool->refcount--;
6078 fdel->minipool = NULL;
6081 ftmp = last_barrier;
6085 /* ftmp is first fix that we can't fit into this pool and
6086 there no natural barriers that we could use. Insert a
6087 new barrier in the code somewhere between the previous
6088 fix and this one, and arrange to jump around it. */
6089 HOST_WIDE_INT max_address;
6091 /* The last item on the list of fixes must be a barrier, so
6092 we can never run off the end of the list of fixes without
6093 last_barrier being set. */
6097 max_address = minipool_vector_head->max_address;
6098 /* Check that there isn't another fix that is in range that
6099 we couldn't fit into this pool because the pool was
6100 already too large: we need to put the pool before such an
6102 if (ftmp->address < max_address)
6103 max_address = ftmp->address;
6105 last_barrier = create_fix_barrier (last_added_fix, max_address);
6108 assign_minipool_offsets (last_barrier);
6112 if (GET_CODE (ftmp->insn) != BARRIER
6113 && ((ftmp->minipool = add_minipool_backward_ref (ftmp))
6120 /* Scan over the fixes we have identified for this pool, fixing them
6121 up and adding the constants to the pool itself. */
6122 for (this_fix = fix; this_fix && ftmp != this_fix;
6123 this_fix = this_fix->next)
6124 if (GET_CODE (this_fix->insn) != BARRIER)
6127 = plus_constant (gen_rtx_LABEL_REF (VOIDmode,
6128 minipool_vector_label),
6129 this_fix->minipool->offset);
6130 *this_fix->loc = gen_rtx_MEM (this_fix->mode, addr);
6133 dump_minipool (last_barrier->insn);
6137 /* From now on we must synthesize any constants that we can't handle
6138 directly. This can happen if the RTL gets split during final
6139 instruction generation. */
6140 after_arm_reorg = 1;
6142 /* Free the minipool memory. */
6143 obstack_free (&minipool_obstack, minipool_startobj);
6146 /* Routines to output assembly language. */
6148 /* If the rtx is the correct value then return the string of the number.
6149 In this way we can ensure that valid double constants are generated even
6150 when cross compiling. */
6152 fp_immediate_constant (x)
6158 if (!fpa_consts_inited)
6161 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
6162 for (i = 0; i < 8; i++)
6163 if (REAL_VALUES_EQUAL (r, values_fpa[i]))
6164 return strings_fpa[i];
6169 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
6171 fp_const_from_val (r)
6172 REAL_VALUE_TYPE * r;
6176 if (!fpa_consts_inited)
6179 for (i = 0; i < 8; i++)
6180 if (REAL_VALUES_EQUAL (*r, values_fpa[i]))
6181 return strings_fpa[i];
6186 /* Output the operands of a LDM/STM instruction to STREAM.
6187 MASK is the ARM register set mask of which only bits 0-15 are important.
6188 REG is the base register, either the frame pointer or the stack pointer,
6189 INSTR is the possibly suffixed load or store instruction. */
6192 print_multi_reg (stream, instr, reg, mask)
6199 int not_first = FALSE;
6201 fputc ('\t', stream);
6202 asm_fprintf (stream, instr, reg);
6203 fputs (", {", stream);
6205 for (i = 0; i <= LAST_ARM_REGNUM; i++)
6206 if (mask & (1 << i))
6209 fprintf (stream, ", ");
6211 asm_fprintf (stream, "%r", i);
6215 fprintf (stream, "}%s\n", TARGET_APCS_32 ? "" : "^");
6218 /* Output a 'call' insn. */
6221 output_call (operands)
6224 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
6226 if (REGNO (operands[0]) == LR_REGNUM)
6228 operands[0] = gen_rtx_REG (SImode, IP_REGNUM);
6229 output_asm_insn ("mov%?\t%0, %|lr", operands);
6232 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
6234 if (TARGET_INTERWORK)
6235 output_asm_insn ("bx%?\t%0", operands);
6237 output_asm_insn ("mov%?\t%|pc, %0", operands);
6246 int something_changed = 0;
6248 int code = GET_CODE (x0);
6250 register const char * fmt;
6255 if (REGNO (x0) == LR_REGNUM)
6257 *x = gen_rtx_REG (SImode, IP_REGNUM);
6262 /* Scan through the sub-elements and change any references there. */
6263 fmt = GET_RTX_FORMAT (code);
6265 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6267 something_changed |= eliminate_lr2ip (&XEXP (x0, i));
6268 else if (fmt[i] == 'E')
6269 for (j = 0; j < XVECLEN (x0, i); j++)
6270 something_changed |= eliminate_lr2ip (&XVECEXP (x0, i, j));
6272 return something_changed;
6276 /* Output a 'call' insn that is a reference in memory. */
6279 output_call_mem (operands)
6282 operands[0] = copy_rtx (operands[0]); /* Be ultra careful. */
6283 /* Handle calls using lr by using ip (which may be clobbered in subr anyway). */
6284 if (eliminate_lr2ip (&operands[0]))
6285 output_asm_insn ("mov%?\t%|ip, %|lr", operands);
6287 if (TARGET_INTERWORK)
6289 output_asm_insn ("ldr%?\t%|ip, %0", operands);
6290 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
6291 output_asm_insn ("bx%?\t%|ip", operands);
6295 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
6296 output_asm_insn ("ldr%?\t%|pc, %0", operands);
6303 /* Output a move from arm registers to an fpu registers.
6304 OPERANDS[0] is an fpu register.
6305 OPERANDS[1] is the first registers of an arm register pair. */
6308 output_mov_long_double_fpu_from_arm (operands)
6311 int arm_reg0 = REGNO (operands[1]);
6314 if (arm_reg0 == IP_REGNUM)
6317 ops[0] = gen_rtx_REG (SImode, arm_reg0);
6318 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
6319 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
6321 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops);
6322 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands);
6327 /* Output a move from an fpu register to arm registers.
6328 OPERANDS[0] is the first registers of an arm register pair.
6329 OPERANDS[1] is an fpu register. */
6332 output_mov_long_double_arm_from_fpu (operands)
6335 int arm_reg0 = REGNO (operands[0]);
6338 if (arm_reg0 == IP_REGNUM)
6341 ops[0] = gen_rtx_REG (SImode, arm_reg0);
6342 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
6343 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
6345 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands);
6346 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops);
6350 /* Output a move from arm registers to arm registers of a long double
6351 OPERANDS[0] is the destination.
6352 OPERANDS[1] is the source. */
6354 output_mov_long_double_arm_from_arm (operands)
6357 /* We have to be careful here because the two might overlap. */
6358 int dest_start = REGNO (operands[0]);
6359 int src_start = REGNO (operands[1]);
6363 if (dest_start < src_start)
6365 for (i = 0; i < 3; i++)
6367 ops[0] = gen_rtx_REG (SImode, dest_start + i);
6368 ops[1] = gen_rtx_REG (SImode, src_start + i);
6369 output_asm_insn ("mov%?\t%0, %1", ops);
6374 for (i = 2; i >= 0; i--)
6376 ops[0] = gen_rtx_REG (SImode, dest_start + i);
6377 ops[1] = gen_rtx_REG (SImode, src_start + i);
6378 output_asm_insn ("mov%?\t%0, %1", ops);
6386 /* Output a move from arm registers to an fpu registers.
6387 OPERANDS[0] is an fpu register.
6388 OPERANDS[1] is the first registers of an arm register pair. */
6391 output_mov_double_fpu_from_arm (operands)
6394 int arm_reg0 = REGNO (operands[1]);
6397 if (arm_reg0 == IP_REGNUM)
6400 ops[0] = gen_rtx_REG (SImode, arm_reg0);
6401 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
6402 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops);
6403 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands);
6407 /* Output a move from an fpu register to arm registers.
6408 OPERANDS[0] is the first registers of an arm register pair.
6409 OPERANDS[1] is an fpu register. */
6412 output_mov_double_arm_from_fpu (operands)
6415 int arm_reg0 = REGNO (operands[0]);
6418 if (arm_reg0 == IP_REGNUM)
6421 ops[0] = gen_rtx_REG (SImode, arm_reg0);
6422 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
6423 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands);
6424 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops);
6428 /* Output a move between double words.
6429 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
6430 or MEM<-REG and all MEMs must be offsettable addresses. */
6433 output_move_double (operands)
6436 enum rtx_code code0 = GET_CODE (operands[0]);
6437 enum rtx_code code1 = GET_CODE (operands[1]);
6442 int reg0 = REGNO (operands[0]);
6444 otherops[0] = gen_rtx_REG (SImode, 1 + reg0);
6448 int reg1 = REGNO (operands[1]);
6449 if (reg1 == IP_REGNUM)
6452 /* Ensure the second source is not overwritten. */
6453 if (reg1 == reg0 + (WORDS_BIG_ENDIAN ? -1 : 1))
6454 output_asm_insn ("mov%?\t%Q0, %Q1\n\tmov%?\t%R0, %R1", operands);
6456 output_asm_insn ("mov%?\t%R0, %R1\n\tmov%?\t%Q0, %Q1", operands);
6458 else if (code1 == CONST_DOUBLE)
6460 if (GET_MODE (operands[1]) == DFmode)
6463 union real_extract u;
6465 memcpy (&u, &CONST_DOUBLE_LOW (operands[1]), sizeof (u));
6466 REAL_VALUE_TO_TARGET_DOUBLE (u.d, l);
6467 otherops[1] = GEN_INT (l[1]);
6468 operands[1] = GEN_INT (l[0]);
6470 else if (GET_MODE (operands[1]) != VOIDmode)
6472 else if (WORDS_BIG_ENDIAN)
6475 otherops[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
6476 operands[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
6481 otherops[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
6482 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
6485 output_mov_immediate (operands);
6486 output_mov_immediate (otherops);
6488 else if (code1 == CONST_INT)
6490 #if HOST_BITS_PER_WIDE_INT > 32
6491 /* If HOST_WIDE_INT is more than 32 bits, the intval tells us
6492 what the upper word is. */
6493 if (WORDS_BIG_ENDIAN)
6495 otherops[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1])));
6496 operands[1] = GEN_INT (INTVAL (operands[1]) >> 32);
6500 otherops[1] = GEN_INT (INTVAL (operands[1]) >> 32);
6501 operands[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1])));
6504 /* Sign extend the intval into the high-order word. */
6505 if (WORDS_BIG_ENDIAN)
6507 otherops[1] = operands[1];
6508 operands[1] = (INTVAL (operands[1]) < 0
6509 ? constm1_rtx : const0_rtx);
6512 otherops[1] = INTVAL (operands[1]) < 0 ? constm1_rtx : const0_rtx;
6514 output_mov_immediate (otherops);
6515 output_mov_immediate (operands);
6517 else if (code1 == MEM)
6519 switch (GET_CODE (XEXP (operands[1], 0)))
6522 output_asm_insn ("ldm%?ia\t%m1, %M0", operands);
6526 abort (); /* Should never happen now. */
6530 output_asm_insn ("ldm%?db\t%m1!, %M0", operands);
6534 output_asm_insn ("ldm%?ia\t%m1!, %M0", operands);
6538 abort (); /* Should never happen now. */
6543 output_asm_insn ("adr%?\t%0, %1", operands);
6544 output_asm_insn ("ldm%?ia\t%0, %M0", operands);
6548 if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1),
6549 GET_MODE (XEXP (XEXP (operands[1], 0), 1))))
6551 otherops[0] = operands[0];
6552 otherops[1] = XEXP (XEXP (operands[1], 0), 0);
6553 otherops[2] = XEXP (XEXP (operands[1], 0), 1);
6554 if (GET_CODE (XEXP (operands[1], 0)) == PLUS)
6556 if (GET_CODE (otherops[2]) == CONST_INT)
6558 switch (INTVAL (otherops[2]))
6561 output_asm_insn ("ldm%?db\t%1, %M0", otherops);
6564 output_asm_insn ("ldm%?da\t%1, %M0", otherops);
6567 output_asm_insn ("ldm%?ib\t%1, %M0", otherops);
6570 if (!(const_ok_for_arm (INTVAL (otherops[2]))))
6571 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops);
6573 output_asm_insn ("add%?\t%0, %1, %2", otherops);
6576 output_asm_insn ("add%?\t%0, %1, %2", otherops);
6579 output_asm_insn ("sub%?\t%0, %1, %2", otherops);
6581 return "ldm%?ia\t%0, %M0";
6585 otherops[1] = adjust_address (operands[1], VOIDmode, 4);
6586 /* Take care of overlapping base/data reg. */
6587 if (reg_mentioned_p (operands[0], operands[1]))
6589 output_asm_insn ("ldr%?\t%0, %1", otherops);
6590 output_asm_insn ("ldr%?\t%0, %1", operands);
6594 output_asm_insn ("ldr%?\t%0, %1", operands);
6595 output_asm_insn ("ldr%?\t%0, %1", otherops);
6601 abort (); /* Constraints should prevent this. */
6603 else if (code0 == MEM && code1 == REG)
6605 if (REGNO (operands[1]) == IP_REGNUM)
6608 switch (GET_CODE (XEXP (operands[0], 0)))
6611 output_asm_insn ("stm%?ia\t%m0, %M1", operands);
6615 abort (); /* Should never happen now. */
6619 output_asm_insn ("stm%?db\t%m0!, %M1", operands);
6623 output_asm_insn ("stm%?ia\t%m0!, %M1", operands);
6627 abort (); /* Should never happen now. */
6631 if (GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
6633 switch (INTVAL (XEXP (XEXP (operands[0], 0), 1)))
6636 output_asm_insn ("stm%?db\t%m0, %M1", operands);
6640 output_asm_insn ("stm%?da\t%m0, %M1", operands);
6644 output_asm_insn ("stm%?ib\t%m0, %M1", operands);
6651 otherops[0] = adjust_address (operands[0], VOIDmode, 4);
6652 otherops[1] = gen_rtx_REG (SImode, 1 + REGNO (operands[1]));
6653 output_asm_insn ("str%?\t%1, %0", operands);
6654 output_asm_insn ("str%?\t%1, %0", otherops);
6658 abort (); /* Constraints should prevent this */
6664 /* Output an arbitrary MOV reg, #n.
6665 OPERANDS[0] is a register. OPERANDS[1] is a const_int. */
6668 output_mov_immediate (operands)
6671 HOST_WIDE_INT n = INTVAL (operands[1]);
6675 /* Try to use one MOV */
6676 if (const_ok_for_arm (n))
6678 output_asm_insn ("mov%?\t%0, %1", operands);
6682 /* Try to use one MVN */
6683 if (const_ok_for_arm (~n))
6685 operands[1] = GEN_INT (~n);
6686 output_asm_insn ("mvn%?\t%0, %1", operands);
6690 /* If all else fails, make it out of ORRs or BICs as appropriate. */
6692 for (i=0; i < 32; i++)
6696 if (n_ones > 16) /* Shorter to use MVN with BIC in this case. */
6697 output_multi_immediate (operands, "mvn%?\t%0, %1", "bic%?\t%0, %0, %1", 1, ~n);
6699 output_multi_immediate (operands, "mov%?\t%0, %1", "orr%?\t%0, %0, %1", 1, n);
6705 /* Output an ADD r, s, #n where n may be too big for one instruction. If
6706 adding zero to one register, output nothing. */
6709 output_add_immediate (operands)
6712 HOST_WIDE_INT n = INTVAL (operands[2]);
6714 if (n != 0 || REGNO (operands[0]) != REGNO (operands[1]))
6717 output_multi_immediate (operands,
6718 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
6721 output_multi_immediate (operands,
6722 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
6729 /* Output a multiple immediate operation.
6730 OPERANDS is the vector of operands referred to in the output patterns.
6731 INSTR1 is the output pattern to use for the first constant.
6732 INSTR2 is the output pattern to use for subsequent constants.
6733 IMMED_OP is the index of the constant slot in OPERANDS.
6734 N is the constant value. */
6737 output_multi_immediate (operands, instr1, instr2, immed_op, n)
6739 const char * instr1;
6740 const char * instr2;
6744 #if HOST_BITS_PER_WIDE_INT > 32
6750 operands[immed_op] = const0_rtx;
6751 output_asm_insn (instr1, operands); /* Quick and easy output. */
6756 const char * instr = instr1;
6758 /* Note that n is never zero here (which would give no output). */
6759 for (i = 0; i < 32; i += 2)
6763 operands[immed_op] = GEN_INT (n & (255 << i));
6764 output_asm_insn (instr, operands);
6775 /* Return the appropriate ARM instruction for the operation code.
6776 The returned result should not be overwritten. OP is the rtx of the
6777 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
6781 arithmetic_instr (op, shift_first_arg)
6783 int shift_first_arg;
6785 switch (GET_CODE (op))
6791 return shift_first_arg ? "rsb" : "sub";
6808 /* Ensure valid constant shifts and return the appropriate shift mnemonic
6809 for the operation code. The returned result should not be overwritten.
6810 OP is the rtx code of the shift.
6811 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
6815 shift_op (op, amountp)
6817 HOST_WIDE_INT *amountp;
6820 enum rtx_code code = GET_CODE (op);
6822 if (GET_CODE (XEXP (op, 1)) == REG || GET_CODE (XEXP (op, 1)) == SUBREG)
6824 else if (GET_CODE (XEXP (op, 1)) == CONST_INT)
6825 *amountp = INTVAL (XEXP (op, 1));
6848 /* We never have to worry about the amount being other than a
6849 power of 2, since this case can never be reloaded from a reg. */
6851 *amountp = int_log2 (*amountp);
6862 /* This is not 100% correct, but follows from the desire to merge
6863 multiplication by a power of 2 with the recognizer for a
6864 shift. >=32 is not a valid shift for "asl", so we must try and
6865 output a shift that produces the correct arithmetical result.
6866 Using lsr #32 is identical except for the fact that the carry bit
6867 is not set correctly if we set the flags; but we never use the
6868 carry bit from such an operation, so we can ignore that. */
6869 if (code == ROTATERT)
6870 *amountp &= 31; /* Rotate is just modulo 32 */
6871 else if (*amountp != (*amountp & 31))
6878 /* Shifts of 0 are no-ops. */
6887 /* Obtain the shift from the POWER of two. */
6888 static HOST_WIDE_INT
6890 HOST_WIDE_INT power;
6892 HOST_WIDE_INT shift = 0;
6894 while ((((HOST_WIDE_INT) 1 << shift) & power) == 0)
6904 /* Output a .ascii pseudo-op, keeping track of lengths. This is because
6905 /bin/as is horribly restrictive. */
6906 #define MAX_ASCII_LEN 51
6909 output_ascii_pseudo_op (stream, p, len)
6911 const unsigned char * p;
6917 fputs ("\t.ascii\t\"", stream);
6919 for (i = 0; i < len; i++)
6921 register int c = p[i];
6923 if (len_so_far >= MAX_ASCII_LEN)
6925 fputs ("\"\n\t.ascii\t\"", stream);
6932 fputs ("\\t", stream);
6937 fputs ("\\f", stream);
6942 fputs ("\\b", stream);
6947 fputs ("\\r", stream);
6951 case TARGET_NEWLINE:
6952 fputs ("\\n", stream);
6954 if ((c >= ' ' && c <= '~')
6956 /* This is a good place for a line break. */
6957 len_so_far = MAX_ASCII_LEN;
6964 putc ('\\', stream);
6969 if (c >= ' ' && c <= '~')
6976 fprintf (stream, "\\%03o", c);
6983 fputs ("\"\n", stream);
6986 /* Compute a bit mask of which registers need to be
6987 saved on the stack for the current function. */
6989 static unsigned long
6990 arm_compute_save_reg_mask ()
6992 unsigned int save_reg_mask = 0;
6994 unsigned long func_type = arm_current_func_type ();
6996 if (IS_NAKED (func_type))
6997 /* This should never really happen. */
7000 /* If we are creating a stack frame, then we must save the frame pointer,
7001 IP (which will hold the old stack pointer), LR and the PC. */
7002 if (frame_pointer_needed)
7004 (1 << ARM_HARD_FRAME_POINTER_REGNUM)
7009 /* Volatile functions do not return, so there
7010 is no need to save any other registers. */
7011 if (IS_VOLATILE (func_type))
7012 return save_reg_mask;
7014 if (IS_INTERRUPT (func_type))
7016 unsigned int max_reg;
7018 /* Interrupt functions must not corrupt any registers,
7019 even call clobbered ones. If this is a leaf function
7020 we can just examine the registers used by the RTL, but
7021 otherwise we have to assume that whatever function is
7022 called might clobber anything, and so we have to save
7023 all the call-clobbered registers as well. */
7024 if (ARM_FUNC_TYPE (func_type) == ARM_FT_FIQ)
7025 /* FIQ handlers have registers r8 - r12 banked, so
7026 we only need to check r0 - r7, Normal ISRs only
7027 bank r14 and r15, so ew must check up to r12.
7028 r13 is the stack pointer which is always preserved,
7029 so we do not need to consider it here. */
7034 for (reg = 0; reg <= max_reg; reg++)
7035 if (regs_ever_live[reg]
7036 || (! current_function_is_leaf && call_used_regs [reg]))
7037 save_reg_mask |= (1 << reg);
7041 /* In the normal case we only need to save those registers
7042 which are call saved and which are used by this function. */
7043 for (reg = 0; reg <= 10; reg++)
7044 if (regs_ever_live[reg] && ! call_used_regs [reg])
7045 save_reg_mask |= (1 << reg);
7047 /* Handle the frame pointer as a special case. */
7048 if (! TARGET_APCS_FRAME
7049 && ! frame_pointer_needed
7050 && regs_ever_live[HARD_FRAME_POINTER_REGNUM]
7051 && ! call_used_regs[HARD_FRAME_POINTER_REGNUM])
7052 save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM;
7054 /* If we aren't loading the PIC register,
7055 don't stack it even though it may be live. */
7057 && ! TARGET_SINGLE_PIC_BASE
7058 && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
7059 save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
7062 /* Decide if we need to save the link register.
7063 Interrupt routines have their own banked link register,
7064 so they never need to save it.
7065 Otheriwse if we do not use the link register we do not need to save
7066 it. If we are pushing other registers onto the stack however, we
7067 can save an instruction in the epilogue by pushing the link register
7068 now and then popping it back into the PC. This incurs extra memory
7069 accesses though, so we only do it when optimising for size, and only
7070 if we know that we will not need a fancy return sequence. */
7071 if (! IS_INTERRUPT (func_type)
7072 && (regs_ever_live [LR_REGNUM]
7075 && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL)))
7076 save_reg_mask |= 1 << LR_REGNUM;
7078 if (cfun->machine->lr_save_eliminated)
7079 save_reg_mask &= ~ (1 << LR_REGNUM);
7081 return save_reg_mask;
7084 /* Generate a function exit sequence. If REALLY_RETURN is true, then do
7085 everything bar the final return instruction. */
7088 output_return_instruction (operand, really_return, reverse)
7093 char conditional[10];
7096 unsigned long live_regs_mask;
7097 unsigned long func_type;
7099 func_type = arm_current_func_type ();
7101 if (IS_NAKED (func_type))
7104 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
7106 /* If this function was declared non-returning, and we have found a tail
7107 call, then we have to trust that the called function won't return. */
7112 /* Otherwise, trap an attempted return by aborting. */
7114 ops[1] = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)"
7116 assemble_external_libcall (ops[1]);
7117 output_asm_insn (reverse ? "bl%D0\t%a1" : "bl%d0\t%a1", ops);
7123 if (current_function_calls_alloca && !really_return)
7126 /* Construct the conditional part of the instruction(s) to be emitted. */
7127 sprintf (conditional, "%%?%%%c0", reverse ? 'D' : 'd');
7129 return_used_this_function = 1;
7131 live_regs_mask = arm_compute_save_reg_mask ();
7133 /* On some ARM architectures it is faster to use LDR rather than LDM to
7134 load a single register. On other architectures, the cost is the same.
7135 In 26 bit mode we have to use LDM in order to be able to restore the CPSR. */
7136 if ((live_regs_mask == (1 << LR_REGNUM))
7137 && ! TARGET_INTERWORK
7138 && ! IS_INTERRUPT (func_type)
7139 && (! really_return || TARGET_APCS_32))
7141 if (! really_return)
7142 sprintf (instr, "ldr%s\t%%|lr, [%%|sp], #4", conditional);
7144 sprintf (instr, "ldr%s\t%%|pc, [%%|sp], #4", conditional);
7146 else if (live_regs_mask)
7148 if ((live_regs_mask & (1 << IP_REGNUM)) == (1 << IP_REGNUM))
7149 /* There are two possible reasons for the IP register being saved.
7150 Either a stack frame was created, in which case IP contains the
7151 old stack pointer, or an ISR routine corrupted it. If this in an
7152 ISR routine then just restore IP, otherwise restore IP into SP. */
7153 if (! IS_INTERRUPT (func_type))
7155 live_regs_mask &= ~ (1 << IP_REGNUM);
7156 live_regs_mask |= (1 << SP_REGNUM);
7159 /* Generate the load multiple instruction to restore the registers. */
7160 if (frame_pointer_needed)
7161 sprintf (instr, "ldm%sea\t%%|fp, {", conditional);
7163 sprintf (instr, "ldm%sfd\t%%|sp!, {", conditional);
7165 for (reg = 0; reg <= SP_REGNUM; reg++)
7166 if (live_regs_mask & (1 << reg))
7168 strcat (instr, "%|");
7169 strcat (instr, reg_names[reg]);
7170 strcat (instr, ", ");
7173 if ((live_regs_mask & (1 << LR_REGNUM)) == 0)
7175 /* If we are not restoring the LR register then we will
7176 have added one too many commas to the list above.
7177 Replace it with a closing brace. */
7178 instr [strlen (instr) - 2] = '}';
7182 strcat (instr, "%|");
7184 /* At this point there should only be one or two registers left in
7185 live_regs_mask: always LR, and possibly PC if we created a stack
7186 frame. LR contains the return address. If we do not have any
7187 special requirements for function exit (eg interworking, or ISR)
7188 then we can load this value directly into the PC and save an
7190 if (! TARGET_INTERWORK
7191 && ! IS_INTERRUPT (func_type)
7193 strcat (instr, reg_names [PC_REGNUM]);
7195 strcat (instr, reg_names [LR_REGNUM]);
7197 strcat (instr, (TARGET_APCS_32 || !really_return) ? "}" : "}^");
7202 /* See if we need to generate an extra instruction to
7203 perform the actual function return. */
7204 switch ((int) ARM_FUNC_TYPE (func_type))
7208 output_asm_insn (instr, & operand);
7210 strcpy (instr, "sub");
7211 strcat (instr, conditional);
7212 strcat (instr, "s\t%|pc, %|lr, #4");
7215 case ARM_FT_EXCEPTION:
7216 output_asm_insn (instr, & operand);
7218 strcpy (instr, "mov");
7219 strcat (instr, conditional);
7220 strcat (instr, "s\t%|pc, %|lr");
7223 case ARM_FT_INTERWORKED:
7224 output_asm_insn (instr, & operand);
7226 strcpy (instr, "bx");
7227 strcat (instr, conditional);
7228 strcat (instr, "\t%|lr");
7232 /* The return has already been handled
7233 by loading the LR into the PC. */
7234 if ((live_regs_mask & (1 << LR_REGNUM)) == 0)
7236 output_asm_insn (instr, & operand);
7238 strcpy (instr, "mov");
7239 strcat (instr, conditional);
7240 if (! TARGET_APCS_32)
7241 strcat (instr, "s");
7242 strcat (instr, "\t%|pc, %|lr");
7248 else if (really_return)
7250 switch ((int) ARM_FUNC_TYPE (func_type))
7254 sprintf (instr, "sub%ss\t%%|pc, %%|lr, #4", conditional);
7257 case ARM_FT_INTERWORKED:
7258 sprintf (instr, "bx%s\t%%|lr", conditional);
7261 case ARM_FT_EXCEPTION:
7262 sprintf (instr, "mov%ss\t%%|pc, %%|lr", conditional);
7266 sprintf (instr, "mov%s%s\t%%|pc, %%|lr",
7267 conditional, TARGET_APCS_32 ? "" : "s");
7272 /* Nothing to load off the stack, and
7273 no return instruction to generate. */
7276 output_asm_insn (instr, & operand);
7281 /* Write the function name into the code section, directly preceding
7282 the function prologue.
7284 Code will be output similar to this:
7286 .ascii "arm_poke_function_name", 0
7289 .word 0xff000000 + (t1 - t0)
7290 arm_poke_function_name
7292 stmfd sp!, {fp, ip, lr, pc}
7295 When performing a stack backtrace, code can inspect the value
7296 of 'pc' stored at 'fp' + 0. If the trace function then looks
7297 at location pc - 12 and the top 8 bits are set, then we know
7298 that there is a function name embedded immediately preceding this
7299 location and has length ((pc[-3]) & 0xff000000).
7301 We assume that pc is declared as a pointer to an unsigned long.
7303 It is of no benefit to output the function name if we are assembling
7304 a leaf function. These function types will not contain a stack
7305 backtrace structure, therefore it is not possible to determine the
7309 arm_poke_function_name (stream, name)
7313 unsigned long alignlength;
7314 unsigned long length;
7317 length = strlen (name) + 1;
7318 alignlength = ROUND_UP (length);
7320 ASM_OUTPUT_ASCII (stream, name, length);
7321 ASM_OUTPUT_ALIGN (stream, 2);
7322 x = GEN_INT ((unsigned HOST_WIDE_INT) 0xff000000 + alignlength);
7323 ASM_OUTPUT_INT (stream, x);
7326 /* Place some comments into the assembler stream
7327 describing the current function. */
7330 arm_output_function_prologue (f, frame_size)
7332 HOST_WIDE_INT frame_size;
7334 unsigned long func_type;
7338 thumb_output_function_prologue (f, frame_size);
7343 if (arm_ccfsm_state || arm_target_insn)
7346 func_type = arm_current_func_type ();
7348 switch ((int) ARM_FUNC_TYPE (func_type))
7353 case ARM_FT_INTERWORKED:
7354 asm_fprintf (f, "\t%@ Function supports interworking.\n");
7356 case ARM_FT_EXCEPTION_HANDLER:
7357 asm_fprintf (f, "\t%@ C++ Exception Handler.\n");
7360 asm_fprintf (f, "\t%@ Interrupt Service Routine.\n");
7363 asm_fprintf (f, "\t%@ Fast Interrupt Service Routine.\n");
7365 case ARM_FT_EXCEPTION:
7366 asm_fprintf (f, "\t%@ ARM Exception Handler.\n");
7370 if (IS_NAKED (func_type))
7371 asm_fprintf (f, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n");
7373 if (IS_VOLATILE (func_type))
7374 asm_fprintf (f, "\t%@ Volatile: function does not return.\n");
7376 if (IS_NESTED (func_type))
7377 asm_fprintf (f, "\t%@ Nested: function declared inside another function.\n");
7379 asm_fprintf (f, "\t%@ args = %d, pretend = %d, frame = %d\n",
7380 current_function_args_size,
7381 current_function_pretend_args_size, frame_size);
7383 asm_fprintf (f, "\t%@ frame_needed = %d, current_function_anonymous_args = %d\n",
7384 frame_pointer_needed,
7385 current_function_anonymous_args);
7387 if (cfun->machine->lr_save_eliminated)
7388 asm_fprintf (f, "\t%@ link register save eliminated.\n");
7390 #ifdef AOF_ASSEMBLER
7392 asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, PIC_OFFSET_TABLE_REGNUM);
7395 return_used_this_function = 0;
7399 arm_output_epilogue (really_return)
7403 unsigned long saved_regs_mask;
7404 unsigned long func_type;
7405 /* If we need this, then it will always be at least this much. */
7406 int floats_offset = 12;
7408 int frame_size = get_frame_size ();
7409 FILE * f = asm_out_file;
7410 rtx eh_ofs = cfun->machine->eh_epilogue_sp_ofs;
7412 /* If we have already generated the return instruction
7413 then it is futile to generate anything else. */
7414 if (use_return_insn (FALSE) && return_used_this_function)
7417 func_type = arm_current_func_type ();
7419 if (IS_NAKED (func_type))
7420 /* Naked functions don't have epilogues. */
7423 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
7427 /* A volatile function should never return. Call abort. */
7428 op = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" : "abort");
7429 assemble_external_libcall (op);
7430 output_asm_insn ("bl\t%a0", &op);
7435 if (ARM_FUNC_TYPE (func_type) == ARM_FT_EXCEPTION_HANDLER
7437 /* If we are throwing an exception, then we really must
7438 be doing a return, so we can't tail-call. */
7441 saved_regs_mask = arm_compute_save_reg_mask ();
7443 /* Compute how far away the floats will be. */
7444 for (reg = 0; reg <= LAST_ARM_REGNUM; reg ++)
7445 if (saved_regs_mask & (1 << reg))
7448 if (frame_pointer_needed)
7450 if (arm_fpu_arch == FP_SOFT2)
7452 for (reg = LAST_ARM_FP_REGNUM; reg >= FIRST_ARM_FP_REGNUM; reg--)
7453 if (regs_ever_live[reg] && !call_used_regs[reg])
7455 floats_offset += 12;
7456 asm_fprintf (f, "\tldfe\t%r, [%r, #-%d]\n",
7457 reg, FP_REGNUM, floats_offset);
7462 int start_reg = LAST_ARM_FP_REGNUM;
7464 for (reg = LAST_ARM_FP_REGNUM; reg >= FIRST_ARM_FP_REGNUM; reg--)
7466 if (regs_ever_live[reg] && !call_used_regs[reg])
7468 floats_offset += 12;
7470 /* We can't unstack more than four registers at once. */
7471 if (start_reg - reg == 3)
7473 asm_fprintf (f, "\tlfm\t%r, 4, [%r, #-%d]\n",
7474 reg, FP_REGNUM, floats_offset);
7475 start_reg = reg - 1;
7480 if (reg != start_reg)
7481 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
7482 reg + 1, start_reg - reg,
7483 FP_REGNUM, floats_offset);
7484 start_reg = reg - 1;
7488 /* Just in case the last register checked also needs unstacking. */
7489 if (reg != start_reg)
7490 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
7491 reg + 1, start_reg - reg,
7492 FP_REGNUM, floats_offset);
7495 /* saved_regs_mask should contain the IP, which at the time of stack
7496 frame generation actually contains the old stack pointer. So a
7497 quick way to unwind the stack is just pop the IP register directly
7498 into the stack pointer. */
7499 if ((saved_regs_mask & (1 << IP_REGNUM)) == 0)
7501 saved_regs_mask &= ~ (1 << IP_REGNUM);
7502 saved_regs_mask |= (1 << SP_REGNUM);
7504 /* There are two registers left in saved_regs_mask - LR and PC. We
7505 only need to restore the LR register (the return address), but to
7506 save time we can load it directly into the PC, unless we need a
7507 special function exit sequence, or we are not really returning. */
7508 if (really_return && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL)
7509 /* Delete the LR from the register mask, so that the LR on
7510 the stack is loaded into the PC in the register mask. */
7511 saved_regs_mask &= ~ (1 << LR_REGNUM);
7513 saved_regs_mask &= ~ (1 << PC_REGNUM);
7515 print_multi_reg (f, "ldmea\t%r", FP_REGNUM, saved_regs_mask);
7517 if (IS_INTERRUPT (func_type))
7518 /* Interrupt handlers will have pushed the
7519 IP onto the stack, so restore it now. */
7520 print_multi_reg (f, "ldmea\t%r", SP_REGNUM, 1 << IP_REGNUM);
7524 /* Restore stack pointer if necessary. */
7525 if (frame_size + current_function_outgoing_args_size != 0)
7527 operands[0] = operands[1] = stack_pointer_rtx;
7528 operands[2] = GEN_INT (frame_size
7529 + current_function_outgoing_args_size);
7530 output_add_immediate (operands);
7533 if (arm_fpu_arch == FP_SOFT2)
7535 for (reg = FIRST_ARM_FP_REGNUM; reg <= LAST_ARM_FP_REGNUM; reg++)
7536 if (regs_ever_live[reg] && !call_used_regs[reg])
7537 asm_fprintf (f, "\tldfe\t%r, [%r], #12\n",
7542 int start_reg = FIRST_ARM_FP_REGNUM;
7544 for (reg = FIRST_ARM_FP_REGNUM; reg <= LAST_ARM_FP_REGNUM; reg++)
7546 if (regs_ever_live[reg] && !call_used_regs[reg])
7548 if (reg - start_reg == 3)
7550 asm_fprintf (f, "\tlfmfd\t%r, 4, [%r]!\n",
7551 start_reg, SP_REGNUM);
7552 start_reg = reg + 1;
7557 if (reg != start_reg)
7558 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
7559 start_reg, reg - start_reg,
7562 start_reg = reg + 1;
7566 /* Just in case the last register checked also needs unstacking. */
7567 if (reg != start_reg)
7568 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
7569 start_reg, reg - start_reg, SP_REGNUM);
7572 /* If we can, restore the LR into the PC. */
7573 if (ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
7575 && current_function_pretend_args_size == 0
7576 && saved_regs_mask & (1 << LR_REGNUM))
7578 saved_regs_mask &= ~ (1 << LR_REGNUM);
7579 saved_regs_mask |= (1 << PC_REGNUM);
7582 /* Load the registers off the stack. If we only have one register
7583 to load use the LDR instruction - it is faster. */
7584 if (saved_regs_mask == (1 << LR_REGNUM))
7586 /* The excpetion handler ignores the LR, so we do
7587 not really need to load it off the stack. */
7589 asm_fprintf (f, "\tadd\t%r, %r, #4\n", SP_REGNUM, SP_REGNUM);
7591 asm_fprintf (f, "\tldr\t%r, [%r], #4\n", LR_REGNUM, SP_REGNUM);
7593 else if (saved_regs_mask)
7594 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, saved_regs_mask);
7596 if (current_function_pretend_args_size)
7598 /* Unwind the pre-pushed regs. */
7599 operands[0] = operands[1] = stack_pointer_rtx;
7600 operands[2] = GEN_INT (current_function_pretend_args_size);
7601 output_add_immediate (operands);
7606 if (ARM_FUNC_TYPE (func_type) == ARM_FT_EXCEPTION_HANDLER)
7607 /* Adjust the stack to remove the exception handler stuff. */
7608 asm_fprintf (f, "\tadd\t%r, %r, %r\n", SP_REGNUM, SP_REGNUM,
7612 if (! really_return)
7615 /* Generate the return instruction. */
7616 switch ((int) ARM_FUNC_TYPE (func_type))
7618 case ARM_FT_EXCEPTION_HANDLER:
7619 /* Even in 26-bit mode we do a mov (rather than a movs)
7620 because we don't have the PSR bits set in the address. */
7621 asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, EXCEPTION_LR_REGNUM);
7626 asm_fprintf (f, "\tsubs\t%r, %r, #4\n", PC_REGNUM, LR_REGNUM);
7629 case ARM_FT_EXCEPTION:
7630 asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM);
7633 case ARM_FT_INTERWORKED:
7634 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
7638 if (frame_pointer_needed)
7639 /* If we used the frame pointer then the return adddress
7640 will have been loaded off the stack directly into the
7641 PC, so there is no need to issue a MOV instruction
7644 else if (current_function_pretend_args_size == 0
7645 && (saved_regs_mask & (1 << LR_REGNUM)))
7646 /* Similarly we may have been able to load LR into the PC
7647 even if we did not create a stack frame. */
7649 else if (TARGET_APCS_32)
7650 asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, LR_REGNUM);
7652 asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM);
7660 arm_output_function_epilogue (file, frame_size)
7661 FILE *file ATTRIBUTE_UNUSED;
7662 HOST_WIDE_INT frame_size;
7666 /* ??? Probably not safe to set this here, since it assumes that a
7667 function will be emitted as assembly immediately after we generate
7668 RTL for it. This does not happen for inline functions. */
7669 return_used_this_function = 0;
7673 if (use_return_insn (FALSE)
7674 && return_used_this_function
7675 && (frame_size + current_function_outgoing_args_size) != 0
7676 && !frame_pointer_needed)
7679 /* Reset the ARM-specific per-function variables. */
7680 current_function_anonymous_args = 0;
7681 after_arm_reorg = 0;
7685 /* Generate and emit an insn that we will recognize as a push_multi.
7686 Unfortunately, since this insn does not reflect very well the actual
7687 semantics of the operation, we need to annotate the insn for the benefit
7688 of DWARF2 frame unwind information. */
7691 emit_multi_reg_push (mask)
7699 int dwarf_par_index;
7702 for (i = 0; i <= LAST_ARM_REGNUM; i++)
7703 if (mask & (1 << i))
7706 if (num_regs == 0 || num_regs > 16)
7709 /* We don't record the PC in the dwarf frame information. */
7710 num_dwarf_regs = num_regs;
7711 if (mask & (1 << PC_REGNUM))
7714 /* For the body of the insn we are going to generate an UNSPEC in
7715 parallel with several USEs. This allows the insn to be recognised
7716 by the push_multi pattern in the arm.md file. The insn looks
7717 something like this:
7720 (set (mem:BLK (pre_dec:BLK (reg:SI sp)))
7721 (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT))
7722 (use (reg:SI 11 fp))
7723 (use (reg:SI 12 ip))
7724 (use (reg:SI 14 lr))
7725 (use (reg:SI 15 pc))
7728 For the frame note however, we try to be more explicit and actually
7729 show each register being stored into the stack frame, plus a (single)
7730 decrement of the stack pointer. We do it this way in order to be
7731 friendly to the stack unwinding code, which only wants to see a single
7732 stack decrement per instruction. The RTL we generate for the note looks
7733 something like this:
7736 (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20)))
7737 (set (mem:SI (reg:SI sp)) (reg:SI r4))
7738 (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp))
7739 (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip))
7740 (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr))
7743 This sequence is used both by the code to support stack unwinding for
7744 exceptions handlers and the code to generate dwarf2 frame debugging. */
7746 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_regs));
7747 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (num_dwarf_regs + 1));
7748 RTX_FRAME_RELATED_P (dwarf) = 1;
7749 dwarf_par_index = 1;
7751 for (i = 0; i <= LAST_ARM_REGNUM; i++)
7753 if (mask & (1 << i))
7755 reg = gen_rtx_REG (SImode, i);
7758 = gen_rtx_SET (VOIDmode,
7759 gen_rtx_MEM (BLKmode,
7760 gen_rtx_PRE_DEC (BLKmode,
7761 stack_pointer_rtx)),
7762 gen_rtx_UNSPEC (BLKmode,
7768 tmp = gen_rtx_SET (VOIDmode,
7769 gen_rtx_MEM (SImode, stack_pointer_rtx),
7771 RTX_FRAME_RELATED_P (tmp) = 1;
7772 XVECEXP (dwarf, 0, dwarf_par_index) = tmp;
7780 for (j = 1, i++; j < num_regs; i++)
7782 if (mask & (1 << i))
7784 reg = gen_rtx_REG (SImode, i);
7786 XVECEXP (par, 0, j) = gen_rtx_USE (VOIDmode, reg);
7790 tmp = gen_rtx_SET (VOIDmode,
7791 gen_rtx_MEM (SImode,
7792 plus_constant (stack_pointer_rtx,
7795 RTX_FRAME_RELATED_P (tmp) = 1;
7796 XVECEXP (dwarf, 0, dwarf_par_index++) = tmp;
7803 par = emit_insn (par);
7805 tmp = gen_rtx_SET (SImode,
7807 gen_rtx_PLUS (SImode,
7809 GEN_INT (-4 * num_regs)));
7810 RTX_FRAME_RELATED_P (tmp) = 1;
7811 XVECEXP (dwarf, 0, 0) = tmp;
7813 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
7819 emit_sfm (base_reg, count)
7828 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
7829 dwarf = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
7830 RTX_FRAME_RELATED_P (dwarf) = 1;
7832 reg = gen_rtx_REG (XFmode, base_reg++);
7835 = gen_rtx_SET (VOIDmode,
7836 gen_rtx_MEM (BLKmode,
7837 gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
7838 gen_rtx_UNSPEC (BLKmode,
7842 = gen_rtx_SET (VOIDmode,
7843 gen_rtx_MEM (XFmode,
7844 gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
7846 RTX_FRAME_RELATED_P (tmp) = 1;
7847 XVECEXP (dwarf, 0, count - 1) = tmp;
7849 for (i = 1; i < count; i++)
7851 reg = gen_rtx_REG (XFmode, base_reg++);
7852 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
7854 tmp = gen_rtx_SET (VOIDmode,
7855 gen_rtx_MEM (XFmode,
7856 gen_rtx_PRE_DEC (BLKmode,
7857 stack_pointer_rtx)),
7859 RTX_FRAME_RELATED_P (tmp) = 1;
7860 XVECEXP (dwarf, 0, count - i - 1) = tmp;
7863 par = emit_insn (par);
7864 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
7869 /* Compute the distance from register FROM to register TO.
7870 These can be the arg pointer (26), the soft frame pointer (25),
7871 the stack pointer (13) or the hard frame pointer (11).
7872 Typical stack layout looks like this:
7874 old stack pointer -> | |
7877 | | saved arguments for
7878 | | vararg functions
7881 hard FP & arg pointer -> | | \
7889 soft frame pointer -> | | /
7899 current stack pointer -> | | /
7902 For a given funciton some or all of these stack compomnents
7903 may not be needed, giving rise to the possibility of
7904 eliminating some of the registers.
7906 The values returned by this function must reflect the behaviour
7907 of arm_expand_prologue() and arm_compute_save_reg_mask().
7909 The sign of the number returned reflects the direction of stack
7910 growth, so the values are positive for all eliminations except
7911 from the soft frame pointer to the hard frame pointer. */
7914 arm_compute_initial_elimination_offset (from, to)
7918 unsigned int local_vars = (get_frame_size () + 3) & ~3;
7919 unsigned int outgoing_args = current_function_outgoing_args_size;
7920 unsigned int stack_frame;
7921 unsigned int call_saved_registers;
7922 unsigned long func_type;
7924 func_type = arm_current_func_type ();
7926 /* Volatile functions never return, so there is
7927 no need to save call saved registers. */
7928 call_saved_registers = 0;
7929 if (! IS_VOLATILE (func_type))
7933 /* In theory we should check all of the hard registers to
7934 see if they will be saved onto the stack. In practice
7935 registers 11 upwards have special meanings and need to
7936 be check individually. */
7937 for (reg = 0; reg <= 10; reg ++)
7938 if (regs_ever_live[reg] && ! call_used_regs[reg])
7939 call_saved_registers += 4;
7941 /* Determine if register 11 will be clobbered. */
7942 if (! TARGET_APCS_FRAME
7943 && ! frame_pointer_needed
7944 && regs_ever_live[HARD_FRAME_POINTER_REGNUM]
7945 && ! call_used_regs[HARD_FRAME_POINTER_REGNUM])
7946 call_saved_registers += 4;
7948 /* The PIC register is fixed, so if the function will
7949 corrupt it, it has to be saved onto the stack. */
7950 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
7951 call_saved_registers += 4;
7953 if (regs_ever_live[LR_REGNUM]
7954 /* If a stack frame is going to be created, the LR will
7955 be saved as part of that, so we do not need to allow
7957 && ! frame_pointer_needed)
7958 call_saved_registers += 4;
7960 /* If the hard floating point registers are going to be
7961 used then they must be saved on the stack as well.
7962 Each register occupies 12 bytes of stack space. */
7963 for (reg = FIRST_ARM_FP_REGNUM; reg <= LAST_ARM_FP_REGNUM; reg ++)
7964 if (regs_ever_live[reg] && ! call_used_regs[reg])
7965 call_saved_registers += 12;
7968 /* The stack frame contains 4 registers - the old frame pointer,
7969 the old stack pointer, the return address and PC of the start
7971 stack_frame = frame_pointer_needed ? 16 : 0;
7973 /* OK, now we have enough information to compute the distances.
7974 There must be an entry in these switch tables for each pair
7975 of registers in ELIMINABLE_REGS, even if some of the entries
7976 seem to be redundant or useless. */
7979 case ARG_POINTER_REGNUM:
7982 case THUMB_HARD_FRAME_POINTER_REGNUM:
7985 case FRAME_POINTER_REGNUM:
7986 /* This is the reverse of the soft frame pointer
7987 to hard frame pointer elimination below. */
7988 if (call_saved_registers == 0 && stack_frame == 0)
7990 return (call_saved_registers + stack_frame - 4);
7992 case ARM_HARD_FRAME_POINTER_REGNUM:
7993 /* If there is no stack frame then the hard
7994 frame pointer and the arg pointer coincide. */
7995 if (stack_frame == 0 && call_saved_registers != 0)
7997 /* FIXME: Not sure about this. Maybe we should always return 0 ? */
7998 return (frame_pointer_needed
7999 && current_function_needs_context
8000 && ! current_function_anonymous_args) ? 4 : 0;
8002 case STACK_POINTER_REGNUM:
8003 /* If nothing has been pushed on the stack at all
8004 then this will return -4. This *is* correct! */
8005 return call_saved_registers + stack_frame + local_vars + outgoing_args - 4;
8012 case FRAME_POINTER_REGNUM:
8015 case THUMB_HARD_FRAME_POINTER_REGNUM:
8018 case ARM_HARD_FRAME_POINTER_REGNUM:
8019 /* The hard frame pointer points to the top entry in the
8020 stack frame. The soft frame pointer to the bottom entry
8021 in the stack frame. If there is no stack frame at all,
8022 then they are identical. */
8023 if (call_saved_registers == 0 && stack_frame == 0)
8025 return - (call_saved_registers + stack_frame - 4);
8027 case STACK_POINTER_REGNUM:
8028 return local_vars + outgoing_args;
8036 /* You cannot eliminate from the stack pointer.
8037 In theory you could eliminate from the hard frame
8038 pointer to the stack pointer, but this will never
8039 happen, since if a stack frame is not needed the
8040 hard frame pointer will never be used. */
8045 /* Generate the prologue instructions for entry into an ARM function. */
8048 arm_expand_prologue ()
8054 unsigned long live_regs_mask;
8055 unsigned long func_type;
8057 int saved_pretend_args = 0;
8058 unsigned int args_to_push;
8060 func_type = arm_current_func_type ();
8062 /* Naked functions don't have prologues. */
8063 if (IS_NAKED (func_type))
8066 /* Make a copy of c_f_p_a_s as we may need to modify it locally. */
8067 args_to_push = current_function_pretend_args_size;
8069 /* Compute which register we will have to save onto the stack. */
8070 live_regs_mask = arm_compute_save_reg_mask ();
8072 ip_rtx = gen_rtx_REG (SImode, IP_REGNUM);
8074 if (frame_pointer_needed)
8076 if (IS_INTERRUPT (func_type))
8078 /* Interrupt functions must not corrupt any registers.
8079 Creating a frame pointer however, corrupts the IP
8080 register, so we must push it first. */
8081 insn = emit_multi_reg_push (1 << IP_REGNUM);
8082 RTX_FRAME_RELATED_P (insn) = 1;
8084 else if (IS_NESTED (func_type))
8086 /* The Static chain register is the same as the IP register
8087 used as a scratch register during stack frame creation.
8088 To get around this need to find somewhere to store IP
8089 whilst the frame is being created. We try the following
8092 1. The last argument register.
8093 2. A slot on the stack above the frame. (This only
8094 works if the function is not a varargs function).
8095 3. Register r3, after pushing the argument registers
8098 Note - we only need to tell the dwarf2 backend about the SP
8099 adjustment in the second variant; the static chain register
8100 doesn't need to be unwound, as it doesn't contain a value
8101 inherited from the caller. */
8103 if (regs_ever_live[3] == 0)
8105 insn = gen_rtx_REG (SImode, 3);
8106 insn = gen_rtx_SET (SImode, insn, ip_rtx);
8107 insn = emit_insn (insn);
8109 else if (args_to_push == 0)
8112 insn = gen_rtx_PRE_DEC (SImode, stack_pointer_rtx);
8113 insn = gen_rtx_MEM (SImode, insn);
8114 insn = gen_rtx_SET (VOIDmode, insn, ip_rtx);
8115 insn = emit_insn (insn);
8119 /* Just tell the dwarf backend that we adjusted SP. */
8120 dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8121 gen_rtx_PLUS (SImode, stack_pointer_rtx,
8122 GEN_INT (-fp_offset)));
8123 RTX_FRAME_RELATED_P (insn) = 1;
8124 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
8125 dwarf, REG_NOTES (insn));
8129 /* Store the args on the stack. */
8130 if (current_function_anonymous_args)
8131 insn = emit_multi_reg_push
8132 ((0xf0 >> (args_to_push / 4)) & 0xf);
8135 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
8136 GEN_INT (- args_to_push)));
8138 RTX_FRAME_RELATED_P (insn) = 1;
8140 saved_pretend_args = 1;
8141 fp_offset = args_to_push;
8144 /* Now reuse r3 to preserve IP. */
8145 insn = gen_rtx_REG (SImode, 3);
8146 insn = gen_rtx_SET (SImode, insn, ip_rtx);
8147 (void) emit_insn (insn);
8153 insn = gen_rtx_PLUS (SImode, stack_pointer_rtx, GEN_INT (fp_offset));
8154 insn = gen_rtx_SET (SImode, ip_rtx, insn);
8157 insn = gen_movsi (ip_rtx, stack_pointer_rtx);
8159 insn = emit_insn (insn);
8160 RTX_FRAME_RELATED_P (insn) = 1;
8165 /* Push the argument registers, or reserve space for them. */
8166 if (current_function_anonymous_args)
8167 insn = emit_multi_reg_push
8168 ((0xf0 >> (args_to_push / 4)) & 0xf);
8171 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
8172 GEN_INT (- args_to_push)));
8173 RTX_FRAME_RELATED_P (insn) = 1;
8178 insn = emit_multi_reg_push (live_regs_mask);
8179 RTX_FRAME_RELATED_P (insn) = 1;
8182 if (! IS_VOLATILE (func_type))
8184 /* Save any floating point call-saved registers used by this function. */
8185 if (arm_fpu_arch == FP_SOFT2)
8187 for (reg = LAST_ARM_FP_REGNUM; reg >= FIRST_ARM_FP_REGNUM; reg --)
8188 if (regs_ever_live[reg] && !call_used_regs[reg])
8190 insn = gen_rtx_PRE_DEC (XFmode, stack_pointer_rtx);
8191 insn = gen_rtx_MEM (XFmode, insn);
8192 insn = emit_insn (gen_rtx_SET (VOIDmode, insn,
8193 gen_rtx_REG (XFmode, reg)));
8194 RTX_FRAME_RELATED_P (insn) = 1;
8199 int start_reg = LAST_ARM_FP_REGNUM;
8201 for (reg = LAST_ARM_FP_REGNUM; reg >= FIRST_ARM_FP_REGNUM; reg --)
8203 if (regs_ever_live[reg] && !call_used_regs[reg])
8205 if (start_reg - reg == 3)
8207 insn = emit_sfm (reg, 4);
8208 RTX_FRAME_RELATED_P (insn) = 1;
8209 start_reg = reg - 1;
8214 if (start_reg != reg)
8216 insn = emit_sfm (reg + 1, start_reg - reg);
8217 RTX_FRAME_RELATED_P (insn) = 1;
8219 start_reg = reg - 1;
8223 if (start_reg != reg)
8225 insn = emit_sfm (reg + 1, start_reg - reg);
8226 RTX_FRAME_RELATED_P (insn) = 1;
8231 if (frame_pointer_needed)
8233 /* Create the new frame pointer. */
8234 insn = GEN_INT (-(4 + args_to_push + fp_offset));
8235 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, ip_rtx, insn));
8236 RTX_FRAME_RELATED_P (insn) = 1;
8238 if (IS_NESTED (func_type))
8240 /* Recover the static chain register. */
8241 if (regs_ever_live [3] == 0
8242 || saved_pretend_args)
8244 insn = gen_rtx_REG (SImode, 3);
8245 insn = gen_rtx_SET (SImode, ip_rtx, insn);
8246 (void) emit_insn (insn);
8248 else /* if (current_function_pretend_args_size == 0) */
8250 insn = gen_rtx_PLUS (SImode, hard_frame_pointer_rtx, GEN_INT (4));
8251 insn = gen_rtx_MEM (SImode, insn);
8252 insn = gen_rtx_SET (SImode, ip_rtx, insn);
8253 (void) emit_insn (insn);
8258 amount = GEN_INT (-(get_frame_size ()
8259 + current_function_outgoing_args_size));
8261 if (amount != const0_rtx)
8263 /* This add can produce multiple insns for a large constant, so we
8264 need to get tricky. */
8265 rtx last = get_last_insn ();
8266 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
8270 last = last ? NEXT_INSN (last) : get_insns ();
8271 RTX_FRAME_RELATED_P (last) = 1;
8273 while (last != insn);
8275 /* If the frame pointer is needed, emit a special barrier that
8276 will prevent the scheduler from moving stores to the frame
8277 before the stack adjustment. */
8278 if (frame_pointer_needed)
8280 rtx unspec = gen_rtx_UNSPEC (SImode,
8281 gen_rtvec (2, stack_pointer_rtx,
8282 hard_frame_pointer_rtx),
8285 insn = emit_insn (gen_rtx_CLOBBER (VOIDmode,
8286 gen_rtx_MEM (BLKmode, unspec)));
8290 /* If we are profiling, make sure no instructions are scheduled before
8291 the call to mcount. Similarly if the user has requested no
8292 scheduling in the prolog. */
8293 if (profile_flag || TARGET_NO_SCHED_PRO)
8294 emit_insn (gen_blockage ());
8296 /* If the link register is being kept alive, with the return address in it,
8297 then make sure that it does not get reused by the ce2 pass. */
8298 if ((live_regs_mask & (1 << LR_REGNUM)) == 0)
8300 emit_insn (gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, LR_REGNUM)));
8301 cfun->machine->lr_save_eliminated = 1;
8305 /* If CODE is 'd', then the X is a condition operand and the instruction
8306 should only be executed if the condition is true.
8307 if CODE is 'D', then the X is a condition operand and the instruction
8308 should only be executed if the condition is false: however, if the mode
8309 of the comparison is CCFPEmode, then always execute the instruction -- we
8310 do this because in these circumstances !GE does not necessarily imply LT;
8311 in these cases the instruction pattern will take care to make sure that
8312 an instruction containing %d will follow, thereby undoing the effects of
8313 doing this instruction unconditionally.
8314 If CODE is 'N' then X is a floating point operand that must be negated
8316 If CODE is 'B' then output a bitwise inverted value of X (a const int).
8317 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
8320 arm_print_operand (stream, x, code)
8328 fputs (ASM_COMMENT_START, stream);
8332 fputs (user_label_prefix, stream);
8336 fputs (REGISTER_PREFIX, stream);
8340 if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4)
8342 if (TARGET_THUMB || current_insn_predicate != NULL)
8345 fputs (arm_condition_codes[arm_current_cc], stream);
8347 else if (current_insn_predicate)
8349 enum arm_cond_code code;
8354 code = get_arm_condition_code (current_insn_predicate);
8355 fputs (arm_condition_codes[code], stream);
8362 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
8363 r = REAL_VALUE_NEGATE (r);
8364 fprintf (stream, "%s", fp_const_from_val (&r));
8369 if (GET_CODE (x) == CONST_INT)
8372 val = ARM_SIGN_EXTEND (~INTVAL (x));
8373 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val);
8378 output_addr_const (stream, x);
8383 fprintf (stream, "%s", arithmetic_instr (x, 1));
8387 fprintf (stream, "%s", arithmetic_instr (x, 0));
8393 const char * shift = shift_op (x, &val);
8397 fprintf (stream, ", %s ", shift_op (x, &val));
8399 arm_print_operand (stream, XEXP (x, 1), 0);
8402 fputc ('#', stream);
8403 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val);
8409 /* An explanation of the 'Q', 'R' and 'H' register operands:
8411 In a pair of registers containing a DI or DF value the 'Q'
8412 operand returns the register number of the register containing
8413 the least signficant part of the value. The 'R' operand returns
8414 the register number of the register containing the most
8415 significant part of the value.
8417 The 'H' operand returns the higher of the two register numbers.
8418 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
8419 same as the 'Q' operand, since the most signficant part of the
8420 value is held in the lower number register. The reverse is true
8421 on systems where WORDS_BIG_ENDIAN is false.
8423 The purpose of these operands is to distinguish between cases
8424 where the endian-ness of the values is important (for example
8425 when they are added together), and cases where the endian-ness
8426 is irrelevant, but the order of register operations is important.
8427 For example when loading a value from memory into a register
8428 pair, the endian-ness does not matter. Provided that the value
8429 from the lower memory address is put into the lower numbered
8430 register, and the value from the higher address is put into the
8431 higher numbered register, the load will work regardless of whether
8432 the value being loaded is big-wordian or little-wordian. The
8433 order of the two register loads can matter however, if the address
8434 of the memory location is actually held in one of the registers
8435 being overwritten by the load. */
8437 if (REGNO (x) > LAST_ARM_REGNUM)
8439 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0));
8443 if (REGNO (x) > LAST_ARM_REGNUM)
8445 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1));
8449 if (REGNO (x) > LAST_ARM_REGNUM)
8451 asm_fprintf (stream, "%r", REGNO (x) + 1);
8455 asm_fprintf (stream, "%r",
8456 GET_CODE (XEXP (x, 0)) == REG
8457 ? REGNO (XEXP (x, 0)) : REGNO (XEXP (XEXP (x, 0), 0)));
8461 asm_fprintf (stream, "{%r-%r}",
8463 REGNO (x) + NUM_REGS (GET_MODE (x)) - 1);
8471 fputs (arm_condition_codes[get_arm_condition_code (x)],
8474 fputs (thumb_condition_code (x, 0), stream);
8482 fputs (arm_condition_codes[ARM_INVERSE_CONDITION_CODE
8483 (get_arm_condition_code (x))],
8486 fputs (thumb_condition_code (x, 1), stream);
8493 if (GET_CODE (x) == REG)
8494 asm_fprintf (stream, "%r", REGNO (x));
8495 else if (GET_CODE (x) == MEM)
8497 output_memory_reference_mode = GET_MODE (x);
8498 output_address (XEXP (x, 0));
8500 else if (GET_CODE (x) == CONST_DOUBLE)
8501 fprintf (stream, "#%s", fp_immediate_constant (x));
8502 else if (GET_CODE (x) == NEG)
8503 abort (); /* This should never happen now. */
8506 fputc ('#', stream);
8507 output_addr_const (stream, x);
8512 /* A finite state machine takes care of noticing whether or not instructions
8513 can be conditionally executed, and thus decrease execution time and code
8514 size by deleting branch instructions. The fsm is controlled by
8515 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
8517 /* The state of the fsm controlling condition codes are:
8518 0: normal, do nothing special
8519 1: make ASM_OUTPUT_OPCODE not output this instruction
8520 2: make ASM_OUTPUT_OPCODE not output this instruction
8521 3: make instructions conditional
8522 4: make instructions conditional
8524 State transitions (state->state by whom under condition):
8525 0 -> 1 final_prescan_insn if the `target' is a label
8526 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
8527 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
8528 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
8529 3 -> 0 ASM_OUTPUT_INTERNAL_LABEL if the `target' label is reached
8530 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
8531 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
8532 (the target insn is arm_target_insn).
8534 If the jump clobbers the conditions then we use states 2 and 4.
8536 A similar thing can be done with conditional return insns.
8538 XXX In case the `target' is an unconditional branch, this conditionalising
8539 of the instructions always reduces code size, but not always execution
8540 time. But then, I want to reduce the code size to somewhere near what
8541 /bin/cc produces. */
8543 /* Returns the index of the ARM condition code string in
8544 `arm_condition_codes'. COMPARISON should be an rtx like
8545 `(eq (...) (...))'. */
8547 static enum arm_cond_code
8548 get_arm_condition_code (comparison)
8551 enum machine_mode mode = GET_MODE (XEXP (comparison, 0));
8553 register enum rtx_code comp_code = GET_CODE (comparison);
8555 if (GET_MODE_CLASS (mode) != MODE_CC)
8556 mode = SELECT_CC_MODE (comp_code, XEXP (comparison, 0),
8557 XEXP (comparison, 1));
8561 case CC_DNEmode: code = ARM_NE; goto dominance;
8562 case CC_DEQmode: code = ARM_EQ; goto dominance;
8563 case CC_DGEmode: code = ARM_GE; goto dominance;
8564 case CC_DGTmode: code = ARM_GT; goto dominance;
8565 case CC_DLEmode: code = ARM_LE; goto dominance;
8566 case CC_DLTmode: code = ARM_LT; goto dominance;
8567 case CC_DGEUmode: code = ARM_CS; goto dominance;
8568 case CC_DGTUmode: code = ARM_HI; goto dominance;
8569 case CC_DLEUmode: code = ARM_LS; goto dominance;
8570 case CC_DLTUmode: code = ARM_CC;
8573 if (comp_code != EQ && comp_code != NE)
8576 if (comp_code == EQ)
8577 return ARM_INVERSE_CONDITION_CODE (code);
8583 case NE: return ARM_NE;
8584 case EQ: return ARM_EQ;
8585 case GE: return ARM_PL;
8586 case LT: return ARM_MI;
8593 case NE: return ARM_NE;
8594 case EQ: return ARM_EQ;
8600 /* These encodings assume that AC=1 in the FPA system control
8601 byte. This allows us to handle all cases except UNEQ and
8605 case GE: return ARM_GE;
8606 case GT: return ARM_GT;
8607 case LE: return ARM_LS;
8608 case LT: return ARM_MI;
8609 case NE: return ARM_NE;
8610 case EQ: return ARM_EQ;
8611 case ORDERED: return ARM_VC;
8612 case UNORDERED: return ARM_VS;
8613 case UNLT: return ARM_LT;
8614 case UNLE: return ARM_LE;
8615 case UNGT: return ARM_HI;
8616 case UNGE: return ARM_PL;
8617 /* UNEQ and LTGT do not have a representation. */
8618 case UNEQ: /* Fall through. */
8619 case LTGT: /* Fall through. */
8626 case NE: return ARM_NE;
8627 case EQ: return ARM_EQ;
8628 case GE: return ARM_LE;
8629 case GT: return ARM_LT;
8630 case LE: return ARM_GE;
8631 case LT: return ARM_GT;
8632 case GEU: return ARM_LS;
8633 case GTU: return ARM_CC;
8634 case LEU: return ARM_CS;
8635 case LTU: return ARM_HI;
8642 case LTU: return ARM_CS;
8643 case GEU: return ARM_CC;
8650 case NE: return ARM_NE;
8651 case EQ: return ARM_EQ;
8652 case GE: return ARM_GE;
8653 case GT: return ARM_GT;
8654 case LE: return ARM_LE;
8655 case LT: return ARM_LT;
8656 case GEU: return ARM_CS;
8657 case GTU: return ARM_HI;
8658 case LEU: return ARM_LS;
8659 case LTU: return ARM_CC;
8671 arm_final_prescan_insn (insn)
8674 /* BODY will hold the body of INSN. */
8675 register rtx body = PATTERN (insn);
8677 /* This will be 1 if trying to repeat the trick, and things need to be
8678 reversed if it appears to fail. */
8681 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
8682 taken are clobbered, even if the rtl suggests otherwise. It also
8683 means that we have to grub around within the jump expression to find
8684 out what the conditions are when the jump isn't taken. */
8685 int jump_clobbers = 0;
8687 /* If we start with a return insn, we only succeed if we find another one. */
8688 int seeking_return = 0;
8690 /* START_INSN will hold the insn from where we start looking. This is the
8691 first insn after the following code_label if REVERSE is true. */
8692 rtx start_insn = insn;
8694 /* If in state 4, check if the target branch is reached, in order to
8695 change back to state 0. */
8696 if (arm_ccfsm_state == 4)
8698 if (insn == arm_target_insn)
8700 arm_target_insn = NULL;
8701 arm_ccfsm_state = 0;
8706 /* If in state 3, it is possible to repeat the trick, if this insn is an
8707 unconditional branch to a label, and immediately following this branch
8708 is the previous target label which is only used once, and the label this
8709 branch jumps to is not too far off. */
8710 if (arm_ccfsm_state == 3)
8712 if (simplejump_p (insn))
8714 start_insn = next_nonnote_insn (start_insn);
8715 if (GET_CODE (start_insn) == BARRIER)
8717 /* XXX Isn't this always a barrier? */
8718 start_insn = next_nonnote_insn (start_insn);
8720 if (GET_CODE (start_insn) == CODE_LABEL
8721 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
8722 && LABEL_NUSES (start_insn) == 1)
8727 else if (GET_CODE (body) == RETURN)
8729 start_insn = next_nonnote_insn (start_insn);
8730 if (GET_CODE (start_insn) == BARRIER)
8731 start_insn = next_nonnote_insn (start_insn);
8732 if (GET_CODE (start_insn) == CODE_LABEL
8733 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
8734 && LABEL_NUSES (start_insn) == 1)
8746 if (arm_ccfsm_state != 0 && !reverse)
8748 if (GET_CODE (insn) != JUMP_INSN)
8751 /* This jump might be paralleled with a clobber of the condition codes
8752 the jump should always come first */
8753 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
8754 body = XVECEXP (body, 0, 0);
8757 /* If this is a conditional return then we don't want to know */
8758 if (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
8759 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE
8760 && (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN
8761 || GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN))
8766 || (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
8767 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE))
8770 int fail = FALSE, succeed = FALSE;
8771 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
8772 int then_not_else = TRUE;
8773 rtx this_insn = start_insn, label = 0;
8775 /* If the jump cannot be done with one instruction, we cannot
8776 conditionally execute the instruction in the inverse case. */
8777 if (get_attr_conds (insn) == CONDS_JUMP_CLOB)
8783 /* Register the insn jumped to. */
8786 if (!seeking_return)
8787 label = XEXP (SET_SRC (body), 0);
8789 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == LABEL_REF)
8790 label = XEXP (XEXP (SET_SRC (body), 1), 0);
8791 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == LABEL_REF)
8793 label = XEXP (XEXP (SET_SRC (body), 2), 0);
8794 then_not_else = FALSE;
8796 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN)
8798 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN)
8801 then_not_else = FALSE;
8806 /* See how many insns this branch skips, and what kind of insns. If all
8807 insns are okay, and the label or unconditional branch to the same
8808 label is not too far away, succeed. */
8809 for (insns_skipped = 0;
8810 !fail && !succeed && insns_skipped++ < max_insns_skipped;)
8814 this_insn = next_nonnote_insn (this_insn);
8818 switch (GET_CODE (this_insn))
8821 /* Succeed if it is the target label, otherwise fail since
8822 control falls in from somewhere else. */
8823 if (this_insn == label)
8827 arm_ccfsm_state = 2;
8828 this_insn = next_nonnote_insn (this_insn);
8831 arm_ccfsm_state = 1;
8839 /* Succeed if the following insn is the target label.
8841 If return insns are used then the last insn in a function
8842 will be a barrier. */
8843 this_insn = next_nonnote_insn (this_insn);
8844 if (this_insn && this_insn == label)
8848 arm_ccfsm_state = 2;
8849 this_insn = next_nonnote_insn (this_insn);
8852 arm_ccfsm_state = 1;
8860 /* If using 32-bit addresses the cc is not preserved over
8864 /* Succeed if the following insn is the target label,
8865 or if the following two insns are a barrier and
8866 the target label. */
8867 this_insn = next_nonnote_insn (this_insn);
8868 if (this_insn && GET_CODE (this_insn) == BARRIER)
8869 this_insn = next_nonnote_insn (this_insn);
8871 if (this_insn && this_insn == label
8872 && insns_skipped < max_insns_skipped)
8876 arm_ccfsm_state = 2;
8877 this_insn = next_nonnote_insn (this_insn);
8880 arm_ccfsm_state = 1;
8889 /* If this is an unconditional branch to the same label, succeed.
8890 If it is to another label, do nothing. If it is conditional,
8892 /* XXX Probably, the tests for SET and the PC are unnecessary. */
8894 scanbody = PATTERN (this_insn);
8895 if (GET_CODE (scanbody) == SET
8896 && GET_CODE (SET_DEST (scanbody)) == PC)
8898 if (GET_CODE (SET_SRC (scanbody)) == LABEL_REF
8899 && XEXP (SET_SRC (scanbody), 0) == label && !reverse)
8901 arm_ccfsm_state = 2;
8904 else if (GET_CODE (SET_SRC (scanbody)) == IF_THEN_ELSE)
8907 /* Fail if a conditional return is undesirable (eg on a
8908 StrongARM), but still allow this if optimizing for size. */
8909 else if (GET_CODE (scanbody) == RETURN
8910 && !use_return_insn (TRUE)
8913 else if (GET_CODE (scanbody) == RETURN
8916 arm_ccfsm_state = 2;
8919 else if (GET_CODE (scanbody) == PARALLEL)
8921 switch (get_attr_conds (this_insn))
8931 fail = TRUE; /* Unrecognized jump (eg epilogue). */
8936 /* Instructions using or affecting the condition codes make it
8938 scanbody = PATTERN (this_insn);
8939 if (!(GET_CODE (scanbody) == SET
8940 || GET_CODE (scanbody) == PARALLEL)
8941 || get_attr_conds (this_insn) != CONDS_NOCOND)
8951 if ((!seeking_return) && (arm_ccfsm_state == 1 || reverse))
8952 arm_target_label = CODE_LABEL_NUMBER (label);
8953 else if (seeking_return || arm_ccfsm_state == 2)
8955 while (this_insn && GET_CODE (PATTERN (this_insn)) == USE)
8957 this_insn = next_nonnote_insn (this_insn);
8958 if (this_insn && (GET_CODE (this_insn) == BARRIER
8959 || GET_CODE (this_insn) == CODE_LABEL))
8964 /* Oh, dear! we ran off the end.. give up */
8965 recog (PATTERN (insn), insn, NULL);
8966 arm_ccfsm_state = 0;
8967 arm_target_insn = NULL;
8970 arm_target_insn = this_insn;
8979 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body),
8981 if (GET_CODE (XEXP (XEXP (SET_SRC (body), 0), 0)) == AND)
8982 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
8983 if (GET_CODE (XEXP (SET_SRC (body), 0)) == NE)
8984 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
8988 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
8991 arm_current_cc = get_arm_condition_code (XEXP (SET_SRC (body),
8995 if (reverse || then_not_else)
8996 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
8999 /* Restore recog_data (getting the attributes of other insns can
9000 destroy this array, but final.c assumes that it remains intact
9001 across this call; since the insn has been recognized already we
9002 call recog direct). */
9003 recog (PATTERN (insn), insn, NULL);
9008 arm_regno_class (regno)
9013 if (regno == STACK_POINTER_REGNUM)
9015 if (regno == CC_REGNUM)
9022 if ( regno <= LAST_ARM_REGNUM
9023 || regno == FRAME_POINTER_REGNUM
9024 || regno == ARG_POINTER_REGNUM)
9025 return GENERAL_REGS;
9027 if (regno == CC_REGNUM)
9033 /* Handle a special case when computing the offset
9034 of an argument from the frame pointer. */
9036 arm_debugger_arg_offset (value, addr)
9042 /* We are only interested if dbxout_parms() failed to compute the offset. */
9046 /* We can only cope with the case where the address is held in a register. */
9047 if (GET_CODE (addr) != REG)
9050 /* If we are using the frame pointer to point at the argument, then
9051 an offset of 0 is correct. */
9052 if (REGNO (addr) == (unsigned) HARD_FRAME_POINTER_REGNUM)
9055 /* If we are using the stack pointer to point at the
9056 argument, then an offset of 0 is correct. */
9057 if ((TARGET_THUMB || !frame_pointer_needed)
9058 && REGNO (addr) == SP_REGNUM)
9061 /* Oh dear. The argument is pointed to by a register rather
9062 than being held in a register, or being stored at a known
9063 offset from the frame pointer. Since GDB only understands
9064 those two kinds of argument we must translate the address
9065 held in the register into an offset from the frame pointer.
9066 We do this by searching through the insns for the function
9067 looking to see where this register gets its value. If the
9068 register is initialised from the frame pointer plus an offset
9069 then we are in luck and we can continue, otherwise we give up.
9071 This code is exercised by producing debugging information
9072 for a function with arguments like this:
9074 double func (double a, double b, int c, double d) {return d;}
9076 Without this code the stab for parameter 'd' will be set to
9077 an offset of 0 from the frame pointer, rather than 8. */
9079 /* The if() statement says:
9081 If the insn is a normal instruction
9082 and if the insn is setting the value in a register
9083 and if the register being set is the register holding the address of the argument
9084 and if the address is computing by an addition
9085 that involves adding to a register
9086 which is the frame pointer
9091 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
9093 if ( GET_CODE (insn) == INSN
9094 && GET_CODE (PATTERN (insn)) == SET
9095 && REGNO (XEXP (PATTERN (insn), 0)) == REGNO (addr)
9096 && GET_CODE (XEXP (PATTERN (insn), 1)) == PLUS
9097 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 0)) == REG
9098 && REGNO (XEXP (XEXP (PATTERN (insn), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
9099 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 1)) == CONST_INT
9102 value = INTVAL (XEXP (XEXP (PATTERN (insn), 1), 1));
9111 warning ("unable to compute real location of stacked parameter");
9112 value = 8; /* XXX magic hack */
9118 #define def_builtin(NAME, TYPE, CODE) \
9119 builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, NULL)
9122 arm_init_builtins ()
9124 tree endlink = void_list_node;
9125 tree int_endlink = tree_cons (NULL_TREE, integer_type_node, endlink);
9126 tree pchar_type_node = build_pointer_type (char_type_node);
9128 tree int_ftype_int, void_ftype_pchar;
9130 /* void func (void *) */
9132 = build_function_type (void_type_node,
9133 tree_cons (NULL_TREE, pchar_type_node, endlink));
9135 /* int func (int) */
9137 = build_function_type (integer_type_node, int_endlink);
9139 /* Initialize arm V5 builtins. */
9141 def_builtin ("__builtin_clz", int_ftype_int, ARM_BUILTIN_CLZ);
9144 /* Expand an expression EXP that calls a built-in function,
9145 with result going to TARGET if that's convenient
9146 (and in mode MODE if that's convenient).
9147 SUBTARGET may be used as the target for computing one of EXP's operands.
9148 IGNORE is nonzero if the value is to be ignored. */
9151 arm_expand_builtin (exp, target, subtarget, mode, ignore)
9154 rtx subtarget ATTRIBUTE_UNUSED;
9155 enum machine_mode mode ATTRIBUTE_UNUSED;
9156 int ignore ATTRIBUTE_UNUSED;
9158 enum insn_code icode;
9159 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
9160 tree arglist = TREE_OPERAND (exp, 1);
9163 enum machine_mode tmode, mode0;
9164 int fcode = DECL_FUNCTION_CODE (fndecl);
9171 case ARM_BUILTIN_CLZ:
9172 icode = CODE_FOR_clz;
9173 arg0 = TREE_VALUE (arglist);
9174 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
9175 tmode = insn_data[icode].operand[0].mode;
9176 mode0 = insn_data[icode].operand[1].mode;
9178 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
9179 op0 = copy_to_mode_reg (mode0, op0);
9181 || GET_MODE (target) != tmode
9182 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
9183 target = gen_reg_rtx (tmode);
9184 pat = GEN_FCN (icode) (target, op0);
9191 /* @@@ Should really do something sensible here. */
9195 /* Recursively search through all of the blocks in a function
9196 checking to see if any of the variables created in that
9197 function match the RTX called 'orig'. If they do then
9198 replace them with the RTX called 'new'. */
9201 replace_symbols_in_block (block, orig, new)
9206 for (; block; block = BLOCK_CHAIN (block))
9210 if (!TREE_USED (block))
9213 for (sym = BLOCK_VARS (block); sym; sym = TREE_CHAIN (sym))
9215 if ( (DECL_NAME (sym) == 0 && TREE_CODE (sym) != TYPE_DECL)
9216 || DECL_IGNORED_P (sym)
9217 || TREE_CODE (sym) != VAR_DECL
9218 || DECL_EXTERNAL (sym)
9219 || !rtx_equal_p (DECL_RTL (sym), orig)
9223 SET_DECL_RTL (sym, new);
9226 replace_symbols_in_block (BLOCK_SUBBLOCKS (block), orig, new);
9230 /* Return the number (counting from 0) of the least significant set
9236 number_of_first_bit_set (mask)
9242 (mask & (1 << bit)) == 0;
9249 /* Generate code to return from a thumb function.
9250 If 'reg_containing_return_addr' is -1, then the return address is
9251 actually on the stack, at the stack pointer. */
9253 thumb_exit (f, reg_containing_return_addr, eh_ofs)
9255 int reg_containing_return_addr;
9258 unsigned regs_available_for_popping;
9259 unsigned regs_to_pop;
9265 int restore_a4 = FALSE;
9267 /* Compute the registers we need to pop. */
9271 /* There is an assumption here, that if eh_ofs is not NULL, the
9272 normal return address will have been pushed. */
9273 if (reg_containing_return_addr == -1 || eh_ofs)
9275 /* When we are generating a return for __builtin_eh_return,
9276 reg_containing_return_addr must specify the return regno. */
9277 if (eh_ofs && reg_containing_return_addr == -1)
9280 regs_to_pop |= 1 << LR_REGNUM;
9284 if (TARGET_BACKTRACE)
9286 /* Restore the (ARM) frame pointer and stack pointer. */
9287 regs_to_pop |= (1 << ARM_HARD_FRAME_POINTER_REGNUM) | (1 << SP_REGNUM);
9291 /* If there is nothing to pop then just emit the BX instruction and
9293 if (pops_needed == 0)
9296 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs));
9298 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
9301 /* Otherwise if we are not supporting interworking and we have not created
9302 a backtrace structure and the function was not entered in ARM mode then
9303 just pop the return address straight into the PC. */
9304 else if (!TARGET_INTERWORK
9305 && !TARGET_BACKTRACE
9306 && !is_called_in_ARM_mode (current_function_decl))
9310 asm_fprintf (f, "\tadd\t%r, #4\n", SP_REGNUM);
9311 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs));
9312 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
9315 asm_fprintf (f, "\tpop\t{%r}\n", PC_REGNUM);
9320 /* Find out how many of the (return) argument registers we can corrupt. */
9321 regs_available_for_popping = 0;
9323 /* If returning via __builtin_eh_return, the bottom three registers
9324 all contain information needed for the return. */
9330 /* If we can deduce the registers used from the function's
9331 return value. This is more reliable that examining
9332 regs_ever_live[] because that will be set if the register is
9333 ever used in the function, not just if the register is used
9334 to hold a return value. */
9336 if (current_function_return_rtx != 0)
9337 mode = GET_MODE (current_function_return_rtx);
9340 mode = DECL_MODE (DECL_RESULT (current_function_decl));
9342 size = GET_MODE_SIZE (mode);
9346 /* In a void function we can use any argument register.
9347 In a function that returns a structure on the stack
9348 we can use the second and third argument registers. */
9349 if (mode == VOIDmode)
9350 regs_available_for_popping =
9351 (1 << ARG_REGISTER (1))
9352 | (1 << ARG_REGISTER (2))
9353 | (1 << ARG_REGISTER (3));
9355 regs_available_for_popping =
9356 (1 << ARG_REGISTER (2))
9357 | (1 << ARG_REGISTER (3));
9360 regs_available_for_popping =
9361 (1 << ARG_REGISTER (2))
9362 | (1 << ARG_REGISTER (3));
9364 regs_available_for_popping =
9365 (1 << ARG_REGISTER (3));
9368 /* Match registers to be popped with registers into which we pop them. */
9369 for (available = regs_available_for_popping,
9370 required = regs_to_pop;
9371 required != 0 && available != 0;
9372 available &= ~(available & - available),
9373 required &= ~(required & - required))
9376 /* If we have any popping registers left over, remove them. */
9378 regs_available_for_popping &= ~available;
9380 /* Otherwise if we need another popping register we can use
9381 the fourth argument register. */
9382 else if (pops_needed)
9384 /* If we have not found any free argument registers and
9385 reg a4 contains the return address, we must move it. */
9386 if (regs_available_for_popping == 0
9387 && reg_containing_return_addr == LAST_ARG_REGNUM)
9389 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
9390 reg_containing_return_addr = LR_REGNUM;
9394 /* Register a4 is being used to hold part of the return value,
9395 but we have dire need of a free, low register. */
9398 asm_fprintf (f, "\tmov\t%r, %r\n",IP_REGNUM, LAST_ARG_REGNUM);
9401 if (reg_containing_return_addr != LAST_ARG_REGNUM)
9403 /* The fourth argument register is available. */
9404 regs_available_for_popping |= 1 << LAST_ARG_REGNUM;
9410 /* Pop as many registers as we can. */
9411 thumb_pushpop (f, regs_available_for_popping, FALSE);
9413 /* Process the registers we popped. */
9414 if (reg_containing_return_addr == -1)
9416 /* The return address was popped into the lowest numbered register. */
9417 regs_to_pop &= ~(1 << LR_REGNUM);
9419 reg_containing_return_addr =
9420 number_of_first_bit_set (regs_available_for_popping);
9422 /* Remove this register for the mask of available registers, so that
9423 the return address will not be corrupted by futher pops. */
9424 regs_available_for_popping &= ~(1 << reg_containing_return_addr);
9427 /* If we popped other registers then handle them here. */
9428 if (regs_available_for_popping)
9432 /* Work out which register currently contains the frame pointer. */
9433 frame_pointer = number_of_first_bit_set (regs_available_for_popping);
9435 /* Move it into the correct place. */
9436 asm_fprintf (f, "\tmov\t%r, %r\n",
9437 ARM_HARD_FRAME_POINTER_REGNUM, frame_pointer);
9439 /* (Temporarily) remove it from the mask of popped registers. */
9440 regs_available_for_popping &= ~(1 << frame_pointer);
9441 regs_to_pop &= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM);
9443 if (regs_available_for_popping)
9447 /* We popped the stack pointer as well,
9448 find the register that contains it. */
9449 stack_pointer = number_of_first_bit_set (regs_available_for_popping);
9451 /* Move it into the stack register. */
9452 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, stack_pointer);
9454 /* At this point we have popped all necessary registers, so
9455 do not worry about restoring regs_available_for_popping
9456 to its correct value:
9458 assert (pops_needed == 0)
9459 assert (regs_available_for_popping == (1 << frame_pointer))
9460 assert (regs_to_pop == (1 << STACK_POINTER)) */
9464 /* Since we have just move the popped value into the frame
9465 pointer, the popping register is available for reuse, and
9466 we know that we still have the stack pointer left to pop. */
9467 regs_available_for_popping |= (1 << frame_pointer);
9471 /* If we still have registers left on the stack, but we no longer have
9472 any registers into which we can pop them, then we must move the return
9473 address into the link register and make available the register that
9475 if (regs_available_for_popping == 0 && pops_needed > 0)
9477 regs_available_for_popping |= 1 << reg_containing_return_addr;
9479 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM,
9480 reg_containing_return_addr);
9482 reg_containing_return_addr = LR_REGNUM;
9485 /* If we have registers left on the stack then pop some more.
9486 We know that at most we will want to pop FP and SP. */
9487 if (pops_needed > 0)
9492 thumb_pushpop (f, regs_available_for_popping, FALSE);
9494 /* We have popped either FP or SP.
9495 Move whichever one it is into the correct register. */
9496 popped_into = number_of_first_bit_set (regs_available_for_popping);
9497 move_to = number_of_first_bit_set (regs_to_pop);
9499 asm_fprintf (f, "\tmov\t%r, %r\n", move_to, popped_into);
9501 regs_to_pop &= ~(1 << move_to);
9506 /* If we still have not popped everything then we must have only
9507 had one register available to us and we are now popping the SP. */
9508 if (pops_needed > 0)
9512 thumb_pushpop (f, regs_available_for_popping, FALSE);
9514 popped_into = number_of_first_bit_set (regs_available_for_popping);
9516 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, popped_into);
9518 assert (regs_to_pop == (1 << STACK_POINTER))
9519 assert (pops_needed == 1)
9523 /* If necessary restore the a4 register. */
9526 if (reg_containing_return_addr != LR_REGNUM)
9528 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
9529 reg_containing_return_addr = LR_REGNUM;
9532 asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM);
9536 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs));
9538 /* Return to caller. */
9539 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
9542 /* Emit code to push or pop registers to or from the stack. */
9544 thumb_pushpop (f, mask, push)
9550 int lo_mask = mask & 0xFF;
9552 if (lo_mask == 0 && !push && (mask & (1 << 15)))
9554 /* Special case. Do not generate a POP PC statement here, do it in
9556 thumb_exit (f, -1, NULL_RTX);
9560 fprintf (f, "\t%s\t{", push ? "push" : "pop");
9562 /* Look at the low registers first. */
9563 for (regno = 0; regno <= LAST_LO_REGNUM; regno++, lo_mask >>= 1)
9567 asm_fprintf (f, "%r", regno);
9569 if ((lo_mask & ~1) != 0)
9574 if (push && (mask & (1 << LR_REGNUM)))
9576 /* Catch pushing the LR. */
9580 asm_fprintf (f, "%r", LR_REGNUM);
9582 else if (!push && (mask & (1 << PC_REGNUM)))
9584 /* Catch popping the PC. */
9585 if (TARGET_INTERWORK || TARGET_BACKTRACE)
9587 /* The PC is never poped directly, instead
9588 it is popped into r3 and then BX is used. */
9591 thumb_exit (f, -1, NULL_RTX);
9600 asm_fprintf (f, "%r", PC_REGNUM);
9608 thumb_final_prescan_insn (insn)
9611 if (flag_print_asm_name)
9612 asm_fprintf (asm_out_file, "%@ 0x%04x\n",
9613 INSN_ADDRESSES (INSN_UID (insn)));
9617 thumb_shiftable_const (val)
9618 unsigned HOST_WIDE_INT val;
9620 unsigned HOST_WIDE_INT mask = 0xff;
9623 if (val == 0) /* XXX */
9626 for (i = 0; i < 25; i++)
9627 if ((val & (mask << i)) == val)
9633 /* Returns non-zero if the current function contains,
9634 or might contain a far jump. */
9636 thumb_far_jump_used_p (int in_prologue)
9640 /* This test is only important for leaf functions. */
9641 /* assert (!leaf_function_p ()); */
9643 /* If we have already decided that far jumps may be used,
9644 do not bother checking again, and always return true even if
9645 it turns out that they are not being used. Once we have made
9646 the decision that far jumps are present (and that hence the link
9647 register will be pushed onto the stack) we cannot go back on it. */
9648 if (cfun->machine->far_jump_used)
9651 /* If this function is not being called from the prologue/epilogue
9652 generation code then it must be being called from the
9653 INITIAL_ELIMINATION_OFFSET macro. */
9656 /* In this case we know that we are being asked about the elimination
9657 of the arg pointer register. If that register is not being used,
9658 then there are no arguments on the stack, and we do not have to
9659 worry that a far jump might force the prologue to push the link
9660 register, changing the stack offsets. In this case we can just
9661 return false, since the presence of far jumps in the function will
9662 not affect stack offsets.
9664 If the arg pointer is live (or if it was live, but has now been
9665 eliminated and so set to dead) then we do have to test to see if
9666 the function might contain a far jump. This test can lead to some
9667 false negatives, since before reload is completed, then length of
9668 branch instructions is not known, so gcc defaults to returning their
9669 longest length, which in turn sets the far jump attribute to true.
9671 A false negative will not result in bad code being generated, but it
9672 will result in a needless push and pop of the link register. We
9673 hope that this does not occur too often. */
9674 if (regs_ever_live [ARG_POINTER_REGNUM])
9675 cfun->machine->arg_pointer_live = 1;
9676 else if (!cfun->machine->arg_pointer_live)
9680 /* Check to see if the function contains a branch
9681 insn with the far jump attribute set. */
9682 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
9684 if (GET_CODE (insn) == JUMP_INSN
9685 /* Ignore tablejump patterns. */
9686 && GET_CODE (PATTERN (insn)) != ADDR_VEC
9687 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
9688 && get_attr_far_jump (insn) == FAR_JUMP_YES
9691 /* Record the fact that we have decied that
9692 the function does use far jumps. */
9693 cfun->machine->far_jump_used = 1;
9701 /* Return non-zero if FUNC must be entered in ARM mode. */
9703 is_called_in_ARM_mode (func)
9706 if (TREE_CODE (func) != FUNCTION_DECL)
9709 /* Ignore the problem about functions whoes address is taken. */
9710 if (TARGET_CALLEE_INTERWORKING && TREE_PUBLIC (func))
9714 return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func)) != NULL_TREE;
9720 /* The bits which aren't usefully expanded as rtl. */
9723 thumb_unexpanded_epilogue ()
9726 int live_regs_mask = 0;
9727 int high_regs_pushed = 0;
9728 int leaf_function = leaf_function_p ();
9730 rtx eh_ofs = cfun->machine->eh_epilogue_sp_ofs;
9732 if (return_used_this_function)
9735 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
9736 if (regs_ever_live[regno] && !call_used_regs[regno]
9737 && !(TARGET_SINGLE_PIC_BASE && (regno == arm_pic_register)))
9738 live_regs_mask |= 1 << regno;
9740 for (regno = 8; regno < 13; regno++)
9742 if (regs_ever_live[regno] && !call_used_regs[regno]
9743 && !(TARGET_SINGLE_PIC_BASE && (regno == arm_pic_register)))
9747 /* The prolog may have pushed some high registers to use as
9748 work registers. eg the testuite file:
9749 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
9750 compiles to produce:
9751 push {r4, r5, r6, r7, lr}
9755 as part of the prolog. We have to undo that pushing here. */
9757 if (high_regs_pushed)
9759 int mask = live_regs_mask;
9765 /* If we can deduce the registers used from the function's return value.
9766 This is more reliable that examining regs_ever_live[] because that
9767 will be set if the register is ever used in the function, not just if
9768 the register is used to hold a return value. */
9770 if (current_function_return_rtx != 0)
9771 mode = GET_MODE (current_function_return_rtx);
9774 mode = DECL_MODE (DECL_RESULT (current_function_decl));
9776 size = GET_MODE_SIZE (mode);
9778 /* Unless we are returning a type of size > 12 register r3 is
9784 /* Oh dear! We have no low registers into which we can pop
9787 ("no low registers available for popping high registers");
9789 for (next_hi_reg = 8; next_hi_reg < 13; next_hi_reg++)
9790 if (regs_ever_live[next_hi_reg] && !call_used_regs[next_hi_reg]
9791 && !(TARGET_SINGLE_PIC_BASE && (next_hi_reg == arm_pic_register)))
9794 while (high_regs_pushed)
9796 /* Find lo register(s) into which the high register(s) can
9798 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
9800 if (mask & (1 << regno))
9802 if (high_regs_pushed == 0)
9806 mask &= (2 << regno) - 1; /* A noop if regno == 8 */
9808 /* Pop the values into the low register(s). */
9809 thumb_pushpop (asm_out_file, mask, 0);
9811 /* Move the value(s) into the high registers. */
9812 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
9814 if (mask & (1 << regno))
9816 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", next_hi_reg,
9819 for (next_hi_reg++; next_hi_reg < 13; next_hi_reg++)
9820 if (regs_ever_live[next_hi_reg]
9821 && !call_used_regs[next_hi_reg]
9822 && !(TARGET_SINGLE_PIC_BASE
9823 && (next_hi_reg == arm_pic_register)))
9830 had_to_push_lr = (live_regs_mask || !leaf_function
9831 || thumb_far_jump_used_p (1));
9833 if (TARGET_BACKTRACE
9834 && ((live_regs_mask & 0xFF) == 0)
9835 && regs_ever_live [LAST_ARG_REGNUM] != 0)
9837 /* The stack backtrace structure creation code had to
9838 push R7 in order to get a work register, so we pop
9840 live_regs_mask |= (1 << LAST_LO_REGNUM);
9843 if (current_function_pretend_args_size == 0 || TARGET_BACKTRACE)
9846 && !is_called_in_ARM_mode (current_function_decl)
9848 live_regs_mask |= 1 << PC_REGNUM;
9850 /* Either no argument registers were pushed or a backtrace
9851 structure was created which includes an adjusted stack
9852 pointer, so just pop everything. */
9854 thumb_pushpop (asm_out_file, live_regs_mask, FALSE);
9857 thumb_exit (asm_out_file, 2, eh_ofs);
9858 /* We have either just popped the return address into the
9859 PC or it is was kept in LR for the entire function or
9860 it is still on the stack because we do not want to
9861 return by doing a pop {pc}. */
9862 else if ((live_regs_mask & (1 << PC_REGNUM)) == 0)
9863 thumb_exit (asm_out_file,
9865 && is_called_in_ARM_mode (current_function_decl)) ?
9866 -1 : LR_REGNUM, NULL_RTX);
9870 /* Pop everything but the return address. */
9871 live_regs_mask &= ~(1 << PC_REGNUM);
9874 thumb_pushpop (asm_out_file, live_regs_mask, FALSE);
9877 /* Get the return address into a temporary register. */
9878 thumb_pushpop (asm_out_file, 1 << LAST_ARG_REGNUM, 0);
9880 /* Remove the argument registers that were pushed onto the stack. */
9881 asm_fprintf (asm_out_file, "\tadd\t%r, %r, #%d\n",
9882 SP_REGNUM, SP_REGNUM,
9883 current_function_pretend_args_size);
9886 thumb_exit (asm_out_file, 2, eh_ofs);
9888 thumb_exit (asm_out_file,
9889 had_to_push_lr ? LAST_ARG_REGNUM : LR_REGNUM, NULL_RTX);
9895 /* Functions to save and restore machine-specific function data. */
9898 arm_mark_machine_status (p)
9899 struct function * p;
9901 machine_function *machine = p->machine;
9904 ggc_mark_rtx (machine->eh_epilogue_sp_ofs);
9908 arm_init_machine_status (p)
9909 struct function * p;
9912 (machine_function *) xcalloc (1, sizeof (machine_function));
9914 #if ARM_FT_UNKNOWWN != 0
9915 ((machine_function *) p->machine)->func_type = ARM_FT_UNKNOWN;
9920 arm_free_machine_status (p)
9921 struct function * p;
9930 /* Return an RTX indicating where the return address to the
9931 calling function can be found. */
9933 arm_return_addr (count, frame)
9935 rtx frame ATTRIBUTE_UNUSED;
9941 return get_hard_reg_initial_val (Pmode, LR_REGNUM);
9944 rtx lr = gen_rtx_AND (Pmode, gen_rtx_REG (Pmode, LR_REGNUM),
9945 GEN_INT (RETURN_ADDR_MASK26));
9946 return get_func_hard_reg_initial_val (cfun, lr);
9950 /* Do anything needed before RTL is emitted for each function. */
9952 arm_init_expanders ()
9954 /* Arrange to initialize and mark the machine per-function status. */
9955 init_machine_status = arm_init_machine_status;
9956 mark_machine_status = arm_mark_machine_status;
9957 free_machine_status = arm_free_machine_status;
9960 /* Generate the rest of a function's prologue. */
9962 thumb_expand_prologue ()
9964 HOST_WIDE_INT amount = (get_frame_size ()
9965 + current_function_outgoing_args_size);
9966 unsigned long func_type;
9968 func_type = arm_current_func_type ();
9970 /* Naked functions don't have prologues. */
9971 if (IS_NAKED (func_type))
9974 if (IS_INTERRUPT (func_type))
9976 error ("interrupt Service Routines cannot be coded in Thumb mode");
9980 if (frame_pointer_needed)
9981 emit_insn (gen_movsi (hard_frame_pointer_rtx, stack_pointer_rtx));
9985 amount = ROUND_UP (amount);
9988 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
9989 GEN_INT (-amount)));
9995 /* The stack decrement is too big for an immediate value in a single
9996 insn. In theory we could issue multiple subtracts, but after
9997 three of them it becomes more space efficient to place the full
9998 value in the constant pool and load into a register. (Also the
9999 ARM debugger really likes to see only one stack decrement per
10000 function). So instead we look for a scratch register into which
10001 we can load the decrement, and then we subtract this from the
10002 stack pointer. Unfortunately on the thumb the only available
10003 scratch registers are the argument registers, and we cannot use
10004 these as they may hold arguments to the function. Instead we
10005 attempt to locate a call preserved register which is used by this
10006 function. If we can find one, then we know that it will have
10007 been pushed at the start of the prologue and so we can corrupt
10009 for (regno = LAST_ARG_REGNUM + 1; regno <= LAST_LO_REGNUM; regno++)
10010 if (regs_ever_live[regno]
10011 && !call_used_regs[regno] /* Paranoia */
10012 && !(TARGET_SINGLE_PIC_BASE && (regno == arm_pic_register))
10013 && !(frame_pointer_needed
10014 && (regno == THUMB_HARD_FRAME_POINTER_REGNUM)))
10017 if (regno > LAST_LO_REGNUM) /* Very unlikely */
10019 rtx spare = gen_rtx (REG, SImode, IP_REGNUM);
10021 /* Choose an arbitary, non-argument low register. */
10022 reg = gen_rtx (REG, SImode, LAST_LO_REGNUM);
10024 /* Save it by copying it into a high, scratch register. */
10025 emit_insn (gen_movsi (spare, reg));
10027 /* Decrement the stack. */
10028 emit_insn (gen_movsi (reg, GEN_INT (-amount)));
10029 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
10032 /* Restore the low register's original value. */
10033 emit_insn (gen_movsi (reg, spare));
10035 /* Emit a USE of the restored scratch register, so that flow
10036 analysis will not consider the restore redundant. The
10037 register won't be used again in this function and isn't
10038 restored by the epilogue. */
10039 emit_insn (gen_rtx_USE (VOIDmode, reg));
10043 reg = gen_rtx (REG, SImode, regno);
10045 emit_insn (gen_movsi (reg, GEN_INT (-amount)));
10046 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
10052 if (profile_flag || TARGET_NO_SCHED_PRO)
10053 emit_insn (gen_blockage ());
10057 thumb_expand_epilogue ()
10059 HOST_WIDE_INT amount = (get_frame_size ()
10060 + current_function_outgoing_args_size);
10062 /* Naked functions don't have prologues. */
10063 if (IS_NAKED (arm_current_func_type ()))
10066 if (frame_pointer_needed)
10067 emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx));
10070 amount = ROUND_UP (amount);
10073 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
10074 GEN_INT (amount)));
10077 /* r3 is always free in the epilogue. */
10078 rtx reg = gen_rtx (REG, SImode, LAST_ARG_REGNUM);
10080 emit_insn (gen_movsi (reg, GEN_INT (amount)));
10081 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, reg));
10085 /* Emit a USE (stack_pointer_rtx), so that
10086 the stack adjustment will not be deleted. */
10087 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
10089 if (profile_flag || TARGET_NO_SCHED_PRO)
10090 emit_insn (gen_blockage ());
10094 thumb_output_function_prologue (f, size)
10096 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
10098 int live_regs_mask = 0;
10099 int high_regs_pushed = 0;
10102 if (IS_NAKED (arm_current_func_type ()))
10105 if (is_called_in_ARM_mode (current_function_decl))
10109 if (GET_CODE (DECL_RTL (current_function_decl)) != MEM)
10111 if (GET_CODE (XEXP (DECL_RTL (current_function_decl), 0)) != SYMBOL_REF)
10113 name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
10115 /* Generate code sequence to switch us into Thumb mode. */
10116 /* The .code 32 directive has already been emitted by
10117 ASM_DECLARE_FUNCTION_NAME. */
10118 asm_fprintf (f, "\torr\t%r, %r, #1\n", IP_REGNUM, PC_REGNUM);
10119 asm_fprintf (f, "\tbx\t%r\n", IP_REGNUM);
10121 /* Generate a label, so that the debugger will notice the
10122 change in instruction sets. This label is also used by
10123 the assembler to bypass the ARM code when this function
10124 is called from a Thumb encoded function elsewhere in the
10125 same file. Hence the definition of STUB_NAME here must
10126 agree with the definition in gas/config/tc-arm.c */
10128 #define STUB_NAME ".real_start_of"
10130 asm_fprintf (f, "\t.code\t16\n");
10132 if (arm_dllexport_name_p (name))
10133 name = arm_strip_name_encoding (name);
10135 asm_fprintf (f, "\t.globl %s%U%s\n", STUB_NAME, name);
10136 asm_fprintf (f, "\t.thumb_func\n");
10137 asm_fprintf (f, "%s%U%s:\n", STUB_NAME, name);
10140 if (current_function_pretend_args_size)
10142 if (current_function_anonymous_args)
10146 asm_fprintf (f, "\tpush\t{");
10148 num_pushes = NUM_INTS (current_function_pretend_args_size);
10150 for (regno = LAST_ARG_REGNUM + 1 - num_pushes;
10151 regno <= LAST_ARG_REGNUM;
10153 asm_fprintf (f, "%r%s", regno,
10154 regno == LAST_ARG_REGNUM ? "" : ", ");
10156 asm_fprintf (f, "}\n");
10159 asm_fprintf (f, "\tsub\t%r, %r, #%d\n",
10160 SP_REGNUM, SP_REGNUM,
10161 current_function_pretend_args_size);
10164 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
10165 if (regs_ever_live[regno] && !call_used_regs[regno]
10166 && !(TARGET_SINGLE_PIC_BASE && (regno == arm_pic_register)))
10167 live_regs_mask |= 1 << regno;
10169 if (live_regs_mask || !leaf_function_p () || thumb_far_jump_used_p (1))
10170 live_regs_mask |= 1 << LR_REGNUM;
10172 if (TARGET_BACKTRACE)
10175 int work_register = 0;
10178 /* We have been asked to create a stack backtrace structure.
10179 The code looks like this:
10183 0 sub SP, #16 Reserve space for 4 registers.
10184 2 push {R7} Get a work register.
10185 4 add R7, SP, #20 Get the stack pointer before the push.
10186 6 str R7, [SP, #8] Store the stack pointer (before reserving the space).
10187 8 mov R7, PC Get hold of the start of this code plus 12.
10188 10 str R7, [SP, #16] Store it.
10189 12 mov R7, FP Get hold of the current frame pointer.
10190 14 str R7, [SP, #4] Store it.
10191 16 mov R7, LR Get hold of the current return address.
10192 18 str R7, [SP, #12] Store it.
10193 20 add R7, SP, #16 Point at the start of the backtrace structure.
10194 22 mov FP, R7 Put this value into the frame pointer. */
10196 if ((live_regs_mask & 0xFF) == 0)
10198 /* See if the a4 register is free. */
10200 if (regs_ever_live [LAST_ARG_REGNUM] == 0)
10201 work_register = LAST_ARG_REGNUM;
10202 else /* We must push a register of our own */
10203 live_regs_mask |= (1 << LAST_LO_REGNUM);
10206 if (work_register == 0)
10208 /* Select a register from the list that will be pushed to
10209 use as our work register. */
10210 for (work_register = (LAST_LO_REGNUM + 1); work_register--;)
10211 if ((1 << work_register) & live_regs_mask)
10216 (f, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n",
10217 SP_REGNUM, SP_REGNUM);
10219 if (live_regs_mask)
10220 thumb_pushpop (f, live_regs_mask, 1);
10222 for (offset = 0, wr = 1 << 15; wr != 0; wr >>= 1)
10223 if (wr & live_regs_mask)
10226 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
10227 offset + 16 + current_function_pretend_args_size);
10229 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
10232 /* Make sure that the instruction fetching the PC is in the right place
10233 to calculate "start of backtrace creation code + 12". */
10234 if (live_regs_mask)
10236 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
10237 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
10239 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
10240 ARM_HARD_FRAME_POINTER_REGNUM);
10241 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
10246 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
10247 ARM_HARD_FRAME_POINTER_REGNUM);
10248 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
10250 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
10251 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
10255 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, LR_REGNUM);
10256 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
10258 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
10260 asm_fprintf (f, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n",
10261 ARM_HARD_FRAME_POINTER_REGNUM, work_register);
10263 else if (live_regs_mask)
10264 thumb_pushpop (f, live_regs_mask, 1);
10266 for (regno = 8; regno < 13; regno++)
10268 if (regs_ever_live[regno] && !call_used_regs[regno]
10269 && !(TARGET_SINGLE_PIC_BASE && (regno == arm_pic_register)))
10270 high_regs_pushed++;
10273 if (high_regs_pushed)
10275 int pushable_regs = 0;
10276 int mask = live_regs_mask & 0xff;
10279 for (next_hi_reg = 12; next_hi_reg > LAST_LO_REGNUM; next_hi_reg--)
10281 if (regs_ever_live[next_hi_reg] && !call_used_regs[next_hi_reg]
10282 && !(TARGET_SINGLE_PIC_BASE
10283 && (next_hi_reg == arm_pic_register)))
10287 pushable_regs = mask;
10289 if (pushable_regs == 0)
10291 /* Desperation time -- this probably will never happen. */
10292 if (regs_ever_live[LAST_ARG_REGNUM]
10293 || !call_used_regs[LAST_ARG_REGNUM])
10294 asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, LAST_ARG_REGNUM);
10295 mask = 1 << LAST_ARG_REGNUM;
10298 while (high_regs_pushed > 0)
10300 for (regno = LAST_LO_REGNUM; regno >= 0; regno--)
10302 if (mask & (1 << regno))
10304 asm_fprintf (f, "\tmov\t%r, %r\n", regno, next_hi_reg);
10306 high_regs_pushed--;
10308 if (high_regs_pushed)
10309 for (next_hi_reg--; next_hi_reg > LAST_LO_REGNUM;
10312 if (regs_ever_live[next_hi_reg]
10313 && !call_used_regs[next_hi_reg]
10314 && !(TARGET_SINGLE_PIC_BASE
10315 && (next_hi_reg == arm_pic_register)))
10320 mask &= ~((1 << regno) - 1);
10326 thumb_pushpop (f, mask, 1);
10329 if (pushable_regs == 0
10330 && (regs_ever_live[LAST_ARG_REGNUM]
10331 || !call_used_regs[LAST_ARG_REGNUM]))
10332 asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM);
10336 /* Handle the case of a double word load into a low register from
10337 a computed memory address. The computed address may involve a
10338 register which is overwritten by the load. */
10341 thumb_load_double_from_address (operands)
10350 if (GET_CODE (operands[0]) != REG)
10353 if (GET_CODE (operands[1]) != MEM)
10356 /* Get the memory address. */
10357 addr = XEXP (operands[1], 0);
10359 /* Work out how the memory address is computed. */
10360 switch (GET_CODE (addr))
10363 operands[2] = gen_rtx (MEM, SImode,
10364 plus_constant (XEXP (operands[1], 0), 4));
10366 if (REGNO (operands[0]) == REGNO (addr))
10368 output_asm_insn ("ldr\t%H0, %2", operands);
10369 output_asm_insn ("ldr\t%0, %1", operands);
10373 output_asm_insn ("ldr\t%0, %1", operands);
10374 output_asm_insn ("ldr\t%H0, %2", operands);
10379 /* Compute <address> + 4 for the high order load. */
10380 operands[2] = gen_rtx (MEM, SImode,
10381 plus_constant (XEXP (operands[1], 0), 4));
10383 output_asm_insn ("ldr\t%0, %1", operands);
10384 output_asm_insn ("ldr\t%H0, %2", operands);
10388 arg1 = XEXP (addr, 0);
10389 arg2 = XEXP (addr, 1);
10391 if (CONSTANT_P (arg1))
10392 base = arg2, offset = arg1;
10394 base = arg1, offset = arg2;
10396 if (GET_CODE (base) != REG)
10399 /* Catch the case of <address> = <reg> + <reg> */
10400 if (GET_CODE (offset) == REG)
10402 int reg_offset = REGNO (offset);
10403 int reg_base = REGNO (base);
10404 int reg_dest = REGNO (operands[0]);
10406 /* Add the base and offset registers together into the
10407 higher destination register. */
10408 asm_fprintf (asm_out_file, "\tadd\t%r, %r, %r",
10409 reg_dest + 1, reg_base, reg_offset);
10411 /* Load the lower destination register from the address in
10412 the higher destination register. */
10413 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #0]",
10414 reg_dest, reg_dest + 1);
10416 /* Load the higher destination register from its own address
10418 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #4]",
10419 reg_dest + 1, reg_dest + 1);
10423 /* Compute <address> + 4 for the high order load. */
10424 operands[2] = gen_rtx (MEM, SImode,
10425 plus_constant (XEXP (operands[1], 0), 4));
10427 /* If the computed address is held in the low order register
10428 then load the high order register first, otherwise always
10429 load the low order register first. */
10430 if (REGNO (operands[0]) == REGNO (base))
10432 output_asm_insn ("ldr\t%H0, %2", operands);
10433 output_asm_insn ("ldr\t%0, %1", operands);
10437 output_asm_insn ("ldr\t%0, %1", operands);
10438 output_asm_insn ("ldr\t%H0, %2", operands);
10444 /* With no registers to worry about we can just load the value
10446 operands[2] = gen_rtx (MEM, SImode,
10447 plus_constant (XEXP (operands[1], 0), 4));
10449 output_asm_insn ("ldr\t%H0, %2", operands);
10450 output_asm_insn ("ldr\t%0, %1", operands);
10463 thumb_output_move_mem_multiple (n, operands)
10472 if (REGNO (operands[4]) > REGNO (operands[5]))
10475 operands[4] = operands[5];
10478 output_asm_insn ("ldmia\t%1!, {%4, %5}", operands);
10479 output_asm_insn ("stmia\t%0!, {%4, %5}", operands);
10483 if (REGNO (operands[4]) > REGNO (operands[5]))
10486 operands[4] = operands[5];
10489 if (REGNO (operands[5]) > REGNO (operands[6]))
10492 operands[5] = operands[6];
10495 if (REGNO (operands[4]) > REGNO (operands[5]))
10498 operands[4] = operands[5];
10502 output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands);
10503 output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands);
10513 /* Routines for generating rtl */
10516 thumb_expand_movstrqi (operands)
10519 rtx out = copy_to_mode_reg (SImode, XEXP (operands[0], 0));
10520 rtx in = copy_to_mode_reg (SImode, XEXP (operands[1], 0));
10521 HOST_WIDE_INT len = INTVAL (operands[2]);
10522 HOST_WIDE_INT offset = 0;
10526 emit_insn (gen_movmem12b (out, in, out, in));
10532 emit_insn (gen_movmem8b (out, in, out, in));
10538 rtx reg = gen_reg_rtx (SImode);
10539 emit_insn (gen_movsi (reg, gen_rtx (MEM, SImode, in)));
10540 emit_insn (gen_movsi (gen_rtx (MEM, SImode, out), reg));
10547 rtx reg = gen_reg_rtx (HImode);
10548 emit_insn (gen_movhi (reg, gen_rtx (MEM, HImode,
10549 plus_constant (in, offset))));
10550 emit_insn (gen_movhi (gen_rtx (MEM, HImode, plus_constant (out, offset)),
10558 rtx reg = gen_reg_rtx (QImode);
10559 emit_insn (gen_movqi (reg, gen_rtx (MEM, QImode,
10560 plus_constant (in, offset))));
10561 emit_insn (gen_movqi (gen_rtx (MEM, QImode, plus_constant (out, offset)),
10567 thumb_cmp_operand (op, mode)
10569 enum machine_mode mode;
10571 return ((GET_CODE (op) == CONST_INT
10572 && (unsigned HOST_WIDE_INT) (INTVAL (op)) < 256)
10573 || register_operand (op, mode));
10576 static const char *
10577 thumb_condition_code (x, invert)
10581 static const char *const conds[] =
10583 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
10584 "hi", "ls", "ge", "lt", "gt", "le"
10588 switch (GET_CODE (x))
10590 case EQ: val = 0; break;
10591 case NE: val = 1; break;
10592 case GEU: val = 2; break;
10593 case LTU: val = 3; break;
10594 case GTU: val = 8; break;
10595 case LEU: val = 9; break;
10596 case GE: val = 10; break;
10597 case LT: val = 11; break;
10598 case GT: val = 12; break;
10599 case LE: val = 13; break;
10604 return conds[val ^ invert];
10607 /* Handle storing a half-word to memory during reload. */
10609 thumb_reload_out_hi (operands)
10612 emit_insn (gen_thumb_movhi_clobber (operands[0], operands[1], operands[2]));
10615 /* Handle storing a half-word to memory during reload. */
10617 thumb_reload_in_hi (operands)
10618 rtx * operands ATTRIBUTE_UNUSED;
10623 /* Return the length of a function name prefix
10624 that starts with the character 'c'. */
10626 arm_get_strip_length (char c)
10630 ARM_NAME_ENCODING_LENGTHS
10635 /* Return a pointer to a function's name with any
10636 and all prefix encodings stripped from it. */
10638 arm_strip_name_encoding (const char * name)
10642 while ((skip = arm_get_strip_length (* name)))
10648 #ifdef AOF_ASSEMBLER
10649 /* Special functions only needed when producing AOF syntax assembler. */
10651 rtx aof_pic_label = NULL_RTX;
10654 struct pic_chain * next;
10655 const char * symname;
10658 static struct pic_chain * aof_pic_chain = NULL;
10664 struct pic_chain ** chainp;
10667 if (aof_pic_label == NULL_RTX)
10669 /* We mark this here and not in arm_add_gc_roots() to avoid
10670 polluting even more code with ifdefs, and because it never
10671 contains anything useful until we assign to it here. */
10672 ggc_add_rtx_root (&aof_pic_label, 1);
10673 aof_pic_label = gen_rtx_SYMBOL_REF (Pmode, "x$adcons");
10676 for (offset = 0, chainp = &aof_pic_chain; *chainp;
10677 offset += 4, chainp = &(*chainp)->next)
10678 if ((*chainp)->symname == XSTR (x, 0))
10679 return plus_constant (aof_pic_label, offset);
10681 *chainp = (struct pic_chain *) xmalloc (sizeof (struct pic_chain));
10682 (*chainp)->next = NULL;
10683 (*chainp)->symname = XSTR (x, 0);
10684 return plus_constant (aof_pic_label, offset);
10688 aof_dump_pic_table (f)
10691 struct pic_chain * chain;
10693 if (aof_pic_chain == NULL)
10696 asm_fprintf (f, "\tAREA |%r$$adcons|, BASED %r\n",
10697 PIC_OFFSET_TABLE_REGNUM,
10698 PIC_OFFSET_TABLE_REGNUM);
10699 fputs ("|x$adcons|\n", f);
10701 for (chain = aof_pic_chain; chain; chain = chain->next)
10703 fputs ("\tDCD\t", f);
10704 assemble_name (f, chain->symname);
10709 int arm_text_section_count = 1;
10712 aof_text_section ()
10714 static char buf[100];
10715 sprintf (buf, "\tAREA |C$$code%d|, CODE, READONLY",
10716 arm_text_section_count++);
10718 strcat (buf, ", PIC, REENTRANT");
10722 static int arm_data_section_count = 1;
10725 aof_data_section ()
10727 static char buf[100];
10728 sprintf (buf, "\tAREA |C$$data%d|, DATA", arm_data_section_count++);
10732 /* The AOF assembler is religiously strict about declarations of
10733 imported and exported symbols, so that it is impossible to declare
10734 a function as imported near the beginning of the file, and then to
10735 export it later on. It is, however, possible to delay the decision
10736 until all the functions in the file have been compiled. To get
10737 around this, we maintain a list of the imports and exports, and
10738 delete from it any that are subsequently defined. At the end of
10739 compilation we spit the remainder of the list out before the END
10744 struct import * next;
10748 static struct import * imports_list = NULL;
10751 aof_add_import (name)
10754 struct import * new;
10756 for (new = imports_list; new; new = new->next)
10757 if (new->name == name)
10760 new = (struct import *) xmalloc (sizeof (struct import));
10761 new->next = imports_list;
10762 imports_list = new;
10767 aof_delete_import (name)
10770 struct import ** old;
10772 for (old = &imports_list; *old; old = & (*old)->next)
10774 if ((*old)->name == name)
10776 *old = (*old)->next;
10782 int arm_main_function = 0;
10785 aof_dump_imports (f)
10788 /* The AOF assembler needs this to cause the startup code to be extracted
10789 from the library. Brining in __main causes the whole thing to work
10791 if (arm_main_function)
10794 fputs ("\tIMPORT __main\n", f);
10795 fputs ("\tDCD __main\n", f);
10798 /* Now dump the remaining imports. */
10799 while (imports_list)
10801 fprintf (f, "\tIMPORT\t");
10802 assemble_name (f, imports_list->name);
10804 imports_list = imports_list->next;
10807 #endif /* AOF_ASSEMBLER */
10809 #ifdef OBJECT_FORMAT_ELF
10810 /* Switch to an arbitrary section NAME with attributes as specified
10811 by FLAGS. ALIGN specifies any known alignment requirements for
10812 the section; 0 if the default should be used.
10814 Differs from the default elf version only in the prefix character
10815 used before the section type. */
10818 arm_elf_asm_named_section (name, flags)
10820 unsigned int flags;
10822 char flagchars[8], *f = flagchars;
10825 if (!(flags & SECTION_DEBUG))
10827 if (flags & SECTION_WRITE)
10829 if (flags & SECTION_CODE)
10831 if (flags & SECTION_SMALL)
10833 if (flags & SECTION_MERGE)
10835 if (flags & SECTION_STRINGS)
10839 if (flags & SECTION_BSS)
10844 if (flags & SECTION_ENTSIZE)
10845 fprintf (asm_out_file, "\t.section\t%s,\"%s\",%%%s,%d\n",
10846 name, flagchars, type, flags & SECTION_ENTSIZE);
10848 fprintf (asm_out_file, "\t.section\t%s,\"%s\",%%%s\n",
10849 name, flagchars, type);