1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com).
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it
11 under the terms of the GNU General Public License as published
12 by the Free Software Foundation; either version 2, or (at your
13 option) any later version.
15 GCC is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
27 #include "coretypes.h"
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
38 #include "insn-attr.h"
49 #include "integrate.h"
52 #include "target-def.h"
55 /* Forward definitions of types. */
56 typedef struct minipool_node Mnode;
57 typedef struct minipool_fixup Mfix;
59 const struct attribute_spec arm_attribute_table[];
61 /* Forward function declarations. */
62 static arm_stack_offsets *arm_get_frame_offsets (void);
63 static void arm_add_gc_roots (void);
64 static int arm_gen_constant (enum rtx_code, enum machine_mode, rtx,
65 HOST_WIDE_INT, rtx, rtx, int, int);
66 static unsigned bit_count (unsigned long);
67 static int arm_address_register_rtx_p (rtx, int);
68 static int arm_legitimate_index_p (enum machine_mode, rtx, RTX_CODE, int);
69 static int thumb_base_register_rtx_p (rtx, enum machine_mode, int);
70 inline static int thumb_index_register_rtx_p (rtx, int);
71 static int thumb_far_jump_used_p (void);
72 static int const_ok_for_op (HOST_WIDE_INT, enum rtx_code);
73 static rtx emit_multi_reg_push (int);
74 static rtx emit_sfm (int, int);
76 static bool arm_assemble_integer (rtx, unsigned int, int);
78 static const char *fp_const_from_val (REAL_VALUE_TYPE *);
79 static arm_cc get_arm_condition_code (rtx);
80 static HOST_WIDE_INT int_log2 (HOST_WIDE_INT);
81 static rtx is_jump_table (rtx);
82 static const char *output_multi_immediate (rtx *, const char *, const char *,
84 static void print_multi_reg (FILE *, const char *, int, int);
85 static const char *shift_op (rtx, HOST_WIDE_INT *);
86 static struct machine_function *arm_init_machine_status (void);
87 static int number_of_first_bit_set (int);
88 static void replace_symbols_in_block (tree, rtx, rtx);
89 static void thumb_exit (FILE *, int, rtx);
90 static void thumb_pushpop (FILE *, int, int, int *, int);
91 static rtx is_jump_table (rtx);
92 static HOST_WIDE_INT get_jump_table_size (rtx);
93 static Mnode *move_minipool_fix_forward_ref (Mnode *, Mnode *, HOST_WIDE_INT);
94 static Mnode *add_minipool_forward_ref (Mfix *);
95 static Mnode *move_minipool_fix_backward_ref (Mnode *, Mnode *, HOST_WIDE_INT);
96 static Mnode *add_minipool_backward_ref (Mfix *);
97 static void assign_minipool_offsets (Mfix *);
98 static void arm_print_value (FILE *, rtx);
99 static void dump_minipool (rtx);
100 static int arm_barrier_cost (rtx);
101 static Mfix *create_fix_barrier (Mfix *, HOST_WIDE_INT);
102 static void push_minipool_barrier (rtx, HOST_WIDE_INT);
103 static void push_minipool_fix (rtx, HOST_WIDE_INT, rtx *, enum machine_mode,
105 static void arm_reorg (void);
106 static bool note_invalid_constants (rtx, HOST_WIDE_INT, int);
107 static int current_file_function_operand (rtx);
108 static unsigned long arm_compute_save_reg0_reg12_mask (void);
109 static unsigned long arm_compute_save_reg_mask (void);
110 static unsigned long arm_isr_value (tree);
111 static unsigned long arm_compute_func_type (void);
112 static tree arm_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
113 static tree arm_handle_isr_attribute (tree *, tree, tree, int, bool *);
114 static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT);
115 static void arm_output_function_prologue (FILE *, HOST_WIDE_INT);
116 static void thumb_output_function_prologue (FILE *, HOST_WIDE_INT);
117 static int arm_comp_type_attributes (tree, tree);
118 static void arm_set_default_type_attributes (tree);
119 static int arm_adjust_cost (rtx, rtx, rtx, int);
120 static int arm_use_dfa_pipeline_interface (void);
121 static int count_insns_for_constant (HOST_WIDE_INT, int);
122 static int arm_get_strip_length (int);
123 static bool arm_function_ok_for_sibcall (tree, tree);
124 static void arm_internal_label (FILE *, const char *, unsigned long);
125 static void arm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
127 static int arm_rtx_costs_1 (rtx, enum rtx_code, enum rtx_code);
128 static bool arm_slowmul_rtx_costs (rtx, int, int, int *);
129 static bool arm_fastmul_rtx_costs (rtx, int, int, int *);
130 static bool arm_xscale_rtx_costs (rtx, int, int, int *);
131 static bool arm_9e_rtx_costs (rtx, int, int, int *);
132 static int arm_address_cost (rtx);
133 static bool arm_memory_load_p (rtx);
134 static bool arm_cirrus_insn_p (rtx);
135 static void cirrus_reorg (rtx);
136 static void arm_init_builtins (void);
137 static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
138 static void arm_init_iwmmxt_builtins (void);
139 static rtx safe_vector_operand (rtx, enum machine_mode);
140 static rtx arm_expand_binop_builtin (enum insn_code, tree, rtx);
141 static rtx arm_expand_unop_builtin (enum insn_code, tree, rtx, int);
142 static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
143 static void emit_constant_insn (rtx cond, rtx pattern);
145 #ifdef OBJECT_FORMAT_ELF
146 static void arm_elf_asm_named_section (const char *, unsigned int);
149 static void arm_encode_section_info (tree, rtx, int);
152 static void aof_globalize_label (FILE *, const char *);
153 static void aof_dump_imports (FILE *);
154 static void aof_dump_pic_table (FILE *);
155 static void aof_file_start (void);
156 static void aof_file_end (void);
158 static rtx arm_struct_value_rtx (tree, int);
159 static void arm_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
163 /* Initialize the GCC target structure. */
164 #ifdef TARGET_DLLIMPORT_DECL_ATTRIBUTES
165 #undef TARGET_MERGE_DECL_ATTRIBUTES
166 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
169 #undef TARGET_ATTRIBUTE_TABLE
170 #define TARGET_ATTRIBUTE_TABLE arm_attribute_table
173 #undef TARGET_ASM_BYTE_OP
174 #define TARGET_ASM_BYTE_OP "\tDCB\t"
175 #undef TARGET_ASM_ALIGNED_HI_OP
176 #define TARGET_ASM_ALIGNED_HI_OP "\tDCW\t"
177 #undef TARGET_ASM_ALIGNED_SI_OP
178 #define TARGET_ASM_ALIGNED_SI_OP "\tDCD\t"
179 #undef TARGET_ASM_GLOBALIZE_LABEL
180 #define TARGET_ASM_GLOBALIZE_LABEL aof_globalize_label
181 #undef TARGET_ASM_FILE_START
182 #define TARGET_ASM_FILE_START aof_file_start
183 #undef TARGET_ASM_FILE_END
184 #define TARGET_ASM_FILE_END aof_file_end
186 #undef TARGET_ASM_ALIGNED_SI_OP
187 #define TARGET_ASM_ALIGNED_SI_OP NULL
188 #undef TARGET_ASM_INTEGER
189 #define TARGET_ASM_INTEGER arm_assemble_integer
192 #undef TARGET_ASM_FUNCTION_PROLOGUE
193 #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue
195 #undef TARGET_ASM_FUNCTION_EPILOGUE
196 #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue
198 #undef TARGET_COMP_TYPE_ATTRIBUTES
199 #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes
201 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
202 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes
204 #undef TARGET_SCHED_ADJUST_COST
205 #define TARGET_SCHED_ADJUST_COST arm_adjust_cost
207 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
208 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE arm_use_dfa_pipeline_interface
210 #undef TARGET_ENCODE_SECTION_INFO
212 #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info
214 #define TARGET_ENCODE_SECTION_INFO arm_encode_section_info
217 #undef TARGET_STRIP_NAME_ENCODING
218 #define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding
220 #undef TARGET_ASM_INTERNAL_LABEL
221 #define TARGET_ASM_INTERNAL_LABEL arm_internal_label
223 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
224 #define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall
226 #undef TARGET_ASM_OUTPUT_MI_THUNK
227 #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk
228 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
229 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
231 /* This will be overridden in arm_override_options. */
232 #undef TARGET_RTX_COSTS
233 #define TARGET_RTX_COSTS arm_slowmul_rtx_costs
234 #undef TARGET_ADDRESS_COST
235 #define TARGET_ADDRESS_COST arm_address_cost
237 #undef TARGET_MACHINE_DEPENDENT_REORG
238 #define TARGET_MACHINE_DEPENDENT_REORG arm_reorg
240 #undef TARGET_INIT_BUILTINS
241 #define TARGET_INIT_BUILTINS arm_init_builtins
242 #undef TARGET_EXPAND_BUILTIN
243 #define TARGET_EXPAND_BUILTIN arm_expand_builtin
245 #undef TARGET_PROMOTE_FUNCTION_ARGS
246 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
247 #undef TARGET_PROMOTE_FUNCTION_RETURN
248 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
249 #undef TARGET_PROMOTE_PROTOTYPES
250 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_false
252 #undef TARGET_STRUCT_VALUE_RTX
253 #define TARGET_STRUCT_VALUE_RTX arm_struct_value_rtx
255 #undef TARGET_SETUP_INCOMING_VARARGS
256 #define TARGET_SETUP_INCOMING_VARARGS arm_setup_incoming_varargs
258 struct gcc_target targetm = TARGET_INITIALIZER;
260 /* Obstack for minipool constant handling. */
261 static struct obstack minipool_obstack;
262 static char * minipool_startobj;
264 /* The maximum number of insns skipped which
265 will be conditionalised if possible. */
266 static int max_insns_skipped = 5;
268 extern FILE * asm_out_file;
270 /* True if we are currently building a constant table. */
271 int making_const_table;
273 /* Define the information needed to generate branch insns. This is
274 stored from the compare operation. */
275 rtx arm_compare_op0, arm_compare_op1;
277 /* The processor for which instructions should be scheduled. */
278 enum processor_type arm_tune = arm_none;
280 /* Which floating point model to use. */
281 enum arm_fp_model arm_fp_model;
283 /* Which floating point hardware is available. */
284 enum fputype arm_fpu_arch;
286 /* Which floating point hardware to schedule for. */
287 enum fputype arm_fpu_tune;
289 /* Whether to use floating point hardware. */
290 enum float_abi_type arm_float_abi;
292 /* Which ABI to use. */
293 enum arm_abi_type arm_abi;
295 /* What program mode is the cpu running in? 26-bit mode or 32-bit mode. */
296 enum prog_mode_type arm_prgmode;
298 /* Set by the -mfpu=... option. */
299 const char * target_fpu_name = NULL;
301 /* Set by the -mfpe=... option. */
302 const char * target_fpe_name = NULL;
304 /* Set by the -mfloat-abi=... option. */
305 const char * target_float_abi_name = NULL;
307 /* Set by the -mabi=... option. */
308 const char * target_abi_name = NULL;
310 /* Used to parse -mstructure_size_boundary command line option. */
311 const char * structure_size_string = NULL;
312 int arm_structure_size_boundary = DEFAULT_STRUCTURE_SIZE_BOUNDARY;
314 /* Bit values used to identify processor capabilities. */
315 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
316 #define FL_ARCH3M (1 << 1) /* Extended multiply */
317 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
318 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
319 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
320 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
321 #define FL_THUMB (1 << 6) /* Thumb aware */
322 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
323 #define FL_STRONG (1 << 8) /* StrongARM */
324 #define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */
325 #define FL_XSCALE (1 << 10) /* XScale */
326 #define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */
327 #define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds
328 media instructions. */
329 #define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */
331 #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
333 /* The bits in this mask specify which
334 instructions we are allowed to generate. */
335 static unsigned long insn_flags = 0;
337 /* The bits in this mask specify which instruction scheduling options should
339 static unsigned long tune_flags = 0;
341 /* The following are used in the arm.md file as equivalents to bits
342 in the above two flag variables. */
344 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */
347 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
350 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
353 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
356 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */
359 /* Nonzero if this chip can benefit from load scheduling. */
360 int arm_ld_sched = 0;
362 /* Nonzero if this chip is a StrongARM. */
363 int arm_is_strong = 0;
365 /* Nonzero if this chip supports Intel Wireless MMX technology. */
366 int arm_arch_iwmmxt = 0;
368 /* Nonzero if this chip is an XScale. */
369 int arm_arch_xscale = 0;
371 /* Nonzero if tuning for XScale */
372 int arm_tune_xscale = 0;
374 /* Nonzero if this chip is an ARM6 or an ARM7. */
375 int arm_is_6_or_7 = 0;
377 /* Nonzero if generating Thumb instructions. */
380 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
381 must report the mode of the memory reference from PRINT_OPERAND to
382 PRINT_OPERAND_ADDRESS. */
383 enum machine_mode output_memory_reference_mode;
385 /* The register number to be used for the PIC offset register. */
386 const char * arm_pic_register_string = NULL;
387 int arm_pic_register = INVALID_REGNUM;
389 /* Set to 1 when a return insn is output, this means that the epilogue
391 int return_used_this_function;
393 /* Set to 1 after arm_reorg has started. Reset to start at the start of
394 the next function. */
395 static int after_arm_reorg = 0;
397 /* The maximum number of insns to be used when loading a constant. */
398 static int arm_constant_limit = 3;
400 /* For an explanation of these variables, see final_prescan_insn below. */
402 enum arm_cond_code arm_current_cc;
404 int arm_target_label;
406 /* The condition codes of the ARM, and the inverse function. */
407 static const char * const arm_condition_codes[] =
409 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
410 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
413 #define streq(string1, string2) (strcmp (string1, string2) == 0)
415 /* Initialization code. */
419 const char *const name;
420 enum processor_type core;
421 const unsigned long flags;
422 bool (* rtx_costs) (rtx, int, int, int *);
425 /* Not all of these give usefully different compilation alternatives,
426 but there is no simple way of generalizing them. */
427 static const struct processors all_cores[] =
430 #define ARM_CORE(NAME, FLAGS, COSTS) \
431 {#NAME, arm_none, FLAGS, arm_##COSTS##_rtx_costs},
432 #include "arm-cores.def"
434 {NULL, arm_none, 0, NULL}
437 static const struct processors all_architectures[] =
439 /* ARM Architectures */
440 /* We don't specify rtx_costs here as it will be figured out
443 { "armv2", arm2, FL_CO_PROC | FL_MODE26 , NULL},
444 { "armv2a", arm2, FL_CO_PROC | FL_MODE26 , NULL},
445 { "armv3", arm6, FL_CO_PROC | FL_MODE26 | FL_MODE32 , NULL},
446 { "armv3m", arm7m, FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_ARCH3M , NULL},
447 { "armv4", arm7tdmi, FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_ARCH3M | FL_ARCH4 , NULL},
448 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
449 implementations that support it, so we will leave it out for now. */
450 { "armv4t", arm7tdmi, FL_CO_PROC | FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_THUMB , NULL},
451 { "armv5", arm10tdmi, FL_CO_PROC | FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_THUMB | FL_ARCH5 , NULL},
452 { "armv5t", arm10tdmi, FL_CO_PROC | FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_THUMB | FL_ARCH5 , NULL},
453 { "armv5te", arm1026ejs, FL_CO_PROC | FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E , NULL},
454 { "armv6", arm1136js, FL_CO_PROC | FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E | FL_ARCH6 , NULL},
455 { "armv6j", arm1136js, FL_CO_PROC | FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E | FL_ARCH6 , NULL},
456 { "ep9312", ep9312, FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_LDSCHED | FL_CIRRUS , NULL},
457 {"iwmmxt", iwmmxt, FL_MODE32 | FL_ARCH3M | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_STRONG | FL_ARCH5 | FL_ARCH5E | FL_XSCALE | FL_IWMMXT , NULL},
458 { NULL, arm_none, 0 , NULL}
461 /* This is a magic structure. The 'string' field is magically filled in
462 with a pointer to the value specified by the user on the command line
463 assuming that the user has specified such a value. */
465 struct arm_cpu_select arm_select[] =
467 /* string name processors */
468 { NULL, "-mcpu=", all_cores },
469 { NULL, "-march=", all_architectures },
470 { NULL, "-mtune=", all_cores }
480 /* Available values for for -mfpu=. */
482 static const struct fpu_desc all_fpus[] =
484 {"fpa", FPUTYPE_FPA},
485 {"fpe2", FPUTYPE_FPA_EMU2},
486 {"fpe3", FPUTYPE_FPA_EMU2},
487 {"maverick", FPUTYPE_MAVERICK},
492 /* Floating point models used by the different hardware.
493 See fputype in arm.h. */
495 static const enum fputype fp_model_for_fpu[] =
497 /* No FP hardware. */
498 ARM_FP_MODEL_UNKNOWN, /* FPUTYPE_NONE */
499 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA */
500 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA_EMU2 */
501 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA_EMU3 */
502 ARM_FP_MODEL_MAVERICK, /* FPUTYPE_MAVERICK */
503 ARM_FP_MODEL_VFP /* FPUTYPE_VFP */
510 enum float_abi_type abi_type;
514 /* Available values for -mfloat-abi=. */
516 static const struct float_abi all_float_abis[] =
518 {"soft", ARM_FLOAT_ABI_SOFT},
519 {"softfp", ARM_FLOAT_ABI_SOFTFP},
520 {"hard", ARM_FLOAT_ABI_HARD}
527 enum arm_abi_type abi_type;
531 /* Available values for -mabi=. */
533 static const struct abi_name arm_all_abis[] =
535 {"apcs-gnu", ARM_ABI_APCS},
536 {"atpcs", ARM_ABI_ATPCS},
537 {"aapcs", ARM_ABI_AAPCS},
538 {"iwmmxt", ARM_ABI_IWMMXT}
541 /* Return the number of bits set in VALUE. */
543 bit_count (unsigned long value)
545 unsigned long count = 0;
550 value &= value - 1; /* Clear the least-significant set bit. */
556 /* Fix up any incompatible options that the user has specified.
557 This has now turned into a maze. */
559 arm_override_options (void)
563 /* Set up the flags based on the cpu/architecture selected by the user. */
564 for (i = ARRAY_SIZE (arm_select); i--;)
566 struct arm_cpu_select * ptr = arm_select + i;
568 if (ptr->string != NULL && ptr->string[0] != '\0')
570 const struct processors * sel;
572 for (sel = ptr->processors; sel->name != NULL; sel++)
573 if (streq (ptr->string, sel->name))
575 /* Determine the processor core for which we should
576 tune code-generation. */
577 if (/* -mcpu= is a sensible default. */
579 /* If -march= is used, and -mcpu= has not been used,
580 assume that we should tune for a representative
581 CPU from that architecture. */
583 /* -mtune= overrides -mcpu= and -march=. */
585 arm_tune = (enum processor_type) (sel - ptr->processors);
589 /* If we have been given an architecture and a processor
590 make sure that they are compatible. We only generate
591 a warning though, and we prefer the CPU over the
593 if (insn_flags != 0 && (insn_flags ^ sel->flags))
594 warning ("switch -mcpu=%s conflicts with -march= switch",
597 insn_flags = sel->flags;
603 if (sel->name == NULL)
604 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
608 /* If the user did not specify a processor, choose one for them. */
611 const struct processors * sel;
613 static const struct cpu_default
616 const char *const name;
620 { TARGET_CPU_arm2, "arm2" },
621 { TARGET_CPU_arm6, "arm6" },
622 { TARGET_CPU_arm610, "arm610" },
623 { TARGET_CPU_arm710, "arm710" },
624 { TARGET_CPU_arm7m, "arm7m" },
625 { TARGET_CPU_arm7500fe, "arm7500fe" },
626 { TARGET_CPU_arm7tdmi, "arm7tdmi" },
627 { TARGET_CPU_arm8, "arm8" },
628 { TARGET_CPU_arm810, "arm810" },
629 { TARGET_CPU_arm9, "arm9" },
630 { TARGET_CPU_strongarm, "strongarm" },
631 { TARGET_CPU_xscale, "xscale" },
632 { TARGET_CPU_ep9312, "ep9312" },
633 { TARGET_CPU_iwmmxt, "iwmmxt" },
634 { TARGET_CPU_arm926ejs, "arm926ejs" },
635 { TARGET_CPU_arm1026ejs, "arm1026ejs" },
636 { TARGET_CPU_arm1136js, "arm1136js" },
637 { TARGET_CPU_arm1136jfs, "arm1136jfs" },
638 { TARGET_CPU_generic, "arm" },
641 const struct cpu_default * def;
643 /* Find the default. */
644 for (def = cpu_defaults; def->name; def++)
645 if (def->cpu == TARGET_CPU_DEFAULT)
648 /* Make sure we found the default CPU. */
649 if (def->name == NULL)
652 /* Find the default CPU's flags. */
653 for (sel = all_cores; sel->name != NULL; sel++)
654 if (streq (def->name, sel->name))
657 if (sel->name == NULL)
660 insn_flags = sel->flags;
662 /* Now check to see if the user has specified some command line
663 switch that require certain abilities from the cpu. */
666 if (TARGET_INTERWORK || TARGET_THUMB)
668 sought |= (FL_THUMB | FL_MODE32);
670 /* Force apcs-32 to be used for interworking. */
671 target_flags |= ARM_FLAG_APCS_32;
673 /* There are no ARM processors that support both APCS-26 and
674 interworking. Therefore we force FL_MODE26 to be removed
675 from insn_flags here (if it was set), so that the search
676 below will always be able to find a compatible processor. */
677 insn_flags &= ~FL_MODE26;
679 else if (!TARGET_APCS_32)
682 if (sought != 0 && ((sought & insn_flags) != sought))
684 /* Try to locate a CPU type that supports all of the abilities
685 of the default CPU, plus the extra abilities requested by
687 for (sel = all_cores; sel->name != NULL; sel++)
688 if ((sel->flags & sought) == (sought | insn_flags))
691 if (sel->name == NULL)
693 unsigned current_bit_count = 0;
694 const struct processors * best_fit = NULL;
696 /* Ideally we would like to issue an error message here
697 saying that it was not possible to find a CPU compatible
698 with the default CPU, but which also supports the command
699 line options specified by the programmer, and so they
700 ought to use the -mcpu=<name> command line option to
701 override the default CPU type.
703 Unfortunately this does not work with multilibing. We
704 need to be able to support multilibs for -mapcs-26 and for
705 -mthumb-interwork and there is no CPU that can support both
706 options. Instead if we cannot find a cpu that has both the
707 characteristics of the default cpu and the given command line
708 options we scan the array again looking for a best match. */
709 for (sel = all_cores; sel->name != NULL; sel++)
710 if ((sel->flags & sought) == sought)
714 count = bit_count (sel->flags & insn_flags);
716 if (count >= current_bit_count)
719 current_bit_count = count;
723 if (best_fit == NULL)
729 insn_flags = sel->flags;
731 if (arm_tune == arm_none)
732 arm_tune = (enum processor_type) (sel - all_cores);
735 /* The processor for which we should tune should now have been
737 if (arm_tune == arm_none)
740 tune_flags = all_cores[(int)arm_tune].flags;
741 targetm.rtx_costs = all_cores[(int)arm_tune].rtx_costs;
743 /* Make sure that the processor choice does not conflict with any of the
744 other command line choices. */
745 if (TARGET_APCS_32 && !(insn_flags & FL_MODE32))
747 /* If APCS-32 was not the default then it must have been set by the
748 user, so issue a warning message. If the user has specified
749 "-mapcs-32 -mcpu=arm2" then we loose here. */
750 if ((TARGET_DEFAULT & ARM_FLAG_APCS_32) == 0)
751 warning ("target CPU does not support APCS-32" );
752 target_flags &= ~ARM_FLAG_APCS_32;
754 else if (!TARGET_APCS_32 && !(insn_flags & FL_MODE26))
756 warning ("target CPU does not support APCS-26" );
757 target_flags |= ARM_FLAG_APCS_32;
760 if (TARGET_INTERWORK && !(insn_flags & FL_THUMB))
762 warning ("target CPU does not support interworking" );
763 target_flags &= ~ARM_FLAG_INTERWORK;
766 if (TARGET_THUMB && !(insn_flags & FL_THUMB))
768 warning ("target CPU does not support THUMB instructions");
769 target_flags &= ~ARM_FLAG_THUMB;
772 if (TARGET_APCS_FRAME && TARGET_THUMB)
774 /* warning ("ignoring -mapcs-frame because -mthumb was used"); */
775 target_flags &= ~ARM_FLAG_APCS_FRAME;
778 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
779 from here where no function is being compiled currently. */
780 if ((target_flags & (THUMB_FLAG_LEAF_BACKTRACE | THUMB_FLAG_BACKTRACE))
782 warning ("enabling backtrace support is only meaningful when compiling for the Thumb");
784 if (TARGET_ARM && TARGET_CALLEE_INTERWORKING)
785 warning ("enabling callee interworking support is only meaningful when compiling for the Thumb");
787 if (TARGET_ARM && TARGET_CALLER_INTERWORKING)
788 warning ("enabling caller interworking support is only meaningful when compiling for the Thumb");
790 /* If interworking is enabled then APCS-32 must be selected as well. */
791 if (TARGET_INTERWORK)
794 warning ("interworking forces APCS-32 to be used" );
795 target_flags |= ARM_FLAG_APCS_32;
798 if (TARGET_APCS_STACK && !TARGET_APCS_FRAME)
800 warning ("-mapcs-stack-check incompatible with -mno-apcs-frame");
801 target_flags |= ARM_FLAG_APCS_FRAME;
804 if (TARGET_POKE_FUNCTION_NAME)
805 target_flags |= ARM_FLAG_APCS_FRAME;
807 if (TARGET_APCS_REENT && flag_pic)
808 error ("-fpic and -mapcs-reent are incompatible");
810 if (TARGET_APCS_REENT)
811 warning ("APCS reentrant code not supported. Ignored");
813 /* If this target is normally configured to use APCS frames, warn if they
814 are turned off and debugging is turned on. */
816 && write_symbols != NO_DEBUG
817 && !TARGET_APCS_FRAME
818 && (TARGET_DEFAULT & ARM_FLAG_APCS_FRAME))
819 warning ("-g with -mno-apcs-frame may not give sensible debugging");
821 /* If stack checking is disabled, we can use r10 as the PIC register,
822 which keeps r9 available. */
824 arm_pic_register = TARGET_APCS_STACK ? 9 : 10;
826 if (TARGET_APCS_FLOAT)
827 warning ("passing floating point arguments in fp regs not yet supported");
829 /* Initialize boolean versions of the flags, for use in the arm.md file. */
830 arm_arch3m = (insn_flags & FL_ARCH3M) != 0;
831 arm_arch4 = (insn_flags & FL_ARCH4) != 0;
832 arm_arch5 = (insn_flags & FL_ARCH5) != 0;
833 arm_arch5e = (insn_flags & FL_ARCH5E) != 0;
834 arm_arch6 = (insn_flags & FL_ARCH6) != 0;
835 arm_arch_xscale = (insn_flags & FL_XSCALE) != 0;
837 arm_ld_sched = (tune_flags & FL_LDSCHED) != 0;
838 arm_is_strong = (tune_flags & FL_STRONG) != 0;
839 thumb_code = (TARGET_ARM == 0);
840 arm_is_6_or_7 = (((tune_flags & (FL_MODE26 | FL_MODE32))
841 && !(tune_flags & FL_ARCH4))) != 0;
842 arm_tune_xscale = (tune_flags & FL_XSCALE) != 0;
843 arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0;
847 for (i = 0; i < ARRAY_SIZE (arm_all_abis); i++)
849 if (streq (arm_all_abis[i].name, target_abi_name))
851 arm_abi = arm_all_abis[i].abi_type;
855 if (i == ARRAY_SIZE (arm_all_abis))
856 error ("invalid ABI option: -mabi=%s", target_abi_name);
861 arm_abi = ARM_ABI_AAPCS;
863 arm_abi = ARM_DEFAULT_ABI;
866 if (TARGET_IWMMXT && !ARM_DOUBLEWORD_ALIGN)
867 error ("iwmmxt requires an AAPCS compatible ABI for proper operation");
869 if (TARGET_IWMMXT_ABI && !TARGET_IWMMXT)
870 error ("iwmmxt abi requires an iwmmxt capable cpu");
872 arm_fp_model = ARM_FP_MODEL_UNKNOWN;
873 if (target_fpu_name == NULL && target_fpe_name != NULL)
875 if (streq (target_fpe_name, "2"))
876 target_fpu_name = "fpe2";
877 else if (streq (target_fpe_name, "3"))
878 target_fpu_name = "fpe3";
880 error ("invalid floating point emulation option: -mfpe=%s",
883 if (target_fpu_name != NULL)
885 /* The user specified a FPU. */
886 for (i = 0; i < ARRAY_SIZE (all_fpus); i++)
888 if (streq (all_fpus[i].name, target_fpu_name))
890 arm_fpu_arch = all_fpus[i].fpu;
891 arm_fpu_tune = arm_fpu_arch;
892 arm_fp_model = fp_model_for_fpu[arm_fpu_arch];
896 if (arm_fp_model == ARM_FP_MODEL_UNKNOWN)
897 error ("invalid floating point option: -mfpu=%s", target_fpu_name);
901 #ifdef FPUTYPE_DEFAULT
902 /* Use the default is it is specified for this platform. */
903 arm_fpu_arch = FPUTYPE_DEFAULT;
904 arm_fpu_tune = FPUTYPE_DEFAULT;
906 /* Pick one based on CPU type. */
907 if ((insn_flags & FL_VFP) != 0)
908 arm_fpu_arch = FPUTYPE_VFP;
909 else if (insn_flags & FL_CIRRUS)
910 arm_fpu_arch = FPUTYPE_MAVERICK;
912 arm_fpu_arch = FPUTYPE_FPA_EMU2;
914 if (tune_flags & FL_CO_PROC && arm_fpu_arch == FPUTYPE_FPA_EMU2)
915 arm_fpu_tune = FPUTYPE_FPA;
917 arm_fpu_tune = arm_fpu_arch;
918 arm_fp_model = fp_model_for_fpu[arm_fpu_arch];
919 if (arm_fp_model == ARM_FP_MODEL_UNKNOWN)
923 if (target_float_abi_name != NULL)
925 /* The user specified a FP ABI. */
926 for (i = 0; i < ARRAY_SIZE (all_float_abis); i++)
928 if (streq (all_float_abis[i].name, target_float_abi_name))
930 arm_float_abi = all_float_abis[i].abi_type;
934 if (i == ARRAY_SIZE (all_float_abis))
935 error ("invalid floating point abi: -mfloat-abi=%s",
936 target_float_abi_name);
940 /* Use soft-float target flag. */
941 if (target_flags & ARM_FLAG_SOFT_FLOAT)
942 arm_float_abi = ARM_FLOAT_ABI_SOFT;
944 arm_float_abi = ARM_FLOAT_ABI_HARD;
947 if (arm_float_abi == ARM_FLOAT_ABI_SOFTFP)
948 sorry ("-mfloat-abi=softfp");
949 /* If soft-float is specified then don't use FPU. */
950 if (TARGET_SOFT_FLOAT)
951 arm_fpu_arch = FPUTYPE_NONE;
953 /* For arm2/3 there is no need to do any scheduling if there is only
954 a floating point emulator, or we are doing software floating-point. */
955 if ((TARGET_SOFT_FLOAT
956 || arm_fpu_tune == FPUTYPE_FPA_EMU2
957 || arm_fpu_tune == FPUTYPE_FPA_EMU3)
958 && (tune_flags & FL_MODE32) == 0)
959 flag_schedule_insns = flag_schedule_insns_after_reload = 0;
961 arm_prgmode = TARGET_APCS_32 ? PROG_MODE_PROG32 : PROG_MODE_PROG26;
963 /* Override the default structure alignment for AAPCS ABI. */
964 if (arm_abi == ARM_ABI_AAPCS)
965 arm_structure_size_boundary = 8;
967 if (structure_size_string != NULL)
969 int size = strtol (structure_size_string, NULL, 0);
971 if (size == 8 || size == 32
972 || (ARM_DOUBLEWORD_ALIGN && size == 64))
973 arm_structure_size_boundary = size;
975 warning ("structure size boundary can only be set to %s",
976 ARM_DOUBLEWORD_ALIGN ? "8, 32 or 64": "8 or 32");
979 if (arm_pic_register_string != NULL)
981 int pic_register = decode_reg_name (arm_pic_register_string);
984 warning ("-mpic-register= is useless without -fpic");
986 /* Prevent the user from choosing an obviously stupid PIC register. */
987 else if (pic_register < 0 || call_used_regs[pic_register]
988 || pic_register == HARD_FRAME_POINTER_REGNUM
989 || pic_register == STACK_POINTER_REGNUM
990 || pic_register >= PC_REGNUM)
991 error ("unable to use '%s' for PIC register", arm_pic_register_string);
993 arm_pic_register = pic_register;
996 if (TARGET_THUMB && flag_schedule_insns)
998 /* Don't warn since it's on by default in -O2. */
999 flag_schedule_insns = 0;
1004 /* There's some dispute as to whether this should be 1 or 2. However,
1005 experiments seem to show that in pathological cases a setting of
1006 1 degrades less severely than a setting of 2. This could change if
1007 other parts of the compiler change their behavior. */
1008 arm_constant_limit = 1;
1010 /* If optimizing for size, bump the number of instructions that we
1011 are prepared to conditionally execute (even on a StrongARM). */
1012 max_insns_skipped = 6;
1016 /* For processors with load scheduling, it never costs more than
1017 2 cycles to load a constant, and the load scheduler may well
1018 reduce that to 1. */
1019 if (tune_flags & FL_LDSCHED)
1020 arm_constant_limit = 1;
1022 /* On XScale the longer latency of a load makes it more difficult
1023 to achieve a good schedule, so it's faster to synthesize
1024 constants that can be done in two insns. */
1025 if (arm_tune_xscale)
1026 arm_constant_limit = 2;
1028 /* StrongARM has early execution of branches, so a sequence
1029 that is worth skipping is shorter. */
1031 max_insns_skipped = 3;
1034 /* Register global variables with the garbage collector. */
1035 arm_add_gc_roots ();
1039 arm_add_gc_roots (void)
1041 gcc_obstack_init(&minipool_obstack);
1042 minipool_startobj = (char *) obstack_alloc (&minipool_obstack, 0);
1045 /* A table of known ARM exception types.
1046 For use with the interrupt function attribute. */
1050 const char *const arg;
1051 const unsigned long return_value;
1055 static const isr_attribute_arg isr_attribute_args [] =
1057 { "IRQ", ARM_FT_ISR },
1058 { "irq", ARM_FT_ISR },
1059 { "FIQ", ARM_FT_FIQ },
1060 { "fiq", ARM_FT_FIQ },
1061 { "ABORT", ARM_FT_ISR },
1062 { "abort", ARM_FT_ISR },
1063 { "ABORT", ARM_FT_ISR },
1064 { "abort", ARM_FT_ISR },
1065 { "UNDEF", ARM_FT_EXCEPTION },
1066 { "undef", ARM_FT_EXCEPTION },
1067 { "SWI", ARM_FT_EXCEPTION },
1068 { "swi", ARM_FT_EXCEPTION },
1069 { NULL, ARM_FT_NORMAL }
1072 /* Returns the (interrupt) function type of the current
1073 function, or ARM_FT_UNKNOWN if the type cannot be determined. */
1075 static unsigned long
1076 arm_isr_value (tree argument)
1078 const isr_attribute_arg * ptr;
1081 /* No argument - default to IRQ. */
1082 if (argument == NULL_TREE)
1085 /* Get the value of the argument. */
1086 if (TREE_VALUE (argument) == NULL_TREE
1087 || TREE_CODE (TREE_VALUE (argument)) != STRING_CST)
1088 return ARM_FT_UNKNOWN;
1090 arg = TREE_STRING_POINTER (TREE_VALUE (argument));
1092 /* Check it against the list of known arguments. */
1093 for (ptr = isr_attribute_args; ptr->arg != NULL; ptr++)
1094 if (streq (arg, ptr->arg))
1095 return ptr->return_value;
1097 /* An unrecognized interrupt type. */
1098 return ARM_FT_UNKNOWN;
1101 /* Computes the type of the current function. */
1103 static unsigned long
1104 arm_compute_func_type (void)
1106 unsigned long type = ARM_FT_UNKNOWN;
1110 if (TREE_CODE (current_function_decl) != FUNCTION_DECL)
1113 /* Decide if the current function is volatile. Such functions
1114 never return, and many memory cycles can be saved by not storing
1115 register values that will never be needed again. This optimization
1116 was added to speed up context switching in a kernel application. */
1118 && current_function_nothrow
1119 && TREE_THIS_VOLATILE (current_function_decl))
1120 type |= ARM_FT_VOLATILE;
1122 if (current_function_needs_context)
1123 type |= ARM_FT_NESTED;
1125 attr = DECL_ATTRIBUTES (current_function_decl);
1127 a = lookup_attribute ("naked", attr);
1129 type |= ARM_FT_NAKED;
1131 if (cfun->machine->eh_epilogue_sp_ofs != NULL_RTX)
1132 type |= ARM_FT_EXCEPTION_HANDLER;
1135 a = lookup_attribute ("isr", attr);
1137 a = lookup_attribute ("interrupt", attr);
1140 type |= TARGET_INTERWORK ? ARM_FT_INTERWORKED : ARM_FT_NORMAL;
1142 type |= arm_isr_value (TREE_VALUE (a));
1148 /* Returns the type of the current function. */
1151 arm_current_func_type (void)
1153 if (ARM_FUNC_TYPE (cfun->machine->func_type) == ARM_FT_UNKNOWN)
1154 cfun->machine->func_type = arm_compute_func_type ();
1156 return cfun->machine->func_type;
1159 /* Return 1 if it is possible to return using a single instruction.
1160 If SIBLING is non-null, this is a test for a return before a sibling
1161 call. SIBLING is the call insn, so we can examine its register usage. */
1164 use_return_insn (int iscond, rtx sibling)
1167 unsigned int func_type;
1168 unsigned long saved_int_regs;
1169 unsigned HOST_WIDE_INT stack_adjust;
1170 arm_stack_offsets *offsets;
1172 /* Never use a return instruction before reload has run. */
1173 if (!reload_completed)
1176 func_type = arm_current_func_type ();
1178 /* Naked functions and volatile functions need special
1180 if (func_type & (ARM_FT_VOLATILE | ARM_FT_NAKED))
1183 /* So do interrupt functions that use the frame pointer. */
1184 if (IS_INTERRUPT (func_type) && frame_pointer_needed)
1187 offsets = arm_get_frame_offsets ();
1188 stack_adjust = offsets->outgoing_args - offsets->saved_regs;
1190 /* As do variadic functions. */
1191 if (current_function_pretend_args_size
1192 || cfun->machine->uses_anonymous_args
1193 /* Or if the function calls __builtin_eh_return () */
1194 || ARM_FUNC_TYPE (func_type) == ARM_FT_EXCEPTION_HANDLER
1195 /* Or if the function calls alloca */
1196 || current_function_calls_alloca
1197 /* Or if there is a stack adjustment. However, if the stack pointer
1198 is saved on the stack, we can use a pre-incrementing stack load. */
1199 || !(stack_adjust == 0 || (frame_pointer_needed && stack_adjust == 4)))
1202 saved_int_regs = arm_compute_save_reg_mask ();
1204 /* Unfortunately, the insn
1206 ldmib sp, {..., sp, ...}
1208 triggers a bug on most SA-110 based devices, such that the stack
1209 pointer won't be correctly restored if the instruction takes a
1210 page fault. We work around this problem by popping r3 along with
1211 the other registers, since that is never slower than executing
1212 another instruction.
1214 We test for !arm_arch5 here, because code for any architecture
1215 less than this could potentially be run on one of the buggy
1217 if (stack_adjust == 4 && !arm_arch5)
1219 /* Validate that r3 is a call-clobbered register (always true in
1220 the default abi) ... */
1221 if (!call_used_regs[3])
1224 /* ... that it isn't being used for a return value (always true
1225 until we implement return-in-regs), or for a tail-call
1229 if (GET_CODE (sibling) != CALL_INSN)
1232 if (find_regno_fusage (sibling, USE, 3))
1236 /* ... and that there are no call-saved registers in r0-r2
1237 (always true in the default ABI). */
1238 if (saved_int_regs & 0x7)
1242 /* Can't be done if interworking with Thumb, and any registers have been
1244 if (TARGET_INTERWORK && saved_int_regs != 0)
1247 /* On StrongARM, conditional returns are expensive if they aren't
1248 taken and multiple registers have been stacked. */
1249 if (iscond && arm_is_strong)
1251 /* Conditional return when just the LR is stored is a simple
1252 conditional-load instruction, that's not expensive. */
1253 if (saved_int_regs != 0 && saved_int_regs != (1 << LR_REGNUM))
1256 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
1260 /* If there are saved registers but the LR isn't saved, then we need
1261 two instructions for the return. */
1262 if (saved_int_regs && !(saved_int_regs & (1 << LR_REGNUM)))
1265 /* Can't be done if any of the FPA regs are pushed,
1266 since this also requires an insn. */
1267 if (TARGET_HARD_FLOAT && TARGET_FPA)
1268 for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++)
1269 if (regs_ever_live[regno] && !call_used_regs[regno])
1272 /* Likewise VFP regs. */
1273 if (TARGET_HARD_FLOAT && TARGET_VFP)
1274 for (regno = FIRST_VFP_REGNUM; regno <= LAST_VFP_REGNUM; regno++)
1275 if (regs_ever_live[regno] && !call_used_regs[regno])
1278 if (TARGET_REALLY_IWMMXT)
1279 for (regno = FIRST_IWMMXT_REGNUM; regno <= LAST_IWMMXT_REGNUM; regno++)
1280 if (regs_ever_live[regno] && ! call_used_regs [regno])
1286 /* Return TRUE if int I is a valid immediate ARM constant. */
1289 const_ok_for_arm (HOST_WIDE_INT i)
1291 unsigned HOST_WIDE_INT mask = ~(unsigned HOST_WIDE_INT)0xFF;
1293 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
1294 be all zero, or all one. */
1295 if ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0
1296 && ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff)
1297 != ((~(unsigned HOST_WIDE_INT) 0)
1298 & ~(unsigned HOST_WIDE_INT) 0xffffffff)))
1301 /* Fast return for 0 and powers of 2 */
1302 if ((i & (i - 1)) == 0)
1307 if ((i & mask & (unsigned HOST_WIDE_INT) 0xffffffff) == 0)
1310 (mask << 2) | ((mask & (unsigned HOST_WIDE_INT) 0xffffffff)
1311 >> (32 - 2)) | ~(unsigned HOST_WIDE_INT) 0xffffffff;
1313 while (mask != ~(unsigned HOST_WIDE_INT) 0xFF);
1318 /* Return true if I is a valid constant for the operation CODE. */
1320 const_ok_for_op (HOST_WIDE_INT i, enum rtx_code code)
1322 if (const_ok_for_arm (i))
1328 return const_ok_for_arm (ARM_SIGN_EXTEND (-i));
1330 case MINUS: /* Should only occur with (MINUS I reg) => rsb */
1336 return const_ok_for_arm (ARM_SIGN_EXTEND (~i));
1343 /* Emit a sequence of insns to handle a large constant.
1344 CODE is the code of the operation required, it can be any of SET, PLUS,
1345 IOR, AND, XOR, MINUS;
1346 MODE is the mode in which the operation is being performed;
1347 VAL is the integer to operate on;
1348 SOURCE is the other operand (a register, or a null-pointer for SET);
1349 SUBTARGETS means it is safe to create scratch registers if that will
1350 either produce a simpler sequence, or we will want to cse the values.
1351 Return value is the number of insns emitted. */
1354 arm_split_constant (enum rtx_code code, enum machine_mode mode, rtx insn,
1355 HOST_WIDE_INT val, rtx target, rtx source, int subtargets)
1359 if (insn && GET_CODE (PATTERN (insn)) == COND_EXEC)
1360 cond = COND_EXEC_TEST (PATTERN (insn));
1364 if (subtargets || code == SET
1365 || (GET_CODE (target) == REG && GET_CODE (source) == REG
1366 && REGNO (target) != REGNO (source)))
1368 /* After arm_reorg has been called, we can't fix up expensive
1369 constants by pushing them into memory so we must synthesize
1370 them in-line, regardless of the cost. This is only likely to
1371 be more costly on chips that have load delay slots and we are
1372 compiling without running the scheduler (so no splitting
1373 occurred before the final instruction emission).
1375 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
1377 if (!after_arm_reorg
1379 && (arm_gen_constant (code, mode, NULL_RTX, val, target, source,
1381 > arm_constant_limit + (code != SET)))
1385 /* Currently SET is the only monadic value for CODE, all
1386 the rest are diadic. */
1387 emit_insn (gen_rtx_SET (VOIDmode, target, GEN_INT (val)));
1392 rtx temp = subtargets ? gen_reg_rtx (mode) : target;
1394 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (val)));
1395 /* For MINUS, the value is subtracted from, since we never
1396 have subtraction of a constant. */
1398 emit_insn (gen_rtx_SET (VOIDmode, target,
1399 gen_rtx_MINUS (mode, temp, source)));
1401 emit_insn (gen_rtx_SET (VOIDmode, target,
1402 gen_rtx_fmt_ee (code, mode, source, temp)));
1408 return arm_gen_constant (code, mode, cond, val, target, source, subtargets,
1413 count_insns_for_constant (HOST_WIDE_INT remainder, int i)
1415 HOST_WIDE_INT temp1;
1423 if (remainder & (3 << (i - 2)))
1428 temp1 = remainder & ((0x0ff << end)
1429 | ((i < end) ? (0xff >> (32 - end)) : 0));
1430 remainder &= ~temp1;
1435 } while (remainder);
1439 /* Emit an instruction with the indicated PATTERN. If COND is
1440 non-NULL, conditionalize the execution of the instruction on COND
1444 emit_constant_insn (rtx cond, rtx pattern)
1447 pattern = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (cond), pattern);
1448 emit_insn (pattern);
1451 /* As above, but extra parameter GENERATE which, if clear, suppresses
1455 arm_gen_constant (enum rtx_code code, enum machine_mode mode, rtx cond,
1456 HOST_WIDE_INT val, rtx target, rtx source, int subtargets,
1461 int can_negate_initial = 0;
1464 int num_bits_set = 0;
1465 int set_sign_bit_copies = 0;
1466 int clear_sign_bit_copies = 0;
1467 int clear_zero_bit_copies = 0;
1468 int set_zero_bit_copies = 0;
1470 unsigned HOST_WIDE_INT temp1, temp2;
1471 unsigned HOST_WIDE_INT remainder = val & 0xffffffff;
1473 /* Find out which operations are safe for a given CODE. Also do a quick
1474 check for degenerate cases; these can occur when DImode operations
1486 can_negate_initial = 1;
1490 if (remainder == 0xffffffff)
1493 emit_constant_insn (cond,
1494 gen_rtx_SET (VOIDmode, target,
1495 GEN_INT (ARM_SIGN_EXTEND (val))));
1500 if (reload_completed && rtx_equal_p (target, source))
1503 emit_constant_insn (cond,
1504 gen_rtx_SET (VOIDmode, target, source));
1513 emit_constant_insn (cond,
1514 gen_rtx_SET (VOIDmode, target, const0_rtx));
1517 if (remainder == 0xffffffff)
1519 if (reload_completed && rtx_equal_p (target, source))
1522 emit_constant_insn (cond,
1523 gen_rtx_SET (VOIDmode, target, source));
1532 if (reload_completed && rtx_equal_p (target, source))
1535 emit_constant_insn (cond,
1536 gen_rtx_SET (VOIDmode, target, source));
1539 if (remainder == 0xffffffff)
1542 emit_constant_insn (cond,
1543 gen_rtx_SET (VOIDmode, target,
1544 gen_rtx_NOT (mode, source)));
1548 /* We don't know how to handle this yet below. */
1552 /* We treat MINUS as (val - source), since (source - val) is always
1553 passed as (source + (-val)). */
1557 emit_constant_insn (cond,
1558 gen_rtx_SET (VOIDmode, target,
1559 gen_rtx_NEG (mode, source)));
1562 if (const_ok_for_arm (val))
1565 emit_constant_insn (cond,
1566 gen_rtx_SET (VOIDmode, target,
1567 gen_rtx_MINUS (mode, GEN_INT (val),
1579 /* If we can do it in one insn get out quickly. */
1580 if (const_ok_for_arm (val)
1581 || (can_negate_initial && const_ok_for_arm (-val))
1582 || (can_invert && const_ok_for_arm (~val)))
1585 emit_constant_insn (cond,
1586 gen_rtx_SET (VOIDmode, target,
1588 ? gen_rtx_fmt_ee (code, mode, source,
1594 /* Calculate a few attributes that may be useful for specific
1596 for (i = 31; i >= 0; i--)
1598 if ((remainder & (1 << i)) == 0)
1599 clear_sign_bit_copies++;
1604 for (i = 31; i >= 0; i--)
1606 if ((remainder & (1 << i)) != 0)
1607 set_sign_bit_copies++;
1612 for (i = 0; i <= 31; i++)
1614 if ((remainder & (1 << i)) == 0)
1615 clear_zero_bit_copies++;
1620 for (i = 0; i <= 31; i++)
1622 if ((remainder & (1 << i)) != 0)
1623 set_zero_bit_copies++;
1631 /* See if we can do this by sign_extending a constant that is known
1632 to be negative. This is a good, way of doing it, since the shift
1633 may well merge into a subsequent insn. */
1634 if (set_sign_bit_copies > 1)
1636 if (const_ok_for_arm
1637 (temp1 = ARM_SIGN_EXTEND (remainder
1638 << (set_sign_bit_copies - 1))))
1642 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1643 emit_constant_insn (cond,
1644 gen_rtx_SET (VOIDmode, new_src,
1646 emit_constant_insn (cond,
1647 gen_ashrsi3 (target, new_src,
1648 GEN_INT (set_sign_bit_copies - 1)));
1652 /* For an inverted constant, we will need to set the low bits,
1653 these will be shifted out of harm's way. */
1654 temp1 |= (1 << (set_sign_bit_copies - 1)) - 1;
1655 if (const_ok_for_arm (~temp1))
1659 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1660 emit_constant_insn (cond,
1661 gen_rtx_SET (VOIDmode, new_src,
1663 emit_constant_insn (cond,
1664 gen_ashrsi3 (target, new_src,
1665 GEN_INT (set_sign_bit_copies - 1)));
1671 /* See if we can generate this by setting the bottom (or the top)
1672 16 bits, and then shifting these into the other half of the
1673 word. We only look for the simplest cases, to do more would cost
1674 too much. Be careful, however, not to generate this when the
1675 alternative would take fewer insns. */
1676 if (val & 0xffff0000)
1678 temp1 = remainder & 0xffff0000;
1679 temp2 = remainder & 0x0000ffff;
1681 /* Overlaps outside this range are best done using other methods. */
1682 for (i = 9; i < 24; i++)
1684 if ((((temp2 | (temp2 << i)) & 0xffffffff) == remainder)
1685 && !const_ok_for_arm (temp2))
1687 rtx new_src = (subtargets
1688 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
1690 insns = arm_gen_constant (code, mode, cond, temp2, new_src,
1691 source, subtargets, generate);
1699 gen_rtx_ASHIFT (mode, source,
1706 /* Don't duplicate cases already considered. */
1707 for (i = 17; i < 24; i++)
1709 if (((temp1 | (temp1 >> i)) == remainder)
1710 && !const_ok_for_arm (temp1))
1712 rtx new_src = (subtargets
1713 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
1715 insns = arm_gen_constant (code, mode, cond, temp1, new_src,
1716 source, subtargets, generate);
1721 gen_rtx_SET (VOIDmode, target,
1724 gen_rtx_LSHIFTRT (mode, source,
1735 /* If we have IOR or XOR, and the constant can be loaded in a
1736 single instruction, and we can find a temporary to put it in,
1737 then this can be done in two instructions instead of 3-4. */
1739 /* TARGET can't be NULL if SUBTARGETS is 0 */
1740 || (reload_completed && !reg_mentioned_p (target, source)))
1742 if (const_ok_for_arm (ARM_SIGN_EXTEND (~val)))
1746 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1748 emit_constant_insn (cond,
1749 gen_rtx_SET (VOIDmode, sub,
1751 emit_constant_insn (cond,
1752 gen_rtx_SET (VOIDmode, target,
1753 gen_rtx_fmt_ee (code, mode,
1763 if (set_sign_bit_copies > 8
1764 && (val & (-1 << (32 - set_sign_bit_copies))) == val)
1768 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1769 rtx shift = GEN_INT (set_sign_bit_copies);
1773 gen_rtx_SET (VOIDmode, sub,
1775 gen_rtx_ASHIFT (mode,
1780 gen_rtx_SET (VOIDmode, target,
1782 gen_rtx_LSHIFTRT (mode, sub,
1788 if (set_zero_bit_copies > 8
1789 && (remainder & ((1 << set_zero_bit_copies) - 1)) == remainder)
1793 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1794 rtx shift = GEN_INT (set_zero_bit_copies);
1798 gen_rtx_SET (VOIDmode, sub,
1800 gen_rtx_LSHIFTRT (mode,
1805 gen_rtx_SET (VOIDmode, target,
1807 gen_rtx_ASHIFT (mode, sub,
1813 if (const_ok_for_arm (temp1 = ARM_SIGN_EXTEND (~val)))
1817 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1818 emit_constant_insn (cond,
1819 gen_rtx_SET (VOIDmode, sub,
1820 gen_rtx_NOT (mode, source)));
1823 sub = gen_reg_rtx (mode);
1824 emit_constant_insn (cond,
1825 gen_rtx_SET (VOIDmode, sub,
1826 gen_rtx_AND (mode, source,
1828 emit_constant_insn (cond,
1829 gen_rtx_SET (VOIDmode, target,
1830 gen_rtx_NOT (mode, sub)));
1837 /* See if two shifts will do 2 or more insn's worth of work. */
1838 if (clear_sign_bit_copies >= 16 && clear_sign_bit_copies < 24)
1840 HOST_WIDE_INT shift_mask = ((0xffffffff
1841 << (32 - clear_sign_bit_copies))
1844 if ((remainder | shift_mask) != 0xffffffff)
1848 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1849 insns = arm_gen_constant (AND, mode, cond,
1850 remainder | shift_mask,
1851 new_src, source, subtargets, 1);
1856 rtx targ = subtargets ? NULL_RTX : target;
1857 insns = arm_gen_constant (AND, mode, cond,
1858 remainder | shift_mask,
1859 targ, source, subtargets, 0);
1865 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1866 rtx shift = GEN_INT (clear_sign_bit_copies);
1868 emit_insn (gen_ashlsi3 (new_src, source, shift));
1869 emit_insn (gen_lshrsi3 (target, new_src, shift));
1875 if (clear_zero_bit_copies >= 16 && clear_zero_bit_copies < 24)
1877 HOST_WIDE_INT shift_mask = (1 << clear_zero_bit_copies) - 1;
1879 if ((remainder | shift_mask) != 0xffffffff)
1883 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1885 insns = arm_gen_constant (AND, mode, cond,
1886 remainder | shift_mask,
1887 new_src, source, subtargets, 1);
1892 rtx targ = subtargets ? NULL_RTX : target;
1894 insns = arm_gen_constant (AND, mode, cond,
1895 remainder | shift_mask,
1896 targ, source, subtargets, 0);
1902 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1903 rtx shift = GEN_INT (clear_zero_bit_copies);
1905 emit_insn (gen_lshrsi3 (new_src, source, shift));
1906 emit_insn (gen_ashlsi3 (target, new_src, shift));
1918 for (i = 0; i < 32; i++)
1919 if (remainder & (1 << i))
1922 if (code == AND || (can_invert && num_bits_set > 16))
1923 remainder = (~remainder) & 0xffffffff;
1924 else if (code == PLUS && num_bits_set > 16)
1925 remainder = (-remainder) & 0xffffffff;
1932 /* Now try and find a way of doing the job in either two or three
1934 We start by looking for the largest block of zeros that are aligned on
1935 a 2-bit boundary, we then fill up the temps, wrapping around to the
1936 top of the word when we drop off the bottom.
1937 In the worst case this code should produce no more than four insns. */
1940 int best_consecutive_zeros = 0;
1942 for (i = 0; i < 32; i += 2)
1944 int consecutive_zeros = 0;
1946 if (!(remainder & (3 << i)))
1948 while ((i < 32) && !(remainder & (3 << i)))
1950 consecutive_zeros += 2;
1953 if (consecutive_zeros > best_consecutive_zeros)
1955 best_consecutive_zeros = consecutive_zeros;
1956 best_start = i - consecutive_zeros;
1962 /* So long as it won't require any more insns to do so, it's
1963 desirable to emit a small constant (in bits 0...9) in the last
1964 insn. This way there is more chance that it can be combined with
1965 a later addressing insn to form a pre-indexed load or store
1966 operation. Consider:
1968 *((volatile int *)0xe0000100) = 1;
1969 *((volatile int *)0xe0000110) = 2;
1971 We want this to wind up as:
1975 str rB, [rA, #0x100]
1977 str rB, [rA, #0x110]
1979 rather than having to synthesize both large constants from scratch.
1981 Therefore, we calculate how many insns would be required to emit
1982 the constant starting from `best_start', and also starting from
1983 zero (ie with bit 31 first to be output). If `best_start' doesn't
1984 yield a shorter sequence, we may as well use zero. */
1986 && ((((unsigned HOST_WIDE_INT) 1) << best_start) < remainder)
1987 && (count_insns_for_constant (remainder, 0) <=
1988 count_insns_for_constant (remainder, best_start)))
1991 /* Now start emitting the insns. */
1999 if (remainder & (3 << (i - 2)))
2004 temp1 = remainder & ((0x0ff << end)
2005 | ((i < end) ? (0xff >> (32 - end)) : 0));
2006 remainder &= ~temp1;
2010 rtx new_src, temp1_rtx;
2012 if (code == SET || code == MINUS)
2014 new_src = (subtargets ? gen_reg_rtx (mode) : target);
2015 if (can_invert && code != MINUS)
2020 if (remainder && subtargets)
2021 new_src = gen_reg_rtx (mode);
2026 else if (can_negate)
2030 temp1 = trunc_int_for_mode (temp1, mode);
2031 temp1_rtx = GEN_INT (temp1);
2035 else if (code == MINUS)
2036 temp1_rtx = gen_rtx_MINUS (mode, temp1_rtx, source);
2038 temp1_rtx = gen_rtx_fmt_ee (code, mode, source, temp1_rtx);
2040 emit_constant_insn (cond,
2041 gen_rtx_SET (VOIDmode, new_src,
2051 else if (code == MINUS)
2065 /* Canonicalize a comparison so that we are more likely to recognize it.
2066 This can be done for a few constant compares, where we can make the
2067 immediate value easier to load. */
2070 arm_canonicalize_comparison (enum rtx_code code, rtx * op1)
2072 unsigned HOST_WIDE_INT i = INTVAL (*op1);
2082 if (i != ((((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1)) - 1)
2083 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
2085 *op1 = GEN_INT (i + 1);
2086 return code == GT ? GE : LT;
2092 if (i != (((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1))
2093 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
2095 *op1 = GEN_INT (i - 1);
2096 return code == GE ? GT : LE;
2102 if (i != ~((unsigned HOST_WIDE_INT) 0)
2103 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
2105 *op1 = GEN_INT (i + 1);
2106 return code == GTU ? GEU : LTU;
2113 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
2115 *op1 = GEN_INT (i - 1);
2116 return code == GEU ? GTU : LEU;
2128 /* Define how to find the value returned by a function. */
2130 rtx arm_function_value(tree type, tree func ATTRIBUTE_UNUSED)
2132 enum machine_mode mode;
2133 int unsignedp ATTRIBUTE_UNUSED;
2134 rtx r ATTRIBUTE_UNUSED;
2137 mode = TYPE_MODE (type);
2138 /* Promote integer types. */
2139 if (INTEGRAL_TYPE_P (type))
2140 PROMOTE_FUNCTION_MODE (mode, unsignedp, type);
2141 return LIBCALL_VALUE(mode);
2145 /* Decide whether a type should be returned in memory (true)
2146 or in a register (false). This is called by the macro
2147 RETURN_IN_MEMORY. */
2149 arm_return_in_memory (tree type)
2153 if (!AGGREGATE_TYPE_P (type))
2154 /* All simple types are returned in registers. */
2157 size = int_size_in_bytes (type);
2159 if (arm_abi != ARM_ABI_APCS)
2161 /* ATPCS and later return aggregate types in memory only if they are
2162 larger than a word (or are variable size). */
2163 return (size < 0 || size > UNITS_PER_WORD);
2166 /* For the arm-wince targets we choose to be compatible with Microsoft's
2167 ARM and Thumb compilers, which always return aggregates in memory. */
2169 /* All structures/unions bigger than one word are returned in memory.
2170 Also catch the case where int_size_in_bytes returns -1. In this case
2171 the aggregate is either huge or of variable size, and in either case
2172 we will want to return it via memory and not in a register. */
2173 if (size < 0 || size > UNITS_PER_WORD)
2176 if (TREE_CODE (type) == RECORD_TYPE)
2180 /* For a struct the APCS says that we only return in a register
2181 if the type is 'integer like' and every addressable element
2182 has an offset of zero. For practical purposes this means
2183 that the structure can have at most one non bit-field element
2184 and that this element must be the first one in the structure. */
2186 /* Find the first field, ignoring non FIELD_DECL things which will
2187 have been created by C++. */
2188 for (field = TYPE_FIELDS (type);
2189 field && TREE_CODE (field) != FIELD_DECL;
2190 field = TREE_CHAIN (field))
2194 return 0; /* An empty structure. Allowed by an extension to ANSI C. */
2196 /* Check that the first field is valid for returning in a register. */
2198 /* ... Floats are not allowed */
2199 if (FLOAT_TYPE_P (TREE_TYPE (field)))
2202 /* ... Aggregates that are not themselves valid for returning in
2203 a register are not allowed. */
2204 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
2207 /* Now check the remaining fields, if any. Only bitfields are allowed,
2208 since they are not addressable. */
2209 for (field = TREE_CHAIN (field);
2211 field = TREE_CHAIN (field))
2213 if (TREE_CODE (field) != FIELD_DECL)
2216 if (!DECL_BIT_FIELD_TYPE (field))
2223 if (TREE_CODE (type) == UNION_TYPE)
2227 /* Unions can be returned in registers if every element is
2228 integral, or can be returned in an integer register. */
2229 for (field = TYPE_FIELDS (type);
2231 field = TREE_CHAIN (field))
2233 if (TREE_CODE (field) != FIELD_DECL)
2236 if (FLOAT_TYPE_P (TREE_TYPE (field)))
2239 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
2245 #endif /* not ARM_WINCE */
2247 /* Return all other types in memory. */
2251 /* Indicate whether or not words of a double are in big-endian order. */
2254 arm_float_words_big_endian (void)
2256 if (TARGET_MAVERICK)
2259 /* For FPA, float words are always big-endian. For VFP, floats words
2260 follow the memory system mode. */
2268 return (TARGET_BIG_END ? 1 : 0);
2273 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2274 for a call to a function whose data type is FNTYPE.
2275 For a library call, FNTYPE is NULL. */
2277 arm_init_cumulative_args (CUMULATIVE_ARGS *pcum, tree fntype,
2278 rtx libname ATTRIBUTE_UNUSED,
2279 tree fndecl ATTRIBUTE_UNUSED)
2281 /* On the ARM, the offset starts at 0. */
2282 pcum->nregs = ((fntype && aggregate_value_p (TREE_TYPE (fntype), fntype)) ? 1 : 0);
2283 pcum->iwmmxt_nregs = 0;
2284 pcum->can_split = true;
2286 pcum->call_cookie = CALL_NORMAL;
2288 if (TARGET_LONG_CALLS)
2289 pcum->call_cookie = CALL_LONG;
2291 /* Check for long call/short call attributes. The attributes
2292 override any command line option. */
2295 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (fntype)))
2296 pcum->call_cookie = CALL_SHORT;
2297 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (fntype)))
2298 pcum->call_cookie = CALL_LONG;
2301 /* Varargs vectors are treated the same as long long.
2302 named_count avoids having to change the way arm handles 'named' */
2303 pcum->named_count = 0;
2306 if (TARGET_REALLY_IWMMXT && fntype)
2310 for (fn_arg = TYPE_ARG_TYPES (fntype);
2312 fn_arg = TREE_CHAIN (fn_arg))
2313 pcum->named_count += 1;
2315 if (! pcum->named_count)
2316 pcum->named_count = INT_MAX;
2321 /* Return true if mode/type need doubleword alignment. */
2323 arm_needs_doubleword_align (enum machine_mode mode, tree type)
2325 return (mode == DImode
2327 || VECTOR_MODE_SUPPORTED_P (mode)
2329 && TYPE_ALIGN (type) > PARM_BOUNDARY));
2333 /* Determine where to put an argument to a function.
2334 Value is zero to push the argument on the stack,
2335 or a hard register in which to store the argument.
2337 MODE is the argument's machine mode.
2338 TYPE is the data type of the argument (as a tree).
2339 This is null for libcalls where that information may
2341 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2342 the preceding args and about the function being called.
2343 NAMED is nonzero if this argument is a named parameter
2344 (otherwise it is an extra parameter matching an ellipsis). */
2347 arm_function_arg (CUMULATIVE_ARGS *pcum, enum machine_mode mode,
2348 tree type, int named)
2352 /* Varargs vectors are treated the same as long long.
2353 named_count avoids having to change the way arm handles 'named' */
2354 if (TARGET_IWMMXT_ABI
2355 && VECTOR_MODE_SUPPORTED_P (mode)
2356 && pcum->named_count > pcum->nargs + 1)
2358 if (pcum->iwmmxt_nregs <= 9)
2359 return gen_rtx_REG (mode, pcum->iwmmxt_nregs + FIRST_IWMMXT_REGNUM);
2362 pcum->can_split = false;
2367 /* Put doubleword aligned quantities in even register pairs. */
2369 && ARM_DOUBLEWORD_ALIGN
2370 && arm_needs_doubleword_align (mode, type))
2373 if (mode == VOIDmode)
2374 /* Compute operand 2 of the call insn. */
2375 return GEN_INT (pcum->call_cookie);
2377 /* Only allow splitting an arg between regs and memory if all preceding
2378 args were allocated to regs. For args passed by reference we only count
2379 the reference pointer. */
2380 if (pcum->can_split)
2383 nregs = ARM_NUM_REGS2 (mode, type);
2385 if (!named || pcum->nregs + nregs > NUM_ARG_REGS)
2388 return gen_rtx_REG (mode, pcum->nregs);
2391 /* Variable sized types are passed by reference. This is a GCC
2392 extension to the ARM ABI. */
2395 arm_function_arg_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
2396 enum machine_mode mode ATTRIBUTE_UNUSED,
2397 tree type, int named ATTRIBUTE_UNUSED)
2399 return type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST;
2402 /* Implement va_arg. */
2405 arm_va_arg (tree valist, tree type)
2409 /* Variable sized types are passed by reference. */
2410 if (TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
2412 rtx addr = std_expand_builtin_va_arg (valist, build_pointer_type (type));
2413 return gen_rtx_MEM (ptr_mode, force_reg (Pmode, addr));
2416 align = FUNCTION_ARG_BOUNDARY (TYPE_MODE (type), type);
2417 if (align > PARM_BOUNDARY)
2422 /* Maintain 64-bit alignment of the valist pointer by
2423 constructing: valist = ((valist + (8 - 1)) & -8). */
2424 mask = build_int_2 (- (align / BITS_PER_UNIT), -1);
2425 t = build_int_2 ((align / BITS_PER_UNIT) - 1, 0);
2426 t = build (PLUS_EXPR, TREE_TYPE (valist), valist, t);
2427 t = build (BIT_AND_EXPR, TREE_TYPE (t), t, mask);
2428 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
2429 TREE_SIDE_EFFECTS (t) = 1;
2430 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
2432 /* This is to stop the combine pass optimizing
2433 away the alignment adjustment. */
2434 mark_reg_pointer (arg_pointer_rtx, PARM_BOUNDARY);
2437 return std_expand_builtin_va_arg (valist, type);
2440 /* Encode the current state of the #pragma [no_]long_calls. */
2443 OFF, /* No #pramgma [no_]long_calls is in effect. */
2444 LONG, /* #pragma long_calls is in effect. */
2445 SHORT /* #pragma no_long_calls is in effect. */
2448 static arm_pragma_enum arm_pragma_long_calls = OFF;
2451 arm_pr_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2453 arm_pragma_long_calls = LONG;
2457 arm_pr_no_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2459 arm_pragma_long_calls = SHORT;
2463 arm_pr_long_calls_off (struct cpp_reader * pfile ATTRIBUTE_UNUSED)
2465 arm_pragma_long_calls = OFF;
2468 /* Table of machine attributes. */
2469 const struct attribute_spec arm_attribute_table[] =
2471 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
2472 /* Function calls made to this symbol must be done indirectly, because
2473 it may lie outside of the 26 bit addressing range of a normal function
2475 { "long_call", 0, 0, false, true, true, NULL },
2476 /* Whereas these functions are always known to reside within the 26 bit
2477 addressing range. */
2478 { "short_call", 0, 0, false, true, true, NULL },
2479 /* Interrupt Service Routines have special prologue and epilogue requirements. */
2480 { "isr", 0, 1, false, false, false, arm_handle_isr_attribute },
2481 { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute },
2482 { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute },
2484 /* ARM/PE has three new attributes:
2486 dllexport - for exporting a function/variable that will live in a dll
2487 dllimport - for importing a function/variable from a dll
2489 Microsoft allows multiple declspecs in one __declspec, separating
2490 them with spaces. We do NOT support this. Instead, use __declspec
2493 { "dllimport", 0, 0, true, false, false, NULL },
2494 { "dllexport", 0, 0, true, false, false, NULL },
2495 { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute },
2497 { NULL, 0, 0, false, false, false, NULL }
2500 /* Handle an attribute requiring a FUNCTION_DECL;
2501 arguments as in struct attribute_spec.handler. */
2503 arm_handle_fndecl_attribute (tree *node, tree name, tree args ATTRIBUTE_UNUSED,
2504 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
2506 if (TREE_CODE (*node) != FUNCTION_DECL)
2508 warning ("`%s' attribute only applies to functions",
2509 IDENTIFIER_POINTER (name));
2510 *no_add_attrs = true;
2516 /* Handle an "interrupt" or "isr" attribute;
2517 arguments as in struct attribute_spec.handler. */
2519 arm_handle_isr_attribute (tree *node, tree name, tree args, int flags,
2524 if (TREE_CODE (*node) != FUNCTION_DECL)
2526 warning ("`%s' attribute only applies to functions",
2527 IDENTIFIER_POINTER (name));
2528 *no_add_attrs = true;
2530 /* FIXME: the argument if any is checked for type attributes;
2531 should it be checked for decl ones? */
2535 if (TREE_CODE (*node) == FUNCTION_TYPE
2536 || TREE_CODE (*node) == METHOD_TYPE)
2538 if (arm_isr_value (args) == ARM_FT_UNKNOWN)
2540 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
2541 *no_add_attrs = true;
2544 else if (TREE_CODE (*node) == POINTER_TYPE
2545 && (TREE_CODE (TREE_TYPE (*node)) == FUNCTION_TYPE
2546 || TREE_CODE (TREE_TYPE (*node)) == METHOD_TYPE)
2547 && arm_isr_value (args) != ARM_FT_UNKNOWN)
2549 *node = build_type_copy (*node);
2550 TREE_TYPE (*node) = build_type_attribute_variant
2552 tree_cons (name, args, TYPE_ATTRIBUTES (TREE_TYPE (*node))));
2553 *no_add_attrs = true;
2557 /* Possibly pass this attribute on from the type to a decl. */
2558 if (flags & ((int) ATTR_FLAG_DECL_NEXT
2559 | (int) ATTR_FLAG_FUNCTION_NEXT
2560 | (int) ATTR_FLAG_ARRAY_NEXT))
2562 *no_add_attrs = true;
2563 return tree_cons (name, args, NULL_TREE);
2567 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
2575 /* Return 0 if the attributes for two types are incompatible, 1 if they
2576 are compatible, and 2 if they are nearly compatible (which causes a
2577 warning to be generated). */
2579 arm_comp_type_attributes (tree type1, tree type2)
2583 /* Check for mismatch of non-default calling convention. */
2584 if (TREE_CODE (type1) != FUNCTION_TYPE)
2587 /* Check for mismatched call attributes. */
2588 l1 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1)) != NULL;
2589 l2 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2)) != NULL;
2590 s1 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1)) != NULL;
2591 s2 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2)) != NULL;
2593 /* Only bother to check if an attribute is defined. */
2594 if (l1 | l2 | s1 | s2)
2596 /* If one type has an attribute, the other must have the same attribute. */
2597 if ((l1 != l2) || (s1 != s2))
2600 /* Disallow mixed attributes. */
2601 if ((l1 & s2) || (l2 & s1))
2605 /* Check for mismatched ISR attribute. */
2606 l1 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type1)) != NULL;
2608 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1)) != NULL;
2609 l2 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type2)) != NULL;
2611 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2)) != NULL;
2618 /* Encode long_call or short_call attribute by prefixing
2619 symbol name in DECL with a special character FLAG. */
2621 arm_encode_call_attribute (tree decl, int flag)
2623 const char * str = XSTR (XEXP (DECL_RTL (decl), 0), 0);
2624 int len = strlen (str);
2627 /* Do not allow weak functions to be treated as short call. */
2628 if (DECL_WEAK (decl) && flag == SHORT_CALL_FLAG_CHAR)
2631 newstr = alloca (len + 2);
2633 strcpy (newstr + 1, str);
2635 newstr = (char *) ggc_alloc_string (newstr, len + 1);
2636 XSTR (XEXP (DECL_RTL (decl), 0), 0) = newstr;
2639 /* Assigns default attributes to newly defined type. This is used to
2640 set short_call/long_call attributes for function types of
2641 functions defined inside corresponding #pragma scopes. */
2643 arm_set_default_type_attributes (tree type)
2645 /* Add __attribute__ ((long_call)) to all functions, when
2646 inside #pragma long_calls or __attribute__ ((short_call)),
2647 when inside #pragma no_long_calls. */
2648 if (TREE_CODE (type) == FUNCTION_TYPE || TREE_CODE (type) == METHOD_TYPE)
2650 tree type_attr_list, attr_name;
2651 type_attr_list = TYPE_ATTRIBUTES (type);
2653 if (arm_pragma_long_calls == LONG)
2654 attr_name = get_identifier ("long_call");
2655 else if (arm_pragma_long_calls == SHORT)
2656 attr_name = get_identifier ("short_call");
2660 type_attr_list = tree_cons (attr_name, NULL_TREE, type_attr_list);
2661 TYPE_ATTRIBUTES (type) = type_attr_list;
2665 /* Return 1 if the operand is a SYMBOL_REF for a function known to be
2666 defined within the current compilation unit. If this cannot be
2667 determined, then 0 is returned. */
2669 current_file_function_operand (rtx sym_ref)
2671 /* This is a bit of a fib. A function will have a short call flag
2672 applied to its name if it has the short call attribute, or it has
2673 already been defined within the current compilation unit. */
2674 if (ENCODED_SHORT_CALL_ATTR_P (XSTR (sym_ref, 0)))
2677 /* The current function is always defined within the current compilation
2678 unit. if it s a weak definition however, then this may not be the real
2679 definition of the function, and so we have to say no. */
2680 if (sym_ref == XEXP (DECL_RTL (current_function_decl), 0)
2681 && !DECL_WEAK (current_function_decl))
2684 /* We cannot make the determination - default to returning 0. */
2688 /* Return nonzero if a 32 bit "long_call" should be generated for
2689 this call. We generate a long_call if the function:
2691 a. has an __attribute__((long call))
2692 or b. is within the scope of a #pragma long_calls
2693 or c. the -mlong-calls command line switch has been specified
2695 However we do not generate a long call if the function:
2697 d. has an __attribute__ ((short_call))
2698 or e. is inside the scope of a #pragma no_long_calls
2699 or f. has an __attribute__ ((section))
2700 or g. is defined within the current compilation unit.
2702 This function will be called by C fragments contained in the machine
2703 description file. CALL_REF and CALL_COOKIE correspond to the matched
2704 rtl operands. CALL_SYMBOL is used to distinguish between
2705 two different callers of the function. It is set to 1 in the
2706 "call_symbol" and "call_symbol_value" patterns and to 0 in the "call"
2707 and "call_value" patterns. This is because of the difference in the
2708 SYM_REFs passed by these patterns. */
2710 arm_is_longcall_p (rtx sym_ref, int call_cookie, int call_symbol)
2714 if (GET_CODE (sym_ref) != MEM)
2717 sym_ref = XEXP (sym_ref, 0);
2720 if (GET_CODE (sym_ref) != SYMBOL_REF)
2723 if (call_cookie & CALL_SHORT)
2726 if (TARGET_LONG_CALLS && flag_function_sections)
2729 if (current_file_function_operand (sym_ref))
2732 return (call_cookie & CALL_LONG)
2733 || ENCODED_LONG_CALL_ATTR_P (XSTR (sym_ref, 0))
2734 || TARGET_LONG_CALLS;
2737 /* Return nonzero if it is ok to make a tail-call to DECL. */
2739 arm_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
2741 int call_type = TARGET_LONG_CALLS ? CALL_LONG : CALL_NORMAL;
2743 if (cfun->machine->sibcall_blocked)
2746 /* Never tailcall something for which we have no decl, or if we
2747 are in Thumb mode. */
2748 if (decl == NULL || TARGET_THUMB)
2751 /* Get the calling method. */
2752 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
2753 call_type = CALL_SHORT;
2754 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
2755 call_type = CALL_LONG;
2757 /* Cannot tail-call to long calls, since these are out of range of
2758 a branch instruction. However, if not compiling PIC, we know
2759 we can reach the symbol if it is in this compilation unit. */
2760 if (call_type == CALL_LONG && (flag_pic || !TREE_ASM_WRITTEN (decl)))
2763 /* If we are interworking and the function is not declared static
2764 then we can't tail-call it unless we know that it exists in this
2765 compilation unit (since it might be a Thumb routine). */
2766 if (TARGET_INTERWORK && TREE_PUBLIC (decl) && !TREE_ASM_WRITTEN (decl))
2769 /* Never tailcall from an ISR routine - it needs a special exit sequence. */
2770 if (IS_INTERRUPT (arm_current_func_type ()))
2773 /* Everything else is ok. */
2778 /* Addressing mode support functions. */
2780 /* Return nonzero if X is a legitimate immediate operand when compiling
2783 legitimate_pic_operand_p (rtx x)
2787 && (GET_CODE (x) == SYMBOL_REF
2788 || (GET_CODE (x) == CONST
2789 && GET_CODE (XEXP (x, 0)) == PLUS
2790 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)))
2797 legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg)
2799 if (GET_CODE (orig) == SYMBOL_REF
2800 || GET_CODE (orig) == LABEL_REF)
2802 #ifndef AOF_ASSEMBLER
2803 rtx pic_ref, address;
2813 reg = gen_reg_rtx (Pmode);
2818 #ifdef AOF_ASSEMBLER
2819 /* The AOF assembler can generate relocations for these directly, and
2820 understands that the PIC register has to be added into the offset. */
2821 insn = emit_insn (gen_pic_load_addr_based (reg, orig));
2824 address = gen_reg_rtx (Pmode);
2829 emit_insn (gen_pic_load_addr_arm (address, orig));
2831 emit_insn (gen_pic_load_addr_thumb (address, orig));
2833 if ((GET_CODE (orig) == LABEL_REF
2834 || (GET_CODE (orig) == SYMBOL_REF &&
2835 SYMBOL_REF_LOCAL_P (orig)))
2837 pic_ref = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, address);
2840 pic_ref = gen_rtx_MEM (Pmode,
2841 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
2843 RTX_UNCHANGING_P (pic_ref) = 1;
2846 insn = emit_move_insn (reg, pic_ref);
2848 current_function_uses_pic_offset_table = 1;
2849 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2851 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
2855 else if (GET_CODE (orig) == CONST)
2859 if (GET_CODE (XEXP (orig, 0)) == PLUS
2860 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
2868 reg = gen_reg_rtx (Pmode);
2871 if (GET_CODE (XEXP (orig, 0)) == PLUS)
2873 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
2874 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
2875 base == reg ? 0 : reg);
2880 if (GET_CODE (offset) == CONST_INT)
2882 /* The base register doesn't really matter, we only want to
2883 test the index for the appropriate mode. */
2884 if (!arm_legitimate_index_p (mode, offset, SET, 0))
2886 if (!no_new_pseudos)
2887 offset = force_reg (Pmode, offset);
2892 if (GET_CODE (offset) == CONST_INT)
2893 return plus_constant (base, INTVAL (offset));
2896 if (GET_MODE_SIZE (mode) > 4
2897 && (GET_MODE_CLASS (mode) == MODE_INT
2898 || TARGET_SOFT_FLOAT))
2900 emit_insn (gen_addsi3 (reg, base, offset));
2904 return gen_rtx_PLUS (Pmode, base, offset);
2910 /* Generate code to load the PIC register. PROLOGUE is true if
2911 called from arm_expand_prologue (in which case we want the
2912 generated insns at the start of the function); false if called
2913 by an exception receiver that needs the PIC register reloaded
2914 (in which case the insns are just dumped at the current location). */
2916 arm_finalize_pic (int prologue ATTRIBUTE_UNUSED)
2918 #ifndef AOF_ASSEMBLER
2919 rtx l1, pic_tmp, pic_tmp2, seq, pic_rtx;
2920 rtx global_offset_table;
2922 if (current_function_uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE)
2929 l1 = gen_label_rtx ();
2931 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
2932 /* On the ARM the PC register contains 'dot + 8' at the time of the
2933 addition, on the Thumb it is 'dot + 4'. */
2934 pic_tmp = plus_constant (gen_rtx_LABEL_REF (Pmode, l1), TARGET_ARM ? 8 : 4);
2936 pic_tmp2 = gen_rtx_CONST (VOIDmode,
2937 gen_rtx_PLUS (Pmode, global_offset_table, pc_rtx));
2939 pic_tmp2 = gen_rtx_CONST (VOIDmode, global_offset_table);
2941 pic_rtx = gen_rtx_CONST (Pmode, gen_rtx_MINUS (Pmode, pic_tmp2, pic_tmp));
2945 emit_insn (gen_pic_load_addr_arm (pic_offset_table_rtx, pic_rtx));
2946 emit_insn (gen_pic_add_dot_plus_eight (pic_offset_table_rtx, l1));
2950 emit_insn (gen_pic_load_addr_thumb (pic_offset_table_rtx, pic_rtx));
2951 emit_insn (gen_pic_add_dot_plus_four (pic_offset_table_rtx, l1));
2957 emit_insn_after (seq, get_insns ());
2961 /* Need to emit this whether or not we obey regdecls,
2962 since setjmp/longjmp can cause life info to screw up. */
2963 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
2964 #endif /* AOF_ASSEMBLER */
2967 /* Return nonzero if X is valid as an ARM state addressing register. */
2969 arm_address_register_rtx_p (rtx x, int strict_p)
2973 if (GET_CODE (x) != REG)
2979 return ARM_REGNO_OK_FOR_BASE_P (regno);
2981 return (regno <= LAST_ARM_REGNUM
2982 || regno >= FIRST_PSEUDO_REGISTER
2983 || regno == FRAME_POINTER_REGNUM
2984 || regno == ARG_POINTER_REGNUM);
2987 /* Return nonzero if X is a valid ARM state address operand. */
2989 arm_legitimate_address_p (enum machine_mode mode, rtx x, RTX_CODE outer,
2992 if (arm_address_register_rtx_p (x, strict_p))
2995 else if (GET_CODE (x) == POST_INC || GET_CODE (x) == PRE_DEC)
2996 return arm_address_register_rtx_p (XEXP (x, 0), strict_p);
2998 else if ((GET_CODE (x) == POST_MODIFY || GET_CODE (x) == PRE_MODIFY)
2999 && GET_MODE_SIZE (mode) <= 4
3000 && arm_address_register_rtx_p (XEXP (x, 0), strict_p)
3001 && GET_CODE (XEXP (x, 1)) == PLUS
3002 && XEXP (XEXP (x, 1), 0) == XEXP (x, 0))
3003 return arm_legitimate_index_p (mode, XEXP (XEXP (x, 1), 1), outer,
3006 /* After reload constants split into minipools will have addresses
3007 from a LABEL_REF. */
3008 else if (reload_completed
3009 && (GET_CODE (x) == LABEL_REF
3010 || (GET_CODE (x) == CONST
3011 && GET_CODE (XEXP (x, 0)) == PLUS
3012 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
3013 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
3016 else if (mode == TImode)
3019 else if (mode == DImode || (TARGET_SOFT_FLOAT && mode == DFmode))
3021 if (GET_CODE (x) == PLUS
3022 && arm_address_register_rtx_p (XEXP (x, 0), strict_p)
3023 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3025 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
3027 if (val == 4 || val == -4 || val == -8)
3032 else if (TARGET_HARD_FLOAT && TARGET_VFP && mode == DFmode)
3034 if (GET_CODE (x) == PLUS
3035 && arm_address_register_rtx_p (XEXP (x, 0), strict_p)
3036 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3038 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
3040 /* ??? valid arm offsets are a subset of VFP offsets.
3041 For now only allow this subset. Proper fix is to add an
3042 additional memory constraint for arm address modes.
3043 Alternatively allow full vfp addressing and let
3044 output_move_double fix it up with a sub-optimal sequence. */
3045 if (val == 4 || val == -4 || val == -8)
3050 else if (GET_CODE (x) == PLUS)
3052 rtx xop0 = XEXP (x, 0);
3053 rtx xop1 = XEXP (x, 1);
3055 return ((arm_address_register_rtx_p (xop0, strict_p)
3056 && arm_legitimate_index_p (mode, xop1, outer, strict_p))
3057 || (arm_address_register_rtx_p (xop1, strict_p)
3058 && arm_legitimate_index_p (mode, xop0, outer, strict_p)));
3062 /* Reload currently can't handle MINUS, so disable this for now */
3063 else if (GET_CODE (x) == MINUS)
3065 rtx xop0 = XEXP (x, 0);
3066 rtx xop1 = XEXP (x, 1);
3068 return (arm_address_register_rtx_p (xop0, strict_p)
3069 && arm_legitimate_index_p (mode, xop1, outer, strict_p));
3073 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
3074 && GET_CODE (x) == SYMBOL_REF
3075 && CONSTANT_POOL_ADDRESS_P (x)
3077 && symbol_mentioned_p (get_pool_constant (x))))
3080 else if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == POST_DEC)
3081 && (GET_MODE_SIZE (mode) <= 4)
3082 && arm_address_register_rtx_p (XEXP (x, 0), strict_p))
3088 /* Return nonzero if INDEX is valid for an address index operand in
3091 arm_legitimate_index_p (enum machine_mode mode, rtx index, RTX_CODE outer,
3094 HOST_WIDE_INT range;
3095 enum rtx_code code = GET_CODE (index);
3097 if (TARGET_HARD_FLOAT && TARGET_FPA && GET_MODE_CLASS (mode) == MODE_FLOAT)
3098 return (code == CONST_INT && INTVAL (index) < 1024
3099 && INTVAL (index) > -1024
3100 && (INTVAL (index) & 3) == 0);
3102 if (TARGET_HARD_FLOAT && TARGET_MAVERICK
3103 && (GET_MODE_CLASS (mode) == MODE_FLOAT || mode == DImode))
3104 return (code == CONST_INT
3105 && INTVAL (index) < 255
3106 && INTVAL (index) > -255);
3108 if (arm_address_register_rtx_p (index, strict_p)
3109 && GET_MODE_SIZE (mode) <= 4)
3112 if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode))
3113 return (code == CONST_INT
3114 && INTVAL (index) < 256
3115 && INTVAL (index) > -256);
3117 if (GET_MODE_SIZE (mode) <= 4
3120 || (mode == QImode && outer == SIGN_EXTEND))))
3124 rtx xiop0 = XEXP (index, 0);
3125 rtx xiop1 = XEXP (index, 1);
3127 return ((arm_address_register_rtx_p (xiop0, strict_p)
3128 && power_of_two_operand (xiop1, SImode))
3129 || (arm_address_register_rtx_p (xiop1, strict_p)
3130 && power_of_two_operand (xiop0, SImode)));
3132 else if (code == LSHIFTRT || code == ASHIFTRT
3133 || code == ASHIFT || code == ROTATERT)
3135 rtx op = XEXP (index, 1);
3137 return (arm_address_register_rtx_p (XEXP (index, 0), strict_p)
3138 && GET_CODE (op) == CONST_INT
3140 && INTVAL (op) <= 31);
3144 /* For ARM v4 we may be doing a sign-extend operation during the
3148 if (mode == HImode || (outer == SIGN_EXTEND && mode == QImode))
3154 range = (mode == HImode) ? 4095 : 4096;
3156 return (code == CONST_INT
3157 && INTVAL (index) < range
3158 && INTVAL (index) > -range);
3161 /* Return nonzero if X is valid as a Thumb state base register. */
3163 thumb_base_register_rtx_p (rtx x, enum machine_mode mode, int strict_p)
3167 if (GET_CODE (x) != REG)
3173 return THUMB_REGNO_MODE_OK_FOR_BASE_P (regno, mode);
3175 return (regno <= LAST_LO_REGNUM
3176 || regno > LAST_VIRTUAL_REGISTER
3177 || regno == FRAME_POINTER_REGNUM
3178 || (GET_MODE_SIZE (mode) >= 4
3179 && (regno == STACK_POINTER_REGNUM
3180 || regno >= FIRST_PSEUDO_REGISTER
3181 || x == hard_frame_pointer_rtx
3182 || x == arg_pointer_rtx)));
3185 /* Return nonzero if x is a legitimate index register. This is the case
3186 for any base register that can access a QImode object. */
3188 thumb_index_register_rtx_p (rtx x, int strict_p)
3190 return thumb_base_register_rtx_p (x, QImode, strict_p);
3193 /* Return nonzero if x is a legitimate Thumb-state address.
3195 The AP may be eliminated to either the SP or the FP, so we use the
3196 least common denominator, e.g. SImode, and offsets from 0 to 64.
3198 ??? Verify whether the above is the right approach.
3200 ??? Also, the FP may be eliminated to the SP, so perhaps that
3201 needs special handling also.
3203 ??? Look at how the mips16 port solves this problem. It probably uses
3204 better ways to solve some of these problems.
3206 Although it is not incorrect, we don't accept QImode and HImode
3207 addresses based on the frame pointer or arg pointer until the
3208 reload pass starts. This is so that eliminating such addresses
3209 into stack based ones won't produce impossible code. */
3211 thumb_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p)
3213 /* ??? Not clear if this is right. Experiment. */
3214 if (GET_MODE_SIZE (mode) < 4
3215 && !(reload_in_progress || reload_completed)
3216 && (reg_mentioned_p (frame_pointer_rtx, x)
3217 || reg_mentioned_p (arg_pointer_rtx, x)
3218 || reg_mentioned_p (virtual_incoming_args_rtx, x)
3219 || reg_mentioned_p (virtual_outgoing_args_rtx, x)
3220 || reg_mentioned_p (virtual_stack_dynamic_rtx, x)
3221 || reg_mentioned_p (virtual_stack_vars_rtx, x)))
3224 /* Accept any base register. SP only in SImode or larger. */
3225 else if (thumb_base_register_rtx_p (x, mode, strict_p))
3228 /* This is PC relative data before arm_reorg runs. */
3229 else if (GET_MODE_SIZE (mode) >= 4 && CONSTANT_P (x)
3230 && GET_CODE (x) == SYMBOL_REF
3231 && CONSTANT_POOL_ADDRESS_P (x) && ! flag_pic)
3234 /* This is PC relative data after arm_reorg runs. */
3235 else if (GET_MODE_SIZE (mode) >= 4 && reload_completed
3236 && (GET_CODE (x) == LABEL_REF
3237 || (GET_CODE (x) == CONST
3238 && GET_CODE (XEXP (x, 0)) == PLUS
3239 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
3240 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
3243 /* Post-inc indexing only supported for SImode and larger. */
3244 else if (GET_CODE (x) == POST_INC && GET_MODE_SIZE (mode) >= 4
3245 && thumb_index_register_rtx_p (XEXP (x, 0), strict_p))
3248 else if (GET_CODE (x) == PLUS)
3250 /* REG+REG address can be any two index registers. */
3251 /* We disallow FRAME+REG addressing since we know that FRAME
3252 will be replaced with STACK, and SP relative addressing only
3253 permits SP+OFFSET. */
3254 if (GET_MODE_SIZE (mode) <= 4
3255 && XEXP (x, 0) != frame_pointer_rtx
3256 && XEXP (x, 1) != frame_pointer_rtx
3257 && thumb_index_register_rtx_p (XEXP (x, 0), strict_p)
3258 && thumb_index_register_rtx_p (XEXP (x, 1), strict_p))
3261 /* REG+const has 5-7 bit offset for non-SP registers. */
3262 else if ((thumb_index_register_rtx_p (XEXP (x, 0), strict_p)
3263 || XEXP (x, 0) == arg_pointer_rtx)
3264 && GET_CODE (XEXP (x, 1)) == CONST_INT
3265 && thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1))))
3268 /* REG+const has 10 bit offset for SP, but only SImode and
3269 larger is supported. */
3270 /* ??? Should probably check for DI/DFmode overflow here
3271 just like GO_IF_LEGITIMATE_OFFSET does. */
3272 else if (GET_CODE (XEXP (x, 0)) == REG
3273 && REGNO (XEXP (x, 0)) == STACK_POINTER_REGNUM
3274 && GET_MODE_SIZE (mode) >= 4
3275 && GET_CODE (XEXP (x, 1)) == CONST_INT
3276 && INTVAL (XEXP (x, 1)) >= 0
3277 && INTVAL (XEXP (x, 1)) + GET_MODE_SIZE (mode) <= 1024
3278 && (INTVAL (XEXP (x, 1)) & 3) == 0)
3281 else if (GET_CODE (XEXP (x, 0)) == REG
3282 && REGNO (XEXP (x, 0)) == FRAME_POINTER_REGNUM
3283 && GET_MODE_SIZE (mode) >= 4
3284 && GET_CODE (XEXP (x, 1)) == CONST_INT
3285 && (INTVAL (XEXP (x, 1)) & 3) == 0)
3289 else if (GET_MODE_CLASS (mode) != MODE_FLOAT
3290 && GET_MODE_SIZE (mode) == 4
3291 && GET_CODE (x) == SYMBOL_REF
3292 && CONSTANT_POOL_ADDRESS_P (x)
3294 && symbol_mentioned_p (get_pool_constant (x))))
3300 /* Return nonzero if VAL can be used as an offset in a Thumb-state address
3301 instruction of mode MODE. */
3303 thumb_legitimate_offset_p (enum machine_mode mode, HOST_WIDE_INT val)
3305 switch (GET_MODE_SIZE (mode))
3308 return val >= 0 && val < 32;
3311 return val >= 0 && val < 64 && (val & 1) == 0;
3315 && (val + GET_MODE_SIZE (mode)) <= 128
3320 /* Try machine-dependent ways of modifying an illegitimate address
3321 to be legitimate. If we find one, return the new, valid address. */
3323 arm_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)
3325 if (GET_CODE (x) == PLUS)
3327 rtx xop0 = XEXP (x, 0);
3328 rtx xop1 = XEXP (x, 1);
3330 if (CONSTANT_P (xop0) && !symbol_mentioned_p (xop0))
3331 xop0 = force_reg (SImode, xop0);
3333 if (CONSTANT_P (xop1) && !symbol_mentioned_p (xop1))
3334 xop1 = force_reg (SImode, xop1);
3336 if (ARM_BASE_REGISTER_RTX_P (xop0)
3337 && GET_CODE (xop1) == CONST_INT)
3339 HOST_WIDE_INT n, low_n;
3343 /* VFP addressing modes actually allow greater offsets, but for
3344 now we just stick with the lowest common denominator. */
3346 || ((TARGET_SOFT_FLOAT || TARGET_VFP) && mode == DFmode))
3358 low_n = ((mode) == TImode ? 0
3359 : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff));
3363 base_reg = gen_reg_rtx (SImode);
3364 val = force_operand (gen_rtx_PLUS (SImode, xop0,
3365 GEN_INT (n)), NULL_RTX);
3366 emit_move_insn (base_reg, val);
3367 x = (low_n == 0 ? base_reg
3368 : gen_rtx_PLUS (SImode, base_reg, GEN_INT (low_n)));
3370 else if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1))
3371 x = gen_rtx_PLUS (SImode, xop0, xop1);
3374 /* XXX We don't allow MINUS any more -- see comment in
3375 arm_legitimate_address_p (). */
3376 else if (GET_CODE (x) == MINUS)
3378 rtx xop0 = XEXP (x, 0);
3379 rtx xop1 = XEXP (x, 1);
3381 if (CONSTANT_P (xop0))
3382 xop0 = force_reg (SImode, xop0);
3384 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1))
3385 xop1 = force_reg (SImode, xop1);
3387 if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1))
3388 x = gen_rtx_MINUS (SImode, xop0, xop1);
3393 /* We need to find and carefully transform any SYMBOL and LABEL
3394 references; so go back to the original address expression. */
3395 rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX);
3397 if (new_x != orig_x)
3405 /* Try machine-dependent ways of modifying an illegitimate Thumb address
3406 to be legitimate. If we find one, return the new, valid address. */
3408 thumb_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)
3410 if (GET_CODE (x) == PLUS
3411 && GET_CODE (XEXP (x, 1)) == CONST_INT
3412 && (INTVAL (XEXP (x, 1)) >= 32 * GET_MODE_SIZE (mode)
3413 || INTVAL (XEXP (x, 1)) < 0))
3415 rtx xop0 = XEXP (x, 0);
3416 rtx xop1 = XEXP (x, 1);
3417 HOST_WIDE_INT offset = INTVAL (xop1);
3419 /* Try and fold the offset into a biasing of the base register and
3420 then offsetting that. Don't do this when optimizing for space
3421 since it can cause too many CSEs. */
3422 if (optimize_size && offset >= 0
3423 && offset < 256 + 31 * GET_MODE_SIZE (mode))
3425 HOST_WIDE_INT delta;
3428 delta = offset - (256 - GET_MODE_SIZE (mode));
3429 else if (offset < 32 * GET_MODE_SIZE (mode) + 8)
3430 delta = 31 * GET_MODE_SIZE (mode);
3432 delta = offset & (~31 * GET_MODE_SIZE (mode));
3434 xop0 = force_operand (plus_constant (xop0, offset - delta),
3436 x = plus_constant (xop0, delta);
3438 else if (offset < 0 && offset > -256)
3439 /* Small negative offsets are best done with a subtract before the
3440 dereference, forcing these into a register normally takes two
3442 x = force_operand (x, NULL_RTX);
3445 /* For the remaining cases, force the constant into a register. */
3446 xop1 = force_reg (SImode, xop1);
3447 x = gen_rtx_PLUS (SImode, xop0, xop1);
3450 else if (GET_CODE (x) == PLUS
3451 && s_register_operand (XEXP (x, 1), SImode)
3452 && !s_register_operand (XEXP (x, 0), SImode))
3454 rtx xop0 = force_operand (XEXP (x, 0), NULL_RTX);
3456 x = gen_rtx_PLUS (SImode, xop0, XEXP (x, 1));
3461 /* We need to find and carefully transform any SYMBOL and LABEL
3462 references; so go back to the original address expression. */
3463 rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX);
3465 if (new_x != orig_x)
3474 #define REG_OR_SUBREG_REG(X) \
3475 (GET_CODE (X) == REG \
3476 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
3478 #define REG_OR_SUBREG_RTX(X) \
3479 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
3481 #ifndef COSTS_N_INSNS
3482 #define COSTS_N_INSNS(N) ((N) * 4 - 2)
3485 thumb_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer)
3487 enum machine_mode mode = GET_MODE (x);
3500 return COSTS_N_INSNS (1);
3503 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
3506 unsigned HOST_WIDE_INT i = INTVAL (XEXP (x, 1));
3513 return COSTS_N_INSNS (2) + cycles;
3515 return COSTS_N_INSNS (1) + 16;
3518 return (COSTS_N_INSNS (1)
3519 + 4 * ((GET_CODE (SET_SRC (x)) == MEM)
3520 + GET_CODE (SET_DEST (x)) == MEM));
3525 if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256)
3527 if (thumb_shiftable_const (INTVAL (x)))
3528 return COSTS_N_INSNS (2);
3529 return COSTS_N_INSNS (3);
3531 else if ((outer == PLUS || outer == COMPARE)
3532 && INTVAL (x) < 256 && INTVAL (x) > -256)
3534 else if (outer == AND
3535 && INTVAL (x) < 256 && INTVAL (x) >= -256)
3536 return COSTS_N_INSNS (1);
3537 else if (outer == ASHIFT || outer == ASHIFTRT
3538 || outer == LSHIFTRT)
3540 return COSTS_N_INSNS (2);
3546 return COSTS_N_INSNS (3);
3565 /* XXX another guess. */
3566 /* Memory costs quite a lot for the first word, but subsequent words
3567 load at the equivalent of a single insn each. */
3568 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
3569 + ((GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
3574 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
3579 /* XXX still guessing. */
3580 switch (GET_MODE (XEXP (x, 0)))
3583 return (1 + (mode == DImode ? 4 : 0)
3584 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3587 return (4 + (mode == DImode ? 4 : 0)
3588 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3591 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3603 /* Worker routine for arm_rtx_costs. */
3605 arm_rtx_costs_1 (rtx x, enum rtx_code code, enum rtx_code outer)
3607 enum machine_mode mode = GET_MODE (x);
3608 enum rtx_code subcode;
3614 /* Memory costs quite a lot for the first word, but subsequent words
3615 load at the equivalent of a single insn each. */
3616 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
3617 + (GET_CODE (x) == SYMBOL_REF
3618 && CONSTANT_POOL_ADDRESS_P (x) ? 4 : 0));
3624 return optimize_size ? COSTS_N_INSNS (2) : 100;
3627 if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG)
3634 case ASHIFT: case LSHIFTRT: case ASHIFTRT:
3636 return (8 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : 8)
3637 + ((GET_CODE (XEXP (x, 0)) == REG
3638 || (GET_CODE (XEXP (x, 0)) == SUBREG
3639 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
3641 return (1 + ((GET_CODE (XEXP (x, 0)) == REG
3642 || (GET_CODE (XEXP (x, 0)) == SUBREG
3643 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
3645 + ((GET_CODE (XEXP (x, 1)) == REG
3646 || (GET_CODE (XEXP (x, 1)) == SUBREG
3647 && GET_CODE (SUBREG_REG (XEXP (x, 1))) == REG)
3648 || (GET_CODE (XEXP (x, 1)) == CONST_INT))
3653 return (4 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 8)
3654 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
3655 || (GET_CODE (XEXP (x, 0)) == CONST_INT
3656 && const_ok_for_arm (INTVAL (XEXP (x, 0)))))
3659 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
3660 return (2 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
3661 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
3662 && arm_const_double_rtx (XEXP (x, 1))))
3664 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
3665 || (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE
3666 && arm_const_double_rtx (XEXP (x, 0))))
3669 if (((GET_CODE (XEXP (x, 0)) == CONST_INT
3670 && const_ok_for_arm (INTVAL (XEXP (x, 0)))
3671 && REG_OR_SUBREG_REG (XEXP (x, 1))))
3672 || (((subcode = GET_CODE (XEXP (x, 1))) == ASHIFT
3673 || subcode == ASHIFTRT || subcode == LSHIFTRT
3674 || subcode == ROTATE || subcode == ROTATERT
3676 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
3677 && ((INTVAL (XEXP (XEXP (x, 1), 1)) &
3678 (INTVAL (XEXP (XEXP (x, 1), 1)) - 1)) == 0)))
3679 && REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 0))
3680 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 1))
3681 || GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT)
3682 && REG_OR_SUBREG_REG (XEXP (x, 0))))
3687 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
3688 return (2 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
3689 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
3690 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
3691 && arm_const_double_rtx (XEXP (x, 1))))
3695 case AND: case XOR: case IOR:
3698 /* Normally the frame registers will be spilt into reg+const during
3699 reload, so it is a bad idea to combine them with other instructions,
3700 since then they might not be moved outside of loops. As a compromise
3701 we allow integration with ops that have a constant as their second
3703 if ((REG_OR_SUBREG_REG (XEXP (x, 0))
3704 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))
3705 && GET_CODE (XEXP (x, 1)) != CONST_INT)
3706 || (REG_OR_SUBREG_REG (XEXP (x, 0))
3707 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))))
3711 return (4 + extra_cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
3712 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
3713 || (GET_CODE (XEXP (x, 1)) == CONST_INT
3714 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
3717 if (REG_OR_SUBREG_REG (XEXP (x, 0)))
3718 return (1 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : extra_cost)
3719 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
3720 || (GET_CODE (XEXP (x, 1)) == CONST_INT
3721 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
3724 else if (REG_OR_SUBREG_REG (XEXP (x, 1)))
3725 return (1 + extra_cost
3726 + ((((subcode = GET_CODE (XEXP (x, 0))) == ASHIFT
3727 || subcode == LSHIFTRT || subcode == ASHIFTRT
3728 || subcode == ROTATE || subcode == ROTATERT
3730 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3731 && ((INTVAL (XEXP (XEXP (x, 0), 1)) &
3732 (INTVAL (XEXP (XEXP (x, 0), 1)) - 1)) == 0)))
3733 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 0)))
3734 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 1)))
3735 || GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))
3741 /* This should have been handled by the CPU specific routines. */
3745 if (arm_arch3m && mode == SImode
3746 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
3747 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
3748 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0))
3749 == GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)))
3750 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ZERO_EXTEND
3751 || GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SIGN_EXTEND))
3756 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
3757 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 6);
3761 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
3763 return 1 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
3766 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
3774 return 4 + (mode == DImode ? 4 : 0);
3777 if (GET_MODE (XEXP (x, 0)) == QImode)
3778 return (4 + (mode == DImode ? 4 : 0)
3779 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3782 switch (GET_MODE (XEXP (x, 0)))
3785 return (1 + (mode == DImode ? 4 : 0)
3786 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3789 return (4 + (mode == DImode ? 4 : 0)
3790 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3793 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
3808 if (const_ok_for_arm (INTVAL (x)))
3809 return outer == SET ? 2 : -1;
3810 else if (outer == AND
3811 && const_ok_for_arm (~INTVAL (x)))
3813 else if ((outer == COMPARE
3814 || outer == PLUS || outer == MINUS)
3815 && const_ok_for_arm (-INTVAL (x)))
3826 if (arm_const_double_rtx (x))
3827 return outer == SET ? 2 : -1;
3828 else if ((outer == COMPARE || outer == PLUS)
3829 && neg_const_double_rtx_ok_for_fpa (x))
3838 /* RTX costs for cores with a slow MUL implementation. */
3841 arm_slowmul_rtx_costs (rtx x, int code, int outer_code, int *total)
3843 enum machine_mode mode = GET_MODE (x);
3847 *total = thumb_rtx_costs (x, code, outer_code);
3854 if (GET_MODE_CLASS (mode) == MODE_FLOAT
3861 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
3863 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
3864 & (unsigned HOST_WIDE_INT) 0xffffffff);
3865 int cost, const_ok = const_ok_for_arm (i);
3866 int j, booth_unit_size;
3868 /* Tune as appropriate. */
3869 cost = const_ok ? 4 : 8;
3870 booth_unit_size = 2;
3871 for (j = 0; i && j < 32; j += booth_unit_size)
3873 i >>= booth_unit_size;
3881 *total = 30 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
3882 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
3886 *total = arm_rtx_costs_1 (x, code, outer_code);
3892 /* RTX cost for cores with a fast multiply unit (M variants). */
3895 arm_fastmul_rtx_costs (rtx x, int code, int outer_code, int *total)
3897 enum machine_mode mode = GET_MODE (x);
3901 *total = thumb_rtx_costs (x, code, outer_code);
3908 /* There is no point basing this on the tuning, since it is always the
3909 fast variant if it exists at all. */
3911 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
3912 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
3913 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
3920 if (GET_MODE_CLASS (mode) == MODE_FLOAT
3927 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
3929 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
3930 & (unsigned HOST_WIDE_INT) 0xffffffff);
3931 int cost, const_ok = const_ok_for_arm (i);
3932 int j, booth_unit_size;
3934 /* Tune as appropriate. */
3935 cost = const_ok ? 4 : 8;
3936 booth_unit_size = 8;
3937 for (j = 0; i && j < 32; j += booth_unit_size)
3939 i >>= booth_unit_size;
3947 *total = 8 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
3948 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
3952 *total = arm_rtx_costs_1 (x, code, outer_code);
3958 /* RTX cost for XScale CPUs. */
3961 arm_xscale_rtx_costs (rtx x, int code, int outer_code, int *total)
3963 enum machine_mode mode = GET_MODE (x);
3967 *total = thumb_rtx_costs (x, code, outer_code);
3974 /* There is no point basing this on the tuning, since it is always the
3975 fast variant if it exists at all. */
3977 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
3978 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
3979 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
3986 if (GET_MODE_CLASS (mode) == MODE_FLOAT
3993 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
3995 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
3996 & (unsigned HOST_WIDE_INT) 0xffffffff);
3997 int cost, const_ok = const_ok_for_arm (i);
3998 unsigned HOST_WIDE_INT masked_const;
4000 /* The cost will be related to two insns.
4001 First a load of the constant (MOV or LDR), then a multiply. */
4004 cost += 1; /* LDR is probably more expensive because
4005 of longer result latency. */
4006 masked_const = i & 0xffff8000;
4007 if (masked_const != 0 && masked_const != 0xffff8000)
4009 masked_const = i & 0xf8000000;
4010 if (masked_const == 0 || masked_const == 0xf8000000)
4019 *total = 8 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
4020 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4);
4024 *total = arm_rtx_costs_1 (x, code, outer_code);
4030 /* RTX costs for 9e (and later) cores. */
4033 arm_9e_rtx_costs (rtx x, int code, int outer_code, int *total)
4035 enum machine_mode mode = GET_MODE (x);
4044 *total = COSTS_N_INSNS (3);
4048 *total = thumb_rtx_costs (x, code, outer_code);
4056 /* There is no point basing this on the tuning, since it is always the
4057 fast variant if it exists at all. */
4059 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
4060 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
4061 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
4068 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
4085 *total = cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : nonreg_cost)
4086 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : nonreg_cost);
4090 *total = arm_rtx_costs_1 (x, code, outer_code);
4094 /* All address computations that can be done are free, but rtx cost returns
4095 the same for practically all of them. So we weight the different types
4096 of address here in the order (most pref first):
4097 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
4099 arm_arm_address_cost (rtx x)
4101 enum rtx_code c = GET_CODE (x);
4103 if (c == PRE_INC || c == PRE_DEC || c == POST_INC || c == POST_DEC)
4105 if (c == MEM || c == LABEL_REF || c == SYMBOL_REF)
4108 if (c == PLUS || c == MINUS)
4110 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
4113 if (ARITHMETIC_P (XEXP (x, 0)) || ARITHMETIC_P (XEXP (x, 1)))
4123 arm_thumb_address_cost (rtx x)
4125 enum rtx_code c = GET_CODE (x);
4130 && GET_CODE (XEXP (x, 0)) == REG
4131 && GET_CODE (XEXP (x, 1)) == CONST_INT)
4138 arm_address_cost (rtx x)
4140 return TARGET_ARM ? arm_arm_address_cost (x) : arm_thumb_address_cost (x);
4144 arm_use_dfa_pipeline_interface (void)
4150 arm_adjust_cost (rtx insn, rtx link, rtx dep, int cost)
4154 /* Some true dependencies can have a higher cost depending
4155 on precisely how certain input operands are used. */
4157 && REG_NOTE_KIND (link) == 0
4158 && recog_memoized (insn) >= 0
4159 && recog_memoized (dep) >= 0)
4161 int shift_opnum = get_attr_shift (insn);
4162 enum attr_type attr_type = get_attr_type (dep);
4164 /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted
4165 operand for INSN. If we have a shifted input operand and the
4166 instruction we depend on is another ALU instruction, then we may
4167 have to account for an additional stall. */
4168 if (shift_opnum != 0
4169 && (attr_type == TYPE_ALU_SHIFT || attr_type == TYPE_ALU_SHIFT_REG))
4171 rtx shifted_operand;
4174 /* Get the shifted operand. */
4175 extract_insn (insn);
4176 shifted_operand = recog_data.operand[shift_opnum];
4178 /* Iterate over all the operands in DEP. If we write an operand
4179 that overlaps with SHIFTED_OPERAND, then we have increase the
4180 cost of this dependency. */
4182 preprocess_constraints ();
4183 for (opno = 0; opno < recog_data.n_operands; opno++)
4185 /* We can ignore strict inputs. */
4186 if (recog_data.operand_type[opno] == OP_IN)
4189 if (reg_overlap_mentioned_p (recog_data.operand[opno],
4196 /* XXX This is not strictly true for the FPA. */
4197 if (REG_NOTE_KIND (link) == REG_DEP_ANTI
4198 || REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
4201 /* Call insns don't incur a stall, even if they follow a load. */
4202 if (REG_NOTE_KIND (link) == 0
4203 && GET_CODE (insn) == CALL_INSN)
4206 if ((i_pat = single_set (insn)) != NULL
4207 && GET_CODE (SET_SRC (i_pat)) == MEM
4208 && (d_pat = single_set (dep)) != NULL
4209 && GET_CODE (SET_DEST (d_pat)) == MEM)
4211 rtx src_mem = XEXP (SET_SRC (i_pat), 0);
4212 /* This is a load after a store, there is no conflict if the load reads
4213 from a cached area. Assume that loads from the stack, and from the
4214 constant pool are cached, and that others will miss. This is a
4217 if ((GET_CODE (src_mem) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (src_mem))
4218 || reg_mentioned_p (stack_pointer_rtx, src_mem)
4219 || reg_mentioned_p (frame_pointer_rtx, src_mem)
4220 || reg_mentioned_p (hard_frame_pointer_rtx, src_mem))
4227 static int fp_consts_inited = 0;
4229 /* Only zero is valid for VFP. Other values are also valid for FPA. */
4230 static const char * const strings_fp[8] =
4233 "4", "5", "0.5", "10"
4236 static REAL_VALUE_TYPE values_fp[8];
4239 init_fp_table (void)
4245 fp_consts_inited = 1;
4247 fp_consts_inited = 8;
4249 for (i = 0; i < fp_consts_inited; i++)
4251 r = REAL_VALUE_ATOF (strings_fp[i], DFmode);
4256 /* Return TRUE if rtx X is a valid immediate FP constant. */
4258 arm_const_double_rtx (rtx x)
4263 if (!fp_consts_inited)
4266 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
4267 if (REAL_VALUE_MINUS_ZERO (r))
4270 for (i = 0; i < fp_consts_inited; i++)
4271 if (REAL_VALUES_EQUAL (r, values_fp[i]))
4277 /* Return TRUE if rtx X is a valid immediate FPA constant. */
4279 neg_const_double_rtx_ok_for_fpa (rtx x)
4284 if (!fp_consts_inited)
4287 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
4288 r = REAL_VALUE_NEGATE (r);
4289 if (REAL_VALUE_MINUS_ZERO (r))
4292 for (i = 0; i < 8; i++)
4293 if (REAL_VALUES_EQUAL (r, values_fp[i]))
4299 /* Predicates for `match_operand' and `match_operator'. */
4301 /* s_register_operand is the same as register_operand, but it doesn't accept
4304 This function exists because at the time it was put in it led to better
4305 code. SUBREG(MEM) always needs a reload in the places where
4306 s_register_operand is used, and this seemed to lead to excessive
4309 s_register_operand (rtx op, enum machine_mode mode)
4311 if (GET_MODE (op) != mode && mode != VOIDmode)
4314 if (GET_CODE (op) == SUBREG)
4315 op = SUBREG_REG (op);
4317 /* We don't consider registers whose class is NO_REGS
4318 to be a register operand. */
4319 /* XXX might have to check for lo regs only for thumb ??? */
4320 return (GET_CODE (op) == REG
4321 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
4322 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
4325 /* A hard register operand (even before reload. */
4327 arm_hard_register_operand (rtx op, enum machine_mode mode)
4329 if (GET_MODE (op) != mode && mode != VOIDmode)
4332 return (GET_CODE (op) == REG
4333 && REGNO (op) < FIRST_PSEUDO_REGISTER);
4336 /* An arm register operand. */
4338 arm_general_register_operand (rtx op, enum machine_mode mode)
4340 if (GET_MODE (op) != mode && mode != VOIDmode)
4343 if (GET_CODE (op) == SUBREG)
4344 op = SUBREG_REG (op);
4346 return (GET_CODE (op) == REG
4347 && (REGNO (op) <= LAST_ARM_REGNUM
4348 || REGNO (op) >= FIRST_PSEUDO_REGISTER));
4351 /* Only accept reg, subreg(reg), const_int. */
4353 reg_or_int_operand (rtx op, enum machine_mode mode)
4355 if (GET_CODE (op) == CONST_INT)
4358 if (GET_MODE (op) != mode && mode != VOIDmode)
4361 if (GET_CODE (op) == SUBREG)
4362 op = SUBREG_REG (op);
4364 /* We don't consider registers whose class is NO_REGS
4365 to be a register operand. */
4366 return (GET_CODE (op) == REG
4367 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
4368 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
4371 /* Return 1 if OP is an item in memory, given that we are in reload. */
4373 arm_reload_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4375 int regno = true_regnum (op);
4377 return (!CONSTANT_P (op)
4379 || (GET_CODE (op) == REG
4380 && REGNO (op) >= FIRST_PSEUDO_REGISTER)));
4383 /* Return TRUE for valid operands for the rhs of an ARM instruction. */
4385 arm_rhs_operand (rtx op, enum machine_mode mode)
4387 return (s_register_operand (op, mode)
4388 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op))));
4391 /* Return TRUE for valid operands for the
4392 rhs of an ARM instruction, or a load. */
4394 arm_rhsm_operand (rtx op, enum machine_mode mode)
4396 return (s_register_operand (op, mode)
4397 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op)))
4398 || memory_operand (op, mode));
4401 /* Return TRUE for valid operands for the rhs of an ARM instruction, or if a
4402 constant that is valid when negated. */
4404 arm_add_operand (rtx op, enum machine_mode mode)
4407 return thumb_cmp_operand (op, mode);
4409 return (s_register_operand (op, mode)
4410 || (GET_CODE (op) == CONST_INT
4411 && (const_ok_for_arm (INTVAL (op))
4412 || const_ok_for_arm (-INTVAL (op)))));
4415 /* Return TRUE for valid ARM constants (or when valid if negated). */
4417 arm_addimm_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4419 return (GET_CODE (op) == CONST_INT
4420 && (const_ok_for_arm (INTVAL (op))
4421 || const_ok_for_arm (-INTVAL (op))));
4425 arm_not_operand (rtx op, enum machine_mode mode)
4427 return (s_register_operand (op, mode)
4428 || (GET_CODE (op) == CONST_INT
4429 && (const_ok_for_arm (INTVAL (op))
4430 || const_ok_for_arm (~INTVAL (op)))));
4433 /* Return TRUE if the operand is a memory reference which contains an
4434 offsettable address. */
4436 offsettable_memory_operand (rtx op, enum machine_mode mode)
4438 if (mode == VOIDmode)
4439 mode = GET_MODE (op);
4441 return (mode == GET_MODE (op)
4442 && GET_CODE (op) == MEM
4443 && offsettable_address_p (reload_completed | reload_in_progress,
4444 mode, XEXP (op, 0)));
4447 /* Return TRUE if the operand is a memory reference which is, or can be
4448 made word aligned by adjusting the offset. */
4450 alignable_memory_operand (rtx op, enum machine_mode mode)
4454 if (mode == VOIDmode)
4455 mode = GET_MODE (op);
4457 if (mode != GET_MODE (op) || GET_CODE (op) != MEM)
4462 return ((GET_CODE (reg = op) == REG
4463 || (GET_CODE (op) == SUBREG
4464 && GET_CODE (reg = SUBREG_REG (op)) == REG)
4465 || (GET_CODE (op) == PLUS
4466 && GET_CODE (XEXP (op, 1)) == CONST_INT
4467 && (GET_CODE (reg = XEXP (op, 0)) == REG
4468 || (GET_CODE (XEXP (op, 0)) == SUBREG
4469 && GET_CODE (reg = SUBREG_REG (XEXP (op, 0))) == REG))))
4470 && REGNO_POINTER_ALIGN (REGNO (reg)) >= 32);
4473 /* Similar to s_register_operand, but does not allow hard integer
4476 f_register_operand (rtx op, enum machine_mode mode)
4478 if (GET_MODE (op) != mode && mode != VOIDmode)
4481 if (GET_CODE (op) == SUBREG)
4482 op = SUBREG_REG (op);
4484 /* We don't consider registers whose class is NO_REGS
4485 to be a register operand. */
4486 return (GET_CODE (op) == REG
4487 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
4488 || REGNO_REG_CLASS (REGNO (op)) == FPA_REGS));
4491 /* Return TRUE for valid operands for the rhs of an floating point insns.
4492 Allows regs or certain consts on FPA, just regs for everything else. */
4494 arm_float_rhs_operand (rtx op, enum machine_mode mode)
4496 if (s_register_operand (op, mode))
4499 if (GET_MODE (op) != mode && mode != VOIDmode)
4502 if (TARGET_FPA && GET_CODE (op) == CONST_DOUBLE)
4503 return arm_const_double_rtx (op);
4509 arm_float_add_operand (rtx op, enum machine_mode mode)
4511 if (s_register_operand (op, mode))
4514 if (GET_MODE (op) != mode && mode != VOIDmode)
4517 if (TARGET_FPA && GET_CODE (op) == CONST_DOUBLE)
4518 return (arm_const_double_rtx (op)
4519 || neg_const_double_rtx_ok_for_fpa (op));
4525 /* Return TRUE if OP is suitable for the rhs of a floating point comparison.
4526 Depends which fpu we are targeting. */
4529 arm_float_compare_operand (rtx op, enum machine_mode mode)
4532 return vfp_compare_operand (op, mode);
4534 return arm_float_rhs_operand (op, mode);
4538 /* Return nonzero if OP is a valid Cirrus memory address pattern. */
4540 cirrus_memory_offset (rtx op)
4542 /* Reject eliminable registers. */
4543 if (! (reload_in_progress || reload_completed)
4544 && ( reg_mentioned_p (frame_pointer_rtx, op)
4545 || reg_mentioned_p (arg_pointer_rtx, op)
4546 || reg_mentioned_p (virtual_incoming_args_rtx, op)
4547 || reg_mentioned_p (virtual_outgoing_args_rtx, op)
4548 || reg_mentioned_p (virtual_stack_dynamic_rtx, op)
4549 || reg_mentioned_p (virtual_stack_vars_rtx, op)))
4552 if (GET_CODE (op) == MEM)
4558 /* Match: (mem (reg)). */
4559 if (GET_CODE (ind) == REG)
4565 if (GET_CODE (ind) == PLUS
4566 && GET_CODE (XEXP (ind, 0)) == REG
4567 && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode)
4568 && GET_CODE (XEXP (ind, 1)) == CONST_INT)
4576 arm_extendqisi_mem_op (rtx op, enum machine_mode mode)
4578 if (!memory_operand (op, mode))
4581 return arm_legitimate_address_p (mode, XEXP (op, 0), SIGN_EXTEND, 0);
4584 /* Return nonzero if OP is a Cirrus or general register. */
4586 cirrus_register_operand (rtx op, enum machine_mode mode)
4588 if (GET_MODE (op) != mode && mode != VOIDmode)
4591 if (GET_CODE (op) == SUBREG)
4592 op = SUBREG_REG (op);
4594 return (GET_CODE (op) == REG
4595 && (REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS
4596 || REGNO_REG_CLASS (REGNO (op)) == GENERAL_REGS));
4599 /* Return nonzero if OP is a cirrus FP register. */
4601 cirrus_fp_register (rtx op, enum machine_mode mode)
4603 if (GET_MODE (op) != mode && mode != VOIDmode)
4606 if (GET_CODE (op) == SUBREG)
4607 op = SUBREG_REG (op);
4609 return (GET_CODE (op) == REG
4610 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
4611 || REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS));
4614 /* Return nonzero if OP is a 6bit constant (0..63). */
4616 cirrus_shift_const (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4618 return (GET_CODE (op) == CONST_INT
4620 && INTVAL (op) < 64);
4624 /* Return TRUE if OP is a valid VFP memory address pattern. */
4625 /* Copied from cirrus_memory_offset but with restricted offset range. */
4628 vfp_mem_operand (rtx op)
4630 /* Reject eliminable registers. */
4632 if (! (reload_in_progress || reload_completed)
4633 && ( reg_mentioned_p (frame_pointer_rtx, op)
4634 || reg_mentioned_p (arg_pointer_rtx, op)
4635 || reg_mentioned_p (virtual_incoming_args_rtx, op)
4636 || reg_mentioned_p (virtual_outgoing_args_rtx, op)
4637 || reg_mentioned_p (virtual_stack_dynamic_rtx, op)
4638 || reg_mentioned_p (virtual_stack_vars_rtx, op)))
4641 /* Constants are converted into offsets from labels. */
4642 if (GET_CODE (op) == MEM)
4648 if (reload_completed
4649 && (GET_CODE (ind) == LABEL_REF
4650 || (GET_CODE (ind) == CONST
4651 && GET_CODE (XEXP (ind, 0)) == PLUS
4652 && GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF
4653 && GET_CODE (XEXP (XEXP (ind, 0), 1)) == CONST_INT)))
4656 /* Match: (mem (reg)). */
4657 if (GET_CODE (ind) == REG)
4658 return arm_address_register_rtx_p (ind, 0);
4663 if (GET_CODE (ind) == PLUS
4664 && GET_CODE (XEXP (ind, 0)) == REG
4665 && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode)
4666 && GET_CODE (XEXP (ind, 1)) == CONST_INT
4667 && INTVAL (XEXP (ind, 1)) > -1024
4668 && INTVAL (XEXP (ind, 1)) < 1024)
4676 /* Return TRUE if OP is a REG or constant zero. */
4678 vfp_compare_operand (rtx op, enum machine_mode mode)
4680 if (s_register_operand (op, mode))
4683 return (GET_CODE (op) == CONST_DOUBLE
4684 && arm_const_double_rtx (op));
4688 /* Return GENERAL_REGS if a scratch register required to reload x to/from
4689 VFP registers. Otherwise return NO_REGS. */
4692 vfp_secondary_reload_class (enum machine_mode mode, rtx x)
4694 if (vfp_mem_operand (x) || s_register_operand (x, mode))
4697 return GENERAL_REGS;
4701 /* Returns TRUE if INSN is an "LDR REG, ADDR" instruction.
4702 Use by the Cirrus Maverick code which has to workaround
4703 a hardware bug triggered by such instructions. */
4705 arm_memory_load_p (rtx insn)
4707 rtx body, lhs, rhs;;
4709 if (insn == NULL_RTX || GET_CODE (insn) != INSN)
4712 body = PATTERN (insn);
4714 if (GET_CODE (body) != SET)
4717 lhs = XEXP (body, 0);
4718 rhs = XEXP (body, 1);
4720 lhs = REG_OR_SUBREG_RTX (lhs);
4722 /* If the destination is not a general purpose
4723 register we do not have to worry. */
4724 if (GET_CODE (lhs) != REG
4725 || REGNO_REG_CLASS (REGNO (lhs)) != GENERAL_REGS)
4728 /* As well as loads from memory we also have to react
4729 to loads of invalid constants which will be turned
4730 into loads from the minipool. */
4731 return (GET_CODE (rhs) == MEM
4732 || GET_CODE (rhs) == SYMBOL_REF
4733 || note_invalid_constants (insn, -1, false));
4736 /* Return TRUE if INSN is a Cirrus instruction. */
4738 arm_cirrus_insn_p (rtx insn)
4740 enum attr_cirrus attr;
4742 /* get_attr aborts on USE and CLOBBER. */
4744 || GET_CODE (insn) != INSN
4745 || GET_CODE (PATTERN (insn)) == USE
4746 || GET_CODE (PATTERN (insn)) == CLOBBER)
4749 attr = get_attr_cirrus (insn);
4751 return attr != CIRRUS_NOT;
4754 /* Cirrus reorg for invalid instruction combinations. */
4756 cirrus_reorg (rtx first)
4758 enum attr_cirrus attr;
4759 rtx body = PATTERN (first);
4763 /* Any branch must be followed by 2 non Cirrus instructions. */
4764 if (GET_CODE (first) == JUMP_INSN && GET_CODE (body) != RETURN)
4767 t = next_nonnote_insn (first);
4769 if (arm_cirrus_insn_p (t))
4772 if (arm_cirrus_insn_p (next_nonnote_insn (t)))
4776 emit_insn_after (gen_nop (), first);
4781 /* (float (blah)) is in parallel with a clobber. */
4782 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
4783 body = XVECEXP (body, 0, 0);
4785 if (GET_CODE (body) == SET)
4787 rtx lhs = XEXP (body, 0), rhs = XEXP (body, 1);
4789 /* cfldrd, cfldr64, cfstrd, cfstr64 must
4790 be followed by a non Cirrus insn. */
4791 if (get_attr_cirrus (first) == CIRRUS_DOUBLE)
4793 if (arm_cirrus_insn_p (next_nonnote_insn (first)))
4794 emit_insn_after (gen_nop (), first);
4798 else if (arm_memory_load_p (first))
4800 unsigned int arm_regno;
4802 /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr,
4803 ldr/cfmv64hr combination where the Rd field is the same
4804 in both instructions must be split with a non Cirrus
4811 /* Get Arm register number for ldr insn. */
4812 if (GET_CODE (lhs) == REG)
4813 arm_regno = REGNO (lhs);
4814 else if (GET_CODE (rhs) == REG)
4815 arm_regno = REGNO (rhs);
4820 first = next_nonnote_insn (first);
4822 if (! arm_cirrus_insn_p (first))
4825 body = PATTERN (first);
4827 /* (float (blah)) is in parallel with a clobber. */
4828 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0))
4829 body = XVECEXP (body, 0, 0);
4831 if (GET_CODE (body) == FLOAT)
4832 body = XEXP (body, 0);
4834 if (get_attr_cirrus (first) == CIRRUS_MOVE
4835 && GET_CODE (XEXP (body, 1)) == REG
4836 && arm_regno == REGNO (XEXP (body, 1)))
4837 emit_insn_after (gen_nop (), first);
4843 /* get_attr aborts on USE and CLOBBER. */
4845 || GET_CODE (first) != INSN
4846 || GET_CODE (PATTERN (first)) == USE
4847 || GET_CODE (PATTERN (first)) == CLOBBER)
4850 attr = get_attr_cirrus (first);
4852 /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...)
4853 must be followed by a non-coprocessor instruction. */
4854 if (attr == CIRRUS_COMPARE)
4858 t = next_nonnote_insn (first);
4860 if (arm_cirrus_insn_p (t))
4863 if (arm_cirrus_insn_p (next_nonnote_insn (t)))
4867 emit_insn_after (gen_nop (), first);
4873 /* Return nonzero if OP is a constant power of two. */
4875 power_of_two_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
4877 if (GET_CODE (op) == CONST_INT)
4879 HOST_WIDE_INT value = INTVAL (op);
4881 return value != 0 && (value & (value - 1)) == 0;
4887 /* Return TRUE for a valid operand of a DImode operation.
4888 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
4889 Note that this disallows MEM(REG+REG), but allows
4890 MEM(PRE/POST_INC/DEC(REG)). */
4892 di_operand (rtx op, enum machine_mode mode)
4894 if (s_register_operand (op, mode))
4897 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && GET_MODE (op) != DImode)
4900 if (GET_CODE (op) == SUBREG)
4901 op = SUBREG_REG (op);
4903 switch (GET_CODE (op))
4910 return memory_address_p (DImode, XEXP (op, 0));
4917 /* Like di_operand, but don't accept constants. */
4919 nonimmediate_di_operand (rtx op, enum machine_mode mode)
4921 if (s_register_operand (op, mode))
4924 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && GET_MODE (op) != DImode)
4927 if (GET_CODE (op) == SUBREG)
4928 op = SUBREG_REG (op);
4930 if (GET_CODE (op) == MEM)
4931 return memory_address_p (DImode, XEXP (op, 0));
4936 /* Return TRUE for a valid operand of a DFmode operation when soft-float.
4937 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
4938 Note that this disallows MEM(REG+REG), but allows
4939 MEM(PRE/POST_INC/DEC(REG)). */
4941 soft_df_operand (rtx op, enum machine_mode mode)
4943 if (s_register_operand (op, mode))
4946 if (mode != VOIDmode && GET_MODE (op) != mode)
4949 if (GET_CODE (op) == SUBREG && CONSTANT_P (SUBREG_REG (op)))
4952 if (GET_CODE (op) == SUBREG)
4953 op = SUBREG_REG (op);
4955 switch (GET_CODE (op))
4961 return memory_address_p (DFmode, XEXP (op, 0));
4968 /* Like soft_df_operand, but don't accept constants. */
4970 nonimmediate_soft_df_operand (rtx op, enum machine_mode mode)
4972 if (s_register_operand (op, mode))
4975 if (mode != VOIDmode && GET_MODE (op) != mode)
4978 if (GET_CODE (op) == SUBREG)
4979 op = SUBREG_REG (op);
4981 if (GET_CODE (op) == MEM)
4982 return memory_address_p (DFmode, XEXP (op, 0));
4986 /* Return TRUE for valid index operands. */
4988 index_operand (rtx op, enum machine_mode mode)
4990 return (s_register_operand (op, mode)
4991 || (immediate_operand (op, mode)
4992 && (GET_CODE (op) != CONST_INT
4993 || (INTVAL (op) < 4096 && INTVAL (op) > -4096))));
4996 /* Return TRUE for valid shifts by a constant. This also accepts any
4997 power of two on the (somewhat overly relaxed) assumption that the
4998 shift operator in this case was a mult. */
5000 const_shift_operand (rtx op, enum machine_mode mode)
5002 return (power_of_two_operand (op, mode)
5003 || (immediate_operand (op, mode)
5004 && (GET_CODE (op) != CONST_INT
5005 || (INTVAL (op) < 32 && INTVAL (op) > 0))));
5008 /* Return TRUE for arithmetic operators which can be combined with a multiply
5011 shiftable_operator (rtx x, enum machine_mode mode)
5015 if (GET_MODE (x) != mode)
5018 code = GET_CODE (x);
5020 return (code == PLUS || code == MINUS
5021 || code == IOR || code == XOR || code == AND);
5024 /* Return TRUE for binary logical operators. */
5026 logical_binary_operator (rtx x, enum machine_mode mode)
5030 if (GET_MODE (x) != mode)
5033 code = GET_CODE (x);
5035 return (code == IOR || code == XOR || code == AND);
5038 /* Return TRUE for shift operators. */
5040 shift_operator (rtx x,enum machine_mode mode)
5044 if (GET_MODE (x) != mode)
5047 code = GET_CODE (x);
5050 return power_of_two_operand (XEXP (x, 1), mode);
5052 return (code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT
5053 || code == ROTATERT);
5056 /* Return TRUE if x is EQ or NE. */
5058 equality_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
5060 return GET_CODE (x) == EQ || GET_CODE (x) == NE;
5063 /* Return TRUE if x is a comparison operator other than LTGT or UNEQ. */
5065 arm_comparison_operator (rtx x, enum machine_mode mode)
5067 return (comparison_operator (x, mode)
5068 && GET_CODE (x) != LTGT
5069 && GET_CODE (x) != UNEQ);
5072 /* Return TRUE for SMIN SMAX UMIN UMAX operators. */
5074 minmax_operator (rtx x, enum machine_mode mode)
5076 enum rtx_code code = GET_CODE (x);
5078 if (GET_MODE (x) != mode)
5081 return code == SMIN || code == SMAX || code == UMIN || code == UMAX;
5084 /* Return TRUE if this is the condition code register, if we aren't given
5085 a mode, accept any class CCmode register. */
5087 cc_register (rtx x, enum machine_mode mode)
5089 if (mode == VOIDmode)
5091 mode = GET_MODE (x);
5093 if (GET_MODE_CLASS (mode) != MODE_CC)
5097 if ( GET_MODE (x) == mode
5098 && GET_CODE (x) == REG
5099 && REGNO (x) == CC_REGNUM)
5105 /* Return TRUE if this is the condition code register, if we aren't given
5106 a mode, accept any class CCmode register which indicates a dominance
5109 dominant_cc_register (rtx x, enum machine_mode mode)
5111 if (mode == VOIDmode)
5113 mode = GET_MODE (x);
5115 if (GET_MODE_CLASS (mode) != MODE_CC)
5119 if (mode != CC_DNEmode && mode != CC_DEQmode
5120 && mode != CC_DLEmode && mode != CC_DLTmode
5121 && mode != CC_DGEmode && mode != CC_DGTmode
5122 && mode != CC_DLEUmode && mode != CC_DLTUmode
5123 && mode != CC_DGEUmode && mode != CC_DGTUmode)
5126 return cc_register (x, mode);
5129 /* Return TRUE if X references a SYMBOL_REF. */
5131 symbol_mentioned_p (rtx x)
5136 if (GET_CODE (x) == SYMBOL_REF)
5139 fmt = GET_RTX_FORMAT (GET_CODE (x));
5141 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5147 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5148 if (symbol_mentioned_p (XVECEXP (x, i, j)))
5151 else if (fmt[i] == 'e' && symbol_mentioned_p (XEXP (x, i)))
5158 /* Return TRUE if X references a LABEL_REF. */
5160 label_mentioned_p (rtx x)
5165 if (GET_CODE (x) == LABEL_REF)
5168 fmt = GET_RTX_FORMAT (GET_CODE (x));
5169 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
5175 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5176 if (label_mentioned_p (XVECEXP (x, i, j)))
5179 else if (fmt[i] == 'e' && label_mentioned_p (XEXP (x, i)))
5189 enum rtx_code code = GET_CODE (x);
5193 else if (code == SMIN)
5195 else if (code == UMIN)
5197 else if (code == UMAX)
5203 /* Return 1 if memory locations are adjacent. */
5205 adjacent_mem_locations (rtx a, rtx b)
5207 if ((GET_CODE (XEXP (a, 0)) == REG
5208 || (GET_CODE (XEXP (a, 0)) == PLUS
5209 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
5210 && (GET_CODE (XEXP (b, 0)) == REG
5211 || (GET_CODE (XEXP (b, 0)) == PLUS
5212 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
5214 int val0 = 0, val1 = 0;
5217 if (GET_CODE (XEXP (a, 0)) == PLUS)
5219 reg0 = REGNO (XEXP (XEXP (a, 0), 0));
5220 val0 = INTVAL (XEXP (XEXP (a, 0), 1));
5223 reg0 = REGNO (XEXP (a, 0));
5225 if (GET_CODE (XEXP (b, 0)) == PLUS)
5227 reg1 = REGNO (XEXP (XEXP (b, 0), 0));
5228 val1 = INTVAL (XEXP (XEXP (b, 0), 1));
5231 reg1 = REGNO (XEXP (b, 0));
5233 /* Don't accept any offset that will require multiple
5234 instructions to handle, since this would cause the
5235 arith_adjacentmem pattern to output an overlong sequence. */
5236 if (!const_ok_for_op (PLUS, val0) || !const_ok_for_op (PLUS, val1))
5239 return (reg0 == reg1) && ((val1 - val0) == 4 || (val0 - val1) == 4);
5244 /* Return 1 if OP is a load multiple operation. It is known to be
5245 parallel and the first section will be tested. */
5247 load_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
5249 HOST_WIDE_INT count = XVECLEN (op, 0);
5252 HOST_WIDE_INT i = 1, base = 0;
5256 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
5259 /* Check to see if this might be a write-back. */
5260 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
5265 /* Now check it more carefully. */
5266 if (GET_CODE (SET_DEST (elt)) != REG
5267 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
5268 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
5269 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4)
5273 /* Perform a quick check so we don't blow up below. */
5275 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
5276 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != REG
5277 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != MEM)
5280 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, i - 1)));
5281 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, i - 1)), 0);
5283 for (; i < count; i++)
5285 elt = XVECEXP (op, 0, i);
5287 if (GET_CODE (elt) != SET
5288 || GET_CODE (SET_DEST (elt)) != REG
5289 || GET_MODE (SET_DEST (elt)) != SImode
5290 || REGNO (SET_DEST (elt)) != (unsigned int)(dest_regno + i - base)
5291 || GET_CODE (SET_SRC (elt)) != MEM
5292 || GET_MODE (SET_SRC (elt)) != SImode
5293 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
5294 || !rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
5295 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
5296 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != (i - base) * 4)
5303 /* Return 1 if OP is a store multiple operation. It is known to be
5304 parallel and the first section will be tested. */
5306 store_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
5308 HOST_WIDE_INT count = XVECLEN (op, 0);
5311 HOST_WIDE_INT i = 1, base = 0;
5315 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
5318 /* Check to see if this might be a write-back. */
5319 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
5324 /* Now check it more carefully. */
5325 if (GET_CODE (SET_DEST (elt)) != REG
5326 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
5327 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
5328 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4)
5332 /* Perform a quick check so we don't blow up below. */
5334 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
5335 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != MEM
5336 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != REG)
5339 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, i - 1)));
5340 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, i - 1)), 0);
5342 for (; i < count; i++)
5344 elt = XVECEXP (op, 0, i);
5346 if (GET_CODE (elt) != SET
5347 || GET_CODE (SET_SRC (elt)) != REG
5348 || GET_MODE (SET_SRC (elt)) != SImode
5349 || REGNO (SET_SRC (elt)) != (unsigned int)(src_regno + i - base)
5350 || GET_CODE (SET_DEST (elt)) != MEM
5351 || GET_MODE (SET_DEST (elt)) != SImode
5352 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
5353 || !rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
5354 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
5355 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != (i - base) * 4)
5363 load_multiple_sequence (rtx *operands, int nops, int *regs, int *base,
5364 HOST_WIDE_INT *load_offset)
5366 int unsorted_regs[4];
5367 HOST_WIDE_INT unsorted_offsets[4];
5372 /* Can only handle 2, 3, or 4 insns at present,
5373 though could be easily extended if required. */
5374 if (nops < 2 || nops > 4)
5377 /* Loop over the operands and check that the memory references are
5378 suitable (ie immediate offsets from the same base register). At
5379 the same time, extract the target register, and the memory
5381 for (i = 0; i < nops; i++)
5386 /* Convert a subreg of a mem into the mem itself. */
5387 if (GET_CODE (operands[nops + i]) == SUBREG)
5388 operands[nops + i] = alter_subreg (operands + (nops + i));
5390 if (GET_CODE (operands[nops + i]) != MEM)
5393 /* Don't reorder volatile memory references; it doesn't seem worth
5394 looking for the case where the order is ok anyway. */
5395 if (MEM_VOLATILE_P (operands[nops + i]))
5398 offset = const0_rtx;
5400 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
5401 || (GET_CODE (reg) == SUBREG
5402 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
5403 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
5404 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
5406 || (GET_CODE (reg) == SUBREG
5407 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
5408 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
5413 base_reg = REGNO (reg);
5414 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
5415 ? REGNO (operands[i])
5416 : REGNO (SUBREG_REG (operands[i])));
5421 if (base_reg != (int) REGNO (reg))
5422 /* Not addressed from the same base register. */
5425 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
5426 ? REGNO (operands[i])
5427 : REGNO (SUBREG_REG (operands[i])));
5428 if (unsorted_regs[i] < unsorted_regs[order[0]])
5432 /* If it isn't an integer register, or if it overwrites the
5433 base register but isn't the last insn in the list, then
5434 we can't do this. */
5435 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14
5436 || (i != nops - 1 && unsorted_regs[i] == base_reg))
5439 unsorted_offsets[i] = INTVAL (offset);
5442 /* Not a suitable memory address. */
5446 /* All the useful information has now been extracted from the
5447 operands into unsorted_regs and unsorted_offsets; additionally,
5448 order[0] has been set to the lowest numbered register in the
5449 list. Sort the registers into order, and check that the memory
5450 offsets are ascending and adjacent. */
5452 for (i = 1; i < nops; i++)
5456 order[i] = order[i - 1];
5457 for (j = 0; j < nops; j++)
5458 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
5459 && (order[i] == order[i - 1]
5460 || unsorted_regs[j] < unsorted_regs[order[i]]))
5463 /* Have we found a suitable register? if not, one must be used more
5465 if (order[i] == order[i - 1])
5468 /* Is the memory address adjacent and ascending? */
5469 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
5477 for (i = 0; i < nops; i++)
5478 regs[i] = unsorted_regs[order[i]];
5480 *load_offset = unsorted_offsets[order[0]];
5483 if (unsorted_offsets[order[0]] == 0)
5484 return 1; /* ldmia */
5486 if (unsorted_offsets[order[0]] == 4)
5487 return 2; /* ldmib */
5489 if (unsorted_offsets[order[nops - 1]] == 0)
5490 return 3; /* ldmda */
5492 if (unsorted_offsets[order[nops - 1]] == -4)
5493 return 4; /* ldmdb */
5495 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
5496 if the offset isn't small enough. The reason 2 ldrs are faster
5497 is because these ARMs are able to do more than one cache access
5498 in a single cycle. The ARM9 and StrongARM have Harvard caches,
5499 whilst the ARM8 has a double bandwidth cache. This means that
5500 these cores can do both an instruction fetch and a data fetch in
5501 a single cycle, so the trick of calculating the address into a
5502 scratch register (one of the result regs) and then doing a load
5503 multiple actually becomes slower (and no smaller in code size).
5504 That is the transformation
5506 ldr rd1, [rbase + offset]
5507 ldr rd2, [rbase + offset + 4]
5511 add rd1, rbase, offset
5512 ldmia rd1, {rd1, rd2}
5514 produces worse code -- '3 cycles + any stalls on rd2' instead of
5515 '2 cycles + any stalls on rd2'. On ARMs with only one cache
5516 access per cycle, the first sequence could never complete in less
5517 than 6 cycles, whereas the ldm sequence would only take 5 and
5518 would make better use of sequential accesses if not hitting the
5521 We cheat here and test 'arm_ld_sched' which we currently know to
5522 only be true for the ARM8, ARM9 and StrongARM. If this ever
5523 changes, then the test below needs to be reworked. */
5524 if (nops == 2 && arm_ld_sched)
5527 /* Can't do it without setting up the offset, only do this if it takes
5528 no more than one insn. */
5529 return (const_ok_for_arm (unsorted_offsets[order[0]])
5530 || const_ok_for_arm (-unsorted_offsets[order[0]])) ? 5 : 0;
5534 emit_ldm_seq (rtx *operands, int nops)
5538 HOST_WIDE_INT offset;
5542 switch (load_multiple_sequence (operands, nops, regs, &base_reg, &offset))
5545 strcpy (buf, "ldm%?ia\t");
5549 strcpy (buf, "ldm%?ib\t");
5553 strcpy (buf, "ldm%?da\t");
5557 strcpy (buf, "ldm%?db\t");
5562 sprintf (buf, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
5563 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
5566 sprintf (buf, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
5567 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
5569 output_asm_insn (buf, operands);
5571 strcpy (buf, "ldm%?ia\t");
5578 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
5579 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
5581 for (i = 1; i < nops; i++)
5582 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
5583 reg_names[regs[i]]);
5585 strcat (buf, "}\t%@ phole ldm");
5587 output_asm_insn (buf, operands);
5592 store_multiple_sequence (rtx *operands, int nops, int *regs, int *base,
5593 HOST_WIDE_INT * load_offset)
5595 int unsorted_regs[4];
5596 HOST_WIDE_INT unsorted_offsets[4];
5601 /* Can only handle 2, 3, or 4 insns at present, though could be easily
5602 extended if required. */
5603 if (nops < 2 || nops > 4)
5606 /* Loop over the operands and check that the memory references are
5607 suitable (ie immediate offsets from the same base register). At
5608 the same time, extract the target register, and the memory
5610 for (i = 0; i < nops; i++)
5615 /* Convert a subreg of a mem into the mem itself. */
5616 if (GET_CODE (operands[nops + i]) == SUBREG)
5617 operands[nops + i] = alter_subreg (operands + (nops + i));
5619 if (GET_CODE (operands[nops + i]) != MEM)
5622 /* Don't reorder volatile memory references; it doesn't seem worth
5623 looking for the case where the order is ok anyway. */
5624 if (MEM_VOLATILE_P (operands[nops + i]))
5627 offset = const0_rtx;
5629 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
5630 || (GET_CODE (reg) == SUBREG
5631 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
5632 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
5633 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
5635 || (GET_CODE (reg) == SUBREG
5636 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
5637 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
5642 base_reg = REGNO (reg);
5643 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
5644 ? REGNO (operands[i])
5645 : REGNO (SUBREG_REG (operands[i])));
5650 if (base_reg != (int) REGNO (reg))
5651 /* Not addressed from the same base register. */
5654 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
5655 ? REGNO (operands[i])
5656 : REGNO (SUBREG_REG (operands[i])));
5657 if (unsorted_regs[i] < unsorted_regs[order[0]])
5661 /* If it isn't an integer register, then we can't do this. */
5662 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14)
5665 unsorted_offsets[i] = INTVAL (offset);
5668 /* Not a suitable memory address. */
5672 /* All the useful information has now been extracted from the
5673 operands into unsorted_regs and unsorted_offsets; additionally,
5674 order[0] has been set to the lowest numbered register in the
5675 list. Sort the registers into order, and check that the memory
5676 offsets are ascending and adjacent. */
5678 for (i = 1; i < nops; i++)
5682 order[i] = order[i - 1];
5683 for (j = 0; j < nops; j++)
5684 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
5685 && (order[i] == order[i - 1]
5686 || unsorted_regs[j] < unsorted_regs[order[i]]))
5689 /* Have we found a suitable register? if not, one must be used more
5691 if (order[i] == order[i - 1])
5694 /* Is the memory address adjacent and ascending? */
5695 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
5703 for (i = 0; i < nops; i++)
5704 regs[i] = unsorted_regs[order[i]];
5706 *load_offset = unsorted_offsets[order[0]];
5709 if (unsorted_offsets[order[0]] == 0)
5710 return 1; /* stmia */
5712 if (unsorted_offsets[order[0]] == 4)
5713 return 2; /* stmib */
5715 if (unsorted_offsets[order[nops - 1]] == 0)
5716 return 3; /* stmda */
5718 if (unsorted_offsets[order[nops - 1]] == -4)
5719 return 4; /* stmdb */
5725 emit_stm_seq (rtx *operands, int nops)
5729 HOST_WIDE_INT offset;
5733 switch (store_multiple_sequence (operands, nops, regs, &base_reg, &offset))
5736 strcpy (buf, "stm%?ia\t");
5740 strcpy (buf, "stm%?ib\t");
5744 strcpy (buf, "stm%?da\t");
5748 strcpy (buf, "stm%?db\t");
5755 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
5756 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
5758 for (i = 1; i < nops; i++)
5759 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
5760 reg_names[regs[i]]);
5762 strcat (buf, "}\t%@ phole stm");
5764 output_asm_insn (buf, operands);
5769 multi_register_push (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
5771 if (GET_CODE (op) != PARALLEL
5772 || (GET_CODE (XVECEXP (op, 0, 0)) != SET)
5773 || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC)
5774 || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPEC_PUSH_MULT))
5780 /* Routines for use in generating RTL. */
5783 arm_gen_load_multiple (int base_regno, int count, rtx from, int up,
5784 int write_back, int unchanging_p, int in_struct_p,
5789 int sign = up ? 1 : -1;
5792 /* XScale has load-store double instructions, but they have stricter
5793 alignment requirements than load-store multiple, so we can not
5796 For XScale ldm requires 2 + NREGS cycles to complete and blocks
5797 the pipeline until completion.
5805 An ldr instruction takes 1-3 cycles, but does not block the
5814 Best case ldr will always win. However, the more ldr instructions
5815 we issue, the less likely we are to be able to schedule them well.
5816 Using ldr instructions also increases code size.
5818 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
5819 for counts of 3 or 4 regs. */
5820 if (arm_tune_xscale && count <= 2 && ! optimize_size)
5826 for (i = 0; i < count; i++)
5828 mem = gen_rtx_MEM (SImode, plus_constant (from, i * 4 * sign));
5829 RTX_UNCHANGING_P (mem) = unchanging_p;
5830 MEM_IN_STRUCT_P (mem) = in_struct_p;
5831 MEM_SCALAR_P (mem) = scalar_p;
5832 emit_move_insn (gen_rtx_REG (SImode, base_regno + i), mem);
5836 emit_move_insn (from, plus_constant (from, count * 4 * sign));
5844 result = gen_rtx_PARALLEL (VOIDmode,
5845 rtvec_alloc (count + (write_back ? 1 : 0)));
5848 XVECEXP (result, 0, 0)
5849 = gen_rtx_SET (GET_MODE (from), from,
5850 plus_constant (from, count * 4 * sign));
5855 for (j = 0; i < count; i++, j++)
5857 mem = gen_rtx_MEM (SImode, plus_constant (from, j * 4 * sign));
5858 RTX_UNCHANGING_P (mem) = unchanging_p;
5859 MEM_IN_STRUCT_P (mem) = in_struct_p;
5860 MEM_SCALAR_P (mem) = scalar_p;
5861 XVECEXP (result, 0, i)
5862 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, base_regno + j), mem);
5869 arm_gen_store_multiple (int base_regno, int count, rtx to, int up,
5870 int write_back, int unchanging_p, int in_struct_p,
5875 int sign = up ? 1 : -1;
5878 /* See arm_gen_load_multiple for discussion of
5879 the pros/cons of ldm/stm usage for XScale. */
5880 if (arm_tune_xscale && count <= 2 && ! optimize_size)
5886 for (i = 0; i < count; i++)
5888 mem = gen_rtx_MEM (SImode, plus_constant (to, i * 4 * sign));
5889 RTX_UNCHANGING_P (mem) = unchanging_p;
5890 MEM_IN_STRUCT_P (mem) = in_struct_p;
5891 MEM_SCALAR_P (mem) = scalar_p;
5892 emit_move_insn (mem, gen_rtx_REG (SImode, base_regno + i));
5896 emit_move_insn (to, plus_constant (to, count * 4 * sign));
5904 result = gen_rtx_PARALLEL (VOIDmode,
5905 rtvec_alloc (count + (write_back ? 1 : 0)));
5908 XVECEXP (result, 0, 0)
5909 = gen_rtx_SET (GET_MODE (to), to,
5910 plus_constant (to, count * 4 * sign));
5915 for (j = 0; i < count; i++, j++)
5917 mem = gen_rtx_MEM (SImode, plus_constant (to, j * 4 * sign));
5918 RTX_UNCHANGING_P (mem) = unchanging_p;
5919 MEM_IN_STRUCT_P (mem) = in_struct_p;
5920 MEM_SCALAR_P (mem) = scalar_p;
5922 XVECEXP (result, 0, i)
5923 = gen_rtx_SET (VOIDmode, mem, gen_rtx_REG (SImode, base_regno + j));
5930 arm_gen_movstrqi (rtx *operands)
5932 HOST_WIDE_INT in_words_to_go, out_words_to_go, last_bytes;
5935 rtx st_src, st_dst, fin_src, fin_dst;
5936 rtx part_bytes_reg = NULL;
5938 int dst_unchanging_p, dst_in_struct_p, src_unchanging_p, src_in_struct_p;
5939 int dst_scalar_p, src_scalar_p;
5941 if (GET_CODE (operands[2]) != CONST_INT
5942 || GET_CODE (operands[3]) != CONST_INT
5943 || INTVAL (operands[2]) > 64
5944 || INTVAL (operands[3]) & 3)
5947 st_dst = XEXP (operands[0], 0);
5948 st_src = XEXP (operands[1], 0);
5950 dst_unchanging_p = RTX_UNCHANGING_P (operands[0]);
5951 dst_in_struct_p = MEM_IN_STRUCT_P (operands[0]);
5952 dst_scalar_p = MEM_SCALAR_P (operands[0]);
5953 src_unchanging_p = RTX_UNCHANGING_P (operands[1]);
5954 src_in_struct_p = MEM_IN_STRUCT_P (operands[1]);
5955 src_scalar_p = MEM_SCALAR_P (operands[1]);
5957 fin_dst = dst = copy_to_mode_reg (SImode, st_dst);
5958 fin_src = src = copy_to_mode_reg (SImode, st_src);
5960 in_words_to_go = ARM_NUM_INTS (INTVAL (operands[2]));
5961 out_words_to_go = INTVAL (operands[2]) / 4;
5962 last_bytes = INTVAL (operands[2]) & 3;
5964 if (out_words_to_go != in_words_to_go && ((in_words_to_go - 1) & 3) != 0)
5965 part_bytes_reg = gen_rtx_REG (SImode, (in_words_to_go - 1) & 3);
5967 for (i = 0; in_words_to_go >= 2; i+=4)
5969 if (in_words_to_go > 4)
5970 emit_insn (arm_gen_load_multiple (0, 4, src, TRUE, TRUE,
5975 emit_insn (arm_gen_load_multiple (0, in_words_to_go, src, TRUE,
5976 FALSE, src_unchanging_p,
5977 src_in_struct_p, src_scalar_p));
5979 if (out_words_to_go)
5981 if (out_words_to_go > 4)
5982 emit_insn (arm_gen_store_multiple (0, 4, dst, TRUE, TRUE,
5986 else if (out_words_to_go != 1)
5987 emit_insn (arm_gen_store_multiple (0, out_words_to_go,
5996 mem = gen_rtx_MEM (SImode, dst);
5997 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
5998 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
5999 MEM_SCALAR_P (mem) = dst_scalar_p;
6000 emit_move_insn (mem, gen_rtx_REG (SImode, 0));
6001 if (last_bytes != 0)
6002 emit_insn (gen_addsi3 (dst, dst, GEN_INT (4)));
6006 in_words_to_go -= in_words_to_go < 4 ? in_words_to_go : 4;
6007 out_words_to_go -= out_words_to_go < 4 ? out_words_to_go : 4;
6010 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
6011 if (out_words_to_go)
6015 mem = gen_rtx_MEM (SImode, src);
6016 RTX_UNCHANGING_P (mem) = src_unchanging_p;
6017 MEM_IN_STRUCT_P (mem) = src_in_struct_p;
6018 MEM_SCALAR_P (mem) = src_scalar_p;
6019 emit_move_insn (sreg = gen_reg_rtx (SImode), mem);
6020 emit_move_insn (fin_src = gen_reg_rtx (SImode), plus_constant (src, 4));
6022 mem = gen_rtx_MEM (SImode, dst);
6023 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
6024 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
6025 MEM_SCALAR_P (mem) = dst_scalar_p;
6026 emit_move_insn (mem, sreg);
6027 emit_move_insn (fin_dst = gen_reg_rtx (SImode), plus_constant (dst, 4));
6030 if (in_words_to_go) /* Sanity check */
6036 if (in_words_to_go < 0)
6039 mem = gen_rtx_MEM (SImode, src);
6040 RTX_UNCHANGING_P (mem) = src_unchanging_p;
6041 MEM_IN_STRUCT_P (mem) = src_in_struct_p;
6042 MEM_SCALAR_P (mem) = src_scalar_p;
6043 part_bytes_reg = copy_to_mode_reg (SImode, mem);
6046 if (last_bytes && part_bytes_reg == NULL)
6049 if (BYTES_BIG_ENDIAN && last_bytes)
6051 rtx tmp = gen_reg_rtx (SImode);
6053 /* The bytes we want are in the top end of the word. */
6054 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg,
6055 GEN_INT (8 * (4 - last_bytes))));
6056 part_bytes_reg = tmp;
6060 mem = gen_rtx_MEM (QImode, plus_constant (dst, last_bytes - 1));
6061 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
6062 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
6063 MEM_SCALAR_P (mem) = dst_scalar_p;
6064 emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
6068 tmp = gen_reg_rtx (SImode);
6069 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8)));
6070 part_bytes_reg = tmp;
6079 mem = gen_rtx_MEM (HImode, dst);
6080 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
6081 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
6082 MEM_SCALAR_P (mem) = dst_scalar_p;
6083 emit_move_insn (mem, gen_lowpart (HImode, part_bytes_reg));
6087 rtx tmp = gen_reg_rtx (SImode);
6089 emit_insn (gen_addsi3 (dst, dst, const2_rtx));
6090 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (16)));
6091 part_bytes_reg = tmp;
6097 mem = gen_rtx_MEM (QImode, dst);
6098 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
6099 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
6100 MEM_SCALAR_P (mem) = dst_scalar_p;
6101 emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
6108 /* Generate a memory reference for a half word, such that it will be loaded
6109 into the top 16 bits of the word. We can assume that the address is
6110 known to be alignable and of the form reg, or plus (reg, const). */
6113 arm_gen_rotated_half_load (rtx memref)
6115 HOST_WIDE_INT offset = 0;
6116 rtx base = XEXP (memref, 0);
6118 if (GET_CODE (base) == PLUS)
6120 offset = INTVAL (XEXP (base, 1));
6121 base = XEXP (base, 0);
6124 /* If we aren't allowed to generate unaligned addresses, then fail. */
6125 if (TARGET_MMU_TRAPS
6126 && ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 0)))
6129 base = gen_rtx_MEM (SImode, plus_constant (base, offset & ~2));
6131 if ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 2))
6134 return gen_rtx_ROTATE (SImode, base, GEN_INT (16));
6137 /* Select a dominance comparison mode if possible for a test of the general
6138 form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms.
6139 COND_OR == DOM_CC_X_AND_Y => (X && Y)
6140 COND_OR == DOM_CC_NX_OR_Y => ((! X) || Y)
6141 COND_OR == DOM_CC_X_OR_Y => (X || Y)
6142 In all cases OP will be either EQ or NE, but we don't need to know which
6143 here. If we are unable to support a dominance comparison we return
6144 CC mode. This will then fail to match for the RTL expressions that
6145 generate this call. */
6147 arm_select_dominance_cc_mode (rtx x, rtx y, HOST_WIDE_INT cond_or)
6149 enum rtx_code cond1, cond2;
6152 /* Currently we will probably get the wrong result if the individual
6153 comparisons are not simple. This also ensures that it is safe to
6154 reverse a comparison if necessary. */
6155 if ((arm_select_cc_mode (cond1 = GET_CODE (x), XEXP (x, 0), XEXP (x, 1))
6157 || (arm_select_cc_mode (cond2 = GET_CODE (y), XEXP (y, 0), XEXP (y, 1))
6161 /* The if_then_else variant of this tests the second condition if the
6162 first passes, but is true if the first fails. Reverse the first
6163 condition to get a true "inclusive-or" expression. */
6164 if (cond_or == DOM_CC_NX_OR_Y)
6165 cond1 = reverse_condition (cond1);
6167 /* If the comparisons are not equal, and one doesn't dominate the other,
6168 then we can't do this. */
6170 && !comparison_dominates_p (cond1, cond2)
6171 && (swapped = 1, !comparison_dominates_p (cond2, cond1)))
6176 enum rtx_code temp = cond1;
6184 if (cond2 == EQ || cond_or == DOM_CC_X_AND_Y)
6189 case LE: return CC_DLEmode;
6190 case LEU: return CC_DLEUmode;
6191 case GE: return CC_DGEmode;
6192 case GEU: return CC_DGEUmode;
6199 if (cond2 == LT || cond_or == DOM_CC_X_AND_Y)
6208 if (cond2 == GT || cond_or == DOM_CC_X_AND_Y)
6217 if (cond2 == LTU || cond_or == DOM_CC_X_AND_Y)
6226 if (cond2 == GTU || cond_or == DOM_CC_X_AND_Y)
6234 /* The remaining cases only occur when both comparisons are the
6259 arm_select_cc_mode (enum rtx_code op, rtx x, rtx y)
6261 /* All floating point compares return CCFP if it is an equality
6262 comparison, and CCFPE otherwise. */
6263 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
6283 if (TARGET_HARD_FLOAT && TARGET_MAVERICK)
6292 /* A compare with a shifted operand. Because of canonicalization, the
6293 comparison will have to be swapped when we emit the assembler. */
6294 if (GET_MODE (y) == SImode && GET_CODE (y) == REG
6295 && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
6296 || GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE
6297 || GET_CODE (x) == ROTATERT))
6300 /* This is a special case that is used by combine to allow a
6301 comparison of a shifted byte load to be split into a zero-extend
6302 followed by a comparison of the shifted integer (only valid for
6303 equalities and unsigned inequalities). */
6304 if (GET_MODE (x) == SImode
6305 && GET_CODE (x) == ASHIFT
6306 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 24
6307 && GET_CODE (XEXP (x, 0)) == SUBREG
6308 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == MEM
6309 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == QImode
6310 && (op == EQ || op == NE
6311 || op == GEU || op == GTU || op == LTU || op == LEU)
6312 && GET_CODE (y) == CONST_INT)
6315 /* A construct for a conditional compare, if the false arm contains
6316 0, then both conditions must be true, otherwise either condition
6317 must be true. Not all conditions are possible, so CCmode is
6318 returned if it can't be done. */
6319 if (GET_CODE (x) == IF_THEN_ELSE
6320 && (XEXP (x, 2) == const0_rtx
6321 || XEXP (x, 2) == const1_rtx)
6322 && COMPARISON_P (XEXP (x, 0))
6323 && COMPARISON_P (XEXP (x, 1)))
6324 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
6325 INTVAL (XEXP (x, 2)));
6327 /* Alternate canonicalizations of the above. These are somewhat cleaner. */
6328 if (GET_CODE (x) == AND
6329 && COMPARISON_P (XEXP (x, 0))
6330 && COMPARISON_P (XEXP (x, 1)))
6331 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
6334 if (GET_CODE (x) == IOR
6335 && COMPARISON_P (XEXP (x, 0))
6336 && COMPARISON_P (XEXP (x, 1)))
6337 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
6340 /* An operation (on Thumb) where we want to test for a single bit.
6341 This is done by shifting that bit up into the top bit of a
6342 scratch register; we can then branch on the sign bit. */
6344 && GET_MODE (x) == SImode
6345 && (op == EQ || op == NE)
6346 && (GET_CODE (x) == ZERO_EXTRACT))
6349 /* An operation that sets the condition codes as a side-effect, the
6350 V flag is not set correctly, so we can only use comparisons where
6351 this doesn't matter. (For LT and GE we can use "mi" and "pl"
6353 if (GET_MODE (x) == SImode
6355 && (op == EQ || op == NE || op == LT || op == GE)
6356 && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
6357 || GET_CODE (x) == AND || GET_CODE (x) == IOR
6358 || GET_CODE (x) == XOR || GET_CODE (x) == MULT
6359 || GET_CODE (x) == NOT || GET_CODE (x) == NEG
6360 || GET_CODE (x) == LSHIFTRT
6361 || GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
6362 || GET_CODE (x) == ROTATERT
6363 || (TARGET_ARM && GET_CODE (x) == ZERO_EXTRACT)))
6366 if (GET_MODE (x) == QImode && (op == EQ || op == NE))
6369 if (GET_MODE (x) == SImode && (op == LTU || op == GEU)
6370 && GET_CODE (x) == PLUS
6371 && (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y)))
6377 /* X and Y are two things to compare using CODE. Emit the compare insn and
6378 return the rtx for register 0 in the proper mode. FP means this is a
6379 floating point compare: I don't think that it is needed on the arm. */
6381 arm_gen_compare_reg (enum rtx_code code, rtx x, rtx y)
6383 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
6384 rtx cc_reg = gen_rtx_REG (mode, CC_REGNUM);
6386 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
6387 gen_rtx_COMPARE (mode, x, y)));
6392 /* Generate a sequence of insns that will generate the correct return
6393 address mask depending on the physical architecture that the program
6396 arm_gen_return_addr_mask (void)
6398 rtx reg = gen_reg_rtx (Pmode);
6400 emit_insn (gen_return_addr_mask (reg));
6405 arm_reload_in_hi (rtx *operands)
6407 rtx ref = operands[1];
6409 HOST_WIDE_INT offset = 0;
6411 if (GET_CODE (ref) == SUBREG)
6413 offset = SUBREG_BYTE (ref);
6414 ref = SUBREG_REG (ref);
6417 if (GET_CODE (ref) == REG)
6419 /* We have a pseudo which has been spilt onto the stack; there
6420 are two cases here: the first where there is a simple
6421 stack-slot replacement and a second where the stack-slot is
6422 out of range, or is used as a subreg. */
6423 if (reg_equiv_mem[REGNO (ref)])
6425 ref = reg_equiv_mem[REGNO (ref)];
6426 base = find_replacement (&XEXP (ref, 0));
6429 /* The slot is out of range, or was dressed up in a SUBREG. */
6430 base = reg_equiv_address[REGNO (ref)];
6433 base = find_replacement (&XEXP (ref, 0));
6435 /* Handle the case where the address is too complex to be offset by 1. */
6436 if (GET_CODE (base) == MINUS
6437 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
6439 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6441 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
6444 else if (GET_CODE (base) == PLUS)
6446 /* The addend must be CONST_INT, or we would have dealt with it above. */
6447 HOST_WIDE_INT hi, lo;
6449 offset += INTVAL (XEXP (base, 1));
6450 base = XEXP (base, 0);
6452 /* Rework the address into a legal sequence of insns. */
6453 /* Valid range for lo is -4095 -> 4095 */
6456 : -((-offset) & 0xfff));
6458 /* Corner case, if lo is the max offset then we would be out of range
6459 once we have added the additional 1 below, so bump the msb into the
6460 pre-loading insn(s). */
6464 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff)
6465 ^ (HOST_WIDE_INT) 0x80000000)
6466 - (HOST_WIDE_INT) 0x80000000);
6468 if (hi + lo != offset)
6473 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6475 /* Get the base address; addsi3 knows how to handle constants
6476 that require more than one insn. */
6477 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
6483 /* Operands[2] may overlap operands[0] (though it won't overlap
6484 operands[1]), that's why we asked for a DImode reg -- so we can
6485 use the bit that does not overlap. */
6486 if (REGNO (operands[2]) == REGNO (operands[0]))
6487 scratch = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6489 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
6491 emit_insn (gen_zero_extendqisi2 (scratch,
6492 gen_rtx_MEM (QImode,
6493 plus_constant (base,
6495 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode, operands[0], 0),
6496 gen_rtx_MEM (QImode,
6497 plus_constant (base,
6499 if (!BYTES_BIG_ENDIAN)
6500 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
6501 gen_rtx_IOR (SImode,
6504 gen_rtx_SUBREG (SImode, operands[0], 0),
6508 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
6509 gen_rtx_IOR (SImode,
6510 gen_rtx_ASHIFT (SImode, scratch,
6512 gen_rtx_SUBREG (SImode, operands[0],
6516 /* Handle storing a half-word to memory during reload by synthesizing as two
6517 byte stores. Take care not to clobber the input values until after we
6518 have moved them somewhere safe. This code assumes that if the DImode
6519 scratch in operands[2] overlaps either the input value or output address
6520 in some way, then that value must die in this insn (we absolutely need
6521 two scratch registers for some corner cases). */
6523 arm_reload_out_hi (rtx *operands)
6525 rtx ref = operands[0];
6526 rtx outval = operands[1];
6528 HOST_WIDE_INT offset = 0;
6530 if (GET_CODE (ref) == SUBREG)
6532 offset = SUBREG_BYTE (ref);
6533 ref = SUBREG_REG (ref);
6536 if (GET_CODE (ref) == REG)
6538 /* We have a pseudo which has been spilt onto the stack; there
6539 are two cases here: the first where there is a simple
6540 stack-slot replacement and a second where the stack-slot is
6541 out of range, or is used as a subreg. */
6542 if (reg_equiv_mem[REGNO (ref)])
6544 ref = reg_equiv_mem[REGNO (ref)];
6545 base = find_replacement (&XEXP (ref, 0));
6548 /* The slot is out of range, or was dressed up in a SUBREG. */
6549 base = reg_equiv_address[REGNO (ref)];
6552 base = find_replacement (&XEXP (ref, 0));
6554 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
6556 /* Handle the case where the address is too complex to be offset by 1. */
6557 if (GET_CODE (base) == MINUS
6558 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
6560 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6562 /* Be careful not to destroy OUTVAL. */
6563 if (reg_overlap_mentioned_p (base_plus, outval))
6565 /* Updating base_plus might destroy outval, see if we can
6566 swap the scratch and base_plus. */
6567 if (!reg_overlap_mentioned_p (scratch, outval))
6570 scratch = base_plus;
6575 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
6577 /* Be conservative and copy OUTVAL into the scratch now,
6578 this should only be necessary if outval is a subreg
6579 of something larger than a word. */
6580 /* XXX Might this clobber base? I can't see how it can,
6581 since scratch is known to overlap with OUTVAL, and
6582 must be wider than a word. */
6583 emit_insn (gen_movhi (scratch_hi, outval));
6584 outval = scratch_hi;
6588 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
6591 else if (GET_CODE (base) == PLUS)
6593 /* The addend must be CONST_INT, or we would have dealt with it above. */
6594 HOST_WIDE_INT hi, lo;
6596 offset += INTVAL (XEXP (base, 1));
6597 base = XEXP (base, 0);
6599 /* Rework the address into a legal sequence of insns. */
6600 /* Valid range for lo is -4095 -> 4095 */
6603 : -((-offset) & 0xfff));
6605 /* Corner case, if lo is the max offset then we would be out of range
6606 once we have added the additional 1 below, so bump the msb into the
6607 pre-loading insn(s). */
6611 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff)
6612 ^ (HOST_WIDE_INT) 0x80000000)
6613 - (HOST_WIDE_INT) 0x80000000);
6615 if (hi + lo != offset)
6620 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
6622 /* Be careful not to destroy OUTVAL. */
6623 if (reg_overlap_mentioned_p (base_plus, outval))
6625 /* Updating base_plus might destroy outval, see if we
6626 can swap the scratch and base_plus. */
6627 if (!reg_overlap_mentioned_p (scratch, outval))
6630 scratch = base_plus;
6635 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
6637 /* Be conservative and copy outval into scratch now,
6638 this should only be necessary if outval is a
6639 subreg of something larger than a word. */
6640 /* XXX Might this clobber base? I can't see how it
6641 can, since scratch is known to overlap with
6643 emit_insn (gen_movhi (scratch_hi, outval));
6644 outval = scratch_hi;
6648 /* Get the base address; addsi3 knows how to handle constants
6649 that require more than one insn. */
6650 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
6656 if (BYTES_BIG_ENDIAN)
6658 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
6659 plus_constant (base, offset + 1)),
6660 gen_lowpart (QImode, outval)));
6661 emit_insn (gen_lshrsi3 (scratch,
6662 gen_rtx_SUBREG (SImode, outval, 0),
6664 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
6665 gen_lowpart (QImode, scratch)));
6669 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
6670 gen_lowpart (QImode, outval)));
6671 emit_insn (gen_lshrsi3 (scratch,
6672 gen_rtx_SUBREG (SImode, outval, 0),
6674 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
6675 plus_constant (base, offset + 1)),
6676 gen_lowpart (QImode, scratch)));
6680 /* Print a symbolic form of X to the debug file, F. */
6682 arm_print_value (FILE *f, rtx x)
6684 switch (GET_CODE (x))
6687 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (x));
6691 fprintf (f, "<0x%lx,0x%lx>", (long)XWINT (x, 2), (long)XWINT (x, 3));
6699 for (i = 0; i < CONST_VECTOR_NUNITS (x); i++)
6701 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (CONST_VECTOR_ELT (x, i)));
6702 if (i < (CONST_VECTOR_NUNITS (x) - 1))
6710 fprintf (f, "\"%s\"", XSTR (x, 0));
6714 fprintf (f, "`%s'", XSTR (x, 0));
6718 fprintf (f, "L%d", INSN_UID (XEXP (x, 0)));
6722 arm_print_value (f, XEXP (x, 0));
6726 arm_print_value (f, XEXP (x, 0));
6728 arm_print_value (f, XEXP (x, 1));
6736 fprintf (f, "????");
6741 /* Routines for manipulation of the constant pool. */
6743 /* Arm instructions cannot load a large constant directly into a
6744 register; they have to come from a pc relative load. The constant
6745 must therefore be placed in the addressable range of the pc
6746 relative load. Depending on the precise pc relative load
6747 instruction the range is somewhere between 256 bytes and 4k. This
6748 means that we often have to dump a constant inside a function, and
6749 generate code to branch around it.
6751 It is important to minimize this, since the branches will slow
6752 things down and make the code larger.
6754 Normally we can hide the table after an existing unconditional
6755 branch so that there is no interruption of the flow, but in the
6756 worst case the code looks like this:
6774 We fix this by performing a scan after scheduling, which notices
6775 which instructions need to have their operands fetched from the
6776 constant table and builds the table.
6778 The algorithm starts by building a table of all the constants that
6779 need fixing up and all the natural barriers in the function (places
6780 where a constant table can be dropped without breaking the flow).
6781 For each fixup we note how far the pc-relative replacement will be
6782 able to reach and the offset of the instruction into the function.
6784 Having built the table we then group the fixes together to form
6785 tables that are as large as possible (subject to addressing
6786 constraints) and emit each table of constants after the last
6787 barrier that is within range of all the instructions in the group.
6788 If a group does not contain a barrier, then we forcibly create one
6789 by inserting a jump instruction into the flow. Once the table has
6790 been inserted, the insns are then modified to reference the
6791 relevant entry in the pool.
6793 Possible enhancements to the algorithm (not implemented) are:
6795 1) For some processors and object formats, there may be benefit in
6796 aligning the pools to the start of cache lines; this alignment
6797 would need to be taken into account when calculating addressability
6800 /* These typedefs are located at the start of this file, so that
6801 they can be used in the prototypes there. This comment is to
6802 remind readers of that fact so that the following structures
6803 can be understood more easily.
6805 typedef struct minipool_node Mnode;
6806 typedef struct minipool_fixup Mfix; */
6808 struct minipool_node
6810 /* Doubly linked chain of entries. */
6813 /* The maximum offset into the code that this entry can be placed. While
6814 pushing fixes for forward references, all entries are sorted in order
6815 of increasing max_address. */
6816 HOST_WIDE_INT max_address;
6817 /* Similarly for an entry inserted for a backwards ref. */
6818 HOST_WIDE_INT min_address;
6819 /* The number of fixes referencing this entry. This can become zero
6820 if we "unpush" an entry. In this case we ignore the entry when we
6821 come to emit the code. */
6823 /* The offset from the start of the minipool. */
6824 HOST_WIDE_INT offset;
6825 /* The value in table. */
6827 /* The mode of value. */
6828 enum machine_mode mode;
6829 /* The size of the value. With iWMMXt enabled
6830 sizes > 4 also imply an alignment of 8-bytes. */
6834 struct minipool_fixup
6838 HOST_WIDE_INT address;
6840 enum machine_mode mode;
6844 HOST_WIDE_INT forwards;
6845 HOST_WIDE_INT backwards;
6848 /* Fixes less than a word need padding out to a word boundary. */
6849 #define MINIPOOL_FIX_SIZE(mode) \
6850 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4)
6852 static Mnode * minipool_vector_head;
6853 static Mnode * minipool_vector_tail;
6854 static rtx minipool_vector_label;
6856 /* The linked list of all minipool fixes required for this function. */
6857 Mfix * minipool_fix_head;
6858 Mfix * minipool_fix_tail;
6859 /* The fix entry for the current minipool, once it has been placed. */
6860 Mfix * minipool_barrier;
6862 /* Determines if INSN is the start of a jump table. Returns the end
6863 of the TABLE or NULL_RTX. */
6865 is_jump_table (rtx insn)
6869 if (GET_CODE (insn) == JUMP_INSN
6870 && JUMP_LABEL (insn) != NULL
6871 && ((table = next_real_insn (JUMP_LABEL (insn)))
6872 == next_real_insn (insn))
6874 && GET_CODE (table) == JUMP_INSN
6875 && (GET_CODE (PATTERN (table)) == ADDR_VEC
6876 || GET_CODE (PATTERN (table)) == ADDR_DIFF_VEC))
6882 #ifndef JUMP_TABLES_IN_TEXT_SECTION
6883 #define JUMP_TABLES_IN_TEXT_SECTION 0
6886 static HOST_WIDE_INT
6887 get_jump_table_size (rtx insn)
6889 /* ADDR_VECs only take room if read-only data does into the text
6891 if (JUMP_TABLES_IN_TEXT_SECTION
6892 #if !defined(READONLY_DATA_SECTION) && !defined(READONLY_DATA_SECTION_ASM_OP)
6897 rtx body = PATTERN (insn);
6898 int elt = GET_CODE (body) == ADDR_DIFF_VEC ? 1 : 0;
6900 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, elt);
6906 /* Move a minipool fix MP from its current location to before MAX_MP.
6907 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
6908 constraints may need updating. */
6910 move_minipool_fix_forward_ref (Mnode *mp, Mnode *max_mp,
6911 HOST_WIDE_INT max_address)
6913 /* This should never be true and the code below assumes these are
6920 if (max_address < mp->max_address)
6921 mp->max_address = max_address;
6925 if (max_address > max_mp->max_address - mp->fix_size)
6926 mp->max_address = max_mp->max_address - mp->fix_size;
6928 mp->max_address = max_address;
6930 /* Unlink MP from its current position. Since max_mp is non-null,
6931 mp->prev must be non-null. */
6932 mp->prev->next = mp->next;
6933 if (mp->next != NULL)
6934 mp->next->prev = mp->prev;
6936 minipool_vector_tail = mp->prev;
6938 /* Re-insert it before MAX_MP. */
6940 mp->prev = max_mp->prev;
6943 if (mp->prev != NULL)
6944 mp->prev->next = mp;
6946 minipool_vector_head = mp;
6949 /* Save the new entry. */
6952 /* Scan over the preceding entries and adjust their addresses as
6954 while (mp->prev != NULL
6955 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
6957 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
6964 /* Add a constant to the minipool for a forward reference. Returns the
6965 node added or NULL if the constant will not fit in this pool. */
6967 add_minipool_forward_ref (Mfix *fix)
6969 /* If set, max_mp is the first pool_entry that has a lower
6970 constraint than the one we are trying to add. */
6971 Mnode * max_mp = NULL;
6972 HOST_WIDE_INT max_address = fix->address + fix->forwards;
6975 /* If this fix's address is greater than the address of the first
6976 entry, then we can't put the fix in this pool. We subtract the
6977 size of the current fix to ensure that if the table is fully
6978 packed we still have enough room to insert this value by suffling
6979 the other fixes forwards. */
6980 if (minipool_vector_head &&
6981 fix->address >= minipool_vector_head->max_address - fix->fix_size)
6984 /* Scan the pool to see if a constant with the same value has
6985 already been added. While we are doing this, also note the
6986 location where we must insert the constant if it doesn't already
6988 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
6990 if (GET_CODE (fix->value) == GET_CODE (mp->value)
6991 && fix->mode == mp->mode
6992 && (GET_CODE (fix->value) != CODE_LABEL
6993 || (CODE_LABEL_NUMBER (fix->value)
6994 == CODE_LABEL_NUMBER (mp->value)))
6995 && rtx_equal_p (fix->value, mp->value))
6997 /* More than one fix references this entry. */
6999 return move_minipool_fix_forward_ref (mp, max_mp, max_address);
7002 /* Note the insertion point if necessary. */
7004 && mp->max_address > max_address)
7007 /* If we are inserting an 8-bytes aligned quantity and
7008 we have not already found an insertion point, then
7009 make sure that all such 8-byte aligned quantities are
7010 placed at the start of the pool. */
7011 if (ARM_DOUBLEWORD_ALIGN
7013 && fix->fix_size == 8
7014 && mp->fix_size != 8)
7017 max_address = mp->max_address;
7021 /* The value is not currently in the minipool, so we need to create
7022 a new entry for it. If MAX_MP is NULL, the entry will be put on
7023 the end of the list since the placement is less constrained than
7024 any existing entry. Otherwise, we insert the new fix before
7025 MAX_MP and, if necessary, adjust the constraints on the other
7027 mp = xmalloc (sizeof (* mp));
7028 mp->fix_size = fix->fix_size;
7029 mp->mode = fix->mode;
7030 mp->value = fix->value;
7032 /* Not yet required for a backwards ref. */
7033 mp->min_address = -65536;
7037 mp->max_address = max_address;
7039 mp->prev = minipool_vector_tail;
7041 if (mp->prev == NULL)
7043 minipool_vector_head = mp;
7044 minipool_vector_label = gen_label_rtx ();
7047 mp->prev->next = mp;
7049 minipool_vector_tail = mp;
7053 if (max_address > max_mp->max_address - mp->fix_size)
7054 mp->max_address = max_mp->max_address - mp->fix_size;
7056 mp->max_address = max_address;
7059 mp->prev = max_mp->prev;
7061 if (mp->prev != NULL)
7062 mp->prev->next = mp;
7064 minipool_vector_head = mp;
7067 /* Save the new entry. */
7070 /* Scan over the preceding entries and adjust their addresses as
7072 while (mp->prev != NULL
7073 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
7075 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
7083 move_minipool_fix_backward_ref (Mnode *mp, Mnode *min_mp,
7084 HOST_WIDE_INT min_address)
7086 HOST_WIDE_INT offset;
7088 /* This should never be true, and the code below assumes these are
7095 if (min_address > mp->min_address)
7096 mp->min_address = min_address;
7100 /* We will adjust this below if it is too loose. */
7101 mp->min_address = min_address;
7103 /* Unlink MP from its current position. Since min_mp is non-null,
7104 mp->next must be non-null. */
7105 mp->next->prev = mp->prev;
7106 if (mp->prev != NULL)
7107 mp->prev->next = mp->next;
7109 minipool_vector_head = mp->next;
7111 /* Reinsert it after MIN_MP. */
7113 mp->next = min_mp->next;
7115 if (mp->next != NULL)
7116 mp->next->prev = mp;
7118 minipool_vector_tail = mp;
7124 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
7126 mp->offset = offset;
7127 if (mp->refcount > 0)
7128 offset += mp->fix_size;
7130 if (mp->next && mp->next->min_address < mp->min_address + mp->fix_size)
7131 mp->next->min_address = mp->min_address + mp->fix_size;
7137 /* Add a constant to the minipool for a backward reference. Returns the
7138 node added or NULL if the constant will not fit in this pool.
7140 Note that the code for insertion for a backwards reference can be
7141 somewhat confusing because the calculated offsets for each fix do
7142 not take into account the size of the pool (which is still under
7145 add_minipool_backward_ref (Mfix *fix)
7147 /* If set, min_mp is the last pool_entry that has a lower constraint
7148 than the one we are trying to add. */
7149 Mnode *min_mp = NULL;
7150 /* This can be negative, since it is only a constraint. */
7151 HOST_WIDE_INT min_address = fix->address - fix->backwards;
7154 /* If we can't reach the current pool from this insn, or if we can't
7155 insert this entry at the end of the pool without pushing other
7156 fixes out of range, then we don't try. This ensures that we
7157 can't fail later on. */
7158 if (min_address >= minipool_barrier->address
7159 || (minipool_vector_tail->min_address + fix->fix_size
7160 >= minipool_barrier->address))
7163 /* Scan the pool to see if a constant with the same value has
7164 already been added. While we are doing this, also note the
7165 location where we must insert the constant if it doesn't already
7167 for (mp = minipool_vector_tail; mp != NULL; mp = mp->prev)
7169 if (GET_CODE (fix->value) == GET_CODE (mp->value)
7170 && fix->mode == mp->mode
7171 && (GET_CODE (fix->value) != CODE_LABEL
7172 || (CODE_LABEL_NUMBER (fix->value)
7173 == CODE_LABEL_NUMBER (mp->value)))
7174 && rtx_equal_p (fix->value, mp->value)
7175 /* Check that there is enough slack to move this entry to the
7176 end of the table (this is conservative). */
7178 > (minipool_barrier->address
7179 + minipool_vector_tail->offset
7180 + minipool_vector_tail->fix_size)))
7183 return move_minipool_fix_backward_ref (mp, min_mp, min_address);
7187 mp->min_address += fix->fix_size;
7190 /* Note the insertion point if necessary. */
7191 if (mp->min_address < min_address)
7193 /* For now, we do not allow the insertion of 8-byte alignment
7194 requiring nodes anywhere but at the start of the pool. */
7195 if (ARM_DOUBLEWORD_ALIGN
7196 && fix->fix_size == 8 && mp->fix_size != 8)
7201 else if (mp->max_address
7202 < minipool_barrier->address + mp->offset + fix->fix_size)
7204 /* Inserting before this entry would push the fix beyond
7205 its maximum address (which can happen if we have
7206 re-located a forwards fix); force the new fix to come
7209 min_address = mp->min_address + fix->fix_size;
7211 /* If we are inserting an 8-bytes aligned quantity and
7212 we have not already found an insertion point, then
7213 make sure that all such 8-byte aligned quantities are
7214 placed at the start of the pool. */
7215 else if (ARM_DOUBLEWORD_ALIGN
7217 && fix->fix_size == 8
7218 && mp->fix_size < 8)
7221 min_address = mp->min_address + fix->fix_size;
7226 /* We need to create a new entry. */
7227 mp = xmalloc (sizeof (* mp));
7228 mp->fix_size = fix->fix_size;
7229 mp->mode = fix->mode;
7230 mp->value = fix->value;
7232 mp->max_address = minipool_barrier->address + 65536;
7234 mp->min_address = min_address;
7239 mp->next = minipool_vector_head;
7241 if (mp->next == NULL)
7243 minipool_vector_tail = mp;
7244 minipool_vector_label = gen_label_rtx ();
7247 mp->next->prev = mp;
7249 minipool_vector_head = mp;
7253 mp->next = min_mp->next;
7257 if (mp->next != NULL)
7258 mp->next->prev = mp;
7260 minipool_vector_tail = mp;
7263 /* Save the new entry. */
7271 /* Scan over the following entries and adjust their offsets. */
7272 while (mp->next != NULL)
7274 if (mp->next->min_address < mp->min_address + mp->fix_size)
7275 mp->next->min_address = mp->min_address + mp->fix_size;
7278 mp->next->offset = mp->offset + mp->fix_size;
7280 mp->next->offset = mp->offset;
7289 assign_minipool_offsets (Mfix *barrier)
7291 HOST_WIDE_INT offset = 0;
7294 minipool_barrier = barrier;
7296 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
7298 mp->offset = offset;
7300 if (mp->refcount > 0)
7301 offset += mp->fix_size;
7305 /* Output the literal table */
7307 dump_minipool (rtx scan)
7313 if (ARM_DOUBLEWORD_ALIGN)
7314 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
7315 if (mp->refcount > 0 && mp->fix_size == 8)
7323 ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n",
7324 INSN_UID (scan), (unsigned long) minipool_barrier->address, align64 ? 8 : 4);
7326 scan = emit_label_after (gen_label_rtx (), scan);
7327 scan = emit_insn_after (align64 ? gen_align_8 () : gen_align_4 (), scan);
7328 scan = emit_label_after (minipool_vector_label, scan);
7330 for (mp = minipool_vector_head; mp != NULL; mp = nmp)
7332 if (mp->refcount > 0)
7337 ";; Offset %u, min %ld, max %ld ",
7338 (unsigned) mp->offset, (unsigned long) mp->min_address,
7339 (unsigned long) mp->max_address);
7340 arm_print_value (dump_file, mp->value);
7341 fputc ('\n', dump_file);
7344 switch (mp->fix_size)
7346 #ifdef HAVE_consttable_1
7348 scan = emit_insn_after (gen_consttable_1 (mp->value), scan);
7352 #ifdef HAVE_consttable_2
7354 scan = emit_insn_after (gen_consttable_2 (mp->value), scan);
7358 #ifdef HAVE_consttable_4
7360 scan = emit_insn_after (gen_consttable_4 (mp->value), scan);
7364 #ifdef HAVE_consttable_8
7366 scan = emit_insn_after (gen_consttable_8 (mp->value), scan);
7380 minipool_vector_head = minipool_vector_tail = NULL;
7381 scan = emit_insn_after (gen_consttable_end (), scan);
7382 scan = emit_barrier_after (scan);
7385 /* Return the cost of forcibly inserting a barrier after INSN. */
7387 arm_barrier_cost (rtx insn)
7389 /* Basing the location of the pool on the loop depth is preferable,
7390 but at the moment, the basic block information seems to be
7391 corrupt by this stage of the compilation. */
7393 rtx next = next_nonnote_insn (insn);
7395 if (next != NULL && GET_CODE (next) == CODE_LABEL)
7398 switch (GET_CODE (insn))
7401 /* It will always be better to place the table before the label, rather
7410 return base_cost - 10;
7413 return base_cost + 10;
7417 /* Find the best place in the insn stream in the range
7418 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
7419 Create the barrier by inserting a jump and add a new fix entry for
7422 create_fix_barrier (Mfix *fix, HOST_WIDE_INT max_address)
7424 HOST_WIDE_INT count = 0;
7426 rtx from = fix->insn;
7427 rtx selected = from;
7429 HOST_WIDE_INT selected_address;
7431 HOST_WIDE_INT max_count = max_address - fix->address;
7432 rtx label = gen_label_rtx ();
7434 selected_cost = arm_barrier_cost (from);
7435 selected_address = fix->address;
7437 while (from && count < max_count)
7442 /* This code shouldn't have been called if there was a natural barrier
7444 if (GET_CODE (from) == BARRIER)
7447 /* Count the length of this insn. */
7448 count += get_attr_length (from);
7450 /* If there is a jump table, add its length. */
7451 tmp = is_jump_table (from);
7454 count += get_jump_table_size (tmp);
7456 /* Jump tables aren't in a basic block, so base the cost on
7457 the dispatch insn. If we select this location, we will
7458 still put the pool after the table. */
7459 new_cost = arm_barrier_cost (from);
7461 if (count < max_count && new_cost <= selected_cost)
7464 selected_cost = new_cost;
7465 selected_address = fix->address + count;
7468 /* Continue after the dispatch table. */
7469 from = NEXT_INSN (tmp);
7473 new_cost = arm_barrier_cost (from);
7475 if (count < max_count && new_cost <= selected_cost)
7478 selected_cost = new_cost;
7479 selected_address = fix->address + count;
7482 from = NEXT_INSN (from);
7485 /* Create a new JUMP_INSN that branches around a barrier. */
7486 from = emit_jump_insn_after (gen_jump (label), selected);
7487 JUMP_LABEL (from) = label;
7488 barrier = emit_barrier_after (from);
7489 emit_label_after (label, barrier);
7491 /* Create a minipool barrier entry for the new barrier. */
7492 new_fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* new_fix));
7493 new_fix->insn = barrier;
7494 new_fix->address = selected_address;
7495 new_fix->next = fix->next;
7496 fix->next = new_fix;
7501 /* Record that there is a natural barrier in the insn stream at
7504 push_minipool_barrier (rtx insn, HOST_WIDE_INT address)
7506 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
7509 fix->address = address;
7512 if (minipool_fix_head != NULL)
7513 minipool_fix_tail->next = fix;
7515 minipool_fix_head = fix;
7517 minipool_fix_tail = fix;
7520 /* Record INSN, which will need fixing up to load a value from the
7521 minipool. ADDRESS is the offset of the insn since the start of the
7522 function; LOC is a pointer to the part of the insn which requires
7523 fixing; VALUE is the constant that must be loaded, which is of type
7526 push_minipool_fix (rtx insn, HOST_WIDE_INT address, rtx *loc,
7527 enum machine_mode mode, rtx value)
7529 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
7531 #ifdef AOF_ASSEMBLER
7532 /* PIC symbol references need to be converted into offsets into the
7534 /* XXX This shouldn't be done here. */
7535 if (flag_pic && GET_CODE (value) == SYMBOL_REF)
7536 value = aof_pic_entry (value);
7537 #endif /* AOF_ASSEMBLER */
7540 fix->address = address;
7543 fix->fix_size = MINIPOOL_FIX_SIZE (mode);
7545 fix->forwards = get_attr_pool_range (insn);
7546 fix->backwards = get_attr_neg_pool_range (insn);
7547 fix->minipool = NULL;
7549 /* If an insn doesn't have a range defined for it, then it isn't
7550 expecting to be reworked by this code. Better to abort now than
7551 to generate duff assembly code. */
7552 if (fix->forwards == 0 && fix->backwards == 0)
7555 /* With AAPCS/iWMMXt enabled, the pool is aligned to an 8-byte boundary.
7556 So there might be an empty word before the start of the pool.
7557 Hence we reduce the forward range by 4 to allow for this
7559 if (ARM_DOUBLEWORD_ALIGN && fix->fix_size == 8)
7565 ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ",
7566 GET_MODE_NAME (mode),
7567 INSN_UID (insn), (unsigned long) address,
7568 -1 * (long)fix->backwards, (long)fix->forwards);
7569 arm_print_value (dump_file, fix->value);
7570 fprintf (dump_file, "\n");
7573 /* Add it to the chain of fixes. */
7576 if (minipool_fix_head != NULL)
7577 minipool_fix_tail->next = fix;
7579 minipool_fix_head = fix;
7581 minipool_fix_tail = fix;
7584 /* Scan INSN and note any of its operands that need fixing.
7585 If DO_PUSHES is false we do not actually push any of the fixups
7586 needed. The function returns TRUE is any fixups were needed/pushed.
7587 This is used by arm_memory_load_p() which needs to know about loads
7588 of constants that will be converted into minipool loads. */
7590 note_invalid_constants (rtx insn, HOST_WIDE_INT address, int do_pushes)
7592 bool result = false;
7595 extract_insn (insn);
7597 if (!constrain_operands (1))
7598 fatal_insn_not_found (insn);
7600 if (recog_data.n_alternatives == 0)
7603 /* Fill in recog_op_alt with information about the constraints of this insn. */
7604 preprocess_constraints ();
7606 for (opno = 0; opno < recog_data.n_operands; opno++)
7608 /* Things we need to fix can only occur in inputs. */
7609 if (recog_data.operand_type[opno] != OP_IN)
7612 /* If this alternative is a memory reference, then any mention
7613 of constants in this alternative is really to fool reload
7614 into allowing us to accept one there. We need to fix them up
7615 now so that we output the right code. */
7616 if (recog_op_alt[opno][which_alternative].memory_ok)
7618 rtx op = recog_data.operand[opno];
7620 if (CONSTANT_P (op))
7623 push_minipool_fix (insn, address, recog_data.operand_loc[opno],
7624 recog_data.operand_mode[opno], op);
7627 else if (GET_CODE (op) == MEM
7628 && GET_CODE (XEXP (op, 0)) == SYMBOL_REF
7629 && CONSTANT_POOL_ADDRESS_P (XEXP (op, 0)))
7633 rtx cop = avoid_constant_pool_reference (op);
7635 /* Casting the address of something to a mode narrower
7636 than a word can cause avoid_constant_pool_reference()
7637 to return the pool reference itself. That's no good to
7638 us here. Lets just hope that we can use the
7639 constant pool value directly. */
7641 cop = get_pool_constant (XEXP (op, 0));
7643 push_minipool_fix (insn, address,
7644 recog_data.operand_loc[opno],
7645 recog_data.operand_mode[opno], cop);
7656 /* Gcc puts the pool in the wrong place for ARM, since we can only
7657 load addresses a limited distance around the pc. We do some
7658 special munging to move the constant pool values to the correct
7659 point in the code. */
7664 HOST_WIDE_INT address = 0;
7667 minipool_fix_head = minipool_fix_tail = NULL;
7669 /* The first insn must always be a note, or the code below won't
7670 scan it properly. */
7671 insn = get_insns ();
7672 if (GET_CODE (insn) != NOTE)
7675 /* Scan all the insns and record the operands that will need fixing. */
7676 for (insn = next_nonnote_insn (insn); insn; insn = next_nonnote_insn (insn))
7678 if (TARGET_CIRRUS_FIX_INVALID_INSNS
7679 && (arm_cirrus_insn_p (insn)
7680 || GET_CODE (insn) == JUMP_INSN
7681 || arm_memory_load_p (insn)))
7682 cirrus_reorg (insn);
7684 if (GET_CODE (insn) == BARRIER)
7685 push_minipool_barrier (insn, address);
7686 else if (INSN_P (insn))
7690 note_invalid_constants (insn, address, true);
7691 address += get_attr_length (insn);
7693 /* If the insn is a vector jump, add the size of the table
7694 and skip the table. */
7695 if ((table = is_jump_table (insn)) != NULL)
7697 address += get_jump_table_size (table);
7703 fix = minipool_fix_head;
7705 /* Now scan the fixups and perform the required changes. */
7710 Mfix * last_added_fix;
7711 Mfix * last_barrier = NULL;
7714 /* Skip any further barriers before the next fix. */
7715 while (fix && GET_CODE (fix->insn) == BARRIER)
7718 /* No more fixes. */
7722 last_added_fix = NULL;
7724 for (ftmp = fix; ftmp; ftmp = ftmp->next)
7726 if (GET_CODE (ftmp->insn) == BARRIER)
7728 if (ftmp->address >= minipool_vector_head->max_address)
7731 last_barrier = ftmp;
7733 else if ((ftmp->minipool = add_minipool_forward_ref (ftmp)) == NULL)
7736 last_added_fix = ftmp; /* Keep track of the last fix added. */
7739 /* If we found a barrier, drop back to that; any fixes that we
7740 could have reached but come after the barrier will now go in
7741 the next mini-pool. */
7742 if (last_barrier != NULL)
7744 /* Reduce the refcount for those fixes that won't go into this
7746 for (fdel = last_barrier->next;
7747 fdel && fdel != ftmp;
7750 fdel->minipool->refcount--;
7751 fdel->minipool = NULL;
7754 ftmp = last_barrier;
7758 /* ftmp is first fix that we can't fit into this pool and
7759 there no natural barriers that we could use. Insert a
7760 new barrier in the code somewhere between the previous
7761 fix and this one, and arrange to jump around it. */
7762 HOST_WIDE_INT max_address;
7764 /* The last item on the list of fixes must be a barrier, so
7765 we can never run off the end of the list of fixes without
7766 last_barrier being set. */
7770 max_address = minipool_vector_head->max_address;
7771 /* Check that there isn't another fix that is in range that
7772 we couldn't fit into this pool because the pool was
7773 already too large: we need to put the pool before such an
7775 if (ftmp->address < max_address)
7776 max_address = ftmp->address;
7778 last_barrier = create_fix_barrier (last_added_fix, max_address);
7781 assign_minipool_offsets (last_barrier);
7785 if (GET_CODE (ftmp->insn) != BARRIER
7786 && ((ftmp->minipool = add_minipool_backward_ref (ftmp))
7793 /* Scan over the fixes we have identified for this pool, fixing them
7794 up and adding the constants to the pool itself. */
7795 for (this_fix = fix; this_fix && ftmp != this_fix;
7796 this_fix = this_fix->next)
7797 if (GET_CODE (this_fix->insn) != BARRIER)
7800 = plus_constant (gen_rtx_LABEL_REF (VOIDmode,
7801 minipool_vector_label),
7802 this_fix->minipool->offset);
7803 *this_fix->loc = gen_rtx_MEM (this_fix->mode, addr);
7806 dump_minipool (last_barrier->insn);
7810 /* From now on we must synthesize any constants that we can't handle
7811 directly. This can happen if the RTL gets split during final
7812 instruction generation. */
7813 after_arm_reorg = 1;
7815 /* Free the minipool memory. */
7816 obstack_free (&minipool_obstack, minipool_startobj);
7819 /* Routines to output assembly language. */
7821 /* If the rtx is the correct value then return the string of the number.
7822 In this way we can ensure that valid double constants are generated even
7823 when cross compiling. */
7825 fp_immediate_constant (rtx x)
7830 if (!fp_consts_inited)
7833 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
7834 for (i = 0; i < 8; i++)
7835 if (REAL_VALUES_EQUAL (r, values_fp[i]))
7836 return strings_fp[i];
7841 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
7843 fp_const_from_val (REAL_VALUE_TYPE *r)
7847 if (!fp_consts_inited)
7850 for (i = 0; i < 8; i++)
7851 if (REAL_VALUES_EQUAL (*r, values_fp[i]))
7852 return strings_fp[i];
7857 /* Output the operands of a LDM/STM instruction to STREAM.
7858 MASK is the ARM register set mask of which only bits 0-15 are important.
7859 REG is the base register, either the frame pointer or the stack pointer,
7860 INSTR is the possibly suffixed load or store instruction. */
7862 print_multi_reg (FILE *stream, const char *instr, int reg, int mask)
7865 int not_first = FALSE;
7867 fputc ('\t', stream);
7868 asm_fprintf (stream, instr, reg);
7869 fputs (", {", stream);
7871 for (i = 0; i <= LAST_ARM_REGNUM; i++)
7872 if (mask & (1 << i))
7875 fprintf (stream, ", ");
7877 asm_fprintf (stream, "%r", i);
7881 fprintf (stream, "}");
7883 /* Add a ^ character for the 26-bit ABI, but only if we were loading
7884 the PC. Otherwise we would generate an UNPREDICTABLE instruction.
7885 Strictly speaking the instruction would be unpredicatble only if
7886 we were writing back the base register as well, but since we never
7887 want to generate an LDM type 2 instruction (register bank switching)
7888 which is what you get if the PC is not being loaded, we do not need
7889 to check for writeback. */
7890 if (! TARGET_APCS_32
7891 && ((mask & (1 << PC_REGNUM)) != 0))
7892 fprintf (stream, "^");
7894 fprintf (stream, "\n");
7898 /* Output a FLDMX instruction to STREAM.
7899 BASE if the register containing the address.
7900 REG and COUNT specify the register range.
7901 Extra registers may be added to avoid hardware bugs. */
7904 arm_output_fldmx (FILE * stream, unsigned int base, int reg, int count)
7908 /* Workaround ARM10 VFPr1 bug. */
7909 if (count == 2 && !arm_arch6)
7916 fputc ('\t', stream);
7917 asm_fprintf (stream, "fldmfdx\t%r!, {", base);
7919 for (i = reg; i < reg + count; i++)
7922 fputs (", ", stream);
7923 asm_fprintf (stream, "d%d", i);
7925 fputs ("}\n", stream);
7930 /* Output the assembly for a store multiple. */
7933 vfp_output_fstmx (rtx * operands)
7940 strcpy (pattern, "fstmfdx\t%m0!, {%P1");
7941 p = strlen (pattern);
7943 if (GET_CODE (operands[1]) != REG)
7946 base = (REGNO (operands[1]) - FIRST_VFP_REGNUM) / 2;
7947 for (i = 1; i < XVECLEN (operands[2], 0); i++)
7949 p += sprintf (&pattern[p], ", d%d", base + i);
7951 strcpy (&pattern[p], "}");
7953 output_asm_insn (pattern, operands);
7958 /* Emit RTL to save block of VFP register pairs to the stack. Returns the
7959 number of bytes pushed. */
7962 vfp_emit_fstmx (int base_reg, int count)
7969 /* Workaround ARM10 VFPr1 bug. Data corruption can occur when exactly two
7970 register pairs are stored by a store multiple insn. We avoid this
7971 by pushing an extra pair. */
7972 if (count == 2 && !arm_arch6)
7974 if (base_reg == LAST_VFP_REGNUM - 3)
7979 /* ??? The frame layout is implementation defined. We describe
7980 standard format 1 (equivalent to a FSTMD insn and unused pad word).
7981 We really need some way of representing the whole block so that the
7982 unwinder can figure it out at runtime. */
7983 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
7984 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (count + 1));
7986 reg = gen_rtx_REG (DFmode, base_reg);
7990 = gen_rtx_SET (VOIDmode,
7991 gen_rtx_MEM (BLKmode,
7992 gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
7993 gen_rtx_UNSPEC (BLKmode,
7997 tmp = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7998 gen_rtx_PLUS (SImode, stack_pointer_rtx,
7999 GEN_INT (-(count * 8 + 4))));
8000 RTX_FRAME_RELATED_P (tmp) = 1;
8001 XVECEXP (dwarf, 0, 0) = tmp;
8003 tmp = gen_rtx_SET (VOIDmode,
8004 gen_rtx_MEM (DFmode, stack_pointer_rtx),
8006 RTX_FRAME_RELATED_P (tmp) = 1;
8007 XVECEXP (dwarf, 0, 1) = tmp;
8009 for (i = 1; i < count; i++)
8011 reg = gen_rtx_REG (DFmode, base_reg);
8013 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
8015 tmp = gen_rtx_SET (VOIDmode,
8016 gen_rtx_MEM (DFmode,
8017 gen_rtx_PLUS (SImode,
8021 RTX_FRAME_RELATED_P (tmp) = 1;
8022 XVECEXP (dwarf, 0, i + 1) = tmp;
8025 par = emit_insn (par);
8026 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
8028 RTX_FRAME_RELATED_P (par) = 1;
8030 return count * 8 + 4;
8034 /* Output a 'call' insn. */
8036 output_call (rtx *operands)
8038 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
8040 if (REGNO (operands[0]) == LR_REGNUM)
8042 operands[0] = gen_rtx_REG (SImode, IP_REGNUM);
8043 output_asm_insn ("mov%?\t%0, %|lr", operands);
8046 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
8048 if (TARGET_INTERWORK)
8049 output_asm_insn ("bx%?\t%0", operands);
8051 output_asm_insn ("mov%?\t%|pc, %0", operands);
8056 /* Output a 'call' insn that is a reference in memory. */
8058 output_call_mem (rtx *operands)
8060 if (TARGET_INTERWORK)
8062 output_asm_insn ("ldr%?\t%|ip, %0", operands);
8063 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
8064 output_asm_insn ("bx%?\t%|ip", operands);
8066 else if (regno_use_in (LR_REGNUM, operands[0]))
8068 /* LR is used in the memory address. We load the address in the
8069 first instruction. It's safe to use IP as the target of the
8070 load since the call will kill it anyway. */
8071 output_asm_insn ("ldr%?\t%|ip, %0", operands);
8072 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
8073 output_asm_insn ("mov%?\t%|pc, %|ip", operands);
8077 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
8078 output_asm_insn ("ldr%?\t%|pc, %0", operands);
8085 /* Output a move from arm registers to an fpa registers.
8086 OPERANDS[0] is an fpa register.
8087 OPERANDS[1] is the first registers of an arm register pair. */
8089 output_mov_long_double_fpa_from_arm (rtx *operands)
8091 int arm_reg0 = REGNO (operands[1]);
8094 if (arm_reg0 == IP_REGNUM)
8097 ops[0] = gen_rtx_REG (SImode, arm_reg0);
8098 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
8099 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
8101 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops);
8102 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands);
8107 /* Output a move from an fpa register to arm registers.
8108 OPERANDS[0] is the first registers of an arm register pair.
8109 OPERANDS[1] is an fpa register. */
8111 output_mov_long_double_arm_from_fpa (rtx *operands)
8113 int arm_reg0 = REGNO (operands[0]);
8116 if (arm_reg0 == IP_REGNUM)
8119 ops[0] = gen_rtx_REG (SImode, arm_reg0);
8120 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
8121 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
8123 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands);
8124 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops);
8128 /* Output a move from arm registers to arm registers of a long double
8129 OPERANDS[0] is the destination.
8130 OPERANDS[1] is the source. */
8132 output_mov_long_double_arm_from_arm (rtx *operands)
8134 /* We have to be careful here because the two might overlap. */
8135 int dest_start = REGNO (operands[0]);
8136 int src_start = REGNO (operands[1]);
8140 if (dest_start < src_start)
8142 for (i = 0; i < 3; i++)
8144 ops[0] = gen_rtx_REG (SImode, dest_start + i);
8145 ops[1] = gen_rtx_REG (SImode, src_start + i);
8146 output_asm_insn ("mov%?\t%0, %1", ops);
8151 for (i = 2; i >= 0; i--)
8153 ops[0] = gen_rtx_REG (SImode, dest_start + i);
8154 ops[1] = gen_rtx_REG (SImode, src_start + i);
8155 output_asm_insn ("mov%?\t%0, %1", ops);
8163 /* Output a move from arm registers to an fpa registers.
8164 OPERANDS[0] is an fpa register.
8165 OPERANDS[1] is the first registers of an arm register pair. */
8167 output_mov_double_fpa_from_arm (rtx *operands)
8169 int arm_reg0 = REGNO (operands[1]);
8172 if (arm_reg0 == IP_REGNUM)
8175 ops[0] = gen_rtx_REG (SImode, arm_reg0);
8176 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
8177 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops);
8178 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands);
8182 /* Output a move from an fpa register to arm registers.
8183 OPERANDS[0] is the first registers of an arm register pair.
8184 OPERANDS[1] is an fpa register. */
8186 output_mov_double_arm_from_fpa (rtx *operands)
8188 int arm_reg0 = REGNO (operands[0]);
8191 if (arm_reg0 == IP_REGNUM)
8194 ops[0] = gen_rtx_REG (SImode, arm_reg0);
8195 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
8196 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands);
8197 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops);
8201 /* Output a move between double words.
8202 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
8203 or MEM<-REG and all MEMs must be offsettable addresses. */
8205 output_move_double (rtx *operands)
8207 enum rtx_code code0 = GET_CODE (operands[0]);
8208 enum rtx_code code1 = GET_CODE (operands[1]);
8213 int reg0 = REGNO (operands[0]);
8215 otherops[0] = gen_rtx_REG (SImode, 1 + reg0);
8219 int reg1 = REGNO (operands[1]);
8220 if (reg1 == IP_REGNUM)
8223 /* Ensure the second source is not overwritten. */
8224 if (reg1 == reg0 + (WORDS_BIG_ENDIAN ? -1 : 1))
8225 output_asm_insn ("mov%?\t%Q0, %Q1\n\tmov%?\t%R0, %R1", operands);
8227 output_asm_insn ("mov%?\t%R0, %R1\n\tmov%?\t%Q0, %Q1", operands);
8229 else if (code1 == CONST_VECTOR)
8231 HOST_WIDE_INT hint = 0;
8233 switch (GET_MODE (operands[1]))
8236 otherops[1] = GEN_INT (INTVAL (CONST_VECTOR_ELT (operands[1], 1)));
8237 operands[1] = GEN_INT (INTVAL (CONST_VECTOR_ELT (operands[1], 0)));
8241 if (BYTES_BIG_ENDIAN)
8243 hint = INTVAL (CONST_VECTOR_ELT (operands[1], 2));
8245 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 3));
8249 hint = INTVAL (CONST_VECTOR_ELT (operands[1], 3));
8251 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 2));
8254 otherops[1] = GEN_INT (hint);
8257 if (BYTES_BIG_ENDIAN)
8259 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0));
8261 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1));
8265 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1));
8267 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0));
8270 operands[1] = GEN_INT (hint);
8274 if (BYTES_BIG_ENDIAN)
8276 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 4));
8278 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 5));
8280 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 6));
8282 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 7));
8286 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 7));
8288 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 6));
8290 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 5));
8292 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 4));
8295 otherops[1] = GEN_INT (hint);
8298 if (BYTES_BIG_ENDIAN)
8300 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0));
8302 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1));
8304 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 2));
8306 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 3));
8310 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 3));
8312 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 2));
8314 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1));
8316 hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0));
8319 operands[1] = GEN_INT (hint);
8325 output_mov_immediate (operands);
8326 output_mov_immediate (otherops);
8328 else if (code1 == CONST_DOUBLE)
8330 if (GET_MODE (operands[1]) == DFmode)
8335 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
8336 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
8337 otherops[1] = GEN_INT (l[1]);
8338 operands[1] = GEN_INT (l[0]);
8340 else if (GET_MODE (operands[1]) != VOIDmode)
8342 else if (WORDS_BIG_ENDIAN)
8344 otherops[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
8345 operands[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
8349 otherops[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
8350 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
8353 output_mov_immediate (operands);
8354 output_mov_immediate (otherops);
8356 else if (code1 == CONST_INT)
8358 #if HOST_BITS_PER_WIDE_INT > 32
8359 /* If HOST_WIDE_INT is more than 32 bits, the intval tells us
8360 what the upper word is. */
8361 if (WORDS_BIG_ENDIAN)
8363 otherops[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1])));
8364 operands[1] = GEN_INT (INTVAL (operands[1]) >> 32);
8368 otherops[1] = GEN_INT (INTVAL (operands[1]) >> 32);
8369 operands[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1])));
8372 /* Sign extend the intval into the high-order word. */
8373 if (WORDS_BIG_ENDIAN)
8375 otherops[1] = operands[1];
8376 operands[1] = (INTVAL (operands[1]) < 0
8377 ? constm1_rtx : const0_rtx);
8380 otherops[1] = INTVAL (operands[1]) < 0 ? constm1_rtx : const0_rtx;
8382 output_mov_immediate (otherops);
8383 output_mov_immediate (operands);
8385 else if (code1 == MEM)
8387 switch (GET_CODE (XEXP (operands[1], 0)))
8390 output_asm_insn ("ldm%?ia\t%m1, %M0", operands);
8394 abort (); /* Should never happen now. */
8398 output_asm_insn ("ldm%?db\t%m1!, %M0", operands);
8402 output_asm_insn ("ldm%?ia\t%m1!, %M0", operands);
8406 abort (); /* Should never happen now. */
8411 output_asm_insn ("adr%?\t%0, %1", operands);
8412 output_asm_insn ("ldm%?ia\t%0, %M0", operands);
8416 if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1),
8417 GET_MODE (XEXP (XEXP (operands[1], 0), 1))))
8419 otherops[0] = operands[0];
8420 otherops[1] = XEXP (XEXP (operands[1], 0), 0);
8421 otherops[2] = XEXP (XEXP (operands[1], 0), 1);
8423 if (GET_CODE (XEXP (operands[1], 0)) == PLUS)
8425 if (GET_CODE (otherops[2]) == CONST_INT)
8427 switch ((int) INTVAL (otherops[2]))
8430 output_asm_insn ("ldm%?db\t%1, %M0", otherops);
8433 output_asm_insn ("ldm%?da\t%1, %M0", otherops);
8436 output_asm_insn ("ldm%?ib\t%1, %M0", otherops);
8440 if (!(const_ok_for_arm (INTVAL (otherops[2]))))
8441 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops);
8443 output_asm_insn ("add%?\t%0, %1, %2", otherops);
8446 output_asm_insn ("add%?\t%0, %1, %2", otherops);
8449 output_asm_insn ("sub%?\t%0, %1, %2", otherops);
8451 return "ldm%?ia\t%0, %M0";
8455 otherops[1] = adjust_address (operands[1], SImode, 4);
8456 /* Take care of overlapping base/data reg. */
8457 if (reg_mentioned_p (operands[0], operands[1]))
8459 output_asm_insn ("ldr%?\t%0, %1", otherops);
8460 output_asm_insn ("ldr%?\t%0, %1", operands);
8464 output_asm_insn ("ldr%?\t%0, %1", operands);
8465 output_asm_insn ("ldr%?\t%0, %1", otherops);
8471 abort (); /* Constraints should prevent this. */
8473 else if (code0 == MEM && code1 == REG)
8475 if (REGNO (operands[1]) == IP_REGNUM)
8478 switch (GET_CODE (XEXP (operands[0], 0)))
8481 output_asm_insn ("stm%?ia\t%m0, %M1", operands);
8485 abort (); /* Should never happen now. */
8489 output_asm_insn ("stm%?db\t%m0!, %M1", operands);
8493 output_asm_insn ("stm%?ia\t%m0!, %M1", operands);
8497 abort (); /* Should never happen now. */
8501 if (GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
8503 switch ((int) INTVAL (XEXP (XEXP (operands[0], 0), 1)))
8506 output_asm_insn ("stm%?db\t%m0, %M1", operands);
8510 output_asm_insn ("stm%?da\t%m0, %M1", operands);
8514 output_asm_insn ("stm%?ib\t%m0, %M1", operands);
8521 otherops[0] = adjust_address (operands[0], SImode, 4);
8522 otherops[1] = gen_rtx_REG (SImode, 1 + REGNO (operands[1]));
8523 output_asm_insn ("str%?\t%1, %0", operands);
8524 output_asm_insn ("str%?\t%1, %0", otherops);
8528 /* Constraints should prevent this. */
8535 /* Output an arbitrary MOV reg, #n.
8536 OPERANDS[0] is a register. OPERANDS[1] is a const_int. */
8538 output_mov_immediate (rtx *operands)
8540 HOST_WIDE_INT n = INTVAL (operands[1]);
8542 /* Try to use one MOV. */
8543 if (const_ok_for_arm (n))
8544 output_asm_insn ("mov%?\t%0, %1", operands);
8546 /* Try to use one MVN. */
8547 else if (const_ok_for_arm (~n))
8549 operands[1] = GEN_INT (~n);
8550 output_asm_insn ("mvn%?\t%0, %1", operands);
8557 /* If all else fails, make it out of ORRs or BICs as appropriate. */
8558 for (i = 0; i < 32; i++)
8562 if (n_ones > 16) /* Shorter to use MVN with BIC in this case. */
8563 output_multi_immediate (operands, "mvn%?\t%0, %1", "bic%?\t%0, %0, %1", 1, ~ n);
8565 output_multi_immediate (operands, "mov%?\t%0, %1", "orr%?\t%0, %0, %1", 1, n);
8571 /* Output an ADD r, s, #n where n may be too big for one instruction.
8572 If adding zero to one register, output nothing. */
8574 output_add_immediate (rtx *operands)
8576 HOST_WIDE_INT n = INTVAL (operands[2]);
8578 if (n != 0 || REGNO (operands[0]) != REGNO (operands[1]))
8581 output_multi_immediate (operands,
8582 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
8585 output_multi_immediate (operands,
8586 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
8593 /* Output a multiple immediate operation.
8594 OPERANDS is the vector of operands referred to in the output patterns.
8595 INSTR1 is the output pattern to use for the first constant.
8596 INSTR2 is the output pattern to use for subsequent constants.
8597 IMMED_OP is the index of the constant slot in OPERANDS.
8598 N is the constant value. */
8600 output_multi_immediate (rtx *operands, const char *instr1, const char *instr2,
8601 int immed_op, HOST_WIDE_INT n)
8603 #if HOST_BITS_PER_WIDE_INT > 32
8609 /* Quick and easy output. */
8610 operands[immed_op] = const0_rtx;
8611 output_asm_insn (instr1, operands);
8616 const char * instr = instr1;
8618 /* Note that n is never zero here (which would give no output). */
8619 for (i = 0; i < 32; i += 2)
8623 operands[immed_op] = GEN_INT (n & (255 << i));
8624 output_asm_insn (instr, operands);
8634 /* Return the appropriate ARM instruction for the operation code.
8635 The returned result should not be overwritten. OP is the rtx of the
8636 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
8639 arithmetic_instr (rtx op, int shift_first_arg)
8641 switch (GET_CODE (op))
8647 return shift_first_arg ? "rsb" : "sub";
8663 /* Ensure valid constant shifts and return the appropriate shift mnemonic
8664 for the operation code. The returned result should not be overwritten.
8665 OP is the rtx code of the shift.
8666 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
8669 shift_op (rtx op, HOST_WIDE_INT *amountp)
8672 enum rtx_code code = GET_CODE (op);
8674 if (GET_CODE (XEXP (op, 1)) == REG || GET_CODE (XEXP (op, 1)) == SUBREG)
8676 else if (GET_CODE (XEXP (op, 1)) == CONST_INT)
8677 *amountp = INTVAL (XEXP (op, 1));
8700 /* We never have to worry about the amount being other than a
8701 power of 2, since this case can never be reloaded from a reg. */
8703 *amountp = int_log2 (*amountp);
8714 /* This is not 100% correct, but follows from the desire to merge
8715 multiplication by a power of 2 with the recognizer for a
8716 shift. >=32 is not a valid shift for "asl", so we must try and
8717 output a shift that produces the correct arithmetical result.
8718 Using lsr #32 is identical except for the fact that the carry bit
8719 is not set correctly if we set the flags; but we never use the
8720 carry bit from such an operation, so we can ignore that. */
8721 if (code == ROTATERT)
8722 /* Rotate is just modulo 32. */
8724 else if (*amountp != (*amountp & 31))
8731 /* Shifts of 0 are no-ops. */
8739 /* Obtain the shift from the POWER of two. */
8741 static HOST_WIDE_INT
8742 int_log2 (HOST_WIDE_INT power)
8744 HOST_WIDE_INT shift = 0;
8746 while ((((HOST_WIDE_INT) 1 << shift) & power) == 0)
8756 /* Output a .ascii pseudo-op, keeping track of lengths. This is because
8757 /bin/as is horribly restrictive. */
8758 #define MAX_ASCII_LEN 51
8761 output_ascii_pseudo_op (FILE *stream, const unsigned char *p, int len)
8766 fputs ("\t.ascii\t\"", stream);
8768 for (i = 0; i < len; i++)
8772 if (len_so_far >= MAX_ASCII_LEN)
8774 fputs ("\"\n\t.ascii\t\"", stream);
8781 fputs ("\\t", stream);
8786 fputs ("\\f", stream);
8791 fputs ("\\b", stream);
8796 fputs ("\\r", stream);
8800 case TARGET_NEWLINE:
8801 fputs ("\\n", stream);
8803 if ((c >= ' ' && c <= '~')
8805 /* This is a good place for a line break. */
8806 len_so_far = MAX_ASCII_LEN;
8813 putc ('\\', stream);
8818 if (c >= ' ' && c <= '~')
8825 fprintf (stream, "\\%03o", c);
8832 fputs ("\"\n", stream);
8835 /* Compute the register sabe mask for registers 0 through 12
8836 inclusive. This code is used by arm_compute_save_reg_mask. */
8837 static unsigned long
8838 arm_compute_save_reg0_reg12_mask (void)
8840 unsigned long func_type = arm_current_func_type ();
8841 unsigned int save_reg_mask = 0;
8844 if (IS_INTERRUPT (func_type))
8846 unsigned int max_reg;
8847 /* Interrupt functions must not corrupt any registers,
8848 even call clobbered ones. If this is a leaf function
8849 we can just examine the registers used by the RTL, but
8850 otherwise we have to assume that whatever function is
8851 called might clobber anything, and so we have to save
8852 all the call-clobbered registers as well. */
8853 if (ARM_FUNC_TYPE (func_type) == ARM_FT_FIQ)
8854 /* FIQ handlers have registers r8 - r12 banked, so
8855 we only need to check r0 - r7, Normal ISRs only
8856 bank r14 and r15, so we must check up to r12.
8857 r13 is the stack pointer which is always preserved,
8858 so we do not need to consider it here. */
8863 for (reg = 0; reg <= max_reg; reg++)
8864 if (regs_ever_live[reg]
8865 || (! current_function_is_leaf && call_used_regs [reg]))
8866 save_reg_mask |= (1 << reg);
8870 /* In the normal case we only need to save those registers
8871 which are call saved and which are used by this function. */
8872 for (reg = 0; reg <= 10; reg++)
8873 if (regs_ever_live[reg] && ! call_used_regs [reg])
8874 save_reg_mask |= (1 << reg);
8876 /* Handle the frame pointer as a special case. */
8877 if (! TARGET_APCS_FRAME
8878 && ! frame_pointer_needed
8879 && regs_ever_live[HARD_FRAME_POINTER_REGNUM]
8880 && ! call_used_regs[HARD_FRAME_POINTER_REGNUM])
8881 save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM;
8883 /* If we aren't loading the PIC register,
8884 don't stack it even though it may be live. */
8886 && ! TARGET_SINGLE_PIC_BASE
8887 && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
8888 save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
8891 return save_reg_mask;
8894 /* Compute a bit mask of which registers need to be
8895 saved on the stack for the current function. */
8897 static unsigned long
8898 arm_compute_save_reg_mask (void)
8900 unsigned int save_reg_mask = 0;
8901 unsigned long func_type = arm_current_func_type ();
8903 if (IS_NAKED (func_type))
8904 /* This should never really happen. */
8907 /* If we are creating a stack frame, then we must save the frame pointer,
8908 IP (which will hold the old stack pointer), LR and the PC. */
8909 if (frame_pointer_needed)
8911 (1 << ARM_HARD_FRAME_POINTER_REGNUM)
8916 /* Volatile functions do not return, so there
8917 is no need to save any other registers. */
8918 if (IS_VOLATILE (func_type))
8919 return save_reg_mask;
8921 save_reg_mask |= arm_compute_save_reg0_reg12_mask ();
8923 /* Decide if we need to save the link register.
8924 Interrupt routines have their own banked link register,
8925 so they never need to save it.
8926 Otherwise if we do not use the link register we do not need to save
8927 it. If we are pushing other registers onto the stack however, we
8928 can save an instruction in the epilogue by pushing the link register
8929 now and then popping it back into the PC. This incurs extra memory
8930 accesses though, so we only do it when optimizing for size, and only
8931 if we know that we will not need a fancy return sequence. */
8932 if (regs_ever_live [LR_REGNUM]
8935 && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL))
8936 save_reg_mask |= 1 << LR_REGNUM;
8938 if (cfun->machine->lr_save_eliminated)
8939 save_reg_mask &= ~ (1 << LR_REGNUM);
8941 if (TARGET_REALLY_IWMMXT
8942 && ((bit_count (save_reg_mask)
8943 + ARM_NUM_INTS (current_function_pretend_args_size)) % 2) != 0)
8947 /* The total number of registers that are going to be pushed
8948 onto the stack is odd. We need to ensure that the stack
8949 is 64-bit aligned before we start to save iWMMXt registers,
8950 and also before we start to create locals. (A local variable
8951 might be a double or long long which we will load/store using
8952 an iWMMXt instruction). Therefore we need to push another
8953 ARM register, so that the stack will be 64-bit aligned. We
8954 try to avoid using the arg registers (r0 -r3) as they might be
8955 used to pass values in a tail call. */
8956 for (reg = 4; reg <= 12; reg++)
8957 if ((save_reg_mask & (1 << reg)) == 0)
8961 save_reg_mask |= (1 << reg);
8964 cfun->machine->sibcall_blocked = 1;
8965 save_reg_mask |= (1 << 3);
8969 return save_reg_mask;
8973 /* Return the number of bytes required to save VFP registers. */
8975 arm_get_vfp_saved_size (void)
8982 /* Space for saved VFP registers. */
8983 if (TARGET_HARD_FLOAT && TARGET_VFP)
8986 for (regno = FIRST_VFP_REGNUM;
8987 regno < LAST_VFP_REGNUM;
8990 if ((!regs_ever_live[regno] || call_used_regs[regno])
8991 && (!regs_ever_live[regno + 1] || call_used_regs[regno + 1]))
8995 /* Workaround ARM10 VFPr1 bug. */
8996 if (count == 2 && !arm_arch6)
8998 saved += count * 8 + 4;
9007 if (count == 2 && !arm_arch6)
9009 saved += count * 8 + 4;
9016 /* Generate a function exit sequence. If REALLY_RETURN is false, then do
9017 everything bar the final return instruction. */
9019 output_return_instruction (rtx operand, int really_return, int reverse)
9021 char conditional[10];
9024 unsigned long live_regs_mask;
9025 unsigned long func_type;
9026 arm_stack_offsets *offsets;
9028 func_type = arm_current_func_type ();
9030 if (IS_NAKED (func_type))
9033 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
9035 /* If this function was declared non-returning, and we have
9036 found a tail call, then we have to trust that the called
9037 function won't return. */
9042 /* Otherwise, trap an attempted return by aborting. */
9044 ops[1] = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)"
9046 assemble_external_libcall (ops[1]);
9047 output_asm_insn (reverse ? "bl%D0\t%a1" : "bl%d0\t%a1", ops);
9053 if (current_function_calls_alloca && !really_return)
9056 sprintf (conditional, "%%?%%%c0", reverse ? 'D' : 'd');
9058 return_used_this_function = 1;
9060 live_regs_mask = arm_compute_save_reg_mask ();
9064 const char * return_reg;
9066 /* If we do not have any special requirements for function exit
9067 (eg interworking, or ISR) then we can load the return address
9068 directly into the PC. Otherwise we must load it into LR. */
9070 && ! TARGET_INTERWORK)
9071 return_reg = reg_names[PC_REGNUM];
9073 return_reg = reg_names[LR_REGNUM];
9075 if ((live_regs_mask & (1 << IP_REGNUM)) == (1 << IP_REGNUM))
9077 /* There are three possible reasons for the IP register
9078 being saved. 1) a stack frame was created, in which case
9079 IP contains the old stack pointer, or 2) an ISR routine
9080 corrupted it, or 3) it was saved to align the stack on
9081 iWMMXt. In case 1, restore IP into SP, otherwise just
9083 if (frame_pointer_needed)
9085 live_regs_mask &= ~ (1 << IP_REGNUM);
9086 live_regs_mask |= (1 << SP_REGNUM);
9090 if (! IS_INTERRUPT (func_type)
9091 && ! TARGET_REALLY_IWMMXT)
9096 /* On some ARM architectures it is faster to use LDR rather than
9097 LDM to load a single register. On other architectures, the
9098 cost is the same. In 26 bit mode, or for exception handlers,
9099 we have to use LDM to load the PC so that the CPSR is also
9101 for (reg = 0; reg <= LAST_ARM_REGNUM; reg++)
9103 if (live_regs_mask == (unsigned int)(1 << reg))
9106 if (reg <= LAST_ARM_REGNUM
9107 && (reg != LR_REGNUM
9109 || (TARGET_APCS_32 && ! IS_INTERRUPT (func_type))))
9111 sprintf (instr, "ldr%s\t%%|%s, [%%|sp], #4", conditional,
9112 (reg == LR_REGNUM) ? return_reg : reg_names[reg]);
9119 /* Generate the load multiple instruction to restore the
9120 registers. Note we can get here, even if
9121 frame_pointer_needed is true, but only if sp already
9122 points to the base of the saved core registers. */
9123 if (live_regs_mask & (1 << SP_REGNUM))
9125 unsigned HOST_WIDE_INT stack_adjust;
9127 offsets = arm_get_frame_offsets ();
9128 stack_adjust = offsets->outgoing_args - offsets->saved_regs;
9129 if (stack_adjust != 0 && stack_adjust != 4)
9132 if (stack_adjust && arm_arch5)
9133 sprintf (instr, "ldm%sib\t%%|sp, {", conditional);
9136 /* If we can't use ldmib (SA110 bug), then try to pop r3
9139 live_regs_mask |= 1 << 3;
9140 sprintf (instr, "ldm%sfd\t%%|sp, {", conditional);
9144 sprintf (instr, "ldm%sfd\t%%|sp!, {", conditional);
9146 p = instr + strlen (instr);
9148 for (reg = 0; reg <= SP_REGNUM; reg++)
9149 if (live_regs_mask & (1 << reg))
9151 int l = strlen (reg_names[reg]);
9157 memcpy (p, ", ", 2);
9161 memcpy (p, "%|", 2);
9162 memcpy (p + 2, reg_names[reg], l);
9166 if (live_regs_mask & (1 << LR_REGNUM))
9168 sprintf (p, "%s%%|%s}", first ? "" : ", ", return_reg);
9169 /* Decide if we need to add the ^ symbol to the end of the
9170 register list. This causes the saved condition codes
9171 register to be copied into the current condition codes
9172 register. We do the copy if we are conforming to the 32-bit
9173 ABI and this is an interrupt function, or if we are
9174 conforming to the 26-bit ABI. There is a special case for
9175 the 26-bit ABI however, which is if we are writing back the
9176 stack pointer but not loading the PC. In this case adding
9177 the ^ symbol would create a type 2 LDM instruction, where
9178 writeback is UNPREDICTABLE. We are safe in leaving the ^
9179 character off in this case however, since the actual return
9180 instruction will be a MOVS which will restore the CPSR. */
9181 if ((TARGET_APCS_32 && IS_INTERRUPT (func_type))
9182 || (! TARGET_APCS_32 && really_return))
9189 output_asm_insn (instr, & operand);
9191 /* See if we need to generate an extra instruction to
9192 perform the actual function return. */
9194 && func_type != ARM_FT_INTERWORKED
9195 && (live_regs_mask & (1 << LR_REGNUM)) != 0)
9197 /* The return has already been handled
9198 by loading the LR into the PC. */
9205 switch ((int) ARM_FUNC_TYPE (func_type))
9209 sprintf (instr, "sub%ss\t%%|pc, %%|lr, #4", conditional);
9212 case ARM_FT_INTERWORKED:
9213 sprintf (instr, "bx%s\t%%|lr", conditional);
9216 case ARM_FT_EXCEPTION:
9217 sprintf (instr, "mov%ss\t%%|pc, %%|lr", conditional);
9221 /* ARMv5 implementations always provide BX, so interworking
9222 is the default unless APCS-26 is in use. */
9223 if ((insn_flags & FL_ARCH5) != 0 && TARGET_APCS_32)
9224 sprintf (instr, "bx%s\t%%|lr", conditional);
9226 sprintf (instr, "mov%s%s\t%%|pc, %%|lr",
9227 conditional, TARGET_APCS_32 ? "" : "s");
9231 output_asm_insn (instr, & operand);
9237 /* Write the function name into the code section, directly preceding
9238 the function prologue.
9240 Code will be output similar to this:
9242 .ascii "arm_poke_function_name", 0
9245 .word 0xff000000 + (t1 - t0)
9246 arm_poke_function_name
9248 stmfd sp!, {fp, ip, lr, pc}
9251 When performing a stack backtrace, code can inspect the value
9252 of 'pc' stored at 'fp' + 0. If the trace function then looks
9253 at location pc - 12 and the top 8 bits are set, then we know
9254 that there is a function name embedded immediately preceding this
9255 location and has length ((pc[-3]) & 0xff000000).
9257 We assume that pc is declared as a pointer to an unsigned long.
9259 It is of no benefit to output the function name if we are assembling
9260 a leaf function. These function types will not contain a stack
9261 backtrace structure, therefore it is not possible to determine the
9264 arm_poke_function_name (FILE *stream, const char *name)
9266 unsigned long alignlength;
9267 unsigned long length;
9270 length = strlen (name) + 1;
9271 alignlength = ROUND_UP_WORD (length);
9273 ASM_OUTPUT_ASCII (stream, name, length);
9274 ASM_OUTPUT_ALIGN (stream, 2);
9275 x = GEN_INT ((unsigned HOST_WIDE_INT) 0xff000000 + alignlength);
9276 assemble_aligned_integer (UNITS_PER_WORD, x);
9279 /* Place some comments into the assembler stream
9280 describing the current function. */
9282 arm_output_function_prologue (FILE *f, HOST_WIDE_INT frame_size)
9284 unsigned long func_type;
9288 thumb_output_function_prologue (f, frame_size);
9293 if (arm_ccfsm_state || arm_target_insn)
9296 func_type = arm_current_func_type ();
9298 switch ((int) ARM_FUNC_TYPE (func_type))
9303 case ARM_FT_INTERWORKED:
9304 asm_fprintf (f, "\t%@ Function supports interworking.\n");
9306 case ARM_FT_EXCEPTION_HANDLER:
9307 asm_fprintf (f, "\t%@ C++ Exception Handler.\n");
9310 asm_fprintf (f, "\t%@ Interrupt Service Routine.\n");
9313 asm_fprintf (f, "\t%@ Fast Interrupt Service Routine.\n");
9315 case ARM_FT_EXCEPTION:
9316 asm_fprintf (f, "\t%@ ARM Exception Handler.\n");
9320 if (IS_NAKED (func_type))
9321 asm_fprintf (f, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n");
9323 if (IS_VOLATILE (func_type))
9324 asm_fprintf (f, "\t%@ Volatile: function does not return.\n");
9326 if (IS_NESTED (func_type))
9327 asm_fprintf (f, "\t%@ Nested: function declared inside another function.\n");
9329 asm_fprintf (f, "\t%@ args = %d, pretend = %d, frame = %wd\n",
9330 current_function_args_size,
9331 current_function_pretend_args_size, frame_size);
9333 asm_fprintf (f, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n",
9334 frame_pointer_needed,
9335 cfun->machine->uses_anonymous_args);
9337 if (cfun->machine->lr_save_eliminated)
9338 asm_fprintf (f, "\t%@ link register save eliminated.\n");
9340 #ifdef AOF_ASSEMBLER
9342 asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, PIC_OFFSET_TABLE_REGNUM);
9345 return_used_this_function = 0;
9349 arm_output_epilogue (rtx sibling)
9352 unsigned long saved_regs_mask;
9353 unsigned long func_type;
9354 /* Floats_offset is the offset from the "virtual" frame. In an APCS
9355 frame that is $fp + 4 for a non-variadic function. */
9356 int floats_offset = 0;
9358 FILE * f = asm_out_file;
9359 rtx eh_ofs = cfun->machine->eh_epilogue_sp_ofs;
9360 unsigned int lrm_count = 0;
9361 int really_return = (sibling == NULL);
9363 arm_stack_offsets *offsets;
9365 /* If we have already generated the return instruction
9366 then it is futile to generate anything else. */
9367 if (use_return_insn (FALSE, sibling) && return_used_this_function)
9370 func_type = arm_current_func_type ();
9372 if (IS_NAKED (func_type))
9373 /* Naked functions don't have epilogues. */
9376 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
9380 /* A volatile function should never return. Call abort. */
9381 op = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" : "abort");
9382 assemble_external_libcall (op);
9383 output_asm_insn ("bl\t%a0", &op);
9388 if (ARM_FUNC_TYPE (func_type) == ARM_FT_EXCEPTION_HANDLER
9390 /* If we are throwing an exception, then we really must
9391 be doing a return, so we can't tail-call. */
9394 offsets = arm_get_frame_offsets ();
9395 saved_regs_mask = arm_compute_save_reg_mask ();
9398 lrm_count = bit_count (saved_regs_mask);
9400 floats_offset = offsets->saved_args;
9401 /* Compute how far away the floats will be. */
9402 for (reg = 0; reg <= LAST_ARM_REGNUM; reg++)
9403 if (saved_regs_mask & (1 << reg))
9406 if (frame_pointer_needed)
9408 /* This variable is for the Virtual Frame Pointer, not VFP regs. */
9409 int vfp_offset = offsets->frame;
9411 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
9413 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
9414 if (regs_ever_live[reg] && !call_used_regs[reg])
9416 floats_offset += 12;
9417 asm_fprintf (f, "\tldfe\t%r, [%r, #-%d]\n",
9418 reg, FP_REGNUM, floats_offset - vfp_offset);
9423 start_reg = LAST_FPA_REGNUM;
9425 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
9427 if (regs_ever_live[reg] && !call_used_regs[reg])
9429 floats_offset += 12;
9431 /* We can't unstack more than four registers at once. */
9432 if (start_reg - reg == 3)
9434 asm_fprintf (f, "\tlfm\t%r, 4, [%r, #-%d]\n",
9435 reg, FP_REGNUM, floats_offset - vfp_offset);
9436 start_reg = reg - 1;
9441 if (reg != start_reg)
9442 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
9443 reg + 1, start_reg - reg,
9444 FP_REGNUM, floats_offset - vfp_offset);
9445 start_reg = reg - 1;
9449 /* Just in case the last register checked also needs unstacking. */
9450 if (reg != start_reg)
9451 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
9452 reg + 1, start_reg - reg,
9453 FP_REGNUM, floats_offset - vfp_offset);
9456 if (TARGET_HARD_FLOAT && TARGET_VFP)
9460 /* The fldmx insn does not have base+offset addressing modes,
9461 so we use IP to hold the address. */
9462 saved_size = arm_get_vfp_saved_size ();
9466 floats_offset += saved_size;
9467 asm_fprintf (f, "\tsub\t%r, %r, #%d\n", IP_REGNUM,
9468 FP_REGNUM, floats_offset - vfp_offset);
9470 start_reg = FIRST_VFP_REGNUM;
9471 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
9473 if ((!regs_ever_live[reg] || call_used_regs[reg])
9474 && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1]))
9476 if (start_reg != reg)
9477 arm_output_fldmx (f, IP_REGNUM,
9478 (start_reg - FIRST_VFP_REGNUM) / 2,
9479 (reg - start_reg) / 2);
9480 start_reg = reg + 2;
9483 if (start_reg != reg)
9484 arm_output_fldmx (f, IP_REGNUM,
9485 (start_reg - FIRST_VFP_REGNUM) / 2,
9486 (reg - start_reg) / 2);
9491 /* The frame pointer is guaranteed to be non-double-word aligned.
9492 This is because it is set to (old_stack_pointer - 4) and the
9493 old_stack_pointer was double word aligned. Thus the offset to
9494 the iWMMXt registers to be loaded must also be non-double-word
9495 sized, so that the resultant address *is* double-word aligned.
9496 We can ignore floats_offset since that was already included in
9497 the live_regs_mask. */
9498 lrm_count += (lrm_count % 2 ? 2 : 1);
9500 for (reg = FIRST_IWMMXT_REGNUM; reg <= LAST_IWMMXT_REGNUM; reg++)
9501 if (regs_ever_live[reg] && !call_used_regs[reg])
9503 asm_fprintf (f, "\twldrd\t%r, [%r, #-%d]\n",
9504 reg, FP_REGNUM, lrm_count * 4);
9509 /* saved_regs_mask should contain the IP, which at the time of stack
9510 frame generation actually contains the old stack pointer. So a
9511 quick way to unwind the stack is just pop the IP register directly
9512 into the stack pointer. */
9513 if ((saved_regs_mask & (1 << IP_REGNUM)) == 0)
9515 saved_regs_mask &= ~ (1 << IP_REGNUM);
9516 saved_regs_mask |= (1 << SP_REGNUM);
9518 /* There are two registers left in saved_regs_mask - LR and PC. We
9519 only need to restore the LR register (the return address), but to
9520 save time we can load it directly into the PC, unless we need a
9521 special function exit sequence, or we are not really returning. */
9522 if (really_return && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL)
9523 /* Delete the LR from the register mask, so that the LR on
9524 the stack is loaded into the PC in the register mask. */
9525 saved_regs_mask &= ~ (1 << LR_REGNUM);
9527 saved_regs_mask &= ~ (1 << PC_REGNUM);
9529 /* We must use SP as the base register, because SP is one of the
9530 registers being restored. If an interrupt or page fault
9531 happens in the ldm instruction, the SP might or might not
9532 have been restored. That would be bad, as then SP will no
9533 longer indicate the safe area of stack, and we can get stack
9534 corruption. Using SP as the base register means that it will
9535 be reset correctly to the original value, should an interrupt
9536 occur. If the stack pointer already points at the right
9537 place, then omit the subtraction. */
9538 if (offsets->outgoing_args != (1 + (int) bit_count (saved_regs_mask))
9539 || current_function_calls_alloca)
9540 asm_fprintf (f, "\tsub\t%r, %r, #%d\n", SP_REGNUM, FP_REGNUM,
9541 4 * bit_count (saved_regs_mask));
9542 print_multi_reg (f, "ldmfd\t%r", SP_REGNUM, saved_regs_mask);
9544 if (IS_INTERRUPT (func_type))
9545 /* Interrupt handlers will have pushed the
9546 IP onto the stack, so restore it now. */
9547 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, 1 << IP_REGNUM);
9551 /* Restore stack pointer if necessary. */
9552 if (offsets->outgoing_args != offsets->saved_regs)
9554 operands[0] = operands[1] = stack_pointer_rtx;
9555 operands[2] = GEN_INT (offsets->outgoing_args - offsets->saved_regs);
9556 output_add_immediate (operands);
9559 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
9561 for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++)
9562 if (regs_ever_live[reg] && !call_used_regs[reg])
9563 asm_fprintf (f, "\tldfe\t%r, [%r], #12\n",
9568 start_reg = FIRST_FPA_REGNUM;
9570 for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++)
9572 if (regs_ever_live[reg] && !call_used_regs[reg])
9574 if (reg - start_reg == 3)
9576 asm_fprintf (f, "\tlfmfd\t%r, 4, [%r]!\n",
9577 start_reg, SP_REGNUM);
9578 start_reg = reg + 1;
9583 if (reg != start_reg)
9584 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
9585 start_reg, reg - start_reg,
9588 start_reg = reg + 1;
9592 /* Just in case the last register checked also needs unstacking. */
9593 if (reg != start_reg)
9594 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
9595 start_reg, reg - start_reg, SP_REGNUM);
9598 if (TARGET_HARD_FLOAT && TARGET_VFP)
9600 start_reg = FIRST_VFP_REGNUM;
9601 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
9603 if ((!regs_ever_live[reg] || call_used_regs[reg])
9604 && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1]))
9606 if (start_reg != reg)
9607 arm_output_fldmx (f, SP_REGNUM,
9608 (start_reg - FIRST_VFP_REGNUM) / 2,
9609 (reg - start_reg) / 2);
9610 start_reg = reg + 2;
9613 if (start_reg != reg)
9614 arm_output_fldmx (f, SP_REGNUM,
9615 (start_reg - FIRST_VFP_REGNUM) / 2,
9616 (reg - start_reg) / 2);
9619 for (reg = FIRST_IWMMXT_REGNUM; reg <= LAST_IWMMXT_REGNUM; reg++)
9620 if (regs_ever_live[reg] && !call_used_regs[reg])
9621 asm_fprintf (f, "\twldrd\t%r, [%r, #+8]!\n", reg, SP_REGNUM);
9623 /* If we can, restore the LR into the PC. */
9624 if (ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
9626 && current_function_pretend_args_size == 0
9627 && saved_regs_mask & (1 << LR_REGNUM))
9629 saved_regs_mask &= ~ (1 << LR_REGNUM);
9630 saved_regs_mask |= (1 << PC_REGNUM);
9633 /* Load the registers off the stack. If we only have one register
9634 to load use the LDR instruction - it is faster. */
9635 if (saved_regs_mask == (1 << LR_REGNUM))
9637 /* The exception handler ignores the LR, so we do
9638 not really need to load it off the stack. */
9640 asm_fprintf (f, "\tadd\t%r, %r, #4\n", SP_REGNUM, SP_REGNUM);
9642 asm_fprintf (f, "\tldr\t%r, [%r], #4\n", LR_REGNUM, SP_REGNUM);
9644 else if (saved_regs_mask)
9646 if (saved_regs_mask & (1 << SP_REGNUM))
9647 /* Note - write back to the stack register is not enabled
9648 (ie "ldmfd sp!..."). We know that the stack pointer is
9649 in the list of registers and if we add writeback the
9650 instruction becomes UNPREDICTABLE. */
9651 print_multi_reg (f, "ldmfd\t%r", SP_REGNUM, saved_regs_mask);
9653 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, saved_regs_mask);
9656 if (current_function_pretend_args_size)
9658 /* Unwind the pre-pushed regs. */
9659 operands[0] = operands[1] = stack_pointer_rtx;
9660 operands[2] = GEN_INT (current_function_pretend_args_size);
9661 output_add_immediate (operands);
9666 || (ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
9667 && current_function_pretend_args_size == 0
9668 && saved_regs_mask & (1 << PC_REGNUM)))
9671 /* Generate the return instruction. */
9672 switch ((int) ARM_FUNC_TYPE (func_type))
9674 case ARM_FT_EXCEPTION_HANDLER:
9675 /* Even in 26-bit mode we do a mov (rather than a movs)
9676 because we don't have the PSR bits set in the address. */
9677 asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, EXCEPTION_LR_REGNUM);
9682 asm_fprintf (f, "\tsubs\t%r, %r, #4\n", PC_REGNUM, LR_REGNUM);
9685 case ARM_FT_EXCEPTION:
9686 asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM);
9689 case ARM_FT_INTERWORKED:
9690 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
9694 if (frame_pointer_needed)
9695 /* If we used the frame pointer then the return address
9696 will have been loaded off the stack directly into the
9697 PC, so there is no need to issue a MOV instruction
9700 else if (current_function_pretend_args_size == 0
9701 && (saved_regs_mask & (1 << LR_REGNUM)))
9702 /* Similarly we may have been able to load LR into the PC
9703 even if we did not create a stack frame. */
9705 else if (TARGET_APCS_32)
9706 asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, LR_REGNUM);
9708 asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM);
9716 arm_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
9717 HOST_WIDE_INT frame_size ATTRIBUTE_UNUSED)
9719 arm_stack_offsets *offsets;
9723 /* ??? Probably not safe to set this here, since it assumes that a
9724 function will be emitted as assembly immediately after we generate
9725 RTL for it. This does not happen for inline functions. */
9726 return_used_this_function = 0;
9730 /* We need to take into account any stack-frame rounding. */
9731 offsets = arm_get_frame_offsets ();
9733 if (use_return_insn (FALSE, NULL)
9734 && return_used_this_function
9735 && offsets->saved_regs != offsets->outgoing_args
9736 && !frame_pointer_needed)
9739 /* Reset the ARM-specific per-function variables. */
9740 after_arm_reorg = 0;
9744 /* Generate and emit an insn that we will recognize as a push_multi.
9745 Unfortunately, since this insn does not reflect very well the actual
9746 semantics of the operation, we need to annotate the insn for the benefit
9747 of DWARF2 frame unwind information. */
9749 emit_multi_reg_push (int mask)
9756 int dwarf_par_index;
9759 for (i = 0; i <= LAST_ARM_REGNUM; i++)
9760 if (mask & (1 << i))
9763 if (num_regs == 0 || num_regs > 16)
9766 /* We don't record the PC in the dwarf frame information. */
9767 num_dwarf_regs = num_regs;
9768 if (mask & (1 << PC_REGNUM))
9771 /* For the body of the insn we are going to generate an UNSPEC in
9772 parallel with several USEs. This allows the insn to be recognized
9773 by the push_multi pattern in the arm.md file. The insn looks
9774 something like this:
9777 (set (mem:BLK (pre_dec:BLK (reg:SI sp)))
9778 (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT))
9779 (use (reg:SI 11 fp))
9780 (use (reg:SI 12 ip))
9781 (use (reg:SI 14 lr))
9782 (use (reg:SI 15 pc))
9785 For the frame note however, we try to be more explicit and actually
9786 show each register being stored into the stack frame, plus a (single)
9787 decrement of the stack pointer. We do it this way in order to be
9788 friendly to the stack unwinding code, which only wants to see a single
9789 stack decrement per instruction. The RTL we generate for the note looks
9790 something like this:
9793 (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20)))
9794 (set (mem:SI (reg:SI sp)) (reg:SI r4))
9795 (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp))
9796 (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip))
9797 (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr))
9800 This sequence is used both by the code to support stack unwinding for
9801 exceptions handlers and the code to generate dwarf2 frame debugging. */
9803 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_regs));
9804 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (num_dwarf_regs + 1));
9805 dwarf_par_index = 1;
9807 for (i = 0; i <= LAST_ARM_REGNUM; i++)
9809 if (mask & (1 << i))
9811 reg = gen_rtx_REG (SImode, i);
9814 = gen_rtx_SET (VOIDmode,
9815 gen_rtx_MEM (BLKmode,
9816 gen_rtx_PRE_DEC (BLKmode,
9817 stack_pointer_rtx)),
9818 gen_rtx_UNSPEC (BLKmode,
9824 tmp = gen_rtx_SET (VOIDmode,
9825 gen_rtx_MEM (SImode, stack_pointer_rtx),
9827 RTX_FRAME_RELATED_P (tmp) = 1;
9828 XVECEXP (dwarf, 0, dwarf_par_index) = tmp;
9836 for (j = 1, i++; j < num_regs; i++)
9838 if (mask & (1 << i))
9840 reg = gen_rtx_REG (SImode, i);
9842 XVECEXP (par, 0, j) = gen_rtx_USE (VOIDmode, reg);
9846 tmp = gen_rtx_SET (VOIDmode,
9847 gen_rtx_MEM (SImode,
9848 plus_constant (stack_pointer_rtx,
9851 RTX_FRAME_RELATED_P (tmp) = 1;
9852 XVECEXP (dwarf, 0, dwarf_par_index++) = tmp;
9859 par = emit_insn (par);
9861 tmp = gen_rtx_SET (SImode,
9863 gen_rtx_PLUS (SImode,
9865 GEN_INT (-4 * num_regs)));
9866 RTX_FRAME_RELATED_P (tmp) = 1;
9867 XVECEXP (dwarf, 0, 0) = tmp;
9869 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
9875 emit_sfm (int base_reg, int count)
9882 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
9883 dwarf = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
9885 reg = gen_rtx_REG (XFmode, base_reg++);
9888 = gen_rtx_SET (VOIDmode,
9889 gen_rtx_MEM (BLKmode,
9890 gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
9891 gen_rtx_UNSPEC (BLKmode,
9895 = gen_rtx_SET (VOIDmode,
9896 gen_rtx_MEM (XFmode,
9897 gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
9899 RTX_FRAME_RELATED_P (tmp) = 1;
9900 XVECEXP (dwarf, 0, count - 1) = tmp;
9902 for (i = 1; i < count; i++)
9904 reg = gen_rtx_REG (XFmode, base_reg++);
9905 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
9907 tmp = gen_rtx_SET (VOIDmode,
9908 gen_rtx_MEM (XFmode,
9909 gen_rtx_PRE_DEC (BLKmode,
9910 stack_pointer_rtx)),
9912 RTX_FRAME_RELATED_P (tmp) = 1;
9913 XVECEXP (dwarf, 0, count - i - 1) = tmp;
9916 par = emit_insn (par);
9917 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
9923 /* Compute the distance from register FROM to register TO.
9924 These can be the arg pointer (26), the soft frame pointer (25),
9925 the stack pointer (13) or the hard frame pointer (11).
9926 Typical stack layout looks like this:
9928 old stack pointer -> | |
9931 | | saved arguments for
9932 | | vararg functions
9935 hard FP & arg pointer -> | | \
9943 soft frame pointer -> | | /
9953 current stack pointer -> | | /
9956 For a given function some or all of these stack components
9957 may not be needed, giving rise to the possibility of
9958 eliminating some of the registers.
9960 The values returned by this function must reflect the behavior
9961 of arm_expand_prologue() and arm_compute_save_reg_mask().
9963 The sign of the number returned reflects the direction of stack
9964 growth, so the values are positive for all eliminations except
9965 from the soft frame pointer to the hard frame pointer.
9967 SFP may point just inside the local variables block to ensure correct
9971 /* Calculate stack offsets. These are used to calculate register elimination
9972 offsets and in prologue/epilogue code. */
9974 static arm_stack_offsets *
9975 arm_get_frame_offsets (void)
9977 struct arm_stack_offsets *offsets;
9978 unsigned long func_type;
9981 HOST_WIDE_INT frame_size;
9983 offsets = &cfun->machine->stack_offsets;
9985 /* We need to know if we are a leaf function. Unfortunately, it
9986 is possible to be called after start_sequence has been called,
9987 which causes get_insns to return the insns for the sequence,
9988 not the function, which will cause leaf_function_p to return
9989 the incorrect result.
9991 to know about leaf functions once reload has completed, and the
9992 frame size cannot be changed after that time, so we can safely
9993 use the cached value. */
9995 if (reload_completed)
9998 /* Initially this is the size of the local variables. It will translated
9999 into an offset once we have determined the size of preceding data. */
10000 frame_size = ROUND_UP_WORD (get_frame_size ());
10002 leaf = leaf_function_p ();
10004 /* Space for variadic functions. */
10005 offsets->saved_args = current_function_pretend_args_size;
10007 offsets->frame = offsets->saved_args + (frame_pointer_needed ? 4 : 0);
10011 unsigned int regno;
10013 saved = bit_count (arm_compute_save_reg_mask ()) * 4;
10015 /* We know that SP will be doubleword aligned on entry, and we must
10016 preserve that condition at any subroutine call. We also require the
10017 soft frame pointer to be doubleword aligned. */
10019 if (TARGET_REALLY_IWMMXT)
10021 /* Check for the call-saved iWMMXt registers. */
10022 for (regno = FIRST_IWMMXT_REGNUM;
10023 regno <= LAST_IWMMXT_REGNUM;
10025 if (regs_ever_live [regno] && ! call_used_regs [regno])
10029 func_type = arm_current_func_type ();
10030 if (! IS_VOLATILE (func_type))
10032 /* Space for saved FPA registers. */
10033 for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++)
10034 if (regs_ever_live[regno] && ! call_used_regs[regno])
10037 /* Space for saved VFP registers. */
10038 if (TARGET_HARD_FLOAT && TARGET_VFP)
10039 saved += arm_get_vfp_saved_size ();
10042 else /* TARGET_THUMB */
10049 for (reg = 8; reg < 13; reg ++)
10050 if (THUMB_REG_PUSHED_P (reg))
10053 saved += 4 * count_regs;
10055 for (reg = 0; reg <= LAST_LO_REGNUM; reg ++)
10056 if (THUMB_REG_PUSHED_P (reg))
10058 if (count_regs || ! leaf_function_p ()
10059 || thumb_far_jump_used_p ())
10060 saved += 4 * (count_regs + 1);
10061 if (TARGET_BACKTRACE)
10063 if ((count_regs & 0xFF) == 0 && (regs_ever_live[3] != 0))
10070 /* Saved registers include the stack frame. */
10071 offsets->saved_regs = offsets->saved_args + saved;
10072 offsets->soft_frame = offsets->saved_regs;
10073 /* A leaf function does not need any stack alignment if it has nothing
10075 if (leaf && frame_size == 0)
10077 offsets->outgoing_args = offsets->soft_frame;
10081 /* Ensure SFP has the correct alignment. */
10082 if (ARM_DOUBLEWORD_ALIGN
10083 && (offsets->soft_frame & 7))
10084 offsets->soft_frame += 4;
10086 offsets->outgoing_args = offsets->soft_frame + frame_size
10087 + current_function_outgoing_args_size;
10089 if (ARM_DOUBLEWORD_ALIGN)
10091 /* Ensure SP remains doubleword aligned. */
10092 if (offsets->outgoing_args & 7)
10093 offsets->outgoing_args += 4;
10094 if (offsets->outgoing_args & 7)
10102 /* Calculate the relative offsets for the different stack pointers. Positive
10103 offsets are in the direction of stack growth. */
10106 arm_compute_initial_elimination_offset (unsigned int from, unsigned int to)
10108 arm_stack_offsets *offsets;
10110 offsets = arm_get_frame_offsets ();
10112 /* OK, now we have enough information to compute the distances.
10113 There must be an entry in these switch tables for each pair
10114 of registers in ELIMINABLE_REGS, even if some of the entries
10115 seem to be redundant or useless. */
10118 case ARG_POINTER_REGNUM:
10121 case THUMB_HARD_FRAME_POINTER_REGNUM:
10124 case FRAME_POINTER_REGNUM:
10125 /* This is the reverse of the soft frame pointer
10126 to hard frame pointer elimination below. */
10127 return offsets->soft_frame - offsets->saved_args;
10129 case ARM_HARD_FRAME_POINTER_REGNUM:
10130 /* If there is no stack frame then the hard
10131 frame pointer and the arg pointer coincide. */
10132 if (offsets->frame == offsets->saved_regs)
10134 /* FIXME: Not sure about this. Maybe we should always return 0 ? */
10135 return (frame_pointer_needed
10136 && current_function_needs_context
10137 && ! cfun->machine->uses_anonymous_args) ? 4 : 0;
10139 case STACK_POINTER_REGNUM:
10140 /* If nothing has been pushed on the stack at all
10141 then this will return -4. This *is* correct! */
10142 return offsets->outgoing_args - (offsets->saved_args + 4);
10149 case FRAME_POINTER_REGNUM:
10152 case THUMB_HARD_FRAME_POINTER_REGNUM:
10155 case ARM_HARD_FRAME_POINTER_REGNUM:
10156 /* The hard frame pointer points to the top entry in the
10157 stack frame. The soft frame pointer to the bottom entry
10158 in the stack frame. If there is no stack frame at all,
10159 then they are identical. */
10161 return offsets->frame - offsets->soft_frame;
10163 case STACK_POINTER_REGNUM:
10164 return offsets->outgoing_args - offsets->soft_frame;
10172 /* You cannot eliminate from the stack pointer.
10173 In theory you could eliminate from the hard frame
10174 pointer to the stack pointer, but this will never
10175 happen, since if a stack frame is not needed the
10176 hard frame pointer will never be used. */
10182 /* Generate the prologue instructions for entry into an ARM function. */
10184 arm_expand_prologue (void)
10190 unsigned long live_regs_mask;
10191 unsigned long func_type;
10193 int saved_pretend_args = 0;
10194 int saved_regs = 0;
10195 unsigned int args_to_push;
10196 arm_stack_offsets *offsets;
10198 func_type = arm_current_func_type ();
10200 /* Naked functions don't have prologues. */
10201 if (IS_NAKED (func_type))
10204 /* Make a copy of c_f_p_a_s as we may need to modify it locally. */
10205 args_to_push = current_function_pretend_args_size;
10207 /* Compute which register we will have to save onto the stack. */
10208 live_regs_mask = arm_compute_save_reg_mask ();
10210 ip_rtx = gen_rtx_REG (SImode, IP_REGNUM);
10212 if (frame_pointer_needed)
10214 if (IS_INTERRUPT (func_type))
10216 /* Interrupt functions must not corrupt any registers.
10217 Creating a frame pointer however, corrupts the IP
10218 register, so we must push it first. */
10219 insn = emit_multi_reg_push (1 << IP_REGNUM);
10221 /* Do not set RTX_FRAME_RELATED_P on this insn.
10222 The dwarf stack unwinding code only wants to see one
10223 stack decrement per function, and this is not it. If
10224 this instruction is labeled as being part of the frame
10225 creation sequence then dwarf2out_frame_debug_expr will
10226 abort when it encounters the assignment of IP to FP
10227 later on, since the use of SP here establishes SP as
10228 the CFA register and not IP.
10230 Anyway this instruction is not really part of the stack
10231 frame creation although it is part of the prologue. */
10233 else if (IS_NESTED (func_type))
10235 /* The Static chain register is the same as the IP register
10236 used as a scratch register during stack frame creation.
10237 To get around this need to find somewhere to store IP
10238 whilst the frame is being created. We try the following
10241 1. The last argument register.
10242 2. A slot on the stack above the frame. (This only
10243 works if the function is not a varargs function).
10244 3. Register r3, after pushing the argument registers
10247 Note - we only need to tell the dwarf2 backend about the SP
10248 adjustment in the second variant; the static chain register
10249 doesn't need to be unwound, as it doesn't contain a value
10250 inherited from the caller. */
10252 if (regs_ever_live[3] == 0)
10254 insn = gen_rtx_REG (SImode, 3);
10255 insn = gen_rtx_SET (SImode, insn, ip_rtx);
10256 insn = emit_insn (insn);
10258 else if (args_to_push == 0)
10261 insn = gen_rtx_PRE_DEC (SImode, stack_pointer_rtx);
10262 insn = gen_rtx_MEM (SImode, insn);
10263 insn = gen_rtx_SET (VOIDmode, insn, ip_rtx);
10264 insn = emit_insn (insn);
10268 /* Just tell the dwarf backend that we adjusted SP. */
10269 dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
10270 gen_rtx_PLUS (SImode, stack_pointer_rtx,
10271 GEN_INT (-fp_offset)));
10272 RTX_FRAME_RELATED_P (insn) = 1;
10273 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
10274 dwarf, REG_NOTES (insn));
10278 /* Store the args on the stack. */
10279 if (cfun->machine->uses_anonymous_args)
10280 insn = emit_multi_reg_push
10281 ((0xf0 >> (args_to_push / 4)) & 0xf);
10284 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
10285 GEN_INT (- args_to_push)));
10287 RTX_FRAME_RELATED_P (insn) = 1;
10289 saved_pretend_args = 1;
10290 fp_offset = args_to_push;
10293 /* Now reuse r3 to preserve IP. */
10294 insn = gen_rtx_REG (SImode, 3);
10295 insn = gen_rtx_SET (SImode, insn, ip_rtx);
10296 (void) emit_insn (insn);
10302 insn = gen_rtx_PLUS (SImode, stack_pointer_rtx, GEN_INT (fp_offset));
10303 insn = gen_rtx_SET (SImode, ip_rtx, insn);
10306 insn = gen_movsi (ip_rtx, stack_pointer_rtx);
10308 insn = emit_insn (insn);
10309 RTX_FRAME_RELATED_P (insn) = 1;
10314 /* Push the argument registers, or reserve space for them. */
10315 if (cfun->machine->uses_anonymous_args)
10316 insn = emit_multi_reg_push
10317 ((0xf0 >> (args_to_push / 4)) & 0xf);
10320 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
10321 GEN_INT (- args_to_push)));
10322 RTX_FRAME_RELATED_P (insn) = 1;
10325 /* If this is an interrupt service routine, and the link register
10326 is going to be pushed, and we are not creating a stack frame,
10327 (which would involve an extra push of IP and a pop in the epilogue)
10328 subtracting four from LR now will mean that the function return
10329 can be done with a single instruction. */
10330 if ((func_type == ARM_FT_ISR || func_type == ARM_FT_FIQ)
10331 && (live_regs_mask & (1 << LR_REGNUM)) != 0
10332 && ! frame_pointer_needed)
10333 emit_insn (gen_rtx_SET (SImode,
10334 gen_rtx_REG (SImode, LR_REGNUM),
10335 gen_rtx_PLUS (SImode,
10336 gen_rtx_REG (SImode, LR_REGNUM),
10339 if (live_regs_mask)
10341 insn = emit_multi_reg_push (live_regs_mask);
10342 saved_regs += bit_count (live_regs_mask) * 4;
10343 RTX_FRAME_RELATED_P (insn) = 1;
10347 for (reg = FIRST_IWMMXT_REGNUM; reg <= LAST_IWMMXT_REGNUM; reg++)
10348 if (regs_ever_live[reg] && ! call_used_regs [reg])
10350 insn = gen_rtx_PRE_DEC (V2SImode, stack_pointer_rtx);
10351 insn = gen_rtx_MEM (V2SImode, insn);
10352 insn = emit_insn (gen_rtx_SET (VOIDmode, insn,
10353 gen_rtx_REG (V2SImode, reg)));
10354 RTX_FRAME_RELATED_P (insn) = 1;
10358 if (! IS_VOLATILE (func_type))
10362 /* Save any floating point call-saved registers used by this
10364 if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
10366 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
10367 if (regs_ever_live[reg] && !call_used_regs[reg])
10369 insn = gen_rtx_PRE_DEC (XFmode, stack_pointer_rtx);
10370 insn = gen_rtx_MEM (XFmode, insn);
10371 insn = emit_insn (gen_rtx_SET (VOIDmode, insn,
10372 gen_rtx_REG (XFmode, reg)));
10373 RTX_FRAME_RELATED_P (insn) = 1;
10379 start_reg = LAST_FPA_REGNUM;
10381 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
10383 if (regs_ever_live[reg] && !call_used_regs[reg])
10385 if (start_reg - reg == 3)
10387 insn = emit_sfm (reg, 4);
10388 RTX_FRAME_RELATED_P (insn) = 1;
10389 start_reg = reg - 1;
10394 if (start_reg != reg)
10396 insn = emit_sfm (reg + 1, start_reg - reg);
10397 RTX_FRAME_RELATED_P (insn) = 1;
10398 saved_regs += (reg - start_reg) * 12;
10400 start_reg = reg - 1;
10404 if (start_reg != reg)
10406 insn = emit_sfm (reg + 1, start_reg - reg);
10407 saved_regs += (reg - start_reg) * 12;
10408 RTX_FRAME_RELATED_P (insn) = 1;
10411 if (TARGET_HARD_FLOAT && TARGET_VFP)
10413 start_reg = FIRST_VFP_REGNUM;
10415 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2)
10417 if ((!regs_ever_live[reg] || call_used_regs[reg])
10418 && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1]))
10420 if (start_reg != reg)
10421 saved_regs += vfp_emit_fstmx (start_reg,
10422 (reg - start_reg) / 2);
10423 start_reg = reg + 2;
10426 if (start_reg != reg)
10427 saved_regs += vfp_emit_fstmx (start_reg,
10428 (reg - start_reg) / 2);
10432 if (frame_pointer_needed)
10434 /* Create the new frame pointer. */
10435 insn = GEN_INT (-(4 + args_to_push + fp_offset));
10436 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, ip_rtx, insn));
10437 RTX_FRAME_RELATED_P (insn) = 1;
10439 if (IS_NESTED (func_type))
10441 /* Recover the static chain register. */
10442 if (regs_ever_live [3] == 0
10443 || saved_pretend_args)
10444 insn = gen_rtx_REG (SImode, 3);
10445 else /* if (current_function_pretend_args_size == 0) */
10447 insn = gen_rtx_PLUS (SImode, hard_frame_pointer_rtx,
10449 insn = gen_rtx_MEM (SImode, insn);
10452 emit_insn (gen_rtx_SET (SImode, ip_rtx, insn));
10453 /* Add a USE to stop propagate_one_insn() from barfing. */
10454 emit_insn (gen_prologue_use (ip_rtx));
10458 offsets = arm_get_frame_offsets ();
10459 if (offsets->outgoing_args != offsets->saved_args + saved_regs)
10461 /* This add can produce multiple insns for a large constant, so we
10462 need to get tricky. */
10463 rtx last = get_last_insn ();
10465 amount = GEN_INT (offsets->saved_args + saved_regs
10466 - offsets->outgoing_args);
10468 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
10472 last = last ? NEXT_INSN (last) : get_insns ();
10473 RTX_FRAME_RELATED_P (last) = 1;
10475 while (last != insn);
10477 /* If the frame pointer is needed, emit a special barrier that
10478 will prevent the scheduler from moving stores to the frame
10479 before the stack adjustment. */
10480 if (frame_pointer_needed)
10481 insn = emit_insn (gen_stack_tie (stack_pointer_rtx,
10482 hard_frame_pointer_rtx));
10485 /* If we are profiling, make sure no instructions are scheduled before
10486 the call to mcount. Similarly if the user has requested no
10487 scheduling in the prolog. */
10488 if (current_function_profile || TARGET_NO_SCHED_PRO)
10489 emit_insn (gen_blockage ());
10491 /* If the link register is being kept alive, with the return address in it,
10492 then make sure that it does not get reused by the ce2 pass. */
10493 if ((live_regs_mask & (1 << LR_REGNUM)) == 0)
10495 emit_insn (gen_prologue_use (gen_rtx_REG (SImode, LR_REGNUM)));
10496 cfun->machine->lr_save_eliminated = 1;
10500 /* If CODE is 'd', then the X is a condition operand and the instruction
10501 should only be executed if the condition is true.
10502 if CODE is 'D', then the X is a condition operand and the instruction
10503 should only be executed if the condition is false: however, if the mode
10504 of the comparison is CCFPEmode, then always execute the instruction -- we
10505 do this because in these circumstances !GE does not necessarily imply LT;
10506 in these cases the instruction pattern will take care to make sure that
10507 an instruction containing %d will follow, thereby undoing the effects of
10508 doing this instruction unconditionally.
10509 If CODE is 'N' then X is a floating point operand that must be negated
10511 If CODE is 'B' then output a bitwise inverted value of X (a const int).
10512 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
10514 arm_print_operand (FILE *stream, rtx x, int code)
10519 fputs (ASM_COMMENT_START, stream);
10523 fputs (user_label_prefix, stream);
10527 fputs (REGISTER_PREFIX, stream);
10531 if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4)
10533 if (TARGET_THUMB || current_insn_predicate != NULL)
10536 fputs (arm_condition_codes[arm_current_cc], stream);
10538 else if (current_insn_predicate)
10540 enum arm_cond_code code;
10545 code = get_arm_condition_code (current_insn_predicate);
10546 fputs (arm_condition_codes[code], stream);
10553 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
10554 r = REAL_VALUE_NEGATE (r);
10555 fprintf (stream, "%s", fp_const_from_val (&r));
10560 if (GET_CODE (x) == CONST_INT)
10563 val = ARM_SIGN_EXTEND (~INTVAL (x));
10564 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val);
10568 putc ('~', stream);
10569 output_addr_const (stream, x);
10574 fprintf (stream, "%s", arithmetic_instr (x, 1));
10577 /* Truncate Cirrus shift counts. */
10579 if (GET_CODE (x) == CONST_INT)
10581 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0x3f);
10584 arm_print_operand (stream, x, 0);
10588 fprintf (stream, "%s", arithmetic_instr (x, 0));
10594 const char * shift = shift_op (x, &val);
10598 fprintf (stream, ", %s ", shift_op (x, &val));
10600 arm_print_operand (stream, XEXP (x, 1), 0);
10602 fprintf (stream, "#" HOST_WIDE_INT_PRINT_DEC, val);
10607 /* An explanation of the 'Q', 'R' and 'H' register operands:
10609 In a pair of registers containing a DI or DF value the 'Q'
10610 operand returns the register number of the register containing
10611 the least significant part of the value. The 'R' operand returns
10612 the register number of the register containing the most
10613 significant part of the value.
10615 The 'H' operand returns the higher of the two register numbers.
10616 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
10617 same as the 'Q' operand, since the most significant part of the
10618 value is held in the lower number register. The reverse is true
10619 on systems where WORDS_BIG_ENDIAN is false.
10621 The purpose of these operands is to distinguish between cases
10622 where the endian-ness of the values is important (for example
10623 when they are added together), and cases where the endian-ness
10624 is irrelevant, but the order of register operations is important.
10625 For example when loading a value from memory into a register
10626 pair, the endian-ness does not matter. Provided that the value
10627 from the lower memory address is put into the lower numbered
10628 register, and the value from the higher address is put into the
10629 higher numbered register, the load will work regardless of whether
10630 the value being loaded is big-wordian or little-wordian. The
10631 order of the two register loads can matter however, if the address
10632 of the memory location is actually held in one of the registers
10633 being overwritten by the load. */
10635 if (REGNO (x) > LAST_ARM_REGNUM)
10637 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0));
10641 if (REGNO (x) > LAST_ARM_REGNUM)
10643 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1));
10647 if (REGNO (x) > LAST_ARM_REGNUM)
10649 asm_fprintf (stream, "%r", REGNO (x) + 1);
10653 asm_fprintf (stream, "%r",
10654 GET_CODE (XEXP (x, 0)) == REG
10655 ? REGNO (XEXP (x, 0)) : REGNO (XEXP (XEXP (x, 0), 0)));
10659 asm_fprintf (stream, "{%r-%r}",
10661 REGNO (x) + ARM_NUM_REGS (GET_MODE (x)) - 1);
10665 /* CONST_TRUE_RTX means always -- that's the default. */
10666 if (x == const_true_rtx)
10669 fputs (arm_condition_codes[get_arm_condition_code (x)],
10674 /* CONST_TRUE_RTX means not always -- ie never. We shouldn't ever
10675 want to do that. */
10676 if (x == const_true_rtx)
10679 fputs (arm_condition_codes[ARM_INVERSE_CONDITION_CODE
10680 (get_arm_condition_code (x))],
10684 /* Cirrus registers can be accessed in a variety of ways:
10685 single floating point (f)
10686 double floating point (d)
10688 64bit integer (dx). */
10689 case 'W': /* Cirrus register in F mode. */
10690 case 'X': /* Cirrus register in D mode. */
10691 case 'Y': /* Cirrus register in FX mode. */
10692 case 'Z': /* Cirrus register in DX mode. */
10693 if (GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) != CIRRUS_REGS)
10696 fprintf (stream, "mv%s%s",
10698 : code == 'X' ? "d"
10699 : code == 'Y' ? "fx" : "dx", reg_names[REGNO (x)] + 2);
10703 /* Print cirrus register in the mode specified by the register's mode. */
10706 int mode = GET_MODE (x);
10708 if (GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) != CIRRUS_REGS)
10711 fprintf (stream, "mv%s%s",
10712 mode == DFmode ? "d"
10713 : mode == SImode ? "fx"
10714 : mode == DImode ? "dx"
10715 : "f", reg_names[REGNO (x)] + 2);
10721 if (GET_CODE (x) != REG
10722 || REGNO (x) < FIRST_IWMMXT_GR_REGNUM
10723 || REGNO (x) > LAST_IWMMXT_GR_REGNUM)
10724 /* Bad value for wCG register number. */
10727 fprintf (stream, "%d", REGNO (x) - FIRST_IWMMXT_GR_REGNUM);
10730 /* Print an iWMMXt control register name. */
10732 if (GET_CODE (x) != CONST_INT
10734 || INTVAL (x) >= 16)
10735 /* Bad value for wC register number. */
10739 static const char * wc_reg_names [16] =
10741 "wCID", "wCon", "wCSSF", "wCASF",
10742 "wC4", "wC5", "wC6", "wC7",
10743 "wCGR0", "wCGR1", "wCGR2", "wCGR3",
10744 "wC12", "wC13", "wC14", "wC15"
10747 fprintf (stream, wc_reg_names [INTVAL (x)]);
10751 /* Print a VFP double precision register name. */
10754 int mode = GET_MODE (x);
10757 if (mode != DImode && mode != DFmode)
10760 if (GET_CODE (x) != REG
10761 || !IS_VFP_REGNUM (REGNO (x)))
10764 num = REGNO(x) - FIRST_VFP_REGNUM;
10768 fprintf (stream, "d%d", num >> 1);
10776 if (GET_CODE (x) == REG)
10777 asm_fprintf (stream, "%r", REGNO (x));
10778 else if (GET_CODE (x) == MEM)
10780 output_memory_reference_mode = GET_MODE (x);
10781 output_address (XEXP (x, 0));
10783 else if (GET_CODE (x) == CONST_DOUBLE)
10784 fprintf (stream, "#%s", fp_immediate_constant (x));
10785 else if (GET_CODE (x) == NEG)
10786 abort (); /* This should never happen now. */
10789 fputc ('#', stream);
10790 output_addr_const (stream, x);
10795 #ifndef AOF_ASSEMBLER
10796 /* Target hook for assembling integer objects. The ARM version needs to
10797 handle word-sized values specially. */
10799 arm_assemble_integer (rtx x, unsigned int size, int aligned_p)
10801 if (size == UNITS_PER_WORD && aligned_p)
10803 fputs ("\t.word\t", asm_out_file);
10804 output_addr_const (asm_out_file, x);
10806 /* Mark symbols as position independent. We only do this in the
10807 .text segment, not in the .data segment. */
10808 if (NEED_GOT_RELOC && flag_pic && making_const_table &&
10809 (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF))
10811 if (GET_CODE (x) == SYMBOL_REF
10812 && (CONSTANT_POOL_ADDRESS_P (x)
10813 || SYMBOL_REF_LOCAL_P (x)))
10814 fputs ("(GOTOFF)", asm_out_file);
10815 else if (GET_CODE (x) == LABEL_REF)
10816 fputs ("(GOTOFF)", asm_out_file);
10818 fputs ("(GOT)", asm_out_file);
10820 fputc ('\n', asm_out_file);
10824 if (VECTOR_MODE_SUPPORTED_P (GET_MODE (x)))
10828 if (GET_CODE (x) != CONST_VECTOR)
10831 units = CONST_VECTOR_NUNITS (x);
10833 switch (GET_MODE (x))
10835 case V2SImode: size = 4; break;
10836 case V4HImode: size = 2; break;
10837 case V8QImode: size = 1; break;
10842 for (i = 0; i < units; i++)
10846 elt = CONST_VECTOR_ELT (x, i);
10848 (elt, size, i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT, 1);
10854 return default_assemble_integer (x, size, aligned_p);
10858 /* A finite state machine takes care of noticing whether or not instructions
10859 can be conditionally executed, and thus decrease execution time and code
10860 size by deleting branch instructions. The fsm is controlled by
10861 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
10863 /* The state of the fsm controlling condition codes are:
10864 0: normal, do nothing special
10865 1: make ASM_OUTPUT_OPCODE not output this instruction
10866 2: make ASM_OUTPUT_OPCODE not output this instruction
10867 3: make instructions conditional
10868 4: make instructions conditional
10870 State transitions (state->state by whom under condition):
10871 0 -> 1 final_prescan_insn if the `target' is a label
10872 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
10873 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
10874 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
10875 3 -> 0 (*targetm.asm_out.internal_label) if the `target' label is reached
10876 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
10877 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
10878 (the target insn is arm_target_insn).
10880 If the jump clobbers the conditions then we use states 2 and 4.
10882 A similar thing can be done with conditional return insns.
10884 XXX In case the `target' is an unconditional branch, this conditionalising
10885 of the instructions always reduces code size, but not always execution
10886 time. But then, I want to reduce the code size to somewhere near what
10887 /bin/cc produces. */
10889 /* Returns the index of the ARM condition code string in
10890 `arm_condition_codes'. COMPARISON should be an rtx like
10891 `(eq (...) (...))'. */
10892 static enum arm_cond_code
10893 get_arm_condition_code (rtx comparison)
10895 enum machine_mode mode = GET_MODE (XEXP (comparison, 0));
10897 enum rtx_code comp_code = GET_CODE (comparison);
10899 if (GET_MODE_CLASS (mode) != MODE_CC)
10900 mode = SELECT_CC_MODE (comp_code, XEXP (comparison, 0),
10901 XEXP (comparison, 1));
10905 case CC_DNEmode: code = ARM_NE; goto dominance;
10906 case CC_DEQmode: code = ARM_EQ; goto dominance;
10907 case CC_DGEmode: code = ARM_GE; goto dominance;
10908 case CC_DGTmode: code = ARM_GT; goto dominance;
10909 case CC_DLEmode: code = ARM_LE; goto dominance;
10910 case CC_DLTmode: code = ARM_LT; goto dominance;
10911 case CC_DGEUmode: code = ARM_CS; goto dominance;
10912 case CC_DGTUmode: code = ARM_HI; goto dominance;
10913 case CC_DLEUmode: code = ARM_LS; goto dominance;
10914 case CC_DLTUmode: code = ARM_CC;
10917 if (comp_code != EQ && comp_code != NE)
10920 if (comp_code == EQ)
10921 return ARM_INVERSE_CONDITION_CODE (code);
10927 case NE: return ARM_NE;
10928 case EQ: return ARM_EQ;
10929 case GE: return ARM_PL;
10930 case LT: return ARM_MI;
10937 case NE: return ARM_NE;
10938 case EQ: return ARM_EQ;
10945 case NE: return ARM_MI;
10946 case EQ: return ARM_PL;
10952 /* These encodings assume that AC=1 in the FPA system control
10953 byte. This allows us to handle all cases except UNEQ and
10957 case GE: return ARM_GE;
10958 case GT: return ARM_GT;
10959 case LE: return ARM_LS;
10960 case LT: return ARM_MI;
10961 case NE: return ARM_NE;
10962 case EQ: return ARM_EQ;
10963 case ORDERED: return ARM_VC;
10964 case UNORDERED: return ARM_VS;
10965 case UNLT: return ARM_LT;
10966 case UNLE: return ARM_LE;
10967 case UNGT: return ARM_HI;
10968 case UNGE: return ARM_PL;
10969 /* UNEQ and LTGT do not have a representation. */
10970 case UNEQ: /* Fall through. */
10971 case LTGT: /* Fall through. */
10978 case NE: return ARM_NE;
10979 case EQ: return ARM_EQ;
10980 case GE: return ARM_LE;
10981 case GT: return ARM_LT;
10982 case LE: return ARM_GE;
10983 case LT: return ARM_GT;
10984 case GEU: return ARM_LS;
10985 case GTU: return ARM_CC;
10986 case LEU: return ARM_CS;
10987 case LTU: return ARM_HI;
10994 case LTU: return ARM_CS;
10995 case GEU: return ARM_CC;
11002 case NE: return ARM_NE;
11003 case EQ: return ARM_EQ;
11004 case GE: return ARM_GE;
11005 case GT: return ARM_GT;
11006 case LE: return ARM_LE;
11007 case LT: return ARM_LT;
11008 case GEU: return ARM_CS;
11009 case GTU: return ARM_HI;
11010 case LEU: return ARM_LS;
11011 case LTU: return ARM_CC;
11022 arm_final_prescan_insn (rtx insn)
11024 /* BODY will hold the body of INSN. */
11025 rtx body = PATTERN (insn);
11027 /* This will be 1 if trying to repeat the trick, and things need to be
11028 reversed if it appears to fail. */
11031 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
11032 taken are clobbered, even if the rtl suggests otherwise. It also
11033 means that we have to grub around within the jump expression to find
11034 out what the conditions are when the jump isn't taken. */
11035 int jump_clobbers = 0;
11037 /* If we start with a return insn, we only succeed if we find another one. */
11038 int seeking_return = 0;
11040 /* START_INSN will hold the insn from where we start looking. This is the
11041 first insn after the following code_label if REVERSE is true. */
11042 rtx start_insn = insn;
11044 /* If in state 4, check if the target branch is reached, in order to
11045 change back to state 0. */
11046 if (arm_ccfsm_state == 4)
11048 if (insn == arm_target_insn)
11050 arm_target_insn = NULL;
11051 arm_ccfsm_state = 0;
11056 /* If in state 3, it is possible to repeat the trick, if this insn is an
11057 unconditional branch to a label, and immediately following this branch
11058 is the previous target label which is only used once, and the label this
11059 branch jumps to is not too far off. */
11060 if (arm_ccfsm_state == 3)
11062 if (simplejump_p (insn))
11064 start_insn = next_nonnote_insn (start_insn);
11065 if (GET_CODE (start_insn) == BARRIER)
11067 /* XXX Isn't this always a barrier? */
11068 start_insn = next_nonnote_insn (start_insn);
11070 if (GET_CODE (start_insn) == CODE_LABEL
11071 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
11072 && LABEL_NUSES (start_insn) == 1)
11077 else if (GET_CODE (body) == RETURN)
11079 start_insn = next_nonnote_insn (start_insn);
11080 if (GET_CODE (start_insn) == BARRIER)
11081 start_insn = next_nonnote_insn (start_insn);
11082 if (GET_CODE (start_insn) == CODE_LABEL
11083 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
11084 && LABEL_NUSES (start_insn) == 1)
11087 seeking_return = 1;
11096 if (arm_ccfsm_state != 0 && !reverse)
11098 if (GET_CODE (insn) != JUMP_INSN)
11101 /* This jump might be paralleled with a clobber of the condition codes
11102 the jump should always come first */
11103 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
11104 body = XVECEXP (body, 0, 0);
11107 || (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
11108 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE))
11111 int fail = FALSE, succeed = FALSE;
11112 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
11113 int then_not_else = TRUE;
11114 rtx this_insn = start_insn, label = 0;
11116 /* If the jump cannot be done with one instruction, we cannot
11117 conditionally execute the instruction in the inverse case. */
11118 if (get_attr_conds (insn) == CONDS_JUMP_CLOB)
11124 /* Register the insn jumped to. */
11127 if (!seeking_return)
11128 label = XEXP (SET_SRC (body), 0);
11130 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == LABEL_REF)
11131 label = XEXP (XEXP (SET_SRC (body), 1), 0);
11132 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == LABEL_REF)
11134 label = XEXP (XEXP (SET_SRC (body), 2), 0);
11135 then_not_else = FALSE;
11137 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN)
11138 seeking_return = 1;
11139 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN)
11141 seeking_return = 1;
11142 then_not_else = FALSE;
11147 /* See how many insns this branch skips, and what kind of insns. If all
11148 insns are okay, and the label or unconditional branch to the same
11149 label is not too far away, succeed. */
11150 for (insns_skipped = 0;
11151 !fail && !succeed && insns_skipped++ < max_insns_skipped;)
11155 this_insn = next_nonnote_insn (this_insn);
11159 switch (GET_CODE (this_insn))
11162 /* Succeed if it is the target label, otherwise fail since
11163 control falls in from somewhere else. */
11164 if (this_insn == label)
11168 arm_ccfsm_state = 2;
11169 this_insn = next_nonnote_insn (this_insn);
11172 arm_ccfsm_state = 1;
11180 /* Succeed if the following insn is the target label.
11182 If return insns are used then the last insn in a function
11183 will be a barrier. */
11184 this_insn = next_nonnote_insn (this_insn);
11185 if (this_insn && this_insn == label)
11189 arm_ccfsm_state = 2;
11190 this_insn = next_nonnote_insn (this_insn);
11193 arm_ccfsm_state = 1;
11201 /* If using 32-bit addresses the cc is not preserved over
11203 if (TARGET_APCS_32)
11205 /* Succeed if the following insn is the target label,
11206 or if the following two insns are a barrier and
11207 the target label. */
11208 this_insn = next_nonnote_insn (this_insn);
11209 if (this_insn && GET_CODE (this_insn) == BARRIER)
11210 this_insn = next_nonnote_insn (this_insn);
11212 if (this_insn && this_insn == label
11213 && insns_skipped < max_insns_skipped)
11217 arm_ccfsm_state = 2;
11218 this_insn = next_nonnote_insn (this_insn);
11221 arm_ccfsm_state = 1;
11230 /* If this is an unconditional branch to the same label, succeed.
11231 If it is to another label, do nothing. If it is conditional,
11233 /* XXX Probably, the tests for SET and the PC are
11236 scanbody = PATTERN (this_insn);
11237 if (GET_CODE (scanbody) == SET
11238 && GET_CODE (SET_DEST (scanbody)) == PC)
11240 if (GET_CODE (SET_SRC (scanbody)) == LABEL_REF
11241 && XEXP (SET_SRC (scanbody), 0) == label && !reverse)
11243 arm_ccfsm_state = 2;
11246 else if (GET_CODE (SET_SRC (scanbody)) == IF_THEN_ELSE)
11249 /* Fail if a conditional return is undesirable (eg on a
11250 StrongARM), but still allow this if optimizing for size. */
11251 else if (GET_CODE (scanbody) == RETURN
11252 && !use_return_insn (TRUE, NULL)
11255 else if (GET_CODE (scanbody) == RETURN
11258 arm_ccfsm_state = 2;
11261 else if (GET_CODE (scanbody) == PARALLEL)
11263 switch (get_attr_conds (this_insn))
11273 fail = TRUE; /* Unrecognized jump (eg epilogue). */
11278 /* Instructions using or affecting the condition codes make it
11280 scanbody = PATTERN (this_insn);
11281 if (!(GET_CODE (scanbody) == SET
11282 || GET_CODE (scanbody) == PARALLEL)
11283 || get_attr_conds (this_insn) != CONDS_NOCOND)
11286 /* A conditional cirrus instruction must be followed by
11287 a non Cirrus instruction. However, since we
11288 conditionalize instructions in this function and by
11289 the time we get here we can't add instructions
11290 (nops), because shorten_branches() has already been
11291 called, we will disable conditionalizing Cirrus
11292 instructions to be safe. */
11293 if (GET_CODE (scanbody) != USE
11294 && GET_CODE (scanbody) != CLOBBER
11295 && get_attr_cirrus (this_insn) != CIRRUS_NOT)
11305 if ((!seeking_return) && (arm_ccfsm_state == 1 || reverse))
11306 arm_target_label = CODE_LABEL_NUMBER (label);
11307 else if (seeking_return || arm_ccfsm_state == 2)
11309 while (this_insn && GET_CODE (PATTERN (this_insn)) == USE)
11311 this_insn = next_nonnote_insn (this_insn);
11312 if (this_insn && (GET_CODE (this_insn) == BARRIER
11313 || GET_CODE (this_insn) == CODE_LABEL))
11318 /* Oh, dear! we ran off the end.. give up. */
11319 recog (PATTERN (insn), insn, NULL);
11320 arm_ccfsm_state = 0;
11321 arm_target_insn = NULL;
11324 arm_target_insn = this_insn;
11333 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body),
11335 if (GET_CODE (XEXP (XEXP (SET_SRC (body), 0), 0)) == AND)
11336 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
11337 if (GET_CODE (XEXP (SET_SRC (body), 0)) == NE)
11338 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
11342 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
11345 arm_current_cc = get_arm_condition_code (XEXP (SET_SRC (body),
11349 if (reverse || then_not_else)
11350 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
11353 /* Restore recog_data (getting the attributes of other insns can
11354 destroy this array, but final.c assumes that it remains intact
11355 across this call; since the insn has been recognized already we
11356 call recog direct). */
11357 recog (PATTERN (insn), insn, NULL);
11361 /* Returns true if REGNO is a valid register
11362 for holding a quantity of tyoe MODE. */
11364 arm_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
11366 if (GET_MODE_CLASS (mode) == MODE_CC)
11367 return regno == CC_REGNUM || regno == VFPCC_REGNUM;
11370 /* For the Thumb we only allow values bigger than SImode in
11371 registers 0 - 6, so that there is always a second low
11372 register available to hold the upper part of the value.
11373 We probably we ought to ensure that the register is the
11374 start of an even numbered register pair. */
11375 return (ARM_NUM_REGS (mode) < 2) || (regno < LAST_LO_REGNUM);
11377 if (IS_CIRRUS_REGNUM (regno))
11378 /* We have outlawed SI values in Cirrus registers because they
11379 reside in the lower 32 bits, but SF values reside in the
11380 upper 32 bits. This causes gcc all sorts of grief. We can't
11381 even split the registers into pairs because Cirrus SI values
11382 get sign extended to 64bits-- aldyh. */
11383 return (GET_MODE_CLASS (mode) == MODE_FLOAT) || (mode == DImode);
11385 if (IS_VFP_REGNUM (regno))
11387 if (mode == SFmode || mode == SImode)
11390 /* DFmode values are only valid in even register pairs. */
11391 if (mode == DFmode)
11392 return ((regno - FIRST_VFP_REGNUM) & 1) == 0;
11396 if (IS_IWMMXT_GR_REGNUM (regno))
11397 return mode == SImode;
11399 if (IS_IWMMXT_REGNUM (regno))
11400 return VALID_IWMMXT_REG_MODE (mode);
11402 if (regno <= LAST_ARM_REGNUM)
11403 /* We allow any value to be stored in the general registers. */
11406 if ( regno == FRAME_POINTER_REGNUM
11407 || regno == ARG_POINTER_REGNUM)
11408 /* We only allow integers in the fake hard registers. */
11409 return GET_MODE_CLASS (mode) == MODE_INT;
11411 /* The only registers left are the FPA registers
11412 which we only allow to hold FP values. */
11413 return GET_MODE_CLASS (mode) == MODE_FLOAT
11414 && regno >= FIRST_FPA_REGNUM
11415 && regno <= LAST_FPA_REGNUM;
11419 arm_regno_class (int regno)
11423 if (regno == STACK_POINTER_REGNUM)
11425 if (regno == CC_REGNUM)
11432 if ( regno <= LAST_ARM_REGNUM
11433 || regno == FRAME_POINTER_REGNUM
11434 || regno == ARG_POINTER_REGNUM)
11435 return GENERAL_REGS;
11437 if (regno == CC_REGNUM || regno == VFPCC_REGNUM)
11440 if (IS_CIRRUS_REGNUM (regno))
11441 return CIRRUS_REGS;
11443 if (IS_VFP_REGNUM (regno))
11446 if (IS_IWMMXT_REGNUM (regno))
11447 return IWMMXT_REGS;
11449 if (IS_IWMMXT_GR_REGNUM (regno))
11450 return IWMMXT_GR_REGS;
11455 /* Handle a special case when computing the offset
11456 of an argument from the frame pointer. */
11458 arm_debugger_arg_offset (int value, rtx addr)
11462 /* We are only interested if dbxout_parms() failed to compute the offset. */
11466 /* We can only cope with the case where the address is held in a register. */
11467 if (GET_CODE (addr) != REG)
11470 /* If we are using the frame pointer to point at the argument, then
11471 an offset of 0 is correct. */
11472 if (REGNO (addr) == (unsigned) HARD_FRAME_POINTER_REGNUM)
11475 /* If we are using the stack pointer to point at the
11476 argument, then an offset of 0 is correct. */
11477 if ((TARGET_THUMB || !frame_pointer_needed)
11478 && REGNO (addr) == SP_REGNUM)
11481 /* Oh dear. The argument is pointed to by a register rather
11482 than being held in a register, or being stored at a known
11483 offset from the frame pointer. Since GDB only understands
11484 those two kinds of argument we must translate the address
11485 held in the register into an offset from the frame pointer.
11486 We do this by searching through the insns for the function
11487 looking to see where this register gets its value. If the
11488 register is initialized from the frame pointer plus an offset
11489 then we are in luck and we can continue, otherwise we give up.
11491 This code is exercised by producing debugging information
11492 for a function with arguments like this:
11494 double func (double a, double b, int c, double d) {return d;}
11496 Without this code the stab for parameter 'd' will be set to
11497 an offset of 0 from the frame pointer, rather than 8. */
11499 /* The if() statement says:
11501 If the insn is a normal instruction
11502 and if the insn is setting the value in a register
11503 and if the register being set is the register holding the address of the argument
11504 and if the address is computing by an addition
11505 that involves adding to a register
11506 which is the frame pointer
11511 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
11513 if ( GET_CODE (insn) == INSN
11514 && GET_CODE (PATTERN (insn)) == SET
11515 && REGNO (XEXP (PATTERN (insn), 0)) == REGNO (addr)
11516 && GET_CODE (XEXP (PATTERN (insn), 1)) == PLUS
11517 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 0)) == REG
11518 && REGNO (XEXP (XEXP (PATTERN (insn), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
11519 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 1)) == CONST_INT
11522 value = INTVAL (XEXP (XEXP (PATTERN (insn), 1), 1));
11531 warning ("unable to compute real location of stacked parameter");
11532 value = 8; /* XXX magic hack */
11538 #define def_mbuiltin(MASK, NAME, TYPE, CODE) \
11541 if ((MASK) & insn_flags) \
11542 builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, NULL, NULL_TREE); \
11546 struct builtin_description
11548 const unsigned int mask;
11549 const enum insn_code icode;
11550 const char * const name;
11551 const enum arm_builtins code;
11552 const enum rtx_code comparison;
11553 const unsigned int flag;
11556 static const struct builtin_description bdesc_2arg[] =
11558 #define IWMMXT_BUILTIN(code, string, builtin) \
11559 { FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \
11560 ARM_BUILTIN_##builtin, 0, 0 },
11562 IWMMXT_BUILTIN (addv8qi3, "waddb", WADDB)
11563 IWMMXT_BUILTIN (addv4hi3, "waddh", WADDH)
11564 IWMMXT_BUILTIN (addv2si3, "waddw", WADDW)
11565 IWMMXT_BUILTIN (subv8qi3, "wsubb", WSUBB)
11566 IWMMXT_BUILTIN (subv4hi3, "wsubh", WSUBH)
11567 IWMMXT_BUILTIN (subv2si3, "wsubw", WSUBW)
11568 IWMMXT_BUILTIN (ssaddv8qi3, "waddbss", WADDSSB)
11569 IWMMXT_BUILTIN (ssaddv4hi3, "waddhss", WADDSSH)
11570 IWMMXT_BUILTIN (ssaddv2si3, "waddwss", WADDSSW)
11571 IWMMXT_BUILTIN (sssubv8qi3, "wsubbss", WSUBSSB)
11572 IWMMXT_BUILTIN (sssubv4hi3, "wsubhss", WSUBSSH)
11573 IWMMXT_BUILTIN (sssubv2si3, "wsubwss", WSUBSSW)
11574 IWMMXT_BUILTIN (usaddv8qi3, "waddbus", WADDUSB)
11575 IWMMXT_BUILTIN (usaddv4hi3, "waddhus", WADDUSH)
11576 IWMMXT_BUILTIN (usaddv2si3, "waddwus", WADDUSW)
11577 IWMMXT_BUILTIN (ussubv8qi3, "wsubbus", WSUBUSB)
11578 IWMMXT_BUILTIN (ussubv4hi3, "wsubhus", WSUBUSH)
11579 IWMMXT_BUILTIN (ussubv2si3, "wsubwus", WSUBUSW)
11580 IWMMXT_BUILTIN (mulv4hi3, "wmulul", WMULUL)
11581 IWMMXT_BUILTIN (smulv4hi3_highpart, "wmulsm", WMULSM)
11582 IWMMXT_BUILTIN (umulv4hi3_highpart, "wmulum", WMULUM)
11583 IWMMXT_BUILTIN (eqv8qi3, "wcmpeqb", WCMPEQB)
11584 IWMMXT_BUILTIN (eqv4hi3, "wcmpeqh", WCMPEQH)
11585 IWMMXT_BUILTIN (eqv2si3, "wcmpeqw", WCMPEQW)
11586 IWMMXT_BUILTIN (gtuv8qi3, "wcmpgtub", WCMPGTUB)
11587 IWMMXT_BUILTIN (gtuv4hi3, "wcmpgtuh", WCMPGTUH)
11588 IWMMXT_BUILTIN (gtuv2si3, "wcmpgtuw", WCMPGTUW)
11589 IWMMXT_BUILTIN (gtv8qi3, "wcmpgtsb", WCMPGTSB)
11590 IWMMXT_BUILTIN (gtv4hi3, "wcmpgtsh", WCMPGTSH)
11591 IWMMXT_BUILTIN (gtv2si3, "wcmpgtsw", WCMPGTSW)
11592 IWMMXT_BUILTIN (umaxv8qi3, "wmaxub", WMAXUB)
11593 IWMMXT_BUILTIN (smaxv8qi3, "wmaxsb", WMAXSB)
11594 IWMMXT_BUILTIN (umaxv4hi3, "wmaxuh", WMAXUH)
11595 IWMMXT_BUILTIN (smaxv4hi3, "wmaxsh", WMAXSH)
11596 IWMMXT_BUILTIN (umaxv2si3, "wmaxuw", WMAXUW)
11597 IWMMXT_BUILTIN (smaxv2si3, "wmaxsw", WMAXSW)
11598 IWMMXT_BUILTIN (uminv8qi3, "wminub", WMINUB)
11599 IWMMXT_BUILTIN (sminv8qi3, "wminsb", WMINSB)
11600 IWMMXT_BUILTIN (uminv4hi3, "wminuh", WMINUH)
11601 IWMMXT_BUILTIN (sminv4hi3, "wminsh", WMINSH)
11602 IWMMXT_BUILTIN (uminv2si3, "wminuw", WMINUW)
11603 IWMMXT_BUILTIN (sminv2si3, "wminsw", WMINSW)
11604 IWMMXT_BUILTIN (iwmmxt_anddi3, "wand", WAND)
11605 IWMMXT_BUILTIN (iwmmxt_nanddi3, "wandn", WANDN)
11606 IWMMXT_BUILTIN (iwmmxt_iordi3, "wor", WOR)
11607 IWMMXT_BUILTIN (iwmmxt_xordi3, "wxor", WXOR)
11608 IWMMXT_BUILTIN (iwmmxt_uavgv8qi3, "wavg2b", WAVG2B)
11609 IWMMXT_BUILTIN (iwmmxt_uavgv4hi3, "wavg2h", WAVG2H)
11610 IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3, "wavg2br", WAVG2BR)
11611 IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3, "wavg2hr", WAVG2HR)
11612 IWMMXT_BUILTIN (iwmmxt_wunpckilb, "wunpckilb", WUNPCKILB)
11613 IWMMXT_BUILTIN (iwmmxt_wunpckilh, "wunpckilh", WUNPCKILH)
11614 IWMMXT_BUILTIN (iwmmxt_wunpckilw, "wunpckilw", WUNPCKILW)
11615 IWMMXT_BUILTIN (iwmmxt_wunpckihb, "wunpckihb", WUNPCKIHB)
11616 IWMMXT_BUILTIN (iwmmxt_wunpckihh, "wunpckihh", WUNPCKIHH)
11617 IWMMXT_BUILTIN (iwmmxt_wunpckihw, "wunpckihw", WUNPCKIHW)
11618 IWMMXT_BUILTIN (iwmmxt_wmadds, "wmadds", WMADDS)
11619 IWMMXT_BUILTIN (iwmmxt_wmaddu, "wmaddu", WMADDU)
11621 #define IWMMXT_BUILTIN2(code, builtin) \
11622 { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, 0, 0 },
11624 IWMMXT_BUILTIN2 (iwmmxt_wpackhss, WPACKHSS)
11625 IWMMXT_BUILTIN2 (iwmmxt_wpackwss, WPACKWSS)
11626 IWMMXT_BUILTIN2 (iwmmxt_wpackdss, WPACKDSS)
11627 IWMMXT_BUILTIN2 (iwmmxt_wpackhus, WPACKHUS)
11628 IWMMXT_BUILTIN2 (iwmmxt_wpackwus, WPACKWUS)
11629 IWMMXT_BUILTIN2 (iwmmxt_wpackdus, WPACKDUS)
11630 IWMMXT_BUILTIN2 (ashlv4hi3_di, WSLLH)
11631 IWMMXT_BUILTIN2 (ashlv4hi3, WSLLHI)
11632 IWMMXT_BUILTIN2 (ashlv2si3_di, WSLLW)
11633 IWMMXT_BUILTIN2 (ashlv2si3, WSLLWI)
11634 IWMMXT_BUILTIN2 (ashldi3_di, WSLLD)
11635 IWMMXT_BUILTIN2 (ashldi3_iwmmxt, WSLLDI)
11636 IWMMXT_BUILTIN2 (lshrv4hi3_di, WSRLH)
11637 IWMMXT_BUILTIN2 (lshrv4hi3, WSRLHI)
11638 IWMMXT_BUILTIN2 (lshrv2si3_di, WSRLW)
11639 IWMMXT_BUILTIN2 (lshrv2si3, WSRLWI)
11640 IWMMXT_BUILTIN2 (lshrdi3_di, WSRLD)
11641 IWMMXT_BUILTIN2 (lshrdi3_iwmmxt, WSRLDI)
11642 IWMMXT_BUILTIN2 (ashrv4hi3_di, WSRAH)
11643 IWMMXT_BUILTIN2 (ashrv4hi3, WSRAHI)
11644 IWMMXT_BUILTIN2 (ashrv2si3_di, WSRAW)
11645 IWMMXT_BUILTIN2 (ashrv2si3, WSRAWI)
11646 IWMMXT_BUILTIN2 (ashrdi3_di, WSRAD)
11647 IWMMXT_BUILTIN2 (ashrdi3_iwmmxt, WSRADI)
11648 IWMMXT_BUILTIN2 (rorv4hi3_di, WRORH)
11649 IWMMXT_BUILTIN2 (rorv4hi3, WRORHI)
11650 IWMMXT_BUILTIN2 (rorv2si3_di, WRORW)
11651 IWMMXT_BUILTIN2 (rorv2si3, WRORWI)
11652 IWMMXT_BUILTIN2 (rordi3_di, WRORD)
11653 IWMMXT_BUILTIN2 (rordi3, WRORDI)
11654 IWMMXT_BUILTIN2 (iwmmxt_wmacuz, WMACUZ)
11655 IWMMXT_BUILTIN2 (iwmmxt_wmacsz, WMACSZ)
11658 static const struct builtin_description bdesc_1arg[] =
11660 IWMMXT_BUILTIN (iwmmxt_tmovmskb, "tmovmskb", TMOVMSKB)
11661 IWMMXT_BUILTIN (iwmmxt_tmovmskh, "tmovmskh", TMOVMSKH)
11662 IWMMXT_BUILTIN (iwmmxt_tmovmskw, "tmovmskw", TMOVMSKW)
11663 IWMMXT_BUILTIN (iwmmxt_waccb, "waccb", WACCB)
11664 IWMMXT_BUILTIN (iwmmxt_wacch, "wacch", WACCH)
11665 IWMMXT_BUILTIN (iwmmxt_waccw, "waccw", WACCW)
11666 IWMMXT_BUILTIN (iwmmxt_wunpckehub, "wunpckehub", WUNPCKEHUB)
11667 IWMMXT_BUILTIN (iwmmxt_wunpckehuh, "wunpckehuh", WUNPCKEHUH)
11668 IWMMXT_BUILTIN (iwmmxt_wunpckehuw, "wunpckehuw", WUNPCKEHUW)
11669 IWMMXT_BUILTIN (iwmmxt_wunpckehsb, "wunpckehsb", WUNPCKEHSB)
11670 IWMMXT_BUILTIN (iwmmxt_wunpckehsh, "wunpckehsh", WUNPCKEHSH)
11671 IWMMXT_BUILTIN (iwmmxt_wunpckehsw, "wunpckehsw", WUNPCKEHSW)
11672 IWMMXT_BUILTIN (iwmmxt_wunpckelub, "wunpckelub", WUNPCKELUB)
11673 IWMMXT_BUILTIN (iwmmxt_wunpckeluh, "wunpckeluh", WUNPCKELUH)
11674 IWMMXT_BUILTIN (iwmmxt_wunpckeluw, "wunpckeluw", WUNPCKELUW)
11675 IWMMXT_BUILTIN (iwmmxt_wunpckelsb, "wunpckelsb", WUNPCKELSB)
11676 IWMMXT_BUILTIN (iwmmxt_wunpckelsh, "wunpckelsh", WUNPCKELSH)
11677 IWMMXT_BUILTIN (iwmmxt_wunpckelsw, "wunpckelsw", WUNPCKELSW)
11680 /* Set up all the iWMMXt builtins. This is
11681 not called if TARGET_IWMMXT is zero. */
11684 arm_init_iwmmxt_builtins (void)
11686 const struct builtin_description * d;
11688 tree endlink = void_list_node;
11690 tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode);
11691 tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode);
11692 tree V8QI_type_node = build_vector_type_for_mode (intQI_type_node, V8QImode);
11695 = build_function_type (integer_type_node,
11696 tree_cons (NULL_TREE, integer_type_node, endlink));
11697 tree v8qi_ftype_v8qi_v8qi_int
11698 = build_function_type (V8QI_type_node,
11699 tree_cons (NULL_TREE, V8QI_type_node,
11700 tree_cons (NULL_TREE, V8QI_type_node,
11701 tree_cons (NULL_TREE,
11704 tree v4hi_ftype_v4hi_int
11705 = build_function_type (V4HI_type_node,
11706 tree_cons (NULL_TREE, V4HI_type_node,
11707 tree_cons (NULL_TREE, integer_type_node,
11709 tree v2si_ftype_v2si_int
11710 = build_function_type (V2SI_type_node,
11711 tree_cons (NULL_TREE, V2SI_type_node,
11712 tree_cons (NULL_TREE, integer_type_node,
11714 tree v2si_ftype_di_di
11715 = build_function_type (V2SI_type_node,
11716 tree_cons (NULL_TREE, long_long_integer_type_node,
11717 tree_cons (NULL_TREE, long_long_integer_type_node,
11719 tree di_ftype_di_int
11720 = build_function_type (long_long_integer_type_node,
11721 tree_cons (NULL_TREE, long_long_integer_type_node,
11722 tree_cons (NULL_TREE, integer_type_node,
11724 tree di_ftype_di_int_int
11725 = build_function_type (long_long_integer_type_node,
11726 tree_cons (NULL_TREE, long_long_integer_type_node,
11727 tree_cons (NULL_TREE, integer_type_node,
11728 tree_cons (NULL_TREE,
11731 tree int_ftype_v8qi
11732 = build_function_type (integer_type_node,
11733 tree_cons (NULL_TREE, V8QI_type_node,
11735 tree int_ftype_v4hi
11736 = build_function_type (integer_type_node,
11737 tree_cons (NULL_TREE, V4HI_type_node,
11739 tree int_ftype_v2si
11740 = build_function_type (integer_type_node,
11741 tree_cons (NULL_TREE, V2SI_type_node,
11743 tree int_ftype_v8qi_int
11744 = build_function_type (integer_type_node,
11745 tree_cons (NULL_TREE, V8QI_type_node,
11746 tree_cons (NULL_TREE, integer_type_node,
11748 tree int_ftype_v4hi_int
11749 = build_function_type (integer_type_node,
11750 tree_cons (NULL_TREE, V4HI_type_node,
11751 tree_cons (NULL_TREE, integer_type_node,
11753 tree int_ftype_v2si_int
11754 = build_function_type (integer_type_node,
11755 tree_cons (NULL_TREE, V2SI_type_node,
11756 tree_cons (NULL_TREE, integer_type_node,
11758 tree v8qi_ftype_v8qi_int_int
11759 = build_function_type (V8QI_type_node,
11760 tree_cons (NULL_TREE, V8QI_type_node,
11761 tree_cons (NULL_TREE, integer_type_node,
11762 tree_cons (NULL_TREE,
11765 tree v4hi_ftype_v4hi_int_int
11766 = build_function_type (V4HI_type_node,
11767 tree_cons (NULL_TREE, V4HI_type_node,
11768 tree_cons (NULL_TREE, integer_type_node,
11769 tree_cons (NULL_TREE,
11772 tree v2si_ftype_v2si_int_int
11773 = build_function_type (V2SI_type_node,
11774 tree_cons (NULL_TREE, V2SI_type_node,
11775 tree_cons (NULL_TREE, integer_type_node,
11776 tree_cons (NULL_TREE,
11779 /* Miscellaneous. */
11780 tree v8qi_ftype_v4hi_v4hi
11781 = build_function_type (V8QI_type_node,
11782 tree_cons (NULL_TREE, V4HI_type_node,
11783 tree_cons (NULL_TREE, V4HI_type_node,
11785 tree v4hi_ftype_v2si_v2si
11786 = build_function_type (V4HI_type_node,
11787 tree_cons (NULL_TREE, V2SI_type_node,
11788 tree_cons (NULL_TREE, V2SI_type_node,
11790 tree v2si_ftype_v4hi_v4hi
11791 = build_function_type (V2SI_type_node,
11792 tree_cons (NULL_TREE, V4HI_type_node,
11793 tree_cons (NULL_TREE, V4HI_type_node,
11795 tree v2si_ftype_v8qi_v8qi
11796 = build_function_type (V2SI_type_node,
11797 tree_cons (NULL_TREE, V8QI_type_node,
11798 tree_cons (NULL_TREE, V8QI_type_node,
11800 tree v4hi_ftype_v4hi_di
11801 = build_function_type (V4HI_type_node,
11802 tree_cons (NULL_TREE, V4HI_type_node,
11803 tree_cons (NULL_TREE,
11804 long_long_integer_type_node,
11806 tree v2si_ftype_v2si_di
11807 = build_function_type (V2SI_type_node,
11808 tree_cons (NULL_TREE, V2SI_type_node,
11809 tree_cons (NULL_TREE,
11810 long_long_integer_type_node,
11812 tree void_ftype_int_int
11813 = build_function_type (void_type_node,
11814 tree_cons (NULL_TREE, integer_type_node,
11815 tree_cons (NULL_TREE, integer_type_node,
11818 = build_function_type (long_long_unsigned_type_node, endlink);
11820 = build_function_type (long_long_integer_type_node,
11821 tree_cons (NULL_TREE, V8QI_type_node,
11824 = build_function_type (long_long_integer_type_node,
11825 tree_cons (NULL_TREE, V4HI_type_node,
11828 = build_function_type (long_long_integer_type_node,
11829 tree_cons (NULL_TREE, V2SI_type_node,
11831 tree v2si_ftype_v4hi
11832 = build_function_type (V2SI_type_node,
11833 tree_cons (NULL_TREE, V4HI_type_node,
11835 tree v4hi_ftype_v8qi
11836 = build_function_type (V4HI_type_node,
11837 tree_cons (NULL_TREE, V8QI_type_node,
11840 tree di_ftype_di_v4hi_v4hi
11841 = build_function_type (long_long_unsigned_type_node,
11842 tree_cons (NULL_TREE,
11843 long_long_unsigned_type_node,
11844 tree_cons (NULL_TREE, V4HI_type_node,
11845 tree_cons (NULL_TREE,
11849 tree di_ftype_v4hi_v4hi
11850 = build_function_type (long_long_unsigned_type_node,
11851 tree_cons (NULL_TREE, V4HI_type_node,
11852 tree_cons (NULL_TREE, V4HI_type_node,
11855 /* Normal vector binops. */
11856 tree v8qi_ftype_v8qi_v8qi
11857 = build_function_type (V8QI_type_node,
11858 tree_cons (NULL_TREE, V8QI_type_node,
11859 tree_cons (NULL_TREE, V8QI_type_node,
11861 tree v4hi_ftype_v4hi_v4hi
11862 = build_function_type (V4HI_type_node,
11863 tree_cons (NULL_TREE, V4HI_type_node,
11864 tree_cons (NULL_TREE, V4HI_type_node,
11866 tree v2si_ftype_v2si_v2si
11867 = build_function_type (V2SI_type_node,
11868 tree_cons (NULL_TREE, V2SI_type_node,
11869 tree_cons (NULL_TREE, V2SI_type_node,
11871 tree di_ftype_di_di
11872 = build_function_type (long_long_unsigned_type_node,
11873 tree_cons (NULL_TREE, long_long_unsigned_type_node,
11874 tree_cons (NULL_TREE,
11875 long_long_unsigned_type_node,
11878 /* Add all builtins that are more or less simple operations on two
11880 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
11882 /* Use one of the operands; the target can have a different mode for
11883 mask-generating compares. */
11884 enum machine_mode mode;
11890 mode = insn_data[d->icode].operand[1].mode;
11895 type = v8qi_ftype_v8qi_v8qi;
11898 type = v4hi_ftype_v4hi_v4hi;
11901 type = v2si_ftype_v2si_v2si;
11904 type = di_ftype_di_di;
11911 def_mbuiltin (d->mask, d->name, type, d->code);
11914 /* Add the remaining MMX insns with somewhat more complicated types. */
11915 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wzero", di_ftype_void, ARM_BUILTIN_WZERO);
11916 def_mbuiltin (FL_IWMMXT, "__builtin_arm_setwcx", void_ftype_int_int, ARM_BUILTIN_SETWCX);
11917 def_mbuiltin (FL_IWMMXT, "__builtin_arm_getwcx", int_ftype_int, ARM_BUILTIN_GETWCX);
11919 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSLLH);
11920 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllw", v2si_ftype_v2si_di, ARM_BUILTIN_WSLLW);
11921 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslld", di_ftype_di_di, ARM_BUILTIN_WSLLD);
11922 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSLLHI);
11923 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSLLWI);
11924 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslldi", di_ftype_di_int, ARM_BUILTIN_WSLLDI);
11926 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRLH);
11927 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRLW);
11928 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrld", di_ftype_di_di, ARM_BUILTIN_WSRLD);
11929 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRLHI);
11930 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRLWI);
11931 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrldi", di_ftype_di_int, ARM_BUILTIN_WSRLDI);
11933 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrah", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRAH);
11934 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsraw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRAW);
11935 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrad", di_ftype_di_di, ARM_BUILTIN_WSRAD);
11936 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrahi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRAHI);
11937 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrawi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRAWI);
11938 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsradi", di_ftype_di_int, ARM_BUILTIN_WSRADI);
11940 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WRORH);
11941 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorw", v2si_ftype_v2si_di, ARM_BUILTIN_WRORW);
11942 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrord", di_ftype_di_di, ARM_BUILTIN_WRORD);
11943 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WRORHI);
11944 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorwi", v2si_ftype_v2si_int, ARM_BUILTIN_WRORWI);
11945 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrordi", di_ftype_di_int, ARM_BUILTIN_WRORDI);
11947 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wshufh", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSHUFH);
11949 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadb", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADB);
11950 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadh", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADH);
11951 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadbz", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADBZ);
11952 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadhz", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADHZ);
11954 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsb", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMSB);
11955 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMSH);
11956 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMSW);
11957 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmub", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMUB);
11958 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMUH);
11959 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMUW);
11960 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrb", v8qi_ftype_v8qi_int_int, ARM_BUILTIN_TINSRB);
11961 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrh", v4hi_ftype_v4hi_int_int, ARM_BUILTIN_TINSRH);
11962 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrw", v2si_ftype_v2si_int_int, ARM_BUILTIN_TINSRW);
11964 def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccb", di_ftype_v8qi, ARM_BUILTIN_WACCB);
11965 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wacch", di_ftype_v4hi, ARM_BUILTIN_WACCH);
11966 def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccw", di_ftype_v2si, ARM_BUILTIN_WACCW);
11968 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskb", int_ftype_v8qi, ARM_BUILTIN_TMOVMSKB);
11969 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskh", int_ftype_v4hi, ARM_BUILTIN_TMOVMSKH);
11970 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskw", int_ftype_v2si, ARM_BUILTIN_TMOVMSKW);
11972 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhss", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHSS);
11973 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhus", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHUS);
11974 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwus", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWUS);
11975 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwss", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWSS);
11976 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdus", v2si_ftype_di_di, ARM_BUILTIN_WPACKDUS);
11977 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdss", v2si_ftype_di_di, ARM_BUILTIN_WPACKDSS);
11979 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHUB);
11980 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHUH);
11981 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHUW);
11982 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHSB);
11983 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHSH);
11984 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHSW);
11985 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELUB);
11986 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELUH);
11987 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELUW);
11988 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELSB);
11989 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELSH);
11990 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELSW);
11992 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacs", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACS);
11993 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacsz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACSZ);
11994 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacu", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACU);
11995 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacuz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACUZ);
11997 def_mbuiltin (FL_IWMMXT, "__builtin_arm_walign", v8qi_ftype_v8qi_v8qi_int, ARM_BUILTIN_WALIGN);
11998 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmia", di_ftype_di_int_int, ARM_BUILTIN_TMIA);
11999 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiaph", di_ftype_di_int_int, ARM_BUILTIN_TMIAPH);
12000 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabb", di_ftype_di_int_int, ARM_BUILTIN_TMIABB);
12001 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabt", di_ftype_di_int_int, ARM_BUILTIN_TMIABT);
12002 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatb", di_ftype_di_int_int, ARM_BUILTIN_TMIATB);
12003 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatt", di_ftype_di_int_int, ARM_BUILTIN_TMIATT);
12007 arm_init_builtins (void)
12009 if (TARGET_REALLY_IWMMXT)
12010 arm_init_iwmmxt_builtins ();
12013 /* Errors in the source file can cause expand_expr to return const0_rtx
12014 where we expect a vector. To avoid crashing, use one of the vector
12015 clear instructions. */
12018 safe_vector_operand (rtx x, enum machine_mode mode)
12020 if (x != const0_rtx)
12022 x = gen_reg_rtx (mode);
12024 emit_insn (gen_iwmmxt_clrdi (mode == DImode ? x
12025 : gen_rtx_SUBREG (DImode, x, 0)));
12029 /* Subroutine of arm_expand_builtin to take care of binop insns. */
12032 arm_expand_binop_builtin (enum insn_code icode,
12033 tree arglist, rtx target)
12036 tree arg0 = TREE_VALUE (arglist);
12037 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12038 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12039 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12040 enum machine_mode tmode = insn_data[icode].operand[0].mode;
12041 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
12042 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
12044 if (VECTOR_MODE_P (mode0))
12045 op0 = safe_vector_operand (op0, mode0);
12046 if (VECTOR_MODE_P (mode1))
12047 op1 = safe_vector_operand (op1, mode1);
12050 || GET_MODE (target) != tmode
12051 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12052 target = gen_reg_rtx (tmode);
12054 /* In case the insn wants input operands in modes different from
12055 the result, abort. */
12056 if (GET_MODE (op0) != mode0 || GET_MODE (op1) != mode1)
12059 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12060 op0 = copy_to_mode_reg (mode0, op0);
12061 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
12062 op1 = copy_to_mode_reg (mode1, op1);
12064 pat = GEN_FCN (icode) (target, op0, op1);
12071 /* Subroutine of arm_expand_builtin to take care of unop insns. */
12074 arm_expand_unop_builtin (enum insn_code icode,
12075 tree arglist, rtx target, int do_load)
12078 tree arg0 = TREE_VALUE (arglist);
12079 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12080 enum machine_mode tmode = insn_data[icode].operand[0].mode;
12081 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
12084 || GET_MODE (target) != tmode
12085 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12086 target = gen_reg_rtx (tmode);
12088 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
12091 if (VECTOR_MODE_P (mode0))
12092 op0 = safe_vector_operand (op0, mode0);
12094 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12095 op0 = copy_to_mode_reg (mode0, op0);
12098 pat = GEN_FCN (icode) (target, op0);
12105 /* Expand an expression EXP that calls a built-in function,
12106 with result going to TARGET if that's convenient
12107 (and in mode MODE if that's convenient).
12108 SUBTARGET may be used as the target for computing one of EXP's operands.
12109 IGNORE is nonzero if the value is to be ignored. */
12112 arm_expand_builtin (tree exp,
12114 rtx subtarget ATTRIBUTE_UNUSED,
12115 enum machine_mode mode ATTRIBUTE_UNUSED,
12116 int ignore ATTRIBUTE_UNUSED)
12118 const struct builtin_description * d;
12119 enum insn_code icode;
12120 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
12121 tree arglist = TREE_OPERAND (exp, 1);
12129 int fcode = DECL_FUNCTION_CODE (fndecl);
12131 enum machine_mode tmode;
12132 enum machine_mode mode0;
12133 enum machine_mode mode1;
12134 enum machine_mode mode2;
12138 case ARM_BUILTIN_TEXTRMSB:
12139 case ARM_BUILTIN_TEXTRMUB:
12140 case ARM_BUILTIN_TEXTRMSH:
12141 case ARM_BUILTIN_TEXTRMUH:
12142 case ARM_BUILTIN_TEXTRMSW:
12143 case ARM_BUILTIN_TEXTRMUW:
12144 icode = (fcode == ARM_BUILTIN_TEXTRMSB ? CODE_FOR_iwmmxt_textrmsb
12145 : fcode == ARM_BUILTIN_TEXTRMUB ? CODE_FOR_iwmmxt_textrmub
12146 : fcode == ARM_BUILTIN_TEXTRMSH ? CODE_FOR_iwmmxt_textrmsh
12147 : fcode == ARM_BUILTIN_TEXTRMUH ? CODE_FOR_iwmmxt_textrmuh
12148 : CODE_FOR_iwmmxt_textrmw);
12150 arg0 = TREE_VALUE (arglist);
12151 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12152 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12153 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12154 tmode = insn_data[icode].operand[0].mode;
12155 mode0 = insn_data[icode].operand[1].mode;
12156 mode1 = insn_data[icode].operand[2].mode;
12158 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12159 op0 = copy_to_mode_reg (mode0, op0);
12160 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
12162 /* @@@ better error message */
12163 error ("selector must be an immediate");
12164 return gen_reg_rtx (tmode);
12167 || GET_MODE (target) != tmode
12168 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12169 target = gen_reg_rtx (tmode);
12170 pat = GEN_FCN (icode) (target, op0, op1);
12176 case ARM_BUILTIN_TINSRB:
12177 case ARM_BUILTIN_TINSRH:
12178 case ARM_BUILTIN_TINSRW:
12179 icode = (fcode == ARM_BUILTIN_TINSRB ? CODE_FOR_iwmmxt_tinsrb
12180 : fcode == ARM_BUILTIN_TINSRH ? CODE_FOR_iwmmxt_tinsrh
12181 : CODE_FOR_iwmmxt_tinsrw);
12182 arg0 = TREE_VALUE (arglist);
12183 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12184 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
12185 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12186 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12187 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
12188 tmode = insn_data[icode].operand[0].mode;
12189 mode0 = insn_data[icode].operand[1].mode;
12190 mode1 = insn_data[icode].operand[2].mode;
12191 mode2 = insn_data[icode].operand[3].mode;
12193 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12194 op0 = copy_to_mode_reg (mode0, op0);
12195 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
12196 op1 = copy_to_mode_reg (mode1, op1);
12197 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
12199 /* @@@ better error message */
12200 error ("selector must be an immediate");
12204 || GET_MODE (target) != tmode
12205 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12206 target = gen_reg_rtx (tmode);
12207 pat = GEN_FCN (icode) (target, op0, op1, op2);
12213 case ARM_BUILTIN_SETWCX:
12214 arg0 = TREE_VALUE (arglist);
12215 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12216 op0 = force_reg (SImode, expand_expr (arg0, NULL_RTX, VOIDmode, 0));
12217 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12218 emit_insn (gen_iwmmxt_tmcr (op1, op0));
12221 case ARM_BUILTIN_GETWCX:
12222 arg0 = TREE_VALUE (arglist);
12223 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12224 target = gen_reg_rtx (SImode);
12225 emit_insn (gen_iwmmxt_tmrc (target, op0));
12228 case ARM_BUILTIN_WSHUFH:
12229 icode = CODE_FOR_iwmmxt_wshufh;
12230 arg0 = TREE_VALUE (arglist);
12231 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12232 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12233 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12234 tmode = insn_data[icode].operand[0].mode;
12235 mode1 = insn_data[icode].operand[1].mode;
12236 mode2 = insn_data[icode].operand[2].mode;
12238 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1))
12239 op0 = copy_to_mode_reg (mode1, op0);
12240 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2))
12242 /* @@@ better error message */
12243 error ("mask must be an immediate");
12247 || GET_MODE (target) != tmode
12248 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12249 target = gen_reg_rtx (tmode);
12250 pat = GEN_FCN (icode) (target, op0, op1);
12256 case ARM_BUILTIN_WSADB:
12257 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadb, arglist, target);
12258 case ARM_BUILTIN_WSADH:
12259 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadh, arglist, target);
12260 case ARM_BUILTIN_WSADBZ:
12261 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadbz, arglist, target);
12262 case ARM_BUILTIN_WSADHZ:
12263 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadhz, arglist, target);
12265 /* Several three-argument builtins. */
12266 case ARM_BUILTIN_WMACS:
12267 case ARM_BUILTIN_WMACU:
12268 case ARM_BUILTIN_WALIGN:
12269 case ARM_BUILTIN_TMIA:
12270 case ARM_BUILTIN_TMIAPH:
12271 case ARM_BUILTIN_TMIATT:
12272 case ARM_BUILTIN_TMIATB:
12273 case ARM_BUILTIN_TMIABT:
12274 case ARM_BUILTIN_TMIABB:
12275 icode = (fcode == ARM_BUILTIN_WMACS ? CODE_FOR_iwmmxt_wmacs
12276 : fcode == ARM_BUILTIN_WMACU ? CODE_FOR_iwmmxt_wmacu
12277 : fcode == ARM_BUILTIN_TMIA ? CODE_FOR_iwmmxt_tmia
12278 : fcode == ARM_BUILTIN_TMIAPH ? CODE_FOR_iwmmxt_tmiaph
12279 : fcode == ARM_BUILTIN_TMIABB ? CODE_FOR_iwmmxt_tmiabb
12280 : fcode == ARM_BUILTIN_TMIABT ? CODE_FOR_iwmmxt_tmiabt
12281 : fcode == ARM_BUILTIN_TMIATB ? CODE_FOR_iwmmxt_tmiatb
12282 : fcode == ARM_BUILTIN_TMIATT ? CODE_FOR_iwmmxt_tmiatt
12283 : CODE_FOR_iwmmxt_walign);
12284 arg0 = TREE_VALUE (arglist);
12285 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
12286 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
12287 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
12288 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
12289 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
12290 tmode = insn_data[icode].operand[0].mode;
12291 mode0 = insn_data[icode].operand[1].mode;
12292 mode1 = insn_data[icode].operand[2].mode;
12293 mode2 = insn_data[icode].operand[3].mode;
12295 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12296 op0 = copy_to_mode_reg (mode0, op0);
12297 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
12298 op1 = copy_to_mode_reg (mode1, op1);
12299 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
12300 op2 = copy_to_mode_reg (mode2, op2);
12302 || GET_MODE (target) != tmode
12303 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12304 target = gen_reg_rtx (tmode);
12305 pat = GEN_FCN (icode) (target, op0, op1, op2);
12311 case ARM_BUILTIN_WZERO:
12312 target = gen_reg_rtx (DImode);
12313 emit_insn (gen_iwmmxt_clrdi (target));
12320 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
12321 if (d->code == (const enum arm_builtins) fcode)
12322 return arm_expand_binop_builtin (d->icode, arglist, target);
12324 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
12325 if (d->code == (const enum arm_builtins) fcode)
12326 return arm_expand_unop_builtin (d->icode, arglist, target, 0);
12328 /* @@@ Should really do something sensible here. */
12332 /* Recursively search through all of the blocks in a function
12333 checking to see if any of the variables created in that
12334 function match the RTX called 'orig'. If they do then
12335 replace them with the RTX called 'new'. */
12337 replace_symbols_in_block (tree block, rtx orig, rtx new)
12339 for (; block; block = BLOCK_CHAIN (block))
12343 if (!TREE_USED (block))
12346 for (sym = BLOCK_VARS (block); sym; sym = TREE_CHAIN (sym))
12348 if ( (DECL_NAME (sym) == 0 && TREE_CODE (sym) != TYPE_DECL)
12349 || DECL_IGNORED_P (sym)
12350 || TREE_CODE (sym) != VAR_DECL
12351 || DECL_EXTERNAL (sym)
12352 || !rtx_equal_p (DECL_RTL (sym), orig)
12356 SET_DECL_RTL (sym, new);
12359 replace_symbols_in_block (BLOCK_SUBBLOCKS (block), orig, new);
12363 /* Return the number (counting from 0) of
12364 the least significant set bit in MASK. */
12367 number_of_first_bit_set (int mask)
12372 (mask & (1 << bit)) == 0;
12379 /* Generate code to return from a thumb function.
12380 If 'reg_containing_return_addr' is -1, then the return address is
12381 actually on the stack, at the stack pointer. */
12383 thumb_exit (FILE *f, int reg_containing_return_addr, rtx eh_ofs)
12385 unsigned regs_available_for_popping;
12386 unsigned regs_to_pop;
12388 unsigned available;
12392 int restore_a4 = FALSE;
12394 /* Compute the registers we need to pop. */
12398 /* There is an assumption here, that if eh_ofs is not NULL, the
12399 normal return address will have been pushed. */
12400 if (reg_containing_return_addr == -1 || eh_ofs)
12402 /* When we are generating a return for __builtin_eh_return,
12403 reg_containing_return_addr must specify the return regno. */
12404 if (eh_ofs && reg_containing_return_addr == -1)
12407 regs_to_pop |= 1 << LR_REGNUM;
12411 if (TARGET_BACKTRACE)
12413 /* Restore the (ARM) frame pointer and stack pointer. */
12414 regs_to_pop |= (1 << ARM_HARD_FRAME_POINTER_REGNUM) | (1 << SP_REGNUM);
12418 /* If there is nothing to pop then just emit the BX instruction and
12420 if (pops_needed == 0)
12423 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs));
12425 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
12428 /* Otherwise if we are not supporting interworking and we have not created
12429 a backtrace structure and the function was not entered in ARM mode then
12430 just pop the return address straight into the PC. */
12431 else if (!TARGET_INTERWORK
12432 && !TARGET_BACKTRACE
12433 && !is_called_in_ARM_mode (current_function_decl))
12437 asm_fprintf (f, "\tadd\t%r, #4\n", SP_REGNUM);
12438 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs));
12439 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
12442 asm_fprintf (f, "\tpop\t{%r}\n", PC_REGNUM);
12447 /* Find out how many of the (return) argument registers we can corrupt. */
12448 regs_available_for_popping = 0;
12450 /* If returning via __builtin_eh_return, the bottom three registers
12451 all contain information needed for the return. */
12457 /* If we can deduce the registers used from the function's
12458 return value. This is more reliable that examining
12459 regs_ever_live[] because that will be set if the register is
12460 ever used in the function, not just if the register is used
12461 to hold a return value. */
12463 if (current_function_return_rtx != 0)
12464 mode = GET_MODE (current_function_return_rtx);
12467 mode = DECL_MODE (DECL_RESULT (current_function_decl));
12469 size = GET_MODE_SIZE (mode);
12473 /* In a void function we can use any argument register.
12474 In a function that returns a structure on the stack
12475 we can use the second and third argument registers. */
12476 if (mode == VOIDmode)
12477 regs_available_for_popping =
12478 (1 << ARG_REGISTER (1))
12479 | (1 << ARG_REGISTER (2))
12480 | (1 << ARG_REGISTER (3));
12482 regs_available_for_popping =
12483 (1 << ARG_REGISTER (2))
12484 | (1 << ARG_REGISTER (3));
12486 else if (size <= 4)
12487 regs_available_for_popping =
12488 (1 << ARG_REGISTER (2))
12489 | (1 << ARG_REGISTER (3));
12490 else if (size <= 8)
12491 regs_available_for_popping =
12492 (1 << ARG_REGISTER (3));
12495 /* Match registers to be popped with registers into which we pop them. */
12496 for (available = regs_available_for_popping,
12497 required = regs_to_pop;
12498 required != 0 && available != 0;
12499 available &= ~(available & - available),
12500 required &= ~(required & - required))
12503 /* If we have any popping registers left over, remove them. */
12505 regs_available_for_popping &= ~available;
12507 /* Otherwise if we need another popping register we can use
12508 the fourth argument register. */
12509 else if (pops_needed)
12511 /* If we have not found any free argument registers and
12512 reg a4 contains the return address, we must move it. */
12513 if (regs_available_for_popping == 0
12514 && reg_containing_return_addr == LAST_ARG_REGNUM)
12516 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
12517 reg_containing_return_addr = LR_REGNUM;
12519 else if (size > 12)
12521 /* Register a4 is being used to hold part of the return value,
12522 but we have dire need of a free, low register. */
12525 asm_fprintf (f, "\tmov\t%r, %r\n",IP_REGNUM, LAST_ARG_REGNUM);
12528 if (reg_containing_return_addr != LAST_ARG_REGNUM)
12530 /* The fourth argument register is available. */
12531 regs_available_for_popping |= 1 << LAST_ARG_REGNUM;
12537 /* Pop as many registers as we can. */
12538 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
12539 regs_available_for_popping);
12541 /* Process the registers we popped. */
12542 if (reg_containing_return_addr == -1)
12544 /* The return address was popped into the lowest numbered register. */
12545 regs_to_pop &= ~(1 << LR_REGNUM);
12547 reg_containing_return_addr =
12548 number_of_first_bit_set (regs_available_for_popping);
12550 /* Remove this register for the mask of available registers, so that
12551 the return address will not be corrupted by further pops. */
12552 regs_available_for_popping &= ~(1 << reg_containing_return_addr);
12555 /* If we popped other registers then handle them here. */
12556 if (regs_available_for_popping)
12560 /* Work out which register currently contains the frame pointer. */
12561 frame_pointer = number_of_first_bit_set (regs_available_for_popping);
12563 /* Move it into the correct place. */
12564 asm_fprintf (f, "\tmov\t%r, %r\n",
12565 ARM_HARD_FRAME_POINTER_REGNUM, frame_pointer);
12567 /* (Temporarily) remove it from the mask of popped registers. */
12568 regs_available_for_popping &= ~(1 << frame_pointer);
12569 regs_to_pop &= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM);
12571 if (regs_available_for_popping)
12575 /* We popped the stack pointer as well,
12576 find the register that contains it. */
12577 stack_pointer = number_of_first_bit_set (regs_available_for_popping);
12579 /* Move it into the stack register. */
12580 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, stack_pointer);
12582 /* At this point we have popped all necessary registers, so
12583 do not worry about restoring regs_available_for_popping
12584 to its correct value:
12586 assert (pops_needed == 0)
12587 assert (regs_available_for_popping == (1 << frame_pointer))
12588 assert (regs_to_pop == (1 << STACK_POINTER)) */
12592 /* Since we have just move the popped value into the frame
12593 pointer, the popping register is available for reuse, and
12594 we know that we still have the stack pointer left to pop. */
12595 regs_available_for_popping |= (1 << frame_pointer);
12599 /* If we still have registers left on the stack, but we no longer have
12600 any registers into which we can pop them, then we must move the return
12601 address into the link register and make available the register that
12603 if (regs_available_for_popping == 0 && pops_needed > 0)
12605 regs_available_for_popping |= 1 << reg_containing_return_addr;
12607 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM,
12608 reg_containing_return_addr);
12610 reg_containing_return_addr = LR_REGNUM;
12613 /* If we have registers left on the stack then pop some more.
12614 We know that at most we will want to pop FP and SP. */
12615 if (pops_needed > 0)
12620 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
12621 regs_available_for_popping);
12623 /* We have popped either FP or SP.
12624 Move whichever one it is into the correct register. */
12625 popped_into = number_of_first_bit_set (regs_available_for_popping);
12626 move_to = number_of_first_bit_set (regs_to_pop);
12628 asm_fprintf (f, "\tmov\t%r, %r\n", move_to, popped_into);
12630 regs_to_pop &= ~(1 << move_to);
12635 /* If we still have not popped everything then we must have only
12636 had one register available to us and we are now popping the SP. */
12637 if (pops_needed > 0)
12641 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL,
12642 regs_available_for_popping);
12644 popped_into = number_of_first_bit_set (regs_available_for_popping);
12646 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, popped_into);
12648 assert (regs_to_pop == (1 << STACK_POINTER))
12649 assert (pops_needed == 1)
12653 /* If necessary restore the a4 register. */
12656 if (reg_containing_return_addr != LR_REGNUM)
12658 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
12659 reg_containing_return_addr = LR_REGNUM;
12662 asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM);
12666 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs));
12668 /* Return to caller. */
12669 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
12672 /* Emit code to push or pop registers to or from the stack. F is the
12673 assembly file. MASK is the registers to push or pop. PUSH is
12674 nonzero if we should push, and zero if we should pop. For debugging
12675 output, if pushing, adjust CFA_OFFSET by the amount of space added
12676 to the stack. REAL_REGS should have the same number of bits set as
12677 MASK, and will be used instead (in the same order) to describe which
12678 registers were saved - this is used to mark the save slots when we
12679 push high registers after moving them to low registers. */
12681 thumb_pushpop (FILE *f, int mask, int push, int *cfa_offset, int real_regs)
12684 int lo_mask = mask & 0xFF;
12685 int pushed_words = 0;
12687 if (lo_mask == 0 && !push && (mask & (1 << 15)))
12689 /* Special case. Do not generate a POP PC statement here, do it in
12691 thumb_exit (f, -1, NULL_RTX);
12695 fprintf (f, "\t%s\t{", push ? "push" : "pop");
12697 /* Look at the low registers first. */
12698 for (regno = 0; regno <= LAST_LO_REGNUM; regno++, lo_mask >>= 1)
12702 asm_fprintf (f, "%r", regno);
12704 if ((lo_mask & ~1) != 0)
12711 if (push && (mask & (1 << LR_REGNUM)))
12713 /* Catch pushing the LR. */
12717 asm_fprintf (f, "%r", LR_REGNUM);
12721 else if (!push && (mask & (1 << PC_REGNUM)))
12723 /* Catch popping the PC. */
12724 if (TARGET_INTERWORK || TARGET_BACKTRACE)
12726 /* The PC is never poped directly, instead
12727 it is popped into r3 and then BX is used. */
12728 fprintf (f, "}\n");
12730 thumb_exit (f, -1, NULL_RTX);
12739 asm_fprintf (f, "%r", PC_REGNUM);
12743 fprintf (f, "}\n");
12745 if (push && pushed_words && dwarf2out_do_frame ())
12747 char *l = dwarf2out_cfi_label ();
12748 int pushed_mask = real_regs;
12750 *cfa_offset += pushed_words * 4;
12751 dwarf2out_def_cfa (l, SP_REGNUM, *cfa_offset);
12754 pushed_mask = real_regs;
12755 for (regno = 0; regno <= 14; regno++, pushed_mask >>= 1)
12757 if (pushed_mask & 1)
12758 dwarf2out_reg_save (l, regno, 4 * pushed_words++ - *cfa_offset);
12764 thumb_final_prescan_insn (rtx insn)
12766 if (flag_print_asm_name)
12767 asm_fprintf (asm_out_file, "%@ 0x%04x\n",
12768 INSN_ADDRESSES (INSN_UID (insn)));
12772 thumb_shiftable_const (unsigned HOST_WIDE_INT val)
12774 unsigned HOST_WIDE_INT mask = 0xff;
12777 if (val == 0) /* XXX */
12780 for (i = 0; i < 25; i++)
12781 if ((val & (mask << i)) == val)
12787 /* Returns nonzero if the current function contains,
12788 or might contain a far jump. */
12790 thumb_far_jump_used_p (void)
12794 /* This test is only important for leaf functions. */
12795 /* assert (!leaf_function_p ()); */
12797 /* If we have already decided that far jumps may be used,
12798 do not bother checking again, and always return true even if
12799 it turns out that they are not being used. Once we have made
12800 the decision that far jumps are present (and that hence the link
12801 register will be pushed onto the stack) we cannot go back on it. */
12802 if (cfun->machine->far_jump_used)
12805 /* If this function is not being called from the prologue/epilogue
12806 generation code then it must be being called from the
12807 INITIAL_ELIMINATION_OFFSET macro. */
12808 if (!(ARM_DOUBLEWORD_ALIGN || reload_completed))
12810 /* In this case we know that we are being asked about the elimination
12811 of the arg pointer register. If that register is not being used,
12812 then there are no arguments on the stack, and we do not have to
12813 worry that a far jump might force the prologue to push the link
12814 register, changing the stack offsets. In this case we can just
12815 return false, since the presence of far jumps in the function will
12816 not affect stack offsets.
12818 If the arg pointer is live (or if it was live, but has now been
12819 eliminated and so set to dead) then we do have to test to see if
12820 the function might contain a far jump. This test can lead to some
12821 false negatives, since before reload is completed, then length of
12822 branch instructions is not known, so gcc defaults to returning their
12823 longest length, which in turn sets the far jump attribute to true.
12825 A false negative will not result in bad code being generated, but it
12826 will result in a needless push and pop of the link register. We
12827 hope that this does not occur too often.
12829 If we need doubleword stack alignment this could affect the other
12830 elimination offsets so we can't risk getting it wrong. */
12831 if (regs_ever_live [ARG_POINTER_REGNUM])
12832 cfun->machine->arg_pointer_live = 1;
12833 else if (!cfun->machine->arg_pointer_live)
12837 /* Check to see if the function contains a branch
12838 insn with the far jump attribute set. */
12839 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
12841 if (GET_CODE (insn) == JUMP_INSN
12842 /* Ignore tablejump patterns. */
12843 && GET_CODE (PATTERN (insn)) != ADDR_VEC
12844 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
12845 && get_attr_far_jump (insn) == FAR_JUMP_YES
12848 /* Record the fact that we have decided that
12849 the function does use far jumps. */
12850 cfun->machine->far_jump_used = 1;
12858 /* Return nonzero if FUNC must be entered in ARM mode. */
12860 is_called_in_ARM_mode (tree func)
12862 if (TREE_CODE (func) != FUNCTION_DECL)
12865 /* Ignore the problem about functions whoes address is taken. */
12866 if (TARGET_CALLEE_INTERWORKING && TREE_PUBLIC (func))
12870 return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func)) != NULL_TREE;
12876 /* The bits which aren't usefully expanded as rtl. */
12878 thumb_unexpanded_epilogue (void)
12881 int live_regs_mask = 0;
12882 int high_regs_pushed = 0;
12883 int leaf_function = leaf_function_p ();
12884 int had_to_push_lr;
12885 rtx eh_ofs = cfun->machine->eh_epilogue_sp_ofs;
12887 if (return_used_this_function)
12890 if (IS_NAKED (arm_current_func_type ()))
12893 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
12894 if (THUMB_REG_PUSHED_P (regno))
12895 live_regs_mask |= 1 << regno;
12897 for (regno = 8; regno < 13; regno++)
12898 if (THUMB_REG_PUSHED_P (regno))
12899 high_regs_pushed++;
12901 /* The prolog may have pushed some high registers to use as
12902 work registers. eg the testsuite file:
12903 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
12904 compiles to produce:
12905 push {r4, r5, r6, r7, lr}
12909 as part of the prolog. We have to undo that pushing here. */
12911 if (high_regs_pushed)
12913 int mask = live_regs_mask;
12919 /* If we can deduce the registers used from the function's return value.
12920 This is more reliable that examining regs_ever_live[] because that
12921 will be set if the register is ever used in the function, not just if
12922 the register is used to hold a return value. */
12924 if (current_function_return_rtx != 0)
12925 mode = GET_MODE (current_function_return_rtx);
12928 mode = DECL_MODE (DECL_RESULT (current_function_decl));
12930 size = GET_MODE_SIZE (mode);
12932 /* Unless we are returning a type of size > 12 register r3 is
12938 /* Oh dear! We have no low registers into which we can pop
12941 ("no low registers available for popping high registers");
12943 for (next_hi_reg = 8; next_hi_reg < 13; next_hi_reg++)
12944 if (THUMB_REG_PUSHED_P (next_hi_reg))
12947 while (high_regs_pushed)
12949 /* Find lo register(s) into which the high register(s) can
12951 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
12953 if (mask & (1 << regno))
12954 high_regs_pushed--;
12955 if (high_regs_pushed == 0)
12959 mask &= (2 << regno) - 1; /* A noop if regno == 8 */
12961 /* Pop the values into the low register(s). */
12962 thumb_pushpop (asm_out_file, mask, 0, NULL, mask);
12964 /* Move the value(s) into the high registers. */
12965 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
12967 if (mask & (1 << regno))
12969 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", next_hi_reg,
12972 for (next_hi_reg++; next_hi_reg < 13; next_hi_reg++)
12973 if (THUMB_REG_PUSHED_P (next_hi_reg))
12980 had_to_push_lr = (live_regs_mask || !leaf_function
12981 || thumb_far_jump_used_p ());
12983 if (TARGET_BACKTRACE
12984 && ((live_regs_mask & 0xFF) == 0)
12985 && regs_ever_live [LAST_ARG_REGNUM] != 0)
12987 /* The stack backtrace structure creation code had to
12988 push R7 in order to get a work register, so we pop
12990 live_regs_mask |= (1 << LAST_LO_REGNUM);
12993 if (current_function_pretend_args_size == 0 || TARGET_BACKTRACE)
12996 && !is_called_in_ARM_mode (current_function_decl)
12998 live_regs_mask |= 1 << PC_REGNUM;
13000 /* Either no argument registers were pushed or a backtrace
13001 structure was created which includes an adjusted stack
13002 pointer, so just pop everything. */
13003 if (live_regs_mask)
13004 thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL,
13008 thumb_exit (asm_out_file, 2, eh_ofs);
13009 /* We have either just popped the return address into the
13010 PC or it is was kept in LR for the entire function or
13011 it is still on the stack because we do not want to
13012 return by doing a pop {pc}. */
13013 else if ((live_regs_mask & (1 << PC_REGNUM)) == 0)
13014 thumb_exit (asm_out_file,
13016 && is_called_in_ARM_mode (current_function_decl)) ?
13017 -1 : LR_REGNUM, NULL_RTX);
13021 /* Pop everything but the return address. */
13022 live_regs_mask &= ~(1 << PC_REGNUM);
13024 if (live_regs_mask)
13025 thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL,
13028 if (had_to_push_lr)
13029 /* Get the return address into a temporary register. */
13030 thumb_pushpop (asm_out_file, 1 << LAST_ARG_REGNUM, 0, NULL,
13031 1 << LAST_ARG_REGNUM);
13033 /* Remove the argument registers that were pushed onto the stack. */
13034 asm_fprintf (asm_out_file, "\tadd\t%r, %r, #%d\n",
13035 SP_REGNUM, SP_REGNUM,
13036 current_function_pretend_args_size);
13039 thumb_exit (asm_out_file, 2, eh_ofs);
13041 thumb_exit (asm_out_file,
13042 had_to_push_lr ? LAST_ARG_REGNUM : LR_REGNUM, NULL_RTX);
13048 /* Functions to save and restore machine-specific function data. */
13049 static struct machine_function *
13050 arm_init_machine_status (void)
13052 struct machine_function *machine;
13053 machine = (machine_function *) ggc_alloc_cleared (sizeof (machine_function));
13055 #if ARM_FT_UNKNOWN != 0
13056 machine->func_type = ARM_FT_UNKNOWN;
13061 /* Return an RTX indicating where the return address to the
13062 calling function can be found. */
13064 arm_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
13069 if (TARGET_APCS_32)
13070 return get_hard_reg_initial_val (Pmode, LR_REGNUM);
13073 rtx lr = gen_rtx_AND (Pmode, gen_rtx_REG (Pmode, LR_REGNUM),
13074 GEN_INT (RETURN_ADDR_MASK26));
13075 return get_func_hard_reg_initial_val (cfun, lr);
13079 /* Do anything needed before RTL is emitted for each function. */
13081 arm_init_expanders (void)
13083 /* Arrange to initialize and mark the machine per-function status. */
13084 init_machine_status = arm_init_machine_status;
13088 /* Like arm_compute_initial_elimination offset. Simpler because
13089 THUMB_HARD_FRAME_POINTER isn't actually the ABI specified frame pointer. */
13092 thumb_compute_initial_elimination_offset (unsigned int from, unsigned int to)
13094 arm_stack_offsets *offsets;
13096 offsets = arm_get_frame_offsets ();
13100 case ARG_POINTER_REGNUM:
13103 case STACK_POINTER_REGNUM:
13104 return offsets->outgoing_args - offsets->saved_args;
13106 case FRAME_POINTER_REGNUM:
13107 return offsets->soft_frame - offsets->saved_args;
13109 case THUMB_HARD_FRAME_POINTER_REGNUM:
13110 case ARM_HARD_FRAME_POINTER_REGNUM:
13111 return offsets->saved_regs - offsets->saved_args;
13118 case FRAME_POINTER_REGNUM:
13121 case STACK_POINTER_REGNUM:
13122 return offsets->outgoing_args - offsets->soft_frame;
13124 case THUMB_HARD_FRAME_POINTER_REGNUM:
13125 case ARM_HARD_FRAME_POINTER_REGNUM:
13126 return offsets->saved_regs - offsets->soft_frame;
13139 /* Generate the rest of a function's prologue. */
13141 thumb_expand_prologue (void)
13145 HOST_WIDE_INT amount;
13146 arm_stack_offsets *offsets;
13147 unsigned long func_type;
13149 func_type = arm_current_func_type ();
13151 /* Naked functions don't have prologues. */
13152 if (IS_NAKED (func_type))
13155 if (IS_INTERRUPT (func_type))
13157 error ("interrupt Service Routines cannot be coded in Thumb mode");
13161 offsets = arm_get_frame_offsets ();
13163 if (frame_pointer_needed)
13165 insn = emit_insn (gen_movsi (hard_frame_pointer_rtx,
13166 stack_pointer_rtx));
13167 RTX_FRAME_RELATED_P (insn) = 1;
13170 amount = offsets->outgoing_args - offsets->saved_regs;
13175 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
13176 GEN_INT (- amount)));
13177 RTX_FRAME_RELATED_P (insn) = 1;
13184 /* The stack decrement is too big for an immediate value in a single
13185 insn. In theory we could issue multiple subtracts, but after
13186 three of them it becomes more space efficient to place the full
13187 value in the constant pool and load into a register. (Also the
13188 ARM debugger really likes to see only one stack decrement per
13189 function). So instead we look for a scratch register into which
13190 we can load the decrement, and then we subtract this from the
13191 stack pointer. Unfortunately on the thumb the only available
13192 scratch registers are the argument registers, and we cannot use
13193 these as they may hold arguments to the function. Instead we
13194 attempt to locate a call preserved register which is used by this
13195 function. If we can find one, then we know that it will have
13196 been pushed at the start of the prologue and so we can corrupt
13198 for (regno = LAST_ARG_REGNUM + 1; regno <= LAST_LO_REGNUM; regno++)
13199 if (THUMB_REG_PUSHED_P (regno)
13200 && !(frame_pointer_needed
13201 && (regno == THUMB_HARD_FRAME_POINTER_REGNUM)))
13204 if (regno > LAST_LO_REGNUM) /* Very unlikely. */
13206 rtx spare = gen_rtx_REG (SImode, IP_REGNUM);
13208 /* Choose an arbitrary, non-argument low register. */
13209 reg = gen_rtx_REG (SImode, LAST_LO_REGNUM);
13211 /* Save it by copying it into a high, scratch register. */
13212 emit_insn (gen_movsi (spare, reg));
13213 /* Add a USE to stop propagate_one_insn() from barfing. */
13214 emit_insn (gen_prologue_use (spare));
13216 /* Decrement the stack. */
13217 emit_insn (gen_movsi (reg, GEN_INT (- amount)));
13218 insn = emit_insn (gen_addsi3 (stack_pointer_rtx,
13219 stack_pointer_rtx, reg));
13220 RTX_FRAME_RELATED_P (insn) = 1;
13221 dwarf = gen_rtx_SET (SImode, stack_pointer_rtx,
13222 plus_constant (stack_pointer_rtx,
13223 GEN_INT (- amount)));
13224 RTX_FRAME_RELATED_P (dwarf) = 1;
13226 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
13229 /* Restore the low register's original value. */
13230 emit_insn (gen_movsi (reg, spare));
13232 /* Emit a USE of the restored scratch register, so that flow
13233 analysis will not consider the restore redundant. The
13234 register won't be used again in this function and isn't
13235 restored by the epilogue. */
13236 emit_insn (gen_prologue_use (reg));
13240 reg = gen_rtx_REG (SImode, regno);
13242 emit_insn (gen_movsi (reg, GEN_INT (- amount)));
13244 insn = emit_insn (gen_addsi3 (stack_pointer_rtx,
13245 stack_pointer_rtx, reg));
13246 RTX_FRAME_RELATED_P (insn) = 1;
13247 dwarf = gen_rtx_SET (SImode, stack_pointer_rtx,
13248 plus_constant (stack_pointer_rtx,
13249 GEN_INT (- amount)));
13250 RTX_FRAME_RELATED_P (dwarf) = 1;
13252 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
13256 /* If the frame pointer is needed, emit a special barrier that
13257 will prevent the scheduler from moving stores to the frame
13258 before the stack adjustment. */
13259 if (frame_pointer_needed)
13260 emit_insn (gen_stack_tie (stack_pointer_rtx,
13261 hard_frame_pointer_rtx));
13264 if (current_function_profile || TARGET_NO_SCHED_PRO)
13265 emit_insn (gen_blockage ());
13269 thumb_expand_epilogue (void)
13271 HOST_WIDE_INT amount;
13272 arm_stack_offsets *offsets;
13275 /* Naked functions don't have prologues. */
13276 if (IS_NAKED (arm_current_func_type ()))
13279 offsets = arm_get_frame_offsets ();
13280 amount = offsets->outgoing_args - offsets->saved_regs;
13282 if (frame_pointer_needed)
13283 emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx));
13287 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
13288 GEN_INT (amount)));
13291 /* r3 is always free in the epilogue. */
13292 rtx reg = gen_rtx_REG (SImode, LAST_ARG_REGNUM);
13294 emit_insn (gen_movsi (reg, GEN_INT (amount)));
13295 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, reg));
13299 /* Emit a USE (stack_pointer_rtx), so that
13300 the stack adjustment will not be deleted. */
13301 emit_insn (gen_prologue_use (stack_pointer_rtx));
13303 if (current_function_profile || TARGET_NO_SCHED_PRO)
13304 emit_insn (gen_blockage ());
13306 /* Emit a clobber for each insn that will be restored in the epilogue,
13307 so that flow2 will get register lifetimes correct. */
13308 for (regno = 0; regno < 13; regno++)
13309 if (regs_ever_live[regno] && !call_used_regs[regno])
13310 emit_insn (gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, regno)));
13312 if (! regs_ever_live[LR_REGNUM])
13313 emit_insn (gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, LR_REGNUM)));
13317 thumb_output_function_prologue (FILE *f, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
13319 int live_regs_mask = 0;
13320 int high_regs_pushed = 0;
13321 int cfa_offset = 0;
13324 if (IS_NAKED (arm_current_func_type ()))
13327 if (is_called_in_ARM_mode (current_function_decl))
13331 if (GET_CODE (DECL_RTL (current_function_decl)) != MEM)
13333 if (GET_CODE (XEXP (DECL_RTL (current_function_decl), 0)) != SYMBOL_REF)
13335 name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
13337 /* Generate code sequence to switch us into Thumb mode. */
13338 /* The .code 32 directive has already been emitted by
13339 ASM_DECLARE_FUNCTION_NAME. */
13340 asm_fprintf (f, "\torr\t%r, %r, #1\n", IP_REGNUM, PC_REGNUM);
13341 asm_fprintf (f, "\tbx\t%r\n", IP_REGNUM);
13343 /* Generate a label, so that the debugger will notice the
13344 change in instruction sets. This label is also used by
13345 the assembler to bypass the ARM code when this function
13346 is called from a Thumb encoded function elsewhere in the
13347 same file. Hence the definition of STUB_NAME here must
13348 agree with the definition in gas/config/tc-arm.c. */
13350 #define STUB_NAME ".real_start_of"
13352 fprintf (f, "\t.code\t16\n");
13354 if (arm_dllexport_name_p (name))
13355 name = arm_strip_name_encoding (name);
13357 asm_fprintf (f, "\t.globl %s%U%s\n", STUB_NAME, name);
13358 fprintf (f, "\t.thumb_func\n");
13359 asm_fprintf (f, "%s%U%s:\n", STUB_NAME, name);
13362 if (current_function_pretend_args_size)
13364 if (cfun->machine->uses_anonymous_args)
13368 fprintf (f, "\tpush\t{");
13370 num_pushes = ARM_NUM_INTS (current_function_pretend_args_size);
13372 for (regno = LAST_ARG_REGNUM + 1 - num_pushes;
13373 regno <= LAST_ARG_REGNUM;
13375 asm_fprintf (f, "%r%s", regno,
13376 regno == LAST_ARG_REGNUM ? "" : ", ");
13378 fprintf (f, "}\n");
13381 asm_fprintf (f, "\tsub\t%r, %r, #%d\n",
13382 SP_REGNUM, SP_REGNUM,
13383 current_function_pretend_args_size);
13385 /* We don't need to record the stores for unwinding (would it
13386 help the debugger any if we did?), but record the change in
13387 the stack pointer. */
13388 if (dwarf2out_do_frame ())
13390 char *l = dwarf2out_cfi_label ();
13391 cfa_offset = cfa_offset + current_function_pretend_args_size;
13392 dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset);
13396 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
13397 if (THUMB_REG_PUSHED_P (regno))
13398 live_regs_mask |= 1 << regno;
13400 if (live_regs_mask || !leaf_function_p () || thumb_far_jump_used_p ())
13401 live_regs_mask |= 1 << LR_REGNUM;
13403 if (TARGET_BACKTRACE)
13406 int work_register = 0;
13409 /* We have been asked to create a stack backtrace structure.
13410 The code looks like this:
13414 0 sub SP, #16 Reserve space for 4 registers.
13415 2 push {R7} Get a work register.
13416 4 add R7, SP, #20 Get the stack pointer before the push.
13417 6 str R7, [SP, #8] Store the stack pointer (before reserving the space).
13418 8 mov R7, PC Get hold of the start of this code plus 12.
13419 10 str R7, [SP, #16] Store it.
13420 12 mov R7, FP Get hold of the current frame pointer.
13421 14 str R7, [SP, #4] Store it.
13422 16 mov R7, LR Get hold of the current return address.
13423 18 str R7, [SP, #12] Store it.
13424 20 add R7, SP, #16 Point at the start of the backtrace structure.
13425 22 mov FP, R7 Put this value into the frame pointer. */
13427 if ((live_regs_mask & 0xFF) == 0)
13429 /* See if the a4 register is free. */
13431 if (regs_ever_live [LAST_ARG_REGNUM] == 0)
13432 work_register = LAST_ARG_REGNUM;
13433 else /* We must push a register of our own. */
13434 live_regs_mask |= (1 << LAST_LO_REGNUM);
13437 if (work_register == 0)
13439 /* Select a register from the list that will be pushed to
13440 use as our work register. */
13441 for (work_register = (LAST_LO_REGNUM + 1); work_register--;)
13442 if ((1 << work_register) & live_regs_mask)
13447 (f, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n",
13448 SP_REGNUM, SP_REGNUM);
13450 if (dwarf2out_do_frame ())
13452 char *l = dwarf2out_cfi_label ();
13453 cfa_offset = cfa_offset + 16;
13454 dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset);
13457 if (live_regs_mask)
13458 thumb_pushpop (f, live_regs_mask, 1, &cfa_offset, live_regs_mask);
13460 for (offset = 0, wr = 1 << 15; wr != 0; wr >>= 1)
13461 if (wr & live_regs_mask)
13464 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
13465 offset + 16 + current_function_pretend_args_size);
13467 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13470 /* Make sure that the instruction fetching the PC is in the right place
13471 to calculate "start of backtrace creation code + 12". */
13472 if (live_regs_mask)
13474 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
13475 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13477 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
13478 ARM_HARD_FRAME_POINTER_REGNUM);
13479 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13484 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
13485 ARM_HARD_FRAME_POINTER_REGNUM);
13486 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13488 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
13489 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13493 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, LR_REGNUM);
13494 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
13496 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
13498 asm_fprintf (f, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n",
13499 ARM_HARD_FRAME_POINTER_REGNUM, work_register);
13501 else if (live_regs_mask)
13502 thumb_pushpop (f, live_regs_mask, 1, &cfa_offset, live_regs_mask);
13504 for (regno = 8; regno < 13; regno++)
13505 if (THUMB_REG_PUSHED_P (regno))
13506 high_regs_pushed++;
13508 if (high_regs_pushed)
13510 int pushable_regs = 0;
13511 int mask = live_regs_mask & 0xff;
13514 for (next_hi_reg = 12; next_hi_reg > LAST_LO_REGNUM; next_hi_reg--)
13515 if (THUMB_REG_PUSHED_P (next_hi_reg))
13518 pushable_regs = mask;
13520 if (pushable_regs == 0)
13522 /* Desperation time -- this probably will never happen. */
13523 if (THUMB_REG_PUSHED_P (LAST_ARG_REGNUM))
13524 asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, LAST_ARG_REGNUM);
13525 mask = 1 << LAST_ARG_REGNUM;
13528 while (high_regs_pushed > 0)
13530 int real_regs_mask = 0;
13532 for (regno = LAST_LO_REGNUM; regno >= 0; regno--)
13534 if (mask & (1 << regno))
13536 asm_fprintf (f, "\tmov\t%r, %r\n", regno, next_hi_reg);
13538 high_regs_pushed--;
13539 real_regs_mask |= (1 << next_hi_reg);
13541 if (high_regs_pushed)
13543 for (next_hi_reg--; next_hi_reg > LAST_LO_REGNUM;
13545 if (THUMB_REG_PUSHED_P (next_hi_reg))
13550 mask &= ~((1 << regno) - 1);
13556 thumb_pushpop (f, mask, 1, &cfa_offset, real_regs_mask);
13559 if (pushable_regs == 0
13560 && (THUMB_REG_PUSHED_P (LAST_ARG_REGNUM)))
13561 asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM);
13565 /* Handle the case of a double word load into a low register from
13566 a computed memory address. The computed address may involve a
13567 register which is overwritten by the load. */
13569 thumb_load_double_from_address (rtx *operands)
13577 if (GET_CODE (operands[0]) != REG)
13580 if (GET_CODE (operands[1]) != MEM)
13583 /* Get the memory address. */
13584 addr = XEXP (operands[1], 0);
13586 /* Work out how the memory address is computed. */
13587 switch (GET_CODE (addr))
13590 operands[2] = gen_rtx_MEM (SImode,
13591 plus_constant (XEXP (operands[1], 0), 4));
13593 if (REGNO (operands[0]) == REGNO (addr))
13595 output_asm_insn ("ldr\t%H0, %2", operands);
13596 output_asm_insn ("ldr\t%0, %1", operands);
13600 output_asm_insn ("ldr\t%0, %1", operands);
13601 output_asm_insn ("ldr\t%H0, %2", operands);
13606 /* Compute <address> + 4 for the high order load. */
13607 operands[2] = gen_rtx_MEM (SImode,
13608 plus_constant (XEXP (operands[1], 0), 4));
13610 output_asm_insn ("ldr\t%0, %1", operands);
13611 output_asm_insn ("ldr\t%H0, %2", operands);
13615 arg1 = XEXP (addr, 0);
13616 arg2 = XEXP (addr, 1);
13618 if (CONSTANT_P (arg1))
13619 base = arg2, offset = arg1;
13621 base = arg1, offset = arg2;
13623 if (GET_CODE (base) != REG)
13626 /* Catch the case of <address> = <reg> + <reg> */
13627 if (GET_CODE (offset) == REG)
13629 int reg_offset = REGNO (offset);
13630 int reg_base = REGNO (base);
13631 int reg_dest = REGNO (operands[0]);
13633 /* Add the base and offset registers together into the
13634 higher destination register. */
13635 asm_fprintf (asm_out_file, "\tadd\t%r, %r, %r",
13636 reg_dest + 1, reg_base, reg_offset);
13638 /* Load the lower destination register from the address in
13639 the higher destination register. */
13640 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #0]",
13641 reg_dest, reg_dest + 1);
13643 /* Load the higher destination register from its own address
13645 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #4]",
13646 reg_dest + 1, reg_dest + 1);
13650 /* Compute <address> + 4 for the high order load. */
13651 operands[2] = gen_rtx_MEM (SImode,
13652 plus_constant (XEXP (operands[1], 0), 4));
13654 /* If the computed address is held in the low order register
13655 then load the high order register first, otherwise always
13656 load the low order register first. */
13657 if (REGNO (operands[0]) == REGNO (base))
13659 output_asm_insn ("ldr\t%H0, %2", operands);
13660 output_asm_insn ("ldr\t%0, %1", operands);
13664 output_asm_insn ("ldr\t%0, %1", operands);
13665 output_asm_insn ("ldr\t%H0, %2", operands);
13671 /* With no registers to worry about we can just load the value
13673 operands[2] = gen_rtx_MEM (SImode,
13674 plus_constant (XEXP (operands[1], 0), 4));
13676 output_asm_insn ("ldr\t%H0, %2", operands);
13677 output_asm_insn ("ldr\t%0, %1", operands);
13689 thumb_output_move_mem_multiple (int n, rtx *operands)
13696 if (REGNO (operands[4]) > REGNO (operands[5]))
13699 operands[4] = operands[5];
13702 output_asm_insn ("ldmia\t%1!, {%4, %5}", operands);
13703 output_asm_insn ("stmia\t%0!, {%4, %5}", operands);
13707 if (REGNO (operands[4]) > REGNO (operands[5]))
13710 operands[4] = operands[5];
13713 if (REGNO (operands[5]) > REGNO (operands[6]))
13716 operands[5] = operands[6];
13719 if (REGNO (operands[4]) > REGNO (operands[5]))
13722 operands[4] = operands[5];
13726 output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands);
13727 output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands);
13737 /* Routines for generating rtl. */
13739 thumb_expand_movstrqi (rtx *operands)
13741 rtx out = copy_to_mode_reg (SImode, XEXP (operands[0], 0));
13742 rtx in = copy_to_mode_reg (SImode, XEXP (operands[1], 0));
13743 HOST_WIDE_INT len = INTVAL (operands[2]);
13744 HOST_WIDE_INT offset = 0;
13748 emit_insn (gen_movmem12b (out, in, out, in));
13754 emit_insn (gen_movmem8b (out, in, out, in));
13760 rtx reg = gen_reg_rtx (SImode);
13761 emit_insn (gen_movsi (reg, gen_rtx_MEM (SImode, in)));
13762 emit_insn (gen_movsi (gen_rtx_MEM (SImode, out), reg));
13769 rtx reg = gen_reg_rtx (HImode);
13770 emit_insn (gen_movhi (reg, gen_rtx_MEM (HImode,
13771 plus_constant (in, offset))));
13772 emit_insn (gen_movhi (gen_rtx_MEM (HImode, plus_constant (out, offset)),
13780 rtx reg = gen_reg_rtx (QImode);
13781 emit_insn (gen_movqi (reg, gen_rtx_MEM (QImode,
13782 plus_constant (in, offset))));
13783 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (out, offset)),
13789 thumb_cmp_operand (rtx op, enum machine_mode mode)
13791 return ((GET_CODE (op) == CONST_INT
13792 && INTVAL (op) < 256
13793 && INTVAL (op) >= 0)
13794 || s_register_operand (op, mode));
13798 thumb_cmpneg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
13800 return (GET_CODE (op) == CONST_INT
13802 && INTVAL (op) > -256);
13805 /* Return TRUE if a result can be stored in OP without clobbering the
13806 condition code register. Prior to reload we only accept a
13807 register. After reload we have to be able to handle memory as
13808 well, since a pseudo may not get a hard reg and reload cannot
13809 handle output-reloads on jump insns.
13811 We could possibly handle mem before reload as well, but that might
13812 complicate things with the need to handle increment
13816 thumb_cbrch_target_operand (rtx op, enum machine_mode mode)
13818 return (s_register_operand (op, mode)
13819 || ((reload_in_progress || reload_completed)
13820 && memory_operand (op, mode)));
13823 /* Handle storing a half-word to memory during reload. */
13825 thumb_reload_out_hi (rtx *operands)
13827 emit_insn (gen_thumb_movhi_clobber (operands[0], operands[1], operands[2]));
13830 /* Handle reading a half-word from memory during reload. */
13832 thumb_reload_in_hi (rtx *operands ATTRIBUTE_UNUSED)
13837 /* Return the length of a function name prefix
13838 that starts with the character 'c'. */
13840 arm_get_strip_length (int c)
13844 ARM_NAME_ENCODING_LENGTHS
13849 /* Return a pointer to a function's name with any
13850 and all prefix encodings stripped from it. */
13852 arm_strip_name_encoding (const char *name)
13856 while ((skip = arm_get_strip_length (* name)))
13862 /* If there is a '*' anywhere in the name's prefix, then
13863 emit the stripped name verbatim, otherwise prepend an
13864 underscore if leading underscores are being used. */
13866 arm_asm_output_labelref (FILE *stream, const char *name)
13871 while ((skip = arm_get_strip_length (* name)))
13873 verbatim |= (*name == '*');
13878 fputs (name, stream);
13880 asm_fprintf (stream, "%U%s", name);
13885 #ifdef AOF_ASSEMBLER
13886 /* Special functions only needed when producing AOF syntax assembler. */
13890 struct pic_chain * next;
13891 const char * symname;
13894 static struct pic_chain * aof_pic_chain = NULL;
13897 aof_pic_entry (rtx x)
13899 struct pic_chain ** chainp;
13902 if (aof_pic_label == NULL_RTX)
13904 aof_pic_label = gen_rtx_SYMBOL_REF (Pmode, "x$adcons");
13907 for (offset = 0, chainp = &aof_pic_chain; *chainp;
13908 offset += 4, chainp = &(*chainp)->next)
13909 if ((*chainp)->symname == XSTR (x, 0))
13910 return plus_constant (aof_pic_label, offset);
13912 *chainp = (struct pic_chain *) xmalloc (sizeof (struct pic_chain));
13913 (*chainp)->next = NULL;
13914 (*chainp)->symname = XSTR (x, 0);
13915 return plus_constant (aof_pic_label, offset);
13919 aof_dump_pic_table (FILE *f)
13921 struct pic_chain * chain;
13923 if (aof_pic_chain == NULL)
13926 asm_fprintf (f, "\tAREA |%r$$adcons|, BASED %r\n",
13927 PIC_OFFSET_TABLE_REGNUM,
13928 PIC_OFFSET_TABLE_REGNUM);
13929 fputs ("|x$adcons|\n", f);
13931 for (chain = aof_pic_chain; chain; chain = chain->next)
13933 fputs ("\tDCD\t", f);
13934 assemble_name (f, chain->symname);
13939 int arm_text_section_count = 1;
13942 aof_text_section (void )
13944 static char buf[100];
13945 sprintf (buf, "\tAREA |C$$code%d|, CODE, READONLY",
13946 arm_text_section_count++);
13948 strcat (buf, ", PIC, REENTRANT");
13952 static int arm_data_section_count = 1;
13955 aof_data_section (void)
13957 static char buf[100];
13958 sprintf (buf, "\tAREA |C$$data%d|, DATA", arm_data_section_count++);
13962 /* The AOF assembler is religiously strict about declarations of
13963 imported and exported symbols, so that it is impossible to declare
13964 a function as imported near the beginning of the file, and then to
13965 export it later on. It is, however, possible to delay the decision
13966 until all the functions in the file have been compiled. To get
13967 around this, we maintain a list of the imports and exports, and
13968 delete from it any that are subsequently defined. At the end of
13969 compilation we spit the remainder of the list out before the END
13974 struct import * next;
13978 static struct import * imports_list = NULL;
13981 aof_add_import (const char *name)
13983 struct import * new;
13985 for (new = imports_list; new; new = new->next)
13986 if (new->name == name)
13989 new = (struct import *) xmalloc (sizeof (struct import));
13990 new->next = imports_list;
13991 imports_list = new;
13996 aof_delete_import (const char *name)
13998 struct import ** old;
14000 for (old = &imports_list; *old; old = & (*old)->next)
14002 if ((*old)->name == name)
14004 *old = (*old)->next;
14010 int arm_main_function = 0;
14013 aof_dump_imports (FILE *f)
14015 /* The AOF assembler needs this to cause the startup code to be extracted
14016 from the library. Brining in __main causes the whole thing to work
14018 if (arm_main_function)
14021 fputs ("\tIMPORT __main\n", f);
14022 fputs ("\tDCD __main\n", f);
14025 /* Now dump the remaining imports. */
14026 while (imports_list)
14028 fprintf (f, "\tIMPORT\t");
14029 assemble_name (f, imports_list->name);
14031 imports_list = imports_list->next;
14036 aof_globalize_label (FILE *stream, const char *name)
14038 default_globalize_label (stream, name);
14039 if (! strcmp (name, "main"))
14040 arm_main_function = 1;
14044 aof_file_start (void)
14046 fputs ("__r0\tRN\t0\n", asm_out_file);
14047 fputs ("__a1\tRN\t0\n", asm_out_file);
14048 fputs ("__a2\tRN\t1\n", asm_out_file);
14049 fputs ("__a3\tRN\t2\n", asm_out_file);
14050 fputs ("__a4\tRN\t3\n", asm_out_file);
14051 fputs ("__v1\tRN\t4\n", asm_out_file);
14052 fputs ("__v2\tRN\t5\n", asm_out_file);
14053 fputs ("__v3\tRN\t6\n", asm_out_file);
14054 fputs ("__v4\tRN\t7\n", asm_out_file);
14055 fputs ("__v5\tRN\t8\n", asm_out_file);
14056 fputs ("__v6\tRN\t9\n", asm_out_file);
14057 fputs ("__sl\tRN\t10\n", asm_out_file);
14058 fputs ("__fp\tRN\t11\n", asm_out_file);
14059 fputs ("__ip\tRN\t12\n", asm_out_file);
14060 fputs ("__sp\tRN\t13\n", asm_out_file);
14061 fputs ("__lr\tRN\t14\n", asm_out_file);
14062 fputs ("__pc\tRN\t15\n", asm_out_file);
14063 fputs ("__f0\tFN\t0\n", asm_out_file);
14064 fputs ("__f1\tFN\t1\n", asm_out_file);
14065 fputs ("__f2\tFN\t2\n", asm_out_file);
14066 fputs ("__f3\tFN\t3\n", asm_out_file);
14067 fputs ("__f4\tFN\t4\n", asm_out_file);
14068 fputs ("__f5\tFN\t5\n", asm_out_file);
14069 fputs ("__f6\tFN\t6\n", asm_out_file);
14070 fputs ("__f7\tFN\t7\n", asm_out_file);
14075 aof_file_end (void)
14078 aof_dump_pic_table (asm_out_file);
14079 aof_dump_imports (asm_out_file);
14080 fputs ("\tEND\n", asm_out_file);
14082 #endif /* AOF_ASSEMBLER */
14084 #ifdef OBJECT_FORMAT_ELF
14085 /* Switch to an arbitrary section NAME with attributes as specified
14086 by FLAGS. ALIGN specifies any known alignment requirements for
14087 the section; 0 if the default should be used.
14089 Differs from the default elf version only in the prefix character
14090 used before the section type. */
14093 arm_elf_asm_named_section (const char *name, unsigned int flags)
14095 char flagchars[10], *f = flagchars;
14097 if (! named_section_first_declaration (name))
14099 fprintf (asm_out_file, "\t.section\t%s\n", name);
14103 if (!(flags & SECTION_DEBUG))
14105 if (flags & SECTION_WRITE)
14107 if (flags & SECTION_CODE)
14109 if (flags & SECTION_SMALL)
14111 if (flags & SECTION_MERGE)
14113 if (flags & SECTION_STRINGS)
14115 if (flags & SECTION_TLS)
14119 fprintf (asm_out_file, "\t.section\t%s,\"%s\"", name, flagchars);
14121 if (!(flags & SECTION_NOTYPE))
14125 if (flags & SECTION_BSS)
14130 fprintf (asm_out_file, ",%%%s", type);
14132 if (flags & SECTION_ENTSIZE)
14133 fprintf (asm_out_file, ",%d", flags & SECTION_ENTSIZE);
14136 putc ('\n', asm_out_file);
14141 /* Symbols in the text segment can be accessed without indirecting via the
14142 constant pool; it may take an extra binary operation, but this is still
14143 faster than indirecting via memory. Don't do this when not optimizing,
14144 since we won't be calculating al of the offsets necessary to do this
14148 arm_encode_section_info (tree decl, rtx rtl, int first)
14150 /* This doesn't work with AOF syntax, since the string table may be in
14151 a different AREA. */
14152 #ifndef AOF_ASSEMBLER
14153 if (optimize > 0 && TREE_CONSTANT (decl))
14154 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;
14157 /* If we are referencing a function that is weak then encode a long call
14158 flag in the function name, otherwise if the function is static or
14159 or known to be defined in this file then encode a short call flag. */
14160 if (first && TREE_CODE_CLASS (TREE_CODE (decl)) == 'd')
14162 if (TREE_CODE (decl) == FUNCTION_DECL && DECL_WEAK (decl))
14163 arm_encode_call_attribute (decl, LONG_CALL_FLAG_CHAR);
14164 else if (! TREE_PUBLIC (decl))
14165 arm_encode_call_attribute (decl, SHORT_CALL_FLAG_CHAR);
14168 #endif /* !ARM_PE */
14171 arm_internal_label (FILE *stream, const char *prefix, unsigned long labelno)
14173 if (arm_ccfsm_state == 3 && (unsigned) arm_target_label == labelno
14174 && !strcmp (prefix, "L"))
14176 arm_ccfsm_state = 0;
14177 arm_target_insn = NULL;
14179 default_internal_label (stream, prefix, labelno);
14182 /* Output code to add DELTA to the first argument, and then jump
14183 to FUNCTION. Used for C++ multiple inheritance. */
14185 arm_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
14186 HOST_WIDE_INT delta,
14187 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
14190 static int thunk_label = 0;
14192 int mi_delta = delta;
14193 const char *const mi_op = mi_delta < 0 ? "sub" : "add";
14195 int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)
14198 mi_delta = - mi_delta;
14201 int labelno = thunk_label++;
14202 ASM_GENERATE_INTERNAL_LABEL (label, "LTHUMBFUNC", labelno);
14203 fputs ("\tldr\tr12, ", file);
14204 assemble_name (file, label);
14205 fputc ('\n', file);
14207 while (mi_delta != 0)
14209 if ((mi_delta & (3 << shift)) == 0)
14213 asm_fprintf (file, "\t%s\t%r, %r, #%d\n",
14214 mi_op, this_regno, this_regno,
14215 mi_delta & (0xff << shift));
14216 mi_delta &= ~(0xff << shift);
14222 fprintf (file, "\tbx\tr12\n");
14223 ASM_OUTPUT_ALIGN (file, 2);
14224 assemble_name (file, label);
14225 fputs (":\n", file);
14226 assemble_integer (XEXP (DECL_RTL (function), 0), 4, BITS_PER_WORD, 1);
14230 fputs ("\tb\t", file);
14231 assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0));
14232 if (NEED_PLT_RELOC)
14233 fputs ("(PLT)", file);
14234 fputc ('\n', file);
14239 arm_emit_vector_const (FILE *file, rtx x)
14242 const char * pattern;
14244 if (GET_CODE (x) != CONST_VECTOR)
14247 switch (GET_MODE (x))
14249 case V2SImode: pattern = "%08x"; break;
14250 case V4HImode: pattern = "%04x"; break;
14251 case V8QImode: pattern = "%02x"; break;
14255 fprintf (file, "0x");
14256 for (i = CONST_VECTOR_NUNITS (x); i--;)
14260 element = CONST_VECTOR_ELT (x, i);
14261 fprintf (file, pattern, INTVAL (element));
14268 arm_output_load_gr (rtx *operands)
14275 if (GET_CODE (operands [1]) != MEM
14276 || GET_CODE (sum = XEXP (operands [1], 0)) != PLUS
14277 || GET_CODE (reg = XEXP (sum, 0)) != REG
14278 || GET_CODE (offset = XEXP (sum, 1)) != CONST_INT
14279 || ((INTVAL (offset) < 1024) && (INTVAL (offset) > -1024)))
14280 return "wldrw%?\t%0, %1";
14282 /* Fix up an out-of-range load of a GR register. */
14283 output_asm_insn ("str%?\t%0, [sp, #-4]!\t@ Start of GR load expansion", & reg);
14284 wcgr = operands[0];
14286 output_asm_insn ("ldr%?\t%0, %1", operands);
14288 operands[0] = wcgr;
14290 output_asm_insn ("tmcr%?\t%0, %1", operands);
14291 output_asm_insn ("ldr%?\t%0, [sp], #4\t@ End of GR load expansion", & reg);
14297 arm_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
14298 int incoming ATTRIBUTE_UNUSED)
14301 /* FIXME: The ARM backend has special code to handle structure
14302 returns, and will reserve its own hidden first argument. So
14303 if this macro is enabled a *second* hidden argument will be
14304 reserved, which will break binary compatibility with old
14305 toolchains and also thunk handling. One day this should be
14309 /* Register in which address to store a structure value
14310 is passed to a function. */
14311 return gen_rtx_REG (Pmode, ARG_REGISTER (1));
14315 /* Worker function for TARGET_SETUP_INCOMING_VARARGS.
14317 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
14318 named arg and all anonymous args onto the stack.
14319 XXX I know the prologue shouldn't be pushing registers, but it is faster
14323 arm_setup_incoming_varargs (CUMULATIVE_ARGS *cum,
14324 enum machine_mode mode ATTRIBUTE_UNUSED,
14325 tree type ATTRIBUTE_UNUSED,
14327 int second_time ATTRIBUTE_UNUSED)
14329 cfun->machine->uses_anonymous_args = 1;
14330 if (cum->nregs < NUM_ARG_REGS)
14331 *pretend_size = (NUM_ARG_REGS - cum->nregs) * UNITS_PER_WORD;
14334 /* Return nonzero if the CONSUMER instruction (a store) does not need
14335 PRODUCER's value to calculate the address. */
14338 arm_no_early_store_addr_dep (rtx producer, rtx consumer)
14340 rtx value = PATTERN (producer);
14341 rtx addr = PATTERN (consumer);
14343 if (GET_CODE (value) == COND_EXEC)
14344 value = COND_EXEC_CODE (value);
14345 if (GET_CODE (value) == PARALLEL)
14346 value = XVECEXP (value, 0, 0);
14347 value = XEXP (value, 0);
14348 if (GET_CODE (addr) == COND_EXEC)
14349 addr = COND_EXEC_CODE (addr);
14350 if (GET_CODE (addr) == PARALLEL)
14351 addr = XVECEXP (addr, 0, 0);
14352 addr = XEXP (addr, 0);
14354 return !reg_overlap_mentioned_p (value, addr);
14357 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
14358 have an early register shift value or amount dependency on the
14359 result of PRODUCER. */
14362 arm_no_early_alu_shift_dep (rtx producer, rtx consumer)
14364 rtx value = PATTERN (producer);
14365 rtx op = PATTERN (consumer);
14368 if (GET_CODE (value) == COND_EXEC)
14369 value = COND_EXEC_CODE (value);
14370 if (GET_CODE (value) == PARALLEL)
14371 value = XVECEXP (value, 0, 0);
14372 value = XEXP (value, 0);
14373 if (GET_CODE (op) == COND_EXEC)
14374 op = COND_EXEC_CODE (op);
14375 if (GET_CODE (op) == PARALLEL)
14376 op = XVECEXP (op, 0, 0);
14379 early_op = XEXP (op, 0);
14380 /* This is either an actual independent shift, or a shift applied to
14381 the first operand of another operation. We want the whole shift
14383 if (GET_CODE (early_op) == REG)
14386 return !reg_overlap_mentioned_p (value, early_op);
14389 /* Return nonzero if the CONSUMER instruction (an ALU op) does not
14390 have an early register shift value dependency on the result of
14394 arm_no_early_alu_shift_value_dep (rtx producer, rtx consumer)
14396 rtx value = PATTERN (producer);
14397 rtx op = PATTERN (consumer);
14400 if (GET_CODE (value) == COND_EXEC)
14401 value = COND_EXEC_CODE (value);
14402 if (GET_CODE (value) == PARALLEL)
14403 value = XVECEXP (value, 0, 0);
14404 value = XEXP (value, 0);
14405 if (GET_CODE (op) == COND_EXEC)
14406 op = COND_EXEC_CODE (op);
14407 if (GET_CODE (op) == PARALLEL)
14408 op = XVECEXP (op, 0, 0);
14411 early_op = XEXP (op, 0);
14413 /* This is either an actual independent shift, or a shift applied to
14414 the first operand of another operation. We want the value being
14415 shifted, in either case. */
14416 if (GET_CODE (early_op) != REG)
14417 early_op = XEXP (early_op, 0);
14419 return !reg_overlap_mentioned_p (value, early_op);
14422 /* Return nonzero if the CONSUMER (a mul or mac op) does not
14423 have an early register mult dependency on the result of
14427 arm_no_early_mul_dep (rtx producer, rtx consumer)
14429 rtx value = PATTERN (producer);
14430 rtx op = PATTERN (consumer);
14432 if (GET_CODE (value) == COND_EXEC)
14433 value = COND_EXEC_CODE (value);
14434 if (GET_CODE (value) == PARALLEL)
14435 value = XVECEXP (value, 0, 0);
14436 value = XEXP (value, 0);
14437 if (GET_CODE (op) == COND_EXEC)
14438 op = COND_EXEC_CODE (op);
14439 if (GET_CODE (op) == PARALLEL)
14440 op = XVECEXP (op, 0, 0);
14443 return (GET_CODE (op) == PLUS
14444 && !reg_overlap_mentioned_p (value, XEXP (op, 0)));