1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
3 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com).
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
46 #include "integrate.h"
49 #include "target-def.h"
51 /* Forward definitions of types. */
52 typedef struct minipool_node Mnode;
53 typedef struct minipool_fixup Mfix;
55 /* In order to improve the layout of the prototypes below
56 some short type abbreviations are defined here. */
57 #define Hint HOST_WIDE_INT
58 #define Mmode enum machine_mode
59 #define Ulong unsigned long
60 #define Ccstar const char *
62 /* Forward function declarations. */
63 static void arm_add_gc_roots PARAMS ((void));
64 static int arm_gen_constant PARAMS ((enum rtx_code, Mmode, Hint, rtx, rtx, int, int));
65 static Ulong bit_count PARAMS ((signed int));
66 static int const_ok_for_op PARAMS ((Hint, enum rtx_code));
67 static int eliminate_lr2ip PARAMS ((rtx *));
68 static rtx emit_multi_reg_push PARAMS ((int));
69 static rtx emit_sfm PARAMS ((int, int));
70 static Ccstar fp_const_from_val PARAMS ((REAL_VALUE_TYPE *));
71 static arm_cc get_arm_condition_code PARAMS ((rtx));
72 static void init_fpa_table PARAMS ((void));
73 static Hint int_log2 PARAMS ((Hint));
74 static rtx is_jump_table PARAMS ((rtx));
75 static Ccstar output_multi_immediate PARAMS ((rtx *, Ccstar, Ccstar, int, Hint));
76 static void print_multi_reg PARAMS ((FILE *, Ccstar, int, int));
77 static Mmode select_dominance_cc_mode PARAMS ((rtx, rtx, Hint));
78 static Ccstar shift_op PARAMS ((rtx, Hint *));
79 static void arm_init_machine_status PARAMS ((struct function *));
80 static void arm_mark_machine_status PARAMS ((struct function *));
81 static void arm_free_machine_status PARAMS ((struct function *));
82 static int number_of_first_bit_set PARAMS ((int));
83 static void replace_symbols_in_block PARAMS ((tree, rtx, rtx));
84 static void thumb_exit PARAMS ((FILE *, int, rtx));
85 static void thumb_pushpop PARAMS ((FILE *, int, int));
86 static Ccstar thumb_condition_code PARAMS ((rtx, int));
87 static rtx is_jump_table PARAMS ((rtx));
88 static Hint get_jump_table_size PARAMS ((rtx));
89 static Mnode * move_minipool_fix_forward_ref PARAMS ((Mnode *, Mnode *, Hint));
90 static Mnode * add_minipool_forward_ref PARAMS ((Mfix *));
91 static Mnode * move_minipool_fix_backward_ref PARAMS ((Mnode *, Mnode *, Hint));
92 static Mnode * add_minipool_backward_ref PARAMS ((Mfix *));
93 static void assign_minipool_offsets PARAMS ((Mfix *));
94 static void arm_print_value PARAMS ((FILE *, rtx));
95 static void dump_minipool PARAMS ((rtx));
96 static int arm_barrier_cost PARAMS ((rtx));
97 static Mfix * create_fix_barrier PARAMS ((Mfix *, Hint));
98 static void push_minipool_barrier PARAMS ((rtx, Hint));
99 static void push_minipool_fix PARAMS ((rtx, Hint, rtx *, Mmode, rtx));
100 static void note_invalid_constants PARAMS ((rtx, Hint));
101 static int current_file_function_operand PARAMS ((rtx));
102 static Ulong arm_compute_save_reg_mask PARAMS ((void));
103 static Ulong arm_isr_value PARAMS ((tree));
104 static Ulong arm_compute_func_type PARAMS ((void));
105 static int arm_valid_type_attribute_p PARAMS ((tree, tree,
107 static int arm_valid_decl_attribute_p PARAMS ((tree, tree,
109 static int arm_comp_type_attributes PARAMS ((tree, tree));
110 static void arm_set_default_type_attributes PARAMS ((tree));
116 /* Initialize the GCC target structure. */
117 #ifdef TARGET_DLLIMPORT_DECL_ATTRIBUTES
118 #undef TARGET_MERGE_DECL_ATTRIBUTES
119 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
122 #undef TARGET_VALID_TYPE_ATTRIBUTE
123 #define TARGET_VALID_TYPE_ATTRIBUTE arm_valid_type_attribute_p
125 #undef TARGET_VALID_DECL_ATTRIBUTE
127 static int arm_pe_valid_decl_attribute_p PARAMS ((tree, tree, tree, tree));
128 # define TARGET_VALID_DECL_ATTRIBUTE arm_pe_valid_decl_attribute_p
130 # define TARGET_VALID_DECL_ATTRIBUTE arm_valid_decl_attribute_p
133 #undef TARGET_COMP_TYPE_ATTRIBUTES
134 #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes
136 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
137 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes
139 struct gcc_target target = TARGET_INITIALIZER;
141 /* Obstack for minipool constant handling. */
142 static struct obstack minipool_obstack;
143 static char *minipool_startobj;
145 #define obstack_chunk_alloc xmalloc
146 #define obstack_chunk_free free
148 /* The maximum number of insns skipped which will be conditionalised if
150 static int max_insns_skipped = 5;
152 extern FILE * asm_out_file;
154 /* True if we are currently building a constant table. */
155 int making_const_table;
157 /* Define the information needed to generate branch insns. This is
158 stored from the compare operation. */
159 rtx arm_compare_op0, arm_compare_op1;
161 /* What type of floating point are we tuning for? */
162 enum floating_point_type arm_fpu;
164 /* What type of floating point instructions are available? */
165 enum floating_point_type arm_fpu_arch;
167 /* What program mode is the cpu running in? 26-bit mode or 32-bit mode. */
168 enum prog_mode_type arm_prgmode;
170 /* Set by the -mfp=... option. */
171 const char * target_fp_name = NULL;
173 /* Used to parse -mstructure_size_boundary command line option. */
174 const char * structure_size_string = NULL;
175 int arm_structure_size_boundary = DEFAULT_STRUCTURE_SIZE_BOUNDARY;
177 /* Bit values used to identify processor capabilities. */
178 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
179 #define FL_FAST_MULT (1 << 1) /* Fast multiply */
180 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
181 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
182 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
183 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
184 #define FL_THUMB (1 << 6) /* Thumb aware */
185 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
186 #define FL_STRONG (1 << 8) /* StrongARM */
187 #define FL_ARCH5E (1 << 9) /* DSP extenstions to v5 */
188 #define FL_XSCALE (1 << 10) /* XScale */
190 /* The bits in this mask specify which instructions we are
191 allowed to generate. */
192 static int insn_flags = 0;
194 /* The bits in this mask specify which instruction scheduling options should
195 be used. Note - there is an overlap with the FL_FAST_MULT. For some
196 hardware we want to be able to generate the multiply instructions, but to
197 tune as if they were not present in the architecture. */
198 static int tune_flags = 0;
200 /* The following are used in the arm.md file as equivalents to bits
201 in the above two flag variables. */
203 /* Nonzero if this is an "M" variant of the processor. */
204 int arm_fast_multiply = 0;
206 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
209 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
212 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
215 /* Nonzero if this chip can benefit from load scheduling. */
216 int arm_ld_sched = 0;
218 /* Nonzero if this chip is a StrongARM. */
219 int arm_is_strong = 0;
221 /* Nonzero if this chip is an XScale. */
222 int arm_is_xscale = 0;
224 /* Nonzero if this chip is a an ARM6 or an ARM7. */
225 int arm_is_6_or_7 = 0;
227 /* Nonzero if generating Thumb instructions. */
230 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
231 must report the mode of the memory reference from PRINT_OPERAND to
232 PRINT_OPERAND_ADDRESS. */
233 enum machine_mode output_memory_reference_mode;
235 /* Nonzero if the prologue must setup `fp'. */
236 int current_function_anonymous_args;
238 /* The register number to be used for the PIC offset register. */
239 const char * arm_pic_register_string = NULL;
240 int arm_pic_register = 9;
242 /* Set to 1 when a return insn is output, this means that the epilogue
244 int return_used_this_function;
246 /* Set to 1 after arm_reorg has started. Reset to start at the start of
247 the next function. */
248 static int after_arm_reorg = 0;
250 /* The maximum number of insns to be used when loading a constant. */
251 static int arm_constant_limit = 3;
253 /* For an explanation of these variables, see final_prescan_insn below. */
255 enum arm_cond_code arm_current_cc;
257 int arm_target_label;
259 /* The condition codes of the ARM, and the inverse function. */
260 const char * arm_condition_codes[] =
262 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
263 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
266 #define streq(string1, string2) (strcmp (string1, string2) == 0)
268 /* Initialization code. */
276 /* Not all of these give usefully different compilation alternatives,
277 but there is no simple way of generalizing them. */
278 static struct processors all_cores[] =
282 {"arm2", FL_CO_PROC | FL_MODE26 },
283 {"arm250", FL_CO_PROC | FL_MODE26 },
284 {"arm3", FL_CO_PROC | FL_MODE26 },
285 {"arm6", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
286 {"arm60", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
287 {"arm600", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
288 {"arm610", FL_MODE26 | FL_MODE32 },
289 {"arm620", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
290 {"arm7", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
291 /* arm7m doesn't exist on its own, but only with D, (and I), but
292 those don't alter the code, so arm7m is sometimes used. */
293 {"arm7m", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
294 {"arm7d", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
295 {"arm7dm", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
296 {"arm7di", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
297 {"arm7dmi", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
298 {"arm70", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
299 {"arm700", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
300 {"arm700i", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
301 {"arm710", FL_MODE26 | FL_MODE32 },
302 {"arm710t", FL_MODE26 | FL_MODE32 | FL_THUMB },
303 {"arm720", FL_MODE26 | FL_MODE32 },
304 {"arm720t", FL_MODE26 | FL_MODE32 | FL_THUMB },
305 {"arm740t", FL_MODE26 | FL_MODE32 | FL_THUMB },
306 {"arm710c", FL_MODE26 | FL_MODE32 },
307 {"arm7100", FL_MODE26 | FL_MODE32 },
308 {"arm7500", FL_MODE26 | FL_MODE32 },
309 /* Doesn't have an external co-proc, but does have embedded fpu. */
310 {"arm7500fe", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
311 {"arm7tdmi", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB },
312 {"arm8", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED },
313 {"arm810", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED },
314 {"arm9", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED },
315 {"arm920", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED },
316 {"arm920t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED },
317 {"arm940t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED },
318 {"arm9tdmi", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED },
319 {"arm9e", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED },
320 {"strongarm", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG },
321 {"strongarm110", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG },
322 {"strongarm1100", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG },
323 {"strongarm1110", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG },
324 {"arm10tdmi", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_ARCH5 },
325 {"arm1020t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_ARCH5 },
326 {"xscale", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_STRONG | FL_ARCH5 | FL_ARCH5E | FL_XSCALE },
331 static struct processors all_architectures[] =
333 /* ARM Architectures */
335 { "armv2", FL_CO_PROC | FL_MODE26 },
336 { "armv2a", FL_CO_PROC | FL_MODE26 },
337 { "armv3", FL_CO_PROC | FL_MODE26 | FL_MODE32 },
338 { "armv3m", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT },
339 { "armv4", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 },
340 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
341 implementations that support it, so we will leave it out for now. */
342 { "armv4t", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB },
343 { "armv5", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 },
344 { "armv5t", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 },
345 { "armv5te", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E },
349 /* This is a magic stucture. The 'string' field is magically filled in
350 with a pointer to the value specified by the user on the command line
351 assuming that the user has specified such a value. */
353 struct arm_cpu_select arm_select[] =
355 /* string name processors */
356 { NULL, "-mcpu=", all_cores },
357 { NULL, "-march=", all_architectures },
358 { NULL, "-mtune=", all_cores }
361 /* Return the number of bits set in value' */
366 unsigned long count = 0;
370 value &= ~(value & -value);
377 /* Fix up any incompatible options that the user has specified.
378 This has now turned into a maze. */
380 arm_override_options ()
384 /* Set up the flags based on the cpu/architecture selected by the user. */
385 for (i = ARRAY_SIZE (arm_select); i--;)
387 struct arm_cpu_select * ptr = arm_select + i;
389 if (ptr->string != NULL && ptr->string[0] != '\0')
391 const struct processors * sel;
393 for (sel = ptr->processors; sel->name != NULL; sel++)
394 if (streq (ptr->string, sel->name))
397 tune_flags = sel->flags;
400 /* If we have been given an architecture and a processor
401 make sure that they are compatible. We only generate
402 a warning though, and we prefer the CPU over the
404 if (insn_flags != 0 && (insn_flags ^ sel->flags))
405 warning ("switch -mcpu=%s conflicts with -march= switch",
408 insn_flags = sel->flags;
414 if (sel->name == NULL)
415 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
419 /* If the user did not specify a processor, choose one for them. */
422 struct processors * sel;
424 static struct cpu_default
431 { TARGET_CPU_arm2, "arm2" },
432 { TARGET_CPU_arm6, "arm6" },
433 { TARGET_CPU_arm610, "arm610" },
434 { TARGET_CPU_arm710, "arm710" },
435 { TARGET_CPU_arm7m, "arm7m" },
436 { TARGET_CPU_arm7500fe, "arm7500fe" },
437 { TARGET_CPU_arm7tdmi, "arm7tdmi" },
438 { TARGET_CPU_arm8, "arm8" },
439 { TARGET_CPU_arm810, "arm810" },
440 { TARGET_CPU_arm9, "arm9" },
441 { TARGET_CPU_strongarm, "strongarm" },
442 { TARGET_CPU_xscale, "xscale" },
443 { TARGET_CPU_generic, "arm" },
446 struct cpu_default * def;
448 /* Find the default. */
449 for (def = cpu_defaults; def->name; def++)
450 if (def->cpu == TARGET_CPU_DEFAULT)
453 /* Make sure we found the default CPU. */
454 if (def->name == NULL)
457 /* Find the default CPU's flags. */
458 for (sel = all_cores; sel->name != NULL; sel++)
459 if (streq (def->name, sel->name))
462 if (sel->name == NULL)
465 insn_flags = sel->flags;
467 /* Now check to see if the user has specified some command line
468 switch that require certain abilities from the cpu. */
471 if (TARGET_INTERWORK || TARGET_THUMB)
473 sought |= (FL_THUMB | FL_MODE32);
475 /* Force apcs-32 to be used for interworking. */
476 target_flags |= ARM_FLAG_APCS_32;
478 /* There are no ARM processors that support both APCS-26 and
479 interworking. Therefore we force FL_MODE26 to be removed
480 from insn_flags here (if it was set), so that the search
481 below will always be able to find a compatible processor. */
482 insn_flags &= ~FL_MODE26;
484 else if (!TARGET_APCS_32)
487 if (sought != 0 && ((sought & insn_flags) != sought))
489 /* Try to locate a CPU type that supports all of the abilities
490 of the default CPU, plus the extra abilities requested by
492 for (sel = all_cores; sel->name != NULL; sel++)
493 if ((sel->flags & sought) == (sought | insn_flags))
496 if (sel->name == NULL)
498 unsigned int current_bit_count = 0;
499 struct processors * best_fit = NULL;
501 /* Ideally we would like to issue an error message here
502 saying that it was not possible to find a CPU compatible
503 with the default CPU, but which also supports the command
504 line options specified by the programmer, and so they
505 ought to use the -mcpu=<name> command line option to
506 override the default CPU type.
508 Unfortunately this does not work with multilibing. We
509 need to be able to support multilibs for -mapcs-26 and for
510 -mthumb-interwork and there is no CPU that can support both
511 options. Instead if we cannot find a cpu that has both the
512 characteristics of the default cpu and the given command line
513 options we scan the array again looking for a best match. */
514 for (sel = all_cores; sel->name != NULL; sel++)
515 if ((sel->flags & sought) == sought)
519 count = bit_count (sel->flags & insn_flags);
521 if (count >= current_bit_count)
524 current_bit_count = count;
528 if (best_fit == NULL)
534 insn_flags = sel->flags;
538 /* If tuning has not been specified, tune for whichever processor or
539 architecture has been selected. */
541 tune_flags = insn_flags;
543 /* Make sure that the processor choice does not conflict with any of the
544 other command line choices. */
545 if (TARGET_APCS_32 && !(insn_flags & FL_MODE32))
547 /* If APCS-32 was not the default then it must have been set by the
548 user, so issue a warning message. If the user has specified
549 "-mapcs-32 -mcpu=arm2" then we loose here. */
550 if ((TARGET_DEFAULT & ARM_FLAG_APCS_32) == 0)
551 warning ("target CPU does not support APCS-32" );
552 target_flags &= ~ARM_FLAG_APCS_32;
554 else if (!TARGET_APCS_32 && !(insn_flags & FL_MODE26))
556 warning ("target CPU does not support APCS-26" );
557 target_flags |= ARM_FLAG_APCS_32;
560 if (TARGET_INTERWORK && !(insn_flags & FL_THUMB))
562 warning ("target CPU does not support interworking" );
563 target_flags &= ~ARM_FLAG_INTERWORK;
566 if (TARGET_THUMB && !(insn_flags & FL_THUMB))
568 warning ("target CPU does not support THUMB instructions.");
569 target_flags &= ~ARM_FLAG_THUMB;
572 if (TARGET_APCS_FRAME && TARGET_THUMB)
574 /* warning ("ignoring -mapcs-frame because -mthumb was used."); */
575 target_flags &= ~ARM_FLAG_APCS_FRAME;
578 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
579 from here where no function is being compiled currently. */
580 if ((target_flags & (THUMB_FLAG_LEAF_BACKTRACE | THUMB_FLAG_BACKTRACE))
582 warning ("enabling backtrace support is only meaningful when compiling for the Thumb.");
584 if (TARGET_ARM && TARGET_CALLEE_INTERWORKING)
585 warning ("enabling callee interworking support is only meaningful when compiling for the Thumb.");
587 if (TARGET_ARM && TARGET_CALLER_INTERWORKING)
588 warning ("enabling caller interworking support is only meaningful when compiling for the Thumb.");
590 /* If interworking is enabled then APCS-32 must be selected as well. */
591 if (TARGET_INTERWORK)
594 warning ("interworking forces APCS-32 to be used" );
595 target_flags |= ARM_FLAG_APCS_32;
598 if (TARGET_APCS_STACK && !TARGET_APCS_FRAME)
600 warning ("-mapcs-stack-check incompatible with -mno-apcs-frame");
601 target_flags |= ARM_FLAG_APCS_FRAME;
604 if (TARGET_POKE_FUNCTION_NAME)
605 target_flags |= ARM_FLAG_APCS_FRAME;
607 if (TARGET_APCS_REENT && flag_pic)
608 error ("-fpic and -mapcs-reent are incompatible");
610 if (TARGET_APCS_REENT)
611 warning ("APCS reentrant code not supported. Ignored");
613 /* If this target is normally configured to use APCS frames, warn if they
614 are turned off and debugging is turned on. */
616 && write_symbols != NO_DEBUG
617 && !TARGET_APCS_FRAME
618 && (TARGET_DEFAULT & ARM_FLAG_APCS_FRAME))
619 warning ("-g with -mno-apcs-frame may not give sensible debugging");
621 /* If stack checking is disabled, we can use r10 as the PIC register,
622 which keeps r9 available. */
623 if (flag_pic && !TARGET_APCS_STACK)
624 arm_pic_register = 10;
626 if (TARGET_APCS_FLOAT)
627 warning ("Passing floating point arguments in fp regs not yet supported");
629 /* Initialise boolean versions of the flags, for use in the arm.md file. */
630 arm_fast_multiply = (insn_flags & FL_FAST_MULT) != 0;
631 arm_arch4 = (insn_flags & FL_ARCH4) != 0;
632 arm_arch5 = (insn_flags & FL_ARCH5) != 0;
633 arm_arch5e = (insn_flags & FL_ARCH5E) != 0;
634 arm_is_xscale = (insn_flags & FL_XSCALE) != 0;
636 arm_ld_sched = (tune_flags & FL_LDSCHED) != 0;
637 arm_is_strong = (tune_flags & FL_STRONG) != 0;
638 thumb_code = (TARGET_ARM == 0);
639 arm_is_6_or_7 = (((tune_flags & (FL_MODE26 | FL_MODE32))
640 && !(tune_flags & FL_ARCH4))) != 0;
642 /* Default value for floating point code... if no co-processor
643 bus, then schedule for emulated floating point. Otherwise,
644 assume the user has an FPA.
645 Note: this does not prevent use of floating point instructions,
646 -msoft-float does that. */
647 arm_fpu = (tune_flags & FL_CO_PROC) ? FP_HARD : FP_SOFT3;
651 if (streq (target_fp_name, "2"))
652 arm_fpu_arch = FP_SOFT2;
653 else if (streq (target_fp_name, "3"))
654 arm_fpu_arch = FP_SOFT3;
656 error ("Invalid floating point emulation option: -mfpe-%s",
660 arm_fpu_arch = FP_DEFAULT;
662 if (TARGET_FPE && arm_fpu != FP_HARD)
665 /* For arm2/3 there is no need to do any scheduling if there is only
666 a floating point emulator, or we are doing software floating-point. */
667 if ((TARGET_SOFT_FLOAT || arm_fpu != FP_HARD)
668 && (tune_flags & FL_MODE32) == 0)
669 flag_schedule_insns = flag_schedule_insns_after_reload = 0;
671 arm_prgmode = TARGET_APCS_32 ? PROG_MODE_PROG32 : PROG_MODE_PROG26;
673 if (structure_size_string != NULL)
675 int size = strtol (structure_size_string, NULL, 0);
677 if (size == 8 || size == 32)
678 arm_structure_size_boundary = size;
680 warning ("Structure size boundary can only be set to 8 or 32");
683 if (arm_pic_register_string != NULL)
688 warning ("-mpic-register= is useless without -fpic");
690 pic_register = decode_reg_name (arm_pic_register_string);
692 /* Prevent the user from choosing an obviously stupid PIC register. */
693 if (pic_register < 0 || call_used_regs[pic_register]
694 || pic_register == HARD_FRAME_POINTER_REGNUM
695 || pic_register == STACK_POINTER_REGNUM
696 || pic_register >= PC_REGNUM)
697 error ("Unable to use '%s' for PIC register", arm_pic_register_string);
699 arm_pic_register = pic_register;
702 if (TARGET_THUMB && flag_schedule_insns)
704 /* Don't warn since it's on by default in -O2. */
705 flag_schedule_insns = 0;
708 /* If optimizing for space, don't synthesize constants.
709 For processors with load scheduling, it never costs more than 2 cycles
710 to load a constant, and the load scheduler may well reduce that to 1. */
711 if (optimize_size || (tune_flags & FL_LDSCHED))
712 arm_constant_limit = 1;
715 arm_constant_limit = 2;
717 /* If optimizing for size, bump the number of instructions that we
718 are prepared to conditionally execute (even on a StrongARM).
719 Otherwise for the StrongARM, which has early execution of branches,
720 a sequence that is worth skipping is shorter. */
722 max_insns_skipped = 6;
723 else if (arm_is_strong)
724 max_insns_skipped = 3;
726 /* Register global variables with the garbage collector. */
733 ggc_add_rtx_root (&arm_compare_op0, 1);
734 ggc_add_rtx_root (&arm_compare_op1, 1);
735 ggc_add_rtx_root (&arm_target_insn, 1); /* Not sure this is really a root. */
737 gcc_obstack_init(&minipool_obstack);
738 minipool_startobj = (char *) obstack_alloc (&minipool_obstack, 0);
741 /* A table of known ARM exception types.
742 For use with the interrupt function attribute. */
747 unsigned long return_value;
751 static isr_attribute_arg isr_attribute_args [] =
753 { "IRQ", ARM_FT_ISR },
754 { "irq", ARM_FT_ISR },
755 { "FIQ", ARM_FT_FIQ },
756 { "fiq", ARM_FT_FIQ },
757 { "ABORT", ARM_FT_ISR },
758 { "abort", ARM_FT_ISR },
759 { "ABORT", ARM_FT_ISR },
760 { "abort", ARM_FT_ISR },
761 { "UNDEF", ARM_FT_EXCEPTION },
762 { "undef", ARM_FT_EXCEPTION },
763 { "SWI", ARM_FT_EXCEPTION },
764 { "swi", ARM_FT_EXCEPTION },
765 { NULL, ARM_FT_NORMAL }
768 /* Returns the (interrupt) function type of the current
769 function, or ARM_FT_UNKNOWN if the type cannot be determined. */
772 arm_isr_value (argument)
775 isr_attribute_arg * ptr;
778 /* No argument - default to IRQ. */
779 if (argument == NULL_TREE)
782 /* Get the value of the argument. */
783 if (TREE_VALUE (argument) == NULL_TREE
784 || TREE_CODE (TREE_VALUE (argument)) != STRING_CST)
785 return ARM_FT_UNKNOWN;
787 arg = TREE_STRING_POINTER (TREE_VALUE (argument));
789 /* Check it against the list of known arguments. */
790 for (ptr = isr_attribute_args; ptr->arg != NULL; ptr ++)
791 if (strcmp (arg, ptr->arg) == 0)
792 return ptr->return_value;
794 /* An unrecognised interrupt type. */
795 return ARM_FT_UNKNOWN;
798 /* Computes the type of the current function. */
801 arm_compute_func_type ()
803 unsigned long type = ARM_FT_UNKNOWN;
807 if (TREE_CODE (current_function_decl) != FUNCTION_DECL)
810 /* Decide if the current function is volatile. Such functions
811 never return, and many memory cycles can be saved by not storing
812 register values that will never be needed again. This optimization
813 was added to speed up context switching in a kernel application. */
815 && current_function_nothrow
816 && TREE_THIS_VOLATILE (current_function_decl))
817 type |= ARM_FT_VOLATILE;
819 if (current_function_needs_context)
820 type |= ARM_FT_NESTED;
822 attr = DECL_MACHINE_ATTRIBUTES (current_function_decl);
824 a = lookup_attribute ("naked", attr);
826 type |= ARM_FT_NAKED;
828 if (cfun->machine->eh_epilogue_sp_ofs != NULL_RTX)
829 type |= ARM_FT_EXCEPTION_HANDLER;
832 a = lookup_attribute ("isr", attr);
834 a = lookup_attribute ("interrupt", attr);
837 type |= TARGET_INTERWORK ? ARM_FT_INTERWORKED : ARM_FT_NORMAL;
839 type |= arm_isr_value (TREE_VALUE (a));
845 /* Returns the type of the current function. */
848 arm_current_func_type ()
850 if (ARM_FUNC_TYPE (cfun->machine->func_type) == ARM_FT_UNKNOWN)
851 cfun->machine->func_type = arm_compute_func_type ();
853 return cfun->machine->func_type;
856 /* Return 1 if it is possible to return using a single instruction. */
859 use_return_insn (iscond)
863 unsigned int func_type;
865 /* Never use a return instruction before reload has run. */
866 if (!reload_completed)
869 func_type = arm_current_func_type ();
871 /* Naked functions, volatile functiond and interrupt
872 functions all need special consideration. */
873 if (func_type & (ARM_FT_INTERRUPT | ARM_FT_VOLATILE | ARM_FT_NAKED))
876 /* As do variadic functions. */
877 if (current_function_pretend_args_size
878 || current_function_anonymous_args
879 /* Of if the function calls __builtin_eh_return () */
880 || ARM_FUNC_TYPE (func_type) == ARM_FT_EXCEPTION_HANDLER
881 /* Or if there is no frame pointer and there is a stack adjustment. */
882 || ((get_frame_size () + current_function_outgoing_args_size != 0)
883 && !frame_pointer_needed))
886 /* Can't be done if interworking with Thumb, and any registers have been
887 stacked. Similarly, on StrongARM, conditional returns are expensive
888 if they aren't taken and registers have been stacked. */
889 if (iscond && arm_is_strong && frame_pointer_needed)
892 if ((iscond && arm_is_strong)
895 for (regno = 0; regno <= LAST_ARM_REGNUM; regno++)
896 if (regs_ever_live[regno] && !call_used_regs[regno])
899 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
903 /* Can't be done if any of the FPU regs are pushed,
904 since this also requires an insn. */
905 if (TARGET_HARD_FLOAT)
906 for (regno = FIRST_ARM_FP_REGNUM; regno <= LAST_ARM_FP_REGNUM; regno++)
907 if (regs_ever_live[regno] && !call_used_regs[regno])
913 /* Return TRUE if int I is a valid immediate ARM constant. */
919 unsigned HOST_WIDE_INT mask = ~HOST_UINT (0xFF);
921 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
922 be all zero, or all one. */
923 if ((i & ~HOST_UINT (0xffffffff)) != 0
924 && ((i & ~HOST_UINT (0xffffffff))
926 & ~HOST_UINT (0xffffffff))))
929 /* Fast return for 0 and powers of 2 */
930 if ((i & (i - 1)) == 0)
935 if ((i & mask & HOST_UINT (0xffffffff)) == 0)
938 (mask << 2) | ((mask & HOST_UINT (0xffffffff))
939 >> (32 - 2)) | ~(HOST_UINT (0xffffffff));
940 } while (mask != ~HOST_UINT (0xFF));
945 /* Return true if I is a valid constant for the operation CODE. */
947 const_ok_for_op (i, code)
951 if (const_ok_for_arm (i))
957 return const_ok_for_arm (ARM_SIGN_EXTEND (-i));
959 case MINUS: /* Should only occur with (MINUS I reg) => rsb */
965 return const_ok_for_arm (ARM_SIGN_EXTEND (~i));
972 /* Emit a sequence of insns to handle a large constant.
973 CODE is the code of the operation required, it can be any of SET, PLUS,
974 IOR, AND, XOR, MINUS;
975 MODE is the mode in which the operation is being performed;
976 VAL is the integer to operate on;
977 SOURCE is the other operand (a register, or a null-pointer for SET);
978 SUBTARGETS means it is safe to create scratch registers if that will
979 either produce a simpler sequence, or we will want to cse the values.
980 Return value is the number of insns emitted. */
983 arm_split_constant (code, mode, val, target, source, subtargets)
985 enum machine_mode mode;
991 if (subtargets || code == SET
992 || (GET_CODE (target) == REG && GET_CODE (source) == REG
993 && REGNO (target) != REGNO (source)))
995 /* After arm_reorg has been called, we can't fix up expensive
996 constants by pushing them into memory so we must synthesise
997 them in-line, regardless of the cost. This is only likely to
998 be more costly on chips that have load delay slots and we are
999 compiling without running the scheduler (so no splitting
1000 occurred before the final instruction emission).
1002 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
1004 if (!after_arm_reorg
1005 && (arm_gen_constant (code, mode, val, target, source, 1, 0)
1006 > arm_constant_limit + (code != SET)))
1010 /* Currently SET is the only monadic value for CODE, all
1011 the rest are diadic. */
1012 emit_insn (gen_rtx_SET (VOIDmode, target, GEN_INT (val)));
1017 rtx temp = subtargets ? gen_reg_rtx (mode) : target;
1019 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (val)));
1020 /* For MINUS, the value is subtracted from, since we never
1021 have subtraction of a constant. */
1023 emit_insn (gen_rtx_SET (VOIDmode, target,
1024 gen_rtx_MINUS (mode, temp, source)));
1026 emit_insn (gen_rtx_SET (VOIDmode, target,
1027 gen_rtx (code, mode, source, temp)));
1033 return arm_gen_constant (code, mode, val, target, source, subtargets, 1);
1037 count_insns_for_constant (HOST_WIDE_INT remainder, int i)
1039 HOST_WIDE_INT temp1;
1047 if (remainder & (3 << (i - 2)))
1052 temp1 = remainder & ((0x0ff << end)
1053 | ((i < end) ? (0xff >> (32 - end)) : 0));
1054 remainder &= ~temp1;
1059 } while (remainder);
1063 /* As above, but extra parameter GENERATE which, if clear, suppresses
1066 arm_gen_constant (code, mode, val, target, source, subtargets, generate)
1068 enum machine_mode mode;
1077 int can_negate_initial = 0;
1080 int num_bits_set = 0;
1081 int set_sign_bit_copies = 0;
1082 int clear_sign_bit_copies = 0;
1083 int clear_zero_bit_copies = 0;
1084 int set_zero_bit_copies = 0;
1086 unsigned HOST_WIDE_INT temp1, temp2;
1087 unsigned HOST_WIDE_INT remainder = val & HOST_UINT (0xffffffff);
1089 /* Find out which operations are safe for a given CODE. Also do a quick
1090 check for degenerate cases; these can occur when DImode operations
1102 can_negate_initial = 1;
1106 if (remainder == HOST_UINT (0xffffffff))
1109 emit_insn (gen_rtx_SET (VOIDmode, target,
1110 GEN_INT (ARM_SIGN_EXTEND (val))));
1115 if (reload_completed && rtx_equal_p (target, source))
1118 emit_insn (gen_rtx_SET (VOIDmode, target, source));
1127 emit_insn (gen_rtx_SET (VOIDmode, target, const0_rtx));
1130 if (remainder == HOST_UINT (0xffffffff))
1132 if (reload_completed && rtx_equal_p (target, source))
1135 emit_insn (gen_rtx_SET (VOIDmode, target, source));
1144 if (reload_completed && rtx_equal_p (target, source))
1147 emit_insn (gen_rtx_SET (VOIDmode, target, source));
1150 if (remainder == HOST_UINT (0xffffffff))
1153 emit_insn (gen_rtx_SET (VOIDmode, target,
1154 gen_rtx_NOT (mode, source)));
1158 /* We don't know how to handle this yet below. */
1162 /* We treat MINUS as (val - source), since (source - val) is always
1163 passed as (source + (-val)). */
1167 emit_insn (gen_rtx_SET (VOIDmode, target,
1168 gen_rtx_NEG (mode, source)));
1171 if (const_ok_for_arm (val))
1174 emit_insn (gen_rtx_SET (VOIDmode, target,
1175 gen_rtx_MINUS (mode, GEN_INT (val),
1187 /* If we can do it in one insn get out quickly. */
1188 if (const_ok_for_arm (val)
1189 || (can_negate_initial && const_ok_for_arm (-val))
1190 || (can_invert && const_ok_for_arm (~val)))
1193 emit_insn (gen_rtx_SET (VOIDmode, target,
1194 (source ? gen_rtx (code, mode, source,
1200 /* Calculate a few attributes that may be useful for specific
1202 for (i = 31; i >= 0; i--)
1204 if ((remainder & (1 << i)) == 0)
1205 clear_sign_bit_copies++;
1210 for (i = 31; i >= 0; i--)
1212 if ((remainder & (1 << i)) != 0)
1213 set_sign_bit_copies++;
1218 for (i = 0; i <= 31; i++)
1220 if ((remainder & (1 << i)) == 0)
1221 clear_zero_bit_copies++;
1226 for (i = 0; i <= 31; i++)
1228 if ((remainder & (1 << i)) != 0)
1229 set_zero_bit_copies++;
1237 /* See if we can do this by sign_extending a constant that is known
1238 to be negative. This is a good, way of doing it, since the shift
1239 may well merge into a subsequent insn. */
1240 if (set_sign_bit_copies > 1)
1242 if (const_ok_for_arm
1243 (temp1 = ARM_SIGN_EXTEND (remainder
1244 << (set_sign_bit_copies - 1))))
1248 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1249 emit_insn (gen_rtx_SET (VOIDmode, new_src,
1251 emit_insn (gen_ashrsi3 (target, new_src,
1252 GEN_INT (set_sign_bit_copies - 1)));
1256 /* For an inverted constant, we will need to set the low bits,
1257 these will be shifted out of harm's way. */
1258 temp1 |= (1 << (set_sign_bit_copies - 1)) - 1;
1259 if (const_ok_for_arm (~temp1))
1263 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1264 emit_insn (gen_rtx_SET (VOIDmode, new_src,
1266 emit_insn (gen_ashrsi3 (target, new_src,
1267 GEN_INT (set_sign_bit_copies - 1)));
1273 /* See if we can generate this by setting the bottom (or the top)
1274 16 bits, and then shifting these into the other half of the
1275 word. We only look for the simplest cases, to do more would cost
1276 too much. Be careful, however, not to generate this when the
1277 alternative would take fewer insns. */
1278 if (val & HOST_UINT (0xffff0000))
1280 temp1 = remainder & HOST_UINT (0xffff0000);
1281 temp2 = remainder & 0x0000ffff;
1283 /* Overlaps outside this range are best done using other methods. */
1284 for (i = 9; i < 24; i++)
1286 if ((((temp2 | (temp2 << i))
1287 & HOST_UINT (0xffffffff)) == remainder)
1288 && !const_ok_for_arm (temp2))
1290 rtx new_src = (subtargets
1291 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
1293 insns = arm_gen_constant (code, mode, temp2, new_src,
1294 source, subtargets, generate);
1297 emit_insn (gen_rtx_SET
1300 gen_rtx_ASHIFT (mode, source,
1307 /* Don't duplicate cases already considered. */
1308 for (i = 17; i < 24; i++)
1310 if (((temp1 | (temp1 >> i)) == remainder)
1311 && !const_ok_for_arm (temp1))
1313 rtx new_src = (subtargets
1314 ? (generate ? gen_reg_rtx (mode) : NULL_RTX)
1316 insns = arm_gen_constant (code, mode, temp1, new_src,
1317 source, subtargets, generate);
1321 (gen_rtx_SET (VOIDmode, target,
1324 gen_rtx_LSHIFTRT (mode, source,
1335 /* If we have IOR or XOR, and the constant can be loaded in a
1336 single instruction, and we can find a temporary to put it in,
1337 then this can be done in two instructions instead of 3-4. */
1339 /* TARGET can't be NULL if SUBTARGETS is 0 */
1340 || (reload_completed && !reg_mentioned_p (target, source)))
1342 if (const_ok_for_arm (ARM_SIGN_EXTEND (~val)))
1346 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1348 emit_insn (gen_rtx_SET (VOIDmode, sub, GEN_INT (val)));
1349 emit_insn (gen_rtx_SET (VOIDmode, target,
1350 gen_rtx (code, mode, source, sub)));
1359 if (set_sign_bit_copies > 8
1360 && (val & (-1 << (32 - set_sign_bit_copies))) == val)
1364 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1365 rtx shift = GEN_INT (set_sign_bit_copies);
1367 emit_insn (gen_rtx_SET (VOIDmode, sub,
1369 gen_rtx_ASHIFT (mode,
1372 emit_insn (gen_rtx_SET (VOIDmode, target,
1374 gen_rtx_LSHIFTRT (mode, sub,
1380 if (set_zero_bit_copies > 8
1381 && (remainder & ((1 << set_zero_bit_copies) - 1)) == remainder)
1385 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1386 rtx shift = GEN_INT (set_zero_bit_copies);
1388 emit_insn (gen_rtx_SET (VOIDmode, sub,
1390 gen_rtx_LSHIFTRT (mode,
1393 emit_insn (gen_rtx_SET (VOIDmode, target,
1395 gen_rtx_ASHIFT (mode, sub,
1401 if (const_ok_for_arm (temp1 = ARM_SIGN_EXTEND (~val)))
1405 rtx sub = subtargets ? gen_reg_rtx (mode) : target;
1406 emit_insn (gen_rtx_SET (VOIDmode, sub,
1407 gen_rtx_NOT (mode, source)));
1410 sub = gen_reg_rtx (mode);
1411 emit_insn (gen_rtx_SET (VOIDmode, sub,
1412 gen_rtx_AND (mode, source,
1414 emit_insn (gen_rtx_SET (VOIDmode, target,
1415 gen_rtx_NOT (mode, sub)));
1422 /* See if two shifts will do 2 or more insn's worth of work. */
1423 if (clear_sign_bit_copies >= 16 && clear_sign_bit_copies < 24)
1425 HOST_WIDE_INT shift_mask = (((HOST_UINT (0xffffffff))
1426 << (32 - clear_sign_bit_copies))
1427 & HOST_UINT (0xffffffff));
1429 if ((remainder | shift_mask) != HOST_UINT (0xffffffff))
1433 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1434 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1435 new_src, source, subtargets, 1);
1440 rtx targ = subtargets ? NULL_RTX : target;
1441 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1442 targ, source, subtargets, 0);
1448 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1449 rtx shift = GEN_INT (clear_sign_bit_copies);
1451 emit_insn (gen_ashlsi3 (new_src, source, shift));
1452 emit_insn (gen_lshrsi3 (target, new_src, shift));
1458 if (clear_zero_bit_copies >= 16 && clear_zero_bit_copies < 24)
1460 HOST_WIDE_INT shift_mask = (1 << clear_zero_bit_copies) - 1;
1462 if ((remainder | shift_mask) != HOST_UINT (0xffffffff))
1466 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1468 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1469 new_src, source, subtargets, 1);
1474 rtx targ = subtargets ? NULL_RTX : target;
1476 insns = arm_gen_constant (AND, mode, remainder | shift_mask,
1477 targ, source, subtargets, 0);
1483 rtx new_src = subtargets ? gen_reg_rtx (mode) : target;
1484 rtx shift = GEN_INT (clear_zero_bit_copies);
1486 emit_insn (gen_lshrsi3 (new_src, source, shift));
1487 emit_insn (gen_ashlsi3 (target, new_src, shift));
1499 for (i = 0; i < 32; i++)
1500 if (remainder & (1 << i))
1503 if (code == AND || (can_invert && num_bits_set > 16))
1504 remainder = (~remainder) & HOST_UINT (0xffffffff);
1505 else if (code == PLUS && num_bits_set > 16)
1506 remainder = (-remainder) & HOST_UINT (0xffffffff);
1513 /* Now try and find a way of doing the job in either two or three
1515 We start by looking for the largest block of zeros that are aligned on
1516 a 2-bit boundary, we then fill up the temps, wrapping around to the
1517 top of the word when we drop off the bottom.
1518 In the worst case this code should produce no more than four insns. */
1521 int best_consecutive_zeros = 0;
1523 for (i = 0; i < 32; i += 2)
1525 int consecutive_zeros = 0;
1527 if (!(remainder & (3 << i)))
1529 while ((i < 32) && !(remainder & (3 << i)))
1531 consecutive_zeros += 2;
1534 if (consecutive_zeros > best_consecutive_zeros)
1536 best_consecutive_zeros = consecutive_zeros;
1537 best_start = i - consecutive_zeros;
1543 /* So long as it won't require any more insns to do so, it's
1544 desirable to emit a small constant (in bits 0...9) in the last
1545 insn. This way there is more chance that it can be combined with
1546 a later addressing insn to form a pre-indexed load or store
1547 operation. Consider:
1549 *((volatile int *)0xe0000100) = 1;
1550 *((volatile int *)0xe0000110) = 2;
1552 We want this to wind up as:
1556 str rB, [rA, #0x100]
1558 str rB, [rA, #0x110]
1560 rather than having to synthesize both large constants from scratch.
1562 Therefore, we calculate how many insns would be required to emit
1563 the constant starting from `best_start', and also starting from
1564 zero (ie with bit 31 first to be output). If `best_start' doesn't
1565 yield a shorter sequence, we may as well use zero. */
1567 && ((((unsigned HOST_WIDE_INT) 1) << best_start) < remainder)
1568 && (count_insns_for_constant (remainder, 0) <=
1569 count_insns_for_constant (remainder, best_start)))
1572 /* Now start emitting the insns. */
1580 if (remainder & (3 << (i - 2)))
1585 temp1 = remainder & ((0x0ff << end)
1586 | ((i < end) ? (0xff >> (32 - end)) : 0));
1587 remainder &= ~temp1;
1594 emit_insn (gen_rtx_SET (VOIDmode,
1595 new_src = (subtargets
1596 ? gen_reg_rtx (mode)
1599 ? ~temp1 : temp1)));
1600 else if (code == MINUS)
1601 emit_insn (gen_rtx_SET (VOIDmode,
1602 new_src = (subtargets
1603 ? gen_reg_rtx (mode)
1605 gen_rtx (code, mode, GEN_INT (temp1),
1608 emit_insn (gen_rtx_SET (VOIDmode,
1609 new_src = (remainder
1611 ? gen_reg_rtx (mode)
1614 gen_rtx (code, mode, source,
1615 GEN_INT (can_invert ? ~temp1
1627 else if (code == MINUS)
1634 } while (remainder);
1639 /* Canonicalize a comparison so that we are more likely to recognize it.
1640 This can be done for a few constant compares, where we can make the
1641 immediate value easier to load. */
1643 arm_canonicalize_comparison (code, op1)
1647 unsigned HOST_WIDE_INT i = INTVAL (*op1);
1657 if (i != (((HOST_UINT (1)) << (HOST_BITS_PER_WIDE_INT - 1)) - 1)
1658 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
1660 *op1 = GEN_INT (i + 1);
1661 return code == GT ? GE : LT;
1667 if (i != ((HOST_UINT (1)) << (HOST_BITS_PER_WIDE_INT - 1))
1668 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
1670 *op1 = GEN_INT (i - 1);
1671 return code == GE ? GT : LE;
1677 if (i != ~(HOST_UINT (0))
1678 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1))))
1680 *op1 = GEN_INT (i + 1);
1681 return code == GTU ? GEU : LTU;
1688 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1))))
1690 *op1 = GEN_INT (i - 1);
1691 return code == GEU ? GTU : LEU;
1702 /* Decide whether a type should be returned in memory (true)
1703 or in a register (false). This is called by the macro
1704 RETURN_IN_MEMORY. */
1706 arm_return_in_memory (type)
1709 if (!AGGREGATE_TYPE_P (type))
1710 /* All simple types are returned in registers. */
1713 /* For the arm-wince targets we choose to be compitable with Microsoft's
1714 ARM and Thumb compilers, which always return aggregates in memory. */
1717 if (int_size_in_bytes (type) > 4)
1718 /* All structures/unions bigger than one word are returned in memory. */
1721 if (TREE_CODE (type) == RECORD_TYPE)
1725 /* For a struct the APCS says that we only return in a register
1726 if the type is 'integer like' and every addressable element
1727 has an offset of zero. For practical purposes this means
1728 that the structure can have at most one non bit-field element
1729 and that this element must be the first one in the structure. */
1731 /* Find the first field, ignoring non FIELD_DECL things which will
1732 have been created by C++. */
1733 for (field = TYPE_FIELDS (type);
1734 field && TREE_CODE (field) != FIELD_DECL;
1735 field = TREE_CHAIN (field))
1739 return 0; /* An empty structure. Allowed by an extension to ANSI C. */
1741 /* Check that the first field is valid for returning in a register. */
1743 /* ... Floats are not allowed */
1744 if (FLOAT_TYPE_P (TREE_TYPE (field)))
1747 /* ... Aggregates that are not themselves valid for returning in
1748 a register are not allowed. */
1749 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
1752 /* Now check the remaining fields, if any. Only bitfields are allowed,
1753 since they are not addressable. */
1754 for (field = TREE_CHAIN (field);
1756 field = TREE_CHAIN (field))
1758 if (TREE_CODE (field) != FIELD_DECL)
1761 if (!DECL_BIT_FIELD_TYPE (field))
1768 if (TREE_CODE (type) == UNION_TYPE)
1772 /* Unions can be returned in registers if every element is
1773 integral, or can be returned in an integer register. */
1774 for (field = TYPE_FIELDS (type);
1776 field = TREE_CHAIN (field))
1778 if (TREE_CODE (field) != FIELD_DECL)
1781 if (FLOAT_TYPE_P (TREE_TYPE (field)))
1784 if (RETURN_IN_MEMORY (TREE_TYPE (field)))
1790 #endif /* not ARM_WINCE */
1792 /* Return all other types in memory. */
1796 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1797 for a call to a function whose data type is FNTYPE.
1798 For a library call, FNTYPE is NULL. */
1800 arm_init_cumulative_args (pcum, fntype, libname, indirect)
1801 CUMULATIVE_ARGS * pcum;
1803 rtx libname ATTRIBUTE_UNUSED;
1804 int indirect ATTRIBUTE_UNUSED;
1806 /* On the ARM, the offset starts at 0. */
1807 pcum->nregs = ((fntype && aggregate_value_p (TREE_TYPE (fntype))) ? 1 : 0);
1809 pcum->call_cookie = CALL_NORMAL;
1811 if (TARGET_LONG_CALLS)
1812 pcum->call_cookie = CALL_LONG;
1814 /* Check for long call/short call attributes. The attributes
1815 override any command line option. */
1818 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (fntype)))
1819 pcum->call_cookie = CALL_SHORT;
1820 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (fntype)))
1821 pcum->call_cookie = CALL_LONG;
1825 /* Determine where to put an argument to a function.
1826 Value is zero to push the argument on the stack,
1827 or a hard register in which to store the argument.
1829 MODE is the argument's machine mode.
1830 TYPE is the data type of the argument (as a tree).
1831 This is null for libcalls where that information may
1833 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1834 the preceding args and about the function being called.
1835 NAMED is nonzero if this argument is a named parameter
1836 (otherwise it is an extra parameter matching an ellipsis). */
1838 arm_function_arg (pcum, mode, type, named)
1839 CUMULATIVE_ARGS * pcum;
1840 enum machine_mode mode;
1841 tree type ATTRIBUTE_UNUSED;
1844 if (mode == VOIDmode)
1845 /* Compute operand 2 of the call insn. */
1846 return GEN_INT (pcum->call_cookie);
1848 if (!named || pcum->nregs >= NUM_ARG_REGS)
1851 return gen_rtx_REG (mode, pcum->nregs);
1854 /* Encode the current state of the #pragma [no_]long_calls. */
1857 OFF, /* No #pramgma [no_]long_calls is in effect. */
1858 LONG, /* #pragma long_calls is in effect. */
1859 SHORT /* #pragma no_long_calls is in effect. */
1862 static arm_pragma_enum arm_pragma_long_calls = OFF;
1865 arm_pr_long_calls (pfile)
1866 cpp_reader *pfile ATTRIBUTE_UNUSED;
1868 arm_pragma_long_calls = LONG;
1872 arm_pr_no_long_calls (pfile)
1873 cpp_reader *pfile ATTRIBUTE_UNUSED;
1875 arm_pragma_long_calls = SHORT;
1879 arm_pr_long_calls_off (pfile)
1880 cpp_reader *pfile ATTRIBUTE_UNUSED;
1882 arm_pragma_long_calls = OFF;
1886 /* Return nonzero if IDENTIFIER with arguments ARGS is a valid machine
1887 specific attribute for TYPE. The attributes in ATTRIBUTES have
1888 previously been assigned to TYPE. */
1890 arm_valid_type_attribute_p (type, attributes, identifier, args)
1892 tree attributes ATTRIBUTE_UNUSED;
1896 if ( TREE_CODE (type) != FUNCTION_TYPE
1897 && TREE_CODE (type) != METHOD_TYPE
1898 && TREE_CODE (type) != FIELD_DECL
1899 && TREE_CODE (type) != TYPE_DECL)
1902 /* Function calls made to this symbol must be done indirectly, because
1903 it may lie outside of the 26 bit addressing range of a normal function
1905 if (is_attribute_p ("long_call", identifier))
1906 return (args == NULL_TREE);
1908 /* Whereas these functions are always known to reside within the 26 bit
1909 addressing range. */
1910 if (is_attribute_p ("short_call", identifier))
1911 return (args == NULL_TREE);
1913 /* Interrupt Service Routines have special prologue and epilogue requirements. */
1914 if (is_attribute_p ("isr", identifier)
1915 || is_attribute_p ("interrupt", identifier))
1916 return arm_isr_value (args);
1921 /* Return 0 if the attributes for two types are incompatible, 1 if they
1922 are compatible, and 2 if they are nearly compatible (which causes a
1923 warning to be generated). */
1925 arm_comp_type_attributes (type1, type2)
1931 /* Check for mismatch of non-default calling convention. */
1932 if (TREE_CODE (type1) != FUNCTION_TYPE)
1935 /* Check for mismatched call attributes. */
1936 l1 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1)) != NULL;
1937 l2 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2)) != NULL;
1938 s1 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1)) != NULL;
1939 s2 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2)) != NULL;
1941 /* Only bother to check if an attribute is defined. */
1942 if (l1 | l2 | s1 | s2)
1944 /* If one type has an attribute, the other must have the same attribute. */
1945 if ((l1 != l2) || (s1 != s2))
1948 /* Disallow mixed attributes. */
1949 if ((l1 & s2) || (l2 & s1))
1953 /* Check for mismatched ISR attribute. */
1954 l1 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type1)) != NULL;
1956 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1)) != NULL;
1957 l2 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type2)) != NULL;
1959 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2)) != NULL;
1966 /* Encode long_call or short_call attribute by prefixing
1967 symbol name in DECL with a special character FLAG. */
1969 arm_encode_call_attribute (decl, flag)
1973 const char * str = XSTR (XEXP (DECL_RTL (decl), 0), 0);
1974 int len = strlen (str);
1977 if (TREE_CODE (decl) != FUNCTION_DECL)
1980 /* Do not allow weak functions to be treated as short call. */
1981 if (DECL_WEAK (decl) && flag == SHORT_CALL_FLAG_CHAR)
1984 newstr = alloca (len + 2);
1986 strcpy (newstr + 1, str);
1988 newstr = (char *) ggc_alloc_string (newstr, len + 1);
1989 XSTR (XEXP (DECL_RTL (decl), 0), 0) = newstr;
1992 /* Assigns default attributes to newly defined type. This is used to
1993 set short_call/long_call attributes for function types of
1994 functions defined inside corresponding #pragma scopes. */
1996 arm_set_default_type_attributes (type)
1999 /* Add __attribute__ ((long_call)) to all functions, when
2000 inside #pragma long_calls or __attribute__ ((short_call)),
2001 when inside #pragma no_long_calls. */
2002 if (TREE_CODE (type) == FUNCTION_TYPE || TREE_CODE (type) == METHOD_TYPE)
2004 tree type_attr_list, attr_name;
2005 type_attr_list = TYPE_ATTRIBUTES (type);
2007 if (arm_pragma_long_calls == LONG)
2008 attr_name = get_identifier ("long_call");
2009 else if (arm_pragma_long_calls == SHORT)
2010 attr_name = get_identifier ("short_call");
2014 type_attr_list = tree_cons (attr_name, NULL_TREE, type_attr_list);
2015 TYPE_ATTRIBUTES (type) = type_attr_list;
2019 /* Return 1 if the operand is a SYMBOL_REF for a function known to be
2020 defined within the current compilation unit. If this caanot be
2021 determined, then 0 is returned. */
2023 current_file_function_operand (sym_ref)
2026 /* This is a bit of a fib. A function will have a short call flag
2027 applied to its name if it has the short call attribute, or it has
2028 already been defined within the current compilation unit. */
2029 if (ENCODED_SHORT_CALL_ATTR_P (XSTR (sym_ref, 0)))
2032 /* The current function is always defined within the current compilation
2033 unit. if it s a weak defintion however, then this may not be the real
2034 defintion of the function, and so we have to say no. */
2035 if (sym_ref == XEXP (DECL_RTL (current_function_decl), 0)
2036 && !DECL_WEAK (current_function_decl))
2039 /* We cannot make the determination - default to returning 0. */
2043 /* Return non-zero if a 32 bit "long_call" should be generated for
2044 this call. We generate a long_call if the function:
2046 a. has an __attribute__((long call))
2047 or b. is within the scope of a #pragma long_calls
2048 or c. the -mlong-calls command line switch has been specified
2050 However we do not generate a long call if the function:
2052 d. has an __attribute__ ((short_call))
2053 or e. is inside the scope of a #pragma no_long_calls
2054 or f. has an __attribute__ ((section))
2055 or g. is defined within the current compilation unit.
2057 This function will be called by C fragments contained in the machine
2058 description file. CALL_REF and CALL_COOKIE correspond to the matched
2059 rtl operands. CALL_SYMBOL is used to distinguish between
2060 two different callers of the function. It is set to 1 in the
2061 "call_symbol" and "call_symbol_value" patterns and to 0 in the "call"
2062 and "call_value" patterns. This is because of the difference in the
2063 SYM_REFs passed by these patterns. */
2065 arm_is_longcall_p (sym_ref, call_cookie, call_symbol)
2072 if (GET_CODE (sym_ref) != MEM)
2075 sym_ref = XEXP (sym_ref, 0);
2078 if (GET_CODE (sym_ref) != SYMBOL_REF)
2081 if (call_cookie & CALL_SHORT)
2084 if (TARGET_LONG_CALLS && flag_function_sections)
2087 if (current_file_function_operand (sym_ref))
2090 return (call_cookie & CALL_LONG)
2091 || ENCODED_LONG_CALL_ATTR_P (XSTR (sym_ref, 0))
2092 || TARGET_LONG_CALLS;
2095 /* Return non-zero if it is ok to make a tail-call to DECL. */
2097 arm_function_ok_for_sibcall (decl)
2100 int call_type = TARGET_LONG_CALLS ? CALL_LONG : CALL_NORMAL;
2102 /* Never tailcall something for which we have no decl, or if we
2103 are in Thumb mode. */
2104 if (decl == NULL || TARGET_THUMB)
2107 /* Get the calling method. */
2108 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
2109 call_type = CALL_SHORT;
2110 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl))))
2111 call_type = CALL_LONG;
2113 /* Cannot tail-call to long calls, since these are out of range of
2114 a branch instruction. However, if not compiling PIC, we know
2115 we can reach the symbol if it is in this compilation unit. */
2116 if (call_type == CALL_LONG && (flag_pic || !TREE_ASM_WRITTEN (decl)))
2119 /* If we are interworking and the function is not declared static
2120 then we can't tail-call it unless we know that it exists in this
2121 compilation unit (since it might be a Thumb routine). */
2122 if (TARGET_INTERWORK && TREE_PUBLIC (decl) && !TREE_ASM_WRITTEN (decl))
2125 /* Never tailcall from an ISR routine - it needs a special exit sequence. */
2126 if (IS_INTERRUPT (arm_current_func_type ()))
2129 /* Everything else is ok. */
2135 legitimate_pic_operand_p (x)
2140 && (GET_CODE (x) == SYMBOL_REF
2141 || (GET_CODE (x) == CONST
2142 && GET_CODE (XEXP (x, 0)) == PLUS
2143 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)))
2150 legitimize_pic_address (orig, mode, reg)
2152 enum machine_mode mode;
2155 if (GET_CODE (orig) == SYMBOL_REF)
2157 rtx pic_ref, address;
2166 reg = gen_reg_rtx (Pmode);
2171 #ifdef AOF_ASSEMBLER
2172 /* The AOF assembler can generate relocations for these directly, and
2173 understands that the PIC register has to be added into the offset. */
2174 insn = emit_insn (gen_pic_load_addr_based (reg, orig));
2177 address = gen_reg_rtx (Pmode);
2182 emit_insn (gen_pic_load_addr_arm (address, orig));
2184 emit_insn (gen_pic_load_addr_thumb (address, orig));
2186 pic_ref = gen_rtx_MEM (Pmode,
2187 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
2189 RTX_UNCHANGING_P (pic_ref) = 1;
2190 insn = emit_move_insn (reg, pic_ref);
2192 current_function_uses_pic_offset_table = 1;
2193 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2195 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
2199 else if (GET_CODE (orig) == CONST)
2203 if (GET_CODE (XEXP (orig, 0)) == PLUS
2204 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
2212 reg = gen_reg_rtx (Pmode);
2215 if (GET_CODE (XEXP (orig, 0)) == PLUS)
2217 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
2218 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
2219 base == reg ? 0 : reg);
2224 if (GET_CODE (offset) == CONST_INT)
2226 /* The base register doesn't really matter, we only want to
2227 test the index for the appropriate mode. */
2228 ARM_GO_IF_LEGITIMATE_INDEX (mode, 0, offset, win);
2230 if (!no_new_pseudos)
2231 offset = force_reg (Pmode, offset);
2236 if (GET_CODE (offset) == CONST_INT)
2237 return plus_constant (base, INTVAL (offset));
2240 if (GET_MODE_SIZE (mode) > 4
2241 && (GET_MODE_CLASS (mode) == MODE_INT
2242 || TARGET_SOFT_FLOAT))
2244 emit_insn (gen_addsi3 (reg, base, offset));
2248 return gen_rtx_PLUS (Pmode, base, offset);
2250 else if (GET_CODE (orig) == LABEL_REF)
2252 current_function_uses_pic_offset_table = 1;
2256 rtx pic_ref, address = gen_reg_rtx (Pmode);
2259 emit_insn (gen_pic_load_addr_arm (address, orig));
2261 emit_insn (gen_pic_load_addr_thumb (address, orig));
2263 pic_ref = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, address);
2265 emit_move_insn (address, pic_ref);
2273 /* Generate code to load the PIC register. PROLOGUE is true if
2274 called from arm_expand_prologue (in which case we want the
2275 generated insns at the start of the function); false if called
2276 by an exception receiver that needs the PIC register reloaded
2277 (in which case the insns are just dumped at the current location). */
2280 arm_finalize_pic (prologue)
2283 #ifndef AOF_ASSEMBLER
2284 rtx l1, pic_tmp, pic_tmp2, seq, pic_rtx;
2285 rtx global_offset_table;
2287 if (current_function_uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE)
2294 l1 = gen_label_rtx ();
2296 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
2297 /* On the ARM the PC register contains 'dot + 8' at the time of the
2298 addition, on the Thumb it is 'dot + 4'. */
2299 pic_tmp = plus_constant (gen_rtx_LABEL_REF (Pmode, l1), TARGET_ARM ? 8 : 4);
2301 pic_tmp2 = gen_rtx_CONST (VOIDmode,
2302 gen_rtx_PLUS (Pmode, global_offset_table, pc_rtx));
2304 pic_tmp2 = gen_rtx_CONST (VOIDmode, global_offset_table);
2306 pic_rtx = gen_rtx_CONST (Pmode, gen_rtx_MINUS (Pmode, pic_tmp2, pic_tmp));
2310 emit_insn (gen_pic_load_addr_arm (pic_offset_table_rtx, pic_rtx));
2311 emit_insn (gen_pic_add_dot_plus_eight (pic_offset_table_rtx, l1));
2315 emit_insn (gen_pic_load_addr_thumb (pic_offset_table_rtx, pic_rtx));
2316 emit_insn (gen_pic_add_dot_plus_four (pic_offset_table_rtx, l1));
2319 seq = gen_sequence ();
2322 emit_insn_after (seq, get_insns ());
2326 /* Need to emit this whether or not we obey regdecls,
2327 since setjmp/longjmp can cause life info to screw up. */
2328 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
2329 #endif /* AOF_ASSEMBLER */
2332 #define REG_OR_SUBREG_REG(X) \
2333 (GET_CODE (X) == REG \
2334 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
2336 #define REG_OR_SUBREG_RTX(X) \
2337 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
2339 #ifndef COSTS_N_INSNS
2340 #define COSTS_N_INSNS(N) ((N) * 4 - 2)
2344 arm_rtx_costs (x, code, outer)
2347 enum rtx_code outer;
2349 enum machine_mode mode = GET_MODE (x);
2350 enum rtx_code subcode;
2366 return COSTS_N_INSNS (1);
2369 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
2372 unsigned HOST_WIDE_INT i = INTVAL (XEXP (x, 1));
2379 return COSTS_N_INSNS (2) + cycles;
2381 return COSTS_N_INSNS (1) + 16;
2384 return (COSTS_N_INSNS (1)
2385 + 4 * ((GET_CODE (SET_SRC (x)) == MEM)
2386 + GET_CODE (SET_DEST (x)) == MEM));
2391 if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256)
2393 if (thumb_shiftable_const (INTVAL (x)))
2394 return COSTS_N_INSNS (2);
2395 return COSTS_N_INSNS (3);
2397 else if (outer == PLUS
2398 && INTVAL (x) < 256 && INTVAL (x) > -256)
2400 else if (outer == COMPARE
2401 && (unsigned HOST_WIDE_INT) INTVAL (x) < 256)
2403 else if (outer == ASHIFT || outer == ASHIFTRT
2404 || outer == LSHIFTRT)
2406 return COSTS_N_INSNS (2);
2412 return COSTS_N_INSNS (3);
2431 /* XXX another guess. */
2432 /* Memory costs quite a lot for the first word, but subsequent words
2433 load at the equivalent of a single insn each. */
2434 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
2435 + (CONSTANT_POOL_ADDRESS_P (x) ? 4 : 0));
2439 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
2444 /* XXX still guessing. */
2445 switch (GET_MODE (XEXP (x, 0)))
2448 return (1 + (mode == DImode ? 4 : 0)
2449 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
2452 return (4 + (mode == DImode ? 4 : 0)
2453 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
2456 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
2470 fprintf (stderr, "unexpected code for thumb in rtx_costs: %s\n",
2480 /* Memory costs quite a lot for the first word, but subsequent words
2481 load at the equivalent of a single insn each. */
2482 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
2483 + (CONSTANT_POOL_ADDRESS_P (x) ? 4 : 0));
2490 if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG)
2497 case ASHIFT: case LSHIFTRT: case ASHIFTRT:
2499 return (8 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : 8)
2500 + ((GET_CODE (XEXP (x, 0)) == REG
2501 || (GET_CODE (XEXP (x, 0)) == SUBREG
2502 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
2504 return (1 + ((GET_CODE (XEXP (x, 0)) == REG
2505 || (GET_CODE (XEXP (x, 0)) == SUBREG
2506 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG))
2508 + ((GET_CODE (XEXP (x, 1)) == REG
2509 || (GET_CODE (XEXP (x, 1)) == SUBREG
2510 && GET_CODE (SUBREG_REG (XEXP (x, 1))) == REG)
2511 || (GET_CODE (XEXP (x, 1)) == CONST_INT))
2516 return (4 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 8)
2517 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
2518 || (GET_CODE (XEXP (x, 0)) == CONST_INT
2519 && const_ok_for_arm (INTVAL (XEXP (x, 0)))))
2522 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
2523 return (2 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
2524 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
2525 && const_double_rtx_ok_for_fpu (XEXP (x, 1))))
2527 + ((REG_OR_SUBREG_REG (XEXP (x, 0))
2528 || (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE
2529 && const_double_rtx_ok_for_fpu (XEXP (x, 0))))
2532 if (((GET_CODE (XEXP (x, 0)) == CONST_INT
2533 && const_ok_for_arm (INTVAL (XEXP (x, 0)))
2534 && REG_OR_SUBREG_REG (XEXP (x, 1))))
2535 || (((subcode = GET_CODE (XEXP (x, 1))) == ASHIFT
2536 || subcode == ASHIFTRT || subcode == LSHIFTRT
2537 || subcode == ROTATE || subcode == ROTATERT
2539 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
2540 && ((INTVAL (XEXP (XEXP (x, 1), 1)) &
2541 (INTVAL (XEXP (XEXP (x, 1), 1)) - 1)) == 0)))
2542 && REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 0))
2543 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 1))
2544 || GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT)
2545 && REG_OR_SUBREG_REG (XEXP (x, 0))))
2550 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
2551 return (2 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
2552 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
2553 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
2554 && const_double_rtx_ok_for_fpu (XEXP (x, 1))))
2558 case AND: case XOR: case IOR:
2561 /* Normally the frame registers will be spilt into reg+const during
2562 reload, so it is a bad idea to combine them with other instructions,
2563 since then they might not be moved outside of loops. As a compromise
2564 we allow integration with ops that have a constant as their second
2566 if ((REG_OR_SUBREG_REG (XEXP (x, 0))
2567 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))
2568 && GET_CODE (XEXP (x, 1)) != CONST_INT)
2569 || (REG_OR_SUBREG_REG (XEXP (x, 0))
2570 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0)))))
2574 return (4 + extra_cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8)
2575 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
2576 || (GET_CODE (XEXP (x, 1)) == CONST_INT
2577 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
2580 if (REG_OR_SUBREG_REG (XEXP (x, 0)))
2581 return (1 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : extra_cost)
2582 + ((REG_OR_SUBREG_REG (XEXP (x, 1))
2583 || (GET_CODE (XEXP (x, 1)) == CONST_INT
2584 && const_ok_for_op (INTVAL (XEXP (x, 1)), code)))
2587 else if (REG_OR_SUBREG_REG (XEXP (x, 1)))
2588 return (1 + extra_cost
2589 + ((((subcode = GET_CODE (XEXP (x, 0))) == ASHIFT
2590 || subcode == LSHIFTRT || subcode == ASHIFTRT
2591 || subcode == ROTATE || subcode == ROTATERT
2593 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2594 && ((INTVAL (XEXP (XEXP (x, 0), 1)) &
2595 (INTVAL (XEXP (XEXP (x, 0), 1)) - 1)) == 0)))
2596 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 0)))
2597 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 1)))
2598 || GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))
2604 /* There is no point basing this on the tuning, since it is always the
2605 fast variant if it exists at all. */
2606 if (arm_fast_multiply && mode == DImode
2607 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1)))
2608 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
2609 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND))
2612 if (GET_MODE_CLASS (mode) == MODE_FLOAT
2616 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
2618 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1))
2619 & HOST_UINT (0xffffffff));
2620 int add_cost = const_ok_for_arm (i) ? 4 : 8;
2623 /* Tune as appropriate. */
2624 int booth_unit_size = ((tune_flags & FL_FAST_MULT) ? 8 : 2);
2626 for (j = 0; i && j < 32; j += booth_unit_size)
2628 i >>= booth_unit_size;
2635 return (((tune_flags & FL_FAST_MULT) ? 8 : 30)
2636 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4)
2637 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4));
2640 if (arm_fast_multiply && mode == SImode
2641 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
2642 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
2643 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0))
2644 == GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)))
2645 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ZERO_EXTEND
2646 || GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SIGN_EXTEND))
2651 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
2652 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 6);
2656 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
2658 return 1 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4);
2661 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
2669 return 4 + (mode == DImode ? 4 : 0);
2672 if (GET_MODE (XEXP (x, 0)) == QImode)
2673 return (4 + (mode == DImode ? 4 : 0)
2674 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
2677 switch (GET_MODE (XEXP (x, 0)))
2680 return (1 + (mode == DImode ? 4 : 0)
2681 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
2684 return (4 + (mode == DImode ? 4 : 0)
2685 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
2688 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0));
2696 if (const_ok_for_arm (INTVAL (x)))
2697 return outer == SET ? 2 : -1;
2698 else if (outer == AND
2699 && const_ok_for_arm (~INTVAL (x)))
2701 else if ((outer == COMPARE
2702 || outer == PLUS || outer == MINUS)
2703 && const_ok_for_arm (-INTVAL (x)))
2714 if (const_double_rtx_ok_for_fpu (x))
2715 return outer == SET ? 2 : -1;
2716 else if ((outer == COMPARE || outer == PLUS)
2717 && neg_const_double_rtx_ok_for_fpu (x))
2727 arm_adjust_cost (insn, link, dep, cost)
2735 /* Some true dependencies can have a higher cost depending
2736 on precisely how certain input operands are used. */
2738 && REG_NOTE_KIND (link) == 0
2739 && recog_memoized (insn) < 0
2740 && recog_memoized (dep) < 0)
2742 int shift_opnum = get_attr_shift (insn);
2743 enum attr_type attr_type = get_attr_type (dep);
2745 /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted
2746 operand for INSN. If we have a shifted input operand and the
2747 instruction we depend on is another ALU instruction, then we may
2748 have to account for an additional stall. */
2749 if (shift_opnum != 0 && attr_type == TYPE_NORMAL)
2751 rtx shifted_operand;
2754 /* Get the shifted operand. */
2755 extract_insn (insn);
2756 shifted_operand = recog_data.operand[shift_opnum];
2758 /* Iterate over all the operands in DEP. If we write an operand
2759 that overlaps with SHIFTED_OPERAND, then we have increase the
2760 cost of this dependency. */
2762 preprocess_constraints ();
2763 for (opno = 0; opno < recog_data.n_operands; opno++)
2765 /* We can ignore strict inputs. */
2766 if (recog_data.operand_type[opno] == OP_IN)
2769 if (reg_overlap_mentioned_p (recog_data.operand[opno],
2776 /* XXX This is not strictly true for the FPA. */
2777 if (REG_NOTE_KIND (link) == REG_DEP_ANTI
2778 || REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
2781 /* Call insns don't incur a stall, even if they follow a load. */
2782 if (REG_NOTE_KIND (link) == 0
2783 && GET_CODE (insn) == CALL_INSN)
2786 if ((i_pat = single_set (insn)) != NULL
2787 && GET_CODE (SET_SRC (i_pat)) == MEM
2788 && (d_pat = single_set (dep)) != NULL
2789 && GET_CODE (SET_DEST (d_pat)) == MEM)
2791 /* This is a load after a store, there is no conflict if the load reads
2792 from a cached area. Assume that loads from the stack, and from the
2793 constant pool are cached, and that others will miss. This is a
2796 if (CONSTANT_POOL_ADDRESS_P (XEXP (SET_SRC (i_pat), 0))
2797 || reg_mentioned_p (stack_pointer_rtx, XEXP (SET_SRC (i_pat), 0))
2798 || reg_mentioned_p (frame_pointer_rtx, XEXP (SET_SRC (i_pat), 0))
2799 || reg_mentioned_p (hard_frame_pointer_rtx,
2800 XEXP (SET_SRC (i_pat), 0)))
2807 /* This code has been fixed for cross compilation. */
2809 static int fpa_consts_inited = 0;
2811 static const char * strings_fpa[8] =
2814 "4", "5", "0.5", "10"
2817 static REAL_VALUE_TYPE values_fpa[8];
2825 for (i = 0; i < 8; i++)
2827 r = REAL_VALUE_ATOF (strings_fpa[i], DFmode);
2831 fpa_consts_inited = 1;
2834 /* Return TRUE if rtx X is a valid immediate FPU constant. */
2837 const_double_rtx_ok_for_fpu (x)
2843 if (!fpa_consts_inited)
2846 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
2847 if (REAL_VALUE_MINUS_ZERO (r))
2850 for (i = 0; i < 8; i++)
2851 if (REAL_VALUES_EQUAL (r, values_fpa[i]))
2857 /* Return TRUE if rtx X is a valid immediate FPU constant. */
2860 neg_const_double_rtx_ok_for_fpu (x)
2866 if (!fpa_consts_inited)
2869 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
2870 r = REAL_VALUE_NEGATE (r);
2871 if (REAL_VALUE_MINUS_ZERO (r))
2874 for (i = 0; i < 8; i++)
2875 if (REAL_VALUES_EQUAL (r, values_fpa[i]))
2881 /* Predicates for `match_operand' and `match_operator'. */
2883 /* s_register_operand is the same as register_operand, but it doesn't accept
2886 This function exists because at the time it was put in it led to better
2887 code. SUBREG(MEM) always needs a reload in the places where
2888 s_register_operand is used, and this seemed to lead to excessive
2892 s_register_operand (op, mode)
2894 enum machine_mode mode;
2896 if (GET_MODE (op) != mode && mode != VOIDmode)
2899 if (GET_CODE (op) == SUBREG)
2900 op = SUBREG_REG (op);
2902 /* We don't consider registers whose class is NO_REGS
2903 to be a register operand. */
2904 /* XXX might have to check for lo regs only for thumb ??? */
2905 return (GET_CODE (op) == REG
2906 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
2907 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
2910 /* A hard register operand (even before reload. */
2912 arm_hard_register_operand (op, mode)
2914 enum machine_mode mode;
2916 if (GET_MODE (op) != mode && mode != VOIDmode)
2919 return (GET_CODE (op) == REG
2920 && REGNO (op) < FIRST_PSEUDO_REGISTER);
2923 /* Only accept reg, subreg(reg), const_int. */
2926 reg_or_int_operand (op, mode)
2928 enum machine_mode mode;
2930 if (GET_CODE (op) == CONST_INT)
2933 if (GET_MODE (op) != mode && mode != VOIDmode)
2936 if (GET_CODE (op) == SUBREG)
2937 op = SUBREG_REG (op);
2939 /* We don't consider registers whose class is NO_REGS
2940 to be a register operand. */
2941 return (GET_CODE (op) == REG
2942 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
2943 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
2946 /* Return 1 if OP is an item in memory, given that we are in reload. */
2949 arm_reload_memory_operand (op, mode)
2951 enum machine_mode mode ATTRIBUTE_UNUSED;
2953 int regno = true_regnum (op);
2955 return (!CONSTANT_P (op)
2957 || (GET_CODE (op) == REG
2958 && REGNO (op) >= FIRST_PSEUDO_REGISTER)));
2961 /* Return 1 if OP is a valid memory address, but not valid for a signed byte
2962 memory access (architecture V4).
2963 MODE is QImode if called when computing contraints, or VOIDmode when
2964 emitting patterns. In this latter case we cannot use memory_operand()
2965 because it will fail on badly formed MEMs, which is precisly what we are
2968 bad_signed_byte_operand (op, mode)
2970 enum machine_mode mode ATTRIBUTE_UNUSED;
2973 if ((mode == QImode && !memory_operand (op, mode)) || GET_CODE (op) != MEM)
2976 if (GET_CODE (op) != MEM)
2981 /* A sum of anything more complex than reg + reg or reg + const is bad. */
2982 if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS)
2983 && (!s_register_operand (XEXP (op, 0), VOIDmode)
2984 || (!s_register_operand (XEXP (op, 1), VOIDmode)
2985 && GET_CODE (XEXP (op, 1)) != CONST_INT)))
2988 /* Big constants are also bad. */
2989 if (GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT
2990 && (INTVAL (XEXP (op, 1)) > 0xff
2991 || -INTVAL (XEXP (op, 1)) > 0xff))
2994 /* Everything else is good, or can will automatically be made so. */
2998 /* Return TRUE for valid operands for the rhs of an ARM instruction. */
3001 arm_rhs_operand (op, mode)
3003 enum machine_mode mode;
3005 return (s_register_operand (op, mode)
3006 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op))));
3009 /* Return TRUE for valid operands for the rhs of an ARM instruction, or a load.
3013 arm_rhsm_operand (op, mode)
3015 enum machine_mode mode;
3017 return (s_register_operand (op, mode)
3018 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op)))
3019 || memory_operand (op, mode));
3022 /* Return TRUE for valid operands for the rhs of an ARM instruction, or if a
3023 constant that is valid when negated. */
3026 arm_add_operand (op, mode)
3028 enum machine_mode mode;
3031 return thumb_cmp_operand (op, mode);
3033 return (s_register_operand (op, mode)
3034 || (GET_CODE (op) == CONST_INT
3035 && (const_ok_for_arm (INTVAL (op))
3036 || const_ok_for_arm (-INTVAL (op)))));
3040 arm_not_operand (op, mode)
3042 enum machine_mode mode;
3044 return (s_register_operand (op, mode)
3045 || (GET_CODE (op) == CONST_INT
3046 && (const_ok_for_arm (INTVAL (op))
3047 || const_ok_for_arm (~INTVAL (op)))));
3050 /* Return TRUE if the operand is a memory reference which contains an
3051 offsettable address. */
3053 offsettable_memory_operand (op, mode)
3055 enum machine_mode mode;
3057 if (mode == VOIDmode)
3058 mode = GET_MODE (op);
3060 return (mode == GET_MODE (op)
3061 && GET_CODE (op) == MEM
3062 && offsettable_address_p (reload_completed | reload_in_progress,
3063 mode, XEXP (op, 0)));
3066 /* Return TRUE if the operand is a memory reference which is, or can be
3067 made word aligned by adjusting the offset. */
3069 alignable_memory_operand (op, mode)
3071 enum machine_mode mode;
3075 if (mode == VOIDmode)
3076 mode = GET_MODE (op);
3078 if (mode != GET_MODE (op) || GET_CODE (op) != MEM)
3083 return ((GET_CODE (reg = op) == REG
3084 || (GET_CODE (op) == SUBREG
3085 && GET_CODE (reg = SUBREG_REG (op)) == REG)
3086 || (GET_CODE (op) == PLUS
3087 && GET_CODE (XEXP (op, 1)) == CONST_INT
3088 && (GET_CODE (reg = XEXP (op, 0)) == REG
3089 || (GET_CODE (XEXP (op, 0)) == SUBREG
3090 && GET_CODE (reg = SUBREG_REG (XEXP (op, 0))) == REG))))
3091 && REGNO_POINTER_ALIGN (REGNO (reg)) >= 32);
3094 /* Similar to s_register_operand, but does not allow hard integer
3097 f_register_operand (op, mode)
3099 enum machine_mode mode;
3101 if (GET_MODE (op) != mode && mode != VOIDmode)
3104 if (GET_CODE (op) == SUBREG)
3105 op = SUBREG_REG (op);
3107 /* We don't consider registers whose class is NO_REGS
3108 to be a register operand. */
3109 return (GET_CODE (op) == REG
3110 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
3111 || REGNO_REG_CLASS (REGNO (op)) == FPU_REGS));
3114 /* Return TRUE for valid operands for the rhs of an FPU instruction. */
3117 fpu_rhs_operand (op, mode)
3119 enum machine_mode mode;
3121 if (s_register_operand (op, mode))
3124 if (GET_MODE (op) != mode && mode != VOIDmode)
3127 if (GET_CODE (op) == CONST_DOUBLE)
3128 return const_double_rtx_ok_for_fpu (op);
3134 fpu_add_operand (op, mode)
3136 enum machine_mode mode;
3138 if (s_register_operand (op, mode))
3141 if (GET_MODE (op) != mode && mode != VOIDmode)
3144 if (GET_CODE (op) == CONST_DOUBLE)
3145 return (const_double_rtx_ok_for_fpu (op)
3146 || neg_const_double_rtx_ok_for_fpu (op));
3151 /* Return nonzero if OP is a constant power of two. */
3154 power_of_two_operand (op, mode)
3156 enum machine_mode mode ATTRIBUTE_UNUSED;
3158 if (GET_CODE (op) == CONST_INT)
3160 HOST_WIDE_INT value = INTVAL (op);
3161 return value != 0 && (value & (value - 1)) == 0;
3166 /* Return TRUE for a valid operand of a DImode operation.
3167 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
3168 Note that this disallows MEM(REG+REG), but allows
3169 MEM(PRE/POST_INC/DEC(REG)). */
3172 di_operand (op, mode)
3174 enum machine_mode mode;
3176 if (s_register_operand (op, mode))
3179 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && GET_MODE (op) != DImode)
3182 if (GET_CODE (op) == SUBREG)
3183 op = SUBREG_REG (op);
3185 switch (GET_CODE (op))
3192 return memory_address_p (DImode, XEXP (op, 0));
3199 /* Like di_operand, but don't accept constants. */
3201 nonimmediate_di_operand (op, mode)
3203 enum machine_mode mode;
3205 if (s_register_operand (op, mode))
3208 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && GET_MODE (op) != DImode)
3211 if (GET_CODE (op) == SUBREG)
3212 op = SUBREG_REG (op);
3214 if (GET_CODE (op) == MEM)
3215 return memory_address_p (DImode, XEXP (op, 0));
3220 /* Return TRUE for a valid operand of a DFmode operation when -msoft-float.
3221 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
3222 Note that this disallows MEM(REG+REG), but allows
3223 MEM(PRE/POST_INC/DEC(REG)). */
3226 soft_df_operand (op, mode)
3228 enum machine_mode mode;
3230 if (s_register_operand (op, mode))
3233 if (mode != VOIDmode && GET_MODE (op) != mode)
3236 if (GET_CODE (op) == SUBREG && CONSTANT_P (SUBREG_REG (op)))
3239 if (GET_CODE (op) == SUBREG)
3240 op = SUBREG_REG (op);
3242 switch (GET_CODE (op))
3248 return memory_address_p (DFmode, XEXP (op, 0));
3255 /* Like soft_df_operand, but don't accept constants. */
3257 nonimmediate_soft_df_operand (op, mode)
3259 enum machine_mode mode;
3261 if (s_register_operand (op, mode))
3264 if (mode != VOIDmode && GET_MODE (op) != mode)
3267 if (GET_CODE (op) == SUBREG)
3268 op = SUBREG_REG (op);
3270 if (GET_CODE (op) == MEM)
3271 return memory_address_p (DFmode, XEXP (op, 0));
3275 /* Return TRUE for valid index operands. */
3277 index_operand (op, mode)
3279 enum machine_mode mode;
3281 return (s_register_operand (op, mode)
3282 || (immediate_operand (op, mode)
3283 && (GET_CODE (op) != CONST_INT
3284 || (INTVAL (op) < 4096 && INTVAL (op) > -4096))));
3287 /* Return TRUE for valid shifts by a constant. This also accepts any
3288 power of two on the (somewhat overly relaxed) assumption that the
3289 shift operator in this case was a mult. */
3292 const_shift_operand (op, mode)
3294 enum machine_mode mode;
3296 return (power_of_two_operand (op, mode)
3297 || (immediate_operand (op, mode)
3298 && (GET_CODE (op) != CONST_INT
3299 || (INTVAL (op) < 32 && INTVAL (op) > 0))));
3302 /* Return TRUE for arithmetic operators which can be combined with a multiply
3306 shiftable_operator (x, mode)
3308 enum machine_mode mode;
3310 if (GET_MODE (x) != mode)
3314 enum rtx_code code = GET_CODE (x);
3316 return (code == PLUS || code == MINUS
3317 || code == IOR || code == XOR || code == AND);
3321 /* Return TRUE for binary logical operators. */
3324 logical_binary_operator (x, mode)
3326 enum machine_mode mode;
3328 if (GET_MODE (x) != mode)
3332 enum rtx_code code = GET_CODE (x);
3334 return (code == IOR || code == XOR || code == AND);
3338 /* Return TRUE for shift operators. */
3341 shift_operator (x, mode)
3343 enum machine_mode mode;
3345 if (GET_MODE (x) != mode)
3349 enum rtx_code code = GET_CODE (x);
3352 return power_of_two_operand (XEXP (x, 1), mode);
3354 return (code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT
3355 || code == ROTATERT);
3359 /* Return TRUE if x is EQ or NE. */
3361 equality_operator (x, mode)
3363 enum machine_mode mode ATTRIBUTE_UNUSED;
3365 return GET_CODE (x) == EQ || GET_CODE (x) == NE;
3368 /* Return TRUE if x is a comparison operator other than LTGT or UNEQ. */
3370 arm_comparison_operator (x, mode)
3372 enum machine_mode mode;
3374 return (comparison_operator (x, mode)
3375 && GET_CODE (x) != LTGT
3376 && GET_CODE (x) != UNEQ);
3379 /* Return TRUE for SMIN SMAX UMIN UMAX operators. */
3381 minmax_operator (x, mode)
3383 enum machine_mode mode;
3385 enum rtx_code code = GET_CODE (x);
3387 if (GET_MODE (x) != mode)
3390 return code == SMIN || code == SMAX || code == UMIN || code == UMAX;
3393 /* Return TRUE if this is the condition code register, if we aren't given
3394 a mode, accept any class CCmode register. */
3396 cc_register (x, mode)
3398 enum machine_mode mode;
3400 if (mode == VOIDmode)
3402 mode = GET_MODE (x);
3404 if (GET_MODE_CLASS (mode) != MODE_CC)
3408 if ( GET_MODE (x) == mode
3409 && GET_CODE (x) == REG
3410 && REGNO (x) == CC_REGNUM)
3416 /* Return TRUE if this is the condition code register, if we aren't given
3417 a mode, accept any class CCmode register which indicates a dominance
3420 dominant_cc_register (x, mode)
3422 enum machine_mode mode;
3424 if (mode == VOIDmode)
3426 mode = GET_MODE (x);
3428 if (GET_MODE_CLASS (mode) != MODE_CC)
3432 if ( mode != CC_DNEmode && mode != CC_DEQmode
3433 && mode != CC_DLEmode && mode != CC_DLTmode
3434 && mode != CC_DGEmode && mode != CC_DGTmode
3435 && mode != CC_DLEUmode && mode != CC_DLTUmode
3436 && mode != CC_DGEUmode && mode != CC_DGTUmode)
3439 return cc_register (x, mode);
3442 /* Return TRUE if X references a SYMBOL_REF. */
3444 symbol_mentioned_p (x)
3447 register const char * fmt;
3450 if (GET_CODE (x) == SYMBOL_REF)
3453 fmt = GET_RTX_FORMAT (GET_CODE (x));
3455 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
3461 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3462 if (symbol_mentioned_p (XVECEXP (x, i, j)))
3465 else if (fmt[i] == 'e' && symbol_mentioned_p (XEXP (x, i)))
3472 /* Return TRUE if X references a LABEL_REF. */
3474 label_mentioned_p (x)
3477 register const char * fmt;
3480 if (GET_CODE (x) == LABEL_REF)
3483 fmt = GET_RTX_FORMAT (GET_CODE (x));
3484 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
3490 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3491 if (label_mentioned_p (XVECEXP (x, i, j)))
3494 else if (fmt[i] == 'e' && label_mentioned_p (XEXP (x, i)))
3505 enum rtx_code code = GET_CODE (x);
3509 else if (code == SMIN)
3511 else if (code == UMIN)
3513 else if (code == UMAX)
3519 /* Return 1 if memory locations are adjacent. */
3521 adjacent_mem_locations (a, b)
3524 int val0 = 0, val1 = 0;
3527 if ((GET_CODE (XEXP (a, 0)) == REG
3528 || (GET_CODE (XEXP (a, 0)) == PLUS
3529 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
3530 && (GET_CODE (XEXP (b, 0)) == REG
3531 || (GET_CODE (XEXP (b, 0)) == PLUS
3532 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
3534 if (GET_CODE (XEXP (a, 0)) == PLUS)
3536 reg0 = REGNO (XEXP (XEXP (a, 0), 0));
3537 val0 = INTVAL (XEXP (XEXP (a, 0), 1));
3540 reg0 = REGNO (XEXP (a, 0));
3541 if (GET_CODE (XEXP (b, 0)) == PLUS)
3543 reg1 = REGNO (XEXP (XEXP (b, 0), 0));
3544 val1 = INTVAL (XEXP (XEXP (b, 0), 1));
3547 reg1 = REGNO (XEXP (b, 0));
3548 return (reg0 == reg1) && ((val1 - val0) == 4 || (val0 - val1) == 4);
3553 /* Return 1 if OP is a load multiple operation. It is known to be
3554 parallel and the first section will be tested. */
3556 load_multiple_operation (op, mode)
3558 enum machine_mode mode ATTRIBUTE_UNUSED;
3560 HOST_WIDE_INT count = XVECLEN (op, 0);
3563 HOST_WIDE_INT i = 1, base = 0;
3567 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
3570 /* Check to see if this might be a write-back. */
3571 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
3576 /* Now check it more carefully. */
3577 if (GET_CODE (SET_DEST (elt)) != REG
3578 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
3579 || REGNO (XEXP (SET_SRC (elt), 0)) != REGNO (SET_DEST (elt))
3580 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
3581 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4)
3585 /* Perform a quick check so we don't blow up below. */
3587 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
3588 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != REG
3589 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != MEM)
3592 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, i - 1)));
3593 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, i - 1)), 0);
3595 for (; i < count; i++)
3597 elt = XVECEXP (op, 0, i);
3599 if (GET_CODE (elt) != SET
3600 || GET_CODE (SET_DEST (elt)) != REG
3601 || GET_MODE (SET_DEST (elt)) != SImode
3602 || REGNO (SET_DEST (elt)) != (unsigned int)(dest_regno + i - base)
3603 || GET_CODE (SET_SRC (elt)) != MEM
3604 || GET_MODE (SET_SRC (elt)) != SImode
3605 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
3606 || !rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
3607 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
3608 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != (i - base) * 4)
3615 /* Return 1 if OP is a store multiple operation. It is known to be
3616 parallel and the first section will be tested. */
3618 store_multiple_operation (op, mode)
3620 enum machine_mode mode ATTRIBUTE_UNUSED;
3622 HOST_WIDE_INT count = XVECLEN (op, 0);
3625 HOST_WIDE_INT i = 1, base = 0;
3629 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
3632 /* Check to see if this might be a write-back. */
3633 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
3638 /* Now check it more carefully. */
3639 if (GET_CODE (SET_DEST (elt)) != REG
3640 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
3641 || REGNO (XEXP (SET_SRC (elt), 0)) != REGNO (SET_DEST (elt))
3642 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
3643 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4)
3647 /* Perform a quick check so we don't blow up below. */
3649 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
3650 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != MEM
3651 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != REG)
3654 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, i - 1)));
3655 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, i - 1)), 0);
3657 for (; i < count; i++)
3659 elt = XVECEXP (op, 0, i);
3661 if (GET_CODE (elt) != SET
3662 || GET_CODE (SET_SRC (elt)) != REG
3663 || GET_MODE (SET_SRC (elt)) != SImode
3664 || REGNO (SET_SRC (elt)) != (unsigned int)(src_regno + i - base)
3665 || GET_CODE (SET_DEST (elt)) != MEM
3666 || GET_MODE (SET_DEST (elt)) != SImode
3667 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
3668 || !rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
3669 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
3670 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != (i - base) * 4)
3678 load_multiple_sequence (operands, nops, regs, base, load_offset)
3683 HOST_WIDE_INT * load_offset;
3685 int unsorted_regs[4];
3686 HOST_WIDE_INT unsorted_offsets[4];
3691 /* Can only handle 2, 3, or 4 insns at present, though could be easily
3692 extended if required. */
3693 if (nops < 2 || nops > 4)
3696 /* Loop over the operands and check that the memory references are
3697 suitable (ie immediate offsets from the same base register). At
3698 the same time, extract the target register, and the memory
3700 for (i = 0; i < nops; i++)
3705 /* Convert a subreg of a mem into the mem itself. */
3706 if (GET_CODE (operands[nops + i]) == SUBREG)
3707 operands[nops + i] = alter_subreg (operands[nops + i]);
3709 if (GET_CODE (operands[nops + i]) != MEM)
3712 /* Don't reorder volatile memory references; it doesn't seem worth
3713 looking for the case where the order is ok anyway. */
3714 if (MEM_VOLATILE_P (operands[nops + i]))
3717 offset = const0_rtx;
3719 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
3720 || (GET_CODE (reg) == SUBREG
3721 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
3722 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
3723 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
3725 || (GET_CODE (reg) == SUBREG
3726 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
3727 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
3732 base_reg = REGNO (reg);
3733 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
3734 ? REGNO (operands[i])
3735 : REGNO (SUBREG_REG (operands[i])));
3740 if (base_reg != (int) REGNO (reg))
3741 /* Not addressed from the same base register. */
3744 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
3745 ? REGNO (operands[i])
3746 : REGNO (SUBREG_REG (operands[i])));
3747 if (unsorted_regs[i] < unsorted_regs[order[0]])
3751 /* If it isn't an integer register, or if it overwrites the
3752 base register but isn't the last insn in the list, then
3753 we can't do this. */
3754 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14
3755 || (i != nops - 1 && unsorted_regs[i] == base_reg))
3758 unsorted_offsets[i] = INTVAL (offset);
3761 /* Not a suitable memory address. */
3765 /* All the useful information has now been extracted from the
3766 operands into unsorted_regs and unsorted_offsets; additionally,
3767 order[0] has been set to the lowest numbered register in the
3768 list. Sort the registers into order, and check that the memory
3769 offsets are ascending and adjacent. */
3771 for (i = 1; i < nops; i++)
3775 order[i] = order[i - 1];
3776 for (j = 0; j < nops; j++)
3777 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
3778 && (order[i] == order[i - 1]
3779 || unsorted_regs[j] < unsorted_regs[order[i]]))
3782 /* Have we found a suitable register? if not, one must be used more
3784 if (order[i] == order[i - 1])
3787 /* Is the memory address adjacent and ascending? */
3788 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
3796 for (i = 0; i < nops; i++)
3797 regs[i] = unsorted_regs[order[i]];
3799 *load_offset = unsorted_offsets[order[0]];
3802 if (unsorted_offsets[order[0]] == 0)
3803 return 1; /* ldmia */
3805 if (unsorted_offsets[order[0]] == 4)
3806 return 2; /* ldmib */
3808 if (unsorted_offsets[order[nops - 1]] == 0)
3809 return 3; /* ldmda */
3811 if (unsorted_offsets[order[nops - 1]] == -4)
3812 return 4; /* ldmdb */
3814 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
3815 if the offset isn't small enough. The reason 2 ldrs are faster
3816 is because these ARMs are able to do more than one cache access
3817 in a single cycle. The ARM9 and StrongARM have Harvard caches,
3818 whilst the ARM8 has a double bandwidth cache. This means that
3819 these cores can do both an instruction fetch and a data fetch in
3820 a single cycle, so the trick of calculating the address into a
3821 scratch register (one of the result regs) and then doing a load
3822 multiple actually becomes slower (and no smaller in code size).
3823 That is the transformation
3825 ldr rd1, [rbase + offset]
3826 ldr rd2, [rbase + offset + 4]
3830 add rd1, rbase, offset
3831 ldmia rd1, {rd1, rd2}
3833 produces worse code -- '3 cycles + any stalls on rd2' instead of
3834 '2 cycles + any stalls on rd2'. On ARMs with only one cache
3835 access per cycle, the first sequence could never complete in less
3836 than 6 cycles, whereas the ldm sequence would only take 5 and
3837 would make better use of sequential accesses if not hitting the
3840 We cheat here and test 'arm_ld_sched' which we currently know to
3841 only be true for the ARM8, ARM9 and StrongARM. If this ever
3842 changes, then the test below needs to be reworked. */
3843 if (nops == 2 && arm_ld_sched)
3846 /* Can't do it without setting up the offset, only do this if it takes
3847 no more than one insn. */
3848 return (const_ok_for_arm (unsorted_offsets[order[0]])
3849 || const_ok_for_arm (-unsorted_offsets[order[0]])) ? 5 : 0;
3853 emit_ldm_seq (operands, nops)
3859 HOST_WIDE_INT offset;
3863 switch (load_multiple_sequence (operands, nops, regs, &base_reg, &offset))
3866 strcpy (buf, "ldm%?ia\t");
3870 strcpy (buf, "ldm%?ib\t");
3874 strcpy (buf, "ldm%?da\t");
3878 strcpy (buf, "ldm%?db\t");
3883 sprintf (buf, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
3884 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
3887 sprintf (buf, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX,
3888 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg],
3890 output_asm_insn (buf, operands);
3892 strcpy (buf, "ldm%?ia\t");
3899 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
3900 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
3902 for (i = 1; i < nops; i++)
3903 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
3904 reg_names[regs[i]]);
3906 strcat (buf, "}\t%@ phole ldm");
3908 output_asm_insn (buf, operands);
3913 store_multiple_sequence (operands, nops, regs, base, load_offset)
3918 HOST_WIDE_INT * load_offset;
3920 int unsorted_regs[4];
3921 HOST_WIDE_INT unsorted_offsets[4];
3926 /* Can only handle 2, 3, or 4 insns at present, though could be easily
3927 extended if required. */
3928 if (nops < 2 || nops > 4)
3931 /* Loop over the operands and check that the memory references are
3932 suitable (ie immediate offsets from the same base register). At
3933 the same time, extract the target register, and the memory
3935 for (i = 0; i < nops; i++)
3940 /* Convert a subreg of a mem into the mem itself. */
3941 if (GET_CODE (operands[nops + i]) == SUBREG)
3942 operands[nops + i] = alter_subreg (operands[nops + i]);
3944 if (GET_CODE (operands[nops + i]) != MEM)
3947 /* Don't reorder volatile memory references; it doesn't seem worth
3948 looking for the case where the order is ok anyway. */
3949 if (MEM_VOLATILE_P (operands[nops + i]))
3952 offset = const0_rtx;
3954 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG
3955 || (GET_CODE (reg) == SUBREG
3956 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
3957 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
3958 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0))
3960 || (GET_CODE (reg) == SUBREG
3961 && GET_CODE (reg = SUBREG_REG (reg)) == REG))
3962 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1))
3967 base_reg = REGNO (reg);
3968 unsorted_regs[0] = (GET_CODE (operands[i]) == REG
3969 ? REGNO (operands[i])
3970 : REGNO (SUBREG_REG (operands[i])));
3975 if (base_reg != (int) REGNO (reg))
3976 /* Not addressed from the same base register. */
3979 unsorted_regs[i] = (GET_CODE (operands[i]) == REG
3980 ? REGNO (operands[i])
3981 : REGNO (SUBREG_REG (operands[i])));
3982 if (unsorted_regs[i] < unsorted_regs[order[0]])
3986 /* If it isn't an integer register, then we can't do this. */
3987 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14)
3990 unsorted_offsets[i] = INTVAL (offset);
3993 /* Not a suitable memory address. */
3997 /* All the useful information has now been extracted from the
3998 operands into unsorted_regs and unsorted_offsets; additionally,
3999 order[0] has been set to the lowest numbered register in the
4000 list. Sort the registers into order, and check that the memory
4001 offsets are ascending and adjacent. */
4003 for (i = 1; i < nops; i++)
4007 order[i] = order[i - 1];
4008 for (j = 0; j < nops; j++)
4009 if (unsorted_regs[j] > unsorted_regs[order[i - 1]]
4010 && (order[i] == order[i - 1]
4011 || unsorted_regs[j] < unsorted_regs[order[i]]))
4014 /* Have we found a suitable register? if not, one must be used more
4016 if (order[i] == order[i - 1])
4019 /* Is the memory address adjacent and ascending? */
4020 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4)
4028 for (i = 0; i < nops; i++)
4029 regs[i] = unsorted_regs[order[i]];
4031 *load_offset = unsorted_offsets[order[0]];
4034 if (unsorted_offsets[order[0]] == 0)
4035 return 1; /* stmia */
4037 if (unsorted_offsets[order[0]] == 4)
4038 return 2; /* stmib */
4040 if (unsorted_offsets[order[nops - 1]] == 0)
4041 return 3; /* stmda */
4043 if (unsorted_offsets[order[nops - 1]] == -4)
4044 return 4; /* stmdb */
4050 emit_stm_seq (operands, nops)
4056 HOST_WIDE_INT offset;
4060 switch (store_multiple_sequence (operands, nops, regs, &base_reg, &offset))
4063 strcpy (buf, "stm%?ia\t");
4067 strcpy (buf, "stm%?ib\t");
4071 strcpy (buf, "stm%?da\t");
4075 strcpy (buf, "stm%?db\t");
4082 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX,
4083 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]);
4085 for (i = 1; i < nops; i++)
4086 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX,
4087 reg_names[regs[i]]);
4089 strcat (buf, "}\t%@ phole stm");
4091 output_asm_insn (buf, operands);
4096 multi_register_push (op, mode)
4098 enum machine_mode mode ATTRIBUTE_UNUSED;
4100 if (GET_CODE (op) != PARALLEL
4101 || (GET_CODE (XVECEXP (op, 0, 0)) != SET)
4102 || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC)
4103 || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPEC_PUSH_MULT))
4109 /* Routines for use with attributes. */
4111 /* Return nonzero if ATTR is a valid attribute for DECL.
4112 ATTRIBUTES are any existing attributes and ARGS are
4113 the arguments supplied with ATTR.
4115 Supported attributes:
4118 don't output any prologue or epilogue code, the user is assumed
4119 to do the right thing.
4122 Interrupt Service Routine.
4125 Always assume that this function will be entered in ARM mode,
4126 not Thumb mode, and that the caller wishes to be returned to in
4129 arm_valid_decl_attribute_p (decl, attributes, attr, args)
4131 tree attributes ATTRIBUTE_UNUSED;
4135 /* The interrupt attribute can take args, so check for it before
4136 rejecting other attributes on the grounds that they did have args. */
4137 if (is_attribute_p ("isr", attr)
4138 || is_attribute_p ("interrupt", attr))
4139 return TREE_CODE (decl) == FUNCTION_DECL;
4141 if (args != NULL_TREE)
4144 if (is_attribute_p ("naked", attr))
4145 return TREE_CODE (decl) == FUNCTION_DECL;
4148 if (is_attribute_p ("interfacearm", attr))
4149 return TREE_CODE (decl) == FUNCTION_DECL;
4157 /* ARM/PE has three new attributes:
4158 naked - for interrupt functions
4159 dllexport - for exporting a function/variable that will live in a dll
4160 dllimport - for importing a function/variable from a dll
4162 Microsoft allows multiple declspecs in one __declspec, separating
4163 them with spaces. We do NOT support this. Instead, use __declspec
4168 arm_pe_valid_decl_attribute_p (decl, attributes, attr, args)
4174 if (args != NULL_TREE)
4177 if (is_attribute_p ("dllexport", attr))
4180 if (is_attribute_p ("dllimport", attr))
4183 return arm_valid_decl_attribute_p (decl, attributes, attr, args);
4188 /* Routines for use in generating RTL. */
4190 arm_gen_load_multiple (base_regno, count, from, up, write_back, unchanging_p,
4191 in_struct_p, scalar_p)
4203 int sign = up ? 1 : -1;
4206 /* XScale has load-store double instructions, but they have stricter
4207 alignment requirements than load-store multiple, so we can not
4210 For XScale ldm requires 2 + NREGS cycles to complete and blocks
4211 the pipeline until completion.
4219 An ldr instruction takes 1-3 cycles, but does not block the
4228 Best case ldr will always win. However, the more ldr instructions
4229 we issue, the less likely we are to be able to schedule them well.
4230 Using ldr instructions also increases code size.
4232 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
4233 for counts of 3 or 4 regs. */
4234 if (arm_is_xscale && count <= 2 && ! optimize_size)
4240 for (i = 0; i < count; i++)
4242 mem = gen_rtx_MEM (SImode, plus_constant (from, i * 4 * sign));
4243 RTX_UNCHANGING_P (mem) = unchanging_p;
4244 MEM_IN_STRUCT_P (mem) = in_struct_p;
4245 MEM_SCALAR_P (mem) = scalar_p;
4246 emit_move_insn (gen_rtx_REG (SImode, base_regno + i), mem);
4250 emit_move_insn (from, plus_constant (from, count * 4 * sign));
4252 seq = gen_sequence ();
4258 result = gen_rtx_PARALLEL (VOIDmode,
4259 rtvec_alloc (count + (write_back ? 1 : 0)));
4262 XVECEXP (result, 0, 0)
4263 = gen_rtx_SET (GET_MODE (from), from,
4264 plus_constant (from, count * 4 * sign));
4269 for (j = 0; i < count; i++, j++)
4271 mem = gen_rtx_MEM (SImode, plus_constant (from, j * 4 * sign));
4272 RTX_UNCHANGING_P (mem) = unchanging_p;
4273 MEM_IN_STRUCT_P (mem) = in_struct_p;
4274 MEM_SCALAR_P (mem) = scalar_p;
4275 XVECEXP (result, 0, i)
4276 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, base_regno + j), mem);
4283 arm_gen_store_multiple (base_regno, count, to, up, write_back, unchanging_p,
4284 in_struct_p, scalar_p)
4296 int sign = up ? 1 : -1;
4299 /* See arm_gen_load_multiple for discussion of
4300 the pros/cons of ldm/stm usage for XScale. */
4301 if (arm_is_xscale && count <= 2 && ! optimize_size)
4307 for (i = 0; i < count; i++)
4309 mem = gen_rtx_MEM (SImode, plus_constant (to, i * 4 * sign));
4310 RTX_UNCHANGING_P (mem) = unchanging_p;
4311 MEM_IN_STRUCT_P (mem) = in_struct_p;
4312 MEM_SCALAR_P (mem) = scalar_p;
4313 emit_move_insn (mem, gen_rtx_REG (SImode, base_regno + i));
4317 emit_move_insn (to, plus_constant (to, count * 4 * sign));
4319 seq = gen_sequence ();
4325 result = gen_rtx_PARALLEL (VOIDmode,
4326 rtvec_alloc (count + (write_back ? 1 : 0)));
4329 XVECEXP (result, 0, 0)
4330 = gen_rtx_SET (GET_MODE (to), to,
4331 plus_constant (to, count * 4 * sign));
4336 for (j = 0; i < count; i++, j++)
4338 mem = gen_rtx_MEM (SImode, plus_constant (to, j * 4 * sign));
4339 RTX_UNCHANGING_P (mem) = unchanging_p;
4340 MEM_IN_STRUCT_P (mem) = in_struct_p;
4341 MEM_SCALAR_P (mem) = scalar_p;
4343 XVECEXP (result, 0, i)
4344 = gen_rtx_SET (VOIDmode, mem, gen_rtx_REG (SImode, base_regno + j));
4351 arm_gen_movstrqi (operands)
4354 HOST_WIDE_INT in_words_to_go, out_words_to_go, last_bytes;
4357 rtx st_src, st_dst, fin_src, fin_dst;
4358 rtx part_bytes_reg = NULL;
4360 int dst_unchanging_p, dst_in_struct_p, src_unchanging_p, src_in_struct_p;
4361 int dst_scalar_p, src_scalar_p;
4363 if (GET_CODE (operands[2]) != CONST_INT
4364 || GET_CODE (operands[3]) != CONST_INT
4365 || INTVAL (operands[2]) > 64
4366 || INTVAL (operands[3]) & 3)
4369 st_dst = XEXP (operands[0], 0);
4370 st_src = XEXP (operands[1], 0);
4372 dst_unchanging_p = RTX_UNCHANGING_P (operands[0]);
4373 dst_in_struct_p = MEM_IN_STRUCT_P (operands[0]);
4374 dst_scalar_p = MEM_SCALAR_P (operands[0]);
4375 src_unchanging_p = RTX_UNCHANGING_P (operands[1]);
4376 src_in_struct_p = MEM_IN_STRUCT_P (operands[1]);
4377 src_scalar_p = MEM_SCALAR_P (operands[1]);
4379 fin_dst = dst = copy_to_mode_reg (SImode, st_dst);
4380 fin_src = src = copy_to_mode_reg (SImode, st_src);
4382 in_words_to_go = NUM_INTS (INTVAL (operands[2]));
4383 out_words_to_go = INTVAL (operands[2]) / 4;
4384 last_bytes = INTVAL (operands[2]) & 3;
4386 if (out_words_to_go != in_words_to_go && ((in_words_to_go - 1) & 3) != 0)
4387 part_bytes_reg = gen_rtx_REG (SImode, (in_words_to_go - 1) & 3);
4389 for (i = 0; in_words_to_go >= 2; i+=4)
4391 if (in_words_to_go > 4)
4392 emit_insn (arm_gen_load_multiple (0, 4, src, TRUE, TRUE,
4397 emit_insn (arm_gen_load_multiple (0, in_words_to_go, src, TRUE,
4398 FALSE, src_unchanging_p,
4399 src_in_struct_p, src_scalar_p));
4401 if (out_words_to_go)
4403 if (out_words_to_go > 4)
4404 emit_insn (arm_gen_store_multiple (0, 4, dst, TRUE, TRUE,
4408 else if (out_words_to_go != 1)
4409 emit_insn (arm_gen_store_multiple (0, out_words_to_go,
4418 mem = gen_rtx_MEM (SImode, dst);
4419 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
4420 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
4421 MEM_SCALAR_P (mem) = dst_scalar_p;
4422 emit_move_insn (mem, gen_rtx_REG (SImode, 0));
4423 if (last_bytes != 0)
4424 emit_insn (gen_addsi3 (dst, dst, GEN_INT (4)));
4428 in_words_to_go -= in_words_to_go < 4 ? in_words_to_go : 4;
4429 out_words_to_go -= out_words_to_go < 4 ? out_words_to_go : 4;
4432 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
4433 if (out_words_to_go)
4437 mem = gen_rtx_MEM (SImode, src);
4438 RTX_UNCHANGING_P (mem) = src_unchanging_p;
4439 MEM_IN_STRUCT_P (mem) = src_in_struct_p;
4440 MEM_SCALAR_P (mem) = src_scalar_p;
4441 emit_move_insn (sreg = gen_reg_rtx (SImode), mem);
4442 emit_move_insn (fin_src = gen_reg_rtx (SImode), plus_constant (src, 4));
4444 mem = gen_rtx_MEM (SImode, dst);
4445 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
4446 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
4447 MEM_SCALAR_P (mem) = dst_scalar_p;
4448 emit_move_insn (mem, sreg);
4449 emit_move_insn (fin_dst = gen_reg_rtx (SImode), plus_constant (dst, 4));
4452 if (in_words_to_go) /* Sanity check */
4458 if (in_words_to_go < 0)
4461 mem = gen_rtx_MEM (SImode, src);
4462 RTX_UNCHANGING_P (mem) = src_unchanging_p;
4463 MEM_IN_STRUCT_P (mem) = src_in_struct_p;
4464 MEM_SCALAR_P (mem) = src_scalar_p;
4465 part_bytes_reg = copy_to_mode_reg (SImode, mem);
4468 if (last_bytes && part_bytes_reg == NULL)
4471 if (BYTES_BIG_ENDIAN && last_bytes)
4473 rtx tmp = gen_reg_rtx (SImode);
4475 /* The bytes we want are in the top end of the word. */
4476 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg,
4477 GEN_INT (8 * (4 - last_bytes))));
4478 part_bytes_reg = tmp;
4482 mem = gen_rtx_MEM (QImode, plus_constant (dst, last_bytes - 1));
4483 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
4484 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
4485 MEM_SCALAR_P (mem) = dst_scalar_p;
4486 emit_move_insn (mem, gen_rtx_SUBREG (QImode, part_bytes_reg, 0));
4490 tmp = gen_reg_rtx (SImode);
4491 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8)));
4492 part_bytes_reg = tmp;
4501 mem = gen_rtx_MEM (HImode, dst);
4502 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
4503 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
4504 MEM_SCALAR_P (mem) = dst_scalar_p;
4505 emit_move_insn (mem, gen_rtx_SUBREG (HImode, part_bytes_reg, 0));
4509 rtx tmp = gen_reg_rtx (SImode);
4511 emit_insn (gen_addsi3 (dst, dst, GEN_INT (2)));
4512 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (16)));
4513 part_bytes_reg = tmp;
4519 mem = gen_rtx_MEM (QImode, dst);
4520 RTX_UNCHANGING_P (mem) = dst_unchanging_p;
4521 MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
4522 MEM_SCALAR_P (mem) = dst_scalar_p;
4523 emit_move_insn (mem, gen_rtx_SUBREG (QImode, part_bytes_reg, 0));
4530 /* Generate a memory reference for a half word, such that it will be loaded
4531 into the top 16 bits of the word. We can assume that the address is
4532 known to be alignable and of the form reg, or plus (reg, const). */
4534 arm_gen_rotated_half_load (memref)
4537 HOST_WIDE_INT offset = 0;
4538 rtx base = XEXP (memref, 0);
4540 if (GET_CODE (base) == PLUS)
4542 offset = INTVAL (XEXP (base, 1));
4543 base = XEXP (base, 0);
4546 /* If we aren't allowed to generate unaligned addresses, then fail. */
4547 if (TARGET_MMU_TRAPS
4548 && ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 0)))
4551 base = gen_rtx_MEM (SImode, plus_constant (base, offset & ~2));
4553 if ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 2))
4556 return gen_rtx_ROTATE (SImode, base, GEN_INT (16));
4559 /* Select a dominance comparison mode if possible. We support three forms.
4560 COND_OR == 0 => (X && Y)
4561 COND_OR == 1 => ((! X( || Y)
4562 COND_OR == 2 => (X || Y)
4563 If we are unable to support a dominance comparsison we return CC mode.
4564 This will then fail to match for the RTL expressions that generate this
4567 static enum machine_mode
4568 select_dominance_cc_mode (x, y, cond_or)
4571 HOST_WIDE_INT cond_or;
4573 enum rtx_code cond1, cond2;
4576 /* Currently we will probably get the wrong result if the individual
4577 comparisons are not simple. This also ensures that it is safe to
4578 reverse a comparison if necessary. */
4579 if ((arm_select_cc_mode (cond1 = GET_CODE (x), XEXP (x, 0), XEXP (x, 1))
4581 || (arm_select_cc_mode (cond2 = GET_CODE (y), XEXP (y, 0), XEXP (y, 1))
4585 /* The if_then_else variant of this tests the second condition if the
4586 first passes, but is true if the first fails. Reverse the first
4587 condition to get a true "inclusive-or" expression. */
4589 cond1 = reverse_condition (cond1);
4591 /* If the comparisons are not equal, and one doesn't dominate the other,
4592 then we can't do this. */
4594 && !comparison_dominates_p (cond1, cond2)
4595 && (swapped = 1, !comparison_dominates_p (cond2, cond1)))
4600 enum rtx_code temp = cond1;
4608 if (cond2 == EQ || !cond_or)
4613 case LE: return CC_DLEmode;
4614 case LEU: return CC_DLEUmode;
4615 case GE: return CC_DGEmode;
4616 case GEU: return CC_DGEUmode;
4623 if (cond2 == LT || !cond_or)
4632 if (cond2 == GT || !cond_or)
4641 if (cond2 == LTU || !cond_or)
4650 if (cond2 == GTU || !cond_or)
4658 /* The remaining cases only occur when both comparisons are the
4683 arm_select_cc_mode (op, x, y)
4688 /* All floating point compares return CCFP if it is an equality
4689 comparison, and CCFPE otherwise. */
4690 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
4717 /* A compare with a shifted operand. Because of canonicalization, the
4718 comparison will have to be swapped when we emit the assembler. */
4719 if (GET_MODE (y) == SImode && GET_CODE (y) == REG
4720 && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
4721 || GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE
4722 || GET_CODE (x) == ROTATERT))
4725 /* This is a special case that is used by combine to allow a
4726 comparison of a shifted byte load to be split into a zero-extend
4727 followed by a comparison of the shifted integer (only valid for
4728 equalities and unsigned inequalities). */
4729 if (GET_MODE (x) == SImode
4730 && GET_CODE (x) == ASHIFT
4731 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 24
4732 && GET_CODE (XEXP (x, 0)) == SUBREG
4733 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == MEM
4734 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == QImode
4735 && (op == EQ || op == NE
4736 || op == GEU || op == GTU || op == LTU || op == LEU)
4737 && GET_CODE (y) == CONST_INT)
4740 /* A construct for a conditional compare, if the false arm contains
4741 0, then both conditions must be true, otherwise either condition
4742 must be true. Not all conditions are possible, so CCmode is
4743 returned if it can't be done. */
4744 if (GET_CODE (x) == IF_THEN_ELSE
4745 && (XEXP (x, 2) == const0_rtx
4746 || XEXP (x, 2) == const1_rtx)
4747 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4748 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<')
4749 return select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1),
4750 INTVAL (XEXP (x, 2)));
4752 /* Alternate canonicalizations of the above. These are somewhat cleaner. */
4753 if (GET_CODE (x) == AND
4754 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4755 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<')
4756 return select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1), 0);
4758 if (GET_CODE (x) == IOR
4759 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4760 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<')
4761 return select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1), 2);
4763 /* An operation that sets the condition codes as a side-effect, the
4764 V flag is not set correctly, so we can only use comparisons where
4765 this doesn't matter. (For LT and GE we can use "mi" and "pl"
4767 if (GET_MODE (x) == SImode
4769 && (op == EQ || op == NE || op == LT || op == GE)
4770 && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
4771 || GET_CODE (x) == AND || GET_CODE (x) == IOR
4772 || GET_CODE (x) == XOR || GET_CODE (x) == MULT
4773 || GET_CODE (x) == NOT || GET_CODE (x) == NEG
4774 || GET_CODE (x) == LSHIFTRT
4775 || GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
4776 || GET_CODE (x) == ROTATERT || GET_CODE (x) == ZERO_EXTRACT))
4779 if (GET_MODE (x) == QImode && (op == EQ || op == NE))
4782 if (GET_MODE (x) == SImode && (op == LTU || op == GEU)
4783 && GET_CODE (x) == PLUS
4784 && (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y)))
4790 /* X and Y are two things to compare using CODE. Emit the compare insn and
4791 return the rtx for register 0 in the proper mode. FP means this is a
4792 floating point compare: I don't think that it is needed on the arm. */
4795 arm_gen_compare_reg (code, x, y)
4799 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
4800 rtx cc_reg = gen_rtx_REG (mode, CC_REGNUM);
4802 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
4803 gen_rtx_COMPARE (mode, x, y)));
4809 arm_reload_in_hi (operands)
4812 rtx ref = operands[1];
4814 HOST_WIDE_INT offset = 0;
4816 if (GET_CODE (ref) == SUBREG)
4818 offset = SUBREG_BYTE (ref);
4819 ref = SUBREG_REG (ref);
4822 if (GET_CODE (ref) == REG)
4824 /* We have a pseudo which has been spilt onto the stack; there
4825 are two cases here: the first where there is a simple
4826 stack-slot replacement and a second where the stack-slot is
4827 out of range, or is used as a subreg. */
4828 if (reg_equiv_mem[REGNO (ref)])
4830 ref = reg_equiv_mem[REGNO (ref)];
4831 base = find_replacement (&XEXP (ref, 0));
4834 /* The slot is out of range, or was dressed up in a SUBREG. */
4835 base = reg_equiv_address[REGNO (ref)];
4838 base = find_replacement (&XEXP (ref, 0));
4840 /* Handle the case where the address is too complex to be offset by 1. */
4841 if (GET_CODE (base) == MINUS
4842 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
4844 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
4846 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
4849 else if (GET_CODE (base) == PLUS)
4851 /* The addend must be CONST_INT, or we would have dealt with it above. */
4852 HOST_WIDE_INT hi, lo;
4854 offset += INTVAL (XEXP (base, 1));
4855 base = XEXP (base, 0);
4857 /* Rework the address into a legal sequence of insns. */
4858 /* Valid range for lo is -4095 -> 4095 */
4861 : -((-offset) & 0xfff));
4863 /* Corner case, if lo is the max offset then we would be out of range
4864 once we have added the additional 1 below, so bump the msb into the
4865 pre-loading insn(s). */
4869 hi = ((((offset - lo) & HOST_INT (0xffffffff))
4870 ^ HOST_INT (0x80000000))
4871 - HOST_INT (0x80000000));
4873 if (hi + lo != offset)
4878 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
4880 /* Get the base address; addsi3 knows how to handle constants
4881 that require more than one insn. */
4882 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
4888 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
4889 emit_insn (gen_zero_extendqisi2 (scratch,
4890 gen_rtx_MEM (QImode,
4891 plus_constant (base,
4893 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode, operands[0], 0),
4894 gen_rtx_MEM (QImode,
4895 plus_constant (base,
4897 if (!BYTES_BIG_ENDIAN)
4898 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
4899 gen_rtx_IOR (SImode,
4902 gen_rtx_SUBREG (SImode, operands[0], 0),
4906 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
4907 gen_rtx_IOR (SImode,
4908 gen_rtx_ASHIFT (SImode, scratch,
4910 gen_rtx_SUBREG (SImode, operands[0],
4914 /* Handle storing a half-word to memory during reload by synthesising as two
4915 byte stores. Take care not to clobber the input values until after we
4916 have moved them somewhere safe. This code assumes that if the DImode
4917 scratch in operands[2] overlaps either the input value or output address
4918 in some way, then that value must die in this insn (we absolutely need
4919 two scratch registers for some corner cases). */
4921 arm_reload_out_hi (operands)
4924 rtx ref = operands[0];
4925 rtx outval = operands[1];
4927 HOST_WIDE_INT offset = 0;
4929 if (GET_CODE (ref) == SUBREG)
4931 offset = SUBREG_BYTE (ref);
4932 ref = SUBREG_REG (ref);
4936 if (GET_CODE (ref) == REG)
4938 /* We have a pseudo which has been spilt onto the stack; there
4939 are two cases here: the first where there is a simple
4940 stack-slot replacement and a second where the stack-slot is
4941 out of range, or is used as a subreg. */
4942 if (reg_equiv_mem[REGNO (ref)])
4944 ref = reg_equiv_mem[REGNO (ref)];
4945 base = find_replacement (&XEXP (ref, 0));
4948 /* The slot is out of range, or was dressed up in a SUBREG. */
4949 base = reg_equiv_address[REGNO (ref)];
4952 base = find_replacement (&XEXP (ref, 0));
4954 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
4956 /* Handle the case where the address is too complex to be offset by 1. */
4957 if (GET_CODE (base) == MINUS
4958 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
4960 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
4962 /* Be careful not to destroy OUTVAL. */
4963 if (reg_overlap_mentioned_p (base_plus, outval))
4965 /* Updating base_plus might destroy outval, see if we can
4966 swap the scratch and base_plus. */
4967 if (!reg_overlap_mentioned_p (scratch, outval))
4970 scratch = base_plus;
4975 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
4977 /* Be conservative and copy OUTVAL into the scratch now,
4978 this should only be necessary if outval is a subreg
4979 of something larger than a word. */
4980 /* XXX Might this clobber base? I can't see how it can,
4981 since scratch is known to overlap with OUTVAL, and
4982 must be wider than a word. */
4983 emit_insn (gen_movhi (scratch_hi, outval));
4984 outval = scratch_hi;
4988 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
4991 else if (GET_CODE (base) == PLUS)
4993 /* The addend must be CONST_INT, or we would have dealt with it above. */
4994 HOST_WIDE_INT hi, lo;
4996 offset += INTVAL (XEXP (base, 1));
4997 base = XEXP (base, 0);
4999 /* Rework the address into a legal sequence of insns. */
5000 /* Valid range for lo is -4095 -> 4095 */
5003 : -((-offset) & 0xfff));
5005 /* Corner case, if lo is the max offset then we would be out of range
5006 once we have added the additional 1 below, so bump the msb into the
5007 pre-loading insn(s). */
5011 hi = ((((offset - lo) & HOST_INT (0xffffffff))
5012 ^ HOST_INT (0x80000000))
5013 - HOST_INT (0x80000000));
5015 if (hi + lo != offset)
5020 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
5022 /* Be careful not to destroy OUTVAL. */
5023 if (reg_overlap_mentioned_p (base_plus, outval))
5025 /* Updating base_plus might destroy outval, see if we
5026 can swap the scratch and base_plus. */
5027 if (!reg_overlap_mentioned_p (scratch, outval))
5030 scratch = base_plus;
5035 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2]));
5037 /* Be conservative and copy outval into scratch now,
5038 this should only be necessary if outval is a
5039 subreg of something larger than a word. */
5040 /* XXX Might this clobber base? I can't see how it
5041 can, since scratch is known to overlap with
5043 emit_insn (gen_movhi (scratch_hi, outval));
5044 outval = scratch_hi;
5048 /* Get the base address; addsi3 knows how to handle constants
5049 that require more than one insn. */
5050 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi)));
5056 if (BYTES_BIG_ENDIAN)
5058 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
5059 plus_constant (base, offset + 1)),
5060 gen_rtx_SUBREG (QImode, outval, 0)));
5061 emit_insn (gen_lshrsi3 (scratch,
5062 gen_rtx_SUBREG (SImode, outval, 0),
5064 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
5065 gen_rtx_SUBREG (QImode, scratch, 0)));
5069 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
5070 gen_rtx_SUBREG (QImode, outval, 0)));
5071 emit_insn (gen_lshrsi3 (scratch,
5072 gen_rtx_SUBREG (SImode, outval, 0),
5074 emit_insn (gen_movqi (gen_rtx_MEM (QImode,
5075 plus_constant (base, offset + 1)),
5076 gen_rtx_SUBREG (QImode, scratch, 0)));
5080 /* Print a symbolic form of X to the debug file, F. */
5082 arm_print_value (f, x)
5086 switch (GET_CODE (x))
5089 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (x));
5093 fprintf (f, "<0x%lx,0x%lx>", (long)XWINT (x, 2), (long)XWINT (x, 3));
5097 fprintf (f, "\"%s\"", XSTR (x, 0));
5101 fprintf (f, "`%s'", XSTR (x, 0));
5105 fprintf (f, "L%d", INSN_UID (XEXP (x, 0)));
5109 arm_print_value (f, XEXP (x, 0));
5113 arm_print_value (f, XEXP (x, 0));
5115 arm_print_value (f, XEXP (x, 1));
5123 fprintf (f, "????");
5128 /* Routines for manipulation of the constant pool. */
5130 /* Arm instructions cannot load a large constant directly into a
5131 register; they have to come from a pc relative load. The constant
5132 must therefore be placed in the addressable range of the pc
5133 relative load. Depending on the precise pc relative load
5134 instruction the range is somewhere between 256 bytes and 4k. This
5135 means that we often have to dump a constant inside a function, and
5136 generate code to branch around it.
5138 It is important to minimize this, since the branches will slow
5139 things down and make the code larger.
5141 Normally we can hide the table after an existing unconditional
5142 branch so that there is no interruption of the flow, but in the
5143 worst case the code looks like this:
5161 We fix this by performing a scan after scheduling, which notices
5162 which instructions need to have their operands fetched from the
5163 constant table and builds the table.
5165 The algorithm starts by building a table of all the constants that
5166 need fixing up and all the natural barriers in the function (places
5167 where a constant table can be dropped without breaking the flow).
5168 For each fixup we note how far the pc-relative replacement will be
5169 able to reach and the offset of the instruction into the function.
5171 Having built the table we then group the fixes together to form
5172 tables that are as large as possible (subject to addressing
5173 constraints) and emit each table of constants after the last
5174 barrier that is within range of all the instructions in the group.
5175 If a group does not contain a barrier, then we forcibly create one
5176 by inserting a jump instruction into the flow. Once the table has
5177 been inserted, the insns are then modified to reference the
5178 relevant entry in the pool.
5180 Possible enhancements to the algorithm (not implemented) are:
5182 1) For some processors and object formats, there may be benefit in
5183 aligning the pools to the start of cache lines; this alignment
5184 would need to be taken into account when calculating addressability
5187 /* These typedefs are located at the start of this file, so that
5188 they can be used in the prototypes there. This comment is to
5189 remind readers of that fact so that the following structures
5190 can be understood more easily.
5192 typedef struct minipool_node Mnode;
5193 typedef struct minipool_fixup Mfix; */
5195 struct minipool_node
5197 /* Doubly linked chain of entries. */
5200 /* The maximum offset into the code that this entry can be placed. While
5201 pushing fixes for forward references, all entries are sorted in order
5202 of increasing max_address. */
5203 HOST_WIDE_INT max_address;
5204 /* Similarly for a entry inserted for a backwards ref. */
5205 HOST_WIDE_INT min_address;
5206 /* The number of fixes referencing this entry. This can become zero
5207 if we "unpush" an entry. In this case we ignore the entry when we
5208 come to emit the code. */
5210 /* The offset from the start of the minipool. */
5211 HOST_WIDE_INT offset;
5212 /* The value in table. */
5214 /* The mode of value. */
5215 enum machine_mode mode;
5219 struct minipool_fixup
5223 HOST_WIDE_INT address;
5225 enum machine_mode mode;
5229 HOST_WIDE_INT forwards;
5230 HOST_WIDE_INT backwards;
5233 /* Fixes less than a word need padding out to a word boundary. */
5234 #define MINIPOOL_FIX_SIZE(mode) \
5235 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4)
5237 static Mnode * minipool_vector_head;
5238 static Mnode * minipool_vector_tail;
5239 static rtx minipool_vector_label;
5241 /* The linked list of all minipool fixes required for this function. */
5242 Mfix * minipool_fix_head;
5243 Mfix * minipool_fix_tail;
5244 /* The fix entry for the current minipool, once it has been placed. */
5245 Mfix * minipool_barrier;
5247 /* Determines if INSN is the start of a jump table. Returns the end
5248 of the TABLE or NULL_RTX. */
5250 is_jump_table (insn)
5255 if (GET_CODE (insn) == JUMP_INSN
5256 && JUMP_LABEL (insn) != NULL
5257 && ((table = next_real_insn (JUMP_LABEL (insn)))
5258 == next_real_insn (insn))
5260 && GET_CODE (table) == JUMP_INSN
5261 && (GET_CODE (PATTERN (table)) == ADDR_VEC
5262 || GET_CODE (PATTERN (table)) == ADDR_DIFF_VEC))
5268 static HOST_WIDE_INT
5269 get_jump_table_size (insn)
5272 rtx body = PATTERN (insn);
5273 int elt = GET_CODE (body) == ADDR_DIFF_VEC ? 1 : 0;
5275 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, elt);
5278 /* Move a minipool fix MP from its current location to before MAX_MP.
5279 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
5280 contrains may need updating. */
5282 move_minipool_fix_forward_ref (mp, max_mp, max_address)
5285 HOST_WIDE_INT max_address;
5287 /* This should never be true and the code below assumes these are
5294 if (max_address < mp->max_address)
5295 mp->max_address = max_address;
5299 if (max_address > max_mp->max_address - mp->fix_size)
5300 mp->max_address = max_mp->max_address - mp->fix_size;
5302 mp->max_address = max_address;
5304 /* Unlink MP from its current position. Since max_mp is non-null,
5305 mp->prev must be non-null. */
5306 mp->prev->next = mp->next;
5307 if (mp->next != NULL)
5308 mp->next->prev = mp->prev;
5310 minipool_vector_tail = mp->prev;
5312 /* Re-insert it before MAX_MP. */
5314 mp->prev = max_mp->prev;
5317 if (mp->prev != NULL)
5318 mp->prev->next = mp;
5320 minipool_vector_head = mp;
5323 /* Save the new entry. */
5326 /* Scan over the preceeding entries and adjust their addresses as
5328 while (mp->prev != NULL
5329 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
5331 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
5338 /* Add a constant to the minipool for a forward reference. Returns the
5339 node added or NULL if the constant will not fit in this pool. */
5341 add_minipool_forward_ref (fix)
5344 /* If set, max_mp is the first pool_entry that has a lower
5345 constraint than the one we are trying to add. */
5346 Mnode * max_mp = NULL;
5347 HOST_WIDE_INT max_address = fix->address + fix->forwards;
5350 /* If this fix's address is greater than the address of the first
5351 entry, then we can't put the fix in this pool. We subtract the
5352 size of the current fix to ensure that if the table is fully
5353 packed we still have enough room to insert this value by suffling
5354 the other fixes forwards. */
5355 if (minipool_vector_head &&
5356 fix->address >= minipool_vector_head->max_address - fix->fix_size)
5359 /* Scan the pool to see if a constant with the same value has
5360 already been added. While we are doing this, also note the
5361 location where we must insert the constant if it doesn't already
5363 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
5365 if (GET_CODE (fix->value) == GET_CODE (mp->value)
5366 && fix->mode == mp->mode
5367 && (GET_CODE (fix->value) != CODE_LABEL
5368 || (CODE_LABEL_NUMBER (fix->value)
5369 == CODE_LABEL_NUMBER (mp->value)))
5370 && rtx_equal_p (fix->value, mp->value))
5372 /* More than one fix references this entry. */
5374 return move_minipool_fix_forward_ref (mp, max_mp, max_address);
5377 /* Note the insertion point if necessary. */
5379 && mp->max_address > max_address)
5383 /* The value is not currently in the minipool, so we need to create
5384 a new entry for it. If MAX_MP is NULL, the entry will be put on
5385 the end of the list since the placement is less constrained than
5386 any existing entry. Otherwise, we insert the new fix before
5387 MAX_MP and, if neceesary, adjust the constraints on the other
5389 mp = xmalloc (sizeof (* mp));
5390 mp->fix_size = fix->fix_size;
5391 mp->mode = fix->mode;
5392 mp->value = fix->value;
5394 /* Not yet required for a backwards ref. */
5395 mp->min_address = -65536;
5399 mp->max_address = max_address;
5401 mp->prev = minipool_vector_tail;
5403 if (mp->prev == NULL)
5405 minipool_vector_head = mp;
5406 minipool_vector_label = gen_label_rtx ();
5409 mp->prev->next = mp;
5411 minipool_vector_tail = mp;
5415 if (max_address > max_mp->max_address - mp->fix_size)
5416 mp->max_address = max_mp->max_address - mp->fix_size;
5418 mp->max_address = max_address;
5421 mp->prev = max_mp->prev;
5423 if (mp->prev != NULL)
5424 mp->prev->next = mp;
5426 minipool_vector_head = mp;
5429 /* Save the new entry. */
5432 /* Scan over the preceeding entries and adjust their addresses as
5434 while (mp->prev != NULL
5435 && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
5437 mp->prev->max_address = mp->max_address - mp->prev->fix_size;
5445 move_minipool_fix_backward_ref (mp, min_mp, min_address)
5448 HOST_WIDE_INT min_address;
5450 HOST_WIDE_INT offset;
5452 /* This should never be true, and the code below assumes these are
5459 if (min_address > mp->min_address)
5460 mp->min_address = min_address;
5464 /* We will adjust this below if it is too loose. */
5465 mp->min_address = min_address;
5467 /* Unlink MP from its current position. Since min_mp is non-null,
5468 mp->next must be non-null. */
5469 mp->next->prev = mp->prev;
5470 if (mp->prev != NULL)
5471 mp->prev->next = mp->next;
5473 minipool_vector_head = mp->next;
5475 /* Reinsert it after MIN_MP. */
5477 mp->next = min_mp->next;
5479 if (mp->next != NULL)
5480 mp->next->prev = mp;
5482 minipool_vector_tail = mp;
5488 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
5490 mp->offset = offset;
5491 if (mp->refcount > 0)
5492 offset += mp->fix_size;
5494 if (mp->next && mp->next->min_address < mp->min_address + mp->fix_size)
5495 mp->next->min_address = mp->min_address + mp->fix_size;
5501 /* Add a constant to the minipool for a backward reference. Returns the
5502 node added or NULL if the constant will not fit in this pool.
5504 Note that the code for insertion for a backwards reference can be
5505 somewhat confusing because the calculated offsets for each fix do
5506 not take into account the size of the pool (which is still under
5509 add_minipool_backward_ref (fix)
5512 /* If set, min_mp is the last pool_entry that has a lower constraint
5513 than the one we are trying to add. */
5514 Mnode * min_mp = NULL;
5515 /* This can be negative, since it is only a constraint. */
5516 HOST_WIDE_INT min_address = fix->address - fix->backwards;
5519 /* If we can't reach the current pool from this insn, or if we can't
5520 insert this entry at the end of the pool without pushing other
5521 fixes out of range, then we don't try. This ensures that we
5522 can't fail later on. */
5523 if (min_address >= minipool_barrier->address
5524 || (minipool_vector_tail->min_address + fix->fix_size
5525 >= minipool_barrier->address))
5528 /* Scan the pool to see if a constant with the same value has
5529 already been added. While we are doing this, also note the
5530 location where we must insert the constant if it doesn't already
5532 for (mp = minipool_vector_tail; mp != NULL; mp = mp->prev)
5534 if (GET_CODE (fix->value) == GET_CODE (mp->value)
5535 && fix->mode == mp->mode
5536 && (GET_CODE (fix->value) != CODE_LABEL
5537 || (CODE_LABEL_NUMBER (fix->value)
5538 == CODE_LABEL_NUMBER (mp->value)))
5539 && rtx_equal_p (fix->value, mp->value)
5540 /* Check that there is enough slack to move this entry to the
5541 end of the table (this is conservative). */
5543 > (minipool_barrier->address
5544 + minipool_vector_tail->offset
5545 + minipool_vector_tail->fix_size)))
5548 return move_minipool_fix_backward_ref (mp, min_mp, min_address);
5552 mp->min_address += fix->fix_size;
5555 /* Note the insertion point if necessary. */
5556 if (mp->min_address < min_address)
5558 else if (mp->max_address
5559 < minipool_barrier->address + mp->offset + fix->fix_size)
5561 /* Inserting before this entry would push the fix beyond
5562 its maximum address (which can happen if we have
5563 re-located a forwards fix); force the new fix to come
5566 min_address = mp->min_address + fix->fix_size;
5571 /* We need to create a new entry. */
5572 mp = xmalloc (sizeof (* mp));
5573 mp->fix_size = fix->fix_size;
5574 mp->mode = fix->mode;
5575 mp->value = fix->value;
5577 mp->max_address = minipool_barrier->address + 65536;
5579 mp->min_address = min_address;
5584 mp->next = minipool_vector_head;
5586 if (mp->next == NULL)
5588 minipool_vector_tail = mp;
5589 minipool_vector_label = gen_label_rtx ();
5592 mp->next->prev = mp;
5594 minipool_vector_head = mp;
5598 mp->next = min_mp->next;
5602 if (mp->next != NULL)
5603 mp->next->prev = mp;
5605 minipool_vector_tail = mp;
5608 /* Save the new entry. */
5616 /* Scan over the following entries and adjust their offsets. */
5617 while (mp->next != NULL)
5619 if (mp->next->min_address < mp->min_address + mp->fix_size)
5620 mp->next->min_address = mp->min_address + mp->fix_size;
5623 mp->next->offset = mp->offset + mp->fix_size;
5625 mp->next->offset = mp->offset;
5634 assign_minipool_offsets (barrier)
5637 HOST_WIDE_INT offset = 0;
5640 minipool_barrier = barrier;
5642 for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
5644 mp->offset = offset;
5646 if (mp->refcount > 0)
5647 offset += mp->fix_size;
5651 /* Output the literal table */
5653 dump_minipool (scan)
5660 fprintf (rtl_dump_file,
5661 ";; Emitting minipool after insn %u; address %ld\n",
5662 INSN_UID (scan), (unsigned long) minipool_barrier->address);
5664 scan = emit_label_after (gen_label_rtx (), scan);
5665 scan = emit_insn_after (gen_align_4 (), scan);
5666 scan = emit_label_after (minipool_vector_label, scan);
5668 for (mp = minipool_vector_head; mp != NULL; mp = nmp)
5670 if (mp->refcount > 0)
5674 fprintf (rtl_dump_file,
5675 ";; Offset %u, min %ld, max %ld ",
5676 (unsigned) mp->offset, (unsigned long) mp->min_address,
5677 (unsigned long) mp->max_address);
5678 arm_print_value (rtl_dump_file, mp->value);
5679 fputc ('\n', rtl_dump_file);
5682 switch (mp->fix_size)
5684 #ifdef HAVE_consttable_1
5686 scan = emit_insn_after (gen_consttable_1 (mp->value), scan);
5690 #ifdef HAVE_consttable_2
5692 scan = emit_insn_after (gen_consttable_2 (mp->value), scan);
5696 #ifdef HAVE_consttable_4
5698 scan = emit_insn_after (gen_consttable_4 (mp->value), scan);
5702 #ifdef HAVE_consttable_8
5704 scan = emit_insn_after (gen_consttable_8 (mp->value), scan);
5718 minipool_vector_head = minipool_vector_tail = NULL;
5719 scan = emit_insn_after (gen_consttable_end (), scan);
5720 scan = emit_barrier_after (scan);
5723 /* Return the cost of forcibly inserting a barrier after INSN. */
5725 arm_barrier_cost (insn)
5728 /* Basing the location of the pool on the loop depth is preferable,
5729 but at the moment, the basic block information seems to be
5730 corrupt by this stage of the compilation. */
5732 rtx next = next_nonnote_insn (insn);
5734 if (next != NULL && GET_CODE (next) == CODE_LABEL)
5737 switch (GET_CODE (insn))
5740 /* It will always be better to place the table before the label, rather
5749 return base_cost - 10;
5752 return base_cost + 10;
5756 /* Find the best place in the insn stream in the range
5757 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
5758 Create the barrier by inserting a jump and add a new fix entry for
5761 create_fix_barrier (fix, max_address)
5763 HOST_WIDE_INT max_address;
5765 HOST_WIDE_INT count = 0;
5767 rtx from = fix->insn;
5768 rtx selected = from;
5770 HOST_WIDE_INT selected_address;
5772 HOST_WIDE_INT max_count = max_address - fix->address;
5773 rtx label = gen_label_rtx ();
5775 selected_cost = arm_barrier_cost (from);
5776 selected_address = fix->address;
5778 while (from && count < max_count)
5783 /* This code shouldn't have been called if there was a natural barrier
5785 if (GET_CODE (from) == BARRIER)
5788 /* Count the length of this insn. */
5789 count += get_attr_length (from);
5791 /* If there is a jump table, add its length. */
5792 tmp = is_jump_table (from);
5795 count += get_jump_table_size (tmp);
5797 /* Jump tables aren't in a basic block, so base the cost on
5798 the dispatch insn. If we select this location, we will
5799 still put the pool after the table. */
5800 new_cost = arm_barrier_cost (from);
5802 if (count < max_count && new_cost <= selected_cost)
5805 selected_cost = new_cost;
5806 selected_address = fix->address + count;
5809 /* Continue after the dispatch table. */
5810 from = NEXT_INSN (tmp);
5814 new_cost = arm_barrier_cost (from);
5816 if (count < max_count && new_cost <= selected_cost)
5819 selected_cost = new_cost;
5820 selected_address = fix->address + count;
5823 from = NEXT_INSN (from);
5826 /* Create a new JUMP_INSN that branches around a barrier. */
5827 from = emit_jump_insn_after (gen_jump (label), selected);
5828 JUMP_LABEL (from) = label;
5829 barrier = emit_barrier_after (from);
5830 emit_label_after (label, barrier);
5832 /* Create a minipool barrier entry for the new barrier. */
5833 new_fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* new_fix));
5834 new_fix->insn = barrier;
5835 new_fix->address = selected_address;
5836 new_fix->next = fix->next;
5837 fix->next = new_fix;
5842 /* Record that there is a natural barrier in the insn stream at
5845 push_minipool_barrier (insn, address)
5847 HOST_WIDE_INT address;
5849 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
5852 fix->address = address;
5855 if (minipool_fix_head != NULL)
5856 minipool_fix_tail->next = fix;
5858 minipool_fix_head = fix;
5860 minipool_fix_tail = fix;
5863 /* Record INSN, which will need fixing up to load a value from the
5864 minipool. ADDRESS is the offset of the insn since the start of the
5865 function; LOC is a pointer to the part of the insn which requires
5866 fixing; VALUE is the constant that must be loaded, which is of type
5869 push_minipool_fix (insn, address, loc, mode, value)
5871 HOST_WIDE_INT address;
5873 enum machine_mode mode;
5876 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix));
5878 #ifdef AOF_ASSEMBLER
5879 /* PIC symbol refereneces need to be converted into offsets into the
5881 /* XXX This shouldn't be done here. */
5882 if (flag_pic && GET_CODE (value) == SYMBOL_REF)
5883 value = aof_pic_entry (value);
5884 #endif /* AOF_ASSEMBLER */
5887 fix->address = address;
5890 fix->fix_size = MINIPOOL_FIX_SIZE (mode);
5892 fix->forwards = get_attr_pool_range (insn);
5893 fix->backwards = get_attr_neg_pool_range (insn);
5894 fix->minipool = NULL;
5896 /* If an insn doesn't have a range defined for it, then it isn't
5897 expecting to be reworked by this code. Better to abort now than
5898 to generate duff assembly code. */
5899 if (fix->forwards == 0 && fix->backwards == 0)
5904 fprintf (rtl_dump_file,
5905 ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ",
5906 GET_MODE_NAME (mode),
5907 INSN_UID (insn), (unsigned long) address,
5908 -1 * (long)fix->backwards, (long)fix->forwards);
5909 arm_print_value (rtl_dump_file, fix->value);
5910 fprintf (rtl_dump_file, "\n");
5913 /* Add it to the chain of fixes. */
5916 if (minipool_fix_head != NULL)
5917 minipool_fix_tail->next = fix;
5919 minipool_fix_head = fix;
5921 minipool_fix_tail = fix;
5924 /* Scan INSN and note any of its operands that need fixing. */
5926 note_invalid_constants (insn, address)
5928 HOST_WIDE_INT address;
5932 extract_insn (insn);
5934 if (!constrain_operands (1))
5935 fatal_insn_not_found (insn);
5937 /* Fill in recog_op_alt with information about the constraints of this
5939 preprocess_constraints ();
5941 for (opno = 0; opno < recog_data.n_operands; opno++)
5943 /* Things we need to fix can only occur in inputs. */
5944 if (recog_data.operand_type[opno] != OP_IN)
5947 /* If this alternative is a memory reference, then any mention
5948 of constants in this alternative is really to fool reload
5949 into allowing us to accept one there. We need to fix them up
5950 now so that we output the right code. */
5951 if (recog_op_alt[opno][which_alternative].memory_ok)
5953 rtx op = recog_data.operand[opno];
5955 if (CONSTANT_P (op))
5956 push_minipool_fix (insn, address, recog_data.operand_loc[opno],
5957 recog_data.operand_mode[opno], op);
5959 /* RWE: Now we look correctly at the operands for the insn,
5960 this shouldn't be needed any more. */
5961 #ifndef AOF_ASSEMBLER
5962 /* XXX Is this still needed? */
5963 else if (GET_CODE (op) == UNSPEC && XINT (op, 1) == UNSPEC_PIC_SYM)
5964 push_minipool_fix (insn, address, recog_data.operand_loc[opno],
5965 recog_data.operand_mode[opno],
5966 XVECEXP (op, 0, 0));
5969 else if (GET_CODE (op) == MEM
5970 && GET_CODE (XEXP (op, 0)) == SYMBOL_REF
5971 && CONSTANT_POOL_ADDRESS_P (XEXP (op, 0)))
5972 push_minipool_fix (insn, address, recog_data.operand_loc[opno],
5973 recog_data.operand_mode[opno],
5974 get_pool_constant (XEXP (op, 0)));
5984 HOST_WIDE_INT address = 0;
5987 minipool_fix_head = minipool_fix_tail = NULL;
5989 /* The first insn must always be a note, or the code below won't
5990 scan it properly. */
5991 if (GET_CODE (first) != NOTE)
5994 /* Scan all the insns and record the operands that will need fixing. */
5995 for (insn = next_nonnote_insn (first); insn; insn = next_nonnote_insn (insn))
5997 if (GET_CODE (insn) == BARRIER)
5998 push_minipool_barrier (insn, address);
5999 else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN
6000 || GET_CODE (insn) == JUMP_INSN)
6004 note_invalid_constants (insn, address);
6005 address += get_attr_length (insn);
6007 /* If the insn is a vector jump, add the size of the table
6008 and skip the table. */
6009 if ((table = is_jump_table (insn)) != NULL)
6011 address += get_jump_table_size (table);
6017 fix = minipool_fix_head;
6019 /* Now scan the fixups and perform the required changes. */
6024 Mfix * last_added_fix;
6025 Mfix * last_barrier = NULL;
6028 /* Skip any further barriers before the next fix. */
6029 while (fix && GET_CODE (fix->insn) == BARRIER)
6032 /* No more fixes. */
6036 last_added_fix = NULL;
6038 for (ftmp = fix; ftmp; ftmp = ftmp->next)
6040 if (GET_CODE (ftmp->insn) == BARRIER)
6042 if (ftmp->address >= minipool_vector_head->max_address)
6045 last_barrier = ftmp;
6047 else if ((ftmp->minipool = add_minipool_forward_ref (ftmp)) == NULL)
6050 last_added_fix = ftmp; /* Keep track of the last fix added. */
6053 /* If we found a barrier, drop back to that; any fixes that we
6054 could have reached but come after the barrier will now go in
6055 the next mini-pool. */
6056 if (last_barrier != NULL)
6058 /* Reduce the refcount for those fixes that won't go into this
6060 for (fdel = last_barrier->next;
6061 fdel && fdel != ftmp;
6064 fdel->minipool->refcount--;
6065 fdel->minipool = NULL;
6068 ftmp = last_barrier;
6072 /* ftmp is first fix that we can't fit into this pool and
6073 there no natural barriers that we could use. Insert a
6074 new barrier in the code somewhere between the previous
6075 fix and this one, and arrange to jump around it. */
6076 HOST_WIDE_INT max_address;
6078 /* The last item on the list of fixes must be a barrier, so
6079 we can never run off the end of the list of fixes without
6080 last_barrier being set. */
6084 max_address = minipool_vector_head->max_address;
6085 /* Check that there isn't another fix that is in range that
6086 we couldn't fit into this pool because the pool was
6087 already too large: we need to put the pool before such an
6089 if (ftmp->address < max_address)
6090 max_address = ftmp->address;
6092 last_barrier = create_fix_barrier (last_added_fix, max_address);
6095 assign_minipool_offsets (last_barrier);
6099 if (GET_CODE (ftmp->insn) != BARRIER
6100 && ((ftmp->minipool = add_minipool_backward_ref (ftmp))
6107 /* Scan over the fixes we have identified for this pool, fixing them
6108 up and adding the constants to the pool itself. */
6109 for (this_fix = fix; this_fix && ftmp != this_fix;
6110 this_fix = this_fix->next)
6111 if (GET_CODE (this_fix->insn) != BARRIER)
6114 = plus_constant (gen_rtx_LABEL_REF (VOIDmode,
6115 minipool_vector_label),
6116 this_fix->minipool->offset);
6117 *this_fix->loc = gen_rtx_MEM (this_fix->mode, addr);
6120 dump_minipool (last_barrier->insn);
6124 /* From now on we must synthesize any constants that we can't handle
6125 directly. This can happen if the RTL gets split during final
6126 instruction generation. */
6127 after_arm_reorg = 1;
6129 /* Free the minipool memory. */
6130 obstack_free (&minipool_obstack, minipool_startobj);
6133 /* Routines to output assembly language. */
6135 /* If the rtx is the correct value then return the string of the number.
6136 In this way we can ensure that valid double constants are generated even
6137 when cross compiling. */
6139 fp_immediate_constant (x)
6145 if (!fpa_consts_inited)
6148 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
6149 for (i = 0; i < 8; i++)
6150 if (REAL_VALUES_EQUAL (r, values_fpa[i]))
6151 return strings_fpa[i];
6156 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
6158 fp_const_from_val (r)
6159 REAL_VALUE_TYPE * r;
6163 if (!fpa_consts_inited)
6166 for (i = 0; i < 8; i++)
6167 if (REAL_VALUES_EQUAL (*r, values_fpa[i]))
6168 return strings_fpa[i];
6173 /* Output the operands of a LDM/STM instruction to STREAM.
6174 MASK is the ARM register set mask of which only bits 0-15 are important.
6175 REG is the base register, either the frame pointer or the stack pointer,
6176 INSTR is the possibly suffixed load or store instruction. */
6179 print_multi_reg (stream, instr, reg, mask)
6186 int not_first = FALSE;
6188 fputc ('\t', stream);
6189 asm_fprintf (stream, instr, reg);
6190 fputs (", {", stream);
6192 for (i = 0; i <= LAST_ARM_REGNUM; i++)
6193 if (mask & (1 << i))
6196 fprintf (stream, ", ");
6198 asm_fprintf (stream, "%r", i);
6202 fprintf (stream, "}%s\n", TARGET_APCS_32 ? "" : "^");
6205 /* Output a 'call' insn. */
6208 output_call (operands)
6211 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
6213 if (REGNO (operands[0]) == LR_REGNUM)
6215 operands[0] = gen_rtx_REG (SImode, IP_REGNUM);
6216 output_asm_insn ("mov%?\t%0, %|lr", operands);
6219 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
6221 if (TARGET_INTERWORK)
6222 output_asm_insn ("bx%?\t%0", operands);
6224 output_asm_insn ("mov%?\t%|pc, %0", operands);
6233 int something_changed = 0;
6235 int code = GET_CODE (x0);
6237 register const char * fmt;
6242 if (REGNO (x0) == LR_REGNUM)
6244 *x = gen_rtx_REG (SImode, IP_REGNUM);
6249 /* Scan through the sub-elements and change any references there. */
6250 fmt = GET_RTX_FORMAT (code);
6252 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6254 something_changed |= eliminate_lr2ip (&XEXP (x0, i));
6255 else if (fmt[i] == 'E')
6256 for (j = 0; j < XVECLEN (x0, i); j++)
6257 something_changed |= eliminate_lr2ip (&XVECEXP (x0, i, j));
6259 return something_changed;
6263 /* Output a 'call' insn that is a reference in memory. */
6266 output_call_mem (operands)
6269 operands[0] = copy_rtx (operands[0]); /* Be ultra careful. */
6270 /* Handle calls using lr by using ip (which may be clobbered in subr anyway). */
6271 if (eliminate_lr2ip (&operands[0]))
6272 output_asm_insn ("mov%?\t%|ip, %|lr", operands);
6274 if (TARGET_INTERWORK)
6276 output_asm_insn ("ldr%?\t%|ip, %0", operands);
6277 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
6278 output_asm_insn ("bx%?\t%|ip", operands);
6282 output_asm_insn ("mov%?\t%|lr, %|pc", operands);
6283 output_asm_insn ("ldr%?\t%|pc, %0", operands);
6290 /* Output a move from arm registers to an fpu registers.
6291 OPERANDS[0] is an fpu register.
6292 OPERANDS[1] is the first registers of an arm register pair. */
6295 output_mov_long_double_fpu_from_arm (operands)
6298 int arm_reg0 = REGNO (operands[1]);
6301 if (arm_reg0 == IP_REGNUM)
6304 ops[0] = gen_rtx_REG (SImode, arm_reg0);
6305 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
6306 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
6308 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops);
6309 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands);
6314 /* Output a move from an fpu register to arm registers.
6315 OPERANDS[0] is the first registers of an arm register pair.
6316 OPERANDS[1] is an fpu register. */
6319 output_mov_long_double_arm_from_fpu (operands)
6322 int arm_reg0 = REGNO (operands[0]);
6325 if (arm_reg0 == IP_REGNUM)
6328 ops[0] = gen_rtx_REG (SImode, arm_reg0);
6329 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
6330 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0);
6332 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands);
6333 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops);
6337 /* Output a move from arm registers to arm registers of a long double
6338 OPERANDS[0] is the destination.
6339 OPERANDS[1] is the source. */
6341 output_mov_long_double_arm_from_arm (operands)
6344 /* We have to be careful here because the two might overlap. */
6345 int dest_start = REGNO (operands[0]);
6346 int src_start = REGNO (operands[1]);
6350 if (dest_start < src_start)
6352 for (i = 0; i < 3; i++)
6354 ops[0] = gen_rtx_REG (SImode, dest_start + i);
6355 ops[1] = gen_rtx_REG (SImode, src_start + i);
6356 output_asm_insn ("mov%?\t%0, %1", ops);
6361 for (i = 2; i >= 0; i--)
6363 ops[0] = gen_rtx_REG (SImode, dest_start + i);
6364 ops[1] = gen_rtx_REG (SImode, src_start + i);
6365 output_asm_insn ("mov%?\t%0, %1", ops);
6373 /* Output a move from arm registers to an fpu registers.
6374 OPERANDS[0] is an fpu register.
6375 OPERANDS[1] is the first registers of an arm register pair. */
6378 output_mov_double_fpu_from_arm (operands)
6381 int arm_reg0 = REGNO (operands[1]);
6384 if (arm_reg0 == IP_REGNUM)
6387 ops[0] = gen_rtx_REG (SImode, arm_reg0);
6388 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
6389 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops);
6390 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands);
6394 /* Output a move from an fpu register to arm registers.
6395 OPERANDS[0] is the first registers of an arm register pair.
6396 OPERANDS[1] is an fpu register. */
6399 output_mov_double_arm_from_fpu (operands)
6402 int arm_reg0 = REGNO (operands[0]);
6405 if (arm_reg0 == IP_REGNUM)
6408 ops[0] = gen_rtx_REG (SImode, arm_reg0);
6409 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0);
6410 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands);
6411 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops);
6415 /* Output a move between double words.
6416 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
6417 or MEM<-REG and all MEMs must be offsettable addresses. */
6420 output_move_double (operands)
6423 enum rtx_code code0 = GET_CODE (operands[0]);
6424 enum rtx_code code1 = GET_CODE (operands[1]);
6429 int reg0 = REGNO (operands[0]);
6431 otherops[0] = gen_rtx_REG (SImode, 1 + reg0);
6435 int reg1 = REGNO (operands[1]);
6436 if (reg1 == IP_REGNUM)
6439 /* Ensure the second source is not overwritten. */
6440 if (reg1 == reg0 + (WORDS_BIG_ENDIAN ? -1 : 1))
6441 output_asm_insn ("mov%?\t%Q0, %Q1\n\tmov%?\t%R0, %R1", operands);
6443 output_asm_insn ("mov%?\t%R0, %R1\n\tmov%?\t%Q0, %Q1", operands);
6445 else if (code1 == CONST_DOUBLE)
6447 if (GET_MODE (operands[1]) == DFmode)
6450 union real_extract u;
6452 memcpy (&u, &CONST_DOUBLE_LOW (operands[1]), sizeof (u));
6453 REAL_VALUE_TO_TARGET_DOUBLE (u.d, l);
6454 otherops[1] = GEN_INT (l[1]);
6455 operands[1] = GEN_INT (l[0]);
6457 else if (GET_MODE (operands[1]) != VOIDmode)
6459 else if (WORDS_BIG_ENDIAN)
6462 otherops[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
6463 operands[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
6468 otherops[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
6469 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
6472 output_mov_immediate (operands);
6473 output_mov_immediate (otherops);
6475 else if (code1 == CONST_INT)
6477 #if HOST_BITS_PER_WIDE_INT > 32
6478 /* If HOST_WIDE_INT is more than 32 bits, the intval tells us
6479 what the upper word is. */
6480 if (WORDS_BIG_ENDIAN)
6482 otherops[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1])));
6483 operands[1] = GEN_INT (INTVAL (operands[1]) >> 32);
6487 otherops[1] = GEN_INT (INTVAL (operands[1]) >> 32);
6488 operands[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1])));
6491 /* Sign extend the intval into the high-order word. */
6492 if (WORDS_BIG_ENDIAN)
6494 otherops[1] = operands[1];
6495 operands[1] = (INTVAL (operands[1]) < 0
6496 ? constm1_rtx : const0_rtx);
6499 otherops[1] = INTVAL (operands[1]) < 0 ? constm1_rtx : const0_rtx;
6501 output_mov_immediate (otherops);
6502 output_mov_immediate (operands);
6504 else if (code1 == MEM)
6506 switch (GET_CODE (XEXP (operands[1], 0)))
6509 output_asm_insn ("ldm%?ia\t%m1, %M0", operands);
6513 abort (); /* Should never happen now. */
6517 output_asm_insn ("ldm%?db\t%m1!, %M0", operands);
6521 output_asm_insn ("ldm%?ia\t%m1!, %M0", operands);
6525 abort (); /* Should never happen now. */
6530 output_asm_insn ("adr%?\t%0, %1", operands);
6531 output_asm_insn ("ldm%?ia\t%0, %M0", operands);
6535 if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1),
6536 GET_MODE (XEXP (XEXP (operands[1], 0), 1))))
6538 otherops[0] = operands[0];
6539 otherops[1] = XEXP (XEXP (operands[1], 0), 0);
6540 otherops[2] = XEXP (XEXP (operands[1], 0), 1);
6541 if (GET_CODE (XEXP (operands[1], 0)) == PLUS)
6543 if (GET_CODE (otherops[2]) == CONST_INT)
6545 switch (INTVAL (otherops[2]))
6548 output_asm_insn ("ldm%?db\t%1, %M0", otherops);
6551 output_asm_insn ("ldm%?da\t%1, %M0", otherops);
6554 output_asm_insn ("ldm%?ib\t%1, %M0", otherops);
6557 if (!(const_ok_for_arm (INTVAL (otherops[2]))))
6558 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops);
6560 output_asm_insn ("add%?\t%0, %1, %2", otherops);
6563 output_asm_insn ("add%?\t%0, %1, %2", otherops);
6566 output_asm_insn ("sub%?\t%0, %1, %2", otherops);
6568 return "ldm%?ia\t%0, %M0";
6572 otherops[1] = adjust_address (operands[1], VOIDmode, 4);
6573 /* Take care of overlapping base/data reg. */
6574 if (reg_mentioned_p (operands[0], operands[1]))
6576 output_asm_insn ("ldr%?\t%0, %1", otherops);
6577 output_asm_insn ("ldr%?\t%0, %1", operands);
6581 output_asm_insn ("ldr%?\t%0, %1", operands);
6582 output_asm_insn ("ldr%?\t%0, %1", otherops);
6588 abort (); /* Constraints should prevent this. */
6590 else if (code0 == MEM && code1 == REG)
6592 if (REGNO (operands[1]) == IP_REGNUM)
6595 switch (GET_CODE (XEXP (operands[0], 0)))
6598 output_asm_insn ("stm%?ia\t%m0, %M1", operands);
6602 abort (); /* Should never happen now. */
6606 output_asm_insn ("stm%?db\t%m0!, %M1", operands);
6610 output_asm_insn ("stm%?ia\t%m0!, %M1", operands);
6614 abort (); /* Should never happen now. */
6618 if (GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
6620 switch (INTVAL (XEXP (XEXP (operands[0], 0), 1)))
6623 output_asm_insn ("stm%?db\t%m0, %M1", operands);
6627 output_asm_insn ("stm%?da\t%m0, %M1", operands);
6631 output_asm_insn ("stm%?ib\t%m0, %M1", operands);
6638 otherops[0] = adjust_address (operands[0], VOIDmode, 4);
6639 otherops[1] = gen_rtx_REG (SImode, 1 + REGNO (operands[1]));
6640 output_asm_insn ("str%?\t%1, %0", operands);
6641 output_asm_insn ("str%?\t%1, %0", otherops);
6645 abort (); /* Constraints should prevent this */
6651 /* Output an arbitrary MOV reg, #n.
6652 OPERANDS[0] is a register. OPERANDS[1] is a const_int. */
6655 output_mov_immediate (operands)
6658 HOST_WIDE_INT n = INTVAL (operands[1]);
6662 /* Try to use one MOV */
6663 if (const_ok_for_arm (n))
6665 output_asm_insn ("mov%?\t%0, %1", operands);
6669 /* Try to use one MVN */
6670 if (const_ok_for_arm (~n))
6672 operands[1] = GEN_INT (~n);
6673 output_asm_insn ("mvn%?\t%0, %1", operands);
6677 /* If all else fails, make it out of ORRs or BICs as appropriate. */
6679 for (i=0; i < 32; i++)
6683 if (n_ones > 16) /* Shorter to use MVN with BIC in this case. */
6684 output_multi_immediate (operands, "mvn%?\t%0, %1", "bic%?\t%0, %0, %1", 1, ~n);
6686 output_multi_immediate (operands, "mov%?\t%0, %1", "orr%?\t%0, %0, %1", 1, n);
6692 /* Output an ADD r, s, #n where n may be too big for one instruction. If
6693 adding zero to one register, output nothing. */
6696 output_add_immediate (operands)
6699 HOST_WIDE_INT n = INTVAL (operands[2]);
6701 if (n != 0 || REGNO (operands[0]) != REGNO (operands[1]))
6704 output_multi_immediate (operands,
6705 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
6708 output_multi_immediate (operands,
6709 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
6716 /* Output a multiple immediate operation.
6717 OPERANDS is the vector of operands referred to in the output patterns.
6718 INSTR1 is the output pattern to use for the first constant.
6719 INSTR2 is the output pattern to use for subsequent constants.
6720 IMMED_OP is the index of the constant slot in OPERANDS.
6721 N is the constant value. */
6724 output_multi_immediate (operands, instr1, instr2, immed_op, n)
6726 const char * instr1;
6727 const char * instr2;
6731 #if HOST_BITS_PER_WIDE_INT > 32
6732 n &= HOST_UINT (0xffffffff);
6737 operands[immed_op] = const0_rtx;
6738 output_asm_insn (instr1, operands); /* Quick and easy output. */
6743 const char * instr = instr1;
6745 /* Note that n is never zero here (which would give no output). */
6746 for (i = 0; i < 32; i += 2)
6750 operands[immed_op] = GEN_INT (n & (255 << i));
6751 output_asm_insn (instr, operands);
6762 /* Return the appropriate ARM instruction for the operation code.
6763 The returned result should not be overwritten. OP is the rtx of the
6764 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
6768 arithmetic_instr (op, shift_first_arg)
6770 int shift_first_arg;
6772 switch (GET_CODE (op))
6778 return shift_first_arg ? "rsb" : "sub";
6795 /* Ensure valid constant shifts and return the appropriate shift mnemonic
6796 for the operation code. The returned result should not be overwritten.
6797 OP is the rtx code of the shift.
6798 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
6802 shift_op (op, amountp)
6804 HOST_WIDE_INT *amountp;
6807 enum rtx_code code = GET_CODE (op);
6809 if (GET_CODE (XEXP (op, 1)) == REG || GET_CODE (XEXP (op, 1)) == SUBREG)
6811 else if (GET_CODE (XEXP (op, 1)) == CONST_INT)
6812 *amountp = INTVAL (XEXP (op, 1));
6835 /* We never have to worry about the amount being other than a
6836 power of 2, since this case can never be reloaded from a reg. */
6838 *amountp = int_log2 (*amountp);
6849 /* This is not 100% correct, but follows from the desire to merge
6850 multiplication by a power of 2 with the recognizer for a
6851 shift. >=32 is not a valid shift for "asl", so we must try and
6852 output a shift that produces the correct arithmetical result.
6853 Using lsr #32 is identical except for the fact that the carry bit
6854 is not set correctly if we set the flags; but we never use the
6855 carry bit from such an operation, so we can ignore that. */
6856 if (code == ROTATERT)
6857 *amountp &= 31; /* Rotate is just modulo 32 */
6858 else if (*amountp != (*amountp & 31))
6865 /* Shifts of 0 are no-ops. */
6874 /* Obtain the shift from the POWER of two. */
6875 static HOST_WIDE_INT
6877 HOST_WIDE_INT power;
6879 HOST_WIDE_INT shift = 0;
6881 while ((((HOST_INT (1)) << shift) & power) == 0)
6891 /* Output a .ascii pseudo-op, keeping track of lengths. This is because
6892 /bin/as is horribly restrictive. */
6893 #define MAX_ASCII_LEN 51
6896 output_ascii_pseudo_op (stream, p, len)
6898 const unsigned char * p;
6904 fputs ("\t.ascii\t\"", stream);
6906 for (i = 0; i < len; i++)
6908 register int c = p[i];
6910 if (len_so_far >= MAX_ASCII_LEN)
6912 fputs ("\"\n\t.ascii\t\"", stream);
6919 fputs ("\\t", stream);
6924 fputs ("\\f", stream);
6929 fputs ("\\b", stream);
6934 fputs ("\\r", stream);
6938 case TARGET_NEWLINE:
6939 fputs ("\\n", stream);
6941 if ((c >= ' ' && c <= '~')
6943 /* This is a good place for a line break. */
6944 len_so_far = MAX_ASCII_LEN;
6951 putc ('\\', stream);
6956 if (c >= ' ' && c <= '~')
6963 fprintf (stream, "\\%03o", c);
6970 fputs ("\"\n", stream);
6973 /* Compute a bit mask of which registers need to be
6974 saved on the stack for the current function. */
6976 static unsigned long
6977 arm_compute_save_reg_mask ()
6979 unsigned int save_reg_mask = 0;
6981 unsigned long func_type = arm_current_func_type ();
6983 if (IS_NAKED (func_type))
6984 /* This should never really happen. */
6987 /* If we are creating a stack frame, then we must save the frame pointer,
6988 IP (which will hold the old stack pointer), LR and the PC. */
6989 if (frame_pointer_needed)
6991 (1 << ARM_HARD_FRAME_POINTER_REGNUM)
6996 /* Volatile functions do not return, so there
6997 is no need to save any other registers. */
6998 if (IS_VOLATILE (func_type))
6999 return save_reg_mask;
7001 if (IS_INTERRUPT (func_type))
7003 unsigned int max_reg;
7005 /* Interrupt functions must not corrupt any registers,
7006 even call clobbered ones. If this is a leaf function
7007 we can just examine the registers used by the RTL, but
7008 otherwise we have to assume that whatever function is
7009 called might clobber anything, and so we have to save
7010 all the call-clobbered registers as well. */
7011 if (ARM_FUNC_TYPE (func_type) == ARM_FT_FIQ)
7012 /* FIQ handlers have registers r8 - r12 banked, so
7013 we only need to check r0 - r7, Normal ISRs only
7014 bank r14 and r15, so ew must check up to r12.
7015 r13 is the stack pointer which is always preserved,
7016 so we do not need to consider it here. */
7021 for (reg = 0; reg <= max_reg; reg++)
7022 if (regs_ever_live[reg]
7023 || (! current_function_is_leaf && call_used_regs [reg]))
7024 save_reg_mask |= (1 << reg);
7028 /* In the normal case we only need to save those registers
7029 which are call saved and which are used by this function. */
7030 for (reg = 0; reg <= 10; reg++)
7031 if (regs_ever_live[reg] && ! call_used_regs [reg])
7032 save_reg_mask |= (1 << reg);
7034 /* Handle the frame pointer as a special case. */
7035 if (! TARGET_APCS_FRAME
7036 && ! frame_pointer_needed
7037 && regs_ever_live[HARD_FRAME_POINTER_REGNUM]
7038 && ! call_used_regs[HARD_FRAME_POINTER_REGNUM])
7039 save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM;
7041 /* If we aren't loading the PIC register,
7042 don't stack it even though it may be live. */
7044 && ! TARGET_SINGLE_PIC_BASE
7045 && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
7046 save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
7049 /* Decide if we need to save the link register.
7050 Interrupt routines have their own banked link register,
7051 so they never need to save it.
7052 Otheriwse if we do not use the link register we do not need to save
7053 it. If we are pushing other registers onto the stack however, we
7054 can save an instruction in the epilogue by pushing the link register
7055 now and then popping it back into the PC. This incurs extra memory
7056 accesses though, so we only do it when optimising for size, and only
7057 if we know that we will not need a fancy return sequence. */
7058 if (! IS_INTERRUPT (func_type)
7059 && (regs_ever_live [LR_REGNUM]
7062 && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL)))
7063 save_reg_mask |= 1 << LR_REGNUM;
7065 if (cfun->machine->lr_save_eliminated)
7066 save_reg_mask &= ~ (1 << LR_REGNUM);
7068 return save_reg_mask;
7071 /* Generate a function exit sequence. If REALLY_RETURN is true, then do
7072 everything bar the final return instruction. */
7075 output_return_instruction (operand, really_return, reverse)
7080 char conditional[10];
7083 unsigned long live_regs_mask;
7084 unsigned long func_type;
7086 func_type = arm_current_func_type ();
7088 if (IS_NAKED (func_type))
7091 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
7093 /* If this function was declared non-returning, and we have found a tail
7094 call, then we have to trust that the called function won't return. */
7099 /* Otherwise, trap an attempted return by aborting. */
7101 ops[1] = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)"
7103 assemble_external_libcall (ops[1]);
7104 output_asm_insn (reverse ? "bl%D0\t%a1" : "bl%d0\t%a1", ops);
7110 if (current_function_calls_alloca && !really_return)
7113 /* Construct the conditional part of the instruction(s) to be emitted. */
7114 sprintf (conditional, "%%?%%%c0", reverse ? 'D' : 'd');
7116 return_used_this_function = 1;
7118 live_regs_mask = arm_compute_save_reg_mask ();
7120 /* On some ARM architectures it is faster to use LDR rather than LDM to
7121 load a single register. On other architectures, the cost is the same.
7122 In 26 bit mode we have to use LDM in order to be able to restore the CPSR. */
7123 if ((live_regs_mask == (1 << LR_REGNUM))
7124 && ! TARGET_INTERWORK
7125 && ! IS_INTERRUPT (func_type)
7126 && (! really_return || TARGET_APCS_32))
7128 if (! really_return)
7129 sprintf (instr, "ldr%s\t%%|lr, [%%|sp], #4", conditional);
7131 sprintf (instr, "ldr%s\t%%|pc, [%%|sp], #4", conditional);
7133 else if (live_regs_mask)
7135 if ((live_regs_mask & (1 << IP_REGNUM)) == (1 << IP_REGNUM))
7136 /* There are two possible reasons for the IP register being saved.
7137 Either a stack frame was created, in which case IP contains the
7138 old stack pointer, or an ISR routine corrupted it. If this in an
7139 ISR routine then just restore IP, otherwise restore IP into SP. */
7140 if (! IS_INTERRUPT (func_type))
7142 live_regs_mask &= ~ (1 << IP_REGNUM);
7143 live_regs_mask |= (1 << SP_REGNUM);
7146 /* Generate the load multiple instruction to restore the registers. */
7147 if (frame_pointer_needed)
7148 sprintf (instr, "ldm%sea\t%%|fp, {", conditional);
7150 sprintf (instr, "ldm%sfd\t%%|sp!, {", conditional);
7152 for (reg = 0; reg <= SP_REGNUM; reg++)
7153 if (live_regs_mask & (1 << reg))
7155 strcat (instr, "%|");
7156 strcat (instr, reg_names[reg]);
7157 strcat (instr, ", ");
7160 if ((live_regs_mask & (1 << LR_REGNUM)) == 0)
7162 /* If we are not restoring the LR register then we will
7163 have added one too many commas to the list above.
7164 Replace it with a closing brace. */
7165 instr [strlen (instr) - 2] = '}';
7169 strcat (instr, "%|");
7171 /* At this point there should only be one or two registers left in
7172 live_regs_mask: always LR, and possibly PC if we created a stack
7173 frame. LR contains the return address. If we do not have any
7174 special requirements for function exit (eg interworking, or ISR)
7175 then we can load this value directly into the PC and save an
7177 if (! TARGET_INTERWORK
7178 && ! IS_INTERRUPT (func_type)
7180 strcat (instr, reg_names [PC_REGNUM]);
7182 strcat (instr, reg_names [LR_REGNUM]);
7184 strcat (instr, (TARGET_APCS_32 || !really_return) ? "}" : "}^");
7189 /* See if we need to generate an extra instruction to
7190 perform the actual function return. */
7191 switch ((int) ARM_FUNC_TYPE (func_type))
7195 output_asm_insn (instr, & operand);
7197 strcpy (instr, "sub");
7198 strcat (instr, conditional);
7199 strcat (instr, "s\t%|pc, %|lr, #4");
7202 case ARM_FT_EXCEPTION:
7203 output_asm_insn (instr, & operand);
7205 strcpy (instr, "mov");
7206 strcat (instr, conditional);
7207 strcat (instr, "s\t%|pc, %|lr");
7210 case ARM_FT_INTERWORKED:
7211 output_asm_insn (instr, & operand);
7213 strcpy (instr, "bx");
7214 strcat (instr, conditional);
7215 strcat (instr, "\t%|lr");
7219 /* The return has already been handled
7220 by loading the LR into the PC. */
7221 if ((live_regs_mask & (1 << LR_REGNUM)) == 0)
7223 output_asm_insn (instr, & operand);
7225 strcpy (instr, "mov");
7226 strcat (instr, conditional);
7227 if (! TARGET_APCS_32)
7228 strcat (instr, "s");
7229 strcat (instr, "\t%|pc, %|lr");
7235 else if (really_return)
7237 switch ((int) ARM_FUNC_TYPE (func_type))
7241 sprintf (instr, "sub%ss\t%%|pc, %%|lr, #4", conditional);
7244 case ARM_FT_INTERWORKED:
7245 sprintf (instr, "bx%s\t%%|lr", conditional);
7248 case ARM_FT_EXCEPTION:
7249 sprintf (instr, "mov%ss\t%%|pc, %%|lr", conditional);
7253 sprintf (instr, "mov%s%s\t%%|pc, %%|lr",
7254 conditional, TARGET_APCS_32 ? "" : "s");
7259 /* Nothing to load off the stack, and
7260 no return instruction to generate. */
7263 output_asm_insn (instr, & operand);
7268 /* Write the function name into the code section, directly preceding
7269 the function prologue.
7271 Code will be output similar to this:
7273 .ascii "arm_poke_function_name", 0
7276 .word 0xff000000 + (t1 - t0)
7277 arm_poke_function_name
7279 stmfd sp!, {fp, ip, lr, pc}
7282 When performing a stack backtrace, code can inspect the value
7283 of 'pc' stored at 'fp' + 0. If the trace function then looks
7284 at location pc - 12 and the top 8 bits are set, then we know
7285 that there is a function name embedded immediately preceding this
7286 location and has length ((pc[-3]) & 0xff000000).
7288 We assume that pc is declared as a pointer to an unsigned long.
7290 It is of no benefit to output the function name if we are assembling
7291 a leaf function. These function types will not contain a stack
7292 backtrace structure, therefore it is not possible to determine the
7296 arm_poke_function_name (stream, name)
7300 unsigned long alignlength;
7301 unsigned long length;
7304 length = strlen (name) + 1;
7305 alignlength = ROUND_UP (length);
7307 ASM_OUTPUT_ASCII (stream, name, length);
7308 ASM_OUTPUT_ALIGN (stream, 2);
7309 x = GEN_INT (HOST_UINT(0xff000000) + alignlength);
7310 ASM_OUTPUT_INT (stream, x);
7313 /* Place some comments into the assembler stream
7314 describing the current function. */
7317 output_arm_prologue (f, frame_size)
7321 unsigned long func_type;
7324 if (arm_ccfsm_state || arm_target_insn)
7327 func_type = arm_current_func_type ();
7329 switch ((int) ARM_FUNC_TYPE (func_type))
7334 case ARM_FT_INTERWORKED:
7335 asm_fprintf (f, "\t%@ Function supports interworking.\n");
7337 case ARM_FT_EXCEPTION_HANDLER:
7338 asm_fprintf (f, "\t%@ C++ Exception Handler.\n");
7341 asm_fprintf (f, "\t%@ Interrupt Service Routine.\n");
7344 asm_fprintf (f, "\t%@ Fast Interrupt Service Routine.\n");
7346 case ARM_FT_EXCEPTION:
7347 asm_fprintf (f, "\t%@ ARM Exception Handler.\n");
7351 if (IS_NAKED (func_type))
7352 asm_fprintf (f, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n");
7354 if (IS_VOLATILE (func_type))
7355 asm_fprintf (f, "\t%@ Volatile: function does not return.\n");
7357 if (IS_NESTED (func_type))
7358 asm_fprintf (f, "\t%@ Nested: function declared inside another function.\n");
7360 asm_fprintf (f, "\t%@ args = %d, pretend = %d, frame = %d\n",
7361 current_function_args_size,
7362 current_function_pretend_args_size, frame_size);
7364 asm_fprintf (f, "\t%@ frame_needed = %d, current_function_anonymous_args = %d\n",
7365 frame_pointer_needed,
7366 current_function_anonymous_args);
7368 if (cfun->machine->lr_save_eliminated)
7369 asm_fprintf (f, "\t%@ link register save eliminated.\n");
7371 #ifdef AOF_ASSEMBLER
7373 asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, PIC_OFFSET_TABLE_REGNUM);
7376 return_used_this_function = 0;
7380 arm_output_epilogue (really_return)
7384 unsigned long saved_regs_mask;
7385 unsigned long func_type;
7386 /* If we need this, then it will always be at least this much. */
7387 int floats_offset = 12;
7389 int frame_size = get_frame_size ();
7390 FILE * f = asm_out_file;
7391 rtx eh_ofs = cfun->machine->eh_epilogue_sp_ofs;
7393 /* If we have already generated the return instruction
7394 then it is futile to generate anything else. */
7395 if (use_return_insn (FALSE) && return_used_this_function)
7398 func_type = arm_current_func_type ();
7400 if (IS_NAKED (func_type))
7401 /* Naked functions don't have epilogues. */
7404 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN)
7408 /* A volatile function should never return. Call abort. */
7409 op = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" : "abort");
7410 assemble_external_libcall (op);
7411 output_asm_insn ("bl\t%a0", &op);
7416 if (ARM_FUNC_TYPE (func_type) == ARM_FT_EXCEPTION_HANDLER
7418 /* If we are throwing an exception, then we really must
7419 be doing a return, so we can't tail-call. */
7422 saved_regs_mask = arm_compute_save_reg_mask ();
7424 /* Compute how far away the floats will be. */
7425 for (reg = 0; reg <= LAST_ARM_REGNUM; reg ++)
7426 if (saved_regs_mask & (1 << reg))
7429 if (frame_pointer_needed)
7431 if (arm_fpu_arch == FP_SOFT2)
7433 for (reg = LAST_ARM_FP_REGNUM; reg >= FIRST_ARM_FP_REGNUM; reg--)
7434 if (regs_ever_live[reg] && !call_used_regs[reg])
7436 floats_offset += 12;
7437 asm_fprintf (f, "\tldfe\t%r, [%r, #-%d]\n",
7438 reg, FP_REGNUM, floats_offset);
7443 int start_reg = LAST_ARM_FP_REGNUM;
7445 for (reg = LAST_ARM_FP_REGNUM; reg >= FIRST_ARM_FP_REGNUM; reg--)
7447 if (regs_ever_live[reg] && !call_used_regs[reg])
7449 floats_offset += 12;
7451 /* We can't unstack more than four registers at once. */
7452 if (start_reg - reg == 3)
7454 asm_fprintf (f, "\tlfm\t%r, 4, [%r, #-%d]\n",
7455 reg, FP_REGNUM, floats_offset);
7456 start_reg = reg - 1;
7461 if (reg != start_reg)
7462 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
7463 reg + 1, start_reg - reg,
7464 FP_REGNUM, floats_offset);
7465 start_reg = reg - 1;
7469 /* Just in case the last register checked also needs unstacking. */
7470 if (reg != start_reg)
7471 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n",
7472 reg + 1, start_reg - reg,
7473 FP_REGNUM, floats_offset);
7476 /* saved_regs_mask should contain the IP, which at the time of stack
7477 frame generation actually contains the old stack pointer. So a
7478 quick way to unwind the stack is just pop the IP register directly
7479 into the stack pointer. */
7480 if ((saved_regs_mask & (1 << IP_REGNUM)) == 0)
7482 saved_regs_mask &= ~ (1 << IP_REGNUM);
7483 saved_regs_mask |= (1 << SP_REGNUM);
7485 /* There are two registers left in saved_regs_mask - LR and PC. We
7486 only need to restore the LR register (the return address), but to
7487 save time we can load it directly into the PC, unless we need a
7488 special function exit sequence, or we are not really returning. */
7489 if (really_return && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL)
7490 /* Delete the LR from the register mask, so that the LR on
7491 the stack is loaded into the PC in the register mask. */
7492 saved_regs_mask &= ~ (1 << LR_REGNUM);
7494 saved_regs_mask &= ~ (1 << PC_REGNUM);
7496 print_multi_reg (f, "ldmea\t%r", FP_REGNUM, saved_regs_mask);
7498 if (IS_INTERRUPT (func_type))
7499 /* Interrupt handlers will have pushed the
7500 IP onto the stack, so restore it now. */
7501 print_multi_reg (f, "ldmea\t%r", SP_REGNUM, 1 << IP_REGNUM);
7505 /* Restore stack pointer if necessary. */
7506 if (frame_size + current_function_outgoing_args_size != 0)
7508 operands[0] = operands[1] = stack_pointer_rtx;
7509 operands[2] = GEN_INT (frame_size
7510 + current_function_outgoing_args_size);
7511 output_add_immediate (operands);
7514 if (arm_fpu_arch == FP_SOFT2)
7516 for (reg = FIRST_ARM_FP_REGNUM; reg <= LAST_ARM_FP_REGNUM; reg++)
7517 if (regs_ever_live[reg] && !call_used_regs[reg])
7518 asm_fprintf (f, "\tldfe\t%r, [%r], #12\n",
7523 int start_reg = FIRST_ARM_FP_REGNUM;
7525 for (reg = FIRST_ARM_FP_REGNUM; reg <= LAST_ARM_FP_REGNUM; reg++)
7527 if (regs_ever_live[reg] && !call_used_regs[reg])
7529 if (reg - start_reg == 3)
7531 asm_fprintf (f, "\tlfmfd\t%r, 4, [%r]!\n",
7532 start_reg, SP_REGNUM);
7533 start_reg = reg + 1;
7538 if (reg != start_reg)
7539 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
7540 start_reg, reg - start_reg,
7543 start_reg = reg + 1;
7547 /* Just in case the last register checked also needs unstacking. */
7548 if (reg != start_reg)
7549 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n",
7550 start_reg, reg - start_reg, SP_REGNUM);
7553 /* If we can, restore the LR into the PC. */
7554 if (ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL
7556 && current_function_pretend_args_size == 0
7557 && saved_regs_mask & (1 << LR_REGNUM))
7559 saved_regs_mask &= ~ (1 << LR_REGNUM);
7560 saved_regs_mask |= (1 << PC_REGNUM);
7563 /* Load the registers off the stack. If we only have one register
7564 to load use the LDR instruction - it is faster. */
7565 if (saved_regs_mask == (1 << LR_REGNUM))
7567 /* The excpetion handler ignores the LR, so we do
7568 not really need to load it off the stack. */
7570 asm_fprintf (f, "\tadd\t%r, %r, #4\n", SP_REGNUM, SP_REGNUM);
7572 asm_fprintf (f, "\tldr\t%r, [%r], #4\n", LR_REGNUM, SP_REGNUM);
7574 else if (saved_regs_mask)
7575 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, saved_regs_mask);
7577 if (current_function_pretend_args_size)
7579 /* Unwind the pre-pushed regs. */
7580 operands[0] = operands[1] = stack_pointer_rtx;
7581 operands[2] = GEN_INT (current_function_pretend_args_size);
7582 output_add_immediate (operands);
7587 if (ARM_FUNC_TYPE (func_type) == ARM_FT_EXCEPTION_HANDLER)
7588 /* Adjust the stack to remove the exception handler stuff. */
7589 asm_fprintf (f, "\tadd\t%r, %r, %r\n", SP_REGNUM, SP_REGNUM,
7593 if (! really_return)
7596 /* Generate the return instruction. */
7597 switch ((int) ARM_FUNC_TYPE (func_type))
7599 case ARM_FT_EXCEPTION_HANDLER:
7600 /* Even in 26-bit mode we do a mov (rather than a movs)
7601 because we don't have the PSR bits set in the address. */
7602 asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, EXCEPTION_LR_REGNUM);
7607 asm_fprintf (f, "\tsubs\t%r, %r, #4\n", PC_REGNUM, LR_REGNUM);
7610 case ARM_FT_EXCEPTION:
7611 asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM);
7614 case ARM_FT_INTERWORKED:
7615 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM);
7619 if (frame_pointer_needed)
7620 /* If we used the frame pointer then the return adddress
7621 will have been loaded off the stack directly into the
7622 PC, so there is no need to issue a MOV instruction
7625 else if (current_function_pretend_args_size == 0
7626 && (saved_regs_mask & (1 << LR_REGNUM)))
7627 /* Similarly we may have been able to load LR into the PC
7628 even if we did not create a stack frame. */
7630 else if (TARGET_APCS_32)
7631 asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, LR_REGNUM);
7633 asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM);
7641 output_func_epilogue (frame_size)
7646 /* ??? Probably not safe to set this here, since it assumes that a
7647 function will be emitted as assembly immediately after we generate
7648 RTL for it. This does not happen for inline functions. */
7649 return_used_this_function = 0;
7653 if (use_return_insn (FALSE)
7654 && return_used_this_function
7655 && (frame_size + current_function_outgoing_args_size) != 0
7656 && !frame_pointer_needed)
7659 /* Reset the ARM-specific per-function variables. */
7660 current_function_anonymous_args = 0;
7661 after_arm_reorg = 0;
7665 /* Generate and emit an insn that we will recognize as a push_multi.
7666 Unfortunately, since this insn does not reflect very well the actual
7667 semantics of the operation, we need to annotate the insn for the benefit
7668 of DWARF2 frame unwind information. */
7671 emit_multi_reg_push (mask)
7679 int dwarf_par_index;
7682 for (i = 0; i <= LAST_ARM_REGNUM; i++)
7683 if (mask & (1 << i))
7686 if (num_regs == 0 || num_regs > 16)
7689 /* We don't record the PC in the dwarf frame information. */
7690 num_dwarf_regs = num_regs;
7691 if (mask & (1 << PC_REGNUM))
7694 /* For the body of the insn we are going to generate an UNSPEC in
7695 parallel with several USEs. This allows the insn to be recognised
7696 by the push_multi pattern in the arm.md file. The insn looks
7697 something like this:
7700 (set (mem:BLK (pre_dec:BLK (reg:SI sp)))
7701 (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT))
7702 (use (reg:SI 11 fp))
7703 (use (reg:SI 12 ip))
7704 (use (reg:SI 14 lr))
7705 (use (reg:SI 15 pc))
7708 For the frame note however, we try to be more explicit and actually
7709 show each register being stored into the stack frame, plus a (single)
7710 decrement of the stack pointer. We do it this way in order to be
7711 friendly to the stack unwinding code, which only wants to see a single
7712 stack decrement per instruction. The RTL we generate for the note looks
7713 something like this:
7716 (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20)))
7717 (set (mem:SI (reg:SI sp)) (reg:SI r4))
7718 (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp))
7719 (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip))
7720 (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr))
7723 This sequence is used both by the code to support stack unwinding for
7724 exceptions handlers and the code to generate dwarf2 frame debugging. */
7726 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_regs));
7727 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (num_dwarf_regs + 1));
7728 RTX_FRAME_RELATED_P (dwarf) = 1;
7729 dwarf_par_index = 1;
7731 for (i = 0; i <= LAST_ARM_REGNUM; i++)
7733 if (mask & (1 << i))
7735 reg = gen_rtx_REG (SImode, i);
7738 = gen_rtx_SET (VOIDmode,
7739 gen_rtx_MEM (BLKmode,
7740 gen_rtx_PRE_DEC (BLKmode,
7741 stack_pointer_rtx)),
7742 gen_rtx_UNSPEC (BLKmode,
7748 tmp = gen_rtx_SET (VOIDmode,
7749 gen_rtx_MEM (SImode, stack_pointer_rtx),
7751 RTX_FRAME_RELATED_P (tmp) = 1;
7752 XVECEXP (dwarf, 0, dwarf_par_index) = tmp;
7760 for (j = 1, i++; j < num_regs; i++)
7762 if (mask & (1 << i))
7764 reg = gen_rtx_REG (SImode, i);
7766 XVECEXP (par, 0, j) = gen_rtx_USE (VOIDmode, reg);
7770 tmp = gen_rtx_SET (VOIDmode,
7771 gen_rtx_MEM (SImode,
7772 plus_constant (stack_pointer_rtx,
7775 RTX_FRAME_RELATED_P (tmp) = 1;
7776 XVECEXP (dwarf, 0, dwarf_par_index++) = tmp;
7783 par = emit_insn (par);
7785 tmp = gen_rtx_SET (SImode,
7787 gen_rtx_PLUS (SImode,
7789 GEN_INT (-4 * num_regs)));
7790 RTX_FRAME_RELATED_P (tmp) = 1;
7791 XVECEXP (dwarf, 0, 0) = tmp;
7793 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
7799 emit_sfm (base_reg, count)
7808 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
7809 dwarf = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
7810 RTX_FRAME_RELATED_P (dwarf) = 1;
7812 reg = gen_rtx_REG (XFmode, base_reg++);
7815 = gen_rtx_SET (VOIDmode,
7816 gen_rtx_MEM (BLKmode,
7817 gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
7818 gen_rtx_UNSPEC (BLKmode,
7822 = gen_rtx_SET (VOIDmode,
7823 gen_rtx_MEM (XFmode,
7824 gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)),
7826 RTX_FRAME_RELATED_P (tmp) = 1;
7827 XVECEXP (dwarf, 0, count - 1) = tmp;
7829 for (i = 1; i < count; i++)
7831 reg = gen_rtx_REG (XFmode, base_reg++);
7832 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg);
7834 tmp = gen_rtx_SET (VOIDmode,
7835 gen_rtx_MEM (XFmode,
7836 gen_rtx_PRE_DEC (BLKmode,
7837 stack_pointer_rtx)),
7839 RTX_FRAME_RELATED_P (tmp) = 1;
7840 XVECEXP (dwarf, 0, count - i - 1) = tmp;
7843 par = emit_insn (par);
7844 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
7849 /* Generate the prologue instructions for entry into an ARM function. */
7852 arm_expand_prologue ()
7858 unsigned long live_regs_mask;
7859 unsigned long func_type;
7862 func_type = arm_current_func_type ();
7864 /* Naked functions don't have prologues. */
7865 if (IS_NAKED (func_type))
7868 /* Compute which register we will have to save onto the stack. */
7869 live_regs_mask = arm_compute_save_reg_mask ();
7871 ip_rtx = gen_rtx_REG (SImode, IP_REGNUM);
7873 if (frame_pointer_needed)
7875 if (IS_INTERRUPT (func_type))
7877 /* Interrupt functions must not corrupt any registers.
7878 Creating a frame pointer however, corrupts the IP
7879 register, so we must push it first. */
7880 insn = emit_multi_reg_push (1 << IP_REGNUM);
7881 RTX_FRAME_RELATED_P (insn) = 1;
7883 else if (IS_NESTED (func_type))
7885 /* The Static chain register is the same as the IP register
7886 used as a scratch register during stack frame creation.
7887 To get around this need to find somewhere to store IP
7888 whilst the frame is being created. We try the following
7891 1. The last argument register.
7892 2. A slot on the stack above the frame. (This only
7893 works if the function is not a varargs function).
7895 If neither of these places is available, we abort (for now).
7897 Note - we only need to tell the dwarf2 backend about the SP
7898 adjustment in the second variant; the static chain register
7899 doesn't need to be unwound, as it doesn't contain a value
7900 inherited from the caller. */
7902 if (regs_ever_live[3] == 0)
7904 insn = gen_rtx_REG (SImode, 3);
7905 insn = gen_rtx_SET (SImode, insn, ip_rtx);
7906 insn = emit_insn (insn);
7908 else if (current_function_pretend_args_size == 0)
7911 insn = gen_rtx_PRE_DEC (SImode, stack_pointer_rtx);
7912 insn = gen_rtx_MEM (SImode, insn);
7913 insn = gen_rtx_SET (VOIDmode, insn, ip_rtx);
7914 insn = emit_insn (insn);
7918 /* Just tell the dwarf backend that we adjusted SP. */
7919 dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7920 gen_rtx_PLUS (SImode, stack_pointer_rtx,
7921 GEN_INT (-fp_offset)));
7922 RTX_FRAME_RELATED_P (insn) = 1;
7923 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
7924 dwarf, REG_NOTES (insn));
7927 /* FIXME - the way to handle this situation is to allow
7928 the pretend args to be dumped onto the stack, then
7929 reuse r3 to save IP. This would involve moving the
7930 copying of SP into IP until after the pretend args
7931 have been dumped, but this is not too hard. */
7932 /* [See e.g. gcc.c-torture/execute/nest-stdar-1.c.] */
7933 error ("Unable to find a temporary location for static chain register");
7938 insn = gen_rtx_PLUS (SImode, stack_pointer_rtx, GEN_INT (fp_offset));
7939 insn = gen_rtx_SET (SImode, ip_rtx, insn);
7942 insn = gen_movsi (ip_rtx, stack_pointer_rtx);
7944 insn = emit_insn (insn);
7945 RTX_FRAME_RELATED_P (insn) = 1;
7948 if (current_function_pretend_args_size)
7950 /* Push the argument registers, or reserve space for them. */
7951 if (current_function_anonymous_args)
7952 insn = emit_multi_reg_push
7953 ((0xf0 >> (current_function_pretend_args_size / 4)) & 0xf);
7956 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
7957 GEN_INT (-current_function_pretend_args_size)));
7958 RTX_FRAME_RELATED_P (insn) = 1;
7963 insn = emit_multi_reg_push (live_regs_mask);
7964 RTX_FRAME_RELATED_P (insn) = 1;
7967 if (! IS_VOLATILE (func_type))
7969 /* Save any floating point call-saved registers used by this function. */
7970 if (arm_fpu_arch == FP_SOFT2)
7972 for (reg = LAST_ARM_FP_REGNUM; reg >= FIRST_ARM_FP_REGNUM; reg --)
7973 if (regs_ever_live[reg] && !call_used_regs[reg])
7975 insn = gen_rtx_PRE_DEC (XFmode, stack_pointer_rtx);
7976 insn = gen_rtx_MEM (XFmode, insn);
7977 insn = emit_insn (gen_rtx_SET (VOIDmode, insn,
7978 gen_rtx_REG (XFmode, reg)));
7979 RTX_FRAME_RELATED_P (insn) = 1;
7984 int start_reg = LAST_ARM_FP_REGNUM;
7986 for (reg = LAST_ARM_FP_REGNUM; reg >= FIRST_ARM_FP_REGNUM; reg --)
7988 if (regs_ever_live[reg] && !call_used_regs[reg])
7990 if (start_reg - reg == 3)
7992 insn = emit_sfm (reg, 4);
7993 RTX_FRAME_RELATED_P (insn) = 1;
7994 start_reg = reg - 1;
7999 if (start_reg != reg)
8001 insn = emit_sfm (reg + 1, start_reg - reg);
8002 RTX_FRAME_RELATED_P (insn) = 1;
8004 start_reg = reg - 1;
8008 if (start_reg != reg)
8010 insn = emit_sfm (reg + 1, start_reg - reg);
8011 RTX_FRAME_RELATED_P (insn) = 1;
8016 if (frame_pointer_needed)
8018 /* Create the new frame pointer. */
8019 insn = GEN_INT (-(4 + current_function_pretend_args_size + fp_offset));
8020 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, ip_rtx, insn));
8021 RTX_FRAME_RELATED_P (insn) = 1;
8023 if (IS_NESTED (func_type))
8025 /* Recover the static chain register. */
8026 if (regs_ever_live [3] == 0)
8028 insn = gen_rtx_REG (SImode, 3);
8029 insn = gen_rtx_SET (SImode, ip_rtx, insn);
8030 insn = emit_insn (insn);
8032 else /* if (current_function_pretend_args_size == 0) */
8034 insn = gen_rtx_PLUS (SImode, hard_frame_pointer_rtx, GEN_INT (4));
8035 insn = gen_rtx_MEM (SImode, insn);
8036 insn = gen_rtx_SET (SImode, ip_rtx, insn);
8037 insn = emit_insn (insn);
8042 amount = GEN_INT (-(get_frame_size ()
8043 + current_function_outgoing_args_size));
8045 if (amount != const0_rtx)
8047 /* This add can produce multiple insns for a large constant, so we
8048 need to get tricky. */
8049 rtx last = get_last_insn ();
8050 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
8054 last = last ? NEXT_INSN (last) : get_insns ();
8055 RTX_FRAME_RELATED_P (last) = 1;
8057 while (last != insn);
8059 /* If the frame pointer is needed, emit a special barrier that
8060 will prevent the scheduler from moving stores to the frame
8061 before the stack adjustment. */
8062 if (frame_pointer_needed)
8064 rtx unspec = gen_rtx_UNSPEC (SImode,
8065 gen_rtvec (2, stack_pointer_rtx,
8066 hard_frame_pointer_rtx),
8069 insn = emit_insn (gen_rtx_CLOBBER (VOIDmode,
8070 gen_rtx_MEM (BLKmode, unspec)));
8074 /* If we are profiling, make sure no instructions are scheduled before
8075 the call to mcount. Similarly if the user has requested no
8076 scheduling in the prolog. */
8077 if (profile_flag || profile_block_flag || TARGET_NO_SCHED_PRO)
8078 emit_insn (gen_blockage ());
8080 /* If the link register is being kept alive, with the return address in it,
8081 then make sure that it does not get reused by the ce2 pass. */
8082 if ((live_regs_mask & (1 << LR_REGNUM)) == 0)
8084 emit_insn (gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, LR_REGNUM)));
8085 cfun->machine->lr_save_eliminated = 1;
8089 /* If CODE is 'd', then the X is a condition operand and the instruction
8090 should only be executed if the condition is true.
8091 if CODE is 'D', then the X is a condition operand and the instruction
8092 should only be executed if the condition is false: however, if the mode
8093 of the comparison is CCFPEmode, then always execute the instruction -- we
8094 do this because in these circumstances !GE does not necessarily imply LT;
8095 in these cases the instruction pattern will take care to make sure that
8096 an instruction containing %d will follow, thereby undoing the effects of
8097 doing this instruction unconditionally.
8098 If CODE is 'N' then X is a floating point operand that must be negated
8100 If CODE is 'B' then output a bitwise inverted value of X (a const int).
8101 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
8104 arm_print_operand (stream, x, code)
8112 fputs (ASM_COMMENT_START, stream);
8116 fputs (user_label_prefix, stream);
8120 fputs (REGISTER_PREFIX, stream);
8124 if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4)
8126 if (TARGET_THUMB || current_insn_predicate != NULL)
8129 fputs (arm_condition_codes[arm_current_cc], stream);
8131 else if (current_insn_predicate)
8133 enum arm_cond_code code;
8138 code = get_arm_condition_code (current_insn_predicate);
8139 fputs (arm_condition_codes[code], stream);
8146 REAL_VALUE_FROM_CONST_DOUBLE (r, x);
8147 r = REAL_VALUE_NEGATE (r);
8148 fprintf (stream, "%s", fp_const_from_val (&r));
8153 if (GET_CODE (x) == CONST_INT)
8156 val = ARM_SIGN_EXTEND (~INTVAL (x));
8157 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val);
8162 output_addr_const (stream, x);
8167 fprintf (stream, "%s", arithmetic_instr (x, 1));
8171 fprintf (stream, "%s", arithmetic_instr (x, 0));
8177 const char * shift = shift_op (x, &val);
8181 fprintf (stream, ", %s ", shift_op (x, &val));
8183 arm_print_operand (stream, XEXP (x, 1), 0);
8186 fputc ('#', stream);
8187 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val);
8193 /* An explanation of the 'Q', 'R' and 'H' register operands:
8195 In a pair of registers containing a DI or DF value the 'Q'
8196 operand returns the register number of the register containing
8197 the least signficant part of the value. The 'R' operand returns
8198 the register number of the register containing the most
8199 significant part of the value.
8201 The 'H' operand returns the higher of the two register numbers.
8202 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
8203 same as the 'Q' operand, since the most signficant part of the
8204 value is held in the lower number register. The reverse is true
8205 on systems where WORDS_BIG_ENDIAN is false.
8207 The purpose of these operands is to distinguish between cases
8208 where the endian-ness of the values is important (for example
8209 when they are added together), and cases where the endian-ness
8210 is irrelevant, but the order of register operations is important.
8211 For example when loading a value from memory into a register
8212 pair, the endian-ness does not matter. Provided that the value
8213 from the lower memory address is put into the lower numbered
8214 register, and the value from the higher address is put into the
8215 higher numbered register, the load will work regardless of whether
8216 the value being loaded is big-wordian or little-wordian. The
8217 order of the two register loads can matter however, if the address
8218 of the memory location is actually held in one of the registers
8219 being overwritten by the load. */
8221 if (REGNO (x) > LAST_ARM_REGNUM)
8223 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0));
8227 if (REGNO (x) > LAST_ARM_REGNUM)
8229 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1));
8233 if (REGNO (x) > LAST_ARM_REGNUM)
8235 asm_fprintf (stream, "%r", REGNO (x) + 1);
8239 asm_fprintf (stream, "%r",
8240 GET_CODE (XEXP (x, 0)) == REG
8241 ? REGNO (XEXP (x, 0)) : REGNO (XEXP (XEXP (x, 0), 0)));
8245 asm_fprintf (stream, "{%r-%r}",
8247 REGNO (x) + NUM_REGS (GET_MODE (x)) - 1);
8255 fputs (arm_condition_codes[get_arm_condition_code (x)],
8258 fputs (thumb_condition_code (x, 0), stream);
8266 fputs (arm_condition_codes[ARM_INVERSE_CONDITION_CODE
8267 (get_arm_condition_code (x))],
8270 fputs (thumb_condition_code (x, 1), stream);
8277 if (GET_CODE (x) == REG)
8278 asm_fprintf (stream, "%r", REGNO (x));
8279 else if (GET_CODE (x) == MEM)
8281 output_memory_reference_mode = GET_MODE (x);
8282 output_address (XEXP (x, 0));
8284 else if (GET_CODE (x) == CONST_DOUBLE)
8285 fprintf (stream, "#%s", fp_immediate_constant (x));
8286 else if (GET_CODE (x) == NEG)
8287 abort (); /* This should never happen now. */
8290 fputc ('#', stream);
8291 output_addr_const (stream, x);
8296 /* A finite state machine takes care of noticing whether or not instructions
8297 can be conditionally executed, and thus decrease execution time and code
8298 size by deleting branch instructions. The fsm is controlled by
8299 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
8301 /* The state of the fsm controlling condition codes are:
8302 0: normal, do nothing special
8303 1: make ASM_OUTPUT_OPCODE not output this instruction
8304 2: make ASM_OUTPUT_OPCODE not output this instruction
8305 3: make instructions conditional
8306 4: make instructions conditional
8308 State transitions (state->state by whom under condition):
8309 0 -> 1 final_prescan_insn if the `target' is a label
8310 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
8311 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
8312 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
8313 3 -> 0 ASM_OUTPUT_INTERNAL_LABEL if the `target' label is reached
8314 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
8315 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
8316 (the target insn is arm_target_insn).
8318 If the jump clobbers the conditions then we use states 2 and 4.
8320 A similar thing can be done with conditional return insns.
8322 XXX In case the `target' is an unconditional branch, this conditionalising
8323 of the instructions always reduces code size, but not always execution
8324 time. But then, I want to reduce the code size to somewhere near what
8325 /bin/cc produces. */
8327 /* Returns the index of the ARM condition code string in
8328 `arm_condition_codes'. COMPARISON should be an rtx like
8329 `(eq (...) (...))'. */
8331 static enum arm_cond_code
8332 get_arm_condition_code (comparison)
8335 enum machine_mode mode = GET_MODE (XEXP (comparison, 0));
8337 register enum rtx_code comp_code = GET_CODE (comparison);
8339 if (GET_MODE_CLASS (mode) != MODE_CC)
8340 mode = SELECT_CC_MODE (comp_code, XEXP (comparison, 0),
8341 XEXP (comparison, 1));
8345 case CC_DNEmode: code = ARM_NE; goto dominance;
8346 case CC_DEQmode: code = ARM_EQ; goto dominance;
8347 case CC_DGEmode: code = ARM_GE; goto dominance;
8348 case CC_DGTmode: code = ARM_GT; goto dominance;
8349 case CC_DLEmode: code = ARM_LE; goto dominance;
8350 case CC_DLTmode: code = ARM_LT; goto dominance;
8351 case CC_DGEUmode: code = ARM_CS; goto dominance;
8352 case CC_DGTUmode: code = ARM_HI; goto dominance;
8353 case CC_DLEUmode: code = ARM_LS; goto dominance;
8354 case CC_DLTUmode: code = ARM_CC;
8357 if (comp_code != EQ && comp_code != NE)
8360 if (comp_code == EQ)
8361 return ARM_INVERSE_CONDITION_CODE (code);
8367 case NE: return ARM_NE;
8368 case EQ: return ARM_EQ;
8369 case GE: return ARM_PL;
8370 case LT: return ARM_MI;
8377 case NE: return ARM_NE;
8378 case EQ: return ARM_EQ;
8384 /* These encodings assume that AC=1 in the FPA system control
8385 byte. This allows us to handle all cases except UNEQ and
8389 case GE: return ARM_GE;
8390 case GT: return ARM_GT;
8391 case LE: return ARM_LS;
8392 case LT: return ARM_MI;
8393 case NE: return ARM_NE;
8394 case EQ: return ARM_EQ;
8395 case ORDERED: return ARM_VC;
8396 case UNORDERED: return ARM_VS;
8397 case UNLT: return ARM_LT;
8398 case UNLE: return ARM_LE;
8399 case UNGT: return ARM_HI;
8400 case UNGE: return ARM_PL;
8401 /* UNEQ and LTGT do not have a representation. */
8402 case UNEQ: /* Fall through. */
8403 case LTGT: /* Fall through. */
8410 case NE: return ARM_NE;
8411 case EQ: return ARM_EQ;
8412 case GE: return ARM_LE;
8413 case GT: return ARM_LT;
8414 case LE: return ARM_GE;
8415 case LT: return ARM_GT;
8416 case GEU: return ARM_LS;
8417 case GTU: return ARM_CC;
8418 case LEU: return ARM_CS;
8419 case LTU: return ARM_HI;
8426 case LTU: return ARM_CS;
8427 case GEU: return ARM_CC;
8434 case NE: return ARM_NE;
8435 case EQ: return ARM_EQ;
8436 case GE: return ARM_GE;
8437 case GT: return ARM_GT;
8438 case LE: return ARM_LE;
8439 case LT: return ARM_LT;
8440 case GEU: return ARM_CS;
8441 case GTU: return ARM_HI;
8442 case LEU: return ARM_LS;
8443 case LTU: return ARM_CC;
8455 arm_final_prescan_insn (insn)
8458 /* BODY will hold the body of INSN. */
8459 register rtx body = PATTERN (insn);
8461 /* This will be 1 if trying to repeat the trick, and things need to be
8462 reversed if it appears to fail. */
8465 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
8466 taken are clobbered, even if the rtl suggests otherwise. It also
8467 means that we have to grub around within the jump expression to find
8468 out what the conditions are when the jump isn't taken. */
8469 int jump_clobbers = 0;
8471 /* If we start with a return insn, we only succeed if we find another one. */
8472 int seeking_return = 0;
8474 /* START_INSN will hold the insn from where we start looking. This is the
8475 first insn after the following code_label if REVERSE is true. */
8476 rtx start_insn = insn;
8478 /* If in state 4, check if the target branch is reached, in order to
8479 change back to state 0. */
8480 if (arm_ccfsm_state == 4)
8482 if (insn == arm_target_insn)
8484 arm_target_insn = NULL;
8485 arm_ccfsm_state = 0;
8490 /* If in state 3, it is possible to repeat the trick, if this insn is an
8491 unconditional branch to a label, and immediately following this branch
8492 is the previous target label which is only used once, and the label this
8493 branch jumps to is not too far off. */
8494 if (arm_ccfsm_state == 3)
8496 if (simplejump_p (insn))
8498 start_insn = next_nonnote_insn (start_insn);
8499 if (GET_CODE (start_insn) == BARRIER)
8501 /* XXX Isn't this always a barrier? */
8502 start_insn = next_nonnote_insn (start_insn);
8504 if (GET_CODE (start_insn) == CODE_LABEL
8505 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
8506 && LABEL_NUSES (start_insn) == 1)
8511 else if (GET_CODE (body) == RETURN)
8513 start_insn = next_nonnote_insn (start_insn);
8514 if (GET_CODE (start_insn) == BARRIER)
8515 start_insn = next_nonnote_insn (start_insn);
8516 if (GET_CODE (start_insn) == CODE_LABEL
8517 && CODE_LABEL_NUMBER (start_insn) == arm_target_label
8518 && LABEL_NUSES (start_insn) == 1)
8530 if (arm_ccfsm_state != 0 && !reverse)
8532 if (GET_CODE (insn) != JUMP_INSN)
8535 /* This jump might be paralleled with a clobber of the condition codes
8536 the jump should always come first */
8537 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
8538 body = XVECEXP (body, 0, 0);
8541 /* If this is a conditional return then we don't want to know */
8542 if (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
8543 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE
8544 && (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN
8545 || GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN))
8550 || (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
8551 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE))
8554 int fail = FALSE, succeed = FALSE;
8555 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
8556 int then_not_else = TRUE;
8557 rtx this_insn = start_insn, label = 0;
8559 /* If the jump cannot be done with one instruction, we cannot
8560 conditionally execute the instruction in the inverse case. */
8561 if (get_attr_conds (insn) == CONDS_JUMP_CLOB)
8567 /* Register the insn jumped to. */
8570 if (!seeking_return)
8571 label = XEXP (SET_SRC (body), 0);
8573 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == LABEL_REF)
8574 label = XEXP (XEXP (SET_SRC (body), 1), 0);
8575 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == LABEL_REF)
8577 label = XEXP (XEXP (SET_SRC (body), 2), 0);
8578 then_not_else = FALSE;
8580 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN)
8582 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN)
8585 then_not_else = FALSE;
8590 /* See how many insns this branch skips, and what kind of insns. If all
8591 insns are okay, and the label or unconditional branch to the same
8592 label is not too far away, succeed. */
8593 for (insns_skipped = 0;
8594 !fail && !succeed && insns_skipped++ < max_insns_skipped;)
8598 this_insn = next_nonnote_insn (this_insn);
8602 switch (GET_CODE (this_insn))
8605 /* Succeed if it is the target label, otherwise fail since
8606 control falls in from somewhere else. */
8607 if (this_insn == label)
8611 arm_ccfsm_state = 2;
8612 this_insn = next_nonnote_insn (this_insn);
8615 arm_ccfsm_state = 1;
8623 /* Succeed if the following insn is the target label.
8625 If return insns are used then the last insn in a function
8626 will be a barrier. */
8627 this_insn = next_nonnote_insn (this_insn);
8628 if (this_insn && this_insn == label)
8632 arm_ccfsm_state = 2;
8633 this_insn = next_nonnote_insn (this_insn);
8636 arm_ccfsm_state = 1;
8644 /* If using 32-bit addresses the cc is not preserved over
8648 /* Succeed if the following insn is the target label,
8649 or if the following two insns are a barrier and
8650 the target label. */
8651 this_insn = next_nonnote_insn (this_insn);
8652 if (this_insn && GET_CODE (this_insn) == BARRIER)
8653 this_insn = next_nonnote_insn (this_insn);
8655 if (this_insn && this_insn == label
8656 && insns_skipped < max_insns_skipped)
8660 arm_ccfsm_state = 2;
8661 this_insn = next_nonnote_insn (this_insn);
8664 arm_ccfsm_state = 1;
8673 /* If this is an unconditional branch to the same label, succeed.
8674 If it is to another label, do nothing. If it is conditional,
8676 /* XXX Probably, the tests for SET and the PC are unnecessary. */
8678 scanbody = PATTERN (this_insn);
8679 if (GET_CODE (scanbody) == SET
8680 && GET_CODE (SET_DEST (scanbody)) == PC)
8682 if (GET_CODE (SET_SRC (scanbody)) == LABEL_REF
8683 && XEXP (SET_SRC (scanbody), 0) == label && !reverse)
8685 arm_ccfsm_state = 2;
8688 else if (GET_CODE (SET_SRC (scanbody)) == IF_THEN_ELSE)
8691 /* Fail if a conditional return is undesirable (eg on a
8692 StrongARM), but still allow this if optimizing for size. */
8693 else if (GET_CODE (scanbody) == RETURN
8694 && !use_return_insn (TRUE)
8697 else if (GET_CODE (scanbody) == RETURN
8700 arm_ccfsm_state = 2;
8703 else if (GET_CODE (scanbody) == PARALLEL)
8705 switch (get_attr_conds (this_insn))
8715 fail = TRUE; /* Unrecognized jump (eg epilogue). */
8720 /* Instructions using or affecting the condition codes make it
8722 scanbody = PATTERN (this_insn);
8723 if (!(GET_CODE (scanbody) == SET
8724 || GET_CODE (scanbody) == PARALLEL)
8725 || get_attr_conds (this_insn) != CONDS_NOCOND)
8735 if ((!seeking_return) && (arm_ccfsm_state == 1 || reverse))
8736 arm_target_label = CODE_LABEL_NUMBER (label);
8737 else if (seeking_return || arm_ccfsm_state == 2)
8739 while (this_insn && GET_CODE (PATTERN (this_insn)) == USE)
8741 this_insn = next_nonnote_insn (this_insn);
8742 if (this_insn && (GET_CODE (this_insn) == BARRIER
8743 || GET_CODE (this_insn) == CODE_LABEL))
8748 /* Oh, dear! we ran off the end.. give up */
8749 recog (PATTERN (insn), insn, NULL);
8750 arm_ccfsm_state = 0;
8751 arm_target_insn = NULL;
8754 arm_target_insn = this_insn;
8763 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body),
8765 if (GET_CODE (XEXP (XEXP (SET_SRC (body), 0), 0)) == AND)
8766 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
8767 if (GET_CODE (XEXP (SET_SRC (body), 0)) == NE)
8768 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
8772 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
8775 arm_current_cc = get_arm_condition_code (XEXP (SET_SRC (body),
8779 if (reverse || then_not_else)
8780 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc);
8783 /* Restore recog_data (getting the attributes of other insns can
8784 destroy this array, but final.c assumes that it remains intact
8785 across this call; since the insn has been recognized already we
8786 call recog direct). */
8787 recog (PATTERN (insn), insn, NULL);
8792 arm_regno_class (regno)
8797 if (regno == STACK_POINTER_REGNUM)
8799 if (regno == CC_REGNUM)
8806 if ( regno <= LAST_ARM_REGNUM
8807 || regno == FRAME_POINTER_REGNUM
8808 || regno == ARG_POINTER_REGNUM)
8809 return GENERAL_REGS;
8811 if (regno == CC_REGNUM)
8817 /* Handle a special case when computing the offset
8818 of an argument from the frame pointer. */
8820 arm_debugger_arg_offset (value, addr)
8826 /* We are only interested if dbxout_parms() failed to compute the offset. */
8830 /* We can only cope with the case where the address is held in a register. */
8831 if (GET_CODE (addr) != REG)
8834 /* If we are using the frame pointer to point at the argument, then
8835 an offset of 0 is correct. */
8836 if (REGNO (addr) == (unsigned) HARD_FRAME_POINTER_REGNUM)
8839 /* If we are using the stack pointer to point at the
8840 argument, then an offset of 0 is correct. */
8841 if ((TARGET_THUMB || !frame_pointer_needed)
8842 && REGNO (addr) == SP_REGNUM)
8845 /* Oh dear. The argument is pointed to by a register rather
8846 than being held in a register, or being stored at a known
8847 offset from the frame pointer. Since GDB only understands
8848 those two kinds of argument we must translate the address
8849 held in the register into an offset from the frame pointer.
8850 We do this by searching through the insns for the function
8851 looking to see where this register gets its value. If the
8852 register is initialised from the frame pointer plus an offset
8853 then we are in luck and we can continue, otherwise we give up.
8855 This code is exercised by producing debugging information
8856 for a function with arguments like this:
8858 double func (double a, double b, int c, double d) {return d;}
8860 Without this code the stab for parameter 'd' will be set to
8861 an offset of 0 from the frame pointer, rather than 8. */
8863 /* The if() statement says:
8865 If the insn is a normal instruction
8866 and if the insn is setting the value in a register
8867 and if the register being set is the register holding the address of the argument
8868 and if the address is computing by an addition
8869 that involves adding to a register
8870 which is the frame pointer
8875 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8877 if ( GET_CODE (insn) == INSN
8878 && GET_CODE (PATTERN (insn)) == SET
8879 && REGNO (XEXP (PATTERN (insn), 0)) == REGNO (addr)
8880 && GET_CODE (XEXP (PATTERN (insn), 1)) == PLUS
8881 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 0)) == REG
8882 && REGNO (XEXP (XEXP (PATTERN (insn), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
8883 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 1)) == CONST_INT
8886 value = INTVAL (XEXP (XEXP (PATTERN (insn), 1), 1));
8895 warning ("Unable to compute real location of stacked parameter");
8896 value = 8; /* XXX magic hack */
8902 #define def_builtin(NAME, TYPE, CODE) \
8903 builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, NULL)
8906 arm_init_builtins ()
8908 tree endlink = void_list_node;
8909 tree int_endlink = tree_cons (NULL_TREE, integer_type_node, endlink);
8910 tree pchar_type_node = build_pointer_type (char_type_node);
8912 tree int_ftype_int, void_ftype_pchar;
8914 /* void func (void *) */
8916 = build_function_type (void_type_node,
8917 tree_cons (NULL_TREE, pchar_type_node, endlink));
8919 /* int func (int) */
8921 = build_function_type (integer_type_node, int_endlink);
8923 /* Initialize arm V5 builtins. */
8925 def_builtin ("__builtin_clz", int_ftype_int, ARM_BUILTIN_CLZ);
8927 /* Initialize arm V5E builtins. */
8929 def_builtin ("__builtin_prefetch", void_ftype_pchar,
8930 ARM_BUILTIN_PREFETCH);
8933 /* Expand an expression EXP that calls a built-in function,
8934 with result going to TARGET if that's convenient
8935 (and in mode MODE if that's convenient).
8936 SUBTARGET may be used as the target for computing one of EXP's operands.
8937 IGNORE is nonzero if the value is to be ignored. */
8940 arm_expand_builtin (exp, target, subtarget, mode, ignore)
8943 rtx subtarget ATTRIBUTE_UNUSED;
8944 enum machine_mode mode ATTRIBUTE_UNUSED;
8945 int ignore ATTRIBUTE_UNUSED;
8947 enum insn_code icode;
8948 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
8949 tree arglist = TREE_OPERAND (exp, 1);
8952 enum machine_mode tmode, mode0;
8953 int fcode = DECL_FUNCTION_CODE (fndecl);
8960 case ARM_BUILTIN_CLZ:
8961 icode = CODE_FOR_clz;
8962 arg0 = TREE_VALUE (arglist);
8963 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
8964 tmode = insn_data[icode].operand[0].mode;
8965 mode0 = insn_data[icode].operand[1].mode;
8967 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
8968 op0 = copy_to_mode_reg (mode0, op0);
8970 || GET_MODE (target) != tmode
8971 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
8972 target = gen_reg_rtx (tmode);
8973 pat = GEN_FCN (icode) (target, op0);
8979 case ARM_BUILTIN_PREFETCH:
8980 icode = CODE_FOR_prefetch;
8981 arg0 = TREE_VALUE (arglist);
8982 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
8984 op0 = gen_rtx_MEM (SImode, copy_to_mode_reg (Pmode, op0));
8986 pat = GEN_FCN (icode) (op0);
8993 /* @@@ Should really do something sensible here. */
8997 /* Recursively search through all of the blocks in a function
8998 checking to see if any of the variables created in that
8999 function match the RTX called 'orig'. If they do then
9000 replace them with the RTX called 'new'. */
9003 replace_symbols_in_block (block, orig, new)
9008 for (; block; block = BLOCK_CHAIN (block))
9012 if (!TREE_USED (block))
9015 for (sym = BLOCK_VARS (block); sym; sym = TREE_CHAIN (sym))
9017 if ( (DECL_NAME (sym) == 0 && TREE_CODE (sym) != TYPE_DECL)
9018 || DECL_IGNORED_P (sym)
9019 || TREE_CODE (sym) != VAR_DECL
9020 || DECL_EXTERNAL (sym)
9021 || !rtx_equal_p (DECL_RTL (sym), orig)
9025 SET_DECL_RTL (sym, new);
9028 replace_symbols_in_block (BLOCK_SUBBLOCKS (block), orig, new);
9032 /* Return the number (counting from 0) of the least significant set
9038 number_of_first_bit_set (mask)
9044 (mask & (1 << bit)) == 0;
9051 /* Generate code to return from a thumb function.
9052 If 'reg_containing_return_addr' is -1, then the return address is
9053 actually on the stack, at the stack pointer. */
9055 thumb_exit (f, reg_containing_return_addr, eh_ofs)
9057 int reg_containing_return_addr;
9060 unsigned regs_available_for_popping;
9061 unsigned regs_to_pop;
9067 int restore_a4 = FALSE;
9069 /* Compute the registers we need to pop. */
9073 /* There is an assumption here, that if eh_ofs is not NULL, the
9074 normal return address will have been pushed. */
9075 if (reg_containing_return_addr == -1 || eh_ofs)
9077 /* When we are generating a return for __builtin_eh_return,
9078 reg_containing_return_addr must specify the return regno. */
9079 if (eh_ofs && reg_containing_return_addr == -1)
9082 regs_to_pop |= 1 << LR_REGNUM;
9086 if (TARGET_BACKTRACE)
9088 /* Restore the (ARM) frame pointer and stack pointer. */
9089 regs_to_pop |= (1 << ARM_HARD_FRAME_POINTER_REGNUM) | (1 << SP_REGNUM);
9093 /* If there is nothing to pop then just emit the BX instruction and
9095 if (pops_needed == 0)
9098 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs));
9100 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
9103 /* Otherwise if we are not supporting interworking and we have not created
9104 a backtrace structure and the function was not entered in ARM mode then
9105 just pop the return address straight into the PC. */
9106 else if (!TARGET_INTERWORK
9107 && !TARGET_BACKTRACE
9108 && !is_called_in_ARM_mode (current_function_decl))
9112 asm_fprintf (f, "\tadd\t%r, #4\n", SP_REGNUM);
9113 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs));
9114 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
9117 asm_fprintf (f, "\tpop\t{%r}\n", PC_REGNUM);
9122 /* Find out how many of the (return) argument registers we can corrupt. */
9123 regs_available_for_popping = 0;
9125 /* If returning via __builtin_eh_return, the bottom three registers
9126 all contain information needed for the return. */
9132 /* If we can deduce the registers used from the function's
9133 return value. This is more reliable that examining
9134 regs_ever_live[] because that will be set if the register is
9135 ever used in the function, not just if the register is used
9136 to hold a return value. */
9138 if (current_function_return_rtx != 0)
9139 mode = GET_MODE (current_function_return_rtx);
9142 mode = DECL_MODE (DECL_RESULT (current_function_decl));
9144 size = GET_MODE_SIZE (mode);
9148 /* In a void function we can use any argument register.
9149 In a function that returns a structure on the stack
9150 we can use the second and third argument registers. */
9151 if (mode == VOIDmode)
9152 regs_available_for_popping =
9153 (1 << ARG_REGISTER (1))
9154 | (1 << ARG_REGISTER (2))
9155 | (1 << ARG_REGISTER (3));
9157 regs_available_for_popping =
9158 (1 << ARG_REGISTER (2))
9159 | (1 << ARG_REGISTER (3));
9162 regs_available_for_popping =
9163 (1 << ARG_REGISTER (2))
9164 | (1 << ARG_REGISTER (3));
9166 regs_available_for_popping =
9167 (1 << ARG_REGISTER (3));
9170 /* Match registers to be popped with registers into which we pop them. */
9171 for (available = regs_available_for_popping,
9172 required = regs_to_pop;
9173 required != 0 && available != 0;
9174 available &= ~(available & - available),
9175 required &= ~(required & - required))
9178 /* If we have any popping registers left over, remove them. */
9180 regs_available_for_popping &= ~available;
9182 /* Otherwise if we need another popping register we can use
9183 the fourth argument register. */
9184 else if (pops_needed)
9186 /* If we have not found any free argument registers and
9187 reg a4 contains the return address, we must move it. */
9188 if (regs_available_for_popping == 0
9189 && reg_containing_return_addr == LAST_ARG_REGNUM)
9191 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
9192 reg_containing_return_addr = LR_REGNUM;
9196 /* Register a4 is being used to hold part of the return value,
9197 but we have dire need of a free, low register. */
9200 asm_fprintf (f, "\tmov\t%r, %r\n",IP_REGNUM, LAST_ARG_REGNUM);
9203 if (reg_containing_return_addr != LAST_ARG_REGNUM)
9205 /* The fourth argument register is available. */
9206 regs_available_for_popping |= 1 << LAST_ARG_REGNUM;
9212 /* Pop as many registers as we can. */
9213 thumb_pushpop (f, regs_available_for_popping, FALSE);
9215 /* Process the registers we popped. */
9216 if (reg_containing_return_addr == -1)
9218 /* The return address was popped into the lowest numbered register. */
9219 regs_to_pop &= ~(1 << LR_REGNUM);
9221 reg_containing_return_addr =
9222 number_of_first_bit_set (regs_available_for_popping);
9224 /* Remove this register for the mask of available registers, so that
9225 the return address will not be corrupted by futher pops. */
9226 regs_available_for_popping &= ~(1 << reg_containing_return_addr);
9229 /* If we popped other registers then handle them here. */
9230 if (regs_available_for_popping)
9234 /* Work out which register currently contains the frame pointer. */
9235 frame_pointer = number_of_first_bit_set (regs_available_for_popping);
9237 /* Move it into the correct place. */
9238 asm_fprintf (f, "\tmov\t%r, %r\n",
9239 ARM_HARD_FRAME_POINTER_REGNUM, frame_pointer);
9241 /* (Temporarily) remove it from the mask of popped registers. */
9242 regs_available_for_popping &= ~(1 << frame_pointer);
9243 regs_to_pop &= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM);
9245 if (regs_available_for_popping)
9249 /* We popped the stack pointer as well,
9250 find the register that contains it. */
9251 stack_pointer = number_of_first_bit_set (regs_available_for_popping);
9253 /* Move it into the stack register. */
9254 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, stack_pointer);
9256 /* At this point we have popped all necessary registers, so
9257 do not worry about restoring regs_available_for_popping
9258 to its correct value:
9260 assert (pops_needed == 0)
9261 assert (regs_available_for_popping == (1 << frame_pointer))
9262 assert (regs_to_pop == (1 << STACK_POINTER)) */
9266 /* Since we have just move the popped value into the frame
9267 pointer, the popping register is available for reuse, and
9268 we know that we still have the stack pointer left to pop. */
9269 regs_available_for_popping |= (1 << frame_pointer);
9273 /* If we still have registers left on the stack, but we no longer have
9274 any registers into which we can pop them, then we must move the return
9275 address into the link register and make available the register that
9277 if (regs_available_for_popping == 0 && pops_needed > 0)
9279 regs_available_for_popping |= 1 << reg_containing_return_addr;
9281 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM,
9282 reg_containing_return_addr);
9284 reg_containing_return_addr = LR_REGNUM;
9287 /* If we have registers left on the stack then pop some more.
9288 We know that at most we will want to pop FP and SP. */
9289 if (pops_needed > 0)
9294 thumb_pushpop (f, regs_available_for_popping, FALSE);
9296 /* We have popped either FP or SP.
9297 Move whichever one it is into the correct register. */
9298 popped_into = number_of_first_bit_set (regs_available_for_popping);
9299 move_to = number_of_first_bit_set (regs_to_pop);
9301 asm_fprintf (f, "\tmov\t%r, %r\n", move_to, popped_into);
9303 regs_to_pop &= ~(1 << move_to);
9308 /* If we still have not popped everything then we must have only
9309 had one register available to us and we are now popping the SP. */
9310 if (pops_needed > 0)
9314 thumb_pushpop (f, regs_available_for_popping, FALSE);
9316 popped_into = number_of_first_bit_set (regs_available_for_popping);
9318 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, popped_into);
9320 assert (regs_to_pop == (1 << STACK_POINTER))
9321 assert (pops_needed == 1)
9325 /* If necessary restore the a4 register. */
9328 if (reg_containing_return_addr != LR_REGNUM)
9330 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM);
9331 reg_containing_return_addr = LR_REGNUM;
9334 asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM);
9338 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs));
9340 /* Return to caller. */
9341 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr);
9344 /* Emit code to push or pop registers to or from the stack. */
9346 thumb_pushpop (f, mask, push)
9352 int lo_mask = mask & 0xFF;
9354 if (lo_mask == 0 && !push && (mask & (1 << 15)))
9356 /* Special case. Do not generate a POP PC statement here, do it in
9358 thumb_exit (f, -1, NULL_RTX);
9362 fprintf (f, "\t%s\t{", push ? "push" : "pop");
9364 /* Look at the low registers first. */
9365 for (regno = 0; regno <= LAST_LO_REGNUM; regno++, lo_mask >>= 1)
9369 asm_fprintf (f, "%r", regno);
9371 if ((lo_mask & ~1) != 0)
9376 if (push && (mask & (1 << LR_REGNUM)))
9378 /* Catch pushing the LR. */
9382 asm_fprintf (f, "%r", LR_REGNUM);
9384 else if (!push && (mask & (1 << PC_REGNUM)))
9386 /* Catch popping the PC. */
9387 if (TARGET_INTERWORK || TARGET_BACKTRACE)
9389 /* The PC is never poped directly, instead
9390 it is popped into r3 and then BX is used. */
9393 thumb_exit (f, -1, NULL_RTX);
9402 asm_fprintf (f, "%r", PC_REGNUM);
9410 thumb_final_prescan_insn (insn)
9413 if (flag_print_asm_name)
9414 asm_fprintf (asm_out_file, "%@ 0x%04x\n",
9415 INSN_ADDRESSES (INSN_UID (insn)));
9419 thumb_shiftable_const (val)
9420 unsigned HOST_WIDE_INT val;
9422 unsigned HOST_WIDE_INT mask = 0xff;
9425 if (val == 0) /* XXX */
9428 for (i = 0; i < 25; i++)
9429 if ((val & (mask << i)) == val)
9435 /* Returns non-zero if the current function contains,
9436 or might contain a far jump. */
9438 thumb_far_jump_used_p (int in_prologue)
9442 /* This test is only important for leaf functions. */
9443 /* assert (!leaf_function_p ()); */
9445 /* If we have already decided that far jumps may be used,
9446 do not bother checking again, and always return true even if
9447 it turns out that they are not being used. Once we have made
9448 the decision that far jumps are present (and that hence the link
9449 register will be pushed onto the stack) we cannot go back on it. */
9450 if (cfun->machine->far_jump_used)
9453 /* If this function is not being called from the prologue/epilogue
9454 generation code then it must be being called from the
9455 INITIAL_ELIMINATION_OFFSET macro. */
9458 /* In this case we know that we are being asked about the elimination
9459 of the arg pointer register. If that register is not being used,
9460 then there are no arguments on the stack, and we do not have to
9461 worry that a far jump might force the prologue to push the link
9462 register, changing the stack offsets. In this case we can just
9463 return false, since the presence of far jumps in the function will
9464 not affect stack offsets.
9466 If the arg pointer is live (or if it was live, but has now been
9467 eliminated and so set to dead) then we do have to test to see if
9468 the function might contain a far jump. This test can lead to some
9469 false negatives, since before reload is completed, then length of
9470 branch instructions is not known, so gcc defaults to returning their
9471 longest length, which in turn sets the far jump attribute to true.
9473 A false negative will not result in bad code being generated, but it
9474 will result in a needless push and pop of the link register. We
9475 hope that this does not occur too often. */
9476 if (regs_ever_live [ARG_POINTER_REGNUM])
9477 cfun->machine->arg_pointer_live = 1;
9478 else if (!cfun->machine->arg_pointer_live)
9482 /* Check to see if the function contains a branch
9483 insn with the far jump attribute set. */
9484 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
9486 if (GET_CODE (insn) == JUMP_INSN
9487 /* Ignore tablejump patterns. */
9488 && GET_CODE (PATTERN (insn)) != ADDR_VEC
9489 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC
9490 && get_attr_far_jump (insn) == FAR_JUMP_YES
9493 /* Record the fact that we have decied that
9494 the function does use far jumps. */
9495 cfun->machine->far_jump_used = 1;
9503 /* Return non-zero if FUNC must be entered in ARM mode. */
9505 is_called_in_ARM_mode (func)
9508 if (TREE_CODE (func) != FUNCTION_DECL)
9511 /* Ignore the problem about functions whoes address is taken. */
9512 if (TARGET_CALLEE_INTERWORKING && TREE_PUBLIC (func))
9516 return lookup_attribute ("interfacearm", DECL_MACHINE_ATTRIBUTES (func)) != NULL_TREE;
9522 /* The bits which aren't usefully expanded as rtl. */
9525 thumb_unexpanded_epilogue ()
9528 int live_regs_mask = 0;
9529 int high_regs_pushed = 0;
9530 int leaf_function = leaf_function_p ();
9532 rtx eh_ofs = cfun->machine->eh_epilogue_sp_ofs;
9534 if (return_used_this_function)
9537 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
9538 if (regs_ever_live[regno] && !call_used_regs[regno]
9539 && !(TARGET_SINGLE_PIC_BASE && (regno == arm_pic_register)))
9540 live_regs_mask |= 1 << regno;
9542 for (regno = 8; regno < 13; regno++)
9544 if (regs_ever_live[regno] && !call_used_regs[regno]
9545 && !(TARGET_SINGLE_PIC_BASE && (regno == arm_pic_register)))
9549 /* The prolog may have pushed some high registers to use as
9550 work registers. eg the testuite file:
9551 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
9552 compiles to produce:
9553 push {r4, r5, r6, r7, lr}
9557 as part of the prolog. We have to undo that pushing here. */
9559 if (high_regs_pushed)
9561 int mask = live_regs_mask;
9567 /* If we can deduce the registers used from the function's return value.
9568 This is more reliable that examining regs_ever_live[] because that
9569 will be set if the register is ever used in the function, not just if
9570 the register is used to hold a return value. */
9572 if (current_function_return_rtx != 0)
9573 mode = GET_MODE (current_function_return_rtx);
9576 mode = DECL_MODE (DECL_RESULT (current_function_decl));
9578 size = GET_MODE_SIZE (mode);
9580 /* Unless we are returning a type of size > 12 register r3 is
9586 /* Oh dear! We have no low registers into which we can pop
9589 ("no low registers available for popping high registers");
9591 for (next_hi_reg = 8; next_hi_reg < 13; next_hi_reg++)
9592 if (regs_ever_live[next_hi_reg] && !call_used_regs[next_hi_reg]
9593 && !(TARGET_SINGLE_PIC_BASE && (next_hi_reg == arm_pic_register)))
9596 while (high_regs_pushed)
9598 /* Find lo register(s) into which the high register(s) can
9600 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
9602 if (mask & (1 << regno))
9604 if (high_regs_pushed == 0)
9608 mask &= (2 << regno) - 1; /* A noop if regno == 8 */
9610 /* Pop the values into the low register(s). */
9611 thumb_pushpop (asm_out_file, mask, 0);
9613 /* Move the value(s) into the high registers. */
9614 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
9616 if (mask & (1 << regno))
9618 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", next_hi_reg,
9621 for (next_hi_reg++; next_hi_reg < 13; next_hi_reg++)
9622 if (regs_ever_live[next_hi_reg]
9623 && !call_used_regs[next_hi_reg]
9624 && !(TARGET_SINGLE_PIC_BASE
9625 && (next_hi_reg == arm_pic_register)))
9632 had_to_push_lr = (live_regs_mask || !leaf_function
9633 || thumb_far_jump_used_p (1));
9635 if (TARGET_BACKTRACE
9636 && ((live_regs_mask & 0xFF) == 0)
9637 && regs_ever_live [LAST_ARG_REGNUM] != 0)
9639 /* The stack backtrace structure creation code had to
9640 push R7 in order to get a work register, so we pop
9642 live_regs_mask |= (1 << LAST_LO_REGNUM);
9645 if (current_function_pretend_args_size == 0 || TARGET_BACKTRACE)
9648 && !is_called_in_ARM_mode (current_function_decl)
9650 live_regs_mask |= 1 << PC_REGNUM;
9652 /* Either no argument registers were pushed or a backtrace
9653 structure was created which includes an adjusted stack
9654 pointer, so just pop everything. */
9656 thumb_pushpop (asm_out_file, live_regs_mask, FALSE);
9659 thumb_exit (asm_out_file, 2, eh_ofs);
9660 /* We have either just popped the return address into the
9661 PC or it is was kept in LR for the entire function or
9662 it is still on the stack because we do not want to
9663 return by doing a pop {pc}. */
9664 else if ((live_regs_mask & (1 << PC_REGNUM)) == 0)
9665 thumb_exit (asm_out_file,
9667 && is_called_in_ARM_mode (current_function_decl)) ?
9668 -1 : LR_REGNUM, NULL_RTX);
9672 /* Pop everything but the return address. */
9673 live_regs_mask &= ~(1 << PC_REGNUM);
9676 thumb_pushpop (asm_out_file, live_regs_mask, FALSE);
9679 /* Get the return address into a temporary register. */
9680 thumb_pushpop (asm_out_file, 1 << LAST_ARG_REGNUM, 0);
9682 /* Remove the argument registers that were pushed onto the stack. */
9683 asm_fprintf (asm_out_file, "\tadd\t%r, %r, #%d\n",
9684 SP_REGNUM, SP_REGNUM,
9685 current_function_pretend_args_size);
9688 thumb_exit (asm_out_file, 2, eh_ofs);
9690 thumb_exit (asm_out_file,
9691 had_to_push_lr ? LAST_ARG_REGNUM : LR_REGNUM, NULL_RTX);
9697 /* Functions to save and restore machine-specific function data. */
9700 arm_mark_machine_status (p)
9701 struct function * p;
9703 machine_function *machine = p->machine;
9706 ggc_mark_rtx (machine->eh_epilogue_sp_ofs);
9710 arm_init_machine_status (p)
9711 struct function * p;
9714 (machine_function *) xcalloc (1, sizeof (machine_function));
9716 #if ARM_FT_UNKNOWWN != 0
9717 ((machine_function *) p->machine)->func_type = ARM_FT_UNKNOWN;
9722 arm_free_machine_status (p)
9723 struct function * p;
9732 /* Return an RTX indicating where the return address to the
9733 calling function can be found. */
9735 arm_return_addr (count, frame)
9737 rtx frame ATTRIBUTE_UNUSED;
9743 return get_hard_reg_initial_val (Pmode, LR_REGNUM);
9746 rtx lr = gen_rtx_AND (Pmode, gen_rtx_REG (Pmode, LR_REGNUM),
9747 GEN_INT (RETURN_ADDR_MASK26));
9748 return get_func_hard_reg_initial_val (cfun, lr);
9752 /* Do anything needed before RTL is emitted for each function. */
9754 arm_init_expanders ()
9756 /* Arrange to initialize and mark the machine per-function status. */
9757 init_machine_status = arm_init_machine_status;
9758 mark_machine_status = arm_mark_machine_status;
9759 free_machine_status = arm_free_machine_status;
9762 /* Generate the rest of a function's prologue. */
9764 thumb_expand_prologue ()
9766 HOST_WIDE_INT amount = (get_frame_size ()
9767 + current_function_outgoing_args_size);
9768 unsigned long func_type;
9770 func_type = arm_current_func_type ();
9772 /* Naked functions don't have prologues. */
9773 if (IS_NAKED (func_type))
9776 if (IS_INTERRUPT (func_type))
9778 error ("Interrupt Service Routines cannot be coded in Thumb mode.");
9782 if (frame_pointer_needed)
9783 emit_insn (gen_movsi (hard_frame_pointer_rtx, stack_pointer_rtx));
9787 amount = ROUND_UP (amount);
9790 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
9791 GEN_INT (-amount)));
9797 /* The stack decrement is too big for an immediate value in a single
9798 insn. In theory we could issue multiple subtracts, but after
9799 three of them it becomes more space efficient to place the full
9800 value in the constant pool and load into a register. (Also the
9801 ARM debugger really likes to see only one stack decrement per
9802 function). So instead we look for a scratch register into which
9803 we can load the decrement, and then we subtract this from the
9804 stack pointer. Unfortunately on the thumb the only available
9805 scratch registers are the argument registers, and we cannot use
9806 these as they may hold arguments to the function. Instead we
9807 attempt to locate a call preserved register which is used by this
9808 function. If we can find one, then we know that it will have
9809 been pushed at the start of the prologue and so we can corrupt
9811 for (regno = LAST_ARG_REGNUM + 1; regno <= LAST_LO_REGNUM; regno++)
9812 if (regs_ever_live[regno]
9813 && !call_used_regs[regno] /* Paranoia */
9814 && !(TARGET_SINGLE_PIC_BASE && (regno == arm_pic_register))
9815 && !(frame_pointer_needed
9816 && (regno == THUMB_HARD_FRAME_POINTER_REGNUM)))
9819 if (regno > LAST_LO_REGNUM) /* Very unlikely */
9821 rtx spare = gen_rtx (REG, SImode, IP_REGNUM);
9823 /* Choose an arbitary, non-argument low register. */
9824 reg = gen_rtx (REG, SImode, LAST_LO_REGNUM);
9826 /* Save it by copying it into a high, scratch register. */
9827 emit_insn (gen_movsi (spare, reg));
9829 /* Decrement the stack. */
9830 emit_insn (gen_movsi (reg, GEN_INT (-amount)));
9831 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
9834 /* Restore the low register's original value. */
9835 emit_insn (gen_movsi (reg, spare));
9837 /* Emit a USE of the restored scratch register, so that flow
9838 analysis will not consider the restore redundant. The
9839 register won't be used again in this function and isn't
9840 restored by the epilogue. */
9841 emit_insn (gen_rtx_USE (VOIDmode, reg));
9845 reg = gen_rtx (REG, SImode, regno);
9847 emit_insn (gen_movsi (reg, GEN_INT (-amount)));
9848 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
9854 if (profile_flag || profile_block_flag || TARGET_NO_SCHED_PRO)
9855 emit_insn (gen_blockage ());
9859 thumb_expand_epilogue ()
9861 HOST_WIDE_INT amount = (get_frame_size ()
9862 + current_function_outgoing_args_size);
9864 /* Naked functions don't have prologues. */
9865 if (IS_NAKED (arm_current_func_type ()))
9868 if (frame_pointer_needed)
9869 emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx));
9872 amount = ROUND_UP (amount);
9875 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
9879 /* r3 is always free in the epilogue. */
9880 rtx reg = gen_rtx (REG, SImode, LAST_ARG_REGNUM);
9882 emit_insn (gen_movsi (reg, GEN_INT (amount)));
9883 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, reg));
9887 /* Emit a USE (stack_pointer_rtx), so that
9888 the stack adjustment will not be deleted. */
9889 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
9891 if (profile_flag || profile_block_flag || TARGET_NO_SCHED_PRO)
9892 emit_insn (gen_blockage ());
9896 output_thumb_prologue (f)
9899 int live_regs_mask = 0;
9900 int high_regs_pushed = 0;
9903 if (IS_NAKED (arm_current_func_type ()))
9906 if (is_called_in_ARM_mode (current_function_decl))
9910 if (GET_CODE (DECL_RTL (current_function_decl)) != MEM)
9912 if (GET_CODE (XEXP (DECL_RTL (current_function_decl), 0)) != SYMBOL_REF)
9914 name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
9916 /* Generate code sequence to switch us into Thumb mode. */
9917 /* The .code 32 directive has already been emitted by
9918 ASM_DECLARE_FUNCTION_NAME. */
9919 asm_fprintf (f, "\torr\t%r, %r, #1\n", IP_REGNUM, PC_REGNUM);
9920 asm_fprintf (f, "\tbx\t%r\n", IP_REGNUM);
9922 /* Generate a label, so that the debugger will notice the
9923 change in instruction sets. This label is also used by
9924 the assembler to bypass the ARM code when this function
9925 is called from a Thumb encoded function elsewhere in the
9926 same file. Hence the definition of STUB_NAME here must
9927 agree with the definition in gas/config/tc-arm.c */
9929 #define STUB_NAME ".real_start_of"
9931 asm_fprintf (f, "\t.code\t16\n");
9933 if (arm_dllexport_name_p (name))
9934 name = arm_strip_name_encoding (name);
9936 asm_fprintf (f, "\t.globl %s%U%s\n", STUB_NAME, name);
9937 asm_fprintf (f, "\t.thumb_func\n");
9938 asm_fprintf (f, "%s%U%s:\n", STUB_NAME, name);
9941 if (current_function_pretend_args_size)
9943 if (current_function_anonymous_args)
9947 asm_fprintf (f, "\tpush\t{");
9949 num_pushes = NUM_INTS (current_function_pretend_args_size);
9951 for (regno = LAST_ARG_REGNUM + 1 - num_pushes;
9952 regno <= LAST_ARG_REGNUM;
9954 asm_fprintf (f, "%r%s", regno,
9955 regno == LAST_ARG_REGNUM ? "" : ", ");
9957 asm_fprintf (f, "}\n");
9960 asm_fprintf (f, "\tsub\t%r, %r, #%d\n",
9961 SP_REGNUM, SP_REGNUM,
9962 current_function_pretend_args_size);
9965 for (regno = 0; regno <= LAST_LO_REGNUM; regno++)
9966 if (regs_ever_live[regno] && !call_used_regs[regno]
9967 && !(TARGET_SINGLE_PIC_BASE && (regno == arm_pic_register)))
9968 live_regs_mask |= 1 << regno;
9970 if (live_regs_mask || !leaf_function_p () || thumb_far_jump_used_p (1))
9971 live_regs_mask |= 1 << LR_REGNUM;
9973 if (TARGET_BACKTRACE)
9976 int work_register = 0;
9979 /* We have been asked to create a stack backtrace structure.
9980 The code looks like this:
9984 0 sub SP, #16 Reserve space for 4 registers.
9985 2 push {R7} Get a work register.
9986 4 add R7, SP, #20 Get the stack pointer before the push.
9987 6 str R7, [SP, #8] Store the stack pointer (before reserving the space).
9988 8 mov R7, PC Get hold of the start of this code plus 12.
9989 10 str R7, [SP, #16] Store it.
9990 12 mov R7, FP Get hold of the current frame pointer.
9991 14 str R7, [SP, #4] Store it.
9992 16 mov R7, LR Get hold of the current return address.
9993 18 str R7, [SP, #12] Store it.
9994 20 add R7, SP, #16 Point at the start of the backtrace structure.
9995 22 mov FP, R7 Put this value into the frame pointer. */
9997 if ((live_regs_mask & 0xFF) == 0)
9999 /* See if the a4 register is free. */
10001 if (regs_ever_live [LAST_ARG_REGNUM] == 0)
10002 work_register = LAST_ARG_REGNUM;
10003 else /* We must push a register of our own */
10004 live_regs_mask |= (1 << LAST_LO_REGNUM);
10007 if (work_register == 0)
10009 /* Select a register from the list that will be pushed to
10010 use as our work register. */
10011 for (work_register = (LAST_LO_REGNUM + 1); work_register--;)
10012 if ((1 << work_register) & live_regs_mask)
10017 (f, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n",
10018 SP_REGNUM, SP_REGNUM);
10020 if (live_regs_mask)
10021 thumb_pushpop (f, live_regs_mask, 1);
10023 for (offset = 0, wr = 1 << 15; wr != 0; wr >>= 1)
10024 if (wr & live_regs_mask)
10027 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
10028 offset + 16 + current_function_pretend_args_size);
10030 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
10033 /* Make sure that the instruction fetching the PC is in the right place
10034 to calculate "start of backtrace creation code + 12". */
10035 if (live_regs_mask)
10037 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
10038 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
10040 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
10041 ARM_HARD_FRAME_POINTER_REGNUM);
10042 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
10047 asm_fprintf (f, "\tmov\t%r, %r\n", work_register,
10048 ARM_HARD_FRAME_POINTER_REGNUM);
10049 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
10051 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM);
10052 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
10056 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, LR_REGNUM);
10057 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM,
10059 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM,
10061 asm_fprintf (f, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n",
10062 ARM_HARD_FRAME_POINTER_REGNUM, work_register);
10064 else if (live_regs_mask)
10065 thumb_pushpop (f, live_regs_mask, 1);
10067 for (regno = 8; regno < 13; regno++)
10069 if (regs_ever_live[regno] && !call_used_regs[regno]
10070 && !(TARGET_SINGLE_PIC_BASE && (regno == arm_pic_register)))
10071 high_regs_pushed++;
10074 if (high_regs_pushed)
10076 int pushable_regs = 0;
10077 int mask = live_regs_mask & 0xff;
10080 for (next_hi_reg = 12; next_hi_reg > LAST_LO_REGNUM; next_hi_reg--)
10082 if (regs_ever_live[next_hi_reg] && !call_used_regs[next_hi_reg]
10083 && !(TARGET_SINGLE_PIC_BASE
10084 && (next_hi_reg == arm_pic_register)))
10088 pushable_regs = mask;
10090 if (pushable_regs == 0)
10092 /* Desperation time -- this probably will never happen. */
10093 if (regs_ever_live[LAST_ARG_REGNUM]
10094 || !call_used_regs[LAST_ARG_REGNUM])
10095 asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, LAST_ARG_REGNUM);
10096 mask = 1 << LAST_ARG_REGNUM;
10099 while (high_regs_pushed > 0)
10101 for (regno = LAST_LO_REGNUM; regno >= 0; regno--)
10103 if (mask & (1 << regno))
10105 asm_fprintf (f, "\tmov\t%r, %r\n", regno, next_hi_reg);
10107 high_regs_pushed--;
10109 if (high_regs_pushed)
10110 for (next_hi_reg--; next_hi_reg > LAST_LO_REGNUM;
10113 if (regs_ever_live[next_hi_reg]
10114 && !call_used_regs[next_hi_reg]
10115 && !(TARGET_SINGLE_PIC_BASE
10116 && (next_hi_reg == arm_pic_register)))
10121 mask &= ~((1 << regno) - 1);
10127 thumb_pushpop (f, mask, 1);
10130 if (pushable_regs == 0
10131 && (regs_ever_live[LAST_ARG_REGNUM]
10132 || !call_used_regs[LAST_ARG_REGNUM]))
10133 asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM);
10137 /* Handle the case of a double word load into a low register from
10138 a computed memory address. The computed address may involve a
10139 register which is overwritten by the load. */
10142 thumb_load_double_from_address (operands)
10151 if (GET_CODE (operands[0]) != REG)
10154 if (GET_CODE (operands[1]) != MEM)
10157 /* Get the memory address. */
10158 addr = XEXP (operands[1], 0);
10160 /* Work out how the memory address is computed. */
10161 switch (GET_CODE (addr))
10164 operands[2] = gen_rtx (MEM, SImode,
10165 plus_constant (XEXP (operands[1], 0), 4));
10167 if (REGNO (operands[0]) == REGNO (addr))
10169 output_asm_insn ("ldr\t%H0, %2", operands);
10170 output_asm_insn ("ldr\t%0, %1", operands);
10174 output_asm_insn ("ldr\t%0, %1", operands);
10175 output_asm_insn ("ldr\t%H0, %2", operands);
10180 /* Compute <address> + 4 for the high order load. */
10181 operands[2] = gen_rtx (MEM, SImode,
10182 plus_constant (XEXP (operands[1], 0), 4));
10184 output_asm_insn ("ldr\t%0, %1", operands);
10185 output_asm_insn ("ldr\t%H0, %2", operands);
10189 arg1 = XEXP (addr, 0);
10190 arg2 = XEXP (addr, 1);
10192 if (CONSTANT_P (arg1))
10193 base = arg2, offset = arg1;
10195 base = arg1, offset = arg2;
10197 if (GET_CODE (base) != REG)
10200 /* Catch the case of <address> = <reg> + <reg> */
10201 if (GET_CODE (offset) == REG)
10203 int reg_offset = REGNO (offset);
10204 int reg_base = REGNO (base);
10205 int reg_dest = REGNO (operands[0]);
10207 /* Add the base and offset registers together into the
10208 higher destination register. */
10209 asm_fprintf (asm_out_file, "\tadd\t%r, %r, %r",
10210 reg_dest + 1, reg_base, reg_offset);
10212 /* Load the lower destination register from the address in
10213 the higher destination register. */
10214 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #0]",
10215 reg_dest, reg_dest + 1);
10217 /* Load the higher destination register from its own address
10219 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #4]",
10220 reg_dest + 1, reg_dest + 1);
10224 /* Compute <address> + 4 for the high order load. */
10225 operands[2] = gen_rtx (MEM, SImode,
10226 plus_constant (XEXP (operands[1], 0), 4));
10228 /* If the computed address is held in the low order register
10229 then load the high order register first, otherwise always
10230 load the low order register first. */
10231 if (REGNO (operands[0]) == REGNO (base))
10233 output_asm_insn ("ldr\t%H0, %2", operands);
10234 output_asm_insn ("ldr\t%0, %1", operands);
10238 output_asm_insn ("ldr\t%0, %1", operands);
10239 output_asm_insn ("ldr\t%H0, %2", operands);
10245 /* With no registers to worry about we can just load the value
10247 operands[2] = gen_rtx (MEM, SImode,
10248 plus_constant (XEXP (operands[1], 0), 4));
10250 output_asm_insn ("ldr\t%H0, %2", operands);
10251 output_asm_insn ("ldr\t%0, %1", operands);
10264 thumb_output_move_mem_multiple (n, operands)
10273 if (REGNO (operands[4]) > REGNO (operands[5]))
10276 operands[4] = operands[5];
10279 output_asm_insn ("ldmia\t%1!, {%4, %5}", operands);
10280 output_asm_insn ("stmia\t%0!, {%4, %5}", operands);
10284 if (REGNO (operands[4]) > REGNO (operands[5]))
10287 operands[4] = operands[5];
10290 if (REGNO (operands[5]) > REGNO (operands[6]))
10293 operands[5] = operands[6];
10296 if (REGNO (operands[4]) > REGNO (operands[5]))
10299 operands[4] = operands[5];
10303 output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands);
10304 output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands);
10314 /* Routines for generating rtl */
10317 thumb_expand_movstrqi (operands)
10320 rtx out = copy_to_mode_reg (SImode, XEXP (operands[0], 0));
10321 rtx in = copy_to_mode_reg (SImode, XEXP (operands[1], 0));
10322 HOST_WIDE_INT len = INTVAL (operands[2]);
10323 HOST_WIDE_INT offset = 0;
10327 emit_insn (gen_movmem12b (out, in, out, in));
10333 emit_insn (gen_movmem8b (out, in, out, in));
10339 rtx reg = gen_reg_rtx (SImode);
10340 emit_insn (gen_movsi (reg, gen_rtx (MEM, SImode, in)));
10341 emit_insn (gen_movsi (gen_rtx (MEM, SImode, out), reg));
10348 rtx reg = gen_reg_rtx (HImode);
10349 emit_insn (gen_movhi (reg, gen_rtx (MEM, HImode,
10350 plus_constant (in, offset))));
10351 emit_insn (gen_movhi (gen_rtx (MEM, HImode, plus_constant (out, offset)),
10359 rtx reg = gen_reg_rtx (QImode);
10360 emit_insn (gen_movqi (reg, gen_rtx (MEM, QImode,
10361 plus_constant (in, offset))));
10362 emit_insn (gen_movqi (gen_rtx (MEM, QImode, plus_constant (out, offset)),
10368 thumb_cmp_operand (op, mode)
10370 enum machine_mode mode;
10372 return ((GET_CODE (op) == CONST_INT
10373 && (unsigned HOST_WIDE_INT) (INTVAL (op)) < 256)
10374 || register_operand (op, mode));
10377 static const char *
10378 thumb_condition_code (x, invert)
10382 static const char * conds[] =
10384 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
10385 "hi", "ls", "ge", "lt", "gt", "le"
10389 switch (GET_CODE (x))
10391 case EQ: val = 0; break;
10392 case NE: val = 1; break;
10393 case GEU: val = 2; break;
10394 case LTU: val = 3; break;
10395 case GTU: val = 8; break;
10396 case LEU: val = 9; break;
10397 case GE: val = 10; break;
10398 case LT: val = 11; break;
10399 case GT: val = 12; break;
10400 case LE: val = 13; break;
10405 return conds[val ^ invert];
10408 /* Handle storing a half-word to memory during reload. */
10410 thumb_reload_out_hi (operands)
10413 emit_insn (gen_thumb_movhi_clobber (operands[0], operands[1], operands[2]));
10416 /* Handle storing a half-word to memory during reload. */
10418 thumb_reload_in_hi (operands)
10419 rtx * operands ATTRIBUTE_UNUSED;
10424 /* Return the length of a function name prefix
10425 that starts with the character 'c'. */
10427 arm_get_strip_length (char c)
10431 ARM_NAME_ENCODING_LENGTHS
10436 /* Return a pointer to a function's name with any
10437 and all prefix encodings stripped from it. */
10439 arm_strip_name_encoding (const char * name)
10443 while ((skip = arm_get_strip_length (* name)))
10449 #ifdef AOF_ASSEMBLER
10450 /* Special functions only needed when producing AOF syntax assembler. */
10452 rtx aof_pic_label = NULL_RTX;
10455 struct pic_chain * next;
10459 static struct pic_chain * aof_pic_chain = NULL;
10465 struct pic_chain ** chainp;
10468 if (aof_pic_label == NULL_RTX)
10470 /* We mark this here and not in arm_add_gc_roots() to avoid
10471 polluting even more code with ifdefs, and because it never
10472 contains anything useful until we assign to it here. */
10473 ggc_add_rtx_root (&aof_pic_label, 1);
10474 aof_pic_label = gen_rtx_SYMBOL_REF (Pmode, "x$adcons");
10477 for (offset = 0, chainp = &aof_pic_chain; *chainp;
10478 offset += 4, chainp = &(*chainp)->next)
10479 if ((*chainp)->symname == XSTR (x, 0))
10480 return plus_constant (aof_pic_label, offset);
10482 *chainp = (struct pic_chain *) xmalloc (sizeof (struct pic_chain));
10483 (*chainp)->next = NULL;
10484 (*chainp)->symname = XSTR (x, 0);
10485 return plus_constant (aof_pic_label, offset);
10489 aof_dump_pic_table (f)
10492 struct pic_chain * chain;
10494 if (aof_pic_chain == NULL)
10497 asm_fprintf (f, "\tAREA |%r$$adcons|, BASED %r\n",
10498 PIC_OFFSET_TABLE_REGNUM,
10499 PIC_OFFSET_TABLE_REGNUM);
10500 fputs ("|x$adcons|\n", f);
10502 for (chain = aof_pic_chain; chain; chain = chain->next)
10504 fputs ("\tDCD\t", f);
10505 assemble_name (f, chain->symname);
10510 int arm_text_section_count = 1;
10513 aof_text_section ()
10515 static char buf[100];
10516 sprintf (buf, "\tAREA |C$$code%d|, CODE, READONLY",
10517 arm_text_section_count++);
10519 strcat (buf, ", PIC, REENTRANT");
10523 static int arm_data_section_count = 1;
10526 aof_data_section ()
10528 static char buf[100];
10529 sprintf (buf, "\tAREA |C$$data%d|, DATA", arm_data_section_count++);
10533 /* The AOF assembler is religiously strict about declarations of
10534 imported and exported symbols, so that it is impossible to declare
10535 a function as imported near the beginning of the file, and then to
10536 export it later on. It is, however, possible to delay the decision
10537 until all the functions in the file have been compiled. To get
10538 around this, we maintain a list of the imports and exports, and
10539 delete from it any that are subsequently defined. At the end of
10540 compilation we spit the remainder of the list out before the END
10545 struct import * next;
10549 static struct import * imports_list = NULL;
10552 aof_add_import (name)
10555 struct import * new;
10557 for (new = imports_list; new; new = new->next)
10558 if (new->name == name)
10561 new = (struct import *) xmalloc (sizeof (struct import));
10562 new->next = imports_list;
10563 imports_list = new;
10568 aof_delete_import (name)
10571 struct import ** old;
10573 for (old = &imports_list; *old; old = & (*old)->next)
10575 if ((*old)->name == name)
10577 *old = (*old)->next;
10583 int arm_main_function = 0;
10586 aof_dump_imports (f)
10589 /* The AOF assembler needs this to cause the startup code to be extracted
10590 from the library. Brining in __main causes the whole thing to work
10592 if (arm_main_function)
10595 fputs ("\tIMPORT __main\n", f);
10596 fputs ("\tDCD __main\n", f);
10599 /* Now dump the remaining imports. */
10600 while (imports_list)
10602 fprintf (f, "\tIMPORT\t");
10603 assemble_name (f, imports_list->name);
10605 imports_list = imports_list->next;
10608 #endif /* AOF_ASSEMBLER */