1 /* Definitions of target machine for GNU compiler, Argonaut ARC cpu.
2 Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2004, 2005,
3 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
21 /* ??? This is an old port, and is undoubtedly suffering from bit rot. */
26 - print active compiler options in assembler output
37 #undef WCHAR_TYPE_SIZE
38 #undef ASM_OUTPUT_LABELREF
40 /* Print subsidiary information on the compiler version in use. */
41 #define TARGET_VERSION fprintf (stderr, " (arc)")
43 /* Names to predefine in the preprocessor for this target machine. */
44 #define TARGET_CPU_CPP_BUILTINS() \
47 builtin_define ("__arc__"); \
48 if (TARGET_BIG_ENDIAN) \
49 builtin_define ("__big_endian__"); \
50 if (arc_cpu_type == 0) \
51 builtin_define ("__base__"); \
52 builtin_assert ("cpu=arc"); \
53 builtin_assert ("machine=arc"); \
56 /* Pass -mmangle-cpu if we get -mcpu=*.
57 Doing it this way lets one have it on as default with -mcpu=*,
58 but also lets one turn it off with -mno-mangle-cpu. */
60 %{mcpu=*:-mmangle-cpu} \
61 %{EB:%{EL:%emay not use both -EB and -EL}} \
62 %{EB:-mbig-endian} %{EL:-mlittle-endian} \
65 #define ASM_SPEC "%{v} %{EB} %{EL}"
67 #define LINK_SPEC "%{v} %{EB} %{EL}"
69 #define STARTFILE_SPEC "%{!shared:crt0.o%s} crtinit.o%s"
71 #define ENDFILE_SPEC "crtfini.o%s"
73 /* Instruction set characteristics.
74 These are internal macros, set by the appropriate -mcpu= option. */
76 /* Nonzero means the cpu has a barrel shifter. */
77 #define TARGET_SHIFTER 0
79 /* Which cpu we're compiling for. */
80 extern int arc_cpu_type;
82 /* Check if CPU is an extension and set `arc_cpu_type' and `arc_mangle_cpu'
83 appropriately. The result should be nonzero if the cpu is recognized,
84 otherwise zero. This is intended to be redefined in a cover file.
85 This is used by arc_handle_option. */
86 #define ARC_EXTENSION_CPU(cpu) 0
89 /* Target machine storage layout. */
91 /* Define this if most significant bit is lowest numbered
92 in instructions that operate on numbered bit-fields. */
93 #define BITS_BIG_ENDIAN 1
95 /* Define this if most significant byte of a word is the lowest numbered. */
96 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN)
98 /* Define this if most significant word of a multiword number is the lowest
100 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN)
102 /* Width of a word, in units (bytes). */
103 #define UNITS_PER_WORD 4
105 /* Define this macro if it is advisable to hold scalars in registers
106 in a wider mode than that declared by the program. In such cases,
107 the value is constrained to be within the bounds of the declared
108 type, but kept valid in the wider mode. The signedness of the
109 extension may differ from that of the type. */
110 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
111 if (GET_MODE_CLASS (MODE) == MODE_INT \
112 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
117 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
118 #define PARM_BOUNDARY 32
120 /* Boundary (in *bits*) on which stack pointer should be aligned. */
121 #define STACK_BOUNDARY 64
123 /* ALIGN FRAMES on word boundaries */
124 #define ARC_STACK_ALIGN(LOC) (((LOC)+7) & ~7)
126 /* Allocation boundary (in *bits*) for the code of a function. */
127 #define FUNCTION_BOUNDARY 32
129 /* Alignment of field after `int : 0' in a structure. */
130 #define EMPTY_FIELD_BOUNDARY 32
132 /* Every structure's size must be a multiple of this. */
133 #define STRUCTURE_SIZE_BOUNDARY 8
135 /* A bit-field declared as `int' forces `int' alignment for the struct. */
136 #define PCC_BITFIELD_TYPE_MATTERS 1
138 /* No data type wants to be aligned rounder than this. */
139 /* This is bigger than currently necessary for the ARC. If 8 byte floats are
140 ever added it's not clear whether they'll need such alignment or not. For
141 now we assume they will. We can always relax it if necessary but the
142 reverse isn't true. */
143 #define BIGGEST_ALIGNMENT 64
145 /* The best alignment to use in cases where we have a choice. */
146 #define FASTEST_ALIGNMENT 32
148 /* Make strings word-aligned so strcpy from constants will be faster. */
149 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
150 ((TREE_CODE (EXP) == STRING_CST \
151 && (ALIGN) < FASTEST_ALIGNMENT) \
152 ? FASTEST_ALIGNMENT : (ALIGN))
154 /* Make arrays of chars word-aligned for the same reasons. */
155 #define DATA_ALIGNMENT(TYPE, ALIGN) \
156 (TREE_CODE (TYPE) == ARRAY_TYPE \
157 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
158 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
160 /* Set this nonzero if move instructions will actually fail to work
161 when given unaligned data. */
162 /* On the ARC the lower address bits are masked to 0 as necessary. The chip
163 won't croak when given an unaligned address, but the insn will still fail
164 to produce the correct result. */
165 #define STRICT_ALIGNMENT 1
167 /* Layout of source language data types. */
169 #define SHORT_TYPE_SIZE 16
170 #define INT_TYPE_SIZE 32
171 #define LONG_TYPE_SIZE 32
172 #define LONG_LONG_TYPE_SIZE 64
173 #define FLOAT_TYPE_SIZE 32
174 #define DOUBLE_TYPE_SIZE 64
175 #define LONG_DOUBLE_TYPE_SIZE 64
177 /* Define this as 1 if `char' should by default be signed; else as 0. */
178 #define DEFAULT_SIGNED_CHAR 1
180 #define SIZE_TYPE "long unsigned int"
181 #define PTRDIFF_TYPE "long int"
182 #define WCHAR_TYPE "short unsigned int"
183 #define WCHAR_TYPE_SIZE 16
185 /* Standard register usage. */
187 /* Number of actual hardware registers.
188 The hardware registers are assigned numbers for the compiler
189 from 0 to just below FIRST_PSEUDO_REGISTER.
190 All registers that the compiler knows about must be given numbers,
191 even those that are not normally considered general registers. */
192 /* Registers 61, 62, and 63 are not really registers and we needn't treat
193 them as such. We still need a register for the condition code. */
194 #define FIRST_PSEUDO_REGISTER 62
196 /* 1 for registers that have pervasive standard uses
197 and are not available for the register allocator.
199 0-28 - general purpose registers
200 29 - ilink1 (interrupt link register)
201 30 - ilink2 (interrupt link register)
202 31 - blink (branch link register)
203 32-59 - reserved for extensions
208 61 - short immediate data indicator (setting flags)
209 62 - long immediate data indicator
210 63 - short immediate data indicator (not setting flags).
212 The general purpose registers are further broken down into:
213 0-7 - arguments/results
216 24 - call used, static chain pointer
217 25 - call used, gptmp
222 By default, the extension registers are not available. */
224 #define FIXED_REGISTERS \
225 { 0, 0, 0, 0, 0, 0, 0, 0, \
226 0, 0, 0, 0, 0, 0, 0, 0, \
227 0, 0, 0, 0, 0, 0, 0, 0, \
228 0, 0, 0, 1, 1, 1, 1, 0, \
230 1, 1, 1, 1, 1, 1, 1, 1, \
231 1, 1, 1, 1, 1, 1, 1, 1, \
232 1, 1, 1, 1, 1, 1, 1, 1, \
235 /* 1 for registers not available across function calls.
236 These must include the FIXED_REGISTERS and also any
237 registers that can be used without being saved.
238 The latter must include the registers where values are returned
239 and the register where structure-value addresses are passed.
240 Aside from that, you can include as many other registers as you like. */
242 #define CALL_USED_REGISTERS \
243 { 1, 1, 1, 1, 1, 1, 1, 1, \
244 1, 1, 1, 1, 1, 1, 1, 1, \
245 0, 0, 0, 0, 0, 0, 0, 0, \
246 1, 1, 1, 1, 1, 1, 1, 1, \
248 1, 1, 1, 1, 1, 1, 1, 1, \
249 1, 1, 1, 1, 1, 1, 1, 1, \
250 1, 1, 1, 1, 1, 1, 1, 1, \
253 /* If defined, an initializer for a vector of integers, containing the
254 numbers of hard registers in the order in which GCC should
255 prefer to use them (from most preferred to least). */
256 #define REG_ALLOC_ORDER \
257 { 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 1, \
258 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 31, \
259 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
260 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, \
263 /* Return number of consecutive hard regs needed starting at reg REGNO
264 to hold something of mode MODE.
265 This is ordinarily the length in words of a value of mode MODE
266 but can be less for certain modes in special long registers. */
267 #define HARD_REGNO_NREGS(REGNO, MODE) \
268 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
270 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
271 extern const unsigned int arc_hard_regno_mode_ok[];
272 extern unsigned int arc_mode_class[];
273 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
274 ((arc_hard_regno_mode_ok[REGNO] & arc_mode_class[MODE]) != 0)
276 /* A C expression that is nonzero if it is desirable to choose
277 register allocation so as to avoid move instructions between a
278 value of mode MODE1 and a value of mode MODE2.
280 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R,
281 MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1,
282 MODE2)' must be zero. */
284 /* Tie QI/HI/SI modes together. */
285 #define MODES_TIEABLE_P(MODE1, MODE2) \
286 (GET_MODE_CLASS (MODE1) == MODE_INT \
287 && GET_MODE_CLASS (MODE2) == MODE_INT \
288 && GET_MODE_SIZE (MODE1) <= UNITS_PER_WORD \
289 && GET_MODE_SIZE (MODE2) <= UNITS_PER_WORD)
291 /* Register classes and constants. */
293 /* Define the classes of registers for register constraints in the
294 machine description. Also define ranges of constants.
296 One of the classes must always be named ALL_REGS and include all hard regs.
297 If there is more than one class, another class must be named NO_REGS
298 and contain no registers.
300 The name GENERAL_REGS must be the name of a class (or an alias for
301 another name such as ALL_REGS). This is the class of registers
302 that is allowed by "g" or "r" in a register constraint.
303 Also, registers outside this class are allocated only when
304 instructions express preferences for them.
306 The classes must be numbered in nondecreasing order; that is,
307 a larger-numbered class must never be contained completely
308 in a smaller-numbered class.
310 For any two classes, it is very desirable that there be another
311 class that represents their union.
313 It is important that any condition codes have class NO_REGS.
314 See `register_operand'. */
317 NO_REGS, LPCOUNT_REG, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES
320 #define N_REG_CLASSES (int) LIM_REG_CLASSES
322 /* Give names of register classes as strings for dump file. */
323 #define REG_CLASS_NAMES \
324 { "NO_REGS", "LPCOUNT_REG", "GENERAL_REGS", "ALL_REGS" }
326 /* Define which registers fit in which classes.
327 This is an initializer for a vector of HARD_REG_SET
328 of length N_REG_CLASSES. */
330 #define REG_CLASS_CONTENTS \
331 { {0, 0}, {0, 0x10000000}, {0xffffffff, 0xfffffff}, \
332 {0xffffffff, 0x1fffffff} }
334 /* The same information, inverted:
335 Return the class number of the smallest class containing
336 reg number REGNO. This could be a conditional expression
337 or could index an array. */
338 extern enum reg_class arc_regno_reg_class[FIRST_PSEUDO_REGISTER];
339 #define REGNO_REG_CLASS(REGNO) \
340 (arc_regno_reg_class[REGNO])
342 /* The class value for index registers, and the one for base regs. */
343 #define INDEX_REG_CLASS GENERAL_REGS
344 #define BASE_REG_CLASS GENERAL_REGS
346 /* Get reg_class from a letter such as appears in the machine description. */
347 #define REG_CLASS_FROM_LETTER(C) \
348 ((C) == 'l' ? LPCOUNT_REG /* ??? needed? */ \
351 /* These assume that REGNO is a hard or pseudo reg number.
352 They give nonzero only if REGNO is a hard reg of the suitable class
353 or a pseudo reg currently allocated to a suitable hard reg.
354 Since they use reg_renumber, they are safe only once reg_renumber
355 has been allocated, which happens in local-alloc.c. */
356 #define REGNO_OK_FOR_BASE_P(REGNO) \
357 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32)
358 #define REGNO_OK_FOR_INDEX_P(REGNO) \
359 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32)
361 /* Return the maximum number of consecutive registers
362 needed to represent mode MODE in a register of class CLASS. */
363 #define CLASS_MAX_NREGS(CLASS, MODE) \
364 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
366 /* The letters I, J, K, L, M, N, O, P in a register constraint string
367 can be used to stand for particular ranges of immediate operands.
368 This macro defines what the ranges are.
369 C is the letter, and VALUE is a constant value.
370 Return 1 if VALUE is in the range specified by C. */
371 /* 'I' is used for short immediates (always signed).
372 'J' is used for long immediates.
373 'K' is used for any constant up to 64 bits (for 64x32 situations?). */
375 /* local to this file */
376 #define SMALL_INT(X) ((unsigned) ((X) + 0x100) < 0x200)
377 /* local to this file */
378 #define LARGE_INT(X) \
379 ((X) >= (-(HOST_WIDE_INT) 0x7fffffff - 1) \
380 && (unsigned HOST_WIDE_INT)(X) <= (unsigned HOST_WIDE_INT) 0xffffffff)
382 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
383 ((C) == 'I' ? SMALL_INT (VALUE) \
384 : (C) == 'J' ? LARGE_INT (VALUE) \
388 /* Similar, but for floating constants, and defining letters G and H.
389 Here VALUE is the CONST_DOUBLE rtx itself. */
390 /* 'G' is used for integer values for the multiplication insns where the
391 operands are extended from 4 bytes to 8 bytes.
392 'H' is used when any 64-bit constant is allowed. */
393 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
394 ((C) == 'G' ? arc_double_limm_p (VALUE) \
398 /* A C expression that defines the optional machine-dependent constraint
399 letters that can be used to segregate specific types of operands,
400 usually memory references, for the target machine. It should return 1 if
401 VALUE corresponds to the operand type represented by the constraint letter
402 C. If C is not defined as an extra constraint, the value returned should
403 be 0 regardless of VALUE. */
404 /* ??? This currently isn't used. Waiting for PIC. */
406 #define EXTRA_CONSTRAINT(VALUE, C) \
407 ((C) == 'R' ? (SYMBOL_REF_FUNCTION_P (VALUE) || GET_CODE (VALUE) == LABEL_REF) \
411 /* Stack layout and stack pointer usage. */
413 /* Define this macro if pushing a word onto the stack moves the stack
414 pointer to a smaller address. */
415 #define STACK_GROWS_DOWNWARD
417 /* Define this to nonzero if the nominal address of the stack frame
418 is at the high-address end of the local variables;
419 that is, each additional local variable allocated
420 goes at a more negative offset in the frame. */
421 #define FRAME_GROWS_DOWNWARD 1
423 /* Offset within stack frame to start allocating local variables at.
424 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
425 first local allocated. Otherwise, it is the offset to the BEGINNING
426 of the first local allocated. */
427 #define STARTING_FRAME_OFFSET 0
429 /* Offset from the stack pointer register to the first location at which
430 outgoing arguments are placed. */
431 #define STACK_POINTER_OFFSET FIRST_PARM_OFFSET (0)
433 /* Offset of first parameter from the argument pointer register value. */
434 /* 4 bytes for each of previous fp, return address, and previous gp.
435 4 byte reserved area for future considerations. */
436 #define FIRST_PARM_OFFSET(FNDECL) 16
438 /* A C expression whose value is RTL representing the address in a
439 stack frame where the pointer to the caller's frame is stored.
440 Assume that FRAMEADDR is an RTL expression for the address of the
443 If you don't define this macro, the default is to return the value
444 of FRAMEADDR--that is, the stack frame address is also the address
445 of the stack word that points to the previous frame. */
447 /*define DYNAMIC_CHAIN_ADDRESS (FRAMEADDR)*/
449 /* A C expression whose value is RTL representing the value of the
450 return address for the frame COUNT steps up from the current frame.
451 FRAMEADDR is the frame pointer of the COUNT frame, or the frame
452 pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME'
454 /* The current return address is in r31. The return address of anything
455 farther back is at [%fp,4]. */
456 #if 0 /* The default value should work. */
457 #define RETURN_ADDR_RTX(COUNT, FRAME) \
459 ? gen_rtx_REG (Pmode, 31) \
460 : copy_to_reg (gen_rtx_MEM (Pmode, \
461 memory_address (Pmode, \
462 plus_constant ((FRAME), \
466 /* Register to use for pushing function arguments. */
467 #define STACK_POINTER_REGNUM 28
469 /* Base register for access to local variables of the function. */
470 #define FRAME_POINTER_REGNUM 27
472 /* Base register for access to arguments of the function. */
473 #define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM
475 /* Register in which static-chain is passed to a function. This must
476 not be a register used by the prologue. */
477 #define STATIC_CHAIN_REGNUM 24
479 /* C statement to store the difference between the frame pointer
480 and the stack pointer values immediately after the function prologue. */
481 #define INITIAL_FRAME_POINTER_OFFSET(VAR) \
482 ((VAR) = arc_compute_frame_size (get_frame_size ()))
484 /* Function argument passing. */
486 /* If defined, the maximum amount of space required for outgoing
487 arguments will be computed and placed into the variable
488 `crtl->outgoing_args_size'. No space will be pushed
489 onto the stack for each call; instead, the function prologue should
490 increase the stack frame size by this amount. */
491 #define ACCUMULATE_OUTGOING_ARGS 1
493 /* Define a data type for recording info about an argument list
494 during the scan of that argument list. This data type should
495 hold all necessary information about the function itself
496 and about the args processed so far, enough to enable macros
497 such as FUNCTION_ARG to determine where the next arg should go. */
498 #define CUMULATIVE_ARGS int
500 /* Initialize a variable CUM of type CUMULATIVE_ARGS
501 for a call to a function whose data type is FNTYPE.
502 For a library call, FNTYPE is 0. */
503 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
506 /* The number of registers used for parameter passing. Local to this file. */
507 #define MAX_ARC_PARM_REGS 8
509 /* 1 if N is a possible register number for function argument passing. */
510 #define FUNCTION_ARG_REGNO_P(N) \
511 ((unsigned) (N) < MAX_ARC_PARM_REGS)
514 /* Function results. */
516 /* Define how to find the value returned by a function.
517 VALTYPE is the data type of the value (as a tree).
518 If the precise function being called is known, FUNC is its FUNCTION_DECL;
519 otherwise, FUNC is 0. */
520 #define FUNCTION_VALUE(VALTYPE, FUNC) gen_rtx_REG (TYPE_MODE (VALTYPE), 0)
522 /* Define how to find the value returned by a library function
523 assuming the value has mode MODE. */
524 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, 0)
526 /* 1 if N is a possible register number for a function value
527 as seen by the caller. */
528 /* ??? What about r1 in DI/DF values. */
529 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
531 /* Tell GCC to use TARGET_RETURN_IN_MEMORY. */
532 #define DEFAULT_PCC_STRUCT_RETURN 0
534 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
535 the stack pointer does not matter. The value is tested only in
536 functions that have frame pointers.
537 No definition is equivalent to always zero. */
538 #define EXIT_IGNORE_STACK 0
540 /* Epilogue delay slots. */
541 #define DELAY_SLOTS_FOR_EPILOGUE arc_delay_slots_for_epilogue ()
543 #define ELIGIBLE_FOR_EPILOGUE_DELAY(TRIAL, SLOTS_FILLED) \
544 arc_eligible_for_epilogue_delay (TRIAL, SLOTS_FILLED)
546 /* Output assembler code to FILE to increment profiler label # LABELNO
547 for profiling a function entry. */
548 #define FUNCTION_PROFILER(FILE, LABELNO)
550 #define TRAMPOLINE_ALIGNMENT 32
551 #define TRAMPOLINE_SIZE 16
553 /* Addressing modes, and classification of registers for them. */
555 /* Maximum number of registers that can appear in a valid memory address. */
556 /* The `ld' insn allows 2, but the `st' insn only allows 1. */
557 #define MAX_REGS_PER_ADDRESS 1
559 /* We have pre inc/dec (load/store with update). */
560 #define HAVE_PRE_INCREMENT 1
561 #define HAVE_PRE_DECREMENT 1
563 /* Recognize any constant value that is a valid address. */
564 #define CONSTANT_ADDRESS_P(X) \
565 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
566 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST)
568 /* Nonzero if the constant value X is a legitimate general operand.
569 We can handle any 32- or 64-bit constant. */
570 /* "1" should work since the largest constant should be a 64 bit critter. */
571 /* ??? Not sure what to do for 64x32 compiler. */
572 #define LEGITIMATE_CONSTANT_P(X) 1
574 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
575 and check its validity for a certain class.
576 We have two alternate definitions for each of them.
577 The usual definition accepts all pseudo regs; the other rejects
578 them unless they have been allocated suitable hard regs.
579 The symbol REG_OK_STRICT causes the latter definition to be used.
581 Most source files want to accept pseudo regs in the hope that
582 they will get allocated to the class that the insn wants them to be in.
583 Source files for reload pass need to be strict.
584 After reload, it makes no difference, since pseudo regs have
585 been eliminated by then. */
587 #ifndef REG_OK_STRICT
589 /* Nonzero if X is a hard reg that can be used as an index
590 or if it is a pseudo reg. */
591 #define REG_OK_FOR_INDEX_P(X) \
592 ((unsigned) REGNO (X) - 32 >= FIRST_PSEUDO_REGISTER - 32)
593 /* Nonzero if X is a hard reg that can be used as a base reg
594 or if it is a pseudo reg. */
595 #define REG_OK_FOR_BASE_P(X) \
596 ((unsigned) REGNO (X) - 32 >= FIRST_PSEUDO_REGISTER - 32)
600 /* Nonzero if X is a hard reg that can be used as an index. */
601 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
602 /* Nonzero if X is a hard reg that can be used as a base reg. */
603 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
607 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
608 that is a valid memory address for an instruction.
609 The MODE argument is the machine mode for the MEM expression
610 that wants to use this address. */
611 /* The `ld' insn allows [reg],[reg+shimm],[reg+limm],[reg+reg],[limm]
612 but the `st' insn only allows [reg],[reg+shimm],[limm].
613 The only thing we can do is only allow the most strict case `st' and hope
614 other parts optimize out the restrictions for `ld'. */
616 /* local to this file */
617 #define RTX_OK_FOR_BASE_P(X) \
618 (REG_P (X) && REG_OK_FOR_BASE_P (X))
620 /* local to this file */
621 #define RTX_OK_FOR_INDEX_P(X) \
622 (0 && /*???*/ REG_P (X) && REG_OK_FOR_INDEX_P (X))
624 /* local to this file */
625 /* ??? Loads can handle any constant, stores can only handle small ones. */
626 #define RTX_OK_FOR_OFFSET_P(X) \
627 (GET_CODE (X) == CONST_INT && SMALL_INT (INTVAL (X)))
629 #define LEGITIMATE_OFFSET_ADDRESS_P(MODE, X) \
630 (GET_CODE (X) == PLUS \
631 && RTX_OK_FOR_BASE_P (XEXP (X, 0)) \
632 && (RTX_OK_FOR_INDEX_P (XEXP (X, 1)) \
633 || RTX_OK_FOR_OFFSET_P (XEXP (X, 1))))
635 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
636 { if (RTX_OK_FOR_BASE_P (X)) \
638 if (LEGITIMATE_OFFSET_ADDRESS_P ((MODE), (X))) \
640 if (GET_CODE (X) == CONST_INT && LARGE_INT (INTVAL (X))) \
642 if (GET_CODE (X) == SYMBOL_REF \
643 || GET_CODE (X) == LABEL_REF \
644 || GET_CODE (X) == CONST) \
646 if ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
647 /* We're restricted here by the `st' insn. */ \
648 && RTX_OK_FOR_BASE_P (XEXP ((X), 0))) \
652 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
653 return the mode to be used for the comparison. */
654 #define SELECT_CC_MODE(OP, X, Y) \
655 arc_select_cc_mode (OP, X, Y)
657 /* Return nonzero if SELECT_CC_MODE will never return MODE for a
658 floating point inequality comparison. */
659 #define REVERSIBLE_CC_MODE(MODE) 1 /*???*/
663 /* Compute extra cost of moving data between one register class
665 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) 2
667 /* Compute the cost of moving data between registers and memory. */
668 /* Memory is 3 times as expensive as registers.
669 ??? Is that the right way to look at it? */
670 #define MEMORY_MOVE_COST(MODE,CLASS,IN) \
671 (GET_MODE_SIZE (MODE) <= UNITS_PER_WORD ? 6 : 12)
673 /* The cost of a branch insn. */
674 /* ??? What's the right value here? Branches are certainly more
675 expensive than reg->reg moves. */
676 #define BRANCH_COST(speed_p, predictable_p) 2
678 /* Nonzero if access to memory by bytes is slow and undesirable.
679 For RISC chips, it means that access to memory by bytes is no
680 better than access by words when possible, so grab a whole word
681 and maybe make use of that. */
682 #define SLOW_BYTE_ACCESS 1
684 /* Define this macro if it is as good or better to call a constant
685 function address than to call an address kept in a register. */
686 /* On the ARC, calling through registers is slow. */
687 #define NO_FUNCTION_CSE
689 /* Section selection. */
690 /* WARNING: These section names also appear in dwarfout.c. */
692 /* The names of the text, data, and readonly-data sections are runtime
695 #define ARC_SECTION_FORMAT "\t.section %s"
696 #define ARC_DEFAULT_TEXT_SECTION ".text"
697 #define ARC_DEFAULT_DATA_SECTION ".data"
698 #define ARC_DEFAULT_RODATA_SECTION ".rodata"
700 extern const char *arc_text_section, *arc_data_section, *arc_rodata_section;
702 /* initfini.c uses this in an asm. */
703 #if defined (CRT_INIT) || defined (CRT_FINI)
704 #define TEXT_SECTION_ASM_OP "\t.section .text"
706 #define TEXT_SECTION_ASM_OP arc_text_section
708 #define DATA_SECTION_ASM_OP arc_data_section
710 #undef READONLY_DATA_SECTION_ASM_OP
711 #define READONLY_DATA_SECTION_ASM_OP arc_rodata_section
713 #define BSS_SECTION_ASM_OP "\t.section .bss"
715 /* Define this macro if jump tables (for tablejump insns) should be
716 output in the text section, along with the assembler instructions.
717 Otherwise, the readonly data section is used.
718 This macro is irrelevant if there is no separate readonly data section. */
719 /*#define JUMP_TABLES_IN_TEXT_SECTION*/
721 /* For DWARF. Marginally different than default so output is "prettier"
722 (and consistent with above). */
723 #define PUSHSECTION_ASM_OP "\t.section "
725 /* Tell crtstuff.c we're using ELF. */
726 #define OBJECT_FORMAT_ELF
730 /* The register number of the register used to address a table of static
731 data addresses in memory. In some cases this register is defined by a
732 processor's ``application binary interface'' (ABI). When this macro
733 is defined, RTL is generated for this register once, as with the stack
734 pointer and frame pointer registers. If this macro is not defined, it
735 is up to the machine-dependent files to allocate such a register (if
737 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 26 : INVALID_REGNUM)
739 /* Define this macro if the register defined by PIC_OFFSET_TABLE_REGNUM is
740 clobbered by calls. Do not define this macro if PIC_OFFSET_TABLE_REGNUM
742 /* This register is call-saved on the ARC. */
743 /*#define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED*/
745 /* A C expression that is nonzero if X is a legitimate immediate
746 operand on the target machine when generating position independent code.
747 You can assume that X satisfies CONSTANT_P, so you need not
748 check this. You can also assume `flag_pic' is true, so you need not
749 check it either. You need not define this macro if all constants
750 (including SYMBOL_REF) can be immediate operands when generating
751 position independent code. */
752 /*#define LEGITIMATE_PIC_OPERAND_P(X)*/
754 /* Control the assembler format that we output. */
756 /* A C string constant describing how to begin a comment in the target
757 assembler language. The compiler assumes that the comment will
758 end at the end of the line. */
759 #define ASM_COMMENT_START ";"
761 /* Output to assembler file text saying following lines
762 may contain character constants, extra white space, comments, etc. */
763 #define ASM_APP_ON ""
765 /* Output to assembler file text saying following lines
766 no longer contain unusual constructs. */
767 #define ASM_APP_OFF ""
769 /* Globalizing directive for a label. */
770 #define GLOBAL_ASM_OP "\t.global\t"
772 /* This is how to output a reference to a user-level label named NAME.
773 `assemble_name' uses this. */
774 /* We mangle all user labels to provide protection from linking code
775 compiled for different cpus. */
776 /* We work around a dwarfout.c deficiency by watching for labels from it and
777 not adding the '_' prefix nor the cpu suffix. There is a comment in
778 dwarfout.c that says it should be using (*targetm.asm_out.internal_label). */
779 extern const char *arc_mangle_cpu;
780 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
782 if ((NAME)[0] == '.' && (NAME)[1] == 'L') \
783 fprintf (FILE, "%s", NAME); \
787 if (TARGET_MANGLE_CPU && arc_mangle_cpu != NULL) \
788 fprintf (FILE, "%s_", arc_mangle_cpu); \
789 fprintf (FILE, "%s", NAME); \
793 /* Assembler pseudo-op to equate one value with another. */
794 /* ??? This is needed because dwarfout.c provides a default definition too
795 late for defaults.h (which contains the default definition of ASM_OUTPUT_DEF
797 #define SET_ASM_OP "\t.set\t"
799 /* How to refer to registers in assembler output.
800 This sequence is indexed by compiler's hard-register-number (see above). */
801 #define REGISTER_NAMES \
802 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
803 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
804 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
805 "r24", "r25", "r26", "fp", "sp", "ilink1", "ilink2", "blink", \
806 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \
807 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", \
808 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \
809 "r56", "r57", "r58", "r59", "lp_count", "cc"}
811 /* Entry to the insn conditionalizer. */
812 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
813 arc_final_prescan_insn (INSN, OPVEC, NOPERANDS)
815 /* A C expression which evaluates to true if CODE is a valid
816 punctuation character for use in the `PRINT_OPERAND' macro. */
817 extern char arc_punct_chars[256];
818 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
819 arc_punct_chars[(unsigned char) (CHAR)]
821 /* Print operand X (an rtx) in assembler syntax to file FILE.
822 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
823 For `%' followed by punctuation, CODE is the punctuation and X is null. */
824 #define PRINT_OPERAND(FILE, X, CODE) \
825 arc_print_operand (FILE, X, CODE)
827 /* A C compound statement to output to stdio stream STREAM the
828 assembler syntax for an instruction operand that is a memory
829 reference whose address is ADDR. ADDR is an RTL expression. */
830 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
831 arc_print_operand_address (FILE, ADDR)
833 /* This is how to output an element of a case-vector that is absolute. */
834 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
837 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
838 fprintf (FILE, "\t.word %%st("); \
839 assemble_name (FILE, label); \
840 fprintf (FILE, ")\n"); \
843 /* This is how to output an element of a case-vector that is relative. */
844 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
847 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
848 fprintf (FILE, "\t.word %%st("); \
849 assemble_name (FILE, label); \
850 fprintf (FILE, "-"); \
851 ASM_GENERATE_INTERNAL_LABEL (label, "L", REL); \
852 assemble_name (FILE, label); \
853 fprintf (FILE, ")\n"); \
856 /* The desired alignment for the location counter at the beginning
858 /* On the ARC, align loops to 32 byte boundaries (cache line size)
860 #define LOOP_ALIGN(LABEL) (TARGET_ALIGN_LOOPS ? 5 : 0)
862 /* This is how to output an assembler line
863 that says to advance the location counter
864 to a multiple of 2**LOG bytes. */
865 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
866 do { if ((LOG) != 0) fprintf (FILE, "\t.align %d\n", 1 << (LOG)); } while (0)
868 /* Debugging information. */
870 /* Generate DBX and DWARF debugging information. */
871 #define DBX_DEBUGGING_INFO 1
873 /* Prefer STABS (for now). */
874 #undef PREFERRED_DEBUGGING_TYPE
875 #define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
877 /* Turn off splitting of long stabs. */
878 #define DBX_CONTIN_LENGTH 0
882 /* Specify the machine mode that this machine uses
883 for the index in the tablejump instruction. */
884 #define CASE_VECTOR_MODE Pmode
886 /* Define if operations between registers always perform the operation
887 on the full register even if a narrower mode is specified. */
888 #define WORD_REGISTER_OPERATIONS
890 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
891 will either zero-extend or sign-extend. The value of this macro should
892 be the code that says which one of the two operations is implicitly
893 done, UNKNOWN if none. */
894 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
896 /* Max number of bytes we can move from memory to memory
897 in one reasonably fast instruction. */
900 /* Define this to be nonzero if shift instructions ignore all but the low-order
902 #define SHIFT_COUNT_TRUNCATED 1
904 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
905 is done just by pretending it is already truncated. */
906 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
908 /* Specify the machine mode that pointers have.
909 After generation of rtl, the compiler makes no further distinction
910 between pointers and any other objects of this machine mode. */
911 /* ??? The arc doesn't have full 32-bit pointers, but making this PSImode has
912 its own problems (you have to add extendpsisi2 and trucnsipsi2 but how does
913 one do it without getting excess code?). Try to avoid it. */
916 /* A function address in a call instruction. */
917 #define FUNCTION_MODE SImode
919 /* alloca should avoid clobbering the old register save area. */
920 /* ??? Not defined in tm.texi. */
921 #define SETJMP_VIA_SAVE_AREA
923 /* ARC function types. */
924 enum arc_function_type {
925 ARC_FUNCTION_UNKNOWN, ARC_FUNCTION_NORMAL,
926 /* These are interrupt handlers. The name corresponds to the register
927 name that contains the return address. */
928 ARC_FUNCTION_ILINK1, ARC_FUNCTION_ILINK2
930 #define ARC_INTERRUPT_P(TYPE) \
931 ((TYPE) == ARC_FUNCTION_ILINK1 || (TYPE) == ARC_FUNCTION_ILINK2)
932 /* Compute the type of a function from its DECL. */