1 /* Subroutines used for code generation on the Argonaut ARC cpu.
2 Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002
3 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 /* ??? This is an old port, and is undoubtedly suffering from bit rot. */
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
34 #include "insn-attr.h"
42 #include "target-def.h"
44 /* Which cpu we're compiling for (NULL(=base), ???). */
45 const char *arc_cpu_string;
48 /* Name of mangle string to add to symbols to separate code compiled for each
50 const char *arc_mangle_cpu;
52 /* Save the operands last given to a compare for use when we
53 generate a scc or bcc insn. */
54 rtx arc_compare_op0, arc_compare_op1;
56 /* Name of text, data, and rodata sections, as specified on command line.
57 Selected by -m{text,data,rodata} flags. */
58 const char *arc_text_string = ARC_DEFAULT_TEXT_SECTION;
59 const char *arc_data_string = ARC_DEFAULT_DATA_SECTION;
60 const char *arc_rodata_string = ARC_DEFAULT_RODATA_SECTION;
62 /* Name of text, data, and rodata sections used in varasm.c. */
63 const char *arc_text_section;
64 const char *arc_data_section;
65 const char *arc_rodata_section;
67 /* Array of valid operand punctuation characters. */
68 char arc_punct_chars[256];
70 /* Variables used by arc_final_prescan_insn to implement conditional
72 static int arc_ccfsm_state;
73 static int arc_ccfsm_current_cc;
74 static rtx arc_ccfsm_target_insn;
75 static int arc_ccfsm_target_label;
77 /* The maximum number of insns skipped which will be conditionalised if
79 #define MAX_INSNS_SKIPPED 3
81 /* A nop is needed between a 4 byte insn that sets the condition codes and
82 a branch that uses them (the same isn't true for an 8 byte insn that sets
83 the condition codes). Set by arc_final_prescan_insn. Used by
85 static int last_insn_set_cc_p;
86 static int current_insn_set_cc_p;
87 static void record_cc_ref PARAMS ((rtx));
88 static void arc_init_reg_tables PARAMS ((void));
89 static int get_arc_condition_code PARAMS ((rtx));
90 const struct attribute_spec arc_attribute_table[];
91 static tree arc_handle_interrupt_attribute PARAMS ((tree *, tree, tree, int, bool *));
92 static bool arc_assemble_integer PARAMS ((rtx, unsigned int, int));
93 static void arc_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
94 static void arc_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
95 static void arc_encode_section_info PARAMS ((tree, int));
97 /* Initialize the GCC target structure. */
98 #undef TARGET_ASM_ALIGNED_HI_OP
99 #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
100 #undef TARGET_ASM_ALIGNED_SI_OP
101 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
102 #undef TARGET_ASM_INTEGER
103 #define TARGET_ASM_INTEGER arc_assemble_integer
105 #undef TARGET_ASM_FUNCTION_PROLOGUE
106 #define TARGET_ASM_FUNCTION_PROLOGUE arc_output_function_prologue
107 #undef TARGET_ASM_FUNCTION_EPILOGUE
108 #define TARGET_ASM_FUNCTION_EPILOGUE arc_output_function_epilogue
109 #undef TARGET_ATTRIBUTE_TABLE
110 #define TARGET_ATTRIBUTE_TABLE arc_attribute_table
111 #undef TARGET_ENCODE_SECTION_INFO
112 #define TARGET_ENCODE_SECTION_INFO arc_encode_section_info
114 struct gcc_target targetm = TARGET_INITIALIZER;
116 /* Called by OVERRIDE_OPTIONS to initialize various things. */
123 if (arc_cpu_string == 0
124 || !strcmp (arc_cpu_string, "base"))
126 /* Ensure we have a printable value for the .cpu pseudo-op. */
127 arc_cpu_string = "base";
129 arc_mangle_cpu = NULL;
131 else if (ARC_EXTENSION_CPU (arc_cpu_string))
132 ; /* nothing to do */
135 error ("bad value (%s) for -mcpu switch", arc_cpu_string);
136 arc_cpu_string = "base";
138 arc_mangle_cpu = NULL;
141 /* Set the pseudo-ops for the various standard sections. */
142 arc_text_section = tmp = xmalloc (strlen (arc_text_string) + sizeof (ARC_SECTION_FORMAT) + 1);
143 sprintf (tmp, ARC_SECTION_FORMAT, arc_text_string);
144 arc_data_section = tmp = xmalloc (strlen (arc_data_string) + sizeof (ARC_SECTION_FORMAT) + 1);
145 sprintf (tmp, ARC_SECTION_FORMAT, arc_data_string);
146 arc_rodata_section = tmp = xmalloc (strlen (arc_rodata_string) + sizeof (ARC_SECTION_FORMAT) + 1);
147 sprintf (tmp, ARC_SECTION_FORMAT, arc_rodata_string);
149 arc_init_reg_tables ();
151 /* Initialize array for PRINT_OPERAND_PUNCT_VALID_P. */
152 memset (arc_punct_chars, 0, sizeof (arc_punct_chars));
153 arc_punct_chars['#'] = 1;
154 arc_punct_chars['*'] = 1;
155 arc_punct_chars['?'] = 1;
156 arc_punct_chars['!'] = 1;
157 arc_punct_chars['~'] = 1;
160 /* The condition codes of the ARC, and the inverse function. */
161 static const char *const arc_condition_codes[] =
163 "al", 0, "eq", "ne", "p", "n", "c", "nc", "v", "nv",
164 "gt", "le", "ge", "lt", "hi", "ls", "pnz", 0
167 #define ARC_INVERSE_CONDITION_CODE(X) ((X) ^ 1)
169 /* Returns the index of the ARC condition code string in
170 `arc_condition_codes'. COMPARISON should be an rtx like
171 `(eq (...) (...))'. */
174 get_arc_condition_code (comparison)
177 switch (GET_CODE (comparison))
185 case GTU : return 14;
186 case LEU : return 15;
195 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
196 return the mode to be used for the comparison. */
199 arc_select_cc_mode (op, x, y)
201 rtx x, y ATTRIBUTE_UNUSED;
209 switch (GET_CODE (x))
228 /* Vectors to keep interesting information about registers where it can easily
229 be got. We use to use the actual mode value as the bit number, but there
230 is (or may be) more than 32 modes now. Instead we use two tables: one
231 indexed by hard register number, and one indexed by mode. */
233 /* The purpose of arc_mode_class is to shrink the range of modes so that
234 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
235 mapped into one arc_mode_class mode. */
237 enum arc_mode_class {
239 S_MODE, D_MODE, T_MODE, O_MODE,
240 SF_MODE, DF_MODE, TF_MODE, OF_MODE
243 /* Modes for condition codes. */
244 #define C_MODES (1 << (int) C_MODE)
246 /* Modes for single-word and smaller quantities. */
247 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
249 /* Modes for double-word and smaller quantities. */
250 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
252 /* Modes for quad-word and smaller quantities. */
253 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
255 /* Value is 1 if register/mode pair is acceptable on arc. */
257 const unsigned int arc_hard_regno_mode_ok[] = {
258 T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES,
259 T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES,
260 T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, D_MODES,
261 D_MODES, S_MODES, S_MODES, S_MODES, S_MODES, S_MODES, S_MODES, S_MODES,
263 /* ??? Leave these as S_MODES for now. */
264 S_MODES, S_MODES, S_MODES, S_MODES, S_MODES, S_MODES, S_MODES, S_MODES,
265 S_MODES, S_MODES, S_MODES, S_MODES, S_MODES, S_MODES, S_MODES, S_MODES,
266 S_MODES, S_MODES, S_MODES, S_MODES, S_MODES, S_MODES, S_MODES, S_MODES,
267 S_MODES, S_MODES, S_MODES, S_MODES, S_MODES, C_MODES
270 unsigned int arc_mode_class [NUM_MACHINE_MODES];
272 enum reg_class arc_regno_reg_class[FIRST_PSEUDO_REGISTER];
275 arc_init_reg_tables ()
279 for (i = 0; i < NUM_MACHINE_MODES; i++)
281 switch (GET_MODE_CLASS (i))
284 case MODE_PARTIAL_INT:
285 case MODE_COMPLEX_INT:
286 if (GET_MODE_SIZE (i) <= 4)
287 arc_mode_class[i] = 1 << (int) S_MODE;
288 else if (GET_MODE_SIZE (i) == 8)
289 arc_mode_class[i] = 1 << (int) D_MODE;
290 else if (GET_MODE_SIZE (i) == 16)
291 arc_mode_class[i] = 1 << (int) T_MODE;
292 else if (GET_MODE_SIZE (i) == 32)
293 arc_mode_class[i] = 1 << (int) O_MODE;
295 arc_mode_class[i] = 0;
298 case MODE_COMPLEX_FLOAT:
299 if (GET_MODE_SIZE (i) <= 4)
300 arc_mode_class[i] = 1 << (int) SF_MODE;
301 else if (GET_MODE_SIZE (i) == 8)
302 arc_mode_class[i] = 1 << (int) DF_MODE;
303 else if (GET_MODE_SIZE (i) == 16)
304 arc_mode_class[i] = 1 << (int) TF_MODE;
305 else if (GET_MODE_SIZE (i) == 32)
306 arc_mode_class[i] = 1 << (int) OF_MODE;
308 arc_mode_class[i] = 0;
312 /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so
313 we must explicitly check for them here. */
314 if (i == (int) CCmode || i == (int) CCZNmode || i == (int) CCZNCmode)
315 arc_mode_class[i] = 1 << (int) C_MODE;
317 arc_mode_class[i] = 0;
322 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
325 arc_regno_reg_class[i] = GENERAL_REGS;
327 arc_regno_reg_class[i] = LPCOUNT_REG;
329 arc_regno_reg_class[i] = NO_REGS /* CC_REG: must be NO_REGS */;
331 arc_regno_reg_class[i] = NO_REGS;
335 /* ARC specific attribute support.
337 The ARC has these attributes:
338 interrupt - for interrupt functions
341 const struct attribute_spec arc_attribute_table[] =
343 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
344 { "interrupt", 1, 1, true, false, false, arc_handle_interrupt_attribute },
345 { NULL, 0, 0, false, false, false, NULL }
348 /* Handle an "interrupt" attribute; arguments as in
349 struct attribute_spec.handler. */
351 arc_handle_interrupt_attribute (node, name, args, flags, no_add_attrs)
352 tree *node ATTRIBUTE_UNUSED;
355 int flags ATTRIBUTE_UNUSED;
358 tree value = TREE_VALUE (args);
360 if (TREE_CODE (value) != STRING_CST)
362 warning ("argument of `%s' attribute is not a string constant",
363 IDENTIFIER_POINTER (name));
364 *no_add_attrs = true;
366 else if (strcmp (TREE_STRING_POINTER (value), "ilink1")
367 && strcmp (TREE_STRING_POINTER (value), "ilink2"))
369 warning ("argument of `%s' attribute is not \"ilink1\" or \"ilink2\"",
370 IDENTIFIER_POINTER (name));
371 *no_add_attrs = true;
378 /* Acceptable arguments to the call insn. */
381 call_address_operand (op, mode)
383 enum machine_mode mode;
385 return (symbolic_operand (op, mode)
386 || (GET_CODE (op) == CONST_INT && LEGITIMATE_CONSTANT_P (op))
387 || (GET_CODE (op) == REG));
391 call_operand (op, mode)
393 enum machine_mode mode;
395 if (GET_CODE (op) != MEM)
398 return call_address_operand (op, mode);
401 /* Returns 1 if OP is a symbol reference. */
404 symbolic_operand (op, mode)
406 enum machine_mode mode ATTRIBUTE_UNUSED;
408 switch (GET_CODE (op))
419 /* Return truth value of statement that OP is a symbolic memory
420 operand of mode MODE. */
423 symbolic_memory_operand (op, mode)
425 enum machine_mode mode ATTRIBUTE_UNUSED;
427 if (GET_CODE (op) == SUBREG)
428 op = SUBREG_REG (op);
429 if (GET_CODE (op) != MEM)
432 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
433 || GET_CODE (op) == LABEL_REF);
436 /* Return true if OP is a short immediate (shimm) value. */
439 short_immediate_operand (op, mode)
441 enum machine_mode mode ATTRIBUTE_UNUSED;
443 if (GET_CODE (op) != CONST_INT)
445 return SMALL_INT (INTVAL (op));
448 /* Return true if OP will require a long immediate (limm) value.
449 This is currently only used when calculating length attributes. */
452 long_immediate_operand (op, mode)
454 enum machine_mode mode ATTRIBUTE_UNUSED;
456 switch (GET_CODE (op))
463 return !SMALL_INT (INTVAL (op));
465 /* These can happen because large unsigned 32 bit constants are
466 represented this way (the multiplication patterns can cause these
467 to be generated). They also occur for SFmode values. */
475 /* Return true if OP is a MEM that when used as a load or store address will
476 require an 8 byte insn.
477 Load and store instructions don't allow the same possibilities but they're
478 similar enough that this one function will do.
479 This is currently only used when calculating length attributes. */
482 long_immediate_loadstore_operand (op, mode)
484 enum machine_mode mode ATTRIBUTE_UNUSED;
486 if (GET_CODE (op) != MEM)
490 switch (GET_CODE (op))
497 /* This must be handled as "st c,[limm]". Ditto for load.
498 Technically, the assembler could translate some possibilities to
499 "st c,[limm/2 + limm/2]" if limm/2 will fit in a shimm, but we don't
500 assume that it does. */
503 /* These can happen because large unsigned 32 bit constants are
504 represented this way (the multiplication patterns can cause these
505 to be generated). They also occur for SFmode values. */
510 if (GET_CODE (XEXP (op, 1)) == CONST_INT
511 && !SMALL_INT (INTVAL (XEXP (op, 1))))
520 /* Return true if OP is an acceptable argument for a single word
524 move_src_operand (op, mode)
526 enum machine_mode mode;
528 switch (GET_CODE (op))
535 return (LARGE_INT (INTVAL (op)));
537 /* We can handle DImode integer constants in SImode if the value
538 (signed or unsigned) will fit in 32 bits. This is needed because
539 large unsigned 32 bit constants are represented as CONST_DOUBLEs. */
541 return arc_double_limm_p (op);
542 /* We can handle 32 bit floating point constants. */
544 return GET_MODE (op) == SFmode;
547 return register_operand (op, mode);
549 /* (subreg (mem ...) ...) can occur here if the inner part was once a
550 pseudo-reg and is now a stack slot. */
551 if (GET_CODE (SUBREG_REG (op)) == MEM)
552 return address_operand (XEXP (SUBREG_REG (op), 0), mode);
554 return register_operand (op, mode);
556 return address_operand (XEXP (op, 0), mode);
562 /* Return true if OP is an acceptable argument for a double word
566 move_double_src_operand (op, mode)
568 enum machine_mode mode;
570 switch (GET_CODE (op))
573 return register_operand (op, mode);
575 /* (subreg (mem ...) ...) can occur here if the inner part was once a
576 pseudo-reg and is now a stack slot. */
577 if (GET_CODE (SUBREG_REG (op)) == MEM)
578 return move_double_src_operand (SUBREG_REG (op), mode);
580 return register_operand (op, mode);
582 /* Disallow auto inc/dec for now. */
583 if (GET_CODE (XEXP (op, 0)) == PRE_DEC
584 || GET_CODE (XEXP (op, 0)) == PRE_INC)
586 return address_operand (XEXP (op, 0), mode);
595 /* Return true if OP is an acceptable argument for a move destination. */
598 move_dest_operand (op, mode)
600 enum machine_mode mode;
602 switch (GET_CODE (op))
605 return register_operand (op, mode);
607 /* (subreg (mem ...) ...) can occur here if the inner part was once a
608 pseudo-reg and is now a stack slot. */
609 if (GET_CODE (SUBREG_REG (op)) == MEM)
610 return address_operand (XEXP (SUBREG_REG (op), 0), mode);
612 return register_operand (op, mode);
614 return address_operand (XEXP (op, 0), mode);
620 /* Return true if OP is valid load with update operand. */
623 load_update_operand (op, mode)
625 enum machine_mode mode;
627 if (GET_CODE (op) != MEM
628 || GET_MODE (op) != mode)
631 if (GET_CODE (op) != PLUS
632 || GET_MODE (op) != Pmode
633 || !register_operand (XEXP (op, 0), Pmode)
634 || !nonmemory_operand (XEXP (op, 1), Pmode))
639 /* Return true if OP is valid store with update operand. */
642 store_update_operand (op, mode)
644 enum machine_mode mode;
646 if (GET_CODE (op) != MEM
647 || GET_MODE (op) != mode)
650 if (GET_CODE (op) != PLUS
651 || GET_MODE (op) != Pmode
652 || !register_operand (XEXP (op, 0), Pmode)
653 || !(GET_CODE (XEXP (op, 1)) == CONST_INT
654 && SMALL_INT (INTVAL (XEXP (op, 1)))))
659 /* Return true if OP is a non-volatile non-immediate operand.
660 Volatile memory refs require a special "cache-bypass" instruction
661 and only the standard movXX patterns are set up to handle them. */
664 nonvol_nonimm_operand (op, mode)
666 enum machine_mode mode;
668 if (GET_CODE (op) == MEM && MEM_VOLATILE_P (op))
670 return nonimmediate_operand (op, mode);
673 /* Accept integer operands in the range -0x80000000..0x7fffffff. We have
674 to check the range carefully since this predicate is used in DImode
678 const_sint32_operand (op, mode)
680 enum machine_mode mode ATTRIBUTE_UNUSED;
682 /* All allowed constants will fit a CONST_INT. */
683 return (GET_CODE (op) == CONST_INT
684 && (INTVAL (op) >= (-0x7fffffff - 1) && INTVAL (op) <= 0x7fffffff));
687 /* Accept integer operands in the range 0..0xffffffff. We have to check the
688 range carefully since this predicate is used in DImode contexts. Also, we
689 need some extra crud to make it work when hosted on 64-bit machines. */
692 const_uint32_operand (op, mode)
694 enum machine_mode mode ATTRIBUTE_UNUSED;
696 #if HOST_BITS_PER_WIDE_INT > 32
697 /* All allowed constants will fit a CONST_INT. */
698 return (GET_CODE (op) == CONST_INT
699 && (INTVAL (op) >= 0 && INTVAL (op) <= 0xffffffffL));
701 return ((GET_CODE (op) == CONST_INT && INTVAL (op) >= 0)
702 || (GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_HIGH (op) == 0));
706 /* Return 1 if OP is a comparison operator valid for the mode of CC.
707 This allows the use of MATCH_OPERATOR to recognize all the branch insns.
709 Some insns only set a few bits in the condition code. So only allow those
710 comparisons that use the bits that are valid. */
713 proper_comparison_operator (op, mode)
715 enum machine_mode mode ATTRIBUTE_UNUSED;
717 enum rtx_code code = GET_CODE (op);
719 if (GET_RTX_CLASS (code) != '<')
722 if (GET_MODE (XEXP (op, 0)) == CCZNmode)
723 return (code == EQ || code == NE);
724 if (GET_MODE (XEXP (op, 0)) == CCZNCmode)
725 return (code == EQ || code == NE
726 || code == LTU || code == GEU || code == GTU || code == LEU);
730 /* Misc. utilities. */
732 /* X and Y are two things to compare using CODE. Emit the compare insn and
733 return the rtx for the cc reg in the proper mode. */
736 gen_compare_reg (code, x, y)
740 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
743 cc_reg = gen_rtx_REG (mode, 61);
745 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
746 gen_rtx_COMPARE (mode, x, y)));
751 /* Return 1 if VALUE, a const_double, will fit in a limm (4 byte number).
752 We assume the value can be either signed or unsigned. */
755 arc_double_limm_p (value)
758 HOST_WIDE_INT low, high;
760 if (GET_CODE (value) != CONST_DOUBLE)
763 low = CONST_DOUBLE_LOW (value);
764 high = CONST_DOUBLE_HIGH (value);
766 if (low & 0x80000000)
768 return (((unsigned HOST_WIDE_INT) low <= 0xffffffff && high == 0)
769 || (((low & - (unsigned HOST_WIDE_INT) 0x80000000)
770 == - (unsigned HOST_WIDE_INT) 0x80000000)
775 return (unsigned HOST_WIDE_INT) low <= 0x7fffffff && high == 0;
779 /* Do any needed setup for a variadic function. For the ARC, we must
780 create a register parameter block, and then copy any anonymous arguments
781 in registers to memory.
783 CUM has not been updated for the last named argument which has type TYPE
784 and mode MODE, and we rely on this fact.
786 We do things a little weird here. We're supposed to only allocate space
787 for the anonymous arguments. However we need to keep the stack eight byte
788 aligned. So we round the space up if necessary, and leave it to va_start
792 arc_setup_incoming_varargs (cum, mode, type, pretend_size, no_rtl)
793 CUMULATIVE_ARGS *cum;
794 enum machine_mode mode;
795 tree type ATTRIBUTE_UNUSED;
801 /* All BLKmode values are passed by reference. */
805 /* We must treat `__builtin_va_alist' as an anonymous arg. */
806 if (current_function_varargs)
807 first_anon_arg = *cum;
809 first_anon_arg = *cum + ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1)
812 if (first_anon_arg < MAX_ARC_PARM_REGS && !no_rtl)
814 /* Note that first_reg_offset < MAX_ARC_PARM_REGS. */
815 int first_reg_offset = first_anon_arg;
816 /* Size in words to "pretend" allocate. */
817 int size = MAX_ARC_PARM_REGS - first_reg_offset;
818 /* Extra slop to keep stack eight byte aligned. */
819 int align_slop = size & 1;
822 regblock = gen_rtx_MEM (BLKmode,
823 plus_constant (arg_pointer_rtx,
824 FIRST_PARM_OFFSET (0)
825 + align_slop * UNITS_PER_WORD));
826 set_mem_alias_set (regblock, get_varargs_alias_set ());
827 set_mem_align (regblock, BITS_PER_WORD);
828 move_block_from_reg (first_reg_offset, regblock,
829 MAX_ARC_PARM_REGS - first_reg_offset,
830 ((MAX_ARC_PARM_REGS - first_reg_offset)
833 *pretend_size = ((MAX_ARC_PARM_REGS - first_reg_offset + align_slop)
838 /* Cost functions. */
840 /* Provide the costs of an addressing mode that contains ADDR.
841 If ADDR is not a valid address, its cost is irrelevant. */
844 arc_address_cost (addr)
847 switch (GET_CODE (addr))
850 /* This is handled in the macro that calls us.
851 It's here for documentation. */
861 register rtx plus0 = XEXP (addr, 0);
862 register rtx plus1 = XEXP (addr, 1);
864 if (GET_CODE (plus0) != REG)
867 switch (GET_CODE (plus1))
870 return SMALL_INT (plus1) ? 1 : 2;
887 /* Function prologue/epilogue handlers. */
889 /* ARC stack frames look like:
891 Before call After call
892 +-----------------------+ +-----------------------+
894 high | local variables, | | local variables, |
895 mem | reg save area, etc. | | reg save area, etc. |
897 +-----------------------+ +-----------------------+
899 | arguments on stack. | | arguments on stack. |
901 SP+16->+-----------------------+FP+48->+-----------------------+
902 | 4 word save area for | | reg parm save area, |
903 | return addr, prev %fp | | only created for |
904 SP+0->+-----------------------+ | variable argument |
906 FP+16->+-----------------------+
907 | 4 word save area for |
908 | return addr, prev %fp |
909 FP+0->+-----------------------+
913 +-----------------------+
915 | register save area |
917 +-----------------------+
919 | alloca allocations |
921 +-----------------------+
923 | arguments on stack |
925 SP+16->+-----------------------+
926 low | 4 word save area for |
927 memory | return addr, prev %fp |
928 SP+0->+-----------------------+
931 1) The "reg parm save area" does not exist for non variable argument fns.
932 The "reg parm save area" can be eliminated completely if we created our
933 own va-arc.h, but that has tradeoffs as well (so it's not done). */
935 /* Structure to be filled in by arc_compute_frame_size with register
936 save masks, and offsets for the current function. */
937 struct arc_frame_info
939 unsigned int total_size; /* # bytes that the entire frame takes up. */
940 unsigned int extra_size; /* # bytes of extra stuff. */
941 unsigned int pretend_size; /* # bytes we push and pretend caller did. */
942 unsigned int args_size; /* # bytes that outgoing arguments take up. */
943 unsigned int reg_size; /* # bytes needed to store regs. */
944 unsigned int var_size; /* # bytes that variables take up. */
945 unsigned int reg_offset; /* Offset from new sp to store regs. */
946 unsigned int gmask; /* Mask of saved gp registers. */
947 int initialized; /* Nonzero if frame size already calculated. */
950 /* Current frame information calculated by arc_compute_frame_size. */
951 static struct arc_frame_info current_frame_info;
953 /* Zero structure to initialize current_frame_info. */
954 static struct arc_frame_info zero_frame_info;
956 /* Type of function DECL.
958 The result is cached. To reset the cache at the end of a function,
959 call with DECL = NULL_TREE. */
961 enum arc_function_type
962 arc_compute_function_type (decl)
967 static enum arc_function_type fn_type = ARC_FUNCTION_UNKNOWN;
968 /* Last function we were called for. */
969 static tree last_fn = NULL_TREE;
971 /* Resetting the cached value? */
972 if (decl == NULL_TREE)
974 fn_type = ARC_FUNCTION_UNKNOWN;
979 if (decl == last_fn && fn_type != ARC_FUNCTION_UNKNOWN)
982 /* Assume we have a normal function (not an interrupt handler). */
983 fn_type = ARC_FUNCTION_NORMAL;
985 /* Now see if this is an interrupt handler. */
986 for (a = DECL_ATTRIBUTES (current_function_decl);
990 tree name = TREE_PURPOSE (a), args = TREE_VALUE (a);
992 if (name == get_identifier ("__interrupt__")
993 && list_length (args) == 1
994 && TREE_CODE (TREE_VALUE (args)) == STRING_CST)
996 tree value = TREE_VALUE (args);
998 if (!strcmp (TREE_STRING_POINTER (value), "ilink1"))
999 fn_type = ARC_FUNCTION_ILINK1;
1000 else if (!strcmp (TREE_STRING_POINTER (value), "ilink2"))
1001 fn_type = ARC_FUNCTION_ILINK2;
1012 #define ILINK1_REGNUM 29
1013 #define ILINK2_REGNUM 30
1014 #define RETURN_ADDR_REGNUM 31
1015 #define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM))
1016 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
1018 /* Tell prologue and epilogue if register REGNO should be saved / restored.
1019 The return address and frame pointer are treated separately.
1020 Don't consider them here. */
1021 #define MUST_SAVE_REGISTER(regno, interrupt_p) \
1022 ((regno) != RETURN_ADDR_REGNUM && (regno) != FRAME_POINTER_REGNUM \
1023 && (regs_ever_live[regno] && (!call_used_regs[regno] || interrupt_p)))
1025 #define MUST_SAVE_RETURN_ADDR (regs_ever_live[RETURN_ADDR_REGNUM])
1027 /* Return the bytes needed to compute the frame pointer from the current
1030 SIZE is the size needed for local variables. */
1033 arc_compute_frame_size (size)
1034 int size; /* # of var. bytes allocated. */
1037 unsigned int total_size, var_size, args_size, pretend_size, extra_size;
1038 unsigned int reg_size, reg_offset;
1040 enum arc_function_type fn_type;
1044 args_size = current_function_outgoing_args_size;
1045 pretend_size = current_function_pretend_args_size;
1046 extra_size = FIRST_PARM_OFFSET (0);
1047 total_size = extra_size + pretend_size + args_size + var_size;
1048 reg_offset = FIRST_PARM_OFFSET(0) + current_function_outgoing_args_size;
1052 /* See if this is an interrupt handler. Call used registers must be saved
1054 fn_type = arc_compute_function_type (current_function_decl);
1055 interrupt_p = ARC_INTERRUPT_P (fn_type);
1057 /* Calculate space needed for registers.
1058 ??? We ignore the extension registers for now. */
1060 for (regno = 0; regno <= 31; regno++)
1062 if (MUST_SAVE_REGISTER (regno, interrupt_p))
1064 reg_size += UNITS_PER_WORD;
1065 gmask |= 1 << regno;
1069 total_size += reg_size;
1071 /* If the only space to allocate is the fp/blink save area this is an
1072 empty frame. However, if we'll be making a function call we need to
1073 allocate a stack frame for our callee's fp/blink save area. */
1074 if (total_size == extra_size
1075 && !MUST_SAVE_RETURN_ADDR)
1076 total_size = extra_size = 0;
1078 total_size = ARC_STACK_ALIGN (total_size);
1080 /* Save computed information. */
1081 current_frame_info.total_size = total_size;
1082 current_frame_info.extra_size = extra_size;
1083 current_frame_info.pretend_size = pretend_size;
1084 current_frame_info.var_size = var_size;
1085 current_frame_info.args_size = args_size;
1086 current_frame_info.reg_size = reg_size;
1087 current_frame_info.reg_offset = reg_offset;
1088 current_frame_info.gmask = gmask;
1089 current_frame_info.initialized = reload_completed;
1091 /* Ok, we're done. */
1095 /* Common code to save/restore registers. */
1098 arc_save_restore (file, base_reg, offset, gmask, op)
1100 const char *base_reg;
1101 unsigned int offset;
1110 for (regno = 0; regno <= 31; regno++)
1112 if ((gmask & (1L << regno)) != 0)
1114 fprintf (file, "\t%s %s,[%s,%d]\n",
1115 op, reg_names[regno], base_reg, offset);
1116 offset += UNITS_PER_WORD;
1121 /* Target hook to assemble an integer object. The ARC version needs to
1122 emit a special directive for references to labels and function
1126 arc_assemble_integer (x, size, aligned_p)
1131 if (size == UNITS_PER_WORD && aligned_p
1132 && ((GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_FLAG (x))
1133 || GET_CODE (x) == LABEL_REF))
1135 fputs ("\t.word\t%st(", asm_out_file);
1136 output_addr_const (asm_out_file, x);
1137 fputs (")\n", asm_out_file);
1140 return default_assemble_integer (x, size, aligned_p);
1143 /* Set up the stack and frame pointer (if desired) for the function. */
1146 arc_output_function_prologue (file, size)
1150 const char *sp_str = reg_names[STACK_POINTER_REGNUM];
1151 const char *fp_str = reg_names[FRAME_POINTER_REGNUM];
1152 unsigned int gmask = current_frame_info.gmask;
1153 enum arc_function_type fn_type = arc_compute_function_type (current_function_decl);
1155 /* If this is an interrupt handler, set up our stack frame.
1156 ??? Optimize later. */
1157 if (ARC_INTERRUPT_P (fn_type))
1159 fprintf (file, "\t%s interrupt handler\n",
1161 fprintf (file, "\tsub %s,%s,16\n", sp_str, sp_str);
1164 /* This is only for the human reader. */
1165 fprintf (file, "\t%s BEGIN PROLOGUE %s vars= %d, regs= %d, args= %d, extra= %d\n",
1166 ASM_COMMENT_START, ASM_COMMENT_START,
1167 current_frame_info.var_size,
1168 current_frame_info.reg_size / 4,
1169 current_frame_info.args_size,
1170 current_frame_info.extra_size);
1172 size = ARC_STACK_ALIGN (size);
1173 size = (! current_frame_info.initialized
1174 ? arc_compute_frame_size (size)
1175 : current_frame_info.total_size);
1177 /* These cases shouldn't happen. Catch them now. */
1178 if (size == 0 && gmask)
1181 /* Allocate space for register arguments if this is a variadic function. */
1182 if (current_frame_info.pretend_size != 0)
1183 fprintf (file, "\tsub %s,%s,%d\n",
1184 sp_str, sp_str, current_frame_info.pretend_size);
1186 /* The home-grown ABI says link register is saved first. */
1187 if (MUST_SAVE_RETURN_ADDR)
1188 fprintf (file, "\tst %s,[%s,%d]\n",
1189 reg_names[RETURN_ADDR_REGNUM], sp_str, UNITS_PER_WORD);
1191 /* Set up the previous frame pointer next (if we need to). */
1192 if (frame_pointer_needed)
1194 fprintf (file, "\tst %s,[%s]\n", fp_str, sp_str);
1195 fprintf (file, "\tmov %s,%s\n", fp_str, sp_str);
1198 /* ??? We don't handle the case where the saved regs are more than 252
1199 bytes away from sp. This can be handled by decrementing sp once, saving
1200 the regs, and then decrementing it again. The epilogue doesn't have this
1201 problem as the `ld' insn takes reg+limm values (though it would be more
1202 efficient to avoid reg+limm). */
1204 /* Allocate the stack frame. */
1205 if (size - current_frame_info.pretend_size > 0)
1206 fprintf (file, "\tsub %s,%s,%d\n",
1207 sp_str, sp_str, size - current_frame_info.pretend_size);
1209 /* Save any needed call-saved regs (and call-used if this is an
1210 interrupt handler). */
1211 arc_save_restore (file, sp_str, current_frame_info.reg_offset,
1212 /* The zeroing of these two bits is unnecessary,
1213 but leave this in for clarity. */
1214 gmask & ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK),
1217 fprintf (file, "\t%s END PROLOGUE\n", ASM_COMMENT_START);
1220 /* Do any necessary cleanup after a function to restore stack, frame,
1224 arc_output_function_epilogue (file, size)
1228 rtx epilogue_delay = current_function_epilogue_delay_list;
1229 int noepilogue = FALSE;
1230 enum arc_function_type fn_type = arc_compute_function_type (current_function_decl);
1232 /* This is only for the human reader. */
1233 fprintf (file, "\t%s EPILOGUE\n", ASM_COMMENT_START);
1235 size = ARC_STACK_ALIGN (size);
1236 size = (!current_frame_info.initialized
1237 ? arc_compute_frame_size (size)
1238 : current_frame_info.total_size);
1240 if (size == 0 && epilogue_delay == 0)
1242 rtx insn = get_last_insn ();
1244 /* If the last insn was a BARRIER, we don't have to write any code
1245 because a jump (aka return) was put there. */
1246 if (GET_CODE (insn) == NOTE)
1247 insn = prev_nonnote_insn (insn);
1248 if (insn && GET_CODE (insn) == BARRIER)
1254 unsigned int pretend_size = current_frame_info.pretend_size;
1255 unsigned int frame_size = size - pretend_size;
1256 int restored, fp_restored_p;
1257 int can_trust_sp_p = !current_function_calls_alloca;
1258 const char *sp_str = reg_names[STACK_POINTER_REGNUM];
1259 const char *fp_str = reg_names[FRAME_POINTER_REGNUM];
1261 /* ??? There are lots of optimizations that can be done here.
1262 EG: Use fp to restore regs if it's closer.
1263 Maybe in time we'll do them all. For now, always restore regs from
1264 sp, but don't restore sp if we don't have to. */
1266 if (!can_trust_sp_p)
1268 if (!frame_pointer_needed)
1270 fprintf (file,"\tsub %s,%s,%d\t\t%s sp not trusted here\n",
1271 sp_str, fp_str, frame_size, ASM_COMMENT_START);
1274 /* Restore any saved registers. */
1275 arc_save_restore (file, sp_str, current_frame_info.reg_offset,
1276 /* The zeroing of these two bits is unnecessary,
1277 but leave this in for clarity. */
1278 current_frame_info.gmask & ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK),
1281 if (MUST_SAVE_RETURN_ADDR)
1282 fprintf (file, "\tld %s,[%s,%d]\n",
1283 reg_names[RETURN_ADDR_REGNUM],
1284 frame_pointer_needed ? fp_str : sp_str,
1285 UNITS_PER_WORD + (frame_pointer_needed ? 0 : frame_size));
1287 /* Keep track of how much of the stack pointer we've restored.
1288 It makes the following a lot more readable. */
1292 /* We try to emit the epilogue delay slot insn right after the load
1293 of the return address register so that it can execute with the
1294 stack intact. Secondly, loads are delayed. */
1295 /* ??? If stack intactness is important, always emit now. */
1296 if (MUST_SAVE_RETURN_ADDR && epilogue_delay != NULL_RTX)
1298 final_scan_insn (XEXP (epilogue_delay, 0), file, 1, -2, 1);
1299 epilogue_delay = NULL_RTX;
1302 if (frame_pointer_needed)
1304 /* Try to restore the frame pointer in the delay slot. We can't,
1305 however, if any of these is true. */
1306 if (epilogue_delay != NULL_RTX
1307 || !SMALL_INT (frame_size)
1309 || ARC_INTERRUPT_P (fn_type))
1311 /* Note that we restore fp and sp here! */
1312 fprintf (file, "\tld.a %s,[%s,%d]\n", fp_str, sp_str, frame_size);
1313 restored += frame_size;
1317 else if (!SMALL_INT (size /* frame_size + pretend_size */)
1318 || ARC_INTERRUPT_P (fn_type))
1320 fprintf (file, "\tadd %s,%s,%d\n", sp_str, sp_str, frame_size);
1321 restored += frame_size;
1324 /* These must be done before the return insn because the delay slot
1325 does the final stack restore. */
1326 if (ARC_INTERRUPT_P (fn_type))
1330 final_scan_insn (XEXP (epilogue_delay, 0), file, 1, -2, 1);
1334 /* Emit the return instruction. */
1336 static const int regs[4] = {
1337 0, RETURN_ADDR_REGNUM, ILINK1_REGNUM, ILINK2_REGNUM
1339 fprintf (file, "\tj.d %s\n", reg_names[regs[fn_type]]);
1342 /* If the only register saved is the return address, we need a
1343 nop, unless we have an instruction to put into it. Otherwise
1344 we don't since reloading multiple registers doesn't reference
1345 the register being loaded. */
1347 if (ARC_INTERRUPT_P (fn_type))
1348 fprintf (file, "\tadd %s,%s,16\n", sp_str, sp_str);
1349 else if (epilogue_delay != NULL_RTX)
1351 if (frame_pointer_needed && !fp_restored_p)
1353 if (restored < size)
1355 final_scan_insn (XEXP (epilogue_delay, 0), file, 1, -2, 1);
1357 else if (frame_pointer_needed && !fp_restored_p)
1359 if (!SMALL_INT (frame_size))
1361 /* Note that we restore fp and sp here! */
1362 fprintf (file, "\tld.a %s,[%s,%d]\n", fp_str, sp_str, frame_size);
1364 else if (restored < size)
1366 if (!SMALL_INT (size - restored))
1368 fprintf (file, "\tadd %s,%s,%d\n",
1369 sp_str, sp_str, size - restored);
1372 fprintf (file, "\tnop\n");
1375 /* Reset state info for each function. */
1376 current_frame_info = zero_frame_info;
1377 arc_compute_function_type (NULL_TREE);
1380 /* Define the number of delay slots needed for the function epilogue.
1382 Interrupt handlers can't have any epilogue delay slots (it's always needed
1383 for something else, I think). For normal functions, we have to worry about
1384 using call-saved regs as they'll be restored before the delay slot insn.
1385 Functions with non-empty frames already have enough choices for the epilogue
1386 delay slot so for now we only consider functions with empty frames. */
1389 arc_delay_slots_for_epilogue ()
1391 if (arc_compute_function_type (current_function_decl) != ARC_FUNCTION_NORMAL)
1393 if (!current_frame_info.initialized)
1394 (void) arc_compute_frame_size (get_frame_size ());
1395 if (current_frame_info.total_size == 0)
1400 /* Return true if TRIAL is a valid insn for the epilogue delay slot.
1401 Any single length instruction which doesn't reference the stack or frame
1402 pointer or any call-saved register is OK. SLOT will always be 0. */
1405 arc_eligible_for_epilogue_delay (trial, slot)
1412 if (get_attr_length (trial) == 1
1413 /* If registers where saved, presumably there's more than enough
1414 possibilities for the delay slot. The alternative is something
1415 more complicated (of course, if we expanded the epilogue as rtl
1416 this problem would go away). */
1417 /* ??? Note that this will always be true since only functions with
1418 empty frames have epilogue delay slots. See
1419 arc_delay_slots_for_epilogue. */
1420 && current_frame_info.gmask == 0
1421 && ! reg_mentioned_p (stack_pointer_rtx, PATTERN (trial))
1422 && ! reg_mentioned_p (frame_pointer_rtx, PATTERN (trial)))
1429 /* Emit special PIC prologues and epilogues. */
1437 /* Return true if OP is a shift operator. */
1440 shift_operator (op, mode)
1442 enum machine_mode mode ATTRIBUTE_UNUSED;
1444 switch (GET_CODE (op))
1455 /* Output the assembler code for doing a shift.
1456 We go to a bit of trouble to generate efficient code as the ARC only has
1457 single bit shifts. This is taken from the h8300 port. We only have one
1458 mode of shifting and can't access individual bytes like the h8300 can, so
1459 this is greatly simplified (at the expense of not generating hyper-
1462 This function is not used if the variable shift insns are present. */
1464 /* ??? We assume the output operand is the same as operand 1.
1465 This can be optimized (deleted) in the case of 1 bit shifts. */
1466 /* ??? We use the loop register here. We don't use it elsewhere (yet) and
1467 using it here will give us a chance to play with it. */
1470 output_shift (operands)
1473 rtx shift = operands[3];
1474 enum machine_mode mode = GET_MODE (shift);
1475 enum rtx_code code = GET_CODE (shift);
1476 const char *shift_one;
1483 case ASHIFT: shift_one = "asl %0,%0"; break;
1484 case ASHIFTRT: shift_one = "asr %0,%0"; break;
1485 case LSHIFTRT: shift_one = "lsr %0,%0"; break;
1489 if (GET_CODE (operands[2]) != CONST_INT)
1492 output_asm_insn ("mov lp_count,%2", operands);
1494 output_asm_insn ("mov %4,%2", operands);
1499 int n = INTVAL (operands[2]);
1501 /* If the count is negative, make it 0. */
1504 /* If the count is too big, truncate it.
1505 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
1506 do the intuitive thing. */
1507 else if (n > GET_MODE_BITSIZE (mode))
1508 n = GET_MODE_BITSIZE (mode);
1510 /* First see if we can do them inline. */
1514 output_asm_insn (shift_one, operands);
1516 /* See if we can use a rotate/and. */
1517 else if (n == BITS_PER_WORD - 1)
1522 output_asm_insn ("and %0,%0,1\n\tror %0,%0", operands);
1525 /* The ARC doesn't have a rol insn. Use something else. */
1526 output_asm_insn ("asl.f 0,%0\n\tsbc %0,0,0", operands);
1529 /* The ARC doesn't have a rol insn. Use something else. */
1530 output_asm_insn ("asl.f 0,%0\n\tadc %0,0,0", operands);
1542 output_asm_insn ("mov lp_count,%c2", operands);
1544 output_asm_insn ("mov %4,%c2", operands);
1549 sprintf (buf, "lr %%4,[status]\n\tadd %%4,%%4,6\t%s single insn loop start",
1552 sprintf (buf, "mov %%4,%%%%st(1f)\t%s (single insn loop start) >> 2",
1554 output_asm_insn (buf, operands);
1555 output_asm_insn ("sr %4,[lp_start]", operands);
1556 output_asm_insn ("add %4,%4,1", operands);
1557 output_asm_insn ("sr %4,[lp_end]", operands);
1558 output_asm_insn ("nop\n\tnop", operands);
1560 asm_fprintf (asm_out_file, "\t%s single insn loop\n",
1563 asm_fprintf (asm_out_file, "1:\t%s single insn loop\n",
1565 output_asm_insn (shift_one, operands);
1569 asm_fprintf (asm_out_file, "1:\t%s begin shift loop\n",
1571 output_asm_insn ("sub.f %4,%4,1", operands);
1572 output_asm_insn ("nop", operands);
1573 output_asm_insn ("bn.nd 2f", operands);
1574 output_asm_insn (shift_one, operands);
1575 output_asm_insn ("b.nd 1b", operands);
1576 asm_fprintf (asm_out_file, "2:\t%s end shift loop\n",
1585 /* Nested function support. */
1587 /* Emit RTL insns to initialize the variable parts of a trampoline.
1588 FNADDR is an RTX for the address of the function's pure code.
1589 CXT is an RTX for the static chain value for the function. */
1592 arc_initialize_trampoline (tramp, fnaddr, cxt)
1593 rtx tramp ATTRIBUTE_UNUSED, fnaddr ATTRIBUTE_UNUSED, cxt ATTRIBUTE_UNUSED;
1597 /* Set the cpu type and print out other fancy things,
1598 at the top of the file. */
1601 arc_asm_file_start (file)
1604 fprintf (file, "\t.cpu %s\n", arc_cpu_string);
1607 /* Print operand X (an rtx) in assembler syntax to file FILE.
1608 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1609 For `%' followed by punctuation, CODE is the punctuation and X is null. */
1612 arc_print_operand (file, x, code)
1620 /* Conditional branches. For now these are equivalent. */
1622 /* Unconditional branches. Output the appropriate delay slot suffix. */
1623 if (!final_sequence || XVECLEN (final_sequence, 0) == 1)
1625 /* There's nothing in the delay slot. */
1626 fputs (".nd", file);
1630 rtx jump = XVECEXP (final_sequence, 0, 0);
1631 rtx delay = XVECEXP (final_sequence, 0, 1);
1632 if (INSN_ANNULLED_BRANCH_P (jump))
1633 fputs (INSN_FROM_TARGET_P (delay) ? ".jd" : ".nd", file);
1638 case '?' : /* with leading "." */
1639 case '!' : /* without leading "." */
1640 /* This insn can be conditionally executed. See if the ccfsm machinery
1641 says it should be conditionalized. */
1642 if (arc_ccfsm_state == 3 || arc_ccfsm_state == 4)
1644 /* Is this insn in a delay slot? */
1645 if (final_sequence && XVECLEN (final_sequence, 0) == 2)
1647 rtx insn = XVECEXP (final_sequence, 0, 1);
1649 /* If the insn is annulled and is from the target path, we need
1650 to inverse the condition test. */
1651 if (INSN_ANNULLED_BRANCH_P (insn))
1653 if (INSN_FROM_TARGET_P (insn))
1654 fprintf (file, "%s%s",
1655 code == '?' ? "." : "",
1656 arc_condition_codes[ARC_INVERSE_CONDITION_CODE (arc_ccfsm_current_cc)]);
1658 fprintf (file, "%s%s",
1659 code == '?' ? "." : "",
1660 arc_condition_codes[arc_ccfsm_current_cc]);
1664 /* This insn is executed for either path, so don't
1665 conditionalize it at all. */
1666 ; /* nothing to do */
1671 /* This insn isn't in a delay slot. */
1672 fprintf (file, "%s%s",
1673 code == '?' ? "." : "",
1674 arc_condition_codes[arc_ccfsm_current_cc]);
1679 /* Output a nop if we're between a set of the condition codes,
1680 and a conditional branch. */
1681 if (last_insn_set_cc_p)
1682 fputs ("nop\n\t", file);
1685 fputs (arc_condition_codes[get_arc_condition_code (x)], file);
1688 fputs (arc_condition_codes[ARC_INVERSE_CONDITION_CODE
1689 (get_arc_condition_code (x))],
1693 /* Write second word of DImode or DFmode reference,
1694 register or memory. */
1695 if (GET_CODE (x) == REG)
1696 fputs (reg_names[REGNO (x)+1], file);
1697 else if (GET_CODE (x) == MEM)
1700 /* Handle possible auto-increment. Since it is pre-increment and
1701 we have already done it, we can just use an offset of four. */
1702 /* ??? This is taken from rs6000.c I think. I don't think it is
1703 currently necessary, but keep it around. */
1704 if (GET_CODE (XEXP (x, 0)) == PRE_INC
1705 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
1706 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 4));
1708 output_address (plus_constant (XEXP (x, 0), 4));
1712 output_operand_lossage ("invalid operand to %%R code");
1715 if ((GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_FLAG (x))
1716 || GET_CODE (x) == LABEL_REF)
1718 fprintf (file, "%%st(");
1719 output_addr_const (file, x);
1720 fprintf (file, ")");
1726 if (GET_CODE (x) == REG)
1728 /* L = least significant word, H = most significant word */
1729 if ((TARGET_BIG_ENDIAN != 0) ^ (code == 'L'))
1730 fputs (reg_names[REGNO (x)], file);
1732 fputs (reg_names[REGNO (x)+1], file);
1734 else if (GET_CODE (x) == CONST_INT
1735 || GET_CODE (x) == CONST_DOUBLE)
1739 split_double (x, &first, &second);
1740 fprintf (file, "0x%08lx",
1741 (long)(code == 'L' ? INTVAL (first) : INTVAL (second)));
1744 output_operand_lossage ("invalid operand to %%H/%%L code");
1751 if (GET_CODE (x) != CONST_DOUBLE
1752 || GET_MODE_CLASS (GET_MODE (x)) != MODE_FLOAT)
1754 REAL_VALUE_FROM_CONST_DOUBLE (d, x);
1755 REAL_VALUE_TO_DECIMAL (d, "%.20e", str);
1756 fprintf (file, "%s", str);
1760 /* Output a load/store with update indicator if appropriate. */
1761 if (GET_CODE (x) == MEM)
1763 if (GET_CODE (XEXP (x, 0)) == PRE_INC
1764 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
1768 output_operand_lossage ("invalid operand to %%U code");
1771 /* Output cache bypass indicator for a load/store insn. Volatile memory
1772 refs are defined to use the cache bypass mechanism. */
1773 if (GET_CODE (x) == MEM)
1775 if (MEM_VOLATILE_P (x))
1776 fputs (".di", file);
1779 output_operand_lossage ("invalid operand to %%V code");
1782 /* Do nothing special. */
1786 output_operand_lossage ("invalid operand output code");
1789 switch (GET_CODE (x))
1792 fputs (reg_names[REGNO (x)], file);
1796 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
1797 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
1798 GET_MODE_SIZE (GET_MODE (x))));
1799 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
1800 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
1801 - GET_MODE_SIZE (GET_MODE (x))));
1803 output_address (XEXP (x, 0));
1807 /* We handle SFmode constants here as output_addr_const doesn't. */
1808 if (GET_MODE (x) == SFmode)
1813 REAL_VALUE_FROM_CONST_DOUBLE (d, x);
1814 REAL_VALUE_TO_TARGET_SINGLE (d, l);
1815 fprintf (file, "0x%08lx", l);
1818 /* Fall through. Let output_addr_const deal with it. */
1820 output_addr_const (file, x);
1825 /* Print a memory address as an operand to reference that memory location. */
1828 arc_print_operand_address (file, addr)
1832 register rtx base, index = 0;
1835 switch (GET_CODE (addr))
1838 fputs (reg_names[REGNO (addr)], file);
1841 if (/*???*/ 0 && SYMBOL_REF_FLAG (addr))
1843 fprintf (file, "%%st(");
1844 output_addr_const (file, addr);
1845 fprintf (file, ")");
1848 output_addr_const (file, addr);
1851 if (GET_CODE (XEXP (addr, 0)) == CONST_INT)
1852 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);
1853 else if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
1854 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);
1856 base = XEXP (addr, 0), index = XEXP (addr, 1);
1857 if (GET_CODE (base) != REG)
1859 fputs (reg_names[REGNO (base)], file);
1863 fprintf (file, ",%d", offset);
1865 else if (GET_CODE (index) == REG)
1866 fprintf (file, ",%s", reg_names[REGNO (index)]);
1867 else if (GET_CODE (index) == SYMBOL_REF)
1868 fputc (',', file), output_addr_const (file, index);
1874 /* We shouldn't get here as we've lost the mode of the memory object
1875 (which says how much to inc/dec by. */
1879 output_addr_const (file, addr);
1884 /* Update compare/branch separation marker. */
1887 record_cc_ref (insn)
1890 last_insn_set_cc_p = current_insn_set_cc_p;
1892 switch (get_attr_cond (insn))
1897 if (get_attr_length (insn) == 1)
1898 current_insn_set_cc_p = 1;
1900 current_insn_set_cc_p = 0;
1903 current_insn_set_cc_p = 0;
1908 /* Conditional execution support.
1910 This is based on the ARM port but for now is much simpler.
1912 A finite state machine takes care of noticing whether or not instructions
1913 can be conditionally executed, and thus decrease execution time and code
1914 size by deleting branch instructions. The fsm is controlled by
1915 final_prescan_insn, and controls the actions of PRINT_OPERAND. The patterns
1916 in the .md file for the branch insns also have a hand in this. */
1918 /* The state of the fsm controlling condition codes are:
1919 0: normal, do nothing special
1920 1: don't output this insn
1921 2: don't output this insn
1922 3: make insns conditional
1923 4: make insns conditional
1925 State transitions (state->state by whom, under what condition):
1926 0 -> 1 final_prescan_insn, if insn is conditional branch
1927 0 -> 2 final_prescan_insn, if the `target' is an unconditional branch
1928 1 -> 3 branch patterns, after having not output the conditional branch
1929 2 -> 4 branch patterns, after having not output the conditional branch
1930 3 -> 0 ASM_OUTPUT_INTERNAL_LABEL, if the `target' label is reached
1931 (the target label has CODE_LABEL_NUMBER equal to
1932 arc_ccfsm_target_label).
1933 4 -> 0 final_prescan_insn, if `target' unconditional branch is reached
1935 If the jump clobbers the conditions then we use states 2 and 4.
1937 A similar thing can be done with conditional return insns.
1939 We also handle separating branches from sets of the condition code.
1940 This is done here because knowledge of the ccfsm state is required,
1941 we may not be outputting the branch. */
1944 arc_final_prescan_insn (insn, opvec, noperands)
1946 rtx *opvec ATTRIBUTE_UNUSED;
1947 int noperands ATTRIBUTE_UNUSED;
1949 /* BODY will hold the body of INSN. */
1950 register rtx body = PATTERN (insn);
1952 /* This will be 1 if trying to repeat the trick (ie: do the `else' part of
1953 an if/then/else), and things need to be reversed. */
1956 /* If we start with a return insn, we only succeed if we find another one. */
1957 int seeking_return = 0;
1959 /* START_INSN will hold the insn from where we start looking. This is the
1960 first insn after the following code_label if REVERSE is true. */
1961 rtx start_insn = insn;
1963 /* Update compare/branch separation marker. */
1964 record_cc_ref (insn);
1966 /* Allow -mdebug-ccfsm to turn this off so we can see how well it does.
1967 We can't do this in macro FINAL_PRESCAN_INSN because its called from
1968 final_scan_insn which has `optimize' as a local. */
1969 if (optimize < 2 || TARGET_NO_COND_EXEC)
1972 /* If in state 4, check if the target branch is reached, in order to
1973 change back to state 0. */
1974 if (arc_ccfsm_state == 4)
1976 if (insn == arc_ccfsm_target_insn)
1978 arc_ccfsm_target_insn = NULL;
1979 arc_ccfsm_state = 0;
1984 /* If in state 3, it is possible to repeat the trick, if this insn is an
1985 unconditional branch to a label, and immediately following this branch
1986 is the previous target label which is only used once, and the label this
1987 branch jumps to is not too far off. Or in other words "we've done the
1988 `then' part, see if we can do the `else' part." */
1989 if (arc_ccfsm_state == 3)
1991 if (simplejump_p (insn))
1993 start_insn = next_nonnote_insn (start_insn);
1994 if (GET_CODE (start_insn) == BARRIER)
1996 /* ??? Isn't this always a barrier? */
1997 start_insn = next_nonnote_insn (start_insn);
1999 if (GET_CODE (start_insn) == CODE_LABEL
2000 && CODE_LABEL_NUMBER (start_insn) == arc_ccfsm_target_label
2001 && LABEL_NUSES (start_insn) == 1)
2006 else if (GET_CODE (body) == RETURN)
2008 start_insn = next_nonnote_insn (start_insn);
2009 if (GET_CODE (start_insn) == BARRIER)
2010 start_insn = next_nonnote_insn (start_insn);
2011 if (GET_CODE (start_insn) == CODE_LABEL
2012 && CODE_LABEL_NUMBER (start_insn) == arc_ccfsm_target_label
2013 && LABEL_NUSES (start_insn) == 1)
2025 if (GET_CODE (insn) != JUMP_INSN)
2028 /* This jump might be paralleled with a clobber of the condition codes,
2029 the jump should always come first. */
2030 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0)
2031 body = XVECEXP (body, 0, 0);
2034 || (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC
2035 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE))
2037 int insns_skipped = 0, fail = FALSE, succeed = FALSE;
2038 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
2039 int then_not_else = TRUE;
2040 /* Nonzero if next insn must be the target label. */
2041 int next_must_be_target_label_p;
2042 rtx this_insn = start_insn, label = 0;
2044 /* Register the insn jumped to. */
2047 if (!seeking_return)
2048 label = XEXP (SET_SRC (body), 0);
2050 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == LABEL_REF)
2051 label = XEXP (XEXP (SET_SRC (body), 1), 0);
2052 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == LABEL_REF)
2054 label = XEXP (XEXP (SET_SRC (body), 2), 0);
2055 then_not_else = FALSE;
2057 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN)
2059 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN)
2062 then_not_else = FALSE;
2067 /* See how many insns this branch skips, and what kind of insns. If all
2068 insns are okay, and the label or unconditional branch to the same
2069 label is not too far away, succeed. */
2070 for (insns_skipped = 0, next_must_be_target_label_p = FALSE;
2071 !fail && !succeed && insns_skipped < MAX_INSNS_SKIPPED;
2076 this_insn = next_nonnote_insn (this_insn);
2080 if (next_must_be_target_label_p)
2082 if (GET_CODE (this_insn) == BARRIER)
2084 if (GET_CODE (this_insn) == CODE_LABEL
2085 && this_insn == label)
2087 arc_ccfsm_state = 1;
2095 scanbody = PATTERN (this_insn);
2097 switch (GET_CODE (this_insn))
2100 /* Succeed if it is the target label, otherwise fail since
2101 control falls in from somewhere else. */
2102 if (this_insn == label)
2104 arc_ccfsm_state = 1;
2112 /* Succeed if the following insn is the target label.
2114 If return insns are used then the last insn in a function
2115 will be a barrier. */
2116 next_must_be_target_label_p = TRUE;
2120 /* Can handle a call insn if there are no insns after it.
2121 IE: The next "insn" is the target label. We don't have to
2122 worry about delay slots as such insns are SEQUENCE's inside
2123 INSN's. ??? It is possible to handle such insns though. */
2124 if (get_attr_cond (this_insn) == COND_CANUSE)
2125 next_must_be_target_label_p = TRUE;
2131 /* If this is an unconditional branch to the same label, succeed.
2132 If it is to another label, do nothing. If it is conditional,
2134 /* ??? Probably, the test for the SET and the PC are unnecessary. */
2136 if (GET_CODE (scanbody) == SET
2137 && GET_CODE (SET_DEST (scanbody)) == PC)
2139 if (GET_CODE (SET_SRC (scanbody)) == LABEL_REF
2140 && XEXP (SET_SRC (scanbody), 0) == label && !reverse)
2142 arc_ccfsm_state = 2;
2145 else if (GET_CODE (SET_SRC (scanbody)) == IF_THEN_ELSE)
2148 else if (GET_CODE (scanbody) == RETURN
2151 arc_ccfsm_state = 2;
2154 else if (GET_CODE (scanbody) == PARALLEL)
2156 if (get_attr_cond (this_insn) != COND_CANUSE)
2162 /* We can only do this with insns that can use the condition
2163 codes (and don't set them). */
2164 if (GET_CODE (scanbody) == SET
2165 || GET_CODE (scanbody) == PARALLEL)
2167 if (get_attr_cond (this_insn) != COND_CANUSE)
2170 /* We can't handle other insns like sequences. */
2182 if ((!seeking_return) && (arc_ccfsm_state == 1 || reverse))
2183 arc_ccfsm_target_label = CODE_LABEL_NUMBER (label);
2184 else if (seeking_return || arc_ccfsm_state == 2)
2186 while (this_insn && GET_CODE (PATTERN (this_insn)) == USE)
2188 this_insn = next_nonnote_insn (this_insn);
2189 if (this_insn && (GET_CODE (this_insn) == BARRIER
2190 || GET_CODE (this_insn) == CODE_LABEL))
2195 /* Oh dear! we ran off the end, give up. */
2196 extract_insn_cached (insn);
2197 arc_ccfsm_state = 0;
2198 arc_ccfsm_target_insn = NULL;
2201 arc_ccfsm_target_insn = this_insn;
2206 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
2209 arc_ccfsm_current_cc = get_arc_condition_code (XEXP (SET_SRC (body),
2212 if (reverse || then_not_else)
2213 arc_ccfsm_current_cc = ARC_INVERSE_CONDITION_CODE (arc_ccfsm_current_cc);
2216 /* Restore recog_data. Getting the attributes of other insns can
2217 destroy this array, but final.c assumes that it remains intact
2218 across this call. */
2219 extract_insn_cached (insn);
2223 /* Record that we are currently outputting label NUM with prefix PREFIX.
2224 It it's the label we're looking for, reset the ccfsm machinery.
2226 Called from ASM_OUTPUT_INTERNAL_LABEL. */
2229 arc_ccfsm_at_label (prefix, num)
2233 if (arc_ccfsm_state == 3 && arc_ccfsm_target_label == num
2234 && !strcmp (prefix, "L"))
2236 arc_ccfsm_state = 0;
2237 arc_ccfsm_target_insn = NULL_RTX;
2241 /* See if the current insn, which is a conditional branch, is to be
2245 arc_ccfsm_branch_deleted_p ()
2247 if (arc_ccfsm_state == 1 || arc_ccfsm_state == 2)
2252 /* Record a branch isn't output because subsequent insns can be
2256 arc_ccfsm_record_branch_deleted ()
2258 /* Indicate we're conditionalizing insns now. */
2259 arc_ccfsm_state += 2;
2261 /* If the next insn is a subroutine call, we still need a nop between the
2262 cc setter and user. We need to undo the effect of calling record_cc_ref
2263 for the just deleted branch. */
2264 current_insn_set_cc_p = last_insn_set_cc_p;
2268 arc_va_start (stdarg_p, valist, nextarg)
2273 /* See arc_setup_incoming_varargs for reasons for this oddity. */
2274 if (current_function_args_info < 8
2275 && (current_function_args_info & 1))
2276 nextarg = plus_constant (nextarg, UNITS_PER_WORD);
2278 std_expand_builtin_va_start (stdarg_p, valist, nextarg);
2282 arc_va_arg (valist, type)
2287 tree type_ptr = build_pointer_type (type);
2289 /* All aggregates are passed by reference. All scalar types larger
2290 than 8 bytes are passed by reference. */
2292 if (AGGREGATE_TYPE_P (type) || int_size_in_bytes (type) > 8)
2294 tree type_ptr_ptr = build_pointer_type (type_ptr);
2296 addr = build (INDIRECT_REF, type_ptr,
2297 build (NOP_EXPR, type_ptr_ptr, valist));
2299 incr = build (PLUS_EXPR, TREE_TYPE (valist),
2300 valist, build_int_2 (UNITS_PER_WORD, 0));
2304 HOST_WIDE_INT align, rounded_size;
2306 /* Compute the rounded size of the type. */
2307 align = PARM_BOUNDARY / BITS_PER_UNIT;
2308 rounded_size = (((TREE_INT_CST_LOW (TYPE_SIZE (type)) / BITS_PER_UNIT
2309 + align - 1) / align) * align);
2311 /* Align 8 byte operands. */
2313 if (TYPE_ALIGN (type) > BITS_PER_WORD)
2315 /* AP = (TYPE *)(((int)AP + 7) & -8) */
2317 addr = build (NOP_EXPR, integer_type_node, valist);
2318 addr = fold (build (PLUS_EXPR, integer_type_node, addr,
2319 build_int_2 (7, 0)));
2320 addr = fold (build (BIT_AND_EXPR, integer_type_node, addr,
2321 build_int_2 (-8, 0)));
2322 addr = fold (build (NOP_EXPR, TREE_TYPE (valist), addr));
2325 /* The increment is always rounded_size past the aligned pointer. */
2326 incr = fold (build (PLUS_EXPR, TREE_TYPE (addr), addr,
2327 build_int_2 (rounded_size, 0)));
2329 /* Adjust the pointer in big-endian mode. */
2330 if (BYTES_BIG_ENDIAN)
2333 adj = TREE_INT_CST_LOW (TYPE_SIZE (type)) / BITS_PER_UNIT;
2334 if (rounded_size > align)
2337 addr = fold (build (PLUS_EXPR, TREE_TYPE (addr), addr,
2338 build_int_2 (rounded_size - adj, 0)));
2342 /* Evaluate the data address. */
2343 addr_rtx = expand_expr (addr, NULL_RTX, Pmode, EXPAND_NORMAL);
2344 addr_rtx = copy_to_reg (addr_rtx);
2346 /* Compute new value for AP. */
2347 incr = build (MODIFY_EXPR, TREE_TYPE (valist), valist, incr);
2348 TREE_SIDE_EFFECTS (incr) = 1;
2349 expand_expr (incr, const0_rtx, VOIDmode, EXPAND_NORMAL);
2354 /* On the ARC, function addresses are not the same as normal addresses.
2355 Branch to absolute address insns take an address that is right-shifted
2356 by 2. We encode the fact that we have a function here, and then emit a
2357 special assembler op when outputting the address. */
2360 arc_encode_section_info (decl, first)
2362 int first ATTRIBUTE_UNUSED;
2364 if (TREE_CODE (decl) == FUNCTION_DECL)
2365 SYMBOL_REF_FLAG (XEXP (DECL_RTL (decl), 0)) = 1;