1 ;; Machine description for DEC Alpha for GNU C compiler
2 ;; Copyright (C) 1992, 93-98, 1999 Free Software Foundation, Inc.
3 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 ;; This file is part of GNU CC.
7 ;; GNU CC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 2, or (at your option)
12 ;; GNU CC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GNU CC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
20 ;; Boston, MA 02111-1307, USA.
22 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
24 ;; Uses of UNSPEC in this file:
37 ;; 2 builtin_setjmp_receiver
40 ;; 5 prologue_stack_probe_loop
42 ;; 7 exception_receiver
44 ;; Processor type -- this attribute must exactly match the processor_type
45 ;; enumeration in alpha.h.
47 (define_attr "cpu" "ev4,ev5,ev6"
48 (const (symbol_ref "alpha_cpu")))
50 ;; Define an insn type attribute. This is used in function unit delay
51 ;; computations, among other purposes. For the most part, we use the names
52 ;; defined in the EV4 documentation, but add a few that we have to know about
56 "ild,fld,ldsym,ist,fst,ibr,fbr,jsr,iadd,ilog,shift,icmov,fcmov,icmp,imul,fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi"
57 (const_string "iadd"))
59 ;; Describe a user's asm statement.
60 (define_asm_attributes
61 [(set_attr "type" "multi")])
63 ;; Define the operand size an insn operates on. Used primarily by mul
64 ;; and div operations that have size dependant timings.
66 (define_attr "opsize" "si,di,udi" (const_string "di"))
68 ;; The TRAP_TYPE attribute marks instructions that may generate traps
69 ;; (which are imprecise and may need a trapb if software completion
72 (define_attr "trap" "no,yes" (const_string "no"))
74 ;; The length of an instruction sequence in bytes.
76 (define_attr "length" "" (const_int 4))
78 ;; On EV4 there are two classes of resources to consider: resources needed
79 ;; to issue, and resources needed to execute. IBUS[01] are in the first
80 ;; category. ABOX, BBOX, EBOX, FBOX, IMUL & FDIV make up the second.
81 ;; (There are a few other register-like resources, but ...)
83 ; First, describe all of the issue constraints with single cycle delays.
84 ; All insns need a bus, but all except loads require one or the other.
85 (define_function_unit "ev4_ibus0" 1 0
86 (and (eq_attr "cpu" "ev4")
87 (eq_attr "type" "fst,fbr,iadd,imul,ilog,shift,icmov,icmp"))
90 (define_function_unit "ev4_ibus1" 1 0
91 (and (eq_attr "cpu" "ev4")
92 (eq_attr "type" "ist,ibr,jsr,fadd,fcmov,fcpys,fmul,fdiv,misc"))
95 ; Memory delivers its result in three cycles. Actually return one and
96 ; take care of this in adjust_cost, since we want to handle user-defined
98 (define_function_unit "ev4_abox" 1 0
99 (and (eq_attr "cpu" "ev4")
100 (eq_attr "type" "ild,fld,ldsym,ist,fst"))
103 ; Branches have no delay cost, but do tie up the unit for two cycles.
104 (define_function_unit "ev4_bbox" 1 1
105 (and (eq_attr "cpu" "ev4")
106 (eq_attr "type" "ibr,fbr,jsr"))
109 ; Arithmetic insns are normally have their results available after
110 ; two cycles. There are a number of exceptions. They are encoded in
111 ; ADJUST_COST. Some of the other insns have similar exceptions.
112 (define_function_unit "ev4_ebox" 1 0
113 (and (eq_attr "cpu" "ev4")
114 (eq_attr "type" "iadd,ilog,shift,icmov,icmp,misc"))
117 (define_function_unit "imul" 1 0
118 (and (eq_attr "cpu" "ev4")
119 (and (eq_attr "type" "imul")
120 (eq_attr "opsize" "si")))
123 (define_function_unit "imul" 1 0
124 (and (eq_attr "cpu" "ev4")
125 (and (eq_attr "type" "imul")
126 (eq_attr "opsize" "!si")))
129 (define_function_unit "ev4_fbox" 1 0
130 (and (eq_attr "cpu" "ev4")
131 (eq_attr "type" "fadd,fmul,fcpys,fcmov"))
134 (define_function_unit "fdiv" 1 0
135 (and (eq_attr "cpu" "ev4")
136 (and (eq_attr "type" "fdiv")
137 (eq_attr "opsize" "si")))
140 (define_function_unit "fdiv" 1 0
141 (and (eq_attr "cpu" "ev4")
142 (and (eq_attr "type" "fdiv")
143 (eq_attr "opsize" "di")))
146 ;; EV5 scheduling. EV5 can issue 4 insns per clock.
148 ;; EV5 has two asymetric integer units. Model this with E0 & E1 along
149 ;; with the combined resource EBOX.
151 (define_function_unit "ev5_ebox" 2 0
152 (and (eq_attr "cpu" "ev5")
153 (eq_attr "type" "!fbr,fcmov,fadd,fmul,fcpys,fdiv"))
156 ; Memory takes at least 2 clocks. Return one from here and fix up with
157 ; user-defined latencies in adjust_cost.
158 (define_function_unit "ev5_ebox" 2 0
159 (and (eq_attr "cpu" "ev5")
160 (eq_attr "type" "ild,fld,ldsym"))
163 ; Loads can dual issue with one another, but loads and stores do not mix.
164 (define_function_unit "ev5_e0" 1 0
165 (and (eq_attr "cpu" "ev5")
166 (eq_attr "type" "ild,fld,ldsym"))
168 [(eq_attr "type" "ist,fst")])
170 ; Stores, shifts, multiplies can only issue to E0
171 (define_function_unit "ev5_e0" 1 0
172 (and (eq_attr "cpu" "ev5")
173 (eq_attr "type" "ist,fst,shift,imul"))
176 ; Motion video insns also issue only to E0, and take two ticks.
177 (define_function_unit "ev5_e0" 1 0
178 (and (eq_attr "cpu" "ev5")
179 (eq_attr "type" "mvi"))
182 ; Conditional moves always take 2 ticks.
183 (define_function_unit "ev5_ebox" 2 0
184 (and (eq_attr "cpu" "ev5")
185 (eq_attr "type" "icmov"))
188 ; Branches can only issue to E1
189 (define_function_unit "ev5_e1" 1 0
190 (and (eq_attr "cpu" "ev5")
191 (eq_attr "type" "ibr,jsr"))
194 ; Multiplies also use the integer multiplier.
195 ; ??? How to: "No instruction can be issued to pipe E0 exactly two
196 ; cycles before an integer multiplication completes."
197 (define_function_unit "imul" 1 0
198 (and (eq_attr "cpu" "ev5")
199 (and (eq_attr "type" "imul")
200 (eq_attr "opsize" "si")))
203 (define_function_unit "imul" 1 0
204 (and (eq_attr "cpu" "ev5")
205 (and (eq_attr "type" "imul")
206 (eq_attr "opsize" "di")))
209 (define_function_unit "imul" 1 0
210 (and (eq_attr "cpu" "ev5")
211 (and (eq_attr "type" "imul")
212 (eq_attr "opsize" "udi")))
215 ;; Similarly for the FPU we have two asymetric units. But fcpys can issue
216 ;; on either so we have to play the game again.
218 (define_function_unit "ev5_fbox" 2 0
219 (and (eq_attr "cpu" "ev5")
220 (eq_attr "type" "fadd,fcmov,fmul,fcpys,fbr,fdiv"))
223 (define_function_unit "ev5_fm" 1 0
224 (and (eq_attr "cpu" "ev5")
225 (eq_attr "type" "fmul"))
228 ; Add and cmov as you would expect; fbr never produces a result;
229 ; fdiv issues through fa to the divider,
230 (define_function_unit "ev5_fa" 1 0
231 (and (eq_attr "cpu" "ev5")
232 (eq_attr "type" "fadd,fcmov,fbr,fdiv"))
235 ; ??? How to: "No instruction can be issued to pipe FA exactly five
236 ; cycles before a floating point divide completes."
237 (define_function_unit "fdiv" 1 0
238 (and (eq_attr "cpu" "ev5")
239 (and (eq_attr "type" "fdiv")
240 (eq_attr "opsize" "si")))
241 15 15) ; 15 to 31 data dependant
243 (define_function_unit "fdiv" 1 0
244 (and (eq_attr "cpu" "ev5")
245 (and (eq_attr "type" "fdiv")
246 (eq_attr "opsize" "di")))
247 22 22) ; 22 to 60 data dependant
249 ;; EV6 scheduling. EV6 can issue 4 insns per clock.
251 ;; EV6 has two symmetric pairs ("clusters") of two asymetric integer units
252 ;; ("upper" and "lower"), yielding pipe names U0, U1, L0, L1.
254 ;; Conditional moves decompose into two independant primitives, each
255 ;; taking one cycle. Since ev6 is out-of-order, we can't see anything
257 (define_function_unit "ev6_ebox" 4 0
258 (and (eq_attr "cpu" "ev6")
259 (eq_attr "type" "icmov"))
262 (define_function_unit "ev6_ebox" 4 0
263 (and (eq_attr "cpu" "ev6")
264 (eq_attr "type" "!fbr,fcmov,fadd,fmul,fcpys,fdiv,fsqrt"))
267 ;; Integer loads take at least 3 clocks, and only issue to lower units.
268 ;; Return one from here and fix up with user-defined latencies in adjust_cost.
269 (define_function_unit "ev6_l" 2 0
270 (and (eq_attr "cpu" "ev6")
271 (eq_attr "type" "ild,ldsym,ist,fst"))
274 ;; FP loads take at least 4 clocks. Return two from here...
275 (define_function_unit "ev6_l" 2 0
276 (and (eq_attr "cpu" "ev6")
277 (eq_attr "type" "fld"))
280 ;; Motion video insns also issue only to U0, and take three ticks.
281 (define_function_unit "ev6_u0" 1 0
282 (and (eq_attr "cpu" "ev6")
283 (eq_attr "type" "mvi"))
286 (define_function_unit "ev6_u" 2 0
287 (and (eq_attr "cpu" "ev6")
288 (eq_attr "type" "mvi"))
291 ;; Shifts issue to either upper pipe.
292 (define_function_unit "ev6_u" 2 0
293 (and (eq_attr "cpu" "ev6")
294 (eq_attr "type" "shift"))
297 ;; Multiplies issue only to U1, and all take 7 ticks.
298 ;; Rather than create a new function unit just for U1, reuse IMUL
299 (define_function_unit "imul" 1 0
300 (and (eq_attr "cpu" "ev6")
301 (eq_attr "type" "imul"))
304 (define_function_unit "ev6_u" 2 0
305 (and (eq_attr "cpu" "ev6")
306 (eq_attr "type" "imul"))
309 ;; Branches issue to either upper pipe
310 (define_function_unit "ev6_u" 2 0
311 (and (eq_attr "cpu" "ev6")
312 (eq_attr "type" "ibr"))
315 ;; Calls only issue to L0.
316 (define_function_unit "ev6_l0" 1 0
317 (and (eq_attr "cpu" "ev6")
318 (eq_attr "type" "jsr"))
321 (define_function_unit "ev6_l" 2 0
322 (and (eq_attr "cpu" "ev6")
323 (eq_attr "type" "jsr"))
326 ;; Ftoi/itof only issue to lower pipes
327 (define_function_unit "ev6_l" 2 0
328 (and (eq_attr "cpu" "ev6")
329 (eq_attr "type" "ftoi"))
332 (define_function_unit "ev6_l" 2 0
333 (and (eq_attr "cpu" "ev6")
334 (eq_attr "type" "itof"))
337 ;; For the FPU we are very similar to EV5, except there's no insn that
338 ;; can issue to fm & fa, so we get to leave that out.
340 (define_function_unit "ev6_fm" 1 0
341 (and (eq_attr "cpu" "ev6")
342 (eq_attr "type" "fmul"))
345 (define_function_unit "ev6_fa" 1 0
346 (and (eq_attr "cpu" "ev6")
347 (eq_attr "type" "fadd,fcpys,fbr,fdiv,fsqrt"))
350 (define_function_unit "ev6_fa" 1 0
351 (and (eq_attr "cpu" "ev6")
352 (eq_attr "type" "fcmov"))
355 (define_function_unit "fdiv" 1 0
356 (and (eq_attr "cpu" "ev6")
357 (and (eq_attr "type" "fdiv")
358 (eq_attr "opsize" "si")))
361 (define_function_unit "fdiv" 1 0
362 (and (eq_attr "cpu" "ev6")
363 (and (eq_attr "type" "fdiv")
364 (eq_attr "opsize" "di")))
367 (define_function_unit "fsqrt" 1 0
368 (and (eq_attr "cpu" "ev6")
369 (and (eq_attr "type" "fsqrt")
370 (eq_attr "opsize" "si")))
373 (define_function_unit "fsqrt" 1 0
374 (and (eq_attr "cpu" "ev6")
375 (and (eq_attr "type" "fsqrt")
376 (eq_attr "opsize" "di")))
379 ; ??? The FPU communicates with memory and the integer register file
380 ; via two fp store units. We need a slot in the fst immediately, and
381 ; a slot in LOW after the operand data is ready. At which point the
382 ; data may be moved either to the store queue or the integer register
383 ; file and the insn retired.
386 ;; First define the arithmetic insns. Note that the 32-bit forms also
389 ;; Handle 32-64 bit extension from memory to a floating point register
390 ;; specially, since this ocurrs frequently in int->double conversions.
392 ;; Note that while we must retain the =f case in the insn for reload's
393 ;; benefit, it should be eliminated after reload, so we should never emit
394 ;; code for that case. But we don't reject the possibility.
396 (define_expand "extendsidi2"
397 [(set (match_operand:DI 0 "register_operand" "")
398 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
403 [(set (match_operand:DI 0 "register_operand" "=r,r,*f,?*f")
405 (match_operand:SI 1 "nonimmediate_operand" "r,m,*f,m")))]
411 lds %0,%1\;cvtlq %0,%0"
412 [(set_attr "type" "iadd,ild,fadd,fld")
413 (set_attr "length" "*,*,*,8")])
416 [(set (match_operand:DI 0 "register_operand" "=r,r,r,*f,?*f")
418 (match_operand:SI 1 "nonimmediate_operand" "r,m,*f,*f,m")))]
425 lds %0,%1\;cvtlq %0,%0"
426 [(set_attr "type" "iadd,ild,ftoi,fadd,fld")
427 (set_attr "length" "*,*,*,*,8")])
429 ;; Due to issues with CLASS_CANNOT_CHANGE_SIZE, we cannot use a subreg here.
431 [(set (match_operand:DI 0 "hard_fp_register_operand" "")
432 (sign_extend:DI (match_operand:SI 1 "memory_operand" "")))]
434 [(set (match_dup 2) (match_dup 1))
435 (set (match_dup 0) (sign_extend:DI (match_dup 2)))]
436 "operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]));")
438 ;; Do addsi3 the way expand_binop would do if we didn't have one. This
439 ;; generates better code. We have the anonymous addsi3 pattern below in
440 ;; case combine wants to make it.
441 (define_expand "addsi3"
442 [(set (match_operand:SI 0 "register_operand" "")
443 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "")
444 (match_operand:SI 2 "add_operand" "")))]
450 rtx op1 = gen_lowpart (DImode, operands[1]);
451 rtx op2 = gen_lowpart (DImode, operands[2]);
453 if (! cse_not_expected)
455 rtx tmp = gen_reg_rtx (DImode);
456 emit_insn (gen_adddi3 (tmp, op1, op2));
457 emit_move_insn (gen_lowpart (DImode, operands[0]), tmp);
460 emit_insn (gen_adddi3 (gen_lowpart (DImode, operands[0]), op1, op2));
466 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
467 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ")
468 (match_operand:SI 2 "add_operand" "rI,O,K,L")))]
477 [(set (match_operand:SI 0 "register_operand" "")
478 (plus:SI (match_operand:SI 1 "register_operand" "")
479 (match_operand:SI 2 "const_int_operand" "")))]
480 "! add_operand (operands[2], SImode)"
481 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
482 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
485 HOST_WIDE_INT val = INTVAL (operands[2]);
486 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
487 HOST_WIDE_INT rest = val - low;
489 operands[3] = GEN_INT (rest);
490 operands[4] = GEN_INT (low);
494 [(set (match_operand:DI 0 "register_operand" "=r,r")
496 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
497 (match_operand:SI 2 "sext_add_operand" "rI,O"))))]
504 [(set (match_operand:DI 0 "register_operand" "")
506 (plus:SI (match_operand:SI 1 "reg_not_elim_operand" "")
507 (match_operand:SI 2 "const_int_operand" ""))))
508 (clobber (match_operand:SI 3 "reg_not_elim_operand" ""))]
509 "! sext_add_operand (operands[2], SImode) && INTVAL (operands[2]) > 0
510 && INTVAL (operands[2]) % 4 == 0"
511 [(set (match_dup 3) (match_dup 4))
512 (set (match_dup 0) (sign_extend:DI (plus:SI (mult:SI (match_dup 3)
517 HOST_WIDE_INT val = INTVAL (operands[2]) / 4;
523 operands[4] = GEN_INT (val);
524 operands[5] = GEN_INT (mult);
528 [(set (match_operand:DI 0 "register_operand" "")
530 (plus:SI (match_operator:SI 1 "comparison_operator"
531 [(match_operand 2 "" "")
532 (match_operand 3 "" "")])
533 (match_operand:SI 4 "add_operand" ""))))
534 (clobber (match_operand:DI 5 "register_operand" ""))]
536 [(set (match_dup 5) (match_dup 6))
537 (set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 7) (match_dup 4))))]
540 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
541 operands[2], operands[3]);
542 operands[7] = gen_lowpart (SImode, operands[5]);
545 (define_insn "adddi3"
546 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
547 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ")
548 (match_operand:DI 2 "add_operand" "rI,O,K,L")))]
552 static const char * const pattern[4] = {
559 /* The NT stack unwind code can't handle a subq to adjust the stack
560 (that's a bug, but not one we can do anything about). As of NT4.0 SP3,
561 the exception handling code will loop if a subq is used and an
564 The 19980616 change to emit prologues as RTL also confused some
565 versions of GDB, which also interprets prologues. This has been
566 fixed as of GDB 4.18, but it does not harm to unconditionally
569 int which = which_alternative;
571 if (operands[0] == stack_pointer_rtx
572 && GET_CODE (operands[2]) == CONST_INT
573 && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))
576 return pattern[which];
579 ;; ??? Allow large constants when basing off the frame pointer or some
580 ;; virtual register that may eliminate to the frame pointer. This is
581 ;; done because register elimination offsets will change the hi/lo split,
582 ;; and if we split before reload, we will require additional instructions.
585 [(set (match_operand:DI 0 "register_operand" "=r")
586 (plus:DI (match_operand:DI 1 "reg_no_subreg_operand" "r")
587 (match_operand:DI 2 "const_int_operand" "n")))]
588 "REG_OK_FP_BASE_P (operands[1])"
591 ;; Don't do this if we are adjusting SP since we don't want to do it
592 ;; in two steps. Don't split FP sources for the reason listed above.
594 [(set (match_operand:DI 0 "register_operand" "")
595 (plus:DI (match_operand:DI 1 "register_operand" "")
596 (match_operand:DI 2 "const_int_operand" "")))]
597 "! add_operand (operands[2], DImode)
598 && operands[0] != stack_pointer_rtx
599 && operands[1] != frame_pointer_rtx
600 && operands[1] != arg_pointer_rtx"
601 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
602 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
605 HOST_WIDE_INT val = INTVAL (operands[2]);
606 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
607 HOST_WIDE_INT rest = val - low;
609 operands[3] = GEN_INT (rest);
610 operands[4] = GEN_INT (low);
614 [(set (match_operand:SI 0 "register_operand" "=r,r")
615 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
616 (match_operand:SI 2 "const48_operand" "I,I"))
617 (match_operand:SI 3 "sext_add_operand" "rI,O")))]
624 [(set (match_operand:DI 0 "register_operand" "=r,r")
626 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
627 (match_operand:SI 2 "const48_operand" "I,I"))
628 (match_operand:SI 3 "sext_add_operand" "rI,O"))))]
635 [(set (match_operand:DI 0 "register_operand" "")
637 (plus:SI (mult:SI (match_operator:SI 1 "comparison_operator"
638 [(match_operand 2 "" "")
639 (match_operand 3 "" "")])
640 (match_operand:SI 4 "const48_operand" ""))
641 (match_operand:SI 5 "sext_add_operand" ""))))
642 (clobber (match_operand:DI 6 "reg_not_elim_operand" ""))]
644 [(set (match_dup 6) (match_dup 7))
646 (sign_extend:DI (plus:SI (mult:SI (match_dup 8) (match_dup 4))
650 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
651 operands[2], operands[3]);
652 operands[8] = gen_lowpart (SImode, operands[6]);
656 [(set (match_operand:DI 0 "register_operand" "=r,r")
657 (plus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r,r")
658 (match_operand:DI 2 "const48_operand" "I,I"))
659 (match_operand:DI 3 "sext_add_operand" "rI,O")))]
665 ;; These variants of the above insns can occur if the third operand
666 ;; is the frame pointer, or other eliminable register. E.g. some
667 ;; register holding an offset from the stack pointer. This is a
668 ;; kludge, but there doesn't seem to be a way around it. Only
669 ;; recognize them while reloading.
672 [(set (match_operand:DI 0 "some_ni_operand" "=r,&r")
673 (plus:DI (plus:DI (match_operand:DI 1 "some_operand" "%r,r")
674 (match_operand:DI 2 "some_operand" "%r,r"))
675 (match_operand:DI 3 "some_operand" "IOKL,r")))]
680 [(set (match_operand:DI 0 "register_operand" "")
681 (plus:DI (plus:DI (match_operand:DI 1 "register_operand" "")
682 (match_operand:DI 2 "register_operand" ""))
683 (match_operand:DI 3 "add_operand" "")))]
685 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))
686 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
690 [(set (match_operand:SI 0 "some_ni_operand" "=r,&r")
691 (plus:SI (plus:SI (mult:SI (match_operand:SI 1 "some_operand" "rJ,rJ")
692 (match_operand:SI 2 "const48_operand" "I,I"))
693 (match_operand:SI 3 "some_operand" "%r,r"))
694 (match_operand:SI 4 "some_operand" "IOKL,r")))]
699 [(set (match_operand:SI 0 "register_operand" "")
700 (plus:SI (plus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "")
701 (match_operand:SI 2 "const48_operand" ""))
702 (match_operand:SI 3 "register_operand" ""))
703 (match_operand:SI 4 "add_operand" "rIOKL")))]
706 (plus:SI (mult:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
707 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
711 [(set (match_operand:DI 0 "some_ni_operand" "=r,&r")
714 (mult:SI (match_operand:SI 1 "some_operand" "rJ,rJ")
715 (match_operand:SI 2 "const48_operand" "I,I"))
716 (match_operand:SI 3 "some_operand" "%r,r"))
717 (match_operand:SI 4 "some_operand" "IO,r"))))]
722 [(set (match_operand:DI 0 "register_operand" "")
725 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "")
726 (match_operand:SI 2 "const48_operand" ""))
727 (match_operand:SI 3 "register_operand" ""))
728 (match_operand:SI 4 "sext_add_operand" ""))))]
731 (plus:SI (mult:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
732 (set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 5) (match_dup 4))))]
733 "operands[5] = gen_lowpart (SImode, operands[0]);")
736 [(set (match_operand:DI 0 "some_ni_operand" "=r,&r")
737 (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "some_operand" "rJ,rJ")
738 (match_operand:DI 2 "const48_operand" "I,I"))
739 (match_operand:DI 3 "some_operand" "%r,r"))
740 (match_operand:DI 4 "some_operand" "IOKL,r")))]
745 [(set (match_operand:DI 0 "register_operand" "")
746 (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "reg_or_0_operand" "")
747 (match_operand:DI 2 "const48_operand" ""))
748 (match_operand:DI 3 "register_operand" ""))
749 (match_operand:DI 4 "add_operand" "")))]
752 (plus:DI (mult:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
753 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
756 (define_insn "negsi2"
757 [(set (match_operand:SI 0 "register_operand" "=r")
758 (neg:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))]
763 [(set (match_operand:DI 0 "register_operand" "=r")
764 (sign_extend:DI (neg:SI
765 (match_operand:SI 1 "reg_or_8bit_operand" "rI"))))]
769 (define_insn "negdi2"
770 [(set (match_operand:DI 0 "register_operand" "=r")
771 (neg:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
775 (define_expand "subsi3"
776 [(set (match_operand:SI 0 "register_operand" "")
777 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "")
778 (match_operand:SI 2 "reg_or_8bit_operand" "")))]
784 rtx op1 = gen_lowpart (DImode, operands[1]);
785 rtx op2 = gen_lowpart (DImode, operands[2]);
787 if (! cse_not_expected)
789 rtx tmp = gen_reg_rtx (DImode);
790 emit_insn (gen_subdi3 (tmp, op1, op2));
791 emit_move_insn (gen_lowpart (DImode, operands[0]), tmp);
794 emit_insn (gen_subdi3 (gen_lowpart (DImode, operands[0]), op1, op2));
800 [(set (match_operand:SI 0 "register_operand" "=r")
801 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
802 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
807 [(set (match_operand:DI 0 "register_operand" "=r")
808 (sign_extend:DI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
809 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
813 (define_insn "subdi3"
814 [(set (match_operand:DI 0 "register_operand" "=r")
815 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
816 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
821 [(set (match_operand:SI 0 "register_operand" "=r")
822 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
823 (match_operand:SI 2 "const48_operand" "I"))
824 (match_operand:SI 3 "reg_or_8bit_operand" "rI")))]
829 [(set (match_operand:DI 0 "register_operand" "=r")
831 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
832 (match_operand:SI 2 "const48_operand" "I"))
833 (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))]
838 [(set (match_operand:DI 0 "register_operand" "=r")
839 (minus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r")
840 (match_operand:DI 2 "const48_operand" "I"))
841 (match_operand:DI 3 "reg_or_8bit_operand" "rI")))]
845 (define_insn "mulsi3"
846 [(set (match_operand:SI 0 "register_operand" "=r")
847 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
848 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
851 [(set_attr "type" "imul")
852 (set_attr "opsize" "si")])
855 [(set (match_operand:DI 0 "register_operand" "=r")
857 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
858 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
861 [(set_attr "type" "imul")
862 (set_attr "opsize" "si")])
864 (define_insn "muldi3"
865 [(set (match_operand:DI 0 "register_operand" "=r")
866 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
867 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
870 [(set_attr "type" "imul")])
872 (define_insn "umuldi3_highpart"
873 [(set (match_operand:DI 0 "register_operand" "=r")
876 (mult:TI (zero_extend:TI
877 (match_operand:DI 1 "reg_or_0_operand" "%rJ"))
879 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
883 [(set_attr "type" "imul")
884 (set_attr "opsize" "udi")])
887 [(set (match_operand:DI 0 "register_operand" "=r")
890 (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "r"))
891 (match_operand:TI 2 "cint8_operand" "I"))
895 [(set_attr "type" "imul")
896 (set_attr "opsize" "udi")])
898 ;; The divide and remainder operations always take their inputs from
899 ;; r24 and r25, put their output in r27, and clobber r23 and r28.
901 ;; ??? Force sign-extension here because some versions of OSF/1 don't
902 ;; do the right thing if the inputs are not properly sign-extended.
903 ;; But Linux, for instance, does not have this problem. Is it worth
904 ;; the complication here to eliminate the sign extension?
905 ;; Interix/NT has the same sign-extension problem.
907 (define_expand "divsi3"
909 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
911 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
912 (parallel [(set (reg:DI 27)
913 (sign_extend:DI (div:SI (reg:DI 24) (reg:DI 25))))
914 (clobber (reg:DI 23))
915 (clobber (reg:DI 28))])
916 (set (match_operand:SI 0 "nonimmediate_operand" "")
917 (subreg:SI (reg:DI 27) 0))]
921 (define_expand "udivsi3"
923 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
925 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
926 (parallel [(set (reg:DI 27)
927 (sign_extend:DI (udiv:SI (reg:DI 24) (reg:DI 25))))
928 (clobber (reg:DI 23))
929 (clobber (reg:DI 28))])
930 (set (match_operand:SI 0 "nonimmediate_operand" "")
931 (subreg:SI (reg:DI 27) 0))]
935 (define_expand "modsi3"
937 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
939 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
940 (parallel [(set (reg:DI 27)
941 (sign_extend:DI (mod:SI (reg:DI 24) (reg:DI 25))))
942 (clobber (reg:DI 23))
943 (clobber (reg:DI 28))])
944 (set (match_operand:SI 0 "nonimmediate_operand" "")
945 (subreg:SI (reg:DI 27) 0))]
949 (define_expand "umodsi3"
951 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
953 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
954 (parallel [(set (reg:DI 27)
955 (sign_extend:DI (umod:SI (reg:DI 24) (reg:DI 25))))
956 (clobber (reg:DI 23))
957 (clobber (reg:DI 28))])
958 (set (match_operand:SI 0 "nonimmediate_operand" "")
959 (subreg:SI (reg:DI 27) 0))]
963 (define_expand "divdi3"
964 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
965 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
966 (parallel [(set (reg:DI 27)
969 (clobber (reg:DI 23))
970 (clobber (reg:DI 28))])
971 (set (match_operand:DI 0 "nonimmediate_operand" "")
976 (define_expand "udivdi3"
977 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
978 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
979 (parallel [(set (reg:DI 27)
982 (clobber (reg:DI 23))
983 (clobber (reg:DI 28))])
984 (set (match_operand:DI 0 "nonimmediate_operand" "")
989 (define_expand "moddi3"
990 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
991 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
992 (parallel [(set (reg:DI 27)
995 (clobber (reg:DI 23))
996 (clobber (reg:DI 28))])
997 (set (match_operand:DI 0 "nonimmediate_operand" "")
1002 (define_expand "umoddi3"
1003 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
1004 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
1005 (parallel [(set (reg:DI 27)
1006 (umod:DI (reg:DI 24)
1008 (clobber (reg:DI 23))
1009 (clobber (reg:DI 28))])
1010 (set (match_operand:DI 0 "nonimmediate_operand" "")
1015 ;; Lengths of 8 for ldq $t12,__divq($gp); jsr $t9,($t12),__divq as
1016 ;; expanded by the assembler.
1019 (sign_extend:DI (match_operator:SI 1 "divmod_operator"
1020 [(reg:DI 24) (reg:DI 25)])))
1021 (clobber (reg:DI 23))
1022 (clobber (reg:DI 28))]
1025 [(set_attr "type" "jsr")
1026 (set_attr "length" "8")])
1030 (match_operator:DI 1 "divmod_operator"
1031 [(reg:DI 24) (reg:DI 25)]))
1032 (clobber (reg:DI 23))
1033 (clobber (reg:DI 28))]
1036 [(set_attr "type" "jsr")
1037 (set_attr "length" "8")])
1039 ;; Next are the basic logical operations. These only exist in DImode.
1041 (define_insn "anddi3"
1042 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1043 (and:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ")
1044 (match_operand:DI 2 "and_operand" "rI,N,MH")))]
1050 [(set_attr "type" "ilog,ilog,shift")])
1052 ;; There are times when we can split an AND into two AND insns. This occurs
1053 ;; when we can first clear any bytes and then clear anything else. For
1054 ;; example "I & 0xffff07" is "(I & 0xffffff) & 0xffffffffffffff07".
1055 ;; Only do this when running on 64-bit host since the computations are
1056 ;; too messy otherwise.
1059 [(set (match_operand:DI 0 "register_operand" "")
1060 (and:DI (match_operand:DI 1 "register_operand" "")
1061 (match_operand:DI 2 "const_int_operand" "")))]
1062 "HOST_BITS_PER_WIDE_INT == 64 && ! and_operand (operands[2], DImode)"
1063 [(set (match_dup 0) (and:DI (match_dup 1) (match_dup 3)))
1064 (set (match_dup 0) (and:DI (match_dup 0) (match_dup 4)))]
1067 unsigned HOST_WIDE_INT mask1 = INTVAL (operands[2]);
1068 unsigned HOST_WIDE_INT mask2 = mask1;
1071 /* For each byte that isn't all zeros, make it all ones. */
1072 for (i = 0; i < 64; i += 8)
1073 if ((mask1 & ((HOST_WIDE_INT) 0xff << i)) != 0)
1074 mask1 |= (HOST_WIDE_INT) 0xff << i;
1076 /* Now turn on any bits we've just turned off. */
1079 operands[3] = GEN_INT (mask1);
1080 operands[4] = GEN_INT (mask2);
1083 (define_insn "zero_extendqihi2"
1084 [(set (match_operand:HI 0 "register_operand" "=r")
1085 (zero_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1088 [(set_attr "type" "ilog")])
1091 [(set (match_operand:SI 0 "register_operand" "=r,r")
1092 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1097 [(set_attr "type" "ilog,ild")])
1100 [(set (match_operand:SI 0 "register_operand" "=r")
1101 (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1104 [(set_attr "type" "ilog")])
1106 (define_expand "zero_extendqisi2"
1107 [(set (match_operand:SI 0 "register_operand" "")
1108 (zero_extend:SI (match_operand:QI 1 "register_operand" "")))]
1113 [(set (match_operand:DI 0 "register_operand" "=r,r")
1114 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1119 [(set_attr "type" "ilog,ild")])
1122 [(set (match_operand:DI 0 "register_operand" "=r")
1123 (zero_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1126 [(set_attr "type" "ilog")])
1128 (define_expand "zero_extendqidi2"
1129 [(set (match_operand:DI 0 "register_operand" "")
1130 (zero_extend:DI (match_operand:QI 1 "register_operand" "")))]
1135 [(set (match_operand:SI 0 "register_operand" "=r,r")
1136 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1141 [(set_attr "type" "shift,ild")])
1144 [(set (match_operand:SI 0 "register_operand" "=r")
1145 (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1148 [(set_attr "type" "shift")])
1150 (define_expand "zero_extendhisi2"
1151 [(set (match_operand:SI 0 "register_operand" "")
1152 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
1157 [(set (match_operand:DI 0 "register_operand" "=r,r")
1158 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1163 [(set_attr "type" "shift,ild")])
1166 [(set (match_operand:DI 0 "register_operand" "=r")
1167 (zero_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1170 [(set_attr "type" "shift")])
1172 (define_expand "zero_extendhidi2"
1173 [(set (match_operand:DI 0 "register_operand" "")
1174 (zero_extend:DI (match_operand:HI 1 "register_operand" "")))]
1178 (define_insn "zero_extendsidi2"
1179 [(set (match_operand:DI 0 "register_operand" "=r")
1180 (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
1183 [(set_attr "type" "shift")])
1186 [(set (match_operand:DI 0 "register_operand" "=r")
1187 (and:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1188 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1191 [(set_attr "type" "ilog")])
1193 (define_insn "iordi3"
1194 [(set (match_operand:DI 0 "register_operand" "=r,r")
1195 (ior:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1196 (match_operand:DI 2 "or_operand" "rI,N")))]
1201 [(set_attr "type" "ilog")])
1203 (define_insn "one_cmpldi2"
1204 [(set (match_operand:DI 0 "register_operand" "=r")
1205 (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
1208 [(set_attr "type" "ilog")])
1211 [(set (match_operand:DI 0 "register_operand" "=r")
1212 (ior:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1213 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1216 [(set_attr "type" "ilog")])
1218 (define_insn "xordi3"
1219 [(set (match_operand:DI 0 "register_operand" "=r,r")
1220 (xor:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1221 (match_operand:DI 2 "or_operand" "rI,N")))]
1226 [(set_attr "type" "ilog")])
1229 [(set (match_operand:DI 0 "register_operand" "=r")
1230 (not:DI (xor:DI (match_operand:DI 1 "register_operand" "%rJ")
1231 (match_operand:DI 2 "register_operand" "rI"))))]
1234 [(set_attr "type" "ilog")])
1236 ;; Handle the FFS insn iff we support CIX.
1238 ;; These didn't make it into EV6 pass 2 as planned. Instead they
1239 ;; cropped cttz/ctlz/ctpop from the old CIX and renamed it FIX for
1240 ;; "Square Root and Floating Point Convert Extension".
1242 ;; I'm assured that these insns will make it into EV67 (first pass
1243 ;; due Summer 1999), presumably with a new AMASK bit, and presumably
1244 ;; will still be named CIX.
1246 (define_expand "ffsdi2"
1248 (unspec:DI [(match_operand:DI 1 "register_operand" "")] 1))
1250 (plus:DI (match_dup 2) (const_int 1)))
1251 (set (match_operand:DI 0 "register_operand" "")
1252 (if_then_else:DI (eq (match_dup 1) (const_int 0))
1253 (const_int 0) (match_dup 3)))]
1257 operands[2] = gen_reg_rtx (DImode);
1258 operands[3] = gen_reg_rtx (DImode);
1262 [(set (match_operand:DI 0 "register_operand" "=r")
1263 (unspec:DI [(match_operand:DI 1 "register_operand" "r")] 1))]
1266 ; EV6 calls all mvi and cttz/ctlz/popc class imisc, so just
1267 ; reuse the existing type name.
1268 [(set_attr "type" "mvi")])
1270 ;; Next come the shifts and the various extract and insert operations.
1272 (define_insn "ashldi3"
1273 [(set (match_operand:DI 0 "register_operand" "=r,r")
1274 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,rJ")
1275 (match_operand:DI 2 "reg_or_6bit_operand" "P,rS")))]
1279 switch (which_alternative)
1282 if (operands[2] == const1_rtx)
1283 return \"addq %r1,%r1,%0\";
1285 return \"s%P2addq %r1,0,%0\";
1287 return \"sll %r1,%2,%0\";
1292 [(set_attr "type" "iadd,shift")])
1294 ;; ??? The following pattern is made by combine, but earlier phases
1295 ;; (specifically flow) can't handle it. This occurs in jump.c. Deal
1296 ;; with this in a better way at some point.
1298 ;; [(set (match_operand:DI 0 "register_operand" "=r")
1300 ;; (subreg:SI (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1301 ;; (match_operand:DI 2 "const_int_operand" "P"))
1303 ;; "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3"
1306 ;; if (operands[2] == const1_rtx)
1307 ;; return \"addl %r1,%r1,%0\";
1309 ;; return \"s%P2addl %r1,0,%0\";
1311 ;; [(set_attr "type" "iadd")])
1313 (define_insn "lshrdi3"
1314 [(set (match_operand:DI 0 "register_operand" "=r")
1315 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1316 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1319 [(set_attr "type" "shift")])
1321 (define_insn "ashrdi3"
1322 [(set (match_operand:DI 0 "register_operand" "=r")
1323 (ashiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1324 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1327 [(set_attr "type" "shift")])
1329 (define_expand "extendqihi2"
1331 (ashift:DI (match_operand:QI 1 "some_operand" "")
1333 (set (match_operand:HI 0 "register_operand" "")
1334 (ashiftrt:DI (match_dup 2)
1341 emit_insn (gen_extendqihi2x (operands[0],
1342 force_reg (QImode, operands[1])));
1346 /* If we have an unaligned MEM, extend to DImode (which we do
1347 specially) and then copy to the result. */
1348 if (unaligned_memory_operand (operands[1], HImode))
1350 rtx temp = gen_reg_rtx (DImode);
1352 emit_insn (gen_extendqidi2 (temp, operands[1]));
1353 emit_move_insn (operands[0], gen_lowpart (HImode, temp));
1357 operands[0] = gen_lowpart (DImode, operands[0]);
1358 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1359 operands[2] = gen_reg_rtx (DImode);
1362 (define_insn "extendqidi2x"
1363 [(set (match_operand:DI 0 "register_operand" "=r")
1364 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1367 [(set_attr "type" "shift")])
1369 (define_insn "extendhidi2x"
1370 [(set (match_operand:DI 0 "register_operand" "=r")
1371 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1374 [(set_attr "type" "shift")])
1376 (define_insn "extendqisi2x"
1377 [(set (match_operand:SI 0 "register_operand" "=r")
1378 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1381 [(set_attr "type" "shift")])
1383 (define_insn "extendhisi2x"
1384 [(set (match_operand:SI 0 "register_operand" "=r")
1385 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1388 [(set_attr "type" "shift")])
1390 (define_insn "extendqihi2x"
1391 [(set (match_operand:HI 0 "register_operand" "=r")
1392 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1395 [(set_attr "type" "shift")])
1397 (define_expand "extendqisi2"
1399 (ashift:DI (match_operand:QI 1 "some_operand" "")
1401 (set (match_operand:SI 0 "register_operand" "")
1402 (ashiftrt:DI (match_dup 2)
1409 emit_insn (gen_extendqisi2x (operands[0],
1410 force_reg (QImode, operands[1])));
1414 /* If we have an unaligned MEM, extend to a DImode form of
1415 the result (which we do specially). */
1416 if (unaligned_memory_operand (operands[1], QImode))
1418 rtx temp = gen_reg_rtx (DImode);
1420 emit_insn (gen_extendqidi2 (temp, operands[1]));
1421 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1425 operands[0] = gen_lowpart (DImode, operands[0]);
1426 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1427 operands[2] = gen_reg_rtx (DImode);
1430 (define_expand "extendqidi2"
1432 (ashift:DI (match_operand:QI 1 "some_operand" "")
1434 (set (match_operand:DI 0 "register_operand" "")
1435 (ashiftrt:DI (match_dup 2)
1442 emit_insn (gen_extendqidi2x (operands[0],
1443 force_reg (QImode, operands[1])));
1447 if (unaligned_memory_operand (operands[1], QImode))
1450 = gen_unaligned_extendqidi (operands[0],
1451 get_unaligned_address (operands[1], 1));
1453 alpha_set_memflags (seq, operands[1]);
1458 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1459 operands[2] = gen_reg_rtx (DImode);
1462 (define_expand "extendhisi2"
1464 (ashift:DI (match_operand:HI 1 "some_operand" "")
1466 (set (match_operand:SI 0 "register_operand" "")
1467 (ashiftrt:DI (match_dup 2)
1474 emit_insn (gen_extendhisi2x (operands[0],
1475 force_reg (HImode, operands[1])));
1479 /* If we have an unaligned MEM, extend to a DImode form of
1480 the result (which we do specially). */
1481 if (unaligned_memory_operand (operands[1], HImode))
1483 rtx temp = gen_reg_rtx (DImode);
1485 emit_insn (gen_extendhidi2 (temp, operands[1]));
1486 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1490 operands[0] = gen_lowpart (DImode, operands[0]);
1491 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1492 operands[2] = gen_reg_rtx (DImode);
1495 (define_expand "extendhidi2"
1497 (ashift:DI (match_operand:HI 1 "some_operand" "")
1499 (set (match_operand:DI 0 "register_operand" "")
1500 (ashiftrt:DI (match_dup 2)
1507 emit_insn (gen_extendhidi2x (operands[0],
1508 force_reg (HImode, operands[1])));
1512 if (unaligned_memory_operand (operands[1], HImode))
1515 = gen_unaligned_extendhidi (operands[0],
1516 get_unaligned_address (operands[1], 2));
1518 alpha_set_memflags (seq, operands[1]);
1523 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1524 operands[2] = gen_reg_rtx (DImode);
1527 ;; Here's how we sign extend an unaligned byte and halfword. Doing this
1528 ;; as a pattern saves one instruction. The code is similar to that for
1529 ;; the unaligned loads (see below).
1531 ;; Operand 1 is the address + 1 (+2 for HI), operand 0 is the result.
1532 (define_expand "unaligned_extendqidi"
1533 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1535 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -1))
1538 (ashift:DI (match_dup 3)
1539 (minus:DI (const_int 64)
1541 (and:DI (match_dup 2) (const_int 7))
1543 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1544 (ashiftrt:DI (match_dup 4) (const_int 56)))]
1547 { operands[2] = gen_reg_rtx (DImode);
1548 operands[3] = gen_reg_rtx (DImode);
1549 operands[4] = gen_reg_rtx (DImode);
1552 (define_expand "unaligned_extendhidi"
1553 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1555 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -2))
1558 (ashift:DI (match_dup 3)
1559 (minus:DI (const_int 64)
1561 (and:DI (match_dup 2) (const_int 7))
1563 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1564 (ashiftrt:DI (match_dup 4) (const_int 48)))]
1567 { operands[2] = gen_reg_rtx (DImode);
1568 operands[3] = gen_reg_rtx (DImode);
1569 operands[4] = gen_reg_rtx (DImode);
1573 [(set (match_operand:DI 0 "register_operand" "=r")
1574 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1575 (match_operand:DI 2 "mode_width_operand" "n")
1576 (match_operand:DI 3 "mul8_operand" "I")))]
1578 "ext%M2l %r1,%s3,%0"
1579 [(set_attr "type" "shift")])
1581 (define_insn "extxl"
1582 [(set (match_operand:DI 0 "register_operand" "=r")
1583 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1584 (match_operand:DI 2 "mode_width_operand" "n")
1585 (ashift:DI (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1589 [(set_attr "type" "shift")])
1591 ;; Combine has some strange notion of preserving existing undefined behaviour
1592 ;; in shifts larger than a word size. So capture these patterns that it
1593 ;; should have turned into zero_extracts.
1596 [(set (match_operand:DI 0 "register_operand" "=r")
1597 (and:DI (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1598 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1600 (match_operand:DI 3 "mode_mask_operand" "n")))]
1603 [(set_attr "type" "shift")])
1606 [(set (match_operand:DI 0 "register_operand" "=r")
1607 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1608 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1612 [(set_attr "type" "shift")])
1614 (define_insn "extqh"
1615 [(set (match_operand:DI 0 "register_operand" "=r")
1617 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1618 (minus:DI (const_int 64)
1621 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1626 [(set_attr "type" "shift")])
1628 (define_insn "extlh"
1629 [(set (match_operand:DI 0 "register_operand" "=r")
1631 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1632 (const_int 2147483647))
1633 (minus:DI (const_int 64)
1636 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1641 [(set_attr "type" "shift")])
1643 (define_insn "extwh"
1644 [(set (match_operand:DI 0 "register_operand" "=r")
1646 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1648 (minus:DI (const_int 64)
1651 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1656 [(set_attr "type" "shift")])
1658 ;; This converts an extXl into an extXh with an appropriate adjustment
1659 ;; to the address calculation.
1662 ;; [(set (match_operand:DI 0 "register_operand" "")
1663 ;; (ashift:DI (zero_extract:DI (match_operand:DI 1 "register_operand" "")
1664 ;; (match_operand:DI 2 "mode_width_operand" "")
1665 ;; (ashift:DI (match_operand:DI 3 "" "")
1667 ;; (match_operand:DI 4 "const_int_operand" "")))
1668 ;; (clobber (match_operand:DI 5 "register_operand" ""))]
1669 ;; "INTVAL (operands[4]) == 64 - INTVAL (operands[2])"
1670 ;; [(set (match_dup 5) (match_dup 6))
1671 ;; (set (match_dup 0)
1672 ;; (ashift:DI (zero_extract:DI (match_dup 1) (match_dup 2)
1673 ;; (ashift:DI (plus:DI (match_dup 5)
1679 ;; operands[6] = plus_constant (operands[3],
1680 ;; INTVAL (operands[2]) / BITS_PER_UNIT);
1681 ;; operands[7] = GEN_INT (- INTVAL (operands[2]) / BITS_PER_UNIT);
1685 [(set (match_operand:DI 0 "register_operand" "=r")
1686 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
1687 (match_operand:DI 2 "mul8_operand" "I")))]
1690 [(set_attr "type" "shift")])
1693 [(set (match_operand:DI 0 "register_operand" "=r")
1694 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
1695 (match_operand:DI 2 "mul8_operand" "I")))]
1698 [(set_attr "type" "shift")])
1701 [(set (match_operand:DI 0 "register_operand" "=r")
1702 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
1703 (match_operand:DI 2 "mul8_operand" "I")))]
1706 [(set_attr "type" "shift")])
1708 (define_insn "insbl"
1709 [(set (match_operand:DI 0 "register_operand" "=r")
1710 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
1711 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1715 [(set_attr "type" "shift")])
1717 (define_insn "inswl"
1718 [(set (match_operand:DI 0 "register_operand" "=r")
1719 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
1720 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1724 [(set_attr "type" "shift")])
1726 (define_insn "insll"
1727 [(set (match_operand:DI 0 "register_operand" "=r")
1728 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
1729 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1733 [(set_attr "type" "shift")])
1735 (define_insn "insql"
1736 [(set (match_operand:DI 0 "register_operand" "=r")
1737 (ashift:DI (match_operand:DI 1 "register_operand" "r")
1738 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1742 [(set_attr "type" "shift")])
1744 ;; Combine has this sometimes habit of moving the and outside of the
1745 ;; shift, making life more interesting.
1748 [(set (match_operand:DI 0 "register_operand" "=r")
1749 (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
1750 (match_operand:DI 2 "mul8_operand" "I"))
1751 (match_operand:DI 3 "immediate_operand" "i")))]
1752 "HOST_BITS_PER_WIDE_INT == 64
1753 && GET_CODE (operands[3]) == CONST_INT
1754 && (((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
1755 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1756 || ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
1757 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1758 || ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
1759 == (unsigned HOST_WIDE_INT) INTVAL (operands[3])))"
1762 #if HOST_BITS_PER_WIDE_INT == 64
1763 if ((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
1764 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1765 return \"insbl %1,%s2,%0\";
1766 if ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
1767 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1768 return \"inswl %1,%s2,%0\";
1769 if ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
1770 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1771 return \"insll %1,%s2,%0\";
1775 [(set_attr "type" "shift")])
1777 ;; We do not include the insXh insns because they are complex to express
1778 ;; and it does not appear that we would ever want to generate them.
1780 ;; Since we need them for block moves, though, cop out and use unspec.
1782 (define_insn "insxh"
1783 [(set (match_operand:DI 0 "register_operand" "=r")
1784 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
1785 (match_operand:DI 2 "mode_width_operand" "n")
1786 (match_operand:DI 3 "reg_or_8bit_operand" "rI")] 2))]
1789 [(set_attr "type" "shift")])
1791 (define_insn "mskxl"
1792 [(set (match_operand:DI 0 "register_operand" "=r")
1793 (and:DI (not:DI (ashift:DI
1794 (match_operand:DI 2 "mode_mask_operand" "n")
1796 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1798 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
1801 [(set_attr "type" "shift")])
1803 ;; We do not include the mskXh insns because it does not appear we would
1804 ;; ever generate one.
1806 ;; Again, we do for block moves and we use unspec again.
1808 (define_insn "mskxh"
1809 [(set (match_operand:DI 0 "register_operand" "=r")
1810 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
1811 (match_operand:DI 2 "mode_width_operand" "n")
1812 (match_operand:DI 3 "reg_or_8bit_operand" "rI")] 3))]
1815 [(set_attr "type" "shift")])
1817 ;; Floating-point operations. All the double-precision insns can extend
1818 ;; from single, so indicate that. The exception are the ones that simply
1819 ;; play with the sign bits; it's not clear what to do there.
1821 (define_insn "abssf2"
1822 [(set (match_operand:SF 0 "register_operand" "=f")
1823 (abs:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
1826 [(set_attr "type" "fcpys")])
1828 (define_insn "absdf2"
1829 [(set (match_operand:DF 0 "register_operand" "=f")
1830 (abs:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
1833 [(set_attr "type" "fcpys")])
1835 (define_insn "negsf2"
1836 [(set (match_operand:SF 0 "register_operand" "=f")
1837 (neg:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
1840 [(set_attr "type" "fadd")])
1842 (define_insn "negdf2"
1843 [(set (match_operand:DF 0 "register_operand" "=f")
1844 (neg:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
1847 [(set_attr "type" "fadd")])
1850 [(set (match_operand:SF 0 "register_operand" "=&f")
1851 (plus:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
1852 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
1853 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
1854 "add%,%)%& %R1,%R2,%0"
1855 [(set_attr "type" "fadd")
1856 (set_attr "trap" "yes")])
1858 (define_insn "addsf3"
1859 [(set (match_operand:SF 0 "register_operand" "=f")
1860 (plus:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
1861 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
1863 "add%,%)%& %R1,%R2,%0"
1864 [(set_attr "type" "fadd")
1865 (set_attr "trap" "yes")])
1868 [(set (match_operand:DF 0 "register_operand" "=&f")
1869 (plus:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
1870 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
1871 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
1872 "add%-%)%& %R1,%R2,%0"
1873 [(set_attr "type" "fadd")
1874 (set_attr "trap" "yes")])
1876 (define_insn "adddf3"
1877 [(set (match_operand:DF 0 "register_operand" "=f")
1878 (plus:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
1879 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
1881 "add%-%)%& %R1,%R2,%0"
1882 [(set_attr "type" "fadd")
1883 (set_attr "trap" "yes")])
1886 [(set (match_operand:DF 0 "register_operand" "=f")
1887 (plus:DF (float_extend:DF
1888 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
1889 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
1890 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
1891 "add%-%)%& %R1,%R2,%0"
1892 [(set_attr "type" "fadd")
1893 (set_attr "trap" "yes")])
1896 [(set (match_operand:DF 0 "register_operand" "=f")
1897 (plus:DF (float_extend:DF
1898 (match_operand:SF 1 "reg_or_fp0_operand" "%fG"))
1900 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
1901 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
1902 "add%-%)%& %R1,%R2,%0"
1903 [(set_attr "type" "fadd")
1904 (set_attr "trap" "yes")])
1906 ;; Define conversion operators between DFmode and SImode, using the cvtql
1907 ;; instruction. To allow combine et al to do useful things, we keep the
1908 ;; operation as a unit until after reload, at which point we split the
1911 ;; Note that we (attempt to) only consider this optimization when the
1912 ;; ultimate destination is memory. If we will be doing further integer
1913 ;; processing, it is cheaper to do the truncation in the int regs.
1915 (define_insn "*cvtql"
1916 [(set (match_operand:SI 0 "register_operand" "=f")
1917 (unspec:SI [(match_operand:DI 1 "reg_or_fp0_operand" "fG")] 5))]
1920 [(set_attr "type" "fadd")
1921 (set_attr "trap" "yes")])
1924 [(set (match_operand:SI 0 "memory_operand" "")
1925 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "")) 0))
1926 (clobber (match_scratch:DI 2 ""))
1927 (clobber (match_scratch:SI 3 ""))]
1928 "TARGET_FP && reload_completed"
1929 [(set (match_dup 2) (fix:DI (match_dup 1)))
1930 (set (match_dup 3) (unspec:SI [(match_dup 2)] 5))
1931 (set (match_dup 0) (match_dup 3))]
1935 [(set (match_operand:SI 0 "memory_operand" "")
1936 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "")) 0))
1937 (clobber (match_scratch:DI 2 ""))]
1938 "TARGET_FP && reload_completed"
1939 [(set (match_dup 2) (fix:DI (match_dup 1)))
1940 (set (match_dup 3) (unspec:SI [(match_dup 2)] 5))
1941 (set (match_dup 0) (match_dup 3))]
1942 ;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG.
1943 "operands[3] = gen_rtx_REG (SImode, REGNO (operands[2]));")
1946 [(set (match_operand:SI 0 "memory_operand" "=m")
1947 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")) 0))
1948 (clobber (match_scratch:DI 2 "=&f"))
1949 (clobber (match_scratch:SI 3 "=&f"))]
1950 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
1952 [(set_attr "type" "fadd")
1953 (set_attr "trap" "yes")])
1956 [(set (match_operand:SI 0 "memory_operand" "=m")
1957 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")) 0))
1958 (clobber (match_scratch:DI 2 "=f"))]
1959 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
1961 [(set_attr "type" "fadd")
1962 (set_attr "trap" "yes")])
1965 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
1966 (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
1967 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
1969 [(set_attr "type" "fadd")
1970 (set_attr "trap" "yes")])
1972 (define_insn "fix_truncdfdi2"
1973 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
1974 (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
1977 [(set_attr "type" "fadd")
1978 (set_attr "trap" "yes")])
1980 ;; Likewise between SFmode and SImode.
1983 [(set (match_operand:SI 0 "memory_operand" "")
1984 (subreg:SI (fix:DI (float_extend:DF
1985 (match_operand:SF 1 "reg_or_fp0_operand" ""))) 0))
1986 (clobber (match_scratch:DI 2 ""))
1987 (clobber (match_scratch:SI 3 ""))]
1988 "TARGET_FP && reload_completed"
1989 [(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1))))
1990 (set (match_dup 3) (unspec:SI [(match_dup 2)] 5))
1991 (set (match_dup 0) (match_dup 3))]
1995 [(set (match_operand:SI 0 "memory_operand" "")
1996 (subreg:SI (fix:DI (float_extend:DF
1997 (match_operand:SF 1 "reg_or_fp0_operand" ""))) 0))
1998 (clobber (match_scratch:DI 2 ""))]
1999 "TARGET_FP && reload_completed"
2000 [(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1))))
2001 (set (match_dup 3) (unspec:SI [(match_dup 2)] 5))
2002 (set (match_dup 0) (match_dup 3))]
2003 ;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG.
2004 "operands[3] = gen_rtx_REG (SImode, REGNO (operands[2]));")
2007 [(set (match_operand:SI 0 "memory_operand" "=m")
2008 (subreg:SI (fix:DI (float_extend:DF
2009 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))) 0))
2010 (clobber (match_scratch:DI 2 "=&f"))
2011 (clobber (match_scratch:SI 3 "=&f"))]
2012 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2014 [(set_attr "type" "fadd")
2015 (set_attr "trap" "yes")])
2018 [(set (match_operand:SI 0 "memory_operand" "=m")
2019 (subreg:SI (fix:DI (float_extend:DF
2020 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))) 0))
2021 (clobber (match_scratch:DI 2 "=f"))]
2022 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2024 [(set_attr "type" "fadd")
2025 (set_attr "trap" "yes")])
2028 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
2029 (fix:DI (float_extend:DF
2030 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
2031 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2033 [(set_attr "type" "fadd")
2034 (set_attr "trap" "yes")])
2036 (define_insn "fix_truncsfdi2"
2037 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
2038 (fix:DI (float_extend:DF
2039 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
2042 [(set_attr "type" "fadd")
2043 (set_attr "trap" "yes")])
2046 [(set (match_operand:SF 0 "register_operand" "=&f")
2047 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2048 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2050 [(set_attr "type" "fadd")
2051 (set_attr "trap" "yes")])
2053 (define_insn "floatdisf2"
2054 [(set (match_operand:SF 0 "register_operand" "=f")
2055 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2058 [(set_attr "type" "fadd")
2059 (set_attr "trap" "yes")])
2062 [(set (match_operand:DF 0 "register_operand" "=&f")
2063 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2064 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2066 [(set_attr "type" "fadd")
2067 (set_attr "trap" "yes")])
2069 (define_insn "floatdidf2"
2070 [(set (match_operand:DF 0 "register_operand" "=f")
2071 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2074 [(set_attr "type" "fadd")
2075 (set_attr "trap" "yes")])
2077 (define_expand "extendsfdf2"
2078 [(use (match_operand:DF 0 "register_operand" ""))
2079 (use (match_operand:SF 1 "nonimmediate_operand" ""))]
2083 if (alpha_fptm >= ALPHA_FPTM_SU)
2084 emit_insn (gen_extendsfdf2_tp (operands[0],
2085 force_reg (SFmode, operands[1])));
2087 emit_insn (gen_extendsfdf2_no_tp (operands[0], operands[1]));
2092 (define_insn "extendsfdf2_tp"
2093 [(set (match_operand:DF 0 "register_operand" "=&f")
2094 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
2095 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2097 [(set_attr "type" "fadd")
2098 (set_attr "trap" "yes")])
2100 (define_insn "extendsfdf2_no_tp"
2101 [(set (match_operand:DF 0 "register_operand" "=f,f,m")
2102 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m,f")))]
2103 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2108 [(set_attr "type" "fcpys,fld,fst")
2109 (set_attr "trap" "yes")])
2112 [(set (match_operand:SF 0 "register_operand" "=&f")
2113 (float_truncate:SF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2114 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2115 "cvt%-%,%)%& %R1,%0"
2116 [(set_attr "type" "fadd")
2117 (set_attr "trap" "yes")])
2119 (define_insn "truncdfsf2"
2120 [(set (match_operand:SF 0 "register_operand" "=f")
2121 (float_truncate:SF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2123 "cvt%-%,%)%& %R1,%0"
2124 [(set_attr "type" "fadd")
2125 (set_attr "trap" "yes")])
2128 [(set (match_operand:SF 0 "register_operand" "=&f")
2129 (div:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2130 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2131 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2132 "div%,%)%& %R1,%R2,%0"
2133 [(set_attr "type" "fdiv")
2134 (set_attr "opsize" "si")
2135 (set_attr "trap" "yes")])
2137 (define_insn "divsf3"
2138 [(set (match_operand:SF 0 "register_operand" "=f")
2139 (div:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2140 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2142 "div%,%)%& %R1,%R2,%0"
2143 [(set_attr "type" "fdiv")
2144 (set_attr "opsize" "si")
2145 (set_attr "trap" "yes")])
2148 [(set (match_operand:DF 0 "register_operand" "=&f")
2149 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2150 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2151 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2152 "div%-%)%& %R1,%R2,%0"
2153 [(set_attr "type" "fdiv")
2154 (set_attr "trap" "yes")])
2156 (define_insn "divdf3"
2157 [(set (match_operand:DF 0 "register_operand" "=f")
2158 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2159 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2161 "div%-%)%& %R1,%R2,%0"
2162 [(set_attr "type" "fdiv")
2163 (set_attr "trap" "yes")])
2166 [(set (match_operand:DF 0 "register_operand" "=f")
2167 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2168 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2169 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2170 "div%-%)%& %R1,%R2,%0"
2171 [(set_attr "type" "fdiv")
2172 (set_attr "trap" "yes")])
2175 [(set (match_operand:DF 0 "register_operand" "=f")
2176 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2178 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2179 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2180 "div%-%)%& %R1,%R2,%0"
2181 [(set_attr "type" "fdiv")
2182 (set_attr "trap" "yes")])
2185 [(set (match_operand:DF 0 "register_operand" "=f")
2186 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2187 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2188 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2189 "div%-%)%& %R1,%R2,%0"
2190 [(set_attr "type" "fdiv")
2191 (set_attr "trap" "yes")])
2194 [(set (match_operand:SF 0 "register_operand" "=&f")
2195 (mult:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
2196 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2197 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2198 "mul%,%)%& %R1,%R2,%0"
2199 [(set_attr "type" "fmul")
2200 (set_attr "trap" "yes")])
2202 (define_insn "mulsf3"
2203 [(set (match_operand:SF 0 "register_operand" "=f")
2204 (mult:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
2205 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2207 "mul%,%)%& %R1,%R2,%0"
2208 [(set_attr "type" "fmul")
2209 (set_attr "trap" "yes")])
2212 [(set (match_operand:DF 0 "register_operand" "=&f")
2213 (mult:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
2214 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2215 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2216 "mul%-%)%& %R1,%R2,%0"
2217 [(set_attr "type" "fmul")
2218 (set_attr "trap" "yes")])
2220 (define_insn "muldf3"
2221 [(set (match_operand:DF 0 "register_operand" "=f")
2222 (mult:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
2223 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2225 "mul%-%)%& %R1,%R2,%0"
2226 [(set_attr "type" "fmul")
2227 (set_attr "trap" "yes")])
2230 [(set (match_operand:DF 0 "register_operand" "=f")
2231 (mult:DF (float_extend:DF
2232 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2233 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2234 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2235 "mul%-%)%& %R1,%R2,%0"
2236 [(set_attr "type" "fmul")
2237 (set_attr "trap" "yes")])
2240 [(set (match_operand:DF 0 "register_operand" "=f")
2241 (mult:DF (float_extend:DF
2242 (match_operand:SF 1 "reg_or_fp0_operand" "%fG"))
2244 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2245 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2246 "mul%-%)%& %R1,%R2,%0"
2247 [(set_attr "type" "fmul")
2248 (set_attr "trap" "yes")])
2251 [(set (match_operand:SF 0 "register_operand" "=&f")
2252 (minus:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2253 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2254 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2255 "sub%,%)%& %R1,%R2,%0"
2256 [(set_attr "type" "fadd")
2257 (set_attr "trap" "yes")])
2259 (define_insn "subsf3"
2260 [(set (match_operand:SF 0 "register_operand" "=f")
2261 (minus:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2262 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2264 "sub%,%)%& %R1,%R2,%0"
2265 [(set_attr "type" "fadd")
2266 (set_attr "trap" "yes")])
2269 [(set (match_operand:DF 0 "register_operand" "=&f")
2270 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2271 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2272 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2273 "sub%-%)%& %R1,%R2,%0"
2274 [(set_attr "type" "fadd")
2275 (set_attr "trap" "yes")])
2277 (define_insn "subdf3"
2278 [(set (match_operand:DF 0 "register_operand" "=f")
2279 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2280 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2282 "sub%-%)%& %R1,%R2,%0"
2283 [(set_attr "type" "fadd")
2284 (set_attr "trap" "yes")])
2287 [(set (match_operand:DF 0 "register_operand" "=f")
2288 (minus:DF (float_extend:DF
2289 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2290 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2291 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2292 "sub%-%)%& %R1,%R2,%0"
2293 [(set_attr "type" "fadd")
2294 (set_attr "trap" "yes")])
2297 [(set (match_operand:DF 0 "register_operand" "=f")
2298 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2300 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2301 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2302 "sub%-%)%& %R1,%R2,%0"
2303 [(set_attr "type" "fadd")
2304 (set_attr "trap" "yes")])
2307 [(set (match_operand:DF 0 "register_operand" "=f")
2308 (minus:DF (float_extend:DF
2309 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2311 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2312 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2313 "sub%-%)%& %R1,%R2,%0"
2314 [(set_attr "type" "fadd")
2315 (set_attr "trap" "yes")])
2318 [(set (match_operand:SF 0 "register_operand" "=&f")
2319 (sqrt:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
2320 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
2322 [(set_attr "type" "fsqrt")
2323 (set_attr "opsize" "si")
2324 (set_attr "trap" "yes")])
2326 (define_insn "sqrtsf2"
2327 [(set (match_operand:SF 0 "register_operand" "=f")
2328 (sqrt:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
2329 "TARGET_FP && TARGET_FIX"
2331 [(set_attr "type" "fsqrt")
2332 (set_attr "opsize" "si")
2333 (set_attr "trap" "yes")])
2336 [(set (match_operand:DF 0 "register_operand" "=&f")
2337 (sqrt:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2338 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
2340 [(set_attr "type" "fsqrt")
2341 (set_attr "trap" "yes")])
2343 (define_insn "sqrtdf2"
2344 [(set (match_operand:DF 0 "register_operand" "=f")
2345 (sqrt:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2346 "TARGET_FP && TARGET_FIX"
2348 [(set_attr "type" "fsqrt")
2349 (set_attr "trap" "yes")])
2351 ;; Next are all the integer comparisons, and conditional moves and branches
2352 ;; and some of the related define_expand's and define_split's.
2355 [(set (match_operand:DI 0 "register_operand" "=r")
2356 (match_operator:DI 1 "alpha_comparison_operator"
2357 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
2358 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]))]
2361 [(set_attr "type" "icmp")])
2364 [(set (match_operand:DI 0 "register_operand" "=r")
2365 (match_operator:DI 1 "alpha_swapped_comparison_operator"
2366 [(match_operand:DI 2 "reg_or_8bit_operand" "rI")
2367 (match_operand:DI 3 "reg_or_0_operand" "rJ")]))]
2370 [(set_attr "type" "icmp")])
2372 ;; This pattern exists so conditional moves of SImode values are handled.
2373 ;; Comparisons are still done in DImode though.
2376 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
2378 (match_operator 2 "signed_comparison_operator"
2379 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
2380 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
2381 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0,rI,0")
2382 (match_operand:SI 5 "reg_or_8bit_operand" "0,rI,0,rI")))]
2383 "operands[3] == const0_rtx || operands[4] == const0_rtx"
2389 [(set_attr "type" "icmov")])
2392 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
2394 (match_operator 2 "signed_comparison_operator"
2395 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
2396 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
2397 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0,rI,0")
2398 (match_operand:DI 5 "reg_or_8bit_operand" "0,rI,0,rI")))]
2399 "operands[3] == const0_rtx || operands[4] == const0_rtx"
2405 [(set_attr "type" "icmov")])
2408 [(set (match_operand:DI 0 "register_operand" "=r,r")
2410 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2414 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
2415 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
2420 [(set_attr "type" "icmov")])
2423 [(set (match_operand:DI 0 "register_operand" "=r,r")
2425 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2429 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
2430 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
2435 [(set_attr "type" "icmov")])
2437 ;; For ABS, we have two choices, depending on whether the input and output
2438 ;; registers are the same or not.
2439 (define_expand "absdi2"
2440 [(set (match_operand:DI 0 "register_operand" "")
2441 (abs:DI (match_operand:DI 1 "register_operand" "")))]
2444 { if (rtx_equal_p (operands[0], operands[1]))
2445 emit_insn (gen_absdi2_same (operands[0], gen_reg_rtx (DImode)));
2447 emit_insn (gen_absdi2_diff (operands[0], operands[1]));
2452 (define_expand "absdi2_same"
2453 [(set (match_operand:DI 1 "register_operand" "")
2454 (neg:DI (match_operand:DI 0 "register_operand" "")))
2456 (if_then_else:DI (ge (match_dup 0) (const_int 0))
2462 (define_expand "absdi2_diff"
2463 [(set (match_operand:DI 0 "register_operand" "")
2464 (neg:DI (match_operand:DI 1 "register_operand" "")))
2466 (if_then_else:DI (lt (match_dup 1) (const_int 0))
2473 [(set (match_operand:DI 0 "register_operand" "")
2474 (abs:DI (match_dup 0)))
2475 (clobber (match_operand:DI 2 "register_operand" ""))]
2477 [(set (match_dup 1) (neg:DI (match_dup 0)))
2478 (set (match_dup 0) (if_then_else:DI (ge (match_dup 0) (const_int 0))
2479 (match_dup 0) (match_dup 1)))]
2483 [(set (match_operand:DI 0 "register_operand" "")
2484 (abs:DI (match_operand:DI 1 "register_operand" "")))]
2485 "! rtx_equal_p (operands[0], operands[1])"
2486 [(set (match_dup 0) (neg:DI (match_dup 1)))
2487 (set (match_dup 0) (if_then_else:DI (lt (match_dup 1) (const_int 0))
2488 (match_dup 0) (match_dup 1)))]
2492 [(set (match_operand:DI 0 "register_operand" "")
2493 (neg:DI (abs:DI (match_dup 0))))
2494 (clobber (match_operand:DI 2 "register_operand" ""))]
2496 [(set (match_dup 1) (neg:DI (match_dup 0)))
2497 (set (match_dup 0) (if_then_else:DI (le (match_dup 0) (const_int 0))
2498 (match_dup 0) (match_dup 1)))]
2502 [(set (match_operand:DI 0 "register_operand" "")
2503 (neg:DI (abs:DI (match_operand:DI 1 "register_operand" ""))))]
2504 "! rtx_equal_p (operands[0], operands[1])"
2505 [(set (match_dup 0) (neg:DI (match_dup 1)))
2506 (set (match_dup 0) (if_then_else:DI (gt (match_dup 1) (const_int 0))
2507 (match_dup 0) (match_dup 1)))]
2510 (define_insn "sminqi3"
2511 [(set (match_operand:QI 0 "register_operand" "=r")
2512 (smin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
2513 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
2516 [(set_attr "type" "mvi")])
2518 (define_insn "uminqi3"
2519 [(set (match_operand:QI 0 "register_operand" "=r")
2520 (umin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
2521 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
2524 [(set_attr "type" "mvi")])
2526 (define_insn "smaxqi3"
2527 [(set (match_operand:QI 0 "register_operand" "=r")
2528 (smax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
2529 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
2532 [(set_attr "type" "mvi")])
2534 (define_insn "umaxqi3"
2535 [(set (match_operand:QI 0 "register_operand" "=r")
2536 (umax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
2537 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
2540 [(set_attr "type" "mvi")])
2542 (define_insn "sminhi3"
2543 [(set (match_operand:HI 0 "register_operand" "=r")
2544 (smin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
2545 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
2548 [(set_attr "type" "mvi")])
2550 (define_insn "uminhi3"
2551 [(set (match_operand:HI 0 "register_operand" "=r")
2552 (umin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
2553 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
2556 [(set_attr "type" "mvi")])
2558 (define_insn "smaxhi3"
2559 [(set (match_operand:HI 0 "register_operand" "=r")
2560 (smax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
2561 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
2564 [(set_attr "type" "mvi")])
2566 (define_insn "umaxhi3"
2567 [(set (match_operand:HI 0 "register_operand" "=r")
2568 (umax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
2569 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
2572 [(set_attr "type" "shift")])
2574 (define_expand "smaxdi3"
2576 (le:DI (match_operand:DI 1 "reg_or_0_operand" "")
2577 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2578 (set (match_operand:DI 0 "register_operand" "")
2579 (if_then_else:DI (eq (match_dup 3) (const_int 0))
2580 (match_dup 1) (match_dup 2)))]
2583 { operands[3] = gen_reg_rtx (DImode);
2587 [(set (match_operand:DI 0 "register_operand" "")
2588 (smax:DI (match_operand:DI 1 "reg_or_0_operand" "")
2589 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2590 (clobber (match_operand:DI 3 "register_operand" ""))]
2591 "operands[2] != const0_rtx"
2592 [(set (match_dup 3) (le:DI (match_dup 1) (match_dup 2)))
2593 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
2594 (match_dup 1) (match_dup 2)))]
2598 [(set (match_operand:DI 0 "register_operand" "=r")
2599 (smax:DI (match_operand:DI 1 "register_operand" "0")
2603 [(set_attr "type" "icmov")])
2605 (define_expand "smindi3"
2607 (lt:DI (match_operand:DI 1 "reg_or_0_operand" "")
2608 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2609 (set (match_operand:DI 0 "register_operand" "")
2610 (if_then_else:DI (ne (match_dup 3) (const_int 0))
2611 (match_dup 1) (match_dup 2)))]
2614 { operands[3] = gen_reg_rtx (DImode);
2618 [(set (match_operand:DI 0 "register_operand" "")
2619 (smin:DI (match_operand:DI 1 "reg_or_0_operand" "")
2620 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2621 (clobber (match_operand:DI 3 "register_operand" ""))]
2622 "operands[2] != const0_rtx"
2623 [(set (match_dup 3) (lt:DI (match_dup 1) (match_dup 2)))
2624 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
2625 (match_dup 1) (match_dup 2)))]
2629 [(set (match_operand:DI 0 "register_operand" "=r")
2630 (smin:DI (match_operand:DI 1 "register_operand" "0")
2634 [(set_attr "type" "icmov")])
2636 (define_expand "umaxdi3"
2638 (leu:DI (match_operand:DI 1 "reg_or_0_operand" "")
2639 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2640 (set (match_operand:DI 0 "register_operand" "")
2641 (if_then_else:DI (eq (match_dup 3) (const_int 0))
2642 (match_dup 1) (match_dup 2)))]
2645 { operands[3] = gen_reg_rtx (DImode);
2649 [(set (match_operand:DI 0 "register_operand" "")
2650 (umax:DI (match_operand:DI 1 "reg_or_0_operand" "")
2651 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2652 (clobber (match_operand:DI 3 "register_operand" ""))]
2653 "operands[2] != const0_rtx"
2654 [(set (match_dup 3) (leu:DI (match_dup 1) (match_dup 2)))
2655 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
2656 (match_dup 1) (match_dup 2)))]
2659 (define_expand "umindi3"
2661 (ltu:DI (match_operand:DI 1 "reg_or_0_operand" "")
2662 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2663 (set (match_operand:DI 0 "register_operand" "")
2664 (if_then_else:DI (ne (match_dup 3) (const_int 0))
2665 (match_dup 1) (match_dup 2)))]
2668 { operands[3] = gen_reg_rtx (DImode);
2672 [(set (match_operand:DI 0 "register_operand" "")
2673 (umin:DI (match_operand:DI 1 "reg_or_0_operand" "")
2674 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2675 (clobber (match_operand:DI 3 "register_operand" ""))]
2676 "operands[2] != const0_rtx"
2677 [(set (match_dup 3) (ltu:DI (match_dup 1) (match_dup 2)))
2678 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
2679 (match_dup 1) (match_dup 2)))]
2685 (match_operator 1 "signed_comparison_operator"
2686 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
2688 (label_ref (match_operand 0 "" ""))
2692 [(set_attr "type" "ibr")])
2697 (match_operator 1 "signed_comparison_operator"
2699 (match_operand:DI 2 "register_operand" "r")])
2700 (label_ref (match_operand 0 "" ""))
2704 [(set_attr "type" "ibr")])
2709 (ne (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
2713 (label_ref (match_operand 0 "" ""))
2717 [(set_attr "type" "ibr")])
2722 (eq (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
2726 (label_ref (match_operand 0 "" ""))
2730 [(set_attr "type" "ibr")])
2736 (match_operator 1 "comparison_operator"
2737 [(zero_extract:DI (match_operand:DI 2 "register_operand" "")
2739 (match_operand:DI 3 "const_int_operand" ""))
2741 (label_ref (match_operand 0 "" ""))
2743 (clobber (match_operand:DI 4 "register_operand" ""))])]
2744 "INTVAL (operands[3]) != 0"
2746 (lshiftrt:DI (match_dup 2) (match_dup 3)))
2748 (if_then_else (match_op_dup 1
2749 [(zero_extract:DI (match_dup 4)
2753 (label_ref (match_dup 0))
2757 ;; The following are the corresponding floating-point insns. Recall
2758 ;; we need to have variants that expand the arguments from SF mode
2762 [(set (match_operand:DF 0 "register_operand" "=&f")
2763 (match_operator:DF 1 "alpha_comparison_operator"
2764 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
2765 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
2766 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2767 "cmp%-%C1%' %R2,%R3,%0"
2768 [(set_attr "type" "fadd")
2769 (set_attr "trap" "yes")])
2772 [(set (match_operand:DF 0 "register_operand" "=f")
2773 (match_operator:DF 1 "alpha_comparison_operator"
2774 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
2775 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
2776 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2777 "cmp%-%C1%' %R2,%R3,%0"
2778 [(set_attr "type" "fadd")
2779 (set_attr "trap" "yes")])
2782 [(set (match_operand:DF 0 "register_operand" "=&f")
2783 (match_operator:DF 1 "alpha_comparison_operator"
2785 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
2786 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
2787 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2788 "cmp%-%C1%' %R2,%R3,%0"
2789 [(set_attr "type" "fadd")
2790 (set_attr "trap" "yes")])
2793 [(set (match_operand:DF 0 "register_operand" "=f")
2794 (match_operator:DF 1 "alpha_comparison_operator"
2796 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
2797 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
2798 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2799 "cmp%-%C1%' %R2,%R3,%0"
2800 [(set_attr "type" "fadd")
2801 (set_attr "trap" "yes")])
2804 [(set (match_operand:DF 0 "register_operand" "=&f")
2805 (match_operator:DF 1 "alpha_comparison_operator"
2806 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
2808 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
2809 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2810 "cmp%-%C1%' %R2,%R3,%0"
2811 [(set_attr "type" "fadd")
2812 (set_attr "trap" "yes")])
2815 [(set (match_operand:DF 0 "register_operand" "=f")
2816 (match_operator:DF 1 "alpha_comparison_operator"
2817 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
2819 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
2820 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2821 "cmp%-%C1%' %R2,%R3,%0"
2822 [(set_attr "type" "fadd")
2823 (set_attr "trap" "yes")])
2826 [(set (match_operand:DF 0 "register_operand" "=&f")
2827 (match_operator:DF 1 "alpha_comparison_operator"
2829 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
2831 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
2832 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2833 "cmp%-%C1%' %R2,%R3,%0"
2834 [(set_attr "type" "fadd")
2835 (set_attr "trap" "yes")])
2838 [(set (match_operand:DF 0 "register_operand" "=f")
2839 (match_operator:DF 1 "alpha_comparison_operator"
2841 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
2843 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
2844 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2845 "cmp%-%C1%' %R2,%R3,%0"
2846 [(set_attr "type" "fadd")
2847 (set_attr "trap" "yes")])
2850 [(set (match_operand:DF 0 "register_operand" "=f,f")
2852 (match_operator 3 "signed_comparison_operator"
2853 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
2854 (match_operand:DF 2 "fp0_operand" "G,G")])
2855 (match_operand:DF 1 "reg_or_fp0_operand" "fG,0")
2856 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
2860 fcmov%D3 %R4,%R5,%0"
2861 [(set_attr "type" "fcmov")])
2864 [(set (match_operand:SF 0 "register_operand" "=f,f")
2866 (match_operator 3 "signed_comparison_operator"
2867 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
2868 (match_operand:DF 2 "fp0_operand" "G,G")])
2869 (match_operand:SF 1 "reg_or_fp0_operand" "fG,0")
2870 (match_operand:SF 5 "reg_or_fp0_operand" "0,fG")))]
2874 fcmov%D3 %R4,%R5,%0"
2875 [(set_attr "type" "fcmov")])
2878 [(set (match_operand:DF 0 "register_operand" "=f,f")
2880 (match_operator 3 "signed_comparison_operator"
2881 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
2882 (match_operand:DF 2 "fp0_operand" "G,G")])
2883 (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG,0"))
2884 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
2888 fcmov%D3 %R4,%R5,%0"
2889 [(set_attr "type" "fcmov")])
2892 [(set (match_operand:DF 0 "register_operand" "=f,f")
2894 (match_operator 3 "signed_comparison_operator"
2896 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
2897 (match_operand:DF 2 "fp0_operand" "G,G")])
2898 (match_operand:DF 1 "reg_or_fp0_operand" "fG,0")
2899 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
2903 fcmov%D3 %R4,%R5,%0"
2904 [(set_attr "type" "fcmov")])
2907 [(set (match_operand:SF 0 "register_operand" "=f,f")
2909 (match_operator 3 "signed_comparison_operator"
2911 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
2912 (match_operand:DF 2 "fp0_operand" "G,G")])
2913 (match_operand:SF 1 "reg_or_fp0_operand" "fG,0")
2914 (match_operand:SF 5 "reg_or_fp0_operand" "0,fG")))]
2918 fcmov%D3 %R4,%R5,%0"
2919 [(set_attr "type" "fcmov")])
2922 [(set (match_operand:DF 0 "register_operand" "=f,f")
2924 (match_operator 3 "signed_comparison_operator"
2926 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
2927 (match_operand:DF 2 "fp0_operand" "G,G")])
2928 (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG,0"))
2929 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
2933 fcmov%D3 %R4,%R5,%0"
2934 [(set_attr "type" "fcmov")])
2936 (define_expand "maxdf3"
2938 (le:DF (match_operand:DF 1 "reg_or_fp0_operand" "")
2939 (match_operand:DF 2 "reg_or_fp0_operand" "")))
2940 (set (match_operand:DF 0 "register_operand" "")
2941 (if_then_else:DF (eq (match_dup 3) (match_dup 4))
2942 (match_dup 1) (match_dup 2)))]
2945 { operands[3] = gen_reg_rtx (DFmode);
2946 operands[4] = CONST0_RTX (DFmode);
2949 (define_expand "mindf3"
2951 (lt:DF (match_operand:DF 1 "reg_or_fp0_operand" "")
2952 (match_operand:DF 2 "reg_or_fp0_operand" "")))
2953 (set (match_operand:DF 0 "register_operand" "")
2954 (if_then_else:DF (ne (match_dup 3) (match_dup 4))
2955 (match_dup 1) (match_dup 2)))]
2958 { operands[3] = gen_reg_rtx (DFmode);
2959 operands[4] = CONST0_RTX (DFmode);
2962 (define_expand "maxsf3"
2964 (le:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" ""))
2965 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" ""))))
2966 (set (match_operand:SF 0 "register_operand" "")
2967 (if_then_else:SF (eq (match_dup 3) (match_dup 4))
2968 (match_dup 1) (match_dup 2)))]
2971 { operands[3] = gen_reg_rtx (DFmode);
2972 operands[4] = CONST0_RTX (DFmode);
2975 (define_expand "minsf3"
2977 (lt:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" ""))
2978 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" ""))))
2979 (set (match_operand:SF 0 "register_operand" "")
2980 (if_then_else:SF (ne (match_dup 3) (match_dup 4))
2981 (match_dup 1) (match_dup 2)))]
2984 { operands[3] = gen_reg_rtx (DFmode);
2985 operands[4] = CONST0_RTX (DFmode);
2991 (match_operator 1 "signed_comparison_operator"
2992 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
2993 (match_operand:DF 3 "fp0_operand" "G")])
2994 (label_ref (match_operand 0 "" ""))
2998 [(set_attr "type" "fbr")])
3003 (match_operator 1 "signed_comparison_operator"
3005 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3006 (match_operand:DF 3 "fp0_operand" "G")])
3007 (label_ref (match_operand 0 "" ""))
3011 [(set_attr "type" "fbr")])
3013 ;; These are the main define_expand's used to make conditional branches
3016 (define_expand "cmpdf"
3017 [(set (cc0) (compare (match_operand:DF 0 "reg_or_fp0_operand" "")
3018 (match_operand:DF 1 "reg_or_fp0_operand" "")))]
3022 alpha_compare.op0 = operands[0];
3023 alpha_compare.op1 = operands[1];
3024 alpha_compare.fp_p = 1;
3028 (define_expand "cmpdi"
3029 [(set (cc0) (compare (match_operand:DI 0 "reg_or_0_operand" "")
3030 (match_operand:DI 1 "reg_or_8bit_operand" "")))]
3034 alpha_compare.op0 = operands[0];
3035 alpha_compare.op1 = operands[1];
3036 alpha_compare.fp_p = 0;
3040 (define_expand "beq"
3042 (if_then_else (match_dup 1)
3043 (label_ref (match_operand 0 "" ""))
3046 "{ operands[1] = alpha_emit_conditional_branch (EQ); }")
3048 (define_expand "bne"
3050 (if_then_else (match_dup 1)
3051 (label_ref (match_operand 0 "" ""))
3054 "{ operands[1] = alpha_emit_conditional_branch (NE); }")
3056 (define_expand "blt"
3058 (if_then_else (match_dup 1)
3059 (label_ref (match_operand 0 "" ""))
3062 "{ operands[1] = alpha_emit_conditional_branch (LT); }")
3064 (define_expand "ble"
3066 (if_then_else (match_dup 1)
3067 (label_ref (match_operand 0 "" ""))
3070 "{ operands[1] = alpha_emit_conditional_branch (LE); }")
3072 (define_expand "bgt"
3074 (if_then_else (match_dup 1)
3075 (label_ref (match_operand 0 "" ""))
3078 "{ operands[1] = alpha_emit_conditional_branch (GT); }")
3080 (define_expand "bge"
3082 (if_then_else (match_dup 1)
3083 (label_ref (match_operand 0 "" ""))
3086 "{ operands[1] = alpha_emit_conditional_branch (GE); }")
3088 (define_expand "bltu"
3090 (if_then_else (match_dup 1)
3091 (label_ref (match_operand 0 "" ""))
3094 "{ operands[1] = alpha_emit_conditional_branch (LTU); }")
3096 (define_expand "bleu"
3098 (if_then_else (match_dup 1)
3099 (label_ref (match_operand 0 "" ""))
3102 "{ operands[1] = alpha_emit_conditional_branch (LEU); }")
3104 (define_expand "bgtu"
3106 (if_then_else (match_dup 1)
3107 (label_ref (match_operand 0 "" ""))
3110 "{ operands[1] = alpha_emit_conditional_branch (GTU); }")
3112 (define_expand "bgeu"
3114 (if_then_else (match_dup 1)
3115 (label_ref (match_operand 0 "" ""))
3118 "{ operands[1] = alpha_emit_conditional_branch (GEU); }")
3120 (define_expand "seq"
3121 [(set (match_operand:DI 0 "register_operand" "")
3126 if (alpha_compare.fp_p)
3129 operands[1] = gen_rtx_EQ (DImode, alpha_compare.op0, alpha_compare.op1);
3130 alpha_compare.op0 = alpha_compare.op1 = NULL_RTX;
3133 (define_expand "sne"
3134 [(set (match_operand:DI 0 "register_operand" "")
3136 (set (match_dup 0) (xor:DI (match_dup 0) (const_int 1)))]
3140 if (alpha_compare.fp_p)
3143 if (alpha_compare.op1 == const0_rtx)
3145 emit_insn (gen_sgtu (operands[0]));
3149 operands[1] = gen_rtx_EQ (DImode, alpha_compare.op0, alpha_compare.op1);
3150 alpha_compare.op0 = alpha_compare.op1 = NULL_RTX;
3153 (define_expand "slt"
3154 [(set (match_operand:DI 0 "register_operand" "")
3159 if (alpha_compare.fp_p)
3162 operands[1] = gen_rtx_LT (DImode, alpha_compare.op0, alpha_compare.op1);
3163 alpha_compare.op0 = alpha_compare.op1 = NULL_RTX;
3166 (define_expand "sle"
3167 [(set (match_operand:DI 0 "register_operand" "")
3172 if (alpha_compare.fp_p)
3175 operands[1] = gen_rtx_LE (DImode, alpha_compare.op0, alpha_compare.op1);
3176 alpha_compare.op0 = alpha_compare.op1 = NULL_RTX;
3179 (define_expand "sgt"
3180 [(set (match_operand:DI 0 "register_operand" "")
3185 if (alpha_compare.fp_p)
3188 operands[1] = gen_rtx_LT (DImode, force_reg (DImode, alpha_compare.op1),
3190 alpha_compare.op0 = alpha_compare.op1 = NULL_RTX;
3193 (define_expand "sge"
3194 [(set (match_operand:DI 0 "register_operand" "")
3199 if (alpha_compare.fp_p)
3202 operands[1] = gen_rtx_LE (DImode, force_reg (DImode, alpha_compare.op1),
3204 alpha_compare.op0 = alpha_compare.op1 = NULL_RTX;
3207 (define_expand "sltu"
3208 [(set (match_operand:DI 0 "register_operand" "")
3213 if (alpha_compare.fp_p)
3216 operands[1] = gen_rtx_LTU (DImode, alpha_compare.op0, alpha_compare.op1);
3217 alpha_compare.op0 = alpha_compare.op1 = NULL_RTX;
3220 (define_expand "sleu"
3221 [(set (match_operand:DI 0 "register_operand" "")
3226 if (alpha_compare.fp_p)
3229 operands[1] = gen_rtx_LEU (DImode, alpha_compare.op0, alpha_compare.op1);
3230 alpha_compare.op0 = alpha_compare.op1 = NULL_RTX;
3233 (define_expand "sgtu"
3234 [(set (match_operand:DI 0 "register_operand" "")
3239 if (alpha_compare.fp_p)
3242 operands[1] = gen_rtx_LTU (DImode, force_reg (DImode, alpha_compare.op1),
3244 alpha_compare.op0 = alpha_compare.op1 = NULL_RTX;
3247 (define_expand "sgeu"
3248 [(set (match_operand:DI 0 "register_operand" "")
3253 if (alpha_compare.fp_p)
3256 operands[1] = gen_rtx_LEU (DImode, force_reg (DImode, alpha_compare.op1),
3258 alpha_compare.op0 = alpha_compare.op1 = NULL_RTX;
3261 ;; These are the main define_expand's used to make conditional moves.
3263 (define_expand "movsicc"
3264 [(set (match_operand:SI 0 "register_operand" "")
3265 (if_then_else:SI (match_operand 1 "comparison_operator" "")
3266 (match_operand:SI 2 "reg_or_8bit_operand" "")
3267 (match_operand:SI 3 "reg_or_8bit_operand" "")))]
3271 if ((operands[1] = alpha_emit_conditional_move (operands[1], SImode)) == 0)
3275 (define_expand "movdicc"
3276 [(set (match_operand:DI 0 "register_operand" "")
3277 (if_then_else:DI (match_operand 1 "comparison_operator" "")
3278 (match_operand:DI 2 "reg_or_8bit_operand" "")
3279 (match_operand:DI 3 "reg_or_8bit_operand" "")))]
3283 if ((operands[1] = alpha_emit_conditional_move (operands[1], DImode)) == 0)
3287 (define_expand "movsfcc"
3288 [(set (match_operand:SF 0 "register_operand" "")
3289 (if_then_else:SF (match_operand 1 "comparison_operator" "")
3290 (match_operand:SF 2 "reg_or_8bit_operand" "")
3291 (match_operand:SF 3 "reg_or_8bit_operand" "")))]
3295 if ((operands[1] = alpha_emit_conditional_move (operands[1], SFmode)) == 0)
3299 (define_expand "movdfcc"
3300 [(set (match_operand:DF 0 "register_operand" "")
3301 (if_then_else:DF (match_operand 1 "comparison_operator" "")
3302 (match_operand:DF 2 "reg_or_8bit_operand" "")
3303 (match_operand:DF 3 "reg_or_8bit_operand" "")))]
3307 if ((operands[1] = alpha_emit_conditional_move (operands[1], DFmode)) == 0)
3311 ;; These define_split definitions are used in cases when comparisons have
3312 ;; not be stated in the correct way and we need to reverse the second
3313 ;; comparison. For example, x >= 7 has to be done as x < 6 with the
3314 ;; comparison that tests the result being reversed. We have one define_split
3315 ;; for each use of a comparison. They do not match valid insns and need
3316 ;; not generate valid insns.
3318 ;; We can also handle equality comparisons (and inequality comparisons in
3319 ;; cases where the resulting add cannot overflow) by doing an add followed by
3320 ;; a comparison with zero. This is faster since the addition takes one
3321 ;; less cycle than a compare when feeding into a conditional move.
3322 ;; For this case, we also have an SImode pattern since we can merge the add
3323 ;; and sign extend and the order doesn't matter.
3325 ;; We do not do this for floating-point, since it isn't clear how the "wrong"
3326 ;; operation could have been generated.
3329 [(set (match_operand:DI 0 "register_operand" "")
3331 (match_operator 1 "comparison_operator"
3332 [(match_operand:DI 2 "reg_or_0_operand" "")
3333 (match_operand:DI 3 "reg_or_cint_operand" "")])
3334 (match_operand:DI 4 "reg_or_cint_operand" "")
3335 (match_operand:DI 5 "reg_or_cint_operand" "")))
3336 (clobber (match_operand:DI 6 "register_operand" ""))]
3337 "operands[3] != const0_rtx"
3338 [(set (match_dup 6) (match_dup 7))
3340 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
3342 { enum rtx_code code = GET_CODE (operands[1]);
3343 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
3345 /* If we are comparing for equality with a constant and that constant
3346 appears in the arm when the register equals the constant, use the
3347 register since that is more likely to match (and to produce better code
3350 if (code == EQ && GET_CODE (operands[3]) == CONST_INT
3351 && rtx_equal_p (operands[4], operands[3]))
3352 operands[4] = operands[2];
3354 else if (code == NE && GET_CODE (operands[3]) == CONST_INT
3355 && rtx_equal_p (operands[5], operands[3]))
3356 operands[5] = operands[2];
3358 if (code == NE || code == EQ
3359 || (extended_count (operands[2], DImode, unsignedp) >= 1
3360 && extended_count (operands[3], DImode, unsignedp) >= 1))
3362 if (GET_CODE (operands[3]) == CONST_INT)
3363 operands[7] = gen_rtx_PLUS (DImode, operands[2],
3364 GEN_INT (- INTVAL (operands[3])));
3366 operands[7] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
3368 operands[8] = gen_rtx_fmt_ee (code, VOIDmode, operands[6], const0_rtx);
3371 else if (code == EQ || code == LE || code == LT
3372 || code == LEU || code == LTU)
3374 operands[7] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
3375 operands[8] = gen_rtx_NE (VOIDmode, operands[6], const0_rtx);
3379 operands[7] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
3380 operands[2], operands[3]);
3381 operands[8] = gen_rtx_EQ (VOIDmode, operands[6], const0_rtx);
3386 [(set (match_operand:DI 0 "register_operand" "")
3388 (match_operator 1 "comparison_operator"
3389 [(match_operand:SI 2 "reg_or_0_operand" "")
3390 (match_operand:SI 3 "reg_or_cint_operand" "")])
3391 (match_operand:DI 4 "reg_or_8bit_operand" "")
3392 (match_operand:DI 5 "reg_or_8bit_operand" "")))
3393 (clobber (match_operand:DI 6 "register_operand" ""))]
3394 "operands[3] != const0_rtx
3395 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
3396 [(set (match_dup 6) (match_dup 7))
3398 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
3400 { enum rtx_code code = GET_CODE (operands[1]);
3401 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
3404 if ((code != NE && code != EQ
3405 && ! (extended_count (operands[2], DImode, unsignedp) >= 1
3406 && extended_count (operands[3], DImode, unsignedp) >= 1)))
3409 if (GET_CODE (operands[3]) == CONST_INT)
3410 tem = gen_rtx_PLUS (SImode, operands[2],
3411 GEN_INT (- INTVAL (operands[3])));
3413 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
3415 operands[7] = gen_rtx_SIGN_EXTEND (DImode, tem);
3416 operands[8] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
3417 operands[6], const0_rtx);
3423 (match_operator 1 "comparison_operator"
3424 [(match_operand:DI 2 "reg_or_0_operand" "")
3425 (match_operand:DI 3 "reg_or_cint_operand" "")])
3426 (label_ref (match_operand 0 "" ""))
3428 (clobber (match_operand:DI 4 "register_operand" ""))]
3429 "operands[3] != const0_rtx"
3430 [(set (match_dup 4) (match_dup 5))
3431 (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))]
3433 { enum rtx_code code = GET_CODE (operands[1]);
3434 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
3436 if (code == NE || code == EQ
3437 || (extended_count (operands[2], DImode, unsignedp) >= 1
3438 && extended_count (operands[3], DImode, unsignedp) >= 1))
3440 if (GET_CODE (operands[3]) == CONST_INT)
3441 operands[5] = gen_rtx_PLUS (DImode, operands[2],
3442 GEN_INT (- INTVAL (operands[3])));
3444 operands[5] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
3446 operands[6] = gen_rtx_fmt_ee (code, VOIDmode, operands[4], const0_rtx);
3449 else if (code == EQ || code == LE || code == LT
3450 || code == LEU || code == LTU)
3452 operands[5] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
3453 operands[6] = gen_rtx_NE (VOIDmode, operands[4], const0_rtx);
3457 operands[5] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
3458 operands[2], operands[3]);
3459 operands[6] = gen_rtx_EQ (VOIDmode, operands[4], const0_rtx);
3466 (match_operator 1 "comparison_operator"
3467 [(match_operand:SI 2 "reg_or_0_operand" "")
3468 (match_operand:SI 3 "const_int_operand" "")])
3469 (label_ref (match_operand 0 "" ""))
3471 (clobber (match_operand:DI 4 "register_operand" ""))]
3472 "operands[3] != const0_rtx
3473 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
3474 [(set (match_dup 4) (match_dup 5))
3475 (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))]
3479 if (GET_CODE (operands[3]) == CONST_INT)
3480 tem = gen_rtx_PLUS (SImode, operands[2],
3481 GEN_INT (- INTVAL (operands[3])));
3483 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
3485 operands[5] = gen_rtx_SIGN_EXTEND (DImode, tem);
3486 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
3487 operands[4], const0_rtx);
3490 ;; We can convert such things as "a > 0xffff" to "t = a & ~ 0xffff; t != 0".
3491 ;; This eliminates one, and sometimes two, insns when the AND can be done
3494 [(set (match_operand:DI 0 "register_operand" "")
3495 (match_operator:DI 1 "comparison_operator"
3496 [(match_operand:DI 2 "register_operand" "")
3497 (match_operand:DI 3 "const_int_operand" "")]))
3498 (clobber (match_operand:DI 4 "register_operand" ""))]
3499 "exact_log2 (INTVAL (operands[3]) + 1) >= 0
3500 && (GET_CODE (operands[1]) == GTU
3501 || GET_CODE (operands[1]) == LEU
3502 || ((GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == LE)
3503 && extended_count (operands[2], DImode, 1) > 0))"
3504 [(set (match_dup 4) (and:DI (match_dup 2) (match_dup 5)))
3505 (set (match_dup 0) (match_dup 6))]
3508 operands[5] = GEN_INT (~ INTVAL (operands[3]));
3509 operands[6] = gen_rtx_fmt_ee (((GET_CODE (operands[1]) == GTU
3510 || GET_CODE (operands[1]) == GT)
3512 DImode, operands[4], const0_rtx);
3515 ;; Here are the CALL and unconditional branch insns. Calls on NT and OSF
3516 ;; work differently, so we have different patterns for each.
3518 (define_expand "call"
3519 [(use (match_operand:DI 0 "" ""))
3520 (use (match_operand 1 "" ""))
3521 (use (match_operand 2 "" ""))
3522 (use (match_operand 3 "" ""))]
3525 { if (TARGET_WINDOWS_NT)
3526 emit_call_insn (gen_call_nt (operands[0], operands[1]));
3527 else if (TARGET_OPEN_VMS)
3528 emit_call_insn (gen_call_vms (operands[0], operands[2]));
3530 emit_call_insn (gen_call_osf (operands[0], operands[1]));
3535 (define_expand "call_osf"
3536 [(parallel [(call (mem:DI (match_operand 0 "" ""))
3537 (match_operand 1 "" ""))
3538 (clobber (reg:DI 27))
3539 (clobber (reg:DI 26))])]
3542 { if (GET_CODE (operands[0]) != MEM)
3545 operands[0] = XEXP (operands[0], 0);
3547 if (GET_CODE (operands[0]) != SYMBOL_REF
3548 && ! (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 27))
3550 rtx tem = gen_rtx_REG (DImode, 27);
3551 emit_move_insn (tem, operands[0]);
3556 (define_expand "call_nt"
3557 [(parallel [(call (mem:DI (match_operand 0 "" ""))
3558 (match_operand 1 "" ""))
3559 (clobber (reg:DI 26))])]
3562 { if (GET_CODE (operands[0]) != MEM)
3565 operands[0] = XEXP (operands[0], 0);
3566 if (GET_CODE (operands[0]) != SYMBOL_REF && GET_CODE (operands[0]) != REG)
3567 operands[0] = force_reg (DImode, operands[0]);
3571 ;; call openvms/alpha
3572 ;; op 0: symbol ref for called function
3573 ;; op 1: next_arg_reg (argument information value for R25)
3575 (define_expand "call_vms"
3576 [(parallel [(call (mem:DI (match_operand 0 "" ""))
3577 (match_operand 1 "" ""))
3581 (clobber (reg:DI 27))])]
3584 { if (GET_CODE (operands[0]) != MEM)
3587 operands[0] = XEXP (operands[0], 0);
3589 /* Always load AI with argument information, then handle symbolic and
3590 indirect call differently. Load RA and set operands[2] to PV in
3593 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
3594 if (GET_CODE (operands[0]) == SYMBOL_REF)
3596 extern char *savealloc ();
3597 char *linksym, *symbol = XSTR (operands[0], 0);
3602 linksym = savealloc (strlen (symbol) + 6);
3604 alpha_need_linkage (symbol, 0);
3607 strcpy (linksym+1, symbol);
3608 strcat (linksym, \"..lk\");
3609 linkage = gen_rtx_SYMBOL_REF (Pmode, linksym);
3611 emit_move_insn (gen_rtx_REG (Pmode, 26), gen_rtx_MEM (Pmode, linkage));
3614 = validize_mem (gen_rtx_MEM (Pmode, plus_constant (linkage, 8)));
3618 emit_move_insn (gen_rtx_REG (Pmode, 26),
3619 gen_rtx_MEM (Pmode, plus_constant (operands[0], 8)));
3621 operands[2] = operands[0];
3626 (define_expand "call_value"
3627 [(use (match_operand 0 "" ""))
3628 (use (match_operand:DI 1 "" ""))
3629 (use (match_operand 2 "" ""))
3630 (use (match_operand 3 "" ""))
3631 (use (match_operand 4 "" ""))]
3634 { if (TARGET_WINDOWS_NT)
3635 emit_call_insn (gen_call_value_nt (operands[0], operands[1], operands[2]));
3636 else if (TARGET_OPEN_VMS)
3637 emit_call_insn (gen_call_value_vms (operands[0], operands[1],
3640 emit_call_insn (gen_call_value_osf (operands[0], operands[1],
3645 (define_expand "call_value_osf"
3646 [(parallel [(set (match_operand 0 "" "")
3647 (call (mem:DI (match_operand 1 "" ""))
3648 (match_operand 2 "" "")))
3649 (clobber (reg:DI 27))
3650 (clobber (reg:DI 26))])]
3653 { if (GET_CODE (operands[1]) != MEM)
3656 operands[1] = XEXP (operands[1], 0);
3658 if (GET_CODE (operands[1]) != SYMBOL_REF
3659 && ! (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 27))
3661 rtx tem = gen_rtx_REG (DImode, 27);
3662 emit_move_insn (tem, operands[1]);
3667 (define_expand "call_value_nt"
3668 [(parallel [(set (match_operand 0 "" "")
3669 (call (mem:DI (match_operand 1 "" ""))
3670 (match_operand 2 "" "")))
3671 (clobber (reg:DI 26))])]
3674 { if (GET_CODE (operands[1]) != MEM)
3677 operands[1] = XEXP (operands[1], 0);
3678 if (GET_CODE (operands[1]) != SYMBOL_REF && GET_CODE (operands[1]) != REG)
3679 operands[1] = force_reg (DImode, operands[1]);
3682 (define_expand "call_value_vms"
3683 [(parallel [(set (match_operand 0 "" "")
3684 (call (mem:DI (match_operand:DI 1 "" ""))
3685 (match_operand 2 "" "")))
3689 (clobber (reg:DI 27))])]
3692 { if (GET_CODE (operands[1]) != MEM)
3695 operands[1] = XEXP (operands[1], 0);
3697 /* Always load AI with argument information, then handle symbolic and
3698 indirect call differently. Load RA and set operands[3] to PV in
3701 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
3702 if (GET_CODE (operands[1]) == SYMBOL_REF)
3704 extern char *savealloc ();
3705 char *linksym, *symbol = XSTR (operands[1], 0);
3710 linksym = savealloc (strlen (symbol) + 6);
3712 alpha_need_linkage (symbol, 0);
3714 strcpy (linksym+1, symbol);
3715 strcat (linksym, \"..lk\");
3716 linkage = gen_rtx_SYMBOL_REF (Pmode, linksym);
3718 emit_move_insn (gen_rtx_REG (Pmode, 26), gen_rtx_MEM (Pmode, linkage));
3721 = validize_mem (gen_rtx_MEM (Pmode, plus_constant (linkage, 8)));
3725 emit_move_insn (gen_rtx_REG (Pmode, 26),
3726 gen_rtx_MEM (Pmode, plus_constant (operands[1], 8)));
3728 operands[3] = operands[1];
3733 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,R,i"))
3734 (match_operand 1 "" ""))
3735 (clobber (reg:DI 27))
3736 (clobber (reg:DI 26))]
3737 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS"
3739 jsr $26,($27),0\;ldgp $29,0($26)
3741 jsr $26,%0\;ldgp $29,0($26)"
3742 [(set_attr "type" "jsr")
3743 (set_attr "length" "12,*,16")])
3746 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,R,i"))
3747 (match_operand 1 "" ""))
3748 (clobber (reg:DI 26))]
3754 [(set_attr "type" "jsr")
3755 (set_attr "length" "*,*,12")])
3758 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,i"))
3759 (match_operand 1 "" ""))
3760 (use (match_operand:DI 2 "nonimmediate_operand" "r,m"))
3763 (clobber (reg:DI 27))]
3766 mov %2,$27\;jsr $26,0\;ldq $27,0($29)
3767 ldq $27,%2\;jsr $26,%0\;ldq $27,0($29)"
3768 [(set_attr "type" "jsr")
3769 (set_attr "length" "12,16")])
3771 ;; Call subroutine returning any type.
3773 (define_expand "untyped_call"
3774 [(parallel [(call (match_operand 0 "" "")
3776 (match_operand 1 "" "")
3777 (match_operand 2 "" "")])]
3783 emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
3785 for (i = 0; i < XVECLEN (operands[2], 0); i++)
3787 rtx set = XVECEXP (operands[2], 0, i);
3788 emit_move_insn (SET_DEST (set), SET_SRC (set));
3791 /* The optimizer does not know that the call sets the function value
3792 registers we stored in the result block. We avoid problems by
3793 claiming that all hard registers are used and clobbered at this
3795 emit_insn (gen_blockage ());
3800 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
3801 ;; all of memory. This blocks insns from being moved across this point.
3803 (define_insn "blockage"
3804 [(unspec_volatile [(const_int 0)] 1)]
3807 [(set_attr "length" "0")])
3811 (label_ref (match_operand 0 "" "")))]
3814 [(set_attr "type" "ibr")])
3816 (define_insn "return"
3820 [(set_attr "type" "ibr")])
3822 ;; Use a different pattern for functions which have non-trivial
3823 ;; epilogues so as not to confuse jump and reorg.
3824 (define_insn "return_internal"
3829 [(set_attr "type" "ibr")])
3831 (define_insn "indirect_jump"
3832 [(set (pc) (match_operand:DI 0 "register_operand" "r"))]
3835 [(set_attr "type" "ibr")])
3837 (define_expand "tablejump"
3838 [(use (match_operand:SI 0 "register_operand" ""))
3839 (use (match_operand:SI 1 "" ""))]
3843 if (TARGET_WINDOWS_NT)
3844 emit_jump_insn (gen_tablejump_nt (operands[0], operands[1]));
3845 else if (TARGET_OPEN_VMS)
3846 emit_jump_insn (gen_tablejump_vms (operands[0], operands[1]));
3848 emit_jump_insn (gen_tablejump_osf (operands[0], operands[1]));
3853 (define_expand "tablejump_osf"
3855 (sign_extend:DI (match_operand:SI 0 "register_operand" "")))
3856 (parallel [(set (pc)
3857 (plus:DI (match_dup 3)
3858 (label_ref (match_operand 1 "" ""))))
3859 (clobber (match_scratch:DI 2 "=r"))])]
3862 { operands[3] = gen_reg_rtx (DImode); }")
3864 (define_expand "tablejump_nt"
3866 (sign_extend:DI (match_operand:SI 0 "register_operand" "")))
3867 (parallel [(set (pc)
3869 (use (label_ref (match_operand 1 "" "")))])]
3872 { operands[3] = gen_reg_rtx (DImode); }")
3875 ;; tablejump, openVMS way
3877 ;; op 1: label preceding jump-table
3879 (define_expand "tablejump_vms"
3881 (match_operand:DI 0 "register_operand" ""))
3883 (plus:DI (match_dup 2)
3884 (label_ref (match_operand 1 "" ""))))]
3887 { operands[2] = gen_reg_rtx (DImode); }")
3891 (plus (match_operand:DI 0 "register_operand" "r")
3892 (label_ref (match_operand 1 "" ""))))
3893 (clobber (match_scratch:DI 2 "=r"))]
3894 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS && next_active_insn (insn) != 0
3895 && GET_CODE (PATTERN (next_active_insn (insn))) == ADDR_DIFF_VEC
3896 && PREV_INSN (next_active_insn (insn)) == operands[1]"
3898 { rtx best_label = 0;
3899 rtx jump_table_insn = next_active_insn (operands[1]);
3901 if (GET_CODE (jump_table_insn) == JUMP_INSN
3902 && GET_CODE (PATTERN (jump_table_insn)) == ADDR_DIFF_VEC)
3904 rtx jump_table = PATTERN (jump_table_insn);
3905 int n_labels = XVECLEN (jump_table, 1);
3906 int best_count = -1;
3909 for (i = 0; i < n_labels; i++)
3913 for (j = i + 1; j < n_labels; j++)
3914 if (XEXP (XVECEXP (jump_table, 1, i), 0)
3915 == XEXP (XVECEXP (jump_table, 1, j), 0))
3918 if (count > best_count)
3919 best_count = count, best_label = XVECEXP (jump_table, 1, i);
3925 operands[3] = best_label;
3926 return \"addq %0,$29,%2\;jmp $31,(%2),%3\";
3929 return \"addq %0,$29,%2\;jmp $31,(%2),0\";
3931 [(set_attr "type" "ibr")
3932 (set_attr "length" "8")])
3936 (match_operand:DI 0 "register_operand" "r"))
3937 (use (label_ref (match_operand 1 "" "")))]
3938 "TARGET_WINDOWS_NT && next_active_insn (insn) != 0
3939 && GET_CODE (PATTERN (next_active_insn (insn))) == ADDR_DIFF_VEC
3940 && PREV_INSN (next_active_insn (insn)) == operands[1]"
3942 { rtx best_label = 0;
3943 rtx jump_table_insn = next_active_insn (operands[1]);
3945 if (GET_CODE (jump_table_insn) == JUMP_INSN
3946 && GET_CODE (PATTERN (jump_table_insn)) == ADDR_DIFF_VEC)
3948 rtx jump_table = PATTERN (jump_table_insn);
3949 int n_labels = XVECLEN (jump_table, 1);
3950 int best_count = -1;
3953 for (i = 0; i < n_labels; i++)
3957 for (j = i + 1; j < n_labels; j++)
3958 if (XEXP (XVECEXP (jump_table, 1, i), 0)
3959 == XEXP (XVECEXP (jump_table, 1, j), 0))
3962 if (count > best_count)
3963 best_count = count, best_label = XVECEXP (jump_table, 1, i);
3969 operands[2] = best_label;
3970 return \"jmp $31,(%0),%2\";
3973 return \"jmp $31,(%0),0\";
3975 [(set_attr "type" "ibr")])
3978 ;; op 0 is table offset
3979 ;; op 1 is table label
3984 (plus (match_operand:DI 0 "register_operand" "r")
3985 (label_ref (match_operand 1 "" ""))))]
3988 [(set_attr "type" "ibr")])
3990 ;; Cache flush. Used by INITIALIZE_TRAMPOLINE. 0x86 is PAL_imb, but we don't
3991 ;; want to have to include pal.h in our .s file.
3993 ;; Technically the type for call_pal is jsr, but we use that for determining
3994 ;; if we need a GP. Use ibr instead since it has the same EV5 scheduling
3997 [(unspec_volatile [(const_int 0)] 0)]
4000 [(set_attr "type" "ibr")])
4002 ;; Finally, we have the basic data motion insns. The byte and word insns
4003 ;; are done via define_expand. Start with the floating-point insns, since
4004 ;; they are simpler.
4007 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,r,r,m,m")
4008 (match_operand:SF 1 "input_operand" "fG,m,rG,m,fG,r"))]
4010 && (register_operand (operands[0], SFmode)
4011 || reg_or_fp0_operand (operands[1], SFmode))"
4019 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
4022 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,r,r,m,m,f,*r")
4023 (match_operand:SF 1 "input_operand" "fG,m,rG,m,fG,r,r,*f"))]
4025 && (register_operand (operands[0], SFmode)
4026 || reg_or_fp0_operand (operands[1], SFmode))"
4036 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
4039 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,r,r,m,m")
4040 (match_operand:DF 1 "input_operand" "fG,m,rG,m,fG,r"))]
4042 && (register_operand (operands[0], DFmode)
4043 || reg_or_fp0_operand (operands[1], DFmode))"
4051 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
4054 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,r,r,m,m,f,*r")
4055 (match_operand:DF 1 "input_operand" "fG,m,rG,m,fG,r,r,*f"))]
4057 && (register_operand (operands[0], DFmode)
4058 || reg_or_fp0_operand (operands[1], DFmode))"
4068 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
4070 (define_expand "movsf"
4071 [(set (match_operand:SF 0 "nonimmediate_operand" "")
4072 (match_operand:SF 1 "general_operand" ""))]
4076 if (GET_CODE (operands[0]) == MEM
4077 && ! reg_or_fp0_operand (operands[1], SFmode))
4078 operands[1] = force_reg (SFmode, operands[1]);
4081 (define_expand "movdf"
4082 [(set (match_operand:DF 0 "nonimmediate_operand" "")
4083 (match_operand:DF 1 "general_operand" ""))]
4087 if (GET_CODE (operands[0]) == MEM
4088 && ! reg_or_fp0_operand (operands[1], DFmode))
4089 operands[1] = force_reg (DFmode, operands[1]);
4093 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m,f,f,m")
4094 (match_operand:SI 1 "input_operand" "rJ,K,L,m,rJ,fJ,m,f"))]
4095 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS && ! TARGET_FIX
4096 && (register_operand (operands[0], SImode)
4097 || reg_or_0_operand (operands[1], SImode))"
4107 [(set_attr "type" "ilog,iadd,iadd,ild,ist,fcpys,fld,fst")])
4110 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m,f,f,m,r,*f")
4111 (match_operand:SI 1 "input_operand" "rJ,K,L,m,rJ,fJ,m,f,f,*r"))]
4112 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS && TARGET_FIX
4113 && (register_operand (operands[0], SImode)
4114 || reg_or_0_operand (operands[1], SImode))"
4126 [(set_attr "type" "ilog,iadd,iadd,ild,ist,fcpys,fld,fst,ftoi,itof")])
4129 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m,f,f,m")
4130 (match_operand:SI 1 "input_operand" "rJ,K,L,s,m,rJ,fJ,m,f"))]
4131 "(TARGET_WINDOWS_NT || TARGET_OPEN_VMS)
4132 && (register_operand (operands[0], SImode)
4133 || reg_or_0_operand (operands[1], SImode))"
4144 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst")])
4147 [(set (match_operand:HI 0 "register_operand" "=r,r")
4148 (match_operand:HI 1 "input_operand" "rJ,n"))]
4150 && (register_operand (operands[0], HImode)
4151 || register_operand (operands[1], HImode))"
4155 [(set_attr "type" "ilog,iadd")])
4158 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
4159 (match_operand:HI 1 "input_operand" "rJ,n,m,rJ"))]
4161 && (register_operand (operands[0], HImode)
4162 || reg_or_0_operand (operands[1], HImode))"
4168 [(set_attr "type" "ilog,iadd,ild,ist")])
4171 [(set (match_operand:QI 0 "register_operand" "=r,r")
4172 (match_operand:QI 1 "input_operand" "rJ,n"))]
4174 && (register_operand (operands[0], QImode)
4175 || register_operand (operands[1], QImode))"
4179 [(set_attr "type" "ilog,iadd")])
4182 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m")
4183 (match_operand:QI 1 "input_operand" "rJ,n,m,rJ"))]
4185 && (register_operand (operands[0], QImode)
4186 || reg_or_0_operand (operands[1], QImode))"
4192 [(set_attr "type" "ilog,iadd,ild,ist")])
4194 ;; We do two major things here: handle mem->mem and construct long
4197 (define_expand "movsi"
4198 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4199 (match_operand:SI 1 "general_operand" ""))]
4203 if (GET_CODE (operands[0]) == MEM
4204 && ! reg_or_0_operand (operands[1], SImode))
4205 operands[1] = force_reg (SImode, operands[1]);
4207 if (! CONSTANT_P (operands[1]) || input_operand (operands[1], SImode))
4209 else if (GET_CODE (operands[1]) == CONST_INT)
4212 = alpha_emit_set_const (operands[0], SImode, INTVAL (operands[1]), 3);
4213 if (rtx_equal_p (operands[0], operands[1]))
4218 ;; Split a load of a large constant into the appropriate two-insn
4222 [(set (match_operand:SI 0 "register_operand" "")
4223 (match_operand:SI 1 "const_int_operand" ""))]
4224 "! add_operand (operands[1], SImode)"
4225 [(set (match_dup 0) (match_dup 2))
4226 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
4229 = alpha_emit_set_const (operands[0], SImode, INTVAL (operands[1]), 2);
4231 if (tem == operands[0])
4238 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,m,f,f,Q")
4239 (match_operand:DI 1 "input_operand" "rJ,K,L,s,m,rJ,fJ,Q,f"))]
4241 && (register_operand (operands[0], DImode)
4242 || reg_or_0_operand (operands[1], DImode))"
4253 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst")])
4256 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,m,f,f,Q,r,*f")
4257 (match_operand:DI 1 "input_operand" "rJ,K,L,s,m,rJ,fJ,Q,f,f,*r"))]
4259 && (register_operand (operands[0], DImode)
4260 || reg_or_0_operand (operands[1], DImode))"
4273 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof")])
4275 ;; We do three major things here: handle mem->mem, put 64-bit constants in
4276 ;; memory, and construct long 32-bit constants.
4278 (define_expand "movdi"
4279 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4280 (match_operand:DI 1 "general_operand" ""))]
4286 if (GET_CODE (operands[0]) == MEM
4287 && ! reg_or_0_operand (operands[1], DImode))
4288 operands[1] = force_reg (DImode, operands[1]);
4290 if (! CONSTANT_P (operands[1]) || input_operand (operands[1], DImode))
4292 else if (GET_CODE (operands[1]) == CONST_INT
4293 && (tem = alpha_emit_set_const (operands[0], DImode,
4294 INTVAL (operands[1]), 3)) != 0)
4296 if (rtx_equal_p (tem, operands[0]))
4301 else if (CONSTANT_P (operands[1]))
4303 if (TARGET_BUILD_CONSTANTS)
4305 HOST_WIDE_INT i0, i1;
4307 if (GET_CODE (operands[1]) == CONST_INT)
4309 i0 = INTVAL (operands[1]);
4312 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
4314 #if HOST_BITS_PER_WIDE_INT >= 64
4315 i0 = CONST_DOUBLE_LOW (operands[1]);
4318 i0 = CONST_DOUBLE_LOW (operands[1]);
4319 i1 = CONST_DOUBLE_HIGH (operands[1]);
4325 tem = alpha_emit_set_long_const (operands[0], i0, i1);
4326 if (rtx_equal_p (tem, operands[0]))
4333 operands[1] = force_const_mem (DImode, operands[1]);
4334 if (reload_in_progress)
4336 emit_move_insn (operands[0], XEXP (operands[1], 0));
4337 operands[1] = copy_rtx (operands[1]);
4338 XEXP (operands[1], 0) = operands[0];
4341 operands[1] = validize_mem (operands[1]);
4348 ;; Split a load of a large constant into the appropriate two-insn
4352 [(set (match_operand:DI 0 "register_operand" "")
4353 (match_operand:DI 1 "const_int_operand" ""))]
4354 "! add_operand (operands[1], DImode)"
4355 [(set (match_dup 0) (match_dup 2))
4356 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
4359 = alpha_emit_set_const (operands[0], DImode, INTVAL (operands[1]), 2);
4361 if (tem == operands[0])
4367 ;; These are the partial-word cases.
4369 ;; First we have the code to load an aligned word. Operand 0 is the register
4370 ;; in which to place the result. It's mode is QImode or HImode. Operand 1
4371 ;; is an SImode MEM at the low-order byte of the proper word. Operand 2 is the
4372 ;; number of bits within the word that the value is. Operand 3 is an SImode
4373 ;; scratch register. If operand 0 is a hard register, operand 3 may be the
4374 ;; same register. It is allowed to conflict with operand 1 as well.
4376 (define_expand "aligned_loadqi"
4377 [(set (match_operand:SI 3 "register_operand" "")
4378 (match_operand:SI 1 "memory_operand" ""))
4379 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
4380 (zero_extract:DI (subreg:DI (match_dup 3) 0)
4382 (match_operand:DI 2 "const_int_operand" "")))]
4387 (define_expand "aligned_loadhi"
4388 [(set (match_operand:SI 3 "register_operand" "")
4389 (match_operand:SI 1 "memory_operand" ""))
4390 (set (subreg:DI (match_operand:HI 0 "register_operand" "") 0)
4391 (zero_extract:DI (subreg:DI (match_dup 3) 0)
4393 (match_operand:DI 2 "const_int_operand" "")))]
4398 ;; Similar for unaligned loads, where we use the sequence from the
4399 ;; Alpha Architecture manual.
4401 ;; Operand 1 is the address. Operands 2 and 3 are temporaries, where
4402 ;; operand 3 can overlap the input and output registers.
4404 (define_expand "unaligned_loadqi"
4405 [(set (match_operand:DI 2 "register_operand" "")
4406 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
4408 (set (match_operand:DI 3 "register_operand" "")
4410 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
4411 (zero_extract:DI (match_dup 2)
4413 (ashift:DI (match_dup 3) (const_int 3))))]
4417 (define_expand "unaligned_loadhi"
4418 [(set (match_operand:DI 2 "register_operand" "")
4419 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
4421 (set (match_operand:DI 3 "register_operand" "")
4423 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
4424 (zero_extract:DI (match_dup 2)
4426 (ashift:DI (match_dup 3) (const_int 3))))]
4430 ;; Storing an aligned byte or word requires two temporaries. Operand 0 is the
4431 ;; aligned SImode MEM. Operand 1 is the register containing the
4432 ;; byte or word to store. Operand 2 is the number of bits within the word that
4433 ;; the value should be placed. Operands 3 and 4 are SImode temporaries.
4435 (define_expand "aligned_store"
4436 [(set (match_operand:SI 3 "register_operand" "")
4437 (match_operand:SI 0 "memory_operand" ""))
4438 (set (subreg:DI (match_dup 3) 0)
4439 (and:DI (subreg:DI (match_dup 3) 0) (match_dup 5)))
4440 (set (subreg:DI (match_operand:SI 4 "register_operand" "") 0)
4441 (ashift:DI (zero_extend:DI (match_operand 1 "register_operand" ""))
4442 (match_operand:DI 2 "const_int_operand" "")))
4443 (set (subreg:DI (match_dup 4) 0)
4444 (ior:DI (subreg:DI (match_dup 4) 0) (subreg:DI (match_dup 3) 0)))
4445 (set (match_dup 0) (match_dup 4))]
4448 { operands[5] = GEN_INT (~ (GET_MODE_MASK (GET_MODE (operands[1]))
4449 << INTVAL (operands[2])));
4452 ;; For the unaligned byte and halfword cases, we use code similar to that
4453 ;; in the ;; Architecture book, but reordered to lower the number of registers
4454 ;; required. Operand 0 is the address. Operand 1 is the data to store.
4455 ;; Operands 2, 3, and 4 are DImode temporaries, where operands 2 and 4 may
4456 ;; be the same temporary, if desired. If the address is in a register,
4457 ;; operand 2 can be that register.
4459 (define_expand "unaligned_storeqi"
4460 [(set (match_operand:DI 3 "register_operand" "")
4461 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
4463 (set (match_operand:DI 2 "register_operand" "")
4466 (and:DI (not:DI (ashift:DI (const_int 255)
4467 (ashift:DI (match_dup 2) (const_int 3))))
4469 (set (match_operand:DI 4 "register_operand" "")
4470 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
4471 (ashift:DI (match_dup 2) (const_int 3))))
4472 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
4473 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
4478 (define_expand "unaligned_storehi"
4479 [(set (match_operand:DI 3 "register_operand" "")
4480 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
4482 (set (match_operand:DI 2 "register_operand" "")
4485 (and:DI (not:DI (ashift:DI (const_int 65535)
4486 (ashift:DI (match_dup 2) (const_int 3))))
4488 (set (match_operand:DI 4 "register_operand" "")
4489 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
4490 (ashift:DI (match_dup 2) (const_int 3))))
4491 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
4492 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
4497 ;; Here are the define_expand's for QI and HI moves that use the above
4498 ;; patterns. We have the normal sets, plus the ones that need scratch
4499 ;; registers for reload.
4501 (define_expand "movqi"
4502 [(set (match_operand:QI 0 "nonimmediate_operand" "")
4503 (match_operand:QI 1 "general_operand" ""))]
4509 if (GET_CODE (operands[0]) == MEM
4510 && ! reg_or_0_operand (operands[1], QImode))
4511 operands[1] = force_reg (QImode, operands[1]);
4513 if (GET_CODE (operands[1]) == CONST_INT
4514 && ! input_operand (operands[1], QImode))
4516 operands[1] = alpha_emit_set_const (operands[0], QImode,
4517 INTVAL (operands[1]), 3);
4519 if (rtx_equal_p (operands[0], operands[1]))
4526 /* If the output is not a register, the input must be. */
4527 if (GET_CODE (operands[0]) == MEM)
4528 operands[1] = force_reg (QImode, operands[1]);
4530 /* Handle four memory cases, unaligned and aligned for either the input
4531 or the output. The only case where we can be called during reload is
4532 for aligned loads; all other cases require temporaries. */
4534 if (GET_CODE (operands[1]) == MEM
4535 || (GET_CODE (operands[1]) == SUBREG
4536 && GET_CODE (SUBREG_REG (operands[1])) == MEM)
4537 || (reload_in_progress && GET_CODE (operands[1]) == REG
4538 && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
4539 || (reload_in_progress && GET_CODE (operands[1]) == SUBREG
4540 && GET_CODE (SUBREG_REG (operands[1])) == REG
4541 && REGNO (SUBREG_REG (operands[1])) >= FIRST_PSEUDO_REGISTER))
4543 if (aligned_memory_operand (operands[1], QImode))
4545 if (reload_in_progress)
4547 emit_insn (gen_reload_inqi_help
4548 (operands[0], operands[1],
4549 gen_rtx_REG (SImode, REGNO (operands[0]))));
4553 rtx aligned_mem, bitnum;
4554 rtx scratch = gen_reg_rtx (SImode);
4556 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
4558 emit_insn (gen_aligned_loadqi (operands[0], aligned_mem, bitnum,
4564 /* Don't pass these as parameters since that makes the generated
4565 code depend on parameter evaluation order which will cause
4566 bootstrap failures. */
4568 rtx temp1 = gen_reg_rtx (DImode);
4569 rtx temp2 = gen_reg_rtx (DImode);
4571 = gen_unaligned_loadqi (operands[0],
4572 get_unaligned_address (operands[1], 0),
4575 alpha_set_memflags (seq, operands[1]);
4582 else if (GET_CODE (operands[0]) == MEM
4583 || (GET_CODE (operands[0]) == SUBREG
4584 && GET_CODE (SUBREG_REG (operands[0])) == MEM)
4585 || (reload_in_progress && GET_CODE (operands[0]) == REG
4586 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)
4587 || (reload_in_progress && GET_CODE (operands[0]) == SUBREG
4588 && GET_CODE (SUBREG_REG (operands[0])) == REG
4589 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))
4591 if (aligned_memory_operand (operands[0], QImode))
4593 rtx aligned_mem, bitnum;
4594 rtx temp1 = gen_reg_rtx (SImode);
4595 rtx temp2 = gen_reg_rtx (SImode);
4597 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
4599 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
4604 rtx temp1 = gen_reg_rtx (DImode);
4605 rtx temp2 = gen_reg_rtx (DImode);
4606 rtx temp3 = gen_reg_rtx (DImode);
4608 = gen_unaligned_storeqi (get_unaligned_address (operands[0], 0),
4609 operands[1], temp1, temp2, temp3);
4611 alpha_set_memflags (seq, operands[0]);
4619 (define_expand "movhi"
4620 [(set (match_operand:HI 0 "nonimmediate_operand" "")
4621 (match_operand:HI 1 "general_operand" ""))]
4627 if (GET_CODE (operands[0]) == MEM
4628 && ! reg_or_0_operand (operands[1], HImode))
4629 operands[1] = force_reg (HImode, operands[1]);
4631 if (GET_CODE (operands[1]) == CONST_INT
4632 && ! input_operand (operands[1], HImode))
4634 operands[1] = alpha_emit_set_const (operands[0], HImode,
4635 INTVAL (operands[1]), 3);
4637 if (rtx_equal_p (operands[0], operands[1]))
4644 /* If the output is not a register, the input must be. */
4645 if (GET_CODE (operands[0]) == MEM)
4646 operands[1] = force_reg (HImode, operands[1]);
4648 /* Handle four memory cases, unaligned and aligned for either the input
4649 or the output. The only case where we can be called during reload is
4650 for aligned loads; all other cases require temporaries. */
4652 if (GET_CODE (operands[1]) == MEM
4653 || (GET_CODE (operands[1]) == SUBREG
4654 && GET_CODE (SUBREG_REG (operands[1])) == MEM)
4655 || (reload_in_progress && GET_CODE (operands[1]) == REG
4656 && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
4657 || (reload_in_progress && GET_CODE (operands[1]) == SUBREG
4658 && GET_CODE (SUBREG_REG (operands[1])) == REG
4659 && REGNO (SUBREG_REG (operands[1])) >= FIRST_PSEUDO_REGISTER))
4661 if (aligned_memory_operand (operands[1], HImode))
4663 if (reload_in_progress)
4665 emit_insn (gen_reload_inhi_help
4666 (operands[0], operands[1],
4667 gen_rtx_REG (SImode, REGNO (operands[0]))));
4671 rtx aligned_mem, bitnum;
4672 rtx scratch = gen_reg_rtx (SImode);
4674 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
4676 emit_insn (gen_aligned_loadhi (operands[0], aligned_mem, bitnum,
4682 /* Don't pass these as parameters since that makes the generated
4683 code depend on parameter evaluation order which will cause
4684 bootstrap failures. */
4686 rtx temp1 = gen_reg_rtx (DImode);
4687 rtx temp2 = gen_reg_rtx (DImode);
4689 = gen_unaligned_loadhi (operands[0],
4690 get_unaligned_address (operands[1], 0),
4693 alpha_set_memflags (seq, operands[1]);
4700 else if (GET_CODE (operands[0]) == MEM
4701 || (GET_CODE (operands[0]) == SUBREG
4702 && GET_CODE (SUBREG_REG (operands[0])) == MEM)
4703 || (reload_in_progress && GET_CODE (operands[0]) == REG
4704 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)
4705 || (reload_in_progress && GET_CODE (operands[0]) == SUBREG
4706 && GET_CODE (SUBREG_REG (operands[0])) == REG
4707 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))
4709 if (aligned_memory_operand (operands[0], HImode))
4711 rtx aligned_mem, bitnum;
4712 rtx temp1 = gen_reg_rtx (SImode);
4713 rtx temp2 = gen_reg_rtx (SImode);
4715 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
4717 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
4722 rtx temp1 = gen_reg_rtx (DImode);
4723 rtx temp2 = gen_reg_rtx (DImode);
4724 rtx temp3 = gen_reg_rtx (DImode);
4726 = gen_unaligned_storehi (get_unaligned_address (operands[0], 0),
4727 operands[1], temp1, temp2, temp3);
4729 alpha_set_memflags (seq, operands[0]);
4738 ;; Here are the versions for reload. Note that in the unaligned cases
4739 ;; we know that the operand must not be a pseudo-register because stack
4740 ;; slots are always aligned references.
4742 (define_expand "reload_inqi"
4743 [(parallel [(match_operand:QI 0 "register_operand" "=r")
4744 (match_operand:QI 1 "any_memory_operand" "m")
4745 (match_operand:TI 2 "register_operand" "=&r")])]
4751 if (GET_CODE (operands[1]) != MEM)
4754 if (aligned_memory_operand (operands[1], QImode))
4756 seq = gen_reload_inqi_help (operands[0], operands[1],
4757 gen_rtx_REG (SImode, REGNO (operands[2])));
4763 /* It is possible that one of the registers we got for operands[2]
4764 might coincide with that of operands[0] (which is why we made
4765 it TImode). Pick the other one to use as our scratch. */
4766 if (REGNO (operands[0]) == REGNO (operands[2]))
4767 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
4769 scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
4771 addr = get_unaligned_address (operands[1], 0);
4772 seq = gen_unaligned_loadqi (operands[0], addr, scratch,
4773 gen_rtx_REG (DImode, REGNO (operands[0])));
4774 alpha_set_memflags (seq, operands[1]);
4780 (define_expand "reload_inhi"
4781 [(parallel [(match_operand:HI 0 "register_operand" "=r")
4782 (match_operand:HI 1 "any_memory_operand" "m")
4783 (match_operand:TI 2 "register_operand" "=&r")])]
4789 if (GET_CODE (operands[1]) != MEM)
4792 if (aligned_memory_operand (operands[1], HImode))
4794 seq = gen_reload_inhi_help (operands[0], operands[1],
4795 gen_rtx_REG (SImode, REGNO (operands[2])));
4801 /* It is possible that one of the registers we got for operands[2]
4802 might coincide with that of operands[0] (which is why we made
4803 it TImode). Pick the other one to use as our scratch. */
4804 if (REGNO (operands[0]) == REGNO (operands[2]))
4805 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
4807 scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
4809 addr = get_unaligned_address (operands[1], 0);
4810 seq = gen_unaligned_loadhi (operands[0], addr, scratch,
4811 gen_rtx_REG (DImode, REGNO (operands[0])));
4812 alpha_set_memflags (seq, operands[1]);
4818 (define_expand "reload_outqi"
4819 [(parallel [(match_operand:QI 0 "any_memory_operand" "=m")
4820 (match_operand:QI 1 "register_operand" "r")
4821 (match_operand:TI 2 "register_operand" "=&r")])]
4825 if (GET_CODE (operands[0]) != MEM)
4828 if (aligned_memory_operand (operands[0], QImode))
4830 emit_insn (gen_reload_outqi_help
4831 (operands[0], operands[1],
4832 gen_rtx_REG (SImode, REGNO (operands[2])),
4833 gen_rtx_REG (SImode, REGNO (operands[2]) + 1)));
4837 rtx addr = get_unaligned_address (operands[0], 0);
4838 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
4839 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
4840 rtx scratch3 = scratch1;
4843 if (GET_CODE (addr) == REG)
4846 seq = gen_unaligned_storeqi (addr, operands[1], scratch1,
4847 scratch2, scratch3);
4848 alpha_set_memflags (seq, operands[0]);
4854 (define_expand "reload_outhi"
4855 [(parallel [(match_operand:HI 0 "any_memory_operand" "=m")
4856 (match_operand:HI 1 "register_operand" "r")
4857 (match_operand:TI 2 "register_operand" "=&r")])]
4861 if (GET_CODE (operands[0]) != MEM)
4864 if (aligned_memory_operand (operands[0], HImode))
4866 emit_insn (gen_reload_outhi_help
4867 (operands[0], operands[1],
4868 gen_rtx_REG (SImode, REGNO (operands[2])),
4869 gen_rtx_REG (SImode, REGNO (operands[2]) + 1)));
4873 rtx addr = get_unaligned_address (operands[0], 0);
4874 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
4875 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
4876 rtx scratch3 = scratch1;
4879 if (GET_CODE (addr) == REG)
4882 seq = gen_unaligned_storehi (addr, operands[1], scratch1,
4883 scratch2, scratch3);
4884 alpha_set_memflags (seq, operands[0]);
4890 ;; Helpers for the above. The way reload is structured, we can't
4891 ;; always get a proper address for a stack slot during reload_foo
4892 ;; expansion, so we must delay our address manipulations until after.
4894 (define_insn "reload_inqi_help"
4895 [(set (match_operand:QI 0 "register_operand" "=r")
4896 (match_operand:QI 1 "memory_operand" "m"))
4897 (clobber (match_operand:SI 2 "register_operand" "=r"))]
4898 "! TARGET_BWX && (reload_in_progress || reload_completed)"
4901 (define_insn "reload_inhi_help"
4902 [(set (match_operand:HI 0 "register_operand" "=r")
4903 (match_operand:HI 1 "memory_operand" "m"))
4904 (clobber (match_operand:SI 2 "register_operand" "=r"))]
4905 "! TARGET_BWX && (reload_in_progress || reload_completed)"
4908 (define_insn "reload_outqi_help"
4909 [(set (match_operand:QI 0 "memory_operand" "=m")
4910 (match_operand:QI 1 "register_operand" "r"))
4911 (clobber (match_operand:SI 2 "register_operand" "=r"))
4912 (clobber (match_operand:SI 3 "register_operand" "=r"))]
4913 "! TARGET_BWX && (reload_in_progress || reload_completed)"
4916 (define_insn "reload_outhi_help"
4917 [(set (match_operand:HI 0 "memory_operand" "=m")
4918 (match_operand:HI 1 "register_operand" "r"))
4919 (clobber (match_operand:SI 2 "register_operand" "=r"))
4920 (clobber (match_operand:SI 3 "register_operand" "=r"))]
4921 "! TARGET_BWX && (reload_in_progress || reload_completed)"
4925 [(set (match_operand:QI 0 "register_operand" "")
4926 (match_operand:QI 1 "memory_operand" ""))
4927 (clobber (match_operand:SI 2 "register_operand" ""))]
4928 "! TARGET_BWX && reload_completed"
4932 rtx aligned_mem, bitnum;
4933 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
4934 emit_insn (gen_aligned_loadqi (operands[0], aligned_mem, bitnum,
4940 [(set (match_operand:HI 0 "register_operand" "")
4941 (match_operand:HI 1 "memory_operand" ""))
4942 (clobber (match_operand:SI 2 "register_operand" ""))]
4943 "! TARGET_BWX && reload_completed"
4947 rtx aligned_mem, bitnum;
4948 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
4949 emit_insn (gen_aligned_loadhi (operands[0], aligned_mem, bitnum,
4955 [(set (match_operand:QI 0 "memory_operand" "")
4956 (match_operand:QI 1 "register_operand" ""))
4957 (clobber (match_operand:SI 2 "register_operand" ""))
4958 (clobber (match_operand:SI 3 "register_operand" ""))]
4959 "! TARGET_BWX && reload_completed"
4963 rtx aligned_mem, bitnum;
4964 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
4965 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
4966 operands[2], operands[3]));
4971 [(set (match_operand:HI 0 "memory_operand" "")
4972 (match_operand:HI 1 "register_operand" ""))
4973 (clobber (match_operand:SI 2 "register_operand" ""))
4974 (clobber (match_operand:SI 3 "register_operand" ""))]
4975 "! TARGET_BWX && reload_completed"
4979 rtx aligned_mem, bitnum;
4980 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
4981 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
4982 operands[2], operands[3]));
4986 ;; Bit field extract patterns which use ext[wlq][lh]
4988 (define_expand "extv"
4989 [(set (match_operand:DI 0 "register_operand" "")
4990 (sign_extract:DI (match_operand:QI 1 "memory_operand" "")
4991 (match_operand:DI 2 "immediate_operand" "")
4992 (match_operand:DI 3 "immediate_operand" "")))]
4996 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
4997 if (INTVAL (operands[3]) % 8 != 0
4998 || (INTVAL (operands[2]) != 16
4999 && INTVAL (operands[2]) != 32
5000 && INTVAL (operands[2]) != 64))
5003 /* From mips.md: extract_bit_field doesn't verify that our source
5004 matches the predicate, so we force it to be a MEM here. */
5005 if (GET_CODE (operands[1]) != MEM)
5008 alpha_expand_unaligned_load (operands[0], operands[1],
5009 INTVAL (operands[2]) / 8,
5010 INTVAL (operands[3]) / 8, 1);
5014 (define_expand "extzv"
5015 [(set (match_operand:DI 0 "register_operand" "")
5016 (zero_extract:DI (match_operand:DI 1 "nonimmediate_operand" "")
5017 (match_operand:DI 2 "immediate_operand" "")
5018 (match_operand:DI 3 "immediate_operand" "")))]
5022 /* We can do 8, 16, 32 and 64 bit fields, if aligned on byte boundaries. */
5023 if (INTVAL (operands[3]) % 8 != 0
5024 || (INTVAL (operands[2]) != 8
5025 && INTVAL (operands[2]) != 16
5026 && INTVAL (operands[2]) != 32
5027 && INTVAL (operands[2]) != 64))
5030 if (GET_CODE (operands[1]) == MEM)
5032 /* Fail 8 bit fields, falling back on a simple byte load. */
5033 if (INTVAL (operands[2]) == 8)
5036 alpha_expand_unaligned_load (operands[0], operands[1],
5037 INTVAL (operands[2]) / 8,
5038 INTVAL (operands[3]) / 8, 0);
5043 (define_expand "insv"
5044 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "")
5045 (match_operand:DI 1 "immediate_operand" "")
5046 (match_operand:DI 2 "immediate_operand" ""))
5047 (match_operand:DI 3 "register_operand" ""))]
5051 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
5052 if (INTVAL (operands[2]) % 8 != 0
5053 || (INTVAL (operands[1]) != 16
5054 && INTVAL (operands[1]) != 32
5055 && INTVAL (operands[1]) != 64))
5058 /* From mips.md: store_bit_field doesn't verify that our source
5059 matches the predicate, so we force it to be a MEM here. */
5060 if (GET_CODE (operands[0]) != MEM)
5063 alpha_expand_unaligned_store (operands[0], operands[3],
5064 INTVAL (operands[1]) / 8,
5065 INTVAL (operands[2]) / 8);
5071 ;; Block move/clear, see alpha.c for more details.
5072 ;; Argument 0 is the destination
5073 ;; Argument 1 is the source
5074 ;; Argument 2 is the length
5075 ;; Argument 3 is the alignment
5077 (define_expand "movstrqi"
5078 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
5079 (match_operand:BLK 1 "memory_operand" ""))
5080 (use (match_operand:DI 2 "immediate_operand" ""))
5081 (use (match_operand:DI 3 "immediate_operand" ""))])]
5085 if (alpha_expand_block_move (operands))
5091 (define_expand "clrstrqi"
5092 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
5094 (use (match_operand:DI 1 "immediate_operand" ""))
5095 (use (match_operand:DI 2 "immediate_operand" ""))])]
5099 if (alpha_expand_block_clear (operands))
5105 ;; Subroutine of stack space allocation. Perform a stack probe.
5106 (define_expand "probe_stack"
5107 [(set (match_dup 1) (match_operand:DI 0 "const_int_operand" ""))]
5111 operands[1] = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx,
5112 INTVAL (operands[0])));
5113 MEM_VOLATILE_P (operands[1]) = 1;
5115 operands[0] = const0_rtx;
5118 ;; This is how we allocate stack space. If we are allocating a
5119 ;; constant amount of space and we know it is less than 4096
5120 ;; bytes, we need do nothing.
5122 ;; If it is more than 4096 bytes, we need to probe the stack
5124 (define_expand "allocate_stack"
5126 (plus:DI (reg:DI 30)
5127 (match_operand:DI 1 "reg_or_cint_operand" "")))
5128 (set (match_operand:DI 0 "register_operand" "=r")
5133 if (GET_CODE (operands[1]) == CONST_INT
5134 && INTVAL (operands[1]) < 32768)
5136 if (INTVAL (operands[1]) >= 4096)
5138 /* We do this the same way as in the prologue and generate explicit
5139 probes. Then we update the stack by the constant. */
5143 emit_insn (gen_probe_stack (GEN_INT (- probed)));
5144 while (probed + 8192 < INTVAL (operands[1]))
5145 emit_insn (gen_probe_stack (GEN_INT (- (probed += 8192))));
5147 if (probed + 4096 < INTVAL (operands[1]))
5148 emit_insn (gen_probe_stack (GEN_INT (- INTVAL(operands[1]))));
5151 operands[1] = GEN_INT (- INTVAL (operands[1]));
5152 operands[2] = virtual_stack_dynamic_rtx;
5157 rtx loop_label = gen_label_rtx ();
5158 rtx want = gen_reg_rtx (Pmode);
5159 rtx tmp = gen_reg_rtx (Pmode);
5162 emit_insn (gen_subdi3 (want, stack_pointer_rtx,
5163 force_reg (Pmode, operands[1])));
5164 emit_insn (gen_adddi3 (tmp, stack_pointer_rtx, GEN_INT (-4096)));
5166 if (GET_CODE (operands[1]) != CONST_INT)
5168 out_label = gen_label_rtx ();
5169 emit_insn (gen_cmpdi (want, tmp));
5170 emit_jump_insn (gen_bgeu (out_label));
5173 emit_label (loop_label);
5174 memref = gen_rtx_MEM (DImode, tmp);
5175 MEM_VOLATILE_P (memref) = 1;
5176 emit_move_insn (memref, const0_rtx);
5177 emit_insn (gen_adddi3 (tmp, tmp, GEN_INT(-8192)));
5178 emit_insn (gen_cmpdi (tmp, want));
5179 emit_jump_insn (gen_bgtu (loop_label));
5181 gen_rtx_USE (VOIDmode, tmp);
5183 memref = gen_rtx_MEM (DImode, want);
5184 MEM_VOLATILE_P (memref) = 1;
5185 emit_move_insn (memref, const0_rtx);
5188 emit_label (out_label);
5190 emit_move_insn (stack_pointer_rtx, want);
5191 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
5196 ;; This is used by alpha_expand_prolog to do the same thing as above,
5197 ;; except we cannot at that time generate new basic blocks, so we hide
5198 ;; the loop in this one insn.
5200 (define_insn "prologue_stack_probe_loop"
5201 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")
5202 (match_operand:DI 1 "register_operand" "r")] 5)]
5206 operands[2] = gen_label_rtx ();
5207 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
5208 CODE_LABEL_NUMBER (operands[2]));
5210 return \"stq $31,-8192(%1)\;subq %0,1,%0\;lda %1,-8192(%1)\;bne %0,%l2\";
5212 [(set_attr "length" "16")
5213 (set_attr "type" "multi")])
5215 (define_expand "prologue"
5216 [(clobber (const_int 0))]
5218 "alpha_expand_prologue (); DONE;")
5220 (define_insn "init_fp"
5221 [(set (match_operand:DI 0 "register_operand" "=r")
5222 (match_operand:DI 1 "register_operand" "r"))
5223 (clobber (mem:BLK (match_operand:DI 2 "register_operand" "=r")))]
5227 (define_expand "epilogue"
5228 [(clobber (const_int 0))]
5230 "alpha_expand_epilogue (); DONE;")
5232 (define_expand "eh_epilogue"
5233 [(use (match_operand:DI 0 "register_operand" "r"))
5234 (use (match_operand:DI 1 "register_operand" "r"))
5235 (use (match_operand:DI 2 "register_operand" "r"))]
5239 current_function->machine->eh_epilogue_sp_ofs = operands[1];
5240 if (GET_CODE (operands[2]) != REG || REGNO (operands[2]) != 26)
5242 rtx ra = gen_rtx_REG (Pmode, 26);
5243 emit_move_insn (ra, operands[2]);
5248 ;; In creating a large stack frame, NT _must_ use ldah+lda to load
5249 ;; the frame size into a register. We use this pattern to ensure
5250 ;; we get lda instead of addq.
5251 (define_insn "nt_lda"
5252 [(set (match_operand:DI 0 "register_operand" "=r")
5253 (unspec:DI [(match_dup 0)
5254 (match_operand:DI 1 "const_int_operand" "n")] 6))]
5258 (define_expand "builtin_longjmp"
5259 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")] 3)]
5260 "! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT"
5263 /* The elements of the buffer are, in order: */
5264 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
5265 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 8));
5266 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 16));
5267 rtx pv = gen_rtx_REG (Pmode, 27);
5269 /* This bit is the same as expand_builtin_longjmp. */
5270 emit_move_insn (hard_frame_pointer_rtx, fp);
5271 emit_move_insn (pv, lab);
5272 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
5273 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
5274 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
5276 /* Load the label we are jumping through into $27 so that we know
5277 where to look for it when we get back to setjmp's function for
5278 restoring the gp. */
5279 emit_indirect_jump (pv);
5283 (define_insn "builtin_setjmp_receiver"
5284 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] 2)]
5285 "! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT && TARGET_AS_CAN_SUBTRACT_LABELS"
5286 "\\n$LSJ%=:\;ldgp $29,$LSJ%=-%l0($27)"
5287 [(set_attr "length" "8")
5288 (set_attr "type" "multi")])
5291 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] 2)]
5292 "! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT"
5293 "br $29,$LSJ%=\\n$LSJ%=:\;ldgp $29,0($29)"
5294 [(set_attr "length" "12")
5295 (set_attr "type" "multi")])
5297 (define_insn "exception_receiver"
5298 [(unspec_volatile [(const_int 0)] 7)]
5299 "! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT"
5300 "br $29,$LSJ%=\\n$LSJ%=:\;ldgp $29,0($29)"
5301 [(set_attr "length" "12")
5302 (set_attr "type" "multi")])
5304 (define_expand "nonlocal_goto_receiver"
5305 [(unspec_volatile [(const_int 0)] 1)
5306 (set (reg:DI 27) (mem:DI (reg:DI 29)))
5307 (unspec_volatile [(const_int 0)] 1)
5312 (define_insn "arg_home"
5313 [(unspec [(const_int 0)] 0)
5328 (clobber (mem:BLK (const_int 0)))
5329 (clobber (reg:DI 24))
5330 (clobber (reg:DI 25))
5331 (clobber (reg:DI 0))]
5333 "lda $0,OTS$HOME_ARGS\;ldq $0,8($0)\;jsr $0,OTS$HOME_ARGS"
5334 [(set_attr "length" "16")
5335 (set_attr "type" "multi")])
5337 ;; Close the trap shadow of preceeding instructions. This is generated
5340 (define_insn "trapb"
5341 [(unspec_volatile [(const_int 0)] 4)]
5344 [(set_attr "type" "misc")])
5346 ;; No-op instructions used by machine-dependant reorg to preserve
5347 ;; alignment for instruction issue.
5353 [(set_attr "type" "ilog")])
5359 [(set_attr "type" "fcpys")])
5366 (define_insn "realign"
5367 [(unspec_volatile [(match_operand 0 "immediate_operand" "i")] 6)]
5369 ".align %0 #realign")
5371 ;; The call patterns are at the end of the file because their
5372 ;; wildcard operand0 interferes with nice recognition.
5375 [(set (match_operand 0 "" "")
5376 (call (mem:DI (match_operand:DI 1 "call_operand" "r,R,i"))
5377 (match_operand 2 "" "")))
5378 (clobber (reg:DI 27))
5379 (clobber (reg:DI 26))]
5380 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS"
5382 jsr $26,($27),0\;ldgp $29,0($26)
5384 jsr $26,%1\;ldgp $29,0($26)"
5385 [(set_attr "type" "jsr")
5386 (set_attr "length" "12,*,16")])
5389 [(set (match_operand 0 "" "")
5390 (call (mem:DI (match_operand:DI 1 "call_operand" "r,R,i"))
5391 (match_operand 2 "" "")))
5392 (clobber (reg:DI 26))]
5398 [(set_attr "type" "jsr")
5399 (set_attr "length" "*,*,12")])
5402 [(set (match_operand 0 "" "")
5403 (call (mem:DI (match_operand:DI 1 "call_operand" "r,i"))
5404 (match_operand 2 "" "")))
5405 (use (match_operand:DI 3 "nonimmediate_operand" "r,m"))
5408 (clobber (reg:DI 27))]
5411 mov %3,$27\;jsr $26,0\;ldq $27,0($29)
5412 ldq $27,%3\;jsr $26,%1\;ldq $27,0($29)"
5413 [(set_attr "type" "jsr")
5414 (set_attr "length" "12,16")])
5417 ;; Peepholes go at the end.
5419 ;; Optimize sign-extension of SImode loads. This shows up in the wake of
5420 ;; reload when converting fp->int.
5423 [(set (match_operand:SI 0 "register_operand" "=r")
5424 (match_operand:SI 1 "memory_operand" "m"))
5425 (set (match_operand:DI 2 "register_operand" "=r")
5426 (sign_extend:DI (match_dup 0)))]
5427 "dead_or_set_p (next_nonnote_insn (insn), operands[0])"
5429 (sign_extend:DI (match_dup 1)))]
5433 [(set (match_operand:SI 0 "register_operand" "=r")
5434 (match_operand:SI 1 "hard_fp_register_operand" "f"))
5435 (set (match_operand:DI 2 "register_operand" "=r")
5436 (sign_extend:DI (match_dup 0)))]
5437 "TARGET_FIX && dead_or_set_p (next_nonnote_insn (insn), operands[0])"
5439 (sign_extend:DI (match_dup 1)))]