1 ;; Machine description for DEC Alpha for GNU C compiler
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 ;; 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 2, or (at your option)
13 ;; GCC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING. If not, write to
20 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
21 ;; Boston, MA 02111-1307, USA.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;; Uses of UNSPEC in this file:
37 (UNSPEC_UMK_LOAD_CIW 9)
45 (UNSPEC_TLSGD_CALL 15)
46 (UNSPEC_TLSLDM_CALL 16)
68 (UNSPECV_SETJMPR 2) ; builtin_setjmp_receiver
69 (UNSPECV_LONGJMP 3) ; builtin_longjmp
71 (UNSPECV_PSPL 5) ; prologue_stack_probe_loop
73 (UNSPECV_EHR 7) ; exception_receiver
77 (UNSPECV_PLDGP2 11) ; prologue ldgp
82 ;; Where necessary, the suffixes _le and _be are used to distinguish between
83 ;; little-endian and big-endian patterns.
85 ;; Note that the Unicos/Mk assembler does not support the following
86 ;; opcodes: mov, fmov, nop, fnop, unop.
88 ;; Processor type -- this attribute must exactly match the processor_type
89 ;; enumeration in alpha.h.
91 (define_attr "cpu" "ev4,ev5,ev6"
92 (const (symbol_ref "alpha_cpu")))
94 ;; Define an insn type attribute. This is used in function unit delay
95 ;; computations, among other purposes. For the most part, we use the names
96 ;; defined in the EV4 documentation, but add a few that we have to know about
100 "ild,fld,ldsym,ist,fst,ibr,callpal,fbr,jsr,iadd,ilog,shift,icmov,fcmov,
101 icmp,imul,fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
102 (const_string "iadd"))
104 ;; Describe a user's asm statement.
105 (define_asm_attributes
106 [(set_attr "type" "multi")])
108 ;; Define the operand size an insn operates on. Used primarily by mul
109 ;; and div operations that have size dependent timings.
111 (define_attr "opsize" "si,di,udi"
114 ;; The TRAP attribute marks instructions that may generate traps
115 ;; (which are imprecise and may need a trapb if software completion
118 (define_attr "trap" "no,yes"
121 ;; The ROUND_SUFFIX attribute marks which instructions require a
122 ;; rounding-mode suffix. The value NONE indicates no suffix,
123 ;; the value NORMAL indicates a suffix controlled by alpha_fprm.
125 (define_attr "round_suffix" "none,normal,c"
126 (const_string "none"))
128 ;; The TRAP_SUFFIX attribute marks instructions requiring a trap-mode suffix:
130 ;; SU accepts only /su (cmpt et al)
131 ;; SUI accepts only /sui (cvtqt and cvtqs)
132 ;; V_SV accepts /v and /sv (cvtql only)
133 ;; V_SV_SVI accepts /v, /sv and /svi (cvttq only)
134 ;; U_SU_SUI accepts /u, /su and /sui (most fp instructions)
136 ;; The actual suffix emitted is controlled by alpha_fptm.
138 (define_attr "trap_suffix" "none,su,sui,v_sv,v_sv_svi,u_su_sui"
139 (const_string "none"))
141 ;; The length of an instruction sequence in bytes.
143 (define_attr "length" ""
146 ;; The USEGP attribute marks instructions that have relocations that use
149 (define_attr "usegp" "no,yes"
150 (cond [(eq_attr "type" "ldsym,jsr")
152 (eq_attr "type" "ild,fld,ist,fst")
153 (symbol_ref "alpha_find_lo_sum_using_gp(insn)")
155 (const_string "no")))
157 ;; The CANNOT_COPY attribute marks instructions with relocations that
158 ;; cannot easily be duplicated. This includes insns with gpdisp relocs
159 ;; since they have to stay in 1-1 correspondence with one another. This
160 ;; also includes jsr insns, since they must stay in correspondence with
161 ;; the immediately following gpdisp instructions.
163 (define_attr "cannot_copy" "false,true"
164 (const_string "false"))
166 ;; Include scheduling descriptions.
173 ;; Include predicate definitions
175 (include "predicates.md")
178 ;; First define the arithmetic insns. Note that the 32-bit forms also
181 ;; Handle 32-64 bit extension from memory to a floating point register
182 ;; specially, since this occurs frequently in int->double conversions.
184 ;; Note that while we must retain the =f case in the insn for reload's
185 ;; benefit, it should be eliminated after reload, so we should never emit
186 ;; code for that case. But we don't reject the possibility.
188 (define_expand "extendsidi2"
189 [(set (match_operand:DI 0 "register_operand" "")
190 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
194 (define_insn "*cvtlq"
195 [(set (match_operand:DI 0 "register_operand" "=f")
196 (unspec:DI [(match_operand:SF 1 "reg_or_0_operand" "fG")]
200 [(set_attr "type" "fadd")])
202 (define_insn "*extendsidi2_1"
203 [(set (match_operand:DI 0 "register_operand" "=r,r,!*f")
205 (match_operand:SI 1 "nonimmediate_operand" "r,m,m")))]
210 lds %0,%1\;cvtlq %0,%0"
211 [(set_attr "type" "iadd,ild,fld")
212 (set_attr "length" "*,*,8")])
215 [(set (match_operand:DI 0 "hard_fp_register_operand" "")
216 (sign_extend:DI (match_operand:SI 1 "memory_operand" "")))]
218 [(set (match_dup 2) (match_dup 1))
219 (set (match_dup 0) (unspec:DI [(match_dup 2)] UNSPEC_CVTLQ))]
221 operands[1] = adjust_address (operands[1], SFmode, 0);
222 operands[2] = gen_rtx_REG (SFmode, REGNO (operands[0]));
225 ;; Optimize sign-extension of SImode loads. This shows up in the wake of
226 ;; reload when converting fp->int.
229 [(set (match_operand:SI 0 "hard_int_register_operand" "")
230 (match_operand:SI 1 "memory_operand" ""))
231 (set (match_operand:DI 2 "hard_int_register_operand" "")
232 (sign_extend:DI (match_dup 0)))]
233 "true_regnum (operands[0]) == true_regnum (operands[2])
234 || peep2_reg_dead_p (2, operands[0])"
236 (sign_extend:DI (match_dup 1)))]
239 ;; Don't say we have addsi3 if optimizing. This generates better code. We
240 ;; have the anonymous addsi3 pattern below in case combine wants to make it.
241 (define_expand "addsi3"
242 [(set (match_operand:SI 0 "register_operand" "")
243 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "")
244 (match_operand:SI 2 "add_operand" "")))]
248 (define_insn "*addsi_internal"
249 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
250 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ")
251 (match_operand:SI 2 "add_operand" "rI,O,K,L")))]
260 [(set (match_operand:SI 0 "register_operand" "")
261 (plus:SI (match_operand:SI 1 "register_operand" "")
262 (match_operand:SI 2 "const_int_operand" "")))]
263 "! add_operand (operands[2], SImode)"
264 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
265 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
267 HOST_WIDE_INT val = INTVAL (operands[2]);
268 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
269 HOST_WIDE_INT rest = val - low;
271 operands[3] = GEN_INT (rest);
272 operands[4] = GEN_INT (low);
275 (define_insn "*addsi_se"
276 [(set (match_operand:DI 0 "register_operand" "=r,r")
278 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
279 (match_operand:SI 2 "sext_add_operand" "rI,O"))))]
285 (define_insn "*addsi_se2"
286 [(set (match_operand:DI 0 "register_operand" "=r,r")
288 (subreg:SI (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
289 (match_operand:DI 2 "sext_add_operand" "rI,O"))
297 [(set (match_operand:DI 0 "register_operand" "")
299 (plus:SI (match_operand:SI 1 "reg_not_elim_operand" "")
300 (match_operand:SI 2 "const_int_operand" ""))))
301 (clobber (match_operand:SI 3 "reg_not_elim_operand" ""))]
302 "! sext_add_operand (operands[2], SImode) && INTVAL (operands[2]) > 0
303 && INTVAL (operands[2]) % 4 == 0"
304 [(set (match_dup 3) (match_dup 4))
305 (set (match_dup 0) (sign_extend:DI (plus:SI (mult:SI (match_dup 3)
309 HOST_WIDE_INT val = INTVAL (operands[2]) / 4;
315 operands[4] = GEN_INT (val);
316 operands[5] = GEN_INT (mult);
320 [(set (match_operand:DI 0 "register_operand" "")
322 (plus:SI (match_operator:SI 1 "comparison_operator"
323 [(match_operand 2 "" "")
324 (match_operand 3 "" "")])
325 (match_operand:SI 4 "add_operand" ""))))
326 (clobber (match_operand:DI 5 "register_operand" ""))]
328 [(set (match_dup 5) (match_dup 6))
329 (set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 7) (match_dup 4))))]
331 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
332 operands[2], operands[3]);
333 operands[7] = gen_lowpart (SImode, operands[5]);
336 (define_insn "addvsi3"
337 [(set (match_operand:SI 0 "register_operand" "=r,r")
338 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
339 (match_operand:SI 2 "sext_add_operand" "rI,O")))
340 (trap_if (ne (plus:DI (sign_extend:DI (match_dup 1))
341 (sign_extend:DI (match_dup 2)))
342 (sign_extend:DI (plus:SI (match_dup 1)
350 (define_expand "adddi3"
351 [(set (match_operand:DI 0 "register_operand" "")
352 (plus:DI (match_operand:DI 1 "register_operand" "")
353 (match_operand:DI 2 "add_operand" "")))]
357 (define_insn "*adddi_er_lo16_dtp"
358 [(set (match_operand:DI 0 "register_operand" "=r")
359 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
360 (match_operand:DI 2 "dtp16_symbolic_operand" "")))]
362 "lda %0,%2(%1)\t\t!dtprel")
364 (define_insn "*adddi_er_hi32_dtp"
365 [(set (match_operand:DI 0 "register_operand" "=r")
366 (plus:DI (match_operand:DI 1 "register_operand" "r")
367 (high:DI (match_operand:DI 2 "dtp32_symbolic_operand" ""))))]
369 "ldah %0,%2(%1)\t\t!dtprelhi")
371 (define_insn "*adddi_er_lo32_dtp"
372 [(set (match_operand:DI 0 "register_operand" "=r")
373 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
374 (match_operand:DI 2 "dtp32_symbolic_operand" "")))]
376 "lda %0,%2(%1)\t\t!dtprello")
378 (define_insn "*adddi_er_lo16_tp"
379 [(set (match_operand:DI 0 "register_operand" "=r")
380 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
381 (match_operand:DI 2 "tp16_symbolic_operand" "")))]
383 "lda %0,%2(%1)\t\t!tprel")
385 (define_insn "*adddi_er_hi32_tp"
386 [(set (match_operand:DI 0 "register_operand" "=r")
387 (plus:DI (match_operand:DI 1 "register_operand" "r")
388 (high:DI (match_operand:DI 2 "tp32_symbolic_operand" ""))))]
390 "ldah %0,%2(%1)\t\t!tprelhi")
392 (define_insn "*adddi_er_lo32_tp"
393 [(set (match_operand:DI 0 "register_operand" "=r")
394 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
395 (match_operand:DI 2 "tp32_symbolic_operand" "")))]
397 "lda %0,%2(%1)\t\t!tprello")
399 (define_insn "*adddi_er_high_l"
400 [(set (match_operand:DI 0 "register_operand" "=r")
401 (plus:DI (match_operand:DI 1 "register_operand" "r")
402 (high:DI (match_operand:DI 2 "local_symbolic_operand" ""))))]
403 "TARGET_EXPLICIT_RELOCS && reload_completed"
404 "ldah %0,%2(%1)\t\t!gprelhigh"
405 [(set_attr "usegp" "yes")])
408 [(set (match_operand:DI 0 "register_operand" "")
409 (high:DI (match_operand:DI 1 "local_symbolic_operand" "")))]
410 "TARGET_EXPLICIT_RELOCS && reload_completed"
412 (plus:DI (match_dup 2) (high:DI (match_dup 1))))]
413 "operands[2] = pic_offset_table_rtx;")
415 ;; We used to expend quite a lot of effort choosing addq/subq/lda.
416 ;; With complications like
418 ;; The NT stack unwind code can't handle a subq to adjust the stack
419 ;; (that's a bug, but not one we can do anything about). As of NT4.0 SP3,
420 ;; the exception handling code will loop if a subq is used and an
423 ;; The 19980616 change to emit prologues as RTL also confused some
424 ;; versions of GDB, which also interprets prologues. This has been
425 ;; fixed as of GDB 4.18, but it does not harm to unconditionally
428 ;; and the fact that the three insns schedule exactly the same, it's
429 ;; just not worth the effort.
431 (define_insn "*adddi_internal"
432 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
433 (plus:DI (match_operand:DI 1 "register_operand" "%r,r,r")
434 (match_operand:DI 2 "add_operand" "r,K,L")))]
441 ;; ??? Allow large constants when basing off the frame pointer or some
442 ;; virtual register that may eliminate to the frame pointer. This is
443 ;; done because register elimination offsets will change the hi/lo split,
444 ;; and if we split before reload, we will require additional instructions.
446 (define_insn "*adddi_fp_hack"
447 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
448 (plus:DI (match_operand:DI 1 "reg_no_subreg_operand" "r,r,r")
449 (match_operand:DI 2 "const_int_operand" "K,L,n")))]
450 "NONSTRICT_REG_OK_FP_BASE_P (operands[1])
451 && INTVAL (operands[2]) >= 0
452 /* This is the largest constant an lda+ldah pair can add, minus
453 an upper bound on the displacement between SP and AP during
454 register elimination. See INITIAL_ELIMINATION_OFFSET. */
455 && INTVAL (operands[2])
457 - FIRST_PSEUDO_REGISTER * UNITS_PER_WORD
458 - ALPHA_ROUND(current_function_outgoing_args_size)
459 - (ALPHA_ROUND (get_frame_size ()
460 + max_reg_num () * UNITS_PER_WORD
461 + current_function_pretend_args_size)
462 - current_function_pretend_args_size))"
468 ;; Don't do this if we are adjusting SP since we don't want to do it
469 ;; in two steps. Don't split FP sources for the reason listed above.
471 [(set (match_operand:DI 0 "register_operand" "")
472 (plus:DI (match_operand:DI 1 "register_operand" "")
473 (match_operand:DI 2 "const_int_operand" "")))]
474 "! add_operand (operands[2], DImode)
475 && operands[0] != stack_pointer_rtx
476 && operands[1] != frame_pointer_rtx
477 && operands[1] != arg_pointer_rtx"
478 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
479 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
481 HOST_WIDE_INT val = INTVAL (operands[2]);
482 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
483 HOST_WIDE_INT rest = val - low;
485 operands[4] = GEN_INT (low);
486 if (CONST_OK_FOR_LETTER_P (rest, 'L'))
487 operands[3] = GEN_INT (rest);
488 else if (! no_new_pseudos)
490 operands[3] = gen_reg_rtx (DImode);
491 emit_move_insn (operands[3], operands[2]);
492 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
499 (define_insn "*saddl"
500 [(set (match_operand:SI 0 "register_operand" "=r,r")
501 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
502 (match_operand:SI 2 "const48_operand" "I,I"))
503 (match_operand:SI 3 "sext_add_operand" "rI,O")))]
509 (define_insn "*saddl_se"
510 [(set (match_operand:DI 0 "register_operand" "=r,r")
512 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
513 (match_operand:SI 2 "const48_operand" "I,I"))
514 (match_operand:SI 3 "sext_add_operand" "rI,O"))))]
521 [(set (match_operand:DI 0 "register_operand" "")
523 (plus:SI (mult:SI (match_operator:SI 1 "comparison_operator"
524 [(match_operand 2 "" "")
525 (match_operand 3 "" "")])
526 (match_operand:SI 4 "const48_operand" ""))
527 (match_operand:SI 5 "sext_add_operand" ""))))
528 (clobber (match_operand:DI 6 "reg_not_elim_operand" ""))]
530 [(set (match_dup 6) (match_dup 7))
532 (sign_extend:DI (plus:SI (mult:SI (match_dup 8) (match_dup 4))
535 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
536 operands[2], operands[3]);
537 operands[8] = gen_lowpart (SImode, operands[6]);
540 (define_insn "*saddq"
541 [(set (match_operand:DI 0 "register_operand" "=r,r")
542 (plus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r,r")
543 (match_operand:DI 2 "const48_operand" "I,I"))
544 (match_operand:DI 3 "sext_add_operand" "rI,O")))]
550 (define_insn "addvdi3"
551 [(set (match_operand:DI 0 "register_operand" "=r,r")
552 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
553 (match_operand:DI 2 "sext_add_operand" "rI,O")))
554 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
555 (sign_extend:TI (match_dup 2)))
556 (sign_extend:TI (plus:DI (match_dup 1)
564 (define_insn "negsi2"
565 [(set (match_operand:SI 0 "register_operand" "=r")
566 (neg:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))]
570 (define_insn "*negsi_se"
571 [(set (match_operand:DI 0 "register_operand" "=r")
572 (sign_extend:DI (neg:SI
573 (match_operand:SI 1 "reg_or_8bit_operand" "rI"))))]
577 (define_insn "negvsi2"
578 [(set (match_operand:SI 0 "register_operand" "=r")
579 (neg:SI (match_operand:SI 1 "register_operand" "r")))
580 (trap_if (ne (neg:DI (sign_extend:DI (match_dup 1)))
581 (sign_extend:DI (neg:SI (match_dup 1))))
586 (define_insn "negdi2"
587 [(set (match_operand:DI 0 "register_operand" "=r")
588 (neg:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
592 (define_insn "negvdi2"
593 [(set (match_operand:DI 0 "register_operand" "=r")
594 (neg:DI (match_operand:DI 1 "register_operand" "r")))
595 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
596 (sign_extend:TI (neg:DI (match_dup 1))))
601 (define_expand "subsi3"
602 [(set (match_operand:SI 0 "register_operand" "")
603 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "")
604 (match_operand:SI 2 "reg_or_8bit_operand" "")))]
608 (define_insn "*subsi_internal"
609 [(set (match_operand:SI 0 "register_operand" "=r")
610 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
611 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
615 (define_insn "*subsi_se"
616 [(set (match_operand:DI 0 "register_operand" "=r")
617 (sign_extend:DI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
618 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
622 (define_insn "*subsi_se2"
623 [(set (match_operand:DI 0 "register_operand" "=r")
625 (subreg:SI (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
626 (match_operand:DI 2 "reg_or_8bit_operand" "rI"))
631 (define_insn "subvsi3"
632 [(set (match_operand:SI 0 "register_operand" "=r")
633 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
634 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))
635 (trap_if (ne (minus:DI (sign_extend:DI (match_dup 1))
636 (sign_extend:DI (match_dup 2)))
637 (sign_extend:DI (minus:SI (match_dup 1)
643 (define_insn "subdi3"
644 [(set (match_operand:DI 0 "register_operand" "=r")
645 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
646 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
650 (define_insn "*ssubl"
651 [(set (match_operand:SI 0 "register_operand" "=r")
652 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
653 (match_operand:SI 2 "const48_operand" "I"))
654 (match_operand:SI 3 "reg_or_8bit_operand" "rI")))]
658 (define_insn "*ssubl_se"
659 [(set (match_operand:DI 0 "register_operand" "=r")
661 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
662 (match_operand:SI 2 "const48_operand" "I"))
663 (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))]
667 (define_insn "*ssubq"
668 [(set (match_operand:DI 0 "register_operand" "=r")
669 (minus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r")
670 (match_operand:DI 2 "const48_operand" "I"))
671 (match_operand:DI 3 "reg_or_8bit_operand" "rI")))]
675 (define_insn "subvdi3"
676 [(set (match_operand:DI 0 "register_operand" "=r")
677 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
678 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
679 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
680 (sign_extend:TI (match_dup 2)))
681 (sign_extend:TI (minus:DI (match_dup 1)
687 ;; The Unicos/Mk assembler doesn't support mull.
689 (define_insn "mulsi3"
690 [(set (match_operand:SI 0 "register_operand" "=r")
691 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
692 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
693 "!TARGET_ABI_UNICOSMK"
695 [(set_attr "type" "imul")
696 (set_attr "opsize" "si")])
698 (define_insn "*mulsi_se"
699 [(set (match_operand:DI 0 "register_operand" "=r")
701 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
702 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
703 "!TARGET_ABI_UNICOSMK"
705 [(set_attr "type" "imul")
706 (set_attr "opsize" "si")])
708 (define_insn "mulvsi3"
709 [(set (match_operand:SI 0 "register_operand" "=r")
710 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
711 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))
712 (trap_if (ne (mult:DI (sign_extend:DI (match_dup 1))
713 (sign_extend:DI (match_dup 2)))
714 (sign_extend:DI (mult:SI (match_dup 1)
717 "!TARGET_ABI_UNICOSMK"
719 [(set_attr "type" "imul")
720 (set_attr "opsize" "si")])
722 (define_insn "muldi3"
723 [(set (match_operand:DI 0 "register_operand" "=r")
724 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
725 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
728 [(set_attr "type" "imul")])
730 (define_insn "mulvdi3"
731 [(set (match_operand:DI 0 "register_operand" "=r")
732 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
733 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
734 (trap_if (ne (mult:TI (sign_extend:TI (match_dup 1))
735 (sign_extend:TI (match_dup 2)))
736 (sign_extend:TI (mult:DI (match_dup 1)
741 [(set_attr "type" "imul")])
743 (define_expand "umuldi3_highpart"
744 [(set (match_operand:DI 0 "register_operand" "")
747 (mult:TI (zero_extend:TI
748 (match_operand:DI 1 "register_operand" ""))
749 (match_operand:DI 2 "reg_or_8bit_operand" ""))
753 if (REG_P (operands[2]))
754 operands[2] = gen_rtx_ZERO_EXTEND (TImode, operands[2]);
757 (define_insn "*umuldi3_highpart_reg"
758 [(set (match_operand:DI 0 "register_operand" "=r")
761 (mult:TI (zero_extend:TI
762 (match_operand:DI 1 "register_operand" "r"))
764 (match_operand:DI 2 "register_operand" "r")))
768 [(set_attr "type" "imul")
769 (set_attr "opsize" "udi")])
771 (define_insn "*umuldi3_highpart_const"
772 [(set (match_operand:DI 0 "register_operand" "=r")
775 (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "r"))
776 (match_operand:TI 2 "cint8_operand" "I"))
780 [(set_attr "type" "imul")
781 (set_attr "opsize" "udi")])
783 ;; The divide and remainder operations take their inputs from r24 and
784 ;; r25, put their output in r27, and clobber r23 and r28 on all
785 ;; systems except Unicos/Mk. On Unicos, the standard library provides
786 ;; subroutines which use the standard calling convention and work on
789 ;; ??? Force sign-extension here because some versions of OSF/1 and
790 ;; Interix/NT don't do the right thing if the inputs are not properly
791 ;; sign-extended. But Linux, for instance, does not have this
792 ;; problem. Is it worth the complication here to eliminate the sign
795 (define_expand "divsi3"
797 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
799 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
800 (parallel [(set (match_dup 5)
801 (sign_extend:DI (div:SI (match_dup 3) (match_dup 4))))
802 (clobber (reg:DI 23))
803 (clobber (reg:DI 28))])
804 (set (match_operand:SI 0 "nonimmediate_operand" "")
805 (subreg:SI (match_dup 5) 0))]
806 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
808 operands[3] = gen_reg_rtx (DImode);
809 operands[4] = gen_reg_rtx (DImode);
810 operands[5] = gen_reg_rtx (DImode);
813 (define_expand "udivsi3"
815 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
817 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
818 (parallel [(set (match_dup 5)
819 (sign_extend:DI (udiv:SI (match_dup 3) (match_dup 4))))
820 (clobber (reg:DI 23))
821 (clobber (reg:DI 28))])
822 (set (match_operand:SI 0 "nonimmediate_operand" "")
823 (subreg:SI (match_dup 5) 0))]
824 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
826 operands[3] = gen_reg_rtx (DImode);
827 operands[4] = gen_reg_rtx (DImode);
828 operands[5] = gen_reg_rtx (DImode);
831 (define_expand "modsi3"
833 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
835 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
836 (parallel [(set (match_dup 5)
837 (sign_extend:DI (mod:SI (match_dup 3) (match_dup 4))))
838 (clobber (reg:DI 23))
839 (clobber (reg:DI 28))])
840 (set (match_operand:SI 0 "nonimmediate_operand" "")
841 (subreg:SI (match_dup 5) 0))]
842 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
844 operands[3] = gen_reg_rtx (DImode);
845 operands[4] = gen_reg_rtx (DImode);
846 operands[5] = gen_reg_rtx (DImode);
849 (define_expand "umodsi3"
851 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
853 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
854 (parallel [(set (match_dup 5)
855 (sign_extend:DI (umod:SI (match_dup 3) (match_dup 4))))
856 (clobber (reg:DI 23))
857 (clobber (reg:DI 28))])
858 (set (match_operand:SI 0 "nonimmediate_operand" "")
859 (subreg:SI (match_dup 5) 0))]
860 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
862 operands[3] = gen_reg_rtx (DImode);
863 operands[4] = gen_reg_rtx (DImode);
864 operands[5] = gen_reg_rtx (DImode);
867 (define_expand "divdi3"
868 [(parallel [(set (match_operand:DI 0 "register_operand" "")
869 (div:DI (match_operand:DI 1 "register_operand" "")
870 (match_operand:DI 2 "register_operand" "")))
871 (clobber (reg:DI 23))
872 (clobber (reg:DI 28))])]
873 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
876 (define_expand "udivdi3"
877 [(parallel [(set (match_operand:DI 0 "register_operand" "")
878 (udiv:DI (match_operand:DI 1 "register_operand" "")
879 (match_operand:DI 2 "register_operand" "")))
880 (clobber (reg:DI 23))
881 (clobber (reg:DI 28))])]
882 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
885 (define_expand "moddi3"
886 [(use (match_operand:DI 0 "register_operand" ""))
887 (use (match_operand:DI 1 "register_operand" ""))
888 (use (match_operand:DI 2 "register_operand" ""))]
889 "!TARGET_ABI_OPEN_VMS"
891 if (TARGET_ABI_UNICOSMK)
892 emit_insn (gen_moddi3_umk (operands[0], operands[1], operands[2]));
894 emit_insn (gen_moddi3_dft (operands[0], operands[1], operands[2]));
898 (define_expand "moddi3_dft"
899 [(parallel [(set (match_operand:DI 0 "register_operand" "")
900 (mod:DI (match_operand:DI 1 "register_operand" "")
901 (match_operand:DI 2 "register_operand" "")))
902 (clobber (reg:DI 23))
903 (clobber (reg:DI 28))])]
904 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
907 ;; On Unicos/Mk, we do as the system's C compiler does:
908 ;; compute the quotient, multiply and subtract.
910 (define_expand "moddi3_umk"
911 [(use (match_operand:DI 0 "register_operand" ""))
912 (use (match_operand:DI 1 "register_operand" ""))
913 (use (match_operand:DI 2 "register_operand" ""))]
914 "TARGET_ABI_UNICOSMK"
916 rtx div, mul = gen_reg_rtx (DImode);
918 div = expand_binop (DImode, sdiv_optab, operands[1], operands[2],
919 NULL_RTX, 0, OPTAB_LIB);
920 div = force_reg (DImode, div);
921 emit_insn (gen_muldi3 (mul, operands[2], div));
922 emit_insn (gen_subdi3 (operands[0], operands[1], mul));
926 (define_expand "umoddi3"
927 [(use (match_operand:DI 0 "register_operand" ""))
928 (use (match_operand:DI 1 "register_operand" ""))
929 (use (match_operand:DI 2 "register_operand" ""))]
930 "! TARGET_ABI_OPEN_VMS"
932 if (TARGET_ABI_UNICOSMK)
933 emit_insn (gen_umoddi3_umk (operands[0], operands[1], operands[2]));
935 emit_insn (gen_umoddi3_dft (operands[0], operands[1], operands[2]));
939 (define_expand "umoddi3_dft"
940 [(parallel [(set (match_operand:DI 0 "register_operand" "")
941 (umod:DI (match_operand:DI 1 "register_operand" "")
942 (match_operand:DI 2 "register_operand" "")))
943 (clobber (reg:DI 23))
944 (clobber (reg:DI 28))])]
945 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
948 (define_expand "umoddi3_umk"
949 [(use (match_operand:DI 0 "register_operand" ""))
950 (use (match_operand:DI 1 "register_operand" ""))
951 (use (match_operand:DI 2 "register_operand" ""))]
952 "TARGET_ABI_UNICOSMK"
954 rtx div, mul = gen_reg_rtx (DImode);
956 div = expand_binop (DImode, udiv_optab, operands[1], operands[2],
957 NULL_RTX, 1, OPTAB_LIB);
958 div = force_reg (DImode, div);
959 emit_insn (gen_muldi3 (mul, operands[2], div));
960 emit_insn (gen_subdi3 (operands[0], operands[1], mul));
964 ;; Lengths of 8 for ldq $t12,__divq($gp); jsr $t9,($t12),__divq as
965 ;; expanded by the assembler.
967 (define_insn_and_split "*divmodsi_internal_er"
968 [(set (match_operand:DI 0 "register_operand" "=c")
969 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
970 [(match_operand:DI 1 "register_operand" "a")
971 (match_operand:DI 2 "register_operand" "b")])))
972 (clobber (reg:DI 23))
973 (clobber (reg:DI 28))]
974 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
975 "ldq $27,__%E3($29)\t\t!literal!%#\;jsr $23,($27),__%E3\t\t!lituse_jsr!%#"
976 "&& reload_completed"
977 [(parallel [(set (match_dup 0)
978 (sign_extend:DI (match_dup 3)))
981 (clobber (reg:DI 23))
982 (clobber (reg:DI 28))])]
985 switch (GET_CODE (operands[3]))
1002 operands[4] = GEN_INT (alpha_next_sequence_number++);
1003 emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx,
1004 gen_rtx_SYMBOL_REF (DImode, str),
1007 [(set_attr "type" "jsr")
1008 (set_attr "length" "8")])
1010 (define_insn "*divmodsi_internal_er_1"
1011 [(set (match_operand:DI 0 "register_operand" "=c")
1012 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
1013 [(match_operand:DI 1 "register_operand" "a")
1014 (match_operand:DI 2 "register_operand" "b")])))
1015 (use (match_operand:DI 4 "register_operand" "c"))
1016 (use (match_operand 5 "const_int_operand" ""))
1017 (clobber (reg:DI 23))
1018 (clobber (reg:DI 28))]
1019 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1020 "jsr $23,($27),__%E3%J5"
1021 [(set_attr "type" "jsr")
1022 (set_attr "length" "4")])
1024 (define_insn "*divmodsi_internal"
1025 [(set (match_operand:DI 0 "register_operand" "=c")
1026 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
1027 [(match_operand:DI 1 "register_operand" "a")
1028 (match_operand:DI 2 "register_operand" "b")])))
1029 (clobber (reg:DI 23))
1030 (clobber (reg:DI 28))]
1031 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1033 [(set_attr "type" "jsr")
1034 (set_attr "length" "8")])
1036 (define_insn_and_split "*divmoddi_internal_er"
1037 [(set (match_operand:DI 0 "register_operand" "=c")
1038 (match_operator:DI 3 "divmod_operator"
1039 [(match_operand:DI 1 "register_operand" "a")
1040 (match_operand:DI 2 "register_operand" "b")]))
1041 (clobber (reg:DI 23))
1042 (clobber (reg:DI 28))]
1043 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1044 "ldq $27,__%E3($29)\t\t!literal!%#\;jsr $23,($27),__%E3\t\t!lituse_jsr!%#"
1045 "&& reload_completed"
1046 [(parallel [(set (match_dup 0) (match_dup 3))
1049 (clobber (reg:DI 23))
1050 (clobber (reg:DI 28))])]
1053 switch (GET_CODE (operands[3]))
1070 operands[4] = GEN_INT (alpha_next_sequence_number++);
1071 emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx,
1072 gen_rtx_SYMBOL_REF (DImode, str),
1075 [(set_attr "type" "jsr")
1076 (set_attr "length" "8")])
1078 (define_insn "*divmoddi_internal_er_1"
1079 [(set (match_operand:DI 0 "register_operand" "=c")
1080 (match_operator:DI 3 "divmod_operator"
1081 [(match_operand:DI 1 "register_operand" "a")
1082 (match_operand:DI 2 "register_operand" "b")]))
1083 (use (match_operand:DI 4 "register_operand" "c"))
1084 (use (match_operand 5 "const_int_operand" ""))
1085 (clobber (reg:DI 23))
1086 (clobber (reg:DI 28))]
1087 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1088 "jsr $23,($27),__%E3%J5"
1089 [(set_attr "type" "jsr")
1090 (set_attr "length" "4")])
1092 (define_insn "*divmoddi_internal"
1093 [(set (match_operand:DI 0 "register_operand" "=c")
1094 (match_operator:DI 3 "divmod_operator"
1095 [(match_operand:DI 1 "register_operand" "a")
1096 (match_operand:DI 2 "register_operand" "b")]))
1097 (clobber (reg:DI 23))
1098 (clobber (reg:DI 28))]
1099 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1101 [(set_attr "type" "jsr")
1102 (set_attr "length" "8")])
1104 ;; Next are the basic logical operations. These only exist in DImode.
1106 (define_insn "anddi3"
1107 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1108 (and:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ")
1109 (match_operand:DI 2 "and_operand" "rI,N,MH")))]
1115 [(set_attr "type" "ilog,ilog,shift")])
1117 ;; There are times when we can split an AND into two AND insns. This occurs
1118 ;; when we can first clear any bytes and then clear anything else. For
1119 ;; example "I & 0xffff07" is "(I & 0xffffff) & 0xffffffffffffff07".
1120 ;; Only do this when running on 64-bit host since the computations are
1121 ;; too messy otherwise.
1124 [(set (match_operand:DI 0 "register_operand" "")
1125 (and:DI (match_operand:DI 1 "register_operand" "")
1126 (match_operand:DI 2 "const_int_operand" "")))]
1127 "HOST_BITS_PER_WIDE_INT == 64 && ! and_operand (operands[2], DImode)"
1128 [(set (match_dup 0) (and:DI (match_dup 1) (match_dup 3)))
1129 (set (match_dup 0) (and:DI (match_dup 0) (match_dup 4)))]
1131 unsigned HOST_WIDE_INT mask1 = INTVAL (operands[2]);
1132 unsigned HOST_WIDE_INT mask2 = mask1;
1135 /* For each byte that isn't all zeros, make it all ones. */
1136 for (i = 0; i < 64; i += 8)
1137 if ((mask1 & ((HOST_WIDE_INT) 0xff << i)) != 0)
1138 mask1 |= (HOST_WIDE_INT) 0xff << i;
1140 /* Now turn on any bits we've just turned off. */
1143 operands[3] = GEN_INT (mask1);
1144 operands[4] = GEN_INT (mask2);
1147 (define_expand "zero_extendqihi2"
1148 [(set (match_operand:HI 0 "register_operand" "")
1149 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
1153 operands[1] = force_reg (QImode, operands[1]);
1156 (define_insn "*zero_extendqihi2_bwx"
1157 [(set (match_operand:HI 0 "register_operand" "=r,r")
1158 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1163 [(set_attr "type" "ilog,ild")])
1165 (define_insn "*zero_extendqihi2_nobwx"
1166 [(set (match_operand:HI 0 "register_operand" "=r")
1167 (zero_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1170 [(set_attr "type" "ilog")])
1172 (define_expand "zero_extendqisi2"
1173 [(set (match_operand:SI 0 "register_operand" "")
1174 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
1178 operands[1] = force_reg (QImode, operands[1]);
1181 (define_insn "*zero_extendqisi2_bwx"
1182 [(set (match_operand:SI 0 "register_operand" "=r,r")
1183 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1188 [(set_attr "type" "ilog,ild")])
1190 (define_insn "*zero_extendqisi2_nobwx"
1191 [(set (match_operand:SI 0 "register_operand" "=r")
1192 (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1195 [(set_attr "type" "ilog")])
1197 (define_expand "zero_extendqidi2"
1198 [(set (match_operand:DI 0 "register_operand" "")
1199 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "")))]
1203 operands[1] = force_reg (QImode, operands[1]);
1206 (define_insn "*zero_extendqidi2_bwx"
1207 [(set (match_operand:DI 0 "register_operand" "=r,r")
1208 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1213 [(set_attr "type" "ilog,ild")])
1215 (define_insn "*zero_extendqidi2_nobwx"
1216 [(set (match_operand:DI 0 "register_operand" "=r")
1217 (zero_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1220 [(set_attr "type" "ilog")])
1222 (define_expand "zero_extendhisi2"
1223 [(set (match_operand:SI 0 "register_operand" "")
1224 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
1228 operands[1] = force_reg (HImode, operands[1]);
1231 (define_insn "*zero_extendhisi2_bwx"
1232 [(set (match_operand:SI 0 "register_operand" "=r,r")
1233 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1238 [(set_attr "type" "shift,ild")])
1240 (define_insn "*zero_extendhisi2_nobwx"
1241 [(set (match_operand:SI 0 "register_operand" "=r")
1242 (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1245 [(set_attr "type" "shift")])
1247 (define_expand "zero_extendhidi2"
1248 [(set (match_operand:DI 0 "register_operand" "")
1249 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "")))]
1253 operands[1] = force_reg (HImode, operands[1]);
1256 (define_insn "*zero_extendhidi2_bwx"
1257 [(set (match_operand:DI 0 "register_operand" "=r,r")
1258 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1263 [(set_attr "type" "shift,ild")])
1265 (define_insn "*zero_extendhidi2_nobwx"
1266 [(set (match_operand:DI 0 "register_operand" "=r")
1267 (zero_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1270 [(set_attr "type" "shift")])
1272 (define_insn "zero_extendsidi2"
1273 [(set (match_operand:DI 0 "register_operand" "=r")
1274 (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
1277 [(set_attr "type" "shift")])
1279 (define_insn "andnotdi3"
1280 [(set (match_operand:DI 0 "register_operand" "=r")
1281 (and:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1282 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1285 [(set_attr "type" "ilog")])
1287 (define_insn "iordi3"
1288 [(set (match_operand:DI 0 "register_operand" "=r,r")
1289 (ior:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1290 (match_operand:DI 2 "or_operand" "rI,N")))]
1295 [(set_attr "type" "ilog")])
1297 (define_insn "one_cmpldi2"
1298 [(set (match_operand:DI 0 "register_operand" "=r")
1299 (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
1302 [(set_attr "type" "ilog")])
1304 (define_insn "*iornot"
1305 [(set (match_operand:DI 0 "register_operand" "=r")
1306 (ior:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1307 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1310 [(set_attr "type" "ilog")])
1312 (define_insn "xordi3"
1313 [(set (match_operand:DI 0 "register_operand" "=r,r")
1314 (xor:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1315 (match_operand:DI 2 "or_operand" "rI,N")))]
1320 [(set_attr "type" "ilog")])
1322 (define_insn "*xornot"
1323 [(set (match_operand:DI 0 "register_operand" "=r")
1324 (not:DI (xor:DI (match_operand:DI 1 "register_operand" "%rJ")
1325 (match_operand:DI 2 "register_operand" "rI"))))]
1328 [(set_attr "type" "ilog")])
1330 ;; Handle FFS and related insns iff we support CIX.
1332 (define_expand "ffsdi2"
1334 (unspec:DI [(match_operand:DI 1 "register_operand" "")] UNSPEC_CTTZ))
1336 (plus:DI (match_dup 2) (const_int 1)))
1337 (set (match_operand:DI 0 "register_operand" "")
1338 (if_then_else:DI (eq (match_dup 1) (const_int 0))
1339 (const_int 0) (match_dup 3)))]
1342 operands[2] = gen_reg_rtx (DImode);
1343 operands[3] = gen_reg_rtx (DImode);
1346 (define_insn "*cttz"
1347 [(set (match_operand:DI 0 "register_operand" "=r")
1348 (unspec:DI [(match_operand:DI 1 "register_operand" "r")] UNSPEC_CTTZ))]
1351 ; EV6 calls all mvi and cttz/ctlz/popc class imisc, so just
1352 ; reuse the existing type name.
1353 [(set_attr "type" "mvi")])
1355 (define_insn "clzdi2"
1356 [(set (match_operand:DI 0 "register_operand" "=r")
1357 (clz:DI (match_operand:DI 1 "register_operand" "r")))]
1360 [(set_attr "type" "mvi")])
1362 (define_insn "ctzdi2"
1363 [(set (match_operand:DI 0 "register_operand" "=r")
1364 (ctz:DI (match_operand:DI 1 "register_operand" "r")))]
1367 [(set_attr "type" "mvi")])
1369 (define_insn "popcountdi2"
1370 [(set (match_operand:DI 0 "register_operand" "=r")
1371 (popcount:DI (match_operand:DI 1 "register_operand" "r")))]
1374 [(set_attr "type" "mvi")])
1376 ;; Next come the shifts and the various extract and insert operations.
1378 (define_insn "ashldi3"
1379 [(set (match_operand:DI 0 "register_operand" "=r,r")
1380 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,rJ")
1381 (match_operand:DI 2 "reg_or_6bit_operand" "P,rS")))]
1384 switch (which_alternative)
1387 if (operands[2] == const1_rtx)
1388 return "addq %r1,%r1,%0";
1390 return "s%P2addq %r1,0,%0";
1392 return "sll %r1,%2,%0";
1397 [(set_attr "type" "iadd,shift")])
1399 (define_insn "*ashldi_se"
1400 [(set (match_operand:DI 0 "register_operand" "=r")
1402 (subreg:SI (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1403 (match_operand:DI 2 "const_int_operand" "P"))
1405 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3"
1407 if (operands[2] == const1_rtx)
1408 return "addl %r1,%r1,%0";
1410 return "s%P2addl %r1,0,%0";
1412 [(set_attr "type" "iadd")])
1414 (define_insn "lshrdi3"
1415 [(set (match_operand:DI 0 "register_operand" "=r")
1416 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1417 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1420 [(set_attr "type" "shift")])
1422 (define_insn "ashrdi3"
1423 [(set (match_operand:DI 0 "register_operand" "=r")
1424 (ashiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1425 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1428 [(set_attr "type" "shift")])
1430 (define_expand "extendqihi2"
1432 (ashift:DI (match_operand:QI 1 "some_operand" "")
1434 (set (match_operand:HI 0 "register_operand" "")
1435 (ashiftrt:DI (match_dup 2)
1441 emit_insn (gen_extendqihi2x (operands[0],
1442 force_reg (QImode, operands[1])));
1446 /* If we have an unaligned MEM, extend to DImode (which we do
1447 specially) and then copy to the result. */
1448 if (unaligned_memory_operand (operands[1], HImode))
1450 rtx temp = gen_reg_rtx (DImode);
1452 emit_insn (gen_extendqidi2 (temp, operands[1]));
1453 emit_move_insn (operands[0], gen_lowpart (HImode, temp));
1457 operands[0] = gen_lowpart (DImode, operands[0]);
1458 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1459 operands[2] = gen_reg_rtx (DImode);
1462 (define_insn "extendqidi2x"
1463 [(set (match_operand:DI 0 "register_operand" "=r")
1464 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1467 [(set_attr "type" "shift")])
1469 (define_insn "extendhidi2x"
1470 [(set (match_operand:DI 0 "register_operand" "=r")
1471 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1474 [(set_attr "type" "shift")])
1476 (define_insn "extendqisi2x"
1477 [(set (match_operand:SI 0 "register_operand" "=r")
1478 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1481 [(set_attr "type" "shift")])
1483 (define_insn "extendhisi2x"
1484 [(set (match_operand:SI 0 "register_operand" "=r")
1485 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1488 [(set_attr "type" "shift")])
1490 (define_insn "extendqihi2x"
1491 [(set (match_operand:HI 0 "register_operand" "=r")
1492 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1495 [(set_attr "type" "shift")])
1497 (define_expand "extendqisi2"
1499 (ashift:DI (match_operand:QI 1 "some_operand" "")
1501 (set (match_operand:SI 0 "register_operand" "")
1502 (ashiftrt:DI (match_dup 2)
1508 emit_insn (gen_extendqisi2x (operands[0],
1509 force_reg (QImode, operands[1])));
1513 /* If we have an unaligned MEM, extend to a DImode form of
1514 the result (which we do specially). */
1515 if (unaligned_memory_operand (operands[1], QImode))
1517 rtx temp = gen_reg_rtx (DImode);
1519 emit_insn (gen_extendqidi2 (temp, operands[1]));
1520 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1524 operands[0] = gen_lowpart (DImode, operands[0]);
1525 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1526 operands[2] = gen_reg_rtx (DImode);
1529 (define_expand "extendqidi2"
1531 (ashift:DI (match_operand:QI 1 "some_operand" "")
1533 (set (match_operand:DI 0 "register_operand" "")
1534 (ashiftrt:DI (match_dup 2)
1540 emit_insn (gen_extendqidi2x (operands[0],
1541 force_reg (QImode, operands[1])));
1545 if (unaligned_memory_operand (operands[1], QImode))
1548 = gen_unaligned_extendqidi (operands[0],
1549 get_unaligned_address (operands[1], 1));
1551 alpha_set_memflags (seq, operands[1]);
1556 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1557 operands[2] = gen_reg_rtx (DImode);
1560 (define_expand "extendhisi2"
1562 (ashift:DI (match_operand:HI 1 "some_operand" "")
1564 (set (match_operand:SI 0 "register_operand" "")
1565 (ashiftrt:DI (match_dup 2)
1571 emit_insn (gen_extendhisi2x (operands[0],
1572 force_reg (HImode, operands[1])));
1576 /* If we have an unaligned MEM, extend to a DImode form of
1577 the result (which we do specially). */
1578 if (unaligned_memory_operand (operands[1], HImode))
1580 rtx temp = gen_reg_rtx (DImode);
1582 emit_insn (gen_extendhidi2 (temp, operands[1]));
1583 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1587 operands[0] = gen_lowpart (DImode, operands[0]);
1588 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1589 operands[2] = gen_reg_rtx (DImode);
1592 (define_expand "extendhidi2"
1594 (ashift:DI (match_operand:HI 1 "some_operand" "")
1596 (set (match_operand:DI 0 "register_operand" "")
1597 (ashiftrt:DI (match_dup 2)
1603 emit_insn (gen_extendhidi2x (operands[0],
1604 force_reg (HImode, operands[1])));
1608 if (unaligned_memory_operand (operands[1], HImode))
1611 = gen_unaligned_extendhidi (operands[0],
1612 get_unaligned_address (operands[1], 2));
1614 alpha_set_memflags (seq, operands[1]);
1619 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1620 operands[2] = gen_reg_rtx (DImode);
1623 ;; Here's how we sign extend an unaligned byte and halfword. Doing this
1624 ;; as a pattern saves one instruction. The code is similar to that for
1625 ;; the unaligned loads (see below).
1627 ;; Operand 1 is the address + 1 (+2 for HI), operand 0 is the result.
1628 (define_expand "unaligned_extendqidi"
1629 [(use (match_operand:QI 0 "register_operand" ""))
1630 (use (match_operand:DI 1 "address_operand" ""))]
1633 if (WORDS_BIG_ENDIAN)
1634 emit_insn (gen_unaligned_extendqidi_be (operands[0], operands[1]));
1636 emit_insn (gen_unaligned_extendqidi_le (operands[0], operands[1]));
1640 (define_expand "unaligned_extendqidi_le"
1641 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1643 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -1))
1646 (ashift:DI (match_dup 3)
1647 (minus:DI (const_int 64)
1649 (and:DI (match_dup 2) (const_int 7))
1651 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1652 (ashiftrt:DI (match_dup 4) (const_int 56)))]
1653 "! WORDS_BIG_ENDIAN"
1655 operands[2] = gen_reg_rtx (DImode);
1656 operands[3] = gen_reg_rtx (DImode);
1657 operands[4] = gen_reg_rtx (DImode);
1660 (define_expand "unaligned_extendqidi_be"
1661 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1662 (set (match_dup 3) (plus:DI (match_dup 2) (const_int -1)))
1664 (mem:DI (and:DI (match_dup 3)
1666 (set (match_dup 5) (plus:DI (match_dup 2) (const_int -2)))
1668 (ashift:DI (match_dup 4)
1671 (plus:DI (match_dup 5) (const_int 1))
1674 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1675 (ashiftrt:DI (match_dup 6) (const_int 56)))]
1678 operands[2] = gen_reg_rtx (DImode);
1679 operands[3] = gen_reg_rtx (DImode);
1680 operands[4] = gen_reg_rtx (DImode);
1681 operands[5] = gen_reg_rtx (DImode);
1682 operands[6] = gen_reg_rtx (DImode);
1685 (define_expand "unaligned_extendhidi"
1686 [(use (match_operand:QI 0 "register_operand" ""))
1687 (use (match_operand:DI 1 "address_operand" ""))]
1690 operands[0] = gen_lowpart (DImode, operands[0]);
1691 emit_insn ((WORDS_BIG_ENDIAN
1692 ? gen_unaligned_extendhidi_be
1693 : gen_unaligned_extendhidi_le) (operands[0], operands[1]));
1697 (define_expand "unaligned_extendhidi_le"
1698 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1700 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -2))
1703 (ashift:DI (match_dup 3)
1704 (minus:DI (const_int 64)
1706 (and:DI (match_dup 2) (const_int 7))
1708 (set (match_operand:DI 0 "register_operand" "")
1709 (ashiftrt:DI (match_dup 4) (const_int 48)))]
1710 "! WORDS_BIG_ENDIAN"
1712 operands[2] = gen_reg_rtx (DImode);
1713 operands[3] = gen_reg_rtx (DImode);
1714 operands[4] = gen_reg_rtx (DImode);
1717 (define_expand "unaligned_extendhidi_be"
1718 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1719 (set (match_dup 3) (plus:DI (match_dup 2) (const_int -2)))
1721 (mem:DI (and:DI (match_dup 3)
1723 (set (match_dup 5) (plus:DI (match_dup 2) (const_int -3)))
1725 (ashift:DI (match_dup 4)
1728 (plus:DI (match_dup 5) (const_int 1))
1731 (set (match_operand:DI 0 "register_operand" "")
1732 (ashiftrt:DI (match_dup 6) (const_int 48)))]
1735 operands[2] = gen_reg_rtx (DImode);
1736 operands[3] = gen_reg_rtx (DImode);
1737 operands[4] = gen_reg_rtx (DImode);
1738 operands[5] = gen_reg_rtx (DImode);
1739 operands[6] = gen_reg_rtx (DImode);
1742 (define_insn "*extxl_const"
1743 [(set (match_operand:DI 0 "register_operand" "=r")
1744 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1745 (match_operand:DI 2 "mode_width_operand" "n")
1746 (match_operand:DI 3 "mul8_operand" "I")))]
1748 "ext%M2l %r1,%s3,%0"
1749 [(set_attr "type" "shift")])
1751 (define_insn "extxl_le"
1752 [(set (match_operand:DI 0 "register_operand" "=r")
1753 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1754 (match_operand:DI 2 "mode_width_operand" "n")
1755 (ashift:DI (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1757 "! WORDS_BIG_ENDIAN"
1759 [(set_attr "type" "shift")])
1761 (define_insn "extxl_be"
1762 [(set (match_operand:DI 0 "register_operand" "=r")
1763 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1764 (match_operand:DI 2 "mode_width_operand" "n")
1768 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1772 [(set_attr "type" "shift")])
1774 ;; Combine has some strange notion of preserving existing undefined behavior
1775 ;; in shifts larger than a word size. So capture these patterns that it
1776 ;; should have turned into zero_extracts.
1778 (define_insn "*extxl_1_le"
1779 [(set (match_operand:DI 0 "register_operand" "=r")
1780 (and:DI (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1781 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1783 (match_operand:DI 3 "mode_mask_operand" "n")))]
1784 "! WORDS_BIG_ENDIAN"
1786 [(set_attr "type" "shift")])
1788 (define_insn "*extxl_1_be"
1789 [(set (match_operand:DI 0 "register_operand" "=r")
1790 (and:DI (lshiftrt:DI
1791 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1792 (minus:DI (const_int 56)
1793 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1795 (match_operand:DI 3 "mode_mask_operand" "n")))]
1798 [(set_attr "type" "shift")])
1800 (define_insn "*extql_2_le"
1801 [(set (match_operand:DI 0 "register_operand" "=r")
1802 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1803 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1805 "! WORDS_BIG_ENDIAN"
1807 [(set_attr "type" "shift")])
1809 (define_insn "*extql_2_be"
1810 [(set (match_operand:DI 0 "register_operand" "=r")
1812 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1813 (minus:DI (const_int 56)
1815 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1819 [(set_attr "type" "shift")])
1821 (define_insn "extqh_le"
1822 [(set (match_operand:DI 0 "register_operand" "=r")
1824 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1825 (minus:DI (const_int 64)
1828 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1831 "! WORDS_BIG_ENDIAN"
1833 [(set_attr "type" "shift")])
1835 (define_insn "extqh_be"
1836 [(set (match_operand:DI 0 "register_operand" "=r")
1838 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1841 (plus:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1847 [(set_attr "type" "shift")])
1849 (define_insn "extlh_le"
1850 [(set (match_operand:DI 0 "register_operand" "=r")
1852 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1853 (const_int 2147483647))
1854 (minus:DI (const_int 64)
1857 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1860 "! WORDS_BIG_ENDIAN"
1862 [(set_attr "type" "shift")])
1864 (define_insn "extlh_be"
1865 [(set (match_operand:DI 0 "register_operand" "=r")
1868 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1872 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1876 (const_int 2147483647)))]
1879 [(set_attr "type" "shift")])
1881 (define_insn "extwh_le"
1882 [(set (match_operand:DI 0 "register_operand" "=r")
1884 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1886 (minus:DI (const_int 64)
1889 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1892 "! WORDS_BIG_ENDIAN"
1894 [(set_attr "type" "shift")])
1896 (define_insn "extwh_be"
1897 [(set (match_operand:DI 0 "register_operand" "=r")
1899 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1903 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1907 (const_int 65535)))]
1910 [(set_attr "type" "shift")])
1912 ;; This converts an extXl into an extXh with an appropriate adjustment
1913 ;; to the address calculation.
1916 ;; [(set (match_operand:DI 0 "register_operand" "")
1917 ;; (ashift:DI (zero_extract:DI (match_operand:DI 1 "register_operand" "")
1918 ;; (match_operand:DI 2 "mode_width_operand" "")
1919 ;; (ashift:DI (match_operand:DI 3 "" "")
1921 ;; (match_operand:DI 4 "const_int_operand" "")))
1922 ;; (clobber (match_operand:DI 5 "register_operand" ""))]
1923 ;; "INTVAL (operands[4]) == 64 - INTVAL (operands[2])"
1924 ;; [(set (match_dup 5) (match_dup 6))
1925 ;; (set (match_dup 0)
1926 ;; (ashift:DI (zero_extract:DI (match_dup 1) (match_dup 2)
1927 ;; (ashift:DI (plus:DI (match_dup 5)
1933 ;; operands[6] = plus_constant (operands[3],
1934 ;; INTVAL (operands[2]) / BITS_PER_UNIT);
1935 ;; operands[7] = GEN_INT (- INTVAL (operands[2]) / BITS_PER_UNIT);
1938 (define_insn "*insbl_const"
1939 [(set (match_operand:DI 0 "register_operand" "=r")
1940 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
1941 (match_operand:DI 2 "mul8_operand" "I")))]
1944 [(set_attr "type" "shift")])
1946 (define_insn "*inswl_const"
1947 [(set (match_operand:DI 0 "register_operand" "=r")
1948 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
1949 (match_operand:DI 2 "mul8_operand" "I")))]
1952 [(set_attr "type" "shift")])
1954 (define_insn "*insll_const"
1955 [(set (match_operand:DI 0 "register_operand" "=r")
1956 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
1957 (match_operand:DI 2 "mul8_operand" "I")))]
1960 [(set_attr "type" "shift")])
1962 (define_insn "insbl_le"
1963 [(set (match_operand:DI 0 "register_operand" "=r")
1964 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
1965 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1967 "! WORDS_BIG_ENDIAN"
1969 [(set_attr "type" "shift")])
1971 (define_insn "insbl_be"
1972 [(set (match_operand:DI 0 "register_operand" "=r")
1973 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
1974 (minus:DI (const_int 56)
1975 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1979 [(set_attr "type" "shift")])
1981 (define_insn "inswl_le"
1982 [(set (match_operand:DI 0 "register_operand" "=r")
1983 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
1984 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1986 "! WORDS_BIG_ENDIAN"
1988 [(set_attr "type" "shift")])
1990 (define_insn "inswl_be"
1991 [(set (match_operand:DI 0 "register_operand" "=r")
1992 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
1993 (minus:DI (const_int 56)
1994 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1998 [(set_attr "type" "shift")])
2000 (define_insn "insll_le"
2001 [(set (match_operand:DI 0 "register_operand" "=r")
2002 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
2003 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2005 "! WORDS_BIG_ENDIAN"
2007 [(set_attr "type" "shift")])
2009 (define_insn "insll_be"
2010 [(set (match_operand:DI 0 "register_operand" "=r")
2011 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
2012 (minus:DI (const_int 56)
2013 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2017 [(set_attr "type" "shift")])
2019 (define_insn "insql_le"
2020 [(set (match_operand:DI 0 "register_operand" "=r")
2021 (ashift:DI (match_operand:DI 1 "register_operand" "r")
2022 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2024 "! WORDS_BIG_ENDIAN"
2026 [(set_attr "type" "shift")])
2028 (define_insn "insql_be"
2029 [(set (match_operand:DI 0 "register_operand" "=r")
2030 (ashift:DI (match_operand:DI 1 "register_operand" "r")
2031 (minus:DI (const_int 56)
2032 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2036 [(set_attr "type" "shift")])
2038 ;; Combine has this sometimes habit of moving the and outside of the
2039 ;; shift, making life more interesting.
2041 (define_insn "*insxl"
2042 [(set (match_operand:DI 0 "register_operand" "=r")
2043 (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
2044 (match_operand:DI 2 "mul8_operand" "I"))
2045 (match_operand:DI 3 "immediate_operand" "i")))]
2046 "HOST_BITS_PER_WIDE_INT == 64
2047 && GET_CODE (operands[3]) == CONST_INT
2048 && (((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
2049 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2050 || ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
2051 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2052 || ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
2053 == (unsigned HOST_WIDE_INT) INTVAL (operands[3])))"
2055 #if HOST_BITS_PER_WIDE_INT == 64
2056 if ((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
2057 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2058 return "insbl %1,%s2,%0";
2059 if ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
2060 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2061 return "inswl %1,%s2,%0";
2062 if ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
2063 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2064 return "insll %1,%s2,%0";
2068 [(set_attr "type" "shift")])
2070 ;; We do not include the insXh insns because they are complex to express
2071 ;; and it does not appear that we would ever want to generate them.
2073 ;; Since we need them for block moves, though, cop out and use unspec.
2075 (define_insn "insxh"
2076 [(set (match_operand:DI 0 "register_operand" "=r")
2077 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
2078 (match_operand:DI 2 "mode_width_operand" "n")
2079 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]
2083 [(set_attr "type" "shift")])
2085 (define_insn "mskxl_le"
2086 [(set (match_operand:DI 0 "register_operand" "=r")
2087 (and:DI (not:DI (ashift:DI
2088 (match_operand:DI 2 "mode_mask_operand" "n")
2090 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
2092 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
2093 "! WORDS_BIG_ENDIAN"
2095 [(set_attr "type" "shift")])
2097 (define_insn "mskxl_be"
2098 [(set (match_operand:DI 0 "register_operand" "=r")
2099 (and:DI (not:DI (ashift:DI
2100 (match_operand:DI 2 "mode_mask_operand" "n")
2101 (minus:DI (const_int 56)
2103 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
2105 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
2108 [(set_attr "type" "shift")])
2110 ;; We do not include the mskXh insns because it does not appear we would
2111 ;; ever generate one.
2113 ;; Again, we do for block moves and we use unspec again.
2115 (define_insn "mskxh"
2116 [(set (match_operand:DI 0 "register_operand" "=r")
2117 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
2118 (match_operand:DI 2 "mode_width_operand" "n")
2119 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]
2123 [(set_attr "type" "shift")])
2125 ;; Prefer AND + NE over LSHIFTRT + AND.
2127 (define_insn_and_split "*ze_and_ne"
2128 [(set (match_operand:DI 0 "register_operand" "=r")
2129 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
2131 (match_operand 2 "const_int_operand" "I")))]
2132 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8"
2134 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8"
2136 (and:DI (match_dup 1) (match_dup 3)))
2138 (ne:DI (match_dup 0) (const_int 0)))]
2139 "operands[3] = GEN_INT (1 << INTVAL (operands[2]));")
2141 ;; Floating-point operations. All the double-precision insns can extend
2142 ;; from single, so indicate that. The exception are the ones that simply
2143 ;; play with the sign bits; it's not clear what to do there.
2145 (define_insn "abssf2"
2146 [(set (match_operand:SF 0 "register_operand" "=f")
2147 (abs:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
2150 [(set_attr "type" "fcpys")])
2152 (define_insn "*nabssf2"
2153 [(set (match_operand:SF 0 "register_operand" "=f")
2154 (neg:SF (abs:SF (match_operand:SF 1 "reg_or_0_operand" "fG"))))]
2157 [(set_attr "type" "fadd")])
2159 (define_insn "absdf2"
2160 [(set (match_operand:DF 0 "register_operand" "=f")
2161 (abs:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2164 [(set_attr "type" "fcpys")])
2166 (define_insn "*nabsdf2"
2167 [(set (match_operand:DF 0 "register_operand" "=f")
2168 (neg:DF (abs:DF (match_operand:DF 1 "reg_or_0_operand" "fG"))))]
2171 [(set_attr "type" "fadd")])
2173 (define_expand "abstf2"
2174 [(parallel [(set (match_operand:TF 0 "register_operand" "")
2175 (abs:TF (match_operand:TF 1 "reg_or_0_operand" "")))
2176 (use (match_dup 2))])]
2177 "TARGET_HAS_XFLOATING_LIBS"
2179 #if HOST_BITS_PER_WIDE_INT >= 64
2180 operands[2] = force_reg (DImode, GEN_INT ((HOST_WIDE_INT) 1 << 63));
2182 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
2186 (define_insn_and_split "*abstf_internal"
2187 [(set (match_operand:TF 0 "register_operand" "=r")
2188 (abs:TF (match_operand:TF 1 "reg_or_0_operand" "rG")))
2189 (use (match_operand:DI 2 "register_operand" "r"))]
2190 "TARGET_HAS_XFLOATING_LIBS"
2192 "&& reload_completed"
2194 "alpha_split_tfmode_frobsign (operands, gen_andnotdi3); DONE;")
2196 (define_insn "negsf2"
2197 [(set (match_operand:SF 0 "register_operand" "=f")
2198 (neg:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
2201 [(set_attr "type" "fadd")])
2203 (define_insn "negdf2"
2204 [(set (match_operand:DF 0 "register_operand" "=f")
2205 (neg:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2208 [(set_attr "type" "fadd")])
2210 (define_expand "negtf2"
2211 [(parallel [(set (match_operand:TF 0 "register_operand" "")
2212 (neg:TF (match_operand:TF 1 "reg_or_0_operand" "")))
2213 (use (match_dup 2))])]
2214 "TARGET_HAS_XFLOATING_LIBS"
2216 #if HOST_BITS_PER_WIDE_INT >= 64
2217 operands[2] = force_reg (DImode, GEN_INT ((HOST_WIDE_INT) 1 << 63));
2219 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
2223 (define_insn_and_split "*negtf_internal"
2224 [(set (match_operand:TF 0 "register_operand" "=r")
2225 (neg:TF (match_operand:TF 1 "reg_or_0_operand" "rG")))
2226 (use (match_operand:DI 2 "register_operand" "r"))]
2227 "TARGET_HAS_XFLOATING_LIBS"
2229 "&& reload_completed"
2231 "alpha_split_tfmode_frobsign (operands, gen_xordi3); DONE;")
2233 (define_insn "*addsf_ieee"
2234 [(set (match_operand:SF 0 "register_operand" "=&f")
2235 (plus:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
2236 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2237 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2238 "add%,%/ %R1,%R2,%0"
2239 [(set_attr "type" "fadd")
2240 (set_attr "trap" "yes")
2241 (set_attr "round_suffix" "normal")
2242 (set_attr "trap_suffix" "u_su_sui")])
2244 (define_insn "addsf3"
2245 [(set (match_operand:SF 0 "register_operand" "=f")
2246 (plus:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
2247 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2249 "add%,%/ %R1,%R2,%0"
2250 [(set_attr "type" "fadd")
2251 (set_attr "trap" "yes")
2252 (set_attr "round_suffix" "normal")
2253 (set_attr "trap_suffix" "u_su_sui")])
2255 (define_insn "*adddf_ieee"
2256 [(set (match_operand:DF 0 "register_operand" "=&f")
2257 (plus:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
2258 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2259 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2260 "add%-%/ %R1,%R2,%0"
2261 [(set_attr "type" "fadd")
2262 (set_attr "trap" "yes")
2263 (set_attr "round_suffix" "normal")
2264 (set_attr "trap_suffix" "u_su_sui")])
2266 (define_insn "adddf3"
2267 [(set (match_operand:DF 0 "register_operand" "=f")
2268 (plus:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
2269 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2271 "add%-%/ %R1,%R2,%0"
2272 [(set_attr "type" "fadd")
2273 (set_attr "trap" "yes")
2274 (set_attr "round_suffix" "normal")
2275 (set_attr "trap_suffix" "u_su_sui")])
2277 (define_insn "*adddf_ext1"
2278 [(set (match_operand:DF 0 "register_operand" "=f")
2279 (plus:DF (float_extend:DF
2280 (match_operand:SF 1 "reg_or_0_operand" "fG"))
2281 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2282 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2283 "add%-%/ %R1,%R2,%0"
2284 [(set_attr "type" "fadd")
2285 (set_attr "trap" "yes")
2286 (set_attr "round_suffix" "normal")
2287 (set_attr "trap_suffix" "u_su_sui")])
2289 (define_insn "*adddf_ext2"
2290 [(set (match_operand:DF 0 "register_operand" "=f")
2291 (plus:DF (float_extend:DF
2292 (match_operand:SF 1 "reg_or_0_operand" "%fG"))
2294 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2295 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2296 "add%-%/ %R1,%R2,%0"
2297 [(set_attr "type" "fadd")
2298 (set_attr "trap" "yes")
2299 (set_attr "round_suffix" "normal")
2300 (set_attr "trap_suffix" "u_su_sui")])
2302 (define_expand "addtf3"
2303 [(use (match_operand 0 "register_operand" ""))
2304 (use (match_operand 1 "general_operand" ""))
2305 (use (match_operand 2 "general_operand" ""))]
2306 "TARGET_HAS_XFLOATING_LIBS"
2307 "alpha_emit_xfloating_arith (PLUS, operands); DONE;")
2309 ;; Define conversion operators between DFmode and SImode, using the cvtql
2310 ;; instruction. To allow combine et al to do useful things, we keep the
2311 ;; operation as a unit until after reload, at which point we split the
2314 ;; Note that we (attempt to) only consider this optimization when the
2315 ;; ultimate destination is memory. If we will be doing further integer
2316 ;; processing, it is cheaper to do the truncation in the int regs.
2318 (define_insn "*cvtql"
2319 [(set (match_operand:SF 0 "register_operand" "=f")
2320 (unspec:SF [(match_operand:DI 1 "reg_or_0_operand" "fG")]
2324 [(set_attr "type" "fadd")
2325 (set_attr "trap" "yes")
2326 (set_attr "trap_suffix" "v_sv")])
2328 (define_insn_and_split "*fix_truncdfsi_ieee"
2329 [(set (match_operand:SI 0 "memory_operand" "=m")
2331 (match_operator:DI 4 "fix_operator"
2332 [(match_operand:DF 1 "reg_or_0_operand" "fG")]) 0))
2333 (clobber (match_scratch:DI 2 "=&f"))
2334 (clobber (match_scratch:SF 3 "=&f"))]
2335 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2337 "&& reload_completed"
2338 [(set (match_dup 2) (match_op_dup 4 [(match_dup 1)]))
2339 (set (match_dup 3) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL))
2340 (set (match_dup 5) (match_dup 3))]
2342 operands[5] = adjust_address (operands[0], SFmode, 0);
2344 [(set_attr "type" "fadd")
2345 (set_attr "trap" "yes")])
2347 (define_insn_and_split "*fix_truncdfsi_internal"
2348 [(set (match_operand:SI 0 "memory_operand" "=m")
2350 (match_operator:DI 3 "fix_operator"
2351 [(match_operand:DF 1 "reg_or_0_operand" "fG")]) 0))
2352 (clobber (match_scratch:DI 2 "=f"))]
2353 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2355 "&& reload_completed"
2356 [(set (match_dup 2) (match_op_dup 3 [(match_dup 1)]))
2357 (set (match_dup 4) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL))
2358 (set (match_dup 5) (match_dup 4))]
2360 operands[4] = gen_rtx_REG (SFmode, REGNO (operands[2]));
2361 operands[5] = adjust_address (operands[0], SFmode, 0);
2363 [(set_attr "type" "fadd")
2364 (set_attr "trap" "yes")])
2366 (define_insn "*fix_truncdfdi_ieee"
2367 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
2368 (match_operator:DI 2 "fix_operator"
2369 [(match_operand:DF 1 "reg_or_0_operand" "fG")]))]
2370 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2372 [(set_attr "type" "fadd")
2373 (set_attr "trap" "yes")
2374 (set_attr "round_suffix" "c")
2375 (set_attr "trap_suffix" "v_sv_svi")])
2377 (define_insn "*fix_truncdfdi2"
2378 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
2379 (match_operator:DI 2 "fix_operator"
2380 [(match_operand:DF 1 "reg_or_0_operand" "fG")]))]
2383 [(set_attr "type" "fadd")
2384 (set_attr "trap" "yes")
2385 (set_attr "round_suffix" "c")
2386 (set_attr "trap_suffix" "v_sv_svi")])
2388 (define_expand "fix_truncdfdi2"
2389 [(set (match_operand:DI 0 "reg_no_subreg_operand" "")
2390 (fix:DI (match_operand:DF 1 "reg_or_0_operand" "")))]
2394 (define_expand "fixuns_truncdfdi2"
2395 [(set (match_operand:DI 0 "reg_no_subreg_operand" "")
2396 (unsigned_fix:DI (match_operand:DF 1 "reg_or_0_operand" "")))]
2400 ;; Likewise between SFmode and SImode.
2402 (define_insn_and_split "*fix_truncsfsi_ieee"
2403 [(set (match_operand:SI 0 "memory_operand" "=m")
2405 (match_operator:DI 4 "fix_operator"
2407 (match_operand:SF 1 "reg_or_0_operand" "fG"))]) 0))
2408 (clobber (match_scratch:DI 2 "=&f"))
2409 (clobber (match_scratch:SF 3 "=&f"))]
2410 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2412 "&& reload_completed"
2413 [(set (match_dup 2) (match_op_dup 4 [(float_extend:DF (match_dup 1))]))
2414 (set (match_dup 3) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL))
2415 (set (match_dup 5) (match_dup 3))]
2417 operands[5] = adjust_address (operands[0], SFmode, 0);
2419 [(set_attr "type" "fadd")
2420 (set_attr "trap" "yes")])
2422 (define_insn_and_split "*fix_truncsfsi_internal"
2423 [(set (match_operand:SI 0 "memory_operand" "=m")
2425 (match_operator:DI 3 "fix_operator"
2427 (match_operand:SF 1 "reg_or_0_operand" "fG"))]) 0))
2428 (clobber (match_scratch:DI 2 "=f"))]
2429 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2431 "&& reload_completed"
2432 [(set (match_dup 2) (match_op_dup 3 [(float_extend:DF (match_dup 1))]))
2433 (set (match_dup 4) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL))
2434 (set (match_dup 5) (match_dup 4))]
2436 operands[4] = gen_rtx_REG (SFmode, REGNO (operands[2]));
2437 operands[5] = adjust_address (operands[0], SFmode, 0);
2439 [(set_attr "type" "fadd")
2440 (set_attr "trap" "yes")])
2442 (define_insn "*fix_truncsfdi_ieee"
2443 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
2444 (match_operator:DI 2 "fix_operator"
2445 [(float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))]))]
2446 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2448 [(set_attr "type" "fadd")
2449 (set_attr "trap" "yes")
2450 (set_attr "round_suffix" "c")
2451 (set_attr "trap_suffix" "v_sv_svi")])
2453 (define_insn "*fix_truncsfdi2"
2454 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
2455 (match_operator:DI 2 "fix_operator"
2456 [(float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))]))]
2459 [(set_attr "type" "fadd")
2460 (set_attr "trap" "yes")
2461 (set_attr "round_suffix" "c")
2462 (set_attr "trap_suffix" "v_sv_svi")])
2464 (define_expand "fix_truncsfdi2"
2465 [(set (match_operand:DI 0 "reg_no_subreg_operand" "")
2466 (fix:DI (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))))]
2470 (define_expand "fixuns_truncsfdi2"
2471 [(set (match_operand:DI 0 "reg_no_subreg_operand" "")
2473 (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))))]
2477 (define_expand "fix_trunctfdi2"
2478 [(use (match_operand:DI 0 "register_operand" ""))
2479 (use (match_operand:TF 1 "general_operand" ""))]
2480 "TARGET_HAS_XFLOATING_LIBS"
2481 "alpha_emit_xfloating_cvt (FIX, operands); DONE;")
2483 (define_expand "fixuns_trunctfdi2"
2484 [(use (match_operand:DI 0 "register_operand" ""))
2485 (use (match_operand:TF 1 "general_operand" ""))]
2486 "TARGET_HAS_XFLOATING_LIBS"
2487 "alpha_emit_xfloating_cvt (UNSIGNED_FIX, operands); DONE;")
2489 (define_insn "*floatdisf_ieee"
2490 [(set (match_operand:SF 0 "register_operand" "=&f")
2491 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2492 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2494 [(set_attr "type" "fadd")
2495 (set_attr "trap" "yes")
2496 (set_attr "round_suffix" "normal")
2497 (set_attr "trap_suffix" "sui")])
2499 (define_insn "floatdisf2"
2500 [(set (match_operand:SF 0 "register_operand" "=f")
2501 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2504 [(set_attr "type" "fadd")
2505 (set_attr "trap" "yes")
2506 (set_attr "round_suffix" "normal")
2507 (set_attr "trap_suffix" "sui")])
2509 (define_insn_and_split "*floatsisf2_ieee"
2510 [(set (match_operand:SF 0 "register_operand" "=&f")
2511 (float:SF (match_operand:SI 1 "memory_operand" "m")))
2512 (clobber (match_scratch:DI 2 "=&f"))
2513 (clobber (match_scratch:SF 3 "=&f"))]
2514 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2516 "&& reload_completed"
2517 [(set (match_dup 3) (match_dup 1))
2518 (set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ))
2519 (set (match_dup 0) (float:SF (match_dup 2)))]
2521 operands[1] = adjust_address (operands[1], SFmode, 0);
2524 (define_insn_and_split "*floatsisf2"
2525 [(set (match_operand:SF 0 "register_operand" "=f")
2526 (float:SF (match_operand:SI 1 "memory_operand" "m")))]
2529 "&& reload_completed"
2530 [(set (match_dup 0) (match_dup 1))
2531 (set (match_dup 2) (unspec:DI [(match_dup 0)] UNSPEC_CVTLQ))
2532 (set (match_dup 0) (float:SF (match_dup 2)))]
2534 operands[1] = adjust_address (operands[1], SFmode, 0);
2535 operands[2] = gen_rtx_REG (DImode, REGNO (operands[0]));
2538 (define_insn "*floatdidf_ieee"
2539 [(set (match_operand:DF 0 "register_operand" "=&f")
2540 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2541 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2543 [(set_attr "type" "fadd")
2544 (set_attr "trap" "yes")
2545 (set_attr "round_suffix" "normal")
2546 (set_attr "trap_suffix" "sui")])
2548 (define_insn "floatdidf2"
2549 [(set (match_operand:DF 0 "register_operand" "=f")
2550 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2553 [(set_attr "type" "fadd")
2554 (set_attr "trap" "yes")
2555 (set_attr "round_suffix" "normal")
2556 (set_attr "trap_suffix" "sui")])
2558 (define_insn_and_split "*floatsidf2_ieee"
2559 [(set (match_operand:DF 0 "register_operand" "=&f")
2560 (float:DF (match_operand:SI 1 "memory_operand" "m")))
2561 (clobber (match_scratch:DI 2 "=&f"))
2562 (clobber (match_scratch:SF 3 "=&f"))]
2563 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2565 "&& reload_completed"
2566 [(set (match_dup 3) (match_dup 1))
2567 (set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ))
2568 (set (match_dup 0) (float:DF (match_dup 2)))]
2570 operands[1] = adjust_address (operands[1], SFmode, 0);
2573 (define_insn_and_split "*floatsidf2"
2574 [(set (match_operand:DF 0 "register_operand" "=f")
2575 (float:DF (match_operand:SI 1 "memory_operand" "m")))]
2578 "&& reload_completed"
2579 [(set (match_dup 3) (match_dup 1))
2580 (set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ))
2581 (set (match_dup 0) (float:DF (match_dup 2)))]
2583 operands[1] = adjust_address (operands[1], SFmode, 0);
2584 operands[2] = gen_rtx_REG (DImode, REGNO (operands[0]));
2585 operands[3] = gen_rtx_REG (SFmode, REGNO (operands[0]));
2588 (define_expand "floatditf2"
2589 [(use (match_operand:TF 0 "register_operand" ""))
2590 (use (match_operand:DI 1 "general_operand" ""))]
2591 "TARGET_HAS_XFLOATING_LIBS"
2592 "alpha_emit_xfloating_cvt (FLOAT, operands); DONE;")
2594 (define_expand "floatunsdisf2"
2595 [(use (match_operand:SF 0 "register_operand" ""))
2596 (use (match_operand:DI 1 "register_operand" ""))]
2598 "alpha_emit_floatuns (operands); DONE;")
2600 (define_expand "floatunsdidf2"
2601 [(use (match_operand:DF 0 "register_operand" ""))
2602 (use (match_operand:DI 1 "register_operand" ""))]
2604 "alpha_emit_floatuns (operands); DONE;")
2606 (define_expand "floatunsditf2"
2607 [(use (match_operand:TF 0 "register_operand" ""))
2608 (use (match_operand:DI 1 "general_operand" ""))]
2609 "TARGET_HAS_XFLOATING_LIBS"
2610 "alpha_emit_xfloating_cvt (UNSIGNED_FLOAT, operands); DONE;")
2612 (define_expand "extendsfdf2"
2613 [(set (match_operand:DF 0 "register_operand" "")
2614 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
2617 if (alpha_fptm >= ALPHA_FPTM_SU)
2618 operands[1] = force_reg (SFmode, operands[1]);
2621 ;; The Unicos/Mk assembler doesn't support cvtst, but we've already
2622 ;; asserted that alpha_fptm == ALPHA_FPTM_N.
2624 (define_insn "*extendsfdf2_ieee"
2625 [(set (match_operand:DF 0 "register_operand" "=&f")
2626 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
2627 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2629 [(set_attr "type" "fadd")
2630 (set_attr "trap" "yes")])
2632 (define_insn "*extendsfdf2_internal"
2633 [(set (match_operand:DF 0 "register_operand" "=f,f,m")
2634 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m,f")))]
2635 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2640 [(set_attr "type" "fcpys,fld,fst")])
2642 ;; Use register_operand for operand 1 to prevent compress_float_constant
2643 ;; from doing something silly. When optimizing we'll put things back
2645 (define_expand "extendsftf2"
2646 [(use (match_operand:TF 0 "register_operand" ""))
2647 (use (match_operand:SF 1 "register_operand" ""))]
2648 "TARGET_HAS_XFLOATING_LIBS"
2650 rtx tmp = gen_reg_rtx (DFmode);
2651 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
2652 emit_insn (gen_extenddftf2 (operands[0], tmp));
2656 (define_expand "extenddftf2"
2657 [(use (match_operand:TF 0 "register_operand" ""))
2658 (use (match_operand:DF 1 "register_operand" ""))]
2659 "TARGET_HAS_XFLOATING_LIBS"
2660 "alpha_emit_xfloating_cvt (FLOAT_EXTEND, operands); DONE;")
2662 (define_insn "*truncdfsf2_ieee"
2663 [(set (match_operand:SF 0 "register_operand" "=&f")
2664 (float_truncate:SF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2665 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2667 [(set_attr "type" "fadd")
2668 (set_attr "trap" "yes")
2669 (set_attr "round_suffix" "normal")
2670 (set_attr "trap_suffix" "u_su_sui")])
2672 (define_insn "truncdfsf2"
2673 [(set (match_operand:SF 0 "register_operand" "=f")
2674 (float_truncate:SF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2677 [(set_attr "type" "fadd")
2678 (set_attr "trap" "yes")
2679 (set_attr "round_suffix" "normal")
2680 (set_attr "trap_suffix" "u_su_sui")])
2682 (define_expand "trunctfdf2"
2683 [(use (match_operand:DF 0 "register_operand" ""))
2684 (use (match_operand:TF 1 "general_operand" ""))]
2685 "TARGET_HAS_XFLOATING_LIBS"
2686 "alpha_emit_xfloating_cvt (FLOAT_TRUNCATE, operands); DONE;")
2688 (define_expand "trunctfsf2"
2689 [(use (match_operand:SF 0 "register_operand" ""))
2690 (use (match_operand:TF 1 "general_operand" ""))]
2691 "TARGET_FP && TARGET_HAS_XFLOATING_LIBS"
2693 rtx tmpf, sticky, arg, lo, hi;
2695 tmpf = gen_reg_rtx (DFmode);
2696 sticky = gen_reg_rtx (DImode);
2697 arg = copy_to_mode_reg (TFmode, operands[1]);
2698 lo = gen_lowpart (DImode, arg);
2699 hi = gen_highpart (DImode, arg);
2701 /* Convert the low word of the TFmode value into a sticky rounding bit,
2702 then or it into the low bit of the high word. This leaves the sticky
2703 bit at bit 48 of the fraction, which is representable in DFmode,
2704 which prevents rounding error in the final conversion to SFmode. */
2706 emit_insn (gen_rtx_SET (VOIDmode, sticky,
2707 gen_rtx_NE (DImode, lo, const0_rtx)));
2708 emit_insn (gen_iordi3 (hi, hi, sticky));
2709 emit_insn (gen_trunctfdf2 (tmpf, arg));
2710 emit_insn (gen_truncdfsf2 (operands[0], tmpf));
2714 (define_insn "*divsf3_ieee"
2715 [(set (match_operand:SF 0 "register_operand" "=&f")
2716 (div:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
2717 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2718 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2719 "div%,%/ %R1,%R2,%0"
2720 [(set_attr "type" "fdiv")
2721 (set_attr "opsize" "si")
2722 (set_attr "trap" "yes")
2723 (set_attr "round_suffix" "normal")
2724 (set_attr "trap_suffix" "u_su_sui")])
2726 (define_insn "divsf3"
2727 [(set (match_operand:SF 0 "register_operand" "=f")
2728 (div:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
2729 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2731 "div%,%/ %R1,%R2,%0"
2732 [(set_attr "type" "fdiv")
2733 (set_attr "opsize" "si")
2734 (set_attr "trap" "yes")
2735 (set_attr "round_suffix" "normal")
2736 (set_attr "trap_suffix" "u_su_sui")])
2738 (define_insn "*divdf3_ieee"
2739 [(set (match_operand:DF 0 "register_operand" "=&f")
2740 (div:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2741 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2742 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2743 "div%-%/ %R1,%R2,%0"
2744 [(set_attr "type" "fdiv")
2745 (set_attr "trap" "yes")
2746 (set_attr "round_suffix" "normal")
2747 (set_attr "trap_suffix" "u_su_sui")])
2749 (define_insn "divdf3"
2750 [(set (match_operand:DF 0 "register_operand" "=f")
2751 (div:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2752 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2754 "div%-%/ %R1,%R2,%0"
2755 [(set_attr "type" "fdiv")
2756 (set_attr "trap" "yes")
2757 (set_attr "round_suffix" "normal")
2758 (set_attr "trap_suffix" "u_su_sui")])
2760 (define_insn "*divdf_ext1"
2761 [(set (match_operand:DF 0 "register_operand" "=f")
2762 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))
2763 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2764 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2765 "div%-%/ %R1,%R2,%0"
2766 [(set_attr "type" "fdiv")
2767 (set_attr "trap" "yes")
2768 (set_attr "round_suffix" "normal")
2769 (set_attr "trap_suffix" "u_su_sui")])
2771 (define_insn "*divdf_ext2"
2772 [(set (match_operand:DF 0 "register_operand" "=f")
2773 (div:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2775 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2776 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2777 "div%-%/ %R1,%R2,%0"
2778 [(set_attr "type" "fdiv")
2779 (set_attr "trap" "yes")
2780 (set_attr "round_suffix" "normal")
2781 (set_attr "trap_suffix" "u_su_sui")])
2783 (define_insn "*divdf_ext3"
2784 [(set (match_operand:DF 0 "register_operand" "=f")
2785 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))
2786 (float_extend:DF (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2787 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2788 "div%-%/ %R1,%R2,%0"
2789 [(set_attr "type" "fdiv")
2790 (set_attr "trap" "yes")
2791 (set_attr "round_suffix" "normal")
2792 (set_attr "trap_suffix" "u_su_sui")])
2794 (define_expand "divtf3"
2795 [(use (match_operand 0 "register_operand" ""))
2796 (use (match_operand 1 "general_operand" ""))
2797 (use (match_operand 2 "general_operand" ""))]
2798 "TARGET_HAS_XFLOATING_LIBS"
2799 "alpha_emit_xfloating_arith (DIV, operands); DONE;")
2801 (define_insn "*mulsf3_ieee"
2802 [(set (match_operand:SF 0 "register_operand" "=&f")
2803 (mult:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
2804 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2805 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2806 "mul%,%/ %R1,%R2,%0"
2807 [(set_attr "type" "fmul")
2808 (set_attr "trap" "yes")
2809 (set_attr "round_suffix" "normal")
2810 (set_attr "trap_suffix" "u_su_sui")])
2812 (define_insn "mulsf3"
2813 [(set (match_operand:SF 0 "register_operand" "=f")
2814 (mult:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
2815 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2817 "mul%,%/ %R1,%R2,%0"
2818 [(set_attr "type" "fmul")
2819 (set_attr "trap" "yes")
2820 (set_attr "round_suffix" "normal")
2821 (set_attr "trap_suffix" "u_su_sui")])
2823 (define_insn "*muldf3_ieee"
2824 [(set (match_operand:DF 0 "register_operand" "=&f")
2825 (mult:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
2826 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2827 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2828 "mul%-%/ %R1,%R2,%0"
2829 [(set_attr "type" "fmul")
2830 (set_attr "trap" "yes")
2831 (set_attr "round_suffix" "normal")
2832 (set_attr "trap_suffix" "u_su_sui")])
2834 (define_insn "muldf3"
2835 [(set (match_operand:DF 0 "register_operand" "=f")
2836 (mult:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
2837 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2839 "mul%-%/ %R1,%R2,%0"
2840 [(set_attr "type" "fmul")
2841 (set_attr "trap" "yes")
2842 (set_attr "round_suffix" "normal")
2843 (set_attr "trap_suffix" "u_su_sui")])
2845 (define_insn "*muldf_ext1"
2846 [(set (match_operand:DF 0 "register_operand" "=f")
2847 (mult:DF (float_extend:DF
2848 (match_operand:SF 1 "reg_or_0_operand" "fG"))
2849 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2850 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2851 "mul%-%/ %R1,%R2,%0"
2852 [(set_attr "type" "fmul")
2853 (set_attr "trap" "yes")
2854 (set_attr "round_suffix" "normal")
2855 (set_attr "trap_suffix" "u_su_sui")])
2857 (define_insn "*muldf_ext2"
2858 [(set (match_operand:DF 0 "register_operand" "=f")
2859 (mult:DF (float_extend:DF
2860 (match_operand:SF 1 "reg_or_0_operand" "%fG"))
2862 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2863 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2864 "mul%-%/ %R1,%R2,%0"
2865 [(set_attr "type" "fmul")
2866 (set_attr "trap" "yes")
2867 (set_attr "round_suffix" "normal")
2868 (set_attr "trap_suffix" "u_su_sui")])
2870 (define_expand "multf3"
2871 [(use (match_operand 0 "register_operand" ""))
2872 (use (match_operand 1 "general_operand" ""))
2873 (use (match_operand 2 "general_operand" ""))]
2874 "TARGET_HAS_XFLOATING_LIBS"
2875 "alpha_emit_xfloating_arith (MULT, operands); DONE;")
2877 (define_insn "*subsf3_ieee"
2878 [(set (match_operand:SF 0 "register_operand" "=&f")
2879 (minus:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
2880 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2881 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2882 "sub%,%/ %R1,%R2,%0"
2883 [(set_attr "type" "fadd")
2884 (set_attr "trap" "yes")
2885 (set_attr "round_suffix" "normal")
2886 (set_attr "trap_suffix" "u_su_sui")])
2888 (define_insn "subsf3"
2889 [(set (match_operand:SF 0 "register_operand" "=f")
2890 (minus:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
2891 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2893 "sub%,%/ %R1,%R2,%0"
2894 [(set_attr "type" "fadd")
2895 (set_attr "trap" "yes")
2896 (set_attr "round_suffix" "normal")
2897 (set_attr "trap_suffix" "u_su_sui")])
2899 (define_insn "*subdf3_ieee"
2900 [(set (match_operand:DF 0 "register_operand" "=&f")
2901 (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2902 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2903 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2904 "sub%-%/ %R1,%R2,%0"
2905 [(set_attr "type" "fadd")
2906 (set_attr "trap" "yes")
2907 (set_attr "round_suffix" "normal")
2908 (set_attr "trap_suffix" "u_su_sui")])
2910 (define_insn "subdf3"
2911 [(set (match_operand:DF 0 "register_operand" "=f")
2912 (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2913 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2915 "sub%-%/ %R1,%R2,%0"
2916 [(set_attr "type" "fadd")
2917 (set_attr "trap" "yes")
2918 (set_attr "round_suffix" "normal")
2919 (set_attr "trap_suffix" "u_su_sui")])
2921 (define_insn "*subdf_ext1"
2922 [(set (match_operand:DF 0 "register_operand" "=f")
2923 (minus:DF (float_extend:DF
2924 (match_operand:SF 1 "reg_or_0_operand" "fG"))
2925 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2926 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2927 "sub%-%/ %R1,%R2,%0"
2928 [(set_attr "type" "fadd")
2929 (set_attr "trap" "yes")
2930 (set_attr "round_suffix" "normal")
2931 (set_attr "trap_suffix" "u_su_sui")])
2933 (define_insn "*subdf_ext2"
2934 [(set (match_operand:DF 0 "register_operand" "=f")
2935 (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2937 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2938 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2939 "sub%-%/ %R1,%R2,%0"
2940 [(set_attr "type" "fadd")
2941 (set_attr "trap" "yes")
2942 (set_attr "round_suffix" "normal")
2943 (set_attr "trap_suffix" "u_su_sui")])
2945 (define_insn "*subdf_ext3"
2946 [(set (match_operand:DF 0 "register_operand" "=f")
2947 (minus:DF (float_extend:DF
2948 (match_operand:SF 1 "reg_or_0_operand" "fG"))
2950 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2951 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2952 "sub%-%/ %R1,%R2,%0"
2953 [(set_attr "type" "fadd")
2954 (set_attr "trap" "yes")
2955 (set_attr "round_suffix" "normal")
2956 (set_attr "trap_suffix" "u_su_sui")])
2958 (define_expand "subtf3"
2959 [(use (match_operand 0 "register_operand" ""))
2960 (use (match_operand 1 "general_operand" ""))
2961 (use (match_operand 2 "general_operand" ""))]
2962 "TARGET_HAS_XFLOATING_LIBS"
2963 "alpha_emit_xfloating_arith (MINUS, operands); DONE;")
2965 (define_insn "*sqrtsf2_ieee"
2966 [(set (match_operand:SF 0 "register_operand" "=&f")
2967 (sqrt:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
2968 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
2970 [(set_attr "type" "fsqrt")
2971 (set_attr "opsize" "si")
2972 (set_attr "trap" "yes")
2973 (set_attr "round_suffix" "normal")
2974 (set_attr "trap_suffix" "u_su_sui")])
2976 (define_insn "sqrtsf2"
2977 [(set (match_operand:SF 0 "register_operand" "=f")
2978 (sqrt:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
2979 "TARGET_FP && TARGET_FIX"
2981 [(set_attr "type" "fsqrt")
2982 (set_attr "opsize" "si")
2983 (set_attr "trap" "yes")
2984 (set_attr "round_suffix" "normal")
2985 (set_attr "trap_suffix" "u_su_sui")])
2987 (define_insn "*sqrtdf2_ieee"
2988 [(set (match_operand:DF 0 "register_operand" "=&f")
2989 (sqrt:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2990 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
2992 [(set_attr "type" "fsqrt")
2993 (set_attr "trap" "yes")
2994 (set_attr "round_suffix" "normal")
2995 (set_attr "trap_suffix" "u_su_sui")])
2997 (define_insn "sqrtdf2"
2998 [(set (match_operand:DF 0 "register_operand" "=f")
2999 (sqrt:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
3000 "TARGET_FP && TARGET_FIX"
3002 [(set_attr "type" "fsqrt")
3003 (set_attr "trap" "yes")
3004 (set_attr "round_suffix" "normal")
3005 (set_attr "trap_suffix" "u_su_sui")])
3007 ;; Next are all the integer comparisons, and conditional moves and branches
3008 ;; and some of the related define_expand's and define_split's.
3010 (define_insn "*setcc_internal"
3011 [(set (match_operand 0 "register_operand" "=r")
3012 (match_operator 1 "alpha_comparison_operator"
3013 [(match_operand:DI 2 "register_operand" "r")
3014 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]))]
3015 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
3016 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
3017 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
3019 [(set_attr "type" "icmp")])
3021 ;; Yes, we can technically support reg_or_8bit_operand in operand 2,
3022 ;; but that's non-canonical rtl and allowing that causes inefficiencies
3024 (define_insn "*setcc_swapped_internal"
3025 [(set (match_operand 0 "register_operand" "=r")
3026 (match_operator 1 "alpha_swapped_comparison_operator"
3027 [(match_operand:DI 2 "register_operand" "r")
3028 (match_operand:DI 3 "reg_or_0_operand" "rJ")]))]
3029 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
3030 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
3031 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
3033 [(set_attr "type" "icmp")])
3035 ;; Use match_operator rather than ne directly so that we can match
3036 ;; multiple integer modes.
3037 (define_insn "*setne_internal"
3038 [(set (match_operand 0 "register_operand" "=r")
3039 (match_operator 1 "signed_comparison_operator"
3040 [(match_operand:DI 2 "register_operand" "r")
3042 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
3043 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
3044 && GET_CODE (operands[1]) == NE
3045 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
3047 [(set_attr "type" "icmp")])
3049 ;; The mode folding trick can't be used with const_int operands, since
3050 ;; reload needs to know the proper mode.
3052 ;; Use add_operand instead of the more seemingly natural reg_or_8bit_operand
3053 ;; in order to create more pairs of constants. As long as we're allowing
3054 ;; two constants at the same time, and will have to reload one of them...
3056 (define_insn "*movqicc_internal"
3057 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r")
3059 (match_operator 2 "signed_comparison_operator"
3060 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3061 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3062 (match_operand:QI 1 "add_operand" "rI,0,rI,0")
3063 (match_operand:QI 5 "add_operand" "0,rI,0,rI")))]
3064 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
3070 [(set_attr "type" "icmov")])
3072 (define_insn "*movhicc_internal"
3073 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
3075 (match_operator 2 "signed_comparison_operator"
3076 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3077 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3078 (match_operand:HI 1 "add_operand" "rI,0,rI,0")
3079 (match_operand:HI 5 "add_operand" "0,rI,0,rI")))]
3080 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
3086 [(set_attr "type" "icmov")])
3088 (define_insn "*movsicc_internal"
3089 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
3091 (match_operator 2 "signed_comparison_operator"
3092 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3093 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3094 (match_operand:SI 1 "add_operand" "rI,0,rI,0")
3095 (match_operand:SI 5 "add_operand" "0,rI,0,rI")))]
3096 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
3102 [(set_attr "type" "icmov")])
3104 (define_insn "*movdicc_internal"
3105 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
3107 (match_operator 2 "signed_comparison_operator"
3108 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3109 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3110 (match_operand:DI 1 "add_operand" "rI,0,rI,0")
3111 (match_operand:DI 5 "add_operand" "0,rI,0,rI")))]
3112 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
3118 [(set_attr "type" "icmov")])
3120 (define_insn "*movqicc_lbc"
3121 [(set (match_operand:QI 0 "register_operand" "=r,r")
3123 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3127 (match_operand:QI 1 "reg_or_8bit_operand" "rI,0")
3128 (match_operand:QI 3 "reg_or_8bit_operand" "0,rI")))]
3133 [(set_attr "type" "icmov")])
3135 (define_insn "*movhicc_lbc"
3136 [(set (match_operand:HI 0 "register_operand" "=r,r")
3138 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3142 (match_operand:HI 1 "reg_or_8bit_operand" "rI,0")
3143 (match_operand:HI 3 "reg_or_8bit_operand" "0,rI")))]
3148 [(set_attr "type" "icmov")])
3150 (define_insn "*movsicc_lbc"
3151 [(set (match_operand:SI 0 "register_operand" "=r,r")
3153 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3157 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0")
3158 (match_operand:SI 3 "reg_or_8bit_operand" "0,rI")))]
3163 [(set_attr "type" "icmov")])
3165 (define_insn "*movdicc_lbc"
3166 [(set (match_operand:DI 0 "register_operand" "=r,r")
3168 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3172 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
3173 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
3178 [(set_attr "type" "icmov")])
3180 (define_insn "*movqicc_lbs"
3181 [(set (match_operand:QI 0 "register_operand" "=r,r")
3183 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3187 (match_operand:QI 1 "reg_or_8bit_operand" "rI,0")
3188 (match_operand:QI 3 "reg_or_8bit_operand" "0,rI")))]
3193 [(set_attr "type" "icmov")])
3195 (define_insn "*movhicc_lbs"
3196 [(set (match_operand:HI 0 "register_operand" "=r,r")
3198 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3202 (match_operand:HI 1 "reg_or_8bit_operand" "rI,0")
3203 (match_operand:HI 3 "reg_or_8bit_operand" "0,rI")))]
3208 [(set_attr "type" "icmov")])
3210 (define_insn "*movsicc_lbs"
3211 [(set (match_operand:SI 0 "register_operand" "=r,r")
3213 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3217 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0")
3218 (match_operand:SI 3 "reg_or_8bit_operand" "0,rI")))]
3223 [(set_attr "type" "icmov")])
3225 (define_insn "*movdicc_lbs"
3226 [(set (match_operand:DI 0 "register_operand" "=r,r")
3228 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3232 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
3233 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
3238 [(set_attr "type" "icmov")])
3240 ;; For ABS, we have two choices, depending on whether the input and output
3241 ;; registers are the same or not.
3242 (define_expand "absdi2"
3243 [(set (match_operand:DI 0 "register_operand" "")
3244 (abs:DI (match_operand:DI 1 "register_operand" "")))]
3247 if (rtx_equal_p (operands[0], operands[1]))
3248 emit_insn (gen_absdi2_same (operands[0], gen_reg_rtx (DImode)));
3250 emit_insn (gen_absdi2_diff (operands[0], operands[1]));
3254 (define_expand "absdi2_same"
3255 [(set (match_operand:DI 1 "register_operand" "")
3256 (neg:DI (match_operand:DI 0 "register_operand" "")))
3258 (if_then_else:DI (ge (match_dup 0) (const_int 0))
3264 (define_expand "absdi2_diff"
3265 [(set (match_operand:DI 0 "register_operand" "")
3266 (neg:DI (match_operand:DI 1 "register_operand" "")))
3268 (if_then_else:DI (lt (match_dup 1) (const_int 0))
3275 [(set (match_operand:DI 0 "register_operand" "")
3276 (abs:DI (match_dup 0)))
3277 (clobber (match_operand:DI 1 "register_operand" ""))]
3279 [(set (match_dup 1) (neg:DI (match_dup 0)))
3280 (set (match_dup 0) (if_then_else:DI (ge (match_dup 0) (const_int 0))
3281 (match_dup 0) (match_dup 1)))]
3285 [(set (match_operand:DI 0 "register_operand" "")
3286 (abs:DI (match_operand:DI 1 "register_operand" "")))]
3287 "! rtx_equal_p (operands[0], operands[1])"
3288 [(set (match_dup 0) (neg:DI (match_dup 1)))
3289 (set (match_dup 0) (if_then_else:DI (lt (match_dup 1) (const_int 0))
3290 (match_dup 0) (match_dup 1)))]
3294 [(set (match_operand:DI 0 "register_operand" "")
3295 (neg:DI (abs:DI (match_dup 0))))
3296 (clobber (match_operand:DI 1 "register_operand" ""))]
3298 [(set (match_dup 1) (neg:DI (match_dup 0)))
3299 (set (match_dup 0) (if_then_else:DI (le (match_dup 0) (const_int 0))
3300 (match_dup 0) (match_dup 1)))]
3304 [(set (match_operand:DI 0 "register_operand" "")
3305 (neg:DI (abs:DI (match_operand:DI 1 "register_operand" ""))))]
3306 "! rtx_equal_p (operands[0], operands[1])"
3307 [(set (match_dup 0) (neg:DI (match_dup 1)))
3308 (set (match_dup 0) (if_then_else:DI (gt (match_dup 1) (const_int 0))
3309 (match_dup 0) (match_dup 1)))]
3312 (define_insn "sminqi3"
3313 [(set (match_operand:QI 0 "register_operand" "=r")
3314 (smin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3315 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3318 [(set_attr "type" "mvi")])
3320 (define_insn "uminqi3"
3321 [(set (match_operand:QI 0 "register_operand" "=r")
3322 (umin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3323 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3326 [(set_attr "type" "mvi")])
3328 (define_insn "smaxqi3"
3329 [(set (match_operand:QI 0 "register_operand" "=r")
3330 (smax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3331 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3334 [(set_attr "type" "mvi")])
3336 (define_insn "umaxqi3"
3337 [(set (match_operand:QI 0 "register_operand" "=r")
3338 (umax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3339 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3342 [(set_attr "type" "mvi")])
3344 (define_insn "sminhi3"
3345 [(set (match_operand:HI 0 "register_operand" "=r")
3346 (smin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3347 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3350 [(set_attr "type" "mvi")])
3352 (define_insn "uminhi3"
3353 [(set (match_operand:HI 0 "register_operand" "=r")
3354 (umin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3355 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3358 [(set_attr "type" "mvi")])
3360 (define_insn "smaxhi3"
3361 [(set (match_operand:HI 0 "register_operand" "=r")
3362 (smax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3363 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3366 [(set_attr "type" "mvi")])
3368 (define_insn "umaxhi3"
3369 [(set (match_operand:HI 0 "register_operand" "=r")
3370 (umax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3371 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3374 [(set_attr "type" "mvi")])
3376 (define_expand "smaxdi3"
3378 (le:DI (match_operand:DI 1 "reg_or_0_operand" "")
3379 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3380 (set (match_operand:DI 0 "register_operand" "")
3381 (if_then_else:DI (eq (match_dup 3) (const_int 0))
3382 (match_dup 1) (match_dup 2)))]
3384 { operands[3] = gen_reg_rtx (DImode); })
3387 [(set (match_operand:DI 0 "register_operand" "")
3388 (smax:DI (match_operand:DI 1 "reg_or_0_operand" "")
3389 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3390 (clobber (match_operand:DI 3 "register_operand" ""))]
3391 "operands[2] != const0_rtx"
3392 [(set (match_dup 3) (le:DI (match_dup 1) (match_dup 2)))
3393 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
3394 (match_dup 1) (match_dup 2)))]
3397 (define_insn "*smax_const0"
3398 [(set (match_operand:DI 0 "register_operand" "=r")
3399 (smax:DI (match_operand:DI 1 "register_operand" "0")
3403 [(set_attr "type" "icmov")])
3405 (define_expand "smindi3"
3407 (lt:DI (match_operand:DI 1 "reg_or_0_operand" "")
3408 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3409 (set (match_operand:DI 0 "register_operand" "")
3410 (if_then_else:DI (ne (match_dup 3) (const_int 0))
3411 (match_dup 1) (match_dup 2)))]
3413 { operands[3] = gen_reg_rtx (DImode); })
3416 [(set (match_operand:DI 0 "register_operand" "")
3417 (smin:DI (match_operand:DI 1 "reg_or_0_operand" "")
3418 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3419 (clobber (match_operand:DI 3 "register_operand" ""))]
3420 "operands[2] != const0_rtx"
3421 [(set (match_dup 3) (lt:DI (match_dup 1) (match_dup 2)))
3422 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
3423 (match_dup 1) (match_dup 2)))]
3426 (define_insn "*smin_const0"
3427 [(set (match_operand:DI 0 "register_operand" "=r")
3428 (smin:DI (match_operand:DI 1 "register_operand" "0")
3432 [(set_attr "type" "icmov")])
3434 (define_expand "umaxdi3"
3436 (leu:DI (match_operand:DI 1 "reg_or_0_operand" "")
3437 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3438 (set (match_operand:DI 0 "register_operand" "")
3439 (if_then_else:DI (eq (match_dup 3) (const_int 0))
3440 (match_dup 1) (match_dup 2)))]
3442 "operands[3] = gen_reg_rtx (DImode);")
3445 [(set (match_operand:DI 0 "register_operand" "")
3446 (umax:DI (match_operand:DI 1 "reg_or_0_operand" "")
3447 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3448 (clobber (match_operand:DI 3 "register_operand" ""))]
3449 "operands[2] != const0_rtx"
3450 [(set (match_dup 3) (leu:DI (match_dup 1) (match_dup 2)))
3451 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
3452 (match_dup 1) (match_dup 2)))]
3455 (define_expand "umindi3"
3457 (ltu:DI (match_operand:DI 1 "reg_or_0_operand" "")
3458 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3459 (set (match_operand:DI 0 "register_operand" "")
3460 (if_then_else:DI (ne (match_dup 3) (const_int 0))
3461 (match_dup 1) (match_dup 2)))]
3463 "operands[3] = gen_reg_rtx (DImode);")
3466 [(set (match_operand:DI 0 "register_operand" "")
3467 (umin:DI (match_operand:DI 1 "reg_or_0_operand" "")
3468 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3469 (clobber (match_operand:DI 3 "register_operand" ""))]
3470 "operands[2] != const0_rtx"
3471 [(set (match_dup 3) (ltu:DI (match_dup 1) (match_dup 2)))
3472 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
3473 (match_dup 1) (match_dup 2)))]
3476 (define_insn "*bcc_normal"
3479 (match_operator 1 "signed_comparison_operator"
3480 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
3482 (label_ref (match_operand 0 "" ""))
3486 [(set_attr "type" "ibr")])
3488 (define_insn "*bcc_reverse"
3491 (match_operator 1 "signed_comparison_operator"
3492 [(match_operand:DI 2 "register_operand" "r")
3496 (label_ref (match_operand 0 "" ""))))]
3499 [(set_attr "type" "ibr")])
3501 (define_insn "*blbs_normal"
3504 (ne (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
3508 (label_ref (match_operand 0 "" ""))
3512 [(set_attr "type" "ibr")])
3514 (define_insn "*blbc_normal"
3517 (eq (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
3521 (label_ref (match_operand 0 "" ""))
3525 [(set_attr "type" "ibr")])
3531 (match_operator 1 "comparison_operator"
3532 [(zero_extract:DI (match_operand:DI 2 "register_operand" "")
3534 (match_operand:DI 3 "const_int_operand" ""))
3536 (label_ref (match_operand 0 "" ""))
3538 (clobber (match_operand:DI 4 "register_operand" ""))])]
3539 "INTVAL (operands[3]) != 0"
3541 (lshiftrt:DI (match_dup 2) (match_dup 3)))
3543 (if_then_else (match_op_dup 1
3544 [(zero_extract:DI (match_dup 4)
3548 (label_ref (match_dup 0))
3552 ;; The following are the corresponding floating-point insns. Recall
3553 ;; we need to have variants that expand the arguments from SFmode
3556 (define_insn "*cmpdf_ieee"
3557 [(set (match_operand:DF 0 "register_operand" "=&f")
3558 (match_operator:DF 1 "alpha_fp_comparison_operator"
3559 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3560 (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
3561 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3562 "cmp%-%C1%/ %R2,%R3,%0"
3563 [(set_attr "type" "fadd")
3564 (set_attr "trap" "yes")
3565 (set_attr "trap_suffix" "su")])
3567 (define_insn "*cmpdf_internal"
3568 [(set (match_operand:DF 0 "register_operand" "=f")
3569 (match_operator:DF 1 "alpha_fp_comparison_operator"
3570 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3571 (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
3572 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3573 "cmp%-%C1%/ %R2,%R3,%0"
3574 [(set_attr "type" "fadd")
3575 (set_attr "trap" "yes")
3576 (set_attr "trap_suffix" "su")])
3578 (define_insn "*cmpdf_ieee_ext1"
3579 [(set (match_operand:DF 0 "register_operand" "=&f")
3580 (match_operator:DF 1 "alpha_fp_comparison_operator"
3582 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3583 (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
3584 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3585 "cmp%-%C1%/ %R2,%R3,%0"
3586 [(set_attr "type" "fadd")
3587 (set_attr "trap" "yes")
3588 (set_attr "trap_suffix" "su")])
3590 (define_insn "*cmpdf_ext1"
3591 [(set (match_operand:DF 0 "register_operand" "=f")
3592 (match_operator:DF 1 "alpha_fp_comparison_operator"
3594 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3595 (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
3596 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3597 "cmp%-%C1%/ %R2,%R3,%0"
3598 [(set_attr "type" "fadd")
3599 (set_attr "trap" "yes")
3600 (set_attr "trap_suffix" "su")])
3602 (define_insn "*cmpdf_ieee_ext2"
3603 [(set (match_operand:DF 0 "register_operand" "=&f")
3604 (match_operator:DF 1 "alpha_fp_comparison_operator"
3605 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3607 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
3608 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3609 "cmp%-%C1%/ %R2,%R3,%0"
3610 [(set_attr "type" "fadd")
3611 (set_attr "trap" "yes")
3612 (set_attr "trap_suffix" "su")])
3614 (define_insn "*cmpdf_ext2"
3615 [(set (match_operand:DF 0 "register_operand" "=f")
3616 (match_operator:DF 1 "alpha_fp_comparison_operator"
3617 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3619 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
3620 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3621 "cmp%-%C1%/ %R2,%R3,%0"
3622 [(set_attr "type" "fadd")
3623 (set_attr "trap" "yes")
3624 (set_attr "trap_suffix" "su")])
3626 (define_insn "*cmpdf_ieee_ext3"
3627 [(set (match_operand:DF 0 "register_operand" "=&f")
3628 (match_operator:DF 1 "alpha_fp_comparison_operator"
3630 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3632 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
3633 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3634 "cmp%-%C1%/ %R2,%R3,%0"
3635 [(set_attr "type" "fadd")
3636 (set_attr "trap" "yes")
3637 (set_attr "trap_suffix" "su")])
3639 (define_insn "*cmpdf_ext3"
3640 [(set (match_operand:DF 0 "register_operand" "=f")
3641 (match_operator:DF 1 "alpha_fp_comparison_operator"
3643 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3645 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
3646 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3647 "cmp%-%C1%/ %R2,%R3,%0"
3648 [(set_attr "type" "fadd")
3649 (set_attr "trap" "yes")
3650 (set_attr "trap_suffix" "su")])
3652 (define_insn "*movdfcc_internal"
3653 [(set (match_operand:DF 0 "register_operand" "=f,f")
3655 (match_operator 3 "signed_comparison_operator"
3656 [(match_operand:DF 4 "reg_or_0_operand" "fG,fG")
3657 (match_operand:DF 2 "const0_operand" "G,G")])
3658 (match_operand:DF 1 "reg_or_0_operand" "fG,0")
3659 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
3663 fcmov%D3 %R4,%R5,%0"
3664 [(set_attr "type" "fcmov")])
3666 (define_insn "*movsfcc_internal"
3667 [(set (match_operand:SF 0 "register_operand" "=f,f")
3669 (match_operator 3 "signed_comparison_operator"
3670 [(match_operand:DF 4 "reg_or_0_operand" "fG,fG")
3671 (match_operand:DF 2 "const0_operand" "G,G")])
3672 (match_operand:SF 1 "reg_or_0_operand" "fG,0")
3673 (match_operand:SF 5 "reg_or_0_operand" "0,fG")))]
3677 fcmov%D3 %R4,%R5,%0"
3678 [(set_attr "type" "fcmov")])
3680 (define_insn "*movdfcc_ext1"
3681 [(set (match_operand:DF 0 "register_operand" "=f,f")
3683 (match_operator 3 "signed_comparison_operator"
3684 [(match_operand:DF 4 "reg_or_0_operand" "fG,fG")
3685 (match_operand:DF 2 "const0_operand" "G,G")])
3686 (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0"))
3687 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
3691 fcmov%D3 %R4,%R5,%0"
3692 [(set_attr "type" "fcmov")])
3694 (define_insn "*movdfcc_ext2"
3695 [(set (match_operand:DF 0 "register_operand" "=f,f")
3697 (match_operator 3 "signed_comparison_operator"
3699 (match_operand:SF 4 "reg_or_0_operand" "fG,fG"))
3700 (match_operand:DF 2 "const0_operand" "G,G")])
3701 (match_operand:DF 1 "reg_or_0_operand" "fG,0")
3702 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
3706 fcmov%D3 %R4,%R5,%0"
3707 [(set_attr "type" "fcmov")])
3709 (define_insn "*movdfcc_ext3"
3710 [(set (match_operand:SF 0 "register_operand" "=f,f")
3712 (match_operator 3 "signed_comparison_operator"
3714 (match_operand:SF 4 "reg_or_0_operand" "fG,fG"))
3715 (match_operand:DF 2 "const0_operand" "G,G")])
3716 (match_operand:SF 1 "reg_or_0_operand" "fG,0")
3717 (match_operand:SF 5 "reg_or_0_operand" "0,fG")))]
3721 fcmov%D3 %R4,%R5,%0"
3722 [(set_attr "type" "fcmov")])
3724 (define_insn "*movdfcc_ext4"
3725 [(set (match_operand:DF 0 "register_operand" "=f,f")
3727 (match_operator 3 "signed_comparison_operator"
3729 (match_operand:SF 4 "reg_or_0_operand" "fG,fG"))
3730 (match_operand:DF 2 "const0_operand" "G,G")])
3731 (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0"))
3732 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
3736 fcmov%D3 %R4,%R5,%0"
3737 [(set_attr "type" "fcmov")])
3739 (define_expand "maxdf3"
3741 (le:DF (match_operand:DF 1 "reg_or_0_operand" "")
3742 (match_operand:DF 2 "reg_or_0_operand" "")))
3743 (set (match_operand:DF 0 "register_operand" "")
3744 (if_then_else:DF (eq (match_dup 3) (match_dup 4))
3745 (match_dup 1) (match_dup 2)))]
3748 operands[3] = gen_reg_rtx (DFmode);
3749 operands[4] = CONST0_RTX (DFmode);
3752 (define_expand "mindf3"
3754 (lt:DF (match_operand:DF 1 "reg_or_0_operand" "")
3755 (match_operand:DF 2 "reg_or_0_operand" "")))
3756 (set (match_operand:DF 0 "register_operand" "")
3757 (if_then_else:DF (ne (match_dup 3) (match_dup 4))
3758 (match_dup 1) (match_dup 2)))]
3761 operands[3] = gen_reg_rtx (DFmode);
3762 operands[4] = CONST0_RTX (DFmode);
3765 (define_expand "maxsf3"
3767 (le:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))
3768 (float_extend:DF (match_operand:SF 2 "reg_or_0_operand" ""))))
3769 (set (match_operand:SF 0 "register_operand" "")
3770 (if_then_else:SF (eq (match_dup 3) (match_dup 4))
3771 (match_dup 1) (match_dup 2)))]
3774 operands[3] = gen_reg_rtx (DFmode);
3775 operands[4] = CONST0_RTX (DFmode);
3778 (define_expand "minsf3"
3780 (lt:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))
3781 (float_extend:DF (match_operand:SF 2 "reg_or_0_operand" ""))))
3782 (set (match_operand:SF 0 "register_operand" "")
3783 (if_then_else:SF (ne (match_dup 3) (match_dup 4))
3784 (match_dup 1) (match_dup 2)))]
3787 operands[3] = gen_reg_rtx (DFmode);
3788 operands[4] = CONST0_RTX (DFmode);
3791 (define_insn "*fbcc_normal"
3794 (match_operator 1 "signed_comparison_operator"
3795 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3796 (match_operand:DF 3 "const0_operand" "G")])
3797 (label_ref (match_operand 0 "" ""))
3801 [(set_attr "type" "fbr")])
3803 (define_insn "*fbcc_ext_normal"
3806 (match_operator 1 "signed_comparison_operator"
3808 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3809 (match_operand:DF 3 "const0_operand" "G")])
3810 (label_ref (match_operand 0 "" ""))
3814 [(set_attr "type" "fbr")])
3816 ;; These are the main define_expand's used to make conditional branches
3819 (define_expand "cmpdf"
3820 [(set (cc0) (compare (match_operand:DF 0 "reg_or_0_operand" "")
3821 (match_operand:DF 1 "reg_or_0_operand" "")))]
3824 alpha_compare.op0 = operands[0];
3825 alpha_compare.op1 = operands[1];
3826 alpha_compare.fp_p = 1;
3830 (define_expand "cmptf"
3831 [(set (cc0) (compare (match_operand:TF 0 "general_operand" "")
3832 (match_operand:TF 1 "general_operand" "")))]
3833 "TARGET_HAS_XFLOATING_LIBS"
3835 alpha_compare.op0 = operands[0];
3836 alpha_compare.op1 = operands[1];
3837 alpha_compare.fp_p = 1;
3841 (define_expand "cmpdi"
3842 [(set (cc0) (compare (match_operand:DI 0 "some_operand" "")
3843 (match_operand:DI 1 "some_operand" "")))]
3846 alpha_compare.op0 = operands[0];
3847 alpha_compare.op1 = operands[1];
3848 alpha_compare.fp_p = 0;
3852 (define_expand "beq"
3854 (if_then_else (match_dup 1)
3855 (label_ref (match_operand 0 "" ""))
3858 "{ operands[1] = alpha_emit_conditional_branch (EQ); }")
3860 (define_expand "bne"
3862 (if_then_else (match_dup 1)
3863 (label_ref (match_operand 0 "" ""))
3866 "{ operands[1] = alpha_emit_conditional_branch (NE); }")
3868 (define_expand "blt"
3870 (if_then_else (match_dup 1)
3871 (label_ref (match_operand 0 "" ""))
3874 "{ operands[1] = alpha_emit_conditional_branch (LT); }")
3876 (define_expand "ble"
3878 (if_then_else (match_dup 1)
3879 (label_ref (match_operand 0 "" ""))
3882 "{ operands[1] = alpha_emit_conditional_branch (LE); }")
3884 (define_expand "bgt"
3886 (if_then_else (match_dup 1)
3887 (label_ref (match_operand 0 "" ""))
3890 "{ operands[1] = alpha_emit_conditional_branch (GT); }")
3892 (define_expand "bge"
3894 (if_then_else (match_dup 1)
3895 (label_ref (match_operand 0 "" ""))
3898 "{ operands[1] = alpha_emit_conditional_branch (GE); }")
3900 (define_expand "bltu"
3902 (if_then_else (match_dup 1)
3903 (label_ref (match_operand 0 "" ""))
3906 "{ operands[1] = alpha_emit_conditional_branch (LTU); }")
3908 (define_expand "bleu"
3910 (if_then_else (match_dup 1)
3911 (label_ref (match_operand 0 "" ""))
3914 "{ operands[1] = alpha_emit_conditional_branch (LEU); }")
3916 (define_expand "bgtu"
3918 (if_then_else (match_dup 1)
3919 (label_ref (match_operand 0 "" ""))
3922 "{ operands[1] = alpha_emit_conditional_branch (GTU); }")
3924 (define_expand "bgeu"
3926 (if_then_else (match_dup 1)
3927 (label_ref (match_operand 0 "" ""))
3930 "{ operands[1] = alpha_emit_conditional_branch (GEU); }")
3932 (define_expand "bunordered"
3934 (if_then_else (match_dup 1)
3935 (label_ref (match_operand 0 "" ""))
3938 "{ operands[1] = alpha_emit_conditional_branch (UNORDERED); }")
3940 (define_expand "bordered"
3942 (if_then_else (match_dup 1)
3943 (label_ref (match_operand 0 "" ""))
3946 "{ operands[1] = alpha_emit_conditional_branch (ORDERED); }")
3948 (define_expand "seq"
3949 [(set (match_operand:DI 0 "register_operand" "")
3952 "{ if ((operands[1] = alpha_emit_setcc (EQ)) == NULL_RTX) FAIL; }")
3954 (define_expand "sne"
3955 [(set (match_operand:DI 0 "register_operand" "")
3958 "{ if ((operands[1] = alpha_emit_setcc (NE)) == NULL_RTX) FAIL; }")
3960 (define_expand "slt"
3961 [(set (match_operand:DI 0 "register_operand" "")
3964 "{ if ((operands[1] = alpha_emit_setcc (LT)) == NULL_RTX) FAIL; }")
3966 (define_expand "sle"
3967 [(set (match_operand:DI 0 "register_operand" "")
3970 "{ if ((operands[1] = alpha_emit_setcc (LE)) == NULL_RTX) FAIL; }")
3972 (define_expand "sgt"
3973 [(set (match_operand:DI 0 "register_operand" "")
3976 "{ if ((operands[1] = alpha_emit_setcc (GT)) == NULL_RTX) FAIL; }")
3978 (define_expand "sge"
3979 [(set (match_operand:DI 0 "register_operand" "")
3982 "{ if ((operands[1] = alpha_emit_setcc (GE)) == NULL_RTX) FAIL; }")
3984 (define_expand "sltu"
3985 [(set (match_operand:DI 0 "register_operand" "")
3988 "{ if ((operands[1] = alpha_emit_setcc (LTU)) == NULL_RTX) FAIL; }")
3990 (define_expand "sleu"
3991 [(set (match_operand:DI 0 "register_operand" "")
3994 "{ if ((operands[1] = alpha_emit_setcc (LEU)) == NULL_RTX) FAIL; }")
3996 (define_expand "sgtu"
3997 [(set (match_operand:DI 0 "register_operand" "")
4000 "{ if ((operands[1] = alpha_emit_setcc (GTU)) == NULL_RTX) FAIL; }")
4002 (define_expand "sgeu"
4003 [(set (match_operand:DI 0 "register_operand" "")
4006 "{ if ((operands[1] = alpha_emit_setcc (GEU)) == NULL_RTX) FAIL; }")
4008 (define_expand "sunordered"
4009 [(set (match_operand:DI 0 "register_operand" "")
4012 "{ if ((operands[1] = alpha_emit_setcc (UNORDERED)) == NULL_RTX) FAIL; }")
4014 (define_expand "sordered"
4015 [(set (match_operand:DI 0 "register_operand" "")
4018 "{ if ((operands[1] = alpha_emit_setcc (ORDERED)) == NULL_RTX) FAIL; }")
4020 ;; These are the main define_expand's used to make conditional moves.
4022 (define_expand "movsicc"
4023 [(set (match_operand:SI 0 "register_operand" "")
4024 (if_then_else:SI (match_operand 1 "comparison_operator" "")
4025 (match_operand:SI 2 "reg_or_8bit_operand" "")
4026 (match_operand:SI 3 "reg_or_8bit_operand" "")))]
4029 if ((operands[1] = alpha_emit_conditional_move (operands[1], SImode)) == 0)
4033 (define_expand "movdicc"
4034 [(set (match_operand:DI 0 "register_operand" "")
4035 (if_then_else:DI (match_operand 1 "comparison_operator" "")
4036 (match_operand:DI 2 "reg_or_8bit_operand" "")
4037 (match_operand:DI 3 "reg_or_8bit_operand" "")))]
4040 if ((operands[1] = alpha_emit_conditional_move (operands[1], DImode)) == 0)
4044 (define_expand "movsfcc"
4045 [(set (match_operand:SF 0 "register_operand" "")
4046 (if_then_else:SF (match_operand 1 "comparison_operator" "")
4047 (match_operand:SF 2 "reg_or_8bit_operand" "")
4048 (match_operand:SF 3 "reg_or_8bit_operand" "")))]
4051 if ((operands[1] = alpha_emit_conditional_move (operands[1], SFmode)) == 0)
4055 (define_expand "movdfcc"
4056 [(set (match_operand:DF 0 "register_operand" "")
4057 (if_then_else:DF (match_operand 1 "comparison_operator" "")
4058 (match_operand:DF 2 "reg_or_8bit_operand" "")
4059 (match_operand:DF 3 "reg_or_8bit_operand" "")))]
4062 if ((operands[1] = alpha_emit_conditional_move (operands[1], DFmode)) == 0)
4066 ;; These define_split definitions are used in cases when comparisons have
4067 ;; not be stated in the correct way and we need to reverse the second
4068 ;; comparison. For example, x >= 7 has to be done as x < 6 with the
4069 ;; comparison that tests the result being reversed. We have one define_split
4070 ;; for each use of a comparison. They do not match valid insns and need
4071 ;; not generate valid insns.
4073 ;; We can also handle equality comparisons (and inequality comparisons in
4074 ;; cases where the resulting add cannot overflow) by doing an add followed by
4075 ;; a comparison with zero. This is faster since the addition takes one
4076 ;; less cycle than a compare when feeding into a conditional move.
4077 ;; For this case, we also have an SImode pattern since we can merge the add
4078 ;; and sign extend and the order doesn't matter.
4080 ;; We do not do this for floating-point, since it isn't clear how the "wrong"
4081 ;; operation could have been generated.
4084 [(set (match_operand:DI 0 "register_operand" "")
4086 (match_operator 1 "comparison_operator"
4087 [(match_operand:DI 2 "reg_or_0_operand" "")
4088 (match_operand:DI 3 "reg_or_cint_operand" "")])
4089 (match_operand:DI 4 "reg_or_cint_operand" "")
4090 (match_operand:DI 5 "reg_or_cint_operand" "")))
4091 (clobber (match_operand:DI 6 "register_operand" ""))]
4092 "operands[3] != const0_rtx"
4093 [(set (match_dup 6) (match_dup 7))
4095 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
4097 enum rtx_code code = GET_CODE (operands[1]);
4098 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
4100 /* If we are comparing for equality with a constant and that constant
4101 appears in the arm when the register equals the constant, use the
4102 register since that is more likely to match (and to produce better code
4105 if (code == EQ && GET_CODE (operands[3]) == CONST_INT
4106 && rtx_equal_p (operands[4], operands[3]))
4107 operands[4] = operands[2];
4109 else if (code == NE && GET_CODE (operands[3]) == CONST_INT
4110 && rtx_equal_p (operands[5], operands[3]))
4111 operands[5] = operands[2];
4113 if (code == NE || code == EQ
4114 || (extended_count (operands[2], DImode, unsignedp) >= 1
4115 && extended_count (operands[3], DImode, unsignedp) >= 1))
4117 if (GET_CODE (operands[3]) == CONST_INT)
4118 operands[7] = gen_rtx_PLUS (DImode, operands[2],
4119 GEN_INT (- INTVAL (operands[3])));
4121 operands[7] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
4123 operands[8] = gen_rtx_fmt_ee (code, VOIDmode, operands[6], const0_rtx);
4126 else if (code == EQ || code == LE || code == LT
4127 || code == LEU || code == LTU)
4129 operands[7] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
4130 operands[8] = gen_rtx_NE (VOIDmode, operands[6], const0_rtx);
4134 operands[7] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
4135 operands[2], operands[3]);
4136 operands[8] = gen_rtx_EQ (VOIDmode, operands[6], const0_rtx);
4141 [(set (match_operand:DI 0 "register_operand" "")
4143 (match_operator 1 "comparison_operator"
4144 [(match_operand:SI 2 "reg_or_0_operand" "")
4145 (match_operand:SI 3 "reg_or_cint_operand" "")])
4146 (match_operand:DI 4 "reg_or_8bit_operand" "")
4147 (match_operand:DI 5 "reg_or_8bit_operand" "")))
4148 (clobber (match_operand:DI 6 "register_operand" ""))]
4149 "operands[3] != const0_rtx
4150 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
4151 [(set (match_dup 6) (match_dup 7))
4153 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
4155 enum rtx_code code = GET_CODE (operands[1]);
4156 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
4159 if ((code != NE && code != EQ
4160 && ! (extended_count (operands[2], DImode, unsignedp) >= 1
4161 && extended_count (operands[3], DImode, unsignedp) >= 1)))
4164 if (GET_CODE (operands[3]) == CONST_INT)
4165 tem = gen_rtx_PLUS (SImode, operands[2],
4166 GEN_INT (- INTVAL (operands[3])));
4168 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
4170 operands[7] = gen_rtx_SIGN_EXTEND (DImode, tem);
4171 operands[8] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
4172 operands[6], const0_rtx);
4175 ;; Prefer to use cmp and arithmetic when possible instead of a cmove.
4178 [(set (match_operand 0 "register_operand" "")
4179 (if_then_else (match_operator 1 "signed_comparison_operator"
4180 [(match_operand:DI 2 "reg_or_0_operand" "")
4182 (match_operand 3 "const_int_operand" "")
4183 (match_operand 4 "const_int_operand" "")))]
4187 if (alpha_split_conditional_move (GET_CODE (operands[1]), operands[0],
4188 operands[2], operands[3], operands[4]))
4194 ;; ??? Why combine is allowed to create such non-canonical rtl, I don't know.
4195 ;; Oh well, we match it in movcc, so it must be partially our fault.
4197 [(set (match_operand 0 "register_operand" "")
4198 (if_then_else (match_operator 1 "signed_comparison_operator"
4200 (match_operand:DI 2 "reg_or_0_operand" "")])
4201 (match_operand 3 "const_int_operand" "")
4202 (match_operand 4 "const_int_operand" "")))]
4206 if (alpha_split_conditional_move (swap_condition (GET_CODE (operands[1])),
4207 operands[0], operands[2], operands[3],
4214 (define_insn_and_split "*cmp_sadd_di"
4215 [(set (match_operand:DI 0 "register_operand" "=r")
4216 (plus:DI (if_then_else:DI
4217 (match_operator 1 "alpha_zero_comparison_operator"
4218 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4220 (match_operand:DI 3 "const48_operand" "I")
4222 (match_operand:DI 4 "sext_add_operand" "rIO")))
4223 (clobber (match_scratch:DI 5 "=r"))]
4226 "! no_new_pseudos || reload_completed"
4228 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
4230 (plus:DI (mult:DI (match_dup 5) (match_dup 3))
4233 if (! no_new_pseudos)
4234 operands[5] = gen_reg_rtx (DImode);
4235 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4236 operands[5] = operands[0];
4239 (define_insn_and_split "*cmp_sadd_si"
4240 [(set (match_operand:SI 0 "register_operand" "=r")
4241 (plus:SI (if_then_else:SI
4242 (match_operator 1 "alpha_zero_comparison_operator"
4243 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4245 (match_operand:SI 3 "const48_operand" "I")
4247 (match_operand:SI 4 "sext_add_operand" "rIO")))
4248 (clobber (match_scratch:SI 5 "=r"))]
4251 "! no_new_pseudos || reload_completed"
4253 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4255 (plus:SI (mult:SI (match_dup 5) (match_dup 3))
4258 if (! no_new_pseudos)
4259 operands[5] = gen_reg_rtx (DImode);
4260 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4261 operands[5] = operands[0];
4264 (define_insn_and_split "*cmp_sadd_sidi"
4265 [(set (match_operand:DI 0 "register_operand" "=r")
4267 (plus:SI (if_then_else:SI
4268 (match_operator 1 "alpha_zero_comparison_operator"
4269 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4271 (match_operand:SI 3 "const48_operand" "I")
4273 (match_operand:SI 4 "sext_add_operand" "rIO"))))
4274 (clobber (match_scratch:SI 5 "=r"))]
4277 "! no_new_pseudos || reload_completed"
4279 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4281 (sign_extend:DI (plus:SI (mult:SI (match_dup 5) (match_dup 3))
4284 if (! no_new_pseudos)
4285 operands[5] = gen_reg_rtx (DImode);
4286 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4287 operands[5] = operands[0];
4290 (define_insn_and_split "*cmp_ssub_di"
4291 [(set (match_operand:DI 0 "register_operand" "=r")
4292 (minus:DI (if_then_else:DI
4293 (match_operator 1 "alpha_zero_comparison_operator"
4294 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4296 (match_operand:DI 3 "const48_operand" "I")
4298 (match_operand:DI 4 "reg_or_8bit_operand" "rI")))
4299 (clobber (match_scratch:DI 5 "=r"))]
4302 "! no_new_pseudos || reload_completed"
4304 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
4306 (minus:DI (mult:DI (match_dup 5) (match_dup 3))
4309 if (! no_new_pseudos)
4310 operands[5] = gen_reg_rtx (DImode);
4311 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4312 operands[5] = operands[0];
4315 (define_insn_and_split "*cmp_ssub_si"
4316 [(set (match_operand:SI 0 "register_operand" "=r")
4317 (minus:SI (if_then_else:SI
4318 (match_operator 1 "alpha_zero_comparison_operator"
4319 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4321 (match_operand:SI 3 "const48_operand" "I")
4323 (match_operand:SI 4 "reg_or_8bit_operand" "rI")))
4324 (clobber (match_scratch:SI 5 "=r"))]
4327 "! no_new_pseudos || reload_completed"
4329 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4331 (minus:SI (mult:SI (match_dup 5) (match_dup 3))
4334 if (! no_new_pseudos)
4335 operands[5] = gen_reg_rtx (DImode);
4336 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4337 operands[5] = operands[0];
4340 (define_insn_and_split "*cmp_ssub_sidi"
4341 [(set (match_operand:DI 0 "register_operand" "=r")
4343 (minus:SI (if_then_else:SI
4344 (match_operator 1 "alpha_zero_comparison_operator"
4345 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4347 (match_operand:SI 3 "const48_operand" "I")
4349 (match_operand:SI 4 "reg_or_8bit_operand" "rI"))))
4350 (clobber (match_scratch:SI 5 "=r"))]
4353 "! no_new_pseudos || reload_completed"
4355 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4357 (sign_extend:DI (minus:SI (mult:SI (match_dup 5) (match_dup 3))
4360 if (! no_new_pseudos)
4361 operands[5] = gen_reg_rtx (DImode);
4362 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4363 operands[5] = operands[0];
4366 ;; Here are the CALL and unconditional branch insns. Calls on NT and OSF
4367 ;; work differently, so we have different patterns for each.
4369 ;; On Unicos/Mk a call information word (CIW) must be generated for each
4370 ;; call. The CIW contains information about arguments passed in registers
4371 ;; and is stored in the caller's SSIB. Its offset relative to the beginning
4372 ;; of the SSIB is passed in $25. Handling this properly is quite complicated
4373 ;; in the presence of inlining since the CIWs for calls performed by the
4374 ;; inlined function must be stored in the SSIB of the function it is inlined
4375 ;; into as well. We encode the CIW in an unspec and append it to the list
4376 ;; of the CIWs for the current function only when the instruction for loading
4377 ;; $25 is generated.
4379 (define_expand "call"
4380 [(use (match_operand:DI 0 "" ""))
4381 (use (match_operand 1 "" ""))
4382 (use (match_operand 2 "" ""))
4383 (use (match_operand 3 "" ""))]
4386 if (TARGET_ABI_WINDOWS_NT)
4387 emit_call_insn (gen_call_nt (operands[0], operands[1]));
4388 else if (TARGET_ABI_OPEN_VMS)
4389 emit_call_insn (gen_call_vms (operands[0], operands[2]));
4390 else if (TARGET_ABI_UNICOSMK)
4391 emit_call_insn (gen_call_umk (operands[0], operands[2]));
4393 emit_call_insn (gen_call_osf (operands[0], operands[1]));
4397 (define_expand "sibcall"
4398 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4399 (match_operand 1 "" ""))
4400 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)])]
4403 if (GET_CODE (operands[0]) != MEM)
4405 operands[0] = XEXP (operands[0], 0);
4408 (define_expand "call_osf"
4409 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4410 (match_operand 1 "" ""))
4412 (clobber (reg:DI 26))])]
4415 if (GET_CODE (operands[0]) != MEM)
4418 operands[0] = XEXP (operands[0], 0);
4419 if (! call_operand (operands[0], Pmode))
4420 operands[0] = copy_to_mode_reg (Pmode, operands[0]);
4423 (define_expand "call_nt"
4424 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4425 (match_operand 1 "" ""))
4426 (clobber (reg:DI 26))])]
4429 if (GET_CODE (operands[0]) != MEM)
4432 operands[0] = XEXP (operands[0], 0);
4433 if (GET_CODE (operands[0]) != SYMBOL_REF && GET_CODE (operands[0]) != REG)
4434 operands[0] = force_reg (DImode, operands[0]);
4437 ;; Calls on Unicos/Mk are always indirect.
4438 ;; op 0: symbol ref for called function
4439 ;; op 1: CIW for $25 represented by an unspec
4441 (define_expand "call_umk"
4442 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4443 (match_operand 1 "" ""))
4445 (clobber (reg:DI 26))])]
4448 if (GET_CODE (operands[0]) != MEM)
4451 /* Always load the address of the called function into a register;
4452 load the CIW in $25. */
4454 operands[0] = XEXP (operands[0], 0);
4455 if (GET_CODE (operands[0]) != REG)
4456 operands[0] = force_reg (DImode, operands[0]);
4458 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
4462 ;; call openvms/alpha
4463 ;; op 0: symbol ref for called function
4464 ;; op 1: next_arg_reg (argument information value for R25)
4466 (define_expand "call_vms"
4467 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4468 (match_operand 1 "" ""))
4472 (clobber (reg:DI 27))])]
4475 if (GET_CODE (operands[0]) != MEM)
4478 operands[0] = XEXP (operands[0], 0);
4480 /* Always load AI with argument information, then handle symbolic and
4481 indirect call differently. Load RA and set operands[2] to PV in
4484 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
4485 if (GET_CODE (operands[0]) == SYMBOL_REF)
4487 alpha_need_linkage (XSTR (operands[0], 0), 0);
4489 operands[2] = const0_rtx;
4493 emit_move_insn (gen_rtx_REG (Pmode, 26),
4494 gen_rtx_MEM (Pmode, plus_constant (operands[0], 8)));
4495 operands[2] = operands[0];
4500 (define_expand "call_value"
4501 [(use (match_operand 0 "" ""))
4502 (use (match_operand:DI 1 "" ""))
4503 (use (match_operand 2 "" ""))
4504 (use (match_operand 3 "" ""))
4505 (use (match_operand 4 "" ""))]
4508 if (TARGET_ABI_WINDOWS_NT)
4509 emit_call_insn (gen_call_value_nt (operands[0], operands[1], operands[2]));
4510 else if (TARGET_ABI_OPEN_VMS)
4511 emit_call_insn (gen_call_value_vms (operands[0], operands[1],
4513 else if (TARGET_ABI_UNICOSMK)
4514 emit_call_insn (gen_call_value_umk (operands[0], operands[1],
4517 emit_call_insn (gen_call_value_osf (operands[0], operands[1],
4522 (define_expand "sibcall_value"
4523 [(parallel [(set (match_operand 0 "" "")
4524 (call (mem:DI (match_operand 1 "" ""))
4525 (match_operand 2 "" "")))
4526 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)])]
4529 if (GET_CODE (operands[1]) != MEM)
4531 operands[1] = XEXP (operands[1], 0);
4534 (define_expand "call_value_osf"
4535 [(parallel [(set (match_operand 0 "" "")
4536 (call (mem:DI (match_operand 1 "" ""))
4537 (match_operand 2 "" "")))
4539 (clobber (reg:DI 26))])]
4542 if (GET_CODE (operands[1]) != MEM)
4545 operands[1] = XEXP (operands[1], 0);
4546 if (! call_operand (operands[1], Pmode))
4547 operands[1] = copy_to_mode_reg (Pmode, operands[1]);
4550 (define_expand "call_value_nt"
4551 [(parallel [(set (match_operand 0 "" "")
4552 (call (mem:DI (match_operand 1 "" ""))
4553 (match_operand 2 "" "")))
4554 (clobber (reg:DI 26))])]
4557 if (GET_CODE (operands[1]) != MEM)
4560 operands[1] = XEXP (operands[1], 0);
4561 if (GET_CODE (operands[1]) != SYMBOL_REF && GET_CODE (operands[1]) != REG)
4562 operands[1] = force_reg (DImode, operands[1]);
4565 (define_expand "call_value_vms"
4566 [(parallel [(set (match_operand 0 "" "")
4567 (call (mem:DI (match_operand:DI 1 "" ""))
4568 (match_operand 2 "" "")))
4572 (clobber (reg:DI 27))])]
4575 if (GET_CODE (operands[1]) != MEM)
4578 operands[1] = XEXP (operands[1], 0);
4580 /* Always load AI with argument information, then handle symbolic and
4581 indirect call differently. Load RA and set operands[3] to PV in
4584 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
4585 if (GET_CODE (operands[1]) == SYMBOL_REF)
4587 alpha_need_linkage (XSTR (operands[1], 0), 0);
4589 operands[3] = const0_rtx;
4593 emit_move_insn (gen_rtx_REG (Pmode, 26),
4594 gen_rtx_MEM (Pmode, plus_constant (operands[1], 8)));
4595 operands[3] = operands[1];
4599 (define_expand "call_value_umk"
4600 [(parallel [(set (match_operand 0 "" "")
4601 (call (mem:DI (match_operand 1 "" ""))
4602 (match_operand 2 "" "")))
4604 (clobber (reg:DI 26))])]
4607 if (GET_CODE (operands[1]) != MEM)
4610 operands[1] = XEXP (operands[1], 0);
4611 if (GET_CODE (operands[1]) != REG)
4612 operands[1] = force_reg (DImode, operands[1]);
4614 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
4617 (define_insn "*call_osf_1_er"
4618 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4619 (match_operand 1 "" ""))
4621 (clobber (reg:DI 26))]
4622 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4624 jsr $26,(%0),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*
4625 bsr $26,%0\t\t!samegp
4626 ldq $27,%0($29)\t\t!literal!%#\;jsr $26,($27),%0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*"
4627 [(set_attr "type" "jsr")
4628 (set_attr "length" "12,*,16")])
4630 ;; We must use peep2 instead of a split because we need accurate life
4631 ;; information for $gp. Consider the case of { bar(); while (1); }.
4633 [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand" ""))
4634 (match_operand 1 "" ""))
4636 (clobber (reg:DI 26))])]
4637 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
4638 && ! samegp_function_operand (operands[0], Pmode)
4639 && (peep2_regno_dead_p (1, 29)
4640 || find_reg_note (insn, REG_NORETURN, NULL_RTX))"
4641 [(parallel [(call (mem:DI (match_dup 2))
4643 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
4644 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
4646 (use (match_dup 3))])]
4648 if (CONSTANT_P (operands[0]))
4650 operands[2] = gen_rtx_REG (Pmode, 27);
4651 operands[3] = GEN_INT (alpha_next_sequence_number++);
4652 emit_insn (gen_movdi_er_high_g (operands[2], pic_offset_table_rtx,
4653 operands[0], operands[3]));
4657 operands[2] = operands[0];
4658 operands[0] = const0_rtx;
4659 operands[3] = const0_rtx;
4664 [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand" ""))
4665 (match_operand 1 "" ""))
4667 (clobber (reg:DI 26))])]
4668 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
4669 && ! samegp_function_operand (operands[0], Pmode)
4670 && ! (peep2_regno_dead_p (1, 29)
4671 || find_reg_note (insn, REG_NORETURN, NULL_RTX))"
4672 [(parallel [(call (mem:DI (match_dup 2))
4674 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
4675 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
4677 (use (match_dup 4))])
4679 (unspec_volatile:DI [(reg:DI 26) (match_dup 3)] UNSPECV_LDGP1))
4681 (unspec:DI [(reg:DI 29) (match_dup 3)] UNSPEC_LDGP2))]
4683 if (CONSTANT_P (operands[0]))
4685 operands[2] = gen_rtx_REG (Pmode, 27);
4686 operands[4] = GEN_INT (alpha_next_sequence_number++);
4687 emit_insn (gen_movdi_er_high_g (operands[2], pic_offset_table_rtx,
4688 operands[0], operands[4]));
4692 operands[2] = operands[0];
4693 operands[0] = const0_rtx;
4694 operands[4] = const0_rtx;
4696 operands[3] = GEN_INT (alpha_next_sequence_number++);
4699 ;; We add a blockage unspec_volatile to prevent insns from moving down
4700 ;; from above the call to in between the call and the ldah gpdisp.
4702 (define_insn "*call_osf_2_er"
4703 [(call (mem:DI (match_operand:DI 0 "register_operand" "c"))
4704 (match_operand 1 "" ""))
4705 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
4706 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
4707 (use (match_operand 2 "" ""))
4708 (use (match_operand 3 "const_int_operand" ""))]
4709 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4710 "jsr $26,(%0),%2%J3"
4711 [(set_attr "type" "jsr")
4712 (set_attr "cannot_copy" "true")])
4714 ;; We output a nop after noreturn calls at the very end of the function to
4715 ;; ensure that the return address always remains in the caller's code range,
4716 ;; as not doing so might confuse unwinding engines.
4718 ;; The potential change in insn length is not reflected in the length
4719 ;; attributes at this stage. Since the extra space is only actually added at
4720 ;; the very end of the compilation process (via final/print_operand), it
4721 ;; really seems harmless and not worth the trouble of some extra computation
4722 ;; cost and complexity.
4724 (define_insn "*call_osf_1_noreturn"
4725 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4726 (match_operand 1 "" ""))
4728 (clobber (reg:DI 26))]
4729 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
4730 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
4735 [(set_attr "type" "jsr")
4736 (set_attr "length" "*,*,8")])
4738 (define_insn "*call_osf_1"
4739 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4740 (match_operand 1 "" ""))
4742 (clobber (reg:DI 26))]
4743 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4745 jsr $26,($27),0\;ldgp $29,0($26)
4747 jsr $26,%0\;ldgp $29,0($26)"
4748 [(set_attr "type" "jsr")
4749 (set_attr "length" "12,*,16")])
4751 ;; Note that the DEC assembler expands "jmp foo" with $at, which
4752 ;; doesn't do what we want.
4753 (define_insn "*sibcall_osf_1_er"
4754 [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s"))
4755 (match_operand 1 "" ""))
4756 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
4757 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4759 br $31,%0\t\t!samegp
4760 ldq $27,%0($29)\t\t!literal!%#\;jmp $31,($27),%0\t\t!lituse_jsr!%#"
4761 [(set_attr "type" "jsr")
4762 (set_attr "length" "*,8")])
4764 (define_insn "*sibcall_osf_1"
4765 [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s"))
4766 (match_operand 1 "" ""))
4767 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
4768 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4771 lda $27,%0\;jmp $31,($27),%0"
4772 [(set_attr "type" "jsr")
4773 (set_attr "length" "*,8")])
4775 (define_insn "*call_nt_1"
4776 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,R,s"))
4777 (match_operand 1 "" ""))
4778 (clobber (reg:DI 26))]
4779 "TARGET_ABI_WINDOWS_NT"
4784 [(set_attr "type" "jsr")
4785 (set_attr "length" "*,*,12")])
4787 ; GAS relies on the order and position of instructions output below in order
4788 ; to generate relocs for VMS link to potentially optimize the call.
4789 ; Please do not molest.
4790 (define_insn "*call_vms_1"
4791 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,s"))
4792 (match_operand 1 "" ""))
4793 (use (match_operand:DI 2 "nonmemory_operand" "r,n"))
4796 (clobber (reg:DI 27))]
4797 "TARGET_ABI_OPEN_VMS"
4799 switch (which_alternative)
4802 return "mov %2,$27\;jsr $26,0\;ldq $27,0($29)";
4804 operands [2] = alpha_use_linkage (operands [0], cfun->decl, 1, 0);
4805 operands [3] = alpha_use_linkage (operands [0], cfun->decl, 0, 0);
4806 return "ldq $26,%3\;ldq $27,%2\;jsr $26,%0\;ldq $27,0($29)";
4811 [(set_attr "type" "jsr")
4812 (set_attr "length" "12,16")])
4814 (define_insn "*call_umk_1"
4815 [(call (mem:DI (match_operand:DI 0 "call_operand" "r"))
4816 (match_operand 1 "" ""))
4818 (clobber (reg:DI 26))]
4819 "TARGET_ABI_UNICOSMK"
4821 [(set_attr "type" "jsr")])
4823 ;; Call subroutine returning any type.
4825 (define_expand "untyped_call"
4826 [(parallel [(call (match_operand 0 "" "")
4828 (match_operand 1 "" "")
4829 (match_operand 2 "" "")])]
4834 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
4836 for (i = 0; i < XVECLEN (operands[2], 0); i++)
4838 rtx set = XVECEXP (operands[2], 0, i);
4839 emit_move_insn (SET_DEST (set), SET_SRC (set));
4842 /* The optimizer does not know that the call sets the function value
4843 registers we stored in the result block. We avoid problems by
4844 claiming that all hard registers are used and clobbered at this
4846 emit_insn (gen_blockage ());
4851 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
4852 ;; all of memory. This blocks insns from being moved across this point.
4854 (define_insn "blockage"
4855 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
4858 [(set_attr "length" "0")
4859 (set_attr "type" "none")])
4863 (label_ref (match_operand 0 "" "")))]
4866 [(set_attr "type" "ibr")])
4868 (define_expand "return"
4873 (define_insn "*return_internal"
4877 [(set_attr "type" "ibr")])
4879 (define_insn "indirect_jump"
4880 [(set (pc) (match_operand:DI 0 "register_operand" "r"))]
4883 [(set_attr "type" "ibr")])
4885 (define_expand "tablejump"
4886 [(parallel [(set (pc)
4887 (match_operand 0 "register_operand" ""))
4888 (use (label_ref:DI (match_operand 1 "" "")))])]
4891 if (TARGET_ABI_WINDOWS_NT)
4893 rtx dest = gen_reg_rtx (DImode);
4894 emit_insn (gen_extendsidi2 (dest, operands[0]));
4897 else if (TARGET_ABI_OSF)
4899 rtx dest = gen_reg_rtx (DImode);
4900 emit_insn (gen_extendsidi2 (dest, operands[0]));
4901 emit_insn (gen_adddi3 (dest, pic_offset_table_rtx, dest));
4906 (define_insn "*tablejump_osf_nt_internal"
4908 (match_operand:DI 0 "register_operand" "r"))
4909 (use (label_ref:DI (match_operand 1 "" "")))]
4910 "(TARGET_ABI_OSF || TARGET_ABI_WINDOWS_NT)
4911 && alpha_tablejump_addr_vec (insn)"
4913 operands[2] = alpha_tablejump_best_label (insn);
4914 return "jmp $31,(%0),%2";
4916 [(set_attr "type" "ibr")])
4918 (define_insn "*tablejump_internal"
4920 (match_operand:DI 0 "register_operand" "r"))
4921 (use (label_ref (match_operand 1 "" "")))]
4924 [(set_attr "type" "ibr")])
4926 ;; Cache flush. Used by INITIALIZE_TRAMPOLINE. 0x86 is PAL_imb, but we don't
4927 ;; want to have to include pal.h in our .s file.
4929 ;; Technically the type for call_pal is jsr, but we use that for determining
4930 ;; if we need a GP. Use ibr instead since it has the same EV5 scheduling
4933 [(unspec_volatile [(const_int 0)] UNSPECV_IMB)]
4936 [(set_attr "type" "callpal")])
4938 ;; BUGCHK is documented common to OSF/1 and VMS PALcode.
4939 ;; NT does not document anything at 0x81 -- presumably it would generate
4940 ;; the equivalent of SIGILL, but this isn't that important.
4941 ;; ??? Presuming unicosmk uses either OSF/1 or VMS PALcode.
4943 [(trap_if (const_int 1) (const_int 0))]
4944 "!TARGET_ABI_WINDOWS_NT"
4946 [(set_attr "type" "callpal")])
4948 ;; For userland, we load the thread pointer from the TCB.
4949 ;; For the kernel, we load the per-cpu private value.
4951 (define_insn "load_tp"
4952 [(set (match_operand:DI 0 "register_operand" "=v")
4953 (unspec:DI [(const_int 0)] UNSPEC_TP))]
4956 if (TARGET_TLS_KERNEL)
4957 return "call_pal 0x32";
4959 return "call_pal 0x9e";
4961 [(set_attr "type" "callpal")])
4963 ;; For completeness, and possibly a __builtin function, here's how to
4964 ;; set the thread pointer. Since we don't describe enough of this
4965 ;; quantity for CSE, we have to use a volatile unspec, and then there's
4966 ;; not much point in creating an R16_REG register class.
4968 (define_expand "set_tp"
4969 [(set (reg:DI 16) (match_operand:DI 0 "input_operand" ""))
4970 (unspec_volatile [(reg:DI 16)] UNSPECV_SET_TP)]
4974 (define_insn "*set_tp"
4975 [(unspec_volatile [(reg:DI 16)] UNSPECV_SET_TP)]
4978 if (TARGET_TLS_KERNEL)
4979 return "call_pal 0x31";
4981 return "call_pal 0x9f";
4983 [(set_attr "type" "callpal")])
4985 ;; Finally, we have the basic data motion insns. The byte and word insns
4986 ;; are done via define_expand. Start with the floating-point insns, since
4987 ;; they are simpler.
4989 (define_insn "*movsf_nofix"
4990 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
4991 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
4992 "TARGET_FPREGS && ! TARGET_FIX
4993 && (register_operand (operands[0], SFmode)
4994 || reg_or_0_operand (operands[1], SFmode))"
5002 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
5004 (define_insn "*movsf_fix"
5005 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
5006 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
5007 "TARGET_FPREGS && TARGET_FIX
5008 && (register_operand (operands[0], SFmode)
5009 || reg_or_0_operand (operands[1], SFmode))"
5019 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
5021 (define_insn "*movsf_nofp"
5022 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m")
5023 (match_operand:SF 1 "input_operand" "rG,m,r"))]
5025 && (register_operand (operands[0], SFmode)
5026 || reg_or_0_operand (operands[1], SFmode))"
5031 [(set_attr "type" "ilog,ild,ist")])
5033 (define_insn "*movdf_nofix"
5034 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
5035 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
5036 "TARGET_FPREGS && ! TARGET_FIX
5037 && (register_operand (operands[0], DFmode)
5038 || reg_or_0_operand (operands[1], DFmode))"
5046 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
5048 (define_insn "*movdf_fix"
5049 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
5050 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
5051 "TARGET_FPREGS && TARGET_FIX
5052 && (register_operand (operands[0], DFmode)
5053 || reg_or_0_operand (operands[1], DFmode))"
5063 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
5065 (define_insn "*movdf_nofp"
5066 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m")
5067 (match_operand:DF 1 "input_operand" "rG,m,r"))]
5069 && (register_operand (operands[0], DFmode)
5070 || reg_or_0_operand (operands[1], DFmode))"
5075 [(set_attr "type" "ilog,ild,ist")])
5077 ;; Subregs suck for register allocation. Pretend we can move TFmode
5078 ;; data between general registers until after reload.
5080 (define_insn_and_split "*movtf_internal"
5081 [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o")
5082 (match_operand:TF 1 "input_operand" "roG,rG"))]
5083 "register_operand (operands[0], TFmode)
5084 || reg_or_0_operand (operands[1], TFmode)"
5087 [(set (match_dup 0) (match_dup 2))
5088 (set (match_dup 1) (match_dup 3))]
5090 alpha_split_tfmode_pair (operands);
5091 if (reg_overlap_mentioned_p (operands[0], operands[3]))
5094 tmp = operands[0], operands[0] = operands[1], operands[1] = tmp;
5095 tmp = operands[2], operands[2] = operands[3], operands[3] = tmp;
5099 (define_expand "movsf"
5100 [(set (match_operand:SF 0 "nonimmediate_operand" "")
5101 (match_operand:SF 1 "general_operand" ""))]
5104 if (GET_CODE (operands[0]) == MEM
5105 && ! reg_or_0_operand (operands[1], SFmode))
5106 operands[1] = force_reg (SFmode, operands[1]);
5109 (define_expand "movdf"
5110 [(set (match_operand:DF 0 "nonimmediate_operand" "")
5111 (match_operand:DF 1 "general_operand" ""))]
5114 if (GET_CODE (operands[0]) == MEM
5115 && ! reg_or_0_operand (operands[1], DFmode))
5116 operands[1] = force_reg (DFmode, operands[1]);
5119 (define_expand "movtf"
5120 [(set (match_operand:TF 0 "nonimmediate_operand" "")
5121 (match_operand:TF 1 "general_operand" ""))]
5124 if (GET_CODE (operands[0]) == MEM
5125 && ! reg_or_0_operand (operands[1], TFmode))
5126 operands[1] = force_reg (TFmode, operands[1]);
5129 (define_insn "*movsi"
5130 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m")
5131 (match_operand:SI 1 "input_operand" "rJ,K,L,m,rJ"))]
5132 "(TARGET_ABI_OSF || TARGET_ABI_UNICOSMK)
5133 && (register_operand (operands[0], SImode)
5134 || reg_or_0_operand (operands[1], SImode))"
5141 [(set_attr "type" "ilog,iadd,iadd,ild,ist")])
5143 (define_insn "*movsi_nt_vms"
5144 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m")
5145 (match_operand:SI 1 "input_operand" "rJ,K,L,s,m,rJ"))]
5146 "(TARGET_ABI_WINDOWS_NT || TARGET_ABI_OPEN_VMS)
5147 && (register_operand (operands[0], SImode)
5148 || reg_or_0_operand (operands[1], SImode))"
5156 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist")])
5158 (define_insn "*movhi_nobwx"
5159 [(set (match_operand:HI 0 "register_operand" "=r,r")
5160 (match_operand:HI 1 "input_operand" "rJ,n"))]
5162 && (register_operand (operands[0], HImode)
5163 || register_operand (operands[1], HImode))"
5167 [(set_attr "type" "ilog,iadd")])
5169 (define_insn "*movhi_bwx"
5170 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
5171 (match_operand:HI 1 "input_operand" "rJ,n,m,rJ"))]
5173 && (register_operand (operands[0], HImode)
5174 || reg_or_0_operand (operands[1], HImode))"
5180 [(set_attr "type" "ilog,iadd,ild,ist")])
5182 (define_insn "*movqi_nobwx"
5183 [(set (match_operand:QI 0 "register_operand" "=r,r")
5184 (match_operand:QI 1 "input_operand" "rJ,n"))]
5186 && (register_operand (operands[0], QImode)
5187 || register_operand (operands[1], QImode))"
5191 [(set_attr "type" "ilog,iadd")])
5193 (define_insn "*movqi_bwx"
5194 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m")
5195 (match_operand:QI 1 "input_operand" "rJ,n,m,rJ"))]
5197 && (register_operand (operands[0], QImode)
5198 || reg_or_0_operand (operands[1], QImode))"
5204 [(set_attr "type" "ilog,iadd,ild,ist")])
5206 ;; We do two major things here: handle mem->mem and construct long
5209 (define_expand "movsi"
5210 [(set (match_operand:SI 0 "nonimmediate_operand" "")
5211 (match_operand:SI 1 "general_operand" ""))]
5214 if (alpha_expand_mov (SImode, operands))
5218 ;; Split a load of a large constant into the appropriate two-insn
5222 [(set (match_operand:SI 0 "register_operand" "")
5223 (match_operand:SI 1 "const_int_operand" ""))]
5224 "! add_operand (operands[1], SImode)"
5225 [(set (match_dup 0) (match_dup 2))
5226 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
5229 = alpha_emit_set_const (operands[0], SImode, INTVAL (operands[1]), 2);
5231 if (tem == operands[0])
5237 ;; Split the load of an address into a four-insn sequence on Unicos/Mk.
5238 ;; Always generate a REG_EQUAL note for the last instruction to facilitate
5239 ;; optimizations. If the symbolic operand is a label_ref, generate REG_LABEL
5240 ;; notes and update LABEL_NUSES because this is not done automatically.
5241 ;; Labels may be incorrectly deleted if we don't do this.
5243 ;; Describing what the individual instructions do correctly is too complicated
5244 ;; so use UNSPECs for each of the three parts of an address.
5247 [(set (match_operand:DI 0 "register_operand" "")
5248 (match_operand:DI 1 "symbolic_operand" ""))]
5249 "TARGET_ABI_UNICOSMK && reload_completed"
5252 rtx insn1, insn2, insn3;
5254 insn1 = emit_insn (gen_umk_laum (operands[0], operands[1]));
5255 emit_insn (gen_ashldi3 (operands[0], operands[0], GEN_INT (32)));
5256 insn2 = emit_insn (gen_umk_lalm (operands[0], operands[0], operands[1]));
5257 insn3 = emit_insn (gen_umk_lal (operands[0], operands[0], operands[1]));
5258 REG_NOTES (insn3) = gen_rtx_EXPR_LIST (REG_EQUAL, operands[1],
5260 if (GET_CODE (operands[1]) == LABEL_REF)
5264 label = XEXP (operands[1], 0);
5265 REG_NOTES (insn1) = gen_rtx_EXPR_LIST (REG_LABEL, label,
5267 REG_NOTES (insn2) = gen_rtx_EXPR_LIST (REG_LABEL, label,
5269 REG_NOTES (insn3) = gen_rtx_EXPR_LIST (REG_LABEL, label,
5271 LABEL_NUSES (label) += 3;
5276 ;; Instructions for loading the three parts of an address on Unicos/Mk.
5278 (define_insn "umk_laum"
5279 [(set (match_operand:DI 0 "register_operand" "=r")
5280 (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
5282 "TARGET_ABI_UNICOSMK"
5284 [(set_attr "type" "iadd")])
5286 (define_insn "umk_lalm"
5287 [(set (match_operand:DI 0 "register_operand" "=r")
5288 (plus:DI (match_operand:DI 1 "register_operand" "r")
5289 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
5291 "TARGET_ABI_UNICOSMK"
5293 [(set_attr "type" "iadd")])
5295 (define_insn "umk_lal"
5296 [(set (match_operand:DI 0 "register_operand" "=r")
5297 (plus:DI (match_operand:DI 1 "register_operand" "r")
5298 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
5300 "TARGET_ABI_UNICOSMK"
5302 [(set_attr "type" "iadd")])
5304 ;; Add a new call information word to the current function's list of CIWs
5305 ;; and load its index into $25. Doing it here ensures that the CIW will be
5306 ;; associated with the correct function even in the presence of inlining.
5308 (define_insn "*umk_load_ciw"
5310 (unspec:DI [(match_operand 0 "" "")] UNSPEC_UMK_LOAD_CIW))]
5311 "TARGET_ABI_UNICOSMK"
5313 operands[0] = unicosmk_add_call_info_word (operands[0]);
5314 return "lda $25,%0";
5316 [(set_attr "type" "iadd")])
5318 (define_insn "*movdi_er_low_l"
5319 [(set (match_operand:DI 0 "register_operand" "=r")
5320 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
5321 (match_operand:DI 2 "local_symbolic_operand" "")))]
5322 "TARGET_EXPLICIT_RELOCS"
5324 if (true_regnum (operands[1]) == 29)
5325 return "lda %0,%2(%1)\t\t!gprel";
5327 return "lda %0,%2(%1)\t\t!gprellow";
5329 [(set_attr "usegp" "yes")])
5332 [(set (match_operand:DI 0 "register_operand" "")
5333 (match_operand:DI 1 "small_symbolic_operand" ""))]
5334 "TARGET_EXPLICIT_RELOCS && reload_completed"
5336 (lo_sum:DI (match_dup 2) (match_dup 1)))]
5337 "operands[2] = pic_offset_table_rtx;")
5340 [(set (match_operand:DI 0 "register_operand" "")
5341 (match_operand:DI 1 "local_symbolic_operand" ""))]
5342 "TARGET_EXPLICIT_RELOCS && reload_completed"
5344 (plus:DI (match_dup 2) (high:DI (match_dup 1))))
5346 (lo_sum:DI (match_dup 0) (match_dup 1)))]
5347 "operands[2] = pic_offset_table_rtx;")
5350 [(match_operand 0 "some_small_symbolic_operand" "")]
5351 "TARGET_EXPLICIT_RELOCS && reload_completed"
5353 "operands[0] = split_small_symbolic_operand (operands[0]);")
5355 ;; Accepts any symbolic, not just global, since function calls that
5356 ;; don't go via bsr still use !literal in hopes of linker relaxation.
5357 (define_insn "movdi_er_high_g"
5358 [(set (match_operand:DI 0 "register_operand" "=r")
5359 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5360 (match_operand:DI 2 "symbolic_operand" "")
5361 (match_operand 3 "const_int_operand" "")]
5363 "TARGET_EXPLICIT_RELOCS"
5365 if (INTVAL (operands[3]) == 0)
5366 return "ldq %0,%2(%1)\t\t!literal";
5368 return "ldq %0,%2(%1)\t\t!literal!%3";
5370 [(set_attr "type" "ldsym")])
5373 [(set (match_operand:DI 0 "register_operand" "")
5374 (match_operand:DI 1 "global_symbolic_operand" ""))]
5375 "TARGET_EXPLICIT_RELOCS && reload_completed"
5377 (unspec:DI [(match_dup 2)
5379 (const_int 0)] UNSPEC_LITERAL))]
5380 "operands[2] = pic_offset_table_rtx;")
5382 ;; With RTL inlining, at -O3, rtl is generated, stored, then actually
5383 ;; compiled at the end of compilation. In the meantime, someone can
5384 ;; re-encode-section-info on some symbol changing it e.g. from global
5385 ;; to local-not-small. If this happens, we'd have emitted a plain
5386 ;; load rather than a high+losum load and not recognize the insn.
5388 ;; So if rtl inlining is in effect, we delay the global/not-global
5389 ;; decision until rest_of_compilation by wrapping it in an UNSPEC_SYMBOL.
5391 (define_insn_and_split "movdi_er_maybe_g"
5392 [(set (match_operand:DI 0 "register_operand" "=r")
5393 (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
5395 "TARGET_EXPLICIT_RELOCS && flag_inline_functions"
5398 [(set (match_dup 0) (match_dup 1))]
5400 if (local_symbolic_operand (operands[1], Pmode)
5401 && !small_symbolic_operand (operands[1], Pmode))
5403 rtx subtarget = no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode);
5406 tmp = gen_rtx_HIGH (Pmode, operands[1]);
5407 if (reload_completed)
5408 tmp = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, tmp);
5409 emit_insn (gen_rtx_SET (VOIDmode, subtarget, tmp));
5411 tmp = gen_rtx_LO_SUM (Pmode, subtarget, operands[1]);
5412 emit_insn (gen_rtx_SET (VOIDmode, operands[0], tmp));
5417 (define_insn "movdi_er_tlsgd"
5418 [(set (match_operand:DI 0 "register_operand" "=r")
5419 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5420 (match_operand:DI 2 "symbolic_operand" "")
5421 (match_operand 3 "const_int_operand" "")]
5425 if (INTVAL (operands[3]) == 0)
5426 return "lda %0,%2(%1)\t\t!tlsgd";
5428 return "lda %0,%2(%1)\t\t!tlsgd!%3";
5431 (define_insn "movdi_er_tlsldm"
5432 [(set (match_operand:DI 0 "register_operand" "=r")
5433 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5434 (match_operand 2 "const_int_operand" "")]
5438 if (INTVAL (operands[2]) == 0)
5439 return "lda %0,%&(%1)\t\t!tlsldm";
5441 return "lda %0,%&(%1)\t\t!tlsldm!%2";
5444 (define_insn "*movdi_er_gotdtp"
5445 [(set (match_operand:DI 0 "register_operand" "=r")
5446 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5447 (match_operand:DI 2 "symbolic_operand" "")]
5450 "ldq %0,%2(%1)\t\t!gotdtprel"
5451 [(set_attr "type" "ild")
5452 (set_attr "usegp" "yes")])
5455 [(set (match_operand:DI 0 "register_operand" "")
5456 (match_operand:DI 1 "gotdtp_symbolic_operand" ""))]
5457 "HAVE_AS_TLS && reload_completed"
5459 (unspec:DI [(match_dup 2)
5460 (match_dup 1)] UNSPEC_DTPREL))]
5462 operands[1] = XVECEXP (XEXP (operands[1], 0), 0, 0);
5463 operands[2] = pic_offset_table_rtx;
5466 (define_insn "*movdi_er_gottp"
5467 [(set (match_operand:DI 0 "register_operand" "=r")
5468 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5469 (match_operand:DI 2 "symbolic_operand" "")]
5472 "ldq %0,%2(%1)\t\t!gottprel"
5473 [(set_attr "type" "ild")
5474 (set_attr "usegp" "yes")])
5477 [(set (match_operand:DI 0 "register_operand" "")
5478 (match_operand:DI 1 "gottp_symbolic_operand" ""))]
5479 "HAVE_AS_TLS && reload_completed"
5481 (unspec:DI [(match_dup 2)
5482 (match_dup 1)] UNSPEC_TPREL))]
5484 operands[1] = XVECEXP (XEXP (operands[1], 0), 0, 0);
5485 operands[2] = pic_offset_table_rtx;
5488 (define_insn "*movdi_er_nofix"
5489 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m,*f,*f,Q")
5490 (match_operand:DI 1 "input_operand" "rJ,K,L,T,s,m,rJ,*fJ,Q,*f"))]
5491 "TARGET_EXPLICIT_RELOCS && ! TARGET_FIX
5492 && (register_operand (operands[0], DImode)
5493 || reg_or_0_operand (operands[1], DImode))"
5505 [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst")
5506 (set_attr "usegp" "*,*,*,yes,*,*,*,*,*,*")])
5508 ;; The 'U' constraint matches symbolic operands on Unicos/Mk. Those should
5509 ;; have been split up by the rules above but we shouldn't reject the
5510 ;; possibility of them getting through.
5512 (define_insn "*movdi_nofix"
5513 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m,*f,*f,Q")
5514 (match_operand:DI 1 "input_operand" "rJ,K,L,U,s,m,rJ,*fJ,Q,*f"))]
5516 && (register_operand (operands[0], DImode)
5517 || reg_or_0_operand (operands[1], DImode))"
5522 laum %0,%t1($31)\;sll %0,32,%0\;lalm %0,%t1(%0)\;lal %0,%t1(%0)
5529 [(set_attr "type" "ilog,iadd,iadd,ldsym,ldsym,ild,ist,fcpys,fld,fst")
5530 (set_attr "length" "*,*,*,16,*,*,*,*,*,*")])
5532 (define_insn "*movdi_er_fix"
5533 [(set (match_operand:DI 0 "nonimmediate_operand"
5534 "=r,r,r,r,r,r, m, *f,*f, Q, r,*f")
5535 (match_operand:DI 1 "input_operand"
5536 "rJ,K,L,T,s,m,rJ,*fJ, Q,*f,*f, r"))]
5537 "TARGET_EXPLICIT_RELOCS && TARGET_FIX
5538 && (register_operand (operands[0], DImode)
5539 || reg_or_0_operand (operands[1], DImode))"
5553 [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof")
5554 (set_attr "usegp" "*,*,*,yes,*,*,*,*,*,*,*,*")])
5556 (define_insn "*movdi_fix"
5557 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,Q,r,*f")
5558 (match_operand:DI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,Q,*f,*f,r"))]
5559 "! TARGET_EXPLICIT_RELOCS && TARGET_FIX
5560 && (register_operand (operands[0], DImode)
5561 || reg_or_0_operand (operands[1], DImode))"
5574 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof")])
5576 ;; VMS needs to set up "vms_base_regno" for unwinding. This move
5577 ;; often appears dead to the life analysis code, at which point we
5578 ;; abort for emitting dead prologue instructions. Force this live.
5580 (define_insn "force_movdi"
5581 [(set (match_operand:DI 0 "register_operand" "=r")
5582 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")]
5583 UNSPECV_FORCE_MOV))]
5586 [(set_attr "type" "ilog")])
5588 ;; We do three major things here: handle mem->mem, put 64-bit constants in
5589 ;; memory, and construct long 32-bit constants.
5591 (define_expand "movdi"
5592 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5593 (match_operand:DI 1 "general_operand" ""))]
5596 if (alpha_expand_mov (DImode, operands))
5600 ;; Split a load of a large constant into the appropriate two-insn
5604 [(set (match_operand:DI 0 "register_operand" "")
5605 (match_operand:DI 1 "const_int_operand" ""))]
5606 "! add_operand (operands[1], DImode)"
5607 [(set (match_dup 0) (match_dup 2))
5608 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
5611 = alpha_emit_set_const (operands[0], DImode, INTVAL (operands[1]), 2);
5613 if (tem == operands[0])
5619 ;; These are the partial-word cases.
5621 ;; First we have the code to load an aligned word. Operand 0 is the register
5622 ;; in which to place the result. It's mode is QImode or HImode. Operand 1
5623 ;; is an SImode MEM at the low-order byte of the proper word. Operand 2 is the
5624 ;; number of bits within the word that the value is. Operand 3 is an SImode
5625 ;; scratch register. If operand 0 is a hard register, operand 3 may be the
5626 ;; same register. It is allowed to conflict with operand 1 as well.
5628 (define_expand "aligned_loadqi"
5629 [(set (match_operand:SI 3 "register_operand" "")
5630 (match_operand:SI 1 "memory_operand" ""))
5631 (set (match_operand:DI 0 "register_operand" "")
5632 (zero_extract:DI (subreg:DI (match_dup 3) 0)
5634 (match_operand:DI 2 "const_int_operand" "")))]
5639 (define_expand "aligned_loadhi"
5640 [(set (match_operand:SI 3 "register_operand" "")
5641 (match_operand:SI 1 "memory_operand" ""))
5642 (set (match_operand:DI 0 "register_operand" "")
5643 (zero_extract:DI (subreg:DI (match_dup 3) 0)
5645 (match_operand:DI 2 "const_int_operand" "")))]
5650 ;; Similar for unaligned loads, where we use the sequence from the
5651 ;; Alpha Architecture manual. We have to distinguish between little-endian
5652 ;; and big-endian systems as the sequences are different.
5654 ;; Operand 1 is the address. Operands 2 and 3 are temporaries, where
5655 ;; operand 3 can overlap the input and output registers.
5657 (define_expand "unaligned_loadqi"
5658 [(use (match_operand:DI 0 "register_operand" ""))
5659 (use (match_operand:DI 1 "address_operand" ""))
5660 (use (match_operand:DI 2 "register_operand" ""))
5661 (use (match_operand:DI 3 "register_operand" ""))]
5664 if (WORDS_BIG_ENDIAN)
5665 emit_insn (gen_unaligned_loadqi_be (operands[0], operands[1],
5666 operands[2], operands[3]));
5668 emit_insn (gen_unaligned_loadqi_le (operands[0], operands[1],
5669 operands[2], operands[3]));
5673 (define_expand "unaligned_loadqi_le"
5674 [(set (match_operand:DI 2 "register_operand" "")
5675 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5677 (set (match_operand:DI 3 "register_operand" "")
5679 (set (match_operand:DI 0 "register_operand" "")
5680 (zero_extract:DI (match_dup 2)
5682 (ashift:DI (match_dup 3) (const_int 3))))]
5683 "! WORDS_BIG_ENDIAN"
5686 (define_expand "unaligned_loadqi_be"
5687 [(set (match_operand:DI 2 "register_operand" "")
5688 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5690 (set (match_operand:DI 3 "register_operand" "")
5692 (set (match_operand:DI 0 "register_operand" "")
5693 (zero_extract:DI (match_dup 2)
5697 (ashift:DI (match_dup 3) (const_int 3)))))]
5701 (define_expand "unaligned_loadhi"
5702 [(use (match_operand:DI 0 "register_operand" ""))
5703 (use (match_operand:DI 1 "address_operand" ""))
5704 (use (match_operand:DI 2 "register_operand" ""))
5705 (use (match_operand:DI 3 "register_operand" ""))]
5708 if (WORDS_BIG_ENDIAN)
5709 emit_insn (gen_unaligned_loadhi_be (operands[0], operands[1],
5710 operands[2], operands[3]));
5712 emit_insn (gen_unaligned_loadhi_le (operands[0], operands[1],
5713 operands[2], operands[3]));
5717 (define_expand "unaligned_loadhi_le"
5718 [(set (match_operand:DI 2 "register_operand" "")
5719 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5721 (set (match_operand:DI 3 "register_operand" "")
5723 (set (match_operand:DI 0 "register_operand" "")
5724 (zero_extract:DI (match_dup 2)
5726 (ashift:DI (match_dup 3) (const_int 3))))]
5727 "! WORDS_BIG_ENDIAN"
5730 (define_expand "unaligned_loadhi_be"
5731 [(set (match_operand:DI 2 "register_operand" "")
5732 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5734 (set (match_operand:DI 3 "register_operand" "")
5735 (plus:DI (match_dup 1) (const_int 1)))
5736 (set (match_operand:DI 0 "register_operand" "")
5737 (zero_extract:DI (match_dup 2)
5741 (ashift:DI (match_dup 3) (const_int 3)))))]
5745 ;; Storing an aligned byte or word requires two temporaries. Operand 0 is the
5746 ;; aligned SImode MEM. Operand 1 is the register containing the
5747 ;; byte or word to store. Operand 2 is the number of bits within the word that
5748 ;; the value should be placed. Operands 3 and 4 are SImode temporaries.
5750 (define_expand "aligned_store"
5751 [(set (match_operand:SI 3 "register_operand" "")
5752 (match_operand:SI 0 "memory_operand" ""))
5753 (set (subreg:DI (match_dup 3) 0)
5754 (and:DI (subreg:DI (match_dup 3) 0) (match_dup 5)))
5755 (set (subreg:DI (match_operand:SI 4 "register_operand" "") 0)
5756 (ashift:DI (zero_extend:DI (match_operand 1 "register_operand" ""))
5757 (match_operand:DI 2 "const_int_operand" "")))
5758 (set (subreg:DI (match_dup 4) 0)
5759 (ior:DI (subreg:DI (match_dup 4) 0) (subreg:DI (match_dup 3) 0)))
5760 (set (match_dup 0) (match_dup 4))]
5763 operands[5] = GEN_INT (~ (GET_MODE_MASK (GET_MODE (operands[1]))
5764 << INTVAL (operands[2])));
5767 ;; For the unaligned byte and halfword cases, we use code similar to that
5768 ;; in the ;; Architecture book, but reordered to lower the number of registers
5769 ;; required. Operand 0 is the address. Operand 1 is the data to store.
5770 ;; Operands 2, 3, and 4 are DImode temporaries, where operands 2 and 4 may
5771 ;; be the same temporary, if desired. If the address is in a register,
5772 ;; operand 2 can be that register.
5774 (define_expand "unaligned_storeqi"
5775 [(use (match_operand:DI 0 "address_operand" ""))
5776 (use (match_operand:QI 1 "register_operand" ""))
5777 (use (match_operand:DI 2 "register_operand" ""))
5778 (use (match_operand:DI 3 "register_operand" ""))
5779 (use (match_operand:DI 4 "register_operand" ""))]
5782 if (WORDS_BIG_ENDIAN)
5783 emit_insn (gen_unaligned_storeqi_be (operands[0], operands[1],
5784 operands[2], operands[3],
5787 emit_insn (gen_unaligned_storeqi_le (operands[0], operands[1],
5788 operands[2], operands[3],
5793 (define_expand "unaligned_storeqi_le"
5794 [(set (match_operand:DI 3 "register_operand" "")
5795 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5797 (set (match_operand:DI 2 "register_operand" "")
5800 (and:DI (not:DI (ashift:DI (const_int 255)
5801 (ashift:DI (match_dup 2) (const_int 3))))
5803 (set (match_operand:DI 4 "register_operand" "")
5804 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
5805 (ashift:DI (match_dup 2) (const_int 3))))
5806 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5807 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5809 "! WORDS_BIG_ENDIAN"
5812 (define_expand "unaligned_storeqi_be"
5813 [(set (match_operand:DI 3 "register_operand" "")
5814 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5816 (set (match_operand:DI 2 "register_operand" "")
5819 (and:DI (not:DI (ashift:DI (const_int 255)
5820 (minus:DI (const_int 56)
5821 (ashift:DI (match_dup 2) (const_int 3)))))
5823 (set (match_operand:DI 4 "register_operand" "")
5824 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
5825 (minus:DI (const_int 56)
5826 (ashift:DI (match_dup 2) (const_int 3)))))
5827 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5828 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5833 (define_expand "unaligned_storehi"
5834 [(use (match_operand:DI 0 "address_operand" ""))
5835 (use (match_operand:HI 1 "register_operand" ""))
5836 (use (match_operand:DI 2 "register_operand" ""))
5837 (use (match_operand:DI 3 "register_operand" ""))
5838 (use (match_operand:DI 4 "register_operand" ""))]
5841 if (WORDS_BIG_ENDIAN)
5842 emit_insn (gen_unaligned_storehi_be (operands[0], operands[1],
5843 operands[2], operands[3],
5846 emit_insn (gen_unaligned_storehi_le (operands[0], operands[1],
5847 operands[2], operands[3],
5852 (define_expand "unaligned_storehi_le"
5853 [(set (match_operand:DI 3 "register_operand" "")
5854 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5856 (set (match_operand:DI 2 "register_operand" "")
5859 (and:DI (not:DI (ashift:DI (const_int 65535)
5860 (ashift:DI (match_dup 2) (const_int 3))))
5862 (set (match_operand:DI 4 "register_operand" "")
5863 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
5864 (ashift:DI (match_dup 2) (const_int 3))))
5865 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5866 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5868 "! WORDS_BIG_ENDIAN"
5871 (define_expand "unaligned_storehi_be"
5872 [(set (match_operand:DI 3 "register_operand" "")
5873 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5875 (set (match_operand:DI 2 "register_operand" "")
5876 (plus:DI (match_dup 0) (const_int 1)))
5878 (and:DI (not:DI (ashift:DI
5880 (minus:DI (const_int 56)
5881 (ashift:DI (match_dup 2) (const_int 3)))))
5883 (set (match_operand:DI 4 "register_operand" "")
5884 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
5885 (minus:DI (const_int 56)
5886 (ashift:DI (match_dup 2) (const_int 3)))))
5887 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5888 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5893 ;; Here are the define_expand's for QI and HI moves that use the above
5894 ;; patterns. We have the normal sets, plus the ones that need scratch
5895 ;; registers for reload.
5897 (define_expand "movqi"
5898 [(set (match_operand:QI 0 "nonimmediate_operand" "")
5899 (match_operand:QI 1 "general_operand" ""))]
5903 ? alpha_expand_mov (QImode, operands)
5904 : alpha_expand_mov_nobwx (QImode, operands))
5908 (define_expand "movhi"
5909 [(set (match_operand:HI 0 "nonimmediate_operand" "")
5910 (match_operand:HI 1 "general_operand" ""))]
5914 ? alpha_expand_mov (HImode, operands)
5915 : alpha_expand_mov_nobwx (HImode, operands))
5919 ;; Here are the versions for reload. Note that in the unaligned cases
5920 ;; we know that the operand must not be a pseudo-register because stack
5921 ;; slots are always aligned references.
5923 (define_expand "reload_inqi"
5924 [(parallel [(match_operand:QI 0 "register_operand" "=r")
5925 (match_operand:QI 1 "any_memory_operand" "m")
5926 (match_operand:TI 2 "register_operand" "=&r")])]
5931 if (aligned_memory_operand (operands[1], QImode))
5933 seq = gen_reload_inqi_help (operands[0], operands[1],
5934 gen_rtx_REG (SImode, REGNO (operands[2])));
5940 /* It is possible that one of the registers we got for operands[2]
5941 might coincide with that of operands[0] (which is why we made
5942 it TImode). Pick the other one to use as our scratch. */
5943 if (REGNO (operands[0]) == REGNO (operands[2]))
5944 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5946 scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
5948 addr = get_unaligned_address (operands[1], 0);
5949 operands[0] = gen_rtx_REG (DImode, REGNO (operands[0]));
5950 seq = gen_unaligned_loadqi (operands[0], addr, scratch, operands[0]);
5951 alpha_set_memflags (seq, operands[1]);
5957 (define_expand "reload_inhi"
5958 [(parallel [(match_operand:HI 0 "register_operand" "=r")
5959 (match_operand:HI 1 "any_memory_operand" "m")
5960 (match_operand:TI 2 "register_operand" "=&r")])]
5965 if (aligned_memory_operand (operands[1], HImode))
5967 seq = gen_reload_inhi_help (operands[0], operands[1],
5968 gen_rtx_REG (SImode, REGNO (operands[2])));
5974 /* It is possible that one of the registers we got for operands[2]
5975 might coincide with that of operands[0] (which is why we made
5976 it TImode). Pick the other one to use as our scratch. */
5977 if (REGNO (operands[0]) == REGNO (operands[2]))
5978 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5980 scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
5982 addr = get_unaligned_address (operands[1], 0);
5983 operands[0] = gen_rtx_REG (DImode, REGNO (operands[0]));
5984 seq = gen_unaligned_loadhi (operands[0], addr, scratch, operands[0]);
5985 alpha_set_memflags (seq, operands[1]);
5991 (define_expand "reload_outqi"
5992 [(parallel [(match_operand:QI 0 "any_memory_operand" "=m")
5993 (match_operand:QI 1 "register_operand" "r")
5994 (match_operand:TI 2 "register_operand" "=&r")])]
5997 if (aligned_memory_operand (operands[0], QImode))
5999 emit_insn (gen_reload_outqi_help
6000 (operands[0], operands[1],
6001 gen_rtx_REG (SImode, REGNO (operands[2])),
6002 gen_rtx_REG (SImode, REGNO (operands[2]) + 1)));
6006 rtx addr = get_unaligned_address (operands[0], 0);
6007 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
6008 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
6009 rtx scratch3 = scratch1;
6012 if (GET_CODE (addr) == REG)
6015 seq = gen_unaligned_storeqi (addr, operands[1], scratch1,
6016 scratch2, scratch3);
6017 alpha_set_memflags (seq, operands[0]);
6023 (define_expand "reload_outhi"
6024 [(parallel [(match_operand:HI 0 "any_memory_operand" "=m")
6025 (match_operand:HI 1 "register_operand" "r")
6026 (match_operand:TI 2 "register_operand" "=&r")])]
6029 if (aligned_memory_operand (operands[0], HImode))
6031 emit_insn (gen_reload_outhi_help
6032 (operands[0], operands[1],
6033 gen_rtx_REG (SImode, REGNO (operands[2])),
6034 gen_rtx_REG (SImode, REGNO (operands[2]) + 1)));
6038 rtx addr = get_unaligned_address (operands[0], 0);
6039 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
6040 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
6041 rtx scratch3 = scratch1;
6044 if (GET_CODE (addr) == REG)
6047 seq = gen_unaligned_storehi (addr, operands[1], scratch1,
6048 scratch2, scratch3);
6049 alpha_set_memflags (seq, operands[0]);
6055 ;; Helpers for the above. The way reload is structured, we can't
6056 ;; always get a proper address for a stack slot during reload_foo
6057 ;; expansion, so we must delay our address manipulations until after.
6059 (define_insn_and_split "reload_inqi_help"
6060 [(set (match_operand:QI 0 "register_operand" "=r")
6061 (match_operand:QI 1 "memory_operand" "m"))
6062 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6063 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6065 "! TARGET_BWX && reload_completed"
6068 rtx aligned_mem, bitnum;
6069 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
6070 operands[0] = gen_lowpart (DImode, operands[0]);
6071 emit_insn (gen_aligned_loadqi (operands[0], aligned_mem, bitnum,
6076 (define_insn_and_split "reload_inhi_help"
6077 [(set (match_operand:HI 0 "register_operand" "=r")
6078 (match_operand:HI 1 "memory_operand" "m"))
6079 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6080 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6082 "! TARGET_BWX && reload_completed"
6085 rtx aligned_mem, bitnum;
6086 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
6087 operands[0] = gen_lowpart (DImode, operands[0]);
6088 emit_insn (gen_aligned_loadhi (operands[0], aligned_mem, bitnum,
6093 (define_insn_and_split "reload_outqi_help"
6094 [(set (match_operand:QI 0 "memory_operand" "=m")
6095 (match_operand:QI 1 "register_operand" "r"))
6096 (clobber (match_operand:SI 2 "register_operand" "=r"))
6097 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6098 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6100 "! TARGET_BWX && reload_completed"
6103 rtx aligned_mem, bitnum;
6104 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
6105 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
6106 operands[2], operands[3]));
6110 (define_insn_and_split "reload_outhi_help"
6111 [(set (match_operand:HI 0 "memory_operand" "=m")
6112 (match_operand:HI 1 "register_operand" "r"))
6113 (clobber (match_operand:SI 2 "register_operand" "=r"))
6114 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6115 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6117 "! TARGET_BWX && reload_completed"
6120 rtx aligned_mem, bitnum;
6121 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
6122 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
6123 operands[2], operands[3]));
6127 ;; Vector operations
6129 (define_expand "movv8qi"
6130 [(set (match_operand:V8QI 0 "nonimmediate_operand" "")
6131 (match_operand:V8QI 1 "general_operand" ""))]
6134 if (alpha_expand_mov (V8QImode, operands))
6138 (define_insn "*movv8qi_fix"
6139 [(set (match_operand:V8QI 0 "nonimmediate_operand" "=r,r,m,*f,*f,m,r,*f")
6140 (match_operand:V8QI 1 "input_operand" "rW,m,rW,*fW,m,*f,*f,r"))]
6142 && (register_operand (operands[0], V8QImode)
6143 || reg_or_0_operand (operands[1], V8QImode))"
6153 [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst,ftoi,itof")])
6155 (define_insn "*movv8qi_nofix"
6156 [(set (match_operand:V8QI 0 "nonimmediate_operand" "=r,r,m,*f,*f,m")
6157 (match_operand:V8QI 1 "input_operand" "rW,m,rW,*fW,m,*f"))]
6159 && (register_operand (operands[0], V8QImode)
6160 || reg_or_0_operand (operands[1], V8QImode))"
6168 [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst")])
6170 (define_expand "movv4hi"
6171 [(set (match_operand:V4HI 0 "nonimmediate_operand" "")
6172 (match_operand:V4HI 1 "general_operand" ""))]
6175 if (alpha_expand_mov (V4HImode, operands))
6179 (define_insn "*movv4hi_fix"
6180 [(set (match_operand:V4HI 0 "nonimmediate_operand" "=r,r,m,*f,*f,m,r,*f")
6181 (match_operand:V4HI 1 "input_operand" "rW,m,rW,*fW,m,*f,*f,r"))]
6183 && (register_operand (operands[0], V4HImode)
6184 || reg_or_0_operand (operands[1], V4HImode))"
6194 [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst,ftoi,itof")])
6196 (define_insn "*movv4hi_nofix"
6197 [(set (match_operand:V4HI 0 "nonimmediate_operand" "=r,r,m,*f,*f,m")
6198 (match_operand:V4HI 1 "input_operand" "rW,m,rW,*fW,m,*f"))]
6200 && (register_operand (operands[0], V4HImode)
6201 || reg_or_0_operand (operands[1], V4HImode))"
6209 [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst")])
6211 (define_expand "movv2si"
6212 [(set (match_operand:V2SI 0 "nonimmediate_operand" "")
6213 (match_operand:V2SI 1 "general_operand" ""))]
6216 if (alpha_expand_mov (V2SImode, operands))
6220 (define_insn "*movv2si_fix"
6221 [(set (match_operand:V2SI 0 "nonimmediate_operand" "=r,r,m,*f,*f,m,r,*f")
6222 (match_operand:V2SI 1 "input_operand" "rW,m,rW,*fW,m,*f,*f,r"))]
6224 && (register_operand (operands[0], V2SImode)
6225 || reg_or_0_operand (operands[1], V2SImode))"
6235 [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst,ftoi,itof")])
6237 (define_insn "*movv2si_nofix"
6238 [(set (match_operand:V2SI 0 "nonimmediate_operand" "=r,r,m,*f,*f,m")
6239 (match_operand:V2SI 1 "input_operand" "rW,m,rW,*fW,m,*f"))]
6241 && (register_operand (operands[0], V2SImode)
6242 || reg_or_0_operand (operands[1], V2SImode))"
6250 [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst")])
6252 (define_insn "uminv8qi3"
6253 [(set (match_operand:V8QI 0 "register_operand" "=r")
6254 (umin:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
6255 (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
6258 [(set_attr "type" "mvi")])
6260 (define_insn "sminv8qi3"
6261 [(set (match_operand:V8QI 0 "register_operand" "=r")
6262 (smin:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
6263 (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
6266 [(set_attr "type" "mvi")])
6268 (define_insn "uminv4hi3"
6269 [(set (match_operand:V4HI 0 "register_operand" "=r")
6270 (umin:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
6271 (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
6274 [(set_attr "type" "mvi")])
6276 (define_insn "sminv4hi3"
6277 [(set (match_operand:V4HI 0 "register_operand" "=r")
6278 (smin:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
6279 (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
6282 [(set_attr "type" "mvi")])
6284 (define_insn "umaxv8qi3"
6285 [(set (match_operand:V8QI 0 "register_operand" "=r")
6286 (umax:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
6287 (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
6290 [(set_attr "type" "mvi")])
6292 (define_insn "smaxv8qi3"
6293 [(set (match_operand:V8QI 0 "register_operand" "=r")
6294 (smax:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
6295 (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
6298 [(set_attr "type" "mvi")])
6300 (define_insn "umaxv4hi3"
6301 [(set (match_operand:V4HI 0 "register_operand" "=r")
6302 (umax:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
6303 (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
6306 [(set_attr "type" "mvi")])
6308 (define_insn "smaxv4hi3"
6309 [(set (match_operand:V4HI 0 "register_operand" "=r")
6310 (smax:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
6311 (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
6314 [(set_attr "type" "mvi")])
6316 ;; Bit field extract patterns which use ext[wlq][lh]
6318 (define_expand "extv"
6319 [(set (match_operand:DI 0 "register_operand" "")
6320 (sign_extract:DI (match_operand:QI 1 "memory_operand" "")
6321 (match_operand:DI 2 "immediate_operand" "")
6322 (match_operand:DI 3 "immediate_operand" "")))]
6327 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6328 if (INTVAL (operands[3]) % 8 != 0
6329 || (INTVAL (operands[2]) != 16
6330 && INTVAL (operands[2]) != 32
6331 && INTVAL (operands[2]) != 64))
6334 /* From mips.md: extract_bit_field doesn't verify that our source
6335 matches the predicate, so we force it to be a MEM here. */
6336 if (GET_CODE (operands[1]) != MEM)
6339 /* The bit number is relative to the mode of operand 1 which is
6340 usually QImode (this might actually be a bug in expmed.c). Note
6341 that the bit number is negative in big-endian mode in this case.
6342 We have to convert that to the offset. */
6343 if (WORDS_BIG_ENDIAN)
6344 ofs = GET_MODE_BITSIZE (GET_MODE (operands[1]))
6345 - INTVAL (operands[2]) - INTVAL (operands[3]);
6347 ofs = INTVAL (operands[3]);
6351 alpha_expand_unaligned_load (operands[0], operands[1],
6352 INTVAL (operands[2]) / 8,
6357 (define_expand "extzv"
6358 [(set (match_operand:DI 0 "register_operand" "")
6359 (zero_extract:DI (match_operand:DI 1 "nonimmediate_operand" "")
6360 (match_operand:DI 2 "immediate_operand" "")
6361 (match_operand:DI 3 "immediate_operand" "")))]
6364 /* We can do 8, 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6365 if (INTVAL (operands[3]) % 8 != 0
6366 || (INTVAL (operands[2]) != 8
6367 && INTVAL (operands[2]) != 16
6368 && INTVAL (operands[2]) != 32
6369 && INTVAL (operands[2]) != 64))
6372 if (GET_CODE (operands[1]) == MEM)
6376 /* Fail 8 bit fields, falling back on a simple byte load. */
6377 if (INTVAL (operands[2]) == 8)
6380 /* The bit number is relative to the mode of operand 1 which is
6381 usually QImode (this might actually be a bug in expmed.c). Note
6382 that the bit number is negative in big-endian mode in this case.
6383 We have to convert that to the offset. */
6384 if (WORDS_BIG_ENDIAN)
6385 ofs = GET_MODE_BITSIZE (GET_MODE (operands[1]))
6386 - INTVAL (operands[2]) - INTVAL (operands[3]);
6388 ofs = INTVAL (operands[3]);
6392 alpha_expand_unaligned_load (operands[0], operands[1],
6393 INTVAL (operands[2]) / 8,
6399 (define_expand "insv"
6400 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "")
6401 (match_operand:DI 1 "immediate_operand" "")
6402 (match_operand:DI 2 "immediate_operand" ""))
6403 (match_operand:DI 3 "register_operand" ""))]
6408 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6409 if (INTVAL (operands[2]) % 8 != 0
6410 || (INTVAL (operands[1]) != 16
6411 && INTVAL (operands[1]) != 32
6412 && INTVAL (operands[1]) != 64))
6415 /* From mips.md: store_bit_field doesn't verify that our source
6416 matches the predicate, so we force it to be a MEM here. */
6417 if (GET_CODE (operands[0]) != MEM)
6420 /* The bit number is relative to the mode of operand 1 which is
6421 usually QImode (this might actually be a bug in expmed.c). Note
6422 that the bit number is negative in big-endian mode in this case.
6423 We have to convert that to the offset. */
6424 if (WORDS_BIG_ENDIAN)
6425 ofs = GET_MODE_BITSIZE (GET_MODE (operands[0]))
6426 - INTVAL (operands[1]) - INTVAL (operands[2]);
6428 ofs = INTVAL (operands[2]);
6432 alpha_expand_unaligned_store (operands[0], operands[3],
6433 INTVAL (operands[1]) / 8, ofs);
6437 ;; Block move/clear, see alpha.c for more details.
6438 ;; Argument 0 is the destination
6439 ;; Argument 1 is the source
6440 ;; Argument 2 is the length
6441 ;; Argument 3 is the alignment
6443 (define_expand "movmemqi"
6444 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6445 (match_operand:BLK 1 "memory_operand" ""))
6446 (use (match_operand:DI 2 "immediate_operand" ""))
6447 (use (match_operand:DI 3 "immediate_operand" ""))])]
6450 if (alpha_expand_block_move (operands))
6456 (define_expand "movmemdi"
6457 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6458 (match_operand:BLK 1 "memory_operand" ""))
6459 (use (match_operand:DI 2 "immediate_operand" ""))
6460 (use (match_operand:DI 3 "immediate_operand" ""))
6462 (clobber (reg:DI 25))
6463 (clobber (reg:DI 16))
6464 (clobber (reg:DI 17))
6465 (clobber (reg:DI 18))
6466 (clobber (reg:DI 19))
6467 (clobber (reg:DI 20))
6468 (clobber (reg:DI 26))
6469 (clobber (reg:DI 27))])]
6470 "TARGET_ABI_OPEN_VMS"
6472 operands[4] = gen_rtx_SYMBOL_REF (Pmode, "OTS$MOVE");
6473 alpha_need_linkage (XSTR (operands[4], 0), 0);
6476 (define_insn "*movmemdi_1"
6477 [(set (match_operand:BLK 0 "memory_operand" "=m,=m")
6478 (match_operand:BLK 1 "memory_operand" "m,m"))
6479 (use (match_operand:DI 2 "nonmemory_operand" "r,i"))
6480 (use (match_operand:DI 3 "immediate_operand" ""))
6481 (use (match_operand:DI 4 "call_operand" "i,i"))
6482 (clobber (reg:DI 25))
6483 (clobber (reg:DI 16))
6484 (clobber (reg:DI 17))
6485 (clobber (reg:DI 18))
6486 (clobber (reg:DI 19))
6487 (clobber (reg:DI 20))
6488 (clobber (reg:DI 26))
6489 (clobber (reg:DI 27))]
6490 "TARGET_ABI_OPEN_VMS"
6492 operands [5] = alpha_use_linkage (operands [4], cfun->decl, 0, 1);
6493 switch (which_alternative)
6496 return "lda $16,%0\;bis $31,%2,$17\;lda $18,%1\;ldq $26,%5\;lda $25,3($31)\;jsr $26,%4\;ldq $27,0($29)";
6498 return "lda $16,%0\;lda $17,%2($31)\;lda $18,%1\;ldq $26,%5\;lda $25,3($31)\;jsr $26,%4\;ldq $27,0($29)";
6503 [(set_attr "type" "multi")
6504 (set_attr "length" "28")])
6506 (define_expand "clrmemqi"
6507 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6509 (use (match_operand:DI 1 "immediate_operand" ""))
6510 (use (match_operand:DI 2 "immediate_operand" ""))])]
6513 if (alpha_expand_block_clear (operands))
6519 (define_expand "clrmemdi"
6520 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6522 (use (match_operand:DI 1 "immediate_operand" ""))
6523 (use (match_operand:DI 2 "immediate_operand" ""))
6525 (clobber (reg:DI 25))
6526 (clobber (reg:DI 16))
6527 (clobber (reg:DI 17))
6528 (clobber (reg:DI 26))
6529 (clobber (reg:DI 27))])]
6530 "TARGET_ABI_OPEN_VMS"
6532 operands[3] = gen_rtx_SYMBOL_REF (Pmode, "OTS$ZERO");
6533 alpha_need_linkage (XSTR (operands[3], 0), 0);
6536 (define_insn "*clrmemdi_1"
6537 [(set (match_operand:BLK 0 "memory_operand" "=m,=m")
6539 (use (match_operand:DI 1 "nonmemory_operand" "r,i"))
6540 (use (match_operand:DI 2 "immediate_operand" ""))
6541 (use (match_operand:DI 3 "call_operand" "i,i"))
6542 (clobber (reg:DI 25))
6543 (clobber (reg:DI 16))
6544 (clobber (reg:DI 17))
6545 (clobber (reg:DI 26))
6546 (clobber (reg:DI 27))]
6547 "TARGET_ABI_OPEN_VMS"
6549 operands [4] = alpha_use_linkage (operands [3], cfun->decl, 0, 1);
6550 switch (which_alternative)
6553 return "lda $16,%0\;bis $31,%1,$17\;ldq $26,%4\;lda $25,2($31)\;jsr $26,%3\;ldq $27,0($29)";
6555 return "lda $16,%0\;lda $17,%1($31)\;ldq $26,%4\;lda $25,2($31)\;jsr $26,%3\;ldq $27,0($29)";
6560 [(set_attr "type" "multi")
6561 (set_attr "length" "24")])
6564 ;; Subroutine of stack space allocation. Perform a stack probe.
6565 (define_expand "probe_stack"
6566 [(set (match_dup 1) (match_operand:DI 0 "const_int_operand" ""))]
6569 operands[1] = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx,
6570 INTVAL (operands[0])));
6571 MEM_VOLATILE_P (operands[1]) = 1;
6573 operands[0] = const0_rtx;
6576 ;; This is how we allocate stack space. If we are allocating a
6577 ;; constant amount of space and we know it is less than 4096
6578 ;; bytes, we need do nothing.
6580 ;; If it is more than 4096 bytes, we need to probe the stack
6582 (define_expand "allocate_stack"
6584 (plus:DI (reg:DI 30)
6585 (match_operand:DI 1 "reg_or_cint_operand" "")))
6586 (set (match_operand:DI 0 "register_operand" "=r")
6590 if (GET_CODE (operands[1]) == CONST_INT
6591 && INTVAL (operands[1]) < 32768)
6593 if (INTVAL (operands[1]) >= 4096)
6595 /* We do this the same way as in the prologue and generate explicit
6596 probes. Then we update the stack by the constant. */
6600 emit_insn (gen_probe_stack (GEN_INT (- probed)));
6601 while (probed + 8192 < INTVAL (operands[1]))
6602 emit_insn (gen_probe_stack (GEN_INT (- (probed += 8192))));
6604 if (probed + 4096 < INTVAL (operands[1]))
6605 emit_insn (gen_probe_stack (GEN_INT (- INTVAL(operands[1]))));
6608 operands[1] = GEN_INT (- INTVAL (operands[1]));
6609 operands[2] = virtual_stack_dynamic_rtx;
6614 rtx loop_label = gen_label_rtx ();
6615 rtx want = gen_reg_rtx (Pmode);
6616 rtx tmp = gen_reg_rtx (Pmode);
6619 emit_insn (gen_subdi3 (want, stack_pointer_rtx,
6620 force_reg (Pmode, operands[1])));
6621 emit_insn (gen_adddi3 (tmp, stack_pointer_rtx, GEN_INT (-4096)));
6623 if (GET_CODE (operands[1]) != CONST_INT)
6625 out_label = gen_label_rtx ();
6626 emit_insn (gen_cmpdi (want, tmp));
6627 emit_jump_insn (gen_bgeu (out_label));
6630 emit_label (loop_label);
6631 memref = gen_rtx_MEM (DImode, tmp);
6632 MEM_VOLATILE_P (memref) = 1;
6633 emit_move_insn (memref, const0_rtx);
6634 emit_insn (gen_adddi3 (tmp, tmp, GEN_INT(-8192)));
6635 emit_insn (gen_cmpdi (tmp, want));
6636 emit_jump_insn (gen_bgtu (loop_label));
6638 memref = gen_rtx_MEM (DImode, want);
6639 MEM_VOLATILE_P (memref) = 1;
6640 emit_move_insn (memref, const0_rtx);
6643 emit_label (out_label);
6645 emit_move_insn (stack_pointer_rtx, want);
6646 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
6651 ;; This is used by alpha_expand_prolog to do the same thing as above,
6652 ;; except we cannot at that time generate new basic blocks, so we hide
6653 ;; the loop in this one insn.
6655 (define_insn "prologue_stack_probe_loop"
6656 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")
6657 (match_operand:DI 1 "register_operand" "r")]
6661 operands[2] = gen_label_rtx ();
6662 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6663 CODE_LABEL_NUMBER (operands[2]));
6665 return "stq $31,-8192(%1)\;subq %0,1,%0\;lda %1,-8192(%1)\;bne %0,%l2";
6667 [(set_attr "length" "16")
6668 (set_attr "type" "multi")])
6670 (define_expand "prologue"
6671 [(clobber (const_int 0))]
6674 alpha_expand_prologue ();
6678 ;; These take care of emitting the ldgp insn in the prologue. This will be
6679 ;; an lda/ldah pair and we want to align them properly. So we have two
6680 ;; unspec_volatile insns, the first of which emits the ldgp assembler macro
6681 ;; and the second of which emits nothing. However, both are marked as type
6682 ;; IADD (the default) so the alignment code in alpha.c does the right thing
6685 (define_expand "prologue_ldgp"
6687 (unspec_volatile:DI [(match_dup 1) (match_dup 2)] UNSPECV_LDGP1))
6689 (unspec_volatile:DI [(match_dup 0) (match_dup 2)] UNSPECV_PLDGP2))]
6692 operands[0] = pic_offset_table_rtx;
6693 operands[1] = gen_rtx_REG (Pmode, 27);
6694 operands[2] = (TARGET_EXPLICIT_RELOCS
6695 ? GEN_INT (alpha_next_sequence_number++)
6699 (define_insn "*ldgp_er_1"
6700 [(set (match_operand:DI 0 "register_operand" "=r")
6701 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6702 (match_operand 2 "const_int_operand" "")]
6704 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6705 "ldah %0,0(%1)\t\t!gpdisp!%2"
6706 [(set_attr "cannot_copy" "true")])
6708 (define_insn "*ldgp_er_2"
6709 [(set (match_operand:DI 0 "register_operand" "=r")
6710 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
6711 (match_operand 2 "const_int_operand" "")]
6713 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6714 "lda %0,0(%1)\t\t!gpdisp!%2"
6715 [(set_attr "cannot_copy" "true")])
6717 (define_insn "*prologue_ldgp_er_2"
6718 [(set (match_operand:DI 0 "register_operand" "=r")
6719 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6720 (match_operand 2 "const_int_operand" "")]
6722 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6723 "lda %0,0(%1)\t\t!gpdisp!%2\n$%~..ng:"
6724 [(set_attr "cannot_copy" "true")])
6726 (define_insn "*prologue_ldgp_1"
6727 [(set (match_operand:DI 0 "register_operand" "=r")
6728 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6729 (match_operand 2 "const_int_operand" "")]
6732 "ldgp %0,0(%1)\n$%~..ng:"
6733 [(set_attr "cannot_copy" "true")])
6735 (define_insn "*prologue_ldgp_2"
6736 [(set (match_operand:DI 0 "register_operand" "=r")
6737 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6738 (match_operand 2 "const_int_operand" "")]
6743 ;; The _mcount profiling hook has special calling conventions, and
6744 ;; does not clobber all the registers that a normal call would. So
6745 ;; hide the fact this is a call at all.
6747 (define_insn "prologue_mcount"
6748 [(unspec_volatile [(const_int 0)] UNSPECV_MCOUNT)]
6751 if (TARGET_EXPLICIT_RELOCS)
6752 /* Note that we cannot use a lituse_jsr reloc, since _mcount
6753 cannot be called via the PLT. */
6754 return "ldq $28,_mcount($29)\t\t!literal\;jsr $28,($28),_mcount";
6756 return "lda $28,_mcount\;jsr $28,($28),_mcount";
6758 [(set_attr "type" "multi")
6759 (set_attr "length" "8")])
6761 (define_insn "init_fp"
6762 [(set (match_operand:DI 0 "register_operand" "=r")
6763 (match_operand:DI 1 "register_operand" "r"))
6764 (clobber (mem:BLK (match_operand:DI 2 "register_operand" "=r")))]
6768 (define_expand "epilogue"
6772 alpha_expand_epilogue ();
6775 (define_expand "sibcall_epilogue"
6779 alpha_expand_epilogue ();
6783 (define_expand "builtin_longjmp"
6784 [(use (match_operand:DI 0 "register_operand" "r"))]
6787 /* The elements of the buffer are, in order: */
6788 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
6789 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 8));
6790 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 16));
6791 rtx pv = gen_rtx_REG (Pmode, 27);
6793 /* This bit is the same as expand_builtin_longjmp. */
6794 emit_move_insn (hard_frame_pointer_rtx, fp);
6795 emit_move_insn (pv, lab);
6796 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
6797 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
6798 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
6800 /* Load the label we are jumping through into $27 so that we know
6801 where to look for it when we get back to setjmp's function for
6802 restoring the gp. */
6803 emit_jump_insn (gen_builtin_longjmp_internal (pv));
6808 ;; This is effectively a copy of indirect_jump, but constrained such
6809 ;; that register renaming cannot foil our cunning plan with $27.
6810 (define_insn "builtin_longjmp_internal"
6812 (unspec_volatile [(match_operand:DI 0 "register_operand" "c")]
6816 [(set_attr "type" "ibr")])
6818 (define_insn "*builtin_setjmp_receiver_er_sl_1"
6819 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6820 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && TARGET_AS_CAN_SUBTRACT_LABELS"
6821 "lda $27,$LSJ%=-%l0($27)\n$LSJ%=:")
6823 (define_insn "*builtin_setjmp_receiver_er_1"
6824 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6825 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6826 "br $27,$LSJ%=\n$LSJ%=:"
6827 [(set_attr "type" "ibr")])
6830 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6831 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
6832 && prev_nonnote_insn (insn) == operands[0]"
6836 emit_note (NOTE_INSN_DELETED);
6840 (define_insn "*builtin_setjmp_receiver_1"
6841 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6843 "br $27,$LSJ%=\n$LSJ%=:\;ldgp $29,0($27)"
6844 [(set_attr "length" "12")
6845 (set_attr "type" "multi")])
6847 (define_expand "builtin_setjmp_receiver_er"
6848 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)
6850 (unspec_volatile:DI [(match_dup 2) (match_dup 3)] UNSPECV_LDGP1))
6852 (unspec:DI [(match_dup 1) (match_dup 3)] UNSPEC_LDGP2))]
6855 operands[1] = pic_offset_table_rtx;
6856 operands[2] = gen_rtx_REG (Pmode, 27);
6857 operands[3] = GEN_INT (alpha_next_sequence_number++);
6860 (define_expand "builtin_setjmp_receiver"
6861 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6864 if (TARGET_EXPLICIT_RELOCS)
6866 emit_insn (gen_builtin_setjmp_receiver_er (operands[0]));
6871 (define_expand "exception_receiver_er"
6873 (unspec_volatile:DI [(match_dup 1) (match_dup 2)] UNSPECV_LDGP1))
6875 (unspec:DI [(match_dup 0) (match_dup 2)] UNSPEC_LDGP2))]
6878 operands[0] = pic_offset_table_rtx;
6879 operands[1] = gen_rtx_REG (Pmode, 26);
6880 operands[2] = GEN_INT (alpha_next_sequence_number++);
6883 (define_expand "exception_receiver"
6884 [(unspec_volatile [(match_dup 0)] UNSPECV_EHR)]
6887 if (TARGET_LD_BUGGY_LDGP)
6888 operands[0] = alpha_gp_save_rtx ();
6889 else if (TARGET_EXPLICIT_RELOCS)
6891 emit_insn (gen_exception_receiver_er ());
6895 operands[0] = const0_rtx;
6898 (define_insn "*exception_receiver_1"
6899 [(unspec_volatile [(const_int 0)] UNSPECV_EHR)]
6900 "! TARGET_LD_BUGGY_LDGP"
6902 [(set_attr "length" "8")
6903 (set_attr "type" "multi")])
6905 (define_insn "*exception_receiver_2"
6906 [(unspec_volatile [(match_operand:DI 0 "memory_operand" "m")] UNSPECV_EHR)]
6907 "TARGET_LD_BUGGY_LDGP"
6909 [(set_attr "type" "ild")])
6911 (define_expand "nonlocal_goto_receiver"
6912 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
6913 (set (reg:DI 27) (mem:DI (reg:DI 29)))
6914 (unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
6916 "TARGET_ABI_OPEN_VMS"
6919 (define_insn "arg_home"
6920 [(unspec [(const_int 0)] UNSPEC_ARG_HOME)
6935 (clobber (mem:BLK (const_int 0)))
6936 (clobber (reg:DI 24))
6937 (clobber (reg:DI 25))
6938 (clobber (reg:DI 0))]
6939 "TARGET_ABI_OPEN_VMS"
6940 "lda $0,OTS$HOME_ARGS\;ldq $0,8($0)\;jsr $0,OTS$HOME_ARGS"
6941 [(set_attr "length" "16")
6942 (set_attr "type" "multi")])
6944 ;; Load the CIW into r2 for calling __T3E_MISMATCH
6946 (define_expand "umk_mismatch_args"
6947 [(set:DI (match_dup 1) (mem:DI (plus:DI (reg:DI 15) (const_int -16))))
6948 (set:DI (match_dup 2) (mem:DI (plus:DI (match_dup 1) (const_int -32))))
6949 (set:DI (reg:DI 1) (match_operand:DI 0 "const_int_operand" ""))
6950 (set:DI (match_dup 3) (plus:DI (mult:DI (reg:DI 25)
6953 (set:DI (reg:DI 2) (mem:DI (match_dup 3)))]
6954 "TARGET_ABI_UNICOSMK"
6956 operands[1] = gen_reg_rtx (DImode);
6957 operands[2] = gen_reg_rtx (DImode);
6958 operands[3] = gen_reg_rtx (DImode);
6961 (define_insn "arg_home_umk"
6962 [(unspec [(const_int 0)] UNSPEC_ARG_HOME)
6977 (clobber (mem:BLK (const_int 0)))
6979 (clobber (reg:DI 22))
6980 (clobber (reg:DI 23))
6981 (clobber (reg:DI 24))
6982 (clobber (reg:DI 0))
6983 (clobber (reg:DI 1))
6984 (clobber (reg:DI 2))
6985 (clobber (reg:DI 3))
6986 (clobber (reg:DI 4))
6987 (clobber (reg:DI 5))
6988 (clobber (reg:DI 6))
6989 (clobber (reg:DI 7))
6990 (clobber (reg:DI 8))])]
6991 "TARGET_ABI_UNICOSMK"
6992 "laum $4,__T3E_MISMATCH($31)\;sll $4,32,$4\;lalm $4,__T3E_MISMATCH($4)\;lal $4,__T3E_MISMATCH($4)\;jsr $3,($4)"
6993 [(set_attr "length" "16")
6994 (set_attr "type" "multi")])
6998 ;; On EV4, these instructions are nops -- no load occurs.
7000 ;; On EV5, these instructions act as a normal load, and thus can trap
7001 ;; if the address is invalid. The OS may (or may not) handle this in
7002 ;; the entMM fault handler and suppress the fault. If so, then this
7003 ;; has the effect of a read prefetch instruction.
7005 ;; On EV6, these become official prefetch instructions.
7007 (define_insn "prefetch"
7008 [(prefetch (match_operand:DI 0 "address_operand" "p")
7009 (match_operand:DI 1 "const_int_operand" "n")
7010 (match_operand:DI 2 "const_int_operand" "n"))]
7011 "TARGET_FIXUP_EV5_PREFETCH || TARGET_CPU_EV6"
7013 /* Interpret "no temporal locality" as this data should be evicted once
7014 it is used. The "evict next" alternatives load the data into the cache
7015 and leave the LRU eviction counter pointing to that block. */
7016 static const char * const alt[2][2] = {
7018 "ldq $31,%a0", /* read, evict next */
7019 "ldl $31,%a0", /* read, evict last */
7022 "ldt $f31,%a0", /* write, evict next */
7023 "lds $f31,%a0", /* write, evict last */
7027 bool write = INTVAL (operands[1]) != 0;
7028 bool lru = INTVAL (operands[2]) != 0;
7030 return alt[write][lru];
7032 [(set_attr "type" "ild")])
7034 ;; Close the trap shadow of preceding instructions. This is generated
7037 (define_insn "trapb"
7038 [(unspec_volatile [(const_int 0)] UNSPECV_TRAPB)]
7041 [(set_attr "type" "misc")])
7043 ;; No-op instructions used by machine-dependent reorg to preserve
7044 ;; alignment for instruction issue.
7045 ;; The Unicos/Mk assembler does not support these opcodes.
7051 [(set_attr "type" "ilog")])
7056 "cpys $f31,$f31,$f31"
7057 [(set_attr "type" "fcpys")])
7064 ;; On Unicos/Mk we use a macro for aligning code.
7066 (define_insn "realign"
7067 [(unspec_volatile [(match_operand 0 "immediate_operand" "i")]
7071 if (TARGET_ABI_UNICOSMK)
7072 return "gcc@code@align %0";
7074 return ".align %0 #realign";
7077 ;; Instructions to be emitted from __builtins.
7079 (define_insn "builtin_cmpbge"
7080 [(set (match_operand:DI 0 "register_operand" "=r")
7081 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rJ")
7082 (match_operand:DI 2 "reg_or_8bit_operand" "rI")]
7086 ;; The EV6 data sheets list this as ILOG. OTOH, EV6 doesn't
7087 ;; actually differentiate between ILOG and ICMP in the schedule.
7088 [(set_attr "type" "icmp")])
7090 (define_expand "builtin_extbl"
7091 [(match_operand:DI 0 "register_operand" "")
7092 (match_operand:DI 1 "reg_or_0_operand" "")
7093 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7096 rtx (*gen) (rtx, rtx, rtx, rtx);
7097 if (WORDS_BIG_ENDIAN)
7101 emit_insn ((*gen) (operands[0], operands[1], GEN_INT (8), operands[2]));
7105 (define_expand "builtin_extwl"
7106 [(match_operand:DI 0 "register_operand" "")
7107 (match_operand:DI 1 "reg_or_0_operand" "")
7108 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7111 rtx (*gen) (rtx, rtx, rtx, rtx);
7112 if (WORDS_BIG_ENDIAN)
7116 emit_insn ((*gen) (operands[0], operands[1], GEN_INT (16), operands[2]));
7120 (define_expand "builtin_extll"
7121 [(match_operand:DI 0 "register_operand" "")
7122 (match_operand:DI 1 "reg_or_0_operand" "")
7123 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7126 rtx (*gen) (rtx, rtx, rtx, rtx);
7127 if (WORDS_BIG_ENDIAN)
7131 emit_insn ((*gen) (operands[0], operands[1], GEN_INT (32), operands[2]));
7135 (define_expand "builtin_extql"
7136 [(match_operand:DI 0 "register_operand" "")
7137 (match_operand:DI 1 "reg_or_0_operand" "")
7138 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7141 rtx (*gen) (rtx, rtx, rtx, rtx);
7142 if (WORDS_BIG_ENDIAN)
7146 emit_insn ((*gen) (operands[0], operands[1], GEN_INT (64), operands[2]));
7150 (define_expand "builtin_extwh"
7151 [(match_operand:DI 0 "register_operand" "")
7152 (match_operand:DI 1 "reg_or_0_operand" "")
7153 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7156 rtx (*gen) (rtx, rtx, rtx);
7157 if (WORDS_BIG_ENDIAN)
7161 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7165 (define_expand "builtin_extlh"
7166 [(match_operand:DI 0 "register_operand" "")
7167 (match_operand:DI 1 "reg_or_0_operand" "")
7168 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7171 rtx (*gen) (rtx, rtx, rtx);
7172 if (WORDS_BIG_ENDIAN)
7176 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7180 (define_expand "builtin_extqh"
7181 [(match_operand:DI 0 "register_operand" "")
7182 (match_operand:DI 1 "reg_or_0_operand" "")
7183 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7186 rtx (*gen) (rtx, rtx, rtx);
7187 if (WORDS_BIG_ENDIAN)
7191 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7195 (define_expand "builtin_insbl"
7196 [(match_operand:DI 0 "register_operand" "")
7197 (match_operand:DI 1 "register_operand" "")
7198 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7201 rtx (*gen) (rtx, rtx, rtx);
7202 if (WORDS_BIG_ENDIAN)
7206 operands[1] = gen_lowpart (QImode, operands[1]);
7207 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7211 (define_expand "builtin_inswl"
7212 [(match_operand:DI 0 "register_operand" "")
7213 (match_operand:DI 1 "register_operand" "")
7214 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7217 rtx (*gen) (rtx, rtx, rtx);
7218 if (WORDS_BIG_ENDIAN)
7222 operands[1] = gen_lowpart (HImode, operands[1]);
7223 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7227 (define_expand "builtin_insll"
7228 [(match_operand:DI 0 "register_operand" "")
7229 (match_operand:DI 1 "register_operand" "")
7230 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7233 rtx (*gen) (rtx, rtx, rtx);
7234 if (WORDS_BIG_ENDIAN)
7238 operands[1] = gen_lowpart (SImode, operands[1]);
7239 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7240 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7244 (define_expand "builtin_insql"
7245 [(match_operand:DI 0 "register_operand" "")
7246 (match_operand:DI 1 "reg_or_0_operand" "")
7247 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7250 rtx (*gen) (rtx, rtx, rtx);
7251 if (WORDS_BIG_ENDIAN)
7255 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7259 (define_expand "builtin_inswh"
7260 [(match_operand:DI 0 "register_operand" "")
7261 (match_operand:DI 1 "register_operand" "")
7262 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7265 emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (16), operands[2]));
7269 (define_expand "builtin_inslh"
7270 [(match_operand:DI 0 "register_operand" "")
7271 (match_operand:DI 1 "register_operand" "")
7272 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7275 emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (32), operands[2]));
7279 (define_expand "builtin_insqh"
7280 [(match_operand:DI 0 "register_operand" "")
7281 (match_operand:DI 1 "register_operand" "")
7282 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7285 emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (64), operands[2]));
7289 (define_expand "builtin_mskbl"
7290 [(match_operand:DI 0 "register_operand" "")
7291 (match_operand:DI 1 "reg_or_0_operand" "")
7292 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7295 rtx (*gen) (rtx, rtx, rtx, rtx);
7297 if (WORDS_BIG_ENDIAN)
7301 mask = GEN_INT (0xff);
7302 emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
7306 (define_expand "builtin_mskwl"
7307 [(match_operand:DI 0 "register_operand" "")
7308 (match_operand:DI 1 "reg_or_0_operand" "")
7309 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7312 rtx (*gen) (rtx, rtx, rtx, rtx);
7314 if (WORDS_BIG_ENDIAN)
7318 mask = GEN_INT (0xffff);
7319 emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
7323 (define_expand "builtin_mskll"
7324 [(match_operand:DI 0 "register_operand" "")
7325 (match_operand:DI 1 "reg_or_0_operand" "")
7326 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7329 rtx (*gen) (rtx, rtx, rtx, rtx);
7331 if (WORDS_BIG_ENDIAN)
7335 mask = immed_double_const (0xffffffff, 0, DImode);
7336 emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
7340 (define_expand "builtin_mskql"
7341 [(match_operand:DI 0 "register_operand" "")
7342 (match_operand:DI 1 "reg_or_0_operand" "")
7343 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7346 rtx (*gen) (rtx, rtx, rtx, rtx);
7348 if (WORDS_BIG_ENDIAN)
7353 emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
7357 (define_expand "builtin_mskwh"
7358 [(match_operand:DI 0 "register_operand" "")
7359 (match_operand:DI 1 "register_operand" "")
7360 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7363 emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (16), operands[2]));
7367 (define_expand "builtin_msklh"
7368 [(match_operand:DI 0 "register_operand" "")
7369 (match_operand:DI 1 "register_operand" "")
7370 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7373 emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (32), operands[2]));
7377 (define_expand "builtin_mskqh"
7378 [(match_operand:DI 0 "register_operand" "")
7379 (match_operand:DI 1 "register_operand" "")
7380 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7383 emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (64), operands[2]));
7387 (define_expand "builtin_zap"
7388 [(set (match_operand:DI 0 "register_operand" "")
7390 [(match_operand:DI 2 "reg_or_cint_operand" "")]
7392 (match_operand:DI 1 "reg_or_cint_operand" "")))]
7395 if (GET_CODE (operands[2]) == CONST_INT)
7397 rtx mask = alpha_expand_zap_mask (INTVAL (operands[2]));
7399 if (mask == const0_rtx)
7401 emit_move_insn (operands[0], const0_rtx);
7404 if (mask == constm1_rtx)
7406 emit_move_insn (operands[0], operands[1]);
7410 operands[1] = force_reg (DImode, operands[1]);
7411 emit_insn (gen_anddi3 (operands[0], operands[1], mask));
7415 operands[1] = force_reg (DImode, operands[1]);
7416 operands[2] = gen_lowpart (QImode, operands[2]);
7419 (define_insn "*builtin_zap_1"
7420 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
7422 [(match_operand:QI 2 "reg_or_cint_operand" "n,n,r,r")]
7424 (match_operand:DI 1 "reg_or_cint_operand" "n,r,J,r")))]
7431 [(set_attr "type" "shift,shift,ilog,shift")])
7434 [(set (match_operand:DI 0 "register_operand" "")
7436 [(match_operand:QI 2 "const_int_operand" "")]
7438 (match_operand:DI 1 "const_int_operand" "")))]
7442 rtx mask = alpha_expand_zap_mask (INTVAL (operands[2]));
7443 if (HOST_BITS_PER_WIDE_INT >= 64 || GET_CODE (mask) == CONST_INT)
7444 operands[1] = gen_int_mode (INTVAL (operands[1]) & INTVAL (mask), DImode);
7447 HOST_WIDE_INT c_lo = INTVAL (operands[1]);
7448 HOST_WIDE_INT c_hi = (c_lo < 0 ? -1 : 0);
7449 operands[1] = immed_double_const (c_lo & CONST_DOUBLE_LOW (mask),
7450 c_hi & CONST_DOUBLE_HIGH (mask),
7453 emit_move_insn (operands[0], operands[1]);
7458 [(set (match_operand:DI 0 "register_operand" "")
7460 [(match_operand:QI 2 "const_int_operand" "")]
7462 (match_operand:DI 1 "register_operand" "")))]
7465 (and:DI (match_dup 1) (match_dup 2)))]
7467 operands[2] = alpha_expand_zap_mask (INTVAL (operands[2]));
7468 if (operands[2] == const0_rtx)
7470 emit_move_insn (operands[0], const0_rtx);
7473 if (operands[2] == constm1_rtx)
7475 emit_move_insn (operands[0], operands[1]);
7480 (define_expand "builtin_zapnot"
7481 [(set (match_operand:DI 0 "register_operand" "")
7483 [(not:QI (match_operand:DI 2 "reg_or_cint_operand" ""))]
7485 (match_operand:DI 1 "reg_or_cint_operand" "")))]
7488 if (GET_CODE (operands[2]) == CONST_INT)
7490 rtx mask = alpha_expand_zap_mask (~ INTVAL (operands[2]));
7492 if (mask == const0_rtx)
7494 emit_move_insn (operands[0], const0_rtx);
7497 if (mask == constm1_rtx)
7499 emit_move_insn (operands[0], operands[1]);
7503 operands[1] = force_reg (DImode, operands[1]);
7504 emit_insn (gen_anddi3 (operands[0], operands[1], mask));
7508 operands[1] = force_reg (DImode, operands[1]);
7509 operands[2] = gen_lowpart (QImode, operands[2]);
7512 (define_insn "*builtin_zapnot_1"
7513 [(set (match_operand:DI 0 "register_operand" "=r")
7515 [(not:QI (match_operand:QI 2 "register_operand" "r"))]
7517 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
7520 [(set_attr "type" "shift")])
7522 (define_insn "builtin_amask"
7523 [(set (match_operand:DI 0 "register_operand" "=r")
7524 (unspec:DI [(match_operand:DI 1 "reg_or_8bit_operand" "rI")]
7528 [(set_attr "type" "ilog")])
7530 (define_insn "builtin_implver"
7531 [(set (match_operand:DI 0 "register_operand" "=r")
7532 (unspec:DI [(const_int 0)] UNSPEC_IMPLVER))]
7535 [(set_attr "type" "ilog")])
7537 (define_insn "builtin_rpcc"
7538 [(set (match_operand:DI 0 "register_operand" "=r")
7539 (unspec_volatile:DI [(const_int 0)] UNSPECV_RPCC))]
7542 [(set_attr "type" "ilog")])
7544 (define_expand "builtin_minub8"
7545 [(match_operand:DI 0 "register_operand" "")
7546 (match_operand:DI 1 "reg_or_0_operand" "")
7547 (match_operand:DI 2 "reg_or_0_operand" "")]
7550 alpha_expand_builtin_vector_binop (gen_uminv8qi3, V8QImode, operands[0],
7551 operands[1], operands[2]);
7555 (define_expand "builtin_minsb8"
7556 [(match_operand:DI 0 "register_operand" "")
7557 (match_operand:DI 1 "reg_or_0_operand" "")
7558 (match_operand:DI 2 "reg_or_0_operand" "")]
7561 alpha_expand_builtin_vector_binop (gen_sminv8qi3, V8QImode, operands[0],
7562 operands[1], operands[2]);
7566 (define_expand "builtin_minuw4"
7567 [(match_operand:DI 0 "register_operand" "")
7568 (match_operand:DI 1 "reg_or_0_operand" "")
7569 (match_operand:DI 2 "reg_or_0_operand" "")]
7572 alpha_expand_builtin_vector_binop (gen_uminv4hi3, V4HImode, operands[0],
7573 operands[1], operands[2]);
7577 (define_expand "builtin_minsw4"
7578 [(match_operand:DI 0 "register_operand" "")
7579 (match_operand:DI 1 "reg_or_0_operand" "")
7580 (match_operand:DI 2 "reg_or_0_operand" "")]
7583 alpha_expand_builtin_vector_binop (gen_sminv4hi3, V4HImode, operands[0],
7584 operands[1], operands[2]);
7588 (define_expand "builtin_maxub8"
7589 [(match_operand:DI 0 "register_operand" "")
7590 (match_operand:DI 1 "reg_or_0_operand" "")
7591 (match_operand:DI 2 "reg_or_0_operand" "")]
7594 alpha_expand_builtin_vector_binop (gen_umaxv8qi3, V8QImode, operands[0],
7595 operands[1], operands[2]);
7599 (define_expand "builtin_maxsb8"
7600 [(match_operand:DI 0 "register_operand" "")
7601 (match_operand:DI 1 "reg_or_0_operand" "")
7602 (match_operand:DI 2 "reg_or_0_operand" "")]
7605 alpha_expand_builtin_vector_binop (gen_smaxv8qi3, V8QImode, operands[0],
7606 operands[1], operands[2]);
7610 (define_expand "builtin_maxuw4"
7611 [(match_operand:DI 0 "register_operand" "")
7612 (match_operand:DI 1 "reg_or_0_operand" "")
7613 (match_operand:DI 2 "reg_or_0_operand" "")]
7616 alpha_expand_builtin_vector_binop (gen_umaxv4hi3, V4HImode, operands[0],
7617 operands[1], operands[2]);
7621 (define_expand "builtin_maxsw4"
7622 [(match_operand:DI 0 "register_operand" "")
7623 (match_operand:DI 1 "reg_or_0_operand" "")
7624 (match_operand:DI 2 "reg_or_0_operand" "")]
7627 alpha_expand_builtin_vector_binop (gen_smaxv4hi3, V4HImode, operands[0],
7628 operands[1], operands[2]);
7632 (define_insn "builtin_perr"
7633 [(set (match_operand:DI 0 "register_operand" "=r")
7634 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "%rJ")
7635 (match_operand:DI 2 "reg_or_8bit_operand" "rJ")]
7639 [(set_attr "type" "mvi")])
7641 (define_expand "builtin_pklb"
7642 [(set (match_operand:DI 0 "register_operand" "")
7645 (truncate:V2QI (match_operand:DI 1 "register_operand" ""))
7650 operands[0] = gen_lowpart (V8QImode, operands[0]);
7651 operands[1] = gen_lowpart (V2SImode, operands[1]);
7652 operands[2] = CONST0_RTX (V2QImode);
7653 operands[3] = CONST0_RTX (V4QImode);
7656 (define_insn "*pklb"
7657 [(set (match_operand:V8QI 0 "register_operand" "=r")
7660 (truncate:V2QI (match_operand:V2SI 1 "register_operand" "r"))
7661 (match_operand:V2QI 2 "const0_operand" ""))
7662 (match_operand:V4QI 3 "const0_operand" "")))]
7665 [(set_attr "type" "mvi")])
7667 (define_expand "builtin_pkwb"
7668 [(set (match_operand:DI 0 "register_operand" "")
7670 (truncate:V4QI (match_operand:DI 1 "register_operand" ""))
7674 operands[0] = gen_lowpart (V8QImode, operands[0]);
7675 operands[1] = gen_lowpart (V4HImode, operands[1]);
7676 operands[2] = CONST0_RTX (V4QImode);
7679 (define_insn "*pkwb"
7680 [(set (match_operand:V8QI 0 "register_operand" "=r")
7682 (truncate:V4QI (match_operand:V4HI 1 "register_operand" "r"))
7683 (match_operand:V4QI 2 "const0_operand" "")))]
7686 [(set_attr "type" "mvi")])
7688 (define_expand "builtin_unpkbl"
7689 [(set (match_operand:DI 0 "register_operand" "")
7691 (vec_select:V2QI (match_operand:DI 1 "register_operand" "")
7692 (parallel [(const_int 0) (const_int 1)]))))]
7695 operands[0] = gen_lowpart (V2SImode, operands[0]);
7696 operands[1] = gen_lowpart (V8QImode, operands[1]);
7699 (define_insn "*unpkbl"
7700 [(set (match_operand:V2SI 0 "register_operand" "=r")
7702 (vec_select:V2QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
7703 (parallel [(const_int 0) (const_int 1)]))))]
7706 [(set_attr "type" "mvi")])
7708 (define_expand "builtin_unpkbw"
7709 [(set (match_operand:DI 0 "register_operand" "")
7711 (vec_select:V4QI (match_operand:DI 1 "register_operand" "")
7712 (parallel [(const_int 0)
7718 operands[0] = gen_lowpart (V4HImode, operands[0]);
7719 operands[1] = gen_lowpart (V8QImode, operands[1]);
7722 (define_insn "*unpkbw"
7723 [(set (match_operand:V4HI 0 "register_operand" "=r")
7725 (vec_select:V4QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
7726 (parallel [(const_int 0)
7732 [(set_attr "type" "mvi")])
7734 (define_expand "builtin_cttz"
7735 [(set (match_operand:DI 0 "register_operand" "")
7736 (unspec:DI [(match_operand:DI 1 "register_operand" "")]
7741 (define_insn "builtin_ctlz"
7742 [(set (match_operand:DI 0 "register_operand" "=r")
7743 (unspec:DI [(match_operand:DI 1 "register_operand" "r")]
7747 [(set_attr "type" "mvi")])
7749 (define_insn "builtin_ctpop"
7750 [(set (match_operand:DI 0 "register_operand" "=r")
7751 (unspec:DI [(match_operand:DI 1 "register_operand" "r")]
7755 [(set_attr "type" "mvi")])
7757 ;; The call patterns are at the end of the file because their
7758 ;; wildcard operand0 interferes with nice recognition.
7760 (define_insn "*call_value_osf_1_er"
7761 [(set (match_operand 0 "" "")
7762 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
7763 (match_operand 2 "" "")))
7765 (clobber (reg:DI 26))]
7766 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
7768 jsr $26,(%1),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*
7769 bsr $26,%1\t\t!samegp
7770 ldq $27,%1($29)\t\t!literal!%#\;jsr $26,($27),0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*"
7771 [(set_attr "type" "jsr")
7772 (set_attr "length" "12,*,16")])
7774 ;; We must use peep2 instead of a split because we need accurate life
7775 ;; information for $gp. Consider the case of { bar(); while (1); }.
7777 [(parallel [(set (match_operand 0 "" "")
7778 (call (mem:DI (match_operand:DI 1 "call_operand" ""))
7779 (match_operand 2 "" "")))
7781 (clobber (reg:DI 26))])]
7782 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
7783 && ! samegp_function_operand (operands[1], Pmode)
7784 && (peep2_regno_dead_p (1, 29)
7785 || find_reg_note (insn, REG_NORETURN, NULL_RTX))"
7786 [(parallel [(set (match_dup 0)
7787 (call (mem:DI (match_dup 3))
7789 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
7790 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
7792 (use (match_dup 4))])]
7794 if (CONSTANT_P (operands[1]))
7796 operands[3] = gen_rtx_REG (Pmode, 27);
7797 operands[4] = GEN_INT (alpha_next_sequence_number++);
7798 emit_insn (gen_movdi_er_high_g (operands[3], pic_offset_table_rtx,
7799 operands[1], operands[4]));
7803 operands[3] = operands[1];
7804 operands[1] = const0_rtx;
7805 operands[4] = const0_rtx;
7810 [(parallel [(set (match_operand 0 "" "")
7811 (call (mem:DI (match_operand:DI 1 "call_operand" ""))
7812 (match_operand 2 "" "")))
7814 (clobber (reg:DI 26))])]
7815 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
7816 && ! samegp_function_operand (operands[1], Pmode)
7817 && ! (peep2_regno_dead_p (1, 29)
7818 || find_reg_note (insn, REG_NORETURN, NULL_RTX))"
7819 [(parallel [(set (match_dup 0)
7820 (call (mem:DI (match_dup 3))
7822 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
7823 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
7825 (use (match_dup 5))])
7827 (unspec_volatile:DI [(reg:DI 26) (match_dup 4)] UNSPECV_LDGP1))
7829 (unspec:DI [(reg:DI 29) (match_dup 4)] UNSPEC_LDGP2))]
7831 if (CONSTANT_P (operands[1]))
7833 operands[3] = gen_rtx_REG (Pmode, 27);
7834 operands[5] = GEN_INT (alpha_next_sequence_number++);
7835 emit_insn (gen_movdi_er_high_g (operands[3], pic_offset_table_rtx,
7836 operands[1], operands[5]));
7840 operands[3] = operands[1];
7841 operands[1] = const0_rtx;
7842 operands[5] = const0_rtx;
7844 operands[4] = GEN_INT (alpha_next_sequence_number++);
7847 ;; We add a blockage unspec_volatile to prevent insns from moving down
7848 ;; from above the call to in between the call and the ldah gpdisp.
7849 (define_insn "*call_value_osf_2_er"
7850 [(set (match_operand 0 "" "")
7851 (call (mem:DI (match_operand:DI 1 "register_operand" "c"))
7852 (match_operand 2 "" "")))
7854 (plus:DI (pc) (const_int 4)))
7855 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
7856 (use (match_operand 3 "" ""))
7857 (use (match_operand 4 "" ""))]
7858 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
7859 "jsr $26,(%1),%3%J4"
7860 [(set_attr "type" "jsr")
7861 (set_attr "cannot_copy" "true")])
7863 (define_insn "*call_value_osf_1_noreturn"
7864 [(set (match_operand 0 "" "")
7865 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
7866 (match_operand 2 "" "")))
7868 (clobber (reg:DI 26))]
7869 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
7870 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7875 [(set_attr "type" "jsr")
7876 (set_attr "length" "*,*,8")])
7878 (define_insn_and_split "call_value_osf_tlsgd"
7879 [(set (match_operand 0 "" "")
7880 (call (mem:DI (match_operand:DI 1 "symbolic_operand" ""))
7882 (unspec [(match_operand:DI 2 "const_int_operand" "")] UNSPEC_TLSGD_CALL)
7884 (clobber (reg:DI 26))]
7887 "&& reload_completed"
7889 (unspec:DI [(match_dup 5)
7891 (match_dup 2)] UNSPEC_LITERAL))
7892 (parallel [(set (match_dup 0)
7893 (call (mem:DI (match_dup 3))
7895 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
7896 (unspec_volatile [(match_dup 5)] UNSPECV_BLOCKAGE)
7898 (use (unspec [(match_dup 2)] UNSPEC_TLSGD_CALL))])
7900 (unspec_volatile:DI [(reg:DI 26) (match_dup 4)] UNSPECV_LDGP1))
7902 (unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP2))]
7904 operands[3] = gen_rtx_REG (Pmode, 27);
7905 operands[4] = GEN_INT (alpha_next_sequence_number++);
7906 operands[5] = pic_offset_table_rtx;
7908 [(set_attr "type" "multi")])
7910 (define_insn_and_split "call_value_osf_tlsldm"
7911 [(set (match_operand 0 "" "")
7912 (call (mem:DI (match_operand:DI 1 "symbolic_operand" ""))
7914 (unspec [(match_operand:DI 2 "const_int_operand" "")] UNSPEC_TLSLDM_CALL)
7916 (clobber (reg:DI 26))]
7919 "&& reload_completed"
7921 (unspec:DI [(match_dup 5)
7923 (match_dup 2)] UNSPEC_LITERAL))
7924 (parallel [(set (match_dup 0)
7925 (call (mem:DI (match_dup 3))
7927 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
7928 (unspec_volatile [(match_dup 5)] UNSPECV_BLOCKAGE)
7930 (use (unspec [(match_dup 2)] UNSPEC_TLSLDM_CALL))])
7932 (unspec_volatile:DI [(reg:DI 26) (match_dup 4)] UNSPECV_LDGP1))
7934 (unspec:DI [(reg:DI 29) (match_dup 4)] UNSPEC_LDGP2))]
7936 operands[3] = gen_rtx_REG (Pmode, 27);
7937 operands[4] = GEN_INT (alpha_next_sequence_number++);
7938 operands[5] = pic_offset_table_rtx;
7940 [(set_attr "type" "multi")])
7942 (define_insn "*call_value_osf_1"
7943 [(set (match_operand 0 "" "")
7944 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
7945 (match_operand 2 "" "")))
7947 (clobber (reg:DI 26))]
7948 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
7950 jsr $26,($27),0\;ldgp $29,0($26)
7952 jsr $26,%1\;ldgp $29,0($26)"
7953 [(set_attr "type" "jsr")
7954 (set_attr "length" "12,*,16")])
7956 (define_insn "*sibcall_value_osf_1_er"
7957 [(set (match_operand 0 "" "")
7958 (call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s"))
7959 (match_operand 2 "" "")))
7960 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
7961 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
7963 br $31,%1\t\t!samegp
7964 ldq $27,%1($29)\t\t!literal!%#\;jmp $31,($27),%1\t\t!lituse_jsr!%#"
7965 [(set_attr "type" "jsr")
7966 (set_attr "length" "*,8")])
7968 (define_insn "*sibcall_value_osf_1"
7969 [(set (match_operand 0 "" "")
7970 (call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s"))
7971 (match_operand 2 "" "")))
7972 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
7973 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
7976 lda $27,%1\;jmp $31,($27),%1"
7977 [(set_attr "type" "jsr")
7978 (set_attr "length" "*,8")])
7980 (define_insn "*call_value_nt_1"
7981 [(set (match_operand 0 "" "")
7982 (call (mem:DI (match_operand:DI 1 "call_operand" "r,R,s"))
7983 (match_operand 2 "" "")))
7984 (clobber (reg:DI 26))]
7985 "TARGET_ABI_WINDOWS_NT"
7990 [(set_attr "type" "jsr")
7991 (set_attr "length" "*,*,12")])
7993 ; GAS relies on the order and position of instructions output below in order
7994 ; to generate relocs for VMS link to potentially optimize the call.
7995 ; Please do not molest.
7996 (define_insn "*call_value_vms_1"
7997 [(set (match_operand 0 "" "")
7998 (call (mem:DI (match_operand:DI 1 "call_operand" "r,s"))
7999 (match_operand 2 "" "")))
8000 (use (match_operand:DI 3 "nonmemory_operand" "r,n"))
8003 (clobber (reg:DI 27))]
8004 "TARGET_ABI_OPEN_VMS"
8006 switch (which_alternative)
8009 return "mov %3,$27\;jsr $26,0\;ldq $27,0($29)";
8011 operands [3] = alpha_use_linkage (operands [1], cfun->decl, 1, 0);
8012 operands [4] = alpha_use_linkage (operands [1], cfun->decl, 0, 0);
8013 return "ldq $26,%4\;ldq $27,%3\;jsr $26,%1\;ldq $27,0($29)";
8018 [(set_attr "type" "jsr")
8019 (set_attr "length" "12,16")])
8021 (define_insn "*call_value_umk"
8022 [(set (match_operand 0 "" "")
8023 (call (mem:DI (match_operand:DI 1 "call_operand" "r"))
8024 (match_operand 2 "" "")))
8026 (clobber (reg:DI 26))]
8027 "TARGET_ABI_UNICOSMK"
8029 [(set_attr "type" "jsr")])