1 ;; Machine description for DEC Alpha for GNU C compiler
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 ;; 2000, 2001 Free Software Foundation, Inc.
4 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 ;; This file is part of GNU CC.
8 ;; GNU CC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 2, or (at your option)
13 ;; GNU CC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GNU CC; see the file COPYING. If not, write to
20 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
21 ;; Boston, MA 02111-1307, USA.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;; Uses of UNSPEC in this file:
37 (UNSPEC_UMK_LOAD_CIW 9)
50 (UNSPECV_SETJMPR 2) ; builtin_setjmp_receiver
51 (UNSPECV_LONGJMP 3) ; builtin_longjmp
53 (UNSPECV_PSPL 5) ; prologue_stack_probe_loop
55 (UNSPECV_EHR 7) ; exception_receiver
59 (UNSPECV_PLDGP2 11) ; prologue ldgp
62 ;; Where necessary, the suffixes _le and _be are used to distinguish between
63 ;; little-endian and big-endian patterns.
65 ;; Note that the Unicos/Mk assembler does not support the following
66 ;; opcodes: mov, fmov, nop, fnop, unop.
68 ;; Processor type -- this attribute must exactly match the processor_type
69 ;; enumeration in alpha.h.
71 (define_attr "cpu" "ev4,ev5,ev6"
72 (const (symbol_ref "alpha_cpu")))
74 ;; Define an insn type attribute. This is used in function unit delay
75 ;; computations, among other purposes. For the most part, we use the names
76 ;; defined in the EV4 documentation, but add a few that we have to know about
80 "ild,fld,ldsym,ist,fst,ibr,fbr,jsr,iadd,ilog,shift,icmov,fcmov,icmp,imul,\
81 fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
82 (const_string "iadd"))
84 ;; Describe a user's asm statement.
85 (define_asm_attributes
86 [(set_attr "type" "multi")])
88 ;; Define the operand size an insn operates on. Used primarily by mul
89 ;; and div operations that have size dependent timings.
91 (define_attr "opsize" "si,di,udi"
94 ;; The TRAP attribute marks instructions that may generate traps
95 ;; (which are imprecise and may need a trapb if software completion
98 (define_attr "trap" "no,yes"
101 ;; The ROUND_SUFFIX attribute marks which instructions require a
102 ;; rounding-mode suffix. The value NONE indicates no suffix,
103 ;; the value NORMAL indicates a suffix controled by alpha_fprm.
105 (define_attr "round_suffix" "none,normal,c"
106 (const_string "none"))
108 ;; The TRAP_SUFFIX attribute marks instructions requiring a trap-mode suffix:
110 ;; SU accepts only /su (cmpt et al)
111 ;; SUI accepts only /sui (cvtqt and cvtqs)
112 ;; V_SV accepts /v and /sv (cvtql only)
113 ;; V_SV_SVI accepts /v, /sv and /svi (cvttq only)
114 ;; U_SU_SUI accepts /u, /su and /sui (most fp instructions)
116 ;; The actual suffix emitted is controled by alpha_fptm.
118 (define_attr "trap_suffix" "none,su,sui,v_sv,v_sv_svi,u_su_sui"
119 (const_string "none"))
121 ;; The length of an instruction sequence in bytes.
123 (define_attr "length" ""
126 ;; Include scheduling descriptions.
132 ;; First define the arithmetic insns. Note that the 32-bit forms also
135 ;; Handle 32-64 bit extension from memory to a floating point register
136 ;; specially, since this occurs frequently in int->double conversions.
138 ;; Note that while we must retain the =f case in the insn for reload's
139 ;; benefit, it should be eliminated after reload, so we should never emit
140 ;; code for that case. But we don't reject the possibility.
142 (define_expand "extendsidi2"
143 [(set (match_operand:DI 0 "register_operand" "")
144 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
148 (define_insn "*extendsidi2_nofix"
149 [(set (match_operand:DI 0 "register_operand" "=r,r,*f,?*f")
151 (match_operand:SI 1 "nonimmediate_operand" "r,m,*f,m")))]
157 lds %0,%1\;cvtlq %0,%0"
158 [(set_attr "type" "iadd,ild,fadd,fld")
159 (set_attr "length" "*,*,*,8")])
161 (define_insn "*extendsidi2_fix"
162 [(set (match_operand:DI 0 "register_operand" "=r,r,r,?*f,?*f")
164 (match_operand:SI 1 "nonimmediate_operand" "r,m,*f,*f,m")))]
171 lds %0,%1\;cvtlq %0,%0"
172 [(set_attr "type" "iadd,ild,ftoi,fadd,fld")
173 (set_attr "length" "*,*,*,*,8")])
175 ;; Due to issues with CLASS_CANNOT_CHANGE_SIZE, we cannot use a subreg here.
177 [(set (match_operand:DI 0 "hard_fp_register_operand" "")
178 (sign_extend:DI (match_operand:SI 1 "memory_operand" "")))]
180 [(set (match_dup 2) (match_dup 1))
181 (set (match_dup 0) (sign_extend:DI (match_dup 2)))]
182 "operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]));")
184 ;; Optimize sign-extension of SImode loads. This shows up in the wake of
185 ;; reload when converting fp->int.
188 [(set (match_operand:SI 0 "hard_int_register_operand" "")
189 (match_operand:SI 1 "memory_operand" ""))
190 (set (match_operand:DI 2 "hard_int_register_operand" "")
191 (sign_extend:DI (match_dup 0)))]
192 "true_regnum (operands[0]) == true_regnum (operands[2])
193 || peep2_reg_dead_p (2, operands[0])"
195 (sign_extend:DI (match_dup 1)))]
199 [(set (match_operand:SI 0 "hard_int_register_operand" "")
200 (match_operand:SI 1 "hard_fp_register_operand" ""))
201 (set (match_operand:DI 2 "hard_int_register_operand" "")
202 (sign_extend:DI (match_dup 0)))]
204 && (true_regnum (operands[0]) == true_regnum (operands[2])
205 || peep2_reg_dead_p (2, operands[0]))"
207 (sign_extend:DI (match_dup 1)))]
211 [(set (match_operand:DI 0 "hard_fp_register_operand" "")
212 (sign_extend:DI (match_operand:SI 1 "hard_fp_register_operand" "")))
213 (set (match_operand:DI 2 "hard_int_register_operand" "")
215 "TARGET_FIX && peep2_reg_dead_p (2, operands[0])"
217 (sign_extend:DI (match_dup 1)))]
220 ;; Don't say we have addsi3 if optimizing. This generates better code. We
221 ;; have the anonymous addsi3 pattern below in case combine wants to make it.
222 (define_expand "addsi3"
223 [(set (match_operand:SI 0 "register_operand" "")
224 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "")
225 (match_operand:SI 2 "add_operand" "")))]
229 (define_insn "*addsi_internal"
230 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
231 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ")
232 (match_operand:SI 2 "add_operand" "rI,O,K,L")))]
241 [(set (match_operand:SI 0 "register_operand" "")
242 (plus:SI (match_operand:SI 1 "register_operand" "")
243 (match_operand:SI 2 "const_int_operand" "")))]
244 "! add_operand (operands[2], SImode)"
245 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
246 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
248 HOST_WIDE_INT val = INTVAL (operands[2]);
249 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
250 HOST_WIDE_INT rest = val - low;
252 operands[3] = GEN_INT (rest);
253 operands[4] = GEN_INT (low);
256 (define_insn "*addsi_se"
257 [(set (match_operand:DI 0 "register_operand" "=r,r")
259 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
260 (match_operand:SI 2 "sext_add_operand" "rI,O"))))]
266 (define_insn "*addsi_se2"
267 [(set (match_operand:DI 0 "register_operand" "=r,r")
269 (subreg:SI (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
270 (match_operand:DI 2 "sext_add_operand" "rI,O"))
278 [(set (match_operand:DI 0 "register_operand" "")
280 (plus:SI (match_operand:SI 1 "reg_not_elim_operand" "")
281 (match_operand:SI 2 "const_int_operand" ""))))
282 (clobber (match_operand:SI 3 "reg_not_elim_operand" ""))]
283 "! sext_add_operand (operands[2], SImode) && INTVAL (operands[2]) > 0
284 && INTVAL (operands[2]) % 4 == 0"
285 [(set (match_dup 3) (match_dup 4))
286 (set (match_dup 0) (sign_extend:DI (plus:SI (mult:SI (match_dup 3)
290 HOST_WIDE_INT val = INTVAL (operands[2]) / 4;
296 operands[4] = GEN_INT (val);
297 operands[5] = GEN_INT (mult);
301 [(set (match_operand:DI 0 "register_operand" "")
303 (plus:SI (match_operator:SI 1 "comparison_operator"
304 [(match_operand 2 "" "")
305 (match_operand 3 "" "")])
306 (match_operand:SI 4 "add_operand" ""))))
307 (clobber (match_operand:DI 5 "register_operand" ""))]
309 [(set (match_dup 5) (match_dup 6))
310 (set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 7) (match_dup 4))))]
312 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
313 operands[2], operands[3]);
314 operands[7] = gen_lowpart (SImode, operands[5]);
317 (define_insn "addvsi3"
318 [(set (match_operand:SI 0 "register_operand" "=r,r")
319 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
320 (match_operand:SI 2 "sext_add_operand" "rI,O")))
321 (trap_if (ne (plus:DI (sign_extend:DI (match_dup 1))
322 (sign_extend:DI (match_dup 2)))
323 (sign_extend:DI (plus:SI (match_dup 1)
331 (define_expand "adddi3"
332 [(set (match_operand:DI 0 "register_operand" "")
333 (plus:DI (match_operand:DI 1 "register_operand" "")
334 (match_operand:DI 2 "add_operand" "")))]
338 (define_insn "*adddi_er_high_l"
339 [(set (match_operand:DI 0 "register_operand" "=r")
340 (plus:DI (match_operand:DI 1 "register_operand" "r")
341 (high:DI (match_operand:DI 2 "local_symbolic_operand" ""))))]
342 "TARGET_EXPLICIT_RELOCS"
343 "ldah %0,%2(%1)\t\t!gprelhigh")
346 [(set (match_operand:DI 0 "register_operand" "")
347 (high:DI (match_operand:DI 1 "local_symbolic_operand" "")))]
348 "TARGET_EXPLICIT_RELOCS && reload_completed"
350 (plus:DI (match_dup 2) (high:DI (match_dup 1))))]
351 "operands[2] = pic_offset_table_rtx;")
353 ;; We used to expend quite a lot of effort choosing addq/subq/lda.
354 ;; With complications like
356 ;; The NT stack unwind code can't handle a subq to adjust the stack
357 ;; (that's a bug, but not one we can do anything about). As of NT4.0 SP3,
358 ;; the exception handling code will loop if a subq is used and an
361 ;; The 19980616 change to emit prologues as RTL also confused some
362 ;; versions of GDB, which also interprets prologues. This has been
363 ;; fixed as of GDB 4.18, but it does not harm to unconditionally
366 ;; and the fact that the three insns schedule exactly the same, it's
367 ;; just not worth the effort.
369 (define_insn "*adddi_internal"
370 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
371 (plus:DI (match_operand:DI 1 "register_operand" "%r,r,r")
372 (match_operand:DI 2 "add_operand" "r,K,L")))]
379 ;; ??? Allow large constants when basing off the frame pointer or some
380 ;; virtual register that may eliminate to the frame pointer. This is
381 ;; done because register elimination offsets will change the hi/lo split,
382 ;; and if we split before reload, we will require additional instructions.
384 (define_insn "*adddi_fp_hack"
385 [(set (match_operand:DI 0 "register_operand" "=r")
386 (plus:DI (match_operand:DI 1 "reg_no_subreg_operand" "r")
387 (match_operand:DI 2 "const_int_operand" "n")))]
388 "NONSTRICT_REG_OK_FP_BASE_P (operands[1])
389 && INTVAL (operands[2]) >= 0
390 /* This is the largest constant an lda+ldah pair can add, minus
391 an upper bound on the displacement between SP and AP during
392 register elimination. See INITIAL_ELIMINATION_OFFSET. */
393 && INTVAL (operands[2])
395 - FIRST_PSEUDO_REGISTER * UNITS_PER_WORD
396 - ALPHA_ROUND(current_function_outgoing_args_size)
397 - (ALPHA_ROUND (get_frame_size ()
398 + max_reg_num () * UNITS_PER_WORD
399 + current_function_pretend_args_size)
400 - current_function_pretend_args_size))"
403 ;; Don't do this if we are adjusting SP since we don't want to do it
404 ;; in two steps. Don't split FP sources for the reason listed above.
406 [(set (match_operand:DI 0 "register_operand" "")
407 (plus:DI (match_operand:DI 1 "register_operand" "")
408 (match_operand:DI 2 "const_int_operand" "")))]
409 "! add_operand (operands[2], DImode)
410 && operands[0] != stack_pointer_rtx
411 && operands[1] != frame_pointer_rtx
412 && operands[1] != arg_pointer_rtx"
413 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
414 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
416 HOST_WIDE_INT val = INTVAL (operands[2]);
417 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
418 HOST_WIDE_INT rest = val - low;
420 operands[4] = GEN_INT (low);
421 if (CONST_OK_FOR_LETTER_P (rest, 'L'))
422 operands[3] = GEN_INT (rest);
423 else if (! no_new_pseudos)
425 operands[3] = gen_reg_rtx (DImode);
426 emit_move_insn (operands[3], operands[2]);
427 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
434 (define_insn "*saddl"
435 [(set (match_operand:SI 0 "register_operand" "=r,r")
436 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
437 (match_operand:SI 2 "const48_operand" "I,I"))
438 (match_operand:SI 3 "sext_add_operand" "rI,O")))]
444 (define_insn "*saddl_se"
445 [(set (match_operand:DI 0 "register_operand" "=r,r")
447 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
448 (match_operand:SI 2 "const48_operand" "I,I"))
449 (match_operand:SI 3 "sext_add_operand" "rI,O"))))]
456 [(set (match_operand:DI 0 "register_operand" "")
458 (plus:SI (mult:SI (match_operator:SI 1 "comparison_operator"
459 [(match_operand 2 "" "")
460 (match_operand 3 "" "")])
461 (match_operand:SI 4 "const48_operand" ""))
462 (match_operand:SI 5 "sext_add_operand" ""))))
463 (clobber (match_operand:DI 6 "reg_not_elim_operand" ""))]
465 [(set (match_dup 6) (match_dup 7))
467 (sign_extend:DI (plus:SI (mult:SI (match_dup 8) (match_dup 4))
470 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
471 operands[2], operands[3]);
472 operands[8] = gen_lowpart (SImode, operands[6]);
475 (define_insn "*saddq"
476 [(set (match_operand:DI 0 "register_operand" "=r,r")
477 (plus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r,r")
478 (match_operand:DI 2 "const48_operand" "I,I"))
479 (match_operand:DI 3 "sext_add_operand" "rI,O")))]
485 (define_insn "addvdi3"
486 [(set (match_operand:DI 0 "register_operand" "=r,r")
487 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
488 (match_operand:DI 2 "sext_add_operand" "rI,O")))
489 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
490 (sign_extend:TI (match_dup 2)))
491 (sign_extend:TI (plus:DI (match_dup 1)
499 (define_insn "negsi2"
500 [(set (match_operand:SI 0 "register_operand" "=r")
501 (neg:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))]
505 (define_insn "*negsi_se"
506 [(set (match_operand:DI 0 "register_operand" "=r")
507 (sign_extend:DI (neg:SI
508 (match_operand:SI 1 "reg_or_8bit_operand" "rI"))))]
512 (define_insn "negvsi2"
513 [(set (match_operand:SI 0 "register_operand" "=r")
514 (neg:SI (match_operand:SI 1 "register_operand" "r")))
515 (trap_if (ne (neg:DI (sign_extend:DI (match_dup 1)))
516 (sign_extend:DI (neg:SI (match_dup 1))))
521 (define_insn "negdi2"
522 [(set (match_operand:DI 0 "register_operand" "=r")
523 (neg:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
527 (define_insn "negvdi2"
528 [(set (match_operand:DI 0 "register_operand" "=r")
529 (neg:DI (match_operand:DI 1 "register_operand" "r")))
530 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
531 (sign_extend:TI (neg:DI (match_dup 1))))
536 (define_expand "subsi3"
537 [(set (match_operand:SI 0 "register_operand" "")
538 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "")
539 (match_operand:SI 2 "reg_or_8bit_operand" "")))]
543 (define_insn "*subsi_internal"
544 [(set (match_operand:SI 0 "register_operand" "=r")
545 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
546 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
550 (define_insn "*subsi_se"
551 [(set (match_operand:DI 0 "register_operand" "=r")
552 (sign_extend:DI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
553 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
557 (define_insn "*subsi_se2"
558 [(set (match_operand:DI 0 "register_operand" "=r")
560 (subreg:SI (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
561 (match_operand:DI 2 "reg_or_8bit_operand" "rI"))
566 (define_insn "subvsi3"
567 [(set (match_operand:SI 0 "register_operand" "=r")
568 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
569 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))
570 (trap_if (ne (minus:DI (sign_extend:DI (match_dup 1))
571 (sign_extend:DI (match_dup 2)))
572 (sign_extend:DI (minus:SI (match_dup 1)
578 (define_insn "subdi3"
579 [(set (match_operand:DI 0 "register_operand" "=r")
580 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
581 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
585 (define_insn "*ssubl"
586 [(set (match_operand:SI 0 "register_operand" "=r")
587 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
588 (match_operand:SI 2 "const48_operand" "I"))
589 (match_operand:SI 3 "reg_or_8bit_operand" "rI")))]
593 (define_insn "*ssubl_se"
594 [(set (match_operand:DI 0 "register_operand" "=r")
596 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
597 (match_operand:SI 2 "const48_operand" "I"))
598 (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))]
602 (define_insn "*ssubq"
603 [(set (match_operand:DI 0 "register_operand" "=r")
604 (minus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r")
605 (match_operand:DI 2 "const48_operand" "I"))
606 (match_operand:DI 3 "reg_or_8bit_operand" "rI")))]
610 (define_insn "subvdi3"
611 [(set (match_operand:DI 0 "register_operand" "=r")
612 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
613 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
614 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
615 (sign_extend:TI (match_dup 2)))
616 (sign_extend:TI (minus:DI (match_dup 1)
622 ;; The Unicos/Mk assembler doesn't support mull.
624 (define_insn "mulsi3"
625 [(set (match_operand:SI 0 "register_operand" "=r")
626 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
627 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
628 "!TARGET_ABI_UNICOSMK"
630 [(set_attr "type" "imul")
631 (set_attr "opsize" "si")])
633 (define_insn "*mulsi_se"
634 [(set (match_operand:DI 0 "register_operand" "=r")
636 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
637 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
638 "!TARGET_ABI_UNICOSMK"
640 [(set_attr "type" "imul")
641 (set_attr "opsize" "si")])
643 (define_insn "mulvsi3"
644 [(set (match_operand:SI 0 "register_operand" "=r")
645 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
646 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))
647 (trap_if (ne (mult:DI (sign_extend:DI (match_dup 1))
648 (sign_extend:DI (match_dup 2)))
649 (sign_extend:DI (mult:SI (match_dup 1)
652 "!TARGET_ABI_UNICOSMK"
654 [(set_attr "type" "imul")
655 (set_attr "opsize" "si")])
657 (define_insn "muldi3"
658 [(set (match_operand:DI 0 "register_operand" "=r")
659 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
660 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
663 [(set_attr "type" "imul")])
665 (define_insn "mulvdi3"
666 [(set (match_operand:DI 0 "register_operand" "=r")
667 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
668 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
669 (trap_if (ne (mult:TI (sign_extend:TI (match_dup 1))
670 (sign_extend:TI (match_dup 2)))
671 (sign_extend:TI (mult:DI (match_dup 1)
676 [(set_attr "type" "imul")])
678 (define_insn "umuldi3_highpart"
679 [(set (match_operand:DI 0 "register_operand" "=r")
682 (mult:TI (zero_extend:TI
683 (match_operand:DI 1 "reg_or_0_operand" "%rJ"))
685 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
689 [(set_attr "type" "imul")
690 (set_attr "opsize" "udi")])
692 (define_insn "*umuldi3_highpart_const"
693 [(set (match_operand:DI 0 "register_operand" "=r")
696 (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "r"))
697 (match_operand:TI 2 "cint8_operand" "I"))
701 [(set_attr "type" "imul")
702 (set_attr "opsize" "udi")])
704 ;; The divide and remainder operations take their inputs from r24 and
705 ;; r25, put their output in r27, and clobber r23 and r28 on all
706 ;; systems except Unicos/Mk. On Unicos, the standard library provides
707 ;; subroutines which use the standard calling convention and work on
710 ;; ??? Force sign-extension here because some versions of OSF/1 and
711 ;; Interix/NT don't do the right thing if the inputs are not properly
712 ;; sign-extended. But Linux, for instance, does not have this
713 ;; problem. Is it worth the complication here to eliminate the sign
716 (define_expand "divsi3"
718 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
720 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
721 (parallel [(set (match_dup 5)
722 (sign_extend:DI (div:SI (match_dup 3) (match_dup 4))))
723 (clobber (reg:DI 23))
724 (clobber (reg:DI 28))])
725 (set (match_operand:SI 0 "nonimmediate_operand" "")
726 (subreg:SI (match_dup 5) 0))]
727 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
729 operands[3] = gen_reg_rtx (DImode);
730 operands[4] = gen_reg_rtx (DImode);
731 operands[5] = gen_reg_rtx (DImode);
734 (define_expand "udivsi3"
736 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
738 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
739 (parallel [(set (match_dup 5)
740 (sign_extend:DI (udiv:SI (match_dup 3) (match_dup 4))))
741 (clobber (reg:DI 23))
742 (clobber (reg:DI 28))])
743 (set (match_operand:SI 0 "nonimmediate_operand" "")
744 (subreg:SI (match_dup 5) 0))]
745 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
747 operands[3] = gen_reg_rtx (DImode);
748 operands[4] = gen_reg_rtx (DImode);
749 operands[5] = gen_reg_rtx (DImode);
752 (define_expand "modsi3"
754 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
756 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
757 (parallel [(set (match_dup 5)
758 (sign_extend:DI (mod:SI (match_dup 3) (match_dup 4))))
759 (clobber (reg:DI 23))
760 (clobber (reg:DI 28))])
761 (set (match_operand:SI 0 "nonimmediate_operand" "")
762 (subreg:SI (match_dup 5) 0))]
763 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
765 operands[3] = gen_reg_rtx (DImode);
766 operands[4] = gen_reg_rtx (DImode);
767 operands[5] = gen_reg_rtx (DImode);
770 (define_expand "umodsi3"
772 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
774 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
775 (parallel [(set (match_dup 5)
776 (sign_extend:DI (umod:SI (match_dup 3) (match_dup 4))))
777 (clobber (reg:DI 23))
778 (clobber (reg:DI 28))])
779 (set (match_operand:SI 0 "nonimmediate_operand" "")
780 (subreg:SI (match_dup 5) 0))]
781 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
783 operands[3] = gen_reg_rtx (DImode);
784 operands[4] = gen_reg_rtx (DImode);
785 operands[5] = gen_reg_rtx (DImode);
788 (define_expand "divdi3"
789 [(parallel [(set (match_operand:DI 0 "register_operand" "")
790 (div:DI (match_operand:DI 1 "register_operand" "")
791 (match_operand:DI 2 "register_operand" "")))
792 (clobber (reg:DI 23))
793 (clobber (reg:DI 28))])]
794 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
797 (define_expand "udivdi3"
798 [(parallel [(set (match_operand:DI 0 "register_operand" "")
799 (udiv:DI (match_operand:DI 1 "register_operand" "")
800 (match_operand:DI 2 "register_operand" "")))
801 (clobber (reg:DI 23))
802 (clobber (reg:DI 28))])]
803 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
806 (define_expand "moddi3"
807 [(use (match_operand:DI 0 "register_operand" ""))
808 (use (match_operand:DI 1 "register_operand" ""))
809 (use (match_operand:DI 2 "register_operand" ""))]
810 "!TARGET_ABI_OPEN_VMS"
812 if (TARGET_ABI_UNICOSMK)
813 emit_insn (gen_moddi3_umk (operands[0], operands[1], operands[2]));
815 emit_insn (gen_moddi3_dft (operands[0], operands[1], operands[2]));
819 (define_expand "moddi3_dft"
820 [(parallel [(set (match_operand:DI 0 "register_operand" "")
821 (mod:DI (match_operand:DI 1 "register_operand" "")
822 (match_operand:DI 2 "register_operand" "")))
823 (clobber (reg:DI 23))
824 (clobber (reg:DI 28))])]
825 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
828 ;; On Unicos/Mk, we do as the system's C compiler does:
829 ;; compute the quotient, multiply and subtract.
831 (define_expand "moddi3_umk"
832 [(use (match_operand:DI 0 "register_operand" ""))
833 (use (match_operand:DI 1 "register_operand" ""))
834 (use (match_operand:DI 2 "register_operand" ""))]
835 "TARGET_ABI_UNICOSMK"
837 rtx div, mul = gen_reg_rtx (DImode);
839 div = expand_binop (DImode, sdiv_optab, operands[1], operands[2],
840 NULL_RTX, 0, OPTAB_LIB);
841 div = force_reg (DImode, div);
842 emit_insn (gen_muldi3 (mul, operands[2], div));
843 emit_insn (gen_subdi3 (operands[0], operands[1], mul));
847 (define_expand "umoddi3"
848 [(use (match_operand:DI 0 "register_operand" ""))
849 (use (match_operand:DI 1 "register_operand" ""))
850 (use (match_operand:DI 2 "register_operand" ""))]
851 "! TARGET_ABI_OPEN_VMS"
853 if (TARGET_ABI_UNICOSMK)
854 emit_insn (gen_umoddi3_umk (operands[0], operands[1], operands[2]));
856 emit_insn (gen_umoddi3_dft (operands[0], operands[1], operands[2]));
860 (define_expand "umoddi3_dft"
861 [(parallel [(set (match_operand:DI 0 "register_operand" "")
862 (umod:DI (match_operand:DI 1 "register_operand" "")
863 (match_operand:DI 2 "register_operand" "")))
864 (clobber (reg:DI 23))
865 (clobber (reg:DI 28))])]
866 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
869 (define_expand "umoddi3_umk"
870 [(use (match_operand:DI 0 "register_operand" ""))
871 (use (match_operand:DI 1 "register_operand" ""))
872 (use (match_operand:DI 2 "register_operand" ""))]
873 "TARGET_ABI_UNICOSMK"
875 rtx div, mul = gen_reg_rtx (DImode);
877 div = expand_binop (DImode, udiv_optab, operands[1], operands[2],
878 NULL_RTX, 1, OPTAB_LIB);
879 div = force_reg (DImode, div);
880 emit_insn (gen_muldi3 (mul, operands[2], div));
881 emit_insn (gen_subdi3 (operands[0], operands[1], mul));
885 ;; Lengths of 8 for ldq $t12,__divq($gp); jsr $t9,($t12),__divq as
886 ;; expanded by the assembler.
888 (define_insn_and_split "*divmodsi_internal_er"
889 [(set (match_operand:DI 0 "register_operand" "=c")
890 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
891 [(match_operand:DI 1 "register_operand" "a")
892 (match_operand:DI 2 "register_operand" "b")])))
893 (clobber (reg:DI 23))
894 (clobber (reg:DI 28))]
895 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
896 "ldq $27,__%E3($29)\t\t!literal!%#\;jsr $23,($27),__%E3\t\t!lituse_jsr!%#"
897 "&& reload_completed"
898 [(parallel [(set (match_dup 0)
899 (sign_extend:DI (match_dup 3)))
902 (clobber (reg:DI 23))
903 (clobber (reg:DI 28))])]
906 switch (GET_CODE (operands[3]))
923 operands[4] = GEN_INT (alpha_next_sequence_number++);
924 emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx,
925 gen_rtx_SYMBOL_REF (DImode, str),
928 [(set_attr "type" "jsr")
929 (set_attr "length" "8")])
931 (define_insn "*divmodsi_internal_er_1"
932 [(set (match_operand:DI 0 "register_operand" "=c")
933 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
934 [(match_operand:DI 1 "register_operand" "a")
935 (match_operand:DI 2 "register_operand" "b")])))
936 (use (match_operand:DI 4 "register_operand" "c"))
937 (use (match_operand 5 "const_int_operand" ""))
938 (clobber (reg:DI 23))
939 (clobber (reg:DI 28))]
940 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
941 "jsr $23,($27),__%E3%J5"
942 [(set_attr "type" "jsr")
943 (set_attr "length" "4")])
945 (define_insn "*divmodsi_internal"
946 [(set (match_operand:DI 0 "register_operand" "=c")
947 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
948 [(match_operand:DI 1 "register_operand" "a")
949 (match_operand:DI 2 "register_operand" "b")])))
950 (clobber (reg:DI 23))
951 (clobber (reg:DI 28))]
952 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
954 [(set_attr "type" "jsr")
955 (set_attr "length" "8")])
957 (define_insn_and_split "*divmoddi_internal_er"
958 [(set (match_operand:DI 0 "register_operand" "=c")
959 (match_operator:DI 3 "divmod_operator"
960 [(match_operand:DI 1 "register_operand" "a")
961 (match_operand:DI 2 "register_operand" "b")]))
962 (clobber (reg:DI 23))
963 (clobber (reg:DI 28))]
964 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
965 "ldq $27,__%E3($29)\t\t!literal!%#\;jsr $23,($27),__%E3\t\t!lituse_jsr!%#"
966 "&& reload_completed"
967 [(parallel [(set (match_dup 0) (match_dup 3))
970 (clobber (reg:DI 23))
971 (clobber (reg:DI 28))])]
974 switch (GET_CODE (operands[3]))
991 operands[4] = GEN_INT (alpha_next_sequence_number++);
992 emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx,
993 gen_rtx_SYMBOL_REF (DImode, str),
996 [(set_attr "type" "jsr")
997 (set_attr "length" "8")])
999 (define_insn "*divmoddi_internal_er_1"
1000 [(set (match_operand:DI 0 "register_operand" "=c")
1001 (match_operator:DI 3 "divmod_operator"
1002 [(match_operand:DI 1 "register_operand" "a")
1003 (match_operand:DI 2 "register_operand" "b")]))
1004 (use (match_operand:DI 4 "register_operand" "c"))
1005 (use (match_operand 5 "const_int_operand" ""))
1006 (clobber (reg:DI 23))
1007 (clobber (reg:DI 28))]
1008 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1009 "jsr $23,($27),__%E3%J5"
1010 [(set_attr "type" "jsr")
1011 (set_attr "length" "4")])
1013 (define_insn "*divmoddi_internal"
1014 [(set (match_operand:DI 0 "register_operand" "=c")
1015 (match_operator:DI 3 "divmod_operator"
1016 [(match_operand:DI 1 "register_operand" "a")
1017 (match_operand:DI 2 "register_operand" "b")]))
1018 (clobber (reg:DI 23))
1019 (clobber (reg:DI 28))]
1020 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1022 [(set_attr "type" "jsr")
1023 (set_attr "length" "8")])
1025 ;; Next are the basic logical operations. These only exist in DImode.
1027 (define_insn "anddi3"
1028 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1029 (and:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ")
1030 (match_operand:DI 2 "and_operand" "rI,N,MH")))]
1036 [(set_attr "type" "ilog,ilog,shift")])
1038 ;; There are times when we can split an AND into two AND insns. This occurs
1039 ;; when we can first clear any bytes and then clear anything else. For
1040 ;; example "I & 0xffff07" is "(I & 0xffffff) & 0xffffffffffffff07".
1041 ;; Only do this when running on 64-bit host since the computations are
1042 ;; too messy otherwise.
1045 [(set (match_operand:DI 0 "register_operand" "")
1046 (and:DI (match_operand:DI 1 "register_operand" "")
1047 (match_operand:DI 2 "const_int_operand" "")))]
1048 "HOST_BITS_PER_WIDE_INT == 64 && ! and_operand (operands[2], DImode)"
1049 [(set (match_dup 0) (and:DI (match_dup 1) (match_dup 3)))
1050 (set (match_dup 0) (and:DI (match_dup 0) (match_dup 4)))]
1052 unsigned HOST_WIDE_INT mask1 = INTVAL (operands[2]);
1053 unsigned HOST_WIDE_INT mask2 = mask1;
1056 /* For each byte that isn't all zeros, make it all ones. */
1057 for (i = 0; i < 64; i += 8)
1058 if ((mask1 & ((HOST_WIDE_INT) 0xff << i)) != 0)
1059 mask1 |= (HOST_WIDE_INT) 0xff << i;
1061 /* Now turn on any bits we've just turned off. */
1064 operands[3] = GEN_INT (mask1);
1065 operands[4] = GEN_INT (mask2);
1068 (define_expand "zero_extendqihi2"
1069 [(set (match_operand:HI 0 "register_operand" "")
1070 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
1074 operands[1] = force_reg (QImode, operands[1]);
1077 (define_insn "*zero_extendqihi2_bwx"
1078 [(set (match_operand:HI 0 "register_operand" "=r,r")
1079 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1084 [(set_attr "type" "ilog,ild")])
1086 (define_insn "*zero_extendqihi2_nobwx"
1087 [(set (match_operand:HI 0 "register_operand" "=r")
1088 (zero_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1091 [(set_attr "type" "ilog")])
1093 (define_expand "zero_extendqisi2"
1094 [(set (match_operand:SI 0 "register_operand" "")
1095 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
1099 operands[1] = force_reg (QImode, operands[1]);
1102 (define_insn "*zero_extendqisi2_bwx"
1103 [(set (match_operand:SI 0 "register_operand" "=r,r")
1104 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1109 [(set_attr "type" "ilog,ild")])
1111 (define_insn "*zero_extendqisi2_nobwx"
1112 [(set (match_operand:SI 0 "register_operand" "=r")
1113 (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1116 [(set_attr "type" "ilog")])
1118 (define_expand "zero_extendqidi2"
1119 [(set (match_operand:DI 0 "register_operand" "")
1120 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "")))]
1124 operands[1] = force_reg (QImode, operands[1]);
1127 (define_insn "*zero_extendqidi2_bwx"
1128 [(set (match_operand:DI 0 "register_operand" "=r,r")
1129 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1134 [(set_attr "type" "ilog,ild")])
1136 (define_insn "*zero_extendqidi2_nobwx"
1137 [(set (match_operand:DI 0 "register_operand" "=r")
1138 (zero_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1141 [(set_attr "type" "ilog")])
1143 (define_expand "zero_extendhisi2"
1144 [(set (match_operand:SI 0 "register_operand" "")
1145 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
1149 operands[1] = force_reg (HImode, operands[1]);
1152 (define_insn "*zero_extendhisi2_bwx"
1153 [(set (match_operand:SI 0 "register_operand" "=r,r")
1154 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1159 [(set_attr "type" "shift,ild")])
1161 (define_insn "*zero_extendhisi2_nobwx"
1162 [(set (match_operand:SI 0 "register_operand" "=r")
1163 (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1166 [(set_attr "type" "shift")])
1168 (define_expand "zero_extendhidi2"
1169 [(set (match_operand:DI 0 "register_operand" "")
1170 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "")))]
1174 operands[1] = force_reg (HImode, operands[1]);
1177 (define_insn "*zero_extendhidi2_bwx"
1178 [(set (match_operand:DI 0 "register_operand" "=r,r")
1179 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1184 [(set_attr "type" "shift,ild")])
1186 (define_insn "*zero_extendhidi2_nobwx"
1187 [(set (match_operand:DI 0 "register_operand" "=r")
1188 (zero_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1191 [(set_attr "type" "shift")])
1193 (define_insn "zero_extendsidi2"
1194 [(set (match_operand:DI 0 "register_operand" "=r")
1195 (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
1198 [(set_attr "type" "shift")])
1200 (define_insn "andnotdi3"
1201 [(set (match_operand:DI 0 "register_operand" "=r")
1202 (and:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1203 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1206 [(set_attr "type" "ilog")])
1208 (define_insn "iordi3"
1209 [(set (match_operand:DI 0 "register_operand" "=r,r")
1210 (ior:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1211 (match_operand:DI 2 "or_operand" "rI,N")))]
1216 [(set_attr "type" "ilog")])
1218 (define_insn "one_cmpldi2"
1219 [(set (match_operand:DI 0 "register_operand" "=r")
1220 (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
1223 [(set_attr "type" "ilog")])
1225 (define_insn "*iornot"
1226 [(set (match_operand:DI 0 "register_operand" "=r")
1227 (ior:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1228 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1231 [(set_attr "type" "ilog")])
1233 (define_insn "xordi3"
1234 [(set (match_operand:DI 0 "register_operand" "=r,r")
1235 (xor:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1236 (match_operand:DI 2 "or_operand" "rI,N")))]
1241 [(set_attr "type" "ilog")])
1243 (define_insn "*xornot"
1244 [(set (match_operand:DI 0 "register_operand" "=r")
1245 (not:DI (xor:DI (match_operand:DI 1 "register_operand" "%rJ")
1246 (match_operand:DI 2 "register_operand" "rI"))))]
1249 [(set_attr "type" "ilog")])
1251 ;; Handle the FFS insn iff we support CIX.
1253 (define_expand "ffsdi2"
1255 (unspec:DI [(match_operand:DI 1 "register_operand" "")] UNSPEC_CTTZ))
1257 (plus:DI (match_dup 2) (const_int 1)))
1258 (set (match_operand:DI 0 "register_operand" "")
1259 (if_then_else:DI (eq (match_dup 1) (const_int 0))
1260 (const_int 0) (match_dup 3)))]
1263 operands[2] = gen_reg_rtx (DImode);
1264 operands[3] = gen_reg_rtx (DImode);
1267 (define_insn "*cttz"
1268 [(set (match_operand:DI 0 "register_operand" "=r")
1269 (unspec:DI [(match_operand:DI 1 "register_operand" "r")] UNSPEC_CTTZ))]
1272 ; EV6 calls all mvi and cttz/ctlz/popc class imisc, so just
1273 ; reuse the existing type name.
1274 [(set_attr "type" "mvi")])
1276 ;; Next come the shifts and the various extract and insert operations.
1278 (define_insn "ashldi3"
1279 [(set (match_operand:DI 0 "register_operand" "=r,r")
1280 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,rJ")
1281 (match_operand:DI 2 "reg_or_6bit_operand" "P,rS")))]
1284 switch (which_alternative)
1287 if (operands[2] == const1_rtx)
1288 return "addq %r1,%r1,%0";
1290 return "s%P2addq %r1,0,%0";
1292 return "sll %r1,%2,%0";
1297 [(set_attr "type" "iadd,shift")])
1299 (define_insn "*ashldi_se"
1300 [(set (match_operand:DI 0 "register_operand" "=r")
1302 (subreg:SI (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1303 (match_operand:DI 2 "const_int_operand" "P"))
1305 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3"
1307 if (operands[2] == const1_rtx)
1308 return "addl %r1,%r1,%0";
1310 return "s%P2addl %r1,0,%0";
1312 [(set_attr "type" "iadd")])
1314 (define_insn "lshrdi3"
1315 [(set (match_operand:DI 0 "register_operand" "=r")
1316 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1317 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1320 [(set_attr "type" "shift")])
1322 (define_insn "ashrdi3"
1323 [(set (match_operand:DI 0 "register_operand" "=r")
1324 (ashiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1325 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1328 [(set_attr "type" "shift")])
1330 (define_expand "extendqihi2"
1332 (ashift:DI (match_operand:QI 1 "some_operand" "")
1334 (set (match_operand:HI 0 "register_operand" "")
1335 (ashiftrt:DI (match_dup 2)
1341 emit_insn (gen_extendqihi2x (operands[0],
1342 force_reg (QImode, operands[1])));
1346 /* If we have an unaligned MEM, extend to DImode (which we do
1347 specially) and then copy to the result. */
1348 if (unaligned_memory_operand (operands[1], HImode))
1350 rtx temp = gen_reg_rtx (DImode);
1352 emit_insn (gen_extendqidi2 (temp, operands[1]));
1353 emit_move_insn (operands[0], gen_lowpart (HImode, temp));
1357 operands[0] = gen_lowpart (DImode, operands[0]);
1358 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1359 operands[2] = gen_reg_rtx (DImode);
1362 (define_insn "extendqidi2x"
1363 [(set (match_operand:DI 0 "register_operand" "=r")
1364 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1367 [(set_attr "type" "shift")])
1369 (define_insn "extendhidi2x"
1370 [(set (match_operand:DI 0 "register_operand" "=r")
1371 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1374 [(set_attr "type" "shift")])
1376 (define_insn "extendqisi2x"
1377 [(set (match_operand:SI 0 "register_operand" "=r")
1378 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1381 [(set_attr "type" "shift")])
1383 (define_insn "extendhisi2x"
1384 [(set (match_operand:SI 0 "register_operand" "=r")
1385 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1388 [(set_attr "type" "shift")])
1390 (define_insn "extendqihi2x"
1391 [(set (match_operand:HI 0 "register_operand" "=r")
1392 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1395 [(set_attr "type" "shift")])
1397 (define_expand "extendqisi2"
1399 (ashift:DI (match_operand:QI 1 "some_operand" "")
1401 (set (match_operand:SI 0 "register_operand" "")
1402 (ashiftrt:DI (match_dup 2)
1408 emit_insn (gen_extendqisi2x (operands[0],
1409 force_reg (QImode, operands[1])));
1413 /* If we have an unaligned MEM, extend to a DImode form of
1414 the result (which we do specially). */
1415 if (unaligned_memory_operand (operands[1], QImode))
1417 rtx temp = gen_reg_rtx (DImode);
1419 emit_insn (gen_extendqidi2 (temp, operands[1]));
1420 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1424 operands[0] = gen_lowpart (DImode, operands[0]);
1425 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1426 operands[2] = gen_reg_rtx (DImode);
1429 (define_expand "extendqidi2"
1431 (ashift:DI (match_operand:QI 1 "some_operand" "")
1433 (set (match_operand:DI 0 "register_operand" "")
1434 (ashiftrt:DI (match_dup 2)
1440 emit_insn (gen_extendqidi2x (operands[0],
1441 force_reg (QImode, operands[1])));
1445 if (unaligned_memory_operand (operands[1], QImode))
1448 = gen_unaligned_extendqidi (operands[0],
1449 get_unaligned_address (operands[1], 1));
1451 alpha_set_memflags (seq, operands[1]);
1456 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1457 operands[2] = gen_reg_rtx (DImode);
1460 (define_expand "extendhisi2"
1462 (ashift:DI (match_operand:HI 1 "some_operand" "")
1464 (set (match_operand:SI 0 "register_operand" "")
1465 (ashiftrt:DI (match_dup 2)
1471 emit_insn (gen_extendhisi2x (operands[0],
1472 force_reg (HImode, operands[1])));
1476 /* If we have an unaligned MEM, extend to a DImode form of
1477 the result (which we do specially). */
1478 if (unaligned_memory_operand (operands[1], HImode))
1480 rtx temp = gen_reg_rtx (DImode);
1482 emit_insn (gen_extendhidi2 (temp, operands[1]));
1483 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1487 operands[0] = gen_lowpart (DImode, operands[0]);
1488 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1489 operands[2] = gen_reg_rtx (DImode);
1492 (define_expand "extendhidi2"
1494 (ashift:DI (match_operand:HI 1 "some_operand" "")
1496 (set (match_operand:DI 0 "register_operand" "")
1497 (ashiftrt:DI (match_dup 2)
1503 emit_insn (gen_extendhidi2x (operands[0],
1504 force_reg (HImode, operands[1])));
1508 if (unaligned_memory_operand (operands[1], HImode))
1511 = gen_unaligned_extendhidi (operands[0],
1512 get_unaligned_address (operands[1], 2));
1514 alpha_set_memflags (seq, operands[1]);
1519 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1520 operands[2] = gen_reg_rtx (DImode);
1523 ;; Here's how we sign extend an unaligned byte and halfword. Doing this
1524 ;; as a pattern saves one instruction. The code is similar to that for
1525 ;; the unaligned loads (see below).
1527 ;; Operand 1 is the address + 1 (+2 for HI), operand 0 is the result.
1528 (define_expand "unaligned_extendqidi"
1529 [(use (match_operand:QI 0 "register_operand" ""))
1530 (use (match_operand:DI 1 "address_operand" ""))]
1533 if (WORDS_BIG_ENDIAN)
1534 emit_insn (gen_unaligned_extendqidi_be (operands[0], operands[1]));
1536 emit_insn (gen_unaligned_extendqidi_le (operands[0], operands[1]));
1540 (define_expand "unaligned_extendqidi_le"
1541 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1543 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -1))
1546 (ashift:DI (match_dup 3)
1547 (minus:DI (const_int 64)
1549 (and:DI (match_dup 2) (const_int 7))
1551 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1552 (ashiftrt:DI (match_dup 4) (const_int 56)))]
1553 "! WORDS_BIG_ENDIAN"
1555 operands[2] = gen_reg_rtx (DImode);
1556 operands[3] = gen_reg_rtx (DImode);
1557 operands[4] = gen_reg_rtx (DImode);
1560 (define_expand "unaligned_extendqidi_be"
1561 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1562 (set (match_dup 3) (plus:DI (match_dup 2) (const_int -1)))
1564 (mem:DI (and:DI (match_dup 3)
1566 (set (match_dup 5) (plus:DI (match_dup 2) (const_int -2)))
1568 (ashift:DI (match_dup 4)
1571 (plus:DI (match_dup 5) (const_int 1))
1574 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1575 (ashiftrt:DI (match_dup 6) (const_int 56)))]
1578 operands[2] = gen_reg_rtx (DImode);
1579 operands[3] = gen_reg_rtx (DImode);
1580 operands[4] = gen_reg_rtx (DImode);
1581 operands[5] = gen_reg_rtx (DImode);
1582 operands[6] = gen_reg_rtx (DImode);
1585 (define_expand "unaligned_extendhidi"
1586 [(use (match_operand:QI 0 "register_operand" ""))
1587 (use (match_operand:DI 1 "address_operand" ""))]
1590 operands[0] = gen_lowpart (DImode, operands[0]);
1591 emit_insn ((WORDS_BIG_ENDIAN
1592 ? gen_unaligned_extendhidi_be
1593 : gen_unaligned_extendhidi_le) (operands[0], operands[1]));
1597 (define_expand "unaligned_extendhidi_le"
1598 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1600 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -2))
1603 (ashift:DI (match_dup 3)
1604 (minus:DI (const_int 64)
1606 (and:DI (match_dup 2) (const_int 7))
1608 (set (match_operand:DI 0 "register_operand" "")
1609 (ashiftrt:DI (match_dup 4) (const_int 48)))]
1610 "! WORDS_BIG_ENDIAN"
1612 operands[2] = gen_reg_rtx (DImode);
1613 operands[3] = gen_reg_rtx (DImode);
1614 operands[4] = gen_reg_rtx (DImode);
1617 (define_expand "unaligned_extendhidi_be"
1618 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1619 (set (match_dup 3) (plus:DI (match_dup 2) (const_int -2)))
1621 (mem:DI (and:DI (match_dup 3)
1623 (set (match_dup 5) (plus:DI (match_dup 2) (const_int -3)))
1625 (ashift:DI (match_dup 4)
1628 (plus:DI (match_dup 5) (const_int 1))
1631 (set (match_operand:DI 0 "register_operand" "")
1632 (ashiftrt:DI (match_dup 6) (const_int 48)))]
1635 operands[2] = gen_reg_rtx (DImode);
1636 operands[3] = gen_reg_rtx (DImode);
1637 operands[4] = gen_reg_rtx (DImode);
1638 operands[5] = gen_reg_rtx (DImode);
1639 operands[6] = gen_reg_rtx (DImode);
1642 (define_insn "*extxl_const"
1643 [(set (match_operand:DI 0 "register_operand" "=r")
1644 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1645 (match_operand:DI 2 "mode_width_operand" "n")
1646 (match_operand:DI 3 "mul8_operand" "I")))]
1648 "ext%M2l %r1,%s3,%0"
1649 [(set_attr "type" "shift")])
1651 (define_insn "extxl_le"
1652 [(set (match_operand:DI 0 "register_operand" "=r")
1653 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1654 (match_operand:DI 2 "mode_width_operand" "n")
1655 (ashift:DI (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1657 "! WORDS_BIG_ENDIAN"
1659 [(set_attr "type" "shift")])
1661 (define_insn "extxl_be"
1662 [(set (match_operand:DI 0 "register_operand" "=r")
1663 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1664 (match_operand:DI 2 "mode_width_operand" "n")
1668 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1672 [(set_attr "type" "shift")])
1674 ;; Combine has some strange notion of preserving existing undefined behaviour
1675 ;; in shifts larger than a word size. So capture these patterns that it
1676 ;; should have turned into zero_extracts.
1678 (define_insn "*extxl_1_le"
1679 [(set (match_operand:DI 0 "register_operand" "=r")
1680 (and:DI (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1681 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1683 (match_operand:DI 3 "mode_mask_operand" "n")))]
1684 "! WORDS_BIG_ENDIAN"
1686 [(set_attr "type" "shift")])
1688 (define_insn "*extxl_1_be"
1689 [(set (match_operand:DI 0 "register_operand" "=r")
1690 (and:DI (lshiftrt:DI
1691 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1692 (minus:DI (const_int 56)
1693 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1695 (match_operand:DI 3 "mode_mask_operand" "n")))]
1698 [(set_attr "type" "shift")])
1700 (define_insn "*extql_2_le"
1701 [(set (match_operand:DI 0 "register_operand" "=r")
1702 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1703 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1705 "! WORDS_BIG_ENDIAN"
1707 [(set_attr "type" "shift")])
1709 (define_insn "*extql_2_be"
1710 [(set (match_operand:DI 0 "register_operand" "=r")
1712 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1713 (minus:DI (const_int 56)
1715 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1719 [(set_attr "type" "shift")])
1721 (define_insn "extqh_le"
1722 [(set (match_operand:DI 0 "register_operand" "=r")
1724 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1725 (minus:DI (const_int 64)
1728 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1731 "! WORDS_BIG_ENDIAN"
1733 [(set_attr "type" "shift")])
1735 (define_insn "extqh_be"
1736 [(set (match_operand:DI 0 "register_operand" "=r")
1738 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1741 (plus:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1747 [(set_attr "type" "shift")])
1749 (define_insn "extlh_le"
1750 [(set (match_operand:DI 0 "register_operand" "=r")
1752 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1753 (const_int 2147483647))
1754 (minus:DI (const_int 64)
1757 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1760 "! WORDS_BIG_ENDIAN"
1762 [(set_attr "type" "shift")])
1764 (define_insn "extlh_be"
1765 [(set (match_operand:DI 0 "register_operand" "=r")
1768 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1772 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1776 (const_int 2147483647)))]
1779 [(set_attr "type" "shift")])
1781 (define_insn "extwh_le"
1782 [(set (match_operand:DI 0 "register_operand" "=r")
1784 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1786 (minus:DI (const_int 64)
1789 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1792 "! WORDS_BIG_ENDIAN"
1794 [(set_attr "type" "shift")])
1796 (define_insn "extwh_be"
1797 [(set (match_operand:DI 0 "register_operand" "=r")
1799 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1803 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1807 (const_int 65535)))]
1810 [(set_attr "type" "shift")])
1812 ;; This converts an extXl into an extXh with an appropriate adjustment
1813 ;; to the address calculation.
1816 ;; [(set (match_operand:DI 0 "register_operand" "")
1817 ;; (ashift:DI (zero_extract:DI (match_operand:DI 1 "register_operand" "")
1818 ;; (match_operand:DI 2 "mode_width_operand" "")
1819 ;; (ashift:DI (match_operand:DI 3 "" "")
1821 ;; (match_operand:DI 4 "const_int_operand" "")))
1822 ;; (clobber (match_operand:DI 5 "register_operand" ""))]
1823 ;; "INTVAL (operands[4]) == 64 - INTVAL (operands[2])"
1824 ;; [(set (match_dup 5) (match_dup 6))
1825 ;; (set (match_dup 0)
1826 ;; (ashift:DI (zero_extract:DI (match_dup 1) (match_dup 2)
1827 ;; (ashift:DI (plus:DI (match_dup 5)
1833 ;; operands[6] = plus_constant (operands[3],
1834 ;; INTVAL (operands[2]) / BITS_PER_UNIT);
1835 ;; operands[7] = GEN_INT (- INTVAL (operands[2]) / BITS_PER_UNIT);
1838 (define_insn "*insbl_const"
1839 [(set (match_operand:DI 0 "register_operand" "=r")
1840 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
1841 (match_operand:DI 2 "mul8_operand" "I")))]
1844 [(set_attr "type" "shift")])
1846 (define_insn "*inswl_const"
1847 [(set (match_operand:DI 0 "register_operand" "=r")
1848 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
1849 (match_operand:DI 2 "mul8_operand" "I")))]
1852 [(set_attr "type" "shift")])
1854 (define_insn "*insll_const"
1855 [(set (match_operand:DI 0 "register_operand" "=r")
1856 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
1857 (match_operand:DI 2 "mul8_operand" "I")))]
1860 [(set_attr "type" "shift")])
1862 (define_insn "insbl_le"
1863 [(set (match_operand:DI 0 "register_operand" "=r")
1864 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
1865 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1867 "! WORDS_BIG_ENDIAN"
1869 [(set_attr "type" "shift")])
1871 (define_insn "insbl_be"
1872 [(set (match_operand:DI 0 "register_operand" "=r")
1873 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
1874 (minus:DI (const_int 56)
1875 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1879 [(set_attr "type" "shift")])
1881 (define_insn "inswl_le"
1882 [(set (match_operand:DI 0 "register_operand" "=r")
1883 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
1884 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1886 "! WORDS_BIG_ENDIAN"
1888 [(set_attr "type" "shift")])
1890 (define_insn "inswl_be"
1891 [(set (match_operand:DI 0 "register_operand" "=r")
1892 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
1893 (minus:DI (const_int 56)
1894 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1898 [(set_attr "type" "shift")])
1900 (define_insn "insll_le"
1901 [(set (match_operand:DI 0 "register_operand" "=r")
1902 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
1903 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1905 "! WORDS_BIG_ENDIAN"
1907 [(set_attr "type" "shift")])
1909 (define_insn "insll_be"
1910 [(set (match_operand:DI 0 "register_operand" "=r")
1911 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
1912 (minus:DI (const_int 56)
1913 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1917 [(set_attr "type" "shift")])
1919 (define_insn "insql_le"
1920 [(set (match_operand:DI 0 "register_operand" "=r")
1921 (ashift:DI (match_operand:DI 1 "register_operand" "r")
1922 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1924 "! WORDS_BIG_ENDIAN"
1926 [(set_attr "type" "shift")])
1928 (define_insn "insql_be"
1929 [(set (match_operand:DI 0 "register_operand" "=r")
1930 (ashift:DI (match_operand:DI 1 "register_operand" "r")
1931 (minus:DI (const_int 56)
1932 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1936 [(set_attr "type" "shift")])
1938 ;; Combine has this sometimes habit of moving the and outside of the
1939 ;; shift, making life more interesting.
1941 (define_insn "*insxl"
1942 [(set (match_operand:DI 0 "register_operand" "=r")
1943 (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
1944 (match_operand:DI 2 "mul8_operand" "I"))
1945 (match_operand:DI 3 "immediate_operand" "i")))]
1946 "HOST_BITS_PER_WIDE_INT == 64
1947 && GET_CODE (operands[3]) == CONST_INT
1948 && (((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
1949 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1950 || ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
1951 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1952 || ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
1953 == (unsigned HOST_WIDE_INT) INTVAL (operands[3])))"
1955 #if HOST_BITS_PER_WIDE_INT == 64
1956 if ((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
1957 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1958 return "insbl %1,%s2,%0";
1959 if ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
1960 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1961 return "inswl %1,%s2,%0";
1962 if ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
1963 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1964 return "insll %1,%s2,%0";
1968 [(set_attr "type" "shift")])
1970 ;; We do not include the insXh insns because they are complex to express
1971 ;; and it does not appear that we would ever want to generate them.
1973 ;; Since we need them for block moves, though, cop out and use unspec.
1975 (define_insn "insxh"
1976 [(set (match_operand:DI 0 "register_operand" "=r")
1977 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
1978 (match_operand:DI 2 "mode_width_operand" "n")
1979 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]
1983 [(set_attr "type" "shift")])
1985 (define_insn "mskxl_le"
1986 [(set (match_operand:DI 0 "register_operand" "=r")
1987 (and:DI (not:DI (ashift:DI
1988 (match_operand:DI 2 "mode_mask_operand" "n")
1990 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1992 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
1993 "! WORDS_BIG_ENDIAN"
1995 [(set_attr "type" "shift")])
1997 (define_insn "mskxl_be"
1998 [(set (match_operand:DI 0 "register_operand" "=r")
1999 (and:DI (not:DI (ashift:DI
2000 (match_operand:DI 2 "mode_mask_operand" "n")
2001 (minus:DI (const_int 56)
2003 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
2005 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
2008 [(set_attr "type" "shift")])
2010 ;; We do not include the mskXh insns because it does not appear we would
2011 ;; ever generate one.
2013 ;; Again, we do for block moves and we use unspec again.
2015 (define_insn "mskxh"
2016 [(set (match_operand:DI 0 "register_operand" "=r")
2017 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
2018 (match_operand:DI 2 "mode_width_operand" "n")
2019 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]
2023 [(set_attr "type" "shift")])
2025 ;; Prefer AND + NE over LSHIFTRT + AND.
2027 (define_insn_and_split "*ze_and_ne"
2028 [(set (match_operand:DI 0 "register_operand" "=r")
2029 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
2031 (match_operand 2 "const_int_operand" "I")))]
2032 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8"
2034 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8"
2036 (and:DI (match_dup 1) (match_dup 3)))
2038 (ne:DI (match_dup 0) (const_int 0)))]
2039 "operands[3] = GEN_INT (1 << INTVAL (operands[2]));")
2041 ;; Floating-point operations. All the double-precision insns can extend
2042 ;; from single, so indicate that. The exception are the ones that simply
2043 ;; play with the sign bits; it's not clear what to do there.
2045 (define_insn "abssf2"
2046 [(set (match_operand:SF 0 "register_operand" "=f")
2047 (abs:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
2050 [(set_attr "type" "fcpys")])
2052 (define_insn "*nabssf2"
2053 [(set (match_operand:SF 0 "register_operand" "=f")
2054 (neg:SF (abs:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
2057 [(set_attr "type" "fadd")])
2059 (define_insn "absdf2"
2060 [(set (match_operand:DF 0 "register_operand" "=f")
2061 (abs:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2064 [(set_attr "type" "fcpys")])
2066 (define_insn "*nabsdf2"
2067 [(set (match_operand:DF 0 "register_operand" "=f")
2068 (neg:DF (abs:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG"))))]
2071 [(set_attr "type" "fadd")])
2073 (define_expand "abstf2"
2074 [(parallel [(set (match_operand:TF 0 "register_operand" "")
2075 (neg:TF (match_operand:TF 1 "reg_or_fp0_operand" "")))
2076 (use (match_dup 2))])]
2077 "TARGET_HAS_XFLOATING_LIBS"
2079 #if HOST_BITS_PER_WIDE_INT >= 64
2080 operands[2] = force_reg (DImode, GEN_INT ((HOST_WIDE_INT) 1 << 63));
2082 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
2086 (define_insn_and_split "*abstf_internal"
2087 [(set (match_operand:TF 0 "register_operand" "=r")
2088 (abs:TF (match_operand:TF 1 "reg_or_fp0_operand" "rG")))
2089 (use (match_operand:DI 2 "register_operand" "r"))]
2090 "TARGET_HAS_XFLOATING_LIBS"
2092 "&& reload_completed"
2094 "alpha_split_tfmode_frobsign (operands, gen_andnotdi3); DONE;")
2096 (define_insn "negsf2"
2097 [(set (match_operand:SF 0 "register_operand" "=f")
2098 (neg:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
2101 [(set_attr "type" "fadd")])
2103 (define_insn "negdf2"
2104 [(set (match_operand:DF 0 "register_operand" "=f")
2105 (neg:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2108 [(set_attr "type" "fadd")])
2110 (define_expand "negtf2"
2111 [(parallel [(set (match_operand:TF 0 "register_operand" "")
2112 (neg:TF (match_operand:TF 1 "reg_or_fp0_operand" "")))
2113 (use (match_dup 2))])]
2114 "TARGET_HAS_XFLOATING_LIBS"
2116 #if HOST_BITS_PER_WIDE_INT >= 64
2117 operands[2] = force_reg (DImode, GEN_INT ((HOST_WIDE_INT) 1 << 63));
2119 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
2123 (define_insn_and_split "*negtf_internal"
2124 [(set (match_operand:TF 0 "register_operand" "=r")
2125 (neg:TF (match_operand:TF 1 "reg_or_fp0_operand" "rG")))
2126 (use (match_operand:DI 2 "register_operand" "r"))]
2127 "TARGET_HAS_XFLOATING_LIBS"
2129 "&& reload_completed"
2131 "alpha_split_tfmode_frobsign (operands, gen_xordi3); DONE;")
2133 (define_insn "*addsf_ieee"
2134 [(set (match_operand:SF 0 "register_operand" "=&f")
2135 (plus:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
2136 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2137 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2138 "add%,%/ %R1,%R2,%0"
2139 [(set_attr "type" "fadd")
2140 (set_attr "trap" "yes")
2141 (set_attr "round_suffix" "normal")
2142 (set_attr "trap_suffix" "u_su_sui")])
2144 (define_insn "addsf3"
2145 [(set (match_operand:SF 0 "register_operand" "=f")
2146 (plus:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
2147 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2149 "add%,%/ %R1,%R2,%0"
2150 [(set_attr "type" "fadd")
2151 (set_attr "trap" "yes")
2152 (set_attr "round_suffix" "normal")
2153 (set_attr "trap_suffix" "u_su_sui")])
2155 (define_insn "*adddf_ieee"
2156 [(set (match_operand:DF 0 "register_operand" "=&f")
2157 (plus:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
2158 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2159 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2160 "add%-%/ %R1,%R2,%0"
2161 [(set_attr "type" "fadd")
2162 (set_attr "trap" "yes")
2163 (set_attr "round_suffix" "normal")
2164 (set_attr "trap_suffix" "u_su_sui")])
2166 (define_insn "adddf3"
2167 [(set (match_operand:DF 0 "register_operand" "=f")
2168 (plus:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
2169 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2171 "add%-%/ %R1,%R2,%0"
2172 [(set_attr "type" "fadd")
2173 (set_attr "trap" "yes")
2174 (set_attr "round_suffix" "normal")
2175 (set_attr "trap_suffix" "u_su_sui")])
2177 (define_insn "*adddf_ext1"
2178 [(set (match_operand:DF 0 "register_operand" "=f")
2179 (plus:DF (float_extend:DF
2180 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2181 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2182 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2183 "add%-%/ %R1,%R2,%0"
2184 [(set_attr "type" "fadd")
2185 (set_attr "trap" "yes")
2186 (set_attr "round_suffix" "normal")
2187 (set_attr "trap_suffix" "u_su_sui")])
2189 (define_insn "*adddf_ext2"
2190 [(set (match_operand:DF 0 "register_operand" "=f")
2191 (plus:DF (float_extend:DF
2192 (match_operand:SF 1 "reg_or_fp0_operand" "%fG"))
2194 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2195 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2196 "add%-%/ %R1,%R2,%0"
2197 [(set_attr "type" "fadd")
2198 (set_attr "trap" "yes")
2199 (set_attr "round_suffix" "normal")
2200 (set_attr "trap_suffix" "u_su_sui")])
2202 (define_expand "addtf3"
2203 [(use (match_operand 0 "register_operand" ""))
2204 (use (match_operand 1 "general_operand" ""))
2205 (use (match_operand 2 "general_operand" ""))]
2206 "TARGET_HAS_XFLOATING_LIBS"
2207 "alpha_emit_xfloating_arith (PLUS, operands); DONE;")
2209 ;; Define conversion operators between DFmode and SImode, using the cvtql
2210 ;; instruction. To allow combine et al to do useful things, we keep the
2211 ;; operation as a unit until after reload, at which point we split the
2214 ;; Note that we (attempt to) only consider this optimization when the
2215 ;; ultimate destination is memory. If we will be doing further integer
2216 ;; processing, it is cheaper to do the truncation in the int regs.
2218 (define_insn "*cvtql"
2219 [(set (match_operand:SI 0 "register_operand" "=f")
2220 (unspec:SI [(match_operand:DI 1 "reg_or_fp0_operand" "fG")]
2224 [(set_attr "type" "fadd")
2225 (set_attr "trap" "yes")
2226 (set_attr "trap_suffix" "v_sv")])
2228 (define_insn_and_split "*fix_truncdfsi_ieee"
2229 [(set (match_operand:SI 0 "memory_operand" "=m")
2230 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")) 0))
2231 (clobber (match_scratch:DI 2 "=&f"))
2232 (clobber (match_scratch:SI 3 "=&f"))]
2233 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2235 "&& reload_completed"
2236 [(set (match_dup 2) (fix:DI (match_dup 1)))
2237 (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
2238 (set (match_dup 0) (match_dup 3))]
2240 [(set_attr "type" "fadd")
2241 (set_attr "trap" "yes")])
2243 (define_insn_and_split "*fix_truncdfsi_internal"
2244 [(set (match_operand:SI 0 "memory_operand" "=m")
2245 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")) 0))
2246 (clobber (match_scratch:DI 2 "=f"))]
2247 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2249 "&& reload_completed"
2250 [(set (match_dup 2) (fix:DI (match_dup 1)))
2251 (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
2252 (set (match_dup 0) (match_dup 3))]
2253 ;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG.
2254 "operands[3] = gen_rtx_REG (SImode, REGNO (operands[2]));"
2255 [(set_attr "type" "fadd")
2256 (set_attr "trap" "yes")])
2258 (define_insn "*fix_truncdfdi_ieee"
2259 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
2260 (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2261 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2263 [(set_attr "type" "fadd")
2264 (set_attr "trap" "yes")
2265 (set_attr "round_suffix" "c")
2266 (set_attr "trap_suffix" "v_sv_svi")])
2268 (define_insn "fix_truncdfdi2"
2269 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
2270 (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2273 [(set_attr "type" "fadd")
2274 (set_attr "trap" "yes")
2275 (set_attr "round_suffix" "c")
2276 (set_attr "trap_suffix" "v_sv_svi")])
2278 ;; Likewise between SFmode and SImode.
2280 (define_insn_and_split "*fix_truncsfsi_ieee"
2281 [(set (match_operand:SI 0 "memory_operand" "=m")
2282 (subreg:SI (fix:DI (float_extend:DF
2283 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))) 0))
2284 (clobber (match_scratch:DI 2 "=&f"))
2285 (clobber (match_scratch:SI 3 "=&f"))]
2286 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2288 "&& reload_completed"
2289 [(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1))))
2290 (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
2291 (set (match_dup 0) (match_dup 3))]
2293 [(set_attr "type" "fadd")
2294 (set_attr "trap" "yes")])
2296 (define_insn_and_split "*fix_truncsfsi_internal"
2297 [(set (match_operand:SI 0 "memory_operand" "=m")
2298 (subreg:SI (fix:DI (float_extend:DF
2299 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))) 0))
2300 (clobber (match_scratch:DI 2 "=f"))]
2301 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2303 "&& reload_completed"
2304 [(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1))))
2305 (set (match_dup 3) (unspec:SI [(match_dup 2)] UNSPEC_CVTQL))
2306 (set (match_dup 0) (match_dup 3))]
2307 ;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG.
2308 "operands[3] = gen_rtx_REG (SImode, REGNO (operands[2]));"
2309 [(set_attr "type" "fadd")
2310 (set_attr "trap" "yes")])
2312 (define_insn "*fix_truncsfdi_ieee"
2313 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
2314 (fix:DI (float_extend:DF
2315 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
2316 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2318 [(set_attr "type" "fadd")
2319 (set_attr "trap" "yes")
2320 (set_attr "round_suffix" "c")
2321 (set_attr "trap_suffix" "v_sv_svi")])
2323 (define_insn "fix_truncsfdi2"
2324 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
2325 (fix:DI (float_extend:DF
2326 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
2329 [(set_attr "type" "fadd")
2330 (set_attr "trap" "yes")
2331 (set_attr "round_suffix" "c")
2332 (set_attr "trap_suffix" "v_sv_svi")])
2334 (define_expand "fix_trunctfdi2"
2335 [(use (match_operand:DI 0 "register_operand" ""))
2336 (use (match_operand:TF 1 "general_operand" ""))]
2337 "TARGET_HAS_XFLOATING_LIBS"
2338 "alpha_emit_xfloating_cvt (FIX, operands); DONE;")
2340 (define_insn "*floatdisf_ieee"
2341 [(set (match_operand:SF 0 "register_operand" "=&f")
2342 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2343 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2345 [(set_attr "type" "fadd")
2346 (set_attr "trap" "yes")
2347 (set_attr "round_suffix" "normal")
2348 (set_attr "trap_suffix" "sui")])
2350 (define_insn "floatdisf2"
2351 [(set (match_operand:SF 0 "register_operand" "=f")
2352 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2355 [(set_attr "type" "fadd")
2356 (set_attr "trap" "yes")
2357 (set_attr "round_suffix" "normal")
2358 (set_attr "trap_suffix" "sui")])
2360 (define_insn "*floatdidf_ieee"
2361 [(set (match_operand:DF 0 "register_operand" "=&f")
2362 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2363 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2365 [(set_attr "type" "fadd")
2366 (set_attr "trap" "yes")
2367 (set_attr "round_suffix" "normal")
2368 (set_attr "trap_suffix" "sui")])
2370 (define_insn "floatdidf2"
2371 [(set (match_operand:DF 0 "register_operand" "=f")
2372 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2375 [(set_attr "type" "fadd")
2376 (set_attr "trap" "yes")
2377 (set_attr "round_suffix" "normal")
2378 (set_attr "trap_suffix" "sui")])
2380 (define_expand "floatditf2"
2381 [(use (match_operand:TF 0 "register_operand" ""))
2382 (use (match_operand:DI 1 "general_operand" ""))]
2383 "TARGET_HAS_XFLOATING_LIBS"
2384 "alpha_emit_xfloating_cvt (FLOAT, operands); DONE;")
2386 (define_expand "floatunsdisf2"
2387 [(use (match_operand:SF 0 "register_operand" ""))
2388 (use (match_operand:DI 1 "register_operand" ""))]
2390 "alpha_emit_floatuns (operands); DONE;")
2392 (define_expand "floatunsdidf2"
2393 [(use (match_operand:DF 0 "register_operand" ""))
2394 (use (match_operand:DI 1 "register_operand" ""))]
2396 "alpha_emit_floatuns (operands); DONE;")
2398 (define_expand "floatunsditf2"
2399 [(use (match_operand:TF 0 "register_operand" ""))
2400 (use (match_operand:DI 1 "general_operand" ""))]
2401 "TARGET_HAS_XFLOATING_LIBS"
2402 "alpha_emit_xfloating_cvt (UNSIGNED_FLOAT, operands); DONE;")
2404 (define_expand "extendsfdf2"
2405 [(set (match_operand:DF 0 "register_operand" "")
2406 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
2409 if (alpha_fptm >= ALPHA_FPTM_SU)
2410 operands[1] = force_reg (SFmode, operands[1]);
2413 ;; The Unicos/Mk assembler doesn't support cvtst, but we've already
2414 ;; asserted that alpha_fptm == ALPHA_FPTM_N.
2416 (define_insn "*extendsfdf2_ieee"
2417 [(set (match_operand:DF 0 "register_operand" "=&f")
2418 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
2419 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2421 [(set_attr "type" "fadd")
2422 (set_attr "trap" "yes")])
2424 (define_insn "*extendsfdf2_internal"
2425 [(set (match_operand:DF 0 "register_operand" "=f,f,m")
2426 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m,f")))]
2427 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2432 [(set_attr "type" "fcpys,fld,fst")])
2434 (define_expand "extendsftf2"
2435 [(use (match_operand:TF 0 "register_operand" ""))
2436 (use (match_operand:SF 1 "general_operand" ""))]
2437 "TARGET_HAS_XFLOATING_LIBS"
2439 rtx tmp = gen_reg_rtx (DFmode);
2440 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
2441 emit_insn (gen_extenddftf2 (operands[0], tmp));
2445 (define_expand "extenddftf2"
2446 [(use (match_operand:TF 0 "register_operand" ""))
2447 (use (match_operand:DF 1 "general_operand" ""))]
2448 "TARGET_HAS_XFLOATING_LIBS"
2449 "alpha_emit_xfloating_cvt (FLOAT_EXTEND, operands); DONE;")
2451 (define_insn "*truncdfsf2_ieee"
2452 [(set (match_operand:SF 0 "register_operand" "=&f")
2453 (float_truncate:SF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2454 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2456 [(set_attr "type" "fadd")
2457 (set_attr "trap" "yes")
2458 (set_attr "round_suffix" "normal")
2459 (set_attr "trap_suffix" "u_su_sui")])
2461 (define_insn "truncdfsf2"
2462 [(set (match_operand:SF 0 "register_operand" "=f")
2463 (float_truncate:SF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2466 [(set_attr "type" "fadd")
2467 (set_attr "trap" "yes")
2468 (set_attr "round_suffix" "normal")
2469 (set_attr "trap_suffix" "u_su_sui")])
2471 (define_expand "trunctfdf2"
2472 [(use (match_operand:DF 0 "register_operand" ""))
2473 (use (match_operand:TF 1 "general_operand" ""))]
2474 "TARGET_HAS_XFLOATING_LIBS"
2475 "alpha_emit_xfloating_cvt (FLOAT_TRUNCATE, operands); DONE;")
2477 (define_expand "trunctfsf2"
2478 [(use (match_operand:SF 0 "register_operand" ""))
2479 (use (match_operand:TF 1 "general_operand" ""))]
2480 "TARGET_FP && TARGET_HAS_XFLOATING_LIBS"
2482 rtx tmpf, sticky, arg, lo, hi;
2484 tmpf = gen_reg_rtx (DFmode);
2485 sticky = gen_reg_rtx (DImode);
2486 arg = copy_to_mode_reg (TFmode, operands[1]);
2487 lo = gen_lowpart (DImode, arg);
2488 hi = gen_highpart (DImode, arg);
2490 /* Convert the low word of the TFmode value into a sticky rounding bit,
2491 then or it into the low bit of the high word. This leaves the sticky
2492 bit at bit 48 of the fraction, which is representable in DFmode,
2493 which prevents rounding error in the final conversion to SFmode. */
2495 emit_insn (gen_rtx_SET (VOIDmode, sticky,
2496 gen_rtx_NE (DImode, lo, const0_rtx)));
2497 emit_insn (gen_iordi3 (hi, hi, sticky));
2498 emit_insn (gen_trunctfdf2 (tmpf, arg));
2499 emit_insn (gen_truncdfsf2 (operands[0], tmpf));
2503 (define_insn "*divsf3_ieee"
2504 [(set (match_operand:SF 0 "register_operand" "=&f")
2505 (div:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2506 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2507 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2508 "div%,%/ %R1,%R2,%0"
2509 [(set_attr "type" "fdiv")
2510 (set_attr "opsize" "si")
2511 (set_attr "trap" "yes")
2512 (set_attr "round_suffix" "normal")
2513 (set_attr "trap_suffix" "u_su_sui")])
2515 (define_insn "divsf3"
2516 [(set (match_operand:SF 0 "register_operand" "=f")
2517 (div:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2518 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2520 "div%,%/ %R1,%R2,%0"
2521 [(set_attr "type" "fdiv")
2522 (set_attr "opsize" "si")
2523 (set_attr "trap" "yes")
2524 (set_attr "round_suffix" "normal")
2525 (set_attr "trap_suffix" "u_su_sui")])
2527 (define_insn "*divdf3_ieee"
2528 [(set (match_operand:DF 0 "register_operand" "=&f")
2529 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2530 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2531 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2532 "div%-%/ %R1,%R2,%0"
2533 [(set_attr "type" "fdiv")
2534 (set_attr "trap" "yes")
2535 (set_attr "round_suffix" "normal")
2536 (set_attr "trap_suffix" "u_su_sui")])
2538 (define_insn "divdf3"
2539 [(set (match_operand:DF 0 "register_operand" "=f")
2540 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2541 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2543 "div%-%/ %R1,%R2,%0"
2544 [(set_attr "type" "fdiv")
2545 (set_attr "trap" "yes")
2546 (set_attr "round_suffix" "normal")
2547 (set_attr "trap_suffix" "u_su_sui")])
2549 (define_insn "*divdf_ext1"
2550 [(set (match_operand:DF 0 "register_operand" "=f")
2551 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2552 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2553 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2554 "div%-%/ %R1,%R2,%0"
2555 [(set_attr "type" "fdiv")
2556 (set_attr "trap" "yes")
2557 (set_attr "round_suffix" "normal")
2558 (set_attr "trap_suffix" "u_su_sui")])
2560 (define_insn "*divdf_ext2"
2561 [(set (match_operand:DF 0 "register_operand" "=f")
2562 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2564 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2565 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2566 "div%-%/ %R1,%R2,%0"
2567 [(set_attr "type" "fdiv")
2568 (set_attr "trap" "yes")
2569 (set_attr "round_suffix" "normal")
2570 (set_attr "trap_suffix" "u_su_sui")])
2572 (define_insn "*divdf_ext3"
2573 [(set (match_operand:DF 0 "register_operand" "=f")
2574 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2575 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2576 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2577 "div%-%/ %R1,%R2,%0"
2578 [(set_attr "type" "fdiv")
2579 (set_attr "trap" "yes")
2580 (set_attr "round_suffix" "normal")
2581 (set_attr "trap_suffix" "u_su_sui")])
2583 (define_expand "divtf3"
2584 [(use (match_operand 0 "register_operand" ""))
2585 (use (match_operand 1 "general_operand" ""))
2586 (use (match_operand 2 "general_operand" ""))]
2587 "TARGET_HAS_XFLOATING_LIBS"
2588 "alpha_emit_xfloating_arith (DIV, operands); DONE;")
2590 (define_insn "*mulsf3_ieee"
2591 [(set (match_operand:SF 0 "register_operand" "=&f")
2592 (mult:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
2593 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2594 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2595 "mul%,%/ %R1,%R2,%0"
2596 [(set_attr "type" "fmul")
2597 (set_attr "trap" "yes")
2598 (set_attr "round_suffix" "normal")
2599 (set_attr "trap_suffix" "u_su_sui")])
2601 (define_insn "mulsf3"
2602 [(set (match_operand:SF 0 "register_operand" "=f")
2603 (mult:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
2604 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2606 "mul%,%/ %R1,%R2,%0"
2607 [(set_attr "type" "fmul")
2608 (set_attr "trap" "yes")
2609 (set_attr "round_suffix" "normal")
2610 (set_attr "trap_suffix" "u_su_sui")])
2612 (define_insn "*muldf3_ieee"
2613 [(set (match_operand:DF 0 "register_operand" "=&f")
2614 (mult:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
2615 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2616 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2617 "mul%-%/ %R1,%R2,%0"
2618 [(set_attr "type" "fmul")
2619 (set_attr "trap" "yes")
2620 (set_attr "round_suffix" "normal")
2621 (set_attr "trap_suffix" "u_su_sui")])
2623 (define_insn "muldf3"
2624 [(set (match_operand:DF 0 "register_operand" "=f")
2625 (mult:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
2626 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2628 "mul%-%/ %R1,%R2,%0"
2629 [(set_attr "type" "fmul")
2630 (set_attr "trap" "yes")
2631 (set_attr "round_suffix" "normal")
2632 (set_attr "trap_suffix" "u_su_sui")])
2634 (define_insn "*muldf_ext1"
2635 [(set (match_operand:DF 0 "register_operand" "=f")
2636 (mult:DF (float_extend:DF
2637 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2638 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2639 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2640 "mul%-%/ %R1,%R2,%0"
2641 [(set_attr "type" "fmul")
2642 (set_attr "trap" "yes")
2643 (set_attr "round_suffix" "normal")
2644 (set_attr "trap_suffix" "u_su_sui")])
2646 (define_insn "*muldf_ext2"
2647 [(set (match_operand:DF 0 "register_operand" "=f")
2648 (mult:DF (float_extend:DF
2649 (match_operand:SF 1 "reg_or_fp0_operand" "%fG"))
2651 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2652 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2653 "mul%-%/ %R1,%R2,%0"
2654 [(set_attr "type" "fmul")
2655 (set_attr "trap" "yes")
2656 (set_attr "round_suffix" "normal")
2657 (set_attr "trap_suffix" "u_su_sui")])
2659 (define_expand "multf3"
2660 [(use (match_operand 0 "register_operand" ""))
2661 (use (match_operand 1 "general_operand" ""))
2662 (use (match_operand 2 "general_operand" ""))]
2663 "TARGET_HAS_XFLOATING_LIBS"
2664 "alpha_emit_xfloating_arith (MULT, operands); DONE;")
2666 (define_insn "*subsf3_ieee"
2667 [(set (match_operand:SF 0 "register_operand" "=&f")
2668 (minus:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2669 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2670 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2671 "sub%,%/ %R1,%R2,%0"
2672 [(set_attr "type" "fadd")
2673 (set_attr "trap" "yes")
2674 (set_attr "round_suffix" "normal")
2675 (set_attr "trap_suffix" "u_su_sui")])
2677 (define_insn "subsf3"
2678 [(set (match_operand:SF 0 "register_operand" "=f")
2679 (minus:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2680 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2682 "sub%,%/ %R1,%R2,%0"
2683 [(set_attr "type" "fadd")
2684 (set_attr "trap" "yes")
2685 (set_attr "round_suffix" "normal")
2686 (set_attr "trap_suffix" "u_su_sui")])
2688 (define_insn "*subdf3_ieee"
2689 [(set (match_operand:DF 0 "register_operand" "=&f")
2690 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2691 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2692 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2693 "sub%-%/ %R1,%R2,%0"
2694 [(set_attr "type" "fadd")
2695 (set_attr "trap" "yes")
2696 (set_attr "round_suffix" "normal")
2697 (set_attr "trap_suffix" "u_su_sui")])
2699 (define_insn "subdf3"
2700 [(set (match_operand:DF 0 "register_operand" "=f")
2701 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2702 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2704 "sub%-%/ %R1,%R2,%0"
2705 [(set_attr "type" "fadd")
2706 (set_attr "trap" "yes")
2707 (set_attr "round_suffix" "normal")
2708 (set_attr "trap_suffix" "u_su_sui")])
2710 (define_insn "*subdf_ext1"
2711 [(set (match_operand:DF 0 "register_operand" "=f")
2712 (minus:DF (float_extend:DF
2713 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2714 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2715 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2716 "sub%-%/ %R1,%R2,%0"
2717 [(set_attr "type" "fadd")
2718 (set_attr "trap" "yes")
2719 (set_attr "round_suffix" "normal")
2720 (set_attr "trap_suffix" "u_su_sui")])
2722 (define_insn "*subdf_ext2"
2723 [(set (match_operand:DF 0 "register_operand" "=f")
2724 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2726 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2727 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2728 "sub%-%/ %R1,%R2,%0"
2729 [(set_attr "type" "fadd")
2730 (set_attr "trap" "yes")
2731 (set_attr "round_suffix" "normal")
2732 (set_attr "trap_suffix" "u_su_sui")])
2734 (define_insn "*subdf_ext3"
2735 [(set (match_operand:DF 0 "register_operand" "=f")
2736 (minus:DF (float_extend:DF
2737 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2739 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2740 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2741 "sub%-%/ %R1,%R2,%0"
2742 [(set_attr "type" "fadd")
2743 (set_attr "trap" "yes")
2744 (set_attr "round_suffix" "normal")
2745 (set_attr "trap_suffix" "u_su_sui")])
2747 (define_expand "subtf3"
2748 [(use (match_operand 0 "register_operand" ""))
2749 (use (match_operand 1 "general_operand" ""))
2750 (use (match_operand 2 "general_operand" ""))]
2751 "TARGET_HAS_XFLOATING_LIBS"
2752 "alpha_emit_xfloating_arith (MINUS, operands); DONE;")
2754 (define_insn "*sqrtsf2_ieee"
2755 [(set (match_operand:SF 0 "register_operand" "=&f")
2756 (sqrt:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
2757 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
2759 [(set_attr "type" "fsqrt")
2760 (set_attr "opsize" "si")
2761 (set_attr "trap" "yes")
2762 (set_attr "round_suffix" "normal")
2763 (set_attr "trap_suffix" "u_su_sui")])
2765 (define_insn "sqrtsf2"
2766 [(set (match_operand:SF 0 "register_operand" "=f")
2767 (sqrt:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
2768 "TARGET_FP && TARGET_FIX"
2770 [(set_attr "type" "fsqrt")
2771 (set_attr "opsize" "si")
2772 (set_attr "trap" "yes")
2773 (set_attr "round_suffix" "normal")
2774 (set_attr "trap_suffix" "u_su_sui")])
2776 (define_insn "*sqrtdf2_ieee"
2777 [(set (match_operand:DF 0 "register_operand" "=&f")
2778 (sqrt:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2779 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
2781 [(set_attr "type" "fsqrt")
2782 (set_attr "trap" "yes")
2783 (set_attr "round_suffix" "normal")
2784 (set_attr "trap_suffix" "u_su_sui")])
2786 (define_insn "sqrtdf2"
2787 [(set (match_operand:DF 0 "register_operand" "=f")
2788 (sqrt:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2789 "TARGET_FP && TARGET_FIX"
2791 [(set_attr "type" "fsqrt")
2792 (set_attr "trap" "yes")
2793 (set_attr "round_suffix" "normal")
2794 (set_attr "trap_suffix" "u_su_sui")])
2796 ;; Next are all the integer comparisons, and conditional moves and branches
2797 ;; and some of the related define_expand's and define_split's.
2799 (define_insn "*setcc_internal"
2800 [(set (match_operand 0 "register_operand" "=r")
2801 (match_operator 1 "alpha_comparison_operator"
2802 [(match_operand:DI 2 "register_operand" "r")
2803 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]))]
2804 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
2805 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
2806 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
2808 [(set_attr "type" "icmp")])
2810 ;; Yes, we can technically support reg_or_8bit_operand in operand 2,
2811 ;; but that's non-canonical rtl and allowing that causes inefficiencies
2813 (define_insn "*setcc_swapped_internal"
2814 [(set (match_operand 0 "register_operand" "=r")
2815 (match_operator 1 "alpha_swapped_comparison_operator"
2816 [(match_operand:DI 2 "register_operand" "r")
2817 (match_operand:DI 3 "reg_or_0_operand" "rJ")]))]
2818 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
2819 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
2820 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
2822 [(set_attr "type" "icmp")])
2824 ;; Use match_operator rather than ne directly so that we can match
2825 ;; multiple integer modes.
2826 (define_insn "*setne_internal"
2827 [(set (match_operand 0 "register_operand" "=r")
2828 (match_operator 1 "signed_comparison_operator"
2829 [(match_operand:DI 2 "register_operand" "r")
2831 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
2832 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
2833 && GET_CODE (operands[1]) == NE
2834 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
2836 [(set_attr "type" "icmp")])
2838 ;; The mode folding trick can't be used with const_int operands, since
2839 ;; reload needs to know the proper mode.
2841 ;; Use add_operand instead of the more seemingly natural reg_or_8bit_operand
2842 ;; in order to create more pairs of constants. As long as we're allowing
2843 ;; two constants at the same time, and will have to reload one of them...
2845 (define_insn "*movqicc_internal"
2846 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r")
2848 (match_operator 2 "signed_comparison_operator"
2849 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
2850 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
2851 (match_operand:QI 1 "add_operand" "rI,0,rI,0")
2852 (match_operand:QI 5 "add_operand" "0,rI,0,rI")))]
2853 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
2859 [(set_attr "type" "icmov")])
2861 (define_insn "*movhicc_internal"
2862 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
2864 (match_operator 2 "signed_comparison_operator"
2865 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
2866 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
2867 (match_operand:HI 1 "add_operand" "rI,0,rI,0")
2868 (match_operand:HI 5 "add_operand" "0,rI,0,rI")))]
2869 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
2875 [(set_attr "type" "icmov")])
2877 (define_insn "*movsicc_internal"
2878 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
2880 (match_operator 2 "signed_comparison_operator"
2881 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
2882 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
2883 (match_operand:SI 1 "add_operand" "rI,0,rI,0")
2884 (match_operand:SI 5 "add_operand" "0,rI,0,rI")))]
2885 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
2891 [(set_attr "type" "icmov")])
2893 (define_insn "*movdicc_internal"
2894 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
2896 (match_operator 2 "signed_comparison_operator"
2897 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
2898 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
2899 (match_operand:DI 1 "add_operand" "rI,0,rI,0")
2900 (match_operand:DI 5 "add_operand" "0,rI,0,rI")))]
2901 "(operands[3] == const0_rtx || operands[4] == const0_rtx)"
2907 [(set_attr "type" "icmov")])
2909 (define_insn "*movqicc_lbc"
2910 [(set (match_operand:QI 0 "register_operand" "=r,r")
2912 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2916 (match_operand:QI 1 "reg_or_8bit_operand" "rI,0")
2917 (match_operand:QI 3 "reg_or_8bit_operand" "0,rI")))]
2922 [(set_attr "type" "icmov")])
2924 (define_insn "*movhicc_lbc"
2925 [(set (match_operand:HI 0 "register_operand" "=r,r")
2927 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2931 (match_operand:HI 1 "reg_or_8bit_operand" "rI,0")
2932 (match_operand:HI 3 "reg_or_8bit_operand" "0,rI")))]
2937 [(set_attr "type" "icmov")])
2939 (define_insn "*movsicc_lbc"
2940 [(set (match_operand:SI 0 "register_operand" "=r,r")
2942 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2946 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0")
2947 (match_operand:SI 3 "reg_or_8bit_operand" "0,rI")))]
2952 [(set_attr "type" "icmov")])
2954 (define_insn "*movdicc_lbc"
2955 [(set (match_operand:DI 0 "register_operand" "=r,r")
2957 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2961 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
2962 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
2967 [(set_attr "type" "icmov")])
2969 (define_insn "*movqicc_lbs"
2970 [(set (match_operand:QI 0 "register_operand" "=r,r")
2972 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2976 (match_operand:QI 1 "reg_or_8bit_operand" "rI,0")
2977 (match_operand:QI 3 "reg_or_8bit_operand" "0,rI")))]
2982 [(set_attr "type" "icmov")])
2984 (define_insn "*movhicc_lbs"
2985 [(set (match_operand:HI 0 "register_operand" "=r,r")
2987 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2991 (match_operand:HI 1 "reg_or_8bit_operand" "rI,0")
2992 (match_operand:HI 3 "reg_or_8bit_operand" "0,rI")))]
2997 [(set_attr "type" "icmov")])
2999 (define_insn "*movsicc_lbs"
3000 [(set (match_operand:SI 0 "register_operand" "=r,r")
3002 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3006 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0")
3007 (match_operand:SI 3 "reg_or_8bit_operand" "0,rI")))]
3012 [(set_attr "type" "icmov")])
3014 (define_insn "*movdicc_lbs"
3015 [(set (match_operand:DI 0 "register_operand" "=r,r")
3017 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3021 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
3022 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
3027 [(set_attr "type" "icmov")])
3029 ;; For ABS, we have two choices, depending on whether the input and output
3030 ;; registers are the same or not.
3031 (define_expand "absdi2"
3032 [(set (match_operand:DI 0 "register_operand" "")
3033 (abs:DI (match_operand:DI 1 "register_operand" "")))]
3036 if (rtx_equal_p (operands[0], operands[1]))
3037 emit_insn (gen_absdi2_same (operands[0], gen_reg_rtx (DImode)));
3039 emit_insn (gen_absdi2_diff (operands[0], operands[1]));
3043 (define_expand "absdi2_same"
3044 [(set (match_operand:DI 1 "register_operand" "")
3045 (neg:DI (match_operand:DI 0 "register_operand" "")))
3047 (if_then_else:DI (ge (match_dup 0) (const_int 0))
3053 (define_expand "absdi2_diff"
3054 [(set (match_operand:DI 0 "register_operand" "")
3055 (neg:DI (match_operand:DI 1 "register_operand" "")))
3057 (if_then_else:DI (lt (match_dup 1) (const_int 0))
3064 [(set (match_operand:DI 0 "register_operand" "")
3065 (abs:DI (match_dup 0)))
3066 (clobber (match_operand:DI 1 "register_operand" ""))]
3068 [(set (match_dup 1) (neg:DI (match_dup 0)))
3069 (set (match_dup 0) (if_then_else:DI (ge (match_dup 0) (const_int 0))
3070 (match_dup 0) (match_dup 1)))]
3074 [(set (match_operand:DI 0 "register_operand" "")
3075 (abs:DI (match_operand:DI 1 "register_operand" "")))]
3076 "! rtx_equal_p (operands[0], operands[1])"
3077 [(set (match_dup 0) (neg:DI (match_dup 1)))
3078 (set (match_dup 0) (if_then_else:DI (lt (match_dup 1) (const_int 0))
3079 (match_dup 0) (match_dup 1)))]
3083 [(set (match_operand:DI 0 "register_operand" "")
3084 (neg:DI (abs:DI (match_dup 0))))
3085 (clobber (match_operand:DI 1 "register_operand" ""))]
3087 [(set (match_dup 1) (neg:DI (match_dup 0)))
3088 (set (match_dup 0) (if_then_else:DI (le (match_dup 0) (const_int 0))
3089 (match_dup 0) (match_dup 1)))]
3093 [(set (match_operand:DI 0 "register_operand" "")
3094 (neg:DI (abs:DI (match_operand:DI 1 "register_operand" ""))))]
3095 "! rtx_equal_p (operands[0], operands[1])"
3096 [(set (match_dup 0) (neg:DI (match_dup 1)))
3097 (set (match_dup 0) (if_then_else:DI (gt (match_dup 1) (const_int 0))
3098 (match_dup 0) (match_dup 1)))]
3101 (define_insn "sminqi3"
3102 [(set (match_operand:QI 0 "register_operand" "=r")
3103 (smin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3104 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3107 [(set_attr "type" "mvi")])
3109 (define_insn "uminqi3"
3110 [(set (match_operand:QI 0 "register_operand" "=r")
3111 (umin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3112 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3115 [(set_attr "type" "mvi")])
3117 (define_insn "smaxqi3"
3118 [(set (match_operand:QI 0 "register_operand" "=r")
3119 (smax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3120 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3123 [(set_attr "type" "mvi")])
3125 (define_insn "umaxqi3"
3126 [(set (match_operand:QI 0 "register_operand" "=r")
3127 (umax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3128 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3131 [(set_attr "type" "mvi")])
3133 (define_insn "sminhi3"
3134 [(set (match_operand:HI 0 "register_operand" "=r")
3135 (smin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3136 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3139 [(set_attr "type" "mvi")])
3141 (define_insn "uminhi3"
3142 [(set (match_operand:HI 0 "register_operand" "=r")
3143 (umin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3144 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3147 [(set_attr "type" "mvi")])
3149 (define_insn "smaxhi3"
3150 [(set (match_operand:HI 0 "register_operand" "=r")
3151 (smax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3152 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3155 [(set_attr "type" "mvi")])
3157 (define_insn "umaxhi3"
3158 [(set (match_operand:HI 0 "register_operand" "=r")
3159 (umax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3160 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3163 [(set_attr "type" "shift")])
3165 (define_expand "smaxdi3"
3167 (le:DI (match_operand:DI 1 "reg_or_0_operand" "")
3168 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3169 (set (match_operand:DI 0 "register_operand" "")
3170 (if_then_else:DI (eq (match_dup 3) (const_int 0))
3171 (match_dup 1) (match_dup 2)))]
3173 { operands[3] = gen_reg_rtx (DImode); })
3176 [(set (match_operand:DI 0 "register_operand" "")
3177 (smax:DI (match_operand:DI 1 "reg_or_0_operand" "")
3178 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3179 (clobber (match_operand:DI 3 "register_operand" ""))]
3180 "operands[2] != const0_rtx"
3181 [(set (match_dup 3) (le:DI (match_dup 1) (match_dup 2)))
3182 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
3183 (match_dup 1) (match_dup 2)))]
3186 (define_insn "*smax_const0"
3187 [(set (match_operand:DI 0 "register_operand" "=r")
3188 (smax:DI (match_operand:DI 1 "register_operand" "0")
3192 [(set_attr "type" "icmov")])
3194 (define_expand "smindi3"
3196 (lt:DI (match_operand:DI 1 "reg_or_0_operand" "")
3197 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3198 (set (match_operand:DI 0 "register_operand" "")
3199 (if_then_else:DI (ne (match_dup 3) (const_int 0))
3200 (match_dup 1) (match_dup 2)))]
3202 { operands[3] = gen_reg_rtx (DImode); })
3205 [(set (match_operand:DI 0 "register_operand" "")
3206 (smin:DI (match_operand:DI 1 "reg_or_0_operand" "")
3207 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3208 (clobber (match_operand:DI 3 "register_operand" ""))]
3209 "operands[2] != const0_rtx"
3210 [(set (match_dup 3) (lt:DI (match_dup 1) (match_dup 2)))
3211 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
3212 (match_dup 1) (match_dup 2)))]
3215 (define_insn "*smin_const0"
3216 [(set (match_operand:DI 0 "register_operand" "=r")
3217 (smin:DI (match_operand:DI 1 "register_operand" "0")
3221 [(set_attr "type" "icmov")])
3223 (define_expand "umaxdi3"
3225 (leu:DI (match_operand:DI 1 "reg_or_0_operand" "")
3226 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3227 (set (match_operand:DI 0 "register_operand" "")
3228 (if_then_else:DI (eq (match_dup 3) (const_int 0))
3229 (match_dup 1) (match_dup 2)))]
3231 "operands[3] = gen_reg_rtx (DImode);")
3234 [(set (match_operand:DI 0 "register_operand" "")
3235 (umax:DI (match_operand:DI 1 "reg_or_0_operand" "")
3236 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3237 (clobber (match_operand:DI 3 "register_operand" ""))]
3238 "operands[2] != const0_rtx"
3239 [(set (match_dup 3) (leu:DI (match_dup 1) (match_dup 2)))
3240 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
3241 (match_dup 1) (match_dup 2)))]
3244 (define_expand "umindi3"
3246 (ltu:DI (match_operand:DI 1 "reg_or_0_operand" "")
3247 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3248 (set (match_operand:DI 0 "register_operand" "")
3249 (if_then_else:DI (ne (match_dup 3) (const_int 0))
3250 (match_dup 1) (match_dup 2)))]
3252 "operands[3] = gen_reg_rtx (DImode);")
3255 [(set (match_operand:DI 0 "register_operand" "")
3256 (umin:DI (match_operand:DI 1 "reg_or_0_operand" "")
3257 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3258 (clobber (match_operand:DI 3 "register_operand" ""))]
3259 "operands[2] != const0_rtx"
3260 [(set (match_dup 3) (ltu:DI (match_dup 1) (match_dup 2)))
3261 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
3262 (match_dup 1) (match_dup 2)))]
3265 (define_insn "*bcc_normal"
3268 (match_operator 1 "signed_comparison_operator"
3269 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
3271 (label_ref (match_operand 0 "" ""))
3275 [(set_attr "type" "ibr")])
3277 (define_insn "*bcc_reverse"
3280 (match_operator 1 "signed_comparison_operator"
3281 [(match_operand:DI 2 "register_operand" "r")
3285 (label_ref (match_operand 0 "" ""))))]
3288 [(set_attr "type" "ibr")])
3290 (define_insn "*blbs_normal"
3293 (ne (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
3297 (label_ref (match_operand 0 "" ""))
3301 [(set_attr "type" "ibr")])
3303 (define_insn "*blbc_normal"
3306 (eq (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
3310 (label_ref (match_operand 0 "" ""))
3314 [(set_attr "type" "ibr")])
3320 (match_operator 1 "comparison_operator"
3321 [(zero_extract:DI (match_operand:DI 2 "register_operand" "")
3323 (match_operand:DI 3 "const_int_operand" ""))
3325 (label_ref (match_operand 0 "" ""))
3327 (clobber (match_operand:DI 4 "register_operand" ""))])]
3328 "INTVAL (operands[3]) != 0"
3330 (lshiftrt:DI (match_dup 2) (match_dup 3)))
3332 (if_then_else (match_op_dup 1
3333 [(zero_extract:DI (match_dup 4)
3337 (label_ref (match_dup 0))
3341 ;; The following are the corresponding floating-point insns. Recall
3342 ;; we need to have variants that expand the arguments from SFmode
3345 (define_insn "*cmpdf_ieee"
3346 [(set (match_operand:DF 0 "register_operand" "=&f")
3347 (match_operator:DF 1 "alpha_fp_comparison_operator"
3348 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3349 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
3350 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3351 "cmp%-%C1%/ %R2,%R3,%0"
3352 [(set_attr "type" "fadd")
3353 (set_attr "trap" "yes")
3354 (set_attr "trap_suffix" "su")])
3356 (define_insn "*cmpdf_internal"
3357 [(set (match_operand:DF 0 "register_operand" "=f")
3358 (match_operator:DF 1 "alpha_fp_comparison_operator"
3359 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3360 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
3361 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3362 "cmp%-%C1%/ %R2,%R3,%0"
3363 [(set_attr "type" "fadd")
3364 (set_attr "trap" "yes")
3365 (set_attr "trap_suffix" "su")])
3367 (define_insn "*cmpdf_ieee_ext1"
3368 [(set (match_operand:DF 0 "register_operand" "=&f")
3369 (match_operator:DF 1 "alpha_fp_comparison_operator"
3371 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3372 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
3373 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3374 "cmp%-%C1%/ %R2,%R3,%0"
3375 [(set_attr "type" "fadd")
3376 (set_attr "trap" "yes")
3377 (set_attr "trap_suffix" "su")])
3379 (define_insn "*cmpdf_ext1"
3380 [(set (match_operand:DF 0 "register_operand" "=f")
3381 (match_operator:DF 1 "alpha_fp_comparison_operator"
3383 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3384 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
3385 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3386 "cmp%-%C1%/ %R2,%R3,%0"
3387 [(set_attr "type" "fadd")
3388 (set_attr "trap" "yes")
3389 (set_attr "trap_suffix" "su")])
3391 (define_insn "*cmpdf_ieee_ext2"
3392 [(set (match_operand:DF 0 "register_operand" "=&f")
3393 (match_operator:DF 1 "alpha_fp_comparison_operator"
3394 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3396 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
3397 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3398 "cmp%-%C1%/ %R2,%R3,%0"
3399 [(set_attr "type" "fadd")
3400 (set_attr "trap" "yes")
3401 (set_attr "trap_suffix" "su")])
3403 (define_insn "*cmpdf_ext2"
3404 [(set (match_operand:DF 0 "register_operand" "=f")
3405 (match_operator:DF 1 "alpha_fp_comparison_operator"
3406 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3408 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
3409 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3410 "cmp%-%C1%/ %R2,%R3,%0"
3411 [(set_attr "type" "fadd")
3412 (set_attr "trap" "yes")
3413 (set_attr "trap_suffix" "su")])
3415 (define_insn "*cmpdf_ieee_ext3"
3416 [(set (match_operand:DF 0 "register_operand" "=&f")
3417 (match_operator:DF 1 "alpha_fp_comparison_operator"
3419 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3421 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
3422 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3423 "cmp%-%C1%/ %R2,%R3,%0"
3424 [(set_attr "type" "fadd")
3425 (set_attr "trap" "yes")
3426 (set_attr "trap_suffix" "su")])
3428 (define_insn "*cmpdf_ext3"
3429 [(set (match_operand:DF 0 "register_operand" "=f")
3430 (match_operator:DF 1 "alpha_fp_comparison_operator"
3432 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3434 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
3435 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3436 "cmp%-%C1%/ %R2,%R3,%0"
3437 [(set_attr "type" "fadd")
3438 (set_attr "trap" "yes")
3439 (set_attr "trap_suffix" "su")])
3441 (define_insn "*movdfcc_internal"
3442 [(set (match_operand:DF 0 "register_operand" "=f,f")
3444 (match_operator 3 "signed_comparison_operator"
3445 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
3446 (match_operand:DF 2 "fp0_operand" "G,G")])
3447 (match_operand:DF 1 "reg_or_fp0_operand" "fG,0")
3448 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
3452 fcmov%D3 %R4,%R5,%0"
3453 [(set_attr "type" "fcmov")])
3455 (define_insn "*movsfcc_internal"
3456 [(set (match_operand:SF 0 "register_operand" "=f,f")
3458 (match_operator 3 "signed_comparison_operator"
3459 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
3460 (match_operand:DF 2 "fp0_operand" "G,G")])
3461 (match_operand:SF 1 "reg_or_fp0_operand" "fG,0")
3462 (match_operand:SF 5 "reg_or_fp0_operand" "0,fG")))]
3466 fcmov%D3 %R4,%R5,%0"
3467 [(set_attr "type" "fcmov")])
3469 (define_insn "*movdfcc_ext1"
3470 [(set (match_operand:DF 0 "register_operand" "=f,f")
3472 (match_operator 3 "signed_comparison_operator"
3473 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
3474 (match_operand:DF 2 "fp0_operand" "G,G")])
3475 (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG,0"))
3476 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
3480 fcmov%D3 %R4,%R5,%0"
3481 [(set_attr "type" "fcmov")])
3483 (define_insn "*movdfcc_ext2"
3484 [(set (match_operand:DF 0 "register_operand" "=f,f")
3486 (match_operator 3 "signed_comparison_operator"
3488 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
3489 (match_operand:DF 2 "fp0_operand" "G,G")])
3490 (match_operand:DF 1 "reg_or_fp0_operand" "fG,0")
3491 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
3495 fcmov%D3 %R4,%R5,%0"
3496 [(set_attr "type" "fcmov")])
3498 (define_insn "*movdfcc_ext3"
3499 [(set (match_operand:SF 0 "register_operand" "=f,f")
3501 (match_operator 3 "signed_comparison_operator"
3503 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
3504 (match_operand:DF 2 "fp0_operand" "G,G")])
3505 (match_operand:SF 1 "reg_or_fp0_operand" "fG,0")
3506 (match_operand:SF 5 "reg_or_fp0_operand" "0,fG")))]
3510 fcmov%D3 %R4,%R5,%0"
3511 [(set_attr "type" "fcmov")])
3513 (define_insn "*movdfcc_ext4"
3514 [(set (match_operand:DF 0 "register_operand" "=f,f")
3516 (match_operator 3 "signed_comparison_operator"
3518 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
3519 (match_operand:DF 2 "fp0_operand" "G,G")])
3520 (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG,0"))
3521 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
3525 fcmov%D3 %R4,%R5,%0"
3526 [(set_attr "type" "fcmov")])
3528 (define_expand "maxdf3"
3530 (le:DF (match_operand:DF 1 "reg_or_fp0_operand" "")
3531 (match_operand:DF 2 "reg_or_fp0_operand" "")))
3532 (set (match_operand:DF 0 "register_operand" "")
3533 (if_then_else:DF (eq (match_dup 3) (match_dup 4))
3534 (match_dup 1) (match_dup 2)))]
3537 operands[3] = gen_reg_rtx (DFmode);
3538 operands[4] = CONST0_RTX (DFmode);
3541 (define_expand "mindf3"
3543 (lt:DF (match_operand:DF 1 "reg_or_fp0_operand" "")
3544 (match_operand:DF 2 "reg_or_fp0_operand" "")))
3545 (set (match_operand:DF 0 "register_operand" "")
3546 (if_then_else:DF (ne (match_dup 3) (match_dup 4))
3547 (match_dup 1) (match_dup 2)))]
3550 operands[3] = gen_reg_rtx (DFmode);
3551 operands[4] = CONST0_RTX (DFmode);
3554 (define_expand "maxsf3"
3556 (le:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" ""))
3557 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" ""))))
3558 (set (match_operand:SF 0 "register_operand" "")
3559 (if_then_else:SF (eq (match_dup 3) (match_dup 4))
3560 (match_dup 1) (match_dup 2)))]
3563 operands[3] = gen_reg_rtx (DFmode);
3564 operands[4] = CONST0_RTX (DFmode);
3567 (define_expand "minsf3"
3569 (lt:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" ""))
3570 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" ""))))
3571 (set (match_operand:SF 0 "register_operand" "")
3572 (if_then_else:SF (ne (match_dup 3) (match_dup 4))
3573 (match_dup 1) (match_dup 2)))]
3576 operands[3] = gen_reg_rtx (DFmode);
3577 operands[4] = CONST0_RTX (DFmode);
3580 (define_insn "*fbcc_normal"
3583 (match_operator 1 "signed_comparison_operator"
3584 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
3585 (match_operand:DF 3 "fp0_operand" "G")])
3586 (label_ref (match_operand 0 "" ""))
3590 [(set_attr "type" "fbr")])
3592 (define_insn "*fbcc_ext_normal"
3595 (match_operator 1 "signed_comparison_operator"
3597 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
3598 (match_operand:DF 3 "fp0_operand" "G")])
3599 (label_ref (match_operand 0 "" ""))
3603 [(set_attr "type" "fbr")])
3605 ;; These are the main define_expand's used to make conditional branches
3608 (define_expand "cmpdf"
3609 [(set (cc0) (compare (match_operand:DF 0 "reg_or_fp0_operand" "")
3610 (match_operand:DF 1 "reg_or_fp0_operand" "")))]
3613 alpha_compare.op0 = operands[0];
3614 alpha_compare.op1 = operands[1];
3615 alpha_compare.fp_p = 1;
3619 (define_expand "cmptf"
3620 [(set (cc0) (compare (match_operand:TF 0 "general_operand" "")
3621 (match_operand:TF 1 "general_operand" "")))]
3622 "TARGET_HAS_XFLOATING_LIBS"
3624 alpha_compare.op0 = operands[0];
3625 alpha_compare.op1 = operands[1];
3626 alpha_compare.fp_p = 1;
3630 (define_expand "cmpdi"
3631 [(set (cc0) (compare (match_operand:DI 0 "general_operand" "")
3632 (match_operand:DI 1 "general_operand" "")))]
3635 alpha_compare.op0 = operands[0];
3636 alpha_compare.op1 = operands[1];
3637 alpha_compare.fp_p = 0;
3641 (define_expand "beq"
3643 (if_then_else (match_dup 1)
3644 (label_ref (match_operand 0 "" ""))
3647 "{ operands[1] = alpha_emit_conditional_branch (EQ); }")
3649 (define_expand "bne"
3651 (if_then_else (match_dup 1)
3652 (label_ref (match_operand 0 "" ""))
3655 "{ operands[1] = alpha_emit_conditional_branch (NE); }")
3657 (define_expand "blt"
3659 (if_then_else (match_dup 1)
3660 (label_ref (match_operand 0 "" ""))
3663 "{ operands[1] = alpha_emit_conditional_branch (LT); }")
3665 (define_expand "ble"
3667 (if_then_else (match_dup 1)
3668 (label_ref (match_operand 0 "" ""))
3671 "{ operands[1] = alpha_emit_conditional_branch (LE); }")
3673 (define_expand "bgt"
3675 (if_then_else (match_dup 1)
3676 (label_ref (match_operand 0 "" ""))
3679 "{ operands[1] = alpha_emit_conditional_branch (GT); }")
3681 (define_expand "bge"
3683 (if_then_else (match_dup 1)
3684 (label_ref (match_operand 0 "" ""))
3687 "{ operands[1] = alpha_emit_conditional_branch (GE); }")
3689 (define_expand "bltu"
3691 (if_then_else (match_dup 1)
3692 (label_ref (match_operand 0 "" ""))
3695 "{ operands[1] = alpha_emit_conditional_branch (LTU); }")
3697 (define_expand "bleu"
3699 (if_then_else (match_dup 1)
3700 (label_ref (match_operand 0 "" ""))
3703 "{ operands[1] = alpha_emit_conditional_branch (LEU); }")
3705 (define_expand "bgtu"
3707 (if_then_else (match_dup 1)
3708 (label_ref (match_operand 0 "" ""))
3711 "{ operands[1] = alpha_emit_conditional_branch (GTU); }")
3713 (define_expand "bgeu"
3715 (if_then_else (match_dup 1)
3716 (label_ref (match_operand 0 "" ""))
3719 "{ operands[1] = alpha_emit_conditional_branch (GEU); }")
3721 (define_expand "bunordered"
3723 (if_then_else (match_dup 1)
3724 (label_ref (match_operand 0 "" ""))
3727 "{ operands[1] = alpha_emit_conditional_branch (UNORDERED); }")
3729 (define_expand "bordered"
3731 (if_then_else (match_dup 1)
3732 (label_ref (match_operand 0 "" ""))
3735 "{ operands[1] = alpha_emit_conditional_branch (ORDERED); }")
3737 (define_expand "seq"
3738 [(set (match_operand:DI 0 "register_operand" "")
3741 "{ if ((operands[1] = alpha_emit_setcc (EQ)) == NULL_RTX) FAIL; }")
3743 (define_expand "sne"
3744 [(set (match_operand:DI 0 "register_operand" "")
3747 "{ if ((operands[1] = alpha_emit_setcc (NE)) == NULL_RTX) FAIL; }")
3749 (define_expand "slt"
3750 [(set (match_operand:DI 0 "register_operand" "")
3753 "{ if ((operands[1] = alpha_emit_setcc (LT)) == NULL_RTX) FAIL; }")
3755 (define_expand "sle"
3756 [(set (match_operand:DI 0 "register_operand" "")
3759 "{ if ((operands[1] = alpha_emit_setcc (LE)) == NULL_RTX) FAIL; }")
3761 (define_expand "sgt"
3762 [(set (match_operand:DI 0 "register_operand" "")
3765 "{ if ((operands[1] = alpha_emit_setcc (GT)) == NULL_RTX) FAIL; }")
3767 (define_expand "sge"
3768 [(set (match_operand:DI 0 "register_operand" "")
3771 "{ if ((operands[1] = alpha_emit_setcc (GE)) == NULL_RTX) FAIL; }")
3773 (define_expand "sltu"
3774 [(set (match_operand:DI 0 "register_operand" "")
3777 "{ if ((operands[1] = alpha_emit_setcc (LTU)) == NULL_RTX) FAIL; }")
3779 (define_expand "sleu"
3780 [(set (match_operand:DI 0 "register_operand" "")
3783 "{ if ((operands[1] = alpha_emit_setcc (LEU)) == NULL_RTX) FAIL; }")
3785 (define_expand "sgtu"
3786 [(set (match_operand:DI 0 "register_operand" "")
3789 "{ if ((operands[1] = alpha_emit_setcc (GTU)) == NULL_RTX) FAIL; }")
3791 (define_expand "sgeu"
3792 [(set (match_operand:DI 0 "register_operand" "")
3795 "{ if ((operands[1] = alpha_emit_setcc (GEU)) == NULL_RTX) FAIL; }")
3797 (define_expand "sunordered"
3798 [(set (match_operand:DI 0 "register_operand" "")
3801 "{ if ((operands[1] = alpha_emit_setcc (UNORDERED)) == NULL_RTX) FAIL; }")
3803 (define_expand "sordered"
3804 [(set (match_operand:DI 0 "register_operand" "")
3807 "{ if ((operands[1] = alpha_emit_setcc (ORDERED)) == NULL_RTX) FAIL; }")
3809 ;; These are the main define_expand's used to make conditional moves.
3811 (define_expand "movsicc"
3812 [(set (match_operand:SI 0 "register_operand" "")
3813 (if_then_else:SI (match_operand 1 "comparison_operator" "")
3814 (match_operand:SI 2 "reg_or_8bit_operand" "")
3815 (match_operand:SI 3 "reg_or_8bit_operand" "")))]
3818 if ((operands[1] = alpha_emit_conditional_move (operands[1], SImode)) == 0)
3822 (define_expand "movdicc"
3823 [(set (match_operand:DI 0 "register_operand" "")
3824 (if_then_else:DI (match_operand 1 "comparison_operator" "")
3825 (match_operand:DI 2 "reg_or_8bit_operand" "")
3826 (match_operand:DI 3 "reg_or_8bit_operand" "")))]
3829 if ((operands[1] = alpha_emit_conditional_move (operands[1], DImode)) == 0)
3833 (define_expand "movsfcc"
3834 [(set (match_operand:SF 0 "register_operand" "")
3835 (if_then_else:SF (match_operand 1 "comparison_operator" "")
3836 (match_operand:SF 2 "reg_or_8bit_operand" "")
3837 (match_operand:SF 3 "reg_or_8bit_operand" "")))]
3840 if ((operands[1] = alpha_emit_conditional_move (operands[1], SFmode)) == 0)
3844 (define_expand "movdfcc"
3845 [(set (match_operand:DF 0 "register_operand" "")
3846 (if_then_else:DF (match_operand 1 "comparison_operator" "")
3847 (match_operand:DF 2 "reg_or_8bit_operand" "")
3848 (match_operand:DF 3 "reg_or_8bit_operand" "")))]
3851 if ((operands[1] = alpha_emit_conditional_move (operands[1], DFmode)) == 0)
3855 ;; These define_split definitions are used in cases when comparisons have
3856 ;; not be stated in the correct way and we need to reverse the second
3857 ;; comparison. For example, x >= 7 has to be done as x < 6 with the
3858 ;; comparison that tests the result being reversed. We have one define_split
3859 ;; for each use of a comparison. They do not match valid insns and need
3860 ;; not generate valid insns.
3862 ;; We can also handle equality comparisons (and inequality comparisons in
3863 ;; cases where the resulting add cannot overflow) by doing an add followed by
3864 ;; a comparison with zero. This is faster since the addition takes one
3865 ;; less cycle than a compare when feeding into a conditional move.
3866 ;; For this case, we also have an SImode pattern since we can merge the add
3867 ;; and sign extend and the order doesn't matter.
3869 ;; We do not do this for floating-point, since it isn't clear how the "wrong"
3870 ;; operation could have been generated.
3873 [(set (match_operand:DI 0 "register_operand" "")
3875 (match_operator 1 "comparison_operator"
3876 [(match_operand:DI 2 "reg_or_0_operand" "")
3877 (match_operand:DI 3 "reg_or_cint_operand" "")])
3878 (match_operand:DI 4 "reg_or_cint_operand" "")
3879 (match_operand:DI 5 "reg_or_cint_operand" "")))
3880 (clobber (match_operand:DI 6 "register_operand" ""))]
3881 "operands[3] != const0_rtx"
3882 [(set (match_dup 6) (match_dup 7))
3884 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
3886 enum rtx_code code = GET_CODE (operands[1]);
3887 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
3889 /* If we are comparing for equality with a constant and that constant
3890 appears in the arm when the register equals the constant, use the
3891 register since that is more likely to match (and to produce better code
3894 if (code == EQ && GET_CODE (operands[3]) == CONST_INT
3895 && rtx_equal_p (operands[4], operands[3]))
3896 operands[4] = operands[2];
3898 else if (code == NE && GET_CODE (operands[3]) == CONST_INT
3899 && rtx_equal_p (operands[5], operands[3]))
3900 operands[5] = operands[2];
3902 if (code == NE || code == EQ
3903 || (extended_count (operands[2], DImode, unsignedp) >= 1
3904 && extended_count (operands[3], DImode, unsignedp) >= 1))
3906 if (GET_CODE (operands[3]) == CONST_INT)
3907 operands[7] = gen_rtx_PLUS (DImode, operands[2],
3908 GEN_INT (- INTVAL (operands[3])));
3910 operands[7] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
3912 operands[8] = gen_rtx_fmt_ee (code, VOIDmode, operands[6], const0_rtx);
3915 else if (code == EQ || code == LE || code == LT
3916 || code == LEU || code == LTU)
3918 operands[7] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
3919 operands[8] = gen_rtx_NE (VOIDmode, operands[6], const0_rtx);
3923 operands[7] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
3924 operands[2], operands[3]);
3925 operands[8] = gen_rtx_EQ (VOIDmode, operands[6], const0_rtx);
3930 [(set (match_operand:DI 0 "register_operand" "")
3932 (match_operator 1 "comparison_operator"
3933 [(match_operand:SI 2 "reg_or_0_operand" "")
3934 (match_operand:SI 3 "reg_or_cint_operand" "")])
3935 (match_operand:DI 4 "reg_or_8bit_operand" "")
3936 (match_operand:DI 5 "reg_or_8bit_operand" "")))
3937 (clobber (match_operand:DI 6 "register_operand" ""))]
3938 "operands[3] != const0_rtx
3939 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
3940 [(set (match_dup 6) (match_dup 7))
3942 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
3944 enum rtx_code code = GET_CODE (operands[1]);
3945 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
3948 if ((code != NE && code != EQ
3949 && ! (extended_count (operands[2], DImode, unsignedp) >= 1
3950 && extended_count (operands[3], DImode, unsignedp) >= 1)))
3953 if (GET_CODE (operands[3]) == CONST_INT)
3954 tem = gen_rtx_PLUS (SImode, operands[2],
3955 GEN_INT (- INTVAL (operands[3])));
3957 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
3959 operands[7] = gen_rtx_SIGN_EXTEND (DImode, tem);
3960 operands[8] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
3961 operands[6], const0_rtx);
3967 (match_operator 1 "comparison_operator"
3968 [(match_operand:DI 2 "reg_or_0_operand" "")
3969 (match_operand:DI 3 "reg_or_cint_operand" "")])
3970 (label_ref (match_operand 0 "" ""))
3972 (clobber (match_operand:DI 4 "register_operand" ""))]
3973 "operands[3] != const0_rtx"
3974 [(set (match_dup 4) (match_dup 5))
3975 (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))]
3977 enum rtx_code code = GET_CODE (operands[1]);
3978 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
3980 if (code == NE || code == EQ
3981 || (extended_count (operands[2], DImode, unsignedp) >= 1
3982 && extended_count (operands[3], DImode, unsignedp) >= 1))
3984 if (GET_CODE (operands[3]) == CONST_INT)
3985 operands[5] = gen_rtx_PLUS (DImode, operands[2],
3986 GEN_INT (- INTVAL (operands[3])));
3988 operands[5] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
3990 operands[6] = gen_rtx_fmt_ee (code, VOIDmode, operands[4], const0_rtx);
3993 else if (code == EQ || code == LE || code == LT
3994 || code == LEU || code == LTU)
3996 operands[5] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
3997 operands[6] = gen_rtx_NE (VOIDmode, operands[4], const0_rtx);
4001 operands[5] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
4002 operands[2], operands[3]);
4003 operands[6] = gen_rtx_EQ (VOIDmode, operands[4], const0_rtx);
4010 (match_operator 1 "comparison_operator"
4011 [(match_operand:SI 2 "reg_or_0_operand" "")
4012 (match_operand:SI 3 "const_int_operand" "")])
4013 (label_ref (match_operand 0 "" ""))
4015 (clobber (match_operand:DI 4 "register_operand" ""))]
4016 "operands[3] != const0_rtx
4017 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
4018 [(set (match_dup 4) (match_dup 5))
4019 (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))]
4023 if (GET_CODE (operands[3]) == CONST_INT)
4024 tem = gen_rtx_PLUS (SImode, operands[2],
4025 GEN_INT (- INTVAL (operands[3])));
4027 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
4029 operands[5] = gen_rtx_SIGN_EXTEND (DImode, tem);
4030 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
4031 operands[4], const0_rtx);
4034 ;; We can convert such things as "a > 0xffff" to "t = a & ~ 0xffff; t != 0".
4035 ;; This eliminates one, and sometimes two, insns when the AND can be done
4038 [(set (match_operand:DI 0 "register_operand" "")
4039 (match_operator:DI 1 "comparison_operator"
4040 [(match_operand:DI 2 "register_operand" "")
4041 (match_operand:DI 3 "const_int_operand" "")]))
4042 (clobber (match_operand:DI 4 "register_operand" ""))]
4043 "exact_log2 (INTVAL (operands[3]) + 1) >= 0
4044 && (GET_CODE (operands[1]) == GTU
4045 || GET_CODE (operands[1]) == LEU
4046 || ((GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == LE)
4047 && extended_count (operands[2], DImode, 1) > 0))"
4048 [(set (match_dup 4) (and:DI (match_dup 2) (match_dup 5)))
4049 (set (match_dup 0) (match_dup 6))]
4051 operands[5] = GEN_INT (~ INTVAL (operands[3]));
4052 operands[6] = gen_rtx_fmt_ee (((GET_CODE (operands[1]) == GTU
4053 || GET_CODE (operands[1]) == GT)
4055 DImode, operands[4], const0_rtx);
4058 ;; Prefer to use cmp and arithmetic when possible instead of a cmove.
4061 [(set (match_operand 0 "register_operand" "")
4062 (if_then_else (match_operator 1 "signed_comparison_operator"
4063 [(match_operand:DI 2 "reg_or_0_operand" "")
4065 (match_operand 3 "const_int_operand" "")
4066 (match_operand 4 "const_int_operand" "")))]
4070 if (alpha_split_conditional_move (GET_CODE (operands[1]), operands[0],
4071 operands[2], operands[3], operands[4]))
4077 ;; ??? Why combine is allowed to create such non-canonical rtl, I don't know.
4078 ;; Oh well, we match it in movcc, so it must be partially our fault.
4080 [(set (match_operand 0 "register_operand" "")
4081 (if_then_else (match_operator 1 "signed_comparison_operator"
4083 (match_operand:DI 2 "reg_or_0_operand" "")])
4084 (match_operand 3 "const_int_operand" "")
4085 (match_operand 4 "const_int_operand" "")))]
4089 if (alpha_split_conditional_move (swap_condition (GET_CODE (operands[1])),
4090 operands[0], operands[2], operands[3],
4097 (define_insn_and_split "*cmp_sadd_di"
4098 [(set (match_operand:DI 0 "register_operand" "=r")
4099 (plus:DI (if_then_else:DI
4100 (match_operator 1 "alpha_zero_comparison_operator"
4101 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4103 (match_operand:DI 3 "const48_operand" "I")
4105 (match_operand:DI 4 "sext_add_operand" "rIO")))
4106 (clobber (match_scratch:DI 5 "=r"))]
4109 "! no_new_pseudos || reload_completed"
4111 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
4113 (plus:DI (mult:DI (match_dup 5) (match_dup 3))
4116 if (! no_new_pseudos)
4117 operands[5] = gen_reg_rtx (DImode);
4118 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4119 operands[5] = operands[0];
4122 (define_insn_and_split "*cmp_sadd_si"
4123 [(set (match_operand:SI 0 "register_operand" "=r")
4124 (plus:SI (if_then_else:SI
4125 (match_operator 1 "alpha_zero_comparison_operator"
4126 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4128 (match_operand:SI 3 "const48_operand" "I")
4130 (match_operand:SI 4 "sext_add_operand" "rIO")))
4131 (clobber (match_scratch:SI 5 "=r"))]
4134 "! no_new_pseudos || reload_completed"
4136 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4138 (plus:SI (mult:SI (match_dup 5) (match_dup 3))
4141 if (! no_new_pseudos)
4142 operands[5] = gen_reg_rtx (DImode);
4143 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4144 operands[5] = operands[0];
4147 (define_insn_and_split "*cmp_sadd_sidi"
4148 [(set (match_operand:DI 0 "register_operand" "=r")
4150 (plus:SI (if_then_else:SI
4151 (match_operator 1 "alpha_zero_comparison_operator"
4152 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4154 (match_operand:SI 3 "const48_operand" "I")
4156 (match_operand:SI 4 "sext_add_operand" "rIO"))))
4157 (clobber (match_scratch:SI 5 "=r"))]
4160 "! no_new_pseudos || reload_completed"
4162 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4164 (sign_extend:DI (plus:SI (mult:SI (match_dup 5) (match_dup 3))
4167 if (! no_new_pseudos)
4168 operands[5] = gen_reg_rtx (DImode);
4169 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4170 operands[5] = operands[0];
4173 (define_insn_and_split "*cmp_ssub_di"
4174 [(set (match_operand:DI 0 "register_operand" "=r")
4175 (minus:DI (if_then_else:DI
4176 (match_operator 1 "alpha_zero_comparison_operator"
4177 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4179 (match_operand:DI 3 "const48_operand" "I")
4181 (match_operand:DI 4 "reg_or_8bit_operand" "rI")))
4182 (clobber (match_scratch:DI 5 "=r"))]
4185 "! no_new_pseudos || reload_completed"
4187 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
4189 (minus:DI (mult:DI (match_dup 5) (match_dup 3))
4192 if (! no_new_pseudos)
4193 operands[5] = gen_reg_rtx (DImode);
4194 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4195 operands[5] = operands[0];
4198 (define_insn_and_split "*cmp_ssub_si"
4199 [(set (match_operand:SI 0 "register_operand" "=r")
4200 (minus:SI (if_then_else:SI
4201 (match_operator 1 "alpha_zero_comparison_operator"
4202 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4204 (match_operand:SI 3 "const48_operand" "I")
4206 (match_operand:SI 4 "reg_or_8bit_operand" "rI")))
4207 (clobber (match_scratch:SI 5 "=r"))]
4210 "! no_new_pseudos || reload_completed"
4212 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4214 (minus:SI (mult:SI (match_dup 5) (match_dup 3))
4217 if (! no_new_pseudos)
4218 operands[5] = gen_reg_rtx (DImode);
4219 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4220 operands[5] = operands[0];
4223 (define_insn_and_split "*cmp_ssub_sidi"
4224 [(set (match_operand:DI 0 "register_operand" "=r")
4226 (minus:SI (if_then_else:SI
4227 (match_operator 1 "alpha_zero_comparison_operator"
4228 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4230 (match_operand:SI 3 "const48_operand" "I")
4232 (match_operand:SI 4 "reg_or_8bit_operand" "rI"))))
4233 (clobber (match_scratch:SI 5 "=r"))]
4236 "! no_new_pseudos || reload_completed"
4238 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4240 (sign_extend:DI (minus:SI (mult:SI (match_dup 5) (match_dup 3))
4243 if (! no_new_pseudos)
4244 operands[5] = gen_reg_rtx (DImode);
4245 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4246 operands[5] = operands[0];
4249 ;; Here are the CALL and unconditional branch insns. Calls on NT and OSF
4250 ;; work differently, so we have different patterns for each.
4252 ;; On Unicos/Mk a call information word (CIW) must be generated for each
4253 ;; call. The CIW contains information about arguments passed in registers
4254 ;; and is stored in the caller's SSIB. Its offset relative to the beginning
4255 ;; of the SSIB is passed in $25. Handling this properly is quite complicated
4256 ;; in the presence of inlining since the CIWs for calls performed by the
4257 ;; inlined function must be stored in the SSIB of the function it is inlined
4258 ;; into as well. We encode the CIW in an unspec and append it to the list
4259 ;; of the CIWs for the current function only when the instruction for loading
4260 ;; $25 is generated.
4262 (define_expand "call"
4263 [(use (match_operand:DI 0 "" ""))
4264 (use (match_operand 1 "" ""))
4265 (use (match_operand 2 "" ""))
4266 (use (match_operand 3 "" ""))]
4269 if (TARGET_ABI_WINDOWS_NT)
4270 emit_call_insn (gen_call_nt (operands[0], operands[1]));
4271 else if (TARGET_ABI_OPEN_VMS)
4272 emit_call_insn (gen_call_vms (operands[0], operands[2]));
4273 else if (TARGET_ABI_UNICOSMK)
4274 emit_call_insn (gen_call_umk (operands[0], operands[2]));
4276 emit_call_insn (gen_call_osf (operands[0], operands[1]));
4280 (define_expand "sibcall"
4281 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4282 (match_operand 1 "" ""))
4283 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)])]
4286 if (GET_CODE (operands[0]) != MEM)
4288 operands[0] = XEXP (operands[0], 0);
4291 (define_expand "call_osf"
4292 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4293 (match_operand 1 "" ""))
4295 (clobber (reg:DI 26))])]
4298 if (GET_CODE (operands[0]) != MEM)
4301 operands[0] = XEXP (operands[0], 0);
4302 if (! call_operand (operands[0], Pmode))
4303 operands[0] = copy_to_mode_reg (Pmode, operands[0]);
4306 (define_expand "call_nt"
4307 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4308 (match_operand 1 "" ""))
4309 (clobber (reg:DI 26))])]
4312 if (GET_CODE (operands[0]) != MEM)
4315 operands[0] = XEXP (operands[0], 0);
4316 if (GET_CODE (operands[0]) != SYMBOL_REF && GET_CODE (operands[0]) != REG)
4317 operands[0] = force_reg (DImode, operands[0]);
4320 ;; Calls on Unicos/Mk are always indirect.
4321 ;; op 0: symbol ref for called function
4322 ;; op 1: CIW for $25 represented by an unspec
4324 (define_expand "call_umk"
4325 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4326 (match_operand 1 "" ""))
4328 (clobber (reg:DI 26))])]
4331 if (GET_CODE (operands[0]) != MEM)
4334 /* Always load the address of the called function into a register;
4335 load the CIW in $25. */
4337 operands[0] = XEXP (operands[0], 0);
4338 if (GET_CODE (operands[0]) != REG)
4339 operands[0] = force_reg (DImode, operands[0]);
4341 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
4345 ;; call openvms/alpha
4346 ;; op 0: symbol ref for called function
4347 ;; op 1: next_arg_reg (argument information value for R25)
4349 (define_expand "call_vms"
4350 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4351 (match_operand 1 "" ""))
4355 (clobber (reg:DI 27))])]
4358 if (GET_CODE (operands[0]) != MEM)
4361 operands[0] = XEXP (operands[0], 0);
4363 /* Always load AI with argument information, then handle symbolic and
4364 indirect call differently. Load RA and set operands[2] to PV in
4367 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
4368 if (GET_CODE (operands[0]) == SYMBOL_REF)
4370 rtx linkage = alpha_need_linkage (XSTR (operands[0], 0), 0);
4372 emit_move_insn (gen_rtx_REG (Pmode, 26), gen_rtx_MEM (Pmode, linkage));
4374 = validize_mem (gen_rtx_MEM (Pmode, plus_constant (linkage, 8)));
4378 emit_move_insn (gen_rtx_REG (Pmode, 26),
4379 gen_rtx_MEM (Pmode, plus_constant (operands[0], 8)));
4380 operands[2] = operands[0];
4385 (define_expand "call_value"
4386 [(use (match_operand 0 "" ""))
4387 (use (match_operand:DI 1 "" ""))
4388 (use (match_operand 2 "" ""))
4389 (use (match_operand 3 "" ""))
4390 (use (match_operand 4 "" ""))]
4393 if (TARGET_ABI_WINDOWS_NT)
4394 emit_call_insn (gen_call_value_nt (operands[0], operands[1], operands[2]));
4395 else if (TARGET_ABI_OPEN_VMS)
4396 emit_call_insn (gen_call_value_vms (operands[0], operands[1],
4398 else if (TARGET_ABI_UNICOSMK)
4399 emit_call_insn (gen_call_value_umk (operands[0], operands[1],
4402 emit_call_insn (gen_call_value_osf (operands[0], operands[1],
4407 (define_expand "sibcall_value"
4408 [(parallel [(set (match_operand 0 "" "")
4409 (call (mem:DI (match_operand 1 "" ""))
4410 (match_operand 2 "" "")))
4411 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)])]
4414 if (GET_CODE (operands[1]) != MEM)
4416 operands[1] = XEXP (operands[1], 0);
4419 (define_expand "call_value_osf"
4420 [(parallel [(set (match_operand 0 "" "")
4421 (call (mem:DI (match_operand 1 "" ""))
4422 (match_operand 2 "" "")))
4424 (clobber (reg:DI 26))])]
4427 if (GET_CODE (operands[1]) != MEM)
4430 operands[1] = XEXP (operands[1], 0);
4431 if (! call_operand (operands[1], Pmode))
4432 operands[1] = copy_to_mode_reg (Pmode, operands[1]);
4435 (define_expand "call_value_nt"
4436 [(parallel [(set (match_operand 0 "" "")
4437 (call (mem:DI (match_operand 1 "" ""))
4438 (match_operand 2 "" "")))
4439 (clobber (reg:DI 26))])]
4442 if (GET_CODE (operands[1]) != MEM)
4445 operands[1] = XEXP (operands[1], 0);
4446 if (GET_CODE (operands[1]) != SYMBOL_REF && GET_CODE (operands[1]) != REG)
4447 operands[1] = force_reg (DImode, operands[1]);
4450 (define_expand "call_value_vms"
4451 [(parallel [(set (match_operand 0 "" "")
4452 (call (mem:DI (match_operand:DI 1 "" ""))
4453 (match_operand 2 "" "")))
4457 (clobber (reg:DI 27))])]
4460 if (GET_CODE (operands[1]) != MEM)
4463 operands[1] = XEXP (operands[1], 0);
4465 /* Always load AI with argument information, then handle symbolic and
4466 indirect call differently. Load RA and set operands[3] to PV in
4469 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
4470 if (GET_CODE (operands[1]) == SYMBOL_REF)
4472 rtx linkage = alpha_need_linkage (XSTR (operands[1], 0), 0);
4474 emit_move_insn (gen_rtx_REG (Pmode, 26), gen_rtx_MEM (Pmode, linkage));
4476 = validize_mem (gen_rtx_MEM (Pmode, plus_constant (linkage, 8)));
4480 emit_move_insn (gen_rtx_REG (Pmode, 26),
4481 gen_rtx_MEM (Pmode, plus_constant (operands[1], 8)));
4482 operands[3] = operands[1];
4486 (define_expand "call_value_umk"
4487 [(parallel [(set (match_operand 0 "" "")
4488 (call (mem:DI (match_operand 1 "" ""))
4489 (match_operand 2 "" "")))
4491 (clobber (reg:DI 26))])]
4494 if (GET_CODE (operands[1]) != MEM)
4497 operands[1] = XEXP (operands[1], 0);
4498 if (GET_CODE (operands[1]) != REG)
4499 operands[1] = force_reg (DImode, operands[1]);
4501 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
4504 (define_insn "*call_osf_1_er"
4505 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4506 (match_operand 1 "" ""))
4508 (clobber (reg:DI 26))]
4509 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4511 jsr $26,(%0),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*
4513 ldq $27,%0($29)\t\t!literal!%#\;jsr $26,($27),%0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*"
4514 [(set_attr "type" "jsr")
4515 (set_attr "length" "12,*,16")])
4517 ;; We must use peep2 instead of a split because we need accurate life
4518 ;; information for $gp. Consider the case of { bar(); while (1); }.
4520 [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand" ""))
4521 (match_operand 1 "" ""))
4523 (clobber (reg:DI 26))])]
4524 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
4525 && ! current_file_function_operand (operands[0], Pmode)
4526 && peep2_regno_dead_p (1, 29)"
4527 [(parallel [(call (mem:DI (match_dup 2))
4529 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
4530 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
4532 (use (match_dup 3))])]
4534 if (CONSTANT_P (operands[0]))
4536 operands[2] = gen_rtx_REG (Pmode, 27);
4537 operands[3] = GEN_INT (alpha_next_sequence_number++);
4538 emit_insn (gen_movdi_er_high_g (operands[2], pic_offset_table_rtx,
4539 operands[0], operands[3]));
4543 operands[2] = operands[0];
4544 operands[0] = const0_rtx;
4545 operands[3] = const0_rtx;
4550 [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand" ""))
4551 (match_operand 1 "" ""))
4553 (clobber (reg:DI 26))])]
4554 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
4555 && ! current_file_function_operand (operands[0], Pmode)
4556 && ! peep2_regno_dead_p (1, 29)"
4557 [(parallel [(call (mem:DI (match_dup 2))
4559 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
4560 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
4562 (use (match_dup 4))])
4564 (unspec_volatile:DI [(reg:DI 26) (match_dup 3)] UNSPECV_LDGP1))
4566 (unspec:DI [(reg:DI 29) (match_dup 3)] UNSPEC_LDGP2))]
4568 if (CONSTANT_P (operands[0]))
4570 operands[2] = gen_rtx_REG (Pmode, 27);
4571 operands[4] = GEN_INT (alpha_next_sequence_number++);
4572 emit_insn (gen_movdi_er_high_g (operands[2], pic_offset_table_rtx,
4573 operands[0], operands[4]));
4577 operands[2] = operands[0];
4578 operands[0] = const0_rtx;
4579 operands[4] = const0_rtx;
4581 operands[3] = GEN_INT (alpha_next_sequence_number++);
4584 ;; We add a blockage unspec_volatile to prevent insns from moving down
4585 ;; from above the call to in between the call and the ldah gpdisp.
4587 (define_insn "*call_osf_2_er"
4588 [(call (mem:DI (match_operand:DI 0 "register_operand" "c"))
4589 (match_operand 1 "" ""))
4590 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
4591 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
4592 (use (match_operand 2 "" ""))
4593 (use (match_operand 3 "const_int_operand" ""))]
4594 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4595 "jsr $26,(%0),%2%J3"
4596 [(set_attr "type" "jsr")])
4598 (define_insn "*call_osf_1_noreturn"
4599 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4600 (match_operand 1 "" ""))
4602 (clobber (reg:DI 26))]
4603 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
4604 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
4609 [(set_attr "type" "jsr")
4610 (set_attr "length" "*,*,8")])
4612 (define_insn "*call_osf_1"
4613 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4614 (match_operand 1 "" ""))
4616 (clobber (reg:DI 26))]
4617 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4619 jsr $26,($27),0\;ldgp $29,0($26)
4621 jsr $26,%0\;ldgp $29,0($26)"
4622 [(set_attr "type" "jsr")
4623 (set_attr "length" "12,*,16")])
4625 ;; Note that the DEC assembler expands "jmp foo" with $at, which
4626 ;; doesn't do what we want.
4627 (define_insn "*sibcall_osf_1_er"
4628 [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s"))
4629 (match_operand 1 "" ""))
4630 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
4631 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4634 ldq $27,%0($29)\t\t!literal!%#\;jmp $31,($27),%0\t\t!lituse_jsr!%#"
4635 [(set_attr "type" "jsr")
4636 (set_attr "length" "*,8")])
4638 (define_insn "*sibcall_osf_1"
4639 [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s"))
4640 (match_operand 1 "" ""))
4641 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
4642 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4645 lda $27,%0\;jmp $31,($27),%0"
4646 [(set_attr "type" "jsr")
4647 (set_attr "length" "*,8")])
4649 (define_insn "*call_nt_1"
4650 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,R,s"))
4651 (match_operand 1 "" ""))
4652 (clobber (reg:DI 26))]
4653 "TARGET_ABI_WINDOWS_NT"
4658 [(set_attr "type" "jsr")
4659 (set_attr "length" "*,*,12")])
4661 (define_insn "*call_vms_1"
4662 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,s"))
4663 (match_operand 1 "" ""))
4664 (use (match_operand:DI 2 "nonimmediate_operand" "r,m"))
4667 (clobber (reg:DI 27))]
4668 "TARGET_ABI_OPEN_VMS"
4670 mov %2,$27\;jsr $26,0\;ldq $27,0($29)
4671 ldq $27,%2\;jsr $26,%0\;ldq $27,0($29)"
4672 [(set_attr "type" "jsr")
4673 (set_attr "length" "12,16")])
4675 (define_insn "*call_umk_1"
4676 [(call (mem:DI (match_operand:DI 0 "call_operand" "r"))
4677 (match_operand 1 "" ""))
4679 (clobber (reg:DI 26))]
4680 "TARGET_ABI_UNICOSMK"
4682 [(set_attr "type" "jsr")])
4684 ;; Call subroutine returning any type.
4686 (define_expand "untyped_call"
4687 [(parallel [(call (match_operand 0 "" "")
4689 (match_operand 1 "" "")
4690 (match_operand 2 "" "")])]
4695 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
4697 for (i = 0; i < XVECLEN (operands[2], 0); i++)
4699 rtx set = XVECEXP (operands[2], 0, i);
4700 emit_move_insn (SET_DEST (set), SET_SRC (set));
4703 /* The optimizer does not know that the call sets the function value
4704 registers we stored in the result block. We avoid problems by
4705 claiming that all hard registers are used and clobbered at this
4707 emit_insn (gen_blockage ());
4712 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
4713 ;; all of memory. This blocks insns from being moved across this point.
4715 (define_insn "blockage"
4716 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
4719 [(set_attr "length" "0")
4720 (set_attr "type" "none")])
4724 (label_ref (match_operand 0 "" "")))]
4727 [(set_attr "type" "ibr")])
4729 (define_expand "return"
4734 (define_insn "*return_internal"
4738 [(set_attr "type" "ibr")])
4740 (define_insn "indirect_jump"
4741 [(set (pc) (match_operand:DI 0 "register_operand" "r"))]
4744 [(set_attr "type" "ibr")])
4746 (define_expand "tablejump"
4747 [(parallel [(set (pc)
4748 (match_operand 0 "register_operand" ""))
4749 (use (label_ref:DI (match_operand 1 "" "")))])]
4752 if (TARGET_ABI_WINDOWS_NT)
4754 rtx dest = gen_reg_rtx (DImode);
4755 emit_insn (gen_extendsidi2 (dest, operands[0]));
4758 else if (TARGET_ABI_OSF)
4760 rtx dest = gen_reg_rtx (DImode);
4761 emit_insn (gen_extendsidi2 (dest, operands[0]));
4762 emit_insn (gen_adddi3 (dest, pic_offset_table_rtx, dest));
4767 (define_insn "*tablejump_osf_nt_internal"
4769 (match_operand:DI 0 "register_operand" "r"))
4770 (use (label_ref:DI (match_operand 1 "" "")))]
4771 "(TARGET_ABI_OSF || TARGET_ABI_WINDOWS_NT)
4772 && alpha_tablejump_addr_vec (insn)"
4774 operands[2] = alpha_tablejump_best_label (insn);
4775 return "jmp $31,(%0),%2";
4777 [(set_attr "type" "ibr")])
4779 (define_insn "*tablejump_internal"
4781 (match_operand:DI 0 "register_operand" "r"))
4782 (use (label_ref (match_operand 1 "" "")))]
4785 [(set_attr "type" "ibr")])
4787 ;; Cache flush. Used by INITIALIZE_TRAMPOLINE. 0x86 is PAL_imb, but we don't
4788 ;; want to have to include pal.h in our .s file.
4790 ;; Technically the type for call_pal is jsr, but we use that for determining
4791 ;; if we need a GP. Use ibr instead since it has the same EV5 scheduling
4794 [(unspec_volatile [(const_int 0)] UNSPECV_IMB)]
4797 [(set_attr "type" "ibr")])
4799 ;; BUGCHK is documented common to OSF/1 and VMS PALcode.
4800 ;; NT does not document anything at 0x81 -- presumably it would generate
4801 ;; the equivalent of SIGILL, but this isn't that important.
4802 ;; ??? Presuming unicosmk uses either OSF/1 or VMS PALcode.
4804 [(trap_if (const_int 1) (const_int 0))]
4805 "!TARGET_ABI_WINDOWS_NT"
4807 [(set_attr "type" "ibr")])
4809 ;; Finally, we have the basic data motion insns. The byte and word insns
4810 ;; are done via define_expand. Start with the floating-point insns, since
4811 ;; they are simpler.
4813 (define_insn "*movsf_nofix"
4814 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
4815 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
4816 "TARGET_FPREGS && ! TARGET_FIX
4817 && (register_operand (operands[0], SFmode)
4818 || reg_or_fp0_operand (operands[1], SFmode))"
4826 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
4828 (define_insn "*movsf_fix"
4829 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
4830 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
4831 "TARGET_FPREGS && TARGET_FIX
4832 && (register_operand (operands[0], SFmode)
4833 || reg_or_fp0_operand (operands[1], SFmode))"
4843 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
4845 (define_insn "*movsf_nofp"
4846 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m")
4847 (match_operand:SF 1 "input_operand" "rG,m,r"))]
4849 && (register_operand (operands[0], SFmode)
4850 || reg_or_fp0_operand (operands[1], SFmode))"
4855 [(set_attr "type" "ilog,ild,ist")])
4857 (define_insn "*movdf_nofix"
4858 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
4859 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
4860 "TARGET_FPREGS && ! TARGET_FIX
4861 && (register_operand (operands[0], DFmode)
4862 || reg_or_fp0_operand (operands[1], DFmode))"
4870 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
4872 (define_insn "*movdf_fix"
4873 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
4874 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
4875 "TARGET_FPREGS && TARGET_FIX
4876 && (register_operand (operands[0], DFmode)
4877 || reg_or_fp0_operand (operands[1], DFmode))"
4887 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
4889 (define_insn "*movdf_nofp"
4890 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m")
4891 (match_operand:DF 1 "input_operand" "rG,m,r"))]
4893 && (register_operand (operands[0], DFmode)
4894 || reg_or_fp0_operand (operands[1], DFmode))"
4899 [(set_attr "type" "ilog,ild,ist")])
4901 ;; Subregs suck for register allocation. Pretend we can move TFmode
4902 ;; data between general registers until after reload.
4904 (define_insn_and_split "*movtf_internal"
4905 [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o")
4906 (match_operand:TF 1 "input_operand" "roG,rG"))]
4907 "register_operand (operands[0], TFmode)
4908 || reg_or_fp0_operand (operands[1], TFmode)"
4911 [(set (match_dup 0) (match_dup 2))
4912 (set (match_dup 1) (match_dup 3))]
4914 alpha_split_tfmode_pair (operands);
4915 if (reg_overlap_mentioned_p (operands[0], operands[3]))
4918 tmp = operands[0], operands[0] = operands[1], operands[1] = tmp;
4919 tmp = operands[2], operands[2] = operands[3], operands[3] = tmp;
4923 (define_expand "movsf"
4924 [(set (match_operand:SF 0 "nonimmediate_operand" "")
4925 (match_operand:SF 1 "general_operand" ""))]
4928 if (GET_CODE (operands[0]) == MEM
4929 && ! reg_or_fp0_operand (operands[1], SFmode))
4930 operands[1] = force_reg (SFmode, operands[1]);
4933 (define_expand "movdf"
4934 [(set (match_operand:DF 0 "nonimmediate_operand" "")
4935 (match_operand:DF 1 "general_operand" ""))]
4938 if (GET_CODE (operands[0]) == MEM
4939 && ! reg_or_fp0_operand (operands[1], DFmode))
4940 operands[1] = force_reg (DFmode, operands[1]);
4943 (define_expand "movtf"
4944 [(set (match_operand:TF 0 "nonimmediate_operand" "")
4945 (match_operand:TF 1 "general_operand" ""))]
4948 if (GET_CODE (operands[0]) == MEM
4949 && ! reg_or_fp0_operand (operands[1], TFmode))
4950 operands[1] = force_reg (TFmode, operands[1]);
4953 (define_insn "*movsi_nofix"
4954 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m,*f,*f,m")
4955 (match_operand:SI 1 "input_operand" "rJ,K,L,m,rJ,*fJ,m,*f"))]
4956 "(TARGET_ABI_OSF || TARGET_ABI_UNICOSMK) && ! TARGET_FIX
4957 && (register_operand (operands[0], SImode)
4958 || reg_or_0_operand (operands[1], SImode))"
4968 [(set_attr "type" "ilog,iadd,iadd,ild,ist,fcpys,fld,fst")])
4970 (define_insn "*movsi_fix"
4971 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m,*f,*f,m,r,*f")
4972 (match_operand:SI 1 "input_operand" "rJ,K,L,m,rJ,*fJ,m,*f,*f,r"))]
4973 "TARGET_ABI_OSF && TARGET_FIX
4974 && (register_operand (operands[0], SImode)
4975 || reg_or_0_operand (operands[1], SImode))"
4987 [(set_attr "type" "ilog,iadd,iadd,ild,ist,fcpys,fld,fst,ftoi,itof")])
4989 (define_insn "*movsi_nt_vms_nofix"
4990 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,m")
4991 (match_operand:SI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,m,*f"))]
4992 "(TARGET_ABI_WINDOWS_NT || TARGET_ABI_OPEN_VMS)
4994 && (register_operand (operands[0], SImode)
4995 || reg_or_0_operand (operands[1], SImode))"
5006 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst")])
5008 (define_insn "*movsi_nt_vms_fix"
5009 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,m,r,*f")
5010 (match_operand:SI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,m,*f,*f,r"))]
5011 "(TARGET_ABI_WINDOWS_NT || TARGET_ABI_OPEN_VMS)
5013 && (register_operand (operands[0], SImode)
5014 || reg_or_0_operand (operands[1], SImode))"
5027 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof")])
5029 (define_insn "*movhi_nobwx"
5030 [(set (match_operand:HI 0 "register_operand" "=r,r")
5031 (match_operand:HI 1 "input_operand" "rJ,n"))]
5033 && (register_operand (operands[0], HImode)
5034 || register_operand (operands[1], HImode))"
5038 [(set_attr "type" "ilog,iadd")])
5040 (define_insn "*movhi_bwx"
5041 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
5042 (match_operand:HI 1 "input_operand" "rJ,n,m,rJ"))]
5044 && (register_operand (operands[0], HImode)
5045 || reg_or_0_operand (operands[1], HImode))"
5051 [(set_attr "type" "ilog,iadd,ild,ist")])
5053 (define_insn "*movqi_nobwx"
5054 [(set (match_operand:QI 0 "register_operand" "=r,r")
5055 (match_operand:QI 1 "input_operand" "rJ,n"))]
5057 && (register_operand (operands[0], QImode)
5058 || register_operand (operands[1], QImode))"
5062 [(set_attr "type" "ilog,iadd")])
5064 (define_insn "*movqi_bwx"
5065 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m")
5066 (match_operand:QI 1 "input_operand" "rJ,n,m,rJ"))]
5068 && (register_operand (operands[0], QImode)
5069 || reg_or_0_operand (operands[1], QImode))"
5075 [(set_attr "type" "ilog,iadd,ild,ist")])
5077 ;; We do two major things here: handle mem->mem and construct long
5080 (define_expand "movsi"
5081 [(set (match_operand:SI 0 "nonimmediate_operand" "")
5082 (match_operand:SI 1 "general_operand" ""))]
5085 if (alpha_expand_mov (SImode, operands))
5089 ;; Split a load of a large constant into the appropriate two-insn
5093 [(set (match_operand:SI 0 "register_operand" "")
5094 (match_operand:SI 1 "const_int_operand" ""))]
5095 "! add_operand (operands[1], SImode)"
5096 [(set (match_dup 0) (match_dup 2))
5097 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
5100 = alpha_emit_set_const (operands[0], SImode, INTVAL (operands[1]), 2);
5102 if (tem == operands[0])
5108 ;; Split the load of an address into a four-insn sequence on Unicos/Mk.
5109 ;; Always generate a REG_EQUAL note for the last instruction to facilitate
5110 ;; optimisations. If the symbolic operand is a label_ref, generate REG_LABEL
5111 ;; notes and update LABEL_NUSES because this is not done automatically.
5112 ;; Labels may be incorrectly deleted if we don't do this.
5114 ;; Describing what the individual instructions do correctly is too complicated
5115 ;; so use UNSPECs for each of the three parts of an address.
5118 [(set (match_operand:DI 0 "register_operand" "")
5119 (match_operand:DI 1 "symbolic_operand" ""))]
5120 "TARGET_ABI_UNICOSMK && reload_completed"
5123 rtx insn1, insn2, insn3;
5125 insn1 = emit_insn (gen_umk_laum (operands[0], operands[1]));
5126 emit_insn (gen_ashldi3 (operands[0], operands[0], GEN_INT (32)));
5127 insn2 = emit_insn (gen_umk_lalm (operands[0], operands[0], operands[1]));
5128 insn3 = emit_insn (gen_umk_lal (operands[0], operands[0], operands[1]));
5129 REG_NOTES (insn3) = gen_rtx_EXPR_LIST (REG_EQUAL, operands[1],
5131 if (GET_CODE (operands[1]) == LABEL_REF)
5135 label = XEXP (operands[1], 0);
5136 REG_NOTES (insn1) = gen_rtx_EXPR_LIST (REG_LABEL, label,
5138 REG_NOTES (insn2) = gen_rtx_EXPR_LIST (REG_LABEL, label,
5140 REG_NOTES (insn3) = gen_rtx_EXPR_LIST (REG_LABEL, label,
5142 LABEL_NUSES (label) += 3;
5147 ;; Instructions for loading the three parts of an address on Unicos/Mk.
5149 (define_insn "umk_laum"
5150 [(set (match_operand:DI 0 "register_operand" "=r")
5151 (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
5153 "TARGET_ABI_UNICOSMK"
5155 [(set_attr "type" "iadd")])
5157 (define_insn "umk_lalm"
5158 [(set (match_operand:DI 0 "register_operand" "=r")
5159 (plus:DI (match_operand:DI 1 "register_operand" "r")
5160 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
5162 "TARGET_ABI_UNICOSMK"
5164 [(set_attr "type" "iadd")])
5166 (define_insn "umk_lal"
5167 [(set (match_operand:DI 0 "register_operand" "=r")
5168 (plus:DI (match_operand:DI 1 "register_operand" "r")
5169 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
5171 "TARGET_ABI_UNICOSMK"
5173 [(set_attr "type" "iadd")])
5175 ;; Add a new call information word to the current function's list of CIWs
5176 ;; and load its index into $25. Doing it here ensures that the CIW will be
5177 ;; associated with the correct function even in the presence of inlining.
5179 (define_insn "*umk_load_ciw"
5181 (unspec:DI [(match_operand 0 "" "")] UNSPEC_UMK_LOAD_CIW))]
5182 "TARGET_ABI_UNICOSMK"
5184 operands[0] = unicosmk_add_call_info_word (operands[0]);
5185 return "lda $25,%0";
5187 [(set_attr "type" "iadd")])
5189 (define_insn "*movdi_er_low_l"
5190 [(set (match_operand:DI 0 "register_operand" "=r")
5191 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
5192 (match_operand:DI 2 "local_symbolic_operand" "")))]
5193 "TARGET_EXPLICIT_RELOCS"
5195 if (true_regnum (operands[1]) == 29)
5196 return "lda %0,%2(%1)\t\t!gprel";
5198 return "lda %0,%2(%1)\t\t!gprellow";
5202 [(set (match_operand:DI 0 "register_operand" "")
5203 (match_operand:DI 1 "small_symbolic_operand" ""))]
5204 "TARGET_EXPLICIT_RELOCS && reload_completed"
5206 (lo_sum:DI (match_dup 2) (match_dup 1)))]
5207 "operands[2] = pic_offset_table_rtx;")
5210 [(set (match_operand:DI 0 "register_operand" "")
5211 (match_operand:DI 1 "local_symbolic_operand" ""))]
5212 "TARGET_EXPLICIT_RELOCS && reload_completed"
5214 (plus:DI (match_dup 2) (high:DI (match_dup 1))))
5216 (lo_sum:DI (match_dup 0) (match_dup 1)))]
5217 "operands[2] = pic_offset_table_rtx;")
5220 [(match_operand 0 "some_small_symbolic_operand" "")]
5221 "TARGET_EXPLICIT_RELOCS && reload_completed"
5223 "operands[0] = split_small_symbolic_operand (operands[0]);")
5225 (define_insn "movdi_er_high_g"
5226 [(set (match_operand:DI 0 "register_operand" "=r")
5227 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5228 (match_operand:DI 2 "global_symbolic_operand" "")
5229 (match_operand 3 "const_int_operand" "")]
5231 "TARGET_EXPLICIT_RELOCS"
5233 if (INTVAL (operands[3]) == 0)
5234 return "ldq %0,%2(%1)\t\t!literal";
5236 return "ldq %0,%2(%1)\t\t!literal!%3";
5238 [(set_attr "type" "ldsym")])
5241 [(set (match_operand:DI 0 "register_operand" "")
5242 (match_operand:DI 1 "global_symbolic_operand" ""))]
5243 "TARGET_EXPLICIT_RELOCS && reload_completed"
5245 (unspec:DI [(match_dup 2)
5247 (const_int 0)] UNSPEC_LITERAL))]
5248 "operands[2] = pic_offset_table_rtx;")
5250 ;; With RTL inlining, at -O3, rtl is generated, stored, then actually
5251 ;; compiled at the end of compilation. In the meantime, someone can
5252 ;; re-encode-section-info on some symbol changing it e.g. from global
5253 ;; to local-not-small. If this happens, we'd have emitted a plain
5254 ;; load rather than a high+losum load and not recognize the insn.
5256 ;; So if rtl inlining is in effect, we delay the global/not-global
5257 ;; decision until rest_of_compilation by wrapping it in an UNSPEC_SYMBOL.
5259 (define_insn_and_split "movdi_er_maybe_g"
5260 [(set (match_operand:DI 0 "register_operand" "=r")
5261 (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
5263 "TARGET_EXPLICIT_RELOCS && flag_inline_functions"
5266 [(set (match_dup 0) (match_dup 1))]
5268 if (local_symbolic_operand (operands[1], Pmode)
5269 && !small_symbolic_operand (operands[1], Pmode))
5271 rtx subtarget = no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode);
5274 tmp = gen_rtx_HIGH (Pmode, operands[1]);
5275 if (reload_completed)
5276 tmp = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, tmp);
5277 emit_insn (gen_rtx_SET (VOIDmode, subtarget, tmp));
5279 tmp = gen_rtx_LO_SUM (Pmode, subtarget, operands[1]);
5280 emit_insn (gen_rtx_SET (VOIDmode, operands[0], tmp));
5285 (define_insn "*movdi_er_nofix"
5286 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m,*f,*f,Q")
5287 (match_operand:DI 1 "input_operand" "rJ,K,L,T,s,m,rJ,*fJ,Q,*f"))]
5288 "TARGET_EXPLICIT_RELOCS && ! TARGET_FIX
5289 && (register_operand (operands[0], DImode)
5290 || reg_or_0_operand (operands[1], DImode))"
5302 [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst")])
5304 ;; The 'U' constraint matches symbolic operands on Unicos/Mk. Those should
5305 ;; have been split up by the rules above but we shouldn't reject the
5306 ;; possibility of them getting through.
5308 (define_insn "*movdi_nofix"
5309 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m,*f,*f,Q")
5310 (match_operand:DI 1 "input_operand" "rJ,K,L,U,s,m,rJ,*fJ,Q,*f"))]
5312 && (register_operand (operands[0], DImode)
5313 || reg_or_0_operand (operands[1], DImode))"
5318 laum %0,%t1($31)\;sll %0,32,%0\;lalm %0,%t1(%0)\;lal %0,%t1(%0)
5325 [(set_attr "type" "ilog,iadd,iadd,ldsym,ldsym,ild,ist,fcpys,fld,fst")
5326 (set_attr "length" "*,*,*,16,*,*,*,*,*,*")])
5328 (define_insn "*movdi_er_fix"
5329 [(set (match_operand:DI 0 "nonimmediate_operand"
5330 "=r,r,r,r,r,r, m, *f,*f, Q, r,*f")
5331 (match_operand:DI 1 "input_operand"
5332 "rJ,K,L,T,s,m,rJ,*fJ, Q,*f,*f, r"))]
5333 "TARGET_EXPLICIT_RELOCS && TARGET_FIX
5334 && (register_operand (operands[0], DImode)
5335 || reg_or_0_operand (operands[1], DImode))"
5349 [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof")])
5351 (define_insn "*movdi_fix"
5352 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,Q,r,*f")
5353 (match_operand:DI 1 "input_operand" "rJ,K,L,s,m,rJ,*fJ,Q,*f,*f,r"))]
5354 "! TARGET_EXPLICIT_RELOCS && TARGET_FIX
5355 && (register_operand (operands[0], DImode)
5356 || reg_or_0_operand (operands[1], DImode))"
5369 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof")])
5371 ;; VMS needs to set up "vms_base_regno" for unwinding. This move
5372 ;; often appears dead to the life analysis code, at which point we
5373 ;; abort for emitting dead prologue instructions. Force this live.
5375 (define_insn "force_movdi"
5376 [(set (match_operand:DI 0 "register_operand" "=r")
5377 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")]
5378 UNSPECV_FORCE_MOV))]
5381 [(set_attr "type" "ilog")])
5383 ;; We do three major things here: handle mem->mem, put 64-bit constants in
5384 ;; memory, and construct long 32-bit constants.
5386 (define_expand "movdi"
5387 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5388 (match_operand:DI 1 "general_operand" ""))]
5391 if (alpha_expand_mov (DImode, operands))
5395 ;; Split a load of a large constant into the appropriate two-insn
5399 [(set (match_operand:DI 0 "register_operand" "")
5400 (match_operand:DI 1 "const_int_operand" ""))]
5401 "! add_operand (operands[1], DImode)"
5402 [(set (match_dup 0) (match_dup 2))
5403 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
5406 = alpha_emit_set_const (operands[0], DImode, INTVAL (operands[1]), 2);
5408 if (tem == operands[0])
5414 ;; These are the partial-word cases.
5416 ;; First we have the code to load an aligned word. Operand 0 is the register
5417 ;; in which to place the result. It's mode is QImode or HImode. Operand 1
5418 ;; is an SImode MEM at the low-order byte of the proper word. Operand 2 is the
5419 ;; number of bits within the word that the value is. Operand 3 is an SImode
5420 ;; scratch register. If operand 0 is a hard register, operand 3 may be the
5421 ;; same register. It is allowed to conflict with operand 1 as well.
5423 (define_expand "aligned_loadqi"
5424 [(set (match_operand:SI 3 "register_operand" "")
5425 (match_operand:SI 1 "memory_operand" ""))
5426 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5427 (zero_extract:DI (subreg:DI (match_dup 3) 0)
5429 (match_operand:DI 2 "const_int_operand" "")))]
5434 (define_expand "aligned_loadhi"
5435 [(set (match_operand:SI 3 "register_operand" "")
5436 (match_operand:SI 1 "memory_operand" ""))
5437 (set (subreg:DI (match_operand:HI 0 "register_operand" "") 0)
5438 (zero_extract:DI (subreg:DI (match_dup 3) 0)
5440 (match_operand:DI 2 "const_int_operand" "")))]
5445 ;; Similar for unaligned loads, where we use the sequence from the
5446 ;; Alpha Architecture manual. We have to distinguish between little-endian
5447 ;; and big-endian systems as the sequences are different.
5449 ;; Operand 1 is the address. Operands 2 and 3 are temporaries, where
5450 ;; operand 3 can overlap the input and output registers.
5452 (define_expand "unaligned_loadqi"
5453 [(use (match_operand:QI 0 "register_operand" ""))
5454 (use (match_operand:DI 1 "address_operand" ""))
5455 (use (match_operand:DI 2 "register_operand" ""))
5456 (use (match_operand:DI 3 "register_operand" ""))]
5459 if (WORDS_BIG_ENDIAN)
5460 emit_insn (gen_unaligned_loadqi_be (operands[0], operands[1],
5461 operands[2], operands[3]));
5463 emit_insn (gen_unaligned_loadqi_le (operands[0], operands[1],
5464 operands[2], operands[3]));
5468 (define_expand "unaligned_loadqi_le"
5469 [(set (match_operand:DI 2 "register_operand" "")
5470 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5472 (set (match_operand:DI 3 "register_operand" "")
5474 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5475 (zero_extract:DI (match_dup 2)
5477 (ashift:DI (match_dup 3) (const_int 3))))]
5478 "! WORDS_BIG_ENDIAN"
5481 (define_expand "unaligned_loadqi_be"
5482 [(set (match_operand:DI 2 "register_operand" "")
5483 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5485 (set (match_operand:DI 3 "register_operand" "")
5487 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5488 (zero_extract:DI (match_dup 2)
5492 (ashift:DI (match_dup 3) (const_int 3)))))]
5496 (define_expand "unaligned_loadhi"
5497 [(use (match_operand:QI 0 "register_operand" ""))
5498 (use (match_operand:DI 1 "address_operand" ""))
5499 (use (match_operand:DI 2 "register_operand" ""))
5500 (use (match_operand:DI 3 "register_operand" ""))]
5503 if (WORDS_BIG_ENDIAN)
5504 emit_insn (gen_unaligned_loadhi_be (operands[0], operands[1],
5505 operands[2], operands[3]));
5507 emit_insn (gen_unaligned_loadhi_le (operands[0], operands[1],
5508 operands[2], operands[3]));
5512 (define_expand "unaligned_loadhi_le"
5513 [(set (match_operand:DI 2 "register_operand" "")
5514 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5516 (set (match_operand:DI 3 "register_operand" "")
5518 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5519 (zero_extract:DI (match_dup 2)
5521 (ashift:DI (match_dup 3) (const_int 3))))]
5522 "! WORDS_BIG_ENDIAN"
5525 (define_expand "unaligned_loadhi_be"
5526 [(set (match_operand:DI 2 "register_operand" "")
5527 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5529 (set (match_operand:DI 3 "register_operand" "")
5530 (plus:DI (match_dup 1) (const_int 1)))
5531 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
5532 (zero_extract:DI (match_dup 2)
5536 (ashift:DI (match_dup 3) (const_int 3)))))]
5540 ;; Storing an aligned byte or word requires two temporaries. Operand 0 is the
5541 ;; aligned SImode MEM. Operand 1 is the register containing the
5542 ;; byte or word to store. Operand 2 is the number of bits within the word that
5543 ;; the value should be placed. Operands 3 and 4 are SImode temporaries.
5545 (define_expand "aligned_store"
5546 [(set (match_operand:SI 3 "register_operand" "")
5547 (match_operand:SI 0 "memory_operand" ""))
5548 (set (subreg:DI (match_dup 3) 0)
5549 (and:DI (subreg:DI (match_dup 3) 0) (match_dup 5)))
5550 (set (subreg:DI (match_operand:SI 4 "register_operand" "") 0)
5551 (ashift:DI (zero_extend:DI (match_operand 1 "register_operand" ""))
5552 (match_operand:DI 2 "const_int_operand" "")))
5553 (set (subreg:DI (match_dup 4) 0)
5554 (ior:DI (subreg:DI (match_dup 4) 0) (subreg:DI (match_dup 3) 0)))
5555 (set (match_dup 0) (match_dup 4))]
5558 operands[5] = GEN_INT (~ (GET_MODE_MASK (GET_MODE (operands[1]))
5559 << INTVAL (operands[2])));
5562 ;; For the unaligned byte and halfword cases, we use code similar to that
5563 ;; in the ;; Architecture book, but reordered to lower the number of registers
5564 ;; required. Operand 0 is the address. Operand 1 is the data to store.
5565 ;; Operands 2, 3, and 4 are DImode temporaries, where operands 2 and 4 may
5566 ;; be the same temporary, if desired. If the address is in a register,
5567 ;; operand 2 can be that register.
5569 (define_expand "unaligned_storeqi"
5570 [(use (match_operand:DI 0 "address_operand" ""))
5571 (use (match_operand:QI 1 "register_operand" ""))
5572 (use (match_operand:DI 2 "register_operand" ""))
5573 (use (match_operand:DI 3 "register_operand" ""))
5574 (use (match_operand:DI 4 "register_operand" ""))]
5577 if (WORDS_BIG_ENDIAN)
5578 emit_insn (gen_unaligned_storeqi_be (operands[0], operands[1],
5579 operands[2], operands[3],
5582 emit_insn (gen_unaligned_storeqi_le (operands[0], operands[1],
5583 operands[2], operands[3],
5588 (define_expand "unaligned_storeqi_le"
5589 [(set (match_operand:DI 3 "register_operand" "")
5590 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5592 (set (match_operand:DI 2 "register_operand" "")
5595 (and:DI (not:DI (ashift:DI (const_int 255)
5596 (ashift:DI (match_dup 2) (const_int 3))))
5598 (set (match_operand:DI 4 "register_operand" "")
5599 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
5600 (ashift:DI (match_dup 2) (const_int 3))))
5601 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5602 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5604 "! WORDS_BIG_ENDIAN"
5607 (define_expand "unaligned_storeqi_be"
5608 [(set (match_operand:DI 3 "register_operand" "")
5609 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5611 (set (match_operand:DI 2 "register_operand" "")
5614 (and:DI (not:DI (ashift:DI (const_int 255)
5615 (minus:DI (const_int 56)
5616 (ashift:DI (match_dup 2) (const_int 3)))))
5618 (set (match_operand:DI 4 "register_operand" "")
5619 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
5620 (minus:DI (const_int 56)
5621 (ashift:DI (match_dup 2) (const_int 3)))))
5622 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5623 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5628 (define_expand "unaligned_storehi"
5629 [(use (match_operand:DI 0 "address_operand" ""))
5630 (use (match_operand:HI 1 "register_operand" ""))
5631 (use (match_operand:DI 2 "register_operand" ""))
5632 (use (match_operand:DI 3 "register_operand" ""))
5633 (use (match_operand:DI 4 "register_operand" ""))]
5636 if (WORDS_BIG_ENDIAN)
5637 emit_insn (gen_unaligned_storehi_be (operands[0], operands[1],
5638 operands[2], operands[3],
5641 emit_insn (gen_unaligned_storehi_le (operands[0], operands[1],
5642 operands[2], operands[3],
5647 (define_expand "unaligned_storehi_le"
5648 [(set (match_operand:DI 3 "register_operand" "")
5649 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5651 (set (match_operand:DI 2 "register_operand" "")
5654 (and:DI (not:DI (ashift:DI (const_int 65535)
5655 (ashift:DI (match_dup 2) (const_int 3))))
5657 (set (match_operand:DI 4 "register_operand" "")
5658 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
5659 (ashift:DI (match_dup 2) (const_int 3))))
5660 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5661 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5663 "! WORDS_BIG_ENDIAN"
5666 (define_expand "unaligned_storehi_be"
5667 [(set (match_operand:DI 3 "register_operand" "")
5668 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5670 (set (match_operand:DI 2 "register_operand" "")
5671 (plus:DI (match_dup 0) (const_int 1)))
5673 (and:DI (not:DI (ashift:DI
5675 (minus:DI (const_int 56)
5676 (ashift:DI (match_dup 2) (const_int 3)))))
5678 (set (match_operand:DI 4 "register_operand" "")
5679 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
5680 (minus:DI (const_int 56)
5681 (ashift:DI (match_dup 2) (const_int 3)))))
5682 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5683 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5688 ;; Here are the define_expand's for QI and HI moves that use the above
5689 ;; patterns. We have the normal sets, plus the ones that need scratch
5690 ;; registers for reload.
5692 (define_expand "movqi"
5693 [(set (match_operand:QI 0 "nonimmediate_operand" "")
5694 (match_operand:QI 1 "general_operand" ""))]
5698 ? alpha_expand_mov (QImode, operands)
5699 : alpha_expand_mov_nobwx (QImode, operands))
5703 (define_expand "movhi"
5704 [(set (match_operand:HI 0 "nonimmediate_operand" "")
5705 (match_operand:HI 1 "general_operand" ""))]
5709 ? alpha_expand_mov (HImode, operands)
5710 : alpha_expand_mov_nobwx (HImode, operands))
5714 ;; Here are the versions for reload. Note that in the unaligned cases
5715 ;; we know that the operand must not be a pseudo-register because stack
5716 ;; slots are always aligned references.
5718 (define_expand "reload_inqi"
5719 [(parallel [(match_operand:QI 0 "register_operand" "=r")
5720 (match_operand:QI 1 "any_memory_operand" "m")
5721 (match_operand:TI 2 "register_operand" "=&r")])]
5726 if (GET_CODE (operands[1]) != MEM)
5729 if (aligned_memory_operand (operands[1], QImode))
5731 seq = gen_reload_inqi_help (operands[0], operands[1],
5732 gen_rtx_REG (SImode, REGNO (operands[2])));
5738 /* It is possible that one of the registers we got for operands[2]
5739 might coincide with that of operands[0] (which is why we made
5740 it TImode). Pick the other one to use as our scratch. */
5741 if (REGNO (operands[0]) == REGNO (operands[2]))
5742 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5744 scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
5746 addr = get_unaligned_address (operands[1], 0);
5747 seq = gen_unaligned_loadqi (operands[0], addr, scratch,
5748 gen_rtx_REG (DImode, REGNO (operands[0])));
5749 alpha_set_memflags (seq, operands[1]);
5755 (define_expand "reload_inhi"
5756 [(parallel [(match_operand:HI 0 "register_operand" "=r")
5757 (match_operand:HI 1 "any_memory_operand" "m")
5758 (match_operand:TI 2 "register_operand" "=&r")])]
5763 if (GET_CODE (operands[1]) != MEM)
5766 if (aligned_memory_operand (operands[1], HImode))
5768 seq = gen_reload_inhi_help (operands[0], operands[1],
5769 gen_rtx_REG (SImode, REGNO (operands[2])));
5775 /* It is possible that one of the registers we got for operands[2]
5776 might coincide with that of operands[0] (which is why we made
5777 it TImode). Pick the other one to use as our scratch. */
5778 if (REGNO (operands[0]) == REGNO (operands[2]))
5779 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5781 scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
5783 addr = get_unaligned_address (operands[1], 0);
5784 seq = gen_unaligned_loadhi (operands[0], addr, scratch,
5785 gen_rtx_REG (DImode, REGNO (operands[0])));
5786 alpha_set_memflags (seq, operands[1]);
5792 (define_expand "reload_outqi"
5793 [(parallel [(match_operand:QI 0 "any_memory_operand" "=m")
5794 (match_operand:QI 1 "register_operand" "r")
5795 (match_operand:TI 2 "register_operand" "=&r")])]
5798 if (GET_CODE (operands[0]) != MEM)
5801 if (aligned_memory_operand (operands[0], QImode))
5803 emit_insn (gen_reload_outqi_help
5804 (operands[0], operands[1],
5805 gen_rtx_REG (SImode, REGNO (operands[2])),
5806 gen_rtx_REG (SImode, REGNO (operands[2]) + 1)));
5810 rtx addr = get_unaligned_address (operands[0], 0);
5811 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
5812 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5813 rtx scratch3 = scratch1;
5816 if (GET_CODE (addr) == REG)
5819 seq = gen_unaligned_storeqi (addr, operands[1], scratch1,
5820 scratch2, scratch3);
5821 alpha_set_memflags (seq, operands[0]);
5827 (define_expand "reload_outhi"
5828 [(parallel [(match_operand:HI 0 "any_memory_operand" "=m")
5829 (match_operand:HI 1 "register_operand" "r")
5830 (match_operand:TI 2 "register_operand" "=&r")])]
5833 if (GET_CODE (operands[0]) != MEM)
5836 if (aligned_memory_operand (operands[0], HImode))
5838 emit_insn (gen_reload_outhi_help
5839 (operands[0], operands[1],
5840 gen_rtx_REG (SImode, REGNO (operands[2])),
5841 gen_rtx_REG (SImode, REGNO (operands[2]) + 1)));
5845 rtx addr = get_unaligned_address (operands[0], 0);
5846 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
5847 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5848 rtx scratch3 = scratch1;
5851 if (GET_CODE (addr) == REG)
5854 seq = gen_unaligned_storehi (addr, operands[1], scratch1,
5855 scratch2, scratch3);
5856 alpha_set_memflags (seq, operands[0]);
5862 ;; Helpers for the above. The way reload is structured, we can't
5863 ;; always get a proper address for a stack slot during reload_foo
5864 ;; expansion, so we must delay our address manipulations until after.
5866 (define_insn "reload_inqi_help"
5867 [(set (match_operand:QI 0 "register_operand" "=r")
5868 (match_operand:QI 1 "memory_operand" "m"))
5869 (clobber (match_operand:SI 2 "register_operand" "=r"))]
5870 "! TARGET_BWX && (reload_in_progress || reload_completed)"
5873 (define_insn "reload_inhi_help"
5874 [(set (match_operand:HI 0 "register_operand" "=r")
5875 (match_operand:HI 1 "memory_operand" "m"))
5876 (clobber (match_operand:SI 2 "register_operand" "=r"))]
5877 "! TARGET_BWX && (reload_in_progress || reload_completed)"
5880 (define_insn "reload_outqi_help"
5881 [(set (match_operand:QI 0 "memory_operand" "=m")
5882 (match_operand:QI 1 "register_operand" "r"))
5883 (clobber (match_operand:SI 2 "register_operand" "=r"))
5884 (clobber (match_operand:SI 3 "register_operand" "=r"))]
5885 "! TARGET_BWX && (reload_in_progress || reload_completed)"
5888 (define_insn "reload_outhi_help"
5889 [(set (match_operand:HI 0 "memory_operand" "=m")
5890 (match_operand:HI 1 "register_operand" "r"))
5891 (clobber (match_operand:SI 2 "register_operand" "=r"))
5892 (clobber (match_operand:SI 3 "register_operand" "=r"))]
5893 "! TARGET_BWX && (reload_in_progress || reload_completed)"
5897 [(set (match_operand:QI 0 "register_operand" "")
5898 (match_operand:QI 1 "memory_operand" ""))
5899 (clobber (match_operand:SI 2 "register_operand" ""))]
5900 "! TARGET_BWX && reload_completed"
5903 rtx aligned_mem, bitnum;
5904 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
5906 emit_insn (gen_aligned_loadqi (operands[0], aligned_mem, bitnum,
5912 [(set (match_operand:HI 0 "register_operand" "")
5913 (match_operand:HI 1 "memory_operand" ""))
5914 (clobber (match_operand:SI 2 "register_operand" ""))]
5915 "! TARGET_BWX && reload_completed"
5918 rtx aligned_mem, bitnum;
5919 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
5921 emit_insn (gen_aligned_loadhi (operands[0], aligned_mem, bitnum,
5927 [(set (match_operand:QI 0 "memory_operand" "")
5928 (match_operand:QI 1 "register_operand" ""))
5929 (clobber (match_operand:SI 2 "register_operand" ""))
5930 (clobber (match_operand:SI 3 "register_operand" ""))]
5931 "! TARGET_BWX && reload_completed"
5934 rtx aligned_mem, bitnum;
5935 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
5936 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
5937 operands[2], operands[3]));
5942 [(set (match_operand:HI 0 "memory_operand" "")
5943 (match_operand:HI 1 "register_operand" ""))
5944 (clobber (match_operand:SI 2 "register_operand" ""))
5945 (clobber (match_operand:SI 3 "register_operand" ""))]
5946 "! TARGET_BWX && reload_completed"
5949 rtx aligned_mem, bitnum;
5950 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
5951 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
5952 operands[2], operands[3]));
5956 ;; Bit field extract patterns which use ext[wlq][lh]
5958 (define_expand "extv"
5959 [(set (match_operand:DI 0 "register_operand" "")
5960 (sign_extract:DI (match_operand:QI 1 "memory_operand" "")
5961 (match_operand:DI 2 "immediate_operand" "")
5962 (match_operand:DI 3 "immediate_operand" "")))]
5967 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
5968 if (INTVAL (operands[3]) % 8 != 0
5969 || (INTVAL (operands[2]) != 16
5970 && INTVAL (operands[2]) != 32
5971 && INTVAL (operands[2]) != 64))
5974 /* From mips.md: extract_bit_field doesn't verify that our source
5975 matches the predicate, so we force it to be a MEM here. */
5976 if (GET_CODE (operands[1]) != MEM)
5979 /* The bit number is relative to the mode of operand 1 which is
5980 usually QImode (this might actually be a bug in expmed.c). Note
5981 that the bit number is negative in big-endian mode in this case.
5982 We have to convert that to the offset. */
5983 if (WORDS_BIG_ENDIAN)
5984 ofs = GET_MODE_BITSIZE (GET_MODE (operands[1]))
5985 - INTVAL (operands[2]) - INTVAL (operands[3]);
5987 ofs = INTVAL (operands[3]);
5991 alpha_expand_unaligned_load (operands[0], operands[1],
5992 INTVAL (operands[2]) / 8,
5997 (define_expand "extzv"
5998 [(set (match_operand:DI 0 "register_operand" "")
5999 (zero_extract:DI (match_operand:DI 1 "nonimmediate_operand" "")
6000 (match_operand:DI 2 "immediate_operand" "")
6001 (match_operand:DI 3 "immediate_operand" "")))]
6004 /* We can do 8, 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6005 if (INTVAL (operands[3]) % 8 != 0
6006 || (INTVAL (operands[2]) != 8
6007 && INTVAL (operands[2]) != 16
6008 && INTVAL (operands[2]) != 32
6009 && INTVAL (operands[2]) != 64))
6012 if (GET_CODE (operands[1]) == MEM)
6016 /* Fail 8 bit fields, falling back on a simple byte load. */
6017 if (INTVAL (operands[2]) == 8)
6020 /* The bit number is relative to the mode of operand 1 which is
6021 usually QImode (this might actually be a bug in expmed.c). Note
6022 that the bit number is negative in big-endian mode in this case.
6023 We have to convert that to the offset. */
6024 if (WORDS_BIG_ENDIAN)
6025 ofs = GET_MODE_BITSIZE (GET_MODE (operands[1]))
6026 - INTVAL (operands[2]) - INTVAL (operands[3]);
6028 ofs = INTVAL (operands[3]);
6032 alpha_expand_unaligned_load (operands[0], operands[1],
6033 INTVAL (operands[2]) / 8,
6039 (define_expand "insv"
6040 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "")
6041 (match_operand:DI 1 "immediate_operand" "")
6042 (match_operand:DI 2 "immediate_operand" ""))
6043 (match_operand:DI 3 "register_operand" ""))]
6048 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6049 if (INTVAL (operands[2]) % 8 != 0
6050 || (INTVAL (operands[1]) != 16
6051 && INTVAL (operands[1]) != 32
6052 && INTVAL (operands[1]) != 64))
6055 /* From mips.md: store_bit_field doesn't verify that our source
6056 matches the predicate, so we force it to be a MEM here. */
6057 if (GET_CODE (operands[0]) != MEM)
6060 /* The bit number is relative to the mode of operand 1 which is
6061 usually QImode (this might actually be a bug in expmed.c). Note
6062 that the bit number is negative in big-endian mode in this case.
6063 We have to convert that to the offset. */
6064 if (WORDS_BIG_ENDIAN)
6065 ofs = GET_MODE_BITSIZE (GET_MODE (operands[0]))
6066 - INTVAL (operands[1]) - INTVAL (operands[2]);
6068 ofs = INTVAL (operands[2]);
6072 alpha_expand_unaligned_store (operands[0], operands[3],
6073 INTVAL (operands[1]) / 8, ofs);
6077 ;; Block move/clear, see alpha.c for more details.
6078 ;; Argument 0 is the destination
6079 ;; Argument 1 is the source
6080 ;; Argument 2 is the length
6081 ;; Argument 3 is the alignment
6083 (define_expand "movstrqi"
6084 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6085 (match_operand:BLK 1 "memory_operand" ""))
6086 (use (match_operand:DI 2 "immediate_operand" ""))
6087 (use (match_operand:DI 3 "immediate_operand" ""))])]
6090 if (alpha_expand_block_move (operands))
6096 (define_expand "clrstrqi"
6097 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6099 (use (match_operand:DI 1 "immediate_operand" ""))
6100 (use (match_operand:DI 2 "immediate_operand" ""))])]
6103 if (alpha_expand_block_clear (operands))
6109 ;; Subroutine of stack space allocation. Perform a stack probe.
6110 (define_expand "probe_stack"
6111 [(set (match_dup 1) (match_operand:DI 0 "const_int_operand" ""))]
6114 operands[1] = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx,
6115 INTVAL (operands[0])));
6116 MEM_VOLATILE_P (operands[1]) = 1;
6118 operands[0] = const0_rtx;
6121 ;; This is how we allocate stack space. If we are allocating a
6122 ;; constant amount of space and we know it is less than 4096
6123 ;; bytes, we need do nothing.
6125 ;; If it is more than 4096 bytes, we need to probe the stack
6127 (define_expand "allocate_stack"
6129 (plus:DI (reg:DI 30)
6130 (match_operand:DI 1 "reg_or_cint_operand" "")))
6131 (set (match_operand:DI 0 "register_operand" "=r")
6135 if (GET_CODE (operands[1]) == CONST_INT
6136 && INTVAL (operands[1]) < 32768)
6138 if (INTVAL (operands[1]) >= 4096)
6140 /* We do this the same way as in the prologue and generate explicit
6141 probes. Then we update the stack by the constant. */
6145 emit_insn (gen_probe_stack (GEN_INT (- probed)));
6146 while (probed + 8192 < INTVAL (operands[1]))
6147 emit_insn (gen_probe_stack (GEN_INT (- (probed += 8192))));
6149 if (probed + 4096 < INTVAL (operands[1]))
6150 emit_insn (gen_probe_stack (GEN_INT (- INTVAL(operands[1]))));
6153 operands[1] = GEN_INT (- INTVAL (operands[1]));
6154 operands[2] = virtual_stack_dynamic_rtx;
6159 rtx loop_label = gen_label_rtx ();
6160 rtx want = gen_reg_rtx (Pmode);
6161 rtx tmp = gen_reg_rtx (Pmode);
6164 emit_insn (gen_subdi3 (want, stack_pointer_rtx,
6165 force_reg (Pmode, operands[1])));
6166 emit_insn (gen_adddi3 (tmp, stack_pointer_rtx, GEN_INT (-4096)));
6168 if (GET_CODE (operands[1]) != CONST_INT)
6170 out_label = gen_label_rtx ();
6171 emit_insn (gen_cmpdi (want, tmp));
6172 emit_jump_insn (gen_bgeu (out_label));
6175 emit_label (loop_label);
6176 memref = gen_rtx_MEM (DImode, tmp);
6177 MEM_VOLATILE_P (memref) = 1;
6178 emit_move_insn (memref, const0_rtx);
6179 emit_insn (gen_adddi3 (tmp, tmp, GEN_INT(-8192)));
6180 emit_insn (gen_cmpdi (tmp, want));
6181 emit_jump_insn (gen_bgtu (loop_label));
6183 memref = gen_rtx_MEM (DImode, want);
6184 MEM_VOLATILE_P (memref) = 1;
6185 emit_move_insn (memref, const0_rtx);
6188 emit_label (out_label);
6190 emit_move_insn (stack_pointer_rtx, want);
6191 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
6196 ;; This is used by alpha_expand_prolog to do the same thing as above,
6197 ;; except we cannot at that time generate new basic blocks, so we hide
6198 ;; the loop in this one insn.
6200 (define_insn "prologue_stack_probe_loop"
6201 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")
6202 (match_operand:DI 1 "register_operand" "r")]
6206 operands[2] = gen_label_rtx ();
6207 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
6208 CODE_LABEL_NUMBER (operands[2]));
6210 return "stq $31,-8192(%1)\;subq %0,1,%0\;lda %1,-8192(%1)\;bne %0,%l2";
6212 [(set_attr "length" "16")
6213 (set_attr "type" "multi")])
6215 (define_expand "prologue"
6216 [(clobber (const_int 0))]
6219 alpha_expand_prologue ();
6223 ;; These take care of emitting the ldgp insn in the prologue. This will be
6224 ;; an lda/ldah pair and we want to align them properly. So we have two
6225 ;; unspec_volatile insns, the first of which emits the ldgp assembler macro
6226 ;; and the second of which emits nothing. However, both are marked as type
6227 ;; IADD (the default) so the alignment code in alpha.c does the right thing
6230 (define_expand "prologue_ldgp"
6232 (unspec_volatile:DI [(match_dup 1) (match_dup 2)] UNSPECV_LDGP1))
6234 (unspec_volatile:DI [(match_dup 0) (match_dup 2)] UNSPECV_PLDGP2))]
6237 operands[0] = pic_offset_table_rtx;
6238 operands[1] = gen_rtx_REG (Pmode, 27);
6239 operands[2] = (TARGET_EXPLICIT_RELOCS
6240 ? GEN_INT (alpha_next_sequence_number++)
6244 (define_insn "*ldgp_er_1"
6245 [(set (match_operand:DI 0 "register_operand" "=r")
6246 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6247 (match_operand 2 "const_int_operand" "")]
6249 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6250 "ldah %0,0(%1)\t\t!gpdisp!%2")
6252 (define_insn "*ldgp_er_2"
6253 [(set (match_operand:DI 0 "register_operand" "=r")
6254 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
6255 (match_operand 2 "const_int_operand" "")]
6257 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6258 "lda %0,0(%1)\t\t!gpdisp!%2")
6260 (define_insn "*prologue_ldgp_er_2"
6261 [(set (match_operand:DI 0 "register_operand" "=r")
6262 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6263 (match_operand 2 "const_int_operand" "")]
6265 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6266 "lda %0,0(%1)\t\t!gpdisp!%2\n$%~..ng:")
6268 (define_insn "*prologue_ldgp_1"
6269 [(set (match_operand:DI 0 "register_operand" "=r")
6270 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6271 (match_operand 2 "const_int_operand" "")]
6274 "ldgp %0,0(%1)\n$%~..ng:")
6276 (define_insn "*prologue_ldgp_2"
6277 [(set (match_operand:DI 0 "register_operand" "=r")
6278 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6279 (match_operand 2 "const_int_operand" "")]
6284 ;; The _mcount profiling hook has special calling conventions, and
6285 ;; does not clobber all the registers that a normal call would. So
6286 ;; hide the fact this is a call at all.
6288 (define_insn "prologue_mcount"
6289 [(unspec_volatile [(const_int 0)] UNSPECV_MCOUNT)]
6292 if (TARGET_EXPLICIT_RELOCS)
6293 /* Note that we cannot use a lituse_jsr reloc, since _mcount
6294 cannot be called via the PLT. */
6295 return "ldq $28,_mcount($29)\t\t!literal\;jsr $28,($28),_mcount";
6297 return "lda $28,_mcount\;jsr $28,($28),_mcount";
6299 [(set_attr "type" "multi")
6300 (set_attr "length" "8")])
6302 (define_insn "init_fp"
6303 [(set (match_operand:DI 0 "register_operand" "=r")
6304 (match_operand:DI 1 "register_operand" "r"))
6305 (clobber (mem:BLK (match_operand:DI 2 "register_operand" "=r")))]
6309 (define_expand "epilogue"
6313 alpha_expand_epilogue ();
6316 (define_expand "sibcall_epilogue"
6320 alpha_expand_epilogue ();
6324 ;; In creating a large stack frame, NT _must_ use ldah+lda to load
6325 ;; the frame size into a register. We use this pattern to ensure
6326 ;; we get lda instead of addq.
6327 (define_insn "nt_lda"
6328 [(set (match_operand:DI 0 "register_operand" "=r")
6329 (unspec:DI [(match_dup 0)
6330 (match_operand:DI 1 "const_int_operand" "n")]
6335 (define_expand "builtin_longjmp"
6336 [(use (match_operand:DI 0 "register_operand" "r"))]
6339 /* The elements of the buffer are, in order: */
6340 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
6341 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 8));
6342 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 16));
6343 rtx pv = gen_rtx_REG (Pmode, 27);
6345 /* This bit is the same as expand_builtin_longjmp. */
6346 emit_move_insn (hard_frame_pointer_rtx, fp);
6347 emit_move_insn (pv, lab);
6348 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
6349 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
6350 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
6352 /* Load the label we are jumping through into $27 so that we know
6353 where to look for it when we get back to setjmp's function for
6354 restoring the gp. */
6355 emit_jump_insn (gen_builtin_longjmp_internal (pv));
6360 ;; This is effectively a copy of indirect_jump, but constrained such
6361 ;; that register renaming cannot foil our cunning plan with $27.
6362 (define_insn "builtin_longjmp_internal"
6364 (unspec_volatile [(match_operand:DI 0 "register_operand" "c")]
6368 [(set_attr "type" "ibr")])
6370 (define_insn "*builtin_setjmp_receiver_er_sl_1"
6371 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6372 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && TARGET_AS_CAN_SUBTRACT_LABELS"
6373 "lda $27,$LSJ%=-%l0($27)\n$LSJ%=:")
6375 (define_insn "*builtin_setjmp_receiver_er_1"
6376 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6377 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6378 "br $27,$LSJ%=\n$LSJ%=:"
6379 [(set_attr "type" "ibr")])
6382 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6383 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
6384 && prev_nonnote_insn (insn) == operands[0]"
6388 (define_insn "*builtin_setjmp_receiver_1"
6389 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6391 "br $27,$LSJ%=\n$LSJ%=:\;ldgp $29,0($27)"
6392 [(set_attr "length" "12")
6393 (set_attr "type" "multi")])
6395 (define_expand "builtin_setjmp_receiver_er"
6396 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)
6398 (unspec_volatile:DI [(match_dup 2) (match_dup 3)] UNSPECV_LDGP1))
6400 (unspec:DI [(match_dup 1) (match_dup 3)] UNSPEC_LDGP2))]
6403 operands[1] = pic_offset_table_rtx;
6404 operands[2] = gen_rtx_REG (Pmode, 27);
6405 operands[3] = GEN_INT (alpha_next_sequence_number++);
6408 (define_expand "builtin_setjmp_receiver"
6409 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6412 if (TARGET_EXPLICIT_RELOCS)
6414 emit_insn (gen_builtin_setjmp_receiver_er (operands[0]));
6419 (define_expand "exception_receiver_er"
6421 (unspec_volatile:DI [(match_dup 1) (match_dup 2)] UNSPECV_LDGP1))
6423 (unspec:DI [(match_dup 0) (match_dup 2)] UNSPEC_LDGP2))]
6426 operands[0] = pic_offset_table_rtx;
6427 operands[1] = gen_rtx_REG (Pmode, 26);
6428 operands[2] = GEN_INT (alpha_next_sequence_number++);
6431 (define_expand "exception_receiver"
6432 [(unspec_volatile [(match_dup 0)] UNSPECV_EHR)]
6435 if (TARGET_LD_BUGGY_LDGP)
6436 operands[0] = alpha_gp_save_rtx ();
6437 else if (TARGET_EXPLICIT_RELOCS)
6439 emit_insn (gen_exception_receiver_er ());
6443 operands[0] = const0_rtx;
6446 (define_insn "*exception_receiver_1"
6447 [(unspec_volatile [(const_int 0)] UNSPECV_EHR)]
6448 "! TARGET_LD_BUGGY_LDGP"
6450 [(set_attr "length" "8")
6451 (set_attr "type" "multi")])
6453 (define_insn "*exception_receiver_2"
6454 [(unspec_volatile [(match_operand:DI 0 "memory_operand" "m")] UNSPECV_EHR)]
6455 "TARGET_LD_BUGGY_LDGP"
6457 [(set_attr "type" "ild")])
6459 (define_expand "nonlocal_goto_receiver"
6460 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
6461 (set (reg:DI 27) (mem:DI (reg:DI 29)))
6462 (unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
6464 "TARGET_ABI_OPEN_VMS"
6467 (define_insn "arg_home"
6468 [(unspec [(const_int 0)] UNSPEC_ARG_HOME)
6483 (clobber (mem:BLK (const_int 0)))
6484 (clobber (reg:DI 24))
6485 (clobber (reg:DI 25))
6486 (clobber (reg:DI 0))]
6487 "TARGET_ABI_OPEN_VMS"
6488 "lda $0,OTS$HOME_ARGS\;ldq $0,8($0)\;jsr $0,OTS$HOME_ARGS"
6489 [(set_attr "length" "16")
6490 (set_attr "type" "multi")])
6492 ;; Load the CIW into r2 for calling __T3E_MISMATCH
6494 (define_expand "umk_mismatch_args"
6495 [(set:DI (match_dup 1) (mem:DI (plus:DI (reg:DI 15) (const_int -16))))
6496 (set:DI (match_dup 2) (mem:DI (plus:DI (match_dup 1) (const_int -32))))
6497 (set:DI (reg:DI 1) (match_operand:DI 0 "const_int_operand" ""))
6498 (set:DI (match_dup 3) (plus:DI (mult:DI (reg:DI 25)
6501 (set:DI (reg:DI 2) (mem:DI (match_dup 3)))]
6502 "TARGET_ABI_UNICOSMK"
6504 operands[1] = gen_reg_rtx (DImode);
6505 operands[2] = gen_reg_rtx (DImode);
6506 operands[3] = gen_reg_rtx (DImode);
6509 (define_insn "arg_home_umk"
6510 [(unspec [(const_int 0)] UNSPEC_ARG_HOME)
6525 (clobber (mem:BLK (const_int 0)))
6527 (clobber (reg:DI 22))
6528 (clobber (reg:DI 23))
6529 (clobber (reg:DI 24))
6530 (clobber (reg:DI 0))
6531 (clobber (reg:DI 1))
6532 (clobber (reg:DI 2))
6533 (clobber (reg:DI 3))
6534 (clobber (reg:DI 4))
6535 (clobber (reg:DI 5))
6536 (clobber (reg:DI 6))
6537 (clobber (reg:DI 7))
6538 (clobber (reg:DI 8))])]
6539 "TARGET_ABI_UNICOSMK"
6540 "laum $4,__T3E_MISMATCH($31)\;sll $4,32,$4\;lalm $4,__T3E_MISMATCH($4)\;lal $4,__T3E_MISMATCH($4)\;jsr $3,($4)"
6541 [(set_attr "length" "16")
6542 (set_attr "type" "multi")])
6546 ;; On EV4, these instructions are nops -- no load occurs.
6548 ;; On EV5, these instructions act as a normal load, and thus can trap
6549 ;; if the address is invalid. The OS may (or may not) handle this in
6550 ;; the entMM fault handler and suppress the fault. If so, then this
6551 ;; has the effect of a read prefetch instruction.
6553 ;; On EV6, these become official prefetch instructions.
6555 (define_insn "prefetch"
6556 [(prefetch (match_operand:DI 0 "address_operand" "p")
6557 (match_operand:DI 1 "const_int_operand" "n")
6558 (match_operand:DI 2 "const_int_operand" "n"))]
6559 "TARGET_FIXUP_EV5_PREFETCH || TARGET_CPU_EV6"
6561 /* Interpret "no temporal locality" as this data should be evicted once
6562 it is used. The "evict next" alternatives load the data into the cache
6563 and leave the LRU eviction counter pointing to that block. */
6564 static const char * const alt[2][2] = {
6566 "lds $f31,%a0", /* read, evict next */
6567 "ldl $31,%a0", /* read, evict last */
6570 "ldt $f31,%a0", /* write, evict next */
6571 "ldq $31,%a0", /* write, evict last */
6575 bool write = INTVAL (operands[1]) != 0;
6576 bool lru = INTVAL (operands[2]) != 0;
6578 return alt[write][lru];
6580 [(set_attr "type" "ild")])
6582 ;; Close the trap shadow of preceding instructions. This is generated
6585 (define_insn "trapb"
6586 [(unspec_volatile [(const_int 0)] UNSPECV_TRAPB)]
6589 [(set_attr "type" "misc")])
6591 ;; No-op instructions used by machine-dependent reorg to preserve
6592 ;; alignment for instruction issue.
6593 ;; The Unicos/Mk assembler does not support these opcodes.
6599 [(set_attr "type" "ilog")])
6604 "cpys $f31,$f31,$f31"
6605 [(set_attr "type" "fcpys")])
6612 ;; On Unicos/Mk we use a macro for aligning code.
6614 (define_insn "realign"
6615 [(unspec_volatile [(match_operand 0 "immediate_operand" "i")]
6619 if (TARGET_ABI_UNICOSMK)
6620 return "gcc@code@align %0";
6622 return ".align %0 #realign";
6625 ;; The call patterns are at the end of the file because their
6626 ;; wildcard operand0 interferes with nice recognition.
6628 (define_insn "*call_value_osf_1_er"
6629 [(set (match_operand 0 "" "")
6630 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
6631 (match_operand 2 "" "")))
6633 (clobber (reg:DI 26))]
6634 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6636 jsr $26,(%1),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*
6638 ldq $27,%1($29)\t\t!literal!%#\;jsr $26,($27),0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*"
6639 [(set_attr "type" "jsr")
6640 (set_attr "length" "12,*,16")])
6642 ;; We must use peep2 instead of a split because we need accurate life
6643 ;; information for $gp. Consider the case of { bar(); while (1); }.
6645 [(parallel [(set (match_operand 0 "" "")
6646 (call (mem:DI (match_operand:DI 1 "call_operand" ""))
6647 (match_operand 2 "" "")))
6649 (clobber (reg:DI 26))])]
6650 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
6651 && ! current_file_function_operand (operands[1], Pmode)
6652 && peep2_regno_dead_p (1, 29)"
6653 [(parallel [(set (match_dup 0)
6654 (call (mem:DI (match_dup 3))
6656 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
6657 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
6659 (use (match_dup 4))])]
6661 if (CONSTANT_P (operands[1]))
6663 operands[3] = gen_rtx_REG (Pmode, 27);
6664 operands[4] = GEN_INT (alpha_next_sequence_number++);
6665 emit_insn (gen_movdi_er_high_g (operands[3], pic_offset_table_rtx,
6666 operands[1], operands[4]));
6670 operands[3] = operands[1];
6671 operands[1] = const0_rtx;
6672 operands[4] = const0_rtx;
6677 [(parallel [(set (match_operand 0 "" "")
6678 (call (mem:DI (match_operand:DI 1 "call_operand" ""))
6679 (match_operand 2 "" "")))
6681 (clobber (reg:DI 26))])]
6682 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
6683 && ! current_file_function_operand (operands[1], Pmode)
6684 && ! peep2_regno_dead_p (1, 29)"
6685 [(parallel [(set (match_dup 0)
6686 (call (mem:DI (match_dup 3))
6688 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
6689 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
6691 (use (match_dup 5))])
6693 (unspec_volatile:DI [(reg:DI 26) (match_dup 4)] UNSPECV_LDGP1))
6695 (unspec:DI [(reg:DI 29) (match_dup 4)] UNSPEC_LDGP2))]
6697 if (CONSTANT_P (operands[1]))
6699 operands[3] = gen_rtx_REG (Pmode, 27);
6700 operands[5] = GEN_INT (alpha_next_sequence_number++);
6701 emit_insn (gen_movdi_er_high_g (operands[3], pic_offset_table_rtx,
6702 operands[1], operands[5]));
6706 operands[3] = operands[1];
6707 operands[1] = const0_rtx;
6708 operands[5] = const0_rtx;
6710 operands[4] = GEN_INT (alpha_next_sequence_number++);
6713 ;; We add a blockage unspec_volatile to prevent insns from moving down
6714 ;; from above the call to in between the call and the ldah gpdisp.
6715 (define_insn "*call_value_osf_2_er"
6716 [(set (match_operand 0 "" "")
6717 (call (mem:DI (match_operand:DI 1 "register_operand" "c"))
6718 (match_operand 2 "" "")))
6720 (plus:DI (pc) (const_int 4)))
6721 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
6722 (use (match_operand 3 "" ""))
6723 (use (match_operand 4 "const_int_operand" ""))]
6724 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6725 "jsr $26,(%1),%3%J4"
6726 [(set_attr "type" "jsr")])
6728 (define_insn "*call_value_osf_1_noreturn"
6729 [(set (match_operand 0 "" "")
6730 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
6731 (match_operand 2 "" "")))
6733 (clobber (reg:DI 26))]
6734 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
6735 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
6740 [(set_attr "type" "jsr")
6741 (set_attr "length" "*,*,8")])
6743 (define_insn "*call_value_osf_1"
6744 [(set (match_operand 0 "" "")
6745 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
6746 (match_operand 2 "" "")))
6748 (clobber (reg:DI 26))]
6749 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6751 jsr $26,($27),0\;ldgp $29,0($26)
6753 jsr $26,%1\;ldgp $29,0($26)"
6754 [(set_attr "type" "jsr")
6755 (set_attr "length" "12,*,16")])
6757 (define_insn "*sibcall_value_osf_1_er"
6758 [(set (match_operand 0 "" "")
6759 (call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s"))
6760 (match_operand 2 "" "")))
6761 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
6762 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6765 ldq $27,%1($29)\t\t!literal!%#\;jmp $31,($27),%1\t\t!lituse_jsr!%#"
6766 [(set_attr "type" "jsr")
6767 (set_attr "length" "*,8")])
6769 (define_insn "*sibcall_value_osf_1"
6770 [(set (match_operand 0 "" "")
6771 (call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s"))
6772 (match_operand 2 "" "")))
6773 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
6774 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6777 lda $27,%1\;jmp $31,($27),%1"
6778 [(set_attr "type" "jsr")
6779 (set_attr "length" "*,8")])
6781 (define_insn "*call_value_nt_1"
6782 [(set (match_operand 0 "" "")
6783 (call (mem:DI (match_operand:DI 1 "call_operand" "r,R,s"))
6784 (match_operand 2 "" "")))
6785 (clobber (reg:DI 26))]
6786 "TARGET_ABI_WINDOWS_NT"
6791 [(set_attr "type" "jsr")
6792 (set_attr "length" "*,*,12")])
6794 (define_insn "*call_value_vms_1"
6795 [(set (match_operand 0 "" "")
6796 (call (mem:DI (match_operand:DI 1 "call_operand" "r,s"))
6797 (match_operand 2 "" "")))
6798 (use (match_operand:DI 3 "nonimmediate_operand" "r,m"))
6801 (clobber (reg:DI 27))]
6802 "TARGET_ABI_OPEN_VMS"
6804 mov %3,$27\;jsr $26,0\;ldq $27,0($29)
6805 ldq $27,%3\;jsr $26,%1\;ldq $27,0($29)"
6806 [(set_attr "type" "jsr")
6807 (set_attr "length" "12,16")])
6809 (define_insn "*call_value_umk"
6810 [(set (match_operand 0 "" "")
6811 (call (mem:DI (match_operand:DI 1 "call_operand" "r"))
6812 (match_operand 2 "" "")))
6814 (clobber (reg:DI 26))]
6815 "TARGET_ABI_UNICOSMK"
6817 [(set_attr "type" "jsr")])