1 ;; Machine description for DEC Alpha for GNU C compiler
2 ;; Copyright (C) 1992, 93-98, 1999 Free Software Foundation, Inc.
3 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 ;; This file is part of GNU CC.
7 ;; GNU CC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 2, or (at your option)
12 ;; GNU CC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GNU CC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
20 ;; Boston, MA 02111-1307, USA.
22 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
24 ;; Uses of UNSPEC in this file:
37 ;; 2 builtin_setjmp_receiver
40 ;; 5 prologue_stack_probe_loop
42 ;; 7 exception_receiver
44 ;; Processor type -- this attribute must exactly match the processor_type
45 ;; enumeration in alpha.h.
47 (define_attr "cpu" "ev4,ev5,ev6"
48 (const (symbol_ref "alpha_cpu")))
50 ;; Define an insn type attribute. This is used in function unit delay
51 ;; computations, among other purposes. For the most part, we use the names
52 ;; defined in the EV4 documentation, but add a few that we have to know about
56 "ild,fld,ldsym,ist,fst,ibr,fbr,jsr,iadd,ilog,shift,icmov,fcmov,icmp,imul,fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi"
57 (const_string "iadd"))
59 ;; Describe a user's asm statement.
60 (define_asm_attributes
61 [(set_attr "type" "multi")])
63 ;; Define the operand size an insn operates on. Used primarily by mul
64 ;; and div operations that have size dependant timings.
66 (define_attr "opsize" "si,di,udi" (const_string "di"))
68 ;; The TRAP_TYPE attribute marks instructions that may generate traps
69 ;; (which are imprecise and may need a trapb if software completion
72 (define_attr "trap" "no,yes" (const_string "no"))
74 ;; The length of an instruction sequence in bytes.
76 (define_attr "length" "" (const_int 4))
78 ;; On EV4 there are two classes of resources to consider: resources needed
79 ;; to issue, and resources needed to execute. IBUS[01] are in the first
80 ;; category. ABOX, BBOX, EBOX, FBOX, IMUL & FDIV make up the second.
81 ;; (There are a few other register-like resources, but ...)
83 ; First, describe all of the issue constraints with single cycle delays.
84 ; All insns need a bus, but all except loads require one or the other.
85 (define_function_unit "ev4_ibus0" 1 0
86 (and (eq_attr "cpu" "ev4")
87 (eq_attr "type" "fst,fbr,iadd,imul,ilog,shift,icmov,icmp"))
90 (define_function_unit "ev4_ibus1" 1 0
91 (and (eq_attr "cpu" "ev4")
92 (eq_attr "type" "ist,ibr,jsr,fadd,fcmov,fcpys,fmul,fdiv,misc"))
95 ; Memory delivers its result in three cycles. Actually return one and
96 ; take care of this in adjust_cost, since we want to handle user-defined
98 (define_function_unit "ev4_abox" 1 0
99 (and (eq_attr "cpu" "ev4")
100 (eq_attr "type" "ild,fld,ldsym,ist,fst"))
103 ; Branches have no delay cost, but do tie up the unit for two cycles.
104 (define_function_unit "ev4_bbox" 1 1
105 (and (eq_attr "cpu" "ev4")
106 (eq_attr "type" "ibr,fbr,jsr"))
109 ; Arithmetic insns are normally have their results available after
110 ; two cycles. There are a number of exceptions. They are encoded in
111 ; ADJUST_COST. Some of the other insns have similar exceptions.
112 (define_function_unit "ev4_ebox" 1 0
113 (and (eq_attr "cpu" "ev4")
114 (eq_attr "type" "iadd,ilog,shift,icmov,icmp,misc"))
117 (define_function_unit "imul" 1 0
118 (and (eq_attr "cpu" "ev4")
119 (and (eq_attr "type" "imul")
120 (eq_attr "opsize" "si")))
123 (define_function_unit "imul" 1 0
124 (and (eq_attr "cpu" "ev4")
125 (and (eq_attr "type" "imul")
126 (eq_attr "opsize" "!si")))
129 (define_function_unit "ev4_fbox" 1 0
130 (and (eq_attr "cpu" "ev4")
131 (eq_attr "type" "fadd,fmul,fcpys,fcmov"))
134 (define_function_unit "fdiv" 1 0
135 (and (eq_attr "cpu" "ev4")
136 (and (eq_attr "type" "fdiv")
137 (eq_attr "opsize" "si")))
140 (define_function_unit "fdiv" 1 0
141 (and (eq_attr "cpu" "ev4")
142 (and (eq_attr "type" "fdiv")
143 (eq_attr "opsize" "di")))
146 ;; EV5 scheduling. EV5 can issue 4 insns per clock.
148 ;; EV5 has two asymetric integer units. Model this with E0 & E1 along
149 ;; with the combined resource EBOX.
151 (define_function_unit "ev5_ebox" 2 0
152 (and (eq_attr "cpu" "ev5")
153 (eq_attr "type" "!fbr,fcmov,fadd,fmul,fcpys,fdiv"))
156 ; Memory takes at least 2 clocks. Return one from here and fix up with
157 ; user-defined latencies in adjust_cost.
158 (define_function_unit "ev5_ebox" 2 0
159 (and (eq_attr "cpu" "ev5")
160 (eq_attr "type" "ild,fld,ldsym"))
163 ; Loads can dual issue with one another, but loads and stores do not mix.
164 (define_function_unit "ev5_e0" 1 0
165 (and (eq_attr "cpu" "ev5")
166 (eq_attr "type" "ild,fld,ldsym"))
168 [(eq_attr "type" "ist,fst")])
170 ; Stores, shifts, multiplies can only issue to E0
171 (define_function_unit "ev5_e0" 1 0
172 (and (eq_attr "cpu" "ev5")
173 (eq_attr "type" "ist,fst,shift,imul"))
176 ; Motion video insns also issue only to E0, and take two ticks.
177 (define_function_unit "ev5_e0" 1 0
178 (and (eq_attr "cpu" "ev5")
179 (eq_attr "type" "mvi"))
182 ; Conditional moves always take 2 ticks.
183 (define_function_unit "ev5_ebox" 2 0
184 (and (eq_attr "cpu" "ev5")
185 (eq_attr "type" "icmov"))
188 ; Branches can only issue to E1
189 (define_function_unit "ev5_e1" 1 0
190 (and (eq_attr "cpu" "ev5")
191 (eq_attr "type" "ibr,jsr"))
194 ; Multiplies also use the integer multiplier.
195 ; ??? How to: "No instruction can be issued to pipe E0 exactly two
196 ; cycles before an integer multiplication completes."
197 (define_function_unit "imul" 1 0
198 (and (eq_attr "cpu" "ev5")
199 (and (eq_attr "type" "imul")
200 (eq_attr "opsize" "si")))
203 (define_function_unit "imul" 1 0
204 (and (eq_attr "cpu" "ev5")
205 (and (eq_attr "type" "imul")
206 (eq_attr "opsize" "di")))
209 (define_function_unit "imul" 1 0
210 (and (eq_attr "cpu" "ev5")
211 (and (eq_attr "type" "imul")
212 (eq_attr "opsize" "udi")))
215 ;; Similarly for the FPU we have two asymetric units. But fcpys can issue
216 ;; on either so we have to play the game again.
218 (define_function_unit "ev5_fbox" 2 0
219 (and (eq_attr "cpu" "ev5")
220 (eq_attr "type" "fadd,fcmov,fmul,fcpys,fbr,fdiv"))
223 (define_function_unit "ev5_fm" 1 0
224 (and (eq_attr "cpu" "ev5")
225 (eq_attr "type" "fmul"))
228 ; Add and cmov as you would expect; fbr never produces a result;
229 ; fdiv issues through fa to the divider,
230 (define_function_unit "ev5_fa" 1 0
231 (and (eq_attr "cpu" "ev5")
232 (eq_attr "type" "fadd,fcmov,fbr,fdiv"))
235 ; ??? How to: "No instruction can be issued to pipe FA exactly five
236 ; cycles before a floating point divide completes."
237 (define_function_unit "fdiv" 1 0
238 (and (eq_attr "cpu" "ev5")
239 (and (eq_attr "type" "fdiv")
240 (eq_attr "opsize" "si")))
241 15 15) ; 15 to 31 data dependant
243 (define_function_unit "fdiv" 1 0
244 (and (eq_attr "cpu" "ev5")
245 (and (eq_attr "type" "fdiv")
246 (eq_attr "opsize" "di")))
247 22 22) ; 22 to 60 data dependant
249 ;; EV6 scheduling. EV6 can issue 4 insns per clock.
251 ;; EV6 has two symmetric pairs ("clusters") of two asymetric integer units
252 ;; ("upper" and "lower"), yielding pipe names U0, U1, L0, L1.
254 ;; Conditional moves decompose into two independant primitives, each
255 ;; taking one cycle. Since ev6 is out-of-order, we can't see anything
257 (define_function_unit "ev6_ebox" 4 0
258 (and (eq_attr "cpu" "ev6")
259 (eq_attr "type" "icmov"))
262 (define_function_unit "ev6_ebox" 4 0
263 (and (eq_attr "cpu" "ev6")
264 (eq_attr "type" "!fbr,fcmov,fadd,fmul,fcpys,fdiv,fsqrt"))
267 ;; Integer loads take at least 3 clocks, and only issue to lower units.
268 ;; Return one from here and fix up with user-defined latencies in adjust_cost.
269 (define_function_unit "ev6_l" 2 0
270 (and (eq_attr "cpu" "ev6")
271 (eq_attr "type" "ild,ldsym,ist,fst"))
274 ;; FP loads take at least 4 clocks. Return two from here...
275 (define_function_unit "ev6_l" 2 0
276 (and (eq_attr "cpu" "ev6")
277 (eq_attr "type" "fld"))
280 ;; Motion video insns also issue only to U0, and take three ticks.
281 (define_function_unit "ev6_u0" 1 0
282 (and (eq_attr "cpu" "ev6")
283 (eq_attr "type" "mvi"))
286 (define_function_unit "ev6_u" 2 0
287 (and (eq_attr "cpu" "ev6")
288 (eq_attr "type" "mvi"))
291 ;; Shifts issue to either upper pipe.
292 (define_function_unit "ev6_u" 2 0
293 (and (eq_attr "cpu" "ev6")
294 (eq_attr "type" "shift"))
297 ;; Multiplies issue only to U1, and all take 7 ticks.
298 ;; Rather than create a new function unit just for U1, reuse IMUL
299 (define_function_unit "imul" 1 0
300 (and (eq_attr "cpu" "ev6")
301 (eq_attr "type" "imul"))
304 (define_function_unit "ev6_u" 2 0
305 (and (eq_attr "cpu" "ev6")
306 (eq_attr "type" "imul"))
309 ;; Branches issue to either upper pipe
310 (define_function_unit "ev6_u" 2 0
311 (and (eq_attr "cpu" "ev6")
312 (eq_attr "type" "ibr"))
315 ;; Calls only issue to L0.
316 (define_function_unit "ev6_l0" 1 0
317 (and (eq_attr "cpu" "ev6")
318 (eq_attr "type" "jsr"))
321 (define_function_unit "ev6_l" 2 0
322 (and (eq_attr "cpu" "ev6")
323 (eq_attr "type" "jsr"))
326 ;; Ftoi/itof only issue to lower pipes
327 (define_function_unit "ev6_l" 2 0
328 (and (eq_attr "cpu" "ev6")
329 (eq_attr "type" "ftoi"))
332 (define_function_unit "ev6_l" 2 0
333 (and (eq_attr "cpu" "ev6")
334 (eq_attr "type" "itof"))
337 ;; For the FPU we are very similar to EV5, except there's no insn that
338 ;; can issue to fm & fa, so we get to leave that out.
340 (define_function_unit "ev6_fm" 1 0
341 (and (eq_attr "cpu" "ev6")
342 (eq_attr "type" "fmul"))
345 (define_function_unit "ev6_fa" 1 0
346 (and (eq_attr "cpu" "ev6")
347 (eq_attr "type" "fadd,fcpys,fbr,fdiv,fsqrt"))
350 (define_function_unit "ev6_fa" 1 0
351 (and (eq_attr "cpu" "ev6")
352 (eq_attr "type" "fcmov"))
355 (define_function_unit "fdiv" 1 0
356 (and (eq_attr "cpu" "ev6")
357 (and (eq_attr "type" "fdiv")
358 (eq_attr "opsize" "si")))
361 (define_function_unit "fdiv" 1 0
362 (and (eq_attr "cpu" "ev6")
363 (and (eq_attr "type" "fdiv")
364 (eq_attr "opsize" "di")))
367 (define_function_unit "fsqrt" 1 0
368 (and (eq_attr "cpu" "ev6")
369 (and (eq_attr "type" "fsqrt")
370 (eq_attr "opsize" "si")))
373 (define_function_unit "fsqrt" 1 0
374 (and (eq_attr "cpu" "ev6")
375 (and (eq_attr "type" "fsqrt")
376 (eq_attr "opsize" "di")))
379 ; ??? The FPU communicates with memory and the integer register file
380 ; via two fp store units. We need a slot in the fst immediately, and
381 ; a slot in LOW after the operand data is ready. At which point the
382 ; data may be moved either to the store queue or the integer register
383 ; file and the insn retired.
386 ;; First define the arithmetic insns. Note that the 32-bit forms also
389 ;; Handle 32-64 bit extension from memory to a floating point register
390 ;; specially, since this ocurrs frequently in int->double conversions.
391 ;; This is done with a define_split after reload converting the plain
392 ;; sign-extension into a load+unspec, which of course results in lds+cvtlq.
394 ;; Note that while we must retain the =f case in the insn for reload's
395 ;; benefit, it should be eliminated after reload, so we should never emit
396 ;; code for that case. But we don't reject the possibility.
398 (define_insn "extendsidi2"
399 [(set (match_operand:DI 0 "register_operand" "=r,r,?f")
400 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "r,m,m")))]
405 lds %0,%1\;cvtlq %0,%0"
406 [(set_attr "type" "iadd,ild,fld")
407 (set_attr "length" "*,*,8")])
409 ;; Due to issues with CLASS_CANNOT_CHANGE_SIZE, we cannot use a subreg here.
411 [(set (match_operand:DI 0 "hard_fp_register_operand" "")
412 (sign_extend:DI (match_operand:SI 1 "memory_operand" "")))]
414 [(set (match_dup 2) (match_dup 1))
415 (set (match_dup 0) (unspec:DI [(match_dup 2)] 4))]
416 "operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]));")
419 [(set (match_operand:DI 0 "register_operand" "=f")
420 (unspec:DI [(match_operand:SI 1 "register_operand" "f")] 4))]
423 [(set_attr "type" "fadd")])
425 ;; Do addsi3 the way expand_binop would do if we didn't have one. This
426 ;; generates better code. We have the anonymous addsi3 pattern below in
427 ;; case combine wants to make it.
428 (define_expand "addsi3"
429 [(set (match_operand:SI 0 "register_operand" "")
430 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "")
431 (match_operand:SI 2 "add_operand" "")))]
437 rtx op1 = gen_lowpart (DImode, operands[1]);
438 rtx op2 = gen_lowpart (DImode, operands[2]);
440 if (! cse_not_expected)
442 rtx tmp = gen_reg_rtx (DImode);
443 emit_insn (gen_adddi3 (tmp, op1, op2));
444 emit_move_insn (gen_lowpart (DImode, operands[0]), tmp);
447 emit_insn (gen_adddi3 (gen_lowpart (DImode, operands[0]), op1, op2));
453 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
454 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ")
455 (match_operand:SI 2 "add_operand" "rI,O,K,L")))]
464 [(set (match_operand:SI 0 "register_operand" "")
465 (plus:SI (match_operand:SI 1 "register_operand" "")
466 (match_operand:SI 2 "const_int_operand" "")))]
467 "! add_operand (operands[2], SImode)"
468 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
469 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
472 HOST_WIDE_INT val = INTVAL (operands[2]);
473 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
474 HOST_WIDE_INT rest = val - low;
476 operands[3] = GEN_INT (rest);
477 operands[4] = GEN_INT (low);
481 [(set (match_operand:DI 0 "register_operand" "=r,r")
483 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
484 (match_operand:SI 2 "sext_add_operand" "rI,O"))))]
491 [(set (match_operand:DI 0 "register_operand" "")
493 (plus:SI (match_operand:SI 1 "register_operand" "")
494 (match_operand:SI 2 "const_int_operand" ""))))
495 (clobber (match_operand:SI 3 "reg_not_elim_operand" ""))]
496 "! sext_add_operand (operands[2], SImode) && INTVAL (operands[2]) > 0
497 && INTVAL (operands[2]) % 4 == 0"
498 [(set (match_dup 3) (match_dup 4))
499 (set (match_dup 0) (sign_extend:DI (plus:SI (mult:SI (match_dup 3)
504 HOST_WIDE_INT val = INTVAL (operands[2]) / 4;
510 operands[4] = GEN_INT (val);
511 operands[5] = GEN_INT (mult);
515 [(set (match_operand:DI 0 "register_operand" "")
517 (plus:SI (match_operator:SI 1 "comparison_operator"
518 [(match_operand 2 "" "")
519 (match_operand 3 "" "")])
520 (match_operand:SI 4 "add_operand" ""))))
521 (clobber (match_operand:DI 5 "register_operand" ""))]
523 [(set (match_dup 5) (match_dup 6))
524 (set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 7) (match_dup 4))))]
527 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
528 operands[2], operands[3]);
529 operands[7] = gen_lowpart (SImode, operands[5]);
532 (define_insn "adddi3"
533 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
534 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ")
535 (match_operand:DI 2 "add_operand" "rI,O,K,L")))]
543 ;; Don't do this if we are adjusting SP since we don't want to do
546 [(set (match_operand:DI 0 "register_operand" "")
547 (plus:DI (match_operand:DI 1 "register_operand" "")
548 (match_operand:DI 2 "const_int_operand" "")))]
549 "! add_operand (operands[2], DImode)
550 && REGNO (operands[0]) != STACK_POINTER_REGNUM"
551 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
552 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
555 HOST_WIDE_INT val = INTVAL (operands[2]);
556 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
557 HOST_WIDE_INT rest = val - low;
559 operands[3] = GEN_INT (rest);
560 operands[4] = GEN_INT (low);
564 [(set (match_operand:SI 0 "register_operand" "=r,r")
565 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
566 (match_operand:SI 2 "const48_operand" "I,I"))
567 (match_operand:SI 3 "sext_add_operand" "rI,O")))]
574 [(set (match_operand:DI 0 "register_operand" "=r,r")
576 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
577 (match_operand:SI 2 "const48_operand" "I,I"))
578 (match_operand:SI 3 "sext_add_operand" "rI,O"))))]
585 [(set (match_operand:DI 0 "register_operand" "")
587 (plus:SI (mult:SI (match_operator:SI 1 "comparison_operator"
588 [(match_operand 2 "" "")
589 (match_operand 3 "" "")])
590 (match_operand:SI 4 "const48_operand" ""))
591 (match_operand:SI 5 "add_operand" ""))))
592 (clobber (match_operand:DI 6 "reg_not_elim_operand" ""))]
594 [(set (match_dup 6) (match_dup 7))
596 (sign_extend:DI (plus:SI (mult:SI (match_dup 8) (match_dup 4))
600 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
601 operands[2], operands[3]);
602 operands[8] = gen_lowpart (SImode, operands[6]);
606 [(set (match_operand:DI 0 "register_operand" "=r,r")
607 (plus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r,r")
608 (match_operand:DI 2 "const48_operand" "I,I"))
609 (match_operand:DI 3 "sext_add_operand" "rI,O")))]
615 ;; These variants of the above insns can occur if the third operand
616 ;; is the frame pointer. This is a kludge, but there doesn't
617 ;; seem to be a way around it. Only recognize them while reloading.
620 [(set (match_operand:DI 0 "some_operand" "=&r")
621 (plus:DI (plus:DI (match_operand:DI 1 "some_operand" "r")
622 (match_operand:DI 2 "some_operand" "r"))
623 (match_operand:DI 3 "some_operand" "rIOKL")))]
628 [(set (match_operand:DI 0 "register_operand" "")
629 (plus:DI (plus:DI (match_operand:DI 1 "register_operand" "")
630 (match_operand:DI 2 "register_operand" ""))
631 (match_operand:DI 3 "add_operand" "")))]
633 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))
634 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
638 [(set (match_operand:SI 0 "some_operand" "=&r")
639 (plus:SI (plus:SI (mult:SI (match_operand:SI 1 "some_operand" "rJ")
640 (match_operand:SI 2 "const48_operand" "I"))
641 (match_operand:SI 3 "some_operand" "r"))
642 (match_operand:SI 4 "some_operand" "rIOKL")))]
647 [(set (match_operand:SI 0 "register_operand" "r")
648 (plus:SI (plus:SI (mult:SI (match_operand:SI 1 "reg_or_0_operand" "")
649 (match_operand:SI 2 "const48_operand" ""))
650 (match_operand:SI 3 "register_operand" ""))
651 (match_operand:SI 4 "add_operand" "rIOKL")))]
654 (plus:SI (mult:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
655 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
659 [(set (match_operand:DI 0 "some_operand" "=&r")
662 (mult:SI (match_operand:SI 1 "some_operand" "rJ")
663 (match_operand:SI 2 "const48_operand" "I"))
664 (match_operand:SI 3 "some_operand" "r"))
665 (match_operand:SI 4 "some_operand" "rIOKL"))))]
670 [(set (match_operand:DI 0 "register_operand" "")
673 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "")
674 (match_operand:SI 2 "const48_operand" ""))
675 (match_operand:SI 3 "register_operand" ""))
676 (match_operand:SI 4 "add_operand" ""))))]
679 (plus:SI (mult:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
680 (set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 5) (match_dup 4))))]
681 "operands[5] = gen_lowpart (SImode, operands[0]);")
684 [(set (match_operand:DI 0 "some_operand" "=&r")
685 (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "some_operand" "rJ")
686 (match_operand:DI 2 "const48_operand" "I"))
687 (match_operand:DI 3 "some_operand" "r"))
688 (match_operand:DI 4 "some_operand" "rIOKL")))]
693 [(set (match_operand:DI 0 "register_operand" "=")
694 (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "reg_or_0_operand" "")
695 (match_operand:DI 2 "const48_operand" ""))
696 (match_operand:DI 3 "register_operand" ""))
697 (match_operand:DI 4 "add_operand" "")))]
700 (plus:DI (mult:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
701 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
704 (define_insn "negsi2"
705 [(set (match_operand:SI 0 "register_operand" "=r")
706 (neg:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))]
711 [(set (match_operand:DI 0 "register_operand" "=r")
712 (sign_extend:DI (neg:SI
713 (match_operand:SI 1 "reg_or_8bit_operand" "rI"))))]
717 (define_insn "negdi2"
718 [(set (match_operand:DI 0 "register_operand" "=r")
719 (neg:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
723 (define_expand "subsi3"
724 [(set (match_operand:SI 0 "register_operand" "")
725 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "")
726 (match_operand:SI 2 "reg_or_8bit_operand" "")))]
732 rtx op1 = gen_lowpart (DImode, operands[1]);
733 rtx op2 = gen_lowpart (DImode, operands[2]);
735 if (! cse_not_expected)
737 rtx tmp = gen_reg_rtx (DImode);
738 emit_insn (gen_subdi3 (tmp, op1, op2));
739 emit_move_insn (gen_lowpart (DImode, operands[0]), tmp);
742 emit_insn (gen_subdi3 (gen_lowpart (DImode, operands[0]), op1, op2));
748 [(set (match_operand:SI 0 "register_operand" "=r")
749 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
750 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
755 [(set (match_operand:DI 0 "register_operand" "=r")
756 (sign_extend:DI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
757 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
761 (define_insn "subdi3"
762 [(set (match_operand:DI 0 "register_operand" "=r")
763 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
764 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
769 [(set (match_operand:SI 0 "register_operand" "=r")
770 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
771 (match_operand:SI 2 "const48_operand" "I"))
772 (match_operand:SI 3 "reg_or_8bit_operand" "rI")))]
777 [(set (match_operand:DI 0 "register_operand" "=r")
779 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
780 (match_operand:SI 2 "const48_operand" "I"))
781 (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))]
786 [(set (match_operand:DI 0 "register_operand" "=r")
787 (minus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r")
788 (match_operand:DI 2 "const48_operand" "I"))
789 (match_operand:DI 3 "reg_or_8bit_operand" "rI")))]
793 (define_insn "mulsi3"
794 [(set (match_operand:SI 0 "register_operand" "=r")
795 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
796 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
799 [(set_attr "type" "imul")
800 (set_attr "opsize" "si")])
803 [(set (match_operand:DI 0 "register_operand" "=r")
805 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
806 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
809 [(set_attr "type" "imul")
810 (set_attr "opsize" "si")])
812 (define_insn "muldi3"
813 [(set (match_operand:DI 0 "register_operand" "=r")
814 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
815 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
818 [(set_attr "type" "imul")])
820 (define_insn "umuldi3_highpart"
821 [(set (match_operand:DI 0 "register_operand" "=r")
824 (mult:TI (zero_extend:TI
825 (match_operand:DI 1 "reg_or_0_operand" "%rJ"))
827 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
831 [(set_attr "type" "imul")
832 (set_attr "opsize" "udi")])
835 [(set (match_operand:DI 0 "register_operand" "=r")
838 (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "r"))
839 (match_operand:TI 2 "cint8_operand" "I"))
843 [(set_attr "type" "imul")
844 (set_attr "opsize" "udi")])
846 ;; The divide and remainder operations always take their inputs from
847 ;; r24 and r25, put their output in r27, and clobber r23 and r28.
849 ;; ??? Force sign-extension here because some versions of OSF/1 don't
850 ;; do the right thing if the inputs are not properly sign-extended.
851 ;; But Linux, for instance, does not have this problem. Is it worth
852 ;; the complication here to eliminate the sign extension?
854 (define_expand "divsi3"
856 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
858 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
859 (parallel [(set (reg:DI 27)
860 (sign_extend:DI (div:SI (reg:DI 24) (reg:DI 25))))
861 (clobber (reg:DI 23))
862 (clobber (reg:DI 28))])
863 (set (match_operand:SI 0 "general_operand" "")
864 (subreg:SI (reg:DI 27) 0))]
868 (define_expand "udivsi3"
870 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
872 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
873 (parallel [(set (reg:DI 27)
874 (sign_extend:DI (udiv:SI (reg:DI 24) (reg:DI 25))))
875 (clobber (reg:DI 23))
876 (clobber (reg:DI 28))])
877 (set (match_operand:SI 0 "general_operand" "")
878 (subreg:SI (reg:DI 27) 0))]
882 (define_expand "modsi3"
884 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
886 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
887 (parallel [(set (reg:DI 27)
888 (sign_extend:DI (mod:SI (reg:DI 24) (reg:DI 25))))
889 (clobber (reg:DI 23))
890 (clobber (reg:DI 28))])
891 (set (match_operand:SI 0 "general_operand" "")
892 (subreg:SI (reg:DI 27) 0))]
896 (define_expand "umodsi3"
898 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
900 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
901 (parallel [(set (reg:DI 27)
902 (sign_extend:DI (umod:SI (reg:DI 24) (reg:DI 25))))
903 (clobber (reg:DI 23))
904 (clobber (reg:DI 28))])
905 (set (match_operand:SI 0 "general_operand" "")
906 (subreg:SI (reg:DI 27) 0))]
910 (define_expand "divdi3"
911 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
912 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
913 (parallel [(set (reg:DI 27)
916 (clobber (reg:DI 23))
917 (clobber (reg:DI 28))])
918 (set (match_operand:DI 0 "general_operand" "")
923 (define_expand "udivdi3"
924 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
925 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
926 (parallel [(set (reg:DI 27)
929 (clobber (reg:DI 23))
930 (clobber (reg:DI 28))])
931 (set (match_operand:DI 0 "general_operand" "")
936 (define_expand "moddi3"
937 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
938 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
939 (parallel [(set (reg:DI 27)
942 (clobber (reg:DI 23))
943 (clobber (reg:DI 28))])
944 (set (match_operand:DI 0 "general_operand" "")
949 (define_expand "umoddi3"
950 [(set (reg:DI 24) (match_operand:DI 1 "input_operand" ""))
951 (set (reg:DI 25) (match_operand:DI 2 "input_operand" ""))
952 (parallel [(set (reg:DI 27)
955 (clobber (reg:DI 23))
956 (clobber (reg:DI 28))])
957 (set (match_operand:DI 0 "general_operand" "")
962 ;; Lengths of 8 for ldq $t12,__divq($gp); jsr $t9,($t12),__divq as
963 ;; expanded by the assembler.
966 (sign_extend:DI (match_operator:SI 1 "divmod_operator"
967 [(reg:DI 24) (reg:DI 25)])))
968 (clobber (reg:DI 23))
969 (clobber (reg:DI 28))]
972 [(set_attr "type" "jsr")
973 (set_attr "length" "8")])
977 (match_operator:DI 1 "divmod_operator"
978 [(reg:DI 24) (reg:DI 25)]))
979 (clobber (reg:DI 23))
980 (clobber (reg:DI 28))]
983 [(set_attr "type" "jsr")
984 (set_attr "length" "8")])
986 ;; Next are the basic logical operations. These only exist in DImode.
988 (define_insn "anddi3"
989 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
990 (and:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ")
991 (match_operand:DI 2 "and_operand" "rI,N,MH")))]
997 [(set_attr "type" "ilog,ilog,shift")])
999 ;; There are times when we can split an AND into two AND insns. This occurs
1000 ;; when we can first clear any bytes and then clear anything else. For
1001 ;; example "I & 0xffff07" is "(I & 0xffffff) & 0xffffffffffffff07".
1002 ;; Only do this when running on 64-bit host since the computations are
1003 ;; too messy otherwise.
1006 [(set (match_operand:DI 0 "register_operand" "")
1007 (and:DI (match_operand:DI 1 "register_operand" "")
1008 (match_operand:DI 2 "const_int_operand" "")))]
1009 "HOST_BITS_PER_WIDE_INT == 64 && ! and_operand (operands[2], DImode)"
1010 [(set (match_dup 0) (and:DI (match_dup 1) (match_dup 3)))
1011 (set (match_dup 0) (and:DI (match_dup 0) (match_dup 4)))]
1014 unsigned HOST_WIDE_INT mask1 = INTVAL (operands[2]);
1015 unsigned HOST_WIDE_INT mask2 = mask1;
1018 /* For each byte that isn't all zeros, make it all ones. */
1019 for (i = 0; i < 64; i += 8)
1020 if ((mask1 & ((HOST_WIDE_INT) 0xff << i)) != 0)
1021 mask1 |= (HOST_WIDE_INT) 0xff << i;
1023 /* Now turn on any bits we've just turned off. */
1026 operands[3] = GEN_INT (mask1);
1027 operands[4] = GEN_INT (mask2);
1030 (define_insn "zero_extendqihi2"
1031 [(set (match_operand:HI 0 "register_operand" "=r")
1032 (zero_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1035 [(set_attr "type" "ilog")])
1038 [(set (match_operand:SI 0 "register_operand" "=r,r")
1039 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1044 [(set_attr "type" "ilog,ild")])
1047 [(set (match_operand:SI 0 "register_operand" "=r")
1048 (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1051 [(set_attr "type" "ilog")])
1053 (define_expand "zero_extendqisi2"
1054 [(set (match_operand:SI 0 "register_operand" "")
1055 (zero_extend:SI (match_operand:QI 1 "register_operand" "")))]
1060 [(set (match_operand:DI 0 "register_operand" "=r,r")
1061 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1066 [(set_attr "type" "ilog,ild")])
1069 [(set (match_operand:DI 0 "register_operand" "=r")
1070 (zero_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1073 [(set_attr "type" "ilog")])
1075 (define_expand "zero_extendqidi2"
1076 [(set (match_operand:DI 0 "register_operand" "")
1077 (zero_extend:DI (match_operand:QI 1 "register_operand" "")))]
1082 [(set (match_operand:SI 0 "register_operand" "=r,r")
1083 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1088 [(set_attr "type" "shift,ild")])
1091 [(set (match_operand:SI 0 "register_operand" "=r")
1092 (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1095 [(set_attr "type" "shift")])
1097 (define_expand "zero_extendhisi2"
1098 [(set (match_operand:SI 0 "register_operand" "")
1099 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
1104 [(set (match_operand:DI 0 "register_operand" "=r,r")
1105 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1110 [(set_attr "type" "shift,ild")])
1113 [(set (match_operand:DI 0 "register_operand" "=r")
1114 (zero_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1117 [(set_attr "type" "shift")])
1119 (define_expand "zero_extendhidi2"
1120 [(set (match_operand:DI 0 "register_operand" "")
1121 (zero_extend:DI (match_operand:HI 1 "register_operand" "")))]
1125 (define_insn "zero_extendsidi2"
1126 [(set (match_operand:DI 0 "register_operand" "=r")
1127 (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
1130 [(set_attr "type" "shift")])
1133 [(set (match_operand:DI 0 "register_operand" "=r")
1134 (and:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1135 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1138 [(set_attr "type" "ilog")])
1140 (define_insn "iordi3"
1141 [(set (match_operand:DI 0 "register_operand" "=r,r")
1142 (ior:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1143 (match_operand:DI 2 "or_operand" "rI,N")))]
1148 [(set_attr "type" "ilog")])
1150 (define_insn "one_cmpldi2"
1151 [(set (match_operand:DI 0 "register_operand" "=r")
1152 (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
1155 [(set_attr "type" "ilog")])
1158 [(set (match_operand:DI 0 "register_operand" "=r")
1159 (ior:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1160 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1163 [(set_attr "type" "ilog")])
1165 (define_insn "xordi3"
1166 [(set (match_operand:DI 0 "register_operand" "=r,r")
1167 (xor:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1168 (match_operand:DI 2 "or_operand" "rI,N")))]
1173 [(set_attr "type" "ilog")])
1176 [(set (match_operand:DI 0 "register_operand" "=r")
1177 (not:DI (xor:DI (match_operand:DI 1 "register_operand" "%rJ")
1178 (match_operand:DI 2 "register_operand" "rI"))))]
1181 [(set_attr "type" "ilog")])
1183 ;; Handle the FFS insn if we support CIX.
1185 (define_expand "ffsdi2"
1187 (unspec [(match_operand:DI 1 "register_operand" "")] 1))
1189 (plus:DI (match_dup 2) (const_int 1)))
1190 (set (match_operand:DI 0 "register_operand" "")
1191 (if_then_else:DI (eq (match_dup 1) (const_int 0))
1192 (const_int 0) (match_dup 3)))]
1196 operands[2] = gen_reg_rtx (DImode);
1197 operands[3] = gen_reg_rtx (DImode);
1201 [(set (match_operand:DI 0 "register_operand" "=r")
1202 (unspec [(match_operand:DI 1 "register_operand" "r")] 1))]
1205 ; ev6 calls all mvi and cttz/ctlz/popc class imisc, so just
1206 ; reuse the existing type name.
1207 [(set_attr "type" "mvi")])
1209 ;; Next come the shifts and the various extract and insert operations.
1211 (define_insn "ashldi3"
1212 [(set (match_operand:DI 0 "register_operand" "=r,r")
1213 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,rJ")
1214 (match_operand:DI 2 "reg_or_6bit_operand" "P,rS")))]
1218 switch (which_alternative)
1221 if (operands[2] == const1_rtx)
1222 return \"addq %r1,%r1,%0\";
1224 return \"s%P2addq %r1,0,%0\";
1226 return \"sll %r1,%2,%0\";
1231 [(set_attr "type" "iadd,shift")])
1233 ;; ??? The following pattern is made by combine, but earlier phases
1234 ;; (specifically flow) can't handle it. This occurs in jump.c. Deal
1235 ;; with this in a better way at some point.
1237 ;; [(set (match_operand:DI 0 "register_operand" "=r")
1239 ;; (subreg:SI (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1240 ;; (match_operand:DI 2 "const_int_operand" "P"))
1242 ;; "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3"
1245 ;; if (operands[2] == const1_rtx)
1246 ;; return \"addl %r1,%r1,%0\";
1248 ;; return \"s%P2addl %r1,0,%0\";
1250 ;; [(set_attr "type" "iadd")])
1252 (define_insn "lshrdi3"
1253 [(set (match_operand:DI 0 "register_operand" "=r")
1254 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1255 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1258 [(set_attr "type" "shift")])
1260 (define_insn "ashrdi3"
1261 [(set (match_operand:DI 0 "register_operand" "=r")
1262 (ashiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1263 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1266 [(set_attr "type" "shift")])
1268 (define_expand "extendqihi2"
1270 (ashift:DI (match_operand:QI 1 "some_operand" "")
1272 (set (match_operand:HI 0 "register_operand" "")
1273 (ashiftrt:DI (match_dup 2)
1280 emit_insn (gen_extendqihi2x (operands[0],
1281 force_reg (QImode, operands[1])));
1285 /* If we have an unaligned MEM, extend to DImode (which we do
1286 specially) and then copy to the result. */
1287 if (unaligned_memory_operand (operands[1], HImode))
1289 rtx temp = gen_reg_rtx (DImode);
1291 emit_insn (gen_extendqidi2 (temp, operands[1]));
1292 emit_move_insn (operands[0], gen_lowpart (HImode, temp));
1296 operands[0] = gen_lowpart (DImode, operands[0]);
1297 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1298 operands[2] = gen_reg_rtx (DImode);
1301 (define_insn "extendqidi2x"
1302 [(set (match_operand:DI 0 "register_operand" "=r")
1303 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1306 [(set_attr "type" "shift")])
1308 (define_insn "extendhidi2x"
1309 [(set (match_operand:DI 0 "register_operand" "=r")
1310 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1313 [(set_attr "type" "shift")])
1315 (define_insn "extendqisi2x"
1316 [(set (match_operand:SI 0 "register_operand" "=r")
1317 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1320 [(set_attr "type" "shift")])
1322 (define_insn "extendhisi2x"
1323 [(set (match_operand:SI 0 "register_operand" "=r")
1324 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1327 [(set_attr "type" "shift")])
1329 (define_insn "extendqihi2x"
1330 [(set (match_operand:HI 0 "register_operand" "=r")
1331 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1334 [(set_attr "type" "shift")])
1336 (define_expand "extendqisi2"
1338 (ashift:DI (match_operand:QI 1 "some_operand" "")
1340 (set (match_operand:SI 0 "register_operand" "")
1341 (ashiftrt:DI (match_dup 2)
1348 emit_insn (gen_extendqisi2x (operands[0],
1349 force_reg (QImode, operands[1])));
1353 /* If we have an unaligned MEM, extend to a DImode form of
1354 the result (which we do specially). */
1355 if (unaligned_memory_operand (operands[1], QImode))
1357 rtx temp = gen_reg_rtx (DImode);
1359 emit_insn (gen_extendqidi2 (temp, operands[1]));
1360 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1364 operands[0] = gen_lowpart (DImode, operands[0]);
1365 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1366 operands[2] = gen_reg_rtx (DImode);
1369 (define_expand "extendqidi2"
1371 (ashift:DI (match_operand:QI 1 "some_operand" "")
1373 (set (match_operand:DI 0 "register_operand" "")
1374 (ashiftrt:DI (match_dup 2)
1381 emit_insn (gen_extendqidi2x (operands[0],
1382 force_reg (QImode, operands[1])));
1386 if (unaligned_memory_operand (operands[1], QImode))
1389 = gen_unaligned_extendqidi (operands[0],
1390 get_unaligned_address (operands[1], 1));
1392 alpha_set_memflags (seq, operands[1]);
1397 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1398 operands[2] = gen_reg_rtx (DImode);
1401 (define_expand "extendhisi2"
1403 (ashift:DI (match_operand:HI 1 "some_operand" "")
1405 (set (match_operand:SI 0 "register_operand" "")
1406 (ashiftrt:DI (match_dup 2)
1413 emit_insn (gen_extendhisi2x (operands[0],
1414 force_reg (HImode, operands[1])));
1418 /* If we have an unaligned MEM, extend to a DImode form of
1419 the result (which we do specially). */
1420 if (unaligned_memory_operand (operands[1], HImode))
1422 rtx temp = gen_reg_rtx (DImode);
1424 emit_insn (gen_extendhidi2 (temp, operands[1]));
1425 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1429 operands[0] = gen_lowpart (DImode, operands[0]);
1430 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1431 operands[2] = gen_reg_rtx (DImode);
1434 (define_expand "extendhidi2"
1436 (ashift:DI (match_operand:HI 1 "some_operand" "")
1438 (set (match_operand:DI 0 "register_operand" "")
1439 (ashiftrt:DI (match_dup 2)
1446 emit_insn (gen_extendhidi2x (operands[0],
1447 force_reg (HImode, operands[1])));
1451 if (unaligned_memory_operand (operands[1], HImode))
1454 = gen_unaligned_extendhidi (operands[0],
1455 get_unaligned_address (operands[1], 2));
1457 alpha_set_memflags (seq, operands[1]);
1462 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1463 operands[2] = gen_reg_rtx (DImode);
1466 ;; Here's how we sign extend an unaligned byte and halfword. Doing this
1467 ;; as a pattern saves one instruction. The code is similar to that for
1468 ;; the unaligned loads (see below).
1470 ;; Operand 1 is the address + 1 (+2 for HI), operand 0 is the result.
1471 (define_expand "unaligned_extendqidi"
1472 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1474 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -1))
1477 (ashift:DI (match_dup 3)
1478 (minus:DI (const_int 56)
1480 (and:DI (plus:DI (match_dup 2) (const_int -1))
1483 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1484 (ashiftrt:DI (match_dup 4) (const_int 56)))]
1487 { operands[2] = gen_reg_rtx (DImode);
1488 operands[3] = gen_reg_rtx (DImode);
1489 operands[4] = gen_reg_rtx (DImode);
1492 (define_expand "unaligned_extendhidi"
1493 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1495 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -2))
1498 (ashift:DI (match_dup 3)
1499 (minus:DI (const_int 56)
1501 (and:DI (plus:DI (match_dup 2) (const_int -1))
1504 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1505 (ashiftrt:DI (match_dup 4) (const_int 48)))]
1508 { operands[2] = gen_reg_rtx (DImode);
1509 operands[3] = gen_reg_rtx (DImode);
1510 operands[4] = gen_reg_rtx (DImode);
1514 [(set (match_operand:DI 0 "register_operand" "=r")
1515 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1516 (match_operand:DI 2 "mode_width_operand" "n")
1517 (match_operand:DI 3 "mul8_operand" "I")))]
1519 "ext%M2l %r1,%s3,%0"
1520 [(set_attr "type" "shift")])
1522 (define_insn "extxl"
1523 [(set (match_operand:DI 0 "register_operand" "=r")
1524 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1525 (match_operand:DI 2 "mode_width_operand" "n")
1526 (ashift:DI (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1530 [(set_attr "type" "shift")])
1532 ;; Combine has some strange notion of preserving existing undefined behaviour
1533 ;; in shifts larger than a word size. So capture these patterns that it
1534 ;; should have turned into zero_extracts.
1537 [(set (match_operand:DI 0 "register_operand" "=r")
1538 (and (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1539 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1541 (match_operand:DI 3 "mode_mask_operand" "n")))]
1544 [(set_attr "type" "shift")])
1547 [(set (match_operand:DI 0 "register_operand" "=r")
1548 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1549 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1553 [(set_attr "type" "shift")])
1555 (define_insn "extqh"
1556 [(set (match_operand:DI 0 "register_operand" "=r")
1558 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1559 (minus:DI (const_int 56)
1562 (plus:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1568 [(set_attr "type" "shift")])
1570 (define_insn "extlh"
1571 [(set (match_operand:DI 0 "register_operand" "=r")
1573 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1574 (const_int 2147483647))
1575 (minus:DI (const_int 56)
1578 (plus:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1584 [(set_attr "type" "shift")])
1586 (define_insn "extwh"
1587 [(set (match_operand:DI 0 "register_operand" "=r")
1589 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1591 (minus:DI (const_int 56)
1594 (plus:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1600 [(set_attr "type" "shift")])
1602 ;; This converts an extXl into an extXh with an appropriate adjustment
1603 ;; to the address calculation.
1606 ;; [(set (match_operand:DI 0 "register_operand" "")
1607 ;; (ashift:DI (zero_extract:DI (match_operand:DI 1 "register_operand" "")
1608 ;; (match_operand:DI 2 "mode_width_operand" "")
1609 ;; (ashift:DI (match_operand:DI 3 "" "")
1611 ;; (match_operand:DI 4 "const_int_operand" "")))
1612 ;; (clobber (match_operand:DI 5 "register_operand" ""))]
1613 ;; "INTVAL (operands[4]) == 64 - INTVAL (operands[2])"
1614 ;; [(set (match_dup 5) (match_dup 6))
1615 ;; (set (match_dup 0)
1616 ;; (ashift:DI (zero_extract:DI (match_dup 1) (match_dup 2)
1617 ;; (ashift:DI (plus:DI (match_dup 5)
1623 ;; operands[6] = plus_constant (operands[3],
1624 ;; INTVAL (operands[2]) / BITS_PER_UNIT);
1625 ;; operands[7] = GEN_INT (- INTVAL (operands[2]) / BITS_PER_UNIT);
1629 [(set (match_operand:DI 0 "register_operand" "=r")
1630 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
1631 (match_operand:DI 2 "mul8_operand" "I")))]
1634 [(set_attr "type" "shift")])
1637 [(set (match_operand:DI 0 "register_operand" "=r")
1638 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
1639 (match_operand:DI 2 "mul8_operand" "I")))]
1642 [(set_attr "type" "shift")])
1645 [(set (match_operand:DI 0 "register_operand" "=r")
1646 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
1647 (match_operand:DI 2 "mul8_operand" "I")))]
1650 [(set_attr "type" "shift")])
1652 (define_insn "insbl"
1653 [(set (match_operand:DI 0 "register_operand" "=r")
1654 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
1655 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1659 [(set_attr "type" "shift")])
1661 (define_insn "inswl"
1662 [(set (match_operand:DI 0 "register_operand" "=r")
1663 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
1664 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1668 [(set_attr "type" "shift")])
1670 (define_insn "insll"
1671 [(set (match_operand:DI 0 "register_operand" "=r")
1672 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
1673 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1677 [(set_attr "type" "shift")])
1679 (define_insn "insql"
1680 [(set (match_operand:DI 0 "register_operand" "=r")
1681 (ashift:DI (match_operand:DI 1 "register_operand" "r")
1682 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1686 [(set_attr "type" "shift")])
1688 ;; Combine has this sometimes habit of moving the and outside of the
1689 ;; shift, making life more interesting.
1692 [(set (match_operand:DI 0 "register_operand" "=r")
1693 (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
1694 (match_operand:DI 2 "mul8_operand" "I"))
1695 (match_operand:DI 3 "immediate_operand" "i")))]
1696 "HOST_BITS_PER_WIDE_INT == 64
1697 && GET_CODE (operands[3]) == CONST_INT
1698 && (((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
1699 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1700 || ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
1701 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1702 || ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
1703 == (unsigned HOST_WIDE_INT) INTVAL (operands[3])))"
1706 #if HOST_BITS_PER_WIDE_INT == 64
1707 if ((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
1708 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1709 return \"insbl %1,%s2,%0\";
1710 if ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
1711 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1712 return \"inswl %1,%s2,%0\";
1713 if ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
1714 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
1715 return \"insll %1,%s2,%0\";
1719 [(set_attr "type" "shift")])
1721 ;; We do not include the insXh insns because they are complex to express
1722 ;; and it does not appear that we would ever want to generate them.
1724 ;; Since we need them for block moves, though, cop out and use unspec.
1726 (define_insn "insxh"
1727 [(set (match_operand:DI 0 "register_operand" "=r")
1728 (unspec [(match_operand:DI 1 "register_operand" "r")
1729 (match_operand:DI 2 "mode_width_operand" "n")
1730 (match_operand:DI 3 "reg_or_8bit_operand" "rI")] 2))]
1733 [(set_attr "type" "shift")])
1735 (define_insn "mskxl"
1736 [(set (match_operand:DI 0 "register_operand" "=r")
1737 (and:DI (not:DI (ashift:DI
1738 (match_operand:DI 2 "mode_mask_operand" "n")
1740 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1742 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
1745 [(set_attr "type" "shift")])
1747 ;; We do not include the mskXh insns because it does not appear we would
1748 ;; ever generate one.
1750 ;; Again, we do for block moves and we use unspec again.
1752 (define_insn "mskxh"
1753 [(set (match_operand:DI 0 "register_operand" "=r")
1754 (unspec [(match_operand:DI 1 "register_operand" "r")
1755 (match_operand:DI 2 "mode_width_operand" "n")
1756 (match_operand:DI 3 "reg_or_8bit_operand" "rI")] 3))]
1759 [(set_attr "type" "shift")])
1761 ;; Floating-point operations. All the double-precision insns can extend
1762 ;; from single, so indicate that. The exception are the ones that simply
1763 ;; play with the sign bits; it's not clear what to do there.
1765 (define_insn "abssf2"
1766 [(set (match_operand:SF 0 "register_operand" "=f")
1767 (abs:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
1770 [(set_attr "type" "fcpys")])
1772 (define_insn "absdf2"
1773 [(set (match_operand:DF 0 "register_operand" "=f")
1774 (abs:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
1777 [(set_attr "type" "fcpys")])
1779 (define_insn "negsf2"
1780 [(set (match_operand:SF 0 "register_operand" "=f")
1781 (neg:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
1784 [(set_attr "type" "fadd")])
1786 (define_insn "negdf2"
1787 [(set (match_operand:DF 0 "register_operand" "=f")
1788 (neg:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
1791 [(set_attr "type" "fadd")])
1794 [(set (match_operand:SF 0 "register_operand" "=&f")
1795 (plus:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
1796 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
1797 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
1798 "add%,%)%& %R1,%R2,%0"
1799 [(set_attr "type" "fadd")
1800 (set_attr "trap" "yes")])
1802 (define_insn "addsf3"
1803 [(set (match_operand:SF 0 "register_operand" "=f")
1804 (plus:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
1805 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
1807 "add%,%)%& %R1,%R2,%0"
1808 [(set_attr "type" "fadd")
1809 (set_attr "trap" "yes")])
1812 [(set (match_operand:DF 0 "register_operand" "=&f")
1813 (plus:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
1814 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
1815 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
1816 "add%-%)%& %R1,%R2,%0"
1817 [(set_attr "type" "fadd")
1818 (set_attr "trap" "yes")])
1820 (define_insn "adddf3"
1821 [(set (match_operand:DF 0 "register_operand" "=f")
1822 (plus:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
1823 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
1825 "add%-%)%& %R1,%R2,%0"
1826 [(set_attr "type" "fadd")
1827 (set_attr "trap" "yes")])
1830 [(set (match_operand:DF 0 "register_operand" "=f")
1831 (plus:DF (float_extend:DF
1832 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
1833 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
1834 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
1835 "add%-%)%& %R1,%R2,%0"
1836 [(set_attr "type" "fadd")
1837 (set_attr "trap" "yes")])
1840 [(set (match_operand:DF 0 "register_operand" "=f")
1841 (plus:DF (float_extend:DF
1842 (match_operand:SF 1 "reg_or_fp0_operand" "%fG"))
1844 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
1845 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
1846 "add%-%)%& %R1,%R2,%0"
1847 [(set_attr "type" "fadd")
1848 (set_attr "trap" "yes")])
1850 ;; Define conversion operators between DFmode and SImode, using the cvtql
1851 ;; instruction. To allow combine et al to do useful things, we keep the
1852 ;; operation as a unit until after reload, at which point we split the
1855 ;; Note that we (attempt to) only consider this optimization when the
1856 ;; ultimate destination is memory. If we will be doing further integer
1857 ;; processing, it is cheaper to do the truncation in the int regs.
1859 (define_insn "*cvtql"
1860 [(set (match_operand:SI 0 "register_operand" "=f")
1861 (unspec:SI [(match_operand:DI 1 "reg_or_fp0_operand" "fG")] 5))]
1864 [(set_attr "type" "fadd")
1865 (set_attr "trap" "yes")])
1868 [(set (match_operand:SI 0 "memory_operand" "")
1869 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "")) 0))
1870 (clobber (match_scratch:DI 2 ""))
1871 (clobber (match_scratch:SI 3 ""))]
1872 "TARGET_FP && reload_completed"
1873 [(set (match_dup 2) (fix:DI (match_dup 1)))
1874 (set (match_dup 3) (unspec:SI [(match_dup 2)] 5))
1875 (set (match_dup 0) (match_dup 3))]
1879 [(set (match_operand:SI 0 "memory_operand" "")
1880 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "")) 0))
1881 (clobber (match_scratch:DI 2 ""))]
1882 "TARGET_FP && reload_completed"
1883 [(set (match_dup 2) (fix:DI (match_dup 1)))
1884 (set (match_dup 3) (unspec:SI [(match_dup 2)] 5))
1885 (set (match_dup 0) (match_dup 3))]
1886 ;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG.
1887 "operands[3] = gen_rtx_REG (SImode, REGNO (operands[2]));")
1890 [(set (match_operand:SI 0 "memory_operand" "=m")
1891 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")) 0))
1892 (clobber (match_scratch:DI 2 "=&f"))
1893 (clobber (match_scratch:SI 3 "=&f"))]
1894 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
1896 [(set_attr "type" "fadd")
1897 (set_attr "trap" "yes")])
1900 [(set (match_operand:SI 0 "memory_operand" "=m")
1901 (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")) 0))
1902 (clobber (match_scratch:DI 2 "=f"))]
1903 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
1905 [(set_attr "type" "fadd")
1906 (set_attr "trap" "yes")])
1909 [(set (match_operand:DI 0 "register_operand" "=&f")
1910 (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
1911 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
1913 [(set_attr "type" "fadd")
1914 (set_attr "trap" "yes")])
1916 (define_insn "fix_truncdfdi2"
1917 [(set (match_operand:DI 0 "register_operand" "=f")
1918 (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
1921 [(set_attr "type" "fadd")
1922 (set_attr "trap" "yes")])
1924 ;; Likewise between SFmode and SImode.
1927 [(set (match_operand:SI 0 "memory_operand" "")
1928 (subreg:SI (fix:DI (float_extend:DF
1929 (match_operand:SF 1 "reg_or_fp0_operand" ""))) 0))
1930 (clobber (match_scratch:DI 2 ""))
1931 (clobber (match_scratch:SI 3 ""))]
1932 "TARGET_FP && reload_completed"
1933 [(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1))))
1934 (set (match_dup 3) (unspec:SI [(match_dup 2)] 5))
1935 (set (match_dup 0) (match_dup 3))]
1939 [(set (match_operand:SI 0 "memory_operand" "")
1940 (subreg:SI (fix:DI (float_extend:DF
1941 (match_operand:SF 1 "reg_or_fp0_operand" ""))) 0))
1942 (clobber (match_scratch:DI 2 ""))]
1943 "TARGET_FP && reload_completed"
1944 [(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1))))
1945 (set (match_dup 3) (unspec:SI [(match_dup 2)] 5))
1946 (set (match_dup 0) (match_dup 3))]
1947 ;; Due to REG_CANNOT_CHANGE_SIZE issues, we cannot simply use SUBREG.
1948 "operands[3] = gen_rtx_REG (SImode, REGNO (operands[2]));")
1951 [(set (match_operand:SI 0 "memory_operand" "=m")
1952 (subreg:SI (fix:DI (float_extend:DF
1953 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))) 0))
1954 (clobber (match_scratch:DI 2 "=&f"))
1955 (clobber (match_scratch:SI 3 "=&f"))]
1956 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
1958 [(set_attr "type" "fadd")
1959 (set_attr "trap" "yes")])
1962 [(set (match_operand:SI 0 "memory_operand" "=m")
1963 (subreg:SI (fix:DI (float_extend:DF
1964 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))) 0))
1965 (clobber (match_scratch:DI 2 "=f"))]
1966 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
1968 [(set_attr "type" "fadd")
1969 (set_attr "trap" "yes")])
1972 [(set (match_operand:DI 0 "register_operand" "=&f")
1973 (fix:DI (float_extend:DF
1974 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
1975 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
1977 [(set_attr "type" "fadd")
1978 (set_attr "trap" "yes")])
1980 (define_insn "fix_truncsfdi2"
1981 [(set (match_operand:DI 0 "register_operand" "=f")
1982 (fix:DI (float_extend:DF
1983 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
1986 [(set_attr "type" "fadd")
1987 (set_attr "trap" "yes")])
1990 [(set (match_operand:SF 0 "register_operand" "=&f")
1991 (float:SF (match_operand:DI 1 "register_operand" "f")))]
1992 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
1994 [(set_attr "type" "fadd")
1995 (set_attr "trap" "yes")])
1997 (define_insn "floatdisf2"
1998 [(set (match_operand:SF 0 "register_operand" "=f")
1999 (float:SF (match_operand:DI 1 "register_operand" "f")))]
2002 [(set_attr "type" "fadd")
2003 (set_attr "trap" "yes")])
2006 [(set (match_operand:DF 0 "register_operand" "=&f")
2007 (float:DF (match_operand:DI 1 "register_operand" "f")))]
2008 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
2010 [(set_attr "type" "fadd")
2011 (set_attr "trap" "yes")])
2013 (define_insn "floatdidf2"
2014 [(set (match_operand:DF 0 "register_operand" "=f")
2015 (float:DF (match_operand:DI 1 "register_operand" "f")))]
2018 [(set_attr "type" "fadd")
2019 (set_attr "trap" "yes")])
2021 (define_expand "extendsfdf2"
2022 [(use (match_operand:DF 0 "register_operand" ""))
2023 (use (match_operand:SF 1 "nonimmediate_operand" ""))]
2027 if (alpha_tp == ALPHA_TP_INSN)
2028 emit_insn (gen_extendsfdf2_tp (operands[0],
2029 force_reg (SFmode, operands[1])));
2031 emit_insn (gen_extendsfdf2_no_tp (operands[0], operands[1]));
2036 (define_insn "extendsfdf2_tp"
2037 [(set (match_operand:DF 0 "register_operand" "=&f")
2038 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
2039 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
2041 [(set_attr "type" "fadd")
2042 (set_attr "trap" "yes")])
2044 (define_insn "extendsfdf2_no_tp"
2045 [(set (match_operand:DF 0 "register_operand" "=f,f,m")
2046 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m,f")))]
2047 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
2052 [(set_attr "type" "fcpys,fld,fst")
2053 (set_attr "trap" "yes")])
2056 [(set (match_operand:SF 0 "register_operand" "=&f")
2057 (float_truncate:SF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2058 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
2059 "cvt%-%,%)%& %R1,%0"
2060 [(set_attr "type" "fadd")
2061 (set_attr "trap" "yes")])
2063 (define_insn "truncdfsf2"
2064 [(set (match_operand:SF 0 "register_operand" "=f")
2065 (float_truncate:SF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2067 "cvt%-%,%)%& %R1,%0"
2068 [(set_attr "type" "fadd")
2069 (set_attr "trap" "yes")])
2072 [(set (match_operand:SF 0 "register_operand" "=&f")
2073 (div:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2074 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2075 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
2076 "div%,%)%& %R1,%R2,%0"
2077 [(set_attr "type" "fdiv")
2078 (set_attr "opsize" "si")
2079 (set_attr "trap" "yes")])
2081 (define_insn "divsf3"
2082 [(set (match_operand:SF 0 "register_operand" "=f")
2083 (div:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2084 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2086 "div%,%)%& %R1,%R2,%0"
2087 [(set_attr "type" "fdiv")
2088 (set_attr "opsize" "si")
2089 (set_attr "trap" "yes")])
2092 [(set (match_operand:DF 0 "register_operand" "=&f")
2093 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2094 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2095 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
2096 "div%-%)%& %R1,%R2,%0"
2097 [(set_attr "type" "fdiv")
2098 (set_attr "trap" "yes")])
2100 (define_insn "divdf3"
2101 [(set (match_operand:DF 0 "register_operand" "=f")
2102 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2103 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2105 "div%-%)%& %R1,%R2,%0"
2106 [(set_attr "type" "fdiv")
2107 (set_attr "trap" "yes")])
2110 [(set (match_operand:DF 0 "register_operand" "=f")
2111 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2112 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2113 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
2114 "div%-%)%& %R1,%R2,%0"
2115 [(set_attr "type" "fdiv")
2116 (set_attr "trap" "yes")])
2119 [(set (match_operand:DF 0 "register_operand" "=f")
2120 (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2122 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2123 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
2124 "div%-%)%& %R1,%R2,%0"
2125 [(set_attr "type" "fdiv")
2126 (set_attr "trap" "yes")])
2129 [(set (match_operand:DF 0 "register_operand" "=f")
2130 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2131 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2132 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
2133 "div%-%)%& %R1,%R2,%0"
2134 [(set_attr "type" "fdiv")
2135 (set_attr "trap" "yes")])
2138 [(set (match_operand:SF 0 "register_operand" "=&f")
2139 (mult:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
2140 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2141 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
2142 "mul%,%)%& %R1,%R2,%0"
2143 [(set_attr "type" "fmul")
2144 (set_attr "trap" "yes")])
2146 (define_insn "mulsf3"
2147 [(set (match_operand:SF 0 "register_operand" "=f")
2148 (mult:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
2149 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2151 "mul%,%)%& %R1,%R2,%0"
2152 [(set_attr "type" "fmul")
2153 (set_attr "trap" "yes")])
2156 [(set (match_operand:DF 0 "register_operand" "=&f")
2157 (mult:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
2158 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2159 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
2160 "mul%-%)%& %R1,%R2,%0"
2161 [(set_attr "type" "fmul")
2162 (set_attr "trap" "yes")])
2164 (define_insn "muldf3"
2165 [(set (match_operand:DF 0 "register_operand" "=f")
2166 (mult:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
2167 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2169 "mul%-%)%& %R1,%R2,%0"
2170 [(set_attr "type" "fmul")
2171 (set_attr "trap" "yes")])
2174 [(set (match_operand:DF 0 "register_operand" "=f")
2175 (mult:DF (float_extend:DF
2176 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2177 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2178 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
2179 "mul%-%)%& %R1,%R2,%0"
2180 [(set_attr "type" "fmul")
2181 (set_attr "trap" "yes")])
2184 [(set (match_operand:DF 0 "register_operand" "=f")
2185 (mult:DF (float_extend:DF
2186 (match_operand:SF 1 "reg_or_fp0_operand" "%fG"))
2188 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2189 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
2190 "mul%-%)%& %R1,%R2,%0"
2191 [(set_attr "type" "fmul")
2192 (set_attr "trap" "yes")])
2195 [(set (match_operand:SF 0 "register_operand" "=&f")
2196 (minus:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2197 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2198 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
2199 "sub%,%)%& %R1,%R2,%0"
2200 [(set_attr "type" "fadd")
2201 (set_attr "trap" "yes")])
2203 (define_insn "subsf3"
2204 [(set (match_operand:SF 0 "register_operand" "=f")
2205 (minus:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
2206 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
2208 "sub%,%)%& %R1,%R2,%0"
2209 [(set_attr "type" "fadd")
2210 (set_attr "trap" "yes")])
2213 [(set (match_operand:DF 0 "register_operand" "=&f")
2214 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2215 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2216 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
2217 "sub%-%)%& %R1,%R2,%0"
2218 [(set_attr "type" "fadd")
2219 (set_attr "trap" "yes")])
2221 (define_insn "subdf3"
2222 [(set (match_operand:DF 0 "register_operand" "=f")
2223 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2224 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2226 "sub%-%)%& %R1,%R2,%0"
2227 [(set_attr "type" "fadd")
2228 (set_attr "trap" "yes")])
2231 [(set (match_operand:DF 0 "register_operand" "=f")
2232 (minus:DF (float_extend:DF
2233 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2234 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
2235 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
2236 "sub%-%)%& %R1,%R2,%0"
2237 [(set_attr "type" "fadd")
2238 (set_attr "trap" "yes")])
2241 [(set (match_operand:DF 0 "register_operand" "=f")
2242 (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
2244 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2245 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
2246 "sub%-%)%& %R1,%R2,%0"
2247 [(set_attr "type" "fadd")
2248 (set_attr "trap" "yes")])
2251 [(set (match_operand:DF 0 "register_operand" "=f")
2252 (minus:DF (float_extend:DF
2253 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
2255 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
2256 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
2257 "sub%-%)%& %R1,%R2,%0"
2258 [(set_attr "type" "fadd")
2259 (set_attr "trap" "yes")])
2262 [(set (match_operand:SF 0 "register_operand" "=&f")
2263 (sqrt:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
2264 "TARGET_FP && TARGET_CIX && alpha_tp == ALPHA_TP_INSN"
2266 [(set_attr "type" "fsqrt")
2267 (set_attr "opsize" "si")
2268 (set_attr "trap" "yes")])
2270 (define_insn "sqrtsf2"
2271 [(set (match_operand:SF 0 "register_operand" "=f")
2272 (sqrt:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
2273 "TARGET_FP && TARGET_CIX"
2275 [(set_attr "type" "fsqrt")
2276 (set_attr "opsize" "si")
2277 (set_attr "trap" "yes")])
2280 [(set (match_operand:DF 0 "register_operand" "=&f")
2281 (sqrt:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2282 "TARGET_FP && TARGET_CIX && alpha_tp == ALPHA_TP_INSN"
2284 [(set_attr "type" "fsqrt")
2285 (set_attr "trap" "yes")])
2287 (define_insn "sqrtdf2"
2288 [(set (match_operand:DF 0 "register_operand" "=f")
2289 (sqrt:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
2290 "TARGET_FP && TARGET_CIX"
2292 [(set_attr "type" "fsqrt")
2293 (set_attr "trap" "yes")])
2295 ;; Next are all the integer comparisons, and conditional moves and branches
2296 ;; and some of the related define_expand's and define_split's.
2299 [(set (match_operand:DI 0 "register_operand" "=r")
2300 (match_operator:DI 1 "alpha_comparison_operator"
2301 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
2302 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]))]
2305 [(set_attr "type" "icmp")])
2308 [(set (match_operand:DI 0 "register_operand" "=r")
2309 (match_operator:DI 1 "alpha_swapped_comparison_operator"
2310 [(match_operand:DI 2 "reg_or_8bit_operand" "rI")
2311 (match_operand:DI 3 "reg_or_0_operand" "rJ")]))]
2314 [(set_attr "type" "icmp")])
2316 ;; This pattern exists so conditional moves of SImode values are handled.
2317 ;; Comparisons are still done in DImode though.
2320 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
2322 (match_operator 2 "signed_comparison_operator"
2323 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
2324 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
2325 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0,rI,0")
2326 (match_operand:SI 5 "reg_or_8bit_operand" "0,rI,0,rI")))]
2327 "operands[3] == const0_rtx || operands[4] == const0_rtx"
2333 [(set_attr "type" "icmov")])
2336 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
2338 (match_operator 2 "signed_comparison_operator"
2339 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
2340 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
2341 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0,rI,0")
2342 (match_operand:DI 5 "reg_or_8bit_operand" "0,rI,0,rI")))]
2343 "operands[3] == const0_rtx || operands[4] == const0_rtx"
2349 [(set_attr "type" "icmov")])
2352 [(set (match_operand:DI 0 "register_operand" "=r,r")
2354 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2358 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
2359 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
2364 [(set_attr "type" "icmov")])
2367 [(set (match_operand:DI 0 "register_operand" "=r,r")
2369 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
2373 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
2374 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
2379 [(set_attr "type" "icmov")])
2381 ;; For ABS, we have two choices, depending on whether the input and output
2382 ;; registers are the same or not.
2383 (define_expand "absdi2"
2384 [(set (match_operand:DI 0 "register_operand" "")
2385 (abs:DI (match_operand:DI 1 "register_operand" "")))]
2388 { if (rtx_equal_p (operands[0], operands[1]))
2389 emit_insn (gen_absdi2_same (operands[0], gen_reg_rtx (DImode)));
2391 emit_insn (gen_absdi2_diff (operands[0], operands[1]));
2396 (define_expand "absdi2_same"
2397 [(set (match_operand:DI 1 "register_operand" "")
2398 (neg:DI (match_operand:DI 0 "register_operand" "")))
2400 (if_then_else:DI (ge (match_dup 0) (const_int 0))
2406 (define_expand "absdi2_diff"
2407 [(set (match_operand:DI 0 "register_operand" "")
2408 (neg:DI (match_operand:DI 1 "register_operand" "")))
2410 (if_then_else:DI (lt (match_dup 1) (const_int 0))
2417 [(set (match_operand:DI 0 "register_operand" "")
2418 (abs:DI (match_dup 0)))
2419 (clobber (match_operand:DI 2 "register_operand" ""))]
2421 [(set (match_dup 1) (neg:DI (match_dup 0)))
2422 (set (match_dup 0) (if_then_else:DI (ge (match_dup 0) (const_int 0))
2423 (match_dup 0) (match_dup 1)))]
2427 [(set (match_operand:DI 0 "register_operand" "")
2428 (abs:DI (match_operand:DI 1 "register_operand" "")))]
2429 "! rtx_equal_p (operands[0], operands[1])"
2430 [(set (match_dup 0) (neg:DI (match_dup 1)))
2431 (set (match_dup 0) (if_then_else:DI (lt (match_dup 1) (const_int 0))
2432 (match_dup 0) (match_dup 1)))]
2436 [(set (match_operand:DI 0 "register_operand" "")
2437 (neg:DI (abs:DI (match_dup 0))))
2438 (clobber (match_operand:DI 2 "register_operand" ""))]
2440 [(set (match_dup 1) (neg:DI (match_dup 0)))
2441 (set (match_dup 0) (if_then_else:DI (le (match_dup 0) (const_int 0))
2442 (match_dup 0) (match_dup 1)))]
2446 [(set (match_operand:DI 0 "register_operand" "")
2447 (neg:DI (abs:DI (match_operand:DI 1 "register_operand" ""))))]
2448 "! rtx_equal_p (operands[0], operands[1])"
2449 [(set (match_dup 0) (neg:DI (match_dup 1)))
2450 (set (match_dup 0) (if_then_else:DI (gt (match_dup 1) (const_int 0))
2451 (match_dup 0) (match_dup 1)))]
2454 (define_insn "sminqi3"
2455 [(set (match_operand:QI 0 "register_operand" "=r")
2456 (smin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
2457 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
2460 [(set_attr "type" "mvi")])
2462 (define_insn "uminqi3"
2463 [(set (match_operand:QI 0 "register_operand" "=r")
2464 (umin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
2465 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
2468 [(set_attr "type" "mvi")])
2470 (define_insn "smaxqi3"
2471 [(set (match_operand:QI 0 "register_operand" "=r")
2472 (smax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
2473 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
2476 [(set_attr "type" "mvi")])
2478 (define_insn "umaxqi3"
2479 [(set (match_operand:QI 0 "register_operand" "=r")
2480 (umax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
2481 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
2484 [(set_attr "type" "mvi")])
2486 (define_insn "sminhi3"
2487 [(set (match_operand:HI 0 "register_operand" "=r")
2488 (smin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
2489 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
2492 [(set_attr "type" "mvi")])
2494 (define_insn "uminhi3"
2495 [(set (match_operand:HI 0 "register_operand" "=r")
2496 (umin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
2497 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
2500 [(set_attr "type" "mvi")])
2502 (define_insn "smaxhi3"
2503 [(set (match_operand:HI 0 "register_operand" "=r")
2504 (smax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
2505 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
2508 [(set_attr "type" "mvi")])
2510 (define_insn "umaxhi3"
2511 [(set (match_operand:HI 0 "register_operand" "=r")
2512 (umax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
2513 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
2516 [(set_attr "type" "shift")])
2518 (define_expand "smaxdi3"
2520 (le:DI (match_operand:DI 1 "reg_or_0_operand" "")
2521 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2522 (set (match_operand:DI 0 "register_operand" "")
2523 (if_then_else:DI (eq (match_dup 3) (const_int 0))
2524 (match_dup 1) (match_dup 2)))]
2527 { operands[3] = gen_reg_rtx (DImode);
2531 [(set (match_operand:DI 0 "register_operand" "")
2532 (smax:DI (match_operand:DI 1 "reg_or_0_operand" "")
2533 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2534 (clobber (match_operand:DI 3 "register_operand" ""))]
2535 "operands[2] != const0_rtx"
2536 [(set (match_dup 3) (le:DI (match_dup 1) (match_dup 2)))
2537 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
2538 (match_dup 1) (match_dup 2)))]
2542 [(set (match_operand:DI 0 "register_operand" "=r")
2543 (smax:DI (match_operand:DI 1 "register_operand" "0")
2547 [(set_attr "type" "icmov")])
2549 (define_expand "smindi3"
2551 (lt:DI (match_operand:DI 1 "reg_or_0_operand" "")
2552 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2553 (set (match_operand:DI 0 "register_operand" "")
2554 (if_then_else:DI (ne (match_dup 3) (const_int 0))
2555 (match_dup 1) (match_dup 2)))]
2558 { operands[3] = gen_reg_rtx (DImode);
2562 [(set (match_operand:DI 0 "register_operand" "")
2563 (smin:DI (match_operand:DI 1 "reg_or_0_operand" "")
2564 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2565 (clobber (match_operand:DI 3 "register_operand" ""))]
2566 "operands[2] != const0_rtx"
2567 [(set (match_dup 3) (lt:DI (match_dup 1) (match_dup 2)))
2568 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
2569 (match_dup 1) (match_dup 2)))]
2573 [(set (match_operand:DI 0 "register_operand" "=r")
2574 (smin:DI (match_operand:DI 1 "register_operand" "0")
2578 [(set_attr "type" "icmov")])
2580 (define_expand "umaxdi3"
2582 (leu:DI (match_operand:DI 1 "reg_or_0_operand" "")
2583 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2584 (set (match_operand:DI 0 "register_operand" "")
2585 (if_then_else:DI (eq (match_dup 3) (const_int 0))
2586 (match_dup 1) (match_dup 2)))]
2589 { operands[3] = gen_reg_rtx (DImode);
2593 [(set (match_operand:DI 0 "register_operand" "")
2594 (umax:DI (match_operand:DI 1 "reg_or_0_operand" "")
2595 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2596 (clobber (match_operand:DI 3 "register_operand" ""))]
2597 "operands[2] != const0_rtx"
2598 [(set (match_dup 3) (leu:DI (match_dup 1) (match_dup 2)))
2599 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
2600 (match_dup 1) (match_dup 2)))]
2603 (define_expand "umindi3"
2605 (ltu:DI (match_operand:DI 1 "reg_or_0_operand" "")
2606 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2607 (set (match_operand:DI 0 "register_operand" "")
2608 (if_then_else:DI (ne (match_dup 3) (const_int 0))
2609 (match_dup 1) (match_dup 2)))]
2612 { operands[3] = gen_reg_rtx (DImode);
2616 [(set (match_operand:DI 0 "register_operand" "")
2617 (umin:DI (match_operand:DI 1 "reg_or_0_operand" "")
2618 (match_operand:DI 2 "reg_or_8bit_operand" "")))
2619 (clobber (match_operand:DI 3 "register_operand" ""))]
2620 "operands[2] != const0_rtx"
2621 [(set (match_dup 3) (ltu:DI (match_dup 1) (match_dup 2)))
2622 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
2623 (match_dup 1) (match_dup 2)))]
2629 (match_operator 1 "signed_comparison_operator"
2630 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
2632 (label_ref (match_operand 0 "" ""))
2636 [(set_attr "type" "ibr")])
2641 (match_operator 1 "signed_comparison_operator"
2643 (match_operand:DI 2 "register_operand" "r")])
2644 (label_ref (match_operand 0 "" ""))
2648 [(set_attr "type" "ibr")])
2653 (ne (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
2657 (label_ref (match_operand 0 "" ""))
2661 [(set_attr "type" "ibr")])
2666 (eq (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
2670 (label_ref (match_operand 0 "" ""))
2674 [(set_attr "type" "ibr")])
2680 (match_operator 1 "comparison_operator"
2681 [(zero_extract:DI (match_operand:DI 2 "register_operand" "")
2683 (match_operand:DI 3 "const_int_operand" ""))
2685 (label_ref (match_operand 0 "" ""))
2687 (clobber (match_operand:DI 4 "register_operand" ""))])]
2688 "INTVAL (operands[3]) != 0"
2690 (lshiftrt:DI (match_dup 2) (match_dup 3)))
2692 (if_then_else (match_op_dup 1
2693 [(zero_extract:DI (match_dup 4)
2697 (label_ref (match_dup 0))
2701 ;; The following are the corresponding floating-point insns. Recall
2702 ;; we need to have variants that expand the arguments from SF mode
2706 [(set (match_operand:DF 0 "register_operand" "=&f")
2707 (match_operator:DF 1 "alpha_comparison_operator"
2708 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
2709 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
2710 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
2711 "cmp%-%C1%' %R2,%R3,%0"
2712 [(set_attr "type" "fadd")
2713 (set_attr "trap" "yes")])
2716 [(set (match_operand:DF 0 "register_operand" "=f")
2717 (match_operator:DF 1 "alpha_comparison_operator"
2718 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
2719 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
2720 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
2721 "cmp%-%C1%' %R2,%R3,%0"
2722 [(set_attr "type" "fadd")
2723 (set_attr "trap" "yes")])
2726 [(set (match_operand:DF 0 "register_operand" "=&f")
2727 (match_operator:DF 1 "alpha_comparison_operator"
2729 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
2730 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
2731 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
2732 "cmp%-%C1%' %R2,%R3,%0"
2733 [(set_attr "type" "fadd")
2734 (set_attr "trap" "yes")])
2737 [(set (match_operand:DF 0 "register_operand" "=f")
2738 (match_operator:DF 1 "alpha_comparison_operator"
2740 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
2741 (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
2742 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
2743 "cmp%-%C1%' %R2,%R3,%0"
2744 [(set_attr "type" "fadd")
2745 (set_attr "trap" "yes")])
2748 [(set (match_operand:DF 0 "register_operand" "=&f")
2749 (match_operator:DF 1 "alpha_comparison_operator"
2750 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
2752 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
2753 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
2754 "cmp%-%C1%' %R2,%R3,%0"
2755 [(set_attr "type" "fadd")
2756 (set_attr "trap" "yes")])
2759 [(set (match_operand:DF 0 "register_operand" "=f")
2760 (match_operator:DF 1 "alpha_comparison_operator"
2761 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
2763 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
2764 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
2765 "cmp%-%C1%' %R2,%R3,%0"
2766 [(set_attr "type" "fadd")
2767 (set_attr "trap" "yes")])
2770 [(set (match_operand:DF 0 "register_operand" "=&f")
2771 (match_operator:DF 1 "alpha_comparison_operator"
2773 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
2775 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
2776 "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
2777 "cmp%-%C1%' %R2,%R3,%0"
2778 [(set_attr "type" "fadd")
2779 (set_attr "trap" "yes")])
2782 [(set (match_operand:DF 0 "register_operand" "=f")
2783 (match_operator:DF 1 "alpha_comparison_operator"
2785 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
2787 (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
2788 "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
2789 "cmp%-%C1%' %R2,%R3,%0"
2790 [(set_attr "type" "fadd")
2791 (set_attr "trap" "yes")])
2794 [(set (match_operand:DF 0 "register_operand" "=f,f")
2796 (match_operator 3 "signed_comparison_operator"
2797 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
2798 (match_operand:DF 2 "fp0_operand" "G,G")])
2799 (match_operand:DF 1 "reg_or_fp0_operand" "fG,0")
2800 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
2804 fcmov%D3 %R4,%R5,%0"
2805 [(set_attr "type" "fcmov")])
2808 [(set (match_operand:SF 0 "register_operand" "=f,f")
2810 (match_operator 3 "signed_comparison_operator"
2811 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
2812 (match_operand:DF 2 "fp0_operand" "G,G")])
2813 (match_operand:SF 1 "reg_or_fp0_operand" "fG,0")
2814 (match_operand:SF 5 "reg_or_fp0_operand" "0,fG")))]
2818 fcmov%D3 %R4,%R5,%0"
2819 [(set_attr "type" "fcmov")])
2822 [(set (match_operand:DF 0 "register_operand" "=f,f")
2824 (match_operator 3 "signed_comparison_operator"
2825 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
2826 (match_operand:DF 2 "fp0_operand" "G,G")])
2827 (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG,0"))
2828 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
2832 fcmov%D3 %R4,%R5,%0"
2833 [(set_attr "type" "fcmov")])
2836 [(set (match_operand:DF 0 "register_operand" "=f,f")
2838 (match_operator 3 "signed_comparison_operator"
2840 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
2841 (match_operand:DF 2 "fp0_operand" "G,G")])
2842 (match_operand:DF 1 "reg_or_fp0_operand" "fG,0")
2843 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
2847 fcmov%D3 %R4,%R5,%0"
2848 [(set_attr "type" "fcmov")])
2851 [(set (match_operand:SF 0 "register_operand" "=f,f")
2853 (match_operator 3 "signed_comparison_operator"
2855 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
2856 (match_operand:DF 2 "fp0_operand" "G,G")])
2857 (match_operand:SF 1 "reg_or_fp0_operand" "fG,0")
2858 (match_operand:SF 5 "reg_or_fp0_operand" "0,fG")))]
2862 fcmov%D3 %R4,%R5,%0"
2863 [(set_attr "type" "fcmov")])
2866 [(set (match_operand:DF 0 "register_operand" "=f,f")
2868 (match_operator 3 "signed_comparison_operator"
2870 (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG"))
2871 (match_operand:DF 2 "fp0_operand" "G,G")])
2872 (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG,0"))
2873 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
2877 fcmov%D3 %R4,%R5,%0"
2878 [(set_attr "type" "fcmov")])
2880 (define_expand "maxdf3"
2882 (le:DF (match_operand:DF 1 "reg_or_fp0_operand" "")
2883 (match_operand:DF 2 "reg_or_fp0_operand" "")))
2884 (set (match_operand:DF 0 "register_operand" "")
2885 (if_then_else:DF (eq (match_dup 3) (match_dup 4))
2886 (match_dup 1) (match_dup 2)))]
2889 { operands[3] = gen_reg_rtx (DFmode);
2890 operands[4] = CONST0_RTX (DFmode);
2893 (define_expand "mindf3"
2895 (lt:DF (match_operand:DF 1 "reg_or_fp0_operand" "")
2896 (match_operand:DF 2 "reg_or_fp0_operand" "")))
2897 (set (match_operand:DF 0 "register_operand" "")
2898 (if_then_else:DF (ne (match_dup 3) (match_dup 4))
2899 (match_dup 1) (match_dup 2)))]
2902 { operands[3] = gen_reg_rtx (DFmode);
2903 operands[4] = CONST0_RTX (DFmode);
2906 (define_expand "maxsf3"
2908 (le:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" ""))
2909 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" ""))))
2910 (set (match_operand:SF 0 "register_operand" "")
2911 (if_then_else:SF (eq (match_dup 3) (match_dup 4))
2912 (match_dup 1) (match_dup 2)))]
2915 { operands[3] = gen_reg_rtx (DFmode);
2916 operands[4] = CONST0_RTX (DFmode);
2919 (define_expand "minsf3"
2921 (lt:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" ""))
2922 (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" ""))))
2923 (set (match_operand:SF 0 "register_operand" "")
2924 (if_then_else:SF (ne (match_dup 3) (match_dup 4))
2925 (match_dup 1) (match_dup 2)))]
2928 { operands[3] = gen_reg_rtx (DFmode);
2929 operands[4] = CONST0_RTX (DFmode);
2935 (match_operator 1 "signed_comparison_operator"
2936 [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
2937 (match_operand:DF 3 "fp0_operand" "G")])
2938 (label_ref (match_operand 0 "" ""))
2942 [(set_attr "type" "fbr")])
2947 (match_operator 1 "signed_comparison_operator"
2949 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
2950 (match_operand:DF 3 "fp0_operand" "G")])
2951 (label_ref (match_operand 0 "" ""))
2955 [(set_attr "type" "fbr")])
2957 ;; These are the main define_expand's used to make conditional branches
2960 (define_expand "cmpdf"
2961 [(set (cc0) (compare (match_operand:DF 0 "reg_or_fp0_operand" "")
2962 (match_operand:DF 1 "reg_or_fp0_operand" "")))]
2966 alpha_compare_op0 = operands[0];
2967 alpha_compare_op1 = operands[1];
2968 alpha_compare_fp_p = 1;
2972 (define_expand "cmpdi"
2973 [(set (cc0) (compare (match_operand:DI 0 "reg_or_0_operand" "")
2974 (match_operand:DI 1 "reg_or_8bit_operand" "")))]
2978 alpha_compare_op0 = operands[0];
2979 alpha_compare_op1 = operands[1];
2980 alpha_compare_fp_p = 0;
2984 (define_expand "beq"
2986 (if_then_else (match_dup 1)
2987 (label_ref (match_operand 0 "" ""))
2990 "{ operands[1] = alpha_emit_conditional_branch (EQ); }")
2992 (define_expand "bne"
2994 (if_then_else (match_dup 1)
2995 (label_ref (match_operand 0 "" ""))
2998 "{ operands[1] = alpha_emit_conditional_branch (NE); }")
3000 (define_expand "blt"
3002 (if_then_else (match_dup 1)
3003 (label_ref (match_operand 0 "" ""))
3006 "{ operands[1] = alpha_emit_conditional_branch (LT); }")
3008 (define_expand "ble"
3010 (if_then_else (match_dup 1)
3011 (label_ref (match_operand 0 "" ""))
3014 "{ operands[1] = alpha_emit_conditional_branch (LE); }")
3016 (define_expand "bgt"
3018 (if_then_else (match_dup 1)
3019 (label_ref (match_operand 0 "" ""))
3022 "{ operands[1] = alpha_emit_conditional_branch (GT); }")
3024 (define_expand "bge"
3026 (if_then_else (match_dup 1)
3027 (label_ref (match_operand 0 "" ""))
3030 "{ operands[1] = alpha_emit_conditional_branch (GE); }")
3032 (define_expand "bltu"
3034 (if_then_else (match_dup 1)
3035 (label_ref (match_operand 0 "" ""))
3038 "{ operands[1] = alpha_emit_conditional_branch (LTU); }")
3040 (define_expand "bleu"
3042 (if_then_else (match_dup 1)
3043 (label_ref (match_operand 0 "" ""))
3046 "{ operands[1] = alpha_emit_conditional_branch (LEU); }")
3048 (define_expand "bgtu"
3050 (if_then_else (match_dup 1)
3051 (label_ref (match_operand 0 "" ""))
3054 "{ operands[1] = alpha_emit_conditional_branch (GTU); }")
3056 (define_expand "bgeu"
3058 (if_then_else (match_dup 1)
3059 (label_ref (match_operand 0 "" ""))
3062 "{ operands[1] = alpha_emit_conditional_branch (GEU); }")
3064 (define_expand "seq"
3065 [(set (match_operand:DI 0 "register_operand" "")
3070 if (alpha_compare_fp_p)
3073 operands[1] = gen_rtx_EQ (DImode, alpha_compare_op0, alpha_compare_op1);
3076 (define_expand "sne"
3077 [(set (match_operand:DI 0 "register_operand" "")
3079 (set (match_dup 0) (xor:DI (match_dup 0) (const_int 1)))]
3083 if (alpha_compare_fp_p)
3086 operands[1] = gen_rtx_EQ (DImode, alpha_compare_op0, alpha_compare_op1);
3089 (define_expand "slt"
3090 [(set (match_operand:DI 0 "register_operand" "")
3095 if (alpha_compare_fp_p)
3098 operands[1] = gen_rtx_LT (DImode, alpha_compare_op0, alpha_compare_op1);
3101 (define_expand "sle"
3102 [(set (match_operand:DI 0 "register_operand" "")
3107 if (alpha_compare_fp_p)
3110 operands[1] = gen_rtx_LE (DImode, alpha_compare_op0, alpha_compare_op1);
3113 (define_expand "sgt"
3114 [(set (match_operand:DI 0 "register_operand" "")
3119 if (alpha_compare_fp_p)
3122 operands[1] = gen_rtx_LT (DImode, force_reg (DImode, alpha_compare_op1),
3126 (define_expand "sge"
3127 [(set (match_operand:DI 0 "register_operand" "")
3132 if (alpha_compare_fp_p)
3135 operands[1] = gen_rtx_LE (DImode, force_reg (DImode, alpha_compare_op1),
3139 (define_expand "sltu"
3140 [(set (match_operand:DI 0 "register_operand" "")
3145 if (alpha_compare_fp_p)
3148 operands[1] = gen_rtx_LTU (DImode, alpha_compare_op0, alpha_compare_op1);
3151 (define_expand "sleu"
3152 [(set (match_operand:DI 0 "register_operand" "")
3157 if (alpha_compare_fp_p)
3160 operands[1] = gen_rtx_LEU (DImode, alpha_compare_op0, alpha_compare_op1);
3163 (define_expand "sgtu"
3164 [(set (match_operand:DI 0 "register_operand" "")
3169 if (alpha_compare_fp_p)
3172 operands[1] = gen_rtx_LTU (DImode, force_reg (DImode, alpha_compare_op1),
3176 (define_expand "sgeu"
3177 [(set (match_operand:DI 0 "register_operand" "")
3182 if (alpha_compare_fp_p)
3185 operands[1] = gen_rtx_LEU (DImode, force_reg (DImode, alpha_compare_op1),
3189 ;; These are the main define_expand's used to make conditional moves.
3191 (define_expand "movsicc"
3192 [(set (match_operand:SI 0 "register_operand" "")
3193 (if_then_else:SI (match_operand 1 "comparison_operator" "")
3194 (match_operand:SI 2 "reg_or_8bit_operand" "")
3195 (match_operand:SI 3 "reg_or_8bit_operand" "")))]
3199 if ((operands[1] = alpha_emit_conditional_move (operands[1], SImode)) == 0)
3203 (define_expand "movdicc"
3204 [(set (match_operand:DI 0 "register_operand" "")
3205 (if_then_else:DI (match_operand 1 "comparison_operator" "")
3206 (match_operand:DI 2 "reg_or_8bit_operand" "")
3207 (match_operand:DI 3 "reg_or_8bit_operand" "")))]
3211 if ((operands[1] = alpha_emit_conditional_move (operands[1], DImode)) == 0)
3215 (define_expand "movsfcc"
3216 [(set (match_operand:SF 0 "register_operand" "")
3217 (if_then_else:SF (match_operand 1 "comparison_operator" "")
3218 (match_operand:SF 2 "reg_or_8bit_operand" "")
3219 (match_operand:SF 3 "reg_or_8bit_operand" "")))]
3223 if ((operands[1] = alpha_emit_conditional_move (operands[1], SFmode)) == 0)
3227 (define_expand "movdfcc"
3228 [(set (match_operand:DF 0 "register_operand" "")
3229 (if_then_else:DF (match_operand 1 "comparison_operator" "")
3230 (match_operand:DF 2 "reg_or_8bit_operand" "")
3231 (match_operand:DF 3 "reg_or_8bit_operand" "")))]
3235 if ((operands[1] = alpha_emit_conditional_move (operands[1], DFmode)) == 0)
3239 ;; These define_split definitions are used in cases when comparisons have
3240 ;; not be stated in the correct way and we need to reverse the second
3241 ;; comparison. For example, x >= 7 has to be done as x < 6 with the
3242 ;; comparison that tests the result being reversed. We have one define_split
3243 ;; for each use of a comparison. They do not match valid insns and need
3244 ;; not generate valid insns.
3246 ;; We can also handle equality comparisons (and inequality comparisons in
3247 ;; cases where the resulting add cannot overflow) by doing an add followed by
3248 ;; a comparison with zero. This is faster since the addition takes one
3249 ;; less cycle than a compare when feeding into a conditional move.
3250 ;; For this case, we also have an SImode pattern since we can merge the add
3251 ;; and sign extend and the order doesn't matter.
3253 ;; We do not do this for floating-point, since it isn't clear how the "wrong"
3254 ;; operation could have been generated.
3257 [(set (match_operand:DI 0 "register_operand" "")
3259 (match_operator 1 "comparison_operator"
3260 [(match_operand:DI 2 "reg_or_0_operand" "")
3261 (match_operand:DI 3 "reg_or_cint_operand" "")])
3262 (match_operand:DI 4 "reg_or_cint_operand" "")
3263 (match_operand:DI 5 "reg_or_cint_operand" "")))
3264 (clobber (match_operand:DI 6 "register_operand" ""))]
3265 "operands[3] != const0_rtx"
3266 [(set (match_dup 6) (match_dup 7))
3268 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
3270 { enum rtx_code code = GET_CODE (operands[1]);
3271 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
3273 /* If we are comparing for equality with a constant and that constant
3274 appears in the arm when the register equals the constant, use the
3275 register since that is more likely to match (and to produce better code
3278 if (code == EQ && GET_CODE (operands[3]) == CONST_INT
3279 && rtx_equal_p (operands[4], operands[3]))
3280 operands[4] = operands[2];
3282 else if (code == NE && GET_CODE (operands[3]) == CONST_INT
3283 && rtx_equal_p (operands[5], operands[3]))
3284 operands[5] = operands[2];
3286 if (code == NE || code == EQ
3287 || (extended_count (operands[2], DImode, unsignedp) >= 1
3288 && extended_count (operands[3], DImode, unsignedp) >= 1))
3290 if (GET_CODE (operands[3]) == CONST_INT)
3291 operands[7] = gen_rtx_PLUS (DImode, operands[2],
3292 GEN_INT (- INTVAL (operands[3])));
3294 operands[7] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
3296 operands[8] = gen_rtx_fmt_ee (code, VOIDmode, operands[6], const0_rtx);
3299 else if (code == EQ || code == LE || code == LT
3300 || code == LEU || code == LTU)
3302 operands[7] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
3303 operands[8] = gen_rtx_NE (VOIDmode, operands[6], const0_rtx);
3307 operands[7] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
3308 operands[2], operands[3]);
3309 operands[8] = gen_rtx_EQ (VOIDmode, operands[6], const0_rtx);
3314 [(set (match_operand:DI 0 "register_operand" "")
3316 (match_operator 1 "comparison_operator"
3317 [(match_operand:SI 2 "reg_or_0_operand" "")
3318 (match_operand:SI 3 "reg_or_cint_operand" "")])
3319 (match_operand:DI 4 "reg_or_8bit_operand" "")
3320 (match_operand:DI 5 "reg_or_8bit_operand" "")))
3321 (clobber (match_operand:DI 6 "register_operand" ""))]
3322 "operands[3] != const0_rtx
3323 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
3324 [(set (match_dup 6) (match_dup 7))
3326 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
3328 { enum rtx_code code = GET_CODE (operands[1]);
3329 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
3332 if ((code != NE && code != EQ
3333 && ! (extended_count (operands[2], DImode, unsignedp) >= 1
3334 && extended_count (operands[3], DImode, unsignedp) >= 1)))
3337 if (GET_CODE (operands[3]) == CONST_INT)
3338 tem = gen_rtx_PLUS (SImode, operands[2],
3339 GEN_INT (- INTVAL (operands[3])));
3341 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
3343 operands[7] = gen_rtx_SIGN_EXTEND (DImode, tem);
3344 operands[8] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
3345 operands[6], const0_rtx);
3351 (match_operator 1 "comparison_operator"
3352 [(match_operand:DI 2 "reg_or_0_operand" "")
3353 (match_operand:DI 3 "reg_or_cint_operand" "")])
3354 (label_ref (match_operand 0 "" ""))
3356 (clobber (match_operand:DI 4 "register_operand" ""))]
3357 "operands[3] != const0_rtx"
3358 [(set (match_dup 4) (match_dup 5))
3359 (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))]
3361 { enum rtx_code code = GET_CODE (operands[1]);
3362 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
3364 if (code == NE || code == EQ
3365 || (extended_count (operands[2], DImode, unsignedp) >= 1
3366 && extended_count (operands[3], DImode, unsignedp) >= 1))
3368 if (GET_CODE (operands[3]) == CONST_INT)
3369 operands[5] = gen_rtx_PLUS (DImode, operands[2],
3370 GEN_INT (- INTVAL (operands[3])));
3372 operands[5] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
3374 operands[6] = gen_rtx_fmt_ee (code, VOIDmode, operands[4], const0_rtx);
3377 else if (code == EQ || code == LE || code == LT
3378 || code == LEU || code == LTU)
3380 operands[5] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
3381 operands[6] = gen_rtx_NE (VOIDmode, operands[4], const0_rtx);
3385 operands[5] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
3386 operands[2], operands[3]);
3387 operands[6] = gen_rtx_EQ (VOIDmode, operands[4], const0_rtx);
3394 (match_operator 1 "comparison_operator"
3395 [(match_operand:SI 2 "reg_or_0_operand" "")
3396 (match_operand:SI 3 "const_int_operand" "")])
3397 (label_ref (match_operand 0 "" ""))
3399 (clobber (match_operand:DI 4 "register_operand" ""))]
3400 "operands[3] != const0_rtx
3401 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
3402 [(set (match_dup 4) (match_dup 5))
3403 (set (pc) (if_then_else (match_dup 6) (label_ref (match_dup 0)) (pc)))]
3407 if (GET_CODE (operands[3]) == CONST_INT)
3408 tem = gen_rtx_PLUS (SImode, operands[2],
3409 GEN_INT (- INTVAL (operands[3])));
3411 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
3413 operands[5] = gen_rtx_SIGN_EXTEND (DImode, tem);
3414 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
3415 operands[4], const0_rtx);
3418 ;; We can convert such things as "a > 0xffff" to "t = a & ~ 0xffff; t != 0".
3419 ;; This eliminates one, and sometimes two, insns when the AND can be done
3422 [(set (match_operand:DI 0 "register_operand" "")
3423 (match_operator 1 "comparison_operator"
3424 [(match_operand:DI 2 "register_operand" "")
3425 (match_operand:DI 3 "const_int_operand" "")]))
3426 (clobber (match_operand:DI 4 "register_operand" ""))]
3427 "exact_log2 (INTVAL (operands[3]) + 1) >= 0
3428 && (GET_CODE (operands[1]) == GTU
3429 || GET_CODE (operands[1]) == LEU
3430 || ((GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == LE)
3431 && extended_count (operands[2], DImode, 1) > 0))"
3432 [(set (match_dup 4) (and:DI (match_dup 2) (match_dup 5)))
3433 (set (match_dup 0) (match_dup 6))]
3436 operands[5] = GEN_INT (~ INTVAL (operands[3]));
3437 operands[6] = gen_rtx_fmt_ee (((GET_CODE (operands[1]) == GTU
3438 || GET_CODE (operands[1]) == GT)
3440 DImode, operands[4], const0_rtx);
3443 ;; Here are the CALL and unconditional branch insns. Calls on NT and OSF
3444 ;; work differently, so we have different patterns for each.
3446 (define_expand "call"
3447 [(use (match_operand:DI 0 "" ""))
3448 (use (match_operand 1 "" ""))
3449 (use (match_operand 2 "" ""))
3450 (use (match_operand 3 "" ""))]
3453 { if (TARGET_WINDOWS_NT)
3454 emit_call_insn (gen_call_nt (operands[0], operands[1]));
3455 else if (TARGET_OPEN_VMS)
3456 emit_call_insn (gen_call_vms (operands[0], operands[2]));
3458 emit_call_insn (gen_call_osf (operands[0], operands[1]));
3463 (define_expand "call_osf"
3464 [(parallel [(call (mem:DI (match_operand 0 "" ""))
3465 (match_operand 1 "" ""))
3466 (clobber (reg:DI 27))
3467 (clobber (reg:DI 26))])]
3470 { if (GET_CODE (operands[0]) != MEM)
3473 operands[0] = XEXP (operands[0], 0);
3475 if (GET_CODE (operands[0]) != SYMBOL_REF
3476 && ! (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 27))
3478 rtx tem = gen_rtx_REG (DImode, 27);
3479 emit_move_insn (tem, operands[0]);
3484 (define_expand "call_nt"
3485 [(parallel [(call (mem:DI (match_operand 0 "" ""))
3486 (match_operand 1 "" ""))
3487 (clobber (reg:DI 26))])]
3490 { if (GET_CODE (operands[0]) != MEM)
3493 operands[0] = XEXP (operands[0], 0);
3494 if (GET_CODE (operands[0]) != SYMBOL_REF && GET_CODE (operands[0]) != REG)
3495 operands[0] = force_reg (DImode, operands[0]);
3499 ;; call openvms/alpha
3500 ;; op 0: symbol ref for called function
3501 ;; op 1: next_arg_reg (argument information value for R25)
3503 (define_expand "call_vms"
3504 [(parallel [(call (mem:DI (match_operand 0 "" ""))
3505 (match_operand 1 "" ""))
3509 (clobber (reg:DI 27))])]
3512 { if (GET_CODE (operands[0]) != MEM)
3515 operands[0] = XEXP (operands[0], 0);
3517 /* Always load AI with argument information, then handle symbolic and
3518 indirect call differently. Load RA and set operands[2] to PV in
3521 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
3522 if (GET_CODE (operands[0]) == SYMBOL_REF)
3524 extern char *savealloc ();
3525 char *linksym, *symbol = XSTR (operands[0], 0);
3530 linksym = savealloc (strlen (symbol) + 6);
3532 alpha_need_linkage (symbol, 0);
3535 strcpy (linksym+1, symbol);
3536 strcat (linksym, \"..lk\");
3537 linkage = gen_rtx_SYMBOL_REF (Pmode, linksym);
3539 emit_move_insn (gen_rtx_REG (Pmode, 26), gen_rtx_MEM (Pmode, linkage));
3542 = validize_mem (gen_rtx_MEM (Pmode, plus_constant (linkage, 8)));
3546 emit_move_insn (gen_rtx_REG (Pmode, 26),
3547 gen_rtx_MEM (Pmode, plus_constant (operands[0], 8)));
3549 operands[2] = operands[0];
3554 (define_expand "call_value"
3555 [(use (match_operand 0 "" ""))
3556 (use (match_operand:DI 1 "" ""))
3557 (use (match_operand 2 "" ""))
3558 (use (match_operand 3 "" ""))
3559 (use (match_operand 4 "" ""))]
3562 { if (TARGET_WINDOWS_NT)
3563 emit_call_insn (gen_call_value_nt (operands[0], operands[1], operands[2]));
3564 else if (TARGET_OPEN_VMS)
3565 emit_call_insn (gen_call_value_vms (operands[0], operands[1],
3568 emit_call_insn (gen_call_value_osf (operands[0], operands[1],
3573 (define_expand "call_value_osf"
3574 [(parallel [(set (match_operand 0 "" "")
3575 (call (mem:DI (match_operand 1 "" ""))
3576 (match_operand 2 "" "")))
3577 (clobber (reg:DI 27))
3578 (clobber (reg:DI 26))])]
3581 { if (GET_CODE (operands[1]) != MEM)
3584 operands[1] = XEXP (operands[1], 0);
3586 if (GET_CODE (operands[1]) != SYMBOL_REF
3587 && ! (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 27))
3589 rtx tem = gen_rtx_REG (DImode, 27);
3590 emit_move_insn (tem, operands[1]);
3595 (define_expand "call_value_nt"
3596 [(parallel [(set (match_operand 0 "" "")
3597 (call (mem:DI (match_operand 1 "" ""))
3598 (match_operand 2 "" "")))
3599 (clobber (reg:DI 26))])]
3602 { if (GET_CODE (operands[1]) != MEM)
3605 operands[1] = XEXP (operands[1], 0);
3606 if (GET_CODE (operands[0]) != SYMBOL_REF && GET_CODE (operands[0]) != REG)
3607 operands[1] = force_reg (DImode, operands[1]);
3610 (define_expand "call_value_vms"
3611 [(parallel [(set (match_operand 0 "" "")
3612 (call (mem:DI (match_operand:DI 1 "" ""))
3613 (match_operand 2 "" "")))
3617 (clobber (reg:DI 27))])]
3620 { if (GET_CODE (operands[1]) != MEM)
3623 operands[1] = XEXP (operands[1], 0);
3625 /* Always load AI with argument information, then handle symbolic and
3626 indirect call differently. Load RA and set operands[3] to PV in
3629 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
3630 if (GET_CODE (operands[1]) == SYMBOL_REF)
3632 extern char *savealloc ();
3633 char *linksym, *symbol = XSTR (operands[1], 0);
3638 linksym = savealloc (strlen (symbol) + 6);
3640 alpha_need_linkage (symbol, 0);
3642 strcpy (linksym+1, symbol);
3643 strcat (linksym, \"..lk\");
3644 linkage = gen_rtx_SYMBOL_REF (Pmode, linksym);
3646 emit_move_insn (gen_rtx_REG (Pmode, 26), gen_rtx_MEM (Pmode, linkage));
3649 = validize_mem (gen_rtx_MEM (Pmode, plus_constant (linkage, 8)));
3653 emit_move_insn (gen_rtx_REG (Pmode, 26),
3654 gen_rtx_MEM (Pmode, plus_constant (operands[1], 8)));
3656 operands[3] = operands[1];
3661 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,R,i"))
3662 (match_operand 1 "" ""))
3663 (clobber (reg:DI 27))
3664 (clobber (reg:DI 26))]
3665 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS"
3667 jsr $26,($27),0\;ldgp $29,0($26)
3669 jsr $26,%0\;ldgp $29,0($26)"
3670 [(set_attr "type" "jsr")
3671 (set_attr "length" "12,*,16")])
3674 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,R,i"))
3675 (match_operand 1 "" ""))
3676 (clobber (reg:DI 26))]
3682 [(set_attr "type" "jsr")
3683 (set_attr "length" "*,*,12")])
3686 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,i"))
3687 (match_operand 1 "" ""))
3688 (use (match_operand:DI 2 "general_operand" "r,m"))
3691 (clobber (reg:DI 27))]
3694 mov %2,$27\;jsr $26,0\;ldq $27,0($29)
3695 ldq $27,%2\;jsr $26,%0\;ldq $27,0($29)"
3696 [(set_attr "type" "jsr")
3697 (set_attr "length" "12,16")])
3700 [(set (match_operand 0 "register_operand" "=rf,rf,rf")
3701 (call (mem:DI (match_operand:DI 1 "call_operand" "r,R,i"))
3702 (match_operand 2 "" "")))
3703 (clobber (reg:DI 27))
3704 (clobber (reg:DI 26))]
3705 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS"
3707 jsr $26,($27),0\;ldgp $29,0($26)
3709 jsr $26,%1\;ldgp $29,0($26)"
3710 [(set_attr "type" "jsr")
3711 (set_attr "length" "12,*,16")])
3714 [(set (match_operand 0 "register_operand" "=rf,rf,rf")
3715 (call (mem:DI (match_operand:DI 1 "call_operand" "r,R,i"))
3716 (match_operand 2 "" "")))
3717 (clobber (reg:DI 26))]
3723 [(set_attr "type" "jsr")
3724 (set_attr "length" "*,*,12")])
3727 [(set (match_operand 0 "register_operand" "")
3728 (call (mem:DI (match_operand:DI 1 "call_operand" "r,i"))
3729 (match_operand 2 "" "")))
3730 (use (match_operand:DI 3 "general_operand" "r,m"))
3733 (clobber (reg:DI 27))]
3736 mov %3,$27\;jsr $26,0\;ldq $27,0($29)
3737 ldq $27,%3\;jsr $26,%1\;ldq $27,0($29)"
3738 [(set_attr "type" "jsr")
3739 (set_attr "length" "12,16")])
3741 ;; Call subroutine returning any type.
3743 (define_expand "untyped_call"
3744 [(parallel [(call (match_operand 0 "" "")
3746 (match_operand 1 "" "")
3747 (match_operand 2 "" "")])]
3753 emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
3755 for (i = 0; i < XVECLEN (operands[2], 0); i++)
3757 rtx set = XVECEXP (operands[2], 0, i);
3758 emit_move_insn (SET_DEST (set), SET_SRC (set));
3761 /* The optimizer does not know that the call sets the function value
3762 registers we stored in the result block. We avoid problems by
3763 claiming that all hard registers are used and clobbered at this
3765 emit_insn (gen_blockage ());
3770 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
3771 ;; all of memory. This blocks insns from being moved across this point.
3773 (define_insn "blockage"
3774 [(unspec_volatile [(const_int 0)] 1)]
3777 [(set_attr "length" "0")])
3781 (label_ref (match_operand 0 "" "")))]
3784 [(set_attr "type" "ibr")])
3786 (define_insn "return"
3790 [(set_attr "type" "ibr")])
3792 ;; Use a different pattern for functions which have non-trivial
3793 ;; epilogues so as not to confuse jump and reorg.
3794 (define_insn "return_internal"
3799 [(set_attr "type" "ibr")])
3801 (define_insn "indirect_jump"
3802 [(set (pc) (match_operand:DI 0 "register_operand" "r"))]
3805 [(set_attr "type" "ibr")])
3807 (define_expand "tablejump"
3808 [(use (match_operand:SI 0 "register_operand" ""))
3809 (use (match_operand:SI 1 "" ""))]
3813 if (TARGET_WINDOWS_NT)
3814 emit_jump_insn (gen_tablejump_nt (operands[0], operands[1]));
3815 else if (TARGET_OPEN_VMS)
3816 emit_jump_insn (gen_tablejump_vms (operands[0], operands[1]));
3818 emit_jump_insn (gen_tablejump_osf (operands[0], operands[1]));
3823 (define_expand "tablejump_osf"
3825 (sign_extend:DI (match_operand:SI 0 "register_operand" "")))
3826 (parallel [(set (pc)
3827 (plus:DI (match_dup 3)
3828 (label_ref:DI (match_operand 1 "" ""))))
3829 (clobber (match_scratch:DI 2 "=r"))])]
3832 { operands[3] = gen_reg_rtx (DImode); }")
3834 (define_expand "tablejump_nt"
3836 (sign_extend:DI (match_operand:SI 0 "register_operand" "")))
3837 (parallel [(set (pc)
3839 (use (label_ref (match_operand 1 "" "")))])]
3842 { operands[3] = gen_reg_rtx (DImode); }")
3845 ;; tablejump, openVMS way
3847 ;; op 1: label preceding jump-table
3849 (define_expand "tablejump_vms"
3851 (match_operand:DI 0 "register_operand" ""))
3853 (plus:DI (match_dup 2)
3854 (label_ref:DI (match_operand 1 "" ""))))]
3857 { operands[2] = gen_reg_rtx (DImode); }")
3861 (plus:DI (match_operand:DI 0 "register_operand" "r")
3862 (label_ref:DI (match_operand 1 "" ""))))
3863 (clobber (match_scratch:DI 2 "=r"))]
3864 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS && next_active_insn (insn) != 0
3865 && GET_CODE (PATTERN (next_active_insn (insn))) == ADDR_DIFF_VEC
3866 && PREV_INSN (next_active_insn (insn)) == operands[1]"
3868 { rtx best_label = 0;
3869 rtx jump_table_insn = next_active_insn (operands[1]);
3871 if (GET_CODE (jump_table_insn) == JUMP_INSN
3872 && GET_CODE (PATTERN (jump_table_insn)) == ADDR_DIFF_VEC)
3874 rtx jump_table = PATTERN (jump_table_insn);
3875 int n_labels = XVECLEN (jump_table, 1);
3876 int best_count = -1;
3879 for (i = 0; i < n_labels; i++)
3883 for (j = i + 1; j < n_labels; j++)
3884 if (XEXP (XVECEXP (jump_table, 1, i), 0)
3885 == XEXP (XVECEXP (jump_table, 1, j), 0))
3888 if (count > best_count)
3889 best_count = count, best_label = XVECEXP (jump_table, 1, i);
3895 operands[3] = best_label;
3896 return \"addq %0,$29,%2\;jmp $31,(%2),%3\";
3899 return \"addq %0,$29,%2\;jmp $31,(%2),0\";
3901 [(set_attr "type" "ibr")
3902 (set_attr "length" "8")])
3906 (match_operand:DI 0 "register_operand" "r"))
3907 (use (label_ref (match_operand 1 "" "")))]
3908 "TARGET_WINDOWS_NT && next_active_insn (insn) != 0
3909 && GET_CODE (PATTERN (next_active_insn (insn))) == ADDR_DIFF_VEC
3910 && PREV_INSN (next_active_insn (insn)) == operands[1]"
3912 { rtx best_label = 0;
3913 rtx jump_table_insn = next_active_insn (operands[1]);
3915 if (GET_CODE (jump_table_insn) == JUMP_INSN
3916 && GET_CODE (PATTERN (jump_table_insn)) == ADDR_DIFF_VEC)
3918 rtx jump_table = PATTERN (jump_table_insn);
3919 int n_labels = XVECLEN (jump_table, 1);
3920 int best_count = -1;
3923 for (i = 0; i < n_labels; i++)
3927 for (j = i + 1; j < n_labels; j++)
3928 if (XEXP (XVECEXP (jump_table, 1, i), 0)
3929 == XEXP (XVECEXP (jump_table, 1, j), 0))
3932 if (count > best_count)
3933 best_count = count, best_label = XVECEXP (jump_table, 1, i);
3939 operands[2] = best_label;
3940 return \"jmp $31,(%0),%2\";
3943 return \"jmp $31,(%0),0\";
3945 [(set_attr "type" "ibr")])
3948 ;; op 0 is table offset
3949 ;; op 1 is table label
3954 (plus:DI (match_operand 0 "register_operand" "r")
3955 (label_ref (match_operand 1 "" ""))))]
3958 [(set_attr "type" "ibr")])
3960 ;; Cache flush. Used by INITIALIZE_TRAMPOLINE. 0x86 is PAL_imb, but we don't
3961 ;; want to have to include pal.h in our .s file.
3963 ;; Technically the type for call_pal is jsr, but we use that for determining
3964 ;; if we need a GP. Use ibr instead since it has the same EV5 scheduling
3967 [(unspec_volatile [(const_int 0)] 0)]
3970 [(set_attr "type" "ibr")])
3972 ;; Finally, we have the basic data motion insns. The byte and word insns
3973 ;; are done via define_expand. Start with the floating-point insns, since
3974 ;; they are simpler.
3977 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m,f,f,m")
3978 (match_operand:SF 1 "input_operand" "rG,m,r,fG,m,fG"))]
3980 && (register_operand (operands[0], SFmode)
3981 || reg_or_fp0_operand (operands[1], SFmode))"
3989 [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst")])
3992 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m,f,f,m,f,*r")
3993 (match_operand:SF 1 "input_operand" "rG,m,r,fG,m,fG,r,*f"))]
3995 && (register_operand (operands[0], SFmode)
3996 || reg_or_fp0_operand (operands[1], SFmode))"
4006 [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst,itof,ftoi")])
4009 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,f,f,m")
4010 (match_operand:DF 1 "input_operand" "rG,m,r,fG,m,fG"))]
4012 && (register_operand (operands[0], DFmode)
4013 || reg_or_fp0_operand (operands[1], DFmode))"
4021 [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst")])
4024 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,f,f,m,f,*r")
4025 (match_operand:DF 1 "input_operand" "rG,m,r,fG,m,fG,r,*f"))]
4027 && (register_operand (operands[0], DFmode)
4028 || reg_or_fp0_operand (operands[1], DFmode))"
4038 [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst,itof,ftoi")])
4040 (define_expand "movsf"
4041 [(set (match_operand:SF 0 "nonimmediate_operand" "")
4042 (match_operand:SF 1 "general_operand" ""))]
4046 if (GET_CODE (operands[0]) == MEM
4047 && ! reg_or_fp0_operand (operands[1], SFmode))
4048 operands[1] = force_reg (SFmode, operands[1]);
4051 (define_expand "movdf"
4052 [(set (match_operand:DF 0 "nonimmediate_operand" "")
4053 (match_operand:DF 1 "general_operand" ""))]
4057 if (GET_CODE (operands[0]) == MEM
4058 && ! reg_or_fp0_operand (operands[1], DFmode))
4059 operands[1] = force_reg (DFmode, operands[1]);
4063 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m,f,f,m")
4064 (match_operand:SI 1 "input_operand" "rJ,K,L,m,rJ,fJ,m,f"))]
4065 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS && ! TARGET_CIX
4066 && (register_operand (operands[0], SImode)
4067 || reg_or_0_operand (operands[1], SImode))"
4077 [(set_attr "type" "ilog,iadd,iadd,ild,ist,fcpys,fld,fst")])
4080 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,m,f,f,m,r,*f")
4081 (match_operand:SI 1 "input_operand" "rJ,K,L,m,rJ,fJ,m,f,f,*r"))]
4082 "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS && TARGET_CIX
4083 && (register_operand (operands[0], SImode)
4084 || reg_or_0_operand (operands[1], SImode))"
4096 [(set_attr "type" "ilog,iadd,iadd,ild,ist,fcpys,fld,fst,ftoi,itof")])
4099 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m,f,f,m")
4100 (match_operand:SI 1 "input_operand" "rJ,K,L,s,m,rJ,fJ,m,f"))]
4101 "(TARGET_WINDOWS_NT || TARGET_OPEN_VMS)
4102 && (register_operand (operands[0], SImode)
4103 || reg_or_0_operand (operands[1], SImode))"
4114 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst")])
4117 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,f")
4118 (match_operand:HI 1 "input_operand" "rJ,n,fJ"))]
4120 && (register_operand (operands[0], HImode)
4121 || register_operand (operands[1], HImode))"
4126 [(set_attr "type" "ilog,iadd,fcpys")])
4129 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m,f")
4130 (match_operand:HI 1 "input_operand" "rJ,n,m,rJ,fJ"))]
4132 && (register_operand (operands[0], HImode)
4133 || reg_or_0_operand (operands[1], HImode))"
4140 [(set_attr "type" "ilog,iadd,ild,ist,fcpys")])
4143 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,f")
4144 (match_operand:QI 1 "input_operand" "rJ,n,fJ"))]
4146 && (register_operand (operands[0], QImode)
4147 || register_operand (operands[1], QImode))"
4152 [(set_attr "type" "ilog,iadd,fcpys")])
4155 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m,f")
4156 (match_operand:QI 1 "input_operand" "rJ,n,m,rJ,fJ"))]
4158 && (register_operand (operands[0], QImode)
4159 || reg_or_0_operand (operands[1], QImode))"
4166 [(set_attr "type" "ilog,iadd,ild,ist,fcpys")])
4168 ;; We do two major things here: handle mem->mem and construct long
4171 (define_expand "movsi"
4172 [(set (match_operand:SI 0 "general_operand" "")
4173 (match_operand:SI 1 "general_operand" ""))]
4177 if (GET_CODE (operands[0]) == MEM
4178 && ! reg_or_0_operand (operands[1], SImode))
4179 operands[1] = force_reg (SImode, operands[1]);
4181 if (! CONSTANT_P (operands[1]) || input_operand (operands[1], SImode))
4183 else if (GET_CODE (operands[1]) == CONST_INT)
4186 = alpha_emit_set_const (operands[0], SImode, INTVAL (operands[1]), 3);
4187 if (rtx_equal_p (operands[0], operands[1]))
4192 ;; Split a load of a large constant into the appropriate two-insn
4196 [(set (match_operand:SI 0 "register_operand" "")
4197 (match_operand:SI 1 "const_int_operand" ""))]
4198 "! add_operand (operands[1], SImode)"
4199 [(set (match_dup 0) (match_dup 2))
4200 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
4203 = alpha_emit_set_const (operands[0], SImode, INTVAL (operands[1]), 2);
4205 if (tem == operands[0])
4212 [(set (match_operand:DI 0 "general_operand" "=r,r,r,r,r,m,f,f,Q")
4213 (match_operand:DI 1 "input_operand" "rJ,K,L,s,m,rJ,fJ,Q,f"))]
4215 && (register_operand (operands[0], DImode)
4216 || reg_or_0_operand (operands[1], DImode))"
4227 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst")])
4230 [(set (match_operand:DI 0 "general_operand" "=r,r,r,r,r,m,f,f,Q,r,*f")
4231 (match_operand:DI 1 "input_operand" "rJ,K,L,s,m,rJ,fJ,Q,f,f,*r"))]
4233 && (register_operand (operands[0], DImode)
4234 || reg_or_0_operand (operands[1], DImode))"
4247 [(set_attr "type" "ilog,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof")])
4249 ;; We do three major things here: handle mem->mem, put 64-bit constants in
4250 ;; memory, and construct long 32-bit constants.
4252 (define_expand "movdi"
4253 [(set (match_operand:DI 0 "general_operand" "")
4254 (match_operand:DI 1 "general_operand" ""))]
4260 if (GET_CODE (operands[0]) == MEM
4261 && ! reg_or_0_operand (operands[1], DImode))
4262 operands[1] = force_reg (DImode, operands[1]);
4264 if (! CONSTANT_P (operands[1]) || input_operand (operands[1], DImode))
4266 else if (GET_CODE (operands[1]) == CONST_INT
4267 && (tem = alpha_emit_set_const (operands[0], DImode,
4268 INTVAL (operands[1]), 3)) != 0)
4270 if (rtx_equal_p (tem, operands[0]))
4275 else if (CONSTANT_P (operands[1]))
4277 if (TARGET_BUILD_CONSTANTS)
4279 HOST_WIDE_INT i0, i1;
4281 if (GET_CODE (operands[1]) == CONST_INT)
4283 i0 = INTVAL (operands[1]);
4286 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
4288 #if HOST_BITS_PER_WIDE_INT >= 64
4289 i0 = CONST_DOUBLE_LOW (operands[1]);
4292 i0 = CONST_DOUBLE_LOW (operands[1]);
4293 i1 = CONST_DOUBLE_HIGH (operands[1]);
4299 tem = alpha_emit_set_long_const (operands[0], i0, i1);
4300 if (rtx_equal_p (tem, operands[0]))
4307 operands[1] = force_const_mem (DImode, operands[1]);
4308 if (reload_in_progress)
4310 emit_move_insn (operands[0], XEXP (operands[1], 0));
4311 operands[1] = copy_rtx (operands[1]);
4312 XEXP (operands[1], 0) = operands[0];
4315 operands[1] = validize_mem (operands[1]);
4322 ;; Split a load of a large constant into the appropriate two-insn
4326 [(set (match_operand:DI 0 "register_operand" "")
4327 (match_operand:DI 1 "const_int_operand" ""))]
4328 "! add_operand (operands[1], DImode)"
4329 [(set (match_dup 0) (match_dup 2))
4330 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
4333 = alpha_emit_set_const (operands[0], DImode, INTVAL (operands[1]), 2);
4335 if (tem == operands[0])
4341 ;; These are the partial-word cases.
4343 ;; First we have the code to load an aligned word. Operand 0 is the register
4344 ;; in which to place the result. It's mode is QImode or HImode. Operand 1
4345 ;; is an SImode MEM at the low-order byte of the proper word. Operand 2 is the
4346 ;; number of bits within the word that the value is. Operand 3 is an SImode
4347 ;; scratch register. If operand 0 is a hard register, operand 3 may be the
4348 ;; same register. It is allowed to conflict with operand 1 as well.
4350 (define_expand "aligned_loadqi"
4351 [(set (match_operand:SI 3 "register_operand" "")
4352 (match_operand:SI 1 "memory_operand" ""))
4353 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
4354 (zero_extract:DI (subreg:DI (match_dup 3) 0)
4356 (match_operand:DI 2 "const_int_operand" "")))]
4361 (define_expand "aligned_loadhi"
4362 [(set (match_operand:SI 3 "register_operand" "")
4363 (match_operand:SI 1 "memory_operand" ""))
4364 (set (subreg:DI (match_operand:HI 0 "register_operand" "") 0)
4365 (zero_extract:DI (subreg:DI (match_dup 3) 0)
4367 (match_operand:DI 2 "const_int_operand" "")))]
4372 ;; Similar for unaligned loads, where we use the sequence from the
4373 ;; Alpha Architecture manual.
4375 ;; Operand 1 is the address. Operands 2 and 3 are temporaries, where
4376 ;; operand 3 can overlap the input and output registers.
4378 (define_expand "unaligned_loadqi"
4379 [(set (match_operand:DI 2 "register_operand" "")
4380 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
4382 (set (match_operand:DI 3 "register_operand" "")
4384 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
4385 (zero_extract:DI (match_dup 2)
4387 (ashift:DI (match_dup 3) (const_int 3))))]
4391 (define_expand "unaligned_loadhi"
4392 [(set (match_operand:DI 2 "register_operand" "")
4393 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
4395 (set (match_operand:DI 3 "register_operand" "")
4397 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
4398 (zero_extract:DI (match_dup 2)
4400 (ashift:DI (match_dup 3) (const_int 3))))]
4404 ;; Storing an aligned byte or word requires two temporaries. Operand 0 is the
4405 ;; aligned SImode MEM. Operand 1 is the register containing the
4406 ;; byte or word to store. Operand 2 is the number of bits within the word that
4407 ;; the value should be placed. Operands 3 and 4 are SImode temporaries.
4409 (define_expand "aligned_store"
4410 [(set (match_operand:SI 3 "register_operand" "")
4411 (match_operand:SI 0 "memory_operand" ""))
4412 (set (subreg:DI (match_dup 3) 0)
4413 (and:DI (subreg:DI (match_dup 3) 0) (match_dup 5)))
4414 (set (subreg:DI (match_operand:SI 4 "register_operand" "") 0)
4415 (ashift:DI (zero_extend:DI (match_operand 1 "register_operand" ""))
4416 (match_operand:DI 2 "const_int_operand" "")))
4417 (set (subreg:DI (match_dup 4) 0)
4418 (ior:DI (subreg:DI (match_dup 4) 0) (subreg:DI (match_dup 3) 0)))
4419 (set (match_dup 0) (match_dup 4))]
4422 { operands[5] = GEN_INT (~ (GET_MODE_MASK (GET_MODE (operands[1]))
4423 << INTVAL (operands[2])));
4426 ;; For the unaligned byte and halfword cases, we use code similar to that
4427 ;; in the ;; Architecture book, but reordered to lower the number of registers
4428 ;; required. Operand 0 is the address. Operand 1 is the data to store.
4429 ;; Operands 2, 3, and 4 are DImode temporaries, where operands 2 and 4 may
4430 ;; be the same temporary, if desired. If the address is in a register,
4431 ;; operand 2 can be that register.
4433 (define_expand "unaligned_storeqi"
4434 [(set (match_operand:DI 3 "register_operand" "")
4435 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
4437 (set (match_operand:DI 2 "register_operand" "")
4440 (and:DI (not:DI (ashift:DI (const_int 255)
4441 (ashift:DI (match_dup 2) (const_int 3))))
4443 (set (match_operand:DI 4 "register_operand" "")
4444 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
4445 (ashift:DI (match_dup 2) (const_int 3))))
4446 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
4447 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
4452 (define_expand "unaligned_storehi"
4453 [(set (match_operand:DI 3 "register_operand" "")
4454 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
4456 (set (match_operand:DI 2 "register_operand" "")
4459 (and:DI (not:DI (ashift:DI (const_int 65535)
4460 (ashift:DI (match_dup 2) (const_int 3))))
4462 (set (match_operand:DI 4 "register_operand" "")
4463 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
4464 (ashift:DI (match_dup 2) (const_int 3))))
4465 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
4466 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
4471 ;; Here are the define_expand's for QI and HI moves that use the above
4472 ;; patterns. We have the normal sets, plus the ones that need scratch
4473 ;; registers for reload.
4475 (define_expand "movqi"
4476 [(set (match_operand:QI 0 "general_operand" "")
4477 (match_operand:QI 1 "general_operand" ""))]
4483 if (GET_CODE (operands[0]) == MEM
4484 && ! reg_or_0_operand (operands[1], QImode))
4485 operands[1] = force_reg (QImode, operands[1]);
4487 if (GET_CODE (operands[1]) == CONST_INT
4488 && ! input_operand (operands[1], QImode))
4490 operands[1] = alpha_emit_set_const (operands[0], QImode,
4491 INTVAL (operands[1]), 3);
4493 if (rtx_equal_p (operands[0], operands[1]))
4500 /* If the output is not a register, the input must be. */
4501 if (GET_CODE (operands[0]) == MEM)
4502 operands[1] = force_reg (QImode, operands[1]);
4504 /* Handle four memory cases, unaligned and aligned for either the input
4505 or the output. The only case where we can be called during reload is
4506 for aligned loads; all other cases require temporaries. */
4508 if (GET_CODE (operands[1]) == MEM
4509 || (GET_CODE (operands[1]) == SUBREG
4510 && GET_CODE (SUBREG_REG (operands[1])) == MEM)
4511 || (reload_in_progress && GET_CODE (operands[1]) == REG
4512 && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
4513 || (reload_in_progress && GET_CODE (operands[1]) == SUBREG
4514 && GET_CODE (SUBREG_REG (operands[1])) == REG
4515 && REGNO (SUBREG_REG (operands[1])) >= FIRST_PSEUDO_REGISTER))
4517 if (aligned_memory_operand (operands[1], QImode))
4519 rtx aligned_mem, bitnum;
4520 rtx scratch = (reload_in_progress
4521 ? gen_rtx_REG (SImode, REGNO (operands[0]))
4522 : gen_reg_rtx (SImode));
4524 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
4526 emit_insn (gen_aligned_loadqi (operands[0], aligned_mem, bitnum,
4531 /* Don't pass these as parameters since that makes the generated
4532 code depend on parameter evaluation order which will cause
4533 bootstrap failures. */
4535 rtx temp1 = gen_reg_rtx (DImode);
4536 rtx temp2 = gen_reg_rtx (DImode);
4538 = gen_unaligned_loadqi (operands[0],
4539 get_unaligned_address (operands[1], 0),
4542 alpha_set_memflags (seq, operands[1]);
4549 else if (GET_CODE (operands[0]) == MEM
4550 || (GET_CODE (operands[0]) == SUBREG
4551 && GET_CODE (SUBREG_REG (operands[0])) == MEM)
4552 || (reload_in_progress && GET_CODE (operands[0]) == REG
4553 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)
4554 || (reload_in_progress && GET_CODE (operands[0]) == SUBREG
4555 && GET_CODE (SUBREG_REG (operands[0])) == REG
4556 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))
4558 if (aligned_memory_operand (operands[0], QImode))
4560 rtx aligned_mem, bitnum;
4561 rtx temp1 = gen_reg_rtx (SImode);
4562 rtx temp2 = gen_reg_rtx (SImode);
4564 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
4566 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
4571 rtx temp1 = gen_reg_rtx (DImode);
4572 rtx temp2 = gen_reg_rtx (DImode);
4573 rtx temp3 = gen_reg_rtx (DImode);
4575 = gen_unaligned_storeqi (get_unaligned_address (operands[0], 0),
4576 operands[1], temp1, temp2, temp3);
4578 alpha_set_memflags (seq, operands[0]);
4586 (define_expand "movhi"
4587 [(set (match_operand:HI 0 "general_operand" "")
4588 (match_operand:HI 1 "general_operand" ""))]
4594 if (GET_CODE (operands[0]) == MEM
4595 && ! reg_or_0_operand (operands[1], HImode))
4596 operands[1] = force_reg (HImode, operands[1]);
4598 if (GET_CODE (operands[1]) == CONST_INT
4599 && ! input_operand (operands[1], HImode))
4601 operands[1] = alpha_emit_set_const (operands[0], HImode,
4602 INTVAL (operands[1]), 3);
4604 if (rtx_equal_p (operands[0], operands[1]))
4611 /* If the output is not a register, the input must be. */
4612 if (GET_CODE (operands[0]) == MEM)
4613 operands[1] = force_reg (HImode, operands[1]);
4615 /* Handle four memory cases, unaligned and aligned for either the input
4616 or the output. The only case where we can be called during reload is
4617 for aligned loads; all other cases require temporaries. */
4619 if (GET_CODE (operands[1]) == MEM
4620 || (GET_CODE (operands[1]) == SUBREG
4621 && GET_CODE (SUBREG_REG (operands[1])) == MEM)
4622 || (reload_in_progress && GET_CODE (operands[1]) == REG
4623 && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
4624 || (reload_in_progress && GET_CODE (operands[1]) == SUBREG
4625 && GET_CODE (SUBREG_REG (operands[1])) == REG
4626 && REGNO (SUBREG_REG (operands[1])) >= FIRST_PSEUDO_REGISTER))
4628 if (aligned_memory_operand (operands[1], HImode))
4630 rtx aligned_mem, bitnum;
4631 rtx scratch = (reload_in_progress
4632 ? gen_rtx_REG (SImode, REGNO (operands[0]))
4633 : gen_reg_rtx (SImode));
4635 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
4637 emit_insn (gen_aligned_loadhi (operands[0], aligned_mem, bitnum,
4642 /* Don't pass these as parameters since that makes the generated
4643 code depend on parameter evaluation order which will cause
4644 bootstrap failures. */
4646 rtx temp1 = gen_reg_rtx (DImode);
4647 rtx temp2 = gen_reg_rtx (DImode);
4649 = gen_unaligned_loadhi (operands[0],
4650 get_unaligned_address (operands[1], 0),
4653 alpha_set_memflags (seq, operands[1]);
4660 else if (GET_CODE (operands[0]) == MEM
4661 || (GET_CODE (operands[0]) == SUBREG
4662 && GET_CODE (SUBREG_REG (operands[0])) == MEM)
4663 || (reload_in_progress && GET_CODE (operands[0]) == REG
4664 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)
4665 || (reload_in_progress && GET_CODE (operands[0]) == SUBREG
4666 && GET_CODE (SUBREG_REG (operands[0])) == REG
4667 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))
4669 if (aligned_memory_operand (operands[0], HImode))
4671 rtx aligned_mem, bitnum;
4672 rtx temp1 = gen_reg_rtx (SImode);
4673 rtx temp2 = gen_reg_rtx (SImode);
4675 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
4677 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
4682 rtx temp1 = gen_reg_rtx (DImode);
4683 rtx temp2 = gen_reg_rtx (DImode);
4684 rtx temp3 = gen_reg_rtx (DImode);
4686 = gen_unaligned_storehi (get_unaligned_address (operands[0], 0),
4687 operands[1], temp1, temp2, temp3);
4689 alpha_set_memflags (seq, operands[0]);
4698 ;; Here are the versions for reload. Note that in the unaligned cases
4699 ;; we know that the operand must not be a pseudo-register because stack
4700 ;; slots are always aligned references.
4702 (define_expand "reload_inqi"
4703 [(parallel [(match_operand:QI 0 "register_operand" "=r")
4704 (match_operand:QI 1 "unaligned_memory_operand" "m")
4705 (match_operand:TI 2 "register_operand" "=&r")])]
4709 rtx addr = get_unaligned_address (operands[1], 0);
4711 /* It is possible that one of the registers we got for operands[2]
4712 might coincide with that of operands[0] (which is why we made
4713 it TImode). Pick the other one to use as our scratch. */
4714 rtx scratch = gen_rtx_REG (DImode,
4715 REGNO (operands[0]) == REGNO (operands[2])
4716 ? REGNO (operands[2]) + 1 : REGNO (operands[2]));
4718 rtx seq = gen_unaligned_loadqi (operands[0], addr, scratch,
4719 gen_rtx_REG (DImode, REGNO (operands[0])));
4721 alpha_set_memflags (seq, operands[1]);
4726 (define_expand "reload_inhi"
4727 [(parallel [(match_operand:HI 0 "register_operand" "=r")
4728 (match_operand:HI 1 "unaligned_memory_operand" "m")
4729 (match_operand:TI 2 "register_operand" "=&r")])]
4733 rtx addr = get_unaligned_address (operands[1], 0);
4735 /* It is possible that one of the registers we got for operands[2]
4736 might coincide with that of operands[0] (which is why we made
4737 it TImode). Pick the other one to use as our scratch. */
4738 rtx scratch = gen_rtx_REG (DImode,
4739 REGNO (operands[0]) == REGNO (operands[2])
4740 ? REGNO (operands[2]) + 1 : REGNO (operands[2]));
4742 rtx seq = gen_unaligned_loadhi (operands[0], addr, scratch,
4743 gen_rtx_REG (DImode, REGNO (operands[0])));
4745 alpha_set_memflags (seq, operands[1]);
4750 (define_expand "reload_outqi"
4751 [(parallel [(match_operand:QI 0 "any_memory_operand" "=m")
4752 (match_operand:QI 1 "register_operand" "r")
4753 (match_operand:TI 2 "register_operand" "=&r")])]
4757 if (aligned_memory_operand (operands[0], QImode))
4759 rtx aligned_mem, bitnum;
4761 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
4763 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
4764 gen_rtx_REG (SImode, REGNO (operands[2])),
4765 gen_rtx_REG (SImode,
4766 REGNO (operands[2]) + 1)));
4770 rtx addr = get_unaligned_address (operands[0], 0);
4771 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
4772 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
4773 rtx scratch3 = scratch1;
4776 if (GET_CODE (addr) == REG)
4779 seq = gen_unaligned_storeqi (addr, operands[1], scratch1,
4780 scratch2, scratch3);
4781 alpha_set_memflags (seq, operands[0]);
4788 (define_expand "reload_outhi"
4789 [(parallel [(match_operand:HI 0 "any_memory_operand" "=m")
4790 (match_operand:HI 1 "register_operand" "r")
4791 (match_operand:TI 2 "register_operand" "=&r")])]
4795 if (aligned_memory_operand (operands[0], HImode))
4797 rtx aligned_mem, bitnum;
4799 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
4801 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
4802 gen_rtx_REG (SImode, REGNO (operands[2])),
4803 gen_rtx_REG (SImode,
4804 REGNO (operands[2]) + 1)));
4808 rtx addr = get_unaligned_address (operands[0], 0);
4809 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
4810 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
4811 rtx scratch3 = scratch1;
4814 if (GET_CODE (addr) == REG)
4817 seq = gen_unaligned_storehi (addr, operands[1], scratch1,
4818 scratch2, scratch3);
4819 alpha_set_memflags (seq, operands[0]);
4826 ;; Bit field extract patterns which use ext[wlq][lh]
4828 (define_expand "extv"
4829 [(set (match_operand:DI 0 "register_operand" "")
4830 (sign_extract:DI (match_operand:QI 1 "memory_operand" "")
4831 (match_operand:DI 2 "immediate_operand" "")
4832 (match_operand:DI 3 "immediate_operand" "")))]
4836 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
4837 if (INTVAL (operands[3]) % 8 != 0
4838 || (INTVAL (operands[2]) != 16
4839 && INTVAL (operands[2]) != 32
4840 && INTVAL (operands[2]) != 64))
4843 /* From mips.md: extract_bit_field doesn't verify that our source
4844 matches the predicate, so we force it to be a MEM here. */
4845 if (GET_CODE (operands[1]) != MEM)
4848 alpha_expand_unaligned_load (operands[0], operands[1],
4849 INTVAL (operands[2]) / 8,
4850 INTVAL (operands[3]) / 8, 1);
4854 (define_expand "extzv"
4855 [(set (match_operand:DI 0 "register_operand" "")
4856 (zero_extract:DI (match_operand:DI 1 "general_operand" "")
4857 (match_operand:DI 2 "immediate_operand" "")
4858 (match_operand:DI 3 "immediate_operand" "")))]
4862 /* We can do 8, 16, 32 and 64 bit fields, if aligned on byte boundaries. */
4863 if (INTVAL (operands[3]) % 8 != 0
4864 || (INTVAL (operands[2]) != 8
4865 && INTVAL (operands[2]) != 16
4866 && INTVAL (operands[2]) != 32
4867 && INTVAL (operands[2]) != 64))
4870 if (GET_CODE (operands[1]) == MEM)
4872 /* Fail 8 bit fields, falling back on a simple byte load. */
4873 if (INTVAL (operands[2]) == 8)
4876 alpha_expand_unaligned_load (operands[0], operands[1],
4877 INTVAL (operands[2]) / 8,
4878 INTVAL (operands[3]) / 8, 0);
4883 (define_expand "insv"
4884 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "")
4885 (match_operand:DI 1 "immediate_operand" "")
4886 (match_operand:DI 2 "immediate_operand" ""))
4887 (match_operand:DI 3 "register_operand" ""))]
4891 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
4892 if (INTVAL (operands[2]) % 8 != 0
4893 || (INTVAL (operands[1]) != 16
4894 && INTVAL (operands[1]) != 32
4895 && INTVAL (operands[1]) != 64))
4898 /* From mips.md: store_bit_field doesn't verify that our source
4899 matches the predicate, so we force it to be a MEM here. */
4900 if (GET_CODE (operands[0]) != MEM)
4903 alpha_expand_unaligned_store (operands[0], operands[3],
4904 INTVAL (operands[1]) / 8,
4905 INTVAL (operands[2]) / 8);
4911 ;; Block move/clear, see alpha.c for more details.
4912 ;; Argument 0 is the destination
4913 ;; Argument 1 is the source
4914 ;; Argument 2 is the length
4915 ;; Argument 3 is the alignment
4917 (define_expand "movstrqi"
4918 [(parallel [(set (match_operand:BLK 0 "general_operand" "")
4919 (match_operand:BLK 1 "general_operand" ""))
4920 (use (match_operand:DI 2 "immediate_operand" ""))
4921 (use (match_operand:DI 3 "immediate_operand" ""))])]
4925 if (alpha_expand_block_move (operands))
4931 (define_expand "clrstrqi"
4932 [(parallel [(set (match_operand:BLK 0 "general_operand" "")
4934 (use (match_operand:DI 1 "immediate_operand" ""))
4935 (use (match_operand:DI 2 "immediate_operand" ""))])]
4939 if (alpha_expand_block_clear (operands))
4945 ;; Subroutine of stack space allocation. Perform a stack probe.
4946 (define_expand "probe_stack"
4947 [(set (match_dup 1) (match_operand:DI 0 "const_int_operand" ""))]
4951 operands[1] = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx,
4952 INTVAL (operands[0])));
4953 MEM_VOLATILE_P (operands[1]) = 1;
4955 operands[0] = const0_rtx;
4958 ;; This is how we allocate stack space. If we are allocating a
4959 ;; constant amount of space and we know it is less than 4096
4960 ;; bytes, we need do nothing.
4962 ;; If it is more than 4096 bytes, we need to probe the stack
4964 (define_expand "allocate_stack"
4966 (plus:DI (reg:DI 30)
4967 (match_operand:DI 1 "reg_or_cint_operand" "")))
4968 (set (match_operand:DI 0 "register_operand" "=r")
4973 if (GET_CODE (operands[1]) == CONST_INT
4974 && INTVAL (operands[1]) < 32768)
4976 if (INTVAL (operands[1]) >= 4096)
4978 /* We do this the same way as in the prologue and generate explicit
4979 probes. Then we update the stack by the constant. */
4983 emit_insn (gen_probe_stack (GEN_INT (- probed)));
4984 while (probed + 8192 < INTVAL (operands[1]))
4985 emit_insn (gen_probe_stack (GEN_INT (- (probed += 8192))));
4987 if (probed + 4096 < INTVAL (operands[1]))
4988 emit_insn (gen_probe_stack (GEN_INT (- INTVAL(operands[1]))));
4991 operands[1] = GEN_INT (- INTVAL (operands[1]));
4992 operands[2] = virtual_stack_dynamic_rtx;
4997 rtx loop_label = gen_label_rtx ();
4998 rtx want = gen_reg_rtx (Pmode);
4999 rtx tmp = gen_reg_rtx (Pmode);
5002 emit_insn (gen_subdi3 (want, stack_pointer_rtx,
5003 force_reg (Pmode, operands[1])));
5004 emit_insn (gen_adddi3 (tmp, stack_pointer_rtx, GEN_INT (-4096)));
5006 if (GET_CODE (operands[1]) != CONST_INT)
5008 out_label = gen_label_rtx ();
5009 emit_insn (gen_cmpdi (want, tmp));
5010 emit_jump_insn (gen_bgeu (out_label));
5013 emit_label (loop_label);
5014 memref = gen_rtx_MEM (DImode, tmp);
5015 MEM_VOLATILE_P (memref) = 1;
5016 emit_move_insn (memref, const0_rtx);
5017 emit_insn (gen_adddi3 (tmp, tmp, GEN_INT(-8192)));
5018 emit_insn (gen_cmpdi (tmp, want));
5019 emit_jump_insn (gen_bgtu (loop_label));
5021 gen_rtx_USE (VOIDmode, tmp);
5023 memref = gen_rtx_MEM (DImode, want);
5024 MEM_VOLATILE_P (memref) = 1;
5025 emit_move_insn (memref, const0_rtx);
5028 emit_label (out_label);
5030 emit_move_insn (stack_pointer_rtx, want);
5031 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
5036 ;; This is used by alpha_expand_prolog to do the same thing as above,
5037 ;; except we cannot at that time generate new basic blocks, so we hide
5038 ;; the loop in this one insn.
5040 (define_insn "prologue_stack_probe_loop"
5041 [(unspec_volatile [(match_operand 0 "register_operand" "r")
5042 (match_operand 1 "register_operand" "r")] 5)]
5046 operands[2] = gen_label_rtx ();
5047 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
5048 CODE_LABEL_NUMBER (operands[2]));
5050 return \"stq $31,-8192(%1)\;subq %0,1,%0\;lda %1,-8192(%1)\;bne %0,%l2\";
5052 [(set_attr "length" "16")
5053 (set_attr "type" "multi")])
5055 (define_expand "prologue"
5056 [(clobber (const_int 0))]
5058 "alpha_expand_prologue (); DONE;")
5060 (define_insn "init_fp"
5061 [(set (match_operand:DI 0 "register_operand" "r")
5062 (match_operand:DI 1 "register_operand" "r"))
5063 (clobber (mem:BLK (match_operand:DI 2 "register_operand" "r")))]
5067 (define_expand "epilogue"
5068 [(clobber (const_int 0))]
5070 "alpha_expand_epilogue (); DONE;")
5072 (define_expand "eh_epilogue"
5073 [(use (match_operand:DI 0 "register_operand" "r"))
5074 (use (match_operand:DI 1 "register_operand" "r"))
5075 (use (match_operand:DI 2 "register_operand" "r"))]
5079 alpha_eh_epilogue_sp_ofs = operands[1];
5080 if (GET_CODE (operands[2]) != REG || REGNO (operands[2]) != 26)
5082 rtx ra = gen_rtx_REG (Pmode, 26);
5083 emit_move_insn (ra, operands[2]);
5088 (define_expand "builtin_longjmp"
5089 [(unspec_volatile [(match_operand 0 "register_operand" "r")] 3)]
5090 "! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT"
5093 /* The elements of the buffer are, in order: */
5094 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
5095 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 8));
5096 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 16));
5097 rtx pv = gen_rtx_REG (Pmode, 27);
5099 /* This bit is the same as expand_builtin_longjmp. */
5100 emit_move_insn (hard_frame_pointer_rtx, fp);
5101 emit_move_insn (pv, lab);
5102 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
5103 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
5104 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
5106 /* Load the label we are jumping through into $27 so that we know
5107 where to look for it when we get back to setjmp's function for
5108 restoring the gp. */
5109 emit_indirect_jump (pv);
5113 (define_insn "builtin_setjmp_receiver"
5114 [(unspec_volatile [(match_operand 0 "" "")] 2)]
5115 "! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT && TARGET_AS_CAN_SUBTRACT_LABELS"
5116 "\\n$LSJ%=:\;ldgp $29,$LSJ%=-%l0($27)"
5117 [(set_attr "length" "8")
5118 (set_attr "type" "multi")])
5121 [(unspec_volatile [(match_operand 0 "" "")] 2)]
5122 "! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT"
5123 "br $29,$LSJ%=\\n$LSJ%=:\;ldgp $29,0($29)"
5124 [(set_attr "length" "12")
5125 (set_attr "type" "multi")])
5127 (define_insn "exception_receiver"
5128 [(unspec_volatile [(const_int 0)] 7)]
5129 "! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT"
5130 "br $29,$LSJ%=\\n$LSJ%=:\;ldgp $29,0($29)"
5131 [(set_attr "length" "12")
5132 (set_attr "type" "multi")])
5134 (define_expand "nonlocal_goto_receiver"
5135 [(unspec_volatile [(const_int 0)] 1)
5136 (set (reg:DI 27) (mem:DI (reg:DI 29)))
5137 (unspec_volatile [(const_int 0)] 1)
5142 (define_insn "arg_home"
5143 [(unspec [(const_int 0)] 0)
5158 (clobber (mem:BLK (const_int 0)))
5159 (clobber (reg:DI 24))
5160 (clobber (reg:DI 25))
5161 (clobber (reg:DI 0))]
5163 "lda $0,OTS$HOME_ARGS\;ldq $0,8($0)\;jsr $0,OTS$HOME_ARGS"
5164 [(set_attr "length" "16")
5165 (set_attr "type" "multi")])
5167 ;; Close the trap shadow of preceeding instructions. This is generated
5170 (define_insn "trapb"
5171 [(unspec_volatile [(const_int 0)] 4)]
5174 [(set_attr "type" "misc")])
5176 ;; No-op instructions used by machine-dependant reorg to preserve
5177 ;; alignment for instruction issue.
5183 [(set_attr "type" "ilog")])
5189 [(set_attr "type" "fcpys")])
5196 (define_insn "realign"
5197 [(unspec_volatile [(match_operand 0 "immediate_operand" "i")] 6)]
5199 ".align %0 #realign")
5201 ;; Peepholes go at the end.
5203 ;; Optimize sign-extension of SImode loads. This shows up in the wake of
5204 ;; reload when converting fp->int.
5206 ;; ??? What to do now that we actually care about the packing and
5207 ;; alignment of instructions? Perhaps reload can be enlightened, or
5208 ;; the peephole pass moved up after reload but before sched2?
5211 ; [(set (match_operand:SI 0 "register_operand" "=r")
5212 ; (match_operand:SI 1 "memory_operand" "m"))
5213 ; (set (match_operand:DI 2 "register_operand" "=r")
5214 ; (sign_extend:DI (match_dup 0)))]
5215 ; "dead_or_set_p (insn, operands[0])"
5219 ; [(set (match_operand:SI 0 "register_operand" "=r")
5220 ; (match_operand:SI 1 "hard_fp_register_operand" "f"))
5221 ; (set (match_operand:DI 2 "register_operand" "=r")
5222 ; (sign_extend:DI (match_dup 0)))]
5223 ; "TARGET_CIX && dead_or_set_p (insn, operands[0])"