1 /* Definitions of target machine for GNU compiler, for DEC Alpha.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
24 /* Write out the correct language type definition for the header files.
25 Unless we have assembler language, write out the symbols for C. */
28 %{.S:-D__LANGUAGE_ASSEMBLY__ -D__LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY }}\
29 %{.cc|.cxx|.C:-D__LANGUAGE_C_PLUS_PLUS__ -D__LANGUAGE_C_PLUS_PLUS -D__cplusplus }\
30 %{.m:-D__LANGUAGE_OBJECTIVE_C__ -D__LANGUAGE_OBJECTIVE_C }\
31 %{!.S:%{!.cc:%{!.cxx:%{!.C:%{!.m:-D__LANGUAGE_C__ -D__LANGUAGE_C %{!ansi:-DLANGUAGE_C }}}}}}\
33 %{mieee-with-inexact:-D_IEEE_FP -D_IEEE_FP_INEXACT }}\
34 %(cpp_cpu) %(cpp_subtarget)"
36 #ifndef CPP_SUBTARGET_SPEC
37 #define CPP_SUBTARGET_SPEC ""
40 /* Set the spec to use for signed char. The default tests the above macro
41 but DEC's compiler can't handle the conditional in a "constant"
44 #define SIGNED_CHAR_SPEC "%{funsigned-char:-D__CHAR_UNSIGNED__}"
46 #define WORD_SWITCH_TAKES_ARG(STR) \
47 (!strcmp (STR, "rpath") || DEFAULT_WORD_SWITCH_TAKES_ARG(STR))
49 /* Print subsidiary information on the compiler version in use. */
50 #define TARGET_VERSION
52 /* Run-time compilation parameters selecting different hardware subsets. */
54 /* Which processor to schedule for. The cpu attribute defines a list that
55 mirrors this list, so changes to alpha.md must be made at the same time. */
58 {PROCESSOR_EV4, /* 2106[46]{a,} */
59 PROCESSOR_EV5, /* 21164{a,pc,} */
60 PROCESSOR_EV6}; /* 21264 */
62 extern enum processor_type alpha_cpu;
64 enum alpha_trap_precision
66 ALPHA_TP_PROG, /* No precision (default). */
67 ALPHA_TP_FUNC, /* Trap contained within originating function. */
68 ALPHA_TP_INSN /* Instruction accuracy and code is resumption safe. */
71 enum alpha_fp_rounding_mode
73 ALPHA_FPRM_NORM, /* Normal rounding mode. */
74 ALPHA_FPRM_MINF, /* Round towards minus-infinity. */
75 ALPHA_FPRM_CHOP, /* Chopped rounding mode (towards 0). */
76 ALPHA_FPRM_DYN /* Dynamic rounding mode. */
79 enum alpha_fp_trap_mode
81 ALPHA_FPTM_N, /* Normal trap mode. */
82 ALPHA_FPTM_U, /* Underflow traps enabled. */
83 ALPHA_FPTM_SU, /* Software completion, w/underflow traps */
84 ALPHA_FPTM_SUI /* Software completion, w/underflow & inexact traps */
87 extern int target_flags;
89 extern enum alpha_trap_precision alpha_tp;
90 extern enum alpha_fp_rounding_mode alpha_fprm;
91 extern enum alpha_fp_trap_mode alpha_fptm;
93 /* This means that floating-point support exists in the target implementation
94 of the Alpha architecture. This is usually the default. */
95 #define MASK_FP (1 << 0)
96 #define TARGET_FP (target_flags & MASK_FP)
98 /* This means that floating-point registers are allowed to be used. Note
99 that Alpha implementations without FP operations are required to
100 provide the FP registers. */
102 #define MASK_FPREGS (1 << 1)
103 #define TARGET_FPREGS (target_flags & MASK_FPREGS)
105 /* This means that gas is used to process the assembler file. */
107 #define MASK_GAS (1 << 2)
108 #define TARGET_GAS (target_flags & MASK_GAS)
110 /* This means that we should mark procedures as IEEE conformant. */
112 #define MASK_IEEE_CONFORMANT (1 << 3)
113 #define TARGET_IEEE_CONFORMANT (target_flags & MASK_IEEE_CONFORMANT)
115 /* This means we should be IEEE-compliant except for inexact. */
117 #define MASK_IEEE (1 << 4)
118 #define TARGET_IEEE (target_flags & MASK_IEEE)
120 /* This means we should be fully IEEE-compliant. */
122 #define MASK_IEEE_WITH_INEXACT (1 << 5)
123 #define TARGET_IEEE_WITH_INEXACT (target_flags & MASK_IEEE_WITH_INEXACT)
125 /* This means we must construct all constants rather than emitting
126 them as literal data. */
128 #define MASK_BUILD_CONSTANTS (1 << 6)
129 #define TARGET_BUILD_CONSTANTS (target_flags & MASK_BUILD_CONSTANTS)
131 /* This means we handle floating points in VAX F- (float)
132 or G- (double) Format. */
134 #define MASK_FLOAT_VAX (1 << 7)
135 #define TARGET_FLOAT_VAX (target_flags & MASK_FLOAT_VAX)
137 /* This means that the processor has byte and half word loads and stores
138 (the BWX extension). */
140 #define MASK_BWX (1 << 8)
141 #define TARGET_BWX (target_flags & MASK_BWX)
143 /* This means that the processor has the MAX extension. */
144 #define MASK_MAX (1 << 9)
145 #define TARGET_MAX (target_flags & MASK_MAX)
147 /* This means that the processor has the FIX extension. */
148 #define MASK_FIX (1 << 10)
149 #define TARGET_FIX (target_flags & MASK_FIX)
151 /* This means that the processor has the CIX extension. */
152 #define MASK_CIX (1 << 11)
153 #define TARGET_CIX (target_flags & MASK_CIX)
155 /* This means that the processor is an EV5, EV56, or PCA56.
156 Unlike alpha_cpu this is not affected by -mtune= setting. */
157 #define MASK_CPU_EV5 (1 << 28)
158 #define TARGET_CPU_EV5 (target_flags & MASK_CPU_EV5)
160 /* Likewise for EV6. */
161 #define MASK_CPU_EV6 (1 << 29)
162 #define TARGET_CPU_EV6 (target_flags & MASK_CPU_EV6)
164 /* This means we support the .arch directive in the assembler. Only
165 defined in TARGET_CPU_DEFAULT. */
166 #define MASK_SUPPORT_ARCH (1 << 30)
167 #define TARGET_SUPPORT_ARCH (target_flags & MASK_SUPPORT_ARCH)
169 /* These are for target os support and cannot be changed at runtime. */
170 #ifndef TARGET_WINDOWS_NT
171 #define TARGET_WINDOWS_NT 0
173 #ifndef TARGET_OPEN_VMS
174 #define TARGET_OPEN_VMS 0
177 #ifndef TARGET_AS_CAN_SUBTRACT_LABELS
178 #define TARGET_AS_CAN_SUBTRACT_LABELS TARGET_GAS
180 #ifndef TARGET_CAN_FAULT_IN_PROLOGUE
181 #define TARGET_CAN_FAULT_IN_PROLOGUE 0
183 #ifndef TARGET_HAS_XFLOATING_LIBS
184 #define TARGET_HAS_XFLOATING_LIBS 0
186 #ifndef TARGET_PROFILING_NEEDS_GP
187 #define TARGET_PROFILING_NEEDS_GP 0
190 /* Macro to define tables used to set the flags.
191 This is a list in braces of pairs in braces,
192 each pair being { "NAME", VALUE }
193 where VALUE is the bits to set or minus the bits to clear.
194 An empty string NAME is used to identify the default VALUE. */
196 #define TARGET_SWITCHES \
197 { {"no-soft-float", MASK_FP, N_("Use hardware fp")}, \
198 {"soft-float", - MASK_FP, N_("Do not use hardware fp")}, \
199 {"fp-regs", MASK_FPREGS, N_("Use fp registers")}, \
200 {"no-fp-regs", - (MASK_FP|MASK_FPREGS), \
201 N_("Do not use fp registers")}, \
202 {"alpha-as", -MASK_GAS, N_("Do not assume GAS")}, \
203 {"gas", MASK_GAS, N_("Assume GAS")}, \
204 {"ieee-conformant", MASK_IEEE_CONFORMANT, \
205 N_("Request IEEE-conformant math library routines (OSF/1)")}, \
206 {"ieee", MASK_IEEE|MASK_IEEE_CONFORMANT, \
207 N_("Emit IEEE-conformant code, without inexact exceptions")}, \
208 {"ieee-with-inexact", MASK_IEEE_WITH_INEXACT|MASK_IEEE_CONFORMANT, \
209 N_("Emit IEEE-conformant code, with inexact exceptions")}, \
210 {"build-constants", MASK_BUILD_CONSTANTS, \
211 N_("Do not emit complex integer constants to read-only memory")}, \
212 {"float-vax", MASK_FLOAT_VAX, N_("Use VAX fp")}, \
213 {"float-ieee", -MASK_FLOAT_VAX, N_("Do not use VAX fp")}, \
214 {"bwx", MASK_BWX, N_("Emit code for the byte/word ISA extension")}, \
215 {"no-bwx", -MASK_BWX, ""}, \
217 N_("Emit code for the motion video ISA extension")}, \
218 {"no-max", -MASK_MAX, ""}, \
220 N_("Emit code for the fp move and sqrt ISA extension")}, \
221 {"no-fix", -MASK_FIX, ""}, \
222 {"cix", MASK_CIX, N_("Emit code for the counting ISA extension")}, \
223 {"no-cix", -MASK_CIX, ""}, \
224 {"", TARGET_DEFAULT | TARGET_CPU_DEFAULT, ""} }
226 #define TARGET_DEFAULT MASK_FP|MASK_FPREGS
228 #ifndef TARGET_CPU_DEFAULT
229 #define TARGET_CPU_DEFAULT 0
232 /* This macro is similar to `TARGET_SWITCHES' but defines names of
233 command options that have values. Its definition is an initializer
234 with a subgrouping for each command option.
236 Each subgrouping contains a string constant, that defines the fixed
237 part of the option name, and the address of a variable. The
238 variable, type `char *', is set to the variable part of the given
239 option if the fixed part matches. The actual option name is made
240 by appending `-m' to the specified name.
242 Here is an example which defines `-mshort-data-NUMBER'. If the
243 given option is `-mshort-data-512', the variable `m88k_short_data'
244 will be set to the string `"512"'.
246 extern char *m88k_short_data;
247 #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */
249 extern const char *alpha_cpu_string; /* For -mcpu= */
250 extern const char *alpha_tune_string; /* For -mtune= */
251 extern const char *alpha_fprm_string; /* For -mfp-rounding-mode=[n|m|c|d] */
252 extern const char *alpha_fptm_string; /* For -mfp-trap-mode=[n|u|su|sui] */
253 extern const char *alpha_tp_string; /* For -mtrap-precision=[p|f|i] */
254 extern const char *alpha_mlat_string; /* For -mmemory-latency= */
256 #define TARGET_OPTIONS \
258 {"cpu=", &alpha_cpu_string, \
259 N_("Use features of and schedule given CPU")}, \
260 {"tune=", &alpha_tune_string, \
261 N_("Schedule given CPU")}, \
262 {"fp-rounding-mode=", &alpha_fprm_string, \
263 N_("Control the generated fp rounding mode")}, \
264 {"fp-trap-mode=", &alpha_fptm_string, \
265 N_("Control the IEEE trap mode")}, \
266 {"trap-precision=", &alpha_tp_string, \
267 N_("Control the precision given to fp exceptions")}, \
268 {"memory-latency=", &alpha_mlat_string, \
269 N_("Tune expected memory latency")}, \
272 /* Attempt to describe CPU characteristics to the preprocessor. */
274 /* Corresponding to amask... */
275 #define CPP_AM_BWX_SPEC "-D__alpha_bwx__ -Acpu=bwx"
276 #define CPP_AM_MAX_SPEC "-D__alpha_max__ -Acpu=max"
277 #define CPP_AM_FIX_SPEC "-D__alpha_fix__ -Acpu=fix"
278 #define CPP_AM_CIX_SPEC "-D__alpha_cix__ -Acpu=cix"
280 /* Corresponding to implver... */
281 #define CPP_IM_EV4_SPEC "-D__alpha_ev4__ -Acpu=ev4"
282 #define CPP_IM_EV5_SPEC "-D__alpha_ev5__ -Acpu=ev5"
283 #define CPP_IM_EV6_SPEC "-D__alpha_ev6__ -Acpu=ev6"
285 /* Common combinations. */
286 #define CPP_CPU_EV4_SPEC "%(cpp_im_ev4)"
287 #define CPP_CPU_EV5_SPEC "%(cpp_im_ev5)"
288 #define CPP_CPU_EV56_SPEC "%(cpp_im_ev5) %(cpp_am_bwx)"
289 #define CPP_CPU_PCA56_SPEC "%(cpp_im_ev5) %(cpp_am_bwx) %(cpp_am_max)"
290 #define CPP_CPU_EV6_SPEC \
291 "%(cpp_im_ev6) %(cpp_am_bwx) %(cpp_am_max) %(cpp_am_fix)"
292 #define CPP_CPU_EV67_SPEC \
293 "%(cpp_im_ev6) %(cpp_am_bwx) %(cpp_am_max) %(cpp_am_fix) %(cpp_am_cix)"
295 #ifndef CPP_CPU_DEFAULT_SPEC
296 # if TARGET_CPU_DEFAULT & MASK_CPU_EV6
297 # if TARGET_CPU_DEFAULT & MASK_CIX
298 # define CPP_CPU_DEFAULT_SPEC CPP_CPU_EV67_SPEC
300 # define CPP_CPU_DEFAULT_SPEC CPP_CPU_EV6_SPEC
303 # if TARGET_CPU_DEFAULT & MASK_CPU_EV5
304 # if TARGET_CPU_DEFAULT & MASK_MAX
305 # define CPP_CPU_DEFAULT_SPEC CPP_CPU_PCA56_SPEC
307 # if TARGET_CPU_DEFAULT & MASK_BWX
308 # define CPP_CPU_DEFAULT_SPEC CPP_CPU_EV56_SPEC
310 # define CPP_CPU_DEFAULT_SPEC CPP_CPU_EV5_SPEC
314 # define CPP_CPU_DEFAULT_SPEC CPP_CPU_EV4_SPEC
317 #endif /* CPP_CPU_DEFAULT_SPEC */
320 #define CPP_CPU_SPEC "\
321 %{!undef:-Acpu=alpha -Amachine=alpha -D__alpha -D__alpha__ \
322 %{mcpu=ev4|mcpu=21064:%(cpp_cpu_ev4) }\
323 %{mcpu=ev5|mcpu=21164:%(cpp_cpu_ev5) }\
324 %{mcpu=ev56|mcpu=21164a:%(cpp_cpu_ev56) }\
325 %{mcpu=pca56|mcpu=21164pc|mcpu=21164PC:%(cpp_cpu_pca56) }\
326 %{mcpu=ev6|mcpu=21264:%(cpp_cpu_ev6) }\
327 %{mcpu=ev67|mcpu=21264a:%(cpp_cpu_ev67) }\
328 %{!mcpu*:%(cpp_cpu_default) }}"
331 /* This macro defines names of additional specifications to put in the
332 specs that can be used in various specifications like CC1_SPEC. Its
333 definition is an initializer with a subgrouping for each command option.
335 Each subgrouping contains a string constant, that defines the
336 specification name, and a string constant that used by the GNU CC driver
339 Do not define this macro if it does not need to do anything. */
341 #ifndef SUBTARGET_EXTRA_SPECS
342 #define SUBTARGET_EXTRA_SPECS
345 #define EXTRA_SPECS \
346 { "cpp_am_bwx", CPP_AM_BWX_SPEC }, \
347 { "cpp_am_max", CPP_AM_MAX_SPEC }, \
348 { "cpp_am_fix", CPP_AM_FIX_SPEC }, \
349 { "cpp_am_cix", CPP_AM_CIX_SPEC }, \
350 { "cpp_im_ev4", CPP_IM_EV4_SPEC }, \
351 { "cpp_im_ev5", CPP_IM_EV5_SPEC }, \
352 { "cpp_im_ev6", CPP_IM_EV6_SPEC }, \
353 { "cpp_cpu_ev4", CPP_CPU_EV4_SPEC }, \
354 { "cpp_cpu_ev5", CPP_CPU_EV5_SPEC }, \
355 { "cpp_cpu_ev56", CPP_CPU_EV56_SPEC }, \
356 { "cpp_cpu_pca56", CPP_CPU_PCA56_SPEC }, \
357 { "cpp_cpu_ev6", CPP_CPU_EV6_SPEC }, \
358 { "cpp_cpu_ev67", CPP_CPU_EV67_SPEC }, \
359 { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \
360 { "cpp_cpu", CPP_CPU_SPEC }, \
361 { "cpp_subtarget", CPP_SUBTARGET_SPEC }, \
362 SUBTARGET_EXTRA_SPECS
365 /* Sometimes certain combinations of command options do not make sense
366 on a particular target machine. You can define a macro
367 `OVERRIDE_OPTIONS' to take account of this. This macro, if
368 defined, is executed once just after all the command options have
371 On the Alpha, it is used to translate target-option strings into
374 #define OVERRIDE_OPTIONS override_options ()
377 /* Define this macro to change register usage conditional on target flags.
379 On the Alpha, we use this to disable the floating-point registers when
382 #define CONDITIONAL_REGISTER_USAGE \
383 if (! TARGET_FPREGS) \
384 for (i = 32; i < 63; i++) \
385 fixed_regs[i] = call_used_regs[i] = 1;
387 /* Show we can debug even without a frame pointer. */
388 #define CAN_DEBUG_WITHOUT_FP
390 /* target machine storage layout */
392 /* Define to enable software floating point emulation. */
393 #define REAL_ARITHMETIC
395 /* The following #defines are used when compiling the routines in
396 libgcc1.c. Since the Alpha calling conventions require single
397 precision floats to be passed in the floating-point registers
398 (rather than in the general registers) we have to build the
399 libgcc1.c routines in such a way that they know the actual types
400 of their formal arguments and the actual types of their return
401 values. Otherwise, gcc will generate calls to the libgcc1.c
402 routines, passing arguments in the floating-point registers,
403 but the libgcc1.c routines will expect their arguments on the
404 stack (where the Alpha calling conventions require structs &
405 unions to be passed). */
407 #define FLOAT_VALUE_TYPE double
408 #define INTIFY(FLOATVAL) (FLOATVAL)
409 #define FLOATIFY(INTVAL) (INTVAL)
410 #define FLOAT_ARG_TYPE double
412 /* Define the size of `int'. The default is the same as the word size. */
413 #define INT_TYPE_SIZE 32
415 /* Define the size of `long long'. The default is the twice the word size. */
416 #define LONG_LONG_TYPE_SIZE 64
418 /* The two floating-point formats we support are S-floating, which is
419 4 bytes, and T-floating, which is 8 bytes. `float' is S and `double'
420 and `long double' are T. */
422 #define FLOAT_TYPE_SIZE 32
423 #define DOUBLE_TYPE_SIZE 64
424 #define LONG_DOUBLE_TYPE_SIZE 64
426 #define WCHAR_TYPE "unsigned int"
427 #define WCHAR_TYPE_SIZE 32
429 /* Define this macro if it is advisable to hold scalars in registers
430 in a wider mode than that declared by the program. In such cases,
431 the value is constrained to be within the bounds of the declared
432 type, but kept valid in the wider mode. The signedness of the
433 extension may differ from that of the type.
435 For Alpha, we always store objects in a full register. 32-bit objects
436 are always sign-extended, but smaller objects retain their signedness. */
438 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
439 if (GET_MODE_CLASS (MODE) == MODE_INT \
440 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
442 if ((MODE) == SImode) \
447 /* Define this if function arguments should also be promoted using the above
450 #define PROMOTE_FUNCTION_ARGS
452 /* Likewise, if the function return value is promoted. */
454 #define PROMOTE_FUNCTION_RETURN
456 /* Define this if most significant bit is lowest numbered
457 in instructions that operate on numbered bit-fields.
459 There are no such instructions on the Alpha, but the documentation
461 #define BITS_BIG_ENDIAN 0
463 /* Define this if most significant byte of a word is the lowest numbered.
464 This is false on the Alpha. */
465 #define BYTES_BIG_ENDIAN 0
467 /* Define this if most significant word of a multiword number is lowest
470 For Alpha we can decide arbitrarily since there are no machine instructions
471 for them. Might as well be consistent with bytes. */
472 #define WORDS_BIG_ENDIAN 0
474 /* number of bits in an addressable storage unit */
475 #define BITS_PER_UNIT 8
477 /* Width in bits of a "word", which is the contents of a machine register.
478 Note that this is not necessarily the width of data type `int';
479 if using 16-bit ints on a 68000, this would still be 32.
480 But on a machine with 16-bit registers, this would be 16. */
481 #define BITS_PER_WORD 64
483 /* Width of a word, in units (bytes). */
484 #define UNITS_PER_WORD 8
486 /* Width in bits of a pointer.
487 See also the macro `Pmode' defined below. */
488 #define POINTER_SIZE 64
490 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
491 #define PARM_BOUNDARY 64
493 /* Boundary (in *bits*) on which stack pointer should be aligned. */
494 #define STACK_BOUNDARY 64
496 /* Allocation boundary (in *bits*) for the code of a function. */
497 #define FUNCTION_BOUNDARY 128
499 /* Alignment of field after `int : 0' in a structure. */
500 #define EMPTY_FIELD_BOUNDARY 64
502 /* Every structure's size must be a multiple of this. */
503 #define STRUCTURE_SIZE_BOUNDARY 8
505 /* A bitfield declared as `int' forces `int' alignment for the struct. */
506 #define PCC_BITFIELD_TYPE_MATTERS 1
508 /* Align loop starts for optimal branching.
510 ??? Kludge this and the next macro for the moment by not doing anything if
511 we don't optimize and also if we are writing ECOFF symbols to work around
512 a bug in DEC's assembler. */
514 #define LOOP_ALIGN(LABEL) \
515 (optimize > 0 && write_symbols != SDB_DEBUG ? 4 : 0)
517 /* This is how to align an instruction for optimal branching. On
518 Alpha we'll get better performance by aligning on an octaword
521 #define LABEL_ALIGN_AFTER_BARRIER(FILE) \
522 (optimize > 0 && write_symbols != SDB_DEBUG ? 4 : 0)
524 /* No data type wants to be aligned rounder than this. */
525 #define BIGGEST_ALIGNMENT 128
527 /* For atomic access to objects, must have at least 32-bit alignment
528 unless the machine has byte operations. */
529 #define MINIMUM_ATOMIC_ALIGNMENT ((unsigned int) (TARGET_BWX ? 8 : 32))
531 /* Align all constants and variables to at least a word boundary so
532 we can pick up pieces of them faster. */
533 /* ??? Only if block-move stuff knows about different source/destination
536 #define CONSTANT_ALIGNMENT(EXP, ALIGN) MAX ((ALIGN), BITS_PER_WORD)
537 #define DATA_ALIGNMENT(EXP, ALIGN) MAX ((ALIGN), BITS_PER_WORD)
540 /* Set this non-zero if move instructions will actually fail to work
541 when given unaligned data.
543 Since we get an error message when we do one, call them invalid. */
545 #define STRICT_ALIGNMENT 1
547 /* Set this non-zero if unaligned move instructions are extremely slow.
549 On the Alpha, they trap. */
551 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
553 /* Standard register usage. */
555 /* Number of actual hardware registers.
556 The hardware registers are assigned numbers for the compiler
557 from 0 to just below FIRST_PSEUDO_REGISTER.
558 All registers that the compiler knows about must be given numbers,
559 even those that are not normally considered general registers.
561 We define all 32 integer registers, even though $31 is always zero,
562 and all 32 floating-point registers, even though $f31 is also
563 always zero. We do not bother defining the FP status register and
564 there are no other registers.
566 Since $31 is always zero, we will use register number 31 as the
567 argument pointer. It will never appear in the generated code
568 because we will always be eliminating it in favor of the stack
569 pointer or hardware frame pointer.
571 Likewise, we use $f31 for the frame pointer, which will always
572 be eliminated in favor of the hardware frame pointer or the
575 #define FIRST_PSEUDO_REGISTER 64
577 /* 1 for registers that have pervasive standard uses
578 and are not available for the register allocator. */
580 #define FIXED_REGISTERS \
581 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
582 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, \
583 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
584 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 }
586 /* 1 for registers not available across function calls.
587 These must include the FIXED_REGISTERS and also any
588 registers that can be used without being saved.
589 The latter must include the registers where values are returned
590 and the register where structure-value addresses are passed.
591 Aside from that, you can include as many other registers as you like. */
592 #define CALL_USED_REGISTERS \
593 {1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
594 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, \
595 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, \
596 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }
598 /* List the order in which to allocate registers. Each register must be
599 listed once, even those in FIXED_REGISTERS.
601 We allocate in the following order:
602 $f10-$f15 (nonsaved floating-point register)
604 $f21-$f16 (likewise, but input args)
605 $f0 (nonsaved, but return value)
606 $f1 (nonsaved, but immediate before saved)
607 $f2-$f9 (saved floating-point registers)
608 $1-$8 (nonsaved integer registers)
611 $0 (likewise, but return value)
612 $21-$16 (likewise, but input args)
613 $27 (procedure value in OSF, nonsaved in NT)
614 $9-$14 (saved integer registers)
618 $30, $31, $f31 (stack pointer and always zero/ap & fp) */
620 #define REG_ALLOC_ORDER \
621 {42, 43, 44, 45, 46, 47, \
622 54, 55, 56, 57, 58, 59, 60, 61, 62, \
623 53, 52, 51, 50, 49, 48, \
625 34, 35, 36, 37, 38, 39, 40, 41, \
626 1, 2, 3, 4, 5, 6, 7, 8, \
630 21, 20, 19, 18, 17, 16, \
632 9, 10, 11, 12, 13, 14, \
638 /* Return number of consecutive hard regs needed starting at reg REGNO
639 to hold something of mode MODE.
640 This is ordinarily the length in words of a value of mode MODE
641 but can be less for certain modes in special long registers. */
643 #define HARD_REGNO_NREGS(REGNO, MODE) \
644 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
646 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
647 On Alpha, the integer registers can hold any mode. The floating-point
648 registers can hold 32-bit and 64-bit integers as well, but not 16-bit
651 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
652 ((REGNO) >= 32 && (REGNO) <= 62 \
653 ? GET_MODE_UNIT_SIZE (MODE) == 8 || GET_MODE_UNIT_SIZE (MODE) == 4 \
656 /* A C expression that is nonzero if a value of mode
657 MODE1 is accessible in mode MODE2 without copying.
659 This asymmetric test is true when MODE1 could be put
660 in an FP register but MODE2 could not. */
662 #define MODES_TIEABLE_P(MODE1, MODE2) \
663 (HARD_REGNO_MODE_OK (32, (MODE1)) \
664 ? HARD_REGNO_MODE_OK (32, (MODE2)) \
667 /* Specify the registers used for certain standard purposes.
668 The values of these macros are register numbers. */
670 /* Alpha pc isn't overloaded on a register that the compiler knows about. */
671 /* #define PC_REGNUM */
673 /* Register to use for pushing function arguments. */
674 #define STACK_POINTER_REGNUM 30
676 /* Base register for access to local variables of the function. */
677 #define HARD_FRAME_POINTER_REGNUM 15
679 /* Value should be nonzero if functions must have frame pointers.
680 Zero means the frame pointer need not be set up (and parms
681 may be accessed via the stack pointer) in functions that seem suitable.
682 This is computed in `reload', in reload1.c. */
683 #define FRAME_POINTER_REQUIRED 0
685 /* Base register for access to arguments of the function. */
686 #define ARG_POINTER_REGNUM 31
688 /* Base register for access to local variables of function. */
689 #define FRAME_POINTER_REGNUM 63
691 /* Register in which static-chain is passed to a function.
693 For the Alpha, this is based on an example; the calling sequence
694 doesn't seem to specify this. */
695 #define STATIC_CHAIN_REGNUM 1
697 /* Register in which address to store a structure value
698 arrives in the function. On the Alpha, the address is passed
699 as a hidden argument. */
700 #define STRUCT_VALUE 0
702 /* Define the classes of registers for register constraints in the
703 machine description. Also define ranges of constants.
705 One of the classes must always be named ALL_REGS and include all hard regs.
706 If there is more than one class, another class must be named NO_REGS
707 and contain no registers.
709 The name GENERAL_REGS must be the name of a class (or an alias for
710 another name such as ALL_REGS). This is the class of registers
711 that is allowed by "g" or "r" in a register constraint.
712 Also, registers outside this class are allocated only when
713 instructions express preferences for them.
715 The classes must be numbered in nondecreasing order; that is,
716 a larger-numbered class must never be contained completely
717 in a smaller-numbered class.
719 For any two classes, it is very desirable that there be another
720 class that represents their union. */
722 enum reg_class { NO_REGS, PV_REG, GENERAL_REGS, FLOAT_REGS, ALL_REGS,
725 #define N_REG_CLASSES (int) LIM_REG_CLASSES
727 /* Give names of register classes as strings for dump file. */
729 #define REG_CLASS_NAMES \
730 {"NO_REGS", "PV_REG", "GENERAL_REGS", "FLOAT_REGS", "ALL_REGS" }
732 /* Define which registers fit in which classes.
733 This is an initializer for a vector of HARD_REG_SET
734 of length N_REG_CLASSES. */
736 #define REG_CLASS_CONTENTS \
737 { {0, 0}, {0x08000000, 0}, {~0, 0x80000000}, {0, 0x7fffffff}, {~0, ~0} }
739 /* The same information, inverted:
740 Return the class number of the smallest class containing
741 reg number REGNO. This could be a conditional expression
742 or could index an array. */
744 #define REGNO_REG_CLASS(REGNO) \
745 ((REGNO) == 27 ? PV_REG \
746 : (REGNO) >= 32 && (REGNO) <= 62 ? FLOAT_REGS \
749 /* The class value for index registers, and the one for base regs. */
750 #define INDEX_REG_CLASS NO_REGS
751 #define BASE_REG_CLASS GENERAL_REGS
753 /* Get reg_class from a letter such as appears in the machine description. */
755 #define REG_CLASS_FROM_LETTER(C) \
756 ((C) == 'c' ? PV_REG : (C) == 'f' ? FLOAT_REGS : NO_REGS)
758 /* Define this macro to change register usage conditional on target flags. */
759 /* #define CONDITIONAL_REGISTER_USAGE */
761 /* The letters I, J, K, L, M, N, O, and P in a register constraint string
762 can be used to stand for particular ranges of immediate operands.
763 This macro defines what the ranges are.
764 C is the letter, and VALUE is a constant value.
765 Return 1 if VALUE is in the range specified by C.
768 `I' is used for the range of constants most insns can contain.
769 `J' is the constant zero.
770 `K' is used for the constant in an LDA insn.
771 `L' is used for the constant in a LDAH insn.
772 `M' is used for the constants that can be AND'ed with using a ZAP insn.
773 `N' is used for complemented 8-bit constants.
774 `O' is used for negated 8-bit constants.
775 `P' is used for the constants 1, 2 and 3. */
777 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
778 ((C) == 'I' ? (unsigned HOST_WIDE_INT) (VALUE) < 0x100 \
779 : (C) == 'J' ? (VALUE) == 0 \
780 : (C) == 'K' ? (unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000 \
781 : (C) == 'L' ? (((VALUE) & 0xffff) == 0 \
782 && (((VALUE)) >> 31 == -1 || (VALUE) >> 31 == 0)) \
783 : (C) == 'M' ? zap_mask (VALUE) \
784 : (C) == 'N' ? (unsigned HOST_WIDE_INT) (~ (VALUE)) < 0x100 \
785 : (C) == 'O' ? (unsigned HOST_WIDE_INT) (- (VALUE)) < 0x100 \
786 : (C) == 'P' ? (VALUE) == 1 || (VALUE) == 2 || (VALUE) == 3 \
789 /* Similar, but for floating or large integer constants, and defining letters
790 G and H. Here VALUE is the CONST_DOUBLE rtx itself.
792 For Alpha, `G' is the floating-point constant zero. `H' is a CONST_DOUBLE
793 that is the operand of a ZAP insn. */
795 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
796 ((C) == 'G' ? (GET_MODE_CLASS (GET_MODE (VALUE)) == MODE_FLOAT \
797 && (VALUE) == CONST0_RTX (GET_MODE (VALUE))) \
798 : (C) == 'H' ? (GET_MODE (VALUE) == VOIDmode \
799 && zap_mask (CONST_DOUBLE_LOW (VALUE)) \
800 && zap_mask (CONST_DOUBLE_HIGH (VALUE))) \
803 /* Optional extra constraints for this machine.
805 For the Alpha, `Q' means that this is a memory operand but not a
806 reference to an unaligned location.
808 `R' is a SYMBOL_REF that has SYMBOL_REF_FLAG set or is the current
811 'S' is a 6-bit constant (valid for a shift insn). */
813 #define EXTRA_CONSTRAINT(OP, C) \
814 ((C) == 'Q' ? normal_memory_operand (OP, VOIDmode) \
815 : (C) == 'R' ? current_file_function_operand (OP, Pmode) \
816 : (C) == 'S' ? (GET_CODE (OP) == CONST_INT \
817 && (unsigned HOST_WIDE_INT) INTVAL (OP) < 64) \
820 /* Given an rtx X being reloaded into a reg required to be
821 in class CLASS, return the class of reg to actually use.
822 In general this is just CLASS; but on some machines
823 in some cases it is preferable to use a more restrictive class.
825 On the Alpha, all constants except zero go into a floating-point
826 register via memory. */
828 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
829 (CONSTANT_P (X) && (X) != const0_rtx && (X) != CONST0_RTX (GET_MODE (X)) \
830 ? ((CLASS) == FLOAT_REGS || (CLASS) == NO_REGS ? NO_REGS : GENERAL_REGS)\
833 /* Loading and storing HImode or QImode values to and from memory
834 usually requires a scratch register. The exceptions are loading
835 QImode and HImode from an aligned address to a general register
836 unless byte instructions are permitted.
837 We also cannot load an unaligned address or a paradoxical SUBREG into an
840 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,IN) \
841 secondary_reload_class((CLASS), (MODE), (IN), 1)
843 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,OUT) \
844 secondary_reload_class((CLASS), (MODE), (OUT), 0)
846 /* If we are copying between general and FP registers, we need a memory
847 location unless the FIX extension is available. */
849 #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
850 (! TARGET_FIX && (CLASS1) != (CLASS2))
852 /* Specify the mode to be used for memory when a secondary memory
853 location is needed. If MODE is floating-point, use it. Otherwise,
854 widen to a word like the default. This is needed because we always
855 store integers in FP registers in quadword format. This whole
856 area is very tricky! */
857 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
858 (GET_MODE_CLASS (MODE) == MODE_FLOAT ? (MODE) \
859 : GET_MODE_SIZE (MODE) >= 4 ? (MODE) \
860 : mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0))
862 /* Return the maximum number of consecutive registers
863 needed to represent mode MODE in a register of class CLASS. */
865 #define CLASS_MAX_NREGS(CLASS, MODE) \
866 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
868 /* If defined, gives a class of registers that cannot be used as the
869 operand of a SUBREG that changes the mode of the object illegally. */
871 #define CLASS_CANNOT_CHANGE_MODE FLOAT_REGS
873 /* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE. */
875 #define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \
876 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO))
878 /* Define the cost of moving between registers of various classes. Moving
879 between FLOAT_REGS and anything else except float regs is expensive.
880 In fact, we make it quite expensive because we really don't want to
881 do these moves unless it is clearly worth it. Optimizations may
882 reduce the impact of not being able to allocate a pseudo to a
885 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
886 (((CLASS1) == FLOAT_REGS) == ((CLASS2) == FLOAT_REGS) \
888 : TARGET_FIX ? 3 : 4+2*alpha_memory_latency)
890 /* A C expressions returning the cost of moving data of MODE from a register to
893 On the Alpha, bump this up a bit. */
895 extern int alpha_memory_latency;
896 #define MEMORY_MOVE_COST(MODE,CLASS,IN) (2*alpha_memory_latency)
898 /* Provide the cost of a branch. Exact meaning under development. */
899 #define BRANCH_COST 5
901 /* Adjust the cost of dependencies. */
903 #define ADJUST_COST(INSN,LINK,DEP,COST) \
904 (COST) = alpha_adjust_cost (INSN, LINK, DEP, COST)
906 /* Stack layout; function entry, exit and calling. */
908 /* Define this if pushing a word on the stack
909 makes the stack pointer a smaller address. */
910 #define STACK_GROWS_DOWNWARD
912 /* Define this if the nominal address of the stack frame
913 is at the high-address end of the local variables;
914 that is, each additional local variable allocated
915 goes at a more negative offset in the frame. */
916 /* #define FRAME_GROWS_DOWNWARD */
918 /* Offset within stack frame to start allocating local variables at.
919 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
920 first local allocated. Otherwise, it is the offset to the BEGINNING
921 of the first local allocated. */
923 #define STARTING_FRAME_OFFSET 0
925 /* If we generate an insn to push BYTES bytes,
926 this says how many the stack pointer really advances by.
927 On Alpha, don't define this because there are no push insns. */
928 /* #define PUSH_ROUNDING(BYTES) */
930 /* Define this to be nonzero if stack checking is built into the ABI. */
931 #define STACK_CHECK_BUILTIN 1
933 /* Define this if the maximum size of all the outgoing args is to be
934 accumulated and pushed during the prologue. The amount can be
935 found in the variable current_function_outgoing_args_size. */
936 #define ACCUMULATE_OUTGOING_ARGS 1
938 /* Offset of first parameter from the argument pointer register value. */
940 #define FIRST_PARM_OFFSET(FNDECL) 0
942 /* Definitions for register eliminations.
944 We have two registers that can be eliminated on the Alpha. First, the
945 frame pointer register can often be eliminated in favor of the stack
946 pointer register. Secondly, the argument pointer register can always be
947 eliminated; it is replaced with either the stack or frame pointer. */
949 /* This is an array of structures. Each structure initializes one pair
950 of eliminable registers. The "from" register number is given first,
951 followed by "to". Eliminations of the same "from" register are listed
952 in order of preference. */
954 #define ELIMINABLE_REGS \
955 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
956 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
957 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
958 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
960 /* Given FROM and TO register numbers, say whether this elimination is allowed.
961 Frame pointer elimination is automatically handled.
963 All eliminations are valid since the cases where FP can't be
964 eliminated are already handled. */
966 #define CAN_ELIMINATE(FROM, TO) 1
968 /* Round up to a multiple of 16 bytes. */
969 #define ALPHA_ROUND(X) (((X) + 15) & ~ 15)
971 /* Define the offset between two registers, one to be eliminated, and the other
972 its replacement, at the start of a routine. */
973 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
974 { if ((FROM) == FRAME_POINTER_REGNUM) \
975 (OFFSET) = (ALPHA_ROUND (current_function_outgoing_args_size) \
976 + alpha_sa_size ()); \
977 else if ((FROM) == ARG_POINTER_REGNUM) \
978 (OFFSET) = (ALPHA_ROUND (current_function_outgoing_args_size) \
980 + (ALPHA_ROUND (get_frame_size () \
981 + current_function_pretend_args_size) \
982 - current_function_pretend_args_size)); \
987 /* Define this if stack space is still allocated for a parameter passed
989 /* #define REG_PARM_STACK_SPACE */
991 /* Value is the number of bytes of arguments automatically
992 popped when returning from a subroutine call.
993 FUNDECL is the declaration node of the function (as a tree),
994 FUNTYPE is the data type of the function (as a tree),
995 or for a library call it is an identifier node for the subroutine name.
996 SIZE is the number of bytes of arguments passed on the stack. */
998 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1000 /* Define how to find the value returned by a function.
1001 VALTYPE is the data type of the value (as a tree).
1002 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1003 otherwise, FUNC is 0.
1005 On Alpha the value is found in $0 for integer functions and
1006 $f0 for floating-point functions. */
1008 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1009 gen_rtx_REG (((INTEGRAL_TYPE_P (VALTYPE) \
1010 && TYPE_PRECISION (VALTYPE) < BITS_PER_WORD) \
1011 || POINTER_TYPE_P (VALTYPE)) \
1012 ? word_mode : TYPE_MODE (VALTYPE), \
1014 && (TREE_CODE (VALTYPE) == REAL_TYPE \
1015 || TREE_CODE (VALTYPE) == COMPLEX_TYPE)) \
1018 /* Define how to find the value returned by a library function
1019 assuming the value has mode MODE. */
1021 #define LIBCALL_VALUE(MODE) \
1022 gen_rtx_REG (MODE, \
1024 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1025 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1028 /* The definition of this macro implies that there are cases where
1029 a scalar value cannot be returned in registers.
1031 For the Alpha, any structure or union type is returned in memory, as
1032 are integers whose size is larger than 64 bits. */
1034 #define RETURN_IN_MEMORY(TYPE) \
1035 (TYPE_MODE (TYPE) == BLKmode \
1036 || TYPE_MODE (TYPE) == TFmode \
1037 || TYPE_MODE (TYPE) == TCmode \
1038 || (TREE_CODE (TYPE) == INTEGER_TYPE && TYPE_PRECISION (TYPE) > 64))
1040 /* 1 if N is a possible register number for a function value
1041 as seen by the caller. */
1043 #define FUNCTION_VALUE_REGNO_P(N) \
1044 ((N) == 0 || (N) == 1 || (N) == 32 || (N) == 33)
1046 /* 1 if N is a possible register number for function argument passing.
1047 On Alpha, these are $16-$21 and $f16-$f21. */
1049 #define FUNCTION_ARG_REGNO_P(N) \
1050 (((N) >= 16 && (N) <= 21) || ((N) >= 16 + 32 && (N) <= 21 + 32))
1052 /* Define a data type for recording info about an argument list
1053 during the scan of that argument list. This data type should
1054 hold all necessary information about the function itself
1055 and about the args processed so far, enough to enable macros
1056 such as FUNCTION_ARG to determine where the next arg should go.
1058 On Alpha, this is a single integer, which is a number of words
1059 of arguments scanned so far.
1060 Thus 6 or more means all following args should go on the stack. */
1062 #define CUMULATIVE_ARGS int
1064 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1065 for a call to a function whose data type is FNTYPE.
1066 For a library call, FNTYPE is 0. */
1068 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) (CUM) = 0
1070 /* Define intermediate macro to compute the size (in registers) of an argument
1073 #define ALPHA_ARG_SIZE(MODE, TYPE, NAMED) \
1074 ((MODE) == TFmode || (MODE) == TCmode ? 1 \
1075 : (((MODE) == BLKmode ? int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) \
1076 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
1078 /* Update the data in CUM to advance over an argument
1079 of mode MODE and data type TYPE.
1080 (TYPE is null for libcalls where that information may not be available.) */
1082 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1083 if (MUST_PASS_IN_STACK (MODE, TYPE)) \
1086 (CUM) += ALPHA_ARG_SIZE (MODE, TYPE, NAMED)
1088 /* Determine where to put an argument to a function.
1089 Value is zero to push the argument on the stack,
1090 or a hard register in which to store the argument.
1092 MODE is the argument's machine mode.
1093 TYPE is the data type of the argument (as a tree).
1094 This is null for libcalls where that information may
1096 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1097 the preceding args and about the function being called.
1098 NAMED is nonzero if this argument is a named parameter
1099 (otherwise it is an extra parameter matching an ellipsis).
1101 On Alpha the first 6 words of args are normally in registers
1102 and the rest are pushed. */
1104 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1105 function_arg((CUM), (MODE), (TYPE), (NAMED))
1107 /* A C expression that indicates when an argument must be passed by
1108 reference. If nonzero for an argument, a copy of that argument is
1109 made in memory and a pointer to the argument is passed instead of
1110 the argument itself. The pointer is passed in whatever way is
1111 appropriate for passing a pointer to that type. */
1113 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1114 ((MODE) == TFmode || (MODE) == TCmode)
1116 /* Specify the padding direction of arguments.
1118 On the Alpha, we must pad upwards in order to be able to pass args in
1121 #define FUNCTION_ARG_PADDING(MODE, TYPE) upward
1123 /* For an arg passed partly in registers and partly in memory,
1124 this is the number of registers used.
1125 For args passed entirely in registers or entirely in memory, zero. */
1127 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1128 ((CUM) < 6 && 6 < (CUM) + ALPHA_ARG_SIZE (MODE, TYPE, NAMED) \
1131 /* Perform any needed actions needed for a function that is receiving a
1132 variable number of arguments.
1136 MODE and TYPE are the mode and type of the current parameter.
1138 PRETEND_SIZE is a variable that should be set to the amount of stack
1139 that must be pushed by the prolog to pretend that our caller pushed
1142 Normally, this macro will push all remaining incoming registers on the
1143 stack and set PRETEND_SIZE to the length of the registers pushed.
1145 On the Alpha, we allocate space for all 12 arg registers, but only
1146 push those that are remaining.
1148 However, if NO registers need to be saved, don't allocate any space.
1149 This is not only because we won't need the space, but because AP includes
1150 the current_pretend_args_size and we don't want to mess up any
1151 ap-relative addresses already made.
1153 If we are not to use the floating-point registers, save the integer
1154 registers where we would put the floating-point registers. This is
1155 not the most efficient way to implement varargs with just one register
1156 class, but it isn't worth doing anything more efficient in this rare
1159 #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
1164 rtx tmp; int set = get_varargs_alias_set (); \
1165 tmp = gen_rtx_MEM (BLKmode, \
1166 plus_constant (virtual_incoming_args_rtx, \
1167 ((CUM) + 6)* UNITS_PER_WORD)); \
1168 MEM_ALIAS_SET (tmp) = set; \
1169 move_block_from_reg \
1171 6 - (CUM), (6 - (CUM)) * UNITS_PER_WORD); \
1173 tmp = gen_rtx_MEM (BLKmode, \
1174 plus_constant (virtual_incoming_args_rtx, \
1175 (CUM) * UNITS_PER_WORD)); \
1176 MEM_ALIAS_SET (tmp) = set; \
1177 move_block_from_reg \
1178 (16 + (TARGET_FPREGS ? 32 : 0) + CUM, tmp, \
1179 6 - (CUM), (6 - (CUM)) * UNITS_PER_WORD); \
1181 PRETEND_SIZE = 12 * UNITS_PER_WORD; \
1185 /* We do not allow indirect calls to be optimized into sibling calls, nor
1186 can we allow a call to a function in a different compilation unit to
1187 be optimized into a sibcall. Except if the function is known not to
1188 return, in which case our caller doesn't care what the gp is. */
1189 #define FUNCTION_OK_FOR_SIBCALL(DECL) \
1191 && ((TREE_ASM_WRITTEN (DECL) && !flag_pic) \
1192 || ! TREE_PUBLIC (DECL)))
1194 /* Try to output insns to set TARGET equal to the constant C if it can be
1195 done in less than N insns. Do all computations in MODE. Returns the place
1196 where the output has been placed if it can be done and the insns have been
1197 emitted. If it would take more than N insns, zero is returned and no
1198 insns and emitted. */
1200 /* Define the information needed to generate branch and scc insns. This is
1201 stored from the compare operation. Note that we can't use "rtx" here
1202 since it hasn't been defined! */
1204 struct alpha_compare
1206 struct rtx_def *op0, *op1;
1210 extern struct alpha_compare alpha_compare;
1212 /* Machine specific function data. */
1214 struct machine_function
1216 /* If non-null, this rtx holds the return address for the function. */
1217 struct rtx_def *ra_rtx;
1220 /* Make (or fake) .linkage entry for function call.
1221 IS_LOCAL is 0 if name is used in call, 1 if name is used in definition. */
1223 /* This macro defines the start of an assembly comment. */
1225 #define ASM_COMMENT_START " #"
1227 /* This macro produces the initial definition of a function. */
1229 #define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL) \
1230 alpha_start_function(FILE,NAME,DECL);
1232 /* This macro closes up a function definition for the assembler. */
1234 #define ASM_DECLARE_FUNCTION_SIZE(FILE,NAME,DECL) \
1235 alpha_end_function(FILE,NAME,DECL)
1237 /* This macro notes the end of the prologue. */
1239 #define FUNCTION_END_PROLOGUE(FILE) output_end_prologue (FILE)
1241 /* Output any profiling code before the prologue. */
1243 #define PROFILE_BEFORE_PROLOGUE 1
1245 /* Output assembler code to FILE to increment profiler label # LABELNO
1246 for profiling a function entry. Under OSF/1, profiling is enabled
1247 by simply passing -pg to the assembler and linker. */
1249 #define FUNCTION_PROFILER(FILE, LABELNO)
1251 /* Output assembler code to FILE to initialize this source file's
1252 basic block profiling info, if that has not already been done.
1253 This assumes that __bb_init_func doesn't garble a1-a5. */
1255 #define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \
1257 ASM_OUTPUT_REG_PUSH (FILE, 16); \
1258 fputs ("\tlda $16,$PBX32\n", (FILE)); \
1259 fputs ("\tldq $26,0($16)\n", (FILE)); \
1260 fputs ("\tbne $26,1f\n", (FILE)); \
1261 fputs ("\tlda $27,__bb_init_func\n", (FILE)); \
1262 fputs ("\tjsr $26,($27),__bb_init_func\n", (FILE)); \
1263 fputs ("\tldgp $29,0($26)\n", (FILE)); \
1264 fputs ("1:\n", (FILE)); \
1265 ASM_OUTPUT_REG_POP (FILE, 16); \
1268 /* Output assembler code to FILE to increment the entry-count for
1269 the BLOCKNO'th basic block in this source file. */
1271 #define BLOCK_PROFILER(FILE, BLOCKNO) \
1273 int blockn = (BLOCKNO); \
1274 fputs ("\tsubq $30,16,$30\n", (FILE)); \
1275 fputs ("\tstq $26,0($30)\n", (FILE)); \
1276 fputs ("\tstq $27,8($30)\n", (FILE)); \
1277 fputs ("\tlda $26,$PBX34\n", (FILE)); \
1278 fprintf ((FILE), "\tldq $27,%d($26)\n", 8*blockn); \
1279 fputs ("\taddq $27,1,$27\n", (FILE)); \
1280 fprintf ((FILE), "\tstq $27,%d($26)\n", 8*blockn); \
1281 fputs ("\tldq $26,0($30)\n", (FILE)); \
1282 fputs ("\tldq $27,8($30)\n", (FILE)); \
1283 fputs ("\taddq $30,16,$30\n", (FILE)); \
1287 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1288 the stack pointer does not matter. The value is tested only in
1289 functions that have frame pointers.
1290 No definition is equivalent to always zero. */
1292 #define EXIT_IGNORE_STACK 1
1294 /* Define registers used by the epilogue and return instruction. */
1296 #define EPILOGUE_USES(REGNO) ((REGNO) == 26)
1298 /* Output assembler code for a block containing the constant parts
1299 of a trampoline, leaving space for the variable parts.
1301 The trampoline should set the static chain pointer to value placed
1302 into the trampoline and should branch to the specified routine.
1303 Note that $27 has been set to the address of the trampoline, so we can
1304 use it for addressability of the two data items. Trampolines are always
1305 aligned to FUNCTION_BOUNDARY, which is 64 bits. */
1307 #define TRAMPOLINE_TEMPLATE(FILE) \
1309 fprintf (FILE, "\tldq $1,24($27)\n"); \
1310 fprintf (FILE, "\tldq $27,16($27)\n"); \
1311 fprintf (FILE, "\tjmp $31,($27),0\n"); \
1312 fprintf (FILE, "\tnop\n"); \
1313 fprintf (FILE, "\t.quad 0,0\n"); \
1316 /* Section in which to place the trampoline. On Alpha, instructions
1317 may only be placed in a text segment. */
1319 #define TRAMPOLINE_SECTION text_section
1321 /* Length in units of the trampoline for entering a nested function. */
1323 #define TRAMPOLINE_SIZE 32
1325 /* Emit RTL insns to initialize the variable parts of a trampoline.
1326 FNADDR is an RTX for the address of the function's pure code.
1327 CXT is an RTX for the static chain value for the function. */
1329 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1330 alpha_initialize_trampoline (TRAMP, FNADDR, CXT, 16, 24, 8)
1332 /* A C expression whose value is RTL representing the value of the return
1333 address for the frame COUNT steps up from the current frame.
1334 FRAMEADDR is the frame pointer of the COUNT frame, or the frame pointer of
1335 the COUNT-1 frame if RETURN_ADDR_IN_PREVIOUS_FRAME is defined. */
1337 #define RETURN_ADDR_RTX alpha_return_addr
1339 /* Before the prologue, RA lives in $26. */
1340 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, 26)
1341 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (26)
1343 /* Describe how we implement __builtin_eh_return. */
1344 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 16 : INVALID_REGNUM)
1345 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 28)
1346 #define EH_RETURN_HANDLER_RTX \
1347 gen_rtx_MEM (Pmode, plus_constant (stack_pointer_rtx, \
1348 current_function_outgoing_args_size))
1350 /* Addressing modes, and classification of registers for them. */
1352 /* #define HAVE_POST_INCREMENT 0 */
1353 /* #define HAVE_POST_DECREMENT 0 */
1355 /* #define HAVE_PRE_DECREMENT 0 */
1356 /* #define HAVE_PRE_INCREMENT 0 */
1358 /* Macros to check register numbers against specific register classes. */
1360 /* These assume that REGNO is a hard or pseudo reg number.
1361 They give nonzero only if REGNO is a hard reg of the suitable class
1362 or a pseudo reg currently allocated to a suitable hard reg.
1363 Since they use reg_renumber, they are safe only once reg_renumber
1364 has been allocated, which happens in local-alloc.c. */
1366 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
1367 #define REGNO_OK_FOR_BASE_P(REGNO) \
1368 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32 \
1369 || (REGNO) == 63 || reg_renumber[REGNO] == 63)
1371 /* Maximum number of registers that can appear in a valid memory address. */
1372 #define MAX_REGS_PER_ADDRESS 1
1374 /* Recognize any constant value that is a valid address. For the Alpha,
1375 there are only constants none since we want to use LDA to load any
1376 symbolic addresses into registers. */
1378 #define CONSTANT_ADDRESS_P(X) \
1379 (GET_CODE (X) == CONST_INT \
1380 && (unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
1382 /* Include all constant integers and constant doubles, but not
1383 floating-point, except for floating-point zero. */
1385 #define LEGITIMATE_CONSTANT_P(X) \
1386 (GET_MODE_CLASS (GET_MODE (X)) != MODE_FLOAT \
1387 || (X) == CONST0_RTX (GET_MODE (X)))
1389 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1390 and check its validity for a certain class.
1391 We have two alternate definitions for each of them.
1392 The usual definition accepts all pseudo regs; the other rejects
1393 them unless they have been allocated suitable hard regs.
1394 The symbol REG_OK_STRICT causes the latter definition to be used.
1396 Most source files want to accept pseudo regs in the hope that
1397 they will get allocated to the class that the insn wants them to be in.
1398 Source files for reload pass need to be strict.
1399 After reload, it makes no difference, since pseudo regs have
1400 been eliminated by then. */
1402 #ifndef REG_OK_STRICT
1404 /* Nonzero if X is a hard reg that can be used as an index
1405 or if it is a pseudo reg. */
1406 #define REG_OK_FOR_INDEX_P(X) 0
1408 /* Nonzero if X is a hard reg that can be used as a base reg
1409 or if it is a pseudo reg. */
1410 #define REG_OK_FOR_BASE_P(X) \
1411 (REGNO (X) < 32 || REGNO (X) == 63 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1413 /* ??? Nonzero if X is the frame pointer, or some virtual register
1414 that may eliminate to the frame pointer. These will be allowed to
1415 have offsets greater than 32K. This is done because register
1416 elimination offsets will change the hi/lo split, and if we split
1417 before reload, we will require additional instructions. */
1418 #define REG_OK_FP_BASE_P(X) \
1419 (REGNO (X) == 31 || REGNO (X) == 63 \
1420 || (REGNO (X) >= FIRST_PSEUDO_REGISTER \
1421 && REGNO (X) < LAST_VIRTUAL_REGISTER))
1425 /* Nonzero if X is a hard reg that can be used as an index. */
1426 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1428 /* Nonzero if X is a hard reg that can be used as a base reg. */
1429 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1431 #define REG_OK_FP_BASE_P(X) 0
1435 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1436 that is a valid memory address for an instruction.
1437 The MODE argument is the machine mode for the MEM expression
1438 that wants to use this address.
1440 For Alpha, we have either a constant address or the sum of a register
1441 and a constant address, or just a register. For DImode, any of those
1442 forms can be surrounded with an AND that clear the low-order three bits;
1443 this is an "unaligned" access.
1445 First define the basic valid address. */
1447 #define GO_IF_LEGITIMATE_SIMPLE_ADDRESS(MODE, X, ADDR) \
1450 if (GET_CODE (tmp) == SUBREG \
1451 && (GET_MODE_SIZE (GET_MODE (tmp)) \
1452 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (tmp))))) \
1453 tmp = SUBREG_REG (tmp); \
1454 if (REG_P (tmp) && REG_OK_FOR_BASE_P (tmp)) \
1456 if (CONSTANT_ADDRESS_P (X)) \
1458 if (GET_CODE (X) == PLUS) \
1460 tmp = XEXP (X, 0); \
1461 if (GET_CODE (tmp) == SUBREG \
1462 && (GET_MODE_SIZE (GET_MODE (tmp)) \
1463 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (tmp))))) \
1464 tmp = SUBREG_REG (tmp); \
1467 if (REG_OK_FP_BASE_P (tmp) \
1468 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1470 if (REG_OK_FOR_BASE_P (tmp) \
1471 && CONSTANT_ADDRESS_P (XEXP (X, 1))) \
1474 else if (GET_CODE (tmp) == ADDRESSOF \
1475 && CONSTANT_ADDRESS_P (XEXP (X, 1))) \
1480 /* Now accept the simple address, or, for DImode only, an AND of a simple
1481 address that turns off the low three bits. */
1483 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1484 { GO_IF_LEGITIMATE_SIMPLE_ADDRESS (MODE, X, ADDR); \
1485 if ((MODE) == DImode \
1486 && GET_CODE (X) == AND \
1487 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1488 && INTVAL (XEXP (X, 1)) == -8) \
1489 GO_IF_LEGITIMATE_SIMPLE_ADDRESS (MODE, XEXP (X, 0), ADDR); \
1492 /* Try machine-dependent ways of modifying an illegitimate address
1493 to be legitimate. If we find one, return the new, valid address.
1494 This macro is used in only one place: `memory_address' in explow.c.
1496 OLDX is the address as it was before break_out_memory_refs was called.
1497 In some cases it is useful to look at this to decide what needs to be done.
1499 MODE and WIN are passed so that this macro can use
1500 GO_IF_LEGITIMATE_ADDRESS.
1502 It is always safe for this macro to do nothing. It exists to recognize
1503 opportunities to optimize the output.
1505 For the Alpha, there are three cases we handle:
1507 (1) If the address is (plus reg const_int) and the CONST_INT is not a
1508 valid offset, compute the high part of the constant and add it to the
1509 register. Then our address is (plus temp low-part-const).
1510 (2) If the address is (const (plus FOO const_int)), find the low-order
1511 part of the CONST_INT. Then load FOO plus any high-order part of the
1512 CONST_INT into a register. Our address is (plus reg low-part-const).
1513 This is done to reduce the number of GOT entries.
1514 (3) If we have a (plus reg const), emit the load as in (2), then add
1515 the two registers, and finally generate (plus reg low-part-const) as
1518 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1519 { if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG \
1520 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1521 && ! CONSTANT_ADDRESS_P (XEXP (X, 1))) \
1523 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1524 HOST_WIDE_INT lowpart = (val & 0xffff) - 2 * (val & 0x8000); \
1525 HOST_WIDE_INT highpart = val - lowpart; \
1526 rtx high = GEN_INT (highpart); \
1527 rtx temp = expand_binop (Pmode, add_optab, XEXP (x, 0), \
1528 high, NULL_RTX, 1, OPTAB_LIB_WIDEN); \
1530 (X) = plus_constant (temp, lowpart); \
1533 else if (GET_CODE (X) == CONST \
1534 && GET_CODE (XEXP (X, 0)) == PLUS \
1535 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT) \
1537 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (X, 0), 1)); \
1538 HOST_WIDE_INT lowpart = (val & 0xffff) - 2 * (val & 0x8000); \
1539 HOST_WIDE_INT highpart = val - lowpart; \
1540 rtx high = XEXP (XEXP (X, 0), 0); \
1543 high = plus_constant (high, highpart); \
1545 (X) = plus_constant (force_reg (Pmode, high), lowpart); \
1548 else if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG \
1549 && GET_CODE (XEXP (X, 1)) == CONST \
1550 && GET_CODE (XEXP (XEXP (X, 1), 0)) == PLUS \
1551 && GET_CODE (XEXP (XEXP (XEXP (X, 1), 0), 1)) == CONST_INT) \
1553 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (X, 1), 0), 1)); \
1554 HOST_WIDE_INT lowpart = (val & 0xffff) - 2 * (val & 0x8000); \
1555 HOST_WIDE_INT highpart = val - lowpart; \
1556 rtx high = XEXP (XEXP (XEXP (X, 1), 0), 0); \
1559 high = plus_constant (high, highpart); \
1561 high = expand_binop (Pmode, add_optab, XEXP (X, 0), \
1562 force_reg (Pmode, high), \
1563 high, 1, OPTAB_LIB_WIDEN); \
1564 (X) = plus_constant (high, lowpart); \
1569 /* Try a machine-dependent way of reloading an illegitimate address
1570 operand. If we find one, push the reload and jump to WIN. This
1571 macro is used in only one place: `find_reloads_address' in reload.c.
1573 For the Alpha, we wish to handle large displacements off a base
1574 register by splitting the addend across an ldah and the mem insn.
1575 This cuts number of extra insns needed from 3 to 1. */
1577 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1579 /* We must recognize output that we have already generated ourselves. */ \
1580 if (GET_CODE (X) == PLUS \
1581 && GET_CODE (XEXP (X, 0)) == PLUS \
1582 && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \
1583 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
1584 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1586 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL_PTR, \
1587 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
1591 if (GET_CODE (X) == PLUS \
1592 && GET_CODE (XEXP (X, 0)) == REG \
1593 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1594 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1595 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1597 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1598 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; \
1599 HOST_WIDE_INT high \
1600 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000; \
1602 /* Check for 32-bit overflow. */ \
1603 if (high + low != val) \
1606 /* Reload the high part into a base reg; leave the low part \
1607 in the mem directly. */ \
1609 X = gen_rtx_PLUS (GET_MODE (X), \
1610 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1614 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL_PTR, \
1615 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
1621 /* Go to LABEL if ADDR (a legitimate address expression)
1622 has an effect that depends on the machine mode it is used for.
1623 On the Alpha this is true only for the unaligned modes. We can
1624 simplify this test since we know that the address must be valid. */
1626 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1627 { if (GET_CODE (ADDR) == AND) goto LABEL; }
1629 /* Compute the cost of an address. For the Alpha, all valid addresses are
1632 #define ADDRESS_COST(X) 0
1634 /* Machine-dependent reorg pass. */
1635 #define MACHINE_DEPENDENT_REORG(X) alpha_reorg(X)
1637 /* Specify the machine mode that this machine uses
1638 for the index in the tablejump instruction. */
1639 #define CASE_VECTOR_MODE SImode
1641 /* Define as C expression which evaluates to nonzero if the tablejump
1642 instruction expects the table to contain offsets from the address of the
1645 Do not define this if the table should contain absolute addresses.
1646 On the Alpha, the table is really GP-relative, not relative to the PC
1647 of the table, but we pretend that it is PC-relative; this should be OK,
1648 but we should try to find some better way sometime. */
1649 #define CASE_VECTOR_PC_RELATIVE 1
1651 /* Specify the tree operation to be used to convert reals to integers. */
1652 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1654 /* This is the kind of divide that is easiest to do in the general case. */
1655 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1657 /* Define this as 1 if `char' should by default be signed; else as 0. */
1658 #define DEFAULT_SIGNED_CHAR 1
1660 /* This flag, if defined, says the same insns that convert to a signed fixnum
1661 also convert validly to an unsigned one.
1663 We actually lie a bit here as overflow conditions are different. But
1664 they aren't being checked anyway. */
1666 #define FIXUNS_TRUNC_LIKE_FIX_TRUNC
1668 /* Max number of bytes we can move to or from memory
1669 in one reasonably fast instruction. */
1673 /* If a memory-to-memory move would take MOVE_RATIO or more simple
1674 move-instruction pairs, we will do a movstr or libcall instead.
1676 Without byte/word accesses, we want no more than four instructions;
1677 with, several single byte accesses are better. */
1679 #define MOVE_RATIO (TARGET_BWX ? 7 : 2)
1681 /* Largest number of bytes of an object that can be placed in a register.
1682 On the Alpha we have plenty of registers, so use TImode. */
1683 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode)
1685 /* Nonzero if access to memory by bytes is no faster than for words.
1686 Also non-zero if doing byte operations (specifically shifts) in registers
1689 On the Alpha, we want to not use the byte operation and instead use
1690 masking operations to access fields; these will save instructions. */
1692 #define SLOW_BYTE_ACCESS 1
1694 /* Define if operations between registers always perform the operation
1695 on the full register even if a narrower mode is specified. */
1696 #define WORD_REGISTER_OPERATIONS
1698 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1699 will either zero-extend or sign-extend. The value of this macro should
1700 be the code that says which one of the two operations is implicitly
1701 done, NIL if none. */
1702 #define LOAD_EXTEND_OP(MODE) ((MODE) == SImode ? SIGN_EXTEND : ZERO_EXTEND)
1704 /* Define if loading short immediate values into registers sign extends. */
1705 #define SHORT_IMMEDIATES_SIGN_EXTEND
1707 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1708 is done just by pretending it is already truncated. */
1709 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1711 /* We assume that the store-condition-codes instructions store 0 for false
1712 and some other value for true. This is the value stored for true. */
1714 #define STORE_FLAG_VALUE 1
1716 /* Define the value returned by a floating-point comparison instruction. */
1718 #define FLOAT_STORE_FLAG_VALUE(MODE) \
1719 REAL_VALUE_ATOF ((TARGET_FLOAT_VAX ? "0.5" : "2.0"), (MODE))
1721 /* Canonicalize a comparison from one we don't have to one we do have. */
1723 #define CANONICALIZE_COMPARISON(CODE,OP0,OP1) \
1725 if (((CODE) == GE || (CODE) == GT || (CODE) == GEU || (CODE) == GTU) \
1726 && (GET_CODE (OP1) == REG || (OP1) == const0_rtx)) \
1731 (CODE) = swap_condition (CODE); \
1733 if (((CODE) == LT || (CODE) == LTU) \
1734 && GET_CODE (OP1) == CONST_INT && INTVAL (OP1) == 256) \
1736 (CODE) = (CODE) == LT ? LE : LEU; \
1737 (OP1) = GEN_INT (255); \
1741 /* Specify the machine mode that pointers have.
1742 After generation of rtl, the compiler makes no further distinction
1743 between pointers and any other objects of this machine mode. */
1744 #define Pmode DImode
1746 /* Mode of a function address in a call instruction (for indexing purposes). */
1748 #define FUNCTION_MODE Pmode
1750 /* Define this if addresses of constant functions
1751 shouldn't be put through pseudo regs where they can be cse'd.
1752 Desirable on machines where ordinary constants are expensive
1753 but a CALL with constant address is cheap.
1755 We define this on the Alpha so that gen_call and gen_call_value
1756 get to see the SYMBOL_REF (for the hint field of the jsr). It will
1757 then copy it into a register, thus actually letting the address be
1760 #define NO_FUNCTION_CSE
1762 /* Define this to be nonzero if shift instructions ignore all but the low-order
1764 #define SHIFT_COUNT_TRUNCATED 1
1766 /* The EV4 is dual issue; EV5/EV6 are quad issue. */
1767 #define ISSUE_RATE (alpha_cpu == PROCESSOR_EV4 ? 2 : 4)
1769 /* Describe the fact that MULTI instructions are multiple instructions
1770 and so to assume they don't pair with anything. */
1771 #define MD_SCHED_VARIABLE_ISSUE(DUMP, SCHED_VERBOSE, INSN, CAN_ISSUE_MORE) \
1772 if (recog_memoized (INSN) < 0 || get_attr_type (INSN) == TYPE_MULTI) \
1773 (CAN_ISSUE_MORE) = 0
1775 /* Compute the cost of computing a constant rtl expression RTX
1776 whose rtx-code is CODE. The body of this macro is a portion
1777 of a switch statement. If the code is computed here,
1778 return it with a return statement. Otherwise, break from the switch.
1780 If this is an 8-bit constant, return zero since it can be used
1781 nearly anywhere with no cost. If it is a valid operand for an
1782 ADD or AND, likewise return 0 if we know it will be used in that
1783 context. Otherwise, return 2 since it might be used there later.
1784 All other constants take at least two insns. */
1786 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
1788 if (INTVAL (RTX) >= 0 && INTVAL (RTX) < 256) \
1790 case CONST_DOUBLE: \
1791 if ((RTX) == CONST0_RTX (GET_MODE (RTX))) \
1793 else if (((OUTER_CODE) == PLUS && add_operand (RTX, VOIDmode)) \
1794 || ((OUTER_CODE) == AND && and_operand (RTX, VOIDmode))) \
1796 else if (add_operand (RTX, VOIDmode) || and_operand (RTX, VOIDmode)) \
1799 return COSTS_N_INSNS (2); \
1803 switch (alpha_cpu) \
1805 case PROCESSOR_EV4: \
1806 return COSTS_N_INSNS (3); \
1807 case PROCESSOR_EV5: \
1808 case PROCESSOR_EV6: \
1809 return COSTS_N_INSNS (2); \
1813 /* Provide the costs of a rtl expression. This is in the body of a
1816 #define RTX_COSTS(X,CODE,OUTER_CODE) \
1817 case PLUS: case MINUS: \
1818 if (FLOAT_MODE_P (GET_MODE (X))) \
1819 switch (alpha_cpu) \
1821 case PROCESSOR_EV4: \
1822 return COSTS_N_INSNS (6); \
1823 case PROCESSOR_EV5: \
1824 case PROCESSOR_EV6: \
1825 return COSTS_N_INSNS (4); \
1828 else if (GET_CODE (XEXP (X, 0)) == MULT \
1829 && const48_operand (XEXP (XEXP (X, 0), 1), VOIDmode)) \
1830 return (2 + rtx_cost (XEXP (XEXP (X, 0), 0), OUTER_CODE) \
1831 + rtx_cost (XEXP (X, 1), OUTER_CODE)); \
1834 switch (alpha_cpu) \
1836 case PROCESSOR_EV4: \
1837 if (FLOAT_MODE_P (GET_MODE (X))) \
1838 return COSTS_N_INSNS (6); \
1839 return COSTS_N_INSNS (23); \
1840 case PROCESSOR_EV5: \
1841 if (FLOAT_MODE_P (GET_MODE (X))) \
1842 return COSTS_N_INSNS (4); \
1843 else if (GET_MODE (X) == DImode) \
1844 return COSTS_N_INSNS (12); \
1846 return COSTS_N_INSNS (8); \
1847 case PROCESSOR_EV6: \
1848 if (FLOAT_MODE_P (GET_MODE (X))) \
1849 return COSTS_N_INSNS (4); \
1851 return COSTS_N_INSNS (7); \
1855 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
1856 && INTVAL (XEXP (X, 1)) <= 3) \
1858 /* ... fall through ... */ \
1859 case ASHIFTRT: case LSHIFTRT: \
1860 switch (alpha_cpu) \
1862 case PROCESSOR_EV4: \
1863 return COSTS_N_INSNS (2); \
1864 case PROCESSOR_EV5: \
1865 case PROCESSOR_EV6: \
1866 return COSTS_N_INSNS (1); \
1869 case IF_THEN_ELSE: \
1870 switch (alpha_cpu) \
1872 case PROCESSOR_EV4: \
1873 case PROCESSOR_EV6: \
1874 return COSTS_N_INSNS (2); \
1875 case PROCESSOR_EV5: \
1876 return COSTS_N_INSNS (1); \
1879 case DIV: case UDIV: case MOD: case UMOD: \
1880 switch (alpha_cpu) \
1882 case PROCESSOR_EV4: \
1883 if (GET_MODE (X) == SFmode) \
1884 return COSTS_N_INSNS (34); \
1885 else if (GET_MODE (X) == DFmode) \
1886 return COSTS_N_INSNS (63); \
1888 return COSTS_N_INSNS (70); \
1889 case PROCESSOR_EV5: \
1890 if (GET_MODE (X) == SFmode) \
1891 return COSTS_N_INSNS (15); \
1892 else if (GET_MODE (X) == DFmode) \
1893 return COSTS_N_INSNS (22); \
1895 return COSTS_N_INSNS (70); /* ??? */ \
1896 case PROCESSOR_EV6: \
1897 if (GET_MODE (X) == SFmode) \
1898 return COSTS_N_INSNS (12); \
1899 else if (GET_MODE (X) == DFmode) \
1900 return COSTS_N_INSNS (15); \
1902 return COSTS_N_INSNS (70); /* ??? */ \
1906 switch (alpha_cpu) \
1908 case PROCESSOR_EV4: \
1909 case PROCESSOR_EV6: \
1910 return COSTS_N_INSNS (3); \
1911 case PROCESSOR_EV5: \
1912 return COSTS_N_INSNS (2); \
1915 case NEG: case ABS: \
1916 if (! FLOAT_MODE_P (GET_MODE (X))) \
1918 /* ... fall through ... */ \
1919 case FLOAT: case UNSIGNED_FLOAT: case FIX: case UNSIGNED_FIX: \
1920 case FLOAT_EXTEND: case FLOAT_TRUNCATE: \
1921 switch (alpha_cpu) \
1923 case PROCESSOR_EV4: \
1924 return COSTS_N_INSNS (6); \
1925 case PROCESSOR_EV5: \
1926 case PROCESSOR_EV6: \
1927 return COSTS_N_INSNS (4); \
1931 /* Control the assembler format that we output. */
1933 /* Output to assembler file text saying following lines
1934 may contain character constants, extra white space, comments, etc. */
1936 #define ASM_APP_ON ""
1938 /* Output to assembler file text saying following lines
1939 no longer contain unusual constructs. */
1941 #define ASM_APP_OFF ""
1943 #define TEXT_SECTION_ASM_OP "\t.text"
1945 /* Output before read-only data. */
1947 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata"
1949 /* Output before writable data. */
1951 #define DATA_SECTION_ASM_OP "\t.data"
1953 /* Define an extra section for read-only data, a routine to enter it, and
1954 indicate that it is for read-only data.
1956 The first time we enter the readonly data section for a file, we write
1957 eight bytes of zero. This works around a bug in DEC's assembler in
1958 some versions of OSF/1 V3.x. */
1960 #define EXTRA_SECTIONS readonly_data
1962 #define EXTRA_SECTION_FUNCTIONS \
1964 literal_section () \
1966 if (in_section != readonly_data) \
1968 static int firsttime = 1; \
1970 fprintf (asm_out_file, "%s\n", READONLY_DATA_SECTION_ASM_OP); \
1974 ASM_OUTPUT_DOUBLE_INT (asm_out_file, const0_rtx); \
1977 in_section = readonly_data; \
1981 #define READONLY_DATA_SECTION literal_section
1983 /* If we are referencing a function that is static, make the SYMBOL_REF
1984 special. We use this to see indicate we can branch to this function
1985 without setting PV or restoring GP. */
1987 #define ENCODE_SECTION_INFO(DECL) \
1988 if (TREE_CODE (DECL) == FUNCTION_DECL && ! TREE_PUBLIC (DECL)) \
1989 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1;
1991 /* How to refer to registers in assembler output.
1992 This sequence is indexed by compiler's hard-register-number (see above). */
1994 #define REGISTER_NAMES \
1995 {"$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8", \
1996 "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
1997 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
1998 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "AP", \
1999 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", "$f8", \
2000 "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2001 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",\
2002 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "FP"}
2004 /* How to renumber registers for dbx and gdb. */
2006 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
2008 /* This is how to output the definition of a user-level label named NAME,
2009 such as the label on a static function or variable NAME. */
2011 #define ASM_OUTPUT_LABEL(FILE,NAME) \
2012 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
2014 /* This is how to output a command to make the user-level label named NAME
2015 defined for reference from other files. */
2017 #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
2018 do { fputs ("\t.globl ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
2020 /* The prefix to add to user-visible assembler symbols. */
2022 #define USER_LABEL_PREFIX ""
2024 /* This is how to output an internal numbered label where
2025 PREFIX is the class of label and NUM is the number within the class. */
2027 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
2028 fprintf (FILE, "$%s%d:\n", PREFIX, NUM)
2030 /* This is how to output a label for a jump table. Arguments are the same as
2031 for ASM_OUTPUT_INTERNAL_LABEL, except the insn for the jump table is
2034 #define ASM_OUTPUT_CASE_LABEL(FILE,PREFIX,NUM,TABLEINSN) \
2035 { ASM_OUTPUT_ALIGN (FILE, 2); ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); }
2037 /* This is how to store into the string LABEL
2038 the symbol_ref name of an internal numbered label where
2039 PREFIX is the class of label and NUM is the number within the class.
2040 This is suitable for output with `assemble_name'. */
2042 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2043 sprintf ((LABEL), "*$%s%ld", (PREFIX), (long)(NUM))
2045 /* Check a floating-point value for validity for a particular machine mode. */
2047 #define CHECK_FLOAT_VALUE(MODE, D, OVERFLOW) \
2048 ((OVERFLOW) = check_float_value (MODE, &D, OVERFLOW))
2050 /* This is how to output an assembler line defining a `long double'
2053 #define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) \
2056 REAL_VALUE_TO_TARGET_LONG_DOUBLE ((VALUE), t); \
2057 fprintf (FILE, "\t.quad 0x%lx%08lx,0x%lx%08lx\n", \
2058 t[1] & 0xffffffff, t[0] & 0xffffffff, \
2059 t[3] & 0xffffffff, t[2] & 0xffffffff); \
2062 /* This is how to output an assembler line defining a `double' constant. */
2064 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
2067 REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t); \
2068 fprintf (FILE, "\t.quad 0x%lx%08lx\n", \
2069 t[1] & 0xffffffff, t[0] & 0xffffffff); \
2072 /* This is how to output an assembler line defining a `float' constant. */
2074 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
2077 REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t); \
2078 fprintf (FILE, "\t.long 0x%lx\n", t & 0xffffffff); \
2081 /* This is how to output an assembler line defining an `int' constant. */
2083 #define ASM_OUTPUT_INT(FILE,VALUE) \
2084 ( fprintf (FILE, "\t.long "), \
2085 output_addr_const (FILE, (VALUE)), \
2086 fprintf (FILE, "\n"))
2088 /* This is how to output an assembler line defining a `long' constant. */
2090 #define ASM_OUTPUT_DOUBLE_INT(FILE,VALUE) \
2091 ( fprintf (FILE, "\t.quad "), \
2092 output_addr_const (FILE, (VALUE)), \
2093 fprintf (FILE, "\n"))
2095 /* Likewise for `char' and `short' constants. */
2097 #define ASM_OUTPUT_SHORT(FILE,VALUE) \
2098 fprintf (FILE, "\t.word %d\n", \
2099 (int)(GET_CODE (VALUE) == CONST_INT \
2100 ? INTVAL (VALUE) & 0xffff : (abort (), 0)))
2102 #define ASM_OUTPUT_CHAR(FILE,VALUE) \
2103 fprintf (FILE, "\t.byte %d\n", \
2104 (int)(GET_CODE (VALUE) == CONST_INT \
2105 ? INTVAL (VALUE) & 0xff : (abort (), 0)))
2107 /* We use the default ASCII-output routine, except that we don't write more
2108 than 50 characters since the assembler doesn't support very long lines. */
2110 #define ASM_OUTPUT_ASCII(MYFILE, MYSTRING, MYLENGTH) \
2112 FILE *_hide_asm_out_file = (MYFILE); \
2113 const unsigned char *_hide_p = (const unsigned char *) (MYSTRING); \
2114 int _hide_thissize = (MYLENGTH); \
2115 int _size_so_far = 0; \
2117 FILE *asm_out_file = _hide_asm_out_file; \
2118 const unsigned char *p = _hide_p; \
2119 int thissize = _hide_thissize; \
2121 fprintf (asm_out_file, "\t.ascii \""); \
2123 for (i = 0; i < thissize; i++) \
2125 register int c = p[i]; \
2127 if (_size_so_far ++ > 50 && i < thissize - 4) \
2128 _size_so_far = 0, fprintf (asm_out_file, "\"\n\t.ascii \""); \
2130 if (c == '\"' || c == '\\') \
2131 putc ('\\', asm_out_file); \
2132 if (c >= ' ' && c < 0177) \
2133 putc (c, asm_out_file); \
2136 fprintf (asm_out_file, "\\%o", c); \
2137 /* After an octal-escape, if a digit follows, \
2138 terminate one string constant and start another. \
2139 The Vax assembler fails to stop reading the escape \
2140 after three digits, so this is the only way we \
2141 can get it to parse the data properly. */ \
2142 if (i < thissize - 1 \
2143 && p[i + 1] >= '0' && p[i + 1] <= '9') \
2144 _size_so_far = 0, fprintf (asm_out_file, "\"\n\t.ascii \""); \
2147 fprintf (asm_out_file, "\"\n"); \
2152 /* To get unaligned data, we have to turn off auto alignment. */
2153 #define UNALIGNED_SHORT_ASM_OP "\t.align 0\n\t.word\t"
2154 #define UNALIGNED_INT_ASM_OP "\t.align 0\n\t.long\t"
2155 #define UNALIGNED_DOUBLE_INT_ASM_OP "\t.align 0\n\t.quad\t"
2157 /* This is how to output an insn to push a register on the stack.
2158 It need not be very fast code. */
2160 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
2161 fprintf (FILE, "\tsubq $30,8,$30\n\tst%s $%s%d,0($30)\n", \
2162 (REGNO) > 32 ? "t" : "q", (REGNO) > 32 ? "f" : "", \
2165 /* This is how to output an insn to pop a register from the stack.
2166 It need not be very fast code. */
2168 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
2169 fprintf (FILE, "\tld%s $%s%d,0($30)\n\taddq $30,8,$30\n", \
2170 (REGNO) > 32 ? "t" : "q", (REGNO) > 32 ? "f" : "", \
2173 /* This is how to output an assembler line for a numeric constant byte. */
2175 #define ASM_OUTPUT_BYTE(FILE,VALUE) \
2176 fprintf (FILE, "\t.byte 0x%x\n", (int) ((VALUE) & 0xff))
2178 /* This is how to output an element of a case-vector that is absolute.
2179 (Alpha does not use such vectors, but we must define this macro anyway.) */
2181 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) abort ()
2183 /* This is how to output an element of a case-vector that is relative. */
2185 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2186 fprintf (FILE, "\t.%s $L%d\n", TARGET_WINDOWS_NT ? "long" : "gprel32", \
2189 /* This is how to output an assembler line
2190 that says to advance the location counter
2191 to a multiple of 2**LOG bytes. */
2193 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2195 fprintf (FILE, "\t.align %d\n", LOG);
2197 /* This is how to advance the location counter by SIZE bytes. */
2199 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
2200 fprintf (FILE, "\t.space %d\n", (SIZE))
2202 /* This says how to output an assembler line
2203 to define a global common symbol. */
2205 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
2206 ( fputs ("\t.comm ", (FILE)), \
2207 assemble_name ((FILE), (NAME)), \
2208 fprintf ((FILE), ",%d\n", (SIZE)))
2210 /* This says how to output an assembler line
2211 to define a local common symbol. */
2213 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE,ROUNDED) \
2214 ( fputs ("\t.lcomm ", (FILE)), \
2215 assemble_name ((FILE), (NAME)), \
2216 fprintf ((FILE), ",%d\n", (SIZE)))
2218 /* Store in OUTPUT a string (made with alloca) containing
2219 an assembler-name for a local static variable named NAME.
2220 LABELNO is an integer which is different for each call. */
2222 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
2223 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
2224 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
2226 /* Define the parentheses used to group arithmetic operations
2227 in assembler code. */
2229 #define ASM_OPEN_PAREN "("
2230 #define ASM_CLOSE_PAREN ")"
2232 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
2233 Used for C++ multiple inheritance. */
2234 /* ??? This is only used with the v2 ABI, and alpha.c makes assumptions
2235 about current_function_is_thunk that are not valid with the v3 ABI. */
2237 #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \
2239 const char *fn_name = XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0); \
2242 if (! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT) \
2243 fprintf (FILE, "\tldgp $29,0($27)\n"); \
2245 /* Mark end of prologue. */ \
2246 output_end_prologue (FILE); \
2248 /* Rely on the assembler to macro expand a large delta. */ \
2249 fprintf (FILE, "\t.set at\n"); \
2250 reg = aggregate_value_p (TREE_TYPE (TREE_TYPE (FUNCTION))) ? 17 : 16; \
2251 fprintf (FILE, "\tlda $%d,%ld($%d)\n", reg, (long)(DELTA), reg); \
2253 if (current_file_function_operand (XEXP (DECL_RTL (FUNCTION), 0), \
2256 fprintf (FILE, "\tbr $31,$"); \
2257 assemble_name (FILE, fn_name); \
2258 fprintf (FILE, "..ng\n"); \
2262 fprintf (FILE, "\tjmp $31,"); \
2263 assemble_name (FILE, fn_name); \
2264 fputc ('\n', FILE); \
2266 fprintf (FILE, "\t.set noat\n"); \
2271 /* Define results of standard character escape sequences. */
2272 #define TARGET_BELL 007
2273 #define TARGET_BS 010
2274 #define TARGET_TAB 011
2275 #define TARGET_NEWLINE 012
2276 #define TARGET_VT 013
2277 #define TARGET_FF 014
2278 #define TARGET_CR 015
2280 /* Print operand X (an rtx) in assembler syntax to file FILE.
2281 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2282 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2284 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2286 /* Determine which codes are valid without a following integer. These must
2289 ~ Generates the name of the current function.
2291 & Generates fp-rounding mode suffix: nothing for normal, 'c' for
2292 chopped, 'm' for minus-infinity, and 'd' for dynamic rounding
2293 mode. alpha_fprm controls which suffix is generated.
2295 ' Generates trap-mode suffix for instructions that accept the
2296 su suffix only (cmpt et al).
2298 ` Generates trap-mode suffix for instructions that accept the
2299 v and sv suffix. The only instruction that needs this is cvtql.
2301 ( Generates trap-mode suffix for instructions that accept the
2302 v, sv, and svi suffix. The only instruction that needs this
2305 ) Generates trap-mode suffix for instructions that accept the
2306 u, su, and sui suffix. This is the bulk of the IEEE floating
2307 point instructions (addt et al).
2309 + Generates trap-mode suffix for instructions that accept the
2310 sui suffix (cvtqt and cvtqs).
2312 , Generates single precision suffix for floating point
2313 instructions (s for IEEE, f for VAX)
2315 - Generates double precision suffix for floating point
2316 instructions (t for IEEE, g for VAX)
2319 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2320 ((CODE) == '&' || (CODE) == '`' || (CODE) == '\'' || (CODE) == '(' \
2321 || (CODE) == ')' || (CODE) == '+' || (CODE) == ',' || (CODE) == '-' \
2324 /* Print a memory address as an operand to reference that memory location. */
2326 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2327 print_operand_address((FILE), (ADDR))
2329 /* Define the codes that are matched by predicates in alpha.c. */
2331 #define PREDICATE_CODES \
2332 {"reg_or_0_operand", {SUBREG, REG, CONST_INT}}, \
2333 {"reg_or_6bit_operand", {SUBREG, REG, CONST_INT}}, \
2334 {"reg_or_8bit_operand", {SUBREG, REG, CONST_INT}}, \
2335 {"cint8_operand", {CONST_INT}}, \
2336 {"reg_or_cint_operand", {SUBREG, REG, CONST_INT}}, \
2337 {"add_operand", {SUBREG, REG, CONST_INT}}, \
2338 {"sext_add_operand", {SUBREG, REG, CONST_INT}}, \
2339 {"const48_operand", {CONST_INT}}, \
2340 {"and_operand", {SUBREG, REG, CONST_INT}}, \
2341 {"or_operand", {SUBREG, REG, CONST_INT}}, \
2342 {"mode_mask_operand", {CONST_INT}}, \
2343 {"mul8_operand", {CONST_INT}}, \
2344 {"mode_width_operand", {CONST_INT}}, \
2345 {"reg_or_fp0_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2346 {"alpha_comparison_operator", {EQ, LE, LT, LEU, LTU}}, \
2347 {"alpha_zero_comparison_operator", {EQ, NE, LE, LT, LEU, LTU}}, \
2348 {"alpha_swapped_comparison_operator", {EQ, GE, GT, GEU, GTU}}, \
2349 {"signed_comparison_operator", {EQ, NE, LE, LT, GE, GT}}, \
2350 {"alpha_fp_comparison_operator", {EQ, LE, LT, UNORDERED}}, \
2351 {"divmod_operator", {DIV, MOD, UDIV, UMOD}}, \
2352 {"fp0_operand", {CONST_DOUBLE}}, \
2353 {"current_file_function_operand", {SYMBOL_REF}}, \
2354 {"call_operand", {REG, SYMBOL_REF}}, \
2355 {"input_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE, \
2356 SYMBOL_REF, CONST, LABEL_REF}}, \
2357 {"some_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE, \
2358 SYMBOL_REF, CONST, LABEL_REF}}, \
2359 {"some_ni_operand", {SUBREG, REG, MEM}}, \
2360 {"aligned_memory_operand", {MEM}}, \
2361 {"unaligned_memory_operand", {MEM}}, \
2362 {"reg_or_unaligned_mem_operand", {SUBREG, REG, MEM}}, \
2363 {"any_memory_operand", {MEM}}, \
2364 {"hard_fp_register_operand", {SUBREG, REG}}, \
2365 {"hard_int_register_operand", {SUBREG, REG}}, \
2366 {"reg_not_elim_operand", {SUBREG, REG}}, \
2367 {"reg_no_subreg_operand", {REG}}, \
2368 {"addition_operation", {PLUS}},
2370 /* Define the `__builtin_va_list' type for the ABI. */
2371 #define BUILD_VA_LIST_TYPE(VALIST) \
2372 (VALIST) = alpha_build_va_list ()
2374 /* Implement `va_start' for varargs and stdarg. */
2375 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
2376 alpha_va_start (stdarg, valist, nextarg)
2378 /* Implement `va_arg'. */
2379 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
2380 alpha_va_arg (valist, type)
2382 /* Tell collect that the object format is ECOFF. */
2383 #define OBJECT_FORMAT_COFF
2384 #define EXTENDED_COFF
2386 /* If we use NM, pass -g to it so it only lists globals. */
2387 #define NM_FLAGS "-pg"
2389 /* Definitions for debugging. */
2391 #define SDB_DEBUGGING_INFO /* generate info for mips-tfile */
2392 #define DBX_DEBUGGING_INFO /* generate embedded stabs */
2393 #define MIPS_DEBUGGING_INFO /* MIPS specific debugging info */
2395 #ifndef PREFERRED_DEBUGGING_TYPE /* assume SDB_DEBUGGING_INFO */
2396 #define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
2400 /* Correct the offset of automatic variables and arguments. Note that
2401 the Alpha debug format wants all automatic variables and arguments
2402 to be in terms of two different offsets from the virtual frame pointer,
2403 which is the stack pointer before any adjustment in the function.
2404 The offset for the argument pointer is fixed for the native compiler,
2405 it is either zero (for the no arguments case) or large enough to hold
2406 all argument registers.
2407 The offset for the auto pointer is the fourth argument to the .frame
2408 directive (local_offset).
2409 To stay compatible with the native tools we use the same offsets
2410 from the virtual frame pointer and adjust the debugger arg/auto offsets
2411 accordingly. These debugger offsets are set up in output_prolog. */
2413 extern long alpha_arg_offset;
2414 extern long alpha_auto_offset;
2415 #define DEBUGGER_AUTO_OFFSET(X) \
2416 ((GET_CODE (X) == PLUS ? INTVAL (XEXP (X, 1)) : 0) + alpha_auto_offset)
2417 #define DEBUGGER_ARG_OFFSET(OFFSET, X) (OFFSET + alpha_arg_offset)
2420 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE) \
2421 alpha_output_lineno (STREAM, LINE)
2423 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
2424 alpha_output_filename (STREAM, NAME)
2426 /* mips-tfile.c limits us to strings of one page. We must underestimate this
2427 number, because the real length runs past this up to the next
2428 continuation point. This is really a dbxout.c bug. */
2429 #define DBX_CONTIN_LENGTH 3000
2431 /* By default, turn on GDB extensions. */
2432 #define DEFAULT_GDB_EXTENSIONS 1
2434 /* Stabs-in-ECOFF can't handle dbxout_function_end(). */
2435 #define NO_DBX_FUNCTION_END 1
2437 /* If we are smuggling stabs through the ALPHA ECOFF object
2438 format, put a comment in front of the .stab<x> operation so
2439 that the ALPHA assembler does not choke. The mips-tfile program
2440 will correctly put the stab into the object file. */
2442 #define ASM_STABS_OP ((TARGET_GAS) ? "\t.stabs\t" : " #.stabs\t")
2443 #define ASM_STABN_OP ((TARGET_GAS) ? "\t.stabn\t" : " #.stabn\t")
2444 #define ASM_STABD_OP ((TARGET_GAS) ? "\t.stabd\t" : " #.stabd\t")
2446 /* Forward references to tags are allowed. */
2447 #define SDB_ALLOW_FORWARD_REFERENCES
2449 /* Unknown tags are also allowed. */
2450 #define SDB_ALLOW_UNKNOWN_REFERENCES
2452 #define PUT_SDB_DEF(a) \
2454 fprintf (asm_out_file, "\t%s.def\t", \
2455 (TARGET_GAS) ? "" : "#"); \
2456 ASM_OUTPUT_LABELREF (asm_out_file, a); \
2457 fputc (';', asm_out_file); \
2460 #define PUT_SDB_PLAIN_DEF(a) \
2462 fprintf (asm_out_file, "\t%s.def\t.%s;", \
2463 (TARGET_GAS) ? "" : "#", (a)); \
2466 #define PUT_SDB_TYPE(a) \
2468 fprintf (asm_out_file, "\t.type\t0x%x;", (a)); \
2471 /* For block start and end, we create labels, so that
2472 later we can figure out where the correct offset is.
2473 The normal .ent/.end serve well enough for functions,
2474 so those are just commented out. */
2476 extern int sdb_label_count; /* block start/end next label # */
2478 #define PUT_SDB_BLOCK_START(LINE) \
2480 fprintf (asm_out_file, \
2481 "$Lb%d:\n\t%s.begin\t$Lb%d\t%d\n", \
2483 (TARGET_GAS) ? "" : "#", \
2486 sdb_label_count++; \
2489 #define PUT_SDB_BLOCK_END(LINE) \
2491 fprintf (asm_out_file, \
2492 "$Le%d:\n\t%s.bend\t$Le%d\t%d\n", \
2494 (TARGET_GAS) ? "" : "#", \
2497 sdb_label_count++; \
2500 #define PUT_SDB_FUNCTION_START(LINE)
2502 #define PUT_SDB_FUNCTION_END(LINE)
2504 #define PUT_SDB_EPILOGUE_END(NAME) ((void)(NAME))
2506 /* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for
2507 mips-tdump.c to print them out.
2509 These must match the corresponding definitions in gdb/mipsread.c.
2510 Unfortunately, gcc and gdb do not currently share any directories. */
2512 #define CODE_MASK 0x8F300
2513 #define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
2514 #define MIPS_MARK_STAB(code) ((code)+CODE_MASK)
2515 #define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK)
2517 /* Override some mips-tfile definitions. */
2519 #define SHASH_SIZE 511
2520 #define THASH_SIZE 55
2522 /* Align ecoff symbol tables to avoid OSF1/1.3 nm complaints. */
2524 #define ALIGN_SYMTABLE_OFFSET(OFFSET) (((OFFSET) + 7) & ~7)
2526 /* The system headers under Alpha systems are generally C++-aware. */
2527 #define NO_IMPLICIT_EXTERN_C
2529 /* Generate calls to memcpy, etc., not bcopy, etc. */
2530 #define TARGET_MEM_FUNCTIONS 1
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