1 /* Definitions of target machine for GNU compiler, for DEC Alpha.
2 Copyright (C) 1992, 93-98, 1999 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
23 /* Write out the correct language type definition for the header files.
24 Unless we have assembler language, write out the symbols for C. */
27 %{.S:-D__LANGUAGE_ASSEMBLY__ -D__LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY }}\
28 %{.cc|.cxx|.C:-D__LANGUAGE_C_PLUS_PLUS__ -D__LANGUAGE_C_PLUS_PLUS -D__cplusplus }\
29 %{.m:-D__LANGUAGE_OBJECTIVE_C__ -D__LANGUAGE_OBJECTIVE_C }\
30 %{!.S:%{!.cc:%{!.cxx:%{!.C:%{!.m:-D__LANGUAGE_C__ -D__LANGUAGE_C %{!ansi:-DLANGUAGE_C }}}}}}\
32 %{mieee-with-inexact:-D_IEEE_FP -D_IEEE_FP_INEXACT }}\
33 %(cpp_cpu) %(cpp_subtarget)"
35 #ifndef CPP_SUBTARGET_SPEC
36 #define CPP_SUBTARGET_SPEC ""
39 /* Set the spec to use for signed char. The default tests the above macro
40 but DEC's compiler can't handle the conditional in a "constant"
43 #define SIGNED_CHAR_SPEC "%{funsigned-char:-D__CHAR_UNSIGNED__}"
45 #define WORD_SWITCH_TAKES_ARG(STR) \
46 (!strcmp (STR, "rpath") || !strcmp (STR, "include") \
47 || !strcmp (STR, "imacros") || !strcmp (STR, "aux-info") \
48 || !strcmp (STR, "idirafter") || !strcmp (STR, "iprefix") \
49 || !strcmp (STR, "iwithprefix") || !strcmp (STR, "iwithprefixbefore") \
50 || !strcmp (STR, "isystem"))
52 /* Print subsidiary information on the compiler version in use. */
53 #define TARGET_VERSION
55 /* Run-time compilation parameters selecting different hardware subsets. */
57 /* Which processor to schedule for. The cpu attribute defines a list that
58 mirrors this list, so changes to alpha.md must be made at the same time. */
61 {PROCESSOR_EV4, /* 2106[46]{a,} */
62 PROCESSOR_EV5, /* 21164{a,pc,} */
63 PROCESSOR_EV6}; /* 21264 */
65 extern enum processor_type alpha_cpu;
67 enum alpha_trap_precision
69 ALPHA_TP_PROG, /* No precision (default). */
70 ALPHA_TP_FUNC, /* Trap contained within originating function. */
71 ALPHA_TP_INSN /* Instruction accuracy and code is resumption safe. */
74 enum alpha_fp_rounding_mode
76 ALPHA_FPRM_NORM, /* Normal rounding mode. */
77 ALPHA_FPRM_MINF, /* Round towards minus-infinity. */
78 ALPHA_FPRM_CHOP, /* Chopped rounding mode (towards 0). */
79 ALPHA_FPRM_DYN /* Dynamic rounding mode. */
82 enum alpha_fp_trap_mode
84 ALPHA_FPTM_N, /* Normal trap mode. */
85 ALPHA_FPTM_U, /* Underflow traps enabled. */
86 ALPHA_FPTM_SU, /* Software completion, w/underflow traps */
87 ALPHA_FPTM_SUI /* Software completion, w/underflow & inexact traps */
90 extern int target_flags;
92 extern enum alpha_trap_precision alpha_tp;
93 extern enum alpha_fp_rounding_mode alpha_fprm;
94 extern enum alpha_fp_trap_mode alpha_fptm;
96 /* This means that floating-point support exists in the target implementation
97 of the Alpha architecture. This is usually the default. */
100 #define TARGET_FP (target_flags & MASK_FP)
102 /* This means that floating-point registers are allowed to be used. Note
103 that Alpha implementations without FP operations are required to
104 provide the FP registers. */
106 #define MASK_FPREGS 2
107 #define TARGET_FPREGS (target_flags & MASK_FPREGS)
109 /* This means that gas is used to process the assembler file. */
112 #define TARGET_GAS (target_flags & MASK_GAS)
114 /* This means that we should mark procedures as IEEE conformant. */
116 #define MASK_IEEE_CONFORMANT 8
117 #define TARGET_IEEE_CONFORMANT (target_flags & MASK_IEEE_CONFORMANT)
119 /* This means we should be IEEE-compliant except for inexact. */
122 #define TARGET_IEEE (target_flags & MASK_IEEE)
124 /* This means we should be fully IEEE-compliant. */
126 #define MASK_IEEE_WITH_INEXACT 32
127 #define TARGET_IEEE_WITH_INEXACT (target_flags & MASK_IEEE_WITH_INEXACT)
129 /* This means we must construct all constants rather than emitting
130 them as literal data. */
132 #define MASK_BUILD_CONSTANTS 128
133 #define TARGET_BUILD_CONSTANTS (target_flags & MASK_BUILD_CONSTANTS)
135 /* This means we handle floating points in VAX F- (float)
136 or G- (double) Format. */
138 #define MASK_FLOAT_VAX 512
139 #define TARGET_FLOAT_VAX (target_flags & MASK_FLOAT_VAX)
141 /* This means that the processor has byte and half word loads and stores
142 (the BWX extension). */
144 #define MASK_BWX 1024
145 #define TARGET_BWX (target_flags & MASK_BWX)
147 /* This means that the processor has the CIX extension. */
148 #define MASK_CIX 2048
149 #define TARGET_CIX (target_flags & MASK_CIX)
151 /* This means that the processor has the MAX extension. */
152 #define MASK_MAX 4096
153 #define TARGET_MAX (target_flags & MASK_MAX)
155 /* This means that the processor is an EV5, EV56, or PCA56. This is defined
156 only in TARGET_CPU_DEFAULT. */
157 #define MASK_CPU_EV5 8192
159 /* Likewise for EV6. */
160 #define MASK_CPU_EV6 16384
162 /* This means we support the .arch directive in the assembler. Only
163 defined in TARGET_CPU_DEFAULT. */
164 #define MASK_SUPPORT_ARCH 32768
165 #define TARGET_SUPPORT_ARCH (target_flags & MASK_SUPPORT_ARCH)
167 /* These are for target os support and cannot be changed at runtime. */
168 #ifndef TARGET_WINDOWS_NT
169 #define TARGET_WINDOWS_NT 0
171 #ifndef TARGET_OPEN_VMS
172 #define TARGET_OPEN_VMS 0
175 #ifndef TARGET_AS_CAN_SUBTRACT_LABELS
176 #define TARGET_AS_CAN_SUBTRACT_LABELS TARGET_GAS
178 #ifndef TARGET_CAN_FAULT_IN_PROLOGUE
179 #define TARGET_CAN_FAULT_IN_PROLOGUE 0
182 /* Macro to define tables used to set the flags.
183 This is a list in braces of pairs in braces,
184 each pair being { "NAME", VALUE }
185 where VALUE is the bits to set or minus the bits to clear.
186 An empty string NAME is used to identify the default VALUE. */
188 #define TARGET_SWITCHES \
189 { {"no-soft-float", MASK_FP, "Use hardware fp"}, \
190 {"soft-float", - MASK_FP, "Do not use hardware fp"}, \
191 {"fp-regs", MASK_FPREGS, "Use fp registers"}, \
192 {"no-fp-regs", - (MASK_FP|MASK_FPREGS), "Do not use fp registers"}, \
193 {"alpha-as", -MASK_GAS, "Do not assume GAS"}, \
194 {"gas", MASK_GAS, "Assume GAS"}, \
195 {"ieee-conformant", MASK_IEEE_CONFORMANT, \
196 "Request IEEE-conformant math library routines (OSF/1)"}, \
197 {"ieee", MASK_IEEE|MASK_IEEE_CONFORMANT, \
198 "Emit IEEE-conformant code, without inexact exceptions"}, \
199 {"ieee-with-inexact", MASK_IEEE_WITH_INEXACT|MASK_IEEE_CONFORMANT, \
200 "Emit IEEE-conformant code, with inexact exceptions"}, \
201 {"build-constants", MASK_BUILD_CONSTANTS, \
202 "Do not emit complex integer constants to read-only memory"}, \
203 {"float-vax", MASK_FLOAT_VAX, "Use VAX fp"}, \
204 {"float-ieee", -MASK_FLOAT_VAX, "Do not use VAX fp"}, \
205 {"bwx", MASK_BWX, "Emit code for the byte/word ISA extension"}, \
206 {"no-bwx", -MASK_BWX, ""}, \
207 {"cix", MASK_CIX, "Emit code for the counting ISA extension"}, \
208 {"no-cix", -MASK_CIX, ""}, \
209 {"max", MASK_MAX, "Emit code for the motion video ISA extension"}, \
210 {"no-max", -MASK_MAX, ""}, \
211 {"", TARGET_DEFAULT | TARGET_CPU_DEFAULT, ""} }
213 #define TARGET_DEFAULT MASK_FP|MASK_FPREGS
215 #ifndef TARGET_CPU_DEFAULT
216 #define TARGET_CPU_DEFAULT 0
219 /* This macro is similar to `TARGET_SWITCHES' but defines names of
220 command options that have values. Its definition is an initializer
221 with a subgrouping for each command option.
223 Each subgrouping contains a string constant, that defines the fixed
224 part of the option name, and the address of a variable. The
225 variable, type `char *', is set to the variable part of the given
226 option if the fixed part matches. The actual option name is made
227 by appending `-m' to the specified name.
229 Here is an example which defines `-mshort-data-NUMBER'. If the
230 given option is `-mshort-data-512', the variable `m88k_short_data'
231 will be set to the string `"512"'.
233 extern char *m88k_short_data;
234 #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */
236 extern char *alpha_cpu_string; /* For -mcpu= */
237 extern char *alpha_fprm_string; /* For -mfp-rounding-mode=[n|m|c|d] */
238 extern char *alpha_fptm_string; /* For -mfp-trap-mode=[n|u|su|sui] */
239 extern char *alpha_tp_string; /* For -mtrap-precision=[p|f|i] */
240 extern char *alpha_mlat_string; /* For -mmemory-latency= */
242 #define TARGET_OPTIONS \
244 {"cpu=", &alpha_cpu_string, \
245 "Generate code for a given CPU"}, \
246 {"fp-rounding-mode=", &alpha_fprm_string, \
247 "Control the generated fp rounding mode"}, \
248 {"fp-trap-mode=", &alpha_fptm_string, \
249 "Control the IEEE trap mode"}, \
250 {"trap-precision=", &alpha_tp_string, \
251 "Control the precision given to fp exceptions"}, \
252 {"memory-latency=", &alpha_mlat_string, \
253 "Tune expected memory latency"}, \
256 /* Attempt to describe CPU characteristics to the preprocessor. */
258 /* Corresponding to amask... */
259 #define CPP_AM_BWX_SPEC "-D__alpha_bwx__ -Acpu(bwx)"
260 #define CPP_AM_MAX_SPEC "-D__alpha_max__ -Acpu(max)"
261 #define CPP_AM_CIX_SPEC "-D__alpha_cix__ -Acpu(cix)"
263 /* Corresponding to implver... */
264 #define CPP_IM_EV4_SPEC "-D__alpha_ev4__ -Acpu(ev4)"
265 #define CPP_IM_EV5_SPEC "-D__alpha_ev5__ -Acpu(ev5)"
266 #define CPP_IM_EV6_SPEC "-D__alpha_ev6__ -Acpu(ev6)"
268 /* Common combinations. */
269 #define CPP_CPU_EV4_SPEC "%(cpp_im_ev4)"
270 #define CPP_CPU_EV5_SPEC "%(cpp_im_ev5)"
271 #define CPP_CPU_EV56_SPEC "%(cpp_im_ev5) %(cpp_am_bwx)"
272 #define CPP_CPU_PCA56_SPEC "%(cpp_im_ev5) %(cpp_am_bwx) %(cpp_am_max)"
273 #define CPP_CPU_EV6_SPEC "%(cpp_im_ev6) %(cpp_am_bwx) %(cpp_am_max) %(cpp_am_cix)"
275 #ifndef CPP_CPU_DEFAULT_SPEC
276 # if TARGET_CPU_DEFAULT & MASK_CPU_EV6
277 # define CPP_CPU_DEFAULT_SPEC CPP_CPU_EV6_SPEC
279 # if TARGET_CPU_DEFAULT & MASK_CPU_EV5
280 # if TARGET_CPU_DEFAULT & MASK_MAX
281 # define CPP_CPU_DEFAULT_SPEC CPP_CPU_PCA56_SPEC
283 # if TARGET_CPU_DEFAULT & MASK_BWX
284 # define CPP_CPU_DEFAULT_SPEC CPP_CPU_EV56_SPEC
286 # define CPP_CPU_DEFAULT_SPEC CPP_CPU_EV5_SPEC
290 # define CPP_CPU_DEFAULT_SPEC CPP_CPU_EV4_SPEC
293 #endif /* CPP_CPU_DEFAULT_SPEC */
296 #define CPP_CPU_SPEC "\
297 %{!undef:-Acpu(alpha) -Amachine(alpha) -D__alpha -D__alpha__ \
298 %{mcpu=ev4|mcpu=21064:%(cpp_cpu_ev4) }\
299 %{mcpu=ev5|mcpu=21164:%(cpp_cpu_ev5) }\
300 %{mcpu=ev56|mcpu=21164a:%(cpp_cpu_ev56) }\
301 %{mcpu=pca56|mcpu=21164pc|mcpu=21164PC:%(cpp_cpu_pca56) }\
302 %{mcpu=ev6|mcpu=21264:%(cpp_cpu_ev6) }\
303 %{!mcpu*:%(cpp_cpu_default) }}"
306 /* This macro defines names of additional specifications to put in the
307 specs that can be used in various specifications like CC1_SPEC. Its
308 definition is an initializer with a subgrouping for each command option.
310 Each subgrouping contains a string constant, that defines the
311 specification name, and a string constant that used by the GNU CC driver
314 Do not define this macro if it does not need to do anything. */
316 #ifndef SUBTARGET_EXTRA_SPECS
317 #define SUBTARGET_EXTRA_SPECS
320 #define EXTRA_SPECS \
321 { "cpp_am_bwx", CPP_AM_BWX_SPEC }, \
322 { "cpp_am_max", CPP_AM_MAX_SPEC }, \
323 { "cpp_am_cix", CPP_AM_CIX_SPEC }, \
324 { "cpp_im_ev4", CPP_IM_EV4_SPEC }, \
325 { "cpp_im_ev5", CPP_IM_EV5_SPEC }, \
326 { "cpp_im_ev6", CPP_IM_EV6_SPEC }, \
327 { "cpp_cpu_ev4", CPP_CPU_EV4_SPEC }, \
328 { "cpp_cpu_ev5", CPP_CPU_EV5_SPEC }, \
329 { "cpp_cpu_ev56", CPP_CPU_EV56_SPEC }, \
330 { "cpp_cpu_pca56", CPP_CPU_PCA56_SPEC }, \
331 { "cpp_cpu_ev6", CPP_CPU_EV6_SPEC }, \
332 { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \
333 { "cpp_cpu", CPP_CPU_SPEC }, \
334 { "cpp_subtarget", CPP_SUBTARGET_SPEC }, \
335 SUBTARGET_EXTRA_SPECS
338 /* Sometimes certain combinations of command options do not make sense
339 on a particular target machine. You can define a macro
340 `OVERRIDE_OPTIONS' to take account of this. This macro, if
341 defined, is executed once just after all the command options have
344 On the Alpha, it is used to translate target-option strings into
347 extern void override_options ();
348 #define OVERRIDE_OPTIONS override_options ()
351 /* Define this macro to change register usage conditional on target flags.
353 On the Alpha, we use this to disable the floating-point registers when
356 #define CONDITIONAL_REGISTER_USAGE \
357 if (! TARGET_FPREGS) \
358 for (i = 32; i < 63; i++) \
359 fixed_regs[i] = call_used_regs[i] = 1;
361 /* Show we can debug even without a frame pointer. */
362 #define CAN_DEBUG_WITHOUT_FP
364 /* target machine storage layout */
366 /* Define to enable software floating point emulation. */
367 #define REAL_ARITHMETIC
369 /* The following #defines are used when compiling the routines in
370 libgcc1.c. Since the Alpha calling conventions require single
371 precision floats to be passed in the floating-point registers
372 (rather than in the general registers) we have to build the
373 libgcc1.c routines in such a way that they know the actual types
374 of their formal arguments and the actual types of their return
375 values. Otherwise, gcc will generate calls to the libgcc1.c
376 routines, passing arguments in the floating-point registers,
377 but the libgcc1.c routines will expect their arguments on the
378 stack (where the Alpha calling conventions require structs &
379 unions to be passed). */
381 #define FLOAT_VALUE_TYPE double
382 #define INTIFY(FLOATVAL) (FLOATVAL)
383 #define FLOATIFY(INTVAL) (INTVAL)
384 #define FLOAT_ARG_TYPE double
386 /* Define the size of `int'. The default is the same as the word size. */
387 #define INT_TYPE_SIZE 32
389 /* Define the size of `long long'. The default is the twice the word size. */
390 #define LONG_LONG_TYPE_SIZE 64
392 /* The two floating-point formats we support are S-floating, which is
393 4 bytes, and T-floating, which is 8 bytes. `float' is S and `double'
394 and `long double' are T. */
396 #define FLOAT_TYPE_SIZE 32
397 #define DOUBLE_TYPE_SIZE 64
398 #define LONG_DOUBLE_TYPE_SIZE 64
400 #define WCHAR_TYPE "unsigned int"
401 #define WCHAR_TYPE_SIZE 32
403 /* Define this macro if it is advisable to hold scalars in registers
404 in a wider mode than that declared by the program. In such cases,
405 the value is constrained to be within the bounds of the declared
406 type, but kept valid in the wider mode. The signedness of the
407 extension may differ from that of the type.
409 For Alpha, we always store objects in a full register. 32-bit objects
410 are always sign-extended, but smaller objects retain their signedness. */
412 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
413 if (GET_MODE_CLASS (MODE) == MODE_INT \
414 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
416 if ((MODE) == SImode) \
421 /* Define this if function arguments should also be promoted using the above
424 #define PROMOTE_FUNCTION_ARGS
426 /* Likewise, if the function return value is promoted. */
428 #define PROMOTE_FUNCTION_RETURN
430 /* Define this if most significant bit is lowest numbered
431 in instructions that operate on numbered bit-fields.
433 There are no such instructions on the Alpha, but the documentation
435 #define BITS_BIG_ENDIAN 0
437 /* Define this if most significant byte of a word is the lowest numbered.
438 This is false on the Alpha. */
439 #define BYTES_BIG_ENDIAN 0
441 /* Define this if most significant word of a multiword number is lowest
444 For Alpha we can decide arbitrarily since there are no machine instructions
445 for them. Might as well be consistent with bytes. */
446 #define WORDS_BIG_ENDIAN 0
448 /* number of bits in an addressable storage unit */
449 #define BITS_PER_UNIT 8
451 /* Width in bits of a "word", which is the contents of a machine register.
452 Note that this is not necessarily the width of data type `int';
453 if using 16-bit ints on a 68000, this would still be 32.
454 But on a machine with 16-bit registers, this would be 16. */
455 #define BITS_PER_WORD 64
457 /* Width of a word, in units (bytes). */
458 #define UNITS_PER_WORD 8
460 /* Width in bits of a pointer.
461 See also the macro `Pmode' defined below. */
462 #define POINTER_SIZE 64
464 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
465 #define PARM_BOUNDARY 64
467 /* Boundary (in *bits*) on which stack pointer should be aligned. */
468 #define STACK_BOUNDARY 64
470 /* Allocation boundary (in *bits*) for the code of a function. */
471 #define FUNCTION_BOUNDARY 256
473 /* Alignment of field after `int : 0' in a structure. */
474 #define EMPTY_FIELD_BOUNDARY 64
476 /* Every structure's size must be a multiple of this. */
477 #define STRUCTURE_SIZE_BOUNDARY 8
479 /* A bitfield declared as `int' forces `int' alignment for the struct. */
480 #define PCC_BITFIELD_TYPE_MATTERS 1
482 /* Align loop starts for optimal branching.
484 ??? Kludge this and the next macro for the moment by not doing anything if
485 we don't optimize and also if we are writing ECOFF symbols to work around
486 a bug in DEC's assembler. */
488 #define LOOP_ALIGN(LABEL) \
489 (optimize > 0 && write_symbols != SDB_DEBUG ? 4 : 0)
491 /* This is how to align an instruction for optimal branching. On
492 Alpha we'll get better performance by aligning on an octaword
495 #define LABEL_ALIGN_AFTER_BARRIER(FILE) \
496 (optimize > 0 && write_symbols != SDB_DEBUG ? 4 : 0)
498 /* No data type wants to be aligned rounder than this. */
499 #define BIGGEST_ALIGNMENT 64
501 /* For atomic access to objects, must have at least 32-bit alignment
502 unless the machine has byte operations. */
503 #define MINIMUM_ATOMIC_ALIGNMENT (TARGET_BWX ? 8 : 32)
505 /* Align all constants and variables to at least a word boundary so
506 we can pick up pieces of them faster. */
507 /* ??? Only if block-move stuff knows about different source/destination
510 #define CONSTANT_ALIGNMENT(EXP, ALIGN) MAX ((ALIGN), BITS_PER_WORD)
511 #define DATA_ALIGNMENT(EXP, ALIGN) MAX ((ALIGN), BITS_PER_WORD)
514 /* Set this non-zero if move instructions will actually fail to work
515 when given unaligned data.
517 Since we get an error message when we do one, call them invalid. */
519 #define STRICT_ALIGNMENT 1
521 /* Set this non-zero if unaligned move instructions are extremely slow.
523 On the Alpha, they trap. */
525 #define SLOW_UNALIGNED_ACCESS 1
527 /* Standard register usage. */
529 /* Number of actual hardware registers.
530 The hardware registers are assigned numbers for the compiler
531 from 0 to just below FIRST_PSEUDO_REGISTER.
532 All registers that the compiler knows about must be given numbers,
533 even those that are not normally considered general registers.
535 We define all 32 integer registers, even though $31 is always zero,
536 and all 32 floating-point registers, even though $f31 is also
537 always zero. We do not bother defining the FP status register and
538 there are no other registers.
540 Since $31 is always zero, we will use register number 31 as the
541 argument pointer. It will never appear in the generated code
542 because we will always be eliminating it in favor of the stack
543 pointer or hardware frame pointer.
545 Likewise, we use $f31 for the frame pointer, which will always
546 be eliminated in favor of the hardware frame pointer or the
549 #define FIRST_PSEUDO_REGISTER 64
551 /* 1 for registers that have pervasive standard uses
552 and are not available for the register allocator. */
554 #define FIXED_REGISTERS \
555 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
556 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, \
557 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
558 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 }
560 /* 1 for registers not available across function calls.
561 These must include the FIXED_REGISTERS and also any
562 registers that can be used without being saved.
563 The latter must include the registers where values are returned
564 and the register where structure-value addresses are passed.
565 Aside from that, you can include as many other registers as you like. */
566 #define CALL_USED_REGISTERS \
567 {1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
568 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, \
569 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, \
570 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }
572 /* List the order in which to allocate registers. Each register must be
573 listed once, even those in FIXED_REGISTERS.
575 We allocate in the following order:
576 $f10-$f15 (nonsaved floating-point register)
578 $f21-$f16 (likewise, but input args)
579 $f0 (nonsaved, but return value)
580 $f1 (nonsaved, but immediate before saved)
581 $f2-$f9 (saved floating-point registers)
582 $1-$8 (nonsaved integer registers)
585 $0 (likewise, but return value)
586 $21-$16 (likewise, but input args)
587 $27 (procedure value in OSF, nonsaved in NT)
588 $9-$14 (saved integer registers)
592 $30, $31, $f31 (stack pointer and always zero/ap & fp) */
594 #define REG_ALLOC_ORDER \
595 {42, 43, 44, 45, 46, 47, \
596 54, 55, 56, 57, 58, 59, 60, 61, 62, \
597 53, 52, 51, 50, 49, 48, \
599 34, 35, 36, 37, 38, 39, 40, 41, \
600 1, 2, 3, 4, 5, 6, 7, 8, \
604 21, 20, 19, 18, 17, 16, \
606 9, 10, 11, 12, 13, 14, \
612 /* Return number of consecutive hard regs needed starting at reg REGNO
613 to hold something of mode MODE.
614 This is ordinarily the length in words of a value of mode MODE
615 but can be less for certain modes in special long registers. */
617 #define HARD_REGNO_NREGS(REGNO, MODE) \
618 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
620 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
621 On Alpha, the integer registers can hold any mode. The floating-point
622 registers can hold 32-bit and 64-bit integers as well, but not 16-bit
623 or 8-bit values. If we only allowed the larger integers into FP registers,
624 we'd have to say that QImode and SImode aren't tiable, which is a
625 pain. So say all registers can hold everything and see how that works. */
627 #define HARD_REGNO_MODE_OK(REGNO, MODE) 1
629 /* Value is 1 if it is a good idea to tie two pseudo registers
630 when one has mode MODE1 and one has mode MODE2.
631 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
632 for any hard reg, then this must be 0 for correct output. */
634 #define MODES_TIEABLE_P(MODE1, MODE2) 1
636 /* Specify the registers used for certain standard purposes.
637 The values of these macros are register numbers. */
639 /* Alpha pc isn't overloaded on a register that the compiler knows about. */
640 /* #define PC_REGNUM */
642 /* Register to use for pushing function arguments. */
643 #define STACK_POINTER_REGNUM 30
645 /* Base register for access to local variables of the function. */
646 #define HARD_FRAME_POINTER_REGNUM 15
648 /* Value should be nonzero if functions must have frame pointers.
649 Zero means the frame pointer need not be set up (and parms
650 may be accessed via the stack pointer) in functions that seem suitable.
651 This is computed in `reload', in reload1.c. */
652 #define FRAME_POINTER_REQUIRED 0
654 /* Base register for access to arguments of the function. */
655 #define ARG_POINTER_REGNUM 31
657 /* Base register for access to local variables of function. */
658 #define FRAME_POINTER_REGNUM 63
660 /* Register in which static-chain is passed to a function.
662 For the Alpha, this is based on an example; the calling sequence
663 doesn't seem to specify this. */
664 #define STATIC_CHAIN_REGNUM 1
666 /* Register in which address to store a structure value
667 arrives in the function. On the Alpha, the address is passed
668 as a hidden argument. */
669 #define STRUCT_VALUE 0
671 /* Define the classes of registers for register constraints in the
672 machine description. Also define ranges of constants.
674 One of the classes must always be named ALL_REGS and include all hard regs.
675 If there is more than one class, another class must be named NO_REGS
676 and contain no registers.
678 The name GENERAL_REGS must be the name of a class (or an alias for
679 another name such as ALL_REGS). This is the class of registers
680 that is allowed by "g" or "r" in a register constraint.
681 Also, registers outside this class are allocated only when
682 instructions express preferences for them.
684 The classes must be numbered in nondecreasing order; that is,
685 a larger-numbered class must never be contained completely
686 in a smaller-numbered class.
688 For any two classes, it is very desirable that there be another
689 class that represents their union. */
691 enum reg_class { NO_REGS, GENERAL_REGS, FLOAT_REGS, ALL_REGS,
694 #define N_REG_CLASSES (int) LIM_REG_CLASSES
696 /* Give names of register classes as strings for dump file. */
698 #define REG_CLASS_NAMES \
699 {"NO_REGS", "GENERAL_REGS", "FLOAT_REGS", "ALL_REGS" }
701 /* Define which registers fit in which classes.
702 This is an initializer for a vector of HARD_REG_SET
703 of length N_REG_CLASSES. */
705 #define REG_CLASS_CONTENTS \
706 { {0, 0}, {~0, 0x80000000}, {0, 0x7fffffff}, {~0, ~0} }
708 /* The same information, inverted:
709 Return the class number of the smallest class containing
710 reg number REGNO. This could be a conditional expression
711 or could index an array. */
713 #define REGNO_REG_CLASS(REGNO) \
714 ((REGNO) >= 32 && (REGNO) <= 62 ? FLOAT_REGS : GENERAL_REGS)
716 /* The class value for index registers, and the one for base regs. */
717 #define INDEX_REG_CLASS NO_REGS
718 #define BASE_REG_CLASS GENERAL_REGS
720 /* Get reg_class from a letter such as appears in the machine description. */
722 #define REG_CLASS_FROM_LETTER(C) \
723 ((C) == 'f' ? FLOAT_REGS : NO_REGS)
725 /* Define this macro to change register usage conditional on target flags. */
726 /* #define CONDITIONAL_REGISTER_USAGE */
728 /* The letters I, J, K, L, M, N, O, and P in a register constraint string
729 can be used to stand for particular ranges of immediate operands.
730 This macro defines what the ranges are.
731 C is the letter, and VALUE is a constant value.
732 Return 1 if VALUE is in the range specified by C.
735 `I' is used for the range of constants most insns can contain.
736 `J' is the constant zero.
737 `K' is used for the constant in an LDA insn.
738 `L' is used for the constant in a LDAH insn.
739 `M' is used for the constants that can be AND'ed with using a ZAP insn.
740 `N' is used for complemented 8-bit constants.
741 `O' is used for negated 8-bit constants.
742 `P' is used for the constants 1, 2 and 3. */
744 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
745 ((C) == 'I' ? (unsigned HOST_WIDE_INT) (VALUE) < 0x100 \
746 : (C) == 'J' ? (VALUE) == 0 \
747 : (C) == 'K' ? (unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000 \
748 : (C) == 'L' ? (((VALUE) & 0xffff) == 0 \
749 && (((VALUE)) >> 31 == -1 || (VALUE) >> 31 == 0)) \
750 : (C) == 'M' ? zap_mask (VALUE) \
751 : (C) == 'N' ? (unsigned HOST_WIDE_INT) (~ (VALUE)) < 0x100 \
752 : (C) == 'O' ? (unsigned HOST_WIDE_INT) (- (VALUE)) < 0x100 \
753 : (C) == 'P' ? (VALUE) == 1 || (VALUE) == 2 || (VALUE) == 3 \
756 /* Similar, but for floating or large integer constants, and defining letters
757 G and H. Here VALUE is the CONST_DOUBLE rtx itself.
759 For Alpha, `G' is the floating-point constant zero. `H' is a CONST_DOUBLE
760 that is the operand of a ZAP insn. */
762 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
763 ((C) == 'G' ? (GET_MODE_CLASS (GET_MODE (VALUE)) == MODE_FLOAT \
764 && (VALUE) == CONST0_RTX (GET_MODE (VALUE))) \
765 : (C) == 'H' ? (GET_MODE (VALUE) == VOIDmode \
766 && zap_mask (CONST_DOUBLE_LOW (VALUE)) \
767 && zap_mask (CONST_DOUBLE_HIGH (VALUE))) \
770 /* Optional extra constraints for this machine.
772 For the Alpha, `Q' means that this is a memory operand but not a
773 reference to an unaligned location.
775 `R' is a SYMBOL_REF that has SYMBOL_REF_FLAG set or is the current
778 'S' is a 6-bit constant (valid for a shift insn). */
780 #define EXTRA_CONSTRAINT(OP, C) \
781 ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) != AND \
782 : (C) == 'R' ? current_file_function_operand (OP, Pmode) \
783 : (C) == 'S' ? (GET_CODE (OP) == CONST_INT \
784 && (unsigned HOST_WIDE_INT) INTVAL (OP) < 64) \
787 /* Given an rtx X being reloaded into a reg required to be
788 in class CLASS, return the class of reg to actually use.
789 In general this is just CLASS; but on some machines
790 in some cases it is preferable to use a more restrictive class.
792 On the Alpha, all constants except zero go into a floating-point
793 register via memory. */
795 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
796 (CONSTANT_P (X) && (X) != const0_rtx && (X) != CONST0_RTX (GET_MODE (X)) \
797 ? ((CLASS) == FLOAT_REGS || (CLASS) == NO_REGS ? NO_REGS : GENERAL_REGS)\
800 /* Loading and storing HImode or QImode values to and from memory
801 usually requires a scratch register. The exceptions are loading
802 QImode and HImode from an aligned address to a general register
803 unless byte instructions are permitted.
804 We also cannot load an unaligned address or a paradoxical SUBREG into an
807 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,IN) \
808 (((GET_CODE (IN) == MEM \
809 || (GET_CODE (IN) == REG && REGNO (IN) >= FIRST_PSEUDO_REGISTER) \
810 || (GET_CODE (IN) == SUBREG \
811 && (GET_CODE (SUBREG_REG (IN)) == MEM \
812 || (GET_CODE (SUBREG_REG (IN)) == REG \
813 && REGNO (SUBREG_REG (IN)) >= FIRST_PSEUDO_REGISTER)))) \
814 && (((CLASS) == FLOAT_REGS \
815 && ((MODE) == SImode || (MODE) == HImode || (MODE) == QImode)) \
816 || (((MODE) == QImode || (MODE) == HImode) \
817 && ! TARGET_BWX && unaligned_memory_operand (IN, MODE)))) \
819 : ((CLASS) == FLOAT_REGS && GET_CODE (IN) == MEM \
820 && GET_CODE (XEXP (IN, 0)) == AND) ? GENERAL_REGS \
821 : ((CLASS) == FLOAT_REGS && GET_CODE (IN) == SUBREG \
822 && (GET_MODE_SIZE (GET_MODE (IN)) \
823 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (IN))))) ? GENERAL_REGS \
826 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,OUT) \
827 (((GET_CODE (OUT) == MEM \
828 || (GET_CODE (OUT) == REG && REGNO (OUT) >= FIRST_PSEUDO_REGISTER) \
829 || (GET_CODE (OUT) == SUBREG \
830 && (GET_CODE (SUBREG_REG (OUT)) == MEM \
831 || (GET_CODE (SUBREG_REG (OUT)) == REG \
832 && REGNO (SUBREG_REG (OUT)) >= FIRST_PSEUDO_REGISTER)))) \
833 && ((((MODE) == HImode || (MODE) == QImode) \
834 && (! TARGET_BWX || (CLASS) == FLOAT_REGS)) \
835 || ((MODE) == SImode && (CLASS) == FLOAT_REGS))) \
837 : ((CLASS) == FLOAT_REGS && GET_CODE (OUT) == MEM \
838 && GET_CODE (XEXP (OUT, 0)) == AND) ? GENERAL_REGS \
839 : ((CLASS) == FLOAT_REGS && GET_CODE (OUT) == SUBREG \
840 && (GET_MODE_SIZE (GET_MODE (OUT)) \
841 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (OUT))))) ? GENERAL_REGS \
844 /* If we are copying between general and FP registers, we need a memory
845 location unless the CIX extension is available. */
847 #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
848 (! TARGET_CIX && (CLASS1) != (CLASS2))
850 /* Specify the mode to be used for memory when a secondary memory
851 location is needed. If MODE is floating-point, use it. Otherwise,
852 widen to a word like the default. This is needed because we always
853 store integers in FP registers in quadword format. This whole
854 area is very tricky! */
855 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
856 (GET_MODE_CLASS (MODE) == MODE_FLOAT ? (MODE) \
857 : GET_MODE_SIZE (MODE) >= 4 ? (MODE) \
858 : mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0))
860 /* Return the maximum number of consecutive registers
861 needed to represent mode MODE in a register of class CLASS. */
863 #define CLASS_MAX_NREGS(CLASS, MODE) \
864 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
866 /* If defined, gives a class of registers that cannot be used as the
867 operand of a SUBREG that changes the size of the object. */
869 #define CLASS_CANNOT_CHANGE_SIZE FLOAT_REGS
871 /* Define the cost of moving between registers of various classes. Moving
872 between FLOAT_REGS and anything else except float regs is expensive.
873 In fact, we make it quite expensive because we really don't want to
874 do these moves unless it is clearly worth it. Optimizations may
875 reduce the impact of not being able to allocate a pseudo to a
878 #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
879 (((CLASS1) == FLOAT_REGS) == ((CLASS2) == FLOAT_REGS) \
881 : TARGET_CIX ? 3 : 4+2*alpha_memory_latency)
883 /* A C expressions returning the cost of moving data of MODE from a register to
886 On the Alpha, bump this up a bit. */
888 extern int alpha_memory_latency;
889 #define MEMORY_MOVE_COST(MODE,CLASS,IN) (2*alpha_memory_latency)
891 /* Provide the cost of a branch. Exact meaning under development. */
892 #define BRANCH_COST 5
894 /* Adjust the cost of dependencies. */
896 #define ADJUST_COST(INSN,LINK,DEP,COST) \
897 (COST) = alpha_adjust_cost (INSN, LINK, DEP, COST)
899 /* Stack layout; function entry, exit and calling. */
901 /* Define this if pushing a word on the stack
902 makes the stack pointer a smaller address. */
903 #define STACK_GROWS_DOWNWARD
905 /* Define this if the nominal address of the stack frame
906 is at the high-address end of the local variables;
907 that is, each additional local variable allocated
908 goes at a more negative offset in the frame. */
909 /* #define FRAME_GROWS_DOWNWARD */
911 /* Offset within stack frame to start allocating local variables at.
912 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
913 first local allocated. Otherwise, it is the offset to the BEGINNING
914 of the first local allocated. */
916 #define STARTING_FRAME_OFFSET 0
918 /* If we generate an insn to push BYTES bytes,
919 this says how many the stack pointer really advances by.
920 On Alpha, don't define this because there are no push insns. */
921 /* #define PUSH_ROUNDING(BYTES) */
923 /* Define this to be nonzero if stack checking is built into the ABI. */
924 #define STACK_CHECK_BUILTIN 1
926 /* Define this if the maximum size of all the outgoing args is to be
927 accumulated and pushed during the prologue. The amount can be
928 found in the variable current_function_outgoing_args_size. */
929 #define ACCUMULATE_OUTGOING_ARGS
931 /* Offset of first parameter from the argument pointer register value. */
933 #define FIRST_PARM_OFFSET(FNDECL) 0
935 /* Definitions for register eliminations.
937 We have two registers that can be eliminated on the Alpha. First, the
938 frame pointer register can often be eliminated in favor of the stack
939 pointer register. Secondly, the argument pointer register can always be
940 eliminated; it is replaced with either the stack or frame pointer. */
942 /* This is an array of structures. Each structure initializes one pair
943 of eliminable registers. The "from" register number is given first,
944 followed by "to". Eliminations of the same "from" register are listed
945 in order of preference. */
947 #define ELIMINABLE_REGS \
948 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
949 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
950 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
951 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
953 /* Given FROM and TO register numbers, say whether this elimination is allowed.
954 Frame pointer elimination is automatically handled.
956 All eliminations are valid since the cases where FP can't be
957 eliminated are already handled. */
959 #define CAN_ELIMINATE(FROM, TO) 1
961 /* Round up to a multiple of 16 bytes. */
962 #define ALPHA_ROUND(X) (((X) + 15) & ~ 15)
964 /* Define the offset between two registers, one to be eliminated, and the other
965 its replacement, at the start of a routine. */
966 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
967 { if ((FROM) == FRAME_POINTER_REGNUM) \
968 (OFFSET) = (ALPHA_ROUND (current_function_outgoing_args_size) \
969 + alpha_sa_size ()); \
970 else if ((FROM) == ARG_POINTER_REGNUM) \
971 (OFFSET) = (ALPHA_ROUND (current_function_outgoing_args_size) \
973 + (ALPHA_ROUND (get_frame_size () \
974 + current_function_pretend_args_size) \
975 - current_function_pretend_args_size)); \
978 /* Define this if stack space is still allocated for a parameter passed
980 /* #define REG_PARM_STACK_SPACE */
982 /* Value is the number of bytes of arguments automatically
983 popped when returning from a subroutine call.
984 FUNDECL is the declaration node of the function (as a tree),
985 FUNTYPE is the data type of the function (as a tree),
986 or for a library call it is an identifier node for the subroutine name.
987 SIZE is the number of bytes of arguments passed on the stack. */
989 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
991 /* Define how to find the value returned by a function.
992 VALTYPE is the data type of the value (as a tree).
993 If the precise function being called is known, FUNC is its FUNCTION_DECL;
994 otherwise, FUNC is 0.
996 On Alpha the value is found in $0 for integer functions and
997 $f0 for floating-point functions. */
999 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1001 ((INTEGRAL_TYPE_P (VALTYPE) \
1002 && TYPE_PRECISION (VALTYPE) < BITS_PER_WORD) \
1003 || POINTER_TYPE_P (VALTYPE)) \
1004 ? word_mode : TYPE_MODE (VALTYPE), \
1006 && (TREE_CODE (VALTYPE) == REAL_TYPE \
1007 || TREE_CODE (VALTYPE) == COMPLEX_TYPE)) \
1010 /* Define how to find the value returned by a library function
1011 assuming the value has mode MODE. */
1013 #define LIBCALL_VALUE(MODE) \
1014 gen_rtx (REG, MODE, \
1016 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1017 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1020 /* The definition of this macro implies that there are cases where
1021 a scalar value cannot be returned in registers.
1023 For the Alpha, any structure or union type is returned in memory, as
1024 are integers whose size is larger than 64 bits. */
1026 #define RETURN_IN_MEMORY(TYPE) \
1027 (TYPE_MODE (TYPE) == BLKmode \
1028 || (TREE_CODE (TYPE) == INTEGER_TYPE && TYPE_PRECISION (TYPE) > 64))
1030 /* 1 if N is a possible register number for a function value
1031 as seen by the caller. */
1033 #define FUNCTION_VALUE_REGNO_P(N) \
1034 ((N) == 0 || (N) == 1 || (N) == 32 || (N) == 33)
1036 /* 1 if N is a possible register number for function argument passing.
1037 On Alpha, these are $16-$21 and $f16-$f21. */
1039 #define FUNCTION_ARG_REGNO_P(N) \
1040 (((N) >= 16 && (N) <= 21) || ((N) >= 16 + 32 && (N) <= 21 + 32))
1042 /* Define a data type for recording info about an argument list
1043 during the scan of that argument list. This data type should
1044 hold all necessary information about the function itself
1045 and about the args processed so far, enough to enable macros
1046 such as FUNCTION_ARG to determine where the next arg should go.
1048 On Alpha, this is a single integer, which is a number of words
1049 of arguments scanned so far.
1050 Thus 6 or more means all following args should go on the stack. */
1052 #define CUMULATIVE_ARGS int
1054 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1055 for a call to a function whose data type is FNTYPE.
1056 For a library call, FNTYPE is 0. */
1058 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) (CUM) = 0
1060 /* Define intermediate macro to compute the size (in registers) of an argument
1063 #define ALPHA_ARG_SIZE(MODE, TYPE, NAMED) \
1064 ((MODE) != BLKmode \
1065 ? (GET_MODE_SIZE (MODE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD \
1066 : (int_size_in_bytes (TYPE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
1068 /* Update the data in CUM to advance over an argument
1069 of mode MODE and data type TYPE.
1070 (TYPE is null for libcalls where that information may not be available.) */
1072 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1073 if (MUST_PASS_IN_STACK (MODE, TYPE)) \
1076 (CUM) += ALPHA_ARG_SIZE (MODE, TYPE, NAMED)
1078 /* Determine where to put an argument to a function.
1079 Value is zero to push the argument on the stack,
1080 or a hard register in which to store the argument.
1082 MODE is the argument's machine mode.
1083 TYPE is the data type of the argument (as a tree).
1084 This is null for libcalls where that information may
1086 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1087 the preceding args and about the function being called.
1088 NAMED is nonzero if this argument is a named parameter
1089 (otherwise it is an extra parameter matching an ellipsis).
1091 On Alpha the first 6 words of args are normally in registers
1092 and the rest are pushed. */
1094 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1095 ((CUM) < 6 && ! MUST_PASS_IN_STACK (MODE, TYPE) \
1096 ? gen_rtx(REG, (MODE), \
1097 (CUM) + 16 + ((TARGET_FPREGS \
1098 && (GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT \
1099 || GET_MODE_CLASS (MODE) == MODE_FLOAT)) \
1103 /* Specify the padding direction of arguments.
1105 On the Alpha, we must pad upwards in order to be able to pass args in
1108 #define FUNCTION_ARG_PADDING(MODE, TYPE) upward
1110 /* For an arg passed partly in registers and partly in memory,
1111 this is the number of registers used.
1112 For args passed entirely in registers or entirely in memory, zero. */
1114 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1115 ((CUM) < 6 && 6 < (CUM) + ALPHA_ARG_SIZE (MODE, TYPE, NAMED) \
1118 /* Perform any needed actions needed for a function that is receiving a
1119 variable number of arguments.
1123 MODE and TYPE are the mode and type of the current parameter.
1125 PRETEND_SIZE is a variable that should be set to the amount of stack
1126 that must be pushed by the prolog to pretend that our caller pushed
1129 Normally, this macro will push all remaining incoming registers on the
1130 stack and set PRETEND_SIZE to the length of the registers pushed.
1132 On the Alpha, we allocate space for all 12 arg registers, but only
1133 push those that are remaining.
1135 However, if NO registers need to be saved, don't allocate any space.
1136 This is not only because we won't need the space, but because AP includes
1137 the current_pretend_args_size and we don't want to mess up any
1138 ap-relative addresses already made.
1140 If we are not to use the floating-point registers, save the integer
1141 registers where we would put the floating-point registers. This is
1142 not the most efficient way to implement varargs with just one register
1143 class, but it isn't worth doing anything more efficient in this rare
1147 #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
1152 move_block_from_reg \
1154 gen_rtx (MEM, BLKmode, \
1155 plus_constant (virtual_incoming_args_rtx, \
1156 ((CUM) + 6)* UNITS_PER_WORD)), \
1157 6 - (CUM), (6 - (CUM)) * UNITS_PER_WORD); \
1158 move_block_from_reg \
1159 (16 + (TARGET_FPREGS ? 32 : 0) + CUM, \
1160 gen_rtx (MEM, BLKmode, \
1161 plus_constant (virtual_incoming_args_rtx, \
1162 (CUM) * UNITS_PER_WORD)), \
1163 6 - (CUM), (6 - (CUM)) * UNITS_PER_WORD); \
1164 emit_insn (gen_blockage ()); \
1166 PRETEND_SIZE = 12 * UNITS_PER_WORD; \
1170 /* Try to output insns to set TARGET equal to the constant C if it can be
1171 done in less than N insns. Do all computations in MODE. Returns the place
1172 where the output has been placed if it can be done and the insns have been
1173 emitted. If it would take more than N insns, zero is returned and no
1174 insns and emitted. */
1175 extern struct rtx_def *alpha_emit_set_const ();
1176 extern struct rtx_def *alpha_emit_set_long_const ();
1177 extern struct rtx_def *alpha_emit_conditional_branch ();
1178 extern struct rtx_def *alpha_emit_conditional_move ();
1180 /* Generate necessary RTL for __builtin_saveregs().
1181 ARGLIST is the argument list; see expr.c. */
1182 extern struct rtx_def *alpha_builtin_saveregs ();
1183 #define EXPAND_BUILTIN_SAVEREGS(ARGLIST) alpha_builtin_saveregs (ARGLIST)
1185 /* Define the information needed to generate branch and scc insns. This is
1186 stored from the compare operation. Note that we can't use "rtx" here
1187 since it hasn't been defined! */
1189 extern struct rtx_def *alpha_compare_op0, *alpha_compare_op1;
1190 extern int alpha_compare_fp_p;
1192 /* Define the information needed to modify the epilogue for EH. */
1194 extern struct rtx_def *alpha_eh_epilogue_sp_ofs;
1196 /* Make (or fake) .linkage entry for function call.
1197 IS_LOCAL is 0 if name is used in call, 1 if name is used in definition. */
1198 extern void alpha_need_linkage ();
1200 /* This macro defines the start of an assembly comment. */
1202 #define ASM_COMMENT_START " #"
1204 /* This macro produces the initial definition of a function. */
1206 #define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL) \
1207 alpha_start_function(FILE,NAME,DECL);
1208 extern void alpha_start_function ();
1210 /* This macro closes up a function definition for the assembler. */
1212 #define ASM_DECLARE_FUNCTION_SIZE(FILE,NAME,DECL) \
1213 alpha_end_function(FILE,NAME,DECL)
1214 extern void alpha_end_function ();
1216 /* This macro notes the end of the prologue. */
1218 #define FUNCTION_END_PROLOGUE(FILE) output_end_prologue (FILE)
1219 extern void output_end_prologue ();
1221 /* Output any profiling code before the prologue. */
1223 #define PROFILE_BEFORE_PROLOGUE 1
1225 /* Output assembler code to FILE to increment profiler label # LABELNO
1226 for profiling a function entry. Under OSF/1, profiling is enabled
1227 by simply passing -pg to the assembler and linker. */
1229 #define FUNCTION_PROFILER(FILE, LABELNO)
1231 /* Output assembler code to FILE to initialize this source file's
1232 basic block profiling info, if that has not already been done.
1233 This assumes that __bb_init_func doesn't garble a1-a5. */
1235 #define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \
1237 ASM_OUTPUT_REG_PUSH (FILE, 16); \
1238 fputs ("\tlda $16,$PBX32\n", (FILE)); \
1239 fputs ("\tldq $26,0($16)\n", (FILE)); \
1240 fputs ("\tbne $26,1f\n", (FILE)); \
1241 fputs ("\tlda $27,__bb_init_func\n", (FILE)); \
1242 fputs ("\tjsr $26,($27),__bb_init_func\n", (FILE)); \
1243 fputs ("\tldgp $29,0($26)\n", (FILE)); \
1244 fputs ("1:\n", (FILE)); \
1245 ASM_OUTPUT_REG_POP (FILE, 16); \
1248 /* Output assembler code to FILE to increment the entry-count for
1249 the BLOCKNO'th basic block in this source file. */
1251 #define BLOCK_PROFILER(FILE, BLOCKNO) \
1253 int blockn = (BLOCKNO); \
1254 fputs ("\tsubq $30,16,$30\n", (FILE)); \
1255 fputs ("\tstq $26,0($30)\n", (FILE)); \
1256 fputs ("\tstq $27,8($30)\n", (FILE)); \
1257 fputs ("\tlda $26,$PBX34\n", (FILE)); \
1258 fprintf ((FILE), "\tldq $27,%d($26)\n", 8*blockn); \
1259 fputs ("\taddq $27,1,$27\n", (FILE)); \
1260 fprintf ((FILE), "\tstq $27,%d($26)\n", 8*blockn); \
1261 fputs ("\tldq $26,0($30)\n", (FILE)); \
1262 fputs ("\tldq $27,8($30)\n", (FILE)); \
1263 fputs ("\taddq $30,16,$30\n", (FILE)); \
1267 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1268 the stack pointer does not matter. The value is tested only in
1269 functions that have frame pointers.
1270 No definition is equivalent to always zero. */
1272 #define EXIT_IGNORE_STACK 1
1274 /* Output assembler code for a block containing the constant parts
1275 of a trampoline, leaving space for the variable parts.
1277 The trampoline should set the static chain pointer to value placed
1278 into the trampoline and should branch to the specified routine.
1279 Note that $27 has been set to the address of the trampoline, so we can
1280 use it for addressability of the two data items. Trampolines are always
1281 aligned to FUNCTION_BOUNDARY, which is 64 bits. */
1283 #define TRAMPOLINE_TEMPLATE(FILE) \
1285 fprintf (FILE, "\tldq $1,24($27)\n"); \
1286 fprintf (FILE, "\tldq $27,16($27)\n"); \
1287 fprintf (FILE, "\tjmp $31,($27),0\n"); \
1288 fprintf (FILE, "\tnop\n"); \
1289 fprintf (FILE, "\t.quad 0,0\n"); \
1292 /* Section in which to place the trampoline. On Alpha, instructions
1293 may only be placed in a text segment. */
1295 #define TRAMPOLINE_SECTION text_section
1297 /* Length in units of the trampoline for entering a nested function. */
1299 #define TRAMPOLINE_SIZE 32
1301 /* Emit RTL insns to initialize the variable parts of a trampoline.
1302 FNADDR is an RTX for the address of the function's pure code.
1303 CXT is an RTX for the static chain value for the function. */
1305 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1306 alpha_initialize_trampoline (TRAMP, FNADDR, CXT, 16, 24, 8)
1307 extern void alpha_initialize_trampoline ();
1309 /* A C expression whose value is RTL representing the value of the return
1310 address for the frame COUNT steps up from the current frame.
1311 FRAMEADDR is the frame pointer of the COUNT frame, or the frame pointer of
1312 the COUNT-1 frame if RETURN_ADDR_IN_PREVIOUS_FRAME is defined. */
1314 #define RETURN_ADDR_RTX alpha_return_addr
1315 extern struct rtx_def *alpha_return_addr ();
1317 /* Before the prologue, RA lives in $26. */
1318 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, 26)
1320 /* Initialize data used by insn expanders. This is called from insn_emit,
1321 once for every function before code is generated. */
1323 #define INIT_EXPANDERS alpha_init_expanders ()
1324 extern void alpha_init_expanders ();
1326 /* Addressing modes, and classification of registers for them. */
1328 /* #define HAVE_POST_INCREMENT 0 */
1329 /* #define HAVE_POST_DECREMENT 0 */
1331 /* #define HAVE_PRE_DECREMENT 0 */
1332 /* #define HAVE_PRE_INCREMENT 0 */
1334 /* Macros to check register numbers against specific register classes. */
1336 /* These assume that REGNO is a hard or pseudo reg number.
1337 They give nonzero only if REGNO is a hard reg of the suitable class
1338 or a pseudo reg currently allocated to a suitable hard reg.
1339 Since they use reg_renumber, they are safe only once reg_renumber
1340 has been allocated, which happens in local-alloc.c. */
1342 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
1343 #define REGNO_OK_FOR_BASE_P(REGNO) \
1344 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32 \
1345 || (REGNO) == 63 || reg_renumber[REGNO] == 63)
1347 /* Maximum number of registers that can appear in a valid memory address. */
1348 #define MAX_REGS_PER_ADDRESS 1
1350 /* Recognize any constant value that is a valid address. For the Alpha,
1351 there are only constants none since we want to use LDA to load any
1352 symbolic addresses into registers. */
1354 #define CONSTANT_ADDRESS_P(X) \
1355 (GET_CODE (X) == CONST_INT \
1356 && (unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
1358 /* Include all constant integers and constant doubles, but not
1359 floating-point, except for floating-point zero. */
1361 #define LEGITIMATE_CONSTANT_P(X) \
1362 (GET_MODE_CLASS (GET_MODE (X)) != MODE_FLOAT \
1363 || (X) == CONST0_RTX (GET_MODE (X)))
1365 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1366 and check its validity for a certain class.
1367 We have two alternate definitions for each of them.
1368 The usual definition accepts all pseudo regs; the other rejects
1369 them unless they have been allocated suitable hard regs.
1370 The symbol REG_OK_STRICT causes the latter definition to be used.
1372 Most source files want to accept pseudo regs in the hope that
1373 they will get allocated to the class that the insn wants them to be in.
1374 Source files for reload pass need to be strict.
1375 After reload, it makes no difference, since pseudo regs have
1376 been eliminated by then. */
1378 #ifndef REG_OK_STRICT
1380 /* Nonzero if X is a hard reg that can be used as an index
1381 or if it is a pseudo reg. */
1382 #define REG_OK_FOR_INDEX_P(X) 0
1383 /* Nonzero if X is a hard reg that can be used as a base reg
1384 or if it is a pseudo reg. */
1385 #define REG_OK_FOR_BASE_P(X) \
1386 (REGNO (X) < 32 || REGNO (X) == 63 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1390 /* Nonzero if X is a hard reg that can be used as an index. */
1391 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1392 /* Nonzero if X is a hard reg that can be used as a base reg. */
1393 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1397 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1398 that is a valid memory address for an instruction.
1399 The MODE argument is the machine mode for the MEM expression
1400 that wants to use this address.
1402 For Alpha, we have either a constant address or the sum of a register
1403 and a constant address, or just a register. For DImode, any of those
1404 forms can be surrounded with an AND that clear the low-order three bits;
1405 this is an "unaligned" access.
1407 First define the basic valid address. */
1409 #define GO_IF_LEGITIMATE_SIMPLE_ADDRESS(MODE, X, ADDR) \
1410 { if (REG_P (X) && REG_OK_FOR_BASE_P (X)) \
1412 if (CONSTANT_ADDRESS_P (X)) \
1414 if (GET_CODE (X) == PLUS \
1415 && REG_P (XEXP (X, 0)) \
1416 && REG_OK_FOR_BASE_P (XEXP (X, 0)) \
1417 && CONSTANT_ADDRESS_P (XEXP (X, 1))) \
1421 /* Now accept the simple address, or, for DImode only, an AND of a simple
1422 address that turns off the low three bits. */
1424 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1425 { GO_IF_LEGITIMATE_SIMPLE_ADDRESS (MODE, X, ADDR); \
1426 if ((MODE) == DImode \
1427 && GET_CODE (X) == AND \
1428 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1429 && INTVAL (XEXP (X, 1)) == -8) \
1430 GO_IF_LEGITIMATE_SIMPLE_ADDRESS (MODE, XEXP (X, 0), ADDR); \
1433 /* Try machine-dependent ways of modifying an illegitimate address
1434 to be legitimate. If we find one, return the new, valid address.
1435 This macro is used in only one place: `memory_address' in explow.c.
1437 OLDX is the address as it was before break_out_memory_refs was called.
1438 In some cases it is useful to look at this to decide what needs to be done.
1440 MODE and WIN are passed so that this macro can use
1441 GO_IF_LEGITIMATE_ADDRESS.
1443 It is always safe for this macro to do nothing. It exists to recognize
1444 opportunities to optimize the output.
1446 For the Alpha, there are three cases we handle:
1448 (1) If the address is (plus reg const_int) and the CONST_INT is not a
1449 valid offset, compute the high part of the constant and add it to the
1450 register. Then our address is (plus temp low-part-const).
1451 (2) If the address is (const (plus FOO const_int)), find the low-order
1452 part of the CONST_INT. Then load FOO plus any high-order part of the
1453 CONST_INT into a register. Our address is (plus reg low-part-const).
1454 This is done to reduce the number of GOT entries.
1455 (3) If we have a (plus reg const), emit the load as in (2), then add
1456 the two registers, and finally generate (plus reg low-part-const) as
1459 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1460 { if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG \
1461 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1462 && ! CONSTANT_ADDRESS_P (XEXP (X, 1))) \
1464 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1465 HOST_WIDE_INT lowpart = (val & 0xffff) - 2 * (val & 0x8000); \
1466 HOST_WIDE_INT highpart = val - lowpart; \
1467 rtx high = GEN_INT (highpart); \
1468 rtx temp = expand_binop (Pmode, add_optab, XEXP (x, 0), \
1469 high, NULL_RTX, 1, OPTAB_LIB_WIDEN); \
1471 (X) = plus_constant (temp, lowpart); \
1474 else if (GET_CODE (X) == CONST \
1475 && GET_CODE (XEXP (X, 0)) == PLUS \
1476 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT) \
1478 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (X, 0), 1)); \
1479 HOST_WIDE_INT lowpart = (val & 0xffff) - 2 * (val & 0x8000); \
1480 HOST_WIDE_INT highpart = val - lowpart; \
1481 rtx high = XEXP (XEXP (X, 0), 0); \
1484 high = plus_constant (high, highpart); \
1486 (X) = plus_constant (force_reg (Pmode, high), lowpart); \
1489 else if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG \
1490 && GET_CODE (XEXP (X, 1)) == CONST \
1491 && GET_CODE (XEXP (XEXP (X, 1), 0)) == PLUS \
1492 && GET_CODE (XEXP (XEXP (XEXP (X, 1), 0), 1)) == CONST_INT) \
1494 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (X, 1), 0), 1)); \
1495 HOST_WIDE_INT lowpart = (val & 0xffff) - 2 * (val & 0x8000); \
1496 HOST_WIDE_INT highpart = val - lowpart; \
1497 rtx high = XEXP (XEXP (XEXP (X, 1), 0), 0); \
1500 high = plus_constant (high, highpart); \
1502 high = expand_binop (Pmode, add_optab, XEXP (X, 0), \
1503 force_reg (Pmode, high), \
1504 high, 1, OPTAB_LIB_WIDEN); \
1505 (X) = plus_constant (high, lowpart); \
1510 /* Try a machine-dependent way of reloading an illegitimate address
1511 operand. If we find one, push the reload and jump to WIN. This
1512 macro is used in only one place: `find_reloads_address' in reload.c.
1514 For the Alpha, we wish to handle large displacements off a base
1515 register by splitting the addend across an ldah and the mem insn.
1516 This cuts number of extra insns needed from 3 to 1. */
1518 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1520 /* We must recognize output that we have already generated ourselves. */ \
1521 if (GET_CODE (X) == PLUS \
1522 && GET_CODE (XEXP (X, 0)) == PLUS \
1523 && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \
1524 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
1525 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1527 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL_PTR, \
1528 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
1532 if (GET_CODE (X) == PLUS \
1533 && GET_CODE (XEXP (X, 0)) == REG \
1534 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1535 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1536 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1538 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1539 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; \
1540 HOST_WIDE_INT high \
1541 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000; \
1543 /* Check for 32-bit overflow. */ \
1544 if (high + low != val) \
1547 /* Reload the high part into a base reg; leave the low part \
1548 in the mem directly. */ \
1550 X = gen_rtx_PLUS (GET_MODE (X), \
1551 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1555 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL_PTR, \
1556 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
1562 /* Go to LABEL if ADDR (a legitimate address expression)
1563 has an effect that depends on the machine mode it is used for.
1564 On the Alpha this is true only for the unaligned modes. We can
1565 simplify this test since we know that the address must be valid. */
1567 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1568 { if (GET_CODE (ADDR) == AND) goto LABEL; }
1570 /* Compute the cost of an address. For the Alpha, all valid addresses are
1573 #define ADDRESS_COST(X) 0
1575 /* Machine-dependent reorg pass. */
1576 #define MACHINE_DEPENDENT_REORG(X) alpha_reorg(X)
1578 /* Specify the machine mode that this machine uses
1579 for the index in the tablejump instruction. */
1580 #define CASE_VECTOR_MODE SImode
1582 /* Define as C expression which evaluates to nonzero if the tablejump
1583 instruction expects the table to contain offsets from the address of the
1586 Do not define this if the table should contain absolute addresses.
1587 On the Alpha, the table is really GP-relative, not relative to the PC
1588 of the table, but we pretend that it is PC-relative; this should be OK,
1589 but we should try to find some better way sometime. */
1590 #define CASE_VECTOR_PC_RELATIVE 1
1592 /* Specify the tree operation to be used to convert reals to integers. */
1593 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1595 /* This is the kind of divide that is easiest to do in the general case. */
1596 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1598 /* Define this as 1 if `char' should by default be signed; else as 0. */
1599 #define DEFAULT_SIGNED_CHAR 1
1601 /* This flag, if defined, says the same insns that convert to a signed fixnum
1602 also convert validly to an unsigned one.
1604 We actually lie a bit here as overflow conditions are different. But
1605 they aren't being checked anyway. */
1607 #define FIXUNS_TRUNC_LIKE_FIX_TRUNC
1609 /* Max number of bytes we can move to or from memory
1610 in one reasonably fast instruction. */
1614 /* If a memory-to-memory move would take MOVE_RATIO or more simple
1615 move-instruction pairs, we will do a movstr or libcall instead.
1617 Without byte/word accesses, we want no more than four instructions;
1618 with, several single byte accesses are better. */
1620 #define MOVE_RATIO (TARGET_BWX ? 7 : 2)
1622 /* Largest number of bytes of an object that can be placed in a register.
1623 On the Alpha we have plenty of registers, so use TImode. */
1624 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode)
1626 /* Nonzero if access to memory by bytes is no faster than for words.
1627 Also non-zero if doing byte operations (specifically shifts) in registers
1630 On the Alpha, we want to not use the byte operation and instead use
1631 masking operations to access fields; these will save instructions. */
1633 #define SLOW_BYTE_ACCESS 1
1635 /* Define if operations between registers always perform the operation
1636 on the full register even if a narrower mode is specified. */
1637 #define WORD_REGISTER_OPERATIONS
1639 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1640 will either zero-extend or sign-extend. The value of this macro should
1641 be the code that says which one of the two operations is implicitly
1642 done, NIL if none. */
1643 #define LOAD_EXTEND_OP(MODE) ((MODE) == SImode ? SIGN_EXTEND : ZERO_EXTEND)
1645 /* Define if loading short immediate values into registers sign extends. */
1646 #define SHORT_IMMEDIATES_SIGN_EXTEND
1648 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1649 is done just by pretending it is already truncated. */
1650 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1652 /* We assume that the store-condition-codes instructions store 0 for false
1653 and some other value for true. This is the value stored for true. */
1655 #define STORE_FLAG_VALUE 1
1657 /* Define the value returned by a floating-point comparison instruction. */
1659 #define FLOAT_STORE_FLAG_VALUE (TARGET_FLOAT_VAX ? 0.5 : 2.0)
1661 /* Canonicalize a comparison from one we don't have to one we do have. */
1663 #define CANONICALIZE_COMPARISON(CODE,OP0,OP1) \
1665 if (((CODE) == GE || (CODE) == GT || (CODE) == GEU || (CODE) == GTU) \
1666 && (GET_CODE (OP1) == REG || (OP1) == const0_rtx)) \
1671 (CODE) = swap_condition (CODE); \
1673 if (((CODE) == LT || (CODE) == LTU) \
1674 && GET_CODE (OP1) == CONST_INT && INTVAL (OP1) == 256) \
1676 (CODE) = (CODE) == LT ? LE : LEU; \
1677 (OP1) = GEN_INT (255); \
1681 /* Specify the machine mode that pointers have.
1682 After generation of rtl, the compiler makes no further distinction
1683 between pointers and any other objects of this machine mode. */
1684 #define Pmode DImode
1686 /* Mode of a function address in a call instruction (for indexing purposes). */
1688 #define FUNCTION_MODE Pmode
1690 /* Define this if addresses of constant functions
1691 shouldn't be put through pseudo regs where they can be cse'd.
1692 Desirable on machines where ordinary constants are expensive
1693 but a CALL with constant address is cheap.
1695 We define this on the Alpha so that gen_call and gen_call_value
1696 get to see the SYMBOL_REF (for the hint field of the jsr). It will
1697 then copy it into a register, thus actually letting the address be
1700 #define NO_FUNCTION_CSE
1702 /* Define this to be nonzero if shift instructions ignore all but the low-order
1704 #define SHIFT_COUNT_TRUNCATED 1
1706 /* Use atexit for static constructors/destructors, instead of defining
1707 our own exit function. */
1710 /* The EV4 is dual issue; EV5/EV6 are quad issue. */
1711 #define ISSUE_RATE (alpha_cpu == PROCESSOR_EV4 ? 2 : 4)
1713 /* Describe the fact that MULTI instructions are multiple instructions
1714 and so to assume they don't pair with anything. */
1715 #define MD_SCHED_VARIABLE_ISSUE(DUMP, SCHED_VERBOSE, INSN, CAN_ISSUE_MORE) \
1716 if (recog_memoized (INSN) < 0 || get_attr_type (INSN) == TYPE_MULTI) \
1717 (CAN_ISSUE_MORE) = 0
1719 /* Compute the cost of computing a constant rtl expression RTX
1720 whose rtx-code is CODE. The body of this macro is a portion
1721 of a switch statement. If the code is computed here,
1722 return it with a return statement. Otherwise, break from the switch.
1724 If this is an 8-bit constant, return zero since it can be used
1725 nearly anywhere with no cost. If it is a valid operand for an
1726 ADD or AND, likewise return 0 if we know it will be used in that
1727 context. Otherwise, return 2 since it might be used there later.
1728 All other constants take at least two insns. */
1730 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
1732 if (INTVAL (RTX) >= 0 && INTVAL (RTX) < 256) \
1734 case CONST_DOUBLE: \
1735 if ((RTX) == CONST0_RTX (GET_MODE (RTX))) \
1737 else if (((OUTER_CODE) == PLUS && add_operand (RTX, VOIDmode)) \
1738 || ((OUTER_CODE) == AND && and_operand (RTX, VOIDmode))) \
1740 else if (add_operand (RTX, VOIDmode) || and_operand (RTX, VOIDmode)) \
1743 return COSTS_N_INSNS (2); \
1747 switch (alpha_cpu) \
1749 case PROCESSOR_EV4: \
1750 return COSTS_N_INSNS (3); \
1751 case PROCESSOR_EV5: \
1752 case PROCESSOR_EV6: \
1753 return COSTS_N_INSNS (2); \
1757 /* Provide the costs of a rtl expression. This is in the body of a
1760 #define RTX_COSTS(X,CODE,OUTER_CODE) \
1761 case PLUS: case MINUS: \
1762 if (FLOAT_MODE_P (GET_MODE (X))) \
1763 switch (alpha_cpu) \
1765 case PROCESSOR_EV4: \
1766 return COSTS_N_INSNS (6); \
1767 case PROCESSOR_EV5: \
1768 case PROCESSOR_EV6: \
1769 return COSTS_N_INSNS (4); \
1772 else if (GET_CODE (XEXP (X, 0)) == MULT \
1773 && const48_operand (XEXP (XEXP (X, 0), 1), VOIDmode)) \
1774 return (2 + rtx_cost (XEXP (XEXP (X, 0), 0), OUTER_CODE) \
1775 + rtx_cost (XEXP (X, 1), OUTER_CODE)); \
1778 switch (alpha_cpu) \
1780 case PROCESSOR_EV4: \
1781 if (FLOAT_MODE_P (GET_MODE (X))) \
1782 return COSTS_N_INSNS (6); \
1783 return COSTS_N_INSNS (23); \
1784 case PROCESSOR_EV5: \
1785 if (FLOAT_MODE_P (GET_MODE (X))) \
1786 return COSTS_N_INSNS (4); \
1787 else if (GET_MODE (X) == DImode) \
1788 return COSTS_N_INSNS (12); \
1790 return COSTS_N_INSNS (8); \
1791 case PROCESSOR_EV6: \
1792 if (FLOAT_MODE_P (GET_MODE (X))) \
1793 return COSTS_N_INSNS (4); \
1795 return COSTS_N_INSNS (7); \
1799 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
1800 && INTVAL (XEXP (X, 1)) <= 3) \
1802 /* ... fall through ... */ \
1803 case ASHIFTRT: case LSHIFTRT: \
1804 switch (alpha_cpu) \
1806 case PROCESSOR_EV4: \
1807 return COSTS_N_INSNS (2); \
1808 case PROCESSOR_EV5: \
1809 case PROCESSOR_EV6: \
1810 return COSTS_N_INSNS (1); \
1813 case IF_THEN_ELSE: \
1814 switch (alpha_cpu) \
1816 case PROCESSOR_EV4: \
1817 case PROCESSOR_EV6: \
1818 return COSTS_N_INSNS (2); \
1819 case PROCESSOR_EV5: \
1820 return COSTS_N_INSNS (1); \
1823 case DIV: case UDIV: case MOD: case UMOD: \
1824 switch (alpha_cpu) \
1826 case PROCESSOR_EV4: \
1827 if (GET_MODE (X) == SFmode) \
1828 return COSTS_N_INSNS (34); \
1829 else if (GET_MODE (X) == DFmode) \
1830 return COSTS_N_INSNS (63); \
1832 return COSTS_N_INSNS (70); \
1833 case PROCESSOR_EV5: \
1834 if (GET_MODE (X) == SFmode) \
1835 return COSTS_N_INSNS (15); \
1836 else if (GET_MODE (X) == DFmode) \
1837 return COSTS_N_INSNS (22); \
1839 return COSTS_N_INSNS (70); /* ??? */ \
1840 case PROCESSOR_EV6: \
1841 if (GET_MODE (X) == SFmode) \
1842 return COSTS_N_INSNS (12); \
1843 else if (GET_MODE (X) == DFmode) \
1844 return COSTS_N_INSNS (15); \
1846 return COSTS_N_INSNS (70); /* ??? */ \
1850 switch (alpha_cpu) \
1852 case PROCESSOR_EV4: \
1853 case PROCESSOR_EV6: \
1854 return COSTS_N_INSNS (3); \
1855 case PROCESSOR_EV5: \
1856 return COSTS_N_INSNS (2); \
1859 case NEG: case ABS: \
1860 if (! FLOAT_MODE_P (GET_MODE (X))) \
1862 /* ... fall through ... */ \
1863 case FLOAT: case UNSIGNED_FLOAT: case FIX: case UNSIGNED_FIX: \
1864 case FLOAT_EXTEND: case FLOAT_TRUNCATE: \
1865 switch (alpha_cpu) \
1867 case PROCESSOR_EV4: \
1868 return COSTS_N_INSNS (6); \
1869 case PROCESSOR_EV5: \
1870 case PROCESSOR_EV6: \
1871 return COSTS_N_INSNS (4); \
1875 /* Control the assembler format that we output. */
1877 /* We don't emit these labels, so as to avoid getting linker errors about
1878 missing exception handling info. If we emit a gcc_compiled. label into
1879 text, and the file has no code, then the DEC assembler gives us a zero
1880 sized text section with no associated exception handling info. The
1881 DEC linker sees this text section, and gives a warning saying that
1882 the exception handling info is missing. */
1883 #define ASM_IDENTIFY_GCC(x)
1884 #define ASM_IDENTIFY_LANGUAGE(x)
1886 /* Output to assembler file text saying following lines
1887 may contain character constants, extra white space, comments, etc. */
1889 #define ASM_APP_ON ""
1891 /* Output to assembler file text saying following lines
1892 no longer contain unusual constructs. */
1894 #define ASM_APP_OFF ""
1896 #define TEXT_SECTION_ASM_OP ".text"
1898 /* Output before read-only data. */
1900 #define READONLY_DATA_SECTION_ASM_OP ".rdata"
1902 /* Output before writable data. */
1904 #define DATA_SECTION_ASM_OP ".data"
1906 /* Define an extra section for read-only data, a routine to enter it, and
1907 indicate that it is for read-only data.
1909 The first time we enter the readonly data section for a file, we write
1910 eight bytes of zero. This works around a bug in DEC's assembler in
1911 some versions of OSF/1 V3.x. */
1913 #define EXTRA_SECTIONS readonly_data
1915 #define EXTRA_SECTION_FUNCTIONS \
1917 literal_section () \
1919 if (in_section != readonly_data) \
1921 static int firsttime = 1; \
1923 fprintf (asm_out_file, "%s\n", READONLY_DATA_SECTION_ASM_OP); \
1927 ASM_OUTPUT_DOUBLE_INT (asm_out_file, const0_rtx); \
1930 in_section = readonly_data; \
1934 #define READONLY_DATA_SECTION literal_section
1936 /* If we are referencing a function that is static, make the SYMBOL_REF
1937 special. We use this to see indicate we can branch to this function
1938 without setting PV or restoring GP. */
1940 #define ENCODE_SECTION_INFO(DECL) \
1941 if (TREE_CODE (DECL) == FUNCTION_DECL && ! TREE_PUBLIC (DECL)) \
1942 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1;
1944 /* How to refer to registers in assembler output.
1945 This sequence is indexed by compiler's hard-register-number (see above). */
1947 #define REGISTER_NAMES \
1948 {"$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8", \
1949 "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
1950 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
1951 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "AP", \
1952 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", "$f8", \
1953 "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
1954 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",\
1955 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "FP"}
1957 /* How to renumber registers for dbx and gdb. */
1959 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
1961 /* This is how to output the definition of a user-level label named NAME,
1962 such as the label on a static function or variable NAME. */
1964 #define ASM_OUTPUT_LABEL(FILE,NAME) \
1965 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
1967 /* This is how to output a command to make the user-level label named NAME
1968 defined for reference from other files. */
1970 #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
1971 do { fputs ("\t.globl ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
1973 /* The prefix to add to user-visible assembler symbols. */
1975 #define USER_LABEL_PREFIX ""
1977 /* This is how to output an internal numbered label where
1978 PREFIX is the class of label and NUM is the number within the class. */
1980 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1981 fprintf (FILE, "$%s%d:\n", PREFIX, NUM)
1983 /* This is how to output a label for a jump table. Arguments are the same as
1984 for ASM_OUTPUT_INTERNAL_LABEL, except the insn for the jump table is
1987 #define ASM_OUTPUT_CASE_LABEL(FILE,PREFIX,NUM,TABLEINSN) \
1988 { ASM_OUTPUT_ALIGN (FILE, 2); ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); }
1990 /* This is how to store into the string LABEL
1991 the symbol_ref name of an internal numbered label where
1992 PREFIX is the class of label and NUM is the number within the class.
1993 This is suitable for output with `assemble_name'. */
1995 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1996 sprintf ((LABEL), "*$%s%ld", (PREFIX), (long)(NUM))
1998 /* Check a floating-point value for validity for a particular machine mode. */
2000 #define CHECK_FLOAT_VALUE(MODE, D, OVERFLOW) \
2001 ((OVERFLOW) = check_float_value (MODE, &D, OVERFLOW))
2003 /* This is how to output an assembler line defining a `double' constant. */
2005 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
2007 if (REAL_VALUE_ISINF (VALUE) \
2008 || REAL_VALUE_ISNAN (VALUE) \
2009 || REAL_VALUE_MINUS_ZERO (VALUE)) \
2012 REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t); \
2013 fprintf (FILE, "\t.quad 0x%lx%08lx\n", \
2014 t[1] & 0xffffffff, t[0] & 0xffffffff); \
2019 REAL_VALUE_TO_DECIMAL (VALUE, "%.20e", str); \
2020 fprintf (FILE, "\t.%c_floating %s\n", (TARGET_FLOAT_VAX)?'g':'t', str); \
2024 /* This is how to output an assembler line defining a `float' constant. */
2026 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
2029 REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t); \
2030 fprintf (FILE, "\t.long 0x%lx\n", t & 0xffffffff); \
2033 /* This is how to output an assembler line defining an `int' constant. */
2035 #define ASM_OUTPUT_INT(FILE,VALUE) \
2036 ( fprintf (FILE, "\t.long "), \
2037 output_addr_const (FILE, (VALUE)), \
2038 fprintf (FILE, "\n"))
2040 /* This is how to output an assembler line defining a `long' constant. */
2042 #define ASM_OUTPUT_DOUBLE_INT(FILE,VALUE) \
2043 ( fprintf (FILE, "\t.quad "), \
2044 output_addr_const (FILE, (VALUE)), \
2045 fprintf (FILE, "\n"))
2047 /* Likewise for `char' and `short' constants. */
2049 #define ASM_OUTPUT_SHORT(FILE,VALUE) \
2050 fprintf (FILE, "\t.word %d\n", \
2051 (int)(GET_CODE (VALUE) == CONST_INT \
2052 ? INTVAL (VALUE) & 0xffff : (abort (), 0)))
2054 #define ASM_OUTPUT_CHAR(FILE,VALUE) \
2055 fprintf (FILE, "\t.byte %d\n", \
2056 (int)(GET_CODE (VALUE) == CONST_INT \
2057 ? INTVAL (VALUE) & 0xff : (abort (), 0)))
2059 /* We use the default ASCII-output routine, except that we don't write more
2060 than 50 characters since the assembler doesn't support very long lines. */
2062 #define ASM_OUTPUT_ASCII(MYFILE, MYSTRING, MYLENGTH) \
2064 FILE *_hide_asm_out_file = (MYFILE); \
2065 unsigned char *_hide_p = (unsigned char *) (MYSTRING); \
2066 int _hide_thissize = (MYLENGTH); \
2067 int _size_so_far = 0; \
2069 FILE *asm_out_file = _hide_asm_out_file; \
2070 unsigned char *p = _hide_p; \
2071 int thissize = _hide_thissize; \
2073 fprintf (asm_out_file, "\t.ascii \""); \
2075 for (i = 0; i < thissize; i++) \
2077 register int c = p[i]; \
2079 if (_size_so_far ++ > 50 && i < thissize - 4) \
2080 _size_so_far = 0, fprintf (asm_out_file, "\"\n\t.ascii \""); \
2082 if (c == '\"' || c == '\\') \
2083 putc ('\\', asm_out_file); \
2084 if (c >= ' ' && c < 0177) \
2085 putc (c, asm_out_file); \
2088 fprintf (asm_out_file, "\\%o", c); \
2089 /* After an octal-escape, if a digit follows, \
2090 terminate one string constant and start another. \
2091 The Vax assembler fails to stop reading the escape \
2092 after three digits, so this is the only way we \
2093 can get it to parse the data properly. */ \
2094 if (i < thissize - 1 \
2095 && p[i + 1] >= '0' && p[i + 1] <= '9') \
2096 _size_so_far = 0, fprintf (asm_out_file, "\"\n\t.ascii \""); \
2099 fprintf (asm_out_file, "\"\n"); \
2104 /* This is how to output an insn to push a register on the stack.
2105 It need not be very fast code. */
2107 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
2108 fprintf (FILE, "\tsubq $30,8,$30\n\tst%s $%s%d,0($30)\n", \
2109 (REGNO) > 32 ? "t" : "q", (REGNO) > 32 ? "f" : "", \
2112 /* This is how to output an insn to pop a register from the stack.
2113 It need not be very fast code. */
2115 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
2116 fprintf (FILE, "\tld%s $%s%d,0($30)\n\taddq $30,8,$30\n", \
2117 (REGNO) > 32 ? "t" : "q", (REGNO) > 32 ? "f" : "", \
2120 /* This is how to output an assembler line for a numeric constant byte. */
2122 #define ASM_OUTPUT_BYTE(FILE,VALUE) \
2123 fprintf (FILE, "\t.byte 0x%x\n", (int) ((VALUE) & 0xff))
2125 /* This is how to output an element of a case-vector that is absolute.
2126 (Alpha does not use such vectors, but we must define this macro anyway.) */
2128 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) abort ()
2130 /* This is how to output an element of a case-vector that is relative. */
2132 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2133 fprintf (FILE, "\t.%s $L%d\n", TARGET_WINDOWS_NT ? "long" : "gprel32", \
2136 /* This is how to output an assembler line
2137 that says to advance the location counter
2138 to a multiple of 2**LOG bytes. */
2140 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2142 fprintf (FILE, "\t.align %d\n", LOG);
2144 /* This is how to advance the location counter by SIZE bytes. */
2146 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
2147 fprintf (FILE, "\t.space %d\n", (SIZE))
2149 /* This says how to output an assembler line
2150 to define a global common symbol. */
2152 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
2153 ( fputs ("\t.comm ", (FILE)), \
2154 assemble_name ((FILE), (NAME)), \
2155 fprintf ((FILE), ",%d\n", (SIZE)))
2157 /* This says how to output an assembler line
2158 to define a local common symbol. */
2160 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE,ROUNDED) \
2161 ( fputs ("\t.lcomm ", (FILE)), \
2162 assemble_name ((FILE), (NAME)), \
2163 fprintf ((FILE), ",%d\n", (SIZE)))
2165 /* Store in OUTPUT a string (made with alloca) containing
2166 an assembler-name for a local static variable named NAME.
2167 LABELNO is an integer which is different for each call. */
2169 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
2170 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
2171 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
2173 /* Define the parentheses used to group arithmetic operations
2174 in assembler code. */
2176 #define ASM_OPEN_PAREN "("
2177 #define ASM_CLOSE_PAREN ")"
2179 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
2180 Used for C++ multiple inheritance. */
2182 #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \
2184 char *fn_name = XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0); \
2187 /* Mark end of prologue. */ \
2188 output_end_prologue (FILE); \
2190 /* Rely on the assembler to macro expand a large delta. */ \
2191 reg = aggregate_value_p (TREE_TYPE (TREE_TYPE (FUNCTION))) ? 17 : 16; \
2192 fprintf (FILE, "\tlda $%d,%ld($%d)\n", reg, (long)(DELTA), reg); \
2194 if (current_file_function_operand (XEXP (DECL_RTL (FUNCTION), 0))) \
2196 fprintf (FILE, "\tbr $31,$"); \
2197 assemble_name (FILE, fn_name); \
2198 fprintf (FILE, "..ng\n"); \
2202 fprintf (FILE, "\tjmp $31,"); \
2203 assemble_name (FILE, fn_name); \
2204 fputc ('\n', FILE); \
2209 /* Define results of standard character escape sequences. */
2210 #define TARGET_BELL 007
2211 #define TARGET_BS 010
2212 #define TARGET_TAB 011
2213 #define TARGET_NEWLINE 012
2214 #define TARGET_VT 013
2215 #define TARGET_FF 014
2216 #define TARGET_CR 015
2218 /* Print operand X (an rtx) in assembler syntax to file FILE.
2219 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2220 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2222 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2224 /* Determine which codes are valid without a following integer. These must
2225 not be alphabetic (the characters are chosen so that
2226 PRINT_OPERAND_PUNCT_VALID_P translates into a simple range change when
2229 & Generates fp-rounding mode suffix: nothing for normal, 'c' for
2230 chopped, 'm' for minus-infinity, and 'd' for dynamic rounding
2231 mode. alpha_fprm controls which suffix is generated.
2233 ' Generates trap-mode suffix for instructions that accept the
2234 su suffix only (cmpt et al).
2236 ` Generates trap-mode suffix for instructions that accept the
2237 v and sv suffix. The only instruction that needs this is cvtql.
2239 ( Generates trap-mode suffix for instructions that accept the
2240 v, sv, and svi suffix. The only instruction that needs this
2243 ) Generates trap-mode suffix for instructions that accept the
2244 u, su, and sui suffix. This is the bulk of the IEEE floating
2245 point instructions (addt et al).
2247 + Generates trap-mode suffix for instructions that accept the
2248 sui suffix (cvtqt and cvtqs).
2250 , Generates single precision suffix for floating point
2251 instructions (s for IEEE, f for VAX)
2253 - Generates double precision suffix for floating point
2254 instructions (t for IEEE, g for VAX)
2257 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2258 ((CODE) == '&' || (CODE) == '`' || (CODE) == '\'' || (CODE) == '(' \
2259 || (CODE) == ')' || (CODE) == '+' || (CODE) == ',' || (CODE) == '-')
2261 /* Print a memory address as an operand to reference that memory location. */
2263 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2264 { rtx addr = (ADDR); \
2266 HOST_WIDE_INT offset = 0; \
2268 if (GET_CODE (addr) == AND) \
2269 addr = XEXP (addr, 0); \
2271 if (GET_CODE (addr) == REG) \
2272 basereg = REGNO (addr); \
2273 else if (GET_CODE (addr) == CONST_INT) \
2274 offset = INTVAL (addr); \
2275 else if (GET_CODE (addr) == PLUS \
2276 && GET_CODE (XEXP (addr, 0)) == REG \
2277 && GET_CODE (XEXP (addr, 1)) == CONST_INT) \
2278 basereg = REGNO (XEXP (addr, 0)), offset = INTVAL (XEXP (addr, 1)); \
2282 fprintf (FILE, HOST_WIDE_INT_PRINT_DEC, offset); \
2283 fprintf (FILE, "($%d)", basereg); \
2285 /* Define the codes that are matched by predicates in alpha.c. */
2287 #define PREDICATE_CODES \
2288 {"reg_or_0_operand", {SUBREG, REG, CONST_INT}}, \
2289 {"reg_or_6bit_operand", {SUBREG, REG, CONST_INT}}, \
2290 {"reg_or_8bit_operand", {SUBREG, REG, CONST_INT}}, \
2291 {"cint8_operand", {CONST_INT}}, \
2292 {"reg_or_cint_operand", {SUBREG, REG, CONST_INT}}, \
2293 {"add_operand", {SUBREG, REG, CONST_INT}}, \
2294 {"sext_add_operand", {SUBREG, REG, CONST_INT}}, \
2295 {"const48_operand", {CONST_INT}}, \
2296 {"and_operand", {SUBREG, REG, CONST_INT}}, \
2297 {"or_operand", {SUBREG, REG, CONST_INT}}, \
2298 {"mode_mask_operand", {CONST_INT}}, \
2299 {"mul8_operand", {CONST_INT}}, \
2300 {"mode_width_operand", {CONST_INT}}, \
2301 {"reg_or_fp0_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2302 {"alpha_comparison_operator", {EQ, LE, LT, LEU, LTU}}, \
2303 {"alpha_swapped_comparison_operator", {EQ, GE, GT, GEU, GTU}}, \
2304 {"signed_comparison_operator", {EQ, NE, LE, LT, GE, GT}}, \
2305 {"divmod_operator", {DIV, MOD, UDIV, UMOD}}, \
2306 {"fp0_operand", {CONST_DOUBLE}}, \
2307 {"current_file_function_operand", {SYMBOL_REF}}, \
2308 {"call_operand", {REG, SYMBOL_REF}}, \
2309 {"input_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE, \
2310 SYMBOL_REF, CONST, LABEL_REF}}, \
2311 {"some_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE, \
2312 SYMBOL_REF, CONST, LABEL_REF}}, \
2313 {"aligned_memory_operand", {MEM}}, \
2314 {"unaligned_memory_operand", {MEM}}, \
2315 {"reg_or_unaligned_mem_operand", {SUBREG, REG, MEM}}, \
2316 {"any_memory_operand", {MEM}}, \
2317 {"hard_fp_register_operand", {SUBREG, REG}}, \
2318 {"reg_not_elim_operand", {SUBREG, REG}},
2320 /* Tell collect that the object format is ECOFF. */
2321 #define OBJECT_FORMAT_COFF
2322 #define EXTENDED_COFF
2324 /* If we use NM, pass -g to it so it only lists globals. */
2325 #define NM_FLAGS "-pg"
2327 /* Definitions for debugging. */
2329 #define SDB_DEBUGGING_INFO /* generate info for mips-tfile */
2330 #define DBX_DEBUGGING_INFO /* generate embedded stabs */
2331 #define MIPS_DEBUGGING_INFO /* MIPS specific debugging info */
2333 #ifndef PREFERRED_DEBUGGING_TYPE /* assume SDB_DEBUGGING_INFO */
2334 #define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
2338 /* Correct the offset of automatic variables and arguments. Note that
2339 the Alpha debug format wants all automatic variables and arguments
2340 to be in terms of two different offsets from the virtual frame pointer,
2341 which is the stack pointer before any adjustment in the function.
2342 The offset for the argument pointer is fixed for the native compiler,
2343 it is either zero (for the no arguments case) or large enough to hold
2344 all argument registers.
2345 The offset for the auto pointer is the fourth argument to the .frame
2346 directive (local_offset).
2347 To stay compatible with the native tools we use the same offsets
2348 from the virtual frame pointer and adjust the debugger arg/auto offsets
2349 accordingly. These debugger offsets are set up in output_prolog. */
2351 extern long alpha_arg_offset;
2352 extern long alpha_auto_offset;
2353 #define DEBUGGER_AUTO_OFFSET(X) \
2354 ((GET_CODE (X) == PLUS ? INTVAL (XEXP (X, 1)) : 0) + alpha_auto_offset)
2355 #define DEBUGGER_ARG_OFFSET(OFFSET, X) (OFFSET + alpha_arg_offset)
2358 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE) \
2359 alpha_output_lineno (STREAM, LINE)
2360 extern void alpha_output_lineno ();
2362 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
2363 alpha_output_filename (STREAM, NAME)
2364 extern void alpha_output_filename ();
2366 /* mips-tfile.c limits us to strings of one page. We must underestimate this
2367 number, because the real length runs past this up to the next
2368 continuation point. This is really a dbxout.c bug. */
2369 #define DBX_CONTIN_LENGTH 3000
2371 /* By default, turn on GDB extensions. */
2372 #define DEFAULT_GDB_EXTENSIONS 1
2374 /* Stabs-in-ECOFF can't handle dbxout_function_end(). */
2375 #define NO_DBX_FUNCTION_END 1
2377 /* If we are smuggling stabs through the ALPHA ECOFF object
2378 format, put a comment in front of the .stab<x> operation so
2379 that the ALPHA assembler does not choke. The mips-tfile program
2380 will correctly put the stab into the object file. */
2382 #define ASM_STABS_OP ((TARGET_GAS) ? ".stabs" : " #.stabs")
2383 #define ASM_STABN_OP ((TARGET_GAS) ? ".stabn" : " #.stabn")
2384 #define ASM_STABD_OP ((TARGET_GAS) ? ".stabd" : " #.stabd")
2386 /* Forward references to tags are allowed. */
2387 #define SDB_ALLOW_FORWARD_REFERENCES
2389 /* Unknown tags are also allowed. */
2390 #define SDB_ALLOW_UNKNOWN_REFERENCES
2392 #define PUT_SDB_DEF(a) \
2394 fprintf (asm_out_file, "\t%s.def\t", \
2395 (TARGET_GAS) ? "" : "#"); \
2396 ASM_OUTPUT_LABELREF (asm_out_file, a); \
2397 fputc (';', asm_out_file); \
2400 #define PUT_SDB_PLAIN_DEF(a) \
2402 fprintf (asm_out_file, "\t%s.def\t.%s;", \
2403 (TARGET_GAS) ? "" : "#", (a)); \
2406 #define PUT_SDB_TYPE(a) \
2408 fprintf (asm_out_file, "\t.type\t0x%x;", (a)); \
2411 /* For block start and end, we create labels, so that
2412 later we can figure out where the correct offset is.
2413 The normal .ent/.end serve well enough for functions,
2414 so those are just commented out. */
2416 extern int sdb_label_count; /* block start/end next label # */
2418 #define PUT_SDB_BLOCK_START(LINE) \
2420 fprintf (asm_out_file, \
2421 "$Lb%d:\n\t%s.begin\t$Lb%d\t%d\n", \
2423 (TARGET_GAS) ? "" : "#", \
2426 sdb_label_count++; \
2429 #define PUT_SDB_BLOCK_END(LINE) \
2431 fprintf (asm_out_file, \
2432 "$Le%d:\n\t%s.bend\t$Le%d\t%d\n", \
2434 (TARGET_GAS) ? "" : "#", \
2437 sdb_label_count++; \
2440 #define PUT_SDB_FUNCTION_START(LINE)
2442 #define PUT_SDB_FUNCTION_END(LINE)
2444 #define PUT_SDB_EPILOGUE_END(NAME) ((void)(NAME))
2446 /* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for
2447 mips-tdump.c to print them out.
2449 These must match the corresponding definitions in gdb/mipsread.c.
2450 Unfortunately, gcc and gdb do not currently share any directories. */
2452 #define CODE_MASK 0x8F300
2453 #define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
2454 #define MIPS_MARK_STAB(code) ((code)+CODE_MASK)
2455 #define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK)
2457 /* Override some mips-tfile definitions. */
2459 #define SHASH_SIZE 511
2460 #define THASH_SIZE 55
2462 /* Align ecoff symbol tables to avoid OSF1/1.3 nm complaints. */
2464 #define ALIGN_SYMTABLE_OFFSET(OFFSET) (((OFFSET) + 7) & ~7)
2466 /* The linker will stick __main into the .init section. */
2467 #define HAS_INIT_SECTION
2468 #define LD_INIT_SWITCH "-init"
2469 #define LD_FINI_SWITCH "-fini"
2471 /* The system headers under Alpha systems are generally C++-aware. */
2472 #define NO_IMPLICIT_EXTERN_C
2474 /* Prototypes for alpha.c functions used in the md file & elsewhere. */
2475 extern struct rtx_def *get_unaligned_address ();
2476 extern void alpha_write_verstamp ();
2477 extern void alpha_reorg ();
2478 extern int check_float_value ();
2479 extern int direct_return ();
2480 extern int const48_operand ();
2481 extern int add_operand ();
2482 extern int and_operand ();
2483 extern int unaligned_memory_operand ();
2484 extern int zap_mask ();
2485 extern int current_file_function_operand ();
2486 extern int alpha_sa_size ();
2487 extern int alpha_adjust_cost ();
2488 extern void print_operand ();
2489 extern int reg_or_0_operand ();
2490 extern int reg_or_8bit_operand ();
2491 extern int mul8_operand ();
2492 extern int reg_or_6bit_operand ();
2493 extern int alpha_comparison_operator ();
2494 extern int alpha_swapped_comparison_operator ();
2495 extern int sext_add_operand ();
2496 extern int cint8_operand ();
2497 extern int mode_mask_operand ();
2498 extern int or_operand ();
2499 extern int mode_width_operand ();
2500 extern int reg_or_fp0_operand ();
2501 extern int signed_comparison_operator ();
2502 extern int fp0_operand ();
2503 extern int some_operand ();
2504 extern int input_operand ();
2505 extern int divmod_operator ();
2506 extern int call_operand ();
2507 extern int reg_or_cint_operand ();
2508 extern int hard_fp_register_operand ();
2509 extern int reg_not_elim_operand ();
2510 extern void alpha_set_memflags ();
2511 extern int aligned_memory_operand ();
2512 extern void get_aligned_mem ();
2513 extern void alpha_expand_unaligned_load ();
2514 extern void alpha_expand_unaligned_store ();
2515 extern int alpha_expand_block_move ();
2516 extern int alpha_expand_block_clear ();
2517 extern void alpha_expand_prologue ();
2518 extern void alpha_expand_epilogue ();
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