1 /* Definitions of target machine for GNU compiler, for DEC Alpha.
2 Copyright (C) 1992, 93, 94, 95, 96, 97, 1998 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
23 /* Write out the correct language type definition for the header files.
24 Unless we have assembler language, write out the symbols for C. */
26 %{!.S: -D__LANGUAGE_C__ -D__LANGUAGE_C %{!ansi:-DLANGUAGE_C}} \
27 %{.S: -D__LANGUAGE_ASSEMBLY__ -D__LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \
28 %{.cc: -D__LANGUAGE_C_PLUS_PLUS__ -D__LANGUAGE_C_PLUS_PLUS -D__cplusplus} \
29 %{.cxx: -D__LANGUAGE_C_PLUS_PLUS__ -D__LANGUAGE_C_PLUS_PLUS -D__cplusplus} \
30 %{.C: -D__LANGUAGE_C_PLUS_PLUS__ -D__LANGUAGE_C_PLUS_PLUS -D__cplusplus} \
31 %{.m: -D__LANGUAGE_OBJECTIVE_C__ -D__LANGUAGE_OBJECTIVE_C} \
33 %{mieee-with-inexact:-D_IEEE_FP -D_IEEE_FP_INEXACT}"
35 /* Set the spec to use for signed char. The default tests the above macro
36 but DEC's compiler can't handle the conditional in a "constant"
39 #define SIGNED_CHAR_SPEC "%{funsigned-char:-D__CHAR_UNSIGNED__}"
41 #define WORD_SWITCH_TAKES_ARG(STR) \
42 (!strcmp (STR, "rpath") || !strcmp (STR, "include") \
43 || !strcmp (STR, "imacros") || !strcmp (STR, "aux-info") \
44 || !strcmp (STR, "idirafter") || !strcmp (STR, "iprefix") \
45 || !strcmp (STR, "iwithprefix") || !strcmp (STR, "iwithprefixbefore") \
46 || !strcmp (STR, "isystem"))
48 /* Print subsidiary information on the compiler version in use. */
49 #define TARGET_VERSION
51 /* Run-time compilation parameters selecting different hardware subsets. */
53 /* Which processor to schedule for. The cpu attribute defines a list that
54 mirrors this list, so changes to alpha.md must be made at the same time. */
57 {PROCESSOR_EV4, /* 2106[46]{a,} */
58 PROCESSOR_EV5, /* 21164{a,pc,} */
59 PROCESSOR_EV6}; /* 21264 */
61 extern enum processor_type alpha_cpu;
63 enum alpha_trap_precision
65 ALPHA_TP_PROG, /* No precision (default). */
66 ALPHA_TP_FUNC, /* Trap contained within originating function. */
67 ALPHA_TP_INSN /* Instruction accuracy and code is resumption safe. */
70 enum alpha_fp_rounding_mode
72 ALPHA_FPRM_NORM, /* Normal rounding mode. */
73 ALPHA_FPRM_MINF, /* Round towards minus-infinity. */
74 ALPHA_FPRM_CHOP, /* Chopped rounding mode (towards 0). */
75 ALPHA_FPRM_DYN /* Dynamic rounding mode. */
78 enum alpha_fp_trap_mode
80 ALPHA_FPTM_N, /* Normal trap mode. */
81 ALPHA_FPTM_U, /* Underflow traps enabled. */
82 ALPHA_FPTM_SU, /* Software completion, w/underflow traps */
83 ALPHA_FPTM_SUI /* Software completion, w/underflow & inexact traps */
86 extern int target_flags;
88 extern enum alpha_trap_precision alpha_tp;
89 extern enum alpha_fp_rounding_mode alpha_fprm;
90 extern enum alpha_fp_trap_mode alpha_fptm;
92 /* This means that floating-point support exists in the target implementation
93 of the Alpha architecture. This is usually the default. */
96 #define TARGET_FP (target_flags & MASK_FP)
98 /* This means that floating-point registers are allowed to be used. Note
99 that Alpha implementations without FP operations are required to
100 provide the FP registers. */
102 #define MASK_FPREGS 2
103 #define TARGET_FPREGS (target_flags & MASK_FPREGS)
105 /* This means that gas is used to process the assembler file. */
108 #define TARGET_GAS (target_flags & MASK_GAS)
110 /* This means that we should mark procedures as IEEE conformant. */
112 #define MASK_IEEE_CONFORMANT 8
113 #define TARGET_IEEE_CONFORMANT (target_flags & MASK_IEEE_CONFORMANT)
115 /* This means we should be IEEE-compliant except for inexact. */
118 #define TARGET_IEEE (target_flags & MASK_IEEE)
120 /* This means we should be fully IEEE-compliant. */
122 #define MASK_IEEE_WITH_INEXACT 32
123 #define TARGET_IEEE_WITH_INEXACT (target_flags & MASK_IEEE_WITH_INEXACT)
125 /* This means we must construct all constants rather than emitting
126 them as literal data. */
128 #define MASK_BUILD_CONSTANTS 128
129 #define TARGET_BUILD_CONSTANTS (target_flags & MASK_BUILD_CONSTANTS)
131 /* This means we handle floating points in VAX F- (float)
132 or G- (double) Format. */
134 #define MASK_FLOAT_VAX 512
135 #define TARGET_FLOAT_VAX (target_flags & MASK_FLOAT_VAX)
137 /* This means that the processor has byte and half word loads and stores
138 (the BWX extension). */
140 #define MASK_BWX 1024
141 #define TARGET_BWX (target_flags & MASK_BWX)
143 /* This means that the processor has the CIX extension. */
144 #define MASK_CIX 2048
145 #define TARGET_CIX (target_flags & MASK_CIX)
147 /* This means that the processor has the MAX extension. */
148 #define MASK_MAX 4096
149 #define TARGET_MAX (target_flags & MASK_MAX)
151 /* This means that the processor is an EV5, EV56, or PCA56. This is defined
152 only in TARGET_CPU_DEFAULT. */
153 #define MASK_CPU_EV5 8192
155 /* Likewise for EV6. */
156 #define MASK_CPU_EV6 16384
158 /* This means we support the .arch directive in the assembler. Only
159 defined in TARGET_CPU_DEFAULT. */
160 #define MASK_SUPPORT_ARCH 32768
161 #define TARGET_SUPPORT_ARCH (target_flags & MASK_SUPPORT_ARCH)
163 /* These are for target os support and cannot be changed at runtime. */
164 #ifndef TARGET_WINDOWS_NT
165 #define TARGET_WINDOWS_NT 0
167 #ifndef TARGET_OPEN_VMS
168 #define TARGET_OPEN_VMS 0
171 #ifndef TARGET_AS_CAN_SUBTRACT_LABELS
172 #define TARGET_AS_CAN_SUBTRACT_LABELS TARGET_GAS
176 /* Macro to define tables used to set the flags.
177 This is a list in braces of pairs in braces,
178 each pair being { "NAME", VALUE }
179 where VALUE is the bits to set or minus the bits to clear.
180 An empty string NAME is used to identify the default VALUE. */
182 #define TARGET_SWITCHES \
183 { {"no-soft-float", MASK_FP}, \
184 {"soft-float", - MASK_FP}, \
185 {"fp-regs", MASK_FPREGS}, \
186 {"no-fp-regs", - (MASK_FP|MASK_FPREGS)}, \
187 {"alpha-as", -MASK_GAS}, \
189 {"ieee-conformant", MASK_IEEE_CONFORMANT}, \
190 {"ieee", MASK_IEEE|MASK_IEEE_CONFORMANT}, \
191 {"ieee-with-inexact", MASK_IEEE_WITH_INEXACT|MASK_IEEE_CONFORMANT}, \
192 {"build-constants", MASK_BUILD_CONSTANTS}, \
193 {"float-vax", MASK_FLOAT_VAX}, \
194 {"float-ieee", -MASK_FLOAT_VAX}, \
196 {"no-bwx", -MASK_BWX}, \
198 {"no-cix", -MASK_CIX}, \
200 {"no-max", -MASK_MAX}, \
201 {"", TARGET_DEFAULT | TARGET_CPU_DEFAULT} }
203 #define TARGET_DEFAULT MASK_FP|MASK_FPREGS
205 #ifndef TARGET_CPU_DEFAULT
206 #define TARGET_CPU_DEFAULT 0
209 /* This macro is similar to `TARGET_SWITCHES' but defines names of
210 command options that have values. Its definition is an initializer
211 with a subgrouping for each command option.
213 Each subgrouping contains a string constant, that defines the fixed
214 part of the option name, and the address of a variable. The
215 variable, type `char *', is set to the variable part of the given
216 option if the fixed part matches. The actual option name is made
217 by appending `-m' to the specified name.
219 Here is an example which defines `-mshort-data-NUMBER'. If the
220 given option is `-mshort-data-512', the variable `m88k_short_data'
221 will be set to the string `"512"'.
223 extern char *m88k_short_data;
224 #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */
226 extern char *alpha_cpu_string; /* For -mcpu= */
227 extern char *alpha_fprm_string; /* For -mfp-rounding-mode=[n|m|c|d] */
228 extern char *alpha_fptm_string; /* For -mfp-trap-mode=[n|u|su|sui] */
229 extern char *alpha_tp_string; /* For -mtrap-precision=[p|f|i] */
230 extern char *alpha_mlat_string; /* For -mmemory-latency= */
232 #define TARGET_OPTIONS \
234 {"cpu=", &alpha_cpu_string}, \
235 {"fp-rounding-mode=", &alpha_fprm_string}, \
236 {"fp-trap-mode=", &alpha_fptm_string}, \
237 {"trap-precision=", &alpha_tp_string}, \
238 {"memory-latency=", &alpha_mlat_string}, \
241 /* Sometimes certain combinations of command options do not make sense
242 on a particular target machine. You can define a macro
243 `OVERRIDE_OPTIONS' to take account of this. This macro, if
244 defined, is executed once just after all the command options have
247 On the Alpha, it is used to translate target-option strings into
250 extern void override_options ();
251 #define OVERRIDE_OPTIONS override_options ()
254 /* Define this macro to change register usage conditional on target flags.
256 On the Alpha, we use this to disable the floating-point registers when
259 #define CONDITIONAL_REGISTER_USAGE \
260 if (! TARGET_FPREGS) \
261 for (i = 32; i < 63; i++) \
262 fixed_regs[i] = call_used_regs[i] = 1;
264 /* Show we can debug even without a frame pointer. */
265 #define CAN_DEBUG_WITHOUT_FP
267 /* target machine storage layout */
269 /* Define to enable software floating point emulation. */
270 #define REAL_ARITHMETIC
272 /* The following #defines are used when compiling the routines in
273 libgcc1.c. Since the Alpha calling conventions require single
274 precision floats to be passed in the floating-point registers
275 (rather than in the general registers) we have to build the
276 libgcc1.c routines in such a way that they know the actual types
277 of their formal arguments and the actual types of their return
278 values. Otherwise, gcc will generate calls to the libgcc1.c
279 routines, passing arguments in the floating-point registers,
280 but the libgcc1.c routines will expect their arguments on the
281 stack (where the Alpha calling conventions require structs &
282 unions to be passed). */
284 #define FLOAT_VALUE_TYPE double
285 #define INTIFY(FLOATVAL) (FLOATVAL)
286 #define FLOATIFY(INTVAL) (INTVAL)
287 #define FLOAT_ARG_TYPE double
289 /* Define the size of `int'. The default is the same as the word size. */
290 #define INT_TYPE_SIZE 32
292 /* Define the size of `long long'. The default is the twice the word size. */
293 #define LONG_LONG_TYPE_SIZE 64
295 /* The two floating-point formats we support are S-floating, which is
296 4 bytes, and T-floating, which is 8 bytes. `float' is S and `double'
297 and `long double' are T. */
299 #define FLOAT_TYPE_SIZE 32
300 #define DOUBLE_TYPE_SIZE 64
301 #define LONG_DOUBLE_TYPE_SIZE 64
303 #define WCHAR_TYPE "unsigned int"
304 #define WCHAR_TYPE_SIZE 32
306 /* Define this macro if it is advisable to hold scalars in registers
307 in a wider mode than that declared by the program. In such cases,
308 the value is constrained to be within the bounds of the declared
309 type, but kept valid in the wider mode. The signedness of the
310 extension may differ from that of the type.
312 For Alpha, we always store objects in a full register. 32-bit objects
313 are always sign-extended, but smaller objects retain their signedness. */
315 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
316 if (GET_MODE_CLASS (MODE) == MODE_INT \
317 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
319 if ((MODE) == SImode) \
324 /* Define this if function arguments should also be promoted using the above
327 #define PROMOTE_FUNCTION_ARGS
329 /* Likewise, if the function return value is promoted. */
331 #define PROMOTE_FUNCTION_RETURN
333 /* Define this if most significant bit is lowest numbered
334 in instructions that operate on numbered bit-fields.
336 There are no such instructions on the Alpha, but the documentation
338 #define BITS_BIG_ENDIAN 0
340 /* Define this if most significant byte of a word is the lowest numbered.
341 This is false on the Alpha. */
342 #define BYTES_BIG_ENDIAN 0
344 /* Define this if most significant word of a multiword number is lowest
347 For Alpha we can decide arbitrarily since there are no machine instructions
348 for them. Might as well be consistent with bytes. */
349 #define WORDS_BIG_ENDIAN 0
351 /* number of bits in an addressable storage unit */
352 #define BITS_PER_UNIT 8
354 /* Width in bits of a "word", which is the contents of a machine register.
355 Note that this is not necessarily the width of data type `int';
356 if using 16-bit ints on a 68000, this would still be 32.
357 But on a machine with 16-bit registers, this would be 16. */
358 #define BITS_PER_WORD 64
360 /* Width of a word, in units (bytes). */
361 #define UNITS_PER_WORD 8
363 /* Width in bits of a pointer.
364 See also the macro `Pmode' defined below. */
365 #define POINTER_SIZE 64
367 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
368 #define PARM_BOUNDARY 64
370 /* Boundary (in *bits*) on which stack pointer should be aligned. */
371 #define STACK_BOUNDARY 64
373 /* Allocation boundary (in *bits*) for the code of a function. */
374 #define FUNCTION_BOUNDARY 64
376 /* Alignment of field after `int : 0' in a structure. */
377 #define EMPTY_FIELD_BOUNDARY 64
379 /* Every structure's size must be a multiple of this. */
380 #define STRUCTURE_SIZE_BOUNDARY 8
382 /* A bitfield declared as `int' forces `int' alignment for the struct. */
383 #define PCC_BITFIELD_TYPE_MATTERS 1
385 /* Align loop starts for optimal branching.
387 ??? Kludge this and the next macro for the moment by not doing anything if
388 we don't optimize and also if we are writing ECOFF symbols to work around
389 a bug in DEC's assembler. */
390 /* Aligning past 2**3 wastes insn cache lines, and doesn't buy much
391 issue-wise on average anyway. */
393 #define LOOP_ALIGN(LABEL) \
394 (optimize > 0 && write_symbols != SDB_DEBUG ? 3 : 0)
396 /* This is how to align an instruction for optimal branching.
397 On Alpha we'll get better performance by aligning on a quadword
399 /* Aligning past 2**3 wastes insn cache lines, and doesn't buy much
400 issue-wise on average anyway. */
402 #define ALIGN_LABEL_AFTER_BARRIER(FILE) \
403 (optimize > 0 && write_symbols != SDB_DEBUG ? 3 : 0)
405 /* No data type wants to be aligned rounder than this. */
406 #define BIGGEST_ALIGNMENT 64
408 /* For atomic access to objects, must have at least 32-bit alignment
409 unless the machine has byte operations. */
410 #define MINIMUM_ATOMIC_ALIGNMENT (TARGET_BWX ? 8 : 32)
412 /* Align all constants and variables to at least a word boundary so
413 we can pick up pieces of them faster. */
414 /* ??? Only if block-move stuff knows about different source/destination
417 #define CONSTANT_ALIGNMENT(EXP, ALIGN) MAX ((ALIGN), BITS_PER_WORD)
418 #define DATA_ALIGNMENT(EXP, ALIGN) MAX ((ALIGN), BITS_PER_WORD)
421 /* Set this non-zero if move instructions will actually fail to work
422 when given unaligned data.
424 Since we get an error message when we do one, call them invalid. */
426 #define STRICT_ALIGNMENT 1
428 /* Set this non-zero if unaligned move instructions are extremely slow.
430 On the Alpha, they trap. */
432 #define SLOW_UNALIGNED_ACCESS 1
434 /* Standard register usage. */
436 /* Number of actual hardware registers.
437 The hardware registers are assigned numbers for the compiler
438 from 0 to just below FIRST_PSEUDO_REGISTER.
439 All registers that the compiler knows about must be given numbers,
440 even those that are not normally considered general registers.
442 We define all 32 integer registers, even though $31 is always zero,
443 and all 32 floating-point registers, even though $f31 is also
444 always zero. We do not bother defining the FP status register and
445 there are no other registers.
447 Since $31 is always zero, we will use register number 31 as the
448 argument pointer. It will never appear in the generated code
449 because we will always be eliminating it in favor of the stack
450 pointer or hardware frame pointer.
452 Likewise, we use $f31 for the frame pointer, which will always
453 be eliminated in favor of the hardware frame pointer or the
456 #define FIRST_PSEUDO_REGISTER 64
458 /* 1 for registers that have pervasive standard uses
459 and are not available for the register allocator. */
461 #define FIXED_REGISTERS \
462 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
463 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, \
464 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
465 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 }
467 /* 1 for registers not available across function calls.
468 These must include the FIXED_REGISTERS and also any
469 registers that can be used without being saved.
470 The latter must include the registers where values are returned
471 and the register where structure-value addresses are passed.
472 Aside from that, you can include as many other registers as you like. */
473 #define CALL_USED_REGISTERS \
474 {1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
475 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, \
476 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, \
477 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }
479 /* List the order in which to allocate registers. Each register must be
480 listed once, even those in FIXED_REGISTERS.
482 We allocate in the following order:
483 $f10-$f15 (nonsaved floating-point register)
485 $f21-$f16 (likewise, but input args)
486 $f0 (nonsaved, but return value)
487 $f1 (nonsaved, but immediate before saved)
488 $f2-$f9 (saved floating-point registers)
489 $1-$8 (nonsaved integer registers)
492 $0 (likewise, but return value)
493 $21-$16 (likewise, but input args)
494 $27 (procedure value in OSF, nonsaved in NT)
495 $9-$14 (saved integer registers)
499 $30, $31, $f31 (stack pointer and always zero/ap & fp) */
501 #define REG_ALLOC_ORDER \
502 {42, 43, 44, 45, 46, 47, \
503 54, 55, 56, 57, 58, 59, 60, 61, 62, \
504 53, 52, 51, 50, 49, 48, \
506 34, 35, 36, 37, 38, 39, 40, 41, \
507 1, 2, 3, 4, 5, 6, 7, 8, \
511 21, 20, 19, 18, 17, 16, \
513 9, 10, 11, 12, 13, 14, \
519 /* Return number of consecutive hard regs needed starting at reg REGNO
520 to hold something of mode MODE.
521 This is ordinarily the length in words of a value of mode MODE
522 but can be less for certain modes in special long registers. */
524 #define HARD_REGNO_NREGS(REGNO, MODE) \
525 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
527 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
528 On Alpha, the integer registers can hold any mode. The floating-point
529 registers can hold 32-bit and 64-bit integers as well, but not 16-bit
530 or 8-bit values. If we only allowed the larger integers into FP registers,
531 we'd have to say that QImode and SImode aren't tiable, which is a
532 pain. So say all registers can hold everything and see how that works. */
534 #define HARD_REGNO_MODE_OK(REGNO, MODE) 1
536 /* Value is 1 if it is a good idea to tie two pseudo registers
537 when one has mode MODE1 and one has mode MODE2.
538 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
539 for any hard reg, then this must be 0 for correct output. */
541 #define MODES_TIEABLE_P(MODE1, MODE2) 1
543 /* Specify the registers used for certain standard purposes.
544 The values of these macros are register numbers. */
546 /* Alpha pc isn't overloaded on a register that the compiler knows about. */
547 /* #define PC_REGNUM */
549 /* Register to use for pushing function arguments. */
550 #define STACK_POINTER_REGNUM 30
552 /* Base register for access to local variables of the function. */
553 #define HARD_FRAME_POINTER_REGNUM 15
555 /* Value should be nonzero if functions must have frame pointers.
556 Zero means the frame pointer need not be set up (and parms
557 may be accessed via the stack pointer) in functions that seem suitable.
558 This is computed in `reload', in reload1.c. */
559 #define FRAME_POINTER_REQUIRED 0
561 /* Base register for access to arguments of the function. */
562 #define ARG_POINTER_REGNUM 31
564 /* Base register for access to local variables of function. */
565 #define FRAME_POINTER_REGNUM 63
567 /* Register in which static-chain is passed to a function.
569 For the Alpha, this is based on an example; the calling sequence
570 doesn't seem to specify this. */
571 #define STATIC_CHAIN_REGNUM 1
573 /* Register in which address to store a structure value
574 arrives in the function. On the Alpha, the address is passed
575 as a hidden argument. */
576 #define STRUCT_VALUE 0
578 /* Define the classes of registers for register constraints in the
579 machine description. Also define ranges of constants.
581 One of the classes must always be named ALL_REGS and include all hard regs.
582 If there is more than one class, another class must be named NO_REGS
583 and contain no registers.
585 The name GENERAL_REGS must be the name of a class (or an alias for
586 another name such as ALL_REGS). This is the class of registers
587 that is allowed by "g" or "r" in a register constraint.
588 Also, registers outside this class are allocated only when
589 instructions express preferences for them.
591 The classes must be numbered in nondecreasing order; that is,
592 a larger-numbered class must never be contained completely
593 in a smaller-numbered class.
595 For any two classes, it is very desirable that there be another
596 class that represents their union. */
598 enum reg_class { NO_REGS, GENERAL_REGS, FLOAT_REGS, ALL_REGS,
601 #define N_REG_CLASSES (int) LIM_REG_CLASSES
603 /* Give names of register classes as strings for dump file. */
605 #define REG_CLASS_NAMES \
606 {"NO_REGS", "GENERAL_REGS", "FLOAT_REGS", "ALL_REGS" }
608 /* Define which registers fit in which classes.
609 This is an initializer for a vector of HARD_REG_SET
610 of length N_REG_CLASSES. */
612 #define REG_CLASS_CONTENTS \
613 { {0, 0}, {~0, 0x80000000}, {0, 0x7fffffff}, {~0, ~0} }
615 /* The same information, inverted:
616 Return the class number of the smallest class containing
617 reg number REGNO. This could be a conditional expression
618 or could index an array. */
620 #define REGNO_REG_CLASS(REGNO) \
621 ((REGNO) >= 32 && (REGNO) <= 62 ? FLOAT_REGS : GENERAL_REGS)
623 /* The class value for index registers, and the one for base regs. */
624 #define INDEX_REG_CLASS NO_REGS
625 #define BASE_REG_CLASS GENERAL_REGS
627 /* Get reg_class from a letter such as appears in the machine description. */
629 #define REG_CLASS_FROM_LETTER(C) \
630 ((C) == 'f' ? FLOAT_REGS : NO_REGS)
632 /* Define this macro to change register usage conditional on target flags. */
633 /* #define CONDITIONAL_REGISTER_USAGE */
635 /* The letters I, J, K, L, M, N, O, and P in a register constraint string
636 can be used to stand for particular ranges of immediate operands.
637 This macro defines what the ranges are.
638 C is the letter, and VALUE is a constant value.
639 Return 1 if VALUE is in the range specified by C.
642 `I' is used for the range of constants most insns can contain.
643 `J' is the constant zero.
644 `K' is used for the constant in an LDA insn.
645 `L' is used for the constant in a LDAH insn.
646 `M' is used for the constants that can be AND'ed with using a ZAP insn.
647 `N' is used for complemented 8-bit constants.
648 `O' is used for negated 8-bit constants.
649 `P' is used for the constants 1, 2 and 3. */
651 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
652 ((C) == 'I' ? (unsigned HOST_WIDE_INT) (VALUE) < 0x100 \
653 : (C) == 'J' ? (VALUE) == 0 \
654 : (C) == 'K' ? (unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000 \
655 : (C) == 'L' ? (((VALUE) & 0xffff) == 0 \
656 && (((VALUE)) >> 31 == -1 || (VALUE) >> 31 == 0)) \
657 : (C) == 'M' ? zap_mask (VALUE) \
658 : (C) == 'N' ? (unsigned HOST_WIDE_INT) (~ (VALUE)) < 0x100 \
659 : (C) == 'O' ? (unsigned HOST_WIDE_INT) (- (VALUE)) < 0x100 \
660 : (C) == 'P' ? (VALUE) == 1 || (VALUE) == 2 || (VALUE) == 3 \
663 /* Similar, but for floating or large integer constants, and defining letters
664 G and H. Here VALUE is the CONST_DOUBLE rtx itself.
666 For Alpha, `G' is the floating-point constant zero. `H' is a CONST_DOUBLE
667 that is the operand of a ZAP insn. */
669 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
670 ((C) == 'G' ? (GET_MODE_CLASS (GET_MODE (VALUE)) == MODE_FLOAT \
671 && (VALUE) == CONST0_RTX (GET_MODE (VALUE))) \
672 : (C) == 'H' ? (GET_MODE (VALUE) == VOIDmode \
673 && zap_mask (CONST_DOUBLE_LOW (VALUE)) \
674 && zap_mask (CONST_DOUBLE_HIGH (VALUE))) \
677 /* Optional extra constraints for this machine.
679 For the Alpha, `Q' means that this is a memory operand but not a
680 reference to an unaligned location.
681 `R' is a SYMBOL_REF that has SYMBOL_REF_FLAG set or is the current
684 #define EXTRA_CONSTRAINT(OP, C) \
685 ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) != AND \
686 : (C) == 'R' ? current_file_function_operand (OP, Pmode) \
689 /* Given an rtx X being reloaded into a reg required to be
690 in class CLASS, return the class of reg to actually use.
691 In general this is just CLASS; but on some machines
692 in some cases it is preferable to use a more restrictive class.
694 On the Alpha, all constants except zero go into a floating-point
695 register via memory. */
697 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
698 (CONSTANT_P (X) && (X) != const0_rtx && (X) != CONST0_RTX (GET_MODE (X)) \
699 ? ((CLASS) == FLOAT_REGS || (CLASS) == NO_REGS ? NO_REGS : GENERAL_REGS)\
702 /* Loading and storing HImode or QImode values to and from memory
703 usually requires a scratch register. The exceptions are loading
704 QImode and HImode from an aligned address to a general register
705 unless byte instructions are permitted.
706 We also cannot load an unaligned address or a paradoxical SUBREG into an
709 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,IN) \
710 (((GET_CODE (IN) == MEM \
711 || (GET_CODE (IN) == REG && REGNO (IN) >= FIRST_PSEUDO_REGISTER) \
712 || (GET_CODE (IN) == SUBREG \
713 && (GET_CODE (SUBREG_REG (IN)) == MEM \
714 || (GET_CODE (SUBREG_REG (IN)) == REG \
715 && REGNO (SUBREG_REG (IN)) >= FIRST_PSEUDO_REGISTER)))) \
716 && (((CLASS) == FLOAT_REGS \
717 && ((MODE) == SImode || (MODE) == HImode || (MODE) == QImode)) \
718 || (((MODE) == QImode || (MODE) == HImode) \
719 && ! TARGET_BWX && unaligned_memory_operand (IN, MODE)))) \
721 : ((CLASS) == FLOAT_REGS && GET_CODE (IN) == MEM \
722 && GET_CODE (XEXP (IN, 0)) == AND) ? GENERAL_REGS \
723 : ((CLASS) == FLOAT_REGS && GET_CODE (IN) == SUBREG \
724 && (GET_MODE_SIZE (GET_MODE (IN)) \
725 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (IN))))) ? GENERAL_REGS \
728 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,OUT) \
729 (((GET_CODE (OUT) == MEM \
730 || (GET_CODE (OUT) == REG && REGNO (OUT) >= FIRST_PSEUDO_REGISTER) \
731 || (GET_CODE (OUT) == SUBREG \
732 && (GET_CODE (SUBREG_REG (OUT)) == MEM \
733 || (GET_CODE (SUBREG_REG (OUT)) == REG \
734 && REGNO (SUBREG_REG (OUT)) >= FIRST_PSEUDO_REGISTER)))) \
735 && ((((MODE) == HImode || (MODE) == QImode) \
736 && (! TARGET_BWX || (CLASS) == FLOAT_REGS)) \
737 || ((MODE) == SImode && (CLASS) == FLOAT_REGS))) \
739 : ((CLASS) == FLOAT_REGS && GET_CODE (OUT) == MEM \
740 && GET_CODE (XEXP (OUT, 0)) == AND) ? GENERAL_REGS \
741 : ((CLASS) == FLOAT_REGS && GET_CODE (OUT) == SUBREG \
742 && (GET_MODE_SIZE (GET_MODE (OUT)) \
743 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (OUT))))) ? GENERAL_REGS \
746 /* If we are copying between general and FP registers, we need a memory
747 location unless the CIX extension is available. */
749 #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
750 (! TARGET_CIX && (CLASS1) != (CLASS2))
752 /* Specify the mode to be used for memory when a secondary memory
753 location is needed. If MODE is floating-point, use it. Otherwise,
754 widen to a word like the default. This is needed because we always
755 store integers in FP registers in quadword format. This whole
756 area is very tricky! */
757 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
758 (GET_MODE_CLASS (MODE) == MODE_FLOAT ? (MODE) \
759 : GET_MODE_SIZE (MODE) >= 4 ? (MODE) \
760 : mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0))
762 /* Return the maximum number of consecutive registers
763 needed to represent mode MODE in a register of class CLASS. */
765 #define CLASS_MAX_NREGS(CLASS, MODE) \
766 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
768 /* If defined, gives a class of registers that cannot be used as the
769 operand of a SUBREG that changes the size of the object. */
771 #define CLASS_CANNOT_CHANGE_SIZE FLOAT_REGS
773 /* Define the cost of moving between registers of various classes. Moving
774 between FLOAT_REGS and anything else except float regs is expensive.
775 In fact, we make it quite expensive because we really don't want to
776 do these moves unless it is clearly worth it. Optimizations may
777 reduce the impact of not being able to allocate a pseudo to a
780 #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
781 (((CLASS1) == FLOAT_REGS) == ((CLASS2) == FLOAT_REGS) \
783 : TARGET_CIX ? 3 : 4+2*alpha_memory_latency)
785 /* A C expressions returning the cost of moving data of MODE from a register to
788 On the Alpha, bump this up a bit. */
790 extern int alpha_memory_latency;
791 #define MEMORY_MOVE_COST(MODE,CLASS,IN) (2*alpha_memory_latency)
793 /* Provide the cost of a branch. Exact meaning under development. */
794 #define BRANCH_COST 5
796 /* Adjust the cost of dependencies. */
798 #define ADJUST_COST(INSN,LINK,DEP,COST) \
799 (COST) = alpha_adjust_cost (INSN, LINK, DEP, COST)
801 /* Stack layout; function entry, exit and calling. */
803 /* Define this if pushing a word on the stack
804 makes the stack pointer a smaller address. */
805 #define STACK_GROWS_DOWNWARD
807 /* Define this if the nominal address of the stack frame
808 is at the high-address end of the local variables;
809 that is, each additional local variable allocated
810 goes at a more negative offset in the frame. */
811 /* #define FRAME_GROWS_DOWNWARD */
813 /* Offset within stack frame to start allocating local variables at.
814 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
815 first local allocated. Otherwise, it is the offset to the BEGINNING
816 of the first local allocated. */
818 #define STARTING_FRAME_OFFSET 0
820 /* If we generate an insn to push BYTES bytes,
821 this says how many the stack pointer really advances by.
822 On Alpha, don't define this because there are no push insns. */
823 /* #define PUSH_ROUNDING(BYTES) */
825 /* Define this to be nonzero if stack checking is built into the ABI. */
826 #define STACK_CHECK_BUILTIN 1
828 /* Define this if the maximum size of all the outgoing args is to be
829 accumulated and pushed during the prologue. The amount can be
830 found in the variable current_function_outgoing_args_size. */
831 #define ACCUMULATE_OUTGOING_ARGS
833 /* Offset of first parameter from the argument pointer register value. */
835 #define FIRST_PARM_OFFSET(FNDECL) 0
837 /* Definitions for register eliminations.
839 We have two registers that can be eliminated on the Alpha. First, the
840 frame pointer register can often be eliminated in favor of the stack
841 pointer register. Secondly, the argument pointer register can always be
842 eliminated; it is replaced with either the stack or frame pointer. */
844 /* This is an array of structures. Each structure initializes one pair
845 of eliminable registers. The "from" register number is given first,
846 followed by "to". Eliminations of the same "from" register are listed
847 in order of preference. */
849 #define ELIMINABLE_REGS \
850 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
851 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
852 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
853 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
855 /* Given FROM and TO register numbers, say whether this elimination is allowed.
856 Frame pointer elimination is automatically handled.
858 All eliminations are valid since the cases where FP can't be
859 eliminated are already handled. */
861 #define CAN_ELIMINATE(FROM, TO) 1
863 /* Round up to a multiple of 16 bytes. */
864 #define ALPHA_ROUND(X) (((X) + 15) & ~ 15)
866 /* Define the offset between two registers, one to be eliminated, and the other
867 its replacement, at the start of a routine. */
868 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
869 { if ((FROM) == FRAME_POINTER_REGNUM) \
870 (OFFSET) = (ALPHA_ROUND (current_function_outgoing_args_size) \
871 + alpha_sa_size ()); \
872 else if ((FROM) == ARG_POINTER_REGNUM) \
873 (OFFSET) = (ALPHA_ROUND (current_function_outgoing_args_size) \
875 + (ALPHA_ROUND (get_frame_size () \
876 + current_function_pretend_args_size) \
877 - current_function_pretend_args_size)); \
880 /* Define this if stack space is still allocated for a parameter passed
882 /* #define REG_PARM_STACK_SPACE */
884 /* Value is the number of bytes of arguments automatically
885 popped when returning from a subroutine call.
886 FUNDECL is the declaration node of the function (as a tree),
887 FUNTYPE is the data type of the function (as a tree),
888 or for a library call it is an identifier node for the subroutine name.
889 SIZE is the number of bytes of arguments passed on the stack. */
891 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
893 /* Define how to find the value returned by a function.
894 VALTYPE is the data type of the value (as a tree).
895 If the precise function being called is known, FUNC is its FUNCTION_DECL;
896 otherwise, FUNC is 0.
898 On Alpha the value is found in $0 for integer functions and
899 $f0 for floating-point functions. */
901 #define FUNCTION_VALUE(VALTYPE, FUNC) \
903 ((INTEGRAL_TYPE_P (VALTYPE) \
904 && TYPE_PRECISION (VALTYPE) < BITS_PER_WORD) \
905 || POINTER_TYPE_P (VALTYPE)) \
906 ? word_mode : TYPE_MODE (VALTYPE), \
908 && (TREE_CODE (VALTYPE) == REAL_TYPE \
909 || TREE_CODE (VALTYPE) == COMPLEX_TYPE)) \
912 /* Define how to find the value returned by a library function
913 assuming the value has mode MODE. */
915 #define LIBCALL_VALUE(MODE) \
916 gen_rtx (REG, MODE, \
918 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
919 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
922 /* The definition of this macro implies that there are cases where
923 a scalar value cannot be returned in registers.
925 For the Alpha, any structure or union type is returned in memory, as
926 are integers whose size is larger than 64 bits. */
928 #define RETURN_IN_MEMORY(TYPE) \
929 (TYPE_MODE (TYPE) == BLKmode \
930 || (TREE_CODE (TYPE) == INTEGER_TYPE && TYPE_PRECISION (TYPE) > 64))
932 /* 1 if N is a possible register number for a function value
933 as seen by the caller. */
935 #define FUNCTION_VALUE_REGNO_P(N) \
936 ((N) == 0 || (N) == 1 || (N) == 32 || (N) == 33)
938 /* 1 if N is a possible register number for function argument passing.
939 On Alpha, these are $16-$21 and $f16-$f21. */
941 #define FUNCTION_ARG_REGNO_P(N) \
942 (((N) >= 16 && (N) <= 21) || ((N) >= 16 + 32 && (N) <= 21 + 32))
944 /* Define a data type for recording info about an argument list
945 during the scan of that argument list. This data type should
946 hold all necessary information about the function itself
947 and about the args processed so far, enough to enable macros
948 such as FUNCTION_ARG to determine where the next arg should go.
950 On Alpha, this is a single integer, which is a number of words
951 of arguments scanned so far.
952 Thus 6 or more means all following args should go on the stack. */
954 #define CUMULATIVE_ARGS int
956 /* Initialize a variable CUM of type CUMULATIVE_ARGS
957 for a call to a function whose data type is FNTYPE.
958 For a library call, FNTYPE is 0. */
960 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) (CUM) = 0
962 /* Define intermediate macro to compute the size (in registers) of an argument
965 #define ALPHA_ARG_SIZE(MODE, TYPE, NAMED) \
967 ? (GET_MODE_SIZE (MODE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD \
968 : (int_size_in_bytes (TYPE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
970 /* Update the data in CUM to advance over an argument
971 of mode MODE and data type TYPE.
972 (TYPE is null for libcalls where that information may not be available.) */
974 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
975 if (MUST_PASS_IN_STACK (MODE, TYPE)) \
978 (CUM) += ALPHA_ARG_SIZE (MODE, TYPE, NAMED)
980 /* Determine where to put an argument to a function.
981 Value is zero to push the argument on the stack,
982 or a hard register in which to store the argument.
984 MODE is the argument's machine mode.
985 TYPE is the data type of the argument (as a tree).
986 This is null for libcalls where that information may
988 CUM is a variable of type CUMULATIVE_ARGS which gives info about
989 the preceding args and about the function being called.
990 NAMED is nonzero if this argument is a named parameter
991 (otherwise it is an extra parameter matching an ellipsis).
993 On Alpha the first 6 words of args are normally in registers
994 and the rest are pushed. */
996 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
997 ((CUM) < 6 && ! MUST_PASS_IN_STACK (MODE, TYPE) \
998 ? gen_rtx(REG, (MODE), \
999 (CUM) + 16 + ((TARGET_FPREGS \
1000 && (GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT \
1001 || GET_MODE_CLASS (MODE) == MODE_FLOAT)) \
1005 /* Specify the padding direction of arguments.
1007 On the Alpha, we must pad upwards in order to be able to pass args in
1010 #define FUNCTION_ARG_PADDING(MODE, TYPE) upward
1012 /* For an arg passed partly in registers and partly in memory,
1013 this is the number of registers used.
1014 For args passed entirely in registers or entirely in memory, zero. */
1016 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1017 ((CUM) < 6 && 6 < (CUM) + ALPHA_ARG_SIZE (MODE, TYPE, NAMED) \
1020 /* Perform any needed actions needed for a function that is receiving a
1021 variable number of arguments.
1025 MODE and TYPE are the mode and type of the current parameter.
1027 PRETEND_SIZE is a variable that should be set to the amount of stack
1028 that must be pushed by the prolog to pretend that our caller pushed
1031 Normally, this macro will push all remaining incoming registers on the
1032 stack and set PRETEND_SIZE to the length of the registers pushed.
1034 On the Alpha, we allocate space for all 12 arg registers, but only
1035 push those that are remaining.
1037 However, if NO registers need to be saved, don't allocate any space.
1038 This is not only because we won't need the space, but because AP includes
1039 the current_pretend_args_size and we don't want to mess up any
1040 ap-relative addresses already made.
1042 If we are not to use the floating-point registers, save the integer
1043 registers where we would put the floating-point registers. This is
1044 not the most efficient way to implement varargs with just one register
1045 class, but it isn't worth doing anything more efficient in this rare
1049 #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
1054 move_block_from_reg \
1056 gen_rtx (MEM, BLKmode, \
1057 plus_constant (virtual_incoming_args_rtx, \
1058 ((CUM) + 6)* UNITS_PER_WORD)), \
1059 6 - (CUM), (6 - (CUM)) * UNITS_PER_WORD); \
1060 move_block_from_reg \
1061 (16 + (TARGET_FPREGS ? 32 : 0) + CUM, \
1062 gen_rtx (MEM, BLKmode, \
1063 plus_constant (virtual_incoming_args_rtx, \
1064 (CUM) * UNITS_PER_WORD)), \
1065 6 - (CUM), (6 - (CUM)) * UNITS_PER_WORD); \
1066 emit_insn (gen_blockage ()); \
1068 PRETEND_SIZE = 12 * UNITS_PER_WORD; \
1072 /* Try to output insns to set TARGET equal to the constant C if it can be
1073 done in less than N insns. Do all computations in MODE. Returns the place
1074 where the output has been placed if it can be done and the insns have been
1075 emitted. If it would take more than N insns, zero is returned and no
1076 insns and emitted. */
1077 extern struct rtx_def *alpha_emit_set_const ();
1078 extern struct rtx_def *alpha_emit_set_long_const ();
1079 extern struct rtx_def *alpha_emit_conditional_move ();
1081 /* Generate necessary RTL for __builtin_saveregs().
1082 ARGLIST is the argument list; see expr.c. */
1083 extern struct rtx_def *alpha_builtin_saveregs ();
1084 #define EXPAND_BUILTIN_SAVEREGS(ARGLIST) alpha_builtin_saveregs (ARGLIST)
1086 /* Define the information needed to generate branch and scc insns. This is
1087 stored from the compare operation. Note that we can't use "rtx" here
1088 since it hasn't been defined! */
1090 extern struct rtx_def *alpha_compare_op0, *alpha_compare_op1;
1091 extern int alpha_compare_fp_p;
1093 /* Make (or fake) .linkage entry for function call.
1095 IS_LOCAL is 0 if name is used in call, 1 if name is used in definition. */
1096 extern void alpha_need_linkage ();
1098 /* This macro defines the start of an assembly comment. */
1100 #define ASM_COMMENT_START " #"
1102 /* This macro produces the initial definition of a function name. On the
1103 Alpha, we need to save the function name for the prologue and epilogue. */
1105 extern char *alpha_function_name;
1107 #define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL) \
1109 alpha_function_name = NAME; \
1112 /* This macro generates the assembly code for function entry.
1113 FILE is a stdio stream to output the code to.
1114 SIZE is an int: how many units of temporary storage to allocate.
1115 Refer to the array `regs_ever_live' to determine which registers
1116 to save; `regs_ever_live[I]' is nonzero if register number I
1117 is ever used in the function. This macro is responsible for
1118 knowing which registers should not be saved even if used. */
1120 #define FUNCTION_PROLOGUE(FILE, SIZE) output_prolog (FILE, SIZE)
1122 /* Output assembler code to FILE to increment profiler label # LABELNO
1123 for profiling a function entry. Under OSF/1, profiling is enabled
1124 by simply passing -pg to the assembler and linker. */
1126 #define FUNCTION_PROFILER(FILE, LABELNO)
1128 /* Output assembler code to FILE to initialize this source file's
1129 basic block profiling info, if that has not already been done.
1130 This assumes that __bb_init_func doesn't garble a1-a5. */
1132 #define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \
1134 ASM_OUTPUT_REG_PUSH (FILE, 16); \
1135 fputs ("\tlda $16,$PBX32\n", (FILE)); \
1136 fputs ("\tldq $26,0($16)\n", (FILE)); \
1137 fputs ("\tbne $26,1f\n", (FILE)); \
1138 fputs ("\tlda $27,__bb_init_func\n", (FILE)); \
1139 fputs ("\tjsr $26,($27),__bb_init_func\n", (FILE)); \
1140 fputs ("\tldgp $29,0($26)\n", (FILE)); \
1141 fputs ("1:\n", (FILE)); \
1142 ASM_OUTPUT_REG_POP (FILE, 16); \
1145 /* Output assembler code to FILE to increment the entry-count for
1146 the BLOCKNO'th basic block in this source file. */
1148 #define BLOCK_PROFILER(FILE, BLOCKNO) \
1150 int blockn = (BLOCKNO); \
1151 fputs ("\tsubq $30,16,$30\n", (FILE)); \
1152 fputs ("\tstq $26,0($30)\n", (FILE)); \
1153 fputs ("\tstq $27,8($30)\n", (FILE)); \
1154 fputs ("\tlda $26,$PBX34\n", (FILE)); \
1155 fprintf ((FILE), "\tldq $27,%d($26)\n", 8*blockn); \
1156 fputs ("\taddq $27,1,$27\n", (FILE)); \
1157 fprintf ((FILE), "\tstq $27,%d($26)\n", 8*blockn); \
1158 fputs ("\tldq $26,0($30)\n", (FILE)); \
1159 fputs ("\tldq $27,8($30)\n", (FILE)); \
1160 fputs ("\taddq $30,16,$30\n", (FILE)); \
1164 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1165 the stack pointer does not matter. The value is tested only in
1166 functions that have frame pointers.
1167 No definition is equivalent to always zero. */
1169 #define EXIT_IGNORE_STACK 1
1171 /* This macro generates the assembly code for function exit,
1172 on machines that need it. If FUNCTION_EPILOGUE is not defined
1173 then individual return instructions are generated for each
1174 return statement. Args are same as for FUNCTION_PROLOGUE.
1176 The function epilogue should not depend on the current stack pointer!
1177 It should use the frame pointer only. This is mandatory because
1178 of alloca; we also take advantage of it to omit stack adjustments
1179 before returning. */
1181 #define FUNCTION_EPILOGUE(FILE, SIZE) output_epilog (FILE, SIZE)
1184 /* Output assembler code for a block containing the constant parts
1185 of a trampoline, leaving space for the variable parts.
1187 The trampoline should set the static chain pointer to value placed
1188 into the trampoline and should branch to the specified routine.
1189 Note that $27 has been set to the address of the trampoline, so we can
1190 use it for addressability of the two data items. Trampolines are always
1191 aligned to FUNCTION_BOUNDARY, which is 64 bits. */
1193 #define TRAMPOLINE_TEMPLATE(FILE) \
1195 fprintf (FILE, "\tldq $1,24($27)\n"); \
1196 fprintf (FILE, "\tldq $27,16($27)\n"); \
1197 fprintf (FILE, "\tjmp $31,($27),0\n"); \
1198 fprintf (FILE, "\tnop\n"); \
1199 fprintf (FILE, "\t.quad 0,0\n"); \
1202 /* Section in which to place the trampoline. On Alpha, instructions
1203 may only be placed in a text segment. */
1205 #define TRAMPOLINE_SECTION text_section
1207 /* Length in units of the trampoline for entering a nested function. */
1209 #define TRAMPOLINE_SIZE 32
1211 /* Emit RTL insns to initialize the variable parts of a trampoline.
1212 FNADDR is an RTX for the address of the function's pure code.
1213 CXT is an RTX for the static chain value for the function. We assume
1214 here that a function will be called many more times than its address
1215 is taken (e.g., it might be passed to qsort), so we take the trouble
1216 to initialize the "hint" field in the JMP insn. Note that the hint
1217 field is PC (new) + 4 * bits 13:0. */
1219 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1221 rtx _temp, _temp1, _addr; \
1223 _addr = memory_address (Pmode, plus_constant ((TRAMP), 16)); \
1224 emit_move_insn (gen_rtx (MEM, Pmode, _addr), (FNADDR)); \
1225 _addr = memory_address (Pmode, plus_constant ((TRAMP), 24)); \
1226 emit_move_insn (gen_rtx (MEM, Pmode, _addr), (CXT)); \
1228 _temp = force_operand (plus_constant ((TRAMP), 12), NULL_RTX); \
1229 _temp = expand_binop (DImode, sub_optab, (FNADDR), _temp, _temp, 1, \
1231 _temp = expand_shift (RSHIFT_EXPR, Pmode, _temp, \
1232 build_int_2 (2, 0), NULL_RTX, 1); \
1233 _temp = expand_and (gen_lowpart (SImode, _temp), \
1234 GEN_INT (0x3fff), 0); \
1236 _addr = memory_address (SImode, plus_constant ((TRAMP), 8)); \
1237 _temp1 = force_reg (SImode, gen_rtx (MEM, SImode, _addr)); \
1238 _temp1 = expand_and (_temp1, GEN_INT (0xffffc000), NULL_RTX); \
1239 _temp1 = expand_binop (SImode, ior_optab, _temp1, _temp, _temp1, 1, \
1242 emit_move_insn (gen_rtx (MEM, SImode, _addr), _temp1); \
1244 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, \
1245 "__enable_execute_stack"), \
1246 0, VOIDmode, 1,_addr, Pmode); \
1248 emit_insn (gen_rtx (UNSPEC_VOLATILE, VOIDmode, \
1249 gen_rtvec (1, const0_rtx), 0)); \
1252 /* Attempt to turn on access permissions for the stack. */
1254 #define TRANSFER_FROM_TRAMPOLINE \
1257 __enable_execute_stack (addr) \
1260 long size = getpagesize (); \
1261 long mask = ~(size-1); \
1262 char *page = (char *) (((long) addr) & mask); \
1263 char *end = (char *) ((((long) (addr + TRAMPOLINE_SIZE)) & mask) + size); \
1265 /* 7 is PROT_READ | PROT_WRITE | PROT_EXEC */ \
1266 if (mprotect (page, end - page, 7) < 0) \
1267 perror ("mprotect of trampoline code"); \
1270 /* A C expression whose value is RTL representing the value of the return
1271 address for the frame COUNT steps up from the current frame.
1272 FRAMEADDR is the frame pointer of the COUNT frame, or the frame pointer of
1273 the COUNT-1 frame if RETURN_ADDR_IN_PREVIOUS_FRAME} is defined. */
1275 #define RETURN_ADDR_RTX alpha_return_addr
1276 extern struct rtx_def *alpha_return_addr ();
1278 /* Initialize data used by insn expanders. This is called from insn_emit,
1279 once for every function before code is generated. */
1281 #define INIT_EXPANDERS alpha_init_expanders ()
1282 extern void alpha_init_expanders ();
1285 /* Addressing modes, and classification of registers for them. */
1287 /* #define HAVE_POST_INCREMENT */
1288 /* #define HAVE_POST_DECREMENT */
1290 /* #define HAVE_PRE_DECREMENT */
1291 /* #define HAVE_PRE_INCREMENT */
1293 /* Macros to check register numbers against specific register classes. */
1295 /* These assume that REGNO is a hard or pseudo reg number.
1296 They give nonzero only if REGNO is a hard reg of the suitable class
1297 or a pseudo reg currently allocated to a suitable hard reg.
1298 Since they use reg_renumber, they are safe only once reg_renumber
1299 has been allocated, which happens in local-alloc.c. */
1301 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
1302 #define REGNO_OK_FOR_BASE_P(REGNO) \
1303 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32 \
1304 || (REGNO) == 63 || reg_renumber[REGNO] == 63)
1306 /* Maximum number of registers that can appear in a valid memory address. */
1307 #define MAX_REGS_PER_ADDRESS 1
1309 /* Recognize any constant value that is a valid address. For the Alpha,
1310 there are only constants none since we want to use LDA to load any
1311 symbolic addresses into registers. */
1313 #define CONSTANT_ADDRESS_P(X) \
1314 (GET_CODE (X) == CONST_INT \
1315 && (unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
1317 /* Include all constant integers and constant doubles, but not
1318 floating-point, except for floating-point zero. */
1320 #define LEGITIMATE_CONSTANT_P(X) \
1321 (GET_MODE_CLASS (GET_MODE (X)) != MODE_FLOAT \
1322 || (X) == CONST0_RTX (GET_MODE (X)))
1324 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1325 and check its validity for a certain class.
1326 We have two alternate definitions for each of them.
1327 The usual definition accepts all pseudo regs; the other rejects
1328 them unless they have been allocated suitable hard regs.
1329 The symbol REG_OK_STRICT causes the latter definition to be used.
1331 Most source files want to accept pseudo regs in the hope that
1332 they will get allocated to the class that the insn wants them to be in.
1333 Source files for reload pass need to be strict.
1334 After reload, it makes no difference, since pseudo regs have
1335 been eliminated by then. */
1337 #ifndef REG_OK_STRICT
1339 /* Nonzero if X is a hard reg that can be used as an index
1340 or if it is a pseudo reg. */
1341 #define REG_OK_FOR_INDEX_P(X) 0
1342 /* Nonzero if X is a hard reg that can be used as a base reg
1343 or if it is a pseudo reg. */
1344 #define REG_OK_FOR_BASE_P(X) \
1345 (REGNO (X) < 32 || REGNO (X) == 63 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1349 /* Nonzero if X is a hard reg that can be used as an index. */
1350 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1351 /* Nonzero if X is a hard reg that can be used as a base reg. */
1352 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1356 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1357 that is a valid memory address for an instruction.
1358 The MODE argument is the machine mode for the MEM expression
1359 that wants to use this address.
1361 For Alpha, we have either a constant address or the sum of a register
1362 and a constant address, or just a register. For DImode, any of those
1363 forms can be surrounded with an AND that clear the low-order three bits;
1364 this is an "unaligned" access.
1366 First define the basic valid address. */
1368 #define GO_IF_LEGITIMATE_SIMPLE_ADDRESS(MODE, X, ADDR) \
1369 { if (REG_P (X) && REG_OK_FOR_BASE_P (X)) \
1371 if (CONSTANT_ADDRESS_P (X)) \
1373 if (GET_CODE (X) == PLUS \
1374 && REG_P (XEXP (X, 0)) \
1375 && REG_OK_FOR_BASE_P (XEXP (X, 0)) \
1376 && CONSTANT_ADDRESS_P (XEXP (X, 1))) \
1380 /* Now accept the simple address, or, for DImode only, an AND of a simple
1381 address that turns off the low three bits. */
1383 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1384 { GO_IF_LEGITIMATE_SIMPLE_ADDRESS (MODE, X, ADDR); \
1385 if ((MODE) == DImode \
1386 && GET_CODE (X) == AND \
1387 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1388 && INTVAL (XEXP (X, 1)) == -8) \
1389 GO_IF_LEGITIMATE_SIMPLE_ADDRESS (MODE, XEXP (X, 0), ADDR); \
1392 /* Try machine-dependent ways of modifying an illegitimate address
1393 to be legitimate. If we find one, return the new, valid address.
1394 This macro is used in only one place: `memory_address' in explow.c.
1396 OLDX is the address as it was before break_out_memory_refs was called.
1397 In some cases it is useful to look at this to decide what needs to be done.
1399 MODE and WIN are passed so that this macro can use
1400 GO_IF_LEGITIMATE_ADDRESS.
1402 It is always safe for this macro to do nothing. It exists to recognize
1403 opportunities to optimize the output.
1405 For the Alpha, there are three cases we handle:
1407 (1) If the address is (plus reg const_int) and the CONST_INT is not a
1408 valid offset, compute the high part of the constant and add it to the
1409 register. Then our address is (plus temp low-part-const).
1410 (2) If the address is (const (plus FOO const_int)), find the low-order
1411 part of the CONST_INT. Then load FOO plus any high-order part of the
1412 CONST_INT into a register. Our address is (plus reg low-part-const).
1413 This is done to reduce the number of GOT entries.
1414 (3) If we have a (plus reg const), emit the load as in (2), then add
1415 the two registers, and finally generate (plus reg low-part-const) as
1418 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1419 { if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG \
1420 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1421 && ! CONSTANT_ADDRESS_P (XEXP (X, 1))) \
1423 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1424 HOST_WIDE_INT lowpart = (val & 0xffff) - 2 * (val & 0x8000); \
1425 HOST_WIDE_INT highpart = val - lowpart; \
1426 rtx high = GEN_INT (highpart); \
1427 rtx temp = expand_binop (Pmode, add_optab, XEXP (x, 0), \
1428 high, NULL_RTX, 1, OPTAB_LIB_WIDEN); \
1430 (X) = plus_constant (temp, lowpart); \
1433 else if (GET_CODE (X) == CONST \
1434 && GET_CODE (XEXP (X, 0)) == PLUS \
1435 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT) \
1437 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (X, 0), 1)); \
1438 HOST_WIDE_INT lowpart = (val & 0xffff) - 2 * (val & 0x8000); \
1439 HOST_WIDE_INT highpart = val - lowpart; \
1440 rtx high = XEXP (XEXP (X, 0), 0); \
1443 high = plus_constant (high, highpart); \
1445 (X) = plus_constant (force_reg (Pmode, high), lowpart); \
1448 else if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG \
1449 && GET_CODE (XEXP (X, 1)) == CONST \
1450 && GET_CODE (XEXP (XEXP (X, 1), 0)) == PLUS \
1451 && GET_CODE (XEXP (XEXP (XEXP (X, 1), 0), 1)) == CONST_INT) \
1453 HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (X, 1), 0), 1)); \
1454 HOST_WIDE_INT lowpart = (val & 0xffff) - 2 * (val & 0x8000); \
1455 HOST_WIDE_INT highpart = val - lowpart; \
1456 rtx high = XEXP (XEXP (XEXP (X, 1), 0), 0); \
1459 high = plus_constant (high, highpart); \
1461 high = expand_binop (Pmode, add_optab, XEXP (X, 0), \
1462 force_reg (Pmode, high), \
1463 high, 1, OPTAB_LIB_WIDEN); \
1464 (X) = plus_constant (high, lowpart); \
1469 /* Try a machine-dependent way of reloading an illegitimate address
1470 operand. If we find one, push the reload and jump to WIN. This
1471 macro is used in only one place: `find_reloads_address' in reload.c.
1473 For the Alpha, we wish to handle large displacements off a base
1474 register by splitting the addend across an ldah and the mem insn.
1475 This cuts number of extra insns needed from 3 to 1. */
1477 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1479 if (GET_CODE (X) == PLUS \
1480 && GET_CODE (XEXP (X, 0)) == REG \
1481 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1482 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1483 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1485 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1486 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; \
1487 HOST_WIDE_INT high \
1488 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000; \
1490 /* Check for 32-bit overflow. */ \
1491 if (high + low != val) \
1494 /* Reload the high part into a base reg; leave the low part \
1495 in the mem directly. */ \
1497 X = gen_rtx_PLUS (GET_MODE (X), \
1498 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1502 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL_PTR, \
1503 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
1509 /* Go to LABEL if ADDR (a legitimate address expression)
1510 has an effect that depends on the machine mode it is used for.
1511 On the Alpha this is true only for the unaligned modes. We can
1512 simplify this test since we know that the address must be valid. */
1514 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1515 { if (GET_CODE (ADDR) == AND) goto LABEL; }
1517 /* Compute the cost of an address. For the Alpha, all valid addresses are
1520 #define ADDRESS_COST(X) 0
1522 /* Machine-dependent reorg pass. */
1523 #define MACHINE_DEPENDENT_REORG(X) alpha_reorg(X)
1525 /* Specify the machine mode that this machine uses
1526 for the index in the tablejump instruction. */
1527 #define CASE_VECTOR_MODE SImode
1529 /* Define as C expression which evaluates to nonzero if the tablejump
1530 instruction expects the table to contain offsets from the address of the
1533 Do not define this if the table should contain absolute addresses.
1534 On the Alpha, the table is really GP-relative, not relative to the PC
1535 of the table, but we pretend that it is PC-relative; this should be OK,
1536 but we should try to find some better way sometime. */
1537 #define CASE_VECTOR_PC_RELATIVE 1
1539 /* Specify the tree operation to be used to convert reals to integers. */
1540 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1542 /* This is the kind of divide that is easiest to do in the general case. */
1543 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1545 /* Define this as 1 if `char' should by default be signed; else as 0. */
1546 #define DEFAULT_SIGNED_CHAR 1
1548 /* This flag, if defined, says the same insns that convert to a signed fixnum
1549 also convert validly to an unsigned one.
1551 We actually lie a bit here as overflow conditions are different. But
1552 they aren't being checked anyway. */
1554 #define FIXUNS_TRUNC_LIKE_FIX_TRUNC
1556 /* Max number of bytes we can move to or from memory
1557 in one reasonably fast instruction. */
1561 /* Controls how many units are moved by expr.c before resorting to movstr.
1562 Without byte/word accesses, we want no more than one; with, several single
1563 byte accesses are better. */
1565 #define MOVE_RATIO (TARGET_BWX ? 7 : 2)
1567 /* Largest number of bytes of an object that can be placed in a register.
1568 On the Alpha we have plenty of registers, so use TImode. */
1569 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode)
1571 /* Nonzero if access to memory by bytes is no faster than for words.
1572 Also non-zero if doing byte operations (specifically shifts) in registers
1575 On the Alpha, we want to not use the byte operation and instead use
1576 masking operations to access fields; these will save instructions. */
1578 #define SLOW_BYTE_ACCESS 1
1580 /* Define if operations between registers always perform the operation
1581 on the full register even if a narrower mode is specified. */
1582 #define WORD_REGISTER_OPERATIONS
1584 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1585 will either zero-extend or sign-extend. The value of this macro should
1586 be the code that says which one of the two operations is implicitly
1587 done, NIL if none. */
1588 #define LOAD_EXTEND_OP(MODE) ((MODE) == SImode ? SIGN_EXTEND : ZERO_EXTEND)
1590 /* Define if loading short immediate values into registers sign extends. */
1591 #define SHORT_IMMEDIATES_SIGN_EXTEND
1593 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1594 is done just by pretending it is already truncated. */
1595 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1597 /* We assume that the store-condition-codes instructions store 0 for false
1598 and some other value for true. This is the value stored for true. */
1600 #define STORE_FLAG_VALUE 1
1602 /* Define the value returned by a floating-point comparison instruction. */
1604 #define FLOAT_STORE_FLAG_VALUE (TARGET_FLOAT_VAX ? 0.5 : 2.0)
1606 /* Canonicalize a comparison from one we don't have to one we do have. */
1608 #define CANONICALIZE_COMPARISON(CODE,OP0,OP1) \
1610 if (((CODE) == GE || (CODE) == GT || (CODE) == GEU || (CODE) == GTU) \
1611 && (GET_CODE (OP1) == REG || (OP1) == const0_rtx)) \
1616 (CODE) = swap_condition (CODE); \
1618 if (((CODE) == LT || (CODE) == LTU) \
1619 && GET_CODE (OP1) == CONST_INT && INTVAL (OP1) == 256) \
1621 (CODE) = (CODE) == LT ? LE : LEU; \
1622 (OP1) = GEN_INT (255); \
1626 /* Specify the machine mode that pointers have.
1627 After generation of rtl, the compiler makes no further distinction
1628 between pointers and any other objects of this machine mode. */
1629 #define Pmode DImode
1631 /* Mode of a function address in a call instruction (for indexing purposes). */
1633 #define FUNCTION_MODE Pmode
1635 /* Define this if addresses of constant functions
1636 shouldn't be put through pseudo regs where they can be cse'd.
1637 Desirable on machines where ordinary constants are expensive
1638 but a CALL with constant address is cheap.
1640 We define this on the Alpha so that gen_call and gen_call_value
1641 get to see the SYMBOL_REF (for the hint field of the jsr). It will
1642 then copy it into a register, thus actually letting the address be
1645 #define NO_FUNCTION_CSE
1647 /* Define this to be nonzero if shift instructions ignore all but the low-order
1649 #define SHIFT_COUNT_TRUNCATED 1
1651 /* Use atexit for static constructors/destructors, instead of defining
1652 our own exit function. */
1655 /* The EV4 is dual issue; EV5/EV6 are quad issue. */
1656 #define ISSUE_RATE (alpha_cpu == PROCESSOR_EV4 ? 2 : 4)
1658 /* Compute the cost of computing a constant rtl expression RTX
1659 whose rtx-code is CODE. The body of this macro is a portion
1660 of a switch statement. If the code is computed here,
1661 return it with a return statement. Otherwise, break from the switch.
1663 If this is an 8-bit constant, return zero since it can be used
1664 nearly anywhere with no cost. If it is a valid operand for an
1665 ADD or AND, likewise return 0 if we know it will be used in that
1666 context. Otherwise, return 2 since it might be used there later.
1667 All other constants take at least two insns. */
1669 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
1671 if (INTVAL (RTX) >= 0 && INTVAL (RTX) < 256) \
1673 case CONST_DOUBLE: \
1674 if ((RTX) == CONST0_RTX (GET_MODE (RTX))) \
1676 else if (((OUTER_CODE) == PLUS && add_operand (RTX, VOIDmode)) \
1677 || ((OUTER_CODE) == AND && and_operand (RTX, VOIDmode))) \
1679 else if (add_operand (RTX, VOIDmode) || and_operand (RTX, VOIDmode)) \
1682 return COSTS_N_INSNS (2); \
1686 switch (alpha_cpu) \
1688 case PROCESSOR_EV4: \
1689 return COSTS_N_INSNS (3); \
1690 case PROCESSOR_EV5: \
1691 case PROCESSOR_EV6: \
1692 return COSTS_N_INSNS (2); \
1696 /* Provide the costs of a rtl expression. This is in the body of a
1699 #define RTX_COSTS(X,CODE,OUTER_CODE) \
1700 case PLUS: case MINUS: \
1701 if (FLOAT_MODE_P (GET_MODE (X))) \
1702 switch (alpha_cpu) \
1704 case PROCESSOR_EV4: \
1705 return COSTS_N_INSNS (6); \
1706 case PROCESSOR_EV5: \
1707 case PROCESSOR_EV6: \
1708 return COSTS_N_INSNS (4); \
1711 else if (GET_CODE (XEXP (X, 0)) == MULT \
1712 && const48_operand (XEXP (XEXP (X, 0), 1), VOIDmode)) \
1713 return (2 + rtx_cost (XEXP (XEXP (X, 0), 0), OUTER_CODE) \
1714 + rtx_cost (XEXP (X, 1), OUTER_CODE)); \
1717 switch (alpha_cpu) \
1719 case PROCESSOR_EV4: \
1720 if (FLOAT_MODE_P (GET_MODE (X))) \
1721 return COSTS_N_INSNS (6); \
1722 return COSTS_N_INSNS (23); \
1723 case PROCESSOR_EV5: \
1724 if (FLOAT_MODE_P (GET_MODE (X))) \
1725 return COSTS_N_INSNS (4); \
1726 else if (GET_MODE (X) == DImode) \
1727 return COSTS_N_INSNS (12); \
1729 return COSTS_N_INSNS (8); \
1730 case PROCESSOR_EV6: \
1731 if (FLOAT_MODE_P (GET_MODE (X))) \
1732 return COSTS_N_INSNS (4); \
1734 return COSTS_N_INSNS (7); \
1738 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
1739 && INTVAL (XEXP (X, 1)) <= 3) \
1741 /* ... fall through ... */ \
1742 case ASHIFTRT: case LSHIFTRT: \
1743 switch (alpha_cpu) \
1745 case PROCESSOR_EV4: \
1746 return COSTS_N_INSNS (2); \
1747 case PROCESSOR_EV5: \
1748 case PROCESSOR_EV6: \
1749 return COSTS_N_INSNS (1); \
1752 case IF_THEN_ELSE: \
1753 switch (alpha_cpu) \
1755 case PROCESSOR_EV4: \
1756 case PROCESSOR_EV6: \
1757 return COSTS_N_INSNS (2); \
1758 case PROCESSOR_EV5: \
1759 return COSTS_N_INSNS (1); \
1762 case DIV: case UDIV: case MOD: case UMOD: \
1763 switch (alpha_cpu) \
1765 case PROCESSOR_EV4: \
1766 if (GET_MODE (X) == SFmode) \
1767 return COSTS_N_INSNS (34); \
1768 else if (GET_MODE (X) == DFmode) \
1769 return COSTS_N_INSNS (63); \
1771 return COSTS_N_INSNS (70); \
1772 case PROCESSOR_EV5: \
1773 if (GET_MODE (X) == SFmode) \
1774 return COSTS_N_INSNS (15); \
1775 else if (GET_MODE (X) == DFmode) \
1776 return COSTS_N_INSNS (22); \
1778 return COSTS_N_INSNS (70); /* ??? */ \
1779 case PROCESSOR_EV6: \
1780 if (GET_MODE (X) == SFmode) \
1781 return COSTS_N_INSNS (12); \
1782 else if (GET_MODE (X) == DFmode) \
1783 return COSTS_N_INSNS (15); \
1785 return COSTS_N_INSNS (70); /* ??? */ \
1789 switch (alpha_cpu) \
1791 case PROCESSOR_EV4: \
1792 case PROCESSOR_EV6: \
1793 return COSTS_N_INSNS (3); \
1794 case PROCESSOR_EV5: \
1795 return COSTS_N_INSNS (2); \
1798 case NEG: case ABS: \
1799 if (! FLOAT_MODE_P (GET_MODE (X))) \
1801 /* ... fall through ... */ \
1802 case FLOAT: case UNSIGNED_FLOAT: case FIX: case UNSIGNED_FIX: \
1803 case FLOAT_EXTEND: case FLOAT_TRUNCATE: \
1804 switch (alpha_cpu) \
1806 case PROCESSOR_EV4: \
1807 return COSTS_N_INSNS (6); \
1808 case PROCESSOR_EV5: \
1809 case PROCESSOR_EV6: \
1810 return COSTS_N_INSNS (4); \
1814 /* Control the assembler format that we output. */
1816 /* We don't emit these labels, so as to avoid getting linker errors about
1817 missing exception handling info. If we emit a gcc_compiled. label into
1818 text, and the file has no code, then the DEC assembler gives us a zero
1819 sized text section with no associated exception handling info. The
1820 DEC linker sees this text section, and gives a warning saying saying that
1821 the exception handling info is missing. */
1822 #define ASM_IDENTIFY_GCC
1823 #define ASM_IDENTIFY_LANGUAGE
1825 /* Output to assembler file text saying following lines
1826 may contain character constants, extra white space, comments, etc. */
1828 #define ASM_APP_ON ""
1830 /* Output to assembler file text saying following lines
1831 no longer contain unusual constructs. */
1833 #define ASM_APP_OFF ""
1835 #define TEXT_SECTION_ASM_OP ".text"
1837 /* Output before read-only data. */
1839 #define READONLY_DATA_SECTION_ASM_OP ".rdata"
1841 /* Output before writable data. */
1843 #define DATA_SECTION_ASM_OP ".data"
1845 /* Define an extra section for read-only data, a routine to enter it, and
1846 indicate that it is for read-only data.
1848 The first time we enter the readonly data section for a file, we write
1849 eight bytes of zero. This works around a bug in DEC's assembler in
1850 some versions of OSF/1 V3.x. */
1852 #define EXTRA_SECTIONS readonly_data
1854 #define EXTRA_SECTION_FUNCTIONS \
1856 literal_section () \
1858 if (in_section != readonly_data) \
1860 static int firsttime = 1; \
1862 fprintf (asm_out_file, "%s\n", READONLY_DATA_SECTION_ASM_OP); \
1866 ASM_OUTPUT_DOUBLE_INT (asm_out_file, const0_rtx); \
1869 in_section = readonly_data; \
1873 #define READONLY_DATA_SECTION literal_section
1875 /* If we are referencing a function that is static, make the SYMBOL_REF
1876 special. We use this to see indicate we can branch to this function
1877 without setting PV or restoring GP. */
1879 #define ENCODE_SECTION_INFO(DECL) \
1880 if (TREE_CODE (DECL) == FUNCTION_DECL && ! TREE_PUBLIC (DECL)) \
1881 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1;
1883 /* How to refer to registers in assembler output.
1884 This sequence is indexed by compiler's hard-register-number (see above). */
1886 #define REGISTER_NAMES \
1887 {"$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8", \
1888 "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
1889 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
1890 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "AP", \
1891 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", "$f8", \
1892 "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
1893 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",\
1894 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "FP"}
1896 /* How to renumber registers for dbx and gdb. */
1898 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
1900 /* This is how to output the definition of a user-level label named NAME,
1901 such as the label on a static function or variable NAME. */
1903 #define ASM_OUTPUT_LABEL(FILE,NAME) \
1904 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
1906 /* This is how to output a command to make the user-level label named NAME
1907 defined for reference from other files. */
1909 #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
1910 do { fputs ("\t.globl ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
1912 /* The prefix to add to user-visible assembler symbols. */
1914 #define USER_LABEL_PREFIX ""
1916 /* This is how to output an internal numbered label where
1917 PREFIX is the class of label and NUM is the number within the class. */
1919 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1920 fprintf (FILE, "$%s%d:\n", PREFIX, NUM)
1922 /* This is how to output a label for a jump table. Arguments are the same as
1923 for ASM_OUTPUT_INTERNAL_LABEL, except the insn for the jump table is
1926 #define ASM_OUTPUT_CASE_LABEL(FILE,PREFIX,NUM,TABLEINSN) \
1927 { ASM_OUTPUT_ALIGN (FILE, 2); ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); }
1929 /* This is how to store into the string LABEL
1930 the symbol_ref name of an internal numbered label where
1931 PREFIX is the class of label and NUM is the number within the class.
1932 This is suitable for output with `assemble_name'. */
1934 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1935 sprintf (LABEL, "*$%s%d", PREFIX, NUM)
1937 /* Check a floating-point value for validity for a particular machine mode. */
1939 #define CHECK_FLOAT_VALUE(MODE, D, OVERFLOW) \
1940 ((OVERFLOW) = check_float_value (MODE, &D, OVERFLOW))
1942 /* This is how to output an assembler line defining a `double' constant. */
1944 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
1946 if (REAL_VALUE_ISINF (VALUE) \
1947 || REAL_VALUE_ISNAN (VALUE) \
1948 || REAL_VALUE_MINUS_ZERO (VALUE)) \
1951 REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t); \
1952 fprintf (FILE, "\t.quad 0x%lx%08lx\n", \
1953 t[1] & 0xffffffff, t[0] & 0xffffffff); \
1958 REAL_VALUE_TO_DECIMAL (VALUE, "%.20e", str); \
1959 fprintf (FILE, "\t.%c_floating %s\n", (TARGET_FLOAT_VAX)?'g':'t', str); \
1963 /* This is how to output an assembler line defining a `float' constant. */
1965 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
1968 REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t); \
1969 fprintf (FILE, "\t.long 0x%lx\n", t & 0xffffffff); \
1972 /* This is how to output an assembler line defining an `int' constant. */
1974 #define ASM_OUTPUT_INT(FILE,VALUE) \
1975 ( fprintf (FILE, "\t.long "), \
1976 output_addr_const (FILE, (VALUE)), \
1977 fprintf (FILE, "\n"))
1979 /* This is how to output an assembler line defining a `long' constant. */
1981 #define ASM_OUTPUT_DOUBLE_INT(FILE,VALUE) \
1982 ( fprintf (FILE, "\t.quad "), \
1983 output_addr_const (FILE, (VALUE)), \
1984 fprintf (FILE, "\n"))
1986 /* Likewise for `char' and `short' constants. */
1988 #define ASM_OUTPUT_SHORT(FILE,VALUE) \
1989 fprintf (FILE, "\t.word %d\n", \
1990 (GET_CODE (VALUE) == CONST_INT \
1991 ? INTVAL (VALUE) & 0xffff : (abort (), 0)))
1993 #define ASM_OUTPUT_CHAR(FILE,VALUE) \
1994 fprintf (FILE, "\t.byte %d\n", \
1995 (GET_CODE (VALUE) == CONST_INT \
1996 ? INTVAL (VALUE) & 0xff : (abort (), 0)))
1998 /* We use the default ASCII-output routine, except that we don't write more
1999 than 50 characters since the assembler doesn't support very long lines. */
2001 #define ASM_OUTPUT_ASCII(MYFILE, MYSTRING, MYLENGTH) \
2003 FILE *_hide_asm_out_file = (MYFILE); \
2004 unsigned char *_hide_p = (unsigned char *) (MYSTRING); \
2005 int _hide_thissize = (MYLENGTH); \
2006 int _size_so_far = 0; \
2008 FILE *asm_out_file = _hide_asm_out_file; \
2009 unsigned char *p = _hide_p; \
2010 int thissize = _hide_thissize; \
2012 fprintf (asm_out_file, "\t.ascii \""); \
2014 for (i = 0; i < thissize; i++) \
2016 register int c = p[i]; \
2018 if (_size_so_far ++ > 50 && i < thissize - 4) \
2019 _size_so_far = 0, fprintf (asm_out_file, "\"\n\t.ascii \""); \
2021 if (c == '\"' || c == '\\') \
2022 putc ('\\', asm_out_file); \
2023 if (c >= ' ' && c < 0177) \
2024 putc (c, asm_out_file); \
2027 fprintf (asm_out_file, "\\%o", c); \
2028 /* After an octal-escape, if a digit follows, \
2029 terminate one string constant and start another. \
2030 The Vax assembler fails to stop reading the escape \
2031 after three digits, so this is the only way we \
2032 can get it to parse the data properly. */ \
2033 if (i < thissize - 1 \
2034 && p[i + 1] >= '0' && p[i + 1] <= '9') \
2035 _size_so_far = 0, fprintf (asm_out_file, "\"\n\t.ascii \""); \
2038 fprintf (asm_out_file, "\"\n"); \
2043 /* This is how to output an insn to push a register on the stack.
2044 It need not be very fast code. */
2046 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
2047 fprintf (FILE, "\tsubq $30,8,$30\n\tst%s $%s%d,0($30)\n", \
2048 (REGNO) > 32 ? "t" : "q", (REGNO) > 32 ? "f" : "", \
2051 /* This is how to output an insn to pop a register from the stack.
2052 It need not be very fast code. */
2054 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
2055 fprintf (FILE, "\tld%s $%s%d,0($30)\n\taddq $30,8,$30\n", \
2056 (REGNO) > 32 ? "t" : "q", (REGNO) > 32 ? "f" : "", \
2059 /* This is how to output an assembler line for a numeric constant byte. */
2061 #define ASM_OUTPUT_BYTE(FILE,VALUE) \
2062 fprintf (FILE, "\t.byte 0x%x\n", (VALUE) & 0xff)
2064 /* This is how to output an element of a case-vector that is absolute.
2065 (Alpha does not use such vectors, but we must define this macro anyway.) */
2067 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) abort ()
2069 /* This is how to output an element of a case-vector that is relative. */
2071 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2072 fprintf (FILE, "\t.%s $L%d\n", TARGET_WINDOWS_NT ? "long" : "gprel32", \
2075 /* This is how to output an assembler line
2076 that says to advance the location counter
2077 to a multiple of 2**LOG bytes. */
2079 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2081 fprintf (FILE, "\t.align %d\n", LOG);
2083 /* This is how to advance the location counter by SIZE bytes. */
2085 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
2086 fprintf (FILE, "\t.space %d\n", (SIZE))
2088 /* This says how to output an assembler line
2089 to define a global common symbol. */
2091 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
2092 ( fputs ("\t.comm ", (FILE)), \
2093 assemble_name ((FILE), (NAME)), \
2094 fprintf ((FILE), ",%d\n", (SIZE)))
2096 /* This says how to output an assembler line
2097 to define a local common symbol. */
2099 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE,ROUNDED) \
2100 ( fputs ("\t.lcomm ", (FILE)), \
2101 assemble_name ((FILE), (NAME)), \
2102 fprintf ((FILE), ",%d\n", (SIZE)))
2104 /* Store in OUTPUT a string (made with alloca) containing
2105 an assembler-name for a local static variable named NAME.
2106 LABELNO is an integer which is different for each call. */
2108 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
2109 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
2110 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
2112 /* Define the parentheses used to group arithmetic operations
2113 in assembler code. */
2115 #define ASM_OPEN_PAREN "("
2116 #define ASM_CLOSE_PAREN ")"
2118 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
2119 Used for C++ multiple inheritance. */
2121 #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \
2123 char *fn_name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (FUNCTION)); \
2125 fprintf (FILE, "\t.ent "); \
2126 assemble_name (FILE, alpha_function_name); \
2127 fputc ('\n', FILE); \
2128 ASM_OUTPUT_LABEL (FILE, alpha_function_name); \
2129 fprintf (FILE, "\tldgp $29,0($27)\n"); \
2130 fputc ('$', FILE); \
2131 assemble_name (FILE, alpha_function_name); \
2132 fprintf (FILE, "..ng:\n"); \
2133 fprintf (FILE, "\t.frame $30,0,$26,0\n"); \
2134 fprintf (FILE, "\t.prologue 1\n"); \
2136 /* Rely on the assembler to macro expand a large delta. */ \
2137 fprintf (FILE, "\tlda $16,%ld($16)\n", (long)(DELTA)); \
2139 if (current_file_function_operand (XEXP (DECL_RTL (FUNCTION), 0))) \
2141 fprintf (FILE, "\tbr $31,$"); \
2142 assemble_name (FILE, fn_name); \
2143 fprintf (FILE, "..ng\n"); \
2147 fprintf (FILE, "\tlda $27,"); \
2148 assemble_name (FILE, fn_name); \
2149 fprintf (FILE, "\n\tjmp $31,($27),"); \
2150 assemble_name (FILE, fn_name); \
2151 fputc ('\n', FILE); \
2154 fprintf (FILE, "\t.end "); \
2155 assemble_name (FILE, alpha_function_name); \
2156 fputc ('\n', FILE); \
2160 /* Define results of standard character escape sequences. */
2161 #define TARGET_BELL 007
2162 #define TARGET_BS 010
2163 #define TARGET_TAB 011
2164 #define TARGET_NEWLINE 012
2165 #define TARGET_VT 013
2166 #define TARGET_FF 014
2167 #define TARGET_CR 015
2169 /* Print operand X (an rtx) in assembler syntax to file FILE.
2170 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2171 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2173 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2175 /* Determine which codes are valid without a following integer. These must
2176 not be alphabetic (the characters are chosen so that
2177 PRINT_OPERAND_PUNCT_VALID_P translates into a simple range change when
2180 & Generates fp-rounding mode suffix: nothing for normal, 'c' for
2181 chopped, 'm' for minus-infinity, and 'd' for dynamic rounding
2182 mode. alpha_fprm controls which suffix is generated.
2184 ' Generates trap-mode suffix for instructions that accept the
2185 su suffix only (cmpt et al).
2187 ( Generates trap-mode suffix for instructions that accept the
2188 v, sv, and svi suffix. The only instruction that needs this
2191 ) Generates trap-mode suffix for instructions that accept the
2192 u, su, and sui suffix. This is the bulk of the IEEE floating
2193 point instructions (addt et al).
2195 + Generates trap-mode suffix for instructions that accept the
2196 sui suffix (cvtqt and cvtqs).
2198 , Generates single precision suffix for floating point
2199 instructions (s for IEEE, f for VAX)
2201 - Generates double precision suffix for floating point
2202 instructions (t for IEEE, g for VAX)
2205 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2206 ((CODE) == '&' || (CODE) == '\'' || (CODE) == '(' || (CODE) == ')' \
2207 || (CODE) == '+' || (CODE) == ',' || (CODE) == '-')
2209 /* Print a memory address as an operand to reference that memory location. */
2211 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2212 { rtx addr = (ADDR); \
2214 HOST_WIDE_INT offset = 0; \
2216 if (GET_CODE (addr) == AND) \
2217 addr = XEXP (addr, 0); \
2219 if (GET_CODE (addr) == REG) \
2220 basereg = REGNO (addr); \
2221 else if (GET_CODE (addr) == CONST_INT) \
2222 offset = INTVAL (addr); \
2223 else if (GET_CODE (addr) == PLUS \
2224 && GET_CODE (XEXP (addr, 0)) == REG \
2225 && GET_CODE (XEXP (addr, 1)) == CONST_INT) \
2226 basereg = REGNO (XEXP (addr, 0)), offset = INTVAL (XEXP (addr, 1)); \
2230 fprintf (FILE, "%d($%d)", offset, basereg); \
2232 /* Define the codes that are matched by predicates in alpha.c. */
2234 #define PREDICATE_CODES \
2235 {"reg_or_0_operand", {SUBREG, REG, CONST_INT}}, \
2236 {"reg_or_6bit_operand", {SUBREG, REG, CONST_INT}}, \
2237 {"reg_or_8bit_operand", {SUBREG, REG, CONST_INT}}, \
2238 {"cint8_operand", {CONST_INT}}, \
2239 {"reg_or_cint_operand", {SUBREG, REG, CONST_INT}}, \
2240 {"add_operand", {SUBREG, REG, CONST_INT}}, \
2241 {"sext_add_operand", {SUBREG, REG, CONST_INT}}, \
2242 {"const48_operand", {CONST_INT}}, \
2243 {"and_operand", {SUBREG, REG, CONST_INT}}, \
2244 {"or_operand", {SUBREG, REG, CONST_INT}}, \
2245 {"mode_mask_operand", {CONST_INT}}, \
2246 {"mul8_operand", {CONST_INT}}, \
2247 {"mode_width_operand", {CONST_INT}}, \
2248 {"reg_or_fp0_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2249 {"alpha_comparison_operator", {EQ, LE, LT, LEU, LTU}}, \
2250 {"alpha_swapped_comparison_operator", {EQ, GE, GT, GEU, GTU}}, \
2251 {"signed_comparison_operator", {EQ, NE, LE, LT, GE, GT}}, \
2252 {"divmod_operator", {DIV, MOD, UDIV, UMOD}}, \
2253 {"fp0_operand", {CONST_DOUBLE}}, \
2254 {"current_file_function_operand", {SYMBOL_REF}}, \
2255 {"call_operand", {REG, SYMBOL_REF}}, \
2256 {"input_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE, \
2257 SYMBOL_REF, CONST, LABEL_REF}}, \
2258 {"some_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE, \
2259 SYMBOL_REF, CONST, LABEL_REF}}, \
2260 {"aligned_memory_operand", {MEM}}, \
2261 {"unaligned_memory_operand", {MEM}}, \
2262 {"reg_or_unaligned_mem_operand", {SUBREG, REG, MEM}}, \
2263 {"any_memory_operand", {MEM}}, \
2264 {"hard_fp_register_operand", {SUBREG, REG}},
2266 /* Tell collect that the object format is ECOFF. */
2267 #define OBJECT_FORMAT_COFF
2268 #define EXTENDED_COFF
2270 /* If we use NM, pass -g to it so it only lists globals. */
2271 #define NM_FLAGS "-pg"
2273 /* Definitions for debugging. */
2275 #define SDB_DEBUGGING_INFO /* generate info for mips-tfile */
2276 #define DBX_DEBUGGING_INFO /* generate embedded stabs */
2277 #define MIPS_DEBUGGING_INFO /* MIPS specific debugging info */
2279 #ifndef PREFERRED_DEBUGGING_TYPE /* assume SDB_DEBUGGING_INFO */
2280 #define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
2284 /* Correct the offset of automatic variables and arguments. Note that
2285 the Alpha debug format wants all automatic variables and arguments
2286 to be in terms of two different offsets from the virtual frame pointer,
2287 which is the stack pointer before any adjustment in the function.
2288 The offset for the argument pointer is fixed for the native compiler,
2289 it is either zero (for the no arguments case) or large enough to hold
2290 all argument registers.
2291 The offset for the auto pointer is the fourth argument to the .frame
2292 directive (local_offset).
2293 To stay compatible with the native tools we use the same offsets
2294 from the virtual frame pointer and adjust the debugger arg/auto offsets
2295 accordingly. These debugger offsets are set up in output_prolog. */
2297 extern long alpha_arg_offset;
2298 extern long alpha_auto_offset;
2299 #define DEBUGGER_AUTO_OFFSET(X) \
2300 ((GET_CODE (X) == PLUS ? INTVAL (XEXP (X, 1)) : 0) + alpha_auto_offset)
2301 #define DEBUGGER_ARG_OFFSET(OFFSET, X) (OFFSET + alpha_arg_offset)
2304 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE) \
2305 alpha_output_lineno (STREAM, LINE)
2306 extern void alpha_output_lineno ();
2308 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
2309 alpha_output_filename (STREAM, NAME)
2310 extern void alpha_output_filename ();
2312 /* mips-tfile.c limits us to strings of one page. */
2313 #define DBX_CONTIN_LENGTH 4000
2315 /* By default, turn on GDB extensions. */
2316 #define DEFAULT_GDB_EXTENSIONS 1
2318 /* Stabs-in-ECOFF can't handle dbxout_function_end(). */
2319 #define NO_DBX_FUNCTION_END 1
2321 /* If we are smuggling stabs through the ALPHA ECOFF object
2322 format, put a comment in front of the .stab<x> operation so
2323 that the ALPHA assembler does not choke. The mips-tfile program
2324 will correctly put the stab into the object file. */
2326 #define ASM_STABS_OP ((TARGET_GAS) ? ".stabs" : " #.stabs")
2327 #define ASM_STABN_OP ((TARGET_GAS) ? ".stabn" : " #.stabn")
2328 #define ASM_STABD_OP ((TARGET_GAS) ? ".stabd" : " #.stabd")
2330 /* Forward references to tags are allowed. */
2331 #define SDB_ALLOW_FORWARD_REFERENCES
2333 /* Unknown tags are also allowed. */
2334 #define SDB_ALLOW_UNKNOWN_REFERENCES
2336 #define PUT_SDB_DEF(a) \
2338 fprintf (asm_out_file, "\t%s.def\t", \
2339 (TARGET_GAS) ? "" : "#"); \
2340 ASM_OUTPUT_LABELREF (asm_out_file, a); \
2341 fputc (';', asm_out_file); \
2344 #define PUT_SDB_PLAIN_DEF(a) \
2346 fprintf (asm_out_file, "\t%s.def\t.%s;", \
2347 (TARGET_GAS) ? "" : "#", (a)); \
2350 #define PUT_SDB_TYPE(a) \
2352 fprintf (asm_out_file, "\t.type\t0x%x;", (a)); \
2355 /* For block start and end, we create labels, so that
2356 later we can figure out where the correct offset is.
2357 The normal .ent/.end serve well enough for functions,
2358 so those are just commented out. */
2360 extern int sdb_label_count; /* block start/end next label # */
2362 #define PUT_SDB_BLOCK_START(LINE) \
2364 fprintf (asm_out_file, \
2365 "$Lb%d:\n\t%s.begin\t$Lb%d\t%d\n", \
2367 (TARGET_GAS) ? "" : "#", \
2370 sdb_label_count++; \
2373 #define PUT_SDB_BLOCK_END(LINE) \
2375 fprintf (asm_out_file, \
2376 "$Le%d:\n\t%s.bend\t$Le%d\t%d\n", \
2378 (TARGET_GAS) ? "" : "#", \
2381 sdb_label_count++; \
2384 #define PUT_SDB_FUNCTION_START(LINE)
2386 #define PUT_SDB_FUNCTION_END(LINE)
2388 #define PUT_SDB_EPILOGUE_END(NAME)
2390 /* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for
2391 mips-tdump.c to print them out.
2393 These must match the corresponding definitions in gdb/mipsread.c.
2394 Unfortunately, gcc and gdb do not currently share any directories. */
2396 #define CODE_MASK 0x8F300
2397 #define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
2398 #define MIPS_MARK_STAB(code) ((code)+CODE_MASK)
2399 #define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK)
2401 /* Override some mips-tfile definitions. */
2403 #define SHASH_SIZE 511
2404 #define THASH_SIZE 55
2406 /* Align ecoff symbol tables to avoid OSF1/1.3 nm complaints. */
2408 #define ALIGN_SYMTABLE_OFFSET(OFFSET) (((OFFSET) + 7) & ~7)
2410 /* The linker will stick __main into the .init section. */
2411 #define HAS_INIT_SECTION
2412 #define LD_INIT_SWITCH "-init"
2413 #define LD_FINI_SWITCH "-fini"
2415 /* The system headers under Alpha systems are generally C++-aware. */
2416 #define NO_IMPLICIT_EXTERN_C
2418 /* Prototypes for alpha.c functions used in the md file. */
2419 extern struct rtx_def *get_unaligned_address ();
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