1 /* Subroutines used for code generation on the DEC Alpha.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
5 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
26 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
47 #include "integrate.h"
50 #include "target-def.h"
52 #include "langhooks.h"
53 #include <splay-tree.h>
54 #include "cfglayout.h"
56 #include "tree-flow.h"
57 #include "tree-stdarg.h"
58 #include "tm-constrs.h"
62 /* Specify which cpu to schedule for. */
63 enum processor_type alpha_tune;
65 /* Which cpu we're generating code for. */
66 enum processor_type alpha_cpu;
68 static const char * const alpha_cpu_name[] =
73 /* Specify how accurate floating-point traps need to be. */
75 enum alpha_trap_precision alpha_tp;
77 /* Specify the floating-point rounding mode. */
79 enum alpha_fp_rounding_mode alpha_fprm;
81 /* Specify which things cause traps. */
83 enum alpha_fp_trap_mode alpha_fptm;
85 /* Nonzero if inside of a function, because the Alpha asm can't
86 handle .files inside of functions. */
88 static int inside_function = FALSE;
90 /* The number of cycles of latency we should assume on memory reads. */
92 int alpha_memory_latency = 3;
94 /* Whether the function needs the GP. */
96 static int alpha_function_needs_gp;
98 /* The alias set for prologue/epilogue register save/restore. */
100 static GTY(()) alias_set_type alpha_sr_alias_set;
102 /* The assembler name of the current function. */
104 static const char *alpha_fnname;
106 /* The next explicit relocation sequence number. */
107 extern GTY(()) int alpha_next_sequence_number;
108 int alpha_next_sequence_number = 1;
110 /* The literal and gpdisp sequence numbers for this insn, as printed
111 by %# and %* respectively. */
112 extern GTY(()) int alpha_this_literal_sequence_number;
113 extern GTY(()) int alpha_this_gpdisp_sequence_number;
114 int alpha_this_literal_sequence_number;
115 int alpha_this_gpdisp_sequence_number;
117 /* Costs of various operations on the different architectures. */
119 struct alpha_rtx_cost_data
121 unsigned char fp_add;
122 unsigned char fp_mult;
123 unsigned char fp_div_sf;
124 unsigned char fp_div_df;
125 unsigned char int_mult_si;
126 unsigned char int_mult_di;
127 unsigned char int_shift;
128 unsigned char int_cmov;
129 unsigned short int_div;
132 static struct alpha_rtx_cost_data const alpha_rtx_cost_data[PROCESSOR_MAX] =
135 COSTS_N_INSNS (6), /* fp_add */
136 COSTS_N_INSNS (6), /* fp_mult */
137 COSTS_N_INSNS (34), /* fp_div_sf */
138 COSTS_N_INSNS (63), /* fp_div_df */
139 COSTS_N_INSNS (23), /* int_mult_si */
140 COSTS_N_INSNS (23), /* int_mult_di */
141 COSTS_N_INSNS (2), /* int_shift */
142 COSTS_N_INSNS (2), /* int_cmov */
143 COSTS_N_INSNS (97), /* int_div */
146 COSTS_N_INSNS (4), /* fp_add */
147 COSTS_N_INSNS (4), /* fp_mult */
148 COSTS_N_INSNS (15), /* fp_div_sf */
149 COSTS_N_INSNS (22), /* fp_div_df */
150 COSTS_N_INSNS (8), /* int_mult_si */
151 COSTS_N_INSNS (12), /* int_mult_di */
152 COSTS_N_INSNS (1) + 1, /* int_shift */
153 COSTS_N_INSNS (1), /* int_cmov */
154 COSTS_N_INSNS (83), /* int_div */
157 COSTS_N_INSNS (4), /* fp_add */
158 COSTS_N_INSNS (4), /* fp_mult */
159 COSTS_N_INSNS (12), /* fp_div_sf */
160 COSTS_N_INSNS (15), /* fp_div_df */
161 COSTS_N_INSNS (7), /* int_mult_si */
162 COSTS_N_INSNS (7), /* int_mult_di */
163 COSTS_N_INSNS (1), /* int_shift */
164 COSTS_N_INSNS (2), /* int_cmov */
165 COSTS_N_INSNS (86), /* int_div */
169 /* Similar but tuned for code size instead of execution latency. The
170 extra +N is fractional cost tuning based on latency. It's used to
171 encourage use of cheaper insns like shift, but only if there's just
174 static struct alpha_rtx_cost_data const alpha_rtx_cost_size =
176 COSTS_N_INSNS (1), /* fp_add */
177 COSTS_N_INSNS (1), /* fp_mult */
178 COSTS_N_INSNS (1), /* fp_div_sf */
179 COSTS_N_INSNS (1) + 1, /* fp_div_df */
180 COSTS_N_INSNS (1) + 1, /* int_mult_si */
181 COSTS_N_INSNS (1) + 2, /* int_mult_di */
182 COSTS_N_INSNS (1), /* int_shift */
183 COSTS_N_INSNS (1), /* int_cmov */
184 COSTS_N_INSNS (6), /* int_div */
187 /* Get the number of args of a function in one of two ways. */
188 #if TARGET_ABI_OPEN_VMS || TARGET_ABI_UNICOSMK
189 #define NUM_ARGS crtl->args.info.num_args
191 #define NUM_ARGS crtl->args.info
197 /* Declarations of static functions. */
198 static struct machine_function *alpha_init_machine_status (void);
199 static rtx alpha_emit_xfloating_compare (enum rtx_code *, rtx, rtx);
201 #if TARGET_ABI_OPEN_VMS
202 static void alpha_write_linkage (FILE *, const char *, tree);
203 static bool vms_valid_pointer_mode (enum machine_mode);
206 static void unicosmk_output_deferred_case_vectors (FILE *);
207 static void unicosmk_gen_dsib (unsigned long *);
208 static void unicosmk_output_ssib (FILE *, const char *);
209 static int unicosmk_need_dex (rtx);
211 /* Implement TARGET_HANDLE_OPTION. */
214 alpha_handle_option (size_t code, const char *arg, int value)
220 target_flags |= MASK_SOFT_FP;
224 case OPT_mieee_with_inexact:
225 target_flags |= MASK_IEEE_CONFORMANT;
229 if (value != 16 && value != 32 && value != 64)
230 error ("bad value %qs for -mtls-size switch", arg);
237 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
238 /* Implement TARGET_MANGLE_TYPE. */
241 alpha_mangle_type (const_tree type)
243 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
244 && TARGET_LONG_DOUBLE_128)
247 /* For all other types, use normal C++ mangling. */
252 /* Parse target option strings. */
255 override_options (void)
257 static const struct cpu_table {
258 const char *const name;
259 const enum processor_type processor;
262 { "ev4", PROCESSOR_EV4, 0 },
263 { "ev45", PROCESSOR_EV4, 0 },
264 { "21064", PROCESSOR_EV4, 0 },
265 { "ev5", PROCESSOR_EV5, 0 },
266 { "21164", PROCESSOR_EV5, 0 },
267 { "ev56", PROCESSOR_EV5, MASK_BWX },
268 { "21164a", PROCESSOR_EV5, MASK_BWX },
269 { "pca56", PROCESSOR_EV5, MASK_BWX|MASK_MAX },
270 { "21164PC",PROCESSOR_EV5, MASK_BWX|MASK_MAX },
271 { "21164pc",PROCESSOR_EV5, MASK_BWX|MASK_MAX },
272 { "ev6", PROCESSOR_EV6, MASK_BWX|MASK_MAX|MASK_FIX },
273 { "21264", PROCESSOR_EV6, MASK_BWX|MASK_MAX|MASK_FIX },
274 { "ev67", PROCESSOR_EV6, MASK_BWX|MASK_MAX|MASK_FIX|MASK_CIX },
275 { "21264a", PROCESSOR_EV6, MASK_BWX|MASK_MAX|MASK_FIX|MASK_CIX }
278 int const ct_size = ARRAY_SIZE (cpu_table);
281 /* Unicos/Mk doesn't have shared libraries. */
282 if (TARGET_ABI_UNICOSMK && flag_pic)
284 warning (0, "-f%s ignored for Unicos/Mk (not supported)",
285 (flag_pic > 1) ? "PIC" : "pic");
289 /* On Unicos/Mk, the native compiler consistently generates /d suffices for
290 floating-point instructions. Make that the default for this target. */
291 if (TARGET_ABI_UNICOSMK)
292 alpha_fprm = ALPHA_FPRM_DYN;
294 alpha_fprm = ALPHA_FPRM_NORM;
296 alpha_tp = ALPHA_TP_PROG;
297 alpha_fptm = ALPHA_FPTM_N;
299 /* We cannot use su and sui qualifiers for conversion instructions on
300 Unicos/Mk. I'm not sure if this is due to assembler or hardware
301 limitations. Right now, we issue a warning if -mieee is specified
302 and then ignore it; eventually, we should either get it right or
303 disable the option altogether. */
307 if (TARGET_ABI_UNICOSMK)
308 warning (0, "-mieee not supported on Unicos/Mk");
311 alpha_tp = ALPHA_TP_INSN;
312 alpha_fptm = ALPHA_FPTM_SU;
316 if (TARGET_IEEE_WITH_INEXACT)
318 if (TARGET_ABI_UNICOSMK)
319 warning (0, "-mieee-with-inexact not supported on Unicos/Mk");
322 alpha_tp = ALPHA_TP_INSN;
323 alpha_fptm = ALPHA_FPTM_SUI;
329 if (! strcmp (alpha_tp_string, "p"))
330 alpha_tp = ALPHA_TP_PROG;
331 else if (! strcmp (alpha_tp_string, "f"))
332 alpha_tp = ALPHA_TP_FUNC;
333 else if (! strcmp (alpha_tp_string, "i"))
334 alpha_tp = ALPHA_TP_INSN;
336 error ("bad value %qs for -mtrap-precision switch", alpha_tp_string);
339 if (alpha_fprm_string)
341 if (! strcmp (alpha_fprm_string, "n"))
342 alpha_fprm = ALPHA_FPRM_NORM;
343 else if (! strcmp (alpha_fprm_string, "m"))
344 alpha_fprm = ALPHA_FPRM_MINF;
345 else if (! strcmp (alpha_fprm_string, "c"))
346 alpha_fprm = ALPHA_FPRM_CHOP;
347 else if (! strcmp (alpha_fprm_string,"d"))
348 alpha_fprm = ALPHA_FPRM_DYN;
350 error ("bad value %qs for -mfp-rounding-mode switch",
354 if (alpha_fptm_string)
356 if (strcmp (alpha_fptm_string, "n") == 0)
357 alpha_fptm = ALPHA_FPTM_N;
358 else if (strcmp (alpha_fptm_string, "u") == 0)
359 alpha_fptm = ALPHA_FPTM_U;
360 else if (strcmp (alpha_fptm_string, "su") == 0)
361 alpha_fptm = ALPHA_FPTM_SU;
362 else if (strcmp (alpha_fptm_string, "sui") == 0)
363 alpha_fptm = ALPHA_FPTM_SUI;
365 error ("bad value %qs for -mfp-trap-mode switch", alpha_fptm_string);
368 if (alpha_cpu_string)
370 for (i = 0; i < ct_size; i++)
371 if (! strcmp (alpha_cpu_string, cpu_table [i].name))
373 alpha_tune = alpha_cpu = cpu_table [i].processor;
374 target_flags &= ~ (MASK_BWX | MASK_MAX | MASK_FIX | MASK_CIX);
375 target_flags |= cpu_table [i].flags;
379 error ("bad value %qs for -mcpu switch", alpha_cpu_string);
382 if (alpha_tune_string)
384 for (i = 0; i < ct_size; i++)
385 if (! strcmp (alpha_tune_string, cpu_table [i].name))
387 alpha_tune = cpu_table [i].processor;
391 error ("bad value %qs for -mcpu switch", alpha_tune_string);
394 /* Do some sanity checks on the above options. */
396 if (TARGET_ABI_UNICOSMK && alpha_fptm != ALPHA_FPTM_N)
398 warning (0, "trap mode not supported on Unicos/Mk");
399 alpha_fptm = ALPHA_FPTM_N;
402 if ((alpha_fptm == ALPHA_FPTM_SU || alpha_fptm == ALPHA_FPTM_SUI)
403 && alpha_tp != ALPHA_TP_INSN && alpha_cpu != PROCESSOR_EV6)
405 warning (0, "fp software completion requires -mtrap-precision=i");
406 alpha_tp = ALPHA_TP_INSN;
409 if (alpha_cpu == PROCESSOR_EV6)
411 /* Except for EV6 pass 1 (not released), we always have precise
412 arithmetic traps. Which means we can do software completion
413 without minding trap shadows. */
414 alpha_tp = ALPHA_TP_PROG;
417 if (TARGET_FLOAT_VAX)
419 if (alpha_fprm == ALPHA_FPRM_MINF || alpha_fprm == ALPHA_FPRM_DYN)
421 warning (0, "rounding mode not supported for VAX floats");
422 alpha_fprm = ALPHA_FPRM_NORM;
424 if (alpha_fptm == ALPHA_FPTM_SUI)
426 warning (0, "trap mode not supported for VAX floats");
427 alpha_fptm = ALPHA_FPTM_SU;
429 if (target_flags_explicit & MASK_LONG_DOUBLE_128)
430 warning (0, "128-bit long double not supported for VAX floats");
431 target_flags &= ~MASK_LONG_DOUBLE_128;
438 if (!alpha_mlat_string)
439 alpha_mlat_string = "L1";
441 if (ISDIGIT ((unsigned char)alpha_mlat_string[0])
442 && (lat = strtol (alpha_mlat_string, &end, 10), *end == '\0'))
444 else if ((alpha_mlat_string[0] == 'L' || alpha_mlat_string[0] == 'l')
445 && ISDIGIT ((unsigned char)alpha_mlat_string[1])
446 && alpha_mlat_string[2] == '\0')
448 static int const cache_latency[][4] =
450 { 3, 30, -1 }, /* ev4 -- Bcache is a guess */
451 { 2, 12, 38 }, /* ev5 -- Bcache from PC164 LMbench numbers */
452 { 3, 12, 30 }, /* ev6 -- Bcache from DS20 LMbench. */
455 lat = alpha_mlat_string[1] - '0';
456 if (lat <= 0 || lat > 3 || cache_latency[alpha_tune][lat-1] == -1)
458 warning (0, "L%d cache latency unknown for %s",
459 lat, alpha_cpu_name[alpha_tune]);
463 lat = cache_latency[alpha_tune][lat-1];
465 else if (! strcmp (alpha_mlat_string, "main"))
467 /* Most current memories have about 370ns latency. This is
468 a reasonable guess for a fast cpu. */
473 warning (0, "bad value %qs for -mmemory-latency", alpha_mlat_string);
477 alpha_memory_latency = lat;
480 /* Default the definition of "small data" to 8 bytes. */
484 /* Infer TARGET_SMALL_DATA from -fpic/-fPIC. */
486 target_flags |= MASK_SMALL_DATA;
487 else if (flag_pic == 2)
488 target_flags &= ~MASK_SMALL_DATA;
490 /* Align labels and loops for optimal branching. */
491 /* ??? Kludge these by not doing anything if we don't optimize and also if
492 we are writing ECOFF symbols to work around a bug in DEC's assembler. */
493 if (optimize > 0 && write_symbols != SDB_DEBUG)
495 if (align_loops <= 0)
497 if (align_jumps <= 0)
500 if (align_functions <= 0)
501 align_functions = 16;
503 /* Acquire a unique set number for our register saves and restores. */
504 alpha_sr_alias_set = new_alias_set ();
506 /* Register variables and functions with the garbage collector. */
508 /* Set up function hooks. */
509 init_machine_status = alpha_init_machine_status;
511 /* Tell the compiler when we're using VAX floating point. */
512 if (TARGET_FLOAT_VAX)
514 REAL_MODE_FORMAT (SFmode) = &vax_f_format;
515 REAL_MODE_FORMAT (DFmode) = &vax_g_format;
516 REAL_MODE_FORMAT (TFmode) = NULL;
519 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
520 if (!(target_flags_explicit & MASK_LONG_DOUBLE_128))
521 target_flags |= MASK_LONG_DOUBLE_128;
524 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
525 can be optimized to ap = __builtin_next_arg (0). */
526 if (TARGET_ABI_UNICOSMK)
527 targetm.expand_builtin_va_start = NULL;
530 /* Returns 1 if VALUE is a mask that contains full bytes of zero or ones. */
533 zap_mask (HOST_WIDE_INT value)
537 for (i = 0; i < HOST_BITS_PER_WIDE_INT / HOST_BITS_PER_CHAR;
539 if ((value & 0xff) != 0 && (value & 0xff) != 0xff)
545 /* Return true if OP is valid for a particular TLS relocation.
546 We are already guaranteed that OP is a CONST. */
549 tls_symbolic_operand_1 (rtx op, int size, int unspec)
553 if (GET_CODE (op) != UNSPEC || XINT (op, 1) != unspec)
555 op = XVECEXP (op, 0, 0);
557 if (GET_CODE (op) != SYMBOL_REF)
560 switch (SYMBOL_REF_TLS_MODEL (op))
562 case TLS_MODEL_LOCAL_DYNAMIC:
563 return unspec == UNSPEC_DTPREL && size == alpha_tls_size;
564 case TLS_MODEL_INITIAL_EXEC:
565 return unspec == UNSPEC_TPREL && size == 64;
566 case TLS_MODEL_LOCAL_EXEC:
567 return unspec == UNSPEC_TPREL && size == alpha_tls_size;
573 /* Used by aligned_memory_operand and unaligned_memory_operand to
574 resolve what reload is going to do with OP if it's a register. */
577 resolve_reload_operand (rtx op)
579 if (reload_in_progress)
582 if (GET_CODE (tmp) == SUBREG)
583 tmp = SUBREG_REG (tmp);
585 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER)
587 op = reg_equiv_memory_loc[REGNO (tmp)];
595 /* The scalar modes supported differs from the default check-what-c-supports
596 version in that sometimes TFmode is available even when long double
597 indicates only DFmode. On unicosmk, we have the situation that HImode
598 doesn't map to any C type, but of course we still support that. */
601 alpha_scalar_mode_supported_p (enum machine_mode mode)
609 case TImode: /* via optabs.c */
617 return TARGET_HAS_XFLOATING_LIBS;
624 /* Alpha implements a couple of integer vector mode operations when
625 TARGET_MAX is enabled. We do not check TARGET_MAX here, however,
626 which allows the vectorizer to operate on e.g. move instructions,
627 or when expand_vector_operations can do something useful. */
630 alpha_vector_mode_supported_p (enum machine_mode mode)
632 return mode == V8QImode || mode == V4HImode || mode == V2SImode;
635 /* Return 1 if this function can directly return via $26. */
640 return (! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK
642 && alpha_sa_size () == 0
643 && get_frame_size () == 0
644 && crtl->outgoing_args_size == 0
645 && crtl->args.pretend_args_size == 0);
648 /* Return the ADDR_VEC associated with a tablejump insn. */
651 alpha_tablejump_addr_vec (rtx insn)
655 tmp = JUMP_LABEL (insn);
658 tmp = NEXT_INSN (tmp);
662 && GET_CODE (PATTERN (tmp)) == ADDR_DIFF_VEC)
663 return PATTERN (tmp);
667 /* Return the label of the predicted edge, or CONST0_RTX if we don't know. */
670 alpha_tablejump_best_label (rtx insn)
672 rtx jump_table = alpha_tablejump_addr_vec (insn);
673 rtx best_label = NULL_RTX;
675 /* ??? Once the CFG doesn't keep getting completely rebuilt, look
676 there for edge frequency counts from profile data. */
680 int n_labels = XVECLEN (jump_table, 1);
684 for (i = 0; i < n_labels; i++)
688 for (j = i + 1; j < n_labels; j++)
689 if (XEXP (XVECEXP (jump_table, 1, i), 0)
690 == XEXP (XVECEXP (jump_table, 1, j), 0))
693 if (count > best_count)
694 best_count = count, best_label = XVECEXP (jump_table, 1, i);
698 return best_label ? best_label : const0_rtx;
701 /* Return the TLS model to use for SYMBOL. */
703 static enum tls_model
704 tls_symbolic_operand_type (rtx symbol)
706 enum tls_model model;
708 if (GET_CODE (symbol) != SYMBOL_REF)
709 return TLS_MODEL_NONE;
710 model = SYMBOL_REF_TLS_MODEL (symbol);
712 /* Local-exec with a 64-bit size is the same code as initial-exec. */
713 if (model == TLS_MODEL_LOCAL_EXEC && alpha_tls_size == 64)
714 model = TLS_MODEL_INITIAL_EXEC;
719 /* Return true if the function DECL will share the same GP as any
720 function in the current unit of translation. */
723 decl_has_samegp (const_tree decl)
725 /* Functions that are not local can be overridden, and thus may
726 not share the same gp. */
727 if (!(*targetm.binds_local_p) (decl))
730 /* If -msmall-data is in effect, assume that there is only one GP
731 for the module, and so any local symbol has this property. We
732 need explicit relocations to be able to enforce this for symbols
733 not defined in this unit of translation, however. */
734 if (TARGET_EXPLICIT_RELOCS && TARGET_SMALL_DATA)
737 /* Functions that are not external are defined in this UoT. */
738 /* ??? Irritatingly, static functions not yet emitted are still
739 marked "external". Apply this to non-static functions only. */
740 return !TREE_PUBLIC (decl) || !DECL_EXTERNAL (decl);
743 /* Return true if EXP should be placed in the small data section. */
746 alpha_in_small_data_p (const_tree exp)
748 /* We want to merge strings, so we never consider them small data. */
749 if (TREE_CODE (exp) == STRING_CST)
752 /* Functions are never in the small data area. Duh. */
753 if (TREE_CODE (exp) == FUNCTION_DECL)
756 if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp))
758 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp));
759 if (strcmp (section, ".sdata") == 0
760 || strcmp (section, ".sbss") == 0)
765 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp));
767 /* If this is an incomplete type with size 0, then we can't put it
768 in sdata because it might be too big when completed. */
769 if (size > 0 && (unsigned HOST_WIDE_INT) size <= g_switch_value)
776 #if TARGET_ABI_OPEN_VMS
778 vms_valid_pointer_mode (enum machine_mode mode)
780 return (mode == SImode || mode == DImode);
784 alpha_linkage_symbol_p (const char *symname)
786 int symlen = strlen (symname);
789 return strcmp (&symname [symlen - 4], "..lk") == 0;
794 #define LINKAGE_SYMBOL_REF_P(X) \
795 ((GET_CODE (X) == SYMBOL_REF \
796 && alpha_linkage_symbol_p (XSTR (X, 0))) \
797 || (GET_CODE (X) == CONST \
798 && GET_CODE (XEXP (X, 0)) == PLUS \
799 && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF \
800 && alpha_linkage_symbol_p (XSTR (XEXP (XEXP (X, 0), 0), 0))))
803 /* legitimate_address_p recognizes an RTL expression that is a valid
804 memory address for an instruction. The MODE argument is the
805 machine mode for the MEM expression that wants to use this address.
807 For Alpha, we have either a constant address or the sum of a
808 register and a constant address, or just a register. For DImode,
809 any of those forms can be surrounded with an AND that clear the
810 low-order three bits; this is an "unaligned" access. */
813 alpha_legitimate_address_p (enum machine_mode mode, rtx x, bool strict)
815 /* If this is an ldq_u type address, discard the outer AND. */
817 && GET_CODE (x) == AND
818 && CONST_INT_P (XEXP (x, 1))
819 && INTVAL (XEXP (x, 1)) == -8)
822 /* Discard non-paradoxical subregs. */
823 if (GET_CODE (x) == SUBREG
824 && (GET_MODE_SIZE (GET_MODE (x))
825 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
828 /* Unadorned general registers are valid. */
831 ? STRICT_REG_OK_FOR_BASE_P (x)
832 : NONSTRICT_REG_OK_FOR_BASE_P (x)))
835 /* Constant addresses (i.e. +/- 32k) are valid. */
836 if (CONSTANT_ADDRESS_P (x))
839 #if TARGET_ABI_OPEN_VMS
840 if (LINKAGE_SYMBOL_REF_P (x))
844 /* Register plus a small constant offset is valid. */
845 if (GET_CODE (x) == PLUS)
847 rtx ofs = XEXP (x, 1);
850 /* Discard non-paradoxical subregs. */
851 if (GET_CODE (x) == SUBREG
852 && (GET_MODE_SIZE (GET_MODE (x))
853 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
859 && NONSTRICT_REG_OK_FP_BASE_P (x)
860 && CONST_INT_P (ofs))
863 ? STRICT_REG_OK_FOR_BASE_P (x)
864 : NONSTRICT_REG_OK_FOR_BASE_P (x))
865 && CONSTANT_ADDRESS_P (ofs))
870 /* If we're managing explicit relocations, LO_SUM is valid, as are small
871 data symbols. Avoid explicit relocations of modes larger than word
872 mode since i.e. $LC0+8($1) can fold around +/- 32k offset. */
873 else if (TARGET_EXPLICIT_RELOCS
874 && GET_MODE_SIZE (mode) <= UNITS_PER_WORD)
876 if (small_symbolic_operand (x, Pmode))
879 if (GET_CODE (x) == LO_SUM)
881 rtx ofs = XEXP (x, 1);
884 /* Discard non-paradoxical subregs. */
885 if (GET_CODE (x) == SUBREG
886 && (GET_MODE_SIZE (GET_MODE (x))
887 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
890 /* Must have a valid base register. */
893 ? STRICT_REG_OK_FOR_BASE_P (x)
894 : NONSTRICT_REG_OK_FOR_BASE_P (x))))
897 /* The symbol must be local. */
898 if (local_symbolic_operand (ofs, Pmode)
899 || dtp32_symbolic_operand (ofs, Pmode)
900 || tp32_symbolic_operand (ofs, Pmode))
908 /* Build the SYMBOL_REF for __tls_get_addr. */
910 static GTY(()) rtx tls_get_addr_libfunc;
913 get_tls_get_addr (void)
915 if (!tls_get_addr_libfunc)
916 tls_get_addr_libfunc = init_one_libfunc ("__tls_get_addr");
917 return tls_get_addr_libfunc;
920 /* Try machine-dependent ways of modifying an illegitimate address
921 to be legitimate. If we find one, return the new, valid address. */
924 alpha_legitimize_address_1 (rtx x, rtx scratch, enum machine_mode mode)
926 HOST_WIDE_INT addend;
928 /* If the address is (plus reg const_int) and the CONST_INT is not a
929 valid offset, compute the high part of the constant and add it to
930 the register. Then our address is (plus temp low-part-const). */
931 if (GET_CODE (x) == PLUS
932 && REG_P (XEXP (x, 0))
933 && CONST_INT_P (XEXP (x, 1))
934 && ! CONSTANT_ADDRESS_P (XEXP (x, 1)))
936 addend = INTVAL (XEXP (x, 1));
941 /* If the address is (const (plus FOO const_int)), find the low-order
942 part of the CONST_INT. Then load FOO plus any high-order part of the
943 CONST_INT into a register. Our address is (plus reg low-part-const).
944 This is done to reduce the number of GOT entries. */
945 if (can_create_pseudo_p ()
946 && GET_CODE (x) == CONST
947 && GET_CODE (XEXP (x, 0)) == PLUS
948 && CONST_INT_P (XEXP (XEXP (x, 0), 1)))
950 addend = INTVAL (XEXP (XEXP (x, 0), 1));
951 x = force_reg (Pmode, XEXP (XEXP (x, 0), 0));
955 /* If we have a (plus reg const), emit the load as in (2), then add
956 the two registers, and finally generate (plus reg low-part-const) as
958 if (can_create_pseudo_p ()
959 && GET_CODE (x) == PLUS
960 && REG_P (XEXP (x, 0))
961 && GET_CODE (XEXP (x, 1)) == CONST
962 && GET_CODE (XEXP (XEXP (x, 1), 0)) == PLUS
963 && CONST_INT_P (XEXP (XEXP (XEXP (x, 1), 0), 1)))
965 addend = INTVAL (XEXP (XEXP (XEXP (x, 1), 0), 1));
966 x = expand_simple_binop (Pmode, PLUS, XEXP (x, 0),
967 XEXP (XEXP (XEXP (x, 1), 0), 0),
968 NULL_RTX, 1, OPTAB_LIB_WIDEN);
972 /* If this is a local symbol, split the address into HIGH/LO_SUM parts.
973 Avoid modes larger than word mode since i.e. $LC0+8($1) can fold
974 around +/- 32k offset. */
975 if (TARGET_EXPLICIT_RELOCS
976 && GET_MODE_SIZE (mode) <= UNITS_PER_WORD
977 && symbolic_operand (x, Pmode))
979 rtx r0, r16, eqv, tga, tp, insn, dest, seq;
981 switch (tls_symbolic_operand_type (x))
986 case TLS_MODEL_GLOBAL_DYNAMIC:
989 r0 = gen_rtx_REG (Pmode, 0);
990 r16 = gen_rtx_REG (Pmode, 16);
991 tga = get_tls_get_addr ();
992 dest = gen_reg_rtx (Pmode);
993 seq = GEN_INT (alpha_next_sequence_number++);
995 emit_insn (gen_movdi_er_tlsgd (r16, pic_offset_table_rtx, x, seq));
996 insn = gen_call_value_osf_tlsgd (r0, tga, seq);
997 insn = emit_call_insn (insn);
998 RTL_CONST_CALL_P (insn) = 1;
999 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r16);
1001 insn = get_insns ();
1004 emit_libcall_block (insn, dest, r0, x);
1007 case TLS_MODEL_LOCAL_DYNAMIC:
1010 r0 = gen_rtx_REG (Pmode, 0);
1011 r16 = gen_rtx_REG (Pmode, 16);
1012 tga = get_tls_get_addr ();
1013 scratch = gen_reg_rtx (Pmode);
1014 seq = GEN_INT (alpha_next_sequence_number++);
1016 emit_insn (gen_movdi_er_tlsldm (r16, pic_offset_table_rtx, seq));
1017 insn = gen_call_value_osf_tlsldm (r0, tga, seq);
1018 insn = emit_call_insn (insn);
1019 RTL_CONST_CALL_P (insn) = 1;
1020 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r16);
1022 insn = get_insns ();
1025 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
1026 UNSPEC_TLSLDM_CALL);
1027 emit_libcall_block (insn, scratch, r0, eqv);
1029 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_DTPREL);
1030 eqv = gen_rtx_CONST (Pmode, eqv);
1032 if (alpha_tls_size == 64)
1034 dest = gen_reg_rtx (Pmode);
1035 emit_insn (gen_rtx_SET (VOIDmode, dest, eqv));
1036 emit_insn (gen_adddi3 (dest, dest, scratch));
1039 if (alpha_tls_size == 32)
1041 insn = gen_rtx_HIGH (Pmode, eqv);
1042 insn = gen_rtx_PLUS (Pmode, scratch, insn);
1043 scratch = gen_reg_rtx (Pmode);
1044 emit_insn (gen_rtx_SET (VOIDmode, scratch, insn));
1046 return gen_rtx_LO_SUM (Pmode, scratch, eqv);
1048 case TLS_MODEL_INITIAL_EXEC:
1049 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_TPREL);
1050 eqv = gen_rtx_CONST (Pmode, eqv);
1051 tp = gen_reg_rtx (Pmode);
1052 scratch = gen_reg_rtx (Pmode);
1053 dest = gen_reg_rtx (Pmode);
1055 emit_insn (gen_load_tp (tp));
1056 emit_insn (gen_rtx_SET (VOIDmode, scratch, eqv));
1057 emit_insn (gen_adddi3 (dest, tp, scratch));
1060 case TLS_MODEL_LOCAL_EXEC:
1061 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_TPREL);
1062 eqv = gen_rtx_CONST (Pmode, eqv);
1063 tp = gen_reg_rtx (Pmode);
1065 emit_insn (gen_load_tp (tp));
1066 if (alpha_tls_size == 32)
1068 insn = gen_rtx_HIGH (Pmode, eqv);
1069 insn = gen_rtx_PLUS (Pmode, tp, insn);
1070 tp = gen_reg_rtx (Pmode);
1071 emit_insn (gen_rtx_SET (VOIDmode, tp, insn));
1073 return gen_rtx_LO_SUM (Pmode, tp, eqv);
1079 if (local_symbolic_operand (x, Pmode))
1081 if (small_symbolic_operand (x, Pmode))
1085 if (can_create_pseudo_p ())
1086 scratch = gen_reg_rtx (Pmode);
1087 emit_insn (gen_rtx_SET (VOIDmode, scratch,
1088 gen_rtx_HIGH (Pmode, x)));
1089 return gen_rtx_LO_SUM (Pmode, scratch, x);
1098 HOST_WIDE_INT low, high;
1100 low = ((addend & 0xffff) ^ 0x8000) - 0x8000;
1102 high = ((addend & 0xffffffff) ^ 0x80000000) - 0x80000000;
1106 x = expand_simple_binop (Pmode, PLUS, x, GEN_INT (addend),
1107 (!can_create_pseudo_p () ? scratch : NULL_RTX),
1108 1, OPTAB_LIB_WIDEN);
1110 x = expand_simple_binop (Pmode, PLUS, x, GEN_INT (high),
1111 (!can_create_pseudo_p () ? scratch : NULL_RTX),
1112 1, OPTAB_LIB_WIDEN);
1114 return plus_constant (x, low);
1119 /* Try machine-dependent ways of modifying an illegitimate address
1120 to be legitimate. Return X or the new, valid address. */
1123 alpha_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
1124 enum machine_mode mode)
1126 rtx new_x = alpha_legitimize_address_1 (x, NULL_RTX, mode);
1127 return new_x ? new_x : x;
1130 /* Primarily this is required for TLS symbols, but given that our move
1131 patterns *ought* to be able to handle any symbol at any time, we
1132 should never be spilling symbolic operands to the constant pool, ever. */
1135 alpha_cannot_force_const_mem (rtx x)
1137 enum rtx_code code = GET_CODE (x);
1138 return code == SYMBOL_REF || code == LABEL_REF || code == CONST;
1141 /* We do not allow indirect calls to be optimized into sibling calls, nor
1142 can we allow a call to a function with a different GP to be optimized
1146 alpha_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
1148 /* Can't do indirect tail calls, since we don't know if the target
1149 uses the same GP. */
1153 /* Otherwise, we can make a tail call if the target function shares
1155 return decl_has_samegp (decl);
1159 some_small_symbolic_operand_int (rtx *px, void *data ATTRIBUTE_UNUSED)
1163 /* Don't re-split. */
1164 if (GET_CODE (x) == LO_SUM)
1167 return small_symbolic_operand (x, Pmode) != 0;
1171 split_small_symbolic_operand_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
1175 /* Don't re-split. */
1176 if (GET_CODE (x) == LO_SUM)
1179 if (small_symbolic_operand (x, Pmode))
1181 x = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, x);
1190 split_small_symbolic_operand (rtx x)
1193 for_each_rtx (&x, split_small_symbolic_operand_1, NULL);
1197 /* Indicate that INSN cannot be duplicated. This is true for any insn
1198 that we've marked with gpdisp relocs, since those have to stay in
1199 1-1 correspondence with one another.
1201 Technically we could copy them if we could set up a mapping from one
1202 sequence number to another, across the set of insns to be duplicated.
1203 This seems overly complicated and error-prone since interblock motion
1204 from sched-ebb could move one of the pair of insns to a different block.
1206 Also cannot allow jsr insns to be duplicated. If they throw exceptions,
1207 then they'll be in a different block from their ldgp. Which could lead
1208 the bb reorder code to think that it would be ok to copy just the block
1209 containing the call and branch to the block containing the ldgp. */
1212 alpha_cannot_copy_insn_p (rtx insn)
1214 if (!reload_completed || !TARGET_EXPLICIT_RELOCS)
1216 if (recog_memoized (insn) >= 0)
1217 return get_attr_cannot_copy (insn);
1223 /* Try a machine-dependent way of reloading an illegitimate address
1224 operand. If we find one, push the reload and return the new rtx. */
1227 alpha_legitimize_reload_address (rtx x,
1228 enum machine_mode mode ATTRIBUTE_UNUSED,
1229 int opnum, int type,
1230 int ind_levels ATTRIBUTE_UNUSED)
1232 /* We must recognize output that we have already generated ourselves. */
1233 if (GET_CODE (x) == PLUS
1234 && GET_CODE (XEXP (x, 0)) == PLUS
1235 && REG_P (XEXP (XEXP (x, 0), 0))
1236 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
1237 && CONST_INT_P (XEXP (x, 1)))
1239 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
1240 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
1241 opnum, (enum reload_type) type);
1245 /* We wish to handle large displacements off a base register by
1246 splitting the addend across an ldah and the mem insn. This
1247 cuts number of extra insns needed from 3 to 1. */
1248 if (GET_CODE (x) == PLUS
1249 && REG_P (XEXP (x, 0))
1250 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
1251 && REGNO_OK_FOR_BASE_P (REGNO (XEXP (x, 0)))
1252 && GET_CODE (XEXP (x, 1)) == CONST_INT)
1254 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
1255 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1257 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
1259 /* Check for 32-bit overflow. */
1260 if (high + low != val)
1263 /* Reload the high part into a base reg; leave the low part
1264 in the mem directly. */
1265 x = gen_rtx_PLUS (GET_MODE (x),
1266 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
1270 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
1271 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
1272 opnum, (enum reload_type) type);
1279 /* Compute a (partial) cost for rtx X. Return true if the complete
1280 cost has been computed, and false if subexpressions should be
1281 scanned. In either case, *TOTAL contains the cost result. */
1284 alpha_rtx_costs (rtx x, int code, int outer_code, int *total,
1287 enum machine_mode mode = GET_MODE (x);
1288 bool float_mode_p = FLOAT_MODE_P (mode);
1289 const struct alpha_rtx_cost_data *cost_data;
1292 cost_data = &alpha_rtx_cost_size;
1294 cost_data = &alpha_rtx_cost_data[alpha_tune];
1299 /* If this is an 8-bit constant, return zero since it can be used
1300 nearly anywhere with no cost. If it is a valid operand for an
1301 ADD or AND, likewise return 0 if we know it will be used in that
1302 context. Otherwise, return 2 since it might be used there later.
1303 All other constants take at least two insns. */
1304 if (INTVAL (x) >= 0 && INTVAL (x) < 256)
1312 if (x == CONST0_RTX (mode))
1314 else if ((outer_code == PLUS && add_operand (x, VOIDmode))
1315 || (outer_code == AND && and_operand (x, VOIDmode)))
1317 else if (add_operand (x, VOIDmode) || and_operand (x, VOIDmode))
1320 *total = COSTS_N_INSNS (2);
1326 if (TARGET_EXPLICIT_RELOCS && small_symbolic_operand (x, VOIDmode))
1327 *total = COSTS_N_INSNS (outer_code != MEM);
1328 else if (TARGET_EXPLICIT_RELOCS && local_symbolic_operand (x, VOIDmode))
1329 *total = COSTS_N_INSNS (1 + (outer_code != MEM));
1330 else if (tls_symbolic_operand_type (x))
1331 /* Estimate of cost for call_pal rduniq. */
1332 /* ??? How many insns do we emit here? More than one... */
1333 *total = COSTS_N_INSNS (15);
1335 /* Otherwise we do a load from the GOT. */
1336 *total = COSTS_N_INSNS (!speed ? 1 : alpha_memory_latency);
1340 /* This is effectively an add_operand. */
1347 *total = cost_data->fp_add;
1348 else if (GET_CODE (XEXP (x, 0)) == MULT
1349 && const48_operand (XEXP (XEXP (x, 0), 1), VOIDmode))
1351 *total = (rtx_cost (XEXP (XEXP (x, 0), 0),
1352 (enum rtx_code) outer_code, speed)
1353 + rtx_cost (XEXP (x, 1),
1354 (enum rtx_code) outer_code, speed)
1355 + COSTS_N_INSNS (1));
1362 *total = cost_data->fp_mult;
1363 else if (mode == DImode)
1364 *total = cost_data->int_mult_di;
1366 *total = cost_data->int_mult_si;
1370 if (CONST_INT_P (XEXP (x, 1))
1371 && INTVAL (XEXP (x, 1)) <= 3)
1373 *total = COSTS_N_INSNS (1);
1380 *total = cost_data->int_shift;
1385 *total = cost_data->fp_add;
1387 *total = cost_data->int_cmov;
1395 *total = cost_data->int_div;
1396 else if (mode == SFmode)
1397 *total = cost_data->fp_div_sf;
1399 *total = cost_data->fp_div_df;
1403 *total = COSTS_N_INSNS (!speed ? 1 : alpha_memory_latency);
1409 *total = COSTS_N_INSNS (1);
1417 *total = COSTS_N_INSNS (1) + cost_data->int_cmov;
1423 case UNSIGNED_FLOAT:
1426 case FLOAT_TRUNCATE:
1427 *total = cost_data->fp_add;
1431 if (MEM_P (XEXP (x, 0)))
1434 *total = cost_data->fp_add;
1442 /* REF is an alignable memory location. Place an aligned SImode
1443 reference into *PALIGNED_MEM and the number of bits to shift into
1444 *PBITNUM. SCRATCH is a free register for use in reloading out
1445 of range stack slots. */
1448 get_aligned_mem (rtx ref, rtx *paligned_mem, rtx *pbitnum)
1451 HOST_WIDE_INT disp, offset;
1453 gcc_assert (MEM_P (ref));
1455 if (reload_in_progress
1456 && ! memory_address_p (GET_MODE (ref), XEXP (ref, 0)))
1458 base = find_replacement (&XEXP (ref, 0));
1459 gcc_assert (memory_address_p (GET_MODE (ref), base));
1462 base = XEXP (ref, 0);
1464 if (GET_CODE (base) == PLUS)
1465 disp = INTVAL (XEXP (base, 1)), base = XEXP (base, 0);
1469 /* Find the byte offset within an aligned word. If the memory itself is
1470 claimed to be aligned, believe it. Otherwise, aligned_memory_operand
1471 will have examined the base register and determined it is aligned, and
1472 thus displacements from it are naturally alignable. */
1473 if (MEM_ALIGN (ref) >= 32)
1478 /* Access the entire aligned word. */
1479 *paligned_mem = widen_memory_access (ref, SImode, -offset);
1481 /* Convert the byte offset within the word to a bit offset. */
1482 if (WORDS_BIG_ENDIAN)
1483 offset = 32 - (GET_MODE_BITSIZE (GET_MODE (ref)) + offset * 8);
1486 *pbitnum = GEN_INT (offset);
1489 /* Similar, but just get the address. Handle the two reload cases.
1490 Add EXTRA_OFFSET to the address we return. */
1493 get_unaligned_address (rtx ref)
1496 HOST_WIDE_INT offset = 0;
1498 gcc_assert (MEM_P (ref));
1500 if (reload_in_progress
1501 && ! memory_address_p (GET_MODE (ref), XEXP (ref, 0)))
1503 base = find_replacement (&XEXP (ref, 0));
1505 gcc_assert (memory_address_p (GET_MODE (ref), base));
1508 base = XEXP (ref, 0);
1510 if (GET_CODE (base) == PLUS)
1511 offset += INTVAL (XEXP (base, 1)), base = XEXP (base, 0);
1513 return plus_constant (base, offset);
1516 /* Compute a value X, such that X & 7 == (ADDR + OFS) & 7.
1517 X is always returned in a register. */
1520 get_unaligned_offset (rtx addr, HOST_WIDE_INT ofs)
1522 if (GET_CODE (addr) == PLUS)
1524 ofs += INTVAL (XEXP (addr, 1));
1525 addr = XEXP (addr, 0);
1528 return expand_simple_binop (Pmode, PLUS, addr, GEN_INT (ofs & 7),
1529 NULL_RTX, 1, OPTAB_LIB_WIDEN);
1532 /* On the Alpha, all (non-symbolic) constants except zero go into
1533 a floating-point register via memory. Note that we cannot
1534 return anything that is not a subset of RCLASS, and that some
1535 symbolic constants cannot be dropped to memory. */
1538 alpha_preferred_reload_class(rtx x, enum reg_class rclass)
1540 /* Zero is present in any register class. */
1541 if (x == CONST0_RTX (GET_MODE (x)))
1544 /* These sorts of constants we can easily drop to memory. */
1546 || GET_CODE (x) == CONST_DOUBLE
1547 || GET_CODE (x) == CONST_VECTOR)
1549 if (rclass == FLOAT_REGS)
1551 if (rclass == ALL_REGS)
1552 return GENERAL_REGS;
1556 /* All other kinds of constants should not (and in the case of HIGH
1557 cannot) be dropped to memory -- instead we use a GENERAL_REGS
1558 secondary reload. */
1560 return (rclass == ALL_REGS ? GENERAL_REGS : rclass);
1565 /* Inform reload about cases where moving X with a mode MODE to a register in
1566 RCLASS requires an extra scratch or immediate register. Return the class
1567 needed for the immediate register. */
1569 static enum reg_class
1570 alpha_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
1571 enum machine_mode mode, secondary_reload_info *sri)
1573 /* Loading and storing HImode or QImode values to and from memory
1574 usually requires a scratch register. */
1575 if (!TARGET_BWX && (mode == QImode || mode == HImode || mode == CQImode))
1577 if (any_memory_operand (x, mode))
1581 if (!aligned_memory_operand (x, mode))
1582 sri->icode = reload_in_optab[mode];
1585 sri->icode = reload_out_optab[mode];
1590 /* We also cannot do integral arithmetic into FP regs, as might result
1591 from register elimination into a DImode fp register. */
1592 if (rclass == FLOAT_REGS)
1594 if (MEM_P (x) && GET_CODE (XEXP (x, 0)) == AND)
1595 return GENERAL_REGS;
1596 if (in_p && INTEGRAL_MODE_P (mode)
1597 && !MEM_P (x) && !REG_P (x) && !CONST_INT_P (x))
1598 return GENERAL_REGS;
1604 /* Subfunction of the following function. Update the flags of any MEM
1605 found in part of X. */
1608 alpha_set_memflags_1 (rtx *xp, void *data)
1610 rtx x = *xp, orig = (rtx) data;
1615 MEM_VOLATILE_P (x) = MEM_VOLATILE_P (orig);
1616 MEM_IN_STRUCT_P (x) = MEM_IN_STRUCT_P (orig);
1617 MEM_SCALAR_P (x) = MEM_SCALAR_P (orig);
1618 MEM_NOTRAP_P (x) = MEM_NOTRAP_P (orig);
1619 MEM_READONLY_P (x) = MEM_READONLY_P (orig);
1621 /* Sadly, we cannot use alias sets because the extra aliasing
1622 produced by the AND interferes. Given that two-byte quantities
1623 are the only thing we would be able to differentiate anyway,
1624 there does not seem to be any point in convoluting the early
1625 out of the alias check. */
1630 /* Given SEQ, which is an INSN list, look for any MEMs in either
1631 a SET_DEST or a SET_SRC and copy the in-struct, unchanging, and
1632 volatile flags from REF into each of the MEMs found. If REF is not
1633 a MEM, don't do anything. */
1636 alpha_set_memflags (rtx seq, rtx ref)
1643 /* This is only called from alpha.md, after having had something
1644 generated from one of the insn patterns. So if everything is
1645 zero, the pattern is already up-to-date. */
1646 if (!MEM_VOLATILE_P (ref)
1647 && !MEM_IN_STRUCT_P (ref)
1648 && !MEM_SCALAR_P (ref)
1649 && !MEM_NOTRAP_P (ref)
1650 && !MEM_READONLY_P (ref))
1653 for (insn = seq; insn; insn = NEXT_INSN (insn))
1655 for_each_rtx (&PATTERN (insn), alpha_set_memflags_1, (void *) ref);
1660 static rtx alpha_emit_set_const (rtx, enum machine_mode, HOST_WIDE_INT,
1663 /* Internal routine for alpha_emit_set_const to check for N or below insns.
1664 If NO_OUTPUT is true, then we only check to see if N insns are possible,
1665 and return pc_rtx if successful. */
1668 alpha_emit_set_const_1 (rtx target, enum machine_mode mode,
1669 HOST_WIDE_INT c, int n, bool no_output)
1671 HOST_WIDE_INT new_const;
1673 /* Use a pseudo if highly optimizing and still generating RTL. */
1675 = (flag_expensive_optimizations && can_create_pseudo_p () ? 0 : target);
1678 /* If this is a sign-extended 32-bit constant, we can do this in at most
1679 three insns, so do it if we have enough insns left. We always have
1680 a sign-extended 32-bit constant when compiling on a narrow machine. */
1682 if (HOST_BITS_PER_WIDE_INT != 64
1683 || c >> 31 == -1 || c >> 31 == 0)
1685 HOST_WIDE_INT low = ((c & 0xffff) ^ 0x8000) - 0x8000;
1686 HOST_WIDE_INT tmp1 = c - low;
1687 HOST_WIDE_INT high = (((tmp1 >> 16) & 0xffff) ^ 0x8000) - 0x8000;
1688 HOST_WIDE_INT extra = 0;
1690 /* If HIGH will be interpreted as negative but the constant is
1691 positive, we must adjust it to do two ldha insns. */
1693 if ((high & 0x8000) != 0 && c >= 0)
1697 high = ((tmp1 >> 16) & 0xffff) - 2 * ((tmp1 >> 16) & 0x8000);
1700 if (c == low || (low == 0 && extra == 0))
1702 /* We used to use copy_to_suggested_reg (GEN_INT (c), target, mode)
1703 but that meant that we can't handle INT_MIN on 32-bit machines
1704 (like NT/Alpha), because we recurse indefinitely through
1705 emit_move_insn to gen_movdi. So instead, since we know exactly
1706 what we want, create it explicitly. */
1711 target = gen_reg_rtx (mode);
1712 emit_insn (gen_rtx_SET (VOIDmode, target, GEN_INT (c)));
1715 else if (n >= 2 + (extra != 0))
1719 if (!can_create_pseudo_p ())
1721 emit_insn (gen_rtx_SET (VOIDmode, target, GEN_INT (high << 16)));
1725 temp = copy_to_suggested_reg (GEN_INT (high << 16),
1728 /* As of 2002-02-23, addsi3 is only available when not optimizing.
1729 This means that if we go through expand_binop, we'll try to
1730 generate extensions, etc, which will require new pseudos, which
1731 will fail during some split phases. The SImode add patterns
1732 still exist, but are not named. So build the insns by hand. */
1737 subtarget = gen_reg_rtx (mode);
1738 insn = gen_rtx_PLUS (mode, temp, GEN_INT (extra << 16));
1739 insn = gen_rtx_SET (VOIDmode, subtarget, insn);
1745 target = gen_reg_rtx (mode);
1746 insn = gen_rtx_PLUS (mode, temp, GEN_INT (low));
1747 insn = gen_rtx_SET (VOIDmode, target, insn);
1753 /* If we couldn't do it that way, try some other methods. But if we have
1754 no instructions left, don't bother. Likewise, if this is SImode and
1755 we can't make pseudos, we can't do anything since the expand_binop
1756 and expand_unop calls will widen and try to make pseudos. */
1758 if (n == 1 || (mode == SImode && !can_create_pseudo_p ()))
1761 /* Next, see if we can load a related constant and then shift and possibly
1762 negate it to get the constant we want. Try this once each increasing
1763 numbers of insns. */
1765 for (i = 1; i < n; i++)
1767 /* First, see if minus some low bits, we've an easy load of
1770 new_const = ((c & 0xffff) ^ 0x8000) - 0x8000;
1773 temp = alpha_emit_set_const (subtarget, mode, c - new_const, i, no_output);
1778 return expand_binop (mode, add_optab, temp, GEN_INT (new_const),
1779 target, 0, OPTAB_WIDEN);
1783 /* Next try complementing. */
1784 temp = alpha_emit_set_const (subtarget, mode, ~c, i, no_output);
1789 return expand_unop (mode, one_cmpl_optab, temp, target, 0);
1792 /* Next try to form a constant and do a left shift. We can do this
1793 if some low-order bits are zero; the exact_log2 call below tells
1794 us that information. The bits we are shifting out could be any
1795 value, but here we'll just try the 0- and sign-extended forms of
1796 the constant. To try to increase the chance of having the same
1797 constant in more than one insn, start at the highest number of
1798 bits to shift, but try all possibilities in case a ZAPNOT will
1801 bits = exact_log2 (c & -c);
1803 for (; bits > 0; bits--)
1805 new_const = c >> bits;
1806 temp = alpha_emit_set_const (subtarget, mode, new_const, i, no_output);
1809 new_const = (unsigned HOST_WIDE_INT)c >> bits;
1810 temp = alpha_emit_set_const (subtarget, mode, new_const,
1817 return expand_binop (mode, ashl_optab, temp, GEN_INT (bits),
1818 target, 0, OPTAB_WIDEN);
1822 /* Now try high-order zero bits. Here we try the shifted-in bits as
1823 all zero and all ones. Be careful to avoid shifting outside the
1824 mode and to avoid shifting outside the host wide int size. */
1825 /* On narrow hosts, don't shift a 1 into the high bit, since we'll
1826 confuse the recursive call and set all of the high 32 bits. */
1828 bits = (MIN (HOST_BITS_PER_WIDE_INT, GET_MODE_SIZE (mode) * 8)
1829 - floor_log2 (c) - 1 - (HOST_BITS_PER_WIDE_INT < 64));
1831 for (; bits > 0; bits--)
1833 new_const = c << bits;
1834 temp = alpha_emit_set_const (subtarget, mode, new_const, i, no_output);
1837 new_const = (c << bits) | (((HOST_WIDE_INT) 1 << bits) - 1);
1838 temp = alpha_emit_set_const (subtarget, mode, new_const,
1845 return expand_binop (mode, lshr_optab, temp, GEN_INT (bits),
1846 target, 1, OPTAB_WIDEN);
1850 /* Now try high-order 1 bits. We get that with a sign-extension.
1851 But one bit isn't enough here. Be careful to avoid shifting outside
1852 the mode and to avoid shifting outside the host wide int size. */
1854 bits = (MIN (HOST_BITS_PER_WIDE_INT, GET_MODE_SIZE (mode) * 8)
1855 - floor_log2 (~ c) - 2);
1857 for (; bits > 0; bits--)
1859 new_const = c << bits;
1860 temp = alpha_emit_set_const (subtarget, mode, new_const, i, no_output);
1863 new_const = (c << bits) | (((HOST_WIDE_INT) 1 << bits) - 1);
1864 temp = alpha_emit_set_const (subtarget, mode, new_const,
1871 return expand_binop (mode, ashr_optab, temp, GEN_INT (bits),
1872 target, 0, OPTAB_WIDEN);
1877 #if HOST_BITS_PER_WIDE_INT == 64
1878 /* Finally, see if can load a value into the target that is the same as the
1879 constant except that all bytes that are 0 are changed to be 0xff. If we
1880 can, then we can do a ZAPNOT to obtain the desired constant. */
1883 for (i = 0; i < 64; i += 8)
1884 if ((new_const & ((HOST_WIDE_INT) 0xff << i)) == 0)
1885 new_const |= (HOST_WIDE_INT) 0xff << i;
1887 /* We are only called for SImode and DImode. If this is SImode, ensure that
1888 we are sign extended to a full word. */
1891 new_const = ((new_const & 0xffffffff) ^ 0x80000000) - 0x80000000;
1895 temp = alpha_emit_set_const (subtarget, mode, new_const, n - 1, no_output);
1900 return expand_binop (mode, and_optab, temp, GEN_INT (c | ~ new_const),
1901 target, 0, OPTAB_WIDEN);
1909 /* Try to output insns to set TARGET equal to the constant C if it can be
1910 done in less than N insns. Do all computations in MODE. Returns the place
1911 where the output has been placed if it can be done and the insns have been
1912 emitted. If it would take more than N insns, zero is returned and no
1913 insns and emitted. */
1916 alpha_emit_set_const (rtx target, enum machine_mode mode,
1917 HOST_WIDE_INT c, int n, bool no_output)
1919 enum machine_mode orig_mode = mode;
1920 rtx orig_target = target;
1924 /* If we can't make any pseudos, TARGET is an SImode hard register, we
1925 can't load this constant in one insn, do this in DImode. */
1926 if (!can_create_pseudo_p () && mode == SImode
1927 && REG_P (target) && REGNO (target) < FIRST_PSEUDO_REGISTER)
1929 result = alpha_emit_set_const_1 (target, mode, c, 1, no_output);
1933 target = no_output ? NULL : gen_lowpart (DImode, target);
1936 else if (mode == V8QImode || mode == V4HImode || mode == V2SImode)
1938 target = no_output ? NULL : gen_lowpart (DImode, target);
1942 /* Try 1 insn, then 2, then up to N. */
1943 for (i = 1; i <= n; i++)
1945 result = alpha_emit_set_const_1 (target, mode, c, i, no_output);
1953 insn = get_last_insn ();
1954 set = single_set (insn);
1955 if (! CONSTANT_P (SET_SRC (set)))
1956 set_unique_reg_note (get_last_insn (), REG_EQUAL, GEN_INT (c));
1961 /* Allow for the case where we changed the mode of TARGET. */
1964 if (result == target)
1965 result = orig_target;
1966 else if (mode != orig_mode)
1967 result = gen_lowpart (orig_mode, result);
1973 /* Having failed to find a 3 insn sequence in alpha_emit_set_const,
1974 fall back to a straight forward decomposition. We do this to avoid
1975 exponential run times encountered when looking for longer sequences
1976 with alpha_emit_set_const. */
1979 alpha_emit_set_long_const (rtx target, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
1981 HOST_WIDE_INT d1, d2, d3, d4;
1983 /* Decompose the entire word */
1984 #if HOST_BITS_PER_WIDE_INT >= 64
1985 gcc_assert (c2 == -(c1 < 0));
1986 d1 = ((c1 & 0xffff) ^ 0x8000) - 0x8000;
1988 d2 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000;
1989 c1 = (c1 - d2) >> 32;
1990 d3 = ((c1 & 0xffff) ^ 0x8000) - 0x8000;
1992 d4 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000;
1993 gcc_assert (c1 == d4);
1995 d1 = ((c1 & 0xffff) ^ 0x8000) - 0x8000;
1997 d2 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000;
1998 gcc_assert (c1 == d2);
2000 d3 = ((c2 & 0xffff) ^ 0x8000) - 0x8000;
2002 d4 = ((c2 & 0xffffffff) ^ 0x80000000) - 0x80000000;
2003 gcc_assert (c2 == d4);
2006 /* Construct the high word */
2009 emit_move_insn (target, GEN_INT (d4));
2011 emit_move_insn (target, gen_rtx_PLUS (DImode, target, GEN_INT (d3)));
2014 emit_move_insn (target, GEN_INT (d3));
2016 /* Shift it into place */
2017 emit_move_insn (target, gen_rtx_ASHIFT (DImode, target, GEN_INT (32)));
2019 /* Add in the low bits. */
2021 emit_move_insn (target, gen_rtx_PLUS (DImode, target, GEN_INT (d2)));
2023 emit_move_insn (target, gen_rtx_PLUS (DImode, target, GEN_INT (d1)));
2028 /* Given an integral CONST_INT, CONST_DOUBLE, or CONST_VECTOR, return
2032 alpha_extract_integer (rtx x, HOST_WIDE_INT *p0, HOST_WIDE_INT *p1)
2034 HOST_WIDE_INT i0, i1;
2036 if (GET_CODE (x) == CONST_VECTOR)
2037 x = simplify_subreg (DImode, x, GET_MODE (x), 0);
2040 if (CONST_INT_P (x))
2045 else if (HOST_BITS_PER_WIDE_INT >= 64)
2047 i0 = CONST_DOUBLE_LOW (x);
2052 i0 = CONST_DOUBLE_LOW (x);
2053 i1 = CONST_DOUBLE_HIGH (x);
2060 /* Implement LEGITIMATE_CONSTANT_P. This is all constants for which we
2061 are willing to load the value into a register via a move pattern.
2062 Normally this is all symbolic constants, integral constants that
2063 take three or fewer instructions, and floating-point zero. */
2066 alpha_legitimate_constant_p (rtx x)
2068 enum machine_mode mode = GET_MODE (x);
2069 HOST_WIDE_INT i0, i1;
2071 switch (GET_CODE (x))
2078 if (GET_CODE (XEXP (x, 0)) == PLUS
2079 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
2080 x = XEXP (XEXP (x, 0), 0);
2084 if (GET_CODE (x) != SYMBOL_REF)
2090 /* TLS symbols are never valid. */
2091 return SYMBOL_REF_TLS_MODEL (x) == 0;
2094 if (x == CONST0_RTX (mode))
2096 if (FLOAT_MODE_P (mode))
2101 if (x == CONST0_RTX (mode))
2103 if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT)
2105 if (GET_MODE_SIZE (mode) != 8)
2111 if (TARGET_BUILD_CONSTANTS)
2113 alpha_extract_integer (x, &i0, &i1);
2114 if (HOST_BITS_PER_WIDE_INT >= 64 || i1 == (-i0 < 0))
2115 return alpha_emit_set_const_1 (x, mode, i0, 3, true) != NULL;
2123 /* Operand 1 is known to be a constant, and should require more than one
2124 instruction to load. Emit that multi-part load. */
2127 alpha_split_const_mov (enum machine_mode mode, rtx *operands)
2129 HOST_WIDE_INT i0, i1;
2130 rtx temp = NULL_RTX;
2132 alpha_extract_integer (operands[1], &i0, &i1);
2134 if (HOST_BITS_PER_WIDE_INT >= 64 || i1 == -(i0 < 0))
2135 temp = alpha_emit_set_const (operands[0], mode, i0, 3, false);
2137 if (!temp && TARGET_BUILD_CONSTANTS)
2138 temp = alpha_emit_set_long_const (operands[0], i0, i1);
2142 if (!rtx_equal_p (operands[0], temp))
2143 emit_move_insn (operands[0], temp);
2150 /* Expand a move instruction; return true if all work is done.
2151 We don't handle non-bwx subword loads here. */
2154 alpha_expand_mov (enum machine_mode mode, rtx *operands)
2158 /* If the output is not a register, the input must be. */
2159 if (MEM_P (operands[0])
2160 && ! reg_or_0_operand (operands[1], mode))
2161 operands[1] = force_reg (mode, operands[1]);
2163 /* Allow legitimize_address to perform some simplifications. */
2164 if (mode == Pmode && symbolic_operand (operands[1], mode))
2166 tmp = alpha_legitimize_address_1 (operands[1], operands[0], mode);
2169 if (tmp == operands[0])
2176 /* Early out for non-constants and valid constants. */
2177 if (! CONSTANT_P (operands[1]) || input_operand (operands[1], mode))
2180 /* Split large integers. */
2181 if (CONST_INT_P (operands[1])
2182 || GET_CODE (operands[1]) == CONST_DOUBLE
2183 || GET_CODE (operands[1]) == CONST_VECTOR)
2185 if (alpha_split_const_mov (mode, operands))
2189 /* Otherwise we've nothing left but to drop the thing to memory. */
2190 tmp = force_const_mem (mode, operands[1]);
2192 if (tmp == NULL_RTX)
2195 if (reload_in_progress)
2197 emit_move_insn (operands[0], XEXP (tmp, 0));
2198 operands[1] = replace_equiv_address (tmp, operands[0]);
2201 operands[1] = validize_mem (tmp);
2205 /* Expand a non-bwx QImode or HImode move instruction;
2206 return true if all work is done. */
2209 alpha_expand_mov_nobwx (enum machine_mode mode, rtx *operands)
2213 /* If the output is not a register, the input must be. */
2214 if (MEM_P (operands[0]))
2215 operands[1] = force_reg (mode, operands[1]);
2217 /* Handle four memory cases, unaligned and aligned for either the input
2218 or the output. The only case where we can be called during reload is
2219 for aligned loads; all other cases require temporaries. */
2221 if (any_memory_operand (operands[1], mode))
2223 if (aligned_memory_operand (operands[1], mode))
2225 if (reload_in_progress)
2228 seq = gen_reload_inqi_aligned (operands[0], operands[1]);
2230 seq = gen_reload_inhi_aligned (operands[0], operands[1]);
2235 rtx aligned_mem, bitnum;
2236 rtx scratch = gen_reg_rtx (SImode);
2240 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
2242 subtarget = operands[0];
2243 if (REG_P (subtarget))
2244 subtarget = gen_lowpart (DImode, subtarget), copyout = false;
2246 subtarget = gen_reg_rtx (DImode), copyout = true;
2249 seq = gen_aligned_loadqi (subtarget, aligned_mem,
2252 seq = gen_aligned_loadhi (subtarget, aligned_mem,
2257 emit_move_insn (operands[0], gen_lowpart (mode, subtarget));
2262 /* Don't pass these as parameters since that makes the generated
2263 code depend on parameter evaluation order which will cause
2264 bootstrap failures. */
2266 rtx temp1, temp2, subtarget, ua;
2269 temp1 = gen_reg_rtx (DImode);
2270 temp2 = gen_reg_rtx (DImode);
2272 subtarget = operands[0];
2273 if (REG_P (subtarget))
2274 subtarget = gen_lowpart (DImode, subtarget), copyout = false;
2276 subtarget = gen_reg_rtx (DImode), copyout = true;
2278 ua = get_unaligned_address (operands[1]);
2280 seq = gen_unaligned_loadqi (subtarget, ua, temp1, temp2);
2282 seq = gen_unaligned_loadhi (subtarget, ua, temp1, temp2);
2284 alpha_set_memflags (seq, operands[1]);
2288 emit_move_insn (operands[0], gen_lowpart (mode, subtarget));
2293 if (any_memory_operand (operands[0], mode))
2295 if (aligned_memory_operand (operands[0], mode))
2297 rtx aligned_mem, bitnum;
2298 rtx temp1 = gen_reg_rtx (SImode);
2299 rtx temp2 = gen_reg_rtx (SImode);
2301 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
2303 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
2308 rtx temp1 = gen_reg_rtx (DImode);
2309 rtx temp2 = gen_reg_rtx (DImode);
2310 rtx temp3 = gen_reg_rtx (DImode);
2311 rtx ua = get_unaligned_address (operands[0]);
2314 seq = gen_unaligned_storeqi (ua, operands[1], temp1, temp2, temp3);
2316 seq = gen_unaligned_storehi (ua, operands[1], temp1, temp2, temp3);
2318 alpha_set_memflags (seq, operands[0]);
2327 /* Implement the movmisalign patterns. One of the operands is a memory
2328 that is not naturally aligned. Emit instructions to load it. */
2331 alpha_expand_movmisalign (enum machine_mode mode, rtx *operands)
2333 /* Honor misaligned loads, for those we promised to do so. */
2334 if (MEM_P (operands[1]))
2338 if (register_operand (operands[0], mode))
2341 tmp = gen_reg_rtx (mode);
2343 alpha_expand_unaligned_load (tmp, operands[1], 8, 0, 0);
2344 if (tmp != operands[0])
2345 emit_move_insn (operands[0], tmp);
2347 else if (MEM_P (operands[0]))
2349 if (!reg_or_0_operand (operands[1], mode))
2350 operands[1] = force_reg (mode, operands[1]);
2351 alpha_expand_unaligned_store (operands[0], operands[1], 8, 0);
2357 /* Generate an unsigned DImode to FP conversion. This is the same code
2358 optabs would emit if we didn't have TFmode patterns.
2360 For SFmode, this is the only construction I've found that can pass
2361 gcc.c-torture/execute/ieee/rbug.c. No scenario that uses DFmode
2362 intermediates will work, because you'll get intermediate rounding
2363 that ruins the end result. Some of this could be fixed by turning
2364 on round-to-positive-infinity, but that requires diddling the fpsr,
2365 which kills performance. I tried turning this around and converting
2366 to a negative number, so that I could turn on /m, but either I did
2367 it wrong or there's something else cause I wound up with the exact
2368 same single-bit error. There is a branch-less form of this same code:
2379 fcmoveq $f10,$f11,$f0
2381 I'm not using it because it's the same number of instructions as
2382 this branch-full form, and it has more serialized long latency
2383 instructions on the critical path.
2385 For DFmode, we can avoid rounding errors by breaking up the word
2386 into two pieces, converting them separately, and adding them back:
2388 LC0: .long 0,0x5f800000
2393 cpyse $f11,$f31,$f10
2394 cpyse $f31,$f11,$f11
2402 This doesn't seem to be a clear-cut win over the optabs form.
2403 It probably all depends on the distribution of numbers being
2404 converted -- in the optabs form, all but high-bit-set has a
2405 much lower minimum execution time. */
2408 alpha_emit_floatuns (rtx operands[2])
2410 rtx neglab, donelab, i0, i1, f0, in, out;
2411 enum machine_mode mode;
2414 in = force_reg (DImode, operands[1]);
2415 mode = GET_MODE (out);
2416 neglab = gen_label_rtx ();
2417 donelab = gen_label_rtx ();
2418 i0 = gen_reg_rtx (DImode);
2419 i1 = gen_reg_rtx (DImode);
2420 f0 = gen_reg_rtx (mode);
2422 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, DImode, 0, neglab);
2424 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_FLOAT (mode, in)));
2425 emit_jump_insn (gen_jump (donelab));
2428 emit_label (neglab);
2430 emit_insn (gen_lshrdi3 (i0, in, const1_rtx));
2431 emit_insn (gen_anddi3 (i1, in, const1_rtx));
2432 emit_insn (gen_iordi3 (i0, i0, i1));
2433 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_FLOAT (mode, i0)));
2434 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
2436 emit_label (donelab);
2439 /* Generate the comparison for a conditional branch. */
2442 alpha_emit_conditional_branch (rtx operands[], enum machine_mode cmp_mode)
2444 enum rtx_code cmp_code, branch_code;
2445 enum machine_mode branch_mode = VOIDmode;
2446 enum rtx_code code = GET_CODE (operands[0]);
2447 rtx op0 = operands[1], op1 = operands[2];
2450 if (cmp_mode == TFmode)
2452 op0 = alpha_emit_xfloating_compare (&code, op0, op1);
2457 /* The general case: fold the comparison code to the types of compares
2458 that we have, choosing the branch as necessary. */
2461 case EQ: case LE: case LT: case LEU: case LTU:
2463 /* We have these compares: */
2464 cmp_code = code, branch_code = NE;
2469 /* These must be reversed. */
2470 cmp_code = reverse_condition (code), branch_code = EQ;
2473 case GE: case GT: case GEU: case GTU:
2474 /* For FP, we swap them, for INT, we reverse them. */
2475 if (cmp_mode == DFmode)
2477 cmp_code = swap_condition (code);
2479 tem = op0, op0 = op1, op1 = tem;
2483 cmp_code = reverse_condition (code);
2492 if (cmp_mode == DFmode)
2494 if (flag_unsafe_math_optimizations && cmp_code != UNORDERED)
2496 /* When we are not as concerned about non-finite values, and we
2497 are comparing against zero, we can branch directly. */
2498 if (op1 == CONST0_RTX (DFmode))
2499 cmp_code = UNKNOWN, branch_code = code;
2500 else if (op0 == CONST0_RTX (DFmode))
2502 /* Undo the swap we probably did just above. */
2503 tem = op0, op0 = op1, op1 = tem;
2504 branch_code = swap_condition (cmp_code);
2510 /* ??? We mark the branch mode to be CCmode to prevent the
2511 compare and branch from being combined, since the compare
2512 insn follows IEEE rules that the branch does not. */
2513 branch_mode = CCmode;
2518 /* The following optimizations are only for signed compares. */
2519 if (code != LEU && code != LTU && code != GEU && code != GTU)
2521 /* Whee. Compare and branch against 0 directly. */
2522 if (op1 == const0_rtx)
2523 cmp_code = UNKNOWN, branch_code = code;
2525 /* If the constants doesn't fit into an immediate, but can
2526 be generated by lda/ldah, we adjust the argument and
2527 compare against zero, so we can use beq/bne directly. */
2528 /* ??? Don't do this when comparing against symbols, otherwise
2529 we'll reduce (&x == 0x1234) to (&x-0x1234 == 0), which will
2530 be declared false out of hand (at least for non-weak). */
2531 else if (CONST_INT_P (op1)
2532 && (code == EQ || code == NE)
2533 && !(symbolic_operand (op0, VOIDmode)
2534 || (REG_P (op0) && REG_POINTER (op0))))
2536 rtx n_op1 = GEN_INT (-INTVAL (op1));
2538 if (! satisfies_constraint_I (op1)
2539 && (satisfies_constraint_K (n_op1)
2540 || satisfies_constraint_L (n_op1)))
2541 cmp_code = PLUS, branch_code = code, op1 = n_op1;
2545 if (!reg_or_0_operand (op0, DImode))
2546 op0 = force_reg (DImode, op0);
2547 if (cmp_code != PLUS && !reg_or_8bit_operand (op1, DImode))
2548 op1 = force_reg (DImode, op1);
2551 /* Emit an initial compare instruction, if necessary. */
2553 if (cmp_code != UNKNOWN)
2555 tem = gen_reg_rtx (cmp_mode);
2556 emit_move_insn (tem, gen_rtx_fmt_ee (cmp_code, cmp_mode, op0, op1));
2559 /* Emit the branch instruction. */
2560 tem = gen_rtx_SET (VOIDmode, pc_rtx,
2561 gen_rtx_IF_THEN_ELSE (VOIDmode,
2562 gen_rtx_fmt_ee (branch_code,
2564 CONST0_RTX (cmp_mode)),
2565 gen_rtx_LABEL_REF (VOIDmode,
2568 emit_jump_insn (tem);
2571 /* Certain simplifications can be done to make invalid setcc operations
2572 valid. Return the final comparison, or NULL if we can't work. */
2575 alpha_emit_setcc (rtx operands[], enum machine_mode cmp_mode)
2577 enum rtx_code cmp_code;
2578 enum rtx_code code = GET_CODE (operands[1]);
2579 rtx op0 = operands[2], op1 = operands[3];
2582 if (cmp_mode == TFmode)
2584 op0 = alpha_emit_xfloating_compare (&code, op0, op1);
2589 if (cmp_mode == DFmode && !TARGET_FIX)
2592 /* The general case: fold the comparison code to the types of compares
2593 that we have, choosing the branch as necessary. */
2598 case EQ: case LE: case LT: case LEU: case LTU:
2600 /* We have these compares. */
2601 if (cmp_mode == DFmode)
2602 cmp_code = code, code = NE;
2606 if (cmp_mode == DImode && op1 == const0_rtx)
2611 cmp_code = reverse_condition (code);
2615 case GE: case GT: case GEU: case GTU:
2616 /* These normally need swapping, but for integer zero we have
2617 special patterns that recognize swapped operands. */
2618 if (cmp_mode == DImode && op1 == const0_rtx)
2620 code = swap_condition (code);
2621 if (cmp_mode == DFmode)
2622 cmp_code = code, code = NE;
2623 tmp = op0, op0 = op1, op1 = tmp;
2630 if (cmp_mode == DImode)
2632 if (!register_operand (op0, DImode))
2633 op0 = force_reg (DImode, op0);
2634 if (!reg_or_8bit_operand (op1, DImode))
2635 op1 = force_reg (DImode, op1);
2638 /* Emit an initial compare instruction, if necessary. */
2639 if (cmp_code != UNKNOWN)
2641 tmp = gen_reg_rtx (cmp_mode);
2642 emit_insn (gen_rtx_SET (VOIDmode, tmp,
2643 gen_rtx_fmt_ee (cmp_code, cmp_mode, op0, op1)));
2645 op0 = cmp_mode != DImode ? gen_lowpart (DImode, tmp) : tmp;
2649 /* Emit the setcc instruction. */
2650 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2651 gen_rtx_fmt_ee (code, DImode, op0, op1)));
2656 /* Rewrite a comparison against zero CMP of the form
2657 (CODE (cc0) (const_int 0)) so it can be written validly in
2658 a conditional move (if_then_else CMP ...).
2659 If both of the operands that set cc0 are nonzero we must emit
2660 an insn to perform the compare (it can't be done within
2661 the conditional move). */
2664 alpha_emit_conditional_move (rtx cmp, enum machine_mode mode)
2666 enum rtx_code code = GET_CODE (cmp);
2667 enum rtx_code cmov_code = NE;
2668 rtx op0 = XEXP (cmp, 0);
2669 rtx op1 = XEXP (cmp, 1);
2670 enum machine_mode cmp_mode
2671 = (GET_MODE (op0) == VOIDmode ? DImode : GET_MODE (op0));
2672 enum machine_mode cmov_mode = VOIDmode;
2673 int local_fast_math = flag_unsafe_math_optimizations;
2676 if (cmp_mode == TFmode)
2678 op0 = alpha_emit_xfloating_compare (&code, op0, op1);
2683 gcc_assert (cmp_mode == DFmode || cmp_mode == DImode);
2685 if (FLOAT_MODE_P (cmp_mode) != FLOAT_MODE_P (mode))
2687 enum rtx_code cmp_code;
2692 /* If we have fp<->int register move instructions, do a cmov by
2693 performing the comparison in fp registers, and move the
2694 zero/nonzero value to integer registers, where we can then
2695 use a normal cmov, or vice-versa. */
2699 case EQ: case LE: case LT: case LEU: case LTU:
2700 /* We have these compares. */
2701 cmp_code = code, code = NE;
2705 /* This must be reversed. */
2706 cmp_code = EQ, code = EQ;
2709 case GE: case GT: case GEU: case GTU:
2710 /* These normally need swapping, but for integer zero we have
2711 special patterns that recognize swapped operands. */
2712 if (cmp_mode == DImode && op1 == const0_rtx)
2713 cmp_code = code, code = NE;
2716 cmp_code = swap_condition (code);
2718 tem = op0, op0 = op1, op1 = tem;
2726 tem = gen_reg_rtx (cmp_mode);
2727 emit_insn (gen_rtx_SET (VOIDmode, tem,
2728 gen_rtx_fmt_ee (cmp_code, cmp_mode,
2731 cmp_mode = cmp_mode == DImode ? DFmode : DImode;
2732 op0 = gen_lowpart (cmp_mode, tem);
2733 op1 = CONST0_RTX (cmp_mode);
2734 local_fast_math = 1;
2737 /* We may be able to use a conditional move directly.
2738 This avoids emitting spurious compares. */
2739 if (signed_comparison_operator (cmp, VOIDmode)
2740 && (cmp_mode == DImode || local_fast_math)
2741 && (op0 == CONST0_RTX (cmp_mode) || op1 == CONST0_RTX (cmp_mode)))
2742 return gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
2744 /* We can't put the comparison inside the conditional move;
2745 emit a compare instruction and put that inside the
2746 conditional move. Make sure we emit only comparisons we have;
2747 swap or reverse as necessary. */
2749 if (!can_create_pseudo_p ())
2754 case EQ: case LE: case LT: case LEU: case LTU:
2755 /* We have these compares: */
2759 /* This must be reversed. */
2760 code = reverse_condition (code);
2764 case GE: case GT: case GEU: case GTU:
2765 /* These must be swapped. */
2766 if (op1 != CONST0_RTX (cmp_mode))
2768 code = swap_condition (code);
2769 tem = op0, op0 = op1, op1 = tem;
2777 if (cmp_mode == DImode)
2779 if (!reg_or_0_operand (op0, DImode))
2780 op0 = force_reg (DImode, op0);
2781 if (!reg_or_8bit_operand (op1, DImode))
2782 op1 = force_reg (DImode, op1);
2785 /* ??? We mark the branch mode to be CCmode to prevent the compare
2786 and cmov from being combined, since the compare insn follows IEEE
2787 rules that the cmov does not. */
2788 if (cmp_mode == DFmode && !local_fast_math)
2791 tem = gen_reg_rtx (cmp_mode);
2792 emit_move_insn (tem, gen_rtx_fmt_ee (code, cmp_mode, op0, op1));
2793 return gen_rtx_fmt_ee (cmov_code, cmov_mode, tem, CONST0_RTX (cmp_mode));
2796 /* Simplify a conditional move of two constants into a setcc with
2797 arithmetic. This is done with a splitter since combine would
2798 just undo the work if done during code generation. It also catches
2799 cases we wouldn't have before cse. */
2802 alpha_split_conditional_move (enum rtx_code code, rtx dest, rtx cond,
2803 rtx t_rtx, rtx f_rtx)
2805 HOST_WIDE_INT t, f, diff;
2806 enum machine_mode mode;
2807 rtx target, subtarget, tmp;
2809 mode = GET_MODE (dest);
2814 if (((code == NE || code == EQ) && diff < 0)
2815 || (code == GE || code == GT))
2817 code = reverse_condition (code);
2818 diff = t, t = f, f = diff;
2822 subtarget = target = dest;
2825 target = gen_lowpart (DImode, dest);
2826 if (can_create_pseudo_p ())
2827 subtarget = gen_reg_rtx (DImode);
2831 /* Below, we must be careful to use copy_rtx on target and subtarget
2832 in intermediate insns, as they may be a subreg rtx, which may not
2835 if (f == 0 && exact_log2 (diff) > 0
2836 /* On EV6, we've got enough shifters to make non-arithmetic shifts
2837 viable over a longer latency cmove. On EV5, the E0 slot is a
2838 scarce resource, and on EV4 shift has the same latency as a cmove. */
2839 && (diff <= 8 || alpha_tune == PROCESSOR_EV6))
2841 tmp = gen_rtx_fmt_ee (code, DImode, cond, const0_rtx);
2842 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (subtarget), tmp));
2844 tmp = gen_rtx_ASHIFT (DImode, copy_rtx (subtarget),
2845 GEN_INT (exact_log2 (t)));
2846 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
2848 else if (f == 0 && t == -1)
2850 tmp = gen_rtx_fmt_ee (code, DImode, cond, const0_rtx);
2851 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (subtarget), tmp));
2853 emit_insn (gen_negdi2 (target, copy_rtx (subtarget)));
2855 else if (diff == 1 || diff == 4 || diff == 8)
2859 tmp = gen_rtx_fmt_ee (code, DImode, cond, const0_rtx);
2860 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (subtarget), tmp));
2863 emit_insn (gen_adddi3 (target, copy_rtx (subtarget), GEN_INT (f)));
2866 add_op = GEN_INT (f);
2867 if (sext_add_operand (add_op, mode))
2869 tmp = gen_rtx_MULT (DImode, copy_rtx (subtarget),
2871 tmp = gen_rtx_PLUS (DImode, tmp, add_op);
2872 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
2884 /* Look up the function X_floating library function name for the
2887 struct GTY(()) xfloating_op
2889 const enum rtx_code code;
2890 const char *const GTY((skip)) osf_func;
2891 const char *const GTY((skip)) vms_func;
2895 static GTY(()) struct xfloating_op xfloating_ops[] =
2897 { PLUS, "_OtsAddX", "OTS$ADD_X", 0 },
2898 { MINUS, "_OtsSubX", "OTS$SUB_X", 0 },
2899 { MULT, "_OtsMulX", "OTS$MUL_X", 0 },
2900 { DIV, "_OtsDivX", "OTS$DIV_X", 0 },
2901 { EQ, "_OtsEqlX", "OTS$EQL_X", 0 },
2902 { NE, "_OtsNeqX", "OTS$NEQ_X", 0 },
2903 { LT, "_OtsLssX", "OTS$LSS_X", 0 },
2904 { LE, "_OtsLeqX", "OTS$LEQ_X", 0 },
2905 { GT, "_OtsGtrX", "OTS$GTR_X", 0 },
2906 { GE, "_OtsGeqX", "OTS$GEQ_X", 0 },
2907 { FIX, "_OtsCvtXQ", "OTS$CVTXQ", 0 },
2908 { FLOAT, "_OtsCvtQX", "OTS$CVTQX", 0 },
2909 { UNSIGNED_FLOAT, "_OtsCvtQUX", "OTS$CVTQUX", 0 },
2910 { FLOAT_EXTEND, "_OtsConvertFloatTX", "OTS$CVT_FLOAT_T_X", 0 },
2911 { FLOAT_TRUNCATE, "_OtsConvertFloatXT", "OTS$CVT_FLOAT_X_T", 0 }
2914 static GTY(()) struct xfloating_op vax_cvt_ops[] =
2916 { FLOAT_EXTEND, "_OtsConvertFloatGX", "OTS$CVT_FLOAT_G_X", 0 },
2917 { FLOAT_TRUNCATE, "_OtsConvertFloatXG", "OTS$CVT_FLOAT_X_G", 0 }
2921 alpha_lookup_xfloating_lib_func (enum rtx_code code)
2923 struct xfloating_op *ops = xfloating_ops;
2924 long n = ARRAY_SIZE (xfloating_ops);
2927 gcc_assert (TARGET_HAS_XFLOATING_LIBS);
2929 /* How irritating. Nothing to key off for the main table. */
2930 if (TARGET_FLOAT_VAX && (code == FLOAT_EXTEND || code == FLOAT_TRUNCATE))
2933 n = ARRAY_SIZE (vax_cvt_ops);
2936 for (i = 0; i < n; ++i, ++ops)
2937 if (ops->code == code)
2939 rtx func = ops->libcall;
2942 func = init_one_libfunc (TARGET_ABI_OPEN_VMS
2943 ? ops->vms_func : ops->osf_func);
2944 ops->libcall = func;
2952 /* Most X_floating operations take the rounding mode as an argument.
2953 Compute that here. */
2956 alpha_compute_xfloating_mode_arg (enum rtx_code code,
2957 enum alpha_fp_rounding_mode round)
2963 case ALPHA_FPRM_NORM:
2966 case ALPHA_FPRM_MINF:
2969 case ALPHA_FPRM_CHOP:
2972 case ALPHA_FPRM_DYN:
2978 /* XXX For reference, round to +inf is mode = 3. */
2981 if (code == FLOAT_TRUNCATE && alpha_fptm == ALPHA_FPTM_N)
2987 /* Emit an X_floating library function call.
2989 Note that these functions do not follow normal calling conventions:
2990 TFmode arguments are passed in two integer registers (as opposed to
2991 indirect); TFmode return values appear in R16+R17.
2993 FUNC is the function to call.
2994 TARGET is where the output belongs.
2995 OPERANDS are the inputs.
2996 NOPERANDS is the count of inputs.
2997 EQUIV is the expression equivalent for the function.
3001 alpha_emit_xfloating_libcall (rtx func, rtx target, rtx operands[],
3002 int noperands, rtx equiv)
3004 rtx usage = NULL_RTX, tmp, reg;
3009 for (i = 0; i < noperands; ++i)
3011 switch (GET_MODE (operands[i]))
3014 reg = gen_rtx_REG (TFmode, regno);
3019 reg = gen_rtx_REG (DFmode, regno + 32);
3024 gcc_assert (CONST_INT_P (operands[i]));
3027 reg = gen_rtx_REG (DImode, regno);
3035 emit_move_insn (reg, operands[i]);
3036 usage = alloc_EXPR_LIST (0, gen_rtx_USE (VOIDmode, reg), usage);
3039 switch (GET_MODE (target))
3042 reg = gen_rtx_REG (TFmode, 16);
3045 reg = gen_rtx_REG (DFmode, 32);
3048 reg = gen_rtx_REG (DImode, 0);
3054 tmp = gen_rtx_MEM (QImode, func);
3055 tmp = emit_call_insn (GEN_CALL_VALUE (reg, tmp, const0_rtx,
3056 const0_rtx, const0_rtx));
3057 CALL_INSN_FUNCTION_USAGE (tmp) = usage;
3058 RTL_CONST_CALL_P (tmp) = 1;
3063 emit_libcall_block (tmp, target, reg, equiv);
3066 /* Emit an X_floating library function call for arithmetic (+,-,*,/). */
3069 alpha_emit_xfloating_arith (enum rtx_code code, rtx operands[])
3073 rtx out_operands[3];
3075 func = alpha_lookup_xfloating_lib_func (code);
3076 mode = alpha_compute_xfloating_mode_arg (code, alpha_fprm);
3078 out_operands[0] = operands[1];
3079 out_operands[1] = operands[2];
3080 out_operands[2] = GEN_INT (mode);
3081 alpha_emit_xfloating_libcall (func, operands[0], out_operands, 3,
3082 gen_rtx_fmt_ee (code, TFmode, operands[1],
3086 /* Emit an X_floating library function call for a comparison. */
3089 alpha_emit_xfloating_compare (enum rtx_code *pcode, rtx op0, rtx op1)
3091 enum rtx_code cmp_code, res_code;
3092 rtx func, out, operands[2], note;
3094 /* X_floating library comparison functions return
3098 Convert the compare against the raw return value. */
3126 func = alpha_lookup_xfloating_lib_func (cmp_code);
3130 out = gen_reg_rtx (DImode);
3132 /* What's actually returned is -1,0,1, not a proper boolean value,
3133 so use an EXPR_LIST as with a generic libcall instead of a
3134 comparison type expression. */
3135 note = gen_rtx_EXPR_LIST (VOIDmode, op1, NULL_RTX);
3136 note = gen_rtx_EXPR_LIST (VOIDmode, op0, note);
3137 note = gen_rtx_EXPR_LIST (VOIDmode, func, note);
3138 alpha_emit_xfloating_libcall (func, out, operands, 2, note);
3143 /* Emit an X_floating library function call for a conversion. */
3146 alpha_emit_xfloating_cvt (enum rtx_code orig_code, rtx operands[])
3148 int noperands = 1, mode;
3149 rtx out_operands[2];
3151 enum rtx_code code = orig_code;
3153 if (code == UNSIGNED_FIX)
3156 func = alpha_lookup_xfloating_lib_func (code);
3158 out_operands[0] = operands[1];
3163 mode = alpha_compute_xfloating_mode_arg (code, ALPHA_FPRM_CHOP);
3164 out_operands[1] = GEN_INT (mode);
3167 case FLOAT_TRUNCATE:
3168 mode = alpha_compute_xfloating_mode_arg (code, alpha_fprm);
3169 out_operands[1] = GEN_INT (mode);
3176 alpha_emit_xfloating_libcall (func, operands[0], out_operands, noperands,
3177 gen_rtx_fmt_e (orig_code,
3178 GET_MODE (operands[0]),
3182 /* Split a TImode or TFmode move from OP[1] to OP[0] into a pair of
3183 DImode moves from OP[2,3] to OP[0,1]. If FIXUP_OVERLAP is true,
3184 guarantee that the sequence
3187 is valid. Naturally, output operand ordering is little-endian.
3188 This is used by *movtf_internal and *movti_internal. */
3191 alpha_split_tmode_pair (rtx operands[4], enum machine_mode mode,
3194 switch (GET_CODE (operands[1]))
3197 operands[3] = gen_rtx_REG (DImode, REGNO (operands[1]) + 1);
3198 operands[2] = gen_rtx_REG (DImode, REGNO (operands[1]));
3202 operands[3] = adjust_address (operands[1], DImode, 8);
3203 operands[2] = adjust_address (operands[1], DImode, 0);
3208 gcc_assert (operands[1] == CONST0_RTX (mode));
3209 operands[2] = operands[3] = const0_rtx;
3216 switch (GET_CODE (operands[0]))
3219 operands[1] = gen_rtx_REG (DImode, REGNO (operands[0]) + 1);
3220 operands[0] = gen_rtx_REG (DImode, REGNO (operands[0]));
3224 operands[1] = adjust_address (operands[0], DImode, 8);
3225 operands[0] = adjust_address (operands[0], DImode, 0);
3232 if (fixup_overlap && reg_overlap_mentioned_p (operands[0], operands[3]))
3235 tmp = operands[0], operands[0] = operands[1], operands[1] = tmp;
3236 tmp = operands[2], operands[2] = operands[3], operands[3] = tmp;
3240 /* Implement negtf2 or abstf2. Op0 is destination, op1 is source,
3241 op2 is a register containing the sign bit, operation is the
3242 logical operation to be performed. */
3245 alpha_split_tfmode_frobsign (rtx operands[3], rtx (*operation) (rtx, rtx, rtx))
3247 rtx high_bit = operands[2];
3251 alpha_split_tmode_pair (operands, TFmode, false);
3253 /* Detect three flavors of operand overlap. */
3255 if (rtx_equal_p (operands[0], operands[2]))
3257 else if (rtx_equal_p (operands[1], operands[2]))
3259 if (rtx_equal_p (operands[0], high_bit))
3266 emit_move_insn (operands[0], operands[2]);
3268 /* ??? If the destination overlaps both source tf and high_bit, then
3269 assume source tf is dead in its entirety and use the other half
3270 for a scratch register. Otherwise "scratch" is just the proper
3271 destination register. */
3272 scratch = operands[move < 2 ? 1 : 3];
3274 emit_insn ((*operation) (scratch, high_bit, operands[3]));
3278 emit_move_insn (operands[0], operands[2]);
3280 emit_move_insn (operands[1], scratch);
3284 /* Use ext[wlq][lh] as the Architecture Handbook describes for extracting
3288 word: ldq_u r1,X(r11) ldq_u r1,X(r11)
3289 ldq_u r2,X+1(r11) ldq_u r2,X+1(r11)
3290 lda r3,X(r11) lda r3,X+2(r11)
3291 extwl r1,r3,r1 extql r1,r3,r1
3292 extwh r2,r3,r2 extqh r2,r3,r2
3293 or r1.r2.r1 or r1,r2,r1
3296 long: ldq_u r1,X(r11) ldq_u r1,X(r11)
3297 ldq_u r2,X+3(r11) ldq_u r2,X+3(r11)
3298 lda r3,X(r11) lda r3,X(r11)
3299 extll r1,r3,r1 extll r1,r3,r1
3300 extlh r2,r3,r2 extlh r2,r3,r2
3301 or r1.r2.r1 addl r1,r2,r1
3303 quad: ldq_u r1,X(r11)
3312 alpha_expand_unaligned_load (rtx tgt, rtx mem, HOST_WIDE_INT size,
3313 HOST_WIDE_INT ofs, int sign)
3315 rtx meml, memh, addr, extl, exth, tmp, mema;
3316 enum machine_mode mode;
3318 if (TARGET_BWX && size == 2)
3320 meml = adjust_address (mem, QImode, ofs);
3321 memh = adjust_address (mem, QImode, ofs+1);
3322 if (BYTES_BIG_ENDIAN)
3323 tmp = meml, meml = memh, memh = tmp;
3324 extl = gen_reg_rtx (DImode);
3325 exth = gen_reg_rtx (DImode);
3326 emit_insn (gen_zero_extendqidi2 (extl, meml));
3327 emit_insn (gen_zero_extendqidi2 (exth, memh));
3328 exth = expand_simple_binop (DImode, ASHIFT, exth, GEN_INT (8),
3329 NULL, 1, OPTAB_LIB_WIDEN);
3330 addr = expand_simple_binop (DImode, IOR, extl, exth,
3331 NULL, 1, OPTAB_LIB_WIDEN);
3333 if (sign && GET_MODE (tgt) != HImode)
3335 addr = gen_lowpart (HImode, addr);
3336 emit_insn (gen_extend_insn (tgt, addr, GET_MODE (tgt), HImode, 0));
3340 if (GET_MODE (tgt) != DImode)
3341 addr = gen_lowpart (GET_MODE (tgt), addr);
3342 emit_move_insn (tgt, addr);
3347 meml = gen_reg_rtx (DImode);
3348 memh = gen_reg_rtx (DImode);
3349 addr = gen_reg_rtx (DImode);
3350 extl = gen_reg_rtx (DImode);
3351 exth = gen_reg_rtx (DImode);
3353 mema = XEXP (mem, 0);
3354 if (GET_CODE (mema) == LO_SUM)
3355 mema = force_reg (Pmode, mema);
3357 /* AND addresses cannot be in any alias set, since they may implicitly
3358 alias surrounding code. Ideally we'd have some alias set that
3359 covered all types except those with alignment 8 or higher. */
3361 tmp = change_address (mem, DImode,
3362 gen_rtx_AND (DImode,
3363 plus_constant (mema, ofs),
3365 set_mem_alias_set (tmp, 0);
3366 emit_move_insn (meml, tmp);
3368 tmp = change_address (mem, DImode,
3369 gen_rtx_AND (DImode,
3370 plus_constant (mema, ofs + size - 1),
3372 set_mem_alias_set (tmp, 0);
3373 emit_move_insn (memh, tmp);
3375 if (WORDS_BIG_ENDIAN && sign && (size == 2 || size == 4))
3377 emit_move_insn (addr, plus_constant (mema, -1));
3379 emit_insn (gen_extqh_be (extl, meml, addr));
3380 emit_insn (gen_extxl_be (exth, memh, GEN_INT (64), addr));
3382 addr = expand_binop (DImode, ior_optab, extl, exth, tgt, 1, OPTAB_WIDEN);
3383 addr = expand_binop (DImode, ashr_optab, addr, GEN_INT (64 - size*8),
3384 addr, 1, OPTAB_WIDEN);
3386 else if (sign && size == 2)
3388 emit_move_insn (addr, plus_constant (mema, ofs+2));
3390 emit_insn (gen_extxl_le (extl, meml, GEN_INT (64), addr));
3391 emit_insn (gen_extqh_le (exth, memh, addr));
3393 /* We must use tgt here for the target. Alpha-vms port fails if we use
3394 addr for the target, because addr is marked as a pointer and combine
3395 knows that pointers are always sign-extended 32-bit values. */
3396 addr = expand_binop (DImode, ior_optab, extl, exth, tgt, 1, OPTAB_WIDEN);
3397 addr = expand_binop (DImode, ashr_optab, addr, GEN_INT (48),
3398 addr, 1, OPTAB_WIDEN);
3402 if (WORDS_BIG_ENDIAN)
3404 emit_move_insn (addr, plus_constant (mema, ofs+size-1));
3408 emit_insn (gen_extwh_be (extl, meml, addr));
3413 emit_insn (gen_extlh_be (extl, meml, addr));
3418 emit_insn (gen_extqh_be (extl, meml, addr));
3425 emit_insn (gen_extxl_be (exth, memh, GEN_INT (size*8), addr));
3429 emit_move_insn (addr, plus_constant (mema, ofs));
3430 emit_insn (gen_extxl_le (extl, meml, GEN_INT (size*8), addr));
3434 emit_insn (gen_extwh_le (exth, memh, addr));
3439 emit_insn (gen_extlh_le (exth, memh, addr));
3444 emit_insn (gen_extqh_le (exth, memh, addr));
3453 addr = expand_binop (mode, ior_optab, gen_lowpart (mode, extl),
3454 gen_lowpart (mode, exth), gen_lowpart (mode, tgt),
3459 emit_move_insn (tgt, gen_lowpart (GET_MODE (tgt), addr));
3462 /* Similarly, use ins and msk instructions to perform unaligned stores. */
3465 alpha_expand_unaligned_store (rtx dst, rtx src,
3466 HOST_WIDE_INT size, HOST_WIDE_INT ofs)
3468 rtx dstl, dsth, addr, insl, insh, meml, memh, dsta;
3470 if (TARGET_BWX && size == 2)
3472 if (src != const0_rtx)
3474 dstl = gen_lowpart (QImode, src);
3475 dsth = expand_simple_binop (DImode, LSHIFTRT, src, GEN_INT (8),
3476 NULL, 1, OPTAB_LIB_WIDEN);
3477 dsth = gen_lowpart (QImode, dsth);
3480 dstl = dsth = const0_rtx;
3482 meml = adjust_address (dst, QImode, ofs);
3483 memh = adjust_address (dst, QImode, ofs+1);
3484 if (BYTES_BIG_ENDIAN)
3485 addr = meml, meml = memh, memh = addr;
3487 emit_move_insn (meml, dstl);
3488 emit_move_insn (memh, dsth);
3492 dstl = gen_reg_rtx (DImode);
3493 dsth = gen_reg_rtx (DImode);
3494 insl = gen_reg_rtx (DImode);
3495 insh = gen_reg_rtx (DImode);
3497 dsta = XEXP (dst, 0);
3498 if (GET_CODE (dsta) == LO_SUM)
3499 dsta = force_reg (Pmode, dsta);
3501 /* AND addresses cannot be in any alias set, since they may implicitly
3502 alias surrounding code. Ideally we'd have some alias set that
3503 covered all types except those with alignment 8 or higher. */
3505 meml = change_address (dst, DImode,
3506 gen_rtx_AND (DImode,
3507 plus_constant (dsta, ofs),
3509 set_mem_alias_set (meml, 0);
3511 memh = change_address (dst, DImode,
3512 gen_rtx_AND (DImode,
3513 plus_constant (dsta, ofs + size - 1),
3515 set_mem_alias_set (memh, 0);
3517 emit_move_insn (dsth, memh);
3518 emit_move_insn (dstl, meml);
3519 if (WORDS_BIG_ENDIAN)
3521 addr = copy_addr_to_reg (plus_constant (dsta, ofs+size-1));
3523 if (src != const0_rtx)
3528 emit_insn (gen_inswl_be (insh, gen_lowpart (HImode,src), addr));
3531 emit_insn (gen_insll_be (insh, gen_lowpart (SImode,src), addr));
3534 emit_insn (gen_insql_be (insh, gen_lowpart (DImode,src), addr));
3537 emit_insn (gen_insxh (insl, gen_lowpart (DImode, src),
3538 GEN_INT (size*8), addr));
3544 emit_insn (gen_mskxl_be (dsth, dsth, GEN_INT (0xffff), addr));
3548 rtx msk = immed_double_const (0xffffffff, 0, DImode);
3549 emit_insn (gen_mskxl_be (dsth, dsth, msk, addr));
3553 emit_insn (gen_mskxl_be (dsth, dsth, constm1_rtx, addr));
3557 emit_insn (gen_mskxh (dstl, dstl, GEN_INT (size*8), addr));
3561 addr = copy_addr_to_reg (plus_constant (dsta, ofs));
3563 if (src != CONST0_RTX (GET_MODE (src)))
3565 emit_insn (gen_insxh (insh, gen_lowpart (DImode, src),
3566 GEN_INT (size*8), addr));
3571 emit_insn (gen_inswl_le (insl, gen_lowpart (HImode, src), addr));
3574 emit_insn (gen_insll_le (insl, gen_lowpart (SImode, src), addr));
3577 emit_insn (gen_insql_le (insl, gen_lowpart (DImode, src), addr));
3582 emit_insn (gen_mskxh (dsth, dsth, GEN_INT (size*8), addr));
3587 emit_insn (gen_mskxl_le (dstl, dstl, GEN_INT (0xffff), addr));
3591 rtx msk = immed_double_const (0xffffffff, 0, DImode);
3592 emit_insn (gen_mskxl_le (dstl, dstl, msk, addr));
3596 emit_insn (gen_mskxl_le (dstl, dstl, constm1_rtx, addr));
3601 if (src != CONST0_RTX (GET_MODE (src)))
3603 dsth = expand_binop (DImode, ior_optab, insh, dsth, dsth, 0, OPTAB_WIDEN);
3604 dstl = expand_binop (DImode, ior_optab, insl, dstl, dstl, 0, OPTAB_WIDEN);
3607 if (WORDS_BIG_ENDIAN)
3609 emit_move_insn (meml, dstl);
3610 emit_move_insn (memh, dsth);
3614 /* Must store high before low for degenerate case of aligned. */
3615 emit_move_insn (memh, dsth);
3616 emit_move_insn (meml, dstl);
3620 /* The block move code tries to maximize speed by separating loads and
3621 stores at the expense of register pressure: we load all of the data
3622 before we store it back out. There are two secondary effects worth
3623 mentioning, that this speeds copying to/from aligned and unaligned
3624 buffers, and that it makes the code significantly easier to write. */
3626 #define MAX_MOVE_WORDS 8
3628 /* Load an integral number of consecutive unaligned quadwords. */
3631 alpha_expand_unaligned_load_words (rtx *out_regs, rtx smem,
3632 HOST_WIDE_INT words, HOST_WIDE_INT ofs)
3634 rtx const im8 = GEN_INT (-8);
3635 rtx const i64 = GEN_INT (64);
3636 rtx ext_tmps[MAX_MOVE_WORDS], data_regs[MAX_MOVE_WORDS+1];
3637 rtx sreg, areg, tmp, smema;
3640 smema = XEXP (smem, 0);
3641 if (GET_CODE (smema) == LO_SUM)
3642 smema = force_reg (Pmode, smema);
3644 /* Generate all the tmp registers we need. */
3645 for (i = 0; i < words; ++i)
3647 data_regs[i] = out_regs[i];
3648 ext_tmps[i] = gen_reg_rtx (DImode);
3650 data_regs[words] = gen_reg_rtx (DImode);
3653 smem = adjust_address (smem, GET_MODE (smem), ofs);
3655 /* Load up all of the source data. */
3656 for (i = 0; i < words; ++i)
3658 tmp = change_address (smem, DImode,
3659 gen_rtx_AND (DImode,
3660 plus_constant (smema, 8*i),
3662 set_mem_alias_set (tmp, 0);
3663 emit_move_insn (data_regs[i], tmp);
3666 tmp = change_address (smem, DImode,
3667 gen_rtx_AND (DImode,
3668 plus_constant (smema, 8*words - 1),
3670 set_mem_alias_set (tmp, 0);
3671 emit_move_insn (data_regs[words], tmp);
3673 /* Extract the half-word fragments. Unfortunately DEC decided to make
3674 extxh with offset zero a noop instead of zeroing the register, so
3675 we must take care of that edge condition ourselves with cmov. */
3677 sreg = copy_addr_to_reg (smema);
3678 areg = expand_binop (DImode, and_optab, sreg, GEN_INT (7), NULL,
3680 if (WORDS_BIG_ENDIAN)
3681 emit_move_insn (sreg, plus_constant (sreg, 7));
3682 for (i = 0; i < words; ++i)
3684 if (WORDS_BIG_ENDIAN)
3686 emit_insn (gen_extqh_be (data_regs[i], data_regs[i], sreg));
3687 emit_insn (gen_extxl_be (ext_tmps[i], data_regs[i+1], i64, sreg));
3691 emit_insn (gen_extxl_le (data_regs[i], data_regs[i], i64, sreg));
3692 emit_insn (gen_extqh_le (ext_tmps[i], data_regs[i+1], sreg));
3694 emit_insn (gen_rtx_SET (VOIDmode, ext_tmps[i],
3695 gen_rtx_IF_THEN_ELSE (DImode,
3696 gen_rtx_EQ (DImode, areg,
3698 const0_rtx, ext_tmps[i])));
3701 /* Merge the half-words into whole words. */
3702 for (i = 0; i < words; ++i)
3704 out_regs[i] = expand_binop (DImode, ior_optab, data_regs[i],
3705 ext_tmps[i], data_regs[i], 1, OPTAB_WIDEN);
3709 /* Store an integral number of consecutive unaligned quadwords. DATA_REGS
3710 may be NULL to store zeros. */
3713 alpha_expand_unaligned_store_words (rtx *data_regs, rtx dmem,
3714 HOST_WIDE_INT words, HOST_WIDE_INT ofs)
3716 rtx const im8 = GEN_INT (-8);
3717 rtx const i64 = GEN_INT (64);
3718 rtx ins_tmps[MAX_MOVE_WORDS];
3719 rtx st_tmp_1, st_tmp_2, dreg;
3720 rtx st_addr_1, st_addr_2, dmema;
3723 dmema = XEXP (dmem, 0);
3724 if (GET_CODE (dmema) == LO_SUM)
3725 dmema = force_reg (Pmode, dmema);
3727 /* Generate all the tmp registers we need. */
3728 if (data_regs != NULL)
3729 for (i = 0; i < words; ++i)
3730 ins_tmps[i] = gen_reg_rtx(DImode);
3731 st_tmp_1 = gen_reg_rtx(DImode);
3732 st_tmp_2 = gen_reg_rtx(DImode);
3735 dmem = adjust_address (dmem, GET_MODE (dmem), ofs);
3737 st_addr_2 = change_address (dmem, DImode,
3738 gen_rtx_AND (DImode,
3739 plus_constant (dmema, words*8 - 1),
3741 set_mem_alias_set (st_addr_2, 0);
3743 st_addr_1 = change_address (dmem, DImode,
3744 gen_rtx_AND (DImode, dmema, im8));
3745 set_mem_alias_set (st_addr_1, 0);
3747 /* Load up the destination end bits. */
3748 emit_move_insn (st_tmp_2, st_addr_2);
3749 emit_move_insn (st_tmp_1, st_addr_1);
3751 /* Shift the input data into place. */
3752 dreg = copy_addr_to_reg (dmema);
3753 if (WORDS_BIG_ENDIAN)
3754 emit_move_insn (dreg, plus_constant (dreg, 7));
3755 if (data_regs != NULL)
3757 for (i = words-1; i >= 0; --i)
3759 if (WORDS_BIG_ENDIAN)
3761 emit_insn (gen_insql_be (ins_tmps[i], data_regs[i], dreg));
3762 emit_insn (gen_insxh (data_regs[i], data_regs[i], i64, dreg));
3766 emit_insn (gen_insxh (ins_tmps[i], data_regs[i], i64, dreg));
3767 emit_insn (gen_insql_le (data_regs[i], data_regs[i], dreg));
3770 for (i = words-1; i > 0; --i)
3772 ins_tmps[i-1] = expand_binop (DImode, ior_optab, data_regs[i],
3773 ins_tmps[i-1], ins_tmps[i-1], 1,
3778 /* Split and merge the ends with the destination data. */
3779 if (WORDS_BIG_ENDIAN)
3781 emit_insn (gen_mskxl_be (st_tmp_2, st_tmp_2, constm1_rtx, dreg));
3782 emit_insn (gen_mskxh (st_tmp_1, st_tmp_1, i64, dreg));
3786 emit_insn (gen_mskxh (st_tmp_2, st_tmp_2, i64, dreg));
3787 emit_insn (gen_mskxl_le (st_tmp_1, st_tmp_1, constm1_rtx, dreg));
3790 if (data_regs != NULL)
3792 st_tmp_2 = expand_binop (DImode, ior_optab, st_tmp_2, ins_tmps[words-1],
3793 st_tmp_2, 1, OPTAB_WIDEN);
3794 st_tmp_1 = expand_binop (DImode, ior_optab, st_tmp_1, data_regs[0],
3795 st_tmp_1, 1, OPTAB_WIDEN);
3799 if (WORDS_BIG_ENDIAN)
3800 emit_move_insn (st_addr_1, st_tmp_1);
3802 emit_move_insn (st_addr_2, st_tmp_2);
3803 for (i = words-1; i > 0; --i)
3805 rtx tmp = change_address (dmem, DImode,
3806 gen_rtx_AND (DImode,
3807 plus_constant(dmema,
3808 WORDS_BIG_ENDIAN ? i*8-1 : i*8),
3810 set_mem_alias_set (tmp, 0);
3811 emit_move_insn (tmp, data_regs ? ins_tmps[i-1] : const0_rtx);
3813 if (WORDS_BIG_ENDIAN)
3814 emit_move_insn (st_addr_2, st_tmp_2);
3816 emit_move_insn (st_addr_1, st_tmp_1);
3820 /* Expand string/block move operations.
3822 operands[0] is the pointer to the destination.
3823 operands[1] is the pointer to the source.
3824 operands[2] is the number of bytes to move.
3825 operands[3] is the alignment. */
3828 alpha_expand_block_move (rtx operands[])
3830 rtx bytes_rtx = operands[2];
3831 rtx align_rtx = operands[3];
3832 HOST_WIDE_INT orig_bytes = INTVAL (bytes_rtx);
3833 HOST_WIDE_INT bytes = orig_bytes;
3834 HOST_WIDE_INT src_align = INTVAL (align_rtx) * BITS_PER_UNIT;
3835 HOST_WIDE_INT dst_align = src_align;
3836 rtx orig_src = operands[1];
3837 rtx orig_dst = operands[0];
3838 rtx data_regs[2 * MAX_MOVE_WORDS + 16];
3840 unsigned int i, words, ofs, nregs = 0;
3842 if (orig_bytes <= 0)
3844 else if (orig_bytes > MAX_MOVE_WORDS * UNITS_PER_WORD)
3847 /* Look for additional alignment information from recorded register info. */
3849 tmp = XEXP (orig_src, 0);
3851 src_align = MAX (src_align, REGNO_POINTER_ALIGN (REGNO (tmp)));
3852 else if (GET_CODE (tmp) == PLUS
3853 && REG_P (XEXP (tmp, 0))
3854 && CONST_INT_P (XEXP (tmp, 1)))
3856 unsigned HOST_WIDE_INT c = INTVAL (XEXP (tmp, 1));
3857 unsigned int a = REGNO_POINTER_ALIGN (REGNO (XEXP (tmp, 0)));
3861 if (a >= 64 && c % 8 == 0)
3863 else if (a >= 32 && c % 4 == 0)
3865 else if (a >= 16 && c % 2 == 0)
3870 tmp = XEXP (orig_dst, 0);
3872 dst_align = MAX (dst_align, REGNO_POINTER_ALIGN (REGNO (tmp)));
3873 else if (GET_CODE (tmp) == PLUS
3874 && REG_P (XEXP (tmp, 0))
3875 && CONST_INT_P (XEXP (tmp, 1)))
3877 unsigned HOST_WIDE_INT c = INTVAL (XEXP (tmp, 1));
3878 unsigned int a = REGNO_POINTER_ALIGN (REGNO (XEXP (tmp, 0)));
3882 if (a >= 64 && c % 8 == 0)
3884 else if (a >= 32 && c % 4 == 0)
3886 else if (a >= 16 && c % 2 == 0)
3892 if (src_align >= 64 && bytes >= 8)
3896 for (i = 0; i < words; ++i)
3897 data_regs[nregs + i] = gen_reg_rtx (DImode);
3899 for (i = 0; i < words; ++i)
3900 emit_move_insn (data_regs[nregs + i],
3901 adjust_address (orig_src, DImode, ofs + i * 8));
3908 if (src_align >= 32 && bytes >= 4)
3912 for (i = 0; i < words; ++i)
3913 data_regs[nregs + i] = gen_reg_rtx (SImode);
3915 for (i = 0; i < words; ++i)
3916 emit_move_insn (data_regs[nregs + i],
3917 adjust_address (orig_src, SImode, ofs + i * 4));
3928 for (i = 0; i < words+1; ++i)
3929 data_regs[nregs + i] = gen_reg_rtx (DImode);
3931 alpha_expand_unaligned_load_words (data_regs + nregs, orig_src,
3939 if (! TARGET_BWX && bytes >= 4)
3941 data_regs[nregs++] = tmp = gen_reg_rtx (SImode);
3942 alpha_expand_unaligned_load (tmp, orig_src, 4, ofs, 0);
3949 if (src_align >= 16)
3952 data_regs[nregs++] = tmp = gen_reg_rtx (HImode);
3953 emit_move_insn (tmp, adjust_address (orig_src, HImode, ofs));
3956 } while (bytes >= 2);
3958 else if (! TARGET_BWX)
3960 data_regs[nregs++] = tmp = gen_reg_rtx (HImode);
3961 alpha_expand_unaligned_load (tmp, orig_src, 2, ofs, 0);
3969 data_regs[nregs++] = tmp = gen_reg_rtx (QImode);
3970 emit_move_insn (tmp, adjust_address (orig_src, QImode, ofs));
3975 gcc_assert (nregs <= ARRAY_SIZE (data_regs));
3977 /* Now save it back out again. */
3981 /* Write out the data in whatever chunks reading the source allowed. */
3982 if (dst_align >= 64)
3984 while (i < nregs && GET_MODE (data_regs[i]) == DImode)
3986 emit_move_insn (adjust_address (orig_dst, DImode, ofs),
3993 if (dst_align >= 32)
3995 /* If the source has remaining DImode regs, write them out in
3997 while (i < nregs && GET_MODE (data_regs[i]) == DImode)
3999 tmp = expand_binop (DImode, lshr_optab, data_regs[i], GEN_INT (32),
4000 NULL_RTX, 1, OPTAB_WIDEN);
4002 emit_move_insn (adjust_address (orig_dst, SImode, ofs),
4003 gen_lowpart (SImode, data_regs[i]));
4004 emit_move_insn (adjust_address (orig_dst, SImode, ofs + 4),
4005 gen_lowpart (SImode, tmp));
4010 while (i < nregs && GET_MODE (data_regs[i]) == SImode)
4012 emit_move_insn (adjust_address (orig_dst, SImode, ofs),
4019 if (i < nregs && GET_MODE (data_regs[i]) == DImode)
4021 /* Write out a remaining block of words using unaligned methods. */
4023 for (words = 1; i + words < nregs; words++)
4024 if (GET_MODE (data_regs[i + words]) != DImode)
4028 alpha_expand_unaligned_store (orig_dst, data_regs[i], 8, ofs);
4030 alpha_expand_unaligned_store_words (data_regs + i, orig_dst,
4037 /* Due to the above, this won't be aligned. */
4038 /* ??? If we have more than one of these, consider constructing full
4039 words in registers and using alpha_expand_unaligned_store_words. */
4040 while (i < nregs && GET_MODE (data_regs[i]) == SImode)
4042 alpha_expand_unaligned_store (orig_dst, data_regs[i], 4, ofs);
4047 if (dst_align >= 16)
4048 while (i < nregs && GET_MODE (data_regs[i]) == HImode)
4050 emit_move_insn (adjust_address (orig_dst, HImode, ofs), data_regs[i]);
4055 while (i < nregs && GET_MODE (data_regs[i]) == HImode)
4057 alpha_expand_unaligned_store (orig_dst, data_regs[i], 2, ofs);
4062 /* The remainder must be byte copies. */
4065 gcc_assert (GET_MODE (data_regs[i]) == QImode);
4066 emit_move_insn (adjust_address (orig_dst, QImode, ofs), data_regs[i]);
4075 alpha_expand_block_clear (rtx operands[])
4077 rtx bytes_rtx = operands[1];
4078 rtx align_rtx = operands[3];
4079 HOST_WIDE_INT orig_bytes = INTVAL (bytes_rtx);
4080 HOST_WIDE_INT bytes = orig_bytes;
4081 HOST_WIDE_INT align = INTVAL (align_rtx) * BITS_PER_UNIT;
4082 HOST_WIDE_INT alignofs = 0;
4083 rtx orig_dst = operands[0];
4085 int i, words, ofs = 0;
4087 if (orig_bytes <= 0)
4089 if (orig_bytes > MAX_MOVE_WORDS * UNITS_PER_WORD)
4092 /* Look for stricter alignment. */
4093 tmp = XEXP (orig_dst, 0);
4095 align = MAX (align, REGNO_POINTER_ALIGN (REGNO (tmp)));
4096 else if (GET_CODE (tmp) == PLUS
4097 && REG_P (XEXP (tmp, 0))
4098 && CONST_INT_P (XEXP (tmp, 1)))
4100 HOST_WIDE_INT c = INTVAL (XEXP (tmp, 1));
4101 int a = REGNO_POINTER_ALIGN (REGNO (XEXP (tmp, 0)));
4106 align = a, alignofs = 8 - c % 8;
4108 align = a, alignofs = 4 - c % 4;
4110 align = a, alignofs = 2 - c % 2;
4114 /* Handle an unaligned prefix first. */
4118 #if HOST_BITS_PER_WIDE_INT >= 64
4119 /* Given that alignofs is bounded by align, the only time BWX could
4120 generate three stores is for a 7 byte fill. Prefer two individual
4121 stores over a load/mask/store sequence. */
4122 if ((!TARGET_BWX || alignofs == 7)
4124 && !(alignofs == 4 && bytes >= 4))
4126 enum machine_mode mode = (align >= 64 ? DImode : SImode);
4127 int inv_alignofs = (align >= 64 ? 8 : 4) - alignofs;
4131 mem = adjust_address (orig_dst, mode, ofs - inv_alignofs);
4132 set_mem_alias_set (mem, 0);
4134 mask = ~(~(HOST_WIDE_INT)0 << (inv_alignofs * 8));
4135 if (bytes < alignofs)
4137 mask |= ~(HOST_WIDE_INT)0 << ((inv_alignofs + bytes) * 8);
4148 tmp = expand_binop (mode, and_optab, mem, GEN_INT (mask),
4149 NULL_RTX, 1, OPTAB_WIDEN);
4151 emit_move_insn (mem, tmp);
4155 if (TARGET_BWX && (alignofs & 1) && bytes >= 1)
4157 emit_move_insn (adjust_address (orig_dst, QImode, ofs), const0_rtx);
4162 if (TARGET_BWX && align >= 16 && (alignofs & 3) == 2 && bytes >= 2)
4164 emit_move_insn (adjust_address (orig_dst, HImode, ofs), const0_rtx);
4169 if (alignofs == 4 && bytes >= 4)
4171 emit_move_insn (adjust_address (orig_dst, SImode, ofs), const0_rtx);
4177 /* If we've not used the extra lead alignment information by now,
4178 we won't be able to. Downgrade align to match what's left over. */
4181 alignofs = alignofs & -alignofs;
4182 align = MIN (align, alignofs * BITS_PER_UNIT);
4186 /* Handle a block of contiguous long-words. */
4188 if (align >= 64 && bytes >= 8)
4192 for (i = 0; i < words; ++i)
4193 emit_move_insn (adjust_address (orig_dst, DImode, ofs + i * 8),
4200 /* If the block is large and appropriately aligned, emit a single
4201 store followed by a sequence of stq_u insns. */
4203 if (align >= 32 && bytes > 16)
4207 emit_move_insn (adjust_address (orig_dst, SImode, ofs), const0_rtx);
4211 orig_dsta = XEXP (orig_dst, 0);
4212 if (GET_CODE (orig_dsta) == LO_SUM)
4213 orig_dsta = force_reg (Pmode, orig_dsta);
4216 for (i = 0; i < words; ++i)
4219 = change_address (orig_dst, DImode,
4220 gen_rtx_AND (DImode,
4221 plus_constant (orig_dsta, ofs + i*8),
4223 set_mem_alias_set (mem, 0);
4224 emit_move_insn (mem, const0_rtx);
4227 /* Depending on the alignment, the first stq_u may have overlapped
4228 with the initial stl, which means that the last stq_u didn't
4229 write as much as it would appear. Leave those questionable bytes
4231 bytes -= words * 8 - 4;
4232 ofs += words * 8 - 4;
4235 /* Handle a smaller block of aligned words. */
4237 if ((align >= 64 && bytes == 4)
4238 || (align == 32 && bytes >= 4))
4242 for (i = 0; i < words; ++i)
4243 emit_move_insn (adjust_address (orig_dst, SImode, ofs + i * 4),
4250 /* An unaligned block uses stq_u stores for as many as possible. */
4256 alpha_expand_unaligned_store_words (NULL, orig_dst, words, ofs);
4262 /* Next clean up any trailing pieces. */
4264 #if HOST_BITS_PER_WIDE_INT >= 64
4265 /* Count the number of bits in BYTES for which aligned stores could
4268 for (i = (TARGET_BWX ? 1 : 4); i * BITS_PER_UNIT <= align ; i <<= 1)
4272 /* If we have appropriate alignment (and it wouldn't take too many
4273 instructions otherwise), mask out the bytes we need. */
4274 if (TARGET_BWX ? words > 2 : bytes > 0)
4281 mem = adjust_address (orig_dst, DImode, ofs);
4282 set_mem_alias_set (mem, 0);
4284 mask = ~(HOST_WIDE_INT)0 << (bytes * 8);
4286 tmp = expand_binop (DImode, and_optab, mem, GEN_INT (mask),
4287 NULL_RTX, 1, OPTAB_WIDEN);
4289 emit_move_insn (mem, tmp);
4292 else if (align >= 32 && bytes < 4)
4297 mem = adjust_address (orig_dst, SImode, ofs);
4298 set_mem_alias_set (mem, 0);
4300 mask = ~(HOST_WIDE_INT)0 << (bytes * 8);
4302 tmp = expand_binop (SImode, and_optab, mem, GEN_INT (mask),
4303 NULL_RTX, 1, OPTAB_WIDEN);
4305 emit_move_insn (mem, tmp);
4311 if (!TARGET_BWX && bytes >= 4)
4313 alpha_expand_unaligned_store (orig_dst, const0_rtx, 4, ofs);
4323 emit_move_insn (adjust_address (orig_dst, HImode, ofs),
4327 } while (bytes >= 2);
4329 else if (! TARGET_BWX)
4331 alpha_expand_unaligned_store (orig_dst, const0_rtx, 2, ofs);
4339 emit_move_insn (adjust_address (orig_dst, QImode, ofs), const0_rtx);
4347 /* Returns a mask so that zap(x, value) == x & mask. */
4350 alpha_expand_zap_mask (HOST_WIDE_INT value)
4355 if (HOST_BITS_PER_WIDE_INT >= 64)
4357 HOST_WIDE_INT mask = 0;
4359 for (i = 7; i >= 0; --i)
4362 if (!((value >> i) & 1))
4366 result = gen_int_mode (mask, DImode);
4370 HOST_WIDE_INT mask_lo = 0, mask_hi = 0;
4372 gcc_assert (HOST_BITS_PER_WIDE_INT == 32);
4374 for (i = 7; i >= 4; --i)
4377 if (!((value >> i) & 1))
4381 for (i = 3; i >= 0; --i)
4384 if (!((value >> i) & 1))
4388 result = immed_double_const (mask_lo, mask_hi, DImode);
4395 alpha_expand_builtin_vector_binop (rtx (*gen) (rtx, rtx, rtx),
4396 enum machine_mode mode,
4397 rtx op0, rtx op1, rtx op2)
4399 op0 = gen_lowpart (mode, op0);
4401 if (op1 == const0_rtx)
4402 op1 = CONST0_RTX (mode);
4404 op1 = gen_lowpart (mode, op1);
4406 if (op2 == const0_rtx)
4407 op2 = CONST0_RTX (mode);
4409 op2 = gen_lowpart (mode, op2);
4411 emit_insn ((*gen) (op0, op1, op2));
4414 /* A subroutine of the atomic operation splitters. Jump to LABEL if
4415 COND is true. Mark the jump as unlikely to be taken. */
4418 emit_unlikely_jump (rtx cond, rtx label)
4420 rtx very_unlikely = GEN_INT (REG_BR_PROB_BASE / 100 - 1);
4423 x = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, label, pc_rtx);
4424 x = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, x));
4425 add_reg_note (x, REG_BR_PROB, very_unlikely);
4428 /* A subroutine of the atomic operation splitters. Emit a load-locked
4429 instruction in MODE. */
4432 emit_load_locked (enum machine_mode mode, rtx reg, rtx mem)
4434 rtx (*fn) (rtx, rtx) = NULL;
4436 fn = gen_load_locked_si;
4437 else if (mode == DImode)
4438 fn = gen_load_locked_di;
4439 emit_insn (fn (reg, mem));
4442 /* A subroutine of the atomic operation splitters. Emit a store-conditional
4443 instruction in MODE. */
4446 emit_store_conditional (enum machine_mode mode, rtx res, rtx mem, rtx val)
4448 rtx (*fn) (rtx, rtx, rtx) = NULL;
4450 fn = gen_store_conditional_si;
4451 else if (mode == DImode)
4452 fn = gen_store_conditional_di;
4453 emit_insn (fn (res, mem, val));
4456 /* A subroutine of the atomic operation splitters. Emit an insxl
4457 instruction in MODE. */
4460 emit_insxl (enum machine_mode mode, rtx op1, rtx op2)
4462 rtx ret = gen_reg_rtx (DImode);
4463 rtx (*fn) (rtx, rtx, rtx);
4465 if (WORDS_BIG_ENDIAN)
4479 /* The insbl and inswl patterns require a register operand. */
4480 op1 = force_reg (mode, op1);
4481 emit_insn (fn (ret, op1, op2));
4486 /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation
4487 to perform. MEM is the memory on which to operate. VAL is the second
4488 operand of the binary operator. BEFORE and AFTER are optional locations to
4489 return the value of MEM either before of after the operation. SCRATCH is
4490 a scratch register. */
4493 alpha_split_atomic_op (enum rtx_code code, rtx mem, rtx val,
4494 rtx before, rtx after, rtx scratch)
4496 enum machine_mode mode = GET_MODE (mem);
4497 rtx label, x, cond = gen_rtx_REG (DImode, REGNO (scratch));
4499 emit_insn (gen_memory_barrier ());
4501 label = gen_label_rtx ();
4503 label = gen_rtx_LABEL_REF (DImode, label);
4507 emit_load_locked (mode, before, mem);
4511 x = gen_rtx_AND (mode, before, val);
4512 emit_insn (gen_rtx_SET (VOIDmode, val, x));
4514 x = gen_rtx_NOT (mode, val);
4517 x = gen_rtx_fmt_ee (code, mode, before, val);
4519 emit_insn (gen_rtx_SET (VOIDmode, after, copy_rtx (x)));
4520 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
4522 emit_store_conditional (mode, cond, mem, scratch);
4524 x = gen_rtx_EQ (DImode, cond, const0_rtx);
4525 emit_unlikely_jump (x, label);
4527 emit_insn (gen_memory_barrier ());
4530 /* Expand a compare and swap operation. */
4533 alpha_split_compare_and_swap (rtx retval, rtx mem, rtx oldval, rtx newval,
4536 enum machine_mode mode = GET_MODE (mem);
4537 rtx label1, label2, x, cond = gen_lowpart (DImode, scratch);
4539 emit_insn (gen_memory_barrier ());
4541 label1 = gen_rtx_LABEL_REF (DImode, gen_label_rtx ());
4542 label2 = gen_rtx_LABEL_REF (DImode, gen_label_rtx ());
4543 emit_label (XEXP (label1, 0));
4545 emit_load_locked (mode, retval, mem);
4547 x = gen_lowpart (DImode, retval);
4548 if (oldval == const0_rtx)
4549 x = gen_rtx_NE (DImode, x, const0_rtx);
4552 x = gen_rtx_EQ (DImode, x, oldval);
4553 emit_insn (gen_rtx_SET (VOIDmode, cond, x));
4554 x = gen_rtx_EQ (DImode, cond, const0_rtx);
4556 emit_unlikely_jump (x, label2);
4558 emit_move_insn (scratch, newval);
4559 emit_store_conditional (mode, cond, mem, scratch);
4561 x = gen_rtx_EQ (DImode, cond, const0_rtx);
4562 emit_unlikely_jump (x, label1);
4564 emit_insn (gen_memory_barrier ());
4565 emit_label (XEXP (label2, 0));
4569 alpha_expand_compare_and_swap_12 (rtx dst, rtx mem, rtx oldval, rtx newval)
4571 enum machine_mode mode = GET_MODE (mem);
4572 rtx addr, align, wdst;
4573 rtx (*fn5) (rtx, rtx, rtx, rtx, rtx);
4575 addr = force_reg (DImode, XEXP (mem, 0));
4576 align = expand_simple_binop (Pmode, AND, addr, GEN_INT (-8),
4577 NULL_RTX, 1, OPTAB_DIRECT);
4579 oldval = convert_modes (DImode, mode, oldval, 1);
4580 newval = emit_insxl (mode, newval, addr);
4582 wdst = gen_reg_rtx (DImode);
4584 fn5 = gen_sync_compare_and_swapqi_1;
4586 fn5 = gen_sync_compare_and_swaphi_1;
4587 emit_insn (fn5 (wdst, addr, oldval, newval, align));
4589 emit_move_insn (dst, gen_lowpart (mode, wdst));
4593 alpha_split_compare_and_swap_12 (enum machine_mode mode, rtx dest, rtx addr,
4594 rtx oldval, rtx newval, rtx align,
4595 rtx scratch, rtx cond)
4597 rtx label1, label2, mem, width, mask, x;
4599 mem = gen_rtx_MEM (DImode, align);
4600 MEM_VOLATILE_P (mem) = 1;
4602 emit_insn (gen_memory_barrier ());
4603 label1 = gen_rtx_LABEL_REF (DImode, gen_label_rtx ());
4604 label2 = gen_rtx_LABEL_REF (DImode, gen_label_rtx ());
4605 emit_label (XEXP (label1, 0));
4607 emit_load_locked (DImode, scratch, mem);
4609 width = GEN_INT (GET_MODE_BITSIZE (mode));
4610 mask = GEN_INT (mode == QImode ? 0xff : 0xffff);
4611 if (WORDS_BIG_ENDIAN)
4612 emit_insn (gen_extxl_be (dest, scratch, width, addr));
4614 emit_insn (gen_extxl_le (dest, scratch, width, addr));
4616 if (oldval == const0_rtx)
4617 x = gen_rtx_NE (DImode, dest, const0_rtx);
4620 x = gen_rtx_EQ (DImode, dest, oldval);
4621 emit_insn (gen_rtx_SET (VOIDmode, cond, x));
4622 x = gen_rtx_EQ (DImode, cond, const0_rtx);
4624 emit_unlikely_jump (x, label2);
4626 if (WORDS_BIG_ENDIAN)
4627 emit_insn (gen_mskxl_be (scratch, scratch, mask, addr));
4629 emit_insn (gen_mskxl_le (scratch, scratch, mask, addr));
4630 emit_insn (gen_iordi3 (scratch, scratch, newval));
4632 emit_store_conditional (DImode, scratch, mem, scratch);
4634 x = gen_rtx_EQ (DImode, scratch, const0_rtx);
4635 emit_unlikely_jump (x, label1);
4637 emit_insn (gen_memory_barrier ());
4638 emit_label (XEXP (label2, 0));
4641 /* Expand an atomic exchange operation. */
4644 alpha_split_lock_test_and_set (rtx retval, rtx mem, rtx val, rtx scratch)
4646 enum machine_mode mode = GET_MODE (mem);
4647 rtx label, x, cond = gen_lowpart (DImode, scratch);
4649 label = gen_rtx_LABEL_REF (DImode, gen_label_rtx ());
4650 emit_label (XEXP (label, 0));
4652 emit_load_locked (mode, retval, mem);
4653 emit_move_insn (scratch, val);
4654 emit_store_conditional (mode, cond, mem, scratch);
4656 x = gen_rtx_EQ (DImode, cond, const0_rtx);
4657 emit_unlikely_jump (x, label);
4659 emit_insn (gen_memory_barrier ());
4663 alpha_expand_lock_test_and_set_12 (rtx dst, rtx mem, rtx val)
4665 enum machine_mode mode = GET_MODE (mem);
4666 rtx addr, align, wdst;
4667 rtx (*fn4) (rtx, rtx, rtx, rtx);
4669 /* Force the address into a register. */
4670 addr = force_reg (DImode, XEXP (mem, 0));
4672 /* Align it to a multiple of 8. */
4673 align = expand_simple_binop (Pmode, AND, addr, GEN_INT (-8),
4674 NULL_RTX, 1, OPTAB_DIRECT);
4676 /* Insert val into the correct byte location within the word. */
4677 val = emit_insxl (mode, val, addr);
4679 wdst = gen_reg_rtx (DImode);
4681 fn4 = gen_sync_lock_test_and_setqi_1;
4683 fn4 = gen_sync_lock_test_and_sethi_1;
4684 emit_insn (fn4 (wdst, addr, val, align));
4686 emit_move_insn (dst, gen_lowpart (mode, wdst));
4690 alpha_split_lock_test_and_set_12 (enum machine_mode mode, rtx dest, rtx addr,
4691 rtx val, rtx align, rtx scratch)
4693 rtx label, mem, width, mask, x;
4695 mem = gen_rtx_MEM (DImode, align);
4696 MEM_VOLATILE_P (mem) = 1;
4698 label = gen_rtx_LABEL_REF (DImode, gen_label_rtx ());
4699 emit_label (XEXP (label, 0));
4701 emit_load_locked (DImode, scratch, mem);
4703 width = GEN_INT (GET_MODE_BITSIZE (mode));
4704 mask = GEN_INT (mode == QImode ? 0xff : 0xffff);
4705 if (WORDS_BIG_ENDIAN)
4707 emit_insn (gen_extxl_be (dest, scratch, width, addr));
4708 emit_insn (gen_mskxl_be (scratch, scratch, mask, addr));
4712 emit_insn (gen_extxl_le (dest, scratch, width, addr));
4713 emit_insn (gen_mskxl_le (scratch, scratch, mask, addr));
4715 emit_insn (gen_iordi3 (scratch, scratch, val));
4717 emit_store_conditional (DImode, scratch, mem, scratch);
4719 x = gen_rtx_EQ (DImode, scratch, const0_rtx);
4720 emit_unlikely_jump (x, label);
4722 emit_insn (gen_memory_barrier ());
4725 /* Adjust the cost of a scheduling dependency. Return the new cost of
4726 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
4729 alpha_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
4731 enum attr_type insn_type, dep_insn_type;
4733 /* If the dependence is an anti-dependence, there is no cost. For an
4734 output dependence, there is sometimes a cost, but it doesn't seem
4735 worth handling those few cases. */
4736 if (REG_NOTE_KIND (link) != 0)
4739 /* If we can't recognize the insns, we can't really do anything. */
4740 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
4743 insn_type = get_attr_type (insn);
4744 dep_insn_type = get_attr_type (dep_insn);
4746 /* Bring in the user-defined memory latency. */
4747 if (dep_insn_type == TYPE_ILD
4748 || dep_insn_type == TYPE_FLD
4749 || dep_insn_type == TYPE_LDSYM)
4750 cost += alpha_memory_latency-1;
4752 /* Everything else handled in DFA bypasses now. */
4757 /* The number of instructions that can be issued per cycle. */
4760 alpha_issue_rate (void)
4762 return (alpha_tune == PROCESSOR_EV4 ? 2 : 4);
4765 /* How many alternative schedules to try. This should be as wide as the
4766 scheduling freedom in the DFA, but no wider. Making this value too
4767 large results extra work for the scheduler.
4769 For EV4, loads can be issued to either IB0 or IB1, thus we have 2
4770 alternative schedules. For EV5, we can choose between E0/E1 and
4771 FA/FM. For EV6, an arithmetic insn can be issued to U0/U1/L0/L1. */
4774 alpha_multipass_dfa_lookahead (void)
4776 return (alpha_tune == PROCESSOR_EV6 ? 4 : 2);
4779 /* Machine-specific function data. */
4781 struct GTY(()) machine_function
4784 /* List of call information words for calls from this function. */
4785 struct rtx_def *first_ciw;
4786 struct rtx_def *last_ciw;
4789 /* List of deferred case vectors. */
4790 struct rtx_def *addr_list;
4793 const char *some_ld_name;
4795 /* For TARGET_LD_BUGGY_LDGP. */
4796 struct rtx_def *gp_save_rtx;
4798 /* For VMS condition handlers. */
4799 bool uses_condition_handler;
4802 /* How to allocate a 'struct machine_function'. */
4804 static struct machine_function *
4805 alpha_init_machine_status (void)
4807 return ((struct machine_function *)
4808 ggc_alloc_cleared (sizeof (struct machine_function)));
4811 /* Support for frame based VMS condition handlers. */
4813 /* A VMS condition handler may be established for a function with a call to
4814 __builtin_establish_vms_condition_handler, and cancelled with a call to
4815 __builtin_revert_vms_condition_handler.
4817 The VMS Condition Handling Facility knows about the existence of a handler
4818 from the procedure descriptor .handler field. As the VMS native compilers,
4819 we store the user specified handler's address at a fixed location in the
4820 stack frame and point the procedure descriptor at a common wrapper which
4821 fetches the real handler's address and issues an indirect call.
4823 The indirection wrapper is "__gcc_shell_handler", provided by libgcc.
4825 We force the procedure kind to PT_STACK, and the fixed frame location is
4826 fp+8, just before the register save area. We use the handler_data field in
4827 the procedure descriptor to state the fp offset at which the installed
4828 handler address can be found. */
4830 #define VMS_COND_HANDLER_FP_OFFSET 8
4832 /* Expand code to store the currently installed user VMS condition handler
4833 into TARGET and install HANDLER as the new condition handler. */
4836 alpha_expand_builtin_establish_vms_condition_handler (rtx target, rtx handler)
4838 rtx handler_slot_address
4839 = plus_constant (hard_frame_pointer_rtx, VMS_COND_HANDLER_FP_OFFSET);
4842 = gen_rtx_MEM (DImode, handler_slot_address);
4844 emit_move_insn (target, handler_slot);
4845 emit_move_insn (handler_slot, handler);
4847 /* Notify the start/prologue/epilogue emitters that the condition handler
4848 slot is needed. In addition to reserving the slot space, this will force
4849 the procedure kind to PT_STACK so ensure that the hard_frame_pointer_rtx
4850 use above is correct. */
4851 cfun->machine->uses_condition_handler = true;
4854 /* Expand code to store the current VMS condition handler into TARGET and
4858 alpha_expand_builtin_revert_vms_condition_handler (rtx target)
4860 /* We implement this by establishing a null condition handler, with the tiny
4861 side effect of setting uses_condition_handler. This is a little bit
4862 pessimistic if no actual builtin_establish call is ever issued, which is
4863 not a real problem and expected never to happen anyway. */
4865 alpha_expand_builtin_establish_vms_condition_handler (target, const0_rtx);
4868 /* Functions to save and restore alpha_return_addr_rtx. */
4870 /* Start the ball rolling with RETURN_ADDR_RTX. */
4873 alpha_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
4878 return get_hard_reg_initial_val (Pmode, REG_RA);
4881 /* Return or create a memory slot containing the gp value for the current
4882 function. Needed only if TARGET_LD_BUGGY_LDGP. */
4885 alpha_gp_save_rtx (void)
4887 rtx seq, m = cfun->machine->gp_save_rtx;
4893 m = assign_stack_local (DImode, UNITS_PER_WORD, BITS_PER_WORD);
4894 m = validize_mem (m);
4895 emit_move_insn (m, pic_offset_table_rtx);
4900 /* We used to simply emit the sequence after entry_of_function.
4901 However this breaks the CFG if the first instruction in the
4902 first block is not the NOTE_INSN_BASIC_BLOCK, for example a
4903 label. Emit the sequence properly on the edge. We are only
4904 invoked from dw2_build_landing_pads and finish_eh_generation
4905 will call commit_edge_insertions thanks to a kludge. */
4906 insert_insn_on_edge (seq, single_succ_edge (ENTRY_BLOCK_PTR));
4908 cfun->machine->gp_save_rtx = m;
4915 alpha_ra_ever_killed (void)
4919 if (!has_hard_reg_initial_val (Pmode, REG_RA))
4920 return (int)df_regs_ever_live_p (REG_RA);
4922 push_topmost_sequence ();
4924 pop_topmost_sequence ();
4926 return reg_set_between_p (gen_rtx_REG (Pmode, REG_RA), top, NULL_RTX);
4930 /* Return the trap mode suffix applicable to the current
4931 instruction, or NULL. */
4934 get_trap_mode_suffix (void)
4936 enum attr_trap_suffix s = get_attr_trap_suffix (current_output_insn);
4940 case TRAP_SUFFIX_NONE:
4943 case TRAP_SUFFIX_SU:
4944 if (alpha_fptm >= ALPHA_FPTM_SU)
4948 case TRAP_SUFFIX_SUI:
4949 if (alpha_fptm >= ALPHA_FPTM_SUI)
4953 case TRAP_SUFFIX_V_SV:
4961 case ALPHA_FPTM_SUI:
4967 case TRAP_SUFFIX_V_SV_SVI:
4976 case ALPHA_FPTM_SUI:
4983 case TRAP_SUFFIX_U_SU_SUI:
4992 case ALPHA_FPTM_SUI:
5005 /* Return the rounding mode suffix applicable to the current
5006 instruction, or NULL. */
5009 get_round_mode_suffix (void)
5011 enum attr_round_suffix s = get_attr_round_suffix (current_output_insn);
5015 case ROUND_SUFFIX_NONE:
5017 case ROUND_SUFFIX_NORMAL:
5020 case ALPHA_FPRM_NORM:
5022 case ALPHA_FPRM_MINF:
5024 case ALPHA_FPRM_CHOP:
5026 case ALPHA_FPRM_DYN:
5033 case ROUND_SUFFIX_C:
5042 /* Locate some local-dynamic symbol still in use by this function
5043 so that we can print its name in some movdi_er_tlsldm pattern. */
5046 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
5050 if (GET_CODE (x) == SYMBOL_REF
5051 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
5053 cfun->machine->some_ld_name = XSTR (x, 0);
5061 get_some_local_dynamic_name (void)
5065 if (cfun->machine->some_ld_name)
5066 return cfun->machine->some_ld_name;
5068 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
5070 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
5071 return cfun->machine->some_ld_name;
5076 /* Print an operand. Recognize special options, documented below. */
5079 print_operand (FILE *file, rtx x, int code)
5086 /* Print the assembler name of the current function. */
5087 assemble_name (file, alpha_fnname);
5091 assemble_name (file, get_some_local_dynamic_name ());
5096 const char *trap = get_trap_mode_suffix ();
5097 const char *round = get_round_mode_suffix ();
5100 fprintf (file, (TARGET_AS_SLASH_BEFORE_SUFFIX ? "/%s%s" : "%s%s"),
5101 (trap ? trap : ""), (round ? round : ""));
5106 /* Generates single precision instruction suffix. */
5107 fputc ((TARGET_FLOAT_VAX ? 'f' : 's'), file);
5111 /* Generates double precision instruction suffix. */
5112 fputc ((TARGET_FLOAT_VAX ? 'g' : 't'), file);
5116 if (alpha_this_literal_sequence_number == 0)
5117 alpha_this_literal_sequence_number = alpha_next_sequence_number++;
5118 fprintf (file, "%d", alpha_this_literal_sequence_number);
5122 if (alpha_this_gpdisp_sequence_number == 0)
5123 alpha_this_gpdisp_sequence_number = alpha_next_sequence_number++;
5124 fprintf (file, "%d", alpha_this_gpdisp_sequence_number);
5128 if (GET_CODE (x) == HIGH)
5129 output_addr_const (file, XEXP (x, 0));
5131 output_operand_lossage ("invalid %%H value");
5138 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSGD_CALL)
5140 x = XVECEXP (x, 0, 0);
5141 lituse = "lituse_tlsgd";
5143 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSLDM_CALL)
5145 x = XVECEXP (x, 0, 0);
5146 lituse = "lituse_tlsldm";
5148 else if (CONST_INT_P (x))
5149 lituse = "lituse_jsr";
5152 output_operand_lossage ("invalid %%J value");
5156 if (x != const0_rtx)
5157 fprintf (file, "\t\t!%s!%d", lituse, (int) INTVAL (x));
5165 #ifdef HAVE_AS_JSRDIRECT_RELOCS
5166 lituse = "lituse_jsrdirect";
5168 lituse = "lituse_jsr";
5171 gcc_assert (INTVAL (x) != 0);
5172 fprintf (file, "\t\t!%s!%d", lituse, (int) INTVAL (x));
5176 /* If this operand is the constant zero, write it as "$31". */
5178 fprintf (file, "%s", reg_names[REGNO (x)]);
5179 else if (x == CONST0_RTX (GET_MODE (x)))
5180 fprintf (file, "$31");
5182 output_operand_lossage ("invalid %%r value");
5186 /* Similar, but for floating-point. */
5188 fprintf (file, "%s", reg_names[REGNO (x)]);
5189 else if (x == CONST0_RTX (GET_MODE (x)))
5190 fprintf (file, "$f31");
5192 output_operand_lossage ("invalid %%R value");
5196 /* Write the 1's complement of a constant. */
5197 if (!CONST_INT_P (x))
5198 output_operand_lossage ("invalid %%N value");
5200 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INTVAL (x));
5204 /* Write 1 << C, for a constant C. */
5205 if (!CONST_INT_P (x))
5206 output_operand_lossage ("invalid %%P value");
5208 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (HOST_WIDE_INT) 1 << INTVAL (x));
5212 /* Write the high-order 16 bits of a constant, sign-extended. */
5213 if (!CONST_INT_P (x))
5214 output_operand_lossage ("invalid %%h value");
5216 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) >> 16);
5220 /* Write the low-order 16 bits of a constant, sign-extended. */
5221 if (!CONST_INT_P (x))
5222 output_operand_lossage ("invalid %%L value");
5224 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5225 (INTVAL (x) & 0xffff) - 2 * (INTVAL (x) & 0x8000));
5229 /* Write mask for ZAP insn. */
5230 if (GET_CODE (x) == CONST_DOUBLE)
5232 HOST_WIDE_INT mask = 0;
5233 HOST_WIDE_INT value;
5235 value = CONST_DOUBLE_LOW (x);
5236 for (i = 0; i < HOST_BITS_PER_WIDE_INT / HOST_BITS_PER_CHAR;
5241 value = CONST_DOUBLE_HIGH (x);
5242 for (i = 0; i < HOST_BITS_PER_WIDE_INT / HOST_BITS_PER_CHAR;
5245 mask |= (1 << (i + sizeof (int)));
5247 fprintf (file, HOST_WIDE_INT_PRINT_DEC, mask & 0xff);
5250 else if (CONST_INT_P (x))
5252 HOST_WIDE_INT mask = 0, value = INTVAL (x);
5254 for (i = 0; i < 8; i++, value >>= 8)
5258 fprintf (file, HOST_WIDE_INT_PRINT_DEC, mask);
5261 output_operand_lossage ("invalid %%m value");
5265 /* 'b', 'w', 'l', or 'q' as the value of the constant. */
5266 if (!CONST_INT_P (x)
5267 || (INTVAL (x) != 8 && INTVAL (x) != 16
5268 && INTVAL (x) != 32 && INTVAL (x) != 64))
5269 output_operand_lossage ("invalid %%M value");
5271 fprintf (file, "%s",
5272 (INTVAL (x) == 8 ? "b"
5273 : INTVAL (x) == 16 ? "w"
5274 : INTVAL (x) == 32 ? "l"
5279 /* Similar, except do it from the mask. */
5280 if (CONST_INT_P (x))
5282 HOST_WIDE_INT value = INTVAL (x);
5289 if (value == 0xffff)
5294 if (value == 0xffffffff)
5305 else if (HOST_BITS_PER_WIDE_INT == 32
5306 && GET_CODE (x) == CONST_DOUBLE
5307 && CONST_DOUBLE_LOW (x) == 0xffffffff
5308 && CONST_DOUBLE_HIGH (x) == 0)
5313 output_operand_lossage ("invalid %%U value");
5317 /* Write the constant value divided by 8 for little-endian mode or
5318 (56 - value) / 8 for big-endian mode. */
5320 if (!CONST_INT_P (x)
5321 || (unsigned HOST_WIDE_INT) INTVAL (x) >= (WORDS_BIG_ENDIAN
5324 || (INTVAL (x) & 7) != 0)
5325 output_operand_lossage ("invalid %%s value");
5327 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5329 ? (56 - INTVAL (x)) / 8
5334 /* Same, except compute (64 - c) / 8 */
5336 if (!CONST_INT_P (x)
5337 && (unsigned HOST_WIDE_INT) INTVAL (x) >= 64
5338 && (INTVAL (x) & 7) != 8)
5339 output_operand_lossage ("invalid %%s value");
5341 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (64 - INTVAL (x)) / 8);
5346 /* On Unicos/Mk systems: use a DEX expression if the symbol
5347 clashes with a register name. */
5348 int dex = unicosmk_need_dex (x);
5350 fprintf (file, "DEX(%d)", dex);
5352 output_addr_const (file, x);
5356 case 'C': case 'D': case 'c': case 'd':
5357 /* Write out comparison name. */
5359 enum rtx_code c = GET_CODE (x);
5361 if (!COMPARISON_P (x))
5362 output_operand_lossage ("invalid %%C value");
5364 else if (code == 'D')
5365 c = reverse_condition (c);
5366 else if (code == 'c')
5367 c = swap_condition (c);
5368 else if (code == 'd')
5369 c = swap_condition (reverse_condition (c));
5372 fprintf (file, "ule");
5374 fprintf (file, "ult");
5375 else if (c == UNORDERED)
5376 fprintf (file, "un");
5378 fprintf (file, "%s", GET_RTX_NAME (c));
5383 /* Write the divide or modulus operator. */
5384 switch (GET_CODE (x))
5387 fprintf (file, "div%s", GET_MODE (x) == SImode ? "l" : "q");
5390 fprintf (file, "div%su", GET_MODE (x) == SImode ? "l" : "q");
5393 fprintf (file, "rem%s", GET_MODE (x) == SImode ? "l" : "q");
5396 fprintf (file, "rem%su", GET_MODE (x) == SImode ? "l" : "q");
5399 output_operand_lossage ("invalid %%E value");
5405 /* Write "_u" for unaligned access. */
5406 if (MEM_P (x) && GET_CODE (XEXP (x, 0)) == AND)
5407 fprintf (file, "_u");
5412 fprintf (file, "%s", reg_names[REGNO (x)]);
5414 output_address (XEXP (x, 0));
5415 else if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == UNSPEC)
5417 switch (XINT (XEXP (x, 0), 1))
5421 output_addr_const (file, XVECEXP (XEXP (x, 0), 0, 0));
5424 output_operand_lossage ("unknown relocation unspec");
5429 output_addr_const (file, x);
5433 output_operand_lossage ("invalid %%xn code");
5438 print_operand_address (FILE *file, rtx addr)
5441 HOST_WIDE_INT offset = 0;
5443 if (GET_CODE (addr) == AND)
5444 addr = XEXP (addr, 0);
5446 if (GET_CODE (addr) == PLUS
5447 && CONST_INT_P (XEXP (addr, 1)))
5449 offset = INTVAL (XEXP (addr, 1));
5450 addr = XEXP (addr, 0);
5453 if (GET_CODE (addr) == LO_SUM)
5455 const char *reloc16, *reloclo;
5456 rtx op1 = XEXP (addr, 1);
5458 if (GET_CODE (op1) == CONST && GET_CODE (XEXP (op1, 0)) == UNSPEC)
5460 op1 = XEXP (op1, 0);
5461 switch (XINT (op1, 1))
5465 reloclo = (alpha_tls_size == 16 ? "dtprel" : "dtprello");
5469 reloclo = (alpha_tls_size == 16 ? "tprel" : "tprello");
5472 output_operand_lossage ("unknown relocation unspec");
5476 output_addr_const (file, XVECEXP (op1, 0, 0));
5481 reloclo = "gprellow";
5482 output_addr_const (file, op1);
5486 fprintf (file, "+" HOST_WIDE_INT_PRINT_DEC, offset);
5488 addr = XEXP (addr, 0);
5489 switch (GET_CODE (addr))
5492 basereg = REGNO (addr);
5496 basereg = subreg_regno (addr);
5503 fprintf (file, "($%d)\t\t!%s", basereg,
5504 (basereg == 29 ? reloc16 : reloclo));
5508 switch (GET_CODE (addr))
5511 basereg = REGNO (addr);
5515 basereg = subreg_regno (addr);
5519 offset = INTVAL (addr);
5522 #if TARGET_ABI_OPEN_VMS
5524 fprintf (file, "%s", XSTR (addr, 0));
5528 gcc_assert (GET_CODE (XEXP (addr, 0)) == PLUS
5529 && GET_CODE (XEXP (XEXP (addr, 0), 0)) == SYMBOL_REF);
5530 fprintf (file, "%s+" HOST_WIDE_INT_PRINT_DEC,
5531 XSTR (XEXP (XEXP (addr, 0), 0), 0),
5532 INTVAL (XEXP (XEXP (addr, 0), 1)));
5540 fprintf (file, HOST_WIDE_INT_PRINT_DEC "($%d)", offset, basereg);
5543 /* Emit RTL insns to initialize the variable parts of a trampoline at
5544 M_TRAMP. FNDECL is target function's decl. CHAIN_VALUE is an rtx
5545 for the static chain value for the function. */
5548 alpha_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
5550 rtx fnaddr, mem, word1, word2;
5552 fnaddr = XEXP (DECL_RTL (fndecl), 0);
5554 #ifdef POINTERS_EXTEND_UNSIGNED
5555 fnaddr = convert_memory_address (Pmode, fnaddr);
5556 chain_value = convert_memory_address (Pmode, chain_value);
5559 if (TARGET_ABI_OPEN_VMS)
5564 /* Construct the name of the trampoline entry point. */
5565 fnname = XSTR (fnaddr, 0);
5566 trname = (char *) alloca (strlen (fnname) + 5);
5567 strcpy (trname, fnname);
5568 strcat (trname, "..tr");
5569 fnname = ggc_alloc_string (trname, strlen (trname) + 1);
5570 word2 = gen_rtx_SYMBOL_REF (Pmode, fnname);
5572 /* Trampoline (or "bounded") procedure descriptor is constructed from
5573 the function's procedure descriptor with certain fields zeroed IAW
5574 the VMS calling standard. This is stored in the first quadword. */
5575 word1 = force_reg (DImode, gen_const_mem (DImode, fnaddr));
5576 word1 = expand_and (DImode, word1, GEN_INT (0xffff0fff0000fff0), NULL);
5580 /* These 4 instructions are:
5585 We don't bother setting the HINT field of the jump; the nop
5586 is merely there for padding. */
5587 word1 = GEN_INT (0xa77b0010a43b0018);
5588 word2 = GEN_INT (0x47ff041f6bfb0000);
5591 /* Store the first two words, as computed above. */
5592 mem = adjust_address (m_tramp, DImode, 0);
5593 emit_move_insn (mem, word1);
5594 mem = adjust_address (m_tramp, DImode, 8);
5595 emit_move_insn (mem, word2);
5597 /* Store function address and static chain value. */
5598 mem = adjust_address (m_tramp, Pmode, 16);
5599 emit_move_insn (mem, fnaddr);
5600 mem = adjust_address (m_tramp, Pmode, 24);
5601 emit_move_insn (mem, chain_value);
5603 if (!TARGET_ABI_OPEN_VMS)
5605 emit_insn (gen_imb ());
5606 #ifdef ENABLE_EXECUTE_STACK
5607 emit_library_call (init_one_libfunc ("__enable_execute_stack"),
5608 LCT_NORMAL, VOIDmode, 1, XEXP (m_tramp, 0), Pmode);
5613 /* Determine where to put an argument to a function.
5614 Value is zero to push the argument on the stack,
5615 or a hard register in which to store the argument.
5617 MODE is the argument's machine mode.
5618 TYPE is the data type of the argument (as a tree).
5619 This is null for libcalls where that information may
5621 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5622 the preceding args and about the function being called.
5623 NAMED is nonzero if this argument is a named parameter
5624 (otherwise it is an extra parameter matching an ellipsis).
5626 On Alpha the first 6 words of args are normally in registers
5627 and the rest are pushed. */
5630 function_arg (CUMULATIVE_ARGS cum, enum machine_mode mode, tree type,
5631 int named ATTRIBUTE_UNUSED)
5636 /* Don't get confused and pass small structures in FP registers. */
5637 if (type && AGGREGATE_TYPE_P (type))
5641 #ifdef ENABLE_CHECKING
5642 /* With alpha_split_complex_arg, we shouldn't see any raw complex
5644 gcc_assert (!COMPLEX_MODE_P (mode));
5647 /* Set up defaults for FP operands passed in FP registers, and
5648 integral operands passed in integer registers. */
5649 if (TARGET_FPREGS && GET_MODE_CLASS (mode) == MODE_FLOAT)
5655 /* ??? Irritatingly, the definition of CUMULATIVE_ARGS is different for
5656 the three platforms, so we can't avoid conditional compilation. */
5657 #if TARGET_ABI_OPEN_VMS
5659 if (mode == VOIDmode)
5660 return alpha_arg_info_reg_val (cum);
5662 num_args = cum.num_args;
5664 || targetm.calls.must_pass_in_stack (mode, type))
5667 #elif TARGET_ABI_UNICOSMK
5671 /* If this is the last argument, generate the call info word (CIW). */
5672 /* ??? We don't include the caller's line number in the CIW because
5673 I don't know how to determine it if debug infos are turned off. */
5674 if (mode == VOIDmode)
5683 for (i = 0; i < cum.num_reg_words && i < 5; i++)
5684 if (cum.reg_args_type[i])
5685 lo |= (1 << (7 - i));
5687 if (cum.num_reg_words == 6 && cum.reg_args_type[5])
5690 lo |= cum.num_reg_words;
5692 #if HOST_BITS_PER_WIDE_INT == 32
5693 hi = (cum.num_args << 20) | cum.num_arg_words;
5695 lo = lo | ((HOST_WIDE_INT) cum.num_args << 52)
5696 | ((HOST_WIDE_INT) cum.num_arg_words << 32);
5699 ciw = immed_double_const (lo, hi, DImode);
5701 return gen_rtx_UNSPEC (DImode, gen_rtvec (1, ciw),
5702 UNSPEC_UMK_LOAD_CIW);
5705 size = ALPHA_ARG_SIZE (mode, type, named);
5706 num_args = cum.num_reg_words;
5708 || cum.num_reg_words + size > 6
5709 || targetm.calls.must_pass_in_stack (mode, type))
5711 else if (type && TYPE_MODE (type) == BLKmode)
5715 reg1 = gen_rtx_REG (DImode, num_args + 16);
5716 reg1 = gen_rtx_EXPR_LIST (DImode, reg1, const0_rtx);
5718 /* The argument fits in two registers. Note that we still need to
5719 reserve a register for empty structures. */
5723 return gen_rtx_PARALLEL (mode, gen_rtvec (1, reg1));
5726 reg2 = gen_rtx_REG (DImode, num_args + 17);
5727 reg2 = gen_rtx_EXPR_LIST (DImode, reg2, GEN_INT (8));
5728 return gen_rtx_PARALLEL (mode, gen_rtvec (2, reg1, reg2));
5732 #elif TARGET_ABI_OSF
5738 /* VOID is passed as a special flag for "last argument". */
5739 if (type == void_type_node)
5741 else if (targetm.calls.must_pass_in_stack (mode, type))
5745 #error Unhandled ABI
5748 return gen_rtx_REG (mode, num_args + basereg);
5752 alpha_arg_partial_bytes (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
5753 enum machine_mode mode ATTRIBUTE_UNUSED,
5754 tree type ATTRIBUTE_UNUSED,
5755 bool named ATTRIBUTE_UNUSED)
5759 #if TARGET_ABI_OPEN_VMS
5760 if (cum->num_args < 6
5761 && 6 < cum->num_args + ALPHA_ARG_SIZE (mode, type, named))
5762 words = 6 - cum->num_args;
5763 #elif TARGET_ABI_UNICOSMK
5764 /* Never any split arguments. */
5765 #elif TARGET_ABI_OSF
5766 if (*cum < 6 && 6 < *cum + ALPHA_ARG_SIZE (mode, type, named))
5769 #error Unhandled ABI
5772 return words * UNITS_PER_WORD;
5776 /* Return true if TYPE must be returned in memory, instead of in registers. */
5779 alpha_return_in_memory (const_tree type, const_tree fndecl ATTRIBUTE_UNUSED)
5781 enum machine_mode mode = VOIDmode;
5786 mode = TYPE_MODE (type);
5788 /* All aggregates are returned in memory, except on OpenVMS where
5789 records that fit 64 bits should be returned by immediate value
5790 as required by section 3.8.7.1 of the OpenVMS Calling Standard. */
5791 if (TARGET_ABI_OPEN_VMS
5792 && TREE_CODE (type) != ARRAY_TYPE
5793 && (unsigned HOST_WIDE_INT) int_size_in_bytes(type) <= 8)
5796 if (AGGREGATE_TYPE_P (type))
5800 size = GET_MODE_SIZE (mode);
5801 switch (GET_MODE_CLASS (mode))
5803 case MODE_VECTOR_FLOAT:
5804 /* Pass all float vectors in memory, like an aggregate. */
5807 case MODE_COMPLEX_FLOAT:
5808 /* We judge complex floats on the size of their element,
5809 not the size of the whole type. */
5810 size = GET_MODE_UNIT_SIZE (mode);
5815 case MODE_COMPLEX_INT:
5816 case MODE_VECTOR_INT:
5820 /* ??? We get called on all sorts of random stuff from
5821 aggregate_value_p. We must return something, but it's not
5822 clear what's safe to return. Pretend it's a struct I
5827 /* Otherwise types must fit in one register. */
5828 return size > UNITS_PER_WORD;
5831 /* Return true if TYPE should be passed by invisible reference. */
5834 alpha_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED,
5835 enum machine_mode mode,
5836 const_tree type ATTRIBUTE_UNUSED,
5837 bool named ATTRIBUTE_UNUSED)
5839 return mode == TFmode || mode == TCmode;
5842 /* Define how to find the value returned by a function. VALTYPE is the
5843 data type of the value (as a tree). If the precise function being
5844 called is known, FUNC is its FUNCTION_DECL; otherwise, FUNC is 0.
5845 MODE is set instead of VALTYPE for libcalls.
5847 On Alpha the value is found in $0 for integer functions and
5848 $f0 for floating-point functions. */
5851 function_value (const_tree valtype, const_tree func ATTRIBUTE_UNUSED,
5852 enum machine_mode mode)
5854 unsigned int regnum, dummy;
5855 enum mode_class mclass;
5857 gcc_assert (!valtype || !alpha_return_in_memory (valtype, func));
5860 mode = TYPE_MODE (valtype);
5862 mclass = GET_MODE_CLASS (mode);
5866 /* Do the same thing as PROMOTE_MODE except for libcalls on VMS,
5867 where we have them returning both SImode and DImode. */
5868 if (!(TARGET_ABI_OPEN_VMS && valtype && AGGREGATE_TYPE_P (valtype)))
5869 PROMOTE_MODE (mode, dummy, valtype);
5872 case MODE_COMPLEX_INT:
5873 case MODE_VECTOR_INT:
5881 case MODE_COMPLEX_FLOAT:
5883 enum machine_mode cmode = GET_MODE_INNER (mode);
5885 return gen_rtx_PARALLEL
5888 gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (cmode, 32),
5890 gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (cmode, 33),
5891 GEN_INT (GET_MODE_SIZE (cmode)))));
5895 /* We should only reach here for BLKmode on VMS. */
5896 gcc_assert (TARGET_ABI_OPEN_VMS && mode == BLKmode);
5904 return gen_rtx_REG (mode, regnum);
5907 /* TCmode complex values are passed by invisible reference. We
5908 should not split these values. */
5911 alpha_split_complex_arg (const_tree type)
5913 return TYPE_MODE (type) != TCmode;
5917 alpha_build_builtin_va_list (void)
5919 tree base, ofs, space, record, type_decl;
5921 if (TARGET_ABI_OPEN_VMS || TARGET_ABI_UNICOSMK)
5922 return ptr_type_node;
5924 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
5925 type_decl = build_decl (BUILTINS_LOCATION,
5926 TYPE_DECL, get_identifier ("__va_list_tag"), record);
5927 TREE_CHAIN (record) = type_decl;
5928 TYPE_NAME (record) = type_decl;
5930 /* C++? SET_IS_AGGR_TYPE (record, 1); */
5932 /* Dummy field to prevent alignment warnings. */
5933 space = build_decl (BUILTINS_LOCATION,
5934 FIELD_DECL, NULL_TREE, integer_type_node);
5935 DECL_FIELD_CONTEXT (space) = record;
5936 DECL_ARTIFICIAL (space) = 1;
5937 DECL_IGNORED_P (space) = 1;
5939 ofs = build_decl (BUILTINS_LOCATION,
5940 FIELD_DECL, get_identifier ("__offset"),
5942 DECL_FIELD_CONTEXT (ofs) = record;
5943 TREE_CHAIN (ofs) = space;
5945 base = build_decl (BUILTINS_LOCATION,
5946 FIELD_DECL, get_identifier ("__base"),
5948 DECL_FIELD_CONTEXT (base) = record;
5949 TREE_CHAIN (base) = ofs;
5951 TYPE_FIELDS (record) = base;
5952 layout_type (record);
5954 va_list_gpr_counter_field = ofs;
5959 /* Helper function for alpha_stdarg_optimize_hook. Skip over casts
5960 and constant additions. */
5963 va_list_skip_additions (tree lhs)
5969 enum tree_code code;
5971 stmt = SSA_NAME_DEF_STMT (lhs);
5973 if (gimple_code (stmt) == GIMPLE_PHI)
5976 if (!is_gimple_assign (stmt)
5977 || gimple_assign_lhs (stmt) != lhs)
5980 if (TREE_CODE (gimple_assign_rhs1 (stmt)) != SSA_NAME)
5982 code = gimple_assign_rhs_code (stmt);
5983 if (!CONVERT_EXPR_CODE_P (code)
5984 && ((code != PLUS_EXPR && code != POINTER_PLUS_EXPR)
5985 || TREE_CODE (gimple_assign_rhs2 (stmt)) != INTEGER_CST
5986 || !host_integerp (gimple_assign_rhs2 (stmt), 1)))
5989 lhs = gimple_assign_rhs1 (stmt);
5993 /* Check if LHS = RHS statement is
5994 LHS = *(ap.__base + ap.__offset + cst)
5997 + ((ap.__offset + cst <= 47)
5998 ? ap.__offset + cst - 48 : ap.__offset + cst) + cst2).
5999 If the former, indicate that GPR registers are needed,
6000 if the latter, indicate that FPR registers are needed.
6002 Also look for LHS = (*ptr).field, where ptr is one of the forms
6005 On alpha, cfun->va_list_gpr_size is used as size of the needed
6006 regs and cfun->va_list_fpr_size is a bitmask, bit 0 set if GPR
6007 registers are needed and bit 1 set if FPR registers are needed.
6008 Return true if va_list references should not be scanned for the
6009 current statement. */
6012 alpha_stdarg_optimize_hook (struct stdarg_info *si, const_gimple stmt)
6014 tree base, offset, rhs;
6018 if (get_gimple_rhs_class (gimple_assign_rhs_code (stmt))
6019 != GIMPLE_SINGLE_RHS)
6022 rhs = gimple_assign_rhs1 (stmt);
6023 while (handled_component_p (rhs))
6024 rhs = TREE_OPERAND (rhs, 0);
6025 if (TREE_CODE (rhs) != INDIRECT_REF
6026 || TREE_CODE (TREE_OPERAND (rhs, 0)) != SSA_NAME)
6029 stmt = va_list_skip_additions (TREE_OPERAND (rhs, 0));
6031 || !is_gimple_assign (stmt)
6032 || gimple_assign_rhs_code (stmt) != POINTER_PLUS_EXPR)
6035 base = gimple_assign_rhs1 (stmt);
6036 if (TREE_CODE (base) == SSA_NAME)
6038 base_stmt = va_list_skip_additions (base);
6040 && is_gimple_assign (base_stmt)
6041 && gimple_assign_rhs_code (base_stmt) == COMPONENT_REF)
6042 base = gimple_assign_rhs1 (base_stmt);
6045 if (TREE_CODE (base) != COMPONENT_REF
6046 || TREE_OPERAND (base, 1) != TYPE_FIELDS (va_list_type_node))
6048 base = gimple_assign_rhs2 (stmt);
6049 if (TREE_CODE (base) == SSA_NAME)
6051 base_stmt = va_list_skip_additions (base);
6053 && is_gimple_assign (base_stmt)
6054 && gimple_assign_rhs_code (base_stmt) == COMPONENT_REF)
6055 base = gimple_assign_rhs1 (base_stmt);
6058 if (TREE_CODE (base) != COMPONENT_REF
6059 || TREE_OPERAND (base, 1) != TYPE_FIELDS (va_list_type_node))
6065 base = get_base_address (base);
6066 if (TREE_CODE (base) != VAR_DECL
6067 || !bitmap_bit_p (si->va_list_vars, DECL_UID (base)))
6070 offset = gimple_op (stmt, 1 + offset_arg);
6071 if (TREE_CODE (offset) == SSA_NAME)
6073 gimple offset_stmt = va_list_skip_additions (offset);
6076 && gimple_code (offset_stmt) == GIMPLE_PHI)
6079 gimple arg1_stmt, arg2_stmt;
6081 enum tree_code code1, code2;
6083 if (gimple_phi_num_args (offset_stmt) != 2)
6087 = va_list_skip_additions (gimple_phi_arg_def (offset_stmt, 0));
6089 = va_list_skip_additions (gimple_phi_arg_def (offset_stmt, 1));
6090 if (arg1_stmt == NULL
6091 || !is_gimple_assign (arg1_stmt)
6092 || arg2_stmt == NULL
6093 || !is_gimple_assign (arg2_stmt))
6096 code1 = gimple_assign_rhs_code (arg1_stmt);
6097 code2 = gimple_assign_rhs_code (arg2_stmt);
6098 if (code1 == COMPONENT_REF
6099 && (code2 == MINUS_EXPR || code2 == PLUS_EXPR))
6101 else if (code2 == COMPONENT_REF
6102 && (code1 == MINUS_EXPR || code1 == PLUS_EXPR))
6104 gimple tem = arg1_stmt;
6106 arg1_stmt = arg2_stmt;
6112 if (!host_integerp (gimple_assign_rhs2 (arg2_stmt), 0))
6115 sub = tree_low_cst (gimple_assign_rhs2 (arg2_stmt), 0);
6116 if (code2 == MINUS_EXPR)
6118 if (sub < -48 || sub > -32)
6121 arg1 = gimple_assign_rhs1 (arg1_stmt);
6122 arg2 = gimple_assign_rhs1 (arg2_stmt);
6123 if (TREE_CODE (arg2) == SSA_NAME)
6125 arg2_stmt = va_list_skip_additions (arg2);
6126 if (arg2_stmt == NULL
6127 || !is_gimple_assign (arg2_stmt)
6128 || gimple_assign_rhs_code (arg2_stmt) != COMPONENT_REF)
6130 arg2 = gimple_assign_rhs1 (arg2_stmt);
6135 if (TREE_CODE (arg1) != COMPONENT_REF
6136 || TREE_OPERAND (arg1, 1) != va_list_gpr_counter_field
6137 || get_base_address (arg1) != base)
6140 /* Need floating point regs. */
6141 cfun->va_list_fpr_size |= 2;
6145 && is_gimple_assign (offset_stmt)
6146 && gimple_assign_rhs_code (offset_stmt) == COMPONENT_REF)
6147 offset = gimple_assign_rhs1 (offset_stmt);
6149 if (TREE_CODE (offset) != COMPONENT_REF
6150 || TREE_OPERAND (offset, 1) != va_list_gpr_counter_field
6151 || get_base_address (offset) != base)
6154 /* Need general regs. */
6155 cfun->va_list_fpr_size |= 1;
6159 si->va_list_escapes = true;
6164 /* Perform any needed actions needed for a function that is receiving a
6165 variable number of arguments. */
6168 alpha_setup_incoming_varargs (CUMULATIVE_ARGS *pcum, enum machine_mode mode,
6169 tree type, int *pretend_size, int no_rtl)
6171 CUMULATIVE_ARGS cum = *pcum;
6173 /* Skip the current argument. */
6174 FUNCTION_ARG_ADVANCE (cum, mode, type, 1);
6176 #if TARGET_ABI_UNICOSMK
6177 /* On Unicos/Mk, the standard subroutine __T3E_MISMATCH stores all register
6178 arguments on the stack. Unfortunately, it doesn't always store the first
6179 one (i.e. the one that arrives in $16 or $f16). This is not a problem
6180 with stdargs as we always have at least one named argument there. */
6181 if (cum.num_reg_words < 6)
6185 emit_insn (gen_umk_mismatch_args (GEN_INT (cum.num_reg_words)));
6186 emit_insn (gen_arg_home_umk ());
6190 #elif TARGET_ABI_OPEN_VMS
6191 /* For VMS, we allocate space for all 6 arg registers plus a count.
6193 However, if NO registers need to be saved, don't allocate any space.
6194 This is not only because we won't need the space, but because AP
6195 includes the current_pretend_args_size and we don't want to mess up
6196 any ap-relative addresses already made. */
6197 if (cum.num_args < 6)
6201 emit_move_insn (gen_rtx_REG (DImode, 1), virtual_incoming_args_rtx);
6202 emit_insn (gen_arg_home ());
6204 *pretend_size = 7 * UNITS_PER_WORD;
6207 /* On OSF/1 and friends, we allocate space for all 12 arg registers, but
6208 only push those that are remaining. However, if NO registers need to
6209 be saved, don't allocate any space. This is not only because we won't
6210 need the space, but because AP includes the current_pretend_args_size
6211 and we don't want to mess up any ap-relative addresses already made.
6213 If we are not to use the floating-point registers, save the integer
6214 registers where we would put the floating-point registers. This is
6215 not the most efficient way to implement varargs with just one register
6216 class, but it isn't worth doing anything more efficient in this rare
6224 alias_set_type set = get_varargs_alias_set ();
6227 count = cfun->va_list_gpr_size / UNITS_PER_WORD;
6228 if (count > 6 - cum)
6231 /* Detect whether integer registers or floating-point registers
6232 are needed by the detected va_arg statements. See above for
6233 how these values are computed. Note that the "escape" value
6234 is VA_LIST_MAX_FPR_SIZE, which is 255, which has both of
6236 gcc_assert ((VA_LIST_MAX_FPR_SIZE & 3) == 3);
6238 if (cfun->va_list_fpr_size & 1)
6240 tmp = gen_rtx_MEM (BLKmode,
6241 plus_constant (virtual_incoming_args_rtx,
6242 (cum + 6) * UNITS_PER_WORD));
6243 MEM_NOTRAP_P (tmp) = 1;
6244 set_mem_alias_set (tmp, set);
6245 move_block_from_reg (16 + cum, tmp, count);
6248 if (cfun->va_list_fpr_size & 2)
6250 tmp = gen_rtx_MEM (BLKmode,
6251 plus_constant (virtual_incoming_args_rtx,
6252 cum * UNITS_PER_WORD));
6253 MEM_NOTRAP_P (tmp) = 1;
6254 set_mem_alias_set (tmp, set);
6255 move_block_from_reg (16 + cum + TARGET_FPREGS*32, tmp, count);
6258 *pretend_size = 12 * UNITS_PER_WORD;
6263 alpha_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
6265 HOST_WIDE_INT offset;
6266 tree t, offset_field, base_field;
6268 if (TREE_CODE (TREE_TYPE (valist)) == ERROR_MARK)
6271 if (TARGET_ABI_UNICOSMK)
6272 std_expand_builtin_va_start (valist, nextarg);
6274 /* For Unix, TARGET_SETUP_INCOMING_VARARGS moves the starting address base
6275 up by 48, storing fp arg registers in the first 48 bytes, and the
6276 integer arg registers in the next 48 bytes. This is only done,
6277 however, if any integer registers need to be stored.
6279 If no integer registers need be stored, then we must subtract 48
6280 in order to account for the integer arg registers which are counted
6281 in argsize above, but which are not actually stored on the stack.
6282 Must further be careful here about structures straddling the last
6283 integer argument register; that futzes with pretend_args_size,
6284 which changes the meaning of AP. */
6287 offset = TARGET_ABI_OPEN_VMS ? UNITS_PER_WORD : 6 * UNITS_PER_WORD;
6289 offset = -6 * UNITS_PER_WORD + crtl->args.pretend_args_size;
6291 if (TARGET_ABI_OPEN_VMS)
6293 t = make_tree (ptr_type_node, virtual_incoming_args_rtx);
6294 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t,
6295 size_int (offset + NUM_ARGS * UNITS_PER_WORD));
6296 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
6297 TREE_SIDE_EFFECTS (t) = 1;
6298 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6302 base_field = TYPE_FIELDS (TREE_TYPE (valist));
6303 offset_field = TREE_CHAIN (base_field);
6305 base_field = build3 (COMPONENT_REF, TREE_TYPE (base_field),
6306 valist, base_field, NULL_TREE);
6307 offset_field = build3 (COMPONENT_REF, TREE_TYPE (offset_field),
6308 valist, offset_field, NULL_TREE);
6310 t = make_tree (ptr_type_node, virtual_incoming_args_rtx);
6311 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t,
6313 t = build2 (MODIFY_EXPR, TREE_TYPE (base_field), base_field, t);
6314 TREE_SIDE_EFFECTS (t) = 1;
6315 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6317 t = build_int_cst (NULL_TREE, NUM_ARGS * UNITS_PER_WORD);
6318 t = build2 (MODIFY_EXPR, TREE_TYPE (offset_field), offset_field, t);
6319 TREE_SIDE_EFFECTS (t) = 1;
6320 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6325 alpha_gimplify_va_arg_1 (tree type, tree base, tree offset,
6328 tree type_size, ptr_type, addend, t, addr;
6329 gimple_seq internal_post;
6331 /* If the type could not be passed in registers, skip the block
6332 reserved for the registers. */
6333 if (targetm.calls.must_pass_in_stack (TYPE_MODE (type), type))
6335 t = build_int_cst (TREE_TYPE (offset), 6*8);
6336 gimplify_assign (offset,
6337 build2 (MAX_EXPR, TREE_TYPE (offset), offset, t),
6342 ptr_type = build_pointer_type (type);
6344 if (TREE_CODE (type) == COMPLEX_TYPE)
6346 tree real_part, imag_part, real_temp;
6348 real_part = alpha_gimplify_va_arg_1 (TREE_TYPE (type), base,
6351 /* Copy the value into a new temporary, lest the formal temporary
6352 be reused out from under us. */
6353 real_temp = get_initialized_tmp_var (real_part, pre_p, NULL);
6355 imag_part = alpha_gimplify_va_arg_1 (TREE_TYPE (type), base,
6358 return build2 (COMPLEX_EXPR, type, real_temp, imag_part);
6360 else if (TREE_CODE (type) == REAL_TYPE)
6362 tree fpaddend, cond, fourtyeight;
6364 fourtyeight = build_int_cst (TREE_TYPE (addend), 6*8);
6365 fpaddend = fold_build2 (MINUS_EXPR, TREE_TYPE (addend),
6366 addend, fourtyeight);
6367 cond = fold_build2 (LT_EXPR, boolean_type_node, addend, fourtyeight);
6368 addend = fold_build3 (COND_EXPR, TREE_TYPE (addend), cond,
6372 /* Build the final address and force that value into a temporary. */
6373 addr = build2 (POINTER_PLUS_EXPR, ptr_type, fold_convert (ptr_type, base),
6374 fold_convert (sizetype, addend));
6375 internal_post = NULL;
6376 gimplify_expr (&addr, pre_p, &internal_post, is_gimple_val, fb_rvalue);
6377 gimple_seq_add_seq (pre_p, internal_post);
6379 /* Update the offset field. */
6380 type_size = TYPE_SIZE_UNIT (TYPE_MAIN_VARIANT (type));
6381 if (type_size == NULL || TREE_OVERFLOW (type_size))
6385 t = size_binop (PLUS_EXPR, type_size, size_int (7));
6386 t = size_binop (TRUNC_DIV_EXPR, t, size_int (8));
6387 t = size_binop (MULT_EXPR, t, size_int (8));
6389 t = fold_convert (TREE_TYPE (offset), t);
6390 gimplify_assign (offset, build2 (PLUS_EXPR, TREE_TYPE (offset), offset, t),
6393 return build_va_arg_indirect_ref (addr);
6397 alpha_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
6400 tree offset_field, base_field, offset, base, t, r;
6403 if (TARGET_ABI_OPEN_VMS || TARGET_ABI_UNICOSMK)
6404 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
6406 base_field = TYPE_FIELDS (va_list_type_node);
6407 offset_field = TREE_CHAIN (base_field);
6408 base_field = build3 (COMPONENT_REF, TREE_TYPE (base_field),
6409 valist, base_field, NULL_TREE);
6410 offset_field = build3 (COMPONENT_REF, TREE_TYPE (offset_field),
6411 valist, offset_field, NULL_TREE);
6413 /* Pull the fields of the structure out into temporaries. Since we never
6414 modify the base field, we can use a formal temporary. Sign-extend the
6415 offset field so that it's the proper width for pointer arithmetic. */
6416 base = get_formal_tmp_var (base_field, pre_p);
6418 t = fold_convert (lang_hooks.types.type_for_size (64, 0), offset_field);
6419 offset = get_initialized_tmp_var (t, pre_p, NULL);
6421 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, false);
6423 type = build_pointer_type (type);
6425 /* Find the value. Note that this will be a stable indirection, or
6426 a composite of stable indirections in the case of complex. */
6427 r = alpha_gimplify_va_arg_1 (type, base, offset, pre_p);
6429 /* Stuff the offset temporary back into its field. */
6430 gimplify_assign (unshare_expr (offset_field),
6431 fold_convert (TREE_TYPE (offset_field), offset), pre_p);
6434 r = build_va_arg_indirect_ref (r);
6443 ALPHA_BUILTIN_CMPBGE,
6444 ALPHA_BUILTIN_EXTBL,
6445 ALPHA_BUILTIN_EXTWL,
6446 ALPHA_BUILTIN_EXTLL,
6447 ALPHA_BUILTIN_EXTQL,
6448 ALPHA_BUILTIN_EXTWH,
6449 ALPHA_BUILTIN_EXTLH,
6450 ALPHA_BUILTIN_EXTQH,
6451 ALPHA_BUILTIN_INSBL,
6452 ALPHA_BUILTIN_INSWL,
6453 ALPHA_BUILTIN_INSLL,
6454 ALPHA_BUILTIN_INSQL,
6455 ALPHA_BUILTIN_INSWH,
6456 ALPHA_BUILTIN_INSLH,
6457 ALPHA_BUILTIN_INSQH,
6458 ALPHA_BUILTIN_MSKBL,
6459 ALPHA_BUILTIN_MSKWL,
6460 ALPHA_BUILTIN_MSKLL,
6461 ALPHA_BUILTIN_MSKQL,
6462 ALPHA_BUILTIN_MSKWH,
6463 ALPHA_BUILTIN_MSKLH,
6464 ALPHA_BUILTIN_MSKQH,
6465 ALPHA_BUILTIN_UMULH,
6467 ALPHA_BUILTIN_ZAPNOT,
6468 ALPHA_BUILTIN_AMASK,
6469 ALPHA_BUILTIN_IMPLVER,
6471 ALPHA_BUILTIN_THREAD_POINTER,
6472 ALPHA_BUILTIN_SET_THREAD_POINTER,
6473 ALPHA_BUILTIN_ESTABLISH_VMS_CONDITION_HANDLER,
6474 ALPHA_BUILTIN_REVERT_VMS_CONDITION_HANDLER,
6477 ALPHA_BUILTIN_MINUB8,
6478 ALPHA_BUILTIN_MINSB8,
6479 ALPHA_BUILTIN_MINUW4,
6480 ALPHA_BUILTIN_MINSW4,
6481 ALPHA_BUILTIN_MAXUB8,
6482 ALPHA_BUILTIN_MAXSB8,
6483 ALPHA_BUILTIN_MAXUW4,
6484 ALPHA_BUILTIN_MAXSW4,
6488 ALPHA_BUILTIN_UNPKBL,
6489 ALPHA_BUILTIN_UNPKBW,
6494 ALPHA_BUILTIN_CTPOP,
6499 static enum insn_code const code_for_builtin[ALPHA_BUILTIN_max] = {
6500 CODE_FOR_builtin_cmpbge,
6501 CODE_FOR_builtin_extbl,
6502 CODE_FOR_builtin_extwl,
6503 CODE_FOR_builtin_extll,
6504 CODE_FOR_builtin_extql,
6505 CODE_FOR_builtin_extwh,
6506 CODE_FOR_builtin_extlh,
6507 CODE_FOR_builtin_extqh,
6508 CODE_FOR_builtin_insbl,
6509 CODE_FOR_builtin_inswl,
6510 CODE_FOR_builtin_insll,
6511 CODE_FOR_builtin_insql,
6512 CODE_FOR_builtin_inswh,
6513 CODE_FOR_builtin_inslh,
6514 CODE_FOR_builtin_insqh,
6515 CODE_FOR_builtin_mskbl,
6516 CODE_FOR_builtin_mskwl,
6517 CODE_FOR_builtin_mskll,
6518 CODE_FOR_builtin_mskql,
6519 CODE_FOR_builtin_mskwh,
6520 CODE_FOR_builtin_msklh,
6521 CODE_FOR_builtin_mskqh,
6522 CODE_FOR_umuldi3_highpart,
6523 CODE_FOR_builtin_zap,
6524 CODE_FOR_builtin_zapnot,
6525 CODE_FOR_builtin_amask,
6526 CODE_FOR_builtin_implver,
6527 CODE_FOR_builtin_rpcc,
6530 CODE_FOR_builtin_establish_vms_condition_handler,
6531 CODE_FOR_builtin_revert_vms_condition_handler,
6534 CODE_FOR_builtin_minub8,
6535 CODE_FOR_builtin_minsb8,
6536 CODE_FOR_builtin_minuw4,
6537 CODE_FOR_builtin_minsw4,
6538 CODE_FOR_builtin_maxub8,
6539 CODE_FOR_builtin_maxsb8,
6540 CODE_FOR_builtin_maxuw4,
6541 CODE_FOR_builtin_maxsw4,
6542 CODE_FOR_builtin_perr,
6543 CODE_FOR_builtin_pklb,
6544 CODE_FOR_builtin_pkwb,
6545 CODE_FOR_builtin_unpkbl,
6546 CODE_FOR_builtin_unpkbw,
6551 CODE_FOR_popcountdi2
6554 struct alpha_builtin_def
6557 enum alpha_builtin code;
6558 unsigned int target_mask;
6562 static struct alpha_builtin_def const zero_arg_builtins[] = {
6563 { "__builtin_alpha_implver", ALPHA_BUILTIN_IMPLVER, 0, true },
6564 { "__builtin_alpha_rpcc", ALPHA_BUILTIN_RPCC, 0, false }
6567 static struct alpha_builtin_def const one_arg_builtins[] = {
6568 { "__builtin_alpha_amask", ALPHA_BUILTIN_AMASK, 0, true },
6569 { "__builtin_alpha_pklb", ALPHA_BUILTIN_PKLB, MASK_MAX, true },
6570 { "__builtin_alpha_pkwb", ALPHA_BUILTIN_PKWB, MASK_MAX, true },
6571 { "__builtin_alpha_unpkbl", ALPHA_BUILTIN_UNPKBL, MASK_MAX, true },
6572 { "__builtin_alpha_unpkbw", ALPHA_BUILTIN_UNPKBW, MASK_MAX, true },
6573 { "__builtin_alpha_cttz", ALPHA_BUILTIN_CTTZ, MASK_CIX, true },
6574 { "__builtin_alpha_ctlz", ALPHA_BUILTIN_CTLZ, MASK_CIX, true },
6575 { "__builtin_alpha_ctpop", ALPHA_BUILTIN_CTPOP, MASK_CIX, true }
6578 static struct alpha_builtin_def const two_arg_builtins[] = {
6579 { "__builtin_alpha_cmpbge", ALPHA_BUILTIN_CMPBGE, 0, true },
6580 { "__builtin_alpha_extbl", ALPHA_BUILTIN_EXTBL, 0, true },
6581 { "__builtin_alpha_extwl", ALPHA_BUILTIN_EXTWL, 0, true },
6582 { "__builtin_alpha_extll", ALPHA_BUILTIN_EXTLL, 0, true },
6583 { "__builtin_alpha_extql", ALPHA_BUILTIN_EXTQL, 0, true },
6584 { "__builtin_alpha_extwh", ALPHA_BUILTIN_EXTWH, 0, true },
6585 { "__builtin_alpha_extlh", ALPHA_BUILTIN_EXTLH, 0, true },
6586 { "__builtin_alpha_extqh", ALPHA_BUILTIN_EXTQH, 0, true },
6587 { "__builtin_alpha_insbl", ALPHA_BUILTIN_INSBL, 0, true },
6588 { "__builtin_alpha_inswl", ALPHA_BUILTIN_INSWL, 0, true },
6589 { "__builtin_alpha_insll", ALPHA_BUILTIN_INSLL, 0, true },
6590 { "__builtin_alpha_insql", ALPHA_BUILTIN_INSQL, 0, true },
6591 { "__builtin_alpha_inswh", ALPHA_BUILTIN_INSWH, 0, true },
6592 { "__builtin_alpha_inslh", ALPHA_BUILTIN_INSLH, 0, true },
6593 { "__builtin_alpha_insqh", ALPHA_BUILTIN_INSQH, 0, true },
6594 { "__builtin_alpha_mskbl", ALPHA_BUILTIN_MSKBL, 0, true },
6595 { "__builtin_alpha_mskwl", ALPHA_BUILTIN_MSKWL, 0, true },
6596 { "__builtin_alpha_mskll", ALPHA_BUILTIN_MSKLL, 0, true },
6597 { "__builtin_alpha_mskql", ALPHA_BUILTIN_MSKQL, 0, true },
6598 { "__builtin_alpha_mskwh", ALPHA_BUILTIN_MSKWH, 0, true },
6599 { "__builtin_alpha_msklh", ALPHA_BUILTIN_MSKLH, 0, true },
6600 { "__builtin_alpha_mskqh", ALPHA_BUILTIN_MSKQH, 0, true },
6601 { "__builtin_alpha_umulh", ALPHA_BUILTIN_UMULH, 0, true },
6602 { "__builtin_alpha_zap", ALPHA_BUILTIN_ZAP, 0, true },
6603 { "__builtin_alpha_zapnot", ALPHA_BUILTIN_ZAPNOT, 0, true },
6604 { "__builtin_alpha_minub8", ALPHA_BUILTIN_MINUB8, MASK_MAX, true },
6605 { "__builtin_alpha_minsb8", ALPHA_BUILTIN_MINSB8, MASK_MAX, true },
6606 { "__builtin_alpha_minuw4", ALPHA_BUILTIN_MINUW4, MASK_MAX, true },
6607 { "__builtin_alpha_minsw4", ALPHA_BUILTIN_MINSW4, MASK_MAX, true },
6608 { "__builtin_alpha_maxub8", ALPHA_BUILTIN_MAXUB8, MASK_MAX, true },
6609 { "__builtin_alpha_maxsb8", ALPHA_BUILTIN_MAXSB8, MASK_MAX, true },
6610 { "__builtin_alpha_maxuw4", ALPHA_BUILTIN_MAXUW4, MASK_MAX, true },
6611 { "__builtin_alpha_maxsw4", ALPHA_BUILTIN_MAXSW4, MASK_MAX, true },
6612 { "__builtin_alpha_perr", ALPHA_BUILTIN_PERR, MASK_MAX, true }
6615 static GTY(()) tree alpha_v8qi_u;
6616 static GTY(()) tree alpha_v8qi_s;
6617 static GTY(()) tree alpha_v4hi_u;
6618 static GTY(()) tree alpha_v4hi_s;
6620 /* Helper function of alpha_init_builtins. Add the COUNT built-in
6621 functions pointed to by P, with function type FTYPE. */
6624 alpha_add_builtins (const struct alpha_builtin_def *p, size_t count,
6630 for (i = 0; i < count; ++i, ++p)
6631 if ((target_flags & p->target_mask) == p->target_mask)
6633 decl = add_builtin_function (p->name, ftype, p->code, BUILT_IN_MD,
6636 TREE_READONLY (decl) = 1;
6637 TREE_NOTHROW (decl) = 1;
6643 alpha_init_builtins (void)
6645 tree dimode_integer_type_node;
6648 dimode_integer_type_node = lang_hooks.types.type_for_mode (DImode, 0);
6650 /* Fwrite on VMS is non-standard. */
6651 #if TARGET_ABI_OPEN_VMS
6652 implicit_built_in_decls[(int) BUILT_IN_FWRITE] = NULL_TREE;
6653 implicit_built_in_decls[(int) BUILT_IN_FWRITE_UNLOCKED] = NULL_TREE;
6656 ftype = build_function_type (dimode_integer_type_node, void_list_node);
6657 alpha_add_builtins (zero_arg_builtins, ARRAY_SIZE (zero_arg_builtins),
6660 ftype = build_function_type_list (dimode_integer_type_node,
6661 dimode_integer_type_node, NULL_TREE);
6662 alpha_add_builtins (one_arg_builtins, ARRAY_SIZE (one_arg_builtins),
6665 ftype = build_function_type_list (dimode_integer_type_node,
6666 dimode_integer_type_node,
6667 dimode_integer_type_node, NULL_TREE);
6668 alpha_add_builtins (two_arg_builtins, ARRAY_SIZE (two_arg_builtins),
6671 ftype = build_function_type (ptr_type_node, void_list_node);
6672 decl = add_builtin_function ("__builtin_thread_pointer", ftype,
6673 ALPHA_BUILTIN_THREAD_POINTER, BUILT_IN_MD,
6675 TREE_NOTHROW (decl) = 1;
6677 ftype = build_function_type_list (void_type_node, ptr_type_node, NULL_TREE);
6678 decl = add_builtin_function ("__builtin_set_thread_pointer", ftype,
6679 ALPHA_BUILTIN_SET_THREAD_POINTER, BUILT_IN_MD,
6681 TREE_NOTHROW (decl) = 1;
6683 if (TARGET_ABI_OPEN_VMS)
6685 ftype = build_function_type_list (ptr_type_node, ptr_type_node,
6687 add_builtin_function ("__builtin_establish_vms_condition_handler", ftype,
6688 ALPHA_BUILTIN_ESTABLISH_VMS_CONDITION_HANDLER,
6689 BUILT_IN_MD, NULL, NULL_TREE);
6691 ftype = build_function_type_list (ptr_type_node, void_type_node,
6693 add_builtin_function ("__builtin_revert_vms_condition_handler", ftype,
6694 ALPHA_BUILTIN_REVERT_VMS_CONDITION_HANDLER,
6695 BUILT_IN_MD, NULL, NULL_TREE);
6698 alpha_v8qi_u = build_vector_type (unsigned_intQI_type_node, 8);
6699 alpha_v8qi_s = build_vector_type (intQI_type_node, 8);
6700 alpha_v4hi_u = build_vector_type (unsigned_intHI_type_node, 4);
6701 alpha_v4hi_s = build_vector_type (intHI_type_node, 4);
6704 /* Expand an expression EXP that calls a built-in function,
6705 with result going to TARGET if that's convenient
6706 (and in mode MODE if that's convenient).
6707 SUBTARGET may be used as the target for computing one of EXP's operands.
6708 IGNORE is nonzero if the value is to be ignored. */
6711 alpha_expand_builtin (tree exp, rtx target,
6712 rtx subtarget ATTRIBUTE_UNUSED,
6713 enum machine_mode mode ATTRIBUTE_UNUSED,
6714 int ignore ATTRIBUTE_UNUSED)
6718 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
6719 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6721 call_expr_arg_iterator iter;
6722 enum insn_code icode;
6723 rtx op[MAX_ARGS], pat;
6727 if (fcode >= ALPHA_BUILTIN_max)
6728 internal_error ("bad builtin fcode");
6729 icode = code_for_builtin[fcode];
6731 internal_error ("bad builtin fcode");
6733 nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
6736 FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
6738 const struct insn_operand_data *insn_op;
6740 if (arg == error_mark_node)
6742 if (arity > MAX_ARGS)
6745 insn_op = &insn_data[icode].operand[arity + nonvoid];
6747 op[arity] = expand_expr (arg, NULL_RTX, insn_op->mode, EXPAND_NORMAL);
6749 if (!(*insn_op->predicate) (op[arity], insn_op->mode))
6750 op[arity] = copy_to_mode_reg (insn_op->mode, op[arity]);
6756 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6758 || GET_MODE (target) != tmode
6759 || !(*insn_data[icode].operand[0].predicate) (target, tmode))
6760 target = gen_reg_rtx (tmode);
6766 pat = GEN_FCN (icode) (target);
6770 pat = GEN_FCN (icode) (target, op[0]);
6772 pat = GEN_FCN (icode) (op[0]);
6775 pat = GEN_FCN (icode) (target, op[0], op[1]);
6791 /* Several bits below assume HWI >= 64 bits. This should be enforced
6793 #if HOST_BITS_PER_WIDE_INT < 64
6794 # error "HOST_WIDE_INT too small"
6797 /* Fold the builtin for the CMPBGE instruction. This is a vector comparison
6798 with an 8-bit output vector. OPINT contains the integer operands; bit N
6799 of OP_CONST is set if OPINT[N] is valid. */
6802 alpha_fold_builtin_cmpbge (unsigned HOST_WIDE_INT opint[], long op_const)
6807 for (i = 0, val = 0; i < 8; ++i)
6809 unsigned HOST_WIDE_INT c0 = (opint[0] >> (i * 8)) & 0xff;
6810 unsigned HOST_WIDE_INT c1 = (opint[1] >> (i * 8)) & 0xff;
6814 return build_int_cst (long_integer_type_node, val);
6816 else if (op_const == 2 && opint[1] == 0)
6817 return build_int_cst (long_integer_type_node, 0xff);
6821 /* Fold the builtin for the ZAPNOT instruction. This is essentially a
6822 specialized form of an AND operation. Other byte manipulation instructions
6823 are defined in terms of this instruction, so this is also used as a
6824 subroutine for other builtins.
6826 OP contains the tree operands; OPINT contains the extracted integer values.
6827 Bit N of OP_CONST it set if OPINT[N] is valid. OP may be null if only
6828 OPINT may be considered. */
6831 alpha_fold_builtin_zapnot (tree *op, unsigned HOST_WIDE_INT opint[],
6836 unsigned HOST_WIDE_INT mask = 0;
6839 for (i = 0; i < 8; ++i)
6840 if ((opint[1] >> i) & 1)
6841 mask |= (unsigned HOST_WIDE_INT)0xff << (i * 8);
6844 return build_int_cst (long_integer_type_node, opint[0] & mask);
6847 return fold_build2 (BIT_AND_EXPR, long_integer_type_node, op[0],
6848 build_int_cst (long_integer_type_node, mask));
6850 else if ((op_const & 1) && opint[0] == 0)
6851 return build_int_cst (long_integer_type_node, 0);
6855 /* Fold the builtins for the EXT family of instructions. */
6858 alpha_fold_builtin_extxx (tree op[], unsigned HOST_WIDE_INT opint[],
6859 long op_const, unsigned HOST_WIDE_INT bytemask,
6863 tree *zap_op = NULL;
6867 unsigned HOST_WIDE_INT loc;
6870 if (BYTES_BIG_ENDIAN)
6878 unsigned HOST_WIDE_INT temp = opint[0];
6891 opint[1] = bytemask;
6892 return alpha_fold_builtin_zapnot (zap_op, opint, zap_const);
6895 /* Fold the builtins for the INS family of instructions. */
6898 alpha_fold_builtin_insxx (tree op[], unsigned HOST_WIDE_INT opint[],
6899 long op_const, unsigned HOST_WIDE_INT bytemask,
6902 if ((op_const & 1) && opint[0] == 0)
6903 return build_int_cst (long_integer_type_node, 0);
6907 unsigned HOST_WIDE_INT temp, loc, byteloc;
6908 tree *zap_op = NULL;
6911 if (BYTES_BIG_ENDIAN)
6918 byteloc = (64 - (loc * 8)) & 0x3f;
6935 opint[1] = bytemask;
6936 return alpha_fold_builtin_zapnot (zap_op, opint, op_const);
6943 alpha_fold_builtin_mskxx (tree op[], unsigned HOST_WIDE_INT opint[],
6944 long op_const, unsigned HOST_WIDE_INT bytemask,
6949 unsigned HOST_WIDE_INT loc;
6952 if (BYTES_BIG_ENDIAN)
6959 opint[1] = bytemask ^ 0xff;
6962 return alpha_fold_builtin_zapnot (op, opint, op_const);
6966 alpha_fold_builtin_umulh (unsigned HOST_WIDE_INT opint[], long op_const)
6972 unsigned HOST_WIDE_INT l;
6975 mul_double (opint[0], 0, opint[1], 0, &l, &h);
6977 #if HOST_BITS_PER_WIDE_INT > 64
6981 return build_int_cst (long_integer_type_node, h);
6985 opint[1] = opint[0];
6988 /* Note that (X*1) >> 64 == 0. */
6989 if (opint[1] == 0 || opint[1] == 1)
6990 return build_int_cst (long_integer_type_node, 0);
6997 alpha_fold_vector_minmax (enum tree_code code, tree op[], tree vtype)
6999 tree op0 = fold_convert (vtype, op[0]);
7000 tree op1 = fold_convert (vtype, op[1]);
7001 tree val = fold_build2 (code, vtype, op0, op1);
7002 return fold_build1 (VIEW_CONVERT_EXPR, long_integer_type_node, val);
7006 alpha_fold_builtin_perr (unsigned HOST_WIDE_INT opint[], long op_const)
7008 unsigned HOST_WIDE_INT temp = 0;
7014 for (i = 0; i < 8; ++i)
7016 unsigned HOST_WIDE_INT a = (opint[0] >> (i * 8)) & 0xff;
7017 unsigned HOST_WIDE_INT b = (opint[1] >> (i * 8)) & 0xff;
7024 return build_int_cst (long_integer_type_node, temp);
7028 alpha_fold_builtin_pklb (unsigned HOST_WIDE_INT opint[], long op_const)
7030 unsigned HOST_WIDE_INT temp;
7035 temp = opint[0] & 0xff;
7036 temp |= (opint[0] >> 24) & 0xff00;
7038 return build_int_cst (long_integer_type_node, temp);
7042 alpha_fold_builtin_pkwb (unsigned HOST_WIDE_INT opint[], long op_const)
7044 unsigned HOST_WIDE_INT temp;
7049 temp = opint[0] & 0xff;
7050 temp |= (opint[0] >> 8) & 0xff00;
7051 temp |= (opint[0] >> 16) & 0xff0000;
7052 temp |= (opint[0] >> 24) & 0xff000000;
7054 return build_int_cst (long_integer_type_node, temp);
7058 alpha_fold_builtin_unpkbl (unsigned HOST_WIDE_INT opint[], long op_const)
7060 unsigned HOST_WIDE_INT temp;
7065 temp = opint[0] & 0xff;
7066 temp |= (opint[0] & 0xff00) << 24;
7068 return build_int_cst (long_integer_type_node, temp);
7072 alpha_fold_builtin_unpkbw (unsigned HOST_WIDE_INT opint[], long op_const)
7074 unsigned HOST_WIDE_INT temp;
7079 temp = opint[0] & 0xff;
7080 temp |= (opint[0] & 0x0000ff00) << 8;
7081 temp |= (opint[0] & 0x00ff0000) << 16;
7082 temp |= (opint[0] & 0xff000000) << 24;
7084 return build_int_cst (long_integer_type_node, temp);
7088 alpha_fold_builtin_cttz (unsigned HOST_WIDE_INT opint[], long op_const)
7090 unsigned HOST_WIDE_INT temp;
7098 temp = exact_log2 (opint[0] & -opint[0]);
7100 return build_int_cst (long_integer_type_node, temp);
7104 alpha_fold_builtin_ctlz (unsigned HOST_WIDE_INT opint[], long op_const)
7106 unsigned HOST_WIDE_INT temp;
7114 temp = 64 - floor_log2 (opint[0]) - 1;
7116 return build_int_cst (long_integer_type_node, temp);
7120 alpha_fold_builtin_ctpop (unsigned HOST_WIDE_INT opint[], long op_const)
7122 unsigned HOST_WIDE_INT temp, op;
7130 temp++, op &= op - 1;
7132 return build_int_cst (long_integer_type_node, temp);
7135 /* Fold one of our builtin functions. */
7138 alpha_fold_builtin (tree fndecl, tree arglist, bool ignore ATTRIBUTE_UNUSED)
7140 tree op[MAX_ARGS], t;
7141 unsigned HOST_WIDE_INT opint[MAX_ARGS];
7142 long op_const = 0, arity = 0;
7144 for (t = arglist; t ; t = TREE_CHAIN (t), ++arity)
7146 tree arg = TREE_VALUE (t);
7147 if (arg == error_mark_node)
7149 if (arity >= MAX_ARGS)
7154 if (TREE_CODE (arg) == INTEGER_CST)
7156 op_const |= 1L << arity;
7157 opint[arity] = int_cst_value (arg);
7161 switch (DECL_FUNCTION_CODE (fndecl))
7163 case ALPHA_BUILTIN_CMPBGE:
7164 return alpha_fold_builtin_cmpbge (opint, op_const);
7166 case ALPHA_BUILTIN_EXTBL:
7167 return alpha_fold_builtin_extxx (op, opint, op_const, 0x01, false);
7168 case ALPHA_BUILTIN_EXTWL:
7169 return alpha_fold_builtin_extxx (op, opint, op_const, 0x03, false);
7170 case ALPHA_BUILTIN_EXTLL:
7171 return alpha_fold_builtin_extxx (op, opint, op_const, 0x0f, false);
7172 case ALPHA_BUILTIN_EXTQL:
7173 return alpha_fold_builtin_extxx (op, opint, op_const, 0xff, false);
7174 case ALPHA_BUILTIN_EXTWH:
7175 return alpha_fold_builtin_extxx (op, opint, op_const, 0x03, true);
7176 case ALPHA_BUILTIN_EXTLH:
7177 return alpha_fold_builtin_extxx (op, opint, op_const, 0x0f, true);
7178 case ALPHA_BUILTIN_EXTQH:
7179 return alpha_fold_builtin_extxx (op, opint, op_const, 0xff, true);
7181 case ALPHA_BUILTIN_INSBL:
7182 return alpha_fold_builtin_insxx (op, opint, op_const, 0x01, false);
7183 case ALPHA_BUILTIN_INSWL:
7184 return alpha_fold_builtin_insxx (op, opint, op_const, 0x03, false);
7185 case ALPHA_BUILTIN_INSLL:
7186 return alpha_fold_builtin_insxx (op, opint, op_const, 0x0f, false);
7187 case ALPHA_BUILTIN_INSQL:
7188 return alpha_fold_builtin_insxx (op, opint, op_const, 0xff, false);
7189 case ALPHA_BUILTIN_INSWH:
7190 return alpha_fold_builtin_insxx (op, opint, op_const, 0x03, true);
7191 case ALPHA_BUILTIN_INSLH:
7192 return alpha_fold_builtin_insxx (op, opint, op_const, 0x0f, true);
7193 case ALPHA_BUILTIN_INSQH:
7194 return alpha_fold_builtin_insxx (op, opint, op_const, 0xff, true);
7196 case ALPHA_BUILTIN_MSKBL:
7197 return alpha_fold_builtin_mskxx (op, opint, op_const, 0x01, false);
7198 case ALPHA_BUILTIN_MSKWL:
7199 return alpha_fold_builtin_mskxx (op, opint, op_const, 0x03, false);
7200 case ALPHA_BUILTIN_MSKLL:
7201 return alpha_fold_builtin_mskxx (op, opint, op_const, 0x0f, false);
7202 case ALPHA_BUILTIN_MSKQL:
7203 return alpha_fold_builtin_mskxx (op, opint, op_const, 0xff, false);
7204 case ALPHA_BUILTIN_MSKWH:
7205 return alpha_fold_builtin_mskxx (op, opint, op_const, 0x03, true);
7206 case ALPHA_BUILTIN_MSKLH:
7207 return alpha_fold_builtin_mskxx (op, opint, op_const, 0x0f, true);
7208 case ALPHA_BUILTIN_MSKQH:
7209 return alpha_fold_builtin_mskxx (op, opint, op_const, 0xff, true);
7211 case ALPHA_BUILTIN_UMULH:
7212 return alpha_fold_builtin_umulh (opint, op_const);
7214 case ALPHA_BUILTIN_ZAP:
7217 case ALPHA_BUILTIN_ZAPNOT:
7218 return alpha_fold_builtin_zapnot (op, opint, op_const);
7220 case ALPHA_BUILTIN_MINUB8:
7221 return alpha_fold_vector_minmax (MIN_EXPR, op, alpha_v8qi_u);
7222 case ALPHA_BUILTIN_MINSB8:
7223 return alpha_fold_vector_minmax (MIN_EXPR, op, alpha_v8qi_s);
7224 case ALPHA_BUILTIN_MINUW4:
7225 return alpha_fold_vector_minmax (MIN_EXPR, op, alpha_v4hi_u);
7226 case ALPHA_BUILTIN_MINSW4:
7227 return alpha_fold_vector_minmax (MIN_EXPR, op, alpha_v4hi_s);
7228 case ALPHA_BUILTIN_MAXUB8:
7229 return alpha_fold_vector_minmax (MAX_EXPR, op, alpha_v8qi_u);
7230 case ALPHA_BUILTIN_MAXSB8:
7231 return alpha_fold_vector_minmax (MAX_EXPR, op, alpha_v8qi_s);
7232 case ALPHA_BUILTIN_MAXUW4:
7233 return alpha_fold_vector_minmax (MAX_EXPR, op, alpha_v4hi_u);
7234 case ALPHA_BUILTIN_MAXSW4:
7235 return alpha_fold_vector_minmax (MAX_EXPR, op, alpha_v4hi_s);
7237 case ALPHA_BUILTIN_PERR:
7238 return alpha_fold_builtin_perr (opint, op_const);
7239 case ALPHA_BUILTIN_PKLB:
7240 return alpha_fold_builtin_pklb (opint, op_const);
7241 case ALPHA_BUILTIN_PKWB:
7242 return alpha_fold_builtin_pkwb (opint, op_const);
7243 case ALPHA_BUILTIN_UNPKBL:
7244 return alpha_fold_builtin_unpkbl (opint, op_const);
7245 case ALPHA_BUILTIN_UNPKBW:
7246 return alpha_fold_builtin_unpkbw (opint, op_const);
7248 case ALPHA_BUILTIN_CTTZ:
7249 return alpha_fold_builtin_cttz (opint, op_const);
7250 case ALPHA_BUILTIN_CTLZ:
7251 return alpha_fold_builtin_ctlz (opint, op_const);
7252 case ALPHA_BUILTIN_CTPOP:
7253 return alpha_fold_builtin_ctpop (opint, op_const);
7255 case ALPHA_BUILTIN_AMASK:
7256 case ALPHA_BUILTIN_IMPLVER:
7257 case ALPHA_BUILTIN_RPCC:
7258 case ALPHA_BUILTIN_THREAD_POINTER:
7259 case ALPHA_BUILTIN_SET_THREAD_POINTER:
7260 /* None of these are foldable at compile-time. */
7266 /* This page contains routines that are used to determine what the function
7267 prologue and epilogue code will do and write them out. */
7269 /* Compute the size of the save area in the stack. */
7271 /* These variables are used for communication between the following functions.
7272 They indicate various things about the current function being compiled
7273 that are used to tell what kind of prologue, epilogue and procedure
7274 descriptor to generate. */
7276 /* Nonzero if we need a stack procedure. */
7277 enum alpha_procedure_types {PT_NULL = 0, PT_REGISTER = 1, PT_STACK = 2};
7278 static enum alpha_procedure_types alpha_procedure_type;
7280 /* Register number (either FP or SP) that is used to unwind the frame. */
7281 static int vms_unwind_regno;
7283 /* Register number used to save FP. We need not have one for RA since
7284 we don't modify it for register procedures. This is only defined
7285 for register frame procedures. */
7286 static int vms_save_fp_regno;
7288 /* Register number used to reference objects off our PV. */
7289 static int vms_base_regno;
7291 /* Compute register masks for saved registers. */
7294 alpha_sa_mask (unsigned long *imaskP, unsigned long *fmaskP)
7296 unsigned long imask = 0;
7297 unsigned long fmask = 0;
7300 /* When outputting a thunk, we don't have valid register life info,
7301 but assemble_start_function wants to output .frame and .mask
7310 if (TARGET_ABI_OPEN_VMS && alpha_procedure_type == PT_STACK)
7311 imask |= (1UL << HARD_FRAME_POINTER_REGNUM);
7313 /* One for every register we have to save. */
7314 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
7315 if (! fixed_regs[i] && ! call_used_regs[i]
7316 && df_regs_ever_live_p (i) && i != REG_RA
7317 && (!TARGET_ABI_UNICOSMK || i != HARD_FRAME_POINTER_REGNUM))
7320 imask |= (1UL << i);
7322 fmask |= (1UL << (i - 32));
7325 /* We need to restore these for the handler. */
7326 if (crtl->calls_eh_return)
7330 unsigned regno = EH_RETURN_DATA_REGNO (i);
7331 if (regno == INVALID_REGNUM)
7333 imask |= 1UL << regno;
7337 /* If any register spilled, then spill the return address also. */
7338 /* ??? This is required by the Digital stack unwind specification
7339 and isn't needed if we're doing Dwarf2 unwinding. */
7340 if (imask || fmask || alpha_ra_ever_killed ())
7341 imask |= (1UL << REG_RA);
7348 alpha_sa_size (void)
7350 unsigned long mask[2];
7354 alpha_sa_mask (&mask[0], &mask[1]);
7356 if (TARGET_ABI_UNICOSMK)
7358 if (mask[0] || mask[1])
7363 for (j = 0; j < 2; ++j)
7364 for (i = 0; i < 32; ++i)
7365 if ((mask[j] >> i) & 1)
7369 if (TARGET_ABI_UNICOSMK)
7371 /* We might not need to generate a frame if we don't make any calls
7372 (including calls to __T3E_MISMATCH if this is a vararg function),
7373 don't have any local variables which require stack slots, don't
7374 use alloca and have not determined that we need a frame for other
7377 alpha_procedure_type
7378 = (sa_size || get_frame_size() != 0
7379 || crtl->outgoing_args_size
7380 || cfun->stdarg || cfun->calls_alloca
7381 || frame_pointer_needed)
7382 ? PT_STACK : PT_REGISTER;
7384 /* Always reserve space for saving callee-saved registers if we
7385 need a frame as required by the calling convention. */
7386 if (alpha_procedure_type == PT_STACK)
7389 else if (TARGET_ABI_OPEN_VMS)
7391 /* Start with a stack procedure if we make any calls (REG_RA used), or
7392 need a frame pointer, with a register procedure if we otherwise need
7393 at least a slot, and with a null procedure in other cases. */
7394 if ((mask[0] >> REG_RA) & 1 || frame_pointer_needed)
7395 alpha_procedure_type = PT_STACK;
7396 else if (get_frame_size() != 0)
7397 alpha_procedure_type = PT_REGISTER;
7399 alpha_procedure_type = PT_NULL;
7401 /* Don't reserve space for saving FP & RA yet. Do that later after we've
7402 made the final decision on stack procedure vs register procedure. */
7403 if (alpha_procedure_type == PT_STACK)
7406 /* Decide whether to refer to objects off our PV via FP or PV.
7407 If we need FP for something else or if we receive a nonlocal
7408 goto (which expects PV to contain the value), we must use PV.
7409 Otherwise, start by assuming we can use FP. */
7412 = (frame_pointer_needed
7413 || cfun->has_nonlocal_label
7414 || alpha_procedure_type == PT_STACK
7415 || crtl->outgoing_args_size)
7416 ? REG_PV : HARD_FRAME_POINTER_REGNUM;
7418 /* If we want to copy PV into FP, we need to find some register
7419 in which to save FP. */
7421 vms_save_fp_regno = -1;
7422 if (vms_base_regno == HARD_FRAME_POINTER_REGNUM)
7423 for (i = 0; i < 32; i++)
7424 if (! fixed_regs[i] && call_used_regs[i] && ! df_regs_ever_live_p (i))
7425 vms_save_fp_regno = i;
7427 /* A VMS condition handler requires a stack procedure in our
7428 implementation. (not required by the calling standard). */
7429 if ((vms_save_fp_regno == -1 && alpha_procedure_type == PT_REGISTER)
7430 || cfun->machine->uses_condition_handler)
7431 vms_base_regno = REG_PV, alpha_procedure_type = PT_STACK;
7432 else if (alpha_procedure_type == PT_NULL)
7433 vms_base_regno = REG_PV;
7435 /* Stack unwinding should be done via FP unless we use it for PV. */
7436 vms_unwind_regno = (vms_base_regno == REG_PV
7437 ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM);
7439 /* If this is a stack procedure, allow space for saving FP, RA and
7440 a condition handler slot if needed. */
7441 if (alpha_procedure_type == PT_STACK)
7442 sa_size += 2 + cfun->machine->uses_condition_handler;
7446 /* Our size must be even (multiple of 16 bytes). */
7454 /* Define the offset between two registers, one to be eliminated,
7455 and the other its replacement, at the start of a routine. */
7458 alpha_initial_elimination_offset (unsigned int from,
7459 unsigned int to ATTRIBUTE_UNUSED)
7463 ret = alpha_sa_size ();
7464 ret += ALPHA_ROUND (crtl->outgoing_args_size);
7468 case FRAME_POINTER_REGNUM:
7471 case ARG_POINTER_REGNUM:
7472 ret += (ALPHA_ROUND (get_frame_size ()
7473 + crtl->args.pretend_args_size)
7474 - crtl->args.pretend_args_size);
7484 #if TARGET_ABI_OPEN_VMS
7486 /* Worker function for TARGET_CAN_ELIMINATE. */
7489 alpha_vms_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
7491 /* We need the alpha_procedure_type to decide. Evaluate it now. */
7494 switch (alpha_procedure_type)
7497 /* NULL procedures have no frame of their own and we only
7498 know how to resolve from the current stack pointer. */
7499 return to == STACK_POINTER_REGNUM;
7503 /* We always eliminate except to the stack pointer if there is no
7504 usable frame pointer at hand. */
7505 return (to != STACK_POINTER_REGNUM
7506 || vms_unwind_regno != HARD_FRAME_POINTER_REGNUM);
7512 /* FROM is to be eliminated for TO. Return the offset so that TO+offset
7513 designates the same location as FROM. */
7516 alpha_vms_initial_elimination_offset (unsigned int from, unsigned int to)
7518 /* The only possible attempts we ever expect are ARG or FRAME_PTR to
7519 HARD_FRAME or STACK_PTR. We need the alpha_procedure_type to decide
7520 on the proper computations and will need the register save area size
7523 HOST_WIDE_INT sa_size = alpha_sa_size ();
7525 /* PT_NULL procedures have no frame of their own and we only allow
7526 elimination to the stack pointer. This is the argument pointer and we
7527 resolve the soft frame pointer to that as well. */
7529 if (alpha_procedure_type == PT_NULL)
7532 /* For a PT_STACK procedure the frame layout looks as follows
7534 -----> decreasing addresses
7536 < size rounded up to 16 | likewise >
7537 --------------#------------------------------+++--------------+++-------#
7538 incoming args # pretended args | "frame" | regs sa | PV | outgoing args #
7539 --------------#---------------------------------------------------------#
7541 ARG_PTR FRAME_PTR HARD_FRAME_PTR STACK_PTR
7544 PT_REGISTER procedures are similar in that they may have a frame of their
7545 own. They have no regs-sa/pv/outgoing-args area.
7547 We first compute offset to HARD_FRAME_PTR, then add what we need to get
7548 to STACK_PTR if need be. */
7551 HOST_WIDE_INT offset;
7552 HOST_WIDE_INT pv_save_size = alpha_procedure_type == PT_STACK ? 8 : 0;
7556 case FRAME_POINTER_REGNUM:
7557 offset = ALPHA_ROUND (sa_size + pv_save_size);
7559 case ARG_POINTER_REGNUM:
7560 offset = (ALPHA_ROUND (sa_size + pv_save_size
7562 + crtl->args.pretend_args_size)
7563 - crtl->args.pretend_args_size);
7569 if (to == STACK_POINTER_REGNUM)
7570 offset += ALPHA_ROUND (crtl->outgoing_args_size);
7576 #define COMMON_OBJECT "common_object"
7579 common_object_handler (tree *node, tree name ATTRIBUTE_UNUSED,
7580 tree args ATTRIBUTE_UNUSED, int flags ATTRIBUTE_UNUSED,
7581 bool *no_add_attrs ATTRIBUTE_UNUSED)
7584 gcc_assert (DECL_P (decl));
7586 DECL_COMMON (decl) = 1;
7590 static const struct attribute_spec vms_attribute_table[] =
7592 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
7593 { COMMON_OBJECT, 0, 1, true, false, false, common_object_handler },
7594 { NULL, 0, 0, false, false, false, NULL }
7598 vms_output_aligned_decl_common(FILE *file, tree decl, const char *name,
7599 unsigned HOST_WIDE_INT size,
7602 tree attr = DECL_ATTRIBUTES (decl);
7603 fprintf (file, "%s", COMMON_ASM_OP);
7604 assemble_name (file, name);
7605 fprintf (file, "," HOST_WIDE_INT_PRINT_UNSIGNED, size);
7606 /* ??? Unlike on OSF/1, the alignment factor is not in log units. */
7607 fprintf (file, ",%u", align / BITS_PER_UNIT);
7610 attr = lookup_attribute (COMMON_OBJECT, attr);
7612 fprintf (file, ",%s",
7613 IDENTIFIER_POINTER (TREE_VALUE (TREE_VALUE (attr))));
7618 #undef COMMON_OBJECT
7623 find_lo_sum_using_gp (rtx *px, void *data ATTRIBUTE_UNUSED)
7625 return GET_CODE (*px) == LO_SUM && XEXP (*px, 0) == pic_offset_table_rtx;
7629 alpha_find_lo_sum_using_gp (rtx insn)
7631 return for_each_rtx (&PATTERN (insn), find_lo_sum_using_gp, NULL) > 0;
7635 alpha_does_function_need_gp (void)
7639 /* The GP being variable is an OSF abi thing. */
7640 if (! TARGET_ABI_OSF)
7643 /* We need the gp to load the address of __mcount. */
7644 if (TARGET_PROFILING_NEEDS_GP && crtl->profile)
7647 /* The code emitted by alpha_output_mi_thunk_osf uses the gp. */
7651 /* The nonlocal receiver pattern assumes that the gp is valid for
7652 the nested function. Reasonable because it's almost always set
7653 correctly already. For the cases where that's wrong, make sure
7654 the nested function loads its gp on entry. */
7655 if (crtl->has_nonlocal_goto)
7658 /* If we need a GP (we have a LDSYM insn or a CALL_INSN), load it first.
7659 Even if we are a static function, we still need to do this in case
7660 our address is taken and passed to something like qsort. */
7662 push_topmost_sequence ();
7663 insn = get_insns ();
7664 pop_topmost_sequence ();
7666 for (; insn; insn = NEXT_INSN (insn))
7667 if (NONDEBUG_INSN_P (insn)
7668 && ! JUMP_TABLE_DATA_P (insn)
7669 && GET_CODE (PATTERN (insn)) != USE
7670 && GET_CODE (PATTERN (insn)) != CLOBBER
7671 && get_attr_usegp (insn))
7678 /* Helper function to set RTX_FRAME_RELATED_P on instructions, including
7682 set_frame_related_p (void)
7684 rtx seq = get_insns ();
7695 while (insn != NULL_RTX)
7697 RTX_FRAME_RELATED_P (insn) = 1;
7698 insn = NEXT_INSN (insn);
7700 seq = emit_insn (seq);
7704 seq = emit_insn (seq);
7705 RTX_FRAME_RELATED_P (seq) = 1;
7710 #define FRP(exp) (start_sequence (), exp, set_frame_related_p ())
7712 /* Generates a store with the proper unwind info attached. VALUE is
7713 stored at BASE_REG+BASE_OFS. If FRAME_BIAS is nonzero, then BASE_REG
7714 contains SP+FRAME_BIAS, and that is the unwind info that should be
7715 generated. If FRAME_REG != VALUE, then VALUE is being stored on
7716 behalf of FRAME_REG, and FRAME_REG should be present in the unwind. */
7719 emit_frame_store_1 (rtx value, rtx base_reg, HOST_WIDE_INT frame_bias,
7720 HOST_WIDE_INT base_ofs, rtx frame_reg)
7722 rtx addr, mem, insn;
7724 addr = plus_constant (base_reg, base_ofs);
7725 mem = gen_rtx_MEM (DImode, addr);
7726 set_mem_alias_set (mem, alpha_sr_alias_set);
7728 insn = emit_move_insn (mem, value);
7729 RTX_FRAME_RELATED_P (insn) = 1;
7731 if (frame_bias || value != frame_reg)
7735 addr = plus_constant (stack_pointer_rtx, frame_bias + base_ofs);
7736 mem = gen_rtx_MEM (DImode, addr);
7739 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
7740 gen_rtx_SET (VOIDmode, mem, frame_reg));
7745 emit_frame_store (unsigned int regno, rtx base_reg,
7746 HOST_WIDE_INT frame_bias, HOST_WIDE_INT base_ofs)
7748 rtx reg = gen_rtx_REG (DImode, regno);
7749 emit_frame_store_1 (reg, base_reg, frame_bias, base_ofs, reg);
7752 /* Write function prologue. */
7754 /* On vms we have two kinds of functions:
7756 - stack frame (PROC_STACK)
7757 these are 'normal' functions with local vars and which are
7758 calling other functions
7759 - register frame (PROC_REGISTER)
7760 keeps all data in registers, needs no stack
7762 We must pass this to the assembler so it can generate the
7763 proper pdsc (procedure descriptor)
7764 This is done with the '.pdesc' command.
7766 On not-vms, we don't really differentiate between the two, as we can
7767 simply allocate stack without saving registers. */
7770 alpha_expand_prologue (void)
7772 /* Registers to save. */
7773 unsigned long imask = 0;
7774 unsigned long fmask = 0;
7775 /* Stack space needed for pushing registers clobbered by us. */
7776 HOST_WIDE_INT sa_size;
7777 /* Complete stack size needed. */
7778 HOST_WIDE_INT frame_size;
7779 /* Offset from base reg to register save area. */
7780 HOST_WIDE_INT reg_offset;
7784 sa_size = alpha_sa_size ();
7786 frame_size = get_frame_size ();
7787 if (TARGET_ABI_OPEN_VMS)
7788 frame_size = ALPHA_ROUND (sa_size
7789 + (alpha_procedure_type == PT_STACK ? 8 : 0)
7791 + crtl->args.pretend_args_size);
7792 else if (TARGET_ABI_UNICOSMK)
7793 /* We have to allocate space for the DSIB if we generate a frame. */
7794 frame_size = ALPHA_ROUND (sa_size
7795 + (alpha_procedure_type == PT_STACK ? 48 : 0))
7796 + ALPHA_ROUND (frame_size
7797 + crtl->outgoing_args_size);
7799 frame_size = (ALPHA_ROUND (crtl->outgoing_args_size)
7801 + ALPHA_ROUND (frame_size
7802 + crtl->args.pretend_args_size));
7804 if (TARGET_ABI_OPEN_VMS)
7805 reg_offset = 8 + 8 * cfun->machine->uses_condition_handler;
7807 reg_offset = ALPHA_ROUND (crtl->outgoing_args_size);
7809 alpha_sa_mask (&imask, &fmask);
7811 /* Emit an insn to reload GP, if needed. */
7814 alpha_function_needs_gp = alpha_does_function_need_gp ();
7815 if (alpha_function_needs_gp)
7816 emit_insn (gen_prologue_ldgp ());
7819 /* TARGET_PROFILING_NEEDS_GP actually implies that we need to insert
7820 the call to mcount ourselves, rather than having the linker do it
7821 magically in response to -pg. Since _mcount has special linkage,
7822 don't represent the call as a call. */
7823 if (TARGET_PROFILING_NEEDS_GP && crtl->profile)
7824 emit_insn (gen_prologue_mcount ());
7826 if (TARGET_ABI_UNICOSMK)
7827 unicosmk_gen_dsib (&imask);
7829 /* Adjust the stack by the frame size. If the frame size is > 4096
7830 bytes, we need to be sure we probe somewhere in the first and last
7831 4096 bytes (we can probably get away without the latter test) and
7832 every 8192 bytes in between. If the frame size is > 32768, we
7833 do this in a loop. Otherwise, we generate the explicit probe
7836 Note that we are only allowed to adjust sp once in the prologue. */
7838 if (frame_size <= 32768)
7840 if (frame_size > 4096)
7844 for (probed = 4096; probed < frame_size; probed += 8192)
7845 emit_insn (gen_probe_stack (GEN_INT (TARGET_ABI_UNICOSMK
7849 /* We only have to do this probe if we aren't saving registers. */
7850 if (sa_size == 0 && frame_size > probed - 4096)
7851 emit_insn (gen_probe_stack (GEN_INT (-frame_size)));
7854 if (frame_size != 0)
7855 FRP (emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx,
7856 GEN_INT (TARGET_ABI_UNICOSMK
7862 /* Here we generate code to set R22 to SP + 4096 and set R23 to the
7863 number of 8192 byte blocks to probe. We then probe each block
7864 in the loop and then set SP to the proper location. If the
7865 amount remaining is > 4096, we have to do one more probe if we
7866 are not saving any registers. */
7868 HOST_WIDE_INT blocks = (frame_size + 4096) / 8192;
7869 HOST_WIDE_INT leftover = frame_size + 4096 - blocks * 8192;
7870 rtx ptr = gen_rtx_REG (DImode, 22);
7871 rtx count = gen_rtx_REG (DImode, 23);
7874 emit_move_insn (count, GEN_INT (blocks));
7875 emit_insn (gen_adddi3 (ptr, stack_pointer_rtx,
7876 GEN_INT (TARGET_ABI_UNICOSMK ? 4096 - 64 : 4096)));
7878 /* Because of the difficulty in emitting a new basic block this
7879 late in the compilation, generate the loop as a single insn. */
7880 emit_insn (gen_prologue_stack_probe_loop (count, ptr));
7882 if (leftover > 4096 && sa_size == 0)
7884 rtx last = gen_rtx_MEM (DImode, plus_constant (ptr, -leftover));
7885 MEM_VOLATILE_P (last) = 1;
7886 emit_move_insn (last, const0_rtx);
7889 if (TARGET_ABI_WINDOWS_NT)
7891 /* For NT stack unwind (done by 'reverse execution'), it's
7892 not OK to take the result of a loop, even though the value
7893 is already in ptr, so we reload it via a single operation
7894 and subtract it to sp.
7896 Yes, that's correct -- we have to reload the whole constant
7897 into a temporary via ldah+lda then subtract from sp. */
7899 HOST_WIDE_INT lo, hi;
7900 lo = ((frame_size & 0xffff) ^ 0x8000) - 0x8000;
7901 hi = frame_size - lo;
7903 emit_move_insn (ptr, GEN_INT (hi));
7904 emit_insn (gen_adddi3 (ptr, ptr, GEN_INT (lo)));
7905 seq = emit_insn (gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx,
7910 seq = emit_insn (gen_adddi3 (stack_pointer_rtx, ptr,
7911 GEN_INT (-leftover)));
7914 /* This alternative is special, because the DWARF code cannot
7915 possibly intuit through the loop above. So we invent this
7916 note it looks at instead. */
7917 RTX_FRAME_RELATED_P (seq) = 1;
7918 add_reg_note (seq, REG_FRAME_RELATED_EXPR,
7919 gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7920 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
7921 GEN_INT (TARGET_ABI_UNICOSMK
7926 if (!TARGET_ABI_UNICOSMK)
7928 HOST_WIDE_INT sa_bias = 0;
7930 /* Cope with very large offsets to the register save area. */
7931 sa_reg = stack_pointer_rtx;
7932 if (reg_offset + sa_size > 0x8000)
7934 int low = ((reg_offset & 0xffff) ^ 0x8000) - 0x8000;
7937 if (low + sa_size <= 0x8000)
7938 sa_bias = reg_offset - low, reg_offset = low;
7940 sa_bias = reg_offset, reg_offset = 0;
7942 sa_reg = gen_rtx_REG (DImode, 24);
7943 sa_bias_rtx = GEN_INT (sa_bias);
7945 if (add_operand (sa_bias_rtx, DImode))
7946 emit_insn (gen_adddi3 (sa_reg, stack_pointer_rtx, sa_bias_rtx));
7949 emit_move_insn (sa_reg, sa_bias_rtx);
7950 emit_insn (gen_adddi3 (sa_reg, stack_pointer_rtx, sa_reg));
7954 /* Save regs in stack order. Beginning with VMS PV. */
7955 if (TARGET_ABI_OPEN_VMS && alpha_procedure_type == PT_STACK)
7956 emit_frame_store (REG_PV, stack_pointer_rtx, 0, 0);
7958 /* Save register RA next. */
7959 if (imask & (1UL << REG_RA))
7961 emit_frame_store (REG_RA, sa_reg, sa_bias, reg_offset);
7962 imask &= ~(1UL << REG_RA);
7966 /* Now save any other registers required to be saved. */
7967 for (i = 0; i < 31; i++)
7968 if (imask & (1UL << i))
7970 emit_frame_store (i, sa_reg, sa_bias, reg_offset);
7974 for (i = 0; i < 31; i++)
7975 if (fmask & (1UL << i))
7977 emit_frame_store (i+32, sa_reg, sa_bias, reg_offset);
7981 else if (TARGET_ABI_UNICOSMK && alpha_procedure_type == PT_STACK)
7983 /* The standard frame on the T3E includes space for saving registers.
7984 We just have to use it. We don't have to save the return address and
7985 the old frame pointer here - they are saved in the DSIB. */
7988 for (i = 9; i < 15; i++)
7989 if (imask & (1UL << i))
7991 emit_frame_store (i, hard_frame_pointer_rtx, 0, reg_offset);
7994 for (i = 2; i < 10; i++)
7995 if (fmask & (1UL << i))
7997 emit_frame_store (i+32, hard_frame_pointer_rtx, 0, reg_offset);
8002 if (TARGET_ABI_OPEN_VMS)
8004 /* Register frame procedures save the fp. */
8005 if (alpha_procedure_type == PT_REGISTER)
8007 rtx insn = emit_move_insn (gen_rtx_REG (DImode, vms_save_fp_regno),
8008 hard_frame_pointer_rtx);
8009 add_reg_note (insn, REG_CFA_REGISTER, NULL);
8010 RTX_FRAME_RELATED_P (insn) = 1;
8013 if (alpha_procedure_type != PT_NULL && vms_base_regno != REG_PV)
8014 emit_insn (gen_force_movdi (gen_rtx_REG (DImode, vms_base_regno),
8015 gen_rtx_REG (DImode, REG_PV)));
8017 if (alpha_procedure_type != PT_NULL
8018 && vms_unwind_regno == HARD_FRAME_POINTER_REGNUM)
8019 FRP (emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx));
8021 /* If we have to allocate space for outgoing args, do it now. */
8022 if (crtl->outgoing_args_size != 0)
8025 = emit_move_insn (stack_pointer_rtx,
8027 (hard_frame_pointer_rtx,
8029 (crtl->outgoing_args_size))));
8031 /* Only set FRAME_RELATED_P on the stack adjustment we just emitted
8032 if ! frame_pointer_needed. Setting the bit will change the CFA
8033 computation rule to use sp again, which would be wrong if we had
8034 frame_pointer_needed, as this means sp might move unpredictably
8038 frame_pointer_needed
8039 => vms_unwind_regno == HARD_FRAME_POINTER_REGNUM
8041 crtl->outgoing_args_size != 0
8042 => alpha_procedure_type != PT_NULL,
8044 so when we are not setting the bit here, we are guaranteed to
8045 have emitted an FRP frame pointer update just before. */
8046 RTX_FRAME_RELATED_P (seq) = ! frame_pointer_needed;
8049 else if (!TARGET_ABI_UNICOSMK)
8051 /* If we need a frame pointer, set it from the stack pointer. */
8052 if (frame_pointer_needed)
8054 if (TARGET_CAN_FAULT_IN_PROLOGUE)
8055 FRP (emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx));
8057 /* This must always be the last instruction in the
8058 prologue, thus we emit a special move + clobber. */
8059 FRP (emit_insn (gen_init_fp (hard_frame_pointer_rtx,
8060 stack_pointer_rtx, sa_reg)));
8064 /* The ABIs for VMS and OSF/1 say that while we can schedule insns into
8065 the prologue, for exception handling reasons, we cannot do this for
8066 any insn that might fault. We could prevent this for mems with a
8067 (clobber:BLK (scratch)), but this doesn't work for fp insns. So we
8068 have to prevent all such scheduling with a blockage.
8070 Linux, on the other hand, never bothered to implement OSF/1's
8071 exception handling, and so doesn't care about such things. Anyone
8072 planning to use dwarf2 frame-unwind info can also omit the blockage. */
8074 if (! TARGET_CAN_FAULT_IN_PROLOGUE)
8075 emit_insn (gen_blockage ());
8078 /* Count the number of .file directives, so that .loc is up to date. */
8079 int num_source_filenames = 0;
8081 /* Output the textual info surrounding the prologue. */
8084 alpha_start_function (FILE *file, const char *fnname,
8085 tree decl ATTRIBUTE_UNUSED)
8087 unsigned long imask = 0;
8088 unsigned long fmask = 0;
8089 /* Stack space needed for pushing registers clobbered by us. */
8090 HOST_WIDE_INT sa_size;
8091 /* Complete stack size needed. */
8092 unsigned HOST_WIDE_INT frame_size;
8093 /* The maximum debuggable frame size (512 Kbytes using Tru64 as). */
8094 unsigned HOST_WIDE_INT max_frame_size = TARGET_ABI_OSF && !TARGET_GAS
8097 /* Offset from base reg to register save area. */
8098 HOST_WIDE_INT reg_offset;
8099 char *entry_label = (char *) alloca (strlen (fnname) + 6);
8100 char *tramp_label = (char *) alloca (strlen (fnname) + 6);
8103 /* Don't emit an extern directive for functions defined in the same file. */
8104 if (TARGET_ABI_UNICOSMK)
8107 name_tree = get_identifier (fnname);
8108 TREE_ASM_WRITTEN (name_tree) = 1;
8111 #if TARGET_ABI_OPEN_VMS
8113 && strncmp (vms_debug_main, fnname, strlen (vms_debug_main)) == 0)
8115 targetm.asm_out.globalize_label (asm_out_file, VMS_DEBUG_MAIN_POINTER);
8116 ASM_OUTPUT_DEF (asm_out_file, VMS_DEBUG_MAIN_POINTER, fnname);
8117 switch_to_section (text_section);
8118 vms_debug_main = NULL;
8122 alpha_fnname = fnname;
8123 sa_size = alpha_sa_size ();
8125 frame_size = get_frame_size ();
8126 if (TARGET_ABI_OPEN_VMS)
8127 frame_size = ALPHA_ROUND (sa_size
8128 + (alpha_procedure_type == PT_STACK ? 8 : 0)
8130 + crtl->args.pretend_args_size);
8131 else if (TARGET_ABI_UNICOSMK)
8132 frame_size = ALPHA_ROUND (sa_size
8133 + (alpha_procedure_type == PT_STACK ? 48 : 0))
8134 + ALPHA_ROUND (frame_size
8135 + crtl->outgoing_args_size);
8137 frame_size = (ALPHA_ROUND (crtl->outgoing_args_size)
8139 + ALPHA_ROUND (frame_size
8140 + crtl->args.pretend_args_size));
8142 if (TARGET_ABI_OPEN_VMS)
8143 reg_offset = 8 + 8 * cfun->machine->uses_condition_handler;
8145 reg_offset = ALPHA_ROUND (crtl->outgoing_args_size);
8147 alpha_sa_mask (&imask, &fmask);
8149 /* Ecoff can handle multiple .file directives, so put out file and lineno.
8150 We have to do that before the .ent directive as we cannot switch
8151 files within procedures with native ecoff because line numbers are
8152 linked to procedure descriptors.
8153 Outputting the lineno helps debugging of one line functions as they
8154 would otherwise get no line number at all. Please note that we would
8155 like to put out last_linenum from final.c, but it is not accessible. */
8157 if (write_symbols == SDB_DEBUG)
8159 #ifdef ASM_OUTPUT_SOURCE_FILENAME
8160 ASM_OUTPUT_SOURCE_FILENAME (file,
8161 DECL_SOURCE_FILE (current_function_decl));
8163 #ifdef SDB_OUTPUT_SOURCE_LINE
8164 if (debug_info_level != DINFO_LEVEL_TERSE)
8165 SDB_OUTPUT_SOURCE_LINE (file,
8166 DECL_SOURCE_LINE (current_function_decl));
8170 /* Issue function start and label. */
8171 if (TARGET_ABI_OPEN_VMS
8172 || (!TARGET_ABI_UNICOSMK && !flag_inhibit_size_directive))
8174 fputs ("\t.ent ", file);
8175 assemble_name (file, fnname);
8178 /* If the function needs GP, we'll write the "..ng" label there.
8179 Otherwise, do it here. */
8181 && ! alpha_function_needs_gp
8182 && ! cfun->is_thunk)
8185 assemble_name (file, fnname);
8186 fputs ("..ng:\n", file);
8189 /* Nested functions on VMS that are potentially called via trampoline
8190 get a special transfer entry point that loads the called functions
8191 procedure descriptor and static chain. */
8192 if (TARGET_ABI_OPEN_VMS
8193 && !TREE_PUBLIC (decl)
8194 && DECL_CONTEXT (decl)
8195 && !TYPE_P (DECL_CONTEXT (decl)))
8197 strcpy (tramp_label, fnname);
8198 strcat (tramp_label, "..tr");
8199 ASM_OUTPUT_LABEL (file, tramp_label);
8200 fprintf (file, "\tldq $1,24($27)\n");
8201 fprintf (file, "\tldq $27,16($27)\n");
8204 strcpy (entry_label, fnname);
8205 if (TARGET_ABI_OPEN_VMS)
8206 strcat (entry_label, "..en");
8208 /* For public functions, the label must be globalized by appending an
8209 additional colon. */
8210 if (TARGET_ABI_UNICOSMK && TREE_PUBLIC (decl))
8211 strcat (entry_label, ":");
8213 ASM_OUTPUT_LABEL (file, entry_label);
8214 inside_function = TRUE;
8216 if (TARGET_ABI_OPEN_VMS)
8217 fprintf (file, "\t.base $%d\n", vms_base_regno);
8219 if (!TARGET_ABI_OPEN_VMS && !TARGET_ABI_UNICOSMK && TARGET_IEEE_CONFORMANT
8220 && !flag_inhibit_size_directive)
8222 /* Set flags in procedure descriptor to request IEEE-conformant
8223 math-library routines. The value we set it to is PDSC_EXC_IEEE
8224 (/usr/include/pdsc.h). */
8225 fputs ("\t.eflag 48\n", file);
8228 /* Set up offsets to alpha virtual arg/local debugging pointer. */
8229 alpha_auto_offset = -frame_size + crtl->args.pretend_args_size;
8230 alpha_arg_offset = -frame_size + 48;
8232 /* Describe our frame. If the frame size is larger than an integer,
8233 print it as zero to avoid an assembler error. We won't be
8234 properly describing such a frame, but that's the best we can do. */
8235 if (TARGET_ABI_UNICOSMK)
8237 else if (TARGET_ABI_OPEN_VMS)
8238 fprintf (file, "\t.frame $%d," HOST_WIDE_INT_PRINT_DEC ",$26,"
8239 HOST_WIDE_INT_PRINT_DEC "\n",
8241 frame_size >= (1UL << 31) ? 0 : frame_size,
8243 else if (!flag_inhibit_size_directive)
8244 fprintf (file, "\t.frame $%d," HOST_WIDE_INT_PRINT_DEC ",$26,%d\n",
8245 (frame_pointer_needed
8246 ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM),
8247 frame_size >= max_frame_size ? 0 : frame_size,
8248 crtl->args.pretend_args_size);
8250 /* Describe which registers were spilled. */
8251 if (TARGET_ABI_UNICOSMK)
8253 else if (TARGET_ABI_OPEN_VMS)
8256 /* ??? Does VMS care if mask contains ra? The old code didn't
8257 set it, so I don't here. */
8258 fprintf (file, "\t.mask 0x%lx,0\n", imask & ~(1UL << REG_RA));
8260 fprintf (file, "\t.fmask 0x%lx,0\n", fmask);
8261 if (alpha_procedure_type == PT_REGISTER)
8262 fprintf (file, "\t.fp_save $%d\n", vms_save_fp_regno);
8264 else if (!flag_inhibit_size_directive)
8268 fprintf (file, "\t.mask 0x%lx," HOST_WIDE_INT_PRINT_DEC "\n", imask,
8269 frame_size >= max_frame_size ? 0 : reg_offset - frame_size);
8271 for (i = 0; i < 32; ++i)
8272 if (imask & (1UL << i))
8277 fprintf (file, "\t.fmask 0x%lx," HOST_WIDE_INT_PRINT_DEC "\n", fmask,
8278 frame_size >= max_frame_size ? 0 : reg_offset - frame_size);
8281 #if TARGET_ABI_OPEN_VMS
8282 /* If a user condition handler has been installed at some point, emit
8283 the procedure descriptor bits to point the Condition Handling Facility
8284 at the indirection wrapper, and state the fp offset at which the user
8285 handler may be found. */
8286 if (cfun->machine->uses_condition_handler)
8288 fprintf (file, "\t.handler __gcc_shell_handler\n");
8289 fprintf (file, "\t.handler_data %d\n", VMS_COND_HANDLER_FP_OFFSET);
8292 /* Ifdef'ed cause link_section are only available then. */
8293 switch_to_section (readonly_data_section);
8294 fprintf (file, "\t.align 3\n");
8295 assemble_name (file, fnname); fputs ("..na:\n", file);
8296 fputs ("\t.ascii \"", file);
8297 assemble_name (file, fnname);
8298 fputs ("\\0\"\n", file);
8299 alpha_need_linkage (fnname, 1);
8300 switch_to_section (text_section);
8304 /* Emit the .prologue note at the scheduled end of the prologue. */
8307 alpha_output_function_end_prologue (FILE *file)
8309 if (TARGET_ABI_UNICOSMK)
8311 else if (TARGET_ABI_OPEN_VMS)
8312 fputs ("\t.prologue\n", file);
8313 else if (TARGET_ABI_WINDOWS_NT)
8314 fputs ("\t.prologue 0\n", file);
8315 else if (!flag_inhibit_size_directive)
8316 fprintf (file, "\t.prologue %d\n",
8317 alpha_function_needs_gp || cfun->is_thunk);
8320 /* Write function epilogue. */
8323 alpha_expand_epilogue (void)
8325 /* Registers to save. */
8326 unsigned long imask = 0;
8327 unsigned long fmask = 0;
8328 /* Stack space needed for pushing registers clobbered by us. */
8329 HOST_WIDE_INT sa_size;
8330 /* Complete stack size needed. */
8331 HOST_WIDE_INT frame_size;
8332 /* Offset from base reg to register save area. */
8333 HOST_WIDE_INT reg_offset;
8334 int fp_is_frame_pointer, fp_offset;
8335 rtx sa_reg, sa_reg_exp = NULL;
8336 rtx sp_adj1, sp_adj2, mem, reg, insn;
8338 rtx cfa_restores = NULL_RTX;
8341 sa_size = alpha_sa_size ();
8343 frame_size = get_frame_size ();
8344 if (TARGET_ABI_OPEN_VMS)
8345 frame_size = ALPHA_ROUND (sa_size
8346 + (alpha_procedure_type == PT_STACK ? 8 : 0)
8348 + crtl->args.pretend_args_size);
8349 else if (TARGET_ABI_UNICOSMK)
8350 frame_size = ALPHA_ROUND (sa_size
8351 + (alpha_procedure_type == PT_STACK ? 48 : 0))
8352 + ALPHA_ROUND (frame_size
8353 + crtl->outgoing_args_size);
8355 frame_size = (ALPHA_ROUND (crtl->outgoing_args_size)
8357 + ALPHA_ROUND (frame_size
8358 + crtl->args.pretend_args_size));
8360 if (TARGET_ABI_OPEN_VMS)
8362 if (alpha_procedure_type == PT_STACK)
8363 reg_offset = 8 + 8 * cfun->machine->uses_condition_handler;
8368 reg_offset = ALPHA_ROUND (crtl->outgoing_args_size);
8370 alpha_sa_mask (&imask, &fmask);
8373 = ((TARGET_ABI_OPEN_VMS && alpha_procedure_type == PT_STACK)
8374 || (!TARGET_ABI_OPEN_VMS && frame_pointer_needed));
8376 sa_reg = stack_pointer_rtx;
8378 if (crtl->calls_eh_return)
8379 eh_ofs = EH_RETURN_STACKADJ_RTX;
8383 if (!TARGET_ABI_UNICOSMK && sa_size)
8385 /* If we have a frame pointer, restore SP from it. */
8386 if ((TARGET_ABI_OPEN_VMS
8387 && vms_unwind_regno == HARD_FRAME_POINTER_REGNUM)
8388 || (!TARGET_ABI_OPEN_VMS && frame_pointer_needed))
8389 emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
8391 /* Cope with very large offsets to the register save area. */
8392 if (reg_offset + sa_size > 0x8000)
8394 int low = ((reg_offset & 0xffff) ^ 0x8000) - 0x8000;
8397 if (low + sa_size <= 0x8000)
8398 bias = reg_offset - low, reg_offset = low;
8400 bias = reg_offset, reg_offset = 0;
8402 sa_reg = gen_rtx_REG (DImode, 22);
8403 sa_reg_exp = plus_constant (stack_pointer_rtx, bias);
8405 emit_move_insn (sa_reg, sa_reg_exp);
8408 /* Restore registers in order, excepting a true frame pointer. */
8410 mem = gen_rtx_MEM (DImode, plus_constant (sa_reg, reg_offset));
8412 set_mem_alias_set (mem, alpha_sr_alias_set);
8413 reg = gen_rtx_REG (DImode, REG_RA);
8414 emit_move_insn (reg, mem);
8415 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
8418 imask &= ~(1UL << REG_RA);
8420 for (i = 0; i < 31; ++i)
8421 if (imask & (1UL << i))
8423 if (i == HARD_FRAME_POINTER_REGNUM && fp_is_frame_pointer)
8424 fp_offset = reg_offset;
8427 mem = gen_rtx_MEM (DImode, plus_constant(sa_reg, reg_offset));
8428 set_mem_alias_set (mem, alpha_sr_alias_set);
8429 reg = gen_rtx_REG (DImode, i);
8430 emit_move_insn (reg, mem);
8431 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg,
8437 for (i = 0; i < 31; ++i)
8438 if (fmask & (1UL << i))
8440 mem = gen_rtx_MEM (DFmode, plus_constant(sa_reg, reg_offset));
8441 set_mem_alias_set (mem, alpha_sr_alias_set);
8442 reg = gen_rtx_REG (DFmode, i+32);
8443 emit_move_insn (reg, mem);
8444 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
8448 else if (TARGET_ABI_UNICOSMK && alpha_procedure_type == PT_STACK)
8450 /* Restore callee-saved general-purpose registers. */
8454 for (i = 9; i < 15; i++)
8455 if (imask & (1UL << i))
8457 mem = gen_rtx_MEM (DImode, plus_constant(hard_frame_pointer_rtx,
8459 set_mem_alias_set (mem, alpha_sr_alias_set);
8460 reg = gen_rtx_REG (DImode, i);
8461 emit_move_insn (reg, mem);
8462 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
8466 for (i = 2; i < 10; i++)
8467 if (fmask & (1UL << i))
8469 mem = gen_rtx_MEM (DFmode, plus_constant(hard_frame_pointer_rtx,
8471 set_mem_alias_set (mem, alpha_sr_alias_set);
8472 reg = gen_rtx_REG (DFmode, i+32);
8473 emit_move_insn (reg, mem);
8474 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
8478 /* Restore the return address from the DSIB. */
8479 mem = gen_rtx_MEM (DImode, plus_constant (hard_frame_pointer_rtx, -8));
8480 set_mem_alias_set (mem, alpha_sr_alias_set);
8481 reg = gen_rtx_REG (DImode, REG_RA);
8482 emit_move_insn (reg, mem);
8483 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
8486 if (frame_size || eh_ofs)
8488 sp_adj1 = stack_pointer_rtx;
8492 sp_adj1 = gen_rtx_REG (DImode, 23);
8493 emit_move_insn (sp_adj1,
8494 gen_rtx_PLUS (Pmode, stack_pointer_rtx, eh_ofs));
8497 /* If the stack size is large, begin computation into a temporary
8498 register so as not to interfere with a potential fp restore,
8499 which must be consecutive with an SP restore. */
8500 if (frame_size < 32768
8501 && ! (TARGET_ABI_UNICOSMK && cfun->calls_alloca))
8502 sp_adj2 = GEN_INT (frame_size);
8503 else if (TARGET_ABI_UNICOSMK)
8505 sp_adj1 = gen_rtx_REG (DImode, 23);
8506 emit_move_insn (sp_adj1, hard_frame_pointer_rtx);
8507 sp_adj2 = const0_rtx;
8509 else if (frame_size < 0x40007fffL)
8511 int low = ((frame_size & 0xffff) ^ 0x8000) - 0x8000;
8513 sp_adj2 = plus_constant (sp_adj1, frame_size - low);
8514 if (sa_reg_exp && rtx_equal_p (sa_reg_exp, sp_adj2))
8518 sp_adj1 = gen_rtx_REG (DImode, 23);
8519 emit_move_insn (sp_adj1, sp_adj2);
8521 sp_adj2 = GEN_INT (low);
8525 rtx tmp = gen_rtx_REG (DImode, 23);
8526 sp_adj2 = alpha_emit_set_const (tmp, DImode, frame_size, 3, false);
8529 /* We can't drop new things to memory this late, afaik,
8530 so build it up by pieces. */
8531 sp_adj2 = alpha_emit_set_long_const (tmp, frame_size,
8533 gcc_assert (sp_adj2);
8537 /* From now on, things must be in order. So emit blockages. */
8539 /* Restore the frame pointer. */
8540 if (TARGET_ABI_UNICOSMK)
8542 emit_insn (gen_blockage ());
8543 mem = gen_rtx_MEM (DImode,
8544 plus_constant (hard_frame_pointer_rtx, -16));
8545 set_mem_alias_set (mem, alpha_sr_alias_set);
8546 emit_move_insn (hard_frame_pointer_rtx, mem);
8547 cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
8548 hard_frame_pointer_rtx, cfa_restores);
8550 else if (fp_is_frame_pointer)
8552 emit_insn (gen_blockage ());
8553 mem = gen_rtx_MEM (DImode, plus_constant (sa_reg, fp_offset));
8554 set_mem_alias_set (mem, alpha_sr_alias_set);
8555 emit_move_insn (hard_frame_pointer_rtx, mem);
8556 cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
8557 hard_frame_pointer_rtx, cfa_restores);
8559 else if (TARGET_ABI_OPEN_VMS)
8561 emit_insn (gen_blockage ());
8562 emit_move_insn (hard_frame_pointer_rtx,
8563 gen_rtx_REG (DImode, vms_save_fp_regno));
8564 cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
8565 hard_frame_pointer_rtx, cfa_restores);
8568 /* Restore the stack pointer. */
8569 emit_insn (gen_blockage ());
8570 if (sp_adj2 == const0_rtx)
8571 insn = emit_move_insn (stack_pointer_rtx, sp_adj1);
8573 insn = emit_move_insn (stack_pointer_rtx,
8574 gen_rtx_PLUS (DImode, sp_adj1, sp_adj2));
8575 REG_NOTES (insn) = cfa_restores;
8576 add_reg_note (insn, REG_CFA_DEF_CFA, stack_pointer_rtx);
8577 RTX_FRAME_RELATED_P (insn) = 1;
8581 gcc_assert (cfa_restores == NULL);
8583 if (TARGET_ABI_OPEN_VMS && alpha_procedure_type == PT_REGISTER)
8585 emit_insn (gen_blockage ());
8586 insn = emit_move_insn (hard_frame_pointer_rtx,
8587 gen_rtx_REG (DImode, vms_save_fp_regno));
8588 add_reg_note (insn, REG_CFA_RESTORE, hard_frame_pointer_rtx);
8589 RTX_FRAME_RELATED_P (insn) = 1;
8591 else if (TARGET_ABI_UNICOSMK && alpha_procedure_type != PT_STACK)
8593 /* Decrement the frame pointer if the function does not have a
8595 emit_insn (gen_blockage ());
8596 emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
8597 hard_frame_pointer_rtx, constm1_rtx));
8602 /* Output the rest of the textual info surrounding the epilogue. */
8605 alpha_end_function (FILE *file, const char *fnname, tree decl ATTRIBUTE_UNUSED)
8609 /* We output a nop after noreturn calls at the very end of the function to
8610 ensure that the return address always remains in the caller's code range,
8611 as not doing so might confuse unwinding engines. */
8612 insn = get_last_insn ();
8614 insn = prev_active_insn (insn);
8615 if (insn && CALL_P (insn))
8616 output_asm_insn (get_insn_template (CODE_FOR_nop, NULL), NULL);
8618 #if TARGET_ABI_OPEN_VMS
8619 alpha_write_linkage (file, fnname, decl);
8622 /* End the function. */
8623 if (!TARGET_ABI_UNICOSMK && !flag_inhibit_size_directive)
8625 fputs ("\t.end ", file);
8626 assemble_name (file, fnname);
8629 inside_function = FALSE;
8631 /* Output jump tables and the static subroutine information block. */
8632 if (TARGET_ABI_UNICOSMK)
8634 unicosmk_output_ssib (file, fnname);
8635 unicosmk_output_deferred_case_vectors (file);
8639 #if TARGET_ABI_OPEN_VMS
8640 void avms_asm_output_external (FILE *file, tree decl ATTRIBUTE_UNUSED, const char *name)
8642 #ifdef DO_CRTL_NAMES
8649 /* Emit a tail call to FUNCTION after adjusting THIS by DELTA.
8651 In order to avoid the hordes of differences between generated code
8652 with and without TARGET_EXPLICIT_RELOCS, and to avoid duplicating
8653 lots of code loading up large constants, generate rtl and emit it
8654 instead of going straight to text.
8656 Not sure why this idea hasn't been explored before... */
8659 alpha_output_mi_thunk_osf (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
8660 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
8663 HOST_WIDE_INT hi, lo;
8664 rtx this_rtx, insn, funexp;
8666 /* We always require a valid GP. */
8667 emit_insn (gen_prologue_ldgp ());
8668 emit_note (NOTE_INSN_PROLOGUE_END);
8670 /* Find the "this" pointer. If the function returns a structure,
8671 the structure return pointer is in $16. */
8672 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
8673 this_rtx = gen_rtx_REG (Pmode, 17);
8675 this_rtx = gen_rtx_REG (Pmode, 16);
8677 /* Add DELTA. When possible we use ldah+lda. Otherwise load the
8678 entire constant for the add. */
8679 lo = ((delta & 0xffff) ^ 0x8000) - 0x8000;
8680 hi = (((delta - lo) & 0xffffffff) ^ 0x80000000) - 0x80000000;
8681 if (hi + lo == delta)
8684 emit_insn (gen_adddi3 (this_rtx, this_rtx, GEN_INT (hi)));
8686 emit_insn (gen_adddi3 (this_rtx, this_rtx, GEN_INT (lo)));
8690 rtx tmp = alpha_emit_set_long_const (gen_rtx_REG (Pmode, 0),
8691 delta, -(delta < 0));
8692 emit_insn (gen_adddi3 (this_rtx, this_rtx, tmp));
8695 /* Add a delta stored in the vtable at VCALL_OFFSET. */
8700 tmp = gen_rtx_REG (Pmode, 0);
8701 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this_rtx));
8703 lo = ((vcall_offset & 0xffff) ^ 0x8000) - 0x8000;
8704 hi = (((vcall_offset - lo) & 0xffffffff) ^ 0x80000000) - 0x80000000;
8705 if (hi + lo == vcall_offset)
8708 emit_insn (gen_adddi3 (tmp, tmp, GEN_INT (hi)));
8712 tmp2 = alpha_emit_set_long_const (gen_rtx_REG (Pmode, 1),
8713 vcall_offset, -(vcall_offset < 0));
8714 emit_insn (gen_adddi3 (tmp, tmp, tmp2));
8718 tmp2 = gen_rtx_PLUS (Pmode, tmp, GEN_INT (lo));
8721 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp2));
8723 emit_insn (gen_adddi3 (this_rtx, this_rtx, tmp));
8726 /* Generate a tail call to the target function. */
8727 if (! TREE_USED (function))
8729 assemble_external (function);
8730 TREE_USED (function) = 1;
8732 funexp = XEXP (DECL_RTL (function), 0);
8733 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
8734 insn = emit_call_insn (gen_sibcall (funexp, const0_rtx));
8735 SIBLING_CALL_P (insn) = 1;
8737 /* Run just enough of rest_of_compilation to get the insns emitted.
8738 There's not really enough bulk here to make other passes such as
8739 instruction scheduling worth while. Note that use_thunk calls
8740 assemble_start_function and assemble_end_function. */
8741 insn = get_insns ();
8742 insn_locators_alloc ();
8743 shorten_branches (insn);
8744 final_start_function (insn, file, 1);
8745 final (insn, file, 1);
8746 final_end_function ();
8748 #endif /* TARGET_ABI_OSF */
8750 /* Debugging support. */
8754 /* Count the number of sdb related labels are generated (to find block
8755 start and end boundaries). */
8757 int sdb_label_count = 0;
8759 /* Name of the file containing the current function. */
8761 static const char *current_function_file = "";
8763 /* Offsets to alpha virtual arg/local debugging pointers. */
8765 long alpha_arg_offset;
8766 long alpha_auto_offset;
8768 /* Emit a new filename to a stream. */
8771 alpha_output_filename (FILE *stream, const char *name)
8773 static int first_time = TRUE;
8778 ++num_source_filenames;
8779 current_function_file = name;
8780 fprintf (stream, "\t.file\t%d ", num_source_filenames);
8781 output_quoted_string (stream, name);
8782 fprintf (stream, "\n");
8783 if (!TARGET_GAS && write_symbols == DBX_DEBUG)
8784 fprintf (stream, "\t#@stabs\n");
8787 else if (write_symbols == DBX_DEBUG)
8788 /* dbxout.c will emit an appropriate .stabs directive. */
8791 else if (name != current_function_file
8792 && strcmp (name, current_function_file) != 0)
8794 if (inside_function && ! TARGET_GAS)
8795 fprintf (stream, "\t#.file\t%d ", num_source_filenames);
8798 ++num_source_filenames;
8799 current_function_file = name;
8800 fprintf (stream, "\t.file\t%d ", num_source_filenames);
8803 output_quoted_string (stream, name);
8804 fprintf (stream, "\n");
8808 /* Structure to show the current status of registers and memory. */
8810 struct shadow_summary
8813 unsigned int i : 31; /* Mask of int regs */
8814 unsigned int fp : 31; /* Mask of fp regs */
8815 unsigned int mem : 1; /* mem == imem | fpmem */
8819 /* Summary the effects of expression X on the machine. Update SUM, a pointer
8820 to the summary structure. SET is nonzero if the insn is setting the
8821 object, otherwise zero. */
8824 summarize_insn (rtx x, struct shadow_summary *sum, int set)
8826 const char *format_ptr;
8832 switch (GET_CODE (x))
8834 /* ??? Note that this case would be incorrect if the Alpha had a
8835 ZERO_EXTRACT in SET_DEST. */
8837 summarize_insn (SET_SRC (x), sum, 0);
8838 summarize_insn (SET_DEST (x), sum, 1);
8842 summarize_insn (XEXP (x, 0), sum, 1);
8846 summarize_insn (XEXP (x, 0), sum, 0);
8850 for (i = ASM_OPERANDS_INPUT_LENGTH (x) - 1; i >= 0; i--)
8851 summarize_insn (ASM_OPERANDS_INPUT (x, i), sum, 0);
8855 for (i = XVECLEN (x, 0) - 1; i >= 0; i--)
8856 summarize_insn (XVECEXP (x, 0, i), sum, 0);
8860 summarize_insn (SUBREG_REG (x), sum, 0);
8865 int regno = REGNO (x);
8866 unsigned long mask = ((unsigned long) 1) << (regno % 32);
8868 if (regno == 31 || regno == 63)
8874 sum->defd.i |= mask;
8876 sum->defd.fp |= mask;
8881 sum->used.i |= mask;
8883 sum->used.fp |= mask;
8894 /* Find the regs used in memory address computation: */
8895 summarize_insn (XEXP (x, 0), sum, 0);
8898 case CONST_INT: case CONST_DOUBLE:
8899 case SYMBOL_REF: case LABEL_REF: case CONST:
8900 case SCRATCH: case ASM_INPUT:
8903 /* Handle common unary and binary ops for efficiency. */
8904 case COMPARE: case PLUS: case MINUS: case MULT: case DIV:
8905 case MOD: case UDIV: case UMOD: case AND: case IOR:
8906 case XOR: case ASHIFT: case ROTATE: case ASHIFTRT: case LSHIFTRT:
8907 case ROTATERT: case SMIN: case SMAX: case UMIN: case UMAX:
8908 case NE: case EQ: case GE: case GT: case LE:
8909 case LT: case GEU: case GTU: case LEU: case LTU:
8910 summarize_insn (XEXP (x, 0), sum, 0);
8911 summarize_insn (XEXP (x, 1), sum, 0);
8914 case NEG: case NOT: case SIGN_EXTEND: case ZERO_EXTEND:
8915 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: case FLOAT:
8916 case FIX: case UNSIGNED_FLOAT: case UNSIGNED_FIX: case ABS:
8917 case SQRT: case FFS:
8918 summarize_insn (XEXP (x, 0), sum, 0);
8922 format_ptr = GET_RTX_FORMAT (GET_CODE (x));
8923 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
8924 switch (format_ptr[i])
8927 summarize_insn (XEXP (x, i), sum, 0);
8931 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8932 summarize_insn (XVECEXP (x, i, j), sum, 0);
8944 /* Ensure a sufficient number of `trapb' insns are in the code when
8945 the user requests code with a trap precision of functions or
8948 In naive mode, when the user requests a trap-precision of
8949 "instruction", a trapb is needed after every instruction that may
8950 generate a trap. This ensures that the code is resumption safe but
8953 When optimizations are turned on, we delay issuing a trapb as long
8954 as possible. In this context, a trap shadow is the sequence of
8955 instructions that starts with a (potentially) trap generating
8956 instruction and extends to the next trapb or call_pal instruction
8957 (but GCC never generates call_pal by itself). We can delay (and
8958 therefore sometimes omit) a trapb subject to the following
8961 (a) On entry to the trap shadow, if any Alpha register or memory
8962 location contains a value that is used as an operand value by some
8963 instruction in the trap shadow (live on entry), then no instruction
8964 in the trap shadow may modify the register or memory location.
8966 (b) Within the trap shadow, the computation of the base register
8967 for a memory load or store instruction may not involve using the
8968 result of an instruction that might generate an UNPREDICTABLE
8971 (c) Within the trap shadow, no register may be used more than once
8972 as a destination register. (This is to make life easier for the
8975 (d) The trap shadow may not include any branch instructions. */
8978 alpha_handle_trap_shadows (void)
8980 struct shadow_summary shadow;
8981 int trap_pending, exception_nesting;
8985 exception_nesting = 0;
8988 shadow.used.mem = 0;
8989 shadow.defd = shadow.used;
8991 for (i = get_insns (); i ; i = NEXT_INSN (i))
8995 switch (NOTE_KIND (i))
8997 case NOTE_INSN_EH_REGION_BEG:
8998 exception_nesting++;
9003 case NOTE_INSN_EH_REGION_END:
9004 exception_nesting--;
9009 case NOTE_INSN_EPILOGUE_BEG:
9010 if (trap_pending && alpha_tp >= ALPHA_TP_FUNC)
9015 else if (trap_pending)
9017 if (alpha_tp == ALPHA_TP_FUNC)
9020 && GET_CODE (PATTERN (i)) == RETURN)
9023 else if (alpha_tp == ALPHA_TP_INSN)
9027 struct shadow_summary sum;
9032 sum.defd = sum.used;
9034 switch (GET_CODE (i))
9037 /* Annoyingly, get_attr_trap will die on these. */
9038 if (GET_CODE (PATTERN (i)) == USE
9039 || GET_CODE (PATTERN (i)) == CLOBBER)
9042 summarize_insn (PATTERN (i), &sum, 0);
9044 if ((sum.defd.i & shadow.defd.i)
9045 || (sum.defd.fp & shadow.defd.fp))
9047 /* (c) would be violated */
9051 /* Combine shadow with summary of current insn: */
9052 shadow.used.i |= sum.used.i;
9053 shadow.used.fp |= sum.used.fp;
9054 shadow.used.mem |= sum.used.mem;
9055 shadow.defd.i |= sum.defd.i;
9056 shadow.defd.fp |= sum.defd.fp;
9057 shadow.defd.mem |= sum.defd.mem;
9059 if ((sum.defd.i & shadow.used.i)
9060 || (sum.defd.fp & shadow.used.fp)
9061 || (sum.defd.mem & shadow.used.mem))
9063 /* (a) would be violated (also takes care of (b)) */
9064 gcc_assert (get_attr_trap (i) != TRAP_YES
9065 || (!(sum.defd.i & sum.used.i)
9066 && !(sum.defd.fp & sum.used.fp)));
9084 n = emit_insn_before (gen_trapb (), i);
9085 PUT_MODE (n, TImode);
9086 PUT_MODE (i, TImode);
9090 shadow.used.mem = 0;
9091 shadow.defd = shadow.used;
9096 if ((exception_nesting > 0 || alpha_tp >= ALPHA_TP_FUNC)
9097 && NONJUMP_INSN_P (i)
9098 && GET_CODE (PATTERN (i)) != USE
9099 && GET_CODE (PATTERN (i)) != CLOBBER
9100 && get_attr_trap (i) == TRAP_YES)
9102 if (optimize && !trap_pending)
9103 summarize_insn (PATTERN (i), &shadow, 0);
9109 /* Alpha can only issue instruction groups simultaneously if they are
9110 suitably aligned. This is very processor-specific. */
9111 /* There are a number of entries in alphaev4_insn_pipe and alphaev5_insn_pipe
9112 that are marked "fake". These instructions do not exist on that target,
9113 but it is possible to see these insns with deranged combinations of
9114 command-line options, such as "-mtune=ev4 -mmax". Instead of aborting,
9115 choose a result at random. */
9117 enum alphaev4_pipe {
9124 enum alphaev5_pipe {
9135 static enum alphaev4_pipe
9136 alphaev4_insn_pipe (rtx insn)
9138 if (recog_memoized (insn) < 0)
9140 if (get_attr_length (insn) != 4)
9143 switch (get_attr_type (insn))
9159 case TYPE_MVI: /* fake */
9174 case TYPE_FSQRT: /* fake */
9175 case TYPE_FTOI: /* fake */
9176 case TYPE_ITOF: /* fake */
9184 static enum alphaev5_pipe
9185 alphaev5_insn_pipe (rtx insn)
9187 if (recog_memoized (insn) < 0)
9189 if (get_attr_length (insn) != 4)
9192 switch (get_attr_type (insn))
9212 case TYPE_FTOI: /* fake */
9213 case TYPE_ITOF: /* fake */
9228 case TYPE_FSQRT: /* fake */
9239 /* IN_USE is a mask of the slots currently filled within the insn group.
9240 The mask bits come from alphaev4_pipe above. If EV4_IBX is set, then
9241 the insn in EV4_IB0 can be swapped by the hardware into EV4_IB1.
9243 LEN is, of course, the length of the group in bytes. */
9246 alphaev4_next_group (rtx insn, int *pin_use, int *plen)
9253 || GET_CODE (PATTERN (insn)) == CLOBBER
9254 || GET_CODE (PATTERN (insn)) == USE)
9259 enum alphaev4_pipe pipe;
9261 pipe = alphaev4_insn_pipe (insn);
9265 /* Force complex instructions to start new groups. */
9269 /* If this is a completely unrecognized insn, it's an asm.
9270 We don't know how long it is, so record length as -1 to
9271 signal a needed realignment. */
9272 if (recog_memoized (insn) < 0)
9275 len = get_attr_length (insn);
9279 if (in_use & EV4_IB0)
9281 if (in_use & EV4_IB1)
9286 in_use |= EV4_IB0 | EV4_IBX;
9290 if (in_use & EV4_IB0)
9292 if (!(in_use & EV4_IBX) || (in_use & EV4_IB1))
9300 if (in_use & EV4_IB1)
9310 /* Haifa doesn't do well scheduling branches. */
9315 insn = next_nonnote_insn (insn);
9317 if (!insn || ! INSN_P (insn))
9320 /* Let Haifa tell us where it thinks insn group boundaries are. */
9321 if (GET_MODE (insn) == TImode)
9324 if (GET_CODE (insn) == CLOBBER || GET_CODE (insn) == USE)
9329 insn = next_nonnote_insn (insn);
9337 /* IN_USE is a mask of the slots currently filled within the insn group.
9338 The mask bits come from alphaev5_pipe above. If EV5_E01 is set, then
9339 the insn in EV5_E0 can be swapped by the hardware into EV5_E1.
9341 LEN is, of course, the length of the group in bytes. */
9344 alphaev5_next_group (rtx insn, int *pin_use, int *plen)
9351 || GET_CODE (PATTERN (insn)) == CLOBBER
9352 || GET_CODE (PATTERN (insn)) == USE)
9357 enum alphaev5_pipe pipe;
9359 pipe = alphaev5_insn_pipe (insn);
9363 /* Force complex instructions to start new groups. */
9367 /* If this is a completely unrecognized insn, it's an asm.
9368 We don't know how long it is, so record length as -1 to
9369 signal a needed realignment. */
9370 if (recog_memoized (insn) < 0)
9373 len = get_attr_length (insn);
9376 /* ??? Most of the places below, we would like to assert never
9377 happen, as it would indicate an error either in Haifa, or
9378 in the scheduling description. Unfortunately, Haifa never
9379 schedules the last instruction of the BB, so we don't have
9380 an accurate TI bit to go off. */
9382 if (in_use & EV5_E0)
9384 if (in_use & EV5_E1)
9389 in_use |= EV5_E0 | EV5_E01;
9393 if (in_use & EV5_E0)
9395 if (!(in_use & EV5_E01) || (in_use & EV5_E1))
9403 if (in_use & EV5_E1)
9409 if (in_use & EV5_FA)
9411 if (in_use & EV5_FM)
9416 in_use |= EV5_FA | EV5_FAM;
9420 if (in_use & EV5_FA)
9426 if (in_use & EV5_FM)
9439 /* Haifa doesn't do well scheduling branches. */
9440 /* ??? If this is predicted not-taken, slotting continues, except
9441 that no more IBR, FBR, or JSR insns may be slotted. */
9446 insn = next_nonnote_insn (insn);
9448 if (!insn || ! INSN_P (insn))
9451 /* Let Haifa tell us where it thinks insn group boundaries are. */
9452 if (GET_MODE (insn) == TImode)
9455 if (GET_CODE (insn) == CLOBBER || GET_CODE (insn) == USE)
9460 insn = next_nonnote_insn (insn);
9469 alphaev4_next_nop (int *pin_use)
9471 int in_use = *pin_use;
9474 if (!(in_use & EV4_IB0))
9479 else if ((in_use & (EV4_IBX|EV4_IB1)) == EV4_IBX)
9484 else if (TARGET_FP && !(in_use & EV4_IB1))
9497 alphaev5_next_nop (int *pin_use)
9499 int in_use = *pin_use;
9502 if (!(in_use & EV5_E1))
9507 else if (TARGET_FP && !(in_use & EV5_FA))
9512 else if (TARGET_FP && !(in_use & EV5_FM))
9524 /* The instruction group alignment main loop. */
9527 alpha_align_insns (unsigned int max_align,
9528 rtx (*next_group) (rtx, int *, int *),
9529 rtx (*next_nop) (int *))
9531 /* ALIGN is the known alignment for the insn group. */
9533 /* OFS is the offset of the current insn in the insn group. */
9535 int prev_in_use, in_use, len, ldgp;
9538 /* Let shorten branches care for assigning alignments to code labels. */
9539 shorten_branches (get_insns ());
9541 if (align_functions < 4)
9543 else if ((unsigned int) align_functions < max_align)
9544 align = align_functions;
9548 ofs = prev_in_use = 0;
9551 i = next_nonnote_insn (i);
9553 ldgp = alpha_function_needs_gp ? 8 : 0;
9557 next = (*next_group) (i, &in_use, &len);
9559 /* When we see a label, resync alignment etc. */
9562 unsigned int new_align = 1 << label_to_alignment (i);
9564 if (new_align >= align)
9566 align = new_align < max_align ? new_align : max_align;
9570 else if (ofs & (new_align-1))
9571 ofs = (ofs | (new_align-1)) + 1;
9575 /* Handle complex instructions special. */
9576 else if (in_use == 0)
9578 /* Asms will have length < 0. This is a signal that we have
9579 lost alignment knowledge. Assume, however, that the asm
9580 will not mis-align instructions. */
9589 /* If the known alignment is smaller than the recognized insn group,
9590 realign the output. */
9591 else if ((int) align < len)
9593 unsigned int new_log_align = len > 8 ? 4 : 3;
9596 where = prev = prev_nonnote_insn (i);
9597 if (!where || !LABEL_P (where))
9600 /* Can't realign between a call and its gp reload. */
9601 if (! (TARGET_EXPLICIT_RELOCS
9602 && prev && CALL_P (prev)))
9604 emit_insn_before (gen_realign (GEN_INT (new_log_align)), where);
9605 align = 1 << new_log_align;
9610 /* We may not insert padding inside the initial ldgp sequence. */
9614 /* If the group won't fit in the same INT16 as the previous,
9615 we need to add padding to keep the group together. Rather
9616 than simply leaving the insn filling to the assembler, we
9617 can make use of the knowledge of what sorts of instructions
9618 were issued in the previous group to make sure that all of
9619 the added nops are really free. */
9620 else if (ofs + len > (int) align)
9622 int nop_count = (align - ofs) / 4;
9625 /* Insert nops before labels, branches, and calls to truly merge
9626 the execution of the nops with the previous instruction group. */
9627 where = prev_nonnote_insn (i);
9630 if (LABEL_P (where))
9632 rtx where2 = prev_nonnote_insn (where);
9633 if (where2 && JUMP_P (where2))
9636 else if (NONJUMP_INSN_P (where))
9643 emit_insn_before ((*next_nop)(&prev_in_use), where);
9644 while (--nop_count);
9648 ofs = (ofs + len) & (align - 1);
9649 prev_in_use = in_use;
9654 /* Insert an unop between a noreturn function call and GP load. */
9657 alpha_pad_noreturn (void)
9661 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
9664 || !find_reg_note (insn, REG_NORETURN, NULL_RTX))
9667 next = next_active_insn (insn);
9671 rtx pat = PATTERN (next);
9673 if (GET_CODE (pat) == SET
9674 && GET_CODE (SET_SRC (pat)) == UNSPEC_VOLATILE
9675 && XINT (SET_SRC (pat), 1) == UNSPECV_LDGP1)
9676 emit_insn_after (gen_unop (), insn);
9681 /* Machine dependent reorg pass. */
9686 /* Workaround for a linker error that triggers when an
9687 exception handler immediatelly follows a noreturn function.
9689 The instruction stream from an object file:
9691 54: 00 40 5b 6b jsr ra,(t12),58 <__func+0x58>
9692 58: 00 00 ba 27 ldah gp,0(ra)
9693 5c: 00 00 bd 23 lda gp,0(gp)
9694 60: 00 00 7d a7 ldq t12,0(gp)
9695 64: 00 40 5b 6b jsr ra,(t12),68 <__func+0x68>
9697 was converted in the final link pass to:
9699 fdb24: a0 03 40 d3 bsr ra,fe9a8 <_called_func+0x8>
9700 fdb28: 00 00 fe 2f unop
9701 fdb2c: 00 00 fe 2f unop
9702 fdb30: 30 82 7d a7 ldq t12,-32208(gp)
9703 fdb34: 00 40 5b 6b jsr ra,(t12),fdb38 <__func+0x68>
9705 GP load instructions were wrongly cleared by the linker relaxation
9706 pass. This workaround prevents removal of GP loads by inserting
9707 an unop instruction between a noreturn function call and
9708 exception handler prologue. */
9710 if (current_function_has_exception_handlers ())
9711 alpha_pad_noreturn ();
9713 if (alpha_tp != ALPHA_TP_PROG || flag_exceptions)
9714 alpha_handle_trap_shadows ();
9716 /* Due to the number of extra trapb insns, don't bother fixing up
9717 alignment when trap precision is instruction. Moreover, we can
9718 only do our job when sched2 is run. */
9719 if (optimize && !optimize_size
9720 && alpha_tp != ALPHA_TP_INSN
9721 && flag_schedule_insns_after_reload)
9723 if (alpha_tune == PROCESSOR_EV4)
9724 alpha_align_insns (8, alphaev4_next_group, alphaev4_next_nop);
9725 else if (alpha_tune == PROCESSOR_EV5)
9726 alpha_align_insns (16, alphaev5_next_group, alphaev5_next_nop);
9730 #if !TARGET_ABI_UNICOSMK
9737 alpha_file_start (void)
9739 #ifdef OBJECT_FORMAT_ELF
9740 /* If emitting dwarf2 debug information, we cannot generate a .file
9741 directive to start the file, as it will conflict with dwarf2out
9742 file numbers. So it's only useful when emitting mdebug output. */
9743 targetm.file_start_file_directive = (write_symbols == DBX_DEBUG);
9746 default_file_start ();
9748 fprintf (asm_out_file, "\t.verstamp %d %d\n", MS_STAMP, LS_STAMP);
9751 fputs ("\t.set noreorder\n", asm_out_file);
9752 fputs ("\t.set volatile\n", asm_out_file);
9753 if (!TARGET_ABI_OPEN_VMS)
9754 fputs ("\t.set noat\n", asm_out_file);
9755 if (TARGET_EXPLICIT_RELOCS)
9756 fputs ("\t.set nomacro\n", asm_out_file);
9757 if (TARGET_SUPPORT_ARCH | TARGET_BWX | TARGET_MAX | TARGET_FIX | TARGET_CIX)
9761 if (alpha_cpu == PROCESSOR_EV6 || TARGET_FIX || TARGET_CIX)
9763 else if (TARGET_MAX)
9765 else if (TARGET_BWX)
9767 else if (alpha_cpu == PROCESSOR_EV5)
9772 fprintf (asm_out_file, "\t.arch %s\n", arch);
9777 #ifdef OBJECT_FORMAT_ELF
9778 /* Since we don't have a .dynbss section, we should not allow global
9779 relocations in the .rodata section. */
9782 alpha_elf_reloc_rw_mask (void)
9784 return flag_pic ? 3 : 2;
9787 /* Return a section for X. The only special thing we do here is to
9788 honor small data. */
9791 alpha_elf_select_rtx_section (enum machine_mode mode, rtx x,
9792 unsigned HOST_WIDE_INT align)
9794 if (TARGET_SMALL_DATA && GET_MODE_SIZE (mode) <= g_switch_value)
9795 /* ??? Consider using mergeable sdata sections. */
9796 return sdata_section;
9798 return default_elf_select_rtx_section (mode, x, align);
9802 alpha_elf_section_type_flags (tree decl, const char *name, int reloc)
9804 unsigned int flags = 0;
9806 if (strcmp (name, ".sdata") == 0
9807 || strncmp (name, ".sdata.", 7) == 0
9808 || strncmp (name, ".gnu.linkonce.s.", 16) == 0
9809 || strcmp (name, ".sbss") == 0
9810 || strncmp (name, ".sbss.", 6) == 0
9811 || strncmp (name, ".gnu.linkonce.sb.", 17) == 0)
9812 flags = SECTION_SMALL;
9814 flags |= default_section_type_flags (decl, name, reloc);
9817 #endif /* OBJECT_FORMAT_ELF */
9819 /* Structure to collect function names for final output in link section. */
9820 /* Note that items marked with GTY can't be ifdef'ed out. */
9822 enum links_kind {KIND_UNUSED, KIND_LOCAL, KIND_EXTERN};
9823 enum reloc_kind {KIND_LINKAGE, KIND_CODEADDR};
9825 struct GTY(()) alpha_links
9830 enum links_kind lkind;
9831 enum reloc_kind rkind;
9834 struct GTY(()) alpha_funcs
9837 splay_tree GTY ((param1_is (char *), param2_is (struct alpha_links *)))
9841 static GTY ((param1_is (char *), param2_is (struct alpha_links *)))
9842 splay_tree alpha_links_tree;
9843 static GTY ((param1_is (tree), param2_is (struct alpha_funcs *)))
9844 splay_tree alpha_funcs_tree;
9846 static GTY(()) int alpha_funcs_num;
9848 #if TARGET_ABI_OPEN_VMS
9850 /* Return the VMS argument type corresponding to MODE. */
9853 alpha_arg_type (enum machine_mode mode)
9858 return TARGET_FLOAT_VAX ? FF : FS;
9860 return TARGET_FLOAT_VAX ? FD : FT;
9866 /* Return an rtx for an integer representing the VMS Argument Information
9870 alpha_arg_info_reg_val (CUMULATIVE_ARGS cum)
9872 unsigned HOST_WIDE_INT regval = cum.num_args;
9875 for (i = 0; i < 6; i++)
9876 regval |= ((int) cum.atypes[i]) << (i * 3 + 8);
9878 return GEN_INT (regval);
9881 /* Register the need for a (fake) .linkage entry for calls to function NAME.
9882 IS_LOCAL is 1 if this is for a definition, 0 if this is for a real call.
9883 Return a SYMBOL_REF suited to the call instruction. */
9886 alpha_need_linkage (const char *name, int is_local)
9888 splay_tree_node node;
9889 struct alpha_links *al;
9898 struct alpha_funcs *cfaf;
9900 if (!alpha_funcs_tree)
9901 alpha_funcs_tree = splay_tree_new_ggc ((splay_tree_compare_fn)
9902 splay_tree_compare_pointers);
9904 cfaf = (struct alpha_funcs *) ggc_alloc (sizeof (struct alpha_funcs));
9907 cfaf->num = ++alpha_funcs_num;
9909 splay_tree_insert (alpha_funcs_tree,
9910 (splay_tree_key) current_function_decl,
9911 (splay_tree_value) cfaf);
9914 if (alpha_links_tree)
9916 /* Is this name already defined? */
9918 node = splay_tree_lookup (alpha_links_tree, (splay_tree_key) name);
9921 al = (struct alpha_links *) node->value;
9924 /* Defined here but external assumed. */
9925 if (al->lkind == KIND_EXTERN)
9926 al->lkind = KIND_LOCAL;
9930 /* Used here but unused assumed. */
9931 if (al->lkind == KIND_UNUSED)
9932 al->lkind = KIND_LOCAL;
9938 alpha_links_tree = splay_tree_new_ggc ((splay_tree_compare_fn) strcmp);
9940 al = (struct alpha_links *) ggc_alloc (sizeof (struct alpha_links));
9941 name = ggc_strdup (name);
9943 /* Assume external if no definition. */
9944 al->lkind = (is_local ? KIND_UNUSED : KIND_EXTERN);
9946 /* Ensure we have an IDENTIFIER so assemble_name can mark it used
9947 and find the ultimate alias target like assemble_name. */
9948 id = get_identifier (name);
9950 while (IDENTIFIER_TRANSPARENT_ALIAS (id))
9952 id = TREE_CHAIN (id);
9953 target = IDENTIFIER_POINTER (id);
9956 al->target = target ? target : name;
9957 al->linkage = gen_rtx_SYMBOL_REF (Pmode, name);
9959 splay_tree_insert (alpha_links_tree, (splay_tree_key) name,
9960 (splay_tree_value) al);
9965 /* Return a SYMBOL_REF representing the reference to the .linkage entry
9966 of function FUNC built for calls made from CFUNDECL. LFLAG is 1 if
9967 this is the reference to the linkage pointer value, 0 if this is the
9968 reference to the function entry value. RFLAG is 1 if this a reduced
9969 reference (code address only), 0 if this is a full reference. */
9972 alpha_use_linkage (rtx func, tree cfundecl, int lflag, int rflag)
9974 splay_tree_node cfunnode;
9975 struct alpha_funcs *cfaf;
9976 struct alpha_links *al;
9977 const char *name = XSTR (func, 0);
9979 cfaf = (struct alpha_funcs *) 0;
9980 al = (struct alpha_links *) 0;
9982 cfunnode = splay_tree_lookup (alpha_funcs_tree, (splay_tree_key) cfundecl);
9983 cfaf = (struct alpha_funcs *) cfunnode->value;
9987 splay_tree_node lnode;
9989 /* Is this name already defined? */
9991 lnode = splay_tree_lookup (cfaf->links, (splay_tree_key) name);
9993 al = (struct alpha_links *) lnode->value;
9996 cfaf->links = splay_tree_new_ggc ((splay_tree_compare_fn) strcmp);
10003 splay_tree_node node = 0;
10004 struct alpha_links *anl;
10006 if (name[0] == '*')
10009 name_len = strlen (name);
10010 linksym = (char *) alloca (name_len + 50);
10012 al = (struct alpha_links *) ggc_alloc (sizeof (struct alpha_links));
10013 al->num = cfaf->num;
10015 node = splay_tree_lookup (alpha_links_tree, (splay_tree_key) name);
10018 anl = (struct alpha_links *) node->value;
10019 al->lkind = anl->lkind;
10020 name = anl->target;
10023 sprintf (linksym, "$%d..%s..lk", cfaf->num, name);
10024 buflen = strlen (linksym);
10026 al->linkage = gen_rtx_SYMBOL_REF
10027 (Pmode, ggc_alloc_string (linksym, buflen + 1));
10029 splay_tree_insert (cfaf->links, (splay_tree_key) name,
10030 (splay_tree_value) al);
10034 al->rkind = KIND_CODEADDR;
10036 al->rkind = KIND_LINKAGE;
10039 return gen_rtx_MEM (Pmode, plus_constant (al->linkage, 8));
10041 return al->linkage;
10045 alpha_write_one_linkage (splay_tree_node node, void *data)
10047 const char *const name = (const char *) node->key;
10048 struct alpha_links *link = (struct alpha_links *) node->value;
10049 FILE *stream = (FILE *) data;
10051 fprintf (stream, "$%d..%s..lk:\n", link->num, name);
10052 if (link->rkind == KIND_CODEADDR)
10054 if (link->lkind == KIND_LOCAL)
10056 /* Local and used */
10057 fprintf (stream, "\t.quad %s..en\n", name);
10061 /* External and used, request code address. */
10062 fprintf (stream, "\t.code_address %s\n", name);
10067 if (link->lkind == KIND_LOCAL)
10069 /* Local and used, build linkage pair. */
10070 fprintf (stream, "\t.quad %s..en\n", name);
10071 fprintf (stream, "\t.quad %s\n", name);
10075 /* External and used, request linkage pair. */
10076 fprintf (stream, "\t.linkage %s\n", name);
10084 alpha_write_linkage (FILE *stream, const char *funname, tree fundecl)
10086 splay_tree_node node;
10087 struct alpha_funcs *func;
10089 fprintf (stream, "\t.link\n");
10090 fprintf (stream, "\t.align 3\n");
10093 node = splay_tree_lookup (alpha_funcs_tree, (splay_tree_key) fundecl);
10094 func = (struct alpha_funcs *) node->value;
10096 fputs ("\t.name ", stream);
10097 assemble_name (stream, funname);
10098 fputs ("..na\n", stream);
10099 ASM_OUTPUT_LABEL (stream, funname);
10100 fprintf (stream, "\t.pdesc ");
10101 assemble_name (stream, funname);
10102 fprintf (stream, "..en,%s\n",
10103 alpha_procedure_type == PT_STACK ? "stack"
10104 : alpha_procedure_type == PT_REGISTER ? "reg" : "null");
10108 splay_tree_foreach (func->links, alpha_write_one_linkage, stream);
10109 /* splay_tree_delete (func->links); */
10113 /* Switch to an arbitrary section NAME with attributes as specified
10114 by FLAGS. ALIGN specifies any known alignment requirements for
10115 the section; 0 if the default should be used. */
10118 vms_asm_named_section (const char *name, unsigned int flags,
10119 tree decl ATTRIBUTE_UNUSED)
10121 fputc ('\n', asm_out_file);
10122 fprintf (asm_out_file, ".section\t%s", name);
10124 if (flags & SECTION_DEBUG)
10125 fprintf (asm_out_file, ",NOWRT");
10127 fputc ('\n', asm_out_file);
10130 /* Record an element in the table of global constructors. SYMBOL is
10131 a SYMBOL_REF of the function to be called; PRIORITY is a number
10132 between 0 and MAX_INIT_PRIORITY.
10134 Differs from default_ctors_section_asm_out_constructor in that the
10135 width of the .ctors entry is always 64 bits, rather than the 32 bits
10136 used by a normal pointer. */
10139 vms_asm_out_constructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
10141 switch_to_section (ctors_section);
10142 assemble_align (BITS_PER_WORD);
10143 assemble_integer (symbol, UNITS_PER_WORD, BITS_PER_WORD, 1);
10147 vms_asm_out_destructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
10149 switch_to_section (dtors_section);
10150 assemble_align (BITS_PER_WORD);
10151 assemble_integer (symbol, UNITS_PER_WORD, BITS_PER_WORD, 1);
10156 alpha_need_linkage (const char *name ATTRIBUTE_UNUSED,
10157 int is_local ATTRIBUTE_UNUSED)
10163 alpha_use_linkage (rtx func ATTRIBUTE_UNUSED,
10164 tree cfundecl ATTRIBUTE_UNUSED,
10165 int lflag ATTRIBUTE_UNUSED,
10166 int rflag ATTRIBUTE_UNUSED)
10171 #endif /* TARGET_ABI_OPEN_VMS */
10173 #if TARGET_ABI_UNICOSMK
10175 /* This evaluates to true if we do not know how to pass TYPE solely in
10176 registers. This is the case for all arguments that do not fit in two
10180 unicosmk_must_pass_in_stack (enum machine_mode mode, const_tree type)
10185 if (TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
10187 if (TREE_ADDRESSABLE (type))
10190 return ALPHA_ARG_SIZE (mode, type, 0) > 2;
10193 /* Define the offset between two registers, one to be eliminated, and the
10194 other its replacement, at the start of a routine. */
10197 unicosmk_initial_elimination_offset (int from, int to)
10201 fixed_size = alpha_sa_size();
10202 if (fixed_size != 0)
10205 if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
10206 return -fixed_size;
10207 else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
10209 else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
10210 return (ALPHA_ROUND (crtl->outgoing_args_size)
10211 + ALPHA_ROUND (get_frame_size()));
10212 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
10213 return (ALPHA_ROUND (fixed_size)
10214 + ALPHA_ROUND (get_frame_size()
10215 + crtl->outgoing_args_size));
10217 gcc_unreachable ();
10220 /* Output the module name for .ident and .end directives. We have to strip
10221 directories and add make sure that the module name starts with a letter
10225 unicosmk_output_module_name (FILE *file)
10227 const char *name = lbasename (main_input_filename);
10228 unsigned len = strlen (name);
10229 char *clean_name = alloca (len + 2);
10230 char *ptr = clean_name;
10232 /* CAM only accepts module names that start with a letter or '$'. We
10233 prefix the module name with a '$' if necessary. */
10235 if (!ISALPHA (*name))
10237 memcpy (ptr, name, len + 1);
10238 clean_symbol_name (clean_name);
10239 fputs (clean_name, file);
10242 /* Output the definition of a common variable. */
10245 unicosmk_output_common (FILE *file, const char *name, int size, int align)
10248 printf ("T3E__: common %s\n", name);
10251 fputs("\t.endp\n\n\t.psect ", file);
10252 assemble_name(file, name);
10253 fprintf(file, ",%d,common\n", floor_log2 (align / BITS_PER_UNIT));
10254 fprintf(file, "\t.byte\t0:%d\n", size);
10256 /* Mark the symbol as defined in this module. */
10257 name_tree = get_identifier (name);
10258 TREE_ASM_WRITTEN (name_tree) = 1;
10261 #define SECTION_PUBLIC SECTION_MACH_DEP
10262 #define SECTION_MAIN (SECTION_PUBLIC << 1)
10263 static int current_section_align;
10265 /* A get_unnamed_section callback for switching to the text section. */
10268 unicosmk_output_text_section_asm_op (const void *data ATTRIBUTE_UNUSED)
10270 static int count = 0;
10271 fprintf (asm_out_file, "\t.endp\n\n\t.psect\tgcc@text___%d,code\n", count++);
10274 /* A get_unnamed_section callback for switching to the data section. */
10277 unicosmk_output_data_section_asm_op (const void *data ATTRIBUTE_UNUSED)
10279 static int count = 1;
10280 fprintf (asm_out_file, "\t.endp\n\n\t.psect\tgcc@data___%d,data\n", count++);
10283 /* Implement TARGET_ASM_INIT_SECTIONS.
10285 The Cray assembler is really weird with respect to sections. It has only
10286 named sections and you can't reopen a section once it has been closed.
10287 This means that we have to generate unique names whenever we want to
10288 reenter the text or the data section. */
10291 unicosmk_init_sections (void)
10293 text_section = get_unnamed_section (SECTION_CODE,
10294 unicosmk_output_text_section_asm_op,
10296 data_section = get_unnamed_section (SECTION_WRITE,
10297 unicosmk_output_data_section_asm_op,
10299 readonly_data_section = data_section;
10302 static unsigned int
10303 unicosmk_section_type_flags (tree decl, const char *name,
10304 int reloc ATTRIBUTE_UNUSED)
10306 unsigned int flags = default_section_type_flags (decl, name, reloc);
10311 if (TREE_CODE (decl) == FUNCTION_DECL)
10313 current_section_align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
10314 if (align_functions_log > current_section_align)
10315 current_section_align = align_functions_log;
10317 if (! strcmp (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl)), "main"))
10318 flags |= SECTION_MAIN;
10321 current_section_align = floor_log2 (DECL_ALIGN (decl) / BITS_PER_UNIT);
10323 if (TREE_PUBLIC (decl))
10324 flags |= SECTION_PUBLIC;
10329 /* Generate a section name for decl and associate it with the
10333 unicosmk_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
10340 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
10341 name = default_strip_name_encoding (name);
10342 len = strlen (name);
10344 if (TREE_CODE (decl) == FUNCTION_DECL)
10348 /* It is essential that we prefix the section name here because
10349 otherwise the section names generated for constructors and
10350 destructors confuse collect2. */
10352 string = alloca (len + 6);
10353 sprintf (string, "code@%s", name);
10354 DECL_SECTION_NAME (decl) = build_string (len + 5, string);
10356 else if (TREE_PUBLIC (decl))
10357 DECL_SECTION_NAME (decl) = build_string (len, name);
10362 string = alloca (len + 6);
10363 sprintf (string, "data@%s", name);
10364 DECL_SECTION_NAME (decl) = build_string (len + 5, string);
10368 /* Switch to an arbitrary section NAME with attributes as specified
10369 by FLAGS. ALIGN specifies any known alignment requirements for
10370 the section; 0 if the default should be used. */
10373 unicosmk_asm_named_section (const char *name, unsigned int flags,
10374 tree decl ATTRIBUTE_UNUSED)
10378 /* Close the previous section. */
10380 fputs ("\t.endp\n\n", asm_out_file);
10382 /* Find out what kind of section we are opening. */
10384 if (flags & SECTION_MAIN)
10385 fputs ("\t.start\tmain\n", asm_out_file);
10387 if (flags & SECTION_CODE)
10389 else if (flags & SECTION_PUBLIC)
10394 if (current_section_align != 0)
10395 fprintf (asm_out_file, "\t.psect\t%s,%d,%s\n", name,
10396 current_section_align, kind);
10398 fprintf (asm_out_file, "\t.psect\t%s,%s\n", name, kind);
10402 unicosmk_insert_attributes (tree decl, tree *attr_ptr ATTRIBUTE_UNUSED)
10405 && (TREE_PUBLIC (decl) || TREE_CODE (decl) == FUNCTION_DECL))
10406 unicosmk_unique_section (decl, 0);
10409 /* Output an alignment directive. We have to use the macro 'gcc@code@align'
10410 in code sections because .align fill unused space with zeroes. */
10413 unicosmk_output_align (FILE *file, int align)
10415 if (inside_function)
10416 fprintf (file, "\tgcc@code@align\t%d\n", align);
10418 fprintf (file, "\t.align\t%d\n", align);
10421 /* Add a case vector to the current function's list of deferred case
10422 vectors. Case vectors have to be put into a separate section because CAM
10423 does not allow data definitions in code sections. */
10426 unicosmk_defer_case_vector (rtx lab, rtx vec)
10428 struct machine_function *machine = cfun->machine;
10430 vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec);
10431 machine->addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec,
10432 machine->addr_list);
10435 /* Output a case vector. */
10438 unicosmk_output_addr_vec (FILE *file, rtx vec)
10440 rtx lab = XEXP (vec, 0);
10441 rtx body = XEXP (vec, 1);
10442 int vlen = XVECLEN (body, 0);
10445 (*targetm.asm_out.internal_label) (file, "L", CODE_LABEL_NUMBER (lab));
10447 for (idx = 0; idx < vlen; idx++)
10449 ASM_OUTPUT_ADDR_VEC_ELT
10450 (file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0)));
10454 /* Output current function's deferred case vectors. */
10457 unicosmk_output_deferred_case_vectors (FILE *file)
10459 struct machine_function *machine = cfun->machine;
10462 if (machine->addr_list == NULL_RTX)
10465 switch_to_section (data_section);
10466 for (t = machine->addr_list; t; t = XEXP (t, 1))
10467 unicosmk_output_addr_vec (file, XEXP (t, 0));
10470 /* Generate the name of the SSIB section for the current function. */
10472 #define SSIB_PREFIX "__SSIB_"
10473 #define SSIB_PREFIX_LEN 7
10475 static const char *
10476 unicosmk_ssib_name (void)
10478 /* This is ok since CAM won't be able to deal with names longer than that
10481 static char name[256];
10484 const char *fnname;
10487 x = DECL_RTL (cfun->decl);
10488 gcc_assert (MEM_P (x));
10490 gcc_assert (GET_CODE (x) == SYMBOL_REF);
10491 fnname = XSTR (x, 0);
10493 len = strlen (fnname);
10494 if (len + SSIB_PREFIX_LEN > 255)
10495 len = 255 - SSIB_PREFIX_LEN;
10497 strcpy (name, SSIB_PREFIX);
10498 strncpy (name + SSIB_PREFIX_LEN, fnname, len);
10499 name[len + SSIB_PREFIX_LEN] = 0;
10504 /* Set up the dynamic subprogram information block (DSIB) and update the
10505 frame pointer register ($15) for subroutines which have a frame. If the
10506 subroutine doesn't have a frame, simply increment $15. */
10509 unicosmk_gen_dsib (unsigned long *imaskP)
10511 if (alpha_procedure_type == PT_STACK)
10513 const char *ssib_name;
10516 /* Allocate 64 bytes for the DSIB. */
10518 FRP (emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx,
10520 emit_insn (gen_blockage ());
10522 /* Save the return address. */
10524 mem = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx, 56));
10525 set_mem_alias_set (mem, alpha_sr_alias_set);
10526 FRP (emit_move_insn (mem, gen_rtx_REG (DImode, REG_RA)));
10527 (*imaskP) &= ~(1UL << REG_RA);
10529 /* Save the old frame pointer. */
10531 mem = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx, 48));
10532 set_mem_alias_set (mem, alpha_sr_alias_set);
10533 FRP (emit_move_insn (mem, hard_frame_pointer_rtx));
10534 (*imaskP) &= ~(1UL << HARD_FRAME_POINTER_REGNUM);
10536 emit_insn (gen_blockage ());
10538 /* Store the SSIB pointer. */
10540 ssib_name = ggc_strdup (unicosmk_ssib_name ());
10541 mem = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx, 32));
10542 set_mem_alias_set (mem, alpha_sr_alias_set);
10544 FRP (emit_move_insn (gen_rtx_REG (DImode, 5),
10545 gen_rtx_SYMBOL_REF (Pmode, ssib_name)));
10546 FRP (emit_move_insn (mem, gen_rtx_REG (DImode, 5)));
10548 /* Save the CIW index. */
10550 mem = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx, 24));
10551 set_mem_alias_set (mem, alpha_sr_alias_set);
10552 FRP (emit_move_insn (mem, gen_rtx_REG (DImode, 25)));
10554 emit_insn (gen_blockage ());
10556 /* Set the new frame pointer. */
10557 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
10558 stack_pointer_rtx, GEN_INT (64))));
10562 /* Increment the frame pointer register to indicate that we do not
10564 emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
10565 hard_frame_pointer_rtx, const1_rtx));
10569 /* Output the static subroutine information block for the current
10573 unicosmk_output_ssib (FILE *file, const char *fnname)
10579 struct machine_function *machine = cfun->machine;
10582 fprintf (file, "\t.endp\n\n\t.psect\t%s%s,data\n", user_label_prefix,
10583 unicosmk_ssib_name ());
10585 /* Some required stuff and the function name length. */
10587 len = strlen (fnname);
10588 fprintf (file, "\t.quad\t^X20008%2.2X28\n", len);
10591 ??? We don't do that yet. */
10593 fputs ("\t.quad\t0\n", file);
10595 /* Function address. */
10597 fputs ("\t.quad\t", file);
10598 assemble_name (file, fnname);
10601 fputs ("\t.quad\t0\n", file);
10602 fputs ("\t.quad\t0\n", file);
10605 ??? We do it the same way Cray CC does it but this could be
10608 for( i = 0; i < len; i++ )
10609 fprintf (file, "\t.byte\t%d\n", (int)(fnname[i]));
10610 if( (len % 8) == 0 )
10611 fputs ("\t.quad\t0\n", file);
10613 fprintf (file, "\t.bits\t%d : 0\n", (8 - (len % 8))*8);
10615 /* All call information words used in the function. */
10617 for (x = machine->first_ciw; x; x = XEXP (x, 1))
10620 #if HOST_BITS_PER_WIDE_INT == 32
10621 fprintf (file, "\t.quad\t" HOST_WIDE_INT_PRINT_DOUBLE_HEX "\n",
10622 CONST_DOUBLE_HIGH (ciw), CONST_DOUBLE_LOW (ciw));
10624 fprintf (file, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX "\n", INTVAL (ciw));
10629 /* Add a call information word (CIW) to the list of the current function's
10630 CIWs and return its index.
10632 X is a CONST_INT or CONST_DOUBLE representing the CIW. */
10635 unicosmk_add_call_info_word (rtx x)
10638 struct machine_function *machine = cfun->machine;
10640 node = gen_rtx_EXPR_LIST (VOIDmode, x, NULL_RTX);
10641 if (machine->first_ciw == NULL_RTX)
10642 machine->first_ciw = node;
10644 XEXP (machine->last_ciw, 1) = node;
10646 machine->last_ciw = node;
10647 ++machine->ciw_count;
10649 return GEN_INT (machine->ciw_count
10650 + strlen (current_function_name ())/8 + 5);
10653 /* The Cray assembler doesn't accept extern declarations for symbols which
10654 are defined in the same file. We have to keep track of all global
10655 symbols which are referenced and/or defined in a source file and output
10656 extern declarations for those which are referenced but not defined at
10657 the end of file. */
10659 /* List of identifiers for which an extern declaration might have to be
10661 /* FIXME: needs to use GC, so it can be saved and restored for PCH. */
10663 struct unicosmk_extern_list
10665 struct unicosmk_extern_list *next;
10669 static struct unicosmk_extern_list *unicosmk_extern_head = 0;
10671 /* Output extern declarations which are required for every asm file. */
10674 unicosmk_output_default_externs (FILE *file)
10676 static const char *const externs[] =
10677 { "__T3E_MISMATCH" };
10682 n = ARRAY_SIZE (externs);
10684 for (i = 0; i < n; i++)
10685 fprintf (file, "\t.extern\t%s\n", externs[i]);
10688 /* Output extern declarations for global symbols which are have been
10689 referenced but not defined. */
10692 unicosmk_output_externs (FILE *file)
10694 struct unicosmk_extern_list *p;
10695 const char *real_name;
10699 len = strlen (user_label_prefix);
10700 for (p = unicosmk_extern_head; p != 0; p = p->next)
10702 /* We have to strip the encoding and possibly remove user_label_prefix
10703 from the identifier in order to handle -fleading-underscore and
10704 explicit asm names correctly (cf. gcc.dg/asm-names-1.c). */
10705 real_name = default_strip_name_encoding (p->name);
10706 if (len && p->name[0] == '*'
10707 && !memcmp (real_name, user_label_prefix, len))
10710 name_tree = get_identifier (real_name);
10711 if (! TREE_ASM_WRITTEN (name_tree))
10713 TREE_ASM_WRITTEN (name_tree) = 1;
10714 fputs ("\t.extern\t", file);
10715 assemble_name (file, p->name);
10721 /* Record an extern. */
10724 unicosmk_add_extern (const char *name)
10726 struct unicosmk_extern_list *p;
10728 p = (struct unicosmk_extern_list *)
10729 xmalloc (sizeof (struct unicosmk_extern_list));
10730 p->next = unicosmk_extern_head;
10732 unicosmk_extern_head = p;
10735 /* The Cray assembler generates incorrect code if identifiers which
10736 conflict with register names are used as instruction operands. We have
10737 to replace such identifiers with DEX expressions. */
10739 /* Structure to collect identifiers which have been replaced by DEX
10741 /* FIXME: needs to use GC, so it can be saved and restored for PCH. */
10743 struct unicosmk_dex {
10744 struct unicosmk_dex *next;
10748 /* List of identifiers which have been replaced by DEX expressions. The DEX
10749 number is determined by the position in the list. */
10751 static struct unicosmk_dex *unicosmk_dex_list = NULL;
10753 /* The number of elements in the DEX list. */
10755 static int unicosmk_dex_count = 0;
10757 /* Check if NAME must be replaced by a DEX expression. */
10760 unicosmk_special_name (const char *name)
10762 if (name[0] == '*')
10765 if (name[0] == '$')
10768 if (name[0] != 'r' && name[0] != 'f' && name[0] != 'R' && name[0] != 'F')
10773 case '1': case '2':
10774 return (name[2] == '\0' || (ISDIGIT (name[2]) && name[3] == '\0'));
10777 return (name[2] == '\0'
10778 || ((name[2] == '0' || name[2] == '1') && name[3] == '\0'));
10781 return (ISDIGIT (name[1]) && name[2] == '\0');
10785 /* Return the DEX number if X must be replaced by a DEX expression and 0
10789 unicosmk_need_dex (rtx x)
10791 struct unicosmk_dex *dex;
10795 if (GET_CODE (x) != SYMBOL_REF)
10799 if (! unicosmk_special_name (name))
10802 i = unicosmk_dex_count;
10803 for (dex = unicosmk_dex_list; dex; dex = dex->next)
10805 if (! strcmp (name, dex->name))
10810 dex = (struct unicosmk_dex *) xmalloc (sizeof (struct unicosmk_dex));
10812 dex->next = unicosmk_dex_list;
10813 unicosmk_dex_list = dex;
10815 ++unicosmk_dex_count;
10816 return unicosmk_dex_count;
10819 /* Output the DEX definitions for this file. */
10822 unicosmk_output_dex (FILE *file)
10824 struct unicosmk_dex *dex;
10827 if (unicosmk_dex_list == NULL)
10830 fprintf (file, "\t.dexstart\n");
10832 i = unicosmk_dex_count;
10833 for (dex = unicosmk_dex_list; dex; dex = dex->next)
10835 fprintf (file, "\tDEX (%d) = ", i);
10836 assemble_name (file, dex->name);
10841 fprintf (file, "\t.dexend\n");
10844 /* Output text that to appear at the beginning of an assembler file. */
10847 unicosmk_file_start (void)
10851 fputs ("\t.ident\t", asm_out_file);
10852 unicosmk_output_module_name (asm_out_file);
10853 fputs ("\n\n", asm_out_file);
10855 /* The Unicos/Mk assembler uses different register names. Instead of trying
10856 to support them, we simply use micro definitions. */
10858 /* CAM has different register names: rN for the integer register N and fN
10859 for the floating-point register N. Instead of trying to use these in
10860 alpha.md, we define the symbols $N and $fN to refer to the appropriate
10863 for (i = 0; i < 32; ++i)
10864 fprintf (asm_out_file, "$%d <- r%d\n", i, i);
10866 for (i = 0; i < 32; ++i)
10867 fprintf (asm_out_file, "$f%d <- f%d\n", i, i);
10869 putc ('\n', asm_out_file);
10871 /* The .align directive fill unused space with zeroes which does not work
10872 in code sections. We define the macro 'gcc@code@align' which uses nops
10873 instead. Note that it assumes that code sections always have the
10874 biggest possible alignment since . refers to the current offset from
10875 the beginning of the section. */
10877 fputs ("\t.macro gcc@code@align n\n", asm_out_file);
10878 fputs ("gcc@n@bytes = 1 << n\n", asm_out_file);
10879 fputs ("gcc@here = . % gcc@n@bytes\n", asm_out_file);
10880 fputs ("\t.if ne, gcc@here, 0\n", asm_out_file);
10881 fputs ("\t.repeat (gcc@n@bytes - gcc@here) / 4\n", asm_out_file);
10882 fputs ("\tbis r31,r31,r31\n", asm_out_file);
10883 fputs ("\t.endr\n", asm_out_file);
10884 fputs ("\t.endif\n", asm_out_file);
10885 fputs ("\t.endm gcc@code@align\n\n", asm_out_file);
10887 /* Output extern declarations which should always be visible. */
10888 unicosmk_output_default_externs (asm_out_file);
10890 /* Open a dummy section. We always need to be inside a section for the
10891 section-switching code to work correctly.
10892 ??? This should be a module id or something like that. I still have to
10893 figure out what the rules for those are. */
10894 fputs ("\n\t.psect\t$SG00000,data\n", asm_out_file);
10897 /* Output text to appear at the end of an assembler file. This includes all
10898 pending extern declarations and DEX expressions. */
10901 unicosmk_file_end (void)
10903 fputs ("\t.endp\n\n", asm_out_file);
10905 /* Output all pending externs. */
10907 unicosmk_output_externs (asm_out_file);
10909 /* Output dex definitions used for functions whose names conflict with
10912 unicosmk_output_dex (asm_out_file);
10914 fputs ("\t.end\t", asm_out_file);
10915 unicosmk_output_module_name (asm_out_file);
10916 putc ('\n', asm_out_file);
10922 unicosmk_output_deferred_case_vectors (FILE *file ATTRIBUTE_UNUSED)
10926 unicosmk_gen_dsib (unsigned long *imaskP ATTRIBUTE_UNUSED)
10930 unicosmk_output_ssib (FILE * file ATTRIBUTE_UNUSED,
10931 const char * fnname ATTRIBUTE_UNUSED)
10935 unicosmk_add_call_info_word (rtx x ATTRIBUTE_UNUSED)
10941 unicosmk_need_dex (rtx x ATTRIBUTE_UNUSED)
10946 #endif /* TARGET_ABI_UNICOSMK */
10949 alpha_init_libfuncs (void)
10951 if (TARGET_ABI_UNICOSMK)
10953 /* Prevent gcc from generating calls to __divsi3. */
10954 set_optab_libfunc (sdiv_optab, SImode, 0);
10955 set_optab_libfunc (udiv_optab, SImode, 0);
10957 /* Use the functions provided by the system library
10958 for DImode integer division. */
10959 set_optab_libfunc (sdiv_optab, DImode, "$sldiv");
10960 set_optab_libfunc (udiv_optab, DImode, "$uldiv");
10962 else if (TARGET_ABI_OPEN_VMS)
10964 /* Use the VMS runtime library functions for division and
10966 set_optab_libfunc (sdiv_optab, SImode, "OTS$DIV_I");
10967 set_optab_libfunc (sdiv_optab, DImode, "OTS$DIV_L");
10968 set_optab_libfunc (udiv_optab, SImode, "OTS$DIV_UI");
10969 set_optab_libfunc (udiv_optab, DImode, "OTS$DIV_UL");
10970 set_optab_libfunc (smod_optab, SImode, "OTS$REM_I");
10971 set_optab_libfunc (smod_optab, DImode, "OTS$REM_L");
10972 set_optab_libfunc (umod_optab, SImode, "OTS$REM_UI");
10973 set_optab_libfunc (umod_optab, DImode, "OTS$REM_UL");
10974 abort_libfunc = init_one_libfunc ("decc$abort");
10975 memcmp_libfunc = init_one_libfunc ("decc$memcmp");
10976 #ifdef MEM_LIBFUNCS_INIT
10983 /* Initialize the GCC target structure. */
10984 #if TARGET_ABI_OPEN_VMS
10985 # undef TARGET_ATTRIBUTE_TABLE
10986 # define TARGET_ATTRIBUTE_TABLE vms_attribute_table
10987 # undef TARGET_CAN_ELIMINATE
10988 # define TARGET_CAN_ELIMINATE alpha_vms_can_eliminate
10991 #undef TARGET_IN_SMALL_DATA_P
10992 #define TARGET_IN_SMALL_DATA_P alpha_in_small_data_p
10994 #if TARGET_ABI_UNICOSMK
10995 # undef TARGET_INSERT_ATTRIBUTES
10996 # define TARGET_INSERT_ATTRIBUTES unicosmk_insert_attributes
10997 # undef TARGET_SECTION_TYPE_FLAGS
10998 # define TARGET_SECTION_TYPE_FLAGS unicosmk_section_type_flags
10999 # undef TARGET_ASM_UNIQUE_SECTION
11000 # define TARGET_ASM_UNIQUE_SECTION unicosmk_unique_section
11001 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
11002 #define TARGET_ASM_FUNCTION_RODATA_SECTION default_no_function_rodata_section
11003 # undef TARGET_ASM_GLOBALIZE_LABEL
11004 # define TARGET_ASM_GLOBALIZE_LABEL hook_void_FILEptr_constcharptr
11005 # undef TARGET_MUST_PASS_IN_STACK
11006 # define TARGET_MUST_PASS_IN_STACK unicosmk_must_pass_in_stack
11009 #undef TARGET_ASM_ALIGNED_HI_OP
11010 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
11011 #undef TARGET_ASM_ALIGNED_DI_OP
11012 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
11014 /* Default unaligned ops are provided for ELF systems. To get unaligned
11015 data for non-ELF systems, we have to turn off auto alignment. */
11016 #if !defined (OBJECT_FORMAT_ELF) || TARGET_ABI_OPEN_VMS
11017 #undef TARGET_ASM_UNALIGNED_HI_OP
11018 #define TARGET_ASM_UNALIGNED_HI_OP "\t.align 0\n\t.word\t"
11019 #undef TARGET_ASM_UNALIGNED_SI_OP
11020 #define TARGET_ASM_UNALIGNED_SI_OP "\t.align 0\n\t.long\t"
11021 #undef TARGET_ASM_UNALIGNED_DI_OP
11022 #define TARGET_ASM_UNALIGNED_DI_OP "\t.align 0\n\t.quad\t"
11025 #ifdef OBJECT_FORMAT_ELF
11026 #undef TARGET_ASM_RELOC_RW_MASK
11027 #define TARGET_ASM_RELOC_RW_MASK alpha_elf_reloc_rw_mask
11028 #undef TARGET_ASM_SELECT_RTX_SECTION
11029 #define TARGET_ASM_SELECT_RTX_SECTION alpha_elf_select_rtx_section
11030 #undef TARGET_SECTION_TYPE_FLAGS
11031 #define TARGET_SECTION_TYPE_FLAGS alpha_elf_section_type_flags
11034 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
11035 #define TARGET_ASM_FUNCTION_END_PROLOGUE alpha_output_function_end_prologue
11037 #undef TARGET_INIT_LIBFUNCS
11038 #define TARGET_INIT_LIBFUNCS alpha_init_libfuncs
11040 #undef TARGET_LEGITIMIZE_ADDRESS
11041 #define TARGET_LEGITIMIZE_ADDRESS alpha_legitimize_address
11043 #if TARGET_ABI_UNICOSMK
11044 #undef TARGET_ASM_FILE_START
11045 #define TARGET_ASM_FILE_START unicosmk_file_start
11046 #undef TARGET_ASM_FILE_END
11047 #define TARGET_ASM_FILE_END unicosmk_file_end
11049 #undef TARGET_ASM_FILE_START
11050 #define TARGET_ASM_FILE_START alpha_file_start
11051 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
11052 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
11055 #undef TARGET_SCHED_ADJUST_COST
11056 #define TARGET_SCHED_ADJUST_COST alpha_adjust_cost
11057 #undef TARGET_SCHED_ISSUE_RATE
11058 #define TARGET_SCHED_ISSUE_RATE alpha_issue_rate
11059 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
11060 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
11061 alpha_multipass_dfa_lookahead
11063 #undef TARGET_HAVE_TLS
11064 #define TARGET_HAVE_TLS HAVE_AS_TLS
11066 #undef TARGET_INIT_BUILTINS
11067 #define TARGET_INIT_BUILTINS alpha_init_builtins
11068 #undef TARGET_EXPAND_BUILTIN
11069 #define TARGET_EXPAND_BUILTIN alpha_expand_builtin
11070 #undef TARGET_FOLD_BUILTIN
11071 #define TARGET_FOLD_BUILTIN alpha_fold_builtin
11073 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
11074 #define TARGET_FUNCTION_OK_FOR_SIBCALL alpha_function_ok_for_sibcall
11075 #undef TARGET_CANNOT_COPY_INSN_P
11076 #define TARGET_CANNOT_COPY_INSN_P alpha_cannot_copy_insn_p
11077 #undef TARGET_CANNOT_FORCE_CONST_MEM
11078 #define TARGET_CANNOT_FORCE_CONST_MEM alpha_cannot_force_const_mem
11081 #undef TARGET_ASM_OUTPUT_MI_THUNK
11082 #define TARGET_ASM_OUTPUT_MI_THUNK alpha_output_mi_thunk_osf
11083 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
11084 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
11085 #undef TARGET_STDARG_OPTIMIZE_HOOK
11086 #define TARGET_STDARG_OPTIMIZE_HOOK alpha_stdarg_optimize_hook
11089 #undef TARGET_RTX_COSTS
11090 #define TARGET_RTX_COSTS alpha_rtx_costs
11091 #undef TARGET_ADDRESS_COST
11092 #define TARGET_ADDRESS_COST hook_int_rtx_bool_0
11094 #undef TARGET_MACHINE_DEPENDENT_REORG
11095 #define TARGET_MACHINE_DEPENDENT_REORG alpha_reorg
11097 #undef TARGET_PROMOTE_FUNCTION_MODE
11098 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
11099 #undef TARGET_PROMOTE_PROTOTYPES
11100 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_false
11101 #undef TARGET_RETURN_IN_MEMORY
11102 #define TARGET_RETURN_IN_MEMORY alpha_return_in_memory
11103 #undef TARGET_PASS_BY_REFERENCE
11104 #define TARGET_PASS_BY_REFERENCE alpha_pass_by_reference
11105 #undef TARGET_SETUP_INCOMING_VARARGS
11106 #define TARGET_SETUP_INCOMING_VARARGS alpha_setup_incoming_varargs
11107 #undef TARGET_STRICT_ARGUMENT_NAMING
11108 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
11109 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
11110 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
11111 #undef TARGET_SPLIT_COMPLEX_ARG
11112 #define TARGET_SPLIT_COMPLEX_ARG alpha_split_complex_arg
11113 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
11114 #define TARGET_GIMPLIFY_VA_ARG_EXPR alpha_gimplify_va_arg
11115 #undef TARGET_ARG_PARTIAL_BYTES
11116 #define TARGET_ARG_PARTIAL_BYTES alpha_arg_partial_bytes
11117 #undef TARGET_TRAMPOLINE_INIT
11118 #define TARGET_TRAMPOLINE_INIT alpha_trampoline_init
11120 #undef TARGET_SECONDARY_RELOAD
11121 #define TARGET_SECONDARY_RELOAD alpha_secondary_reload
11123 #undef TARGET_SCALAR_MODE_SUPPORTED_P
11124 #define TARGET_SCALAR_MODE_SUPPORTED_P alpha_scalar_mode_supported_p
11125 #undef TARGET_VECTOR_MODE_SUPPORTED_P
11126 #define TARGET_VECTOR_MODE_SUPPORTED_P alpha_vector_mode_supported_p
11128 #undef TARGET_BUILD_BUILTIN_VA_LIST
11129 #define TARGET_BUILD_BUILTIN_VA_LIST alpha_build_builtin_va_list
11131 #undef TARGET_EXPAND_BUILTIN_VA_START
11132 #define TARGET_EXPAND_BUILTIN_VA_START alpha_va_start
11134 /* The Alpha architecture does not require sequential consistency. See
11135 http://www.cs.umd.edu/~pugh/java/memoryModel/AlphaReordering.html
11136 for an example of how it can be violated in practice. */
11137 #undef TARGET_RELAXED_ORDERING
11138 #define TARGET_RELAXED_ORDERING true
11140 #undef TARGET_DEFAULT_TARGET_FLAGS
11141 #define TARGET_DEFAULT_TARGET_FLAGS \
11142 (TARGET_DEFAULT | TARGET_CPU_DEFAULT | TARGET_DEFAULT_EXPLICIT_RELOCS)
11143 #undef TARGET_HANDLE_OPTION
11144 #define TARGET_HANDLE_OPTION alpha_handle_option
11146 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
11147 #undef TARGET_MANGLE_TYPE
11148 #define TARGET_MANGLE_TYPE alpha_mangle_type
11151 #undef TARGET_LEGITIMATE_ADDRESS_P
11152 #define TARGET_LEGITIMATE_ADDRESS_P alpha_legitimate_address_p
11154 struct gcc_target targetm = TARGET_INITIALIZER;
11157 #include "gt-alpha.h"