1 /* Subroutines used for code generation on the DEC Alpha.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
34 #include "insn-attr.h"
45 #include "integrate.h"
48 #include "target-def.h"
50 #include "langhooks.h"
52 /* Specify which cpu to schedule for. */
54 enum processor_type alpha_cpu;
55 static const char * const alpha_cpu_name[] =
60 /* Specify how accurate floating-point traps need to be. */
62 enum alpha_trap_precision alpha_tp;
64 /* Specify the floating-point rounding mode. */
66 enum alpha_fp_rounding_mode alpha_fprm;
68 /* Specify which things cause traps. */
70 enum alpha_fp_trap_mode alpha_fptm;
72 /* Specify bit size of immediate TLS offsets. */
74 int alpha_tls_size = 32;
76 /* Strings decoded into the above options. */
78 const char *alpha_cpu_string; /* -mcpu= */
79 const char *alpha_tune_string; /* -mtune= */
80 const char *alpha_tp_string; /* -mtrap-precision=[p|s|i] */
81 const char *alpha_fprm_string; /* -mfp-rounding-mode=[n|m|c|d] */
82 const char *alpha_fptm_string; /* -mfp-trap-mode=[n|u|su|sui] */
83 const char *alpha_mlat_string; /* -mmemory-latency= */
84 const char *alpha_tls_size_string; /* -mtls-size=[16|32|64] */
86 /* Save information from a "cmpxx" operation until the branch or scc is
89 struct alpha_compare alpha_compare;
91 /* Nonzero if inside of a function, because the Alpha asm can't
92 handle .files inside of functions. */
94 static int inside_function = FALSE;
96 /* The number of cycles of latency we should assume on memory reads. */
98 int alpha_memory_latency = 3;
100 /* Whether the function needs the GP. */
102 static int alpha_function_needs_gp;
104 /* The alias set for prologue/epilogue register save/restore. */
106 static int alpha_sr_alias_set;
108 /* The assembler name of the current function. */
110 static const char *alpha_fnname;
112 /* The next explicit relocation sequence number. */
113 int alpha_next_sequence_number = 1;
115 /* The literal and gpdisp sequence numbers for this insn, as printed
116 by %# and %* respectively. */
117 int alpha_this_literal_sequence_number;
118 int alpha_this_gpdisp_sequence_number;
120 /* Declarations of static functions. */
121 static int tls_symbolic_operand_1
122 PARAMS ((rtx, enum machine_mode, int, int));
123 static enum tls_model tls_symbolic_operand_type
125 static bool decl_in_text_section
127 static bool alpha_in_small_data_p
129 static void alpha_encode_section_info
130 PARAMS ((tree, int));
131 static const char *alpha_strip_name_encoding
132 PARAMS ((const char *));
133 static int some_small_symbolic_operand_1
134 PARAMS ((rtx *, void *));
135 static int split_small_symbolic_operand_1
136 PARAMS ((rtx *, void *));
137 static void alpha_set_memflags_1
138 PARAMS ((rtx, int, int, int));
139 static rtx alpha_emit_set_const_1
140 PARAMS ((rtx, enum machine_mode, HOST_WIDE_INT, int));
141 static void alpha_expand_unaligned_load_words
142 PARAMS ((rtx *out_regs, rtx smem, HOST_WIDE_INT words, HOST_WIDE_INT ofs));
143 static void alpha_expand_unaligned_store_words
144 PARAMS ((rtx *out_regs, rtx smem, HOST_WIDE_INT words, HOST_WIDE_INT ofs));
145 static void alpha_init_builtins
147 static rtx alpha_expand_builtin
148 PARAMS ((tree, rtx, rtx, enum machine_mode, int));
149 static void alpha_sa_mask
150 PARAMS ((unsigned long *imaskP, unsigned long *fmaskP));
151 static int find_lo_sum
152 PARAMS ((rtx *, void *));
153 static int alpha_does_function_need_gp
155 static int alpha_ra_ever_killed
157 static const char *get_trap_mode_suffix
159 static const char *get_round_mode_suffix
161 static const char *get_some_local_dynamic_name
163 static int get_some_local_dynamic_name_1
164 PARAMS ((rtx *, void *));
165 static rtx set_frame_related_p
167 static const char *alpha_lookup_xfloating_lib_func
168 PARAMS ((enum rtx_code));
169 static int alpha_compute_xfloating_mode_arg
170 PARAMS ((enum rtx_code, enum alpha_fp_rounding_mode));
171 static void alpha_emit_xfloating_libcall
172 PARAMS ((const char *, rtx, rtx[], int, rtx));
173 static rtx alpha_emit_xfloating_compare
174 PARAMS ((enum rtx_code, rtx, rtx));
175 static void alpha_output_function_end_prologue
177 static int alpha_adjust_cost
178 PARAMS ((rtx, rtx, rtx, int));
179 static int alpha_issue_rate
181 static int alpha_use_dfa_pipeline_interface
183 static int alpha_multipass_dfa_lookahead
186 #ifdef OBJECT_FORMAT_ELF
187 static void alpha_elf_select_rtx_section
188 PARAMS ((enum machine_mode, rtx, unsigned HOST_WIDE_INT));
191 #if TARGET_ABI_OPEN_VMS
192 static bool alpha_linkage_symbol_p
193 PARAMS ((const char *symname));
194 static void alpha_write_linkage
195 PARAMS ((FILE *, const char *, tree));
198 static struct machine_function * alpha_init_machine_status
201 static void unicosmk_output_deferred_case_vectors PARAMS ((FILE *));
202 static void unicosmk_gen_dsib PARAMS ((unsigned long *imaskP));
203 static void unicosmk_output_ssib PARAMS ((FILE *, const char *));
204 static int unicosmk_need_dex PARAMS ((rtx));
206 /* Get the number of args of a function in one of two ways. */
207 #if TARGET_ABI_OPEN_VMS || TARGET_ABI_UNICOSMK
208 #define NUM_ARGS current_function_args_info.num_args
210 #define NUM_ARGS current_function_args_info
216 /* Initialize the GCC target structure. */
217 #if TARGET_ABI_OPEN_VMS
218 const struct attribute_spec vms_attribute_table[];
219 static unsigned int vms_section_type_flags PARAMS ((tree, const char *, int));
220 static void vms_asm_named_section PARAMS ((const char *, unsigned int));
221 static void vms_asm_out_constructor PARAMS ((rtx, int));
222 static void vms_asm_out_destructor PARAMS ((rtx, int));
223 # undef TARGET_ATTRIBUTE_TABLE
224 # define TARGET_ATTRIBUTE_TABLE vms_attribute_table
225 # undef TARGET_SECTION_TYPE_FLAGS
226 # define TARGET_SECTION_TYPE_FLAGS vms_section_type_flags
229 #undef TARGET_IN_SMALL_DATA_P
230 #define TARGET_IN_SMALL_DATA_P alpha_in_small_data_p
231 #undef TARGET_ENCODE_SECTION_INFO
232 #define TARGET_ENCODE_SECTION_INFO alpha_encode_section_info
233 #undef TARGET_STRIP_NAME_ENCODING
234 #define TARGET_STRIP_NAME_ENCODING alpha_strip_name_encoding
236 #if TARGET_ABI_UNICOSMK
237 static void unicosmk_asm_named_section PARAMS ((const char *, unsigned int));
238 static void unicosmk_insert_attributes PARAMS ((tree, tree *));
239 static unsigned int unicosmk_section_type_flags PARAMS ((tree, const char *,
241 static void unicosmk_unique_section PARAMS ((tree, int));
242 # undef TARGET_INSERT_ATTRIBUTES
243 # define TARGET_INSERT_ATTRIBUTES unicosmk_insert_attributes
244 # undef TARGET_SECTION_TYPE_FLAGS
245 # define TARGET_SECTION_TYPE_FLAGS unicosmk_section_type_flags
246 # undef TARGET_ASM_UNIQUE_SECTION
247 # define TARGET_ASM_UNIQUE_SECTION unicosmk_unique_section
248 # undef TARGET_ASM_GLOBALIZE_LABEL
249 # define TARGET_ASM_GLOBALIZE_LABEL hook_FILEptr_constcharptr_void
252 #undef TARGET_ASM_ALIGNED_HI_OP
253 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
254 #undef TARGET_ASM_ALIGNED_DI_OP
255 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
257 /* Default unaligned ops are provided for ELF systems. To get unaligned
258 data for non-ELF systems, we have to turn off auto alignment. */
259 #ifndef OBJECT_FORMAT_ELF
260 #undef TARGET_ASM_UNALIGNED_HI_OP
261 #define TARGET_ASM_UNALIGNED_HI_OP "\t.align 0\n\t.word\t"
262 #undef TARGET_ASM_UNALIGNED_SI_OP
263 #define TARGET_ASM_UNALIGNED_SI_OP "\t.align 0\n\t.long\t"
264 #undef TARGET_ASM_UNALIGNED_DI_OP
265 #define TARGET_ASM_UNALIGNED_DI_OP "\t.align 0\n\t.quad\t"
268 #ifdef OBJECT_FORMAT_ELF
269 #undef TARGET_ASM_SELECT_RTX_SECTION
270 #define TARGET_ASM_SELECT_RTX_SECTION alpha_elf_select_rtx_section
273 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
274 #define TARGET_ASM_FUNCTION_END_PROLOGUE alpha_output_function_end_prologue
276 #undef TARGET_SCHED_ADJUST_COST
277 #define TARGET_SCHED_ADJUST_COST alpha_adjust_cost
278 #undef TARGET_SCHED_ISSUE_RATE
279 #define TARGET_SCHED_ISSUE_RATE alpha_issue_rate
280 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
281 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE \
282 alpha_use_dfa_pipeline_interface
283 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
284 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
285 alpha_multipass_dfa_lookahead
287 #undef TARGET_HAVE_TLS
288 #define TARGET_HAVE_TLS HAVE_AS_TLS
290 #undef TARGET_INIT_BUILTINS
291 #define TARGET_INIT_BUILTINS alpha_init_builtins
292 #undef TARGET_EXPAND_BUILTIN
293 #define TARGET_EXPAND_BUILTIN alpha_expand_builtin
295 struct gcc_target targetm = TARGET_INITIALIZER;
297 /* Parse target option strings. */
303 static const struct cpu_table {
304 const char *const name;
305 const enum processor_type processor;
308 #define EV5_MASK (MASK_CPU_EV5)
309 #define EV6_MASK (MASK_CPU_EV6|MASK_BWX|MASK_MAX|MASK_FIX)
310 { "ev4", PROCESSOR_EV4, 0 },
311 { "ev45", PROCESSOR_EV4, 0 },
312 { "21064", PROCESSOR_EV4, 0 },
313 { "ev5", PROCESSOR_EV5, EV5_MASK },
314 { "21164", PROCESSOR_EV5, EV5_MASK },
315 { "ev56", PROCESSOR_EV5, EV5_MASK|MASK_BWX },
316 { "21164a", PROCESSOR_EV5, EV5_MASK|MASK_BWX },
317 { "pca56", PROCESSOR_EV5, EV5_MASK|MASK_BWX|MASK_MAX },
318 { "21164PC",PROCESSOR_EV5, EV5_MASK|MASK_BWX|MASK_MAX },
319 { "21164pc",PROCESSOR_EV5, EV5_MASK|MASK_BWX|MASK_MAX },
320 { "ev6", PROCESSOR_EV6, EV6_MASK },
321 { "21264", PROCESSOR_EV6, EV6_MASK },
322 { "ev67", PROCESSOR_EV6, EV6_MASK|MASK_CIX },
323 { "21264a", PROCESSOR_EV6, EV6_MASK|MASK_CIX },
327 /* Unicos/Mk doesn't have shared libraries. */
328 if (TARGET_ABI_UNICOSMK && flag_pic)
330 warning ("-f%s ignored for Unicos/Mk (not supported)",
331 (flag_pic > 1) ? "PIC" : "pic");
335 /* On Unicos/Mk, the native compiler consistenly generates /d suffices for
336 floating-point instructions. Make that the default for this target. */
337 if (TARGET_ABI_UNICOSMK)
338 alpha_fprm = ALPHA_FPRM_DYN;
340 alpha_fprm = ALPHA_FPRM_NORM;
342 alpha_tp = ALPHA_TP_PROG;
343 alpha_fptm = ALPHA_FPTM_N;
345 /* We cannot use su and sui qualifiers for conversion instructions on
346 Unicos/Mk. I'm not sure if this is due to assembler or hardware
347 limitations. Right now, we issue a warning if -mieee is specified
348 and then ignore it; eventually, we should either get it right or
349 disable the option altogether. */
353 if (TARGET_ABI_UNICOSMK)
354 warning ("-mieee not supported on Unicos/Mk");
357 alpha_tp = ALPHA_TP_INSN;
358 alpha_fptm = ALPHA_FPTM_SU;
362 if (TARGET_IEEE_WITH_INEXACT)
364 if (TARGET_ABI_UNICOSMK)
365 warning ("-mieee-with-inexact not supported on Unicos/Mk");
368 alpha_tp = ALPHA_TP_INSN;
369 alpha_fptm = ALPHA_FPTM_SUI;
375 if (! strcmp (alpha_tp_string, "p"))
376 alpha_tp = ALPHA_TP_PROG;
377 else if (! strcmp (alpha_tp_string, "f"))
378 alpha_tp = ALPHA_TP_FUNC;
379 else if (! strcmp (alpha_tp_string, "i"))
380 alpha_tp = ALPHA_TP_INSN;
382 error ("bad value `%s' for -mtrap-precision switch", alpha_tp_string);
385 if (alpha_fprm_string)
387 if (! strcmp (alpha_fprm_string, "n"))
388 alpha_fprm = ALPHA_FPRM_NORM;
389 else if (! strcmp (alpha_fprm_string, "m"))
390 alpha_fprm = ALPHA_FPRM_MINF;
391 else if (! strcmp (alpha_fprm_string, "c"))
392 alpha_fprm = ALPHA_FPRM_CHOP;
393 else if (! strcmp (alpha_fprm_string,"d"))
394 alpha_fprm = ALPHA_FPRM_DYN;
396 error ("bad value `%s' for -mfp-rounding-mode switch",
400 if (alpha_fptm_string)
402 if (strcmp (alpha_fptm_string, "n") == 0)
403 alpha_fptm = ALPHA_FPTM_N;
404 else if (strcmp (alpha_fptm_string, "u") == 0)
405 alpha_fptm = ALPHA_FPTM_U;
406 else if (strcmp (alpha_fptm_string, "su") == 0)
407 alpha_fptm = ALPHA_FPTM_SU;
408 else if (strcmp (alpha_fptm_string, "sui") == 0)
409 alpha_fptm = ALPHA_FPTM_SUI;
411 error ("bad value `%s' for -mfp-trap-mode switch", alpha_fptm_string);
414 if (alpha_tls_size_string)
416 if (strcmp (alpha_tls_size_string, "16") == 0)
418 else if (strcmp (alpha_tls_size_string, "32") == 0)
420 else if (strcmp (alpha_tls_size_string, "64") == 0)
423 error ("bad value `%s' for -mtls-size switch", alpha_tls_size_string);
427 = TARGET_CPU_DEFAULT & MASK_CPU_EV6 ? PROCESSOR_EV6
428 : (TARGET_CPU_DEFAULT & MASK_CPU_EV5 ? PROCESSOR_EV5 : PROCESSOR_EV4);
430 if (alpha_cpu_string)
432 for (i = 0; cpu_table [i].name; i++)
433 if (! strcmp (alpha_cpu_string, cpu_table [i].name))
435 alpha_cpu = cpu_table [i].processor;
436 target_flags &= ~ (MASK_BWX | MASK_MAX | MASK_FIX | MASK_CIX
437 | MASK_CPU_EV5 | MASK_CPU_EV6);
438 target_flags |= cpu_table [i].flags;
441 if (! cpu_table [i].name)
442 error ("bad value `%s' for -mcpu switch", alpha_cpu_string);
445 if (alpha_tune_string)
447 for (i = 0; cpu_table [i].name; i++)
448 if (! strcmp (alpha_tune_string, cpu_table [i].name))
450 alpha_cpu = cpu_table [i].processor;
453 if (! cpu_table [i].name)
454 error ("bad value `%s' for -mcpu switch", alpha_tune_string);
457 /* Do some sanity checks on the above options. */
459 if (TARGET_ABI_UNICOSMK && alpha_fptm != ALPHA_FPTM_N)
461 warning ("trap mode not supported on Unicos/Mk");
462 alpha_fptm = ALPHA_FPTM_N;
465 if ((alpha_fptm == ALPHA_FPTM_SU || alpha_fptm == ALPHA_FPTM_SUI)
466 && alpha_tp != ALPHA_TP_INSN && ! TARGET_CPU_EV6)
468 warning ("fp software completion requires -mtrap-precision=i");
469 alpha_tp = ALPHA_TP_INSN;
474 /* Except for EV6 pass 1 (not released), we always have precise
475 arithmetic traps. Which means we can do software completion
476 without minding trap shadows. */
477 alpha_tp = ALPHA_TP_PROG;
480 if (TARGET_FLOAT_VAX)
482 if (alpha_fprm == ALPHA_FPRM_MINF || alpha_fprm == ALPHA_FPRM_DYN)
484 warning ("rounding mode not supported for VAX floats");
485 alpha_fprm = ALPHA_FPRM_NORM;
487 if (alpha_fptm == ALPHA_FPTM_SUI)
489 warning ("trap mode not supported for VAX floats");
490 alpha_fptm = ALPHA_FPTM_SU;
498 if (!alpha_mlat_string)
499 alpha_mlat_string = "L1";
501 if (ISDIGIT ((unsigned char)alpha_mlat_string[0])
502 && (lat = strtol (alpha_mlat_string, &end, 10), *end == '\0'))
504 else if ((alpha_mlat_string[0] == 'L' || alpha_mlat_string[0] == 'l')
505 && ISDIGIT ((unsigned char)alpha_mlat_string[1])
506 && alpha_mlat_string[2] == '\0')
508 static int const cache_latency[][4] =
510 { 3, 30, -1 }, /* ev4 -- Bcache is a guess */
511 { 2, 12, 38 }, /* ev5 -- Bcache from PC164 LMbench numbers */
512 { 3, 12, 30 }, /* ev6 -- Bcache from DS20 LMbench. */
515 lat = alpha_mlat_string[1] - '0';
516 if (lat <= 0 || lat > 3 || cache_latency[alpha_cpu][lat-1] == -1)
518 warning ("L%d cache latency unknown for %s",
519 lat, alpha_cpu_name[alpha_cpu]);
523 lat = cache_latency[alpha_cpu][lat-1];
525 else if (! strcmp (alpha_mlat_string, "main"))
527 /* Most current memories have about 370ns latency. This is
528 a reasonable guess for a fast cpu. */
533 warning ("bad value `%s' for -mmemory-latency", alpha_mlat_string);
537 alpha_memory_latency = lat;
540 /* Default the definition of "small data" to 8 bytes. */
544 /* Infer TARGET_SMALL_DATA from -fpic/-fPIC. */
546 target_flags |= MASK_SMALL_DATA;
547 else if (flag_pic == 2)
548 target_flags &= ~MASK_SMALL_DATA;
550 /* Align labels and loops for optimal branching. */
551 /* ??? Kludge these by not doing anything if we don't optimize and also if
552 we are writing ECOFF symbols to work around a bug in DEC's assembler. */
553 if (optimize > 0 && write_symbols != SDB_DEBUG)
555 if (align_loops <= 0)
557 if (align_jumps <= 0)
560 if (align_functions <= 0)
561 align_functions = 16;
563 /* Acquire a unique set number for our register saves and restores. */
564 alpha_sr_alias_set = new_alias_set ();
566 /* Register variables and functions with the garbage collector. */
568 /* Set up function hooks. */
569 init_machine_status = alpha_init_machine_status;
571 /* Tell the compiler when we're using VAX floating point. */
572 if (TARGET_FLOAT_VAX)
574 real_format_for_mode[SFmode - QFmode] = &vax_f_format;
575 real_format_for_mode[DFmode - QFmode] = &vax_g_format;
576 real_format_for_mode[TFmode - QFmode] = NULL;
580 /* Returns 1 if VALUE is a mask that contains full bytes of zero or ones. */
588 for (i = 0; i < HOST_BITS_PER_WIDE_INT / HOST_BITS_PER_CHAR;
590 if ((value & 0xff) != 0 && (value & 0xff) != 0xff)
596 /* Returns 1 if OP is either the constant zero or a register. If a
597 register, it must be in the proper mode unless MODE is VOIDmode. */
600 reg_or_0_operand (op, mode)
602 enum machine_mode mode;
604 return op == CONST0_RTX (mode) || register_operand (op, mode);
607 /* Return 1 if OP is a constant in the range of 0-63 (for a shift) or
611 reg_or_6bit_operand (op, mode)
613 enum machine_mode mode;
615 return ((GET_CODE (op) == CONST_INT
616 && (unsigned HOST_WIDE_INT) INTVAL (op) < 64)
617 || register_operand (op, mode));
621 /* Return 1 if OP is an 8-bit constant or any register. */
624 reg_or_8bit_operand (op, mode)
626 enum machine_mode mode;
628 return ((GET_CODE (op) == CONST_INT
629 && (unsigned HOST_WIDE_INT) INTVAL (op) < 0x100)
630 || register_operand (op, mode));
633 /* Return 1 if OP is a constant or any register. */
636 reg_or_const_int_operand (op, mode)
638 enum machine_mode mode;
640 return GET_CODE (op) == CONST_INT || register_operand (op, mode);
643 /* Return 1 if OP is an 8-bit constant. */
646 cint8_operand (op, mode)
648 enum machine_mode mode ATTRIBUTE_UNUSED;
650 return ((GET_CODE (op) == CONST_INT
651 && (unsigned HOST_WIDE_INT) INTVAL (op) < 0x100));
654 /* Return 1 if the operand is a valid second operand to an add insn. */
657 add_operand (op, mode)
659 enum machine_mode mode;
661 if (GET_CODE (op) == CONST_INT)
662 /* Constraints I, J, O and P are covered by K. */
663 return (CONST_OK_FOR_LETTER_P (INTVAL (op), 'K')
664 || CONST_OK_FOR_LETTER_P (INTVAL (op), 'L'));
666 return register_operand (op, mode);
669 /* Return 1 if the operand is a valid second operand to a sign-extending
673 sext_add_operand (op, mode)
675 enum machine_mode mode;
677 if (GET_CODE (op) == CONST_INT)
678 return (CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')
679 || CONST_OK_FOR_LETTER_P (INTVAL (op), 'O'));
681 return reg_not_elim_operand (op, mode);
684 /* Return 1 if OP is the constant 4 or 8. */
687 const48_operand (op, mode)
689 enum machine_mode mode ATTRIBUTE_UNUSED;
691 return (GET_CODE (op) == CONST_INT
692 && (INTVAL (op) == 4 || INTVAL (op) == 8));
695 /* Return 1 if OP is a valid first operand to an AND insn. */
698 and_operand (op, mode)
700 enum machine_mode mode;
702 if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == VOIDmode)
703 return (zap_mask (CONST_DOUBLE_LOW (op))
704 && zap_mask (CONST_DOUBLE_HIGH (op)));
706 if (GET_CODE (op) == CONST_INT)
707 return ((unsigned HOST_WIDE_INT) INTVAL (op) < 0x100
708 || (unsigned HOST_WIDE_INT) ~ INTVAL (op) < 0x100
709 || zap_mask (INTVAL (op)));
711 return register_operand (op, mode);
714 /* Return 1 if OP is a valid first operand to an IOR or XOR insn. */
717 or_operand (op, mode)
719 enum machine_mode mode;
721 if (GET_CODE (op) == CONST_INT)
722 return ((unsigned HOST_WIDE_INT) INTVAL (op) < 0x100
723 || (unsigned HOST_WIDE_INT) ~ INTVAL (op) < 0x100);
725 return register_operand (op, mode);
728 /* Return 1 if OP is a constant that is the width, in bits, of an integral
729 mode smaller than DImode. */
732 mode_width_operand (op, mode)
734 enum machine_mode mode ATTRIBUTE_UNUSED;
736 return (GET_CODE (op) == CONST_INT
737 && (INTVAL (op) == 8 || INTVAL (op) == 16
738 || INTVAL (op) == 32 || INTVAL (op) == 64));
741 /* Return 1 if OP is a constant that is the width of an integral machine mode
742 smaller than an integer. */
745 mode_mask_operand (op, mode)
747 enum machine_mode mode ATTRIBUTE_UNUSED;
749 if (GET_CODE (op) == CONST_INT)
751 HOST_WIDE_INT value = INTVAL (op);
757 if (value == 0xffffffff)
762 else if (HOST_BITS_PER_WIDE_INT == 32 && GET_CODE (op) == CONST_DOUBLE)
764 if (CONST_DOUBLE_LOW (op) == 0xffffffff && CONST_DOUBLE_HIGH (op) == 0)
771 /* Return 1 if OP is a multiple of 8 less than 64. */
774 mul8_operand (op, mode)
776 enum machine_mode mode ATTRIBUTE_UNUSED;
778 return (GET_CODE (op) == CONST_INT
779 && (unsigned HOST_WIDE_INT) INTVAL (op) < 64
780 && (INTVAL (op) & 7) == 0);
783 /* Return 1 if OP is the zero constant for MODE. */
786 const0_operand (op, mode)
788 enum machine_mode mode;
790 return op == CONST0_RTX (mode);
793 /* Return 1 if OP is a hard floating-point register. */
796 hard_fp_register_operand (op, mode)
798 enum machine_mode mode;
800 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
803 if (GET_CODE (op) == SUBREG)
804 op = SUBREG_REG (op);
805 return GET_CODE (op) == REG && REGNO_REG_CLASS (REGNO (op)) == FLOAT_REGS;
808 /* Return 1 if OP is a hard general register. */
811 hard_int_register_operand (op, mode)
813 enum machine_mode mode;
815 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
818 if (GET_CODE (op) == SUBREG)
819 op = SUBREG_REG (op);
820 return GET_CODE (op) == REG && REGNO_REG_CLASS (REGNO (op)) == GENERAL_REGS;
823 /* Return 1 if OP is a register or a constant integer. */
827 reg_or_cint_operand (op, mode)
829 enum machine_mode mode;
831 return (GET_CODE (op) == CONST_INT
832 || register_operand (op, mode));
835 /* Return 1 if OP is something that can be reloaded into a register;
836 if it is a MEM, it need not be valid. */
839 some_operand (op, mode)
841 enum machine_mode mode;
843 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
846 switch (GET_CODE (op))
860 return some_operand (SUBREG_REG (op), VOIDmode);
869 /* Likewise, but don't accept constants. */
872 some_ni_operand (op, mode)
874 enum machine_mode mode;
876 if (GET_MODE (op) != mode && mode != VOIDmode)
879 if (GET_CODE (op) == SUBREG)
880 op = SUBREG_REG (op);
882 return (GET_CODE (op) == REG || GET_CODE (op) == MEM);
885 /* Return 1 if OP is a valid operand for the source of a move insn. */
888 input_operand (op, mode)
890 enum machine_mode mode;
892 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
895 if (GET_MODE_CLASS (mode) == MODE_FLOAT && GET_MODE (op) != mode)
898 switch (GET_CODE (op))
903 if (TARGET_EXPLICIT_RELOCS)
905 /* We don't split symbolic operands into something unintelligable
906 until after reload, but we do not wish non-small, non-global
907 symbolic operands to be reconstructed from their high/lo_sum
909 return (small_symbolic_operand (op, mode)
910 || global_symbolic_operand (op, mode)
911 || gotdtp_symbolic_operand (op, mode)
912 || gottp_symbolic_operand (op, mode));
915 /* This handles both the Windows/NT and OSF cases. */
916 return mode == ptr_mode || mode == DImode;
919 return (TARGET_EXPLICIT_RELOCS
920 && local_symbolic_operand (XEXP (op, 0), mode));
927 if (register_operand (op, mode))
929 /* ... fall through ... */
931 return ((TARGET_BWX || (mode != HImode && mode != QImode))
932 && general_operand (op, mode));
936 return op == CONST0_RTX (mode);
939 return mode == QImode || mode == HImode || add_operand (op, mode);
951 /* Return 1 if OP is a SYMBOL_REF for a function known to be in this
952 file, and in the same section as the current function. */
955 current_file_function_operand (op, mode)
957 enum machine_mode mode ATTRIBUTE_UNUSED;
959 if (GET_CODE (op) != SYMBOL_REF)
962 /* Easy test for recursion. */
963 if (op == XEXP (DECL_RTL (current_function_decl), 0))
966 /* Otherwise, we need the DECL for the SYMBOL_REF, which we can't get.
967 So SYMBOL_REF_FLAG has been declared to imply that the function is
968 in the default text section. So we must also check that the current
969 function is also in the text section. */
970 if (SYMBOL_REF_FLAG (op) && decl_in_text_section (current_function_decl))
976 /* Return 1 if OP is a SYMBOL_REF for which we can make a call via bsr. */
979 direct_call_operand (op, mode)
981 enum machine_mode mode;
983 /* Must be defined in this file. */
984 if (! current_file_function_operand (op, mode))
987 /* If profiling is implemented via linker tricks, we can't jump
988 to the nogp alternate entry point. */
989 /* ??? TARGET_PROFILING_NEEDS_GP isn't really the right test,
990 but is approximately correct for the OSF ABIs. Don't know
991 what to do for VMS, NT, or UMK. */
992 if (! TARGET_PROFILING_NEEDS_GP
993 && ! current_function_profile)
999 /* Return true if OP is a LABEL_REF, or SYMBOL_REF or CONST referencing
1000 a (non-tls) variable known to be defined in this file. */
1003 local_symbolic_operand (op, mode)
1005 enum machine_mode mode;
1009 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
1012 if (GET_CODE (op) == LABEL_REF)
1015 if (GET_CODE (op) == CONST
1016 && GET_CODE (XEXP (op, 0)) == PLUS
1017 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT)
1018 op = XEXP (XEXP (op, 0), 0);
1020 if (GET_CODE (op) != SYMBOL_REF)
1023 /* Easy pickings. */
1024 if (CONSTANT_POOL_ADDRESS_P (op) || STRING_POOL_ADDRESS_P (op))
1027 /* ??? SYMBOL_REF_FLAG is set for local function symbols, but we
1028 run into problems with the rtl inliner in that the symbol was
1029 once external, but is local after inlining, which results in
1030 unrecognizable insns. */
1034 /* If @[LS], then alpha_encode_section_info sez it's local. */
1035 if (str[0] == '@' && (str[1] == 'L' || str[1] == 'S'))
1038 /* If *$, then ASM_GENERATE_INTERNAL_LABEL sez it's local. */
1039 if (str[0] == '*' && str[1] == '$')
1045 /* Return true if OP is a SYMBOL_REF or CONST referencing a variable
1046 known to be defined in this file in the small data area. */
1049 small_symbolic_operand (op, mode)
1051 enum machine_mode mode ATTRIBUTE_UNUSED;
1055 if (! TARGET_SMALL_DATA)
1058 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
1061 if (GET_CODE (op) == CONST
1062 && GET_CODE (XEXP (op, 0)) == PLUS
1063 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT)
1064 op = XEXP (XEXP (op, 0), 0);
1066 if (GET_CODE (op) != SYMBOL_REF)
1069 if (CONSTANT_POOL_ADDRESS_P (op))
1070 return GET_MODE_SIZE (get_pool_mode (op)) <= (unsigned) g_switch_value;
1074 return str[0] == '@' && str[1] == 'S';
1078 /* Return true if OP is a SYMBOL_REF or CONST referencing a variable
1079 not known (or known not) to be defined in this file. */
1082 global_symbolic_operand (op, mode)
1084 enum machine_mode mode;
1088 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
1091 if (GET_CODE (op) == CONST
1092 && GET_CODE (XEXP (op, 0)) == PLUS
1093 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT)
1094 op = XEXP (XEXP (op, 0), 0);
1096 if (GET_CODE (op) != SYMBOL_REF)
1099 if (local_symbolic_operand (op, mode))
1102 /* Also verify that it's not a TLS symbol. */
1104 return str[0] != '%' && str[0] != '@';
1107 /* Return 1 if OP is a valid operand for the MEM of a CALL insn. */
1110 call_operand (op, mode)
1112 enum machine_mode mode;
1117 if (GET_CODE (op) == REG)
1121 /* Disallow virtual registers to cope with pathalogical test cases
1122 such as compile/930117-1.c in which the virtual reg decomposes
1123 to the frame pointer. Which is a hard reg that is not $27. */
1124 return (REGNO (op) == 27 || REGNO (op) > LAST_VIRTUAL_REGISTER);
1129 if (TARGET_ABI_UNICOSMK)
1131 if (GET_CODE (op) == SYMBOL_REF)
1137 /* Returns 1 if OP is a symbolic operand, i.e. a symbol_ref or a label_ref,
1138 possibly with an offset. */
1141 symbolic_operand (op, mode)
1143 enum machine_mode mode;
1145 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
1147 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
1149 if (GET_CODE (op) == CONST
1150 && GET_CODE (XEXP (op,0)) == PLUS
1151 && GET_CODE (XEXP (XEXP (op,0), 0)) == SYMBOL_REF
1152 && GET_CODE (XEXP (XEXP (op,0), 1)) == CONST_INT)
1157 /* Return true if OP is valid for a particular TLS relocation. */
1160 tls_symbolic_operand_1 (op, mode, size, unspec)
1162 enum machine_mode mode;
1168 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
1171 if (GET_CODE (op) != CONST)
1175 if (GET_CODE (op) != UNSPEC || XINT (op, 1) != unspec)
1177 op = XVECEXP (op, 0, 0);
1179 if (GET_CODE (op) != SYMBOL_REF)
1188 else if (str[0] == '@')
1190 if (alpha_tls_size > size)
1196 letter = (unspec == UNSPEC_DTPREL ? 'D' : 'T');
1198 return str[1] == letter;
1201 /* Return true if OP is valid for 16-bit DTP relative relocations. */
1204 dtp16_symbolic_operand (op, mode)
1206 enum machine_mode mode;
1208 return tls_symbolic_operand_1 (op, mode, 16, UNSPEC_DTPREL);
1211 /* Return true if OP is valid for 32-bit DTP relative relocations. */
1214 dtp32_symbolic_operand (op, mode)
1216 enum machine_mode mode;
1218 return tls_symbolic_operand_1 (op, mode, 32, UNSPEC_DTPREL);
1221 /* Return true if OP is valid for 64-bit DTP relative relocations. */
1224 gotdtp_symbolic_operand (op, mode)
1226 enum machine_mode mode;
1228 return tls_symbolic_operand_1 (op, mode, 64, UNSPEC_DTPREL);
1231 /* Return true if OP is valid for 16-bit TP relative relocations. */
1234 tp16_symbolic_operand (op, mode)
1236 enum machine_mode mode;
1238 return tls_symbolic_operand_1 (op, mode, 16, UNSPEC_TPREL);
1241 /* Return true if OP is valid for 32-bit TP relative relocations. */
1244 tp32_symbolic_operand (op, mode)
1246 enum machine_mode mode;
1248 return tls_symbolic_operand_1 (op, mode, 32, UNSPEC_TPREL);
1251 /* Return true if OP is valid for 64-bit TP relative relocations. */
1254 gottp_symbolic_operand (op, mode)
1256 enum machine_mode mode;
1258 return tls_symbolic_operand_1 (op, mode, 64, UNSPEC_TPREL);
1261 /* Return 1 if OP is a valid Alpha comparison operator. Here we know which
1262 comparisons are valid in which insn. */
1265 alpha_comparison_operator (op, mode)
1267 enum machine_mode mode;
1269 enum rtx_code code = GET_CODE (op);
1271 if (mode != GET_MODE (op) && mode != VOIDmode)
1274 return (code == EQ || code == LE || code == LT
1275 || code == LEU || code == LTU);
1278 /* Return 1 if OP is a valid Alpha comparison operator against zero.
1279 Here we know which comparisons are valid in which insn. */
1282 alpha_zero_comparison_operator (op, mode)
1284 enum machine_mode mode;
1286 enum rtx_code code = GET_CODE (op);
1288 if (mode != GET_MODE (op) && mode != VOIDmode)
1291 return (code == EQ || code == NE || code == LE || code == LT
1292 || code == LEU || code == LTU);
1295 /* Return 1 if OP is a valid Alpha swapped comparison operator. */
1298 alpha_swapped_comparison_operator (op, mode)
1300 enum machine_mode mode;
1302 enum rtx_code code = GET_CODE (op);
1304 if ((mode != GET_MODE (op) && mode != VOIDmode)
1305 || GET_RTX_CLASS (code) != '<')
1308 code = swap_condition (code);
1309 return (code == EQ || code == LE || code == LT
1310 || code == LEU || code == LTU);
1313 /* Return 1 if OP is a signed comparison operation. */
1316 signed_comparison_operator (op, mode)
1318 enum machine_mode mode ATTRIBUTE_UNUSED;
1320 enum rtx_code code = GET_CODE (op);
1322 if (mode != GET_MODE (op) && mode != VOIDmode)
1325 return (code == EQ || code == NE
1326 || code == LE || code == LT
1327 || code == GE || code == GT);
1330 /* Return 1 if OP is a valid Alpha floating point comparison operator.
1331 Here we know which comparisons are valid in which insn. */
1334 alpha_fp_comparison_operator (op, mode)
1336 enum machine_mode mode;
1338 enum rtx_code code = GET_CODE (op);
1340 if (mode != GET_MODE (op) && mode != VOIDmode)
1343 return (code == EQ || code == LE || code == LT || code == UNORDERED);
1346 /* Return 1 if this is a divide or modulus operator. */
1349 divmod_operator (op, mode)
1351 enum machine_mode mode ATTRIBUTE_UNUSED;
1353 switch (GET_CODE (op))
1355 case DIV: case MOD: case UDIV: case UMOD:
1365 /* Return 1 if this memory address is a known aligned register plus
1366 a constant. It must be a valid address. This means that we can do
1367 this as an aligned reference plus some offset.
1369 Take into account what reload will do. */
1372 aligned_memory_operand (op, mode)
1374 enum machine_mode mode;
1378 if (reload_in_progress)
1381 if (GET_CODE (tmp) == SUBREG)
1382 tmp = SUBREG_REG (tmp);
1383 if (GET_CODE (tmp) == REG
1384 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER)
1386 op = reg_equiv_memory_loc[REGNO (tmp)];
1392 if (GET_CODE (op) != MEM
1393 || GET_MODE (op) != mode)
1397 /* LEGITIMIZE_RELOAD_ADDRESS creates (plus (plus reg const_hi) const_lo)
1398 sorts of constructs. Dig for the real base register. */
1399 if (reload_in_progress
1400 && GET_CODE (op) == PLUS
1401 && GET_CODE (XEXP (op, 0)) == PLUS)
1402 base = XEXP (XEXP (op, 0), 0);
1405 if (! memory_address_p (mode, op))
1407 base = (GET_CODE (op) == PLUS ? XEXP (op, 0) : op);
1410 return (GET_CODE (base) == REG && REGNO_POINTER_ALIGN (REGNO (base)) >= 32);
1413 /* Similar, but return 1 if OP is a MEM which is not alignable. */
1416 unaligned_memory_operand (op, mode)
1418 enum machine_mode mode;
1422 if (reload_in_progress)
1425 if (GET_CODE (tmp) == SUBREG)
1426 tmp = SUBREG_REG (tmp);
1427 if (GET_CODE (tmp) == REG
1428 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER)
1430 op = reg_equiv_memory_loc[REGNO (tmp)];
1436 if (GET_CODE (op) != MEM
1437 || GET_MODE (op) != mode)
1441 /* LEGITIMIZE_RELOAD_ADDRESS creates (plus (plus reg const_hi) const_lo)
1442 sorts of constructs. Dig for the real base register. */
1443 if (reload_in_progress
1444 && GET_CODE (op) == PLUS
1445 && GET_CODE (XEXP (op, 0)) == PLUS)
1446 base = XEXP (XEXP (op, 0), 0);
1449 if (! memory_address_p (mode, op))
1451 base = (GET_CODE (op) == PLUS ? XEXP (op, 0) : op);
1454 return (GET_CODE (base) == REG && REGNO_POINTER_ALIGN (REGNO (base)) < 32);
1457 /* Return 1 if OP is either a register or an unaligned memory location. */
1460 reg_or_unaligned_mem_operand (op, mode)
1462 enum machine_mode mode;
1464 return register_operand (op, mode) || unaligned_memory_operand (op, mode);
1467 /* Return 1 if OP is any memory location. During reload a pseudo matches. */
1470 any_memory_operand (op, mode)
1472 enum machine_mode mode ATTRIBUTE_UNUSED;
1474 return (GET_CODE (op) == MEM
1475 || (GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == REG)
1476 || (reload_in_progress && GET_CODE (op) == REG
1477 && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1478 || (reload_in_progress && GET_CODE (op) == SUBREG
1479 && GET_CODE (SUBREG_REG (op)) == REG
1480 && REGNO (SUBREG_REG (op)) >= FIRST_PSEUDO_REGISTER));
1483 /* Returns 1 if OP is not an eliminable register.
1485 This exists to cure a pathological abort in the s8addq (et al) patterns,
1487 long foo () { long t; bar(); return (long) &t * 26107; }
1489 which run afoul of a hack in reload to cure a (presumably) similar
1490 problem with lea-type instructions on other targets. But there is
1491 one of us and many of them, so work around the problem by selectively
1492 preventing combine from making the optimization. */
1495 reg_not_elim_operand (op, mode)
1497 enum machine_mode mode;
1500 if (GET_CODE (op) == SUBREG)
1501 inner = SUBREG_REG (op);
1502 if (inner == frame_pointer_rtx || inner == arg_pointer_rtx)
1505 return register_operand (op, mode);
1508 /* Return 1 is OP is a memory location that is not a reference (using
1509 an AND) to an unaligned location. Take into account what reload
1513 normal_memory_operand (op, mode)
1515 enum machine_mode mode ATTRIBUTE_UNUSED;
1517 if (reload_in_progress)
1520 if (GET_CODE (tmp) == SUBREG)
1521 tmp = SUBREG_REG (tmp);
1522 if (GET_CODE (tmp) == REG
1523 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER)
1525 op = reg_equiv_memory_loc[REGNO (tmp)];
1527 /* This may not have been assigned an equivalent address if it will
1528 be eliminated. In that case, it doesn't matter what we do. */
1534 return GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) != AND;
1537 /* Accept a register, but not a subreg of any kind. This allows us to
1538 avoid pathological cases in reload wrt data movement common in
1539 int->fp conversion. */
1542 reg_no_subreg_operand (op, mode)
1544 enum machine_mode mode;
1546 if (GET_CODE (op) != REG)
1548 return register_operand (op, mode);
1551 /* Recognize an addition operation that includes a constant. Used to
1552 convince reload to canonize (plus (plus reg c1) c2) during register
1556 addition_operation (op, mode)
1558 enum machine_mode mode;
1560 if (GET_MODE (op) != mode && mode != VOIDmode)
1562 if (GET_CODE (op) == PLUS
1563 && register_operand (XEXP (op, 0), mode)
1564 && GET_CODE (XEXP (op, 1)) == CONST_INT
1565 && CONST_OK_FOR_LETTER_P (INTVAL (XEXP (op, 1)), 'K'))
1570 /* Implements CONST_OK_FOR_LETTER_P. Return true if the value matches
1571 the range defined for C in [I-P]. */
1574 alpha_const_ok_for_letter_p (value, c)
1575 HOST_WIDE_INT value;
1581 /* An unsigned 8 bit constant. */
1582 return (unsigned HOST_WIDE_INT) value < 0x100;
1584 /* The constant zero. */
1587 /* A signed 16 bit constant. */
1588 return (unsigned HOST_WIDE_INT) (value + 0x8000) < 0x10000;
1590 /* A shifted signed 16 bit constant appropriate for LDAH. */
1591 return ((value & 0xffff) == 0
1592 && ((value) >> 31 == -1 || value >> 31 == 0));
1594 /* A constant that can be AND'ed with using a ZAP insn. */
1595 return zap_mask (value);
1597 /* A complemented unsigned 8 bit constant. */
1598 return (unsigned HOST_WIDE_INT) (~ value) < 0x100;
1600 /* A negated unsigned 8 bit constant. */
1601 return (unsigned HOST_WIDE_INT) (- value) < 0x100;
1603 /* The constant 1, 2 or 3. */
1604 return value == 1 || value == 2 || value == 3;
1611 /* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
1612 matches for C in [GH]. */
1615 alpha_const_double_ok_for_letter_p (value, c)
1622 /* The floating point zero constant. */
1623 return (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT
1624 && value == CONST0_RTX (GET_MODE (value)));
1627 /* A valid operand of a ZAP insn. */
1628 return (GET_MODE (value) == VOIDmode
1629 && zap_mask (CONST_DOUBLE_LOW (value))
1630 && zap_mask (CONST_DOUBLE_HIGH (value)));
1637 /* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
1641 alpha_extra_constraint (value, c)
1648 return normal_memory_operand (value, VOIDmode);
1650 return direct_call_operand (value, Pmode);
1652 return (GET_CODE (value) == CONST_INT
1653 && (unsigned HOST_WIDE_INT) INTVAL (value) < 64);
1655 return GET_CODE (value) == HIGH;
1657 return TARGET_ABI_UNICOSMK && symbolic_operand (value, VOIDmode);
1659 return (GET_CODE (value) == CONST_VECTOR
1660 && value == CONST0_RTX (GET_MODE (value)));
1666 /* Return 1 if this function can directly return via $26. */
1671 return (! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK
1673 && alpha_sa_size () == 0
1674 && get_frame_size () == 0
1675 && current_function_outgoing_args_size == 0
1676 && current_function_pretend_args_size == 0);
1679 /* Return the ADDR_VEC associated with a tablejump insn. */
1682 alpha_tablejump_addr_vec (insn)
1687 tmp = JUMP_LABEL (insn);
1690 tmp = NEXT_INSN (tmp);
1693 if (GET_CODE (tmp) == JUMP_INSN
1694 && GET_CODE (PATTERN (tmp)) == ADDR_DIFF_VEC)
1695 return PATTERN (tmp);
1699 /* Return the label of the predicted edge, or CONST0_RTX if we don't know. */
1702 alpha_tablejump_best_label (insn)
1705 rtx jump_table = alpha_tablejump_addr_vec (insn);
1706 rtx best_label = NULL_RTX;
1708 /* ??? Once the CFG doesn't keep getting completely rebuilt, look
1709 there for edge frequency counts from profile data. */
1713 int n_labels = XVECLEN (jump_table, 1);
1714 int best_count = -1;
1717 for (i = 0; i < n_labels; i++)
1721 for (j = i + 1; j < n_labels; j++)
1722 if (XEXP (XVECEXP (jump_table, 1, i), 0)
1723 == XEXP (XVECEXP (jump_table, 1, j), 0))
1726 if (count > best_count)
1727 best_count = count, best_label = XVECEXP (jump_table, 1, i);
1731 return best_label ? best_label : const0_rtx;
1734 /* Return the TLS model to use for SYMBOL. */
1736 static enum tls_model
1737 tls_symbolic_operand_type (symbol)
1742 if (GET_CODE (symbol) != SYMBOL_REF)
1744 str = XSTR (symbol, 0);
1748 /* ??? Be prepared for -ftls-model=local-dynamic. Perhaps we shouldn't
1749 have separately encoded local-ness. On well, maybe the user will use
1750 attribute visibility next time. At least we don't crash... */
1751 if (str[1] == 'G' || str[1] == 'D')
1752 return TLS_MODEL_GLOBAL_DYNAMIC;
1754 return TLS_MODEL_INITIAL_EXEC;
1756 else if (str[0] == '@')
1760 /* Local dynamic is a waste if we're not going to combine
1761 the __tls_get_addr calls. So avoid it if not optimizing. */
1763 return TLS_MODEL_LOCAL_DYNAMIC;
1765 return TLS_MODEL_GLOBAL_DYNAMIC;
1769 /* 64-bit local exec is the same as initial exec except without
1770 the dynamic relocation. In either case we use a got entry. */
1771 if (alpha_tls_size == 64)
1772 return TLS_MODEL_INITIAL_EXEC;
1774 return TLS_MODEL_LOCAL_EXEC;
1782 /* Return true if the function DECL will be placed in the default text
1784 /* ??? Ideally we'd be able to always move from a SYMBOL_REF back to the
1785 decl, as that would allow us to determine if two functions are in the
1786 same section, which is what we really want to know. */
1789 decl_in_text_section (decl)
1792 return (DECL_SECTION_NAME (decl) == NULL_TREE
1793 && ! (flag_function_sections
1794 || (targetm.have_named_sections
1795 && DECL_ONE_ONLY (decl))));
1798 /* Return true if EXP should be placed in the small data section. */
1801 alpha_in_small_data_p (exp)
1804 /* We want to merge strings, so we never consider them small data. */
1805 if (TREE_CODE (exp) == STRING_CST)
1808 if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp))
1810 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp));
1811 if (strcmp (section, ".sdata") == 0
1812 || strcmp (section, ".sbss") == 0)
1817 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp));
1819 /* If this is an incomplete type with size 0, then we can't put it
1820 in sdata because it might be too big when completed. */
1821 if (size > 0 && size <= g_switch_value)
1828 /* If we are referencing a function that is static, make the SYMBOL_REF
1829 special. We use this to see indicate we can branch to this function
1830 without setting PV or restoring GP.
1832 If this is a variable that is known to be defined locally, add "@v"
1833 to the name. If in addition the variable is to go in .sdata/.sbss,
1834 then add "@s" instead. */
1837 alpha_encode_section_info (decl, first)
1839 int first ATTRIBUTE_UNUSED;
1841 const char *symbol_str;
1846 rtl = DECL_P (decl) ? DECL_RTL (decl) : TREE_CST_RTL (decl);
1848 /* Careful not to prod global register variables. */
1849 if (GET_CODE (rtl) != MEM)
1851 symbol = XEXP (rtl, 0);
1852 if (GET_CODE (symbol) != SYMBOL_REF)
1855 if (TREE_CODE (decl) == FUNCTION_DECL)
1857 /* We mark public functions once they are emitted; otherwise we
1858 don't know that they exist in this unit of translation. */
1859 if (TREE_PUBLIC (decl))
1862 /* Do not mark functions that are not in .text; otherwise we
1863 don't know that they are near enough for a direct branch. */
1864 if (! decl_in_text_section (decl))
1867 SYMBOL_REF_FLAG (symbol) = 1;
1871 /* Early out if we're not going to do anything with this data. */
1872 if (! TARGET_EXPLICIT_RELOCS)
1875 symbol_str = XSTR (symbol, 0);
1877 /* A variable is considered "local" if it is defined in this module. */
1878 is_local = (*targetm.binds_local_p) (decl);
1880 /* Care for TLS variables. */
1881 if (TREE_CODE (decl) == VAR_DECL && DECL_THREAD_LOCAL (decl))
1883 switch (decl_tls_model (decl))
1885 case TLS_MODEL_GLOBAL_DYNAMIC:
1888 case TLS_MODEL_LOCAL_DYNAMIC:
1891 case TLS_MODEL_INITIAL_EXEC:
1892 case TLS_MODEL_LOCAL_EXEC:
1899 /* Determine if DECL will wind up in .sdata/.sbss. */
1900 if (alpha_in_small_data_p (decl))
1906 /* Finally, encode this into the symbol string. */
1912 if (symbol_str[0] == (is_local ? '@' : '%'))
1914 if (symbol_str[1] == encoding)
1919 len = strlen (symbol_str) + 1;
1920 newstr = alloca (len + 2);
1922 newstr[0] = (is_local ? '@' : '%');
1923 newstr[1] = encoding;
1924 memcpy (newstr + 2, symbol_str, len);
1926 XSTR (symbol, 0) = ggc_alloc_string (newstr, len + 2 - 1);
1930 /* Undo the effects of the above. */
1933 alpha_strip_name_encoding (str)
1936 if (str[0] == '@' || str[0] == '%')
1943 #if TARGET_ABI_OPEN_VMS
1945 alpha_linkage_symbol_p (symname)
1946 const char *symname;
1948 int symlen = strlen (symname);
1951 return strcmp (&symname [symlen - 4], "..lk") == 0;
1956 #define LINKAGE_SYMBOL_REF_P(X) \
1957 ((GET_CODE (X) == SYMBOL_REF \
1958 && alpha_linkage_symbol_p (XSTR (X, 0))) \
1959 || (GET_CODE (X) == CONST \
1960 && GET_CODE (XEXP (X, 0)) == PLUS \
1961 && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF \
1962 && alpha_linkage_symbol_p (XSTR (XEXP (XEXP (X, 0), 0), 0))))
1965 /* legitimate_address_p recognizes an RTL expression that is a valid
1966 memory address for an instruction. The MODE argument is the
1967 machine mode for the MEM expression that wants to use this address.
1969 For Alpha, we have either a constant address or the sum of a
1970 register and a constant address, or just a register. For DImode,
1971 any of those forms can be surrounded with an AND that clear the
1972 low-order three bits; this is an "unaligned" access. */
1975 alpha_legitimate_address_p (mode, x, strict)
1976 enum machine_mode mode;
1980 /* If this is an ldq_u type address, discard the outer AND. */
1982 && GET_CODE (x) == AND
1983 && GET_CODE (XEXP (x, 1)) == CONST_INT
1984 && INTVAL (XEXP (x, 1)) == -8)
1987 /* Discard non-paradoxical subregs. */
1988 if (GET_CODE (x) == SUBREG
1989 && (GET_MODE_SIZE (GET_MODE (x))
1990 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
1993 /* Unadorned general registers are valid. */
1996 ? STRICT_REG_OK_FOR_BASE_P (x)
1997 : NONSTRICT_REG_OK_FOR_BASE_P (x)))
2000 /* Constant addresses (i.e. +/- 32k) are valid. */
2001 if (CONSTANT_ADDRESS_P (x))
2004 #if TARGET_ABI_OPEN_VMS
2005 if (LINKAGE_SYMBOL_REF_P (x))
2009 /* Register plus a small constant offset is valid. */
2010 if (GET_CODE (x) == PLUS)
2012 rtx ofs = XEXP (x, 1);
2015 /* Discard non-paradoxical subregs. */
2016 if (GET_CODE (x) == SUBREG
2017 && (GET_MODE_SIZE (GET_MODE (x))
2018 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
2024 && NONSTRICT_REG_OK_FP_BASE_P (x)
2025 && GET_CODE (ofs) == CONST_INT)
2028 ? STRICT_REG_OK_FOR_BASE_P (x)
2029 : NONSTRICT_REG_OK_FOR_BASE_P (x))
2030 && CONSTANT_ADDRESS_P (ofs))
2033 else if (GET_CODE (x) == ADDRESSOF
2034 && GET_CODE (ofs) == CONST_INT)
2038 /* If we're managing explicit relocations, LO_SUM is valid, as
2039 are small data symbols. */
2040 else if (TARGET_EXPLICIT_RELOCS)
2042 if (small_symbolic_operand (x, Pmode))
2045 if (GET_CODE (x) == LO_SUM)
2047 rtx ofs = XEXP (x, 1);
2050 /* Discard non-paradoxical subregs. */
2051 if (GET_CODE (x) == SUBREG
2052 && (GET_MODE_SIZE (GET_MODE (x))
2053 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
2056 /* Must have a valid base register. */
2059 ? STRICT_REG_OK_FOR_BASE_P (x)
2060 : NONSTRICT_REG_OK_FOR_BASE_P (x))))
2063 /* The symbol must be local. */
2064 if (local_symbolic_operand (ofs, Pmode)
2065 || dtp32_symbolic_operand (ofs, Pmode)
2066 || tp32_symbolic_operand (ofs, Pmode))
2074 /* Try machine-dependent ways of modifying an illegitimate address
2075 to be legitimate. If we find one, return the new, valid address. */
2078 alpha_legitimize_address (x, scratch, mode)
2081 enum machine_mode mode ATTRIBUTE_UNUSED;
2083 HOST_WIDE_INT addend;
2085 /* If the address is (plus reg const_int) and the CONST_INT is not a
2086 valid offset, compute the high part of the constant and add it to
2087 the register. Then our address is (plus temp low-part-const). */
2088 if (GET_CODE (x) == PLUS
2089 && GET_CODE (XEXP (x, 0)) == REG
2090 && GET_CODE (XEXP (x, 1)) == CONST_INT
2091 && ! CONSTANT_ADDRESS_P (XEXP (x, 1)))
2093 addend = INTVAL (XEXP (x, 1));
2098 /* If the address is (const (plus FOO const_int)), find the low-order
2099 part of the CONST_INT. Then load FOO plus any high-order part of the
2100 CONST_INT into a register. Our address is (plus reg low-part-const).
2101 This is done to reduce the number of GOT entries. */
2103 && GET_CODE (x) == CONST
2104 && GET_CODE (XEXP (x, 0)) == PLUS
2105 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
2107 addend = INTVAL (XEXP (XEXP (x, 0), 1));
2108 x = force_reg (Pmode, XEXP (XEXP (x, 0), 0));
2112 /* If we have a (plus reg const), emit the load as in (2), then add
2113 the two registers, and finally generate (plus reg low-part-const) as
2116 && GET_CODE (x) == PLUS
2117 && GET_CODE (XEXP (x, 0)) == REG
2118 && GET_CODE (XEXP (x, 1)) == CONST
2119 && GET_CODE (XEXP (XEXP (x, 1), 0)) == PLUS
2120 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == CONST_INT)
2122 addend = INTVAL (XEXP (XEXP (XEXP (x, 1), 0), 1));
2123 x = expand_simple_binop (Pmode, PLUS, XEXP (x, 0),
2124 XEXP (XEXP (XEXP (x, 1), 0), 0),
2125 NULL_RTX, 1, OPTAB_LIB_WIDEN);
2129 /* If this is a local symbol, split the address into HIGH/LO_SUM parts. */
2130 if (TARGET_EXPLICIT_RELOCS && symbolic_operand (x, Pmode))
2132 rtx r0, r16, eqv, tga, tp, insn, dest, seq;
2134 switch (tls_symbolic_operand_type (x))
2136 case TLS_MODEL_GLOBAL_DYNAMIC:
2139 r0 = gen_rtx_REG (Pmode, 0);
2140 r16 = gen_rtx_REG (Pmode, 16);
2141 tga = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_addr");
2142 dest = gen_reg_rtx (Pmode);
2143 seq = GEN_INT (alpha_next_sequence_number++);
2145 emit_insn (gen_movdi_er_tlsgd (r16, pic_offset_table_rtx, x, seq));
2146 insn = gen_call_value_osf_tlsgd (r0, tga, seq);
2147 insn = emit_call_insn (insn);
2148 CONST_OR_PURE_CALL_P (insn) = 1;
2149 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r16);
2151 insn = get_insns ();
2154 emit_libcall_block (insn, dest, r0, x);
2157 case TLS_MODEL_LOCAL_DYNAMIC:
2160 r0 = gen_rtx_REG (Pmode, 0);
2161 r16 = gen_rtx_REG (Pmode, 16);
2162 tga = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_addr");
2163 scratch = gen_reg_rtx (Pmode);
2164 seq = GEN_INT (alpha_next_sequence_number++);
2166 emit_insn (gen_movdi_er_tlsldm (r16, pic_offset_table_rtx, seq));
2167 insn = gen_call_value_osf_tlsldm (r0, tga, seq);
2168 insn = emit_call_insn (insn);
2169 CONST_OR_PURE_CALL_P (insn) = 1;
2170 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r16);
2172 insn = get_insns ();
2175 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
2176 UNSPEC_TLSLDM_CALL);
2177 emit_libcall_block (insn, scratch, r0, eqv);
2179 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_DTPREL);
2180 eqv = gen_rtx_CONST (Pmode, eqv);
2182 if (alpha_tls_size == 64)
2184 dest = gen_reg_rtx (Pmode);
2185 emit_insn (gen_rtx_SET (VOIDmode, dest, eqv));
2186 emit_insn (gen_adddi3 (dest, dest, scratch));
2189 if (alpha_tls_size == 32)
2191 insn = gen_rtx_HIGH (Pmode, eqv);
2192 insn = gen_rtx_PLUS (Pmode, scratch, insn);
2193 scratch = gen_reg_rtx (Pmode);
2194 emit_insn (gen_rtx_SET (VOIDmode, scratch, insn));
2196 return gen_rtx_LO_SUM (Pmode, scratch, eqv);
2198 case TLS_MODEL_INITIAL_EXEC:
2199 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_TPREL);
2200 eqv = gen_rtx_CONST (Pmode, eqv);
2201 tp = gen_reg_rtx (Pmode);
2202 scratch = gen_reg_rtx (Pmode);
2203 dest = gen_reg_rtx (Pmode);
2205 emit_insn (gen_load_tp (tp));
2206 emit_insn (gen_rtx_SET (VOIDmode, scratch, eqv));
2207 emit_insn (gen_adddi3 (dest, tp, scratch));
2210 case TLS_MODEL_LOCAL_EXEC:
2211 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_TPREL);
2212 eqv = gen_rtx_CONST (Pmode, eqv);
2213 tp = gen_reg_rtx (Pmode);
2215 emit_insn (gen_load_tp (tp));
2216 if (alpha_tls_size == 32)
2218 insn = gen_rtx_HIGH (Pmode, eqv);
2219 insn = gen_rtx_PLUS (Pmode, tp, insn);
2220 tp = gen_reg_rtx (Pmode);
2221 emit_insn (gen_rtx_SET (VOIDmode, tp, insn));
2223 return gen_rtx_LO_SUM (Pmode, tp, eqv);
2226 if (local_symbolic_operand (x, Pmode))
2228 if (small_symbolic_operand (x, Pmode))
2232 if (!no_new_pseudos)
2233 scratch = gen_reg_rtx (Pmode);
2234 emit_insn (gen_rtx_SET (VOIDmode, scratch,
2235 gen_rtx_HIGH (Pmode, x)));
2236 return gen_rtx_LO_SUM (Pmode, scratch, x);
2245 HOST_WIDE_INT low, high;
2247 low = ((addend & 0xffff) ^ 0x8000) - 0x8000;
2249 high = ((addend & 0xffffffff) ^ 0x80000000) - 0x80000000;
2253 x = expand_simple_binop (Pmode, PLUS, x, GEN_INT (addend),
2254 (no_new_pseudos ? scratch : NULL_RTX),
2255 1, OPTAB_LIB_WIDEN);
2257 x = expand_simple_binop (Pmode, PLUS, x, GEN_INT (high),
2258 (no_new_pseudos ? scratch : NULL_RTX),
2259 1, OPTAB_LIB_WIDEN);
2261 return plus_constant (x, low);
2265 /* For TARGET_EXPLICIT_RELOCS, we don't obfuscate a SYMBOL_REF to a
2266 small symbolic operand until after reload. At which point we need
2267 to replace (mem (symbol_ref)) with (mem (lo_sum $29 symbol_ref))
2268 so that sched2 has the proper dependency information. */
2271 some_small_symbolic_operand (x, mode)
2273 enum machine_mode mode ATTRIBUTE_UNUSED;
2275 return for_each_rtx (&x, some_small_symbolic_operand_1, NULL);
2279 some_small_symbolic_operand_1 (px, data)
2281 void *data ATTRIBUTE_UNUSED;
2285 /* Don't re-split. */
2286 if (GET_CODE (x) == LO_SUM)
2289 return small_symbolic_operand (x, Pmode) != 0;
2293 split_small_symbolic_operand (x)
2297 for_each_rtx (&x, split_small_symbolic_operand_1, NULL);
2302 split_small_symbolic_operand_1 (px, data)
2304 void *data ATTRIBUTE_UNUSED;
2308 /* Don't re-split. */
2309 if (GET_CODE (x) == LO_SUM)
2312 if (small_symbolic_operand (x, Pmode))
2314 x = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, x);
2322 /* Try a machine-dependent way of reloading an illegitimate address
2323 operand. If we find one, push the reload and return the new rtx. */
2326 alpha_legitimize_reload_address (x, mode, opnum, type, ind_levels)
2328 enum machine_mode mode ATTRIBUTE_UNUSED;
2331 int ind_levels ATTRIBUTE_UNUSED;
2333 /* We must recognize output that we have already generated ourselves. */
2334 if (GET_CODE (x) == PLUS
2335 && GET_CODE (XEXP (x, 0)) == PLUS
2336 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
2337 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2338 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2340 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
2341 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
2346 /* We wish to handle large displacements off a base register by
2347 splitting the addend across an ldah and the mem insn. This
2348 cuts number of extra insns needed from 3 to 1. */
2349 if (GET_CODE (x) == PLUS
2350 && GET_CODE (XEXP (x, 0)) == REG
2351 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2352 && REGNO_OK_FOR_BASE_P (REGNO (XEXP (x, 0)))
2353 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2355 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
2356 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
2358 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
2360 /* Check for 32-bit overflow. */
2361 if (high + low != val)
2364 /* Reload the high part into a base reg; leave the low part
2365 in the mem directly. */
2366 x = gen_rtx_PLUS (GET_MODE (x),
2367 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
2371 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
2372 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
2380 /* REF is an alignable memory location. Place an aligned SImode
2381 reference into *PALIGNED_MEM and the number of bits to shift into
2382 *PBITNUM. SCRATCH is a free register for use in reloading out
2383 of range stack slots. */
2386 get_aligned_mem (ref, paligned_mem, pbitnum)
2388 rtx *paligned_mem, *pbitnum;
2391 HOST_WIDE_INT offset = 0;
2393 if (GET_CODE (ref) != MEM)
2396 if (reload_in_progress
2397 && ! memory_address_p (GET_MODE (ref), XEXP (ref, 0)))
2399 base = find_replacement (&XEXP (ref, 0));
2401 if (! memory_address_p (GET_MODE (ref), base))
2406 base = XEXP (ref, 0);
2409 if (GET_CODE (base) == PLUS)
2410 offset += INTVAL (XEXP (base, 1)), base = XEXP (base, 0);
2413 = widen_memory_access (ref, SImode, (offset & ~3) - offset);
2415 if (WORDS_BIG_ENDIAN)
2416 *pbitnum = GEN_INT (32 - (GET_MODE_BITSIZE (GET_MODE (ref))
2417 + (offset & 3) * 8));
2419 *pbitnum = GEN_INT ((offset & 3) * 8);
2422 /* Similar, but just get the address. Handle the two reload cases.
2423 Add EXTRA_OFFSET to the address we return. */
2426 get_unaligned_address (ref, extra_offset)
2431 HOST_WIDE_INT offset = 0;
2433 if (GET_CODE (ref) != MEM)
2436 if (reload_in_progress
2437 && ! memory_address_p (GET_MODE (ref), XEXP (ref, 0)))
2439 base = find_replacement (&XEXP (ref, 0));
2441 if (! memory_address_p (GET_MODE (ref), base))
2446 base = XEXP (ref, 0);
2449 if (GET_CODE (base) == PLUS)
2450 offset += INTVAL (XEXP (base, 1)), base = XEXP (base, 0);
2452 return plus_constant (base, offset + extra_offset);
2455 /* On the Alpha, all (non-symbolic) constants except zero go into
2456 a floating-point register via memory. Note that we cannot
2457 return anything that is not a subset of CLASS, and that some
2458 symbolic constants cannot be dropped to memory. */
2461 alpha_preferred_reload_class(x, class)
2463 enum reg_class class;
2465 /* Zero is present in any register class. */
2466 if (x == CONST0_RTX (GET_MODE (x)))
2469 /* These sorts of constants we can easily drop to memory. */
2470 if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
2472 if (class == FLOAT_REGS)
2474 if (class == ALL_REGS)
2475 return GENERAL_REGS;
2479 /* All other kinds of constants should not (and in the case of HIGH
2480 cannot) be dropped to memory -- instead we use a GENERAL_REGS
2481 secondary reload. */
2483 return (class == ALL_REGS ? GENERAL_REGS : class);
2488 /* Loading and storing HImode or QImode values to and from memory
2489 usually requires a scratch register. The exceptions are loading
2490 QImode and HImode from an aligned address to a general register
2491 unless byte instructions are permitted.
2493 We also cannot load an unaligned address or a paradoxical SUBREG
2494 into an FP register.
2496 We also cannot do integral arithmetic into FP regs, as might result
2497 from register elimination into a DImode fp register. */
2500 secondary_reload_class (class, mode, x, in)
2501 enum reg_class class;
2502 enum machine_mode mode;
2506 if ((mode == QImode || mode == HImode) && ! TARGET_BWX)
2508 if (GET_CODE (x) == MEM
2509 || (GET_CODE (x) == REG && REGNO (x) >= FIRST_PSEUDO_REGISTER)
2510 || (GET_CODE (x) == SUBREG
2511 && (GET_CODE (SUBREG_REG (x)) == MEM
2512 || (GET_CODE (SUBREG_REG (x)) == REG
2513 && REGNO (SUBREG_REG (x)) >= FIRST_PSEUDO_REGISTER))))
2515 if (!in || !aligned_memory_operand(x, mode))
2516 return GENERAL_REGS;
2520 if (class == FLOAT_REGS)
2522 if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == AND)
2523 return GENERAL_REGS;
2525 if (GET_CODE (x) == SUBREG
2526 && (GET_MODE_SIZE (GET_MODE (x))
2527 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
2528 return GENERAL_REGS;
2530 if (in && INTEGRAL_MODE_P (mode)
2531 && ! (memory_operand (x, mode) || x == const0_rtx))
2532 return GENERAL_REGS;
2538 /* Subfunction of the following function. Update the flags of any MEM
2539 found in part of X. */
2542 alpha_set_memflags_1 (x, in_struct_p, volatile_p, unchanging_p)
2544 int in_struct_p, volatile_p, unchanging_p;
2548 switch (GET_CODE (x))
2554 for (i = XVECLEN (x, 0) - 1; i >= 0; i--)
2555 alpha_set_memflags_1 (XVECEXP (x, 0, i), in_struct_p, volatile_p,
2560 alpha_set_memflags_1 (PATTERN (x), in_struct_p, volatile_p,
2565 alpha_set_memflags_1 (SET_DEST (x), in_struct_p, volatile_p,
2567 alpha_set_memflags_1 (SET_SRC (x), in_struct_p, volatile_p,
2572 MEM_IN_STRUCT_P (x) = in_struct_p;
2573 MEM_VOLATILE_P (x) = volatile_p;
2574 RTX_UNCHANGING_P (x) = unchanging_p;
2575 /* Sadly, we cannot use alias sets because the extra aliasing
2576 produced by the AND interferes. Given that two-byte quantities
2577 are the only thing we would be able to differentiate anyway,
2578 there does not seem to be any point in convoluting the early
2579 out of the alias check. */
2587 /* Given INSN, which is an INSN list or the PATTERN of a single insn
2588 generated to perform a memory operation, look for any MEMs in either
2589 a SET_DEST or a SET_SRC and copy the in-struct, unchanging, and
2590 volatile flags from REF into each of the MEMs found. If REF is not
2591 a MEM, don't do anything. */
2594 alpha_set_memflags (insn, ref)
2598 int in_struct_p, volatile_p, unchanging_p;
2600 if (GET_CODE (ref) != MEM)
2603 in_struct_p = MEM_IN_STRUCT_P (ref);
2604 volatile_p = MEM_VOLATILE_P (ref);
2605 unchanging_p = RTX_UNCHANGING_P (ref);
2607 /* This is only called from alpha.md, after having had something
2608 generated from one of the insn patterns. So if everything is
2609 zero, the pattern is already up-to-date. */
2610 if (! in_struct_p && ! volatile_p && ! unchanging_p)
2613 alpha_set_memflags_1 (insn, in_struct_p, volatile_p, unchanging_p);
2616 /* Try to output insns to set TARGET equal to the constant C if it can be
2617 done in less than N insns. Do all computations in MODE. Returns the place
2618 where the output has been placed if it can be done and the insns have been
2619 emitted. If it would take more than N insns, zero is returned and no
2620 insns and emitted. */
2623 alpha_emit_set_const (target, mode, c, n)
2625 enum machine_mode mode;
2630 rtx orig_target = target;
2633 /* If we can't make any pseudos, TARGET is an SImode hard register, we
2634 can't load this constant in one insn, do this in DImode. */
2635 if (no_new_pseudos && mode == SImode
2636 && GET_CODE (target) == REG && REGNO (target) < FIRST_PSEUDO_REGISTER
2637 && (result = alpha_emit_set_const_1 (target, mode, c, 1)) == 0)
2639 target = gen_lowpart (DImode, target);
2643 /* Try 1 insn, then 2, then up to N. */
2644 for (i = 1; i <= n; i++)
2646 result = alpha_emit_set_const_1 (target, mode, c, i);
2649 rtx insn = get_last_insn ();
2650 rtx set = single_set (insn);
2651 if (! CONSTANT_P (SET_SRC (set)))
2652 set_unique_reg_note (get_last_insn (), REG_EQUAL, GEN_INT (c));
2657 /* Allow for the case where we changed the mode of TARGET. */
2658 if (result == target)
2659 result = orig_target;
2664 /* Internal routine for the above to check for N or below insns. */
2667 alpha_emit_set_const_1 (target, mode, c, n)
2669 enum machine_mode mode;
2675 /* Use a pseudo if highly optimizing and still generating RTL. */
2677 = (flag_expensive_optimizations && !no_new_pseudos ? 0 : target);
2680 /* If this is a sign-extended 32-bit constant, we can do this in at most
2681 three insns, so do it if we have enough insns left. We always have
2682 a sign-extended 32-bit constant when compiling on a narrow machine. */
2684 if (HOST_BITS_PER_WIDE_INT != 64
2685 || c >> 31 == -1 || c >> 31 == 0)
2687 HOST_WIDE_INT low = ((c & 0xffff) ^ 0x8000) - 0x8000;
2688 HOST_WIDE_INT tmp1 = c - low;
2689 HOST_WIDE_INT high = (((tmp1 >> 16) & 0xffff) ^ 0x8000) - 0x8000;
2690 HOST_WIDE_INT extra = 0;
2692 /* If HIGH will be interpreted as negative but the constant is
2693 positive, we must adjust it to do two ldha insns. */
2695 if ((high & 0x8000) != 0 && c >= 0)
2699 high = ((tmp1 >> 16) & 0xffff) - 2 * ((tmp1 >> 16) & 0x8000);
2702 if (c == low || (low == 0 && extra == 0))
2704 /* We used to use copy_to_suggested_reg (GEN_INT (c), target, mode)
2705 but that meant that we can't handle INT_MIN on 32-bit machines
2706 (like NT/Alpha), because we recurse indefinitely through
2707 emit_move_insn to gen_movdi. So instead, since we know exactly
2708 what we want, create it explicitly. */
2711 target = gen_reg_rtx (mode);
2712 emit_insn (gen_rtx_SET (VOIDmode, target, GEN_INT (c)));
2715 else if (n >= 2 + (extra != 0))
2717 temp = copy_to_suggested_reg (GEN_INT (high << 16), subtarget, mode);
2719 /* As of 2002-02-23, addsi3 is only available when not optimizing.
2720 This means that if we go through expand_binop, we'll try to
2721 generate extensions, etc, which will require new pseudos, which
2722 will fail during some split phases. The SImode add patterns
2723 still exist, but are not named. So build the insns by hand. */
2728 subtarget = gen_reg_rtx (mode);
2729 insn = gen_rtx_PLUS (mode, temp, GEN_INT (extra << 16));
2730 insn = gen_rtx_SET (VOIDmode, subtarget, insn);
2736 target = gen_reg_rtx (mode);
2737 insn = gen_rtx_PLUS (mode, temp, GEN_INT (low));
2738 insn = gen_rtx_SET (VOIDmode, target, insn);
2744 /* If we couldn't do it that way, try some other methods. But if we have
2745 no instructions left, don't bother. Likewise, if this is SImode and
2746 we can't make pseudos, we can't do anything since the expand_binop
2747 and expand_unop calls will widen and try to make pseudos. */
2749 if (n == 1 || (mode == SImode && no_new_pseudos))
2752 /* Next, see if we can load a related constant and then shift and possibly
2753 negate it to get the constant we want. Try this once each increasing
2754 numbers of insns. */
2756 for (i = 1; i < n; i++)
2758 /* First, see if minus some low bits, we've an easy load of
2761 new = ((c & 0xffff) ^ 0x8000) - 0x8000;
2763 && (temp = alpha_emit_set_const (subtarget, mode, c - new, i)) != 0)
2764 return expand_binop (mode, add_optab, temp, GEN_INT (new),
2765 target, 0, OPTAB_WIDEN);
2767 /* Next try complementing. */
2768 if ((temp = alpha_emit_set_const (subtarget, mode, ~ c, i)) != 0)
2769 return expand_unop (mode, one_cmpl_optab, temp, target, 0);
2771 /* Next try to form a constant and do a left shift. We can do this
2772 if some low-order bits are zero; the exact_log2 call below tells
2773 us that information. The bits we are shifting out could be any
2774 value, but here we'll just try the 0- and sign-extended forms of
2775 the constant. To try to increase the chance of having the same
2776 constant in more than one insn, start at the highest number of
2777 bits to shift, but try all possibilities in case a ZAPNOT will
2780 if ((bits = exact_log2 (c & - c)) > 0)
2781 for (; bits > 0; bits--)
2782 if ((temp = (alpha_emit_set_const
2783 (subtarget, mode, c >> bits, i))) != 0
2784 || ((temp = (alpha_emit_set_const
2786 ((unsigned HOST_WIDE_INT) c) >> bits, i)))
2788 return expand_binop (mode, ashl_optab, temp, GEN_INT (bits),
2789 target, 0, OPTAB_WIDEN);
2791 /* Now try high-order zero bits. Here we try the shifted-in bits as
2792 all zero and all ones. Be careful to avoid shifting outside the
2793 mode and to avoid shifting outside the host wide int size. */
2794 /* On narrow hosts, don't shift a 1 into the high bit, since we'll
2795 confuse the recursive call and set all of the high 32 bits. */
2797 if ((bits = (MIN (HOST_BITS_PER_WIDE_INT, GET_MODE_SIZE (mode) * 8)
2798 - floor_log2 (c) - 1 - (HOST_BITS_PER_WIDE_INT < 64))) > 0)
2799 for (; bits > 0; bits--)
2800 if ((temp = alpha_emit_set_const (subtarget, mode,
2802 || ((temp = (alpha_emit_set_const
2804 ((c << bits) | (((HOST_WIDE_INT) 1 << bits) - 1)),
2807 return expand_binop (mode, lshr_optab, temp, GEN_INT (bits),
2808 target, 1, OPTAB_WIDEN);
2810 /* Now try high-order 1 bits. We get that with a sign-extension.
2811 But one bit isn't enough here. Be careful to avoid shifting outside
2812 the mode and to avoid shifting outside the host wide int size. */
2814 if ((bits = (MIN (HOST_BITS_PER_WIDE_INT, GET_MODE_SIZE (mode) * 8)
2815 - floor_log2 (~ c) - 2)) > 0)
2816 for (; bits > 0; bits--)
2817 if ((temp = alpha_emit_set_const (subtarget, mode,
2819 || ((temp = (alpha_emit_set_const
2821 ((c << bits) | (((HOST_WIDE_INT) 1 << bits) - 1)),
2824 return expand_binop (mode, ashr_optab, temp, GEN_INT (bits),
2825 target, 0, OPTAB_WIDEN);
2828 #if HOST_BITS_PER_WIDE_INT == 64
2829 /* Finally, see if can load a value into the target that is the same as the
2830 constant except that all bytes that are 0 are changed to be 0xff. If we
2831 can, then we can do a ZAPNOT to obtain the desired constant. */
2834 for (i = 0; i < 64; i += 8)
2835 if ((new & ((HOST_WIDE_INT) 0xff << i)) == 0)
2836 new |= (HOST_WIDE_INT) 0xff << i;
2838 /* We are only called for SImode and DImode. If this is SImode, ensure that
2839 we are sign extended to a full word. */
2842 new = ((new & 0xffffffff) ^ 0x80000000) - 0x80000000;
2844 if (new != c && new != -1
2845 && (temp = alpha_emit_set_const (subtarget, mode, new, n - 1)) != 0)
2846 return expand_binop (mode, and_optab, temp, GEN_INT (c | ~ new),
2847 target, 0, OPTAB_WIDEN);
2853 /* Having failed to find a 3 insn sequence in alpha_emit_set_const,
2854 fall back to a straight forward decomposition. We do this to avoid
2855 exponential run times encountered when looking for longer sequences
2856 with alpha_emit_set_const. */
2859 alpha_emit_set_long_const (target, c1, c2)
2861 HOST_WIDE_INT c1, c2;
2863 HOST_WIDE_INT d1, d2, d3, d4;
2865 /* Decompose the entire word */
2866 #if HOST_BITS_PER_WIDE_INT >= 64
2867 if (c2 != -(c1 < 0))
2869 d1 = ((c1 & 0xffff) ^ 0x8000) - 0x8000;
2871 d2 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000;
2872 c1 = (c1 - d2) >> 32;
2873 d3 = ((c1 & 0xffff) ^ 0x8000) - 0x8000;
2875 d4 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000;
2879 d1 = ((c1 & 0xffff) ^ 0x8000) - 0x8000;
2881 d2 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000;
2885 d3 = ((c2 & 0xffff) ^ 0x8000) - 0x8000;
2887 d4 = ((c2 & 0xffffffff) ^ 0x80000000) - 0x80000000;
2892 /* Construct the high word */
2895 emit_move_insn (target, GEN_INT (d4));
2897 emit_move_insn (target, gen_rtx_PLUS (DImode, target, GEN_INT (d3)));
2900 emit_move_insn (target, GEN_INT (d3));
2902 /* Shift it into place */
2903 emit_move_insn (target, gen_rtx_ASHIFT (DImode, target, GEN_INT (32)));
2905 /* Add in the low bits. */
2907 emit_move_insn (target, gen_rtx_PLUS (DImode, target, GEN_INT (d2)));
2909 emit_move_insn (target, gen_rtx_PLUS (DImode, target, GEN_INT (d1)));
2914 /* Expand a move instruction; return true if all work is done.
2915 We don't handle non-bwx subword loads here. */
2918 alpha_expand_mov (mode, operands)
2919 enum machine_mode mode;
2922 /* If the output is not a register, the input must be. */
2923 if (GET_CODE (operands[0]) == MEM
2924 && ! reg_or_0_operand (operands[1], mode))
2925 operands[1] = force_reg (mode, operands[1]);
2927 /* Allow legitimize_address to perform some simplifications. */
2928 if (mode == Pmode && symbolic_operand (operands[1], mode))
2932 /* With RTL inlining, at -O3, rtl is generated, stored, then actually
2933 compiled at the end of compilation. In the meantime, someone can
2934 re-encode-section-info on some symbol changing it e.g. from global
2935 to local-not-small. If this happens, we'd have emitted a plain
2936 load rather than a high+losum load and not recognize the insn.
2938 So if rtl inlining is in effect, we delay the global/not-global
2939 decision until rest_of_compilation by wrapping it in an
2941 if (TARGET_EXPLICIT_RELOCS && flag_inline_functions
2942 && rtx_equal_function_value_matters
2943 && global_symbolic_operand (operands[1], mode))
2945 emit_insn (gen_movdi_er_maybe_g (operands[0], operands[1]));
2949 tmp = alpha_legitimize_address (operands[1], operands[0], mode);
2952 if (tmp == operands[0])
2959 /* Early out for non-constants and valid constants. */
2960 if (! CONSTANT_P (operands[1]) || input_operand (operands[1], mode))
2963 /* Split large integers. */
2964 if (GET_CODE (operands[1]) == CONST_INT
2965 || GET_CODE (operands[1]) == CONST_DOUBLE)
2967 HOST_WIDE_INT i0, i1;
2968 rtx temp = NULL_RTX;
2970 if (GET_CODE (operands[1]) == CONST_INT)
2972 i0 = INTVAL (operands[1]);
2975 else if (HOST_BITS_PER_WIDE_INT >= 64)
2977 i0 = CONST_DOUBLE_LOW (operands[1]);
2982 i0 = CONST_DOUBLE_LOW (operands[1]);
2983 i1 = CONST_DOUBLE_HIGH (operands[1]);
2986 if (HOST_BITS_PER_WIDE_INT >= 64 || i1 == -(i0 < 0))
2987 temp = alpha_emit_set_const (operands[0], mode, i0, 3);
2989 if (!temp && TARGET_BUILD_CONSTANTS)
2990 temp = alpha_emit_set_long_const (operands[0], i0, i1);
2994 if (rtx_equal_p (operands[0], temp))
3001 /* Otherwise we've nothing left but to drop the thing to memory. */
3002 operands[1] = force_const_mem (DImode, operands[1]);
3003 if (reload_in_progress)
3005 emit_move_insn (operands[0], XEXP (operands[1], 0));
3006 operands[1] = copy_rtx (operands[1]);
3007 XEXP (operands[1], 0) = operands[0];
3010 operands[1] = validize_mem (operands[1]);
3014 /* Expand a non-bwx QImode or HImode move instruction;
3015 return true if all work is done. */
3018 alpha_expand_mov_nobwx (mode, operands)
3019 enum machine_mode mode;
3022 /* If the output is not a register, the input must be. */
3023 if (GET_CODE (operands[0]) == MEM)
3024 operands[1] = force_reg (mode, operands[1]);
3026 /* Handle four memory cases, unaligned and aligned for either the input
3027 or the output. The only case where we can be called during reload is
3028 for aligned loads; all other cases require temporaries. */
3030 if (GET_CODE (operands[1]) == MEM
3031 || (GET_CODE (operands[1]) == SUBREG
3032 && GET_CODE (SUBREG_REG (operands[1])) == MEM)
3033 || (reload_in_progress && GET_CODE (operands[1]) == REG
3034 && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
3035 || (reload_in_progress && GET_CODE (operands[1]) == SUBREG
3036 && GET_CODE (SUBREG_REG (operands[1])) == REG
3037 && REGNO (SUBREG_REG (operands[1])) >= FIRST_PSEUDO_REGISTER))
3039 if (aligned_memory_operand (operands[1], mode))
3041 if (reload_in_progress)
3043 emit_insn ((mode == QImode
3044 ? gen_reload_inqi_help
3045 : gen_reload_inhi_help)
3046 (operands[0], operands[1],
3047 gen_rtx_REG (SImode, REGNO (operands[0]))));
3051 rtx aligned_mem, bitnum;
3052 rtx scratch = gen_reg_rtx (SImode);
3054 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
3056 emit_insn ((mode == QImode
3057 ? gen_aligned_loadqi
3058 : gen_aligned_loadhi)
3059 (operands[0], aligned_mem, bitnum, scratch));
3064 /* Don't pass these as parameters since that makes the generated
3065 code depend on parameter evaluation order which will cause
3066 bootstrap failures. */
3068 rtx temp1 = gen_reg_rtx (DImode);
3069 rtx temp2 = gen_reg_rtx (DImode);
3070 rtx seq = ((mode == QImode
3071 ? gen_unaligned_loadqi
3072 : gen_unaligned_loadhi)
3073 (operands[0], get_unaligned_address (operands[1], 0),
3076 alpha_set_memflags (seq, operands[1]);
3082 if (GET_CODE (operands[0]) == MEM
3083 || (GET_CODE (operands[0]) == SUBREG
3084 && GET_CODE (SUBREG_REG (operands[0])) == MEM)
3085 || (reload_in_progress && GET_CODE (operands[0]) == REG
3086 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)
3087 || (reload_in_progress && GET_CODE (operands[0]) == SUBREG
3088 && GET_CODE (SUBREG_REG (operands[0])) == REG
3089 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))
3091 if (aligned_memory_operand (operands[0], mode))
3093 rtx aligned_mem, bitnum;
3094 rtx temp1 = gen_reg_rtx (SImode);
3095 rtx temp2 = gen_reg_rtx (SImode);
3097 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
3099 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
3104 rtx temp1 = gen_reg_rtx (DImode);
3105 rtx temp2 = gen_reg_rtx (DImode);
3106 rtx temp3 = gen_reg_rtx (DImode);
3107 rtx seq = ((mode == QImode
3108 ? gen_unaligned_storeqi
3109 : gen_unaligned_storehi)
3110 (get_unaligned_address (operands[0], 0),
3111 operands[1], temp1, temp2, temp3));
3113 alpha_set_memflags (seq, operands[0]);
3122 /* Generate an unsigned DImode to FP conversion. This is the same code
3123 optabs would emit if we didn't have TFmode patterns.
3125 For SFmode, this is the only construction I've found that can pass
3126 gcc.c-torture/execute/ieee/rbug.c. No scenario that uses DFmode
3127 intermediates will work, because you'll get intermediate rounding
3128 that ruins the end result. Some of this could be fixed by turning
3129 on round-to-positive-infinity, but that requires diddling the fpsr,
3130 which kills performance. I tried turning this around and converting
3131 to a negative number, so that I could turn on /m, but either I did
3132 it wrong or there's something else cause I wound up with the exact
3133 same single-bit error. There is a branch-less form of this same code:
3144 fcmoveq $f10,$f11,$f0
3146 I'm not using it because it's the same number of instructions as
3147 this branch-full form, and it has more serialized long latency
3148 instructions on the critical path.
3150 For DFmode, we can avoid rounding errors by breaking up the word
3151 into two pieces, converting them separately, and adding them back:
3153 LC0: .long 0,0x5f800000
3158 cpyse $f11,$f31,$f10
3159 cpyse $f31,$f11,$f11
3167 This doesn't seem to be a clear-cut win over the optabs form.
3168 It probably all depends on the distribution of numbers being
3169 converted -- in the optabs form, all but high-bit-set has a
3170 much lower minimum execution time. */
3173 alpha_emit_floatuns (operands)
3176 rtx neglab, donelab, i0, i1, f0, in, out;
3177 enum machine_mode mode;
3180 in = force_reg (DImode, operands[1]);
3181 mode = GET_MODE (out);
3182 neglab = gen_label_rtx ();
3183 donelab = gen_label_rtx ();
3184 i0 = gen_reg_rtx (DImode);
3185 i1 = gen_reg_rtx (DImode);
3186 f0 = gen_reg_rtx (mode);
3188 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, DImode, 0, neglab);
3190 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_FLOAT (mode, in)));
3191 emit_jump_insn (gen_jump (donelab));
3194 emit_label (neglab);
3196 emit_insn (gen_lshrdi3 (i0, in, const1_rtx));
3197 emit_insn (gen_anddi3 (i1, in, const1_rtx));
3198 emit_insn (gen_iordi3 (i0, i0, i1));
3199 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_FLOAT (mode, i0)));
3200 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
3202 emit_label (donelab);
3205 /* Generate the comparison for a conditional branch. */
3208 alpha_emit_conditional_branch (code)
3211 enum rtx_code cmp_code, branch_code;
3212 enum machine_mode cmp_mode, branch_mode = VOIDmode;
3213 rtx op0 = alpha_compare.op0, op1 = alpha_compare.op1;
3216 if (alpha_compare.fp_p && GET_MODE (op0) == TFmode)
3218 if (! TARGET_HAS_XFLOATING_LIBS)
3221 /* X_floating library comparison functions return
3225 Convert the compare against the raw return value. */
3247 op0 = alpha_emit_xfloating_compare (cmp_code, op0, op1);
3249 alpha_compare.fp_p = 0;
3252 /* The general case: fold the comparison code to the types of compares
3253 that we have, choosing the branch as necessary. */
3256 case EQ: case LE: case LT: case LEU: case LTU:
3258 /* We have these compares: */
3259 cmp_code = code, branch_code = NE;
3264 /* These must be reversed. */
3265 cmp_code = reverse_condition (code), branch_code = EQ;
3268 case GE: case GT: case GEU: case GTU:
3269 /* For FP, we swap them, for INT, we reverse them. */
3270 if (alpha_compare.fp_p)
3272 cmp_code = swap_condition (code);
3274 tem = op0, op0 = op1, op1 = tem;
3278 cmp_code = reverse_condition (code);
3287 if (alpha_compare.fp_p)
3290 if (flag_unsafe_math_optimizations)
3292 /* When we are not as concerned about non-finite values, and we
3293 are comparing against zero, we can branch directly. */
3294 if (op1 == CONST0_RTX (DFmode))
3295 cmp_code = NIL, branch_code = code;
3296 else if (op0 == CONST0_RTX (DFmode))
3298 /* Undo the swap we probably did just above. */
3299 tem = op0, op0 = op1, op1 = tem;
3300 branch_code = swap_condition (cmp_code);
3306 /* ??? We mark the branch mode to be CCmode to prevent the
3307 compare and branch from being combined, since the compare
3308 insn follows IEEE rules that the branch does not. */
3309 branch_mode = CCmode;
3316 /* The following optimizations are only for signed compares. */
3317 if (code != LEU && code != LTU && code != GEU && code != GTU)
3319 /* Whee. Compare and branch against 0 directly. */
3320 if (op1 == const0_rtx)
3321 cmp_code = NIL, branch_code = code;
3323 /* We want to use cmpcc/bcc when we can, since there is a zero delay
3324 bypass between logicals and br/cmov on EV5. But we don't want to
3325 force valid immediate constants into registers needlessly. */
3326 else if (GET_CODE (op1) == CONST_INT)
3328 HOST_WIDE_INT v = INTVAL (op1), n = -v;
3330 if (! CONST_OK_FOR_LETTER_P (v, 'I')
3331 && (CONST_OK_FOR_LETTER_P (n, 'K')
3332 || CONST_OK_FOR_LETTER_P (n, 'L')))
3334 cmp_code = PLUS, branch_code = code;
3340 if (!reg_or_0_operand (op0, DImode))
3341 op0 = force_reg (DImode, op0);
3342 if (cmp_code != PLUS && !reg_or_8bit_operand (op1, DImode))
3343 op1 = force_reg (DImode, op1);
3346 /* Emit an initial compare instruction, if necessary. */
3348 if (cmp_code != NIL)
3350 tem = gen_reg_rtx (cmp_mode);
3351 emit_move_insn (tem, gen_rtx_fmt_ee (cmp_code, cmp_mode, op0, op1));
3354 /* Zero the operands. */
3355 memset (&alpha_compare, 0, sizeof (alpha_compare));
3357 /* Return the branch comparison. */
3358 return gen_rtx_fmt_ee (branch_code, branch_mode, tem, CONST0_RTX (cmp_mode));
3361 /* Certain simplifications can be done to make invalid setcc operations
3362 valid. Return the final comparison, or NULL if we can't work. */
3365 alpha_emit_setcc (code)
3368 enum rtx_code cmp_code;
3369 rtx op0 = alpha_compare.op0, op1 = alpha_compare.op1;
3370 int fp_p = alpha_compare.fp_p;
3373 /* Zero the operands. */
3374 memset (&alpha_compare, 0, sizeof (alpha_compare));
3376 if (fp_p && GET_MODE (op0) == TFmode)
3378 if (! TARGET_HAS_XFLOATING_LIBS)
3381 /* X_floating library comparison functions return
3385 Convert the compare against the raw return value. */
3387 if (code == UNORDERED || code == ORDERED)
3392 op0 = alpha_emit_xfloating_compare (cmp_code, op0, op1);
3396 if (code == UNORDERED)
3398 else if (code == ORDERED)
3404 if (fp_p && !TARGET_FIX)
3407 /* The general case: fold the comparison code to the types of compares
3408 that we have, choosing the branch as necessary. */
3413 case EQ: case LE: case LT: case LEU: case LTU:
3415 /* We have these compares. */
3417 cmp_code = code, code = NE;
3421 if (!fp_p && op1 == const0_rtx)
3426 cmp_code = reverse_condition (code);
3430 case GE: case GT: case GEU: case GTU:
3431 /* These normally need swapping, but for integer zero we have
3432 special patterns that recognize swapped operands. */
3433 if (!fp_p && op1 == const0_rtx)
3435 code = swap_condition (code);
3437 cmp_code = code, code = NE;
3438 tmp = op0, op0 = op1, op1 = tmp;
3447 if (!register_operand (op0, DImode))
3448 op0 = force_reg (DImode, op0);
3449 if (!reg_or_8bit_operand (op1, DImode))
3450 op1 = force_reg (DImode, op1);
3453 /* Emit an initial compare instruction, if necessary. */
3454 if (cmp_code != NIL)
3456 enum machine_mode mode = fp_p ? DFmode : DImode;
3458 tmp = gen_reg_rtx (mode);
3459 emit_insn (gen_rtx_SET (VOIDmode, tmp,
3460 gen_rtx_fmt_ee (cmp_code, mode, op0, op1)));
3462 op0 = fp_p ? gen_lowpart (DImode, tmp) : tmp;
3466 /* Return the setcc comparison. */
3467 return gen_rtx_fmt_ee (code, DImode, op0, op1);
3471 /* Rewrite a comparison against zero CMP of the form
3472 (CODE (cc0) (const_int 0)) so it can be written validly in
3473 a conditional move (if_then_else CMP ...).
3474 If both of the operands that set cc0 are nonzero we must emit
3475 an insn to perform the compare (it can't be done within
3476 the conditional move). */
3478 alpha_emit_conditional_move (cmp, mode)
3480 enum machine_mode mode;
3482 enum rtx_code code = GET_CODE (cmp);
3483 enum rtx_code cmov_code = NE;
3484 rtx op0 = alpha_compare.op0;
3485 rtx op1 = alpha_compare.op1;
3486 int fp_p = alpha_compare.fp_p;
3487 enum machine_mode cmp_mode
3488 = (GET_MODE (op0) == VOIDmode ? DImode : GET_MODE (op0));
3489 enum machine_mode cmp_op_mode = fp_p ? DFmode : DImode;
3490 enum machine_mode cmov_mode = VOIDmode;
3491 int local_fast_math = flag_unsafe_math_optimizations;
3494 /* Zero the operands. */
3495 memset (&alpha_compare, 0, sizeof (alpha_compare));
3497 if (fp_p != FLOAT_MODE_P (mode))
3499 enum rtx_code cmp_code;
3504 /* If we have fp<->int register move instructions, do a cmov by
3505 performing the comparison in fp registers, and move the
3506 zero/nonzero value to integer registers, where we can then
3507 use a normal cmov, or vice-versa. */
3511 case EQ: case LE: case LT: case LEU: case LTU:
3512 /* We have these compares. */
3513 cmp_code = code, code = NE;
3517 /* This must be reversed. */
3518 cmp_code = EQ, code = EQ;
3521 case GE: case GT: case GEU: case GTU:
3522 /* These normally need swapping, but for integer zero we have
3523 special patterns that recognize swapped operands. */
3524 if (!fp_p && op1 == const0_rtx)
3525 cmp_code = code, code = NE;
3528 cmp_code = swap_condition (code);
3530 tem = op0, op0 = op1, op1 = tem;
3538 tem = gen_reg_rtx (cmp_op_mode);
3539 emit_insn (gen_rtx_SET (VOIDmode, tem,
3540 gen_rtx_fmt_ee (cmp_code, cmp_op_mode,
3543 cmp_mode = cmp_op_mode = fp_p ? DImode : DFmode;
3544 op0 = gen_lowpart (cmp_op_mode, tem);
3545 op1 = CONST0_RTX (cmp_op_mode);
3547 local_fast_math = 1;
3550 /* We may be able to use a conditional move directly.
3551 This avoids emitting spurious compares. */
3552 if (signed_comparison_operator (cmp, VOIDmode)
3553 && (!fp_p || local_fast_math)
3554 && (op0 == CONST0_RTX (cmp_mode) || op1 == CONST0_RTX (cmp_mode)))
3555 return gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
3557 /* We can't put the comparison inside the conditional move;
3558 emit a compare instruction and put that inside the
3559 conditional move. Make sure we emit only comparisons we have;
3560 swap or reverse as necessary. */
3567 case EQ: case LE: case LT: case LEU: case LTU:
3568 /* We have these compares: */
3572 /* This must be reversed. */
3573 code = reverse_condition (code);
3577 case GE: case GT: case GEU: case GTU:
3578 /* These must be swapped. */
3579 if (op1 != CONST0_RTX (cmp_mode))
3581 code = swap_condition (code);
3582 tem = op0, op0 = op1, op1 = tem;
3592 if (!reg_or_0_operand (op0, DImode))
3593 op0 = force_reg (DImode, op0);
3594 if (!reg_or_8bit_operand (op1, DImode))
3595 op1 = force_reg (DImode, op1);
3598 /* ??? We mark the branch mode to be CCmode to prevent the compare
3599 and cmov from being combined, since the compare insn follows IEEE
3600 rules that the cmov does not. */
3601 if (fp_p && !local_fast_math)
3604 tem = gen_reg_rtx (cmp_op_mode);
3605 emit_move_insn (tem, gen_rtx_fmt_ee (code, cmp_op_mode, op0, op1));
3606 return gen_rtx_fmt_ee (cmov_code, cmov_mode, tem, CONST0_RTX (cmp_op_mode));
3609 /* Simplify a conditional move of two constants into a setcc with
3610 arithmetic. This is done with a splitter since combine would
3611 just undo the work if done during code generation. It also catches
3612 cases we wouldn't have before cse. */
3615 alpha_split_conditional_move (code, dest, cond, t_rtx, f_rtx)
3617 rtx dest, cond, t_rtx, f_rtx;
3619 HOST_WIDE_INT t, f, diff;
3620 enum machine_mode mode;
3621 rtx target, subtarget, tmp;
3623 mode = GET_MODE (dest);
3628 if (((code == NE || code == EQ) && diff < 0)
3629 || (code == GE || code == GT))
3631 code = reverse_condition (code);
3632 diff = t, t = f, f = diff;
3636 subtarget = target = dest;
3639 target = gen_lowpart (DImode, dest);
3640 if (! no_new_pseudos)
3641 subtarget = gen_reg_rtx (DImode);
3645 /* Below, we must be careful to use copy_rtx on target and subtarget
3646 in intermediate insns, as they may be a subreg rtx, which may not
3649 if (f == 0 && exact_log2 (diff) > 0
3650 /* On EV6, we've got enough shifters to make non-arithmatic shifts
3651 viable over a longer latency cmove. On EV5, the E0 slot is a
3652 scarce resource, and on EV4 shift has the same latency as a cmove. */
3653 && (diff <= 8 || alpha_cpu == PROCESSOR_EV6))
3655 tmp = gen_rtx_fmt_ee (code, DImode, cond, const0_rtx);
3656 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (subtarget), tmp));
3658 tmp = gen_rtx_ASHIFT (DImode, copy_rtx (subtarget),
3659 GEN_INT (exact_log2 (t)));
3660 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
3662 else if (f == 0 && t == -1)
3664 tmp = gen_rtx_fmt_ee (code, DImode, cond, const0_rtx);
3665 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (subtarget), tmp));
3667 emit_insn (gen_negdi2 (target, copy_rtx (subtarget)));
3669 else if (diff == 1 || diff == 4 || diff == 8)
3673 tmp = gen_rtx_fmt_ee (code, DImode, cond, const0_rtx);
3674 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (subtarget), tmp));
3677 emit_insn (gen_adddi3 (target, copy_rtx (subtarget), GEN_INT (f)));
3680 add_op = GEN_INT (f);
3681 if (sext_add_operand (add_op, mode))
3683 tmp = gen_rtx_MULT (DImode, copy_rtx (subtarget),
3685 tmp = gen_rtx_PLUS (DImode, tmp, add_op);
3686 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
3698 /* Look up the function X_floating library function name for the
3702 alpha_lookup_xfloating_lib_func (code)
3707 const enum rtx_code code;
3708 const char *const func;
3711 static const struct xfloating_op vms_xfloating_ops[] =
3713 { PLUS, "OTS$ADD_X" },
3714 { MINUS, "OTS$SUB_X" },
3715 { MULT, "OTS$MUL_X" },
3716 { DIV, "OTS$DIV_X" },
3717 { EQ, "OTS$EQL_X" },
3718 { NE, "OTS$NEQ_X" },
3719 { LT, "OTS$LSS_X" },
3720 { LE, "OTS$LEQ_X" },
3721 { GT, "OTS$GTR_X" },
3722 { GE, "OTS$GEQ_X" },
3723 { FIX, "OTS$CVTXQ" },
3724 { FLOAT, "OTS$CVTQX" },
3725 { UNSIGNED_FLOAT, "OTS$CVTQUX" },
3726 { FLOAT_EXTEND, "OTS$CVT_FLOAT_T_X" },
3727 { FLOAT_TRUNCATE, "OTS$CVT_FLOAT_X_T" },
3730 static const struct xfloating_op osf_xfloating_ops[] =
3732 { PLUS, "_OtsAddX" },
3733 { MINUS, "_OtsSubX" },
3734 { MULT, "_OtsMulX" },
3735 { DIV, "_OtsDivX" },
3742 { FIX, "_OtsCvtXQ" },
3743 { FLOAT, "_OtsCvtQX" },
3744 { UNSIGNED_FLOAT, "_OtsCvtQUX" },
3745 { FLOAT_EXTEND, "_OtsConvertFloatTX" },
3746 { FLOAT_TRUNCATE, "_OtsConvertFloatXT" },
3749 const struct xfloating_op *ops;
3750 const long n = ARRAY_SIZE (osf_xfloating_ops);
3753 /* How irritating. Nothing to key off for the table. Hardcode
3754 knowledge of the G_floating routines. */
3755 if (TARGET_FLOAT_VAX)
3757 if (TARGET_ABI_OPEN_VMS)
3759 if (code == FLOAT_EXTEND)
3760 return "OTS$CVT_FLOAT_G_X";
3761 if (code == FLOAT_TRUNCATE)
3762 return "OTS$CVT_FLOAT_X_G";
3766 if (code == FLOAT_EXTEND)
3767 return "_OtsConvertFloatGX";
3768 if (code == FLOAT_TRUNCATE)
3769 return "_OtsConvertFloatXG";
3773 if (TARGET_ABI_OPEN_VMS)
3774 ops = vms_xfloating_ops;
3776 ops = osf_xfloating_ops;
3778 for (i = 0; i < n; ++i)
3779 if (ops[i].code == code)
3785 /* Most X_floating operations take the rounding mode as an argument.
3786 Compute that here. */
3789 alpha_compute_xfloating_mode_arg (code, round)
3791 enum alpha_fp_rounding_mode round;
3797 case ALPHA_FPRM_NORM:
3800 case ALPHA_FPRM_MINF:
3803 case ALPHA_FPRM_CHOP:
3806 case ALPHA_FPRM_DYN:
3812 /* XXX For reference, round to +inf is mode = 3. */
3815 if (code == FLOAT_TRUNCATE && alpha_fptm == ALPHA_FPTM_N)
3821 /* Emit an X_floating library function call.
3823 Note that these functions do not follow normal calling conventions:
3824 TFmode arguments are passed in two integer registers (as opposed to
3825 indirect); TFmode return values appear in R16+R17.
3827 FUNC is the function name to call.
3828 TARGET is where the output belongs.
3829 OPERANDS are the inputs.
3830 NOPERANDS is the count of inputs.
3831 EQUIV is the expression equivalent for the function.
3835 alpha_emit_xfloating_libcall (func, target, operands, noperands, equiv)
3842 rtx usage = NULL_RTX, tmp, reg;
3847 for (i = 0; i < noperands; ++i)
3849 switch (GET_MODE (operands[i]))
3852 reg = gen_rtx_REG (TFmode, regno);
3857 reg = gen_rtx_REG (DFmode, regno + 32);
3862 if (GET_CODE (operands[i]) != CONST_INT)
3866 reg = gen_rtx_REG (DImode, regno);
3874 emit_move_insn (reg, operands[i]);
3875 usage = alloc_EXPR_LIST (0, gen_rtx_USE (VOIDmode, reg), usage);
3878 switch (GET_MODE (target))
3881 reg = gen_rtx_REG (TFmode, 16);
3884 reg = gen_rtx_REG (DFmode, 32);
3887 reg = gen_rtx_REG (DImode, 0);
3893 tmp = gen_rtx_MEM (QImode, gen_rtx_SYMBOL_REF (Pmode, (char *) func));
3894 tmp = emit_call_insn (GEN_CALL_VALUE (reg, tmp, const0_rtx,
3895 const0_rtx, const0_rtx));
3896 CALL_INSN_FUNCTION_USAGE (tmp) = usage;
3901 emit_libcall_block (tmp, target, reg, equiv);
3904 /* Emit an X_floating library function call for arithmetic (+,-,*,/). */
3907 alpha_emit_xfloating_arith (code, operands)
3913 rtx out_operands[3];
3915 func = alpha_lookup_xfloating_lib_func (code);
3916 mode = alpha_compute_xfloating_mode_arg (code, alpha_fprm);
3918 out_operands[0] = operands[1];
3919 out_operands[1] = operands[2];
3920 out_operands[2] = GEN_INT (mode);
3921 alpha_emit_xfloating_libcall (func, operands[0], out_operands, 3,
3922 gen_rtx_fmt_ee (code, TFmode, operands[1],
3926 /* Emit an X_floating library function call for a comparison. */
3929 alpha_emit_xfloating_compare (code, op0, op1)
3934 rtx out, operands[2];
3936 func = alpha_lookup_xfloating_lib_func (code);
3940 out = gen_reg_rtx (DImode);
3942 /* ??? Strange mode for equiv because what's actually returned
3943 is -1,0,1, not a proper boolean value. */
3944 alpha_emit_xfloating_libcall (func, out, operands, 2,
3945 gen_rtx_fmt_ee (code, CCmode, op0, op1));
3950 /* Emit an X_floating library function call for a conversion. */
3953 alpha_emit_xfloating_cvt (code, operands)
3957 int noperands = 1, mode;
3958 rtx out_operands[2];
3961 func = alpha_lookup_xfloating_lib_func (code);
3963 out_operands[0] = operands[1];
3968 mode = alpha_compute_xfloating_mode_arg (code, ALPHA_FPRM_CHOP);
3969 out_operands[1] = GEN_INT (mode);
3972 case FLOAT_TRUNCATE:
3973 mode = alpha_compute_xfloating_mode_arg (code, alpha_fprm);
3974 out_operands[1] = GEN_INT (mode);
3981 alpha_emit_xfloating_libcall (func, operands[0], out_operands, noperands,
3982 gen_rtx_fmt_e (code, GET_MODE (operands[0]),
3986 /* Split a TFmode OP[1] into DImode OP[2,3] and likewise for
3987 OP[0] into OP[0,1]. Naturally, output operand ordering is
3991 alpha_split_tfmode_pair (operands)
3994 if (GET_CODE (operands[1]) == REG)
3996 operands[3] = gen_rtx_REG (DImode, REGNO (operands[1]) + 1);
3997 operands[2] = gen_rtx_REG (DImode, REGNO (operands[1]));
3999 else if (GET_CODE (operands[1]) == MEM)
4001 operands[3] = adjust_address (operands[1], DImode, 8);
4002 operands[2] = adjust_address (operands[1], DImode, 0);
4004 else if (operands[1] == CONST0_RTX (TFmode))
4005 operands[2] = operands[3] = const0_rtx;
4009 if (GET_CODE (operands[0]) == REG)
4011 operands[1] = gen_rtx_REG (DImode, REGNO (operands[0]) + 1);
4012 operands[0] = gen_rtx_REG (DImode, REGNO (operands[0]));
4014 else if (GET_CODE (operands[0]) == MEM)
4016 operands[1] = adjust_address (operands[0], DImode, 8);
4017 operands[0] = adjust_address (operands[0], DImode, 0);
4023 /* Implement negtf2 or abstf2. Op0 is destination, op1 is source,
4024 op2 is a register containing the sign bit, operation is the
4025 logical operation to be performed. */
4028 alpha_split_tfmode_frobsign (operands, operation)
4030 rtx (*operation) PARAMS ((rtx, rtx, rtx));
4032 rtx high_bit = operands[2];
4036 alpha_split_tfmode_pair (operands);
4038 /* Detect three flavors of operand overlap. */
4040 if (rtx_equal_p (operands[0], operands[2]))
4042 else if (rtx_equal_p (operands[1], operands[2]))
4044 if (rtx_equal_p (operands[0], high_bit))
4051 emit_move_insn (operands[0], operands[2]);
4053 /* ??? If the destination overlaps both source tf and high_bit, then
4054 assume source tf is dead in its entirety and use the other half
4055 for a scratch register. Otherwise "scratch" is just the proper
4056 destination register. */
4057 scratch = operands[move < 2 ? 1 : 3];
4059 emit_insn ((*operation) (scratch, high_bit, operands[3]));
4063 emit_move_insn (operands[0], operands[2]);
4065 emit_move_insn (operands[1], scratch);
4069 /* Use ext[wlq][lh] as the Architecture Handbook describes for extracting
4073 word: ldq_u r1,X(r11) ldq_u r1,X(r11)
4074 ldq_u r2,X+1(r11) ldq_u r2,X+1(r11)
4075 lda r3,X(r11) lda r3,X+2(r11)
4076 extwl r1,r3,r1 extql r1,r3,r1
4077 extwh r2,r3,r2 extqh r2,r3,r2
4078 or r1.r2.r1 or r1,r2,r1
4081 long: ldq_u r1,X(r11) ldq_u r1,X(r11)
4082 ldq_u r2,X+3(r11) ldq_u r2,X+3(r11)
4083 lda r3,X(r11) lda r3,X(r11)
4084 extll r1,r3,r1 extll r1,r3,r1
4085 extlh r2,r3,r2 extlh r2,r3,r2
4086 or r1.r2.r1 addl r1,r2,r1
4088 quad: ldq_u r1,X(r11)
4097 alpha_expand_unaligned_load (tgt, mem, size, ofs, sign)
4099 HOST_WIDE_INT size, ofs;
4102 rtx meml, memh, addr, extl, exth, tmp, mema;
4103 enum machine_mode mode;
4105 meml = gen_reg_rtx (DImode);
4106 memh = gen_reg_rtx (DImode);
4107 addr = gen_reg_rtx (DImode);
4108 extl = gen_reg_rtx (DImode);
4109 exth = gen_reg_rtx (DImode);
4111 mema = XEXP (mem, 0);
4112 if (GET_CODE (mema) == LO_SUM)
4113 mema = force_reg (Pmode, mema);
4115 /* AND addresses cannot be in any alias set, since they may implicitly
4116 alias surrounding code. Ideally we'd have some alias set that
4117 covered all types except those with alignment 8 or higher. */
4119 tmp = change_address (mem, DImode,
4120 gen_rtx_AND (DImode,
4121 plus_constant (mema, ofs),
4123 set_mem_alias_set (tmp, 0);
4124 emit_move_insn (meml, tmp);
4126 tmp = change_address (mem, DImode,
4127 gen_rtx_AND (DImode,
4128 plus_constant (mema, ofs + size - 1),
4130 set_mem_alias_set (tmp, 0);
4131 emit_move_insn (memh, tmp);
4133 if (WORDS_BIG_ENDIAN && sign && (size == 2 || size == 4))
4135 emit_move_insn (addr, plus_constant (mema, -1));
4137 emit_insn (gen_extqh_be (extl, meml, addr));
4138 emit_insn (gen_extxl_be (exth, memh, GEN_INT (64), addr));
4140 addr = expand_binop (DImode, ior_optab, extl, exth, tgt, 1, OPTAB_WIDEN);
4141 addr = expand_binop (DImode, ashr_optab, addr, GEN_INT (64 - size*8),
4142 addr, 1, OPTAB_WIDEN);
4144 else if (sign && size == 2)
4146 emit_move_insn (addr, plus_constant (mema, ofs+2));
4148 emit_insn (gen_extxl_le (extl, meml, GEN_INT (64), addr));
4149 emit_insn (gen_extqh_le (exth, memh, addr));
4151 /* We must use tgt here for the target. Alpha-vms port fails if we use
4152 addr for the target, because addr is marked as a pointer and combine
4153 knows that pointers are always sign-extended 32 bit values. */
4154 addr = expand_binop (DImode, ior_optab, extl, exth, tgt, 1, OPTAB_WIDEN);
4155 addr = expand_binop (DImode, ashr_optab, addr, GEN_INT (48),
4156 addr, 1, OPTAB_WIDEN);
4160 if (WORDS_BIG_ENDIAN)
4162 emit_move_insn (addr, plus_constant (mema, ofs+size-1));
4166 emit_insn (gen_extwh_be (extl, meml, addr));
4171 emit_insn (gen_extlh_be (extl, meml, addr));
4176 emit_insn (gen_extqh_be (extl, meml, addr));
4183 emit_insn (gen_extxl_be (exth, memh, GEN_INT (size*8), addr));
4187 emit_move_insn (addr, plus_constant (mema, ofs));
4188 emit_insn (gen_extxl_le (extl, meml, GEN_INT (size*8), addr));
4192 emit_insn (gen_extwh_le (exth, memh, addr));
4197 emit_insn (gen_extlh_le (exth, memh, addr));
4202 emit_insn (gen_extqh_le (exth, memh, addr));
4211 addr = expand_binop (mode, ior_optab, gen_lowpart (mode, extl),
4212 gen_lowpart (mode, exth), gen_lowpart (mode, tgt),
4217 emit_move_insn (tgt, gen_lowpart(GET_MODE (tgt), addr));
4220 /* Similarly, use ins and msk instructions to perform unaligned stores. */
4223 alpha_expand_unaligned_store (dst, src, size, ofs)
4225 HOST_WIDE_INT size, ofs;
4227 rtx dstl, dsth, addr, insl, insh, meml, memh, dsta;
4229 dstl = gen_reg_rtx (DImode);
4230 dsth = gen_reg_rtx (DImode);
4231 insl = gen_reg_rtx (DImode);
4232 insh = gen_reg_rtx (DImode);
4234 dsta = XEXP (dst, 0);
4235 if (GET_CODE (dsta) == LO_SUM)
4236 dsta = force_reg (Pmode, dsta);
4238 /* AND addresses cannot be in any alias set, since they may implicitly
4239 alias surrounding code. Ideally we'd have some alias set that
4240 covered all types except those with alignment 8 or higher. */
4242 meml = change_address (dst, DImode,
4243 gen_rtx_AND (DImode,
4244 plus_constant (dsta, ofs),
4246 set_mem_alias_set (meml, 0);
4248 memh = change_address (dst, DImode,
4249 gen_rtx_AND (DImode,
4250 plus_constant (dsta, ofs + size - 1),
4252 set_mem_alias_set (memh, 0);
4254 emit_move_insn (dsth, memh);
4255 emit_move_insn (dstl, meml);
4256 if (WORDS_BIG_ENDIAN)
4258 addr = copy_addr_to_reg (plus_constant (dsta, ofs+size-1));
4260 if (src != const0_rtx)
4265 emit_insn (gen_inswl_be (insh, gen_lowpart (HImode,src), addr));
4268 emit_insn (gen_insll_be (insh, gen_lowpart (SImode,src), addr));
4271 emit_insn (gen_insql_be (insh, gen_lowpart (DImode,src), addr));
4274 emit_insn (gen_insxh (insl, gen_lowpart (DImode, src),
4275 GEN_INT (size*8), addr));
4281 emit_insn (gen_mskxl_be (dsth, dsth, GEN_INT (0xffff), addr));
4285 rtx msk = immed_double_const (0xffffffff, 0, DImode);
4286 emit_insn (gen_mskxl_be (dsth, dsth, msk, addr));
4290 emit_insn (gen_mskxl_be (dsth, dsth, constm1_rtx, addr));
4294 emit_insn (gen_mskxh (dstl, dstl, GEN_INT (size*8), addr));
4298 addr = copy_addr_to_reg (plus_constant (dsta, ofs));
4300 if (src != const0_rtx)
4302 emit_insn (gen_insxh (insh, gen_lowpart (DImode, src),
4303 GEN_INT (size*8), addr));
4308 emit_insn (gen_inswl_le (insl, gen_lowpart (HImode, src), addr));
4311 emit_insn (gen_insll_le (insl, gen_lowpart (SImode, src), addr));
4314 emit_insn (gen_insql_le (insl, src, addr));
4319 emit_insn (gen_mskxh (dsth, dsth, GEN_INT (size*8), addr));
4324 emit_insn (gen_mskxl_le (dstl, dstl, GEN_INT (0xffff), addr));
4328 rtx msk = immed_double_const (0xffffffff, 0, DImode);
4329 emit_insn (gen_mskxl_le (dstl, dstl, msk, addr));
4333 emit_insn (gen_mskxl_le (dstl, dstl, constm1_rtx, addr));
4338 if (src != const0_rtx)
4340 dsth = expand_binop (DImode, ior_optab, insh, dsth, dsth, 0, OPTAB_WIDEN);
4341 dstl = expand_binop (DImode, ior_optab, insl, dstl, dstl, 0, OPTAB_WIDEN);
4344 if (WORDS_BIG_ENDIAN)
4346 emit_move_insn (meml, dstl);
4347 emit_move_insn (memh, dsth);
4351 /* Must store high before low for degenerate case of aligned. */
4352 emit_move_insn (memh, dsth);
4353 emit_move_insn (meml, dstl);
4357 /* The block move code tries to maximize speed by separating loads and
4358 stores at the expense of register pressure: we load all of the data
4359 before we store it back out. There are two secondary effects worth
4360 mentioning, that this speeds copying to/from aligned and unaligned
4361 buffers, and that it makes the code significantly easier to write. */
4363 #define MAX_MOVE_WORDS 8
4365 /* Load an integral number of consecutive unaligned quadwords. */
4368 alpha_expand_unaligned_load_words (out_regs, smem, words, ofs)
4371 HOST_WIDE_INT words, ofs;
4373 rtx const im8 = GEN_INT (-8);
4374 rtx const i64 = GEN_INT (64);
4375 rtx ext_tmps[MAX_MOVE_WORDS], data_regs[MAX_MOVE_WORDS+1];
4376 rtx sreg, areg, tmp, smema;
4379 smema = XEXP (smem, 0);
4380 if (GET_CODE (smema) == LO_SUM)
4381 smema = force_reg (Pmode, smema);
4383 /* Generate all the tmp registers we need. */
4384 for (i = 0; i < words; ++i)
4386 data_regs[i] = out_regs[i];
4387 ext_tmps[i] = gen_reg_rtx (DImode);
4389 data_regs[words] = gen_reg_rtx (DImode);
4392 smem = adjust_address (smem, GET_MODE (smem), ofs);
4394 /* Load up all of the source data. */
4395 for (i = 0; i < words; ++i)
4397 tmp = change_address (smem, DImode,
4398 gen_rtx_AND (DImode,
4399 plus_constant (smema, 8*i),
4401 set_mem_alias_set (tmp, 0);
4402 emit_move_insn (data_regs[i], tmp);
4405 tmp = change_address (smem, DImode,
4406 gen_rtx_AND (DImode,
4407 plus_constant (smema, 8*words - 1),
4409 set_mem_alias_set (tmp, 0);
4410 emit_move_insn (data_regs[words], tmp);
4412 /* Extract the half-word fragments. Unfortunately DEC decided to make
4413 extxh with offset zero a noop instead of zeroing the register, so
4414 we must take care of that edge condition ourselves with cmov. */
4416 sreg = copy_addr_to_reg (smema);
4417 areg = expand_binop (DImode, and_optab, sreg, GEN_INT (7), NULL,
4419 if (WORDS_BIG_ENDIAN)
4420 emit_move_insn (sreg, plus_constant (sreg, 7));
4421 for (i = 0; i < words; ++i)
4423 if (WORDS_BIG_ENDIAN)
4425 emit_insn (gen_extqh_be (data_regs[i], data_regs[i], sreg));
4426 emit_insn (gen_extxl_be (ext_tmps[i], data_regs[i+1], i64, sreg));
4430 emit_insn (gen_extxl_le (data_regs[i], data_regs[i], i64, sreg));
4431 emit_insn (gen_extqh_le (ext_tmps[i], data_regs[i+1], sreg));
4433 emit_insn (gen_rtx_SET (VOIDmode, ext_tmps[i],
4434 gen_rtx_IF_THEN_ELSE (DImode,
4435 gen_rtx_EQ (DImode, areg,
4437 const0_rtx, ext_tmps[i])));
4440 /* Merge the half-words into whole words. */
4441 for (i = 0; i < words; ++i)
4443 out_regs[i] = expand_binop (DImode, ior_optab, data_regs[i],
4444 ext_tmps[i], data_regs[i], 1, OPTAB_WIDEN);
4448 /* Store an integral number of consecutive unaligned quadwords. DATA_REGS
4449 may be NULL to store zeros. */
4452 alpha_expand_unaligned_store_words (data_regs, dmem, words, ofs)
4455 HOST_WIDE_INT words, ofs;
4457 rtx const im8 = GEN_INT (-8);
4458 rtx const i64 = GEN_INT (64);
4459 rtx ins_tmps[MAX_MOVE_WORDS];
4460 rtx st_tmp_1, st_tmp_2, dreg;
4461 rtx st_addr_1, st_addr_2, dmema;
4464 dmema = XEXP (dmem, 0);
4465 if (GET_CODE (dmema) == LO_SUM)
4466 dmema = force_reg (Pmode, dmema);
4468 /* Generate all the tmp registers we need. */
4469 if (data_regs != NULL)
4470 for (i = 0; i < words; ++i)
4471 ins_tmps[i] = gen_reg_rtx(DImode);
4472 st_tmp_1 = gen_reg_rtx(DImode);
4473 st_tmp_2 = gen_reg_rtx(DImode);
4476 dmem = adjust_address (dmem, GET_MODE (dmem), ofs);
4478 st_addr_2 = change_address (dmem, DImode,
4479 gen_rtx_AND (DImode,
4480 plus_constant (dmema, words*8 - 1),
4482 set_mem_alias_set (st_addr_2, 0);
4484 st_addr_1 = change_address (dmem, DImode,
4485 gen_rtx_AND (DImode, dmema, im8));
4486 set_mem_alias_set (st_addr_1, 0);
4488 /* Load up the destination end bits. */
4489 emit_move_insn (st_tmp_2, st_addr_2);
4490 emit_move_insn (st_tmp_1, st_addr_1);
4492 /* Shift the input data into place. */
4493 dreg = copy_addr_to_reg (dmema);
4494 if (WORDS_BIG_ENDIAN)
4495 emit_move_insn (dreg, plus_constant (dreg, 7));
4496 if (data_regs != NULL)
4498 for (i = words-1; i >= 0; --i)
4500 if (WORDS_BIG_ENDIAN)
4502 emit_insn (gen_insql_be (ins_tmps[i], data_regs[i], dreg));
4503 emit_insn (gen_insxh (data_regs[i], data_regs[i], i64, dreg));
4507 emit_insn (gen_insxh (ins_tmps[i], data_regs[i], i64, dreg));
4508 emit_insn (gen_insql_le (data_regs[i], data_regs[i], dreg));
4511 for (i = words-1; i > 0; --i)
4513 ins_tmps[i-1] = expand_binop (DImode, ior_optab, data_regs[i],
4514 ins_tmps[i-1], ins_tmps[i-1], 1,
4519 /* Split and merge the ends with the destination data. */
4520 if (WORDS_BIG_ENDIAN)
4522 emit_insn (gen_mskxl_be (st_tmp_2, st_tmp_2, constm1_rtx, dreg));
4523 emit_insn (gen_mskxh (st_tmp_1, st_tmp_1, i64, dreg));
4527 emit_insn (gen_mskxh (st_tmp_2, st_tmp_2, i64, dreg));
4528 emit_insn (gen_mskxl_le (st_tmp_1, st_tmp_1, constm1_rtx, dreg));
4531 if (data_regs != NULL)
4533 st_tmp_2 = expand_binop (DImode, ior_optab, st_tmp_2, ins_tmps[words-1],
4534 st_tmp_2, 1, OPTAB_WIDEN);
4535 st_tmp_1 = expand_binop (DImode, ior_optab, st_tmp_1, data_regs[0],
4536 st_tmp_1, 1, OPTAB_WIDEN);
4540 if (WORDS_BIG_ENDIAN)
4541 emit_move_insn (st_addr_1, st_tmp_1);
4543 emit_move_insn (st_addr_2, st_tmp_2);
4544 for (i = words-1; i > 0; --i)
4546 rtx tmp = change_address (dmem, DImode,
4547 gen_rtx_AND (DImode,
4548 plus_constant(dmema,
4549 WORDS_BIG_ENDIAN ? i*8-1 : i*8),
4551 set_mem_alias_set (tmp, 0);
4552 emit_move_insn (tmp, data_regs ? ins_tmps[i-1] : const0_rtx);
4554 if (WORDS_BIG_ENDIAN)
4555 emit_move_insn (st_addr_2, st_tmp_2);
4557 emit_move_insn (st_addr_1, st_tmp_1);
4561 /* Expand string/block move operations.
4563 operands[0] is the pointer to the destination.
4564 operands[1] is the pointer to the source.
4565 operands[2] is the number of bytes to move.
4566 operands[3] is the alignment. */
4569 alpha_expand_block_move (operands)
4572 rtx bytes_rtx = operands[2];
4573 rtx align_rtx = operands[3];
4574 HOST_WIDE_INT orig_bytes = INTVAL (bytes_rtx);
4575 HOST_WIDE_INT bytes = orig_bytes;
4576 HOST_WIDE_INT src_align = INTVAL (align_rtx) * BITS_PER_UNIT;
4577 HOST_WIDE_INT dst_align = src_align;
4578 rtx orig_src = operands[1];
4579 rtx orig_dst = operands[0];
4580 rtx data_regs[2 * MAX_MOVE_WORDS + 16];
4582 unsigned int i, words, ofs, nregs = 0;
4584 if (orig_bytes <= 0)
4586 else if (orig_bytes > MAX_MOVE_WORDS * UNITS_PER_WORD)
4589 /* Look for additional alignment information from recorded register info. */
4591 tmp = XEXP (orig_src, 0);
4592 if (GET_CODE (tmp) == REG)
4593 src_align = MAX (src_align, REGNO_POINTER_ALIGN (REGNO (tmp)));
4594 else if (GET_CODE (tmp) == PLUS
4595 && GET_CODE (XEXP (tmp, 0)) == REG
4596 && GET_CODE (XEXP (tmp, 1)) == CONST_INT)
4598 unsigned HOST_WIDE_INT c = INTVAL (XEXP (tmp, 1));
4599 unsigned int a = REGNO_POINTER_ALIGN (REGNO (XEXP (tmp, 0)));
4603 if (a >= 64 && c % 8 == 0)
4605 else if (a >= 32 && c % 4 == 0)
4607 else if (a >= 16 && c % 2 == 0)
4612 tmp = XEXP (orig_dst, 0);
4613 if (GET_CODE (tmp) == REG)
4614 dst_align = MAX (dst_align, REGNO_POINTER_ALIGN (REGNO (tmp)));
4615 else if (GET_CODE (tmp) == PLUS
4616 && GET_CODE (XEXP (tmp, 0)) == REG
4617 && GET_CODE (XEXP (tmp, 1)) == CONST_INT)
4619 unsigned HOST_WIDE_INT c = INTVAL (XEXP (tmp, 1));
4620 unsigned int a = REGNO_POINTER_ALIGN (REGNO (XEXP (tmp, 0)));
4624 if (a >= 64 && c % 8 == 0)
4626 else if (a >= 32 && c % 4 == 0)
4628 else if (a >= 16 && c % 2 == 0)
4633 /* Load the entire block into registers. */
4634 if (GET_CODE (XEXP (orig_src, 0)) == ADDRESSOF)
4636 enum machine_mode mode;
4638 tmp = XEXP (XEXP (orig_src, 0), 0);
4640 /* Don't use the existing register if we're reading more than
4641 is held in the register. Nor if there is not a mode that
4642 handles the exact size. */
4643 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 1);
4645 && GET_MODE_SIZE (GET_MODE (tmp)) >= bytes)
4649 data_regs[nregs] = gen_lowpart (DImode, tmp);
4650 data_regs[nregs + 1] = gen_highpart (DImode, tmp);
4654 data_regs[nregs++] = gen_lowpart (mode, tmp);
4659 /* No appropriate mode; fall back on memory. */
4660 orig_src = replace_equiv_address (orig_src,
4661 copy_addr_to_reg (XEXP (orig_src, 0)));
4662 src_align = GET_MODE_BITSIZE (GET_MODE (tmp));
4666 if (src_align >= 64 && bytes >= 8)
4670 for (i = 0; i < words; ++i)
4671 data_regs[nregs + i] = gen_reg_rtx (DImode);
4673 for (i = 0; i < words; ++i)
4674 emit_move_insn (data_regs[nregs + i],
4675 adjust_address (orig_src, DImode, ofs + i * 8));
4682 if (src_align >= 32 && bytes >= 4)
4686 for (i = 0; i < words; ++i)
4687 data_regs[nregs + i] = gen_reg_rtx (SImode);
4689 for (i = 0; i < words; ++i)
4690 emit_move_insn (data_regs[nregs + i],
4691 adjust_address (orig_src, SImode, ofs + i * 4));
4702 for (i = 0; i < words+1; ++i)
4703 data_regs[nregs + i] = gen_reg_rtx (DImode);
4705 alpha_expand_unaligned_load_words (data_regs + nregs, orig_src,
4713 if (! TARGET_BWX && bytes >= 4)
4715 data_regs[nregs++] = tmp = gen_reg_rtx (SImode);
4716 alpha_expand_unaligned_load (tmp, orig_src, 4, ofs, 0);
4723 if (src_align >= 16)
4726 data_regs[nregs++] = tmp = gen_reg_rtx (HImode);
4727 emit_move_insn (tmp, adjust_address (orig_src, HImode, ofs));
4730 } while (bytes >= 2);
4732 else if (! TARGET_BWX)
4734 data_regs[nregs++] = tmp = gen_reg_rtx (HImode);
4735 alpha_expand_unaligned_load (tmp, orig_src, 2, ofs, 0);
4743 data_regs[nregs++] = tmp = gen_reg_rtx (QImode);
4744 emit_move_insn (tmp, adjust_address (orig_src, QImode, ofs));
4751 if (nregs > ARRAY_SIZE (data_regs))
4754 /* Now save it back out again. */
4758 if (GET_CODE (XEXP (orig_dst, 0)) == ADDRESSOF)
4760 enum machine_mode mode;
4761 tmp = XEXP (XEXP (orig_dst, 0), 0);
4763 mode = mode_for_size (orig_bytes * BITS_PER_UNIT, MODE_INT, 1);
4764 if (GET_MODE (tmp) == mode)
4768 emit_move_insn (tmp, data_regs[0]);
4773 else if (nregs == 2 && mode == TImode)
4775 /* Undo the subregging done above when copying between
4776 two TImode registers. */
4777 if (GET_CODE (data_regs[0]) == SUBREG
4778 && GET_MODE (SUBREG_REG (data_regs[0])) == TImode)
4779 emit_move_insn (tmp, SUBREG_REG (data_regs[0]));
4785 emit_move_insn (gen_lowpart (DImode, tmp), data_regs[0]);
4786 emit_move_insn (gen_highpart (DImode, tmp), data_regs[1]);
4790 emit_no_conflict_block (seq, tmp, data_regs[0],
4791 data_regs[1], NULL_RTX);
4799 /* ??? If nregs > 1, consider reconstructing the word in regs. */
4800 /* ??? Optimize mode < dst_mode with strict_low_part. */
4802 /* No appropriate mode; fall back on memory. We can speed things
4803 up by recognizing extra alignment information. */
4804 orig_dst = replace_equiv_address (orig_dst,
4805 copy_addr_to_reg (XEXP (orig_dst, 0)));
4806 dst_align = GET_MODE_BITSIZE (GET_MODE (tmp));
4809 /* Write out the data in whatever chunks reading the source allowed. */
4810 if (dst_align >= 64)
4812 while (i < nregs && GET_MODE (data_regs[i]) == DImode)
4814 emit_move_insn (adjust_address (orig_dst, DImode, ofs),
4821 if (dst_align >= 32)
4823 /* If the source has remaining DImode regs, write them out in
4825 while (i < nregs && GET_MODE (data_regs[i]) == DImode)
4827 tmp = expand_binop (DImode, lshr_optab, data_regs[i], GEN_INT (32),
4828 NULL_RTX, 1, OPTAB_WIDEN);
4830 emit_move_insn (adjust_address (orig_dst, SImode, ofs),
4831 gen_lowpart (SImode, data_regs[i]));
4832 emit_move_insn (adjust_address (orig_dst, SImode, ofs + 4),
4833 gen_lowpart (SImode, tmp));
4838 while (i < nregs && GET_MODE (data_regs[i]) == SImode)
4840 emit_move_insn (adjust_address (orig_dst, SImode, ofs),
4847 if (i < nregs && GET_MODE (data_regs[i]) == DImode)
4849 /* Write out a remaining block of words using unaligned methods. */
4851 for (words = 1; i + words < nregs; words++)
4852 if (GET_MODE (data_regs[i + words]) != DImode)
4856 alpha_expand_unaligned_store (orig_dst, data_regs[i], 8, ofs);
4858 alpha_expand_unaligned_store_words (data_regs + i, orig_dst,
4865 /* Due to the above, this won't be aligned. */
4866 /* ??? If we have more than one of these, consider constructing full
4867 words in registers and using alpha_expand_unaligned_store_words. */
4868 while (i < nregs && GET_MODE (data_regs[i]) == SImode)
4870 alpha_expand_unaligned_store (orig_dst, data_regs[i], 4, ofs);
4875 if (dst_align >= 16)
4876 while (i < nregs && GET_MODE (data_regs[i]) == HImode)
4878 emit_move_insn (adjust_address (orig_dst, HImode, ofs), data_regs[i]);
4883 while (i < nregs && GET_MODE (data_regs[i]) == HImode)
4885 alpha_expand_unaligned_store (orig_dst, data_regs[i], 2, ofs);
4890 while (i < nregs && GET_MODE (data_regs[i]) == QImode)
4892 emit_move_insn (adjust_address (orig_dst, QImode, ofs), data_regs[i]);
4906 alpha_expand_block_clear (operands)
4909 rtx bytes_rtx = operands[1];
4910 rtx align_rtx = operands[2];
4911 HOST_WIDE_INT orig_bytes = INTVAL (bytes_rtx);
4912 HOST_WIDE_INT bytes = orig_bytes;
4913 HOST_WIDE_INT align = INTVAL (align_rtx) * BITS_PER_UNIT;
4914 HOST_WIDE_INT alignofs = 0;
4915 rtx orig_dst = operands[0];
4917 int i, words, ofs = 0;
4919 if (orig_bytes <= 0)
4921 if (orig_bytes > MAX_MOVE_WORDS * UNITS_PER_WORD)
4924 /* Look for stricter alignment. */
4925 tmp = XEXP (orig_dst, 0);
4926 if (GET_CODE (tmp) == REG)
4927 align = MAX (align, REGNO_POINTER_ALIGN (REGNO (tmp)));
4928 else if (GET_CODE (tmp) == PLUS
4929 && GET_CODE (XEXP (tmp, 0)) == REG
4930 && GET_CODE (XEXP (tmp, 1)) == CONST_INT)
4932 HOST_WIDE_INT c = INTVAL (XEXP (tmp, 1));
4933 int a = REGNO_POINTER_ALIGN (REGNO (XEXP (tmp, 0)));
4938 align = a, alignofs = 8 - c % 8;
4940 align = a, alignofs = 4 - c % 4;
4942 align = a, alignofs = 2 - c % 2;
4945 else if (GET_CODE (tmp) == ADDRESSOF)
4947 enum machine_mode mode;
4949 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 1);
4950 if (GET_MODE (XEXP (tmp, 0)) == mode)
4952 emit_move_insn (XEXP (tmp, 0), const0_rtx);
4956 /* No appropriate mode; fall back on memory. */
4957 orig_dst = replace_equiv_address (orig_dst, copy_addr_to_reg (tmp));
4958 align = GET_MODE_BITSIZE (GET_MODE (XEXP (tmp, 0)));
4961 /* Handle an unaligned prefix first. */
4965 #if HOST_BITS_PER_WIDE_INT >= 64
4966 /* Given that alignofs is bounded by align, the only time BWX could
4967 generate three stores is for a 7 byte fill. Prefer two individual
4968 stores over a load/mask/store sequence. */
4969 if ((!TARGET_BWX || alignofs == 7)
4971 && !(alignofs == 4 && bytes >= 4))
4973 enum machine_mode mode = (align >= 64 ? DImode : SImode);
4974 int inv_alignofs = (align >= 64 ? 8 : 4) - alignofs;
4978 mem = adjust_address (orig_dst, mode, ofs - inv_alignofs);
4979 set_mem_alias_set (mem, 0);
4981 mask = ~(~(HOST_WIDE_INT)0 << (inv_alignofs * 8));
4982 if (bytes < alignofs)
4984 mask |= ~(HOST_WIDE_INT)0 << ((inv_alignofs + bytes) * 8);
4995 tmp = expand_binop (mode, and_optab, mem, GEN_INT (mask),
4996 NULL_RTX, 1, OPTAB_WIDEN);
4998 emit_move_insn (mem, tmp);
5002 if (TARGET_BWX && (alignofs & 1) && bytes >= 1)
5004 emit_move_insn (adjust_address (orig_dst, QImode, ofs), const0_rtx);
5009 if (TARGET_BWX && align >= 16 && (alignofs & 3) == 2 && bytes >= 2)
5011 emit_move_insn (adjust_address (orig_dst, HImode, ofs), const0_rtx);
5016 if (alignofs == 4 && bytes >= 4)
5018 emit_move_insn (adjust_address (orig_dst, SImode, ofs), const0_rtx);
5024 /* If we've not used the extra lead alignment information by now,
5025 we won't be able to. Downgrade align to match what's left over. */
5028 alignofs = alignofs & -alignofs;
5029 align = MIN (align, alignofs * BITS_PER_UNIT);
5033 /* Handle a block of contiguous long-words. */
5035 if (align >= 64 && bytes >= 8)
5039 for (i = 0; i < words; ++i)
5040 emit_move_insn (adjust_address (orig_dst, DImode, ofs + i * 8),
5047 /* If the block is large and appropriately aligned, emit a single
5048 store followed by a sequence of stq_u insns. */
5050 if (align >= 32 && bytes > 16)
5054 emit_move_insn (adjust_address (orig_dst, SImode, ofs), const0_rtx);
5058 orig_dsta = XEXP (orig_dst, 0);
5059 if (GET_CODE (orig_dsta) == LO_SUM)
5060 orig_dsta = force_reg (Pmode, orig_dsta);
5063 for (i = 0; i < words; ++i)
5066 = change_address (orig_dst, DImode,
5067 gen_rtx_AND (DImode,
5068 plus_constant (orig_dsta, ofs + i*8),
5070 set_mem_alias_set (mem, 0);
5071 emit_move_insn (mem, const0_rtx);
5074 /* Depending on the alignment, the first stq_u may have overlapped
5075 with the initial stl, which means that the last stq_u didn't
5076 write as much as it would appear. Leave those questionable bytes
5078 bytes -= words * 8 - 4;
5079 ofs += words * 8 - 4;
5082 /* Handle a smaller block of aligned words. */
5084 if ((align >= 64 && bytes == 4)
5085 || (align == 32 && bytes >= 4))
5089 for (i = 0; i < words; ++i)
5090 emit_move_insn (adjust_address (orig_dst, SImode, ofs + i * 4),
5097 /* An unaligned block uses stq_u stores for as many as possible. */
5103 alpha_expand_unaligned_store_words (NULL, orig_dst, words, ofs);
5109 /* Next clean up any trailing pieces. */
5111 #if HOST_BITS_PER_WIDE_INT >= 64
5112 /* Count the number of bits in BYTES for which aligned stores could
5115 for (i = (TARGET_BWX ? 1 : 4); i * BITS_PER_UNIT <= align ; i <<= 1)
5119 /* If we have appropriate alignment (and it wouldn't take too many
5120 instructions otherwise), mask out the bytes we need. */
5121 if (TARGET_BWX ? words > 2 : bytes > 0)
5128 mem = adjust_address (orig_dst, DImode, ofs);
5129 set_mem_alias_set (mem, 0);
5131 mask = ~(HOST_WIDE_INT)0 << (bytes * 8);
5133 tmp = expand_binop (DImode, and_optab, mem, GEN_INT (mask),
5134 NULL_RTX, 1, OPTAB_WIDEN);
5136 emit_move_insn (mem, tmp);
5139 else if (align >= 32 && bytes < 4)
5144 mem = adjust_address (orig_dst, SImode, ofs);
5145 set_mem_alias_set (mem, 0);
5147 mask = ~(HOST_WIDE_INT)0 << (bytes * 8);
5149 tmp = expand_binop (SImode, and_optab, mem, GEN_INT (mask),
5150 NULL_RTX, 1, OPTAB_WIDEN);
5152 emit_move_insn (mem, tmp);
5158 if (!TARGET_BWX && bytes >= 4)
5160 alpha_expand_unaligned_store (orig_dst, const0_rtx, 4, ofs);
5170 emit_move_insn (adjust_address (orig_dst, HImode, ofs),
5174 } while (bytes >= 2);
5176 else if (! TARGET_BWX)
5178 alpha_expand_unaligned_store (orig_dst, const0_rtx, 2, ofs);
5186 emit_move_insn (adjust_address (orig_dst, QImode, ofs), const0_rtx);
5194 /* Returns a mask so that zap(x, value) == x & mask. */
5197 alpha_expand_zap_mask (value)
5198 HOST_WIDE_INT value;
5203 if (HOST_BITS_PER_WIDE_INT >= 64)
5205 HOST_WIDE_INT mask = 0;
5207 for (i = 7; i >= 0; --i)
5210 if (!((value >> i) & 1))
5214 result = gen_int_mode (mask, DImode);
5216 else if (HOST_BITS_PER_WIDE_INT == 32)
5218 HOST_WIDE_INT mask_lo = 0, mask_hi = 0;
5220 for (i = 7; i >= 4; --i)
5223 if (!((value >> i) & 1))
5227 for (i = 3; i >= 0; --i)
5230 if (!((value >> i) & 1))
5234 result = immed_double_const (mask_lo, mask_hi, DImode);
5243 alpha_expand_builtin_vector_binop (gen, mode, op0, op1, op2)
5244 rtx (*gen) PARAMS ((rtx, rtx, rtx));
5245 enum machine_mode mode;
5248 op0 = gen_lowpart (mode, op0);
5250 if (op1 == const0_rtx)
5251 op1 = CONST0_RTX (mode);
5253 op1 = gen_lowpart (mode, op1);
5255 if (op2 == const0_rtx)
5256 op2 = CONST0_RTX (mode);
5258 op2 = gen_lowpart (mode, op2);
5260 emit_insn ((*gen) (op0, op1, op2));
5263 /* Adjust the cost of a scheduling dependency. Return the new cost of
5264 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
5267 alpha_adjust_cost (insn, link, dep_insn, cost)
5273 enum attr_type insn_type, dep_insn_type;
5275 /* If the dependence is an anti-dependence, there is no cost. For an
5276 output dependence, there is sometimes a cost, but it doesn't seem
5277 worth handling those few cases. */
5278 if (REG_NOTE_KIND (link) != 0)
5281 /* If we can't recognize the insns, we can't really do anything. */
5282 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
5285 insn_type = get_attr_type (insn);
5286 dep_insn_type = get_attr_type (dep_insn);
5288 /* Bring in the user-defined memory latency. */
5289 if (dep_insn_type == TYPE_ILD
5290 || dep_insn_type == TYPE_FLD
5291 || dep_insn_type == TYPE_LDSYM)
5292 cost += alpha_memory_latency-1;
5294 /* Everything else handled in DFA bypasses now. */
5299 /* The number of instructions that can be issued per cycle. */
5304 return (alpha_cpu == PROCESSOR_EV4 ? 2 : 4);
5308 alpha_use_dfa_pipeline_interface ()
5313 /* How many alternative schedules to try. This should be as wide as the
5314 scheduling freedom in the DFA, but no wider. Making this value too
5315 large results extra work for the scheduler.
5317 For EV4, loads can be issued to either IB0 or IB1, thus we have 2
5318 alternative schedules. For EV5, we can choose between E0/E1 and
5319 FA/FM. For EV6, an arithmatic insn can be issued to U0/U1/L0/L1. */
5322 alpha_multipass_dfa_lookahead ()
5324 return (alpha_cpu == PROCESSOR_EV6 ? 4 : 2);
5327 /* Machine-specific function data. */
5329 struct machine_function GTY(())
5332 /* List of call information words for calls from this function. */
5333 struct rtx_def *first_ciw;
5334 struct rtx_def *last_ciw;
5337 /* List of deferred case vectors. */
5338 struct rtx_def *addr_list;
5341 const char *some_ld_name;
5344 /* How to allocate a 'struct machine_function'. */
5346 static struct machine_function *
5347 alpha_init_machine_status ()
5349 return ((struct machine_function *)
5350 ggc_alloc_cleared (sizeof (struct machine_function)));
5353 /* Functions to save and restore alpha_return_addr_rtx. */
5355 /* Start the ball rolling with RETURN_ADDR_RTX. */
5358 alpha_return_addr (count, frame)
5360 rtx frame ATTRIBUTE_UNUSED;
5365 return get_hard_reg_initial_val (Pmode, REG_RA);
5368 /* Return or create a pseudo containing the gp value for the current
5369 function. Needed only if TARGET_LD_BUGGY_LDGP. */
5372 alpha_gp_save_rtx ()
5374 rtx r = get_hard_reg_initial_val (DImode, 29);
5375 if (GET_CODE (r) != MEM)
5376 r = gen_mem_addressof (r, NULL_TREE);
5381 alpha_ra_ever_killed ()
5385 if (!has_hard_reg_initial_val (Pmode, REG_RA))
5386 return regs_ever_live[REG_RA];
5388 push_topmost_sequence ();
5390 pop_topmost_sequence ();
5392 return reg_set_between_p (gen_rtx_REG (Pmode, REG_RA), top, NULL_RTX);
5396 /* Return the trap mode suffix applicable to the current
5397 instruction, or NULL. */
5400 get_trap_mode_suffix ()
5402 enum attr_trap_suffix s = get_attr_trap_suffix (current_output_insn);
5406 case TRAP_SUFFIX_NONE:
5409 case TRAP_SUFFIX_SU:
5410 if (alpha_fptm >= ALPHA_FPTM_SU)
5414 case TRAP_SUFFIX_SUI:
5415 if (alpha_fptm >= ALPHA_FPTM_SUI)
5419 case TRAP_SUFFIX_V_SV:
5427 case ALPHA_FPTM_SUI:
5432 case TRAP_SUFFIX_V_SV_SVI:
5441 case ALPHA_FPTM_SUI:
5446 case TRAP_SUFFIX_U_SU_SUI:
5455 case ALPHA_FPTM_SUI:
5463 /* Return the rounding mode suffix applicable to the current
5464 instruction, or NULL. */
5467 get_round_mode_suffix ()
5469 enum attr_round_suffix s = get_attr_round_suffix (current_output_insn);
5473 case ROUND_SUFFIX_NONE:
5475 case ROUND_SUFFIX_NORMAL:
5478 case ALPHA_FPRM_NORM:
5480 case ALPHA_FPRM_MINF:
5482 case ALPHA_FPRM_CHOP:
5484 case ALPHA_FPRM_DYN:
5489 case ROUND_SUFFIX_C:
5495 /* Locate some local-dynamic symbol still in use by this function
5496 so that we can print its name in some movdi_er_tlsldm pattern. */
5499 get_some_local_dynamic_name ()
5503 if (cfun->machine->some_ld_name)
5504 return cfun->machine->some_ld_name;
5506 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
5508 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
5509 return cfun->machine->some_ld_name;
5515 get_some_local_dynamic_name_1 (px, data)
5517 void *data ATTRIBUTE_UNUSED;
5521 if (GET_CODE (x) == SYMBOL_REF)
5523 const char *str = XSTR (x, 0);
5524 if (str[0] == '@' && str[1] == 'D')
5526 cfun->machine->some_ld_name = str;
5534 /* Print an operand. Recognize special options, documented below. */
5537 print_operand (file, x, code)
5547 /* Print the assembler name of the current function. */
5548 assemble_name (file, alpha_fnname);
5552 assemble_name (file, get_some_local_dynamic_name ());
5557 const char *trap = get_trap_mode_suffix ();
5558 const char *round = get_round_mode_suffix ();
5561 fprintf (file, (TARGET_AS_SLASH_BEFORE_SUFFIX ? "/%s%s" : "%s%s"),
5562 (trap ? trap : ""), (round ? round : ""));
5567 /* Generates single precision instruction suffix. */
5568 fputc ((TARGET_FLOAT_VAX ? 'f' : 's'), file);
5572 /* Generates double precision instruction suffix. */
5573 fputc ((TARGET_FLOAT_VAX ? 'g' : 't'), file);
5577 if (alpha_this_literal_sequence_number == 0)
5578 alpha_this_literal_sequence_number = alpha_next_sequence_number++;
5579 fprintf (file, "%d", alpha_this_literal_sequence_number);
5583 if (alpha_this_gpdisp_sequence_number == 0)
5584 alpha_this_gpdisp_sequence_number = alpha_next_sequence_number++;
5585 fprintf (file, "%d", alpha_this_gpdisp_sequence_number);
5589 if (GET_CODE (x) == HIGH)
5590 output_addr_const (file, XEXP (x, 0));
5592 output_operand_lossage ("invalid %%H value");
5599 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSGD_CALL)
5601 x = XVECEXP (x, 0, 0);
5602 lituse = "lituse_tlsgd";
5604 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSLDM_CALL)
5606 x = XVECEXP (x, 0, 0);
5607 lituse = "lituse_tlsldm";
5609 else if (GET_CODE (x) == CONST_INT)
5610 lituse = "lituse_jsr";
5613 output_operand_lossage ("invalid %%J value");
5617 if (x != const0_rtx)
5618 fprintf (file, "\t\t!%s!%d", lituse, (int) INTVAL (x));
5623 /* If this operand is the constant zero, write it as "$31". */
5624 if (GET_CODE (x) == REG)
5625 fprintf (file, "%s", reg_names[REGNO (x)]);
5626 else if (x == CONST0_RTX (GET_MODE (x)))
5627 fprintf (file, "$31");
5629 output_operand_lossage ("invalid %%r value");
5633 /* Similar, but for floating-point. */
5634 if (GET_CODE (x) == REG)
5635 fprintf (file, "%s", reg_names[REGNO (x)]);
5636 else if (x == CONST0_RTX (GET_MODE (x)))
5637 fprintf (file, "$f31");
5639 output_operand_lossage ("invalid %%R value");
5643 /* Write the 1's complement of a constant. */
5644 if (GET_CODE (x) != CONST_INT)
5645 output_operand_lossage ("invalid %%N value");
5647 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INTVAL (x));
5651 /* Write 1 << C, for a constant C. */
5652 if (GET_CODE (x) != CONST_INT)
5653 output_operand_lossage ("invalid %%P value");
5655 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (HOST_WIDE_INT) 1 << INTVAL (x));
5659 /* Write the high-order 16 bits of a constant, sign-extended. */
5660 if (GET_CODE (x) != CONST_INT)
5661 output_operand_lossage ("invalid %%h value");
5663 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) >> 16);
5667 /* Write the low-order 16 bits of a constant, sign-extended. */
5668 if (GET_CODE (x) != CONST_INT)
5669 output_operand_lossage ("invalid %%L value");
5671 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5672 (INTVAL (x) & 0xffff) - 2 * (INTVAL (x) & 0x8000));
5676 /* Write mask for ZAP insn. */
5677 if (GET_CODE (x) == CONST_DOUBLE)
5679 HOST_WIDE_INT mask = 0;
5680 HOST_WIDE_INT value;
5682 value = CONST_DOUBLE_LOW (x);
5683 for (i = 0; i < HOST_BITS_PER_WIDE_INT / HOST_BITS_PER_CHAR;
5688 value = CONST_DOUBLE_HIGH (x);
5689 for (i = 0; i < HOST_BITS_PER_WIDE_INT / HOST_BITS_PER_CHAR;
5692 mask |= (1 << (i + sizeof (int)));
5694 fprintf (file, HOST_WIDE_INT_PRINT_DEC, mask & 0xff);
5697 else if (GET_CODE (x) == CONST_INT)
5699 HOST_WIDE_INT mask = 0, value = INTVAL (x);
5701 for (i = 0; i < 8; i++, value >>= 8)
5705 fprintf (file, HOST_WIDE_INT_PRINT_DEC, mask);
5708 output_operand_lossage ("invalid %%m value");
5712 /* 'b', 'w', 'l', or 'q' as the value of the constant. */
5713 if (GET_CODE (x) != CONST_INT
5714 || (INTVAL (x) != 8 && INTVAL (x) != 16
5715 && INTVAL (x) != 32 && INTVAL (x) != 64))
5716 output_operand_lossage ("invalid %%M value");
5718 fprintf (file, "%s",
5719 (INTVAL (x) == 8 ? "b"
5720 : INTVAL (x) == 16 ? "w"
5721 : INTVAL (x) == 32 ? "l"
5726 /* Similar, except do it from the mask. */
5727 if (GET_CODE (x) == CONST_INT)
5729 HOST_WIDE_INT value = INTVAL (x);
5736 if (value == 0xffff)
5741 if (value == 0xffffffff)
5752 else if (HOST_BITS_PER_WIDE_INT == 32
5753 && GET_CODE (x) == CONST_DOUBLE
5754 && CONST_DOUBLE_LOW (x) == 0xffffffff
5755 && CONST_DOUBLE_HIGH (x) == 0)
5760 output_operand_lossage ("invalid %%U value");
5764 /* Write the constant value divided by 8 for little-endian mode or
5765 (56 - value) / 8 for big-endian mode. */
5767 if (GET_CODE (x) != CONST_INT
5768 || (unsigned HOST_WIDE_INT) INTVAL (x) >= (WORDS_BIG_ENDIAN
5771 || (INTVAL (x) & 7) != 0)
5772 output_operand_lossage ("invalid %%s value");
5774 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5776 ? (56 - INTVAL (x)) / 8
5781 /* Same, except compute (64 - c) / 8 */
5783 if (GET_CODE (x) != CONST_INT
5784 && (unsigned HOST_WIDE_INT) INTVAL (x) >= 64
5785 && (INTVAL (x) & 7) != 8)
5786 output_operand_lossage ("invalid %%s value");
5788 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (64 - INTVAL (x)) / 8);
5793 /* On Unicos/Mk systems: use a DEX expression if the symbol
5794 clashes with a register name. */
5795 int dex = unicosmk_need_dex (x);
5797 fprintf (file, "DEX(%d)", dex);
5799 output_addr_const (file, x);
5803 case 'C': case 'D': case 'c': case 'd':
5804 /* Write out comparison name. */
5806 enum rtx_code c = GET_CODE (x);
5808 if (GET_RTX_CLASS (c) != '<')
5809 output_operand_lossage ("invalid %%C value");
5811 else if (code == 'D')
5812 c = reverse_condition (c);
5813 else if (code == 'c')
5814 c = swap_condition (c);
5815 else if (code == 'd')
5816 c = swap_condition (reverse_condition (c));
5819 fprintf (file, "ule");
5821 fprintf (file, "ult");
5822 else if (c == UNORDERED)
5823 fprintf (file, "un");
5825 fprintf (file, "%s", GET_RTX_NAME (c));
5830 /* Write the divide or modulus operator. */
5831 switch (GET_CODE (x))
5834 fprintf (file, "div%s", GET_MODE (x) == SImode ? "l" : "q");
5837 fprintf (file, "div%su", GET_MODE (x) == SImode ? "l" : "q");
5840 fprintf (file, "rem%s", GET_MODE (x) == SImode ? "l" : "q");
5843 fprintf (file, "rem%su", GET_MODE (x) == SImode ? "l" : "q");
5846 output_operand_lossage ("invalid %%E value");
5852 /* Write "_u" for unaligned access. */
5853 if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == AND)
5854 fprintf (file, "_u");
5858 if (GET_CODE (x) == REG)
5859 fprintf (file, "%s", reg_names[REGNO (x)]);
5860 else if (GET_CODE (x) == MEM)
5861 output_address (XEXP (x, 0));
5862 else if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == UNSPEC)
5864 switch (XINT (XEXP (x, 0), 1))
5868 output_addr_const (file, XVECEXP (XEXP (x, 0), 0, 0));
5871 output_operand_lossage ("unknown relocation unspec");
5876 output_addr_const (file, x);
5880 output_operand_lossage ("invalid %%xn code");
5885 print_operand_address (file, addr)
5890 HOST_WIDE_INT offset = 0;
5892 if (GET_CODE (addr) == AND)
5893 addr = XEXP (addr, 0);
5895 if (GET_CODE (addr) == PLUS
5896 && GET_CODE (XEXP (addr, 1)) == CONST_INT)
5898 offset = INTVAL (XEXP (addr, 1));
5899 addr = XEXP (addr, 0);
5902 if (GET_CODE (addr) == LO_SUM)
5904 const char *reloc16, *reloclo;
5905 rtx op1 = XEXP (addr, 1);
5907 if (GET_CODE (op1) == CONST && GET_CODE (XEXP (op1, 0)) == UNSPEC)
5909 op1 = XEXP (op1, 0);
5910 switch (XINT (op1, 1))
5914 reloclo = (alpha_tls_size == 16 ? "dtprel" : "dtprello");
5918 reloclo = (alpha_tls_size == 16 ? "tprel" : "tprello");
5921 output_operand_lossage ("unknown relocation unspec");
5925 output_addr_const (file, XVECEXP (op1, 0, 0));
5930 reloclo = "gprellow";
5931 output_addr_const (file, op1);
5937 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset);
5940 addr = XEXP (addr, 0);
5941 if (GET_CODE (addr) == REG)
5942 basereg = REGNO (addr);
5943 else if (GET_CODE (addr) == SUBREG
5944 && GET_CODE (SUBREG_REG (addr)) == REG)
5945 basereg = subreg_regno (addr);
5949 fprintf (file, "($%d)\t\t!%s", basereg,
5950 (basereg == 29 ? reloc16 : reloclo));
5954 if (GET_CODE (addr) == REG)
5955 basereg = REGNO (addr);
5956 else if (GET_CODE (addr) == SUBREG
5957 && GET_CODE (SUBREG_REG (addr)) == REG)
5958 basereg = subreg_regno (addr);
5959 else if (GET_CODE (addr) == CONST_INT)
5960 offset = INTVAL (addr);
5962 #if TARGET_ABI_OPEN_VMS
5963 else if (GET_CODE (addr) == SYMBOL_REF)
5965 fprintf (file, "%s", XSTR (addr, 0));
5968 else if (GET_CODE (addr) == CONST
5969 && GET_CODE (XEXP (addr, 0)) == PLUS
5970 && GET_CODE (XEXP (XEXP (addr, 0), 0)) == SYMBOL_REF)
5972 fprintf (file, "%s+%d",
5973 XSTR (XEXP (XEXP (addr, 0), 0), 0),
5974 INTVAL (XEXP (XEXP (addr, 0), 1)));
5982 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset);
5983 fprintf (file, "($%d)", basereg);
5986 /* Emit RTL insns to initialize the variable parts of a trampoline at
5987 TRAMP. FNADDR is an RTX for the address of the function's pure
5988 code. CXT is an RTX for the static chain value for the function.
5990 The three offset parameters are for the individual template's
5991 layout. A JMPOFS < 0 indicates that the trampoline does not
5992 contain instructions at all.
5994 We assume here that a function will be called many more times than
5995 its address is taken (e.g., it might be passed to qsort), so we
5996 take the trouble to initialize the "hint" field in the JMP insn.
5997 Note that the hint field is PC (new) + 4 * bits 13:0. */
6000 alpha_initialize_trampoline (tramp, fnaddr, cxt, fnofs, cxtofs, jmpofs)
6001 rtx tramp, fnaddr, cxt;
6002 int fnofs, cxtofs, jmpofs;
6004 rtx temp, temp1, addr;
6005 /* VMS really uses DImode pointers in memory at this point. */
6006 enum machine_mode mode = TARGET_ABI_OPEN_VMS ? Pmode : ptr_mode;
6008 #ifdef POINTERS_EXTEND_UNSIGNED
6009 fnaddr = convert_memory_address (mode, fnaddr);
6010 cxt = convert_memory_address (mode, cxt);
6013 /* Store function address and CXT. */
6014 addr = memory_address (mode, plus_constant (tramp, fnofs));
6015 emit_move_insn (gen_rtx_MEM (mode, addr), fnaddr);
6016 addr = memory_address (mode, plus_constant (tramp, cxtofs));
6017 emit_move_insn (gen_rtx_MEM (mode, addr), cxt);
6019 /* This has been disabled since the hint only has a 32k range, and in
6020 no existing OS is the stack within 32k of the text segment. */
6021 if (0 && jmpofs >= 0)
6023 /* Compute hint value. */
6024 temp = force_operand (plus_constant (tramp, jmpofs+4), NULL_RTX);
6025 temp = expand_binop (DImode, sub_optab, fnaddr, temp, temp, 1,
6027 temp = expand_shift (RSHIFT_EXPR, Pmode, temp,
6028 build_int_2 (2, 0), NULL_RTX, 1);
6029 temp = expand_and (SImode, gen_lowpart (SImode, temp),
6030 GEN_INT (0x3fff), 0);
6032 /* Merge in the hint. */
6033 addr = memory_address (SImode, plus_constant (tramp, jmpofs));
6034 temp1 = force_reg (SImode, gen_rtx_MEM (SImode, addr));
6035 temp1 = expand_and (SImode, temp1, GEN_INT (0xffffc000), NULL_RTX);
6036 temp1 = expand_binop (SImode, ior_optab, temp1, temp, temp1, 1,
6038 emit_move_insn (gen_rtx_MEM (SImode, addr), temp1);
6041 #ifdef TRANSFER_FROM_TRAMPOLINE
6042 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"),
6043 0, VOIDmode, 1, tramp, Pmode);
6047 emit_insn (gen_imb ());
6050 /* Determine where to put an argument to a function.
6051 Value is zero to push the argument on the stack,
6052 or a hard register in which to store the argument.
6054 MODE is the argument's machine mode.
6055 TYPE is the data type of the argument (as a tree).
6056 This is null for libcalls where that information may
6058 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6059 the preceding args and about the function being called.
6060 NAMED is nonzero if this argument is a named parameter
6061 (otherwise it is an extra parameter matching an ellipsis).
6063 On Alpha the first 6 words of args are normally in registers
6064 and the rest are pushed. */
6067 function_arg (cum, mode, type, named)
6068 CUMULATIVE_ARGS cum;
6069 enum machine_mode mode;
6071 int named ATTRIBUTE_UNUSED;
6076 /* Set up defaults for FP operands passed in FP registers, and
6077 integral operands passed in integer registers. */
6079 && (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
6080 || GET_MODE_CLASS (mode) == MODE_FLOAT))
6085 /* ??? Irritatingly, the definition of CUMULATIVE_ARGS is different for
6086 the three platforms, so we can't avoid conditional compilation. */
6087 #if TARGET_ABI_OPEN_VMS
6089 if (mode == VOIDmode)
6090 return alpha_arg_info_reg_val (cum);
6092 num_args = cum.num_args;
6093 if (num_args >= 6 || MUST_PASS_IN_STACK (mode, type))
6097 #if TARGET_ABI_UNICOSMK
6101 /* If this is the last argument, generate the call info word (CIW). */
6102 /* ??? We don't include the caller's line number in the CIW because
6103 I don't know how to determine it if debug infos are turned off. */
6104 if (mode == VOIDmode)
6113 for (i = 0; i < cum.num_reg_words && i < 5; i++)
6114 if (cum.reg_args_type[i])
6115 lo |= (1 << (7 - i));
6117 if (cum.num_reg_words == 6 && cum.reg_args_type[5])
6120 lo |= cum.num_reg_words;
6122 #if HOST_BITS_PER_WIDE_INT == 32
6123 hi = (cum.num_args << 20) | cum.num_arg_words;
6125 lo = lo | ((HOST_WIDE_INT) cum.num_args << 52)
6126 | ((HOST_WIDE_INT) cum.num_arg_words << 32);
6129 ciw = immed_double_const (lo, hi, DImode);
6131 return gen_rtx_UNSPEC (DImode, gen_rtvec (1, ciw),
6132 UNSPEC_UMK_LOAD_CIW);
6135 size = ALPHA_ARG_SIZE (mode, type, named);
6136 num_args = cum.num_reg_words;
6137 if (MUST_PASS_IN_STACK (mode, type)
6138 || cum.num_reg_words + size > 6 || cum.force_stack)
6140 else if (type && TYPE_MODE (type) == BLKmode)
6144 reg1 = gen_rtx_REG (DImode, num_args + 16);
6145 reg1 = gen_rtx_EXPR_LIST (DImode, reg1, const0_rtx);
6147 /* The argument fits in two registers. Note that we still need to
6148 reserve a register for empty structures. */
6152 return gen_rtx_PARALLEL (mode, gen_rtvec (1, reg1));
6155 reg2 = gen_rtx_REG (DImode, num_args + 17);
6156 reg2 = gen_rtx_EXPR_LIST (DImode, reg2, GEN_INT (8));
6157 return gen_rtx_PARALLEL (mode, gen_rtvec (2, reg1, reg2));
6167 /* VOID is passed as a special flag for "last argument". */
6168 if (type == void_type_node)
6170 else if (MUST_PASS_IN_STACK (mode, type))
6172 else if (FUNCTION_ARG_PASS_BY_REFERENCE (cum, mode, type, named))
6175 #endif /* TARGET_ABI_UNICOSMK */
6176 #endif /* TARGET_ABI_OPEN_VMS */
6178 return gen_rtx_REG (mode, num_args + basereg);
6182 alpha_build_va_list ()
6184 tree base, ofs, record, type_decl;
6186 if (TARGET_ABI_OPEN_VMS || TARGET_ABI_UNICOSMK)
6187 return ptr_type_node;
6189 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
6190 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
6191 TREE_CHAIN (record) = type_decl;
6192 TYPE_NAME (record) = type_decl;
6194 /* C++? SET_IS_AGGR_TYPE (record, 1); */
6196 ofs = build_decl (FIELD_DECL, get_identifier ("__offset"),
6198 DECL_FIELD_CONTEXT (ofs) = record;
6200 base = build_decl (FIELD_DECL, get_identifier ("__base"),
6202 DECL_FIELD_CONTEXT (base) = record;
6203 TREE_CHAIN (base) = ofs;
6205 TYPE_FIELDS (record) = base;
6206 layout_type (record);
6212 alpha_va_start (valist, nextarg)
6214 rtx nextarg ATTRIBUTE_UNUSED;
6216 HOST_WIDE_INT offset;
6217 tree t, offset_field, base_field;
6219 if (TREE_CODE (TREE_TYPE (valist)) == ERROR_MARK)
6222 if (TARGET_ABI_UNICOSMK)
6223 std_expand_builtin_va_start (valist, nextarg);
6225 /* For Unix, SETUP_INCOMING_VARARGS moves the starting address base
6226 up by 48, storing fp arg registers in the first 48 bytes, and the
6227 integer arg registers in the next 48 bytes. This is only done,
6228 however, if any integer registers need to be stored.
6230 If no integer registers need be stored, then we must subtract 48
6231 in order to account for the integer arg registers which are counted
6232 in argsize above, but which are not actually stored on the stack. */
6235 offset = TARGET_ABI_OPEN_VMS ? UNITS_PER_WORD : 6 * UNITS_PER_WORD;
6237 offset = -6 * UNITS_PER_WORD;
6239 if (TARGET_ABI_OPEN_VMS)
6241 nextarg = plus_constant (nextarg, offset);
6242 nextarg = plus_constant (nextarg, NUM_ARGS * UNITS_PER_WORD);
6243 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist,
6244 make_tree (ptr_type_node, nextarg));
6245 TREE_SIDE_EFFECTS (t) = 1;
6247 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6251 base_field = TYPE_FIELDS (TREE_TYPE (valist));
6252 offset_field = TREE_CHAIN (base_field);
6254 base_field = build (COMPONENT_REF, TREE_TYPE (base_field),
6255 valist, base_field);
6256 offset_field = build (COMPONENT_REF, TREE_TYPE (offset_field),
6257 valist, offset_field);
6259 t = make_tree (ptr_type_node, virtual_incoming_args_rtx);
6260 t = build (PLUS_EXPR, ptr_type_node, t, build_int_2 (offset, 0));
6261 t = build (MODIFY_EXPR, TREE_TYPE (base_field), base_field, t);
6262 TREE_SIDE_EFFECTS (t) = 1;
6263 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6265 t = build_int_2 (NUM_ARGS * UNITS_PER_WORD, 0);
6266 t = build (MODIFY_EXPR, TREE_TYPE (offset_field), offset_field, t);
6267 TREE_SIDE_EFFECTS (t) = 1;
6268 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6273 alpha_va_arg (valist, type)
6277 tree t, type_size, rounded_size;
6278 tree offset_field, base_field, addr_tree, addend;
6279 tree wide_type, wide_ofs;
6282 if (TARGET_ABI_OPEN_VMS || TARGET_ABI_UNICOSMK)
6283 return std_expand_builtin_va_arg (valist, type);
6285 if (type == error_mark_node
6286 || (type_size = TYPE_SIZE_UNIT (TYPE_MAIN_VARIANT (type))) == NULL
6287 || TREE_OVERFLOW (type_size))
6288 rounded_size = size_zero_node;
6290 rounded_size = fold (build (MULT_EXPR, sizetype,
6291 fold (build (TRUNC_DIV_EXPR, sizetype,
6292 fold (build (PLUS_EXPR, sizetype,
6298 base_field = TYPE_FIELDS (TREE_TYPE (valist));
6299 offset_field = TREE_CHAIN (base_field);
6301 base_field = build (COMPONENT_REF, TREE_TYPE (base_field),
6302 valist, base_field);
6303 offset_field = build (COMPONENT_REF, TREE_TYPE (offset_field),
6304 valist, offset_field);
6306 /* If the type could not be passed in registers, skip the block
6307 reserved for the registers. */
6308 if (MUST_PASS_IN_STACK (TYPE_MODE (type), type))
6310 t = build (MODIFY_EXPR, TREE_TYPE (offset_field), offset_field,
6311 build (MAX_EXPR, TREE_TYPE (offset_field),
6312 offset_field, build_int_2 (6*8, 0)));
6313 TREE_SIDE_EFFECTS (t) = 1;
6314 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6317 wide_type = make_signed_type (64);
6318 wide_ofs = save_expr (build1 (CONVERT_EXPR, wide_type, offset_field));
6322 if (TYPE_MODE (type) == TFmode || TYPE_MODE (type) == TCmode)
6325 rounded_size = size_int (UNITS_PER_WORD);
6327 else if (FLOAT_TYPE_P (type))
6329 tree fpaddend, cond;
6331 fpaddend = fold (build (PLUS_EXPR, TREE_TYPE (addend),
6332 addend, build_int_2 (-6*8, 0)));
6334 cond = fold (build (LT_EXPR, integer_type_node,
6335 wide_ofs, build_int_2 (6*8, 0)));
6337 addend = fold (build (COND_EXPR, TREE_TYPE (addend), cond,
6341 addr_tree = build (PLUS_EXPR, TREE_TYPE (base_field),
6342 base_field, addend);
6344 addr = expand_expr (addr_tree, NULL_RTX, Pmode, EXPAND_NORMAL);
6345 addr = copy_to_reg (addr);
6347 t = build (MODIFY_EXPR, TREE_TYPE (offset_field), offset_field,
6348 build (PLUS_EXPR, TREE_TYPE (offset_field),
6349 offset_field, rounded_size));
6350 TREE_SIDE_EFFECTS (t) = 1;
6351 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6355 addr = force_reg (Pmode, addr);
6356 addr = gen_rtx_MEM (Pmode, addr);
6366 ALPHA_BUILTIN_CMPBGE,
6367 ALPHA_BUILTIN_EXTBL,
6368 ALPHA_BUILTIN_EXTWL,
6369 ALPHA_BUILTIN_EXTLL,
6370 ALPHA_BUILTIN_EXTQL,
6371 ALPHA_BUILTIN_EXTWH,
6372 ALPHA_BUILTIN_EXTLH,
6373 ALPHA_BUILTIN_EXTQH,
6374 ALPHA_BUILTIN_INSBL,
6375 ALPHA_BUILTIN_INSWL,
6376 ALPHA_BUILTIN_INSLL,
6377 ALPHA_BUILTIN_INSQL,
6378 ALPHA_BUILTIN_INSWH,
6379 ALPHA_BUILTIN_INSLH,
6380 ALPHA_BUILTIN_INSQH,
6381 ALPHA_BUILTIN_MSKBL,
6382 ALPHA_BUILTIN_MSKWL,
6383 ALPHA_BUILTIN_MSKLL,
6384 ALPHA_BUILTIN_MSKQL,
6385 ALPHA_BUILTIN_MSKWH,
6386 ALPHA_BUILTIN_MSKLH,
6387 ALPHA_BUILTIN_MSKQH,
6388 ALPHA_BUILTIN_UMULH,
6390 ALPHA_BUILTIN_ZAPNOT,
6391 ALPHA_BUILTIN_AMASK,
6392 ALPHA_BUILTIN_IMPLVER,
6394 ALPHA_BUILTIN_THREAD_POINTER,
6395 ALPHA_BUILTIN_SET_THREAD_POINTER,
6398 ALPHA_BUILTIN_MINUB8,
6399 ALPHA_BUILTIN_MINSB8,
6400 ALPHA_BUILTIN_MINUW4,
6401 ALPHA_BUILTIN_MINSW4,
6402 ALPHA_BUILTIN_MAXUB8,
6403 ALPHA_BUILTIN_MAXSB8,
6404 ALPHA_BUILTIN_MAXUW4,
6405 ALPHA_BUILTIN_MAXSW4,
6409 ALPHA_BUILTIN_UNPKBL,
6410 ALPHA_BUILTIN_UNPKBW,
6415 ALPHA_BUILTIN_CTPOP,
6420 static unsigned int const code_for_builtin[ALPHA_BUILTIN_max] = {
6421 CODE_FOR_builtin_cmpbge,
6422 CODE_FOR_builtin_extbl,
6423 CODE_FOR_builtin_extwl,
6424 CODE_FOR_builtin_extll,
6425 CODE_FOR_builtin_extql,
6426 CODE_FOR_builtin_extwh,
6427 CODE_FOR_builtin_extlh,
6428 CODE_FOR_builtin_extqh,
6429 CODE_FOR_builtin_insbl,
6430 CODE_FOR_builtin_inswl,
6431 CODE_FOR_builtin_insll,
6432 CODE_FOR_builtin_insql,
6433 CODE_FOR_builtin_inswh,
6434 CODE_FOR_builtin_inslh,
6435 CODE_FOR_builtin_insqh,
6436 CODE_FOR_builtin_mskbl,
6437 CODE_FOR_builtin_mskwl,
6438 CODE_FOR_builtin_mskll,
6439 CODE_FOR_builtin_mskql,
6440 CODE_FOR_builtin_mskwh,
6441 CODE_FOR_builtin_msklh,
6442 CODE_FOR_builtin_mskqh,
6443 CODE_FOR_umuldi3_highpart,
6444 CODE_FOR_builtin_zap,
6445 CODE_FOR_builtin_zapnot,
6446 CODE_FOR_builtin_amask,
6447 CODE_FOR_builtin_implver,
6448 CODE_FOR_builtin_rpcc,
6453 CODE_FOR_builtin_minub8,
6454 CODE_FOR_builtin_minsb8,
6455 CODE_FOR_builtin_minuw4,
6456 CODE_FOR_builtin_minsw4,
6457 CODE_FOR_builtin_maxub8,
6458 CODE_FOR_builtin_maxsb8,
6459 CODE_FOR_builtin_maxuw4,
6460 CODE_FOR_builtin_maxsw4,
6461 CODE_FOR_builtin_perr,
6462 CODE_FOR_builtin_pklb,
6463 CODE_FOR_builtin_pkwb,
6464 CODE_FOR_builtin_unpkbl,
6465 CODE_FOR_builtin_unpkbw,
6468 CODE_FOR_builtin_cttz,
6469 CODE_FOR_builtin_ctlz,
6470 CODE_FOR_builtin_ctpop
6473 struct alpha_builtin_def
6476 enum alpha_builtin code;
6477 unsigned int target_mask;
6480 static struct alpha_builtin_def const zero_arg_builtins[] = {
6481 { "__builtin_alpha_implver", ALPHA_BUILTIN_IMPLVER, 0 },
6482 { "__builtin_alpha_rpcc", ALPHA_BUILTIN_RPCC, 0 }
6485 static struct alpha_builtin_def const one_arg_builtins[] = {
6486 { "__builtin_alpha_amask", ALPHA_BUILTIN_AMASK, 0 },
6487 { "__builtin_alpha_pklb", ALPHA_BUILTIN_PKLB, MASK_MAX },
6488 { "__builtin_alpha_pkwb", ALPHA_BUILTIN_PKWB, MASK_MAX },
6489 { "__builtin_alpha_unpkbl", ALPHA_BUILTIN_UNPKBL, MASK_MAX },
6490 { "__builtin_alpha_unpkbw", ALPHA_BUILTIN_UNPKBW, MASK_MAX },
6491 { "__builtin_alpha_cttz", ALPHA_BUILTIN_CTTZ, MASK_CIX },
6492 { "__builtin_alpha_ctlz", ALPHA_BUILTIN_CTLZ, MASK_CIX },
6493 { "__builtin_alpha_ctpop", ALPHA_BUILTIN_CTPOP, MASK_CIX }
6496 static struct alpha_builtin_def const two_arg_builtins[] = {
6497 { "__builtin_alpha_cmpbge", ALPHA_BUILTIN_CMPBGE, 0 },
6498 { "__builtin_alpha_extbl", ALPHA_BUILTIN_EXTBL, 0 },
6499 { "__builtin_alpha_extwl", ALPHA_BUILTIN_EXTWL, 0 },
6500 { "__builtin_alpha_extll", ALPHA_BUILTIN_EXTLL, 0 },
6501 { "__builtin_alpha_extql", ALPHA_BUILTIN_EXTQL, 0 },
6502 { "__builtin_alpha_extwh", ALPHA_BUILTIN_EXTWH, 0 },
6503 { "__builtin_alpha_extlh", ALPHA_BUILTIN_EXTLH, 0 },
6504 { "__builtin_alpha_extqh", ALPHA_BUILTIN_EXTQH, 0 },
6505 { "__builtin_alpha_insbl", ALPHA_BUILTIN_INSBL, 0 },
6506 { "__builtin_alpha_inswl", ALPHA_BUILTIN_INSWL, 0 },
6507 { "__builtin_alpha_insll", ALPHA_BUILTIN_INSLL, 0 },
6508 { "__builtin_alpha_insql", ALPHA_BUILTIN_INSQL, 0 },
6509 { "__builtin_alpha_inswh", ALPHA_BUILTIN_INSWH, 0 },
6510 { "__builtin_alpha_inslh", ALPHA_BUILTIN_INSLH, 0 },
6511 { "__builtin_alpha_insqh", ALPHA_BUILTIN_INSQH, 0 },
6512 { "__builtin_alpha_mskbl", ALPHA_BUILTIN_MSKBL, 0 },
6513 { "__builtin_alpha_mskwl", ALPHA_BUILTIN_MSKWL, 0 },
6514 { "__builtin_alpha_mskll", ALPHA_BUILTIN_MSKLL, 0 },
6515 { "__builtin_alpha_mskql", ALPHA_BUILTIN_MSKQL, 0 },
6516 { "__builtin_alpha_mskwh", ALPHA_BUILTIN_MSKWH, 0 },
6517 { "__builtin_alpha_msklh", ALPHA_BUILTIN_MSKLH, 0 },
6518 { "__builtin_alpha_mskqh", ALPHA_BUILTIN_MSKQH, 0 },
6519 { "__builtin_alpha_umulh", ALPHA_BUILTIN_UMULH, 0 },
6520 { "__builtin_alpha_zap", ALPHA_BUILTIN_ZAP, 0 },
6521 { "__builtin_alpha_zapnot", ALPHA_BUILTIN_ZAPNOT, 0 },
6522 { "__builtin_alpha_minub8", ALPHA_BUILTIN_MINUB8, MASK_MAX },
6523 { "__builtin_alpha_minsb8", ALPHA_BUILTIN_MINSB8, MASK_MAX },
6524 { "__builtin_alpha_minuw4", ALPHA_BUILTIN_MINUW4, MASK_MAX },
6525 { "__builtin_alpha_minsw4", ALPHA_BUILTIN_MINSW4, MASK_MAX },
6526 { "__builtin_alpha_maxub8", ALPHA_BUILTIN_MAXUB8, MASK_MAX },
6527 { "__builtin_alpha_maxsb8", ALPHA_BUILTIN_MAXSB8, MASK_MAX },
6528 { "__builtin_alpha_maxuw4", ALPHA_BUILTIN_MAXUW4, MASK_MAX },
6529 { "__builtin_alpha_maxsw4", ALPHA_BUILTIN_MAXSW4, MASK_MAX },
6530 { "__builtin_alpha_perr", ALPHA_BUILTIN_PERR, MASK_MAX }
6534 alpha_init_builtins ()
6536 const struct alpha_builtin_def *p;
6540 ftype = build_function_type (long_integer_type_node, void_list_node);
6542 p = zero_arg_builtins;
6543 for (i = 0; i < ARRAY_SIZE (zero_arg_builtins); ++i, ++p)
6544 if ((target_flags & p->target_mask) == p->target_mask)
6545 builtin_function (p->name, ftype, p->code, BUILT_IN_MD,
6548 ftype = build_function_type_list (long_integer_type_node,
6549 long_integer_type_node, NULL_TREE);
6551 p = one_arg_builtins;
6552 for (i = 0; i < ARRAY_SIZE (one_arg_builtins); ++i, ++p)
6553 if ((target_flags & p->target_mask) == p->target_mask)
6554 builtin_function (p->name, ftype, p->code, BUILT_IN_MD,
6557 ftype = build_function_type_list (long_integer_type_node,
6558 long_integer_type_node,
6559 long_integer_type_node, NULL_TREE);
6561 p = two_arg_builtins;
6562 for (i = 0; i < ARRAY_SIZE (two_arg_builtins); ++i, ++p)
6563 if ((target_flags & p->target_mask) == p->target_mask)
6564 builtin_function (p->name, ftype, p->code, BUILT_IN_MD,
6567 ftype = build_function_type (ptr_type_node, void_list_node);
6568 builtin_function ("__builtin_thread_pointer", ftype,
6569 ALPHA_BUILTIN_THREAD_POINTER, BUILT_IN_MD,
6572 ftype = build_function_type_list (void_type_node, ptr_type_node, NULL_TREE);
6573 builtin_function ("__builtin_set_thread_pointer", ftype,
6574 ALPHA_BUILTIN_SET_THREAD_POINTER, BUILT_IN_MD,
6578 /* Expand an expression EXP that calls a built-in function,
6579 with result going to TARGET if that's convenient
6580 (and in mode MODE if that's convenient).
6581 SUBTARGET may be used as the target for computing one of EXP's operands.
6582 IGNORE is nonzero if the value is to be ignored. */
6585 alpha_expand_builtin (exp, target, subtarget, mode, ignore)
6588 rtx subtarget ATTRIBUTE_UNUSED;
6589 enum machine_mode mode ATTRIBUTE_UNUSED;
6590 int ignore ATTRIBUTE_UNUSED;
6594 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6595 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6596 tree arglist = TREE_OPERAND (exp, 1);
6597 enum insn_code icode;
6598 rtx op[MAX_ARGS], pat;
6602 if (fcode >= ALPHA_BUILTIN_max)
6603 internal_error ("bad builtin fcode");
6604 icode = code_for_builtin[fcode];
6606 internal_error ("bad builtin fcode");
6608 nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
6610 for (arglist = TREE_OPERAND (exp, 1), arity = 0;
6612 arglist = TREE_CHAIN (arglist), arity++)
6614 const struct insn_operand_data *insn_op;
6616 tree arg = TREE_VALUE (arglist);
6617 if (arg == error_mark_node)
6619 if (arity > MAX_ARGS)
6622 insn_op = &insn_data[icode].operand[arity + nonvoid];
6624 op[arity] = expand_expr (arg, NULL_RTX, insn_op->mode, 0);
6626 if (!(*insn_op->predicate) (op[arity], insn_op->mode))
6627 op[arity] = copy_to_mode_reg (insn_op->mode, op[arity]);
6632 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6634 || GET_MODE (target) != tmode
6635 || !(*insn_data[icode].operand[0].predicate) (target, tmode))
6636 target = gen_reg_rtx (tmode);
6642 pat = GEN_FCN (icode) (target);
6646 pat = GEN_FCN (icode) (target, op[0]);
6648 pat = GEN_FCN (icode) (op[0]);
6651 pat = GEN_FCN (icode) (target, op[0], op[1]);
6666 /* This page contains routines that are used to determine what the function
6667 prologue and epilogue code will do and write them out. */
6669 /* Compute the size of the save area in the stack. */
6671 /* These variables are used for communication between the following functions.
6672 They indicate various things about the current function being compiled
6673 that are used to tell what kind of prologue, epilogue and procedure
6674 descriptior to generate. */
6676 /* Nonzero if we need a stack procedure. */
6677 enum alpha_procedure_types {PT_NULL = 0, PT_REGISTER = 1, PT_STACK = 2};
6678 static enum alpha_procedure_types alpha_procedure_type;
6680 /* Register number (either FP or SP) that is used to unwind the frame. */
6681 static int vms_unwind_regno;
6683 /* Register number used to save FP. We need not have one for RA since
6684 we don't modify it for register procedures. This is only defined
6685 for register frame procedures. */
6686 static int vms_save_fp_regno;
6688 /* Register number used to reference objects off our PV. */
6689 static int vms_base_regno;
6691 /* Compute register masks for saved registers. */
6694 alpha_sa_mask (imaskP, fmaskP)
6695 unsigned long *imaskP;
6696 unsigned long *fmaskP;
6698 unsigned long imask = 0;
6699 unsigned long fmask = 0;
6702 /* Irritatingly, there are two kinds of thunks -- those created with
6703 TARGET_ASM_OUTPUT_MI_THUNK and those with DECL_THUNK_P that go
6704 through the regular part of the compiler. In the
6705 TARGET_ASM_OUTPUT_MI_THUNK case we don't have valid register life
6706 info, but assemble_start_function wants to output .frame and
6707 .mask directives. */
6708 if (current_function_is_thunk && !no_new_pseudos)
6715 if (TARGET_ABI_OPEN_VMS && alpha_procedure_type == PT_STACK)
6716 imask |= (1L << HARD_FRAME_POINTER_REGNUM);
6718 /* One for every register we have to save. */
6719 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
6720 if (! fixed_regs[i] && ! call_used_regs[i]
6721 && regs_ever_live[i] && i != REG_RA
6722 && (!TARGET_ABI_UNICOSMK || i != HARD_FRAME_POINTER_REGNUM))
6727 fmask |= (1L << (i - 32));
6730 /* We need to restore these for the handler. */
6731 if (current_function_calls_eh_return)
6734 unsigned regno = EH_RETURN_DATA_REGNO (i);
6735 if (regno == INVALID_REGNUM)
6737 imask |= 1L << regno;
6740 /* If any register spilled, then spill the return address also. */
6741 /* ??? This is required by the Digital stack unwind specification
6742 and isn't needed if we're doing Dwarf2 unwinding. */
6743 if (imask || fmask || alpha_ra_ever_killed ())
6744 imask |= (1L << REG_RA);
6753 unsigned long mask[2];
6757 alpha_sa_mask (&mask[0], &mask[1]);
6759 if (TARGET_ABI_UNICOSMK)
6761 if (mask[0] || mask[1])
6766 for (j = 0; j < 2; ++j)
6767 for (i = 0; i < 32; ++i)
6768 if ((mask[j] >> i) & 1)
6772 if (TARGET_ABI_UNICOSMK)
6774 /* We might not need to generate a frame if we don't make any calls
6775 (including calls to __T3E_MISMATCH if this is a vararg function),
6776 don't have any local variables which require stack slots, don't
6777 use alloca and have not determined that we need a frame for other
6780 alpha_procedure_type
6781 = (sa_size || get_frame_size() != 0
6782 || current_function_outgoing_args_size
6783 || current_function_stdarg || current_function_calls_alloca
6784 || frame_pointer_needed)
6785 ? PT_STACK : PT_REGISTER;
6787 /* Always reserve space for saving callee-saved registers if we
6788 need a frame as required by the calling convention. */
6789 if (alpha_procedure_type == PT_STACK)
6792 else if (TARGET_ABI_OPEN_VMS)
6794 /* Start by assuming we can use a register procedure if we don't
6795 make any calls (REG_RA not used) or need to save any
6796 registers and a stack procedure if we do. */
6797 if ((mask[0] >> REG_RA) & 1)
6798 alpha_procedure_type = PT_STACK;
6799 else if (get_frame_size() != 0)
6800 alpha_procedure_type = PT_REGISTER;
6802 alpha_procedure_type = PT_NULL;
6804 /* Don't reserve space for saving FP & RA yet. Do that later after we've
6805 made the final decision on stack procedure vs register procedure. */
6806 if (alpha_procedure_type == PT_STACK)
6809 /* Decide whether to refer to objects off our PV via FP or PV.
6810 If we need FP for something else or if we receive a nonlocal
6811 goto (which expects PV to contain the value), we must use PV.
6812 Otherwise, start by assuming we can use FP. */
6815 = (frame_pointer_needed
6816 || current_function_has_nonlocal_label
6817 || alpha_procedure_type == PT_STACK
6818 || current_function_outgoing_args_size)
6819 ? REG_PV : HARD_FRAME_POINTER_REGNUM;
6821 /* If we want to copy PV into FP, we need to find some register
6822 in which to save FP. */
6824 vms_save_fp_regno = -1;
6825 if (vms_base_regno == HARD_FRAME_POINTER_REGNUM)
6826 for (i = 0; i < 32; i++)
6827 if (! fixed_regs[i] && call_used_regs[i] && ! regs_ever_live[i])
6828 vms_save_fp_regno = i;
6830 if (vms_save_fp_regno == -1 && alpha_procedure_type == PT_REGISTER)
6831 vms_base_regno = REG_PV, alpha_procedure_type = PT_STACK;
6832 else if (alpha_procedure_type == PT_NULL)
6833 vms_base_regno = REG_PV;
6835 /* Stack unwinding should be done via FP unless we use it for PV. */
6836 vms_unwind_regno = (vms_base_regno == REG_PV
6837 ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM);
6839 /* If this is a stack procedure, allow space for saving FP and RA. */
6840 if (alpha_procedure_type == PT_STACK)
6845 /* Our size must be even (multiple of 16 bytes). */
6854 alpha_pv_save_size ()
6857 return alpha_procedure_type == PT_STACK ? 8 : 0;
6864 return vms_unwind_regno == HARD_FRAME_POINTER_REGNUM;
6867 #if TARGET_ABI_OPEN_VMS
6869 const struct attribute_spec vms_attribute_table[] =
6871 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
6872 { "overlaid", 0, 0, true, false, false, NULL },
6873 { "global", 0, 0, true, false, false, NULL },
6874 { "initialize", 0, 0, true, false, false, NULL },
6875 { NULL, 0, 0, false, false, false, NULL }
6881 find_lo_sum (px, data)
6883 void *data ATTRIBUTE_UNUSED;
6885 return GET_CODE (*px) == LO_SUM;
6889 alpha_does_function_need_gp ()
6893 /* The GP being variable is an OSF abi thing. */
6894 if (! TARGET_ABI_OSF)
6897 if (TARGET_PROFILING_NEEDS_GP && current_function_profile)
6900 if (current_function_is_thunk)
6903 /* If we need a GP (we have a LDSYM insn or a CALL_INSN), load it first.
6904 Even if we are a static function, we still need to do this in case
6905 our address is taken and passed to something like qsort. */
6907 push_topmost_sequence ();
6908 insn = get_insns ();
6909 pop_topmost_sequence ();
6911 for (; insn; insn = NEXT_INSN (insn))
6913 && GET_CODE (PATTERN (insn)) != USE
6914 && GET_CODE (PATTERN (insn)) != CLOBBER)
6916 enum attr_type type = get_attr_type (insn);
6917 if (type == TYPE_LDSYM || type == TYPE_JSR)
6919 if (TARGET_EXPLICIT_RELOCS
6920 && for_each_rtx (&PATTERN (insn), find_lo_sum, NULL) > 0)
6927 /* Write a version stamp. Don't write anything if we are running as a
6928 cross-compiler. Otherwise, use the versions in /usr/include/stamp.h. */
6935 alpha_write_verstamp (file)
6936 FILE *file ATTRIBUTE_UNUSED;
6939 fprintf (file, "\t.verstamp %d %d\n", MS_STAMP, LS_STAMP);
6943 /* Helper function to set RTX_FRAME_RELATED_P on instructions, including
6947 set_frame_related_p ()
6949 rtx seq = get_insns ();
6960 while (insn != NULL_RTX)
6962 RTX_FRAME_RELATED_P (insn) = 1;
6963 insn = NEXT_INSN (insn);
6965 seq = emit_insn (seq);
6969 seq = emit_insn (seq);
6970 RTX_FRAME_RELATED_P (seq) = 1;
6975 #define FRP(exp) (start_sequence (), exp, set_frame_related_p ())
6977 /* Write function prologue. */
6979 /* On vms we have two kinds of functions:
6981 - stack frame (PROC_STACK)
6982 these are 'normal' functions with local vars and which are
6983 calling other functions
6984 - register frame (PROC_REGISTER)
6985 keeps all data in registers, needs no stack
6987 We must pass this to the assembler so it can generate the
6988 proper pdsc (procedure descriptor)
6989 This is done with the '.pdesc' command.
6991 On not-vms, we don't really differentiate between the two, as we can
6992 simply allocate stack without saving registers. */
6995 alpha_expand_prologue ()
6997 /* Registers to save. */
6998 unsigned long imask = 0;
6999 unsigned long fmask = 0;
7000 /* Stack space needed for pushing registers clobbered by us. */
7001 HOST_WIDE_INT sa_size;
7002 /* Complete stack size needed. */
7003 HOST_WIDE_INT frame_size;
7004 /* Offset from base reg to register save area. */
7005 HOST_WIDE_INT reg_offset;
7009 sa_size = alpha_sa_size ();
7011 frame_size = get_frame_size ();
7012 if (TARGET_ABI_OPEN_VMS)
7013 frame_size = ALPHA_ROUND (sa_size
7014 + (alpha_procedure_type == PT_STACK ? 8 : 0)
7016 + current_function_pretend_args_size);
7017 else if (TARGET_ABI_UNICOSMK)
7018 /* We have to allocate space for the DSIB if we generate a frame. */
7019 frame_size = ALPHA_ROUND (sa_size
7020 + (alpha_procedure_type == PT_STACK ? 48 : 0))
7021 + ALPHA_ROUND (frame_size
7022 + current_function_outgoing_args_size);
7024 frame_size = (ALPHA_ROUND (current_function_outgoing_args_size)
7026 + ALPHA_ROUND (frame_size
7027 + current_function_pretend_args_size));
7029 if (TARGET_ABI_OPEN_VMS)
7032 reg_offset = ALPHA_ROUND (current_function_outgoing_args_size);
7034 alpha_sa_mask (&imask, &fmask);
7036 /* Emit an insn to reload GP, if needed. */
7039 alpha_function_needs_gp = alpha_does_function_need_gp ();
7040 if (alpha_function_needs_gp)
7041 emit_insn (gen_prologue_ldgp ());
7044 /* TARGET_PROFILING_NEEDS_GP actually implies that we need to insert
7045 the call to mcount ourselves, rather than having the linker do it
7046 magically in response to -pg. Since _mcount has special linkage,
7047 don't represent the call as a call. */
7048 if (TARGET_PROFILING_NEEDS_GP && current_function_profile)
7049 emit_insn (gen_prologue_mcount ());
7051 if (TARGET_ABI_UNICOSMK)
7052 unicosmk_gen_dsib (&imask);
7054 /* Adjust the stack by the frame size. If the frame size is > 4096
7055 bytes, we need to be sure we probe somewhere in the first and last
7056 4096 bytes (we can probably get away without the latter test) and
7057 every 8192 bytes in between. If the frame size is > 32768, we
7058 do this in a loop. Otherwise, we generate the explicit probe
7061 Note that we are only allowed to adjust sp once in the prologue. */
7063 if (frame_size <= 32768)
7065 if (frame_size > 4096)
7070 emit_insn (gen_probe_stack (GEN_INT (TARGET_ABI_UNICOSMK
7073 while ((probed += 8192) < frame_size);
7075 /* We only have to do this probe if we aren't saving registers. */
7076 if (sa_size == 0 && probed + 4096 < frame_size)
7077 emit_insn (gen_probe_stack (GEN_INT (-frame_size)));
7080 if (frame_size != 0)
7081 FRP (emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx,
7082 GEN_INT (TARGET_ABI_UNICOSMK
7088 /* Here we generate code to set R22 to SP + 4096 and set R23 to the
7089 number of 8192 byte blocks to probe. We then probe each block
7090 in the loop and then set SP to the proper location. If the
7091 amount remaining is > 4096, we have to do one more probe if we
7092 are not saving any registers. */
7094 HOST_WIDE_INT blocks = (frame_size + 4096) / 8192;
7095 HOST_WIDE_INT leftover = frame_size + 4096 - blocks * 8192;
7096 rtx ptr = gen_rtx_REG (DImode, 22);
7097 rtx count = gen_rtx_REG (DImode, 23);
7100 emit_move_insn (count, GEN_INT (blocks));
7101 emit_insn (gen_adddi3 (ptr, stack_pointer_rtx,
7102 GEN_INT (TARGET_ABI_UNICOSMK ? 4096 - 64 : 4096)));
7104 /* Because of the difficulty in emitting a new basic block this
7105 late in the compilation, generate the loop as a single insn. */
7106 emit_insn (gen_prologue_stack_probe_loop (count, ptr));
7108 if (leftover > 4096 && sa_size == 0)
7110 rtx last = gen_rtx_MEM (DImode, plus_constant (ptr, -leftover));
7111 MEM_VOLATILE_P (last) = 1;
7112 emit_move_insn (last, const0_rtx);
7115 if (TARGET_ABI_WINDOWS_NT)
7117 /* For NT stack unwind (done by 'reverse execution'), it's
7118 not OK to take the result of a loop, even though the value
7119 is already in ptr, so we reload it via a single operation
7120 and subtract it to sp.
7122 Yes, that's correct -- we have to reload the whole constant
7123 into a temporary via ldah+lda then subtract from sp. To
7124 ensure we get ldah+lda, we use a special pattern. */
7126 HOST_WIDE_INT lo, hi;
7127 lo = ((frame_size & 0xffff) ^ 0x8000) - 0x8000;
7128 hi = frame_size - lo;
7130 emit_move_insn (ptr, GEN_INT (hi));
7131 emit_insn (gen_nt_lda (ptr, GEN_INT (lo)));
7132 seq = emit_insn (gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx,
7137 seq = emit_insn (gen_adddi3 (stack_pointer_rtx, ptr,
7138 GEN_INT (-leftover)));
7141 /* This alternative is special, because the DWARF code cannot
7142 possibly intuit through the loop above. So we invent this
7143 note it looks at instead. */
7144 RTX_FRAME_RELATED_P (seq) = 1;
7146 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
7147 gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7148 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
7149 GEN_INT (TARGET_ABI_UNICOSMK
7155 if (!TARGET_ABI_UNICOSMK)
7157 /* Cope with very large offsets to the register save area. */
7158 sa_reg = stack_pointer_rtx;
7159 if (reg_offset + sa_size > 0x8000)
7161 int low = ((reg_offset & 0xffff) ^ 0x8000) - 0x8000;
7164 if (low + sa_size <= 0x8000)
7165 bias = reg_offset - low, reg_offset = low;
7167 bias = reg_offset, reg_offset = 0;
7169 sa_reg = gen_rtx_REG (DImode, 24);
7170 FRP (emit_insn (gen_adddi3 (sa_reg, stack_pointer_rtx,
7174 /* Save regs in stack order. Beginning with VMS PV. */
7175 if (TARGET_ABI_OPEN_VMS && alpha_procedure_type == PT_STACK)
7177 mem = gen_rtx_MEM (DImode, stack_pointer_rtx);
7178 set_mem_alias_set (mem, alpha_sr_alias_set);
7179 FRP (emit_move_insn (mem, gen_rtx_REG (DImode, REG_PV)));
7182 /* Save register RA next. */
7183 if (imask & (1L << REG_RA))
7185 mem = gen_rtx_MEM (DImode, plus_constant (sa_reg, reg_offset));
7186 set_mem_alias_set (mem, alpha_sr_alias_set);
7187 FRP (emit_move_insn (mem, gen_rtx_REG (DImode, REG_RA)));
7188 imask &= ~(1L << REG_RA);
7192 /* Now save any other registers required to be saved. */
7193 for (i = 0; i < 32; i++)
7194 if (imask & (1L << i))
7196 mem = gen_rtx_MEM (DImode, plus_constant (sa_reg, reg_offset));
7197 set_mem_alias_set (mem, alpha_sr_alias_set);
7198 FRP (emit_move_insn (mem, gen_rtx_REG (DImode, i)));
7202 for (i = 0; i < 32; i++)
7203 if (fmask & (1L << i))
7205 mem = gen_rtx_MEM (DFmode, plus_constant (sa_reg, reg_offset));
7206 set_mem_alias_set (mem, alpha_sr_alias_set);
7207 FRP (emit_move_insn (mem, gen_rtx_REG (DFmode, i+32)));
7211 else if (TARGET_ABI_UNICOSMK && alpha_procedure_type == PT_STACK)
7213 /* The standard frame on the T3E includes space for saving registers.
7214 We just have to use it. We don't have to save the return address and
7215 the old frame pointer here - they are saved in the DSIB. */
7218 for (i = 9; i < 15; i++)
7219 if (imask & (1L << i))
7221 mem = gen_rtx_MEM (DImode, plus_constant(hard_frame_pointer_rtx,
7223 set_mem_alias_set (mem, alpha_sr_alias_set);
7224 FRP (emit_move_insn (mem, gen_rtx_REG (DImode, i)));
7227 for (i = 2; i < 10; i++)
7228 if (fmask & (1L << i))
7230 mem = gen_rtx_MEM (DFmode, plus_constant (hard_frame_pointer_rtx,
7232 set_mem_alias_set (mem, alpha_sr_alias_set);
7233 FRP (emit_move_insn (mem, gen_rtx_REG (DFmode, i+32)));
7238 if (TARGET_ABI_OPEN_VMS)
7240 if (alpha_procedure_type == PT_REGISTER)
7241 /* Register frame procedures save the fp.
7242 ?? Ought to have a dwarf2 save for this. */
7243 emit_move_insn (gen_rtx_REG (DImode, vms_save_fp_regno),
7244 hard_frame_pointer_rtx);
7246 if (alpha_procedure_type != PT_NULL && vms_base_regno != REG_PV)
7247 emit_insn (gen_force_movdi (gen_rtx_REG (DImode, vms_base_regno),
7248 gen_rtx_REG (DImode, REG_PV)));
7250 if (alpha_procedure_type != PT_NULL
7251 && vms_unwind_regno == HARD_FRAME_POINTER_REGNUM)
7252 FRP (emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx));
7254 /* If we have to allocate space for outgoing args, do it now. */
7255 if (current_function_outgoing_args_size != 0)
7258 plus_constant (hard_frame_pointer_rtx,
7260 (current_function_outgoing_args_size)))));
7262 else if (!TARGET_ABI_UNICOSMK)
7264 /* If we need a frame pointer, set it from the stack pointer. */
7265 if (frame_pointer_needed)
7267 if (TARGET_CAN_FAULT_IN_PROLOGUE)
7268 FRP (emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx));
7270 /* This must always be the last instruction in the
7271 prologue, thus we emit a special move + clobber. */
7272 FRP (emit_insn (gen_init_fp (hard_frame_pointer_rtx,
7273 stack_pointer_rtx, sa_reg)));
7277 /* The ABIs for VMS and OSF/1 say that while we can schedule insns into
7278 the prologue, for exception handling reasons, we cannot do this for
7279 any insn that might fault. We could prevent this for mems with a
7280 (clobber:BLK (scratch)), but this doesn't work for fp insns. So we
7281 have to prevent all such scheduling with a blockage.
7283 Linux, on the other hand, never bothered to implement OSF/1's
7284 exception handling, and so doesn't care about such things. Anyone
7285 planning to use dwarf2 frame-unwind info can also omit the blockage. */
7287 if (! TARGET_CAN_FAULT_IN_PROLOGUE)
7288 emit_insn (gen_blockage ());
7291 /* Output the textual info surrounding the prologue. */
7294 alpha_start_function (file, fnname, decl)
7297 tree decl ATTRIBUTE_UNUSED;
7299 unsigned long imask = 0;
7300 unsigned long fmask = 0;
7301 /* Stack space needed for pushing registers clobbered by us. */
7302 HOST_WIDE_INT sa_size;
7303 /* Complete stack size needed. */
7304 HOST_WIDE_INT frame_size;
7305 /* Offset from base reg to register save area. */
7306 HOST_WIDE_INT reg_offset;
7307 char *entry_label = (char *) alloca (strlen (fnname) + 6);
7310 /* Don't emit an extern directive for functions defined in the same file. */
7311 if (TARGET_ABI_UNICOSMK)
7314 name_tree = get_identifier (fnname);
7315 TREE_ASM_WRITTEN (name_tree) = 1;
7318 alpha_fnname = fnname;
7319 sa_size = alpha_sa_size ();
7321 frame_size = get_frame_size ();
7322 if (TARGET_ABI_OPEN_VMS)
7323 frame_size = ALPHA_ROUND (sa_size
7324 + (alpha_procedure_type == PT_STACK ? 8 : 0)
7326 + current_function_pretend_args_size);
7327 else if (TARGET_ABI_UNICOSMK)
7328 frame_size = ALPHA_ROUND (sa_size
7329 + (alpha_procedure_type == PT_STACK ? 48 : 0))
7330 + ALPHA_ROUND (frame_size
7331 + current_function_outgoing_args_size);
7333 frame_size = (ALPHA_ROUND (current_function_outgoing_args_size)
7335 + ALPHA_ROUND (frame_size
7336 + current_function_pretend_args_size));
7338 if (TARGET_ABI_OPEN_VMS)
7341 reg_offset = ALPHA_ROUND (current_function_outgoing_args_size);
7343 alpha_sa_mask (&imask, &fmask);
7345 /* Ecoff can handle multiple .file directives, so put out file and lineno.
7346 We have to do that before the .ent directive as we cannot switch
7347 files within procedures with native ecoff because line numbers are
7348 linked to procedure descriptors.
7349 Outputting the lineno helps debugging of one line functions as they
7350 would otherwise get no line number at all. Please note that we would
7351 like to put out last_linenum from final.c, but it is not accessible. */
7353 if (write_symbols == SDB_DEBUG)
7355 #ifdef ASM_OUTPUT_SOURCE_FILENAME
7356 ASM_OUTPUT_SOURCE_FILENAME (file,
7357 DECL_SOURCE_FILE (current_function_decl));
7359 #ifdef ASM_OUTPUT_SOURCE_LINE
7360 if (debug_info_level != DINFO_LEVEL_TERSE)
7361 ASM_OUTPUT_SOURCE_LINE (file,
7362 DECL_SOURCE_LINE (current_function_decl));
7366 /* Issue function start and label. */
7367 if (TARGET_ABI_OPEN_VMS
7368 || (!TARGET_ABI_UNICOSMK && !flag_inhibit_size_directive))
7370 fputs ("\t.ent ", file);
7371 assemble_name (file, fnname);
7374 /* If the function needs GP, we'll write the "..ng" label there.
7375 Otherwise, do it here. */
7377 && ! alpha_function_needs_gp
7378 && ! current_function_is_thunk)
7381 assemble_name (file, fnname);
7382 fputs ("..ng:\n", file);
7386 strcpy (entry_label, fnname);
7387 if (TARGET_ABI_OPEN_VMS)
7388 strcat (entry_label, "..en");
7390 /* For public functions, the label must be globalized by appending an
7391 additional colon. */
7392 if (TARGET_ABI_UNICOSMK && TREE_PUBLIC (decl))
7393 strcat (entry_label, ":");
7395 ASM_OUTPUT_LABEL (file, entry_label);
7396 inside_function = TRUE;
7398 if (TARGET_ABI_OPEN_VMS)
7399 fprintf (file, "\t.base $%d\n", vms_base_regno);
7401 if (!TARGET_ABI_OPEN_VMS && !TARGET_ABI_UNICOSMK && TARGET_IEEE_CONFORMANT
7402 && !flag_inhibit_size_directive)
7404 /* Set flags in procedure descriptor to request IEEE-conformant
7405 math-library routines. The value we set it to is PDSC_EXC_IEEE
7406 (/usr/include/pdsc.h). */
7407 fputs ("\t.eflag 48\n", file);
7410 /* Set up offsets to alpha virtual arg/local debugging pointer. */
7411 alpha_auto_offset = -frame_size + current_function_pretend_args_size;
7412 alpha_arg_offset = -frame_size + 48;
7414 /* Describe our frame. If the frame size is larger than an integer,
7415 print it as zero to avoid an assembler error. We won't be
7416 properly describing such a frame, but that's the best we can do. */
7417 if (TARGET_ABI_UNICOSMK)
7419 else if (TARGET_ABI_OPEN_VMS)
7421 fprintf (file, "\t.frame $%d,", vms_unwind_regno);
7422 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
7423 frame_size >= ((HOST_WIDE_INT) 1 << 31) ? 0 : frame_size);
7424 fputs (",$26,", file);
7425 fprintf (file, HOST_WIDE_INT_PRINT_DEC, reg_offset);
7428 else if (!flag_inhibit_size_directive)
7430 fprintf (file, "\t.frame $%d,",
7431 (frame_pointer_needed
7432 ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM));
7433 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
7434 frame_size >= (1l << 31) ? 0 : frame_size);
7435 fprintf (file, ",$26,%d\n", current_function_pretend_args_size);
7438 /* Describe which registers were spilled. */
7439 if (TARGET_ABI_UNICOSMK)
7441 else if (TARGET_ABI_OPEN_VMS)
7444 /* ??? Does VMS care if mask contains ra? The old code didn't
7445 set it, so I don't here. */
7446 fprintf (file, "\t.mask 0x%lx,0\n", imask & ~(1L << REG_RA));
7448 fprintf (file, "\t.fmask 0x%lx,0\n", fmask);
7449 if (alpha_procedure_type == PT_REGISTER)
7450 fprintf (file, "\t.fp_save $%d\n", vms_save_fp_regno);
7452 else if (!flag_inhibit_size_directive)
7456 fprintf (file, "\t.mask 0x%lx,", imask);
7457 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
7458 frame_size >= (1l << 31) ? 0 : reg_offset - frame_size);
7461 for (i = 0; i < 32; ++i)
7462 if (imask & (1L << i))
7468 fprintf (file, "\t.fmask 0x%lx,", fmask);
7469 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
7470 frame_size >= (1l << 31) ? 0 : reg_offset - frame_size);
7475 #if TARGET_ABI_OPEN_VMS
7476 /* Ifdef'ed cause link_section are only available then. */
7477 readonly_data_section ();
7478 fprintf (file, "\t.align 3\n");
7479 assemble_name (file, fnname); fputs ("..na:\n", file);
7480 fputs ("\t.ascii \"", file);
7481 assemble_name (file, fnname);
7482 fputs ("\\0\"\n", file);
7483 alpha_need_linkage (fnname, 1);
7488 /* Emit the .prologue note at the scheduled end of the prologue. */
7491 alpha_output_function_end_prologue (file)
7494 if (TARGET_ABI_UNICOSMK)
7496 else if (TARGET_ABI_OPEN_VMS)
7497 fputs ("\t.prologue\n", file);
7498 else if (TARGET_ABI_WINDOWS_NT)
7499 fputs ("\t.prologue 0\n", file);
7500 else if (!flag_inhibit_size_directive)
7501 fprintf (file, "\t.prologue %d\n",
7502 alpha_function_needs_gp || current_function_is_thunk);
7505 /* Write function epilogue. */
7507 /* ??? At some point we will want to support full unwind, and so will
7508 need to mark the epilogue as well. At the moment, we just confuse
7511 #define FRP(exp) exp
7514 alpha_expand_epilogue ()
7516 /* Registers to save. */
7517 unsigned long imask = 0;
7518 unsigned long fmask = 0;
7519 /* Stack space needed for pushing registers clobbered by us. */
7520 HOST_WIDE_INT sa_size;
7521 /* Complete stack size needed. */
7522 HOST_WIDE_INT frame_size;
7523 /* Offset from base reg to register save area. */
7524 HOST_WIDE_INT reg_offset;
7525 int fp_is_frame_pointer, fp_offset;
7526 rtx sa_reg, sa_reg_exp = NULL;
7527 rtx sp_adj1, sp_adj2, mem;
7531 sa_size = alpha_sa_size ();
7533 frame_size = get_frame_size ();
7534 if (TARGET_ABI_OPEN_VMS)
7535 frame_size = ALPHA_ROUND (sa_size
7536 + (alpha_procedure_type == PT_STACK ? 8 : 0)
7538 + current_function_pretend_args_size);
7539 else if (TARGET_ABI_UNICOSMK)
7540 frame_size = ALPHA_ROUND (sa_size
7541 + (alpha_procedure_type == PT_STACK ? 48 : 0))
7542 + ALPHA_ROUND (frame_size
7543 + current_function_outgoing_args_size);
7545 frame_size = (ALPHA_ROUND (current_function_outgoing_args_size)
7547 + ALPHA_ROUND (frame_size
7548 + current_function_pretend_args_size));
7550 if (TARGET_ABI_OPEN_VMS)
7552 if (alpha_procedure_type == PT_STACK)
7558 reg_offset = ALPHA_ROUND (current_function_outgoing_args_size);
7560 alpha_sa_mask (&imask, &fmask);
7563 = ((TARGET_ABI_OPEN_VMS && alpha_procedure_type == PT_STACK)
7564 || (!TARGET_ABI_OPEN_VMS && frame_pointer_needed));
7566 sa_reg = stack_pointer_rtx;
7568 if (current_function_calls_eh_return)
7569 eh_ofs = EH_RETURN_STACKADJ_RTX;
7573 if (!TARGET_ABI_UNICOSMK && sa_size)
7575 /* If we have a frame pointer, restore SP from it. */
7576 if ((TARGET_ABI_OPEN_VMS
7577 && vms_unwind_regno == HARD_FRAME_POINTER_REGNUM)
7578 || (!TARGET_ABI_OPEN_VMS && frame_pointer_needed))
7579 FRP (emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx));
7581 /* Cope with very large offsets to the register save area. */
7582 if (reg_offset + sa_size > 0x8000)
7584 int low = ((reg_offset & 0xffff) ^ 0x8000) - 0x8000;
7587 if (low + sa_size <= 0x8000)
7588 bias = reg_offset - low, reg_offset = low;
7590 bias = reg_offset, reg_offset = 0;
7592 sa_reg = gen_rtx_REG (DImode, 22);
7593 sa_reg_exp = plus_constant (stack_pointer_rtx, bias);
7595 FRP (emit_move_insn (sa_reg, sa_reg_exp));
7598 /* Restore registers in order, excepting a true frame pointer. */
7600 mem = gen_rtx_MEM (DImode, plus_constant (sa_reg, reg_offset));
7602 set_mem_alias_set (mem, alpha_sr_alias_set);
7603 FRP (emit_move_insn (gen_rtx_REG (DImode, REG_RA), mem));
7606 imask &= ~(1L << REG_RA);
7608 for (i = 0; i < 32; ++i)
7609 if (imask & (1L << i))
7611 if (i == HARD_FRAME_POINTER_REGNUM && fp_is_frame_pointer)
7612 fp_offset = reg_offset;
7615 mem = gen_rtx_MEM (DImode, plus_constant(sa_reg, reg_offset));
7616 set_mem_alias_set (mem, alpha_sr_alias_set);
7617 FRP (emit_move_insn (gen_rtx_REG (DImode, i), mem));
7622 for (i = 0; i < 32; ++i)
7623 if (fmask & (1L << i))
7625 mem = gen_rtx_MEM (DFmode, plus_constant(sa_reg, reg_offset));
7626 set_mem_alias_set (mem, alpha_sr_alias_set);
7627 FRP (emit_move_insn (gen_rtx_REG (DFmode, i+32), mem));
7631 else if (TARGET_ABI_UNICOSMK && alpha_procedure_type == PT_STACK)
7633 /* Restore callee-saved general-purpose registers. */
7637 for (i = 9; i < 15; i++)
7638 if (imask & (1L << i))
7640 mem = gen_rtx_MEM (DImode, plus_constant(hard_frame_pointer_rtx,
7642 set_mem_alias_set (mem, alpha_sr_alias_set);
7643 FRP (emit_move_insn (gen_rtx_REG (DImode, i), mem));
7647 for (i = 2; i < 10; i++)
7648 if (fmask & (1L << i))
7650 mem = gen_rtx_MEM (DFmode, plus_constant(hard_frame_pointer_rtx,
7652 set_mem_alias_set (mem, alpha_sr_alias_set);
7653 FRP (emit_move_insn (gen_rtx_REG (DFmode, i+32), mem));
7657 /* Restore the return address from the DSIB. */
7659 mem = gen_rtx_MEM (DImode, plus_constant(hard_frame_pointer_rtx, -8));
7660 set_mem_alias_set (mem, alpha_sr_alias_set);
7661 FRP (emit_move_insn (gen_rtx_REG (DImode, REG_RA), mem));
7664 if (frame_size || eh_ofs)
7666 sp_adj1 = stack_pointer_rtx;
7670 sp_adj1 = gen_rtx_REG (DImode, 23);
7671 emit_move_insn (sp_adj1,
7672 gen_rtx_PLUS (Pmode, stack_pointer_rtx, eh_ofs));
7675 /* If the stack size is large, begin computation into a temporary
7676 register so as not to interfere with a potential fp restore,
7677 which must be consecutive with an SP restore. */
7678 if (frame_size < 32768
7679 && ! (TARGET_ABI_UNICOSMK && current_function_calls_alloca))
7680 sp_adj2 = GEN_INT (frame_size);
7681 else if (TARGET_ABI_UNICOSMK)
7683 sp_adj1 = gen_rtx_REG (DImode, 23);
7684 FRP (emit_move_insn (sp_adj1, hard_frame_pointer_rtx));
7685 sp_adj2 = const0_rtx;
7687 else if (frame_size < 0x40007fffL)
7689 int low = ((frame_size & 0xffff) ^ 0x8000) - 0x8000;
7691 sp_adj2 = plus_constant (sp_adj1, frame_size - low);
7692 if (sa_reg_exp && rtx_equal_p (sa_reg_exp, sp_adj2))
7696 sp_adj1 = gen_rtx_REG (DImode, 23);
7697 FRP (emit_move_insn (sp_adj1, sp_adj2));
7699 sp_adj2 = GEN_INT (low);
7703 rtx tmp = gen_rtx_REG (DImode, 23);
7704 FRP (sp_adj2 = alpha_emit_set_const (tmp, DImode, frame_size, 3));
7707 /* We can't drop new things to memory this late, afaik,
7708 so build it up by pieces. */
7709 FRP (sp_adj2 = alpha_emit_set_long_const (tmp, frame_size,
7710 -(frame_size < 0)));
7716 /* From now on, things must be in order. So emit blockages. */
7718 /* Restore the frame pointer. */
7719 if (TARGET_ABI_UNICOSMK)
7721 emit_insn (gen_blockage ());
7722 mem = gen_rtx_MEM (DImode,
7723 plus_constant (hard_frame_pointer_rtx, -16));
7724 set_mem_alias_set (mem, alpha_sr_alias_set);
7725 FRP (emit_move_insn (hard_frame_pointer_rtx, mem));
7727 else if (fp_is_frame_pointer)
7729 emit_insn (gen_blockage ());
7730 mem = gen_rtx_MEM (DImode, plus_constant (sa_reg, fp_offset));
7731 set_mem_alias_set (mem, alpha_sr_alias_set);
7732 FRP (emit_move_insn (hard_frame_pointer_rtx, mem));
7734 else if (TARGET_ABI_OPEN_VMS)
7736 emit_insn (gen_blockage ());
7737 FRP (emit_move_insn (hard_frame_pointer_rtx,
7738 gen_rtx_REG (DImode, vms_save_fp_regno)));
7741 /* Restore the stack pointer. */
7742 emit_insn (gen_blockage ());
7743 if (sp_adj2 == const0_rtx)
7744 FRP (emit_move_insn (stack_pointer_rtx, sp_adj1));
7746 FRP (emit_move_insn (stack_pointer_rtx,
7747 gen_rtx_PLUS (DImode, sp_adj1, sp_adj2)));
7751 if (TARGET_ABI_OPEN_VMS && alpha_procedure_type == PT_REGISTER)
7753 emit_insn (gen_blockage ());
7754 FRP (emit_move_insn (hard_frame_pointer_rtx,
7755 gen_rtx_REG (DImode, vms_save_fp_regno)));
7757 else if (TARGET_ABI_UNICOSMK && alpha_procedure_type != PT_STACK)
7759 /* Decrement the frame pointer if the function does not have a
7762 emit_insn (gen_blockage ());
7763 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
7764 hard_frame_pointer_rtx, GEN_INT (-1))));
7769 #if TARGET_ABI_OPEN_VMS
7770 #include <splay-tree.h>
7772 /* Structure to collect function names for final output
7775 enum links_kind {KIND_UNUSED, KIND_LOCAL, KIND_EXTERN};
7776 enum reloc_kind {KIND_LINKAGE, KIND_CODEADDR};
7788 enum links_kind lkind;
7789 enum reloc_kind rkind;
7792 static splay_tree alpha_funcs_tree;
7793 static splay_tree alpha_links_tree;
7795 static int mark_alpha_links_node PARAMS ((splay_tree_node, void *));
7796 static void mark_alpha_links PARAMS ((void *));
7797 static int alpha_write_one_linkage PARAMS ((splay_tree_node, void *));
7799 static int alpha_funcs_num;
7802 /* Output the rest of the textual info surrounding the epilogue. */
7805 alpha_end_function (file, fnname, decl)
7810 /* End the function. */
7811 if (!TARGET_ABI_UNICOSMK && !flag_inhibit_size_directive)
7813 fputs ("\t.end ", file);
7814 assemble_name (file, fnname);
7817 inside_function = FALSE;
7819 #if TARGET_ABI_OPEN_VMS
7820 alpha_write_linkage (file, fnname, decl);
7823 /* Show that we know this function if it is called again.
7825 Do this only for functions whose symbols bind locally.
7827 Don't do this for functions not defined in the .text section, as
7828 otherwise it's not unlikely that the destination is out of range
7829 for a direct branch. */
7831 if ((*targetm.binds_local_p) (decl) && decl_in_text_section (decl))
7832 SYMBOL_REF_FLAG (XEXP (DECL_RTL (decl), 0)) = 1;
7834 /* Output jump tables and the static subroutine information block. */
7835 if (TARGET_ABI_UNICOSMK)
7837 unicosmk_output_ssib (file, fnname);
7838 unicosmk_output_deferred_case_vectors (file);
7842 /* Emit a tail call to FUNCTION after adjusting THIS by DELTA.
7844 In order to avoid the hordes of differences between generated code
7845 with and without TARGET_EXPLICIT_RELOCS, and to avoid duplicating
7846 lots of code loading up large constants, generate rtl and emit it
7847 instead of going straight to text.
7849 Not sure why this idea hasn't been explored before... */
7852 alpha_output_mi_thunk_osf (file, thunk_fndecl, delta, function)
7854 tree thunk_fndecl ATTRIBUTE_UNUSED;
7855 HOST_WIDE_INT delta;
7858 HOST_WIDE_INT hi, lo;
7859 rtx this, insn, funexp;
7861 /* We always require a valid GP. */
7862 emit_insn (gen_prologue_ldgp ());
7863 emit_note (NULL, NOTE_INSN_PROLOGUE_END);
7865 /* Find the "this" pointer. If the function returns a structure,
7866 the structure return pointer is in $16. */
7867 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function))))
7868 this = gen_rtx_REG (Pmode, 17);
7870 this = gen_rtx_REG (Pmode, 16);
7872 /* Add DELTA. When possible we use ldah+lda. Otherwise load the
7873 entire constant for the add. */
7874 lo = ((delta & 0xffff) ^ 0x8000) - 0x8000;
7875 hi = (((delta - lo) & 0xffffffff) ^ 0x80000000) - 0x80000000;
7876 if (hi + lo == delta)
7879 emit_insn (gen_adddi3 (this, this, GEN_INT (hi)));
7881 emit_insn (gen_adddi3 (this, this, GEN_INT (lo)));
7885 rtx tmp = alpha_emit_set_long_const (gen_rtx_REG (Pmode, 0),
7886 delta, -(delta < 0));
7887 emit_insn (gen_adddi3 (this, this, tmp));
7890 /* Generate a tail call to the target function. */
7891 if (! TREE_USED (function))
7893 assemble_external (function);
7894 TREE_USED (function) = 1;
7896 funexp = XEXP (DECL_RTL (function), 0);
7897 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
7898 insn = emit_call_insn (gen_sibcall (funexp, const0_rtx));
7899 SIBLING_CALL_P (insn) = 1;
7901 /* Run just enough of rest_of_compilation to get the insns emitted.
7902 There's not really enough bulk here to make other passes such as
7903 instruction scheduling worth while. Note that use_thunk calls
7904 assemble_start_function and assemble_end_function. */
7905 insn = get_insns ();
7906 shorten_branches (insn);
7907 final_start_function (insn, file, 1);
7908 final (insn, file, 1, 0);
7909 final_end_function ();
7912 /* Debugging support. */
7916 /* Count the number of sdb related labels are generated (to find block
7917 start and end boundaries). */
7919 int sdb_label_count = 0;
7921 /* Next label # for each statement. */
7923 static int sym_lineno = 0;
7925 /* Count the number of .file directives, so that .loc is up to date. */
7927 static int num_source_filenames = 0;
7929 /* Name of the file containing the current function. */
7931 static const char *current_function_file = "";
7933 /* Offsets to alpha virtual arg/local debugging pointers. */
7935 long alpha_arg_offset;
7936 long alpha_auto_offset;
7938 /* Emit a new filename to a stream. */
7941 alpha_output_filename (stream, name)
7945 static int first_time = TRUE;
7946 char ltext_label_name[100];
7951 ++num_source_filenames;
7952 current_function_file = name;
7953 fprintf (stream, "\t.file\t%d ", num_source_filenames);
7954 output_quoted_string (stream, name);
7955 fprintf (stream, "\n");
7956 if (!TARGET_GAS && write_symbols == DBX_DEBUG)
7957 fprintf (stream, "\t#@stabs\n");
7960 else if (write_symbols == DBX_DEBUG)
7962 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name, "Ltext", 0);
7963 fprintf (stream, "%s", ASM_STABS_OP);
7964 output_quoted_string (stream, name);
7965 fprintf (stream, ",%d,0,0,%s\n", N_SOL, <ext_label_name[1]);
7968 else if (name != current_function_file
7969 && strcmp (name, current_function_file) != 0)
7971 if (inside_function && ! TARGET_GAS)
7972 fprintf (stream, "\t#.file\t%d ", num_source_filenames);
7975 ++num_source_filenames;
7976 current_function_file = name;
7977 fprintf (stream, "\t.file\t%d ", num_source_filenames);
7980 output_quoted_string (stream, name);
7981 fprintf (stream, "\n");
7985 /* Emit a linenumber to a stream. */
7988 alpha_output_lineno (stream, line)
7992 if (write_symbols == DBX_DEBUG)
7994 /* mips-tfile doesn't understand .stabd directives. */
7996 fprintf (stream, "$LM%d:\n%s%d,0,%d,$LM%d\n",
7997 sym_lineno, ASM_STABN_OP, N_SLINE, line, sym_lineno);
8000 fprintf (stream, "\n\t.loc\t%d %d\n", num_source_filenames, line);
8003 /* Structure to show the current status of registers and memory. */
8005 struct shadow_summary
8008 unsigned int i : 31; /* Mask of int regs */
8009 unsigned int fp : 31; /* Mask of fp regs */
8010 unsigned int mem : 1; /* mem == imem | fpmem */
8014 static void summarize_insn PARAMS ((rtx, struct shadow_summary *, int));
8015 static void alpha_handle_trap_shadows PARAMS ((rtx));
8017 /* Summary the effects of expression X on the machine. Update SUM, a pointer
8018 to the summary structure. SET is nonzero if the insn is setting the
8019 object, otherwise zero. */
8022 summarize_insn (x, sum, set)
8024 struct shadow_summary *sum;
8027 const char *format_ptr;
8033 switch (GET_CODE (x))
8035 /* ??? Note that this case would be incorrect if the Alpha had a
8036 ZERO_EXTRACT in SET_DEST. */
8038 summarize_insn (SET_SRC (x), sum, 0);
8039 summarize_insn (SET_DEST (x), sum, 1);
8043 summarize_insn (XEXP (x, 0), sum, 1);
8047 summarize_insn (XEXP (x, 0), sum, 0);
8051 for (i = ASM_OPERANDS_INPUT_LENGTH (x) - 1; i >= 0; i--)
8052 summarize_insn (ASM_OPERANDS_INPUT (x, i), sum, 0);
8056 for (i = XVECLEN (x, 0) - 1; i >= 0; i--)
8057 summarize_insn (XVECEXP (x, 0, i), sum, 0);
8061 summarize_insn (SUBREG_REG (x), sum, 0);
8066 int regno = REGNO (x);
8067 unsigned long mask = ((unsigned long) 1) << (regno % 32);
8069 if (regno == 31 || regno == 63)
8075 sum->defd.i |= mask;
8077 sum->defd.fp |= mask;
8082 sum->used.i |= mask;
8084 sum->used.fp |= mask;
8095 /* Find the regs used in memory address computation: */
8096 summarize_insn (XEXP (x, 0), sum, 0);
8099 case CONST_INT: case CONST_DOUBLE:
8100 case SYMBOL_REF: case LABEL_REF: case CONST:
8101 case SCRATCH: case ASM_INPUT:
8104 /* Handle common unary and binary ops for efficiency. */
8105 case COMPARE: case PLUS: case MINUS: case MULT: case DIV:
8106 case MOD: case UDIV: case UMOD: case AND: case IOR:
8107 case XOR: case ASHIFT: case ROTATE: case ASHIFTRT: case LSHIFTRT:
8108 case ROTATERT: case SMIN: case SMAX: case UMIN: case UMAX:
8109 case NE: case EQ: case GE: case GT: case LE:
8110 case LT: case GEU: case GTU: case LEU: case LTU:
8111 summarize_insn (XEXP (x, 0), sum, 0);
8112 summarize_insn (XEXP (x, 1), sum, 0);
8115 case NEG: case NOT: case SIGN_EXTEND: case ZERO_EXTEND:
8116 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: case FLOAT:
8117 case FIX: case UNSIGNED_FLOAT: case UNSIGNED_FIX: case ABS:
8118 case SQRT: case FFS:
8119 summarize_insn (XEXP (x, 0), sum, 0);
8123 format_ptr = GET_RTX_FORMAT (GET_CODE (x));
8124 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
8125 switch (format_ptr[i])
8128 summarize_insn (XEXP (x, i), sum, 0);
8132 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8133 summarize_insn (XVECEXP (x, i, j), sum, 0);
8145 /* Ensure a sufficient number of `trapb' insns are in the code when
8146 the user requests code with a trap precision of functions or
8149 In naive mode, when the user requests a trap-precision of
8150 "instruction", a trapb is needed after every instruction that may
8151 generate a trap. This ensures that the code is resumption safe but
8154 When optimizations are turned on, we delay issuing a trapb as long
8155 as possible. In this context, a trap shadow is the sequence of
8156 instructions that starts with a (potentially) trap generating
8157 instruction and extends to the next trapb or call_pal instruction
8158 (but GCC never generates call_pal by itself). We can delay (and
8159 therefore sometimes omit) a trapb subject to the following
8162 (a) On entry to the trap shadow, if any Alpha register or memory
8163 location contains a value that is used as an operand value by some
8164 instruction in the trap shadow (live on entry), then no instruction
8165 in the trap shadow may modify the register or memory location.
8167 (b) Within the trap shadow, the computation of the base register
8168 for a memory load or store instruction may not involve using the
8169 result of an instruction that might generate an UNPREDICTABLE
8172 (c) Within the trap shadow, no register may be used more than once
8173 as a destination register. (This is to make life easier for the
8176 (d) The trap shadow may not include any branch instructions. */
8179 alpha_handle_trap_shadows (insns)
8182 struct shadow_summary shadow;
8183 int trap_pending, exception_nesting;
8187 exception_nesting = 0;
8190 shadow.used.mem = 0;
8191 shadow.defd = shadow.used;
8193 for (i = insns; i ; i = NEXT_INSN (i))
8195 if (GET_CODE (i) == NOTE)
8197 switch (NOTE_LINE_NUMBER (i))
8199 case NOTE_INSN_EH_REGION_BEG:
8200 exception_nesting++;
8205 case NOTE_INSN_EH_REGION_END:
8206 exception_nesting--;
8211 case NOTE_INSN_EPILOGUE_BEG:
8212 if (trap_pending && alpha_tp >= ALPHA_TP_FUNC)
8217 else if (trap_pending)
8219 if (alpha_tp == ALPHA_TP_FUNC)
8221 if (GET_CODE (i) == JUMP_INSN
8222 && GET_CODE (PATTERN (i)) == RETURN)
8225 else if (alpha_tp == ALPHA_TP_INSN)
8229 struct shadow_summary sum;
8234 sum.defd = sum.used;
8236 switch (GET_CODE (i))
8239 /* Annoyingly, get_attr_trap will abort on these. */
8240 if (GET_CODE (PATTERN (i)) == USE
8241 || GET_CODE (PATTERN (i)) == CLOBBER)
8244 summarize_insn (PATTERN (i), &sum, 0);
8246 if ((sum.defd.i & shadow.defd.i)
8247 || (sum.defd.fp & shadow.defd.fp))
8249 /* (c) would be violated */
8253 /* Combine shadow with summary of current insn: */
8254 shadow.used.i |= sum.used.i;
8255 shadow.used.fp |= sum.used.fp;
8256 shadow.used.mem |= sum.used.mem;
8257 shadow.defd.i |= sum.defd.i;
8258 shadow.defd.fp |= sum.defd.fp;
8259 shadow.defd.mem |= sum.defd.mem;
8261 if ((sum.defd.i & shadow.used.i)
8262 || (sum.defd.fp & shadow.used.fp)
8263 || (sum.defd.mem & shadow.used.mem))
8265 /* (a) would be violated (also takes care of (b)) */
8266 if (get_attr_trap (i) == TRAP_YES
8267 && ((sum.defd.i & sum.used.i)
8268 || (sum.defd.fp & sum.used.fp)))
8287 n = emit_insn_before (gen_trapb (), i);
8288 PUT_MODE (n, TImode);
8289 PUT_MODE (i, TImode);
8293 shadow.used.mem = 0;
8294 shadow.defd = shadow.used;
8299 if ((exception_nesting > 0 || alpha_tp >= ALPHA_TP_FUNC)
8300 && GET_CODE (i) == INSN
8301 && GET_CODE (PATTERN (i)) != USE
8302 && GET_CODE (PATTERN (i)) != CLOBBER
8303 && get_attr_trap (i) == TRAP_YES)
8305 if (optimize && !trap_pending)
8306 summarize_insn (PATTERN (i), &shadow, 0);
8312 /* Alpha can only issue instruction groups simultaneously if they are
8313 suitibly aligned. This is very processor-specific. */
8315 enum alphaev4_pipe {
8322 enum alphaev5_pipe {
8333 static enum alphaev4_pipe alphaev4_insn_pipe PARAMS ((rtx));
8334 static enum alphaev5_pipe alphaev5_insn_pipe PARAMS ((rtx));
8335 static rtx alphaev4_next_group PARAMS ((rtx, int *, int *));
8336 static rtx alphaev5_next_group PARAMS ((rtx, int *, int *));
8337 static rtx alphaev4_next_nop PARAMS ((int *));
8338 static rtx alphaev5_next_nop PARAMS ((int *));
8340 static void alpha_align_insns
8341 PARAMS ((rtx, unsigned int, rtx (*)(rtx, int *, int *), rtx (*)(int *)));
8343 static enum alphaev4_pipe
8344 alphaev4_insn_pipe (insn)
8347 if (recog_memoized (insn) < 0)
8349 if (get_attr_length (insn) != 4)
8352 switch (get_attr_type (insn))
8386 static enum alphaev5_pipe
8387 alphaev5_insn_pipe (insn)
8390 if (recog_memoized (insn) < 0)
8392 if (get_attr_length (insn) != 4)
8395 switch (get_attr_type (insn))
8436 /* IN_USE is a mask of the slots currently filled within the insn group.
8437 The mask bits come from alphaev4_pipe above. If EV4_IBX is set, then
8438 the insn in EV4_IB0 can be swapped by the hardware into EV4_IB1.
8440 LEN is, of course, the length of the group in bytes. */
8443 alphaev4_next_group (insn, pin_use, plen)
8445 int *pin_use, *plen;
8452 || GET_CODE (PATTERN (insn)) == CLOBBER
8453 || GET_CODE (PATTERN (insn)) == USE)
8458 enum alphaev4_pipe pipe;
8460 pipe = alphaev4_insn_pipe (insn);
8464 /* Force complex instructions to start new groups. */
8468 /* If this is a completely unrecognized insn, its an asm.
8469 We don't know how long it is, so record length as -1 to
8470 signal a needed realignment. */
8471 if (recog_memoized (insn) < 0)
8474 len = get_attr_length (insn);
8478 if (in_use & EV4_IB0)
8480 if (in_use & EV4_IB1)
8485 in_use |= EV4_IB0 | EV4_IBX;
8489 if (in_use & EV4_IB0)
8491 if (!(in_use & EV4_IBX) || (in_use & EV4_IB1))
8499 if (in_use & EV4_IB1)
8509 /* Haifa doesn't do well scheduling branches. */
8510 if (GET_CODE (insn) == JUMP_INSN)
8514 insn = next_nonnote_insn (insn);
8516 if (!insn || ! INSN_P (insn))
8519 /* Let Haifa tell us where it thinks insn group boundaries are. */
8520 if (GET_MODE (insn) == TImode)
8523 if (GET_CODE (insn) == CLOBBER || GET_CODE (insn) == USE)
8528 insn = next_nonnote_insn (insn);
8536 /* IN_USE is a mask of the slots currently filled within the insn group.
8537 The mask bits come from alphaev5_pipe above. If EV5_E01 is set, then
8538 the insn in EV5_E0 can be swapped by the hardware into EV5_E1.
8540 LEN is, of course, the length of the group in bytes. */
8543 alphaev5_next_group (insn, pin_use, plen)
8545 int *pin_use, *plen;
8552 || GET_CODE (PATTERN (insn)) == CLOBBER
8553 || GET_CODE (PATTERN (insn)) == USE)
8558 enum alphaev5_pipe pipe;
8560 pipe = alphaev5_insn_pipe (insn);
8564 /* Force complex instructions to start new groups. */
8568 /* If this is a completely unrecognized insn, its an asm.
8569 We don't know how long it is, so record length as -1 to
8570 signal a needed realignment. */
8571 if (recog_memoized (insn) < 0)
8574 len = get_attr_length (insn);
8577 /* ??? Most of the places below, we would like to abort, as
8578 it would indicate an error either in Haifa, or in the
8579 scheduling description. Unfortunately, Haifa never
8580 schedules the last instruction of the BB, so we don't
8581 have an accurate TI bit to go off. */
8583 if (in_use & EV5_E0)
8585 if (in_use & EV5_E1)
8590 in_use |= EV5_E0 | EV5_E01;
8594 if (in_use & EV5_E0)
8596 if (!(in_use & EV5_E01) || (in_use & EV5_E1))
8604 if (in_use & EV5_E1)
8610 if (in_use & EV5_FA)
8612 if (in_use & EV5_FM)
8617 in_use |= EV5_FA | EV5_FAM;
8621 if (in_use & EV5_FA)
8627 if (in_use & EV5_FM)
8640 /* Haifa doesn't do well scheduling branches. */
8641 /* ??? If this is predicted not-taken, slotting continues, except
8642 that no more IBR, FBR, or JSR insns may be slotted. */
8643 if (GET_CODE (insn) == JUMP_INSN)
8647 insn = next_nonnote_insn (insn);
8649 if (!insn || ! INSN_P (insn))
8652 /* Let Haifa tell us where it thinks insn group boundaries are. */
8653 if (GET_MODE (insn) == TImode)
8656 if (GET_CODE (insn) == CLOBBER || GET_CODE (insn) == USE)
8661 insn = next_nonnote_insn (insn);
8670 alphaev4_next_nop (pin_use)
8673 int in_use = *pin_use;
8676 if (!(in_use & EV4_IB0))
8681 else if ((in_use & (EV4_IBX|EV4_IB1)) == EV4_IBX)
8686 else if (TARGET_FP && !(in_use & EV4_IB1))
8699 alphaev5_next_nop (pin_use)
8702 int in_use = *pin_use;
8705 if (!(in_use & EV5_E1))
8710 else if (TARGET_FP && !(in_use & EV5_FA))
8715 else if (TARGET_FP && !(in_use & EV5_FM))
8727 /* The instruction group alignment main loop. */
8730 alpha_align_insns (insns, max_align, next_group, next_nop)
8732 unsigned int max_align;
8733 rtx (*next_group) PARAMS ((rtx, int *, int *));
8734 rtx (*next_nop) PARAMS ((int *));
8736 /* ALIGN is the known alignment for the insn group. */
8738 /* OFS is the offset of the current insn in the insn group. */
8740 int prev_in_use, in_use, len;
8743 /* Let shorten branches care for assigning alignments to code labels. */
8744 shorten_branches (insns);
8746 if (align_functions < 4)
8748 else if ((unsigned int) align_functions < max_align)
8749 align = align_functions;
8753 ofs = prev_in_use = 0;
8755 if (GET_CODE (i) == NOTE)
8756 i = next_nonnote_insn (i);
8760 next = (*next_group) (i, &in_use, &len);
8762 /* When we see a label, resync alignment etc. */
8763 if (GET_CODE (i) == CODE_LABEL)
8765 unsigned int new_align = 1 << label_to_alignment (i);
8767 if (new_align >= align)
8769 align = new_align < max_align ? new_align : max_align;
8773 else if (ofs & (new_align-1))
8774 ofs = (ofs | (new_align-1)) + 1;
8779 /* Handle complex instructions special. */
8780 else if (in_use == 0)
8782 /* Asms will have length < 0. This is a signal that we have
8783 lost alignment knowledge. Assume, however, that the asm
8784 will not mis-align instructions. */
8793 /* If the known alignment is smaller than the recognized insn group,
8794 realign the output. */
8795 else if ((int) align < len)
8797 unsigned int new_log_align = len > 8 ? 4 : 3;
8800 where = prev = prev_nonnote_insn (i);
8801 if (!where || GET_CODE (where) != CODE_LABEL)
8804 /* Can't realign between a call and its gp reload. */
8805 if (! (TARGET_EXPLICIT_RELOCS
8806 && prev && GET_CODE (prev) == CALL_INSN))
8808 emit_insn_before (gen_realign (GEN_INT (new_log_align)), where);
8809 align = 1 << new_log_align;
8814 /* If the group won't fit in the same INT16 as the previous,
8815 we need to add padding to keep the group together. Rather
8816 than simply leaving the insn filling to the assembler, we
8817 can make use of the knowledge of what sorts of instructions
8818 were issued in the previous group to make sure that all of
8819 the added nops are really free. */
8820 else if (ofs + len > (int) align)
8822 int nop_count = (align - ofs) / 4;
8825 /* Insert nops before labels, branches, and calls to truely merge
8826 the execution of the nops with the previous instruction group. */
8827 where = prev_nonnote_insn (i);
8830 if (GET_CODE (where) == CODE_LABEL)
8832 rtx where2 = prev_nonnote_insn (where);
8833 if (where2 && GET_CODE (where2) == JUMP_INSN)
8836 else if (GET_CODE (where) == INSN)
8843 emit_insn_before ((*next_nop)(&prev_in_use), where);
8844 while (--nop_count);
8848 ofs = (ofs + len) & (align - 1);
8849 prev_in_use = in_use;
8854 /* Machine dependent reorg pass. */
8860 if (alpha_tp != ALPHA_TP_PROG || flag_exceptions)
8861 alpha_handle_trap_shadows (insns);
8863 /* Due to the number of extra trapb insns, don't bother fixing up
8864 alignment when trap precision is instruction. Moreover, we can
8865 only do our job when sched2 is run. */
8866 if (optimize && !optimize_size
8867 && alpha_tp != ALPHA_TP_INSN
8868 && flag_schedule_insns_after_reload)
8870 if (alpha_cpu == PROCESSOR_EV4)
8871 alpha_align_insns (insns, 8, alphaev4_next_group, alphaev4_next_nop);
8872 else if (alpha_cpu == PROCESSOR_EV5)
8873 alpha_align_insns (insns, 16, alphaev5_next_group, alphaev5_next_nop);
8877 #ifdef OBJECT_FORMAT_ELF
8879 /* Switch to the section to which we should output X. The only thing
8880 special we do here is to honor small data. */
8883 alpha_elf_select_rtx_section (mode, x, align)
8884 enum machine_mode mode;
8886 unsigned HOST_WIDE_INT align;
8888 if (TARGET_SMALL_DATA && GET_MODE_SIZE (mode) <= g_switch_value)
8889 /* ??? Consider using mergable sdata sections. */
8892 default_elf_select_rtx_section (mode, x, align);
8895 #endif /* OBJECT_FORMAT_ELF */
8897 #if TARGET_ABI_OPEN_VMS
8899 /* Return the VMS argument type corresponding to MODE. */
8902 alpha_arg_type (mode)
8903 enum machine_mode mode;
8908 return TARGET_FLOAT_VAX ? FF : FS;
8910 return TARGET_FLOAT_VAX ? FD : FT;
8916 /* Return an rtx for an integer representing the VMS Argument Information
8920 alpha_arg_info_reg_val (cum)
8921 CUMULATIVE_ARGS cum;
8923 unsigned HOST_WIDE_INT regval = cum.num_args;
8926 for (i = 0; i < 6; i++)
8927 regval |= ((int) cum.atypes[i]) << (i * 3 + 8);
8929 return GEN_INT (regval);
8932 /* Protect alpha_links from garbage collection. */
8935 mark_alpha_links_node (node, data)
8936 splay_tree_node node;
8937 void *data ATTRIBUTE_UNUSED;
8939 struct alpha_links *links = (struct alpha_links *) node->value;
8940 ggc_mark_rtx (links->linkage);
8945 mark_alpha_links (ptr)
8948 splay_tree tree = *(splay_tree *) ptr;
8949 splay_tree_foreach (tree, mark_alpha_links_node, NULL);
8952 /* Make (or fake) .linkage entry for function call.
8954 IS_LOCAL is 0 if name is used in call, 1 if name is used in definition.
8956 Return an SYMBOL_REF rtx for the linkage. */
8959 alpha_need_linkage (name, is_local)
8963 splay_tree_node node;
8964 struct alpha_links *al;
8965 struct alpha_funcs *cfaf;
8972 alpha_funcs_tree = splay_tree_new
8973 ((splay_tree_compare_fn) splay_tree_compare_pointers,
8974 (splay_tree_delete_key_fn) free,
8975 (splay_tree_delete_key_fn) free);
8977 cfaf = (struct alpha_funcs *) xmalloc (sizeof (struct alpha_funcs));
8980 cfaf->num = ++alpha_funcs_num;
8982 splay_tree_insert (alpha_funcs_tree,
8983 (splay_tree_key) current_function_decl,
8984 (splay_tree_value) cfaf);
8988 if (alpha_links_tree)
8990 /* Is this name already defined? */
8992 node = splay_tree_lookup (alpha_links_tree, (splay_tree_key) name);
8995 al = (struct alpha_links *) node->value;
8998 /* Defined here but external assumed. */
8999 if (al->lkind == KIND_EXTERN)
9000 al->lkind = KIND_LOCAL;
9004 /* Used here but unused assumed. */
9005 if (al->lkind == KIND_UNUSED)
9006 al->lkind = KIND_LOCAL;
9013 alpha_links_tree = splay_tree_new
9014 ((splay_tree_compare_fn) strcmp,
9015 (splay_tree_delete_key_fn) free,
9016 (splay_tree_delete_key_fn) free);
9018 ggc_add_root (&alpha_links_tree, 1, 1, mark_alpha_links);
9021 al = (struct alpha_links *) xmalloc (sizeof (struct alpha_links));
9022 name = xstrdup (name);
9024 /* Assume external if no definition. */
9025 al->lkind = (is_local ? KIND_UNUSED : KIND_EXTERN);
9027 /* Ensure we have an IDENTIFIER so assemble_name can mark it used. */
9028 get_identifier (name);
9030 /* Construct a SYMBOL_REF for us to call. */
9032 size_t name_len = strlen (name);
9033 char *linksym = alloca (name_len + 6);
9035 memcpy (linksym + 1, name, name_len);
9036 memcpy (linksym + 1 + name_len, "..lk", 5);
9037 al->linkage = gen_rtx_SYMBOL_REF (Pmode,
9038 ggc_alloc_string (linksym, name_len + 5));
9041 splay_tree_insert (alpha_links_tree, (splay_tree_key) name,
9042 (splay_tree_value) al);
9048 alpha_use_linkage (linkage, cfundecl, lflag, rflag)
9054 splay_tree_node cfunnode;
9055 struct alpha_funcs *cfaf;
9056 struct alpha_links *al;
9057 const char *name = XSTR (linkage, 0);
9059 cfaf = (struct alpha_funcs *) 0;
9060 al = (struct alpha_links *) 0;
9062 cfunnode = splay_tree_lookup (alpha_funcs_tree, (splay_tree_key) cfundecl);
9063 cfaf = (struct alpha_funcs *) cfunnode->value;
9067 splay_tree_node lnode;
9069 /* Is this name already defined? */
9071 lnode = splay_tree_lookup (cfaf->links, (splay_tree_key) name);
9073 al = (struct alpha_links *) lnode->value;
9077 cfaf->links = splay_tree_new
9078 ((splay_tree_compare_fn) strcmp,
9079 (splay_tree_delete_key_fn) free,
9080 (splay_tree_delete_key_fn) free);
9081 ggc_add_root (&cfaf->links, 1, 1, mark_alpha_links);
9090 splay_tree_node node = 0;
9091 struct alpha_links *anl;
9096 name_len = strlen (name);
9098 al = (struct alpha_links *) xmalloc (sizeof (struct alpha_links));
9099 al->num = cfaf->num;
9101 node = splay_tree_lookup (alpha_links_tree, (splay_tree_key) name);
9104 anl = (struct alpha_links *) node->value;
9105 al->lkind = anl->lkind;
9108 sprintf (buf, "$%d..%s..lk", cfaf->num, name);
9109 buflen = strlen (buf);
9110 linksym = alloca (buflen + 1);
9111 memcpy (linksym, buf, buflen + 1);
9113 al->linkage = gen_rtx_SYMBOL_REF
9114 (Pmode, ggc_alloc_string (linksym, buflen + 1));
9116 splay_tree_insert (cfaf->links, (splay_tree_key) name,
9117 (splay_tree_value) al);
9121 al->rkind = KIND_CODEADDR;
9123 al->rkind = KIND_LINKAGE;
9126 return gen_rtx_MEM (Pmode, plus_constant (al->linkage, 8));
9132 alpha_write_one_linkage (node, data)
9133 splay_tree_node node;
9136 const char *const name = (const char *) node->key;
9137 struct alpha_links *link = (struct alpha_links *) node->value;
9138 FILE *stream = (FILE *) data;
9140 fprintf (stream, "$%d..%s..lk:\n", link->num, name);
9141 if (link->rkind == KIND_CODEADDR)
9143 if (link->lkind == KIND_LOCAL)
9145 /* Local and used */
9146 fprintf (stream, "\t.quad %s..en\n", name);
9150 /* External and used, request code address. */
9151 fprintf (stream, "\t.code_address %s\n", name);
9156 if (link->lkind == KIND_LOCAL)
9158 /* Local and used, build linkage pair. */
9159 fprintf (stream, "\t.quad %s..en\n", name);
9160 fprintf (stream, "\t.quad %s\n", name);
9164 /* External and used, request linkage pair. */
9165 fprintf (stream, "\t.linkage %s\n", name);
9173 alpha_write_linkage (stream, funname, fundecl)
9175 const char *funname;
9178 splay_tree_node node;
9179 struct alpha_funcs *func;
9182 fprintf (stream, "\t.align 3\n");
9183 node = splay_tree_lookup (alpha_funcs_tree, (splay_tree_key) fundecl);
9184 func = (struct alpha_funcs *) node->value;
9186 fputs ("\t.name ", stream);
9187 assemble_name (stream, funname);
9188 fputs ("..na\n", stream);
9189 ASM_OUTPUT_LABEL (stream, funname);
9190 fprintf (stream, "\t.pdesc ");
9191 assemble_name (stream, funname);
9192 fprintf (stream, "..en,%s\n",
9193 alpha_procedure_type == PT_STACK ? "stack"
9194 : alpha_procedure_type == PT_REGISTER ? "reg" : "null");
9198 splay_tree_foreach (func->links, alpha_write_one_linkage, stream);
9199 /* splay_tree_delete (func->links); */
9203 /* Given a decl, a section name, and whether the decl initializer
9204 has relocs, choose attributes for the section. */
9206 #define SECTION_VMS_OVERLAY SECTION_FORGET
9207 #define SECTION_VMS_GLOBAL SECTION_MACH_DEP
9208 #define SECTION_VMS_INITIALIZE (SECTION_VMS_GLOBAL << 1)
9211 vms_section_type_flags (decl, name, reloc)
9216 unsigned int flags = default_section_type_flags (decl, name, reloc);
9218 if (decl && DECL_ATTRIBUTES (decl)
9219 && lookup_attribute ("overlaid", DECL_ATTRIBUTES (decl)))
9220 flags |= SECTION_VMS_OVERLAY;
9221 if (decl && DECL_ATTRIBUTES (decl)
9222 && lookup_attribute ("global", DECL_ATTRIBUTES (decl)))
9223 flags |= SECTION_VMS_GLOBAL;
9224 if (decl && DECL_ATTRIBUTES (decl)
9225 && lookup_attribute ("initialize", DECL_ATTRIBUTES (decl)))
9226 flags |= SECTION_VMS_INITIALIZE;
9231 /* Switch to an arbitrary section NAME with attributes as specified
9232 by FLAGS. ALIGN specifies any known alignment requirements for
9233 the section; 0 if the default should be used. */
9236 vms_asm_named_section (name, flags)
9240 fputc ('\n', asm_out_file);
9241 fprintf (asm_out_file, ".section\t%s", name);
9243 if (flags & SECTION_VMS_OVERLAY)
9244 fprintf (asm_out_file, ",OVR");
9245 if (flags & SECTION_VMS_GLOBAL)
9246 fprintf (asm_out_file, ",GBL");
9247 if (flags & SECTION_VMS_INITIALIZE)
9248 fprintf (asm_out_file, ",NOMOD");
9249 if (flags & SECTION_DEBUG)
9250 fprintf (asm_out_file, ",NOWRT");
9252 fputc ('\n', asm_out_file);
9255 /* Record an element in the table of global constructors. SYMBOL is
9256 a SYMBOL_REF of the function to be called; PRIORITY is a number
9257 between 0 and MAX_INIT_PRIORITY.
9259 Differs from default_ctors_section_asm_out_constructor in that the
9260 width of the .ctors entry is always 64 bits, rather than the 32 bits
9261 used by a normal pointer. */
9264 vms_asm_out_constructor (symbol, priority)
9266 int priority ATTRIBUTE_UNUSED;
9269 assemble_align (BITS_PER_WORD);
9270 assemble_integer (symbol, UNITS_PER_WORD, BITS_PER_WORD, 1);
9274 vms_asm_out_destructor (symbol, priority)
9276 int priority ATTRIBUTE_UNUSED;
9279 assemble_align (BITS_PER_WORD);
9280 assemble_integer (symbol, UNITS_PER_WORD, BITS_PER_WORD, 1);
9285 alpha_need_linkage (name, is_local)
9286 const char *name ATTRIBUTE_UNUSED;
9287 int is_local ATTRIBUTE_UNUSED;
9293 alpha_use_linkage (linkage, cfundecl, lflag, rflag)
9294 rtx linkage ATTRIBUTE_UNUSED;
9295 tree cfundecl ATTRIBUTE_UNUSED;
9296 int lflag ATTRIBUTE_UNUSED;
9297 int rflag ATTRIBUTE_UNUSED;
9302 #endif /* TARGET_ABI_OPEN_VMS */
9304 #if TARGET_ABI_UNICOSMK
9306 static void unicosmk_output_module_name PARAMS ((FILE *));
9307 static void unicosmk_output_default_externs PARAMS ((FILE *));
9308 static void unicosmk_output_dex PARAMS ((FILE *));
9309 static void unicosmk_output_externs PARAMS ((FILE *));
9310 static void unicosmk_output_addr_vec PARAMS ((FILE *, rtx));
9311 static const char *unicosmk_ssib_name PARAMS ((void));
9312 static int unicosmk_special_name PARAMS ((const char *));
9314 /* Define the offset between two registers, one to be eliminated, and the
9315 other its replacement, at the start of a routine. */
9318 unicosmk_initial_elimination_offset (from, to)
9324 fixed_size = alpha_sa_size();
9325 if (fixed_size != 0)
9328 if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
9330 else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
9332 else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
9333 return (ALPHA_ROUND (current_function_outgoing_args_size)
9334 + ALPHA_ROUND (get_frame_size()));
9335 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
9336 return (ALPHA_ROUND (fixed_size)
9337 + ALPHA_ROUND (get_frame_size()
9338 + current_function_outgoing_args_size));
9343 /* Output the module name for .ident and .end directives. We have to strip
9344 directories and add make sure that the module name starts with a letter
9348 unicosmk_output_module_name (file)
9353 /* Strip directories. */
9355 name = strrchr (main_input_filename, '/');
9359 name = main_input_filename;
9361 /* CAM only accepts module names that start with a letter or '$'. We
9362 prefix the module name with a '$' if necessary. */
9364 if (!ISALPHA (*name))
9366 output_clean_symbol_name (file, name);
9369 /* Output text that to appear at the beginning of an assembler file. */
9372 unicosmk_asm_file_start (file)
9377 fputs ("\t.ident\t", file);
9378 unicosmk_output_module_name (file);
9379 fputs ("\n\n", file);
9381 /* The Unicos/Mk assembler uses different register names. Instead of trying
9382 to support them, we simply use micro definitions. */
9384 /* CAM has different register names: rN for the integer register N and fN
9385 for the floating-point register N. Instead of trying to use these in
9386 alpha.md, we define the symbols $N and $fN to refer to the appropriate
9389 for (i = 0; i < 32; ++i)
9390 fprintf (file, "$%d <- r%d\n", i, i);
9392 for (i = 0; i < 32; ++i)
9393 fprintf (file, "$f%d <- f%d\n", i, i);
9397 /* The .align directive fill unused space with zeroes which does not work
9398 in code sections. We define the macro 'gcc@code@align' which uses nops
9399 instead. Note that it assumes that code sections always have the
9400 biggest possible alignment since . refers to the current offset from
9401 the beginning of the section. */
9403 fputs ("\t.macro gcc@code@align n\n", file);
9404 fputs ("gcc@n@bytes = 1 << n\n", file);
9405 fputs ("gcc@here = . % gcc@n@bytes\n", file);
9406 fputs ("\t.if ne, gcc@here, 0\n", file);
9407 fputs ("\t.repeat (gcc@n@bytes - gcc@here) / 4\n", file);
9408 fputs ("\tbis r31,r31,r31\n", file);
9409 fputs ("\t.endr\n", file);
9410 fputs ("\t.endif\n", file);
9411 fputs ("\t.endm gcc@code@align\n\n", file);
9413 /* Output extern declarations which should always be visible. */
9414 unicosmk_output_default_externs (file);
9416 /* Open a dummy section. We always need to be inside a section for the
9417 section-switching code to work correctly.
9418 ??? This should be a module id or something like that. I still have to
9419 figure out what the rules for those are. */
9420 fputs ("\n\t.psect\t$SG00000,data\n", file);
9423 /* Output text to appear at the end of an assembler file. This includes all
9424 pending extern declarations and DEX expressions. */
9427 unicosmk_asm_file_end (file)
9430 fputs ("\t.endp\n\n", file);
9432 /* Output all pending externs. */
9434 unicosmk_output_externs (file);
9436 /* Output dex definitions used for functions whose names conflict with
9439 unicosmk_output_dex (file);
9441 fputs ("\t.end\t", file);
9442 unicosmk_output_module_name (file);
9446 /* Output the definition of a common variable. */
9449 unicosmk_output_common (file, name, size, align)
9456 printf ("T3E__: common %s\n", name);
9459 fputs("\t.endp\n\n\t.psect ", file);
9460 assemble_name(file, name);
9461 fprintf(file, ",%d,common\n", floor_log2 (align / BITS_PER_UNIT));
9462 fprintf(file, "\t.byte\t0:%d\n", size);
9464 /* Mark the symbol as defined in this module. */
9465 name_tree = get_identifier (name);
9466 TREE_ASM_WRITTEN (name_tree) = 1;
9469 #define SECTION_PUBLIC SECTION_MACH_DEP
9470 #define SECTION_MAIN (SECTION_PUBLIC << 1)
9471 static int current_section_align;
9474 unicosmk_section_type_flags (decl, name, reloc)
9477 int reloc ATTRIBUTE_UNUSED;
9479 unsigned int flags = default_section_type_flags (decl, name, reloc);
9484 if (TREE_CODE (decl) == FUNCTION_DECL)
9486 current_section_align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
9487 if (align_functions_log > current_section_align)
9488 current_section_align = align_functions_log;
9490 if (! strcmp (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl)), "main"))
9491 flags |= SECTION_MAIN;
9494 current_section_align = floor_log2 (DECL_ALIGN (decl) / BITS_PER_UNIT);
9496 if (TREE_PUBLIC (decl))
9497 flags |= SECTION_PUBLIC;
9502 /* Generate a section name for decl and associate it with the
9506 unicosmk_unique_section (decl, reloc)
9508 int reloc ATTRIBUTE_UNUSED;
9516 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
9517 name = alpha_strip_name_encoding (name);
9518 len = strlen (name);
9520 if (TREE_CODE (decl) == FUNCTION_DECL)
9524 /* It is essential that we prefix the section name here because
9525 otherwise the section names generated for constructors and
9526 destructors confuse collect2. */
9528 string = alloca (len + 6);
9529 sprintf (string, "code@%s", name);
9530 DECL_SECTION_NAME (decl) = build_string (len + 5, string);
9532 else if (TREE_PUBLIC (decl))
9533 DECL_SECTION_NAME (decl) = build_string (len, name);
9538 string = alloca (len + 6);
9539 sprintf (string, "data@%s", name);
9540 DECL_SECTION_NAME (decl) = build_string (len + 5, string);
9544 /* Switch to an arbitrary section NAME with attributes as specified
9545 by FLAGS. ALIGN specifies any known alignment requirements for
9546 the section; 0 if the default should be used. */
9549 unicosmk_asm_named_section (name, flags)
9555 /* Close the previous section. */
9557 fputs ("\t.endp\n\n", asm_out_file);
9559 /* Find out what kind of section we are opening. */
9561 if (flags & SECTION_MAIN)
9562 fputs ("\t.start\tmain\n", asm_out_file);
9564 if (flags & SECTION_CODE)
9566 else if (flags & SECTION_PUBLIC)
9571 if (current_section_align != 0)
9572 fprintf (asm_out_file, "\t.psect\t%s,%d,%s\n", name,
9573 current_section_align, kind);
9575 fprintf (asm_out_file, "\t.psect\t%s,%s\n", name, kind);
9579 unicosmk_insert_attributes (decl, attr_ptr)
9581 tree *attr_ptr ATTRIBUTE_UNUSED;
9584 && (TREE_PUBLIC (decl) || TREE_CODE (decl) == FUNCTION_DECL))
9585 unicosmk_unique_section (decl, 0);
9588 /* Output an alignment directive. We have to use the macro 'gcc@code@align'
9589 in code sections because .align fill unused space with zeroes. */
9592 unicosmk_output_align (file, align)
9596 if (inside_function)
9597 fprintf (file, "\tgcc@code@align\t%d\n", align);
9599 fprintf (file, "\t.align\t%d\n", align);
9602 /* Add a case vector to the current function's list of deferred case
9603 vectors. Case vectors have to be put into a separate section because CAM
9604 does not allow data definitions in code sections. */
9607 unicosmk_defer_case_vector (lab, vec)
9611 struct machine_function *machine = cfun->machine;
9613 vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec);
9614 machine->addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec,
9615 machine->addr_list);
9618 /* Output a case vector. */
9621 unicosmk_output_addr_vec (file, vec)
9625 rtx lab = XEXP (vec, 0);
9626 rtx body = XEXP (vec, 1);
9627 int vlen = XVECLEN (body, 0);
9630 ASM_OUTPUT_INTERNAL_LABEL (file, "L", CODE_LABEL_NUMBER (lab));
9632 for (idx = 0; idx < vlen; idx++)
9634 ASM_OUTPUT_ADDR_VEC_ELT
9635 (file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0)));
9639 /* Output current function's deferred case vectors. */
9642 unicosmk_output_deferred_case_vectors (file)
9645 struct machine_function *machine = cfun->machine;
9648 if (machine->addr_list == NULL_RTX)
9652 for (t = machine->addr_list; t; t = XEXP (t, 1))
9653 unicosmk_output_addr_vec (file, XEXP (t, 0));
9656 /* Set up the dynamic subprogram information block (DSIB) and update the
9657 frame pointer register ($15) for subroutines which have a frame. If the
9658 subroutine doesn't have a frame, simply increment $15. */
9661 unicosmk_gen_dsib (imaskP)
9662 unsigned long * imaskP;
9664 if (alpha_procedure_type == PT_STACK)
9666 const char *ssib_name;
9669 /* Allocate 64 bytes for the DSIB. */
9671 FRP (emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx,
9673 emit_insn (gen_blockage ());
9675 /* Save the return address. */
9677 mem = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx, 56));
9678 set_mem_alias_set (mem, alpha_sr_alias_set);
9679 FRP (emit_move_insn (mem, gen_rtx_REG (DImode, REG_RA)));
9680 (*imaskP) &= ~(1L << REG_RA);
9682 /* Save the old frame pointer. */
9684 mem = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx, 48));
9685 set_mem_alias_set (mem, alpha_sr_alias_set);
9686 FRP (emit_move_insn (mem, hard_frame_pointer_rtx));
9687 (*imaskP) &= ~(1L << HARD_FRAME_POINTER_REGNUM);
9689 emit_insn (gen_blockage ());
9691 /* Store the SSIB pointer. */
9693 ssib_name = ggc_strdup (unicosmk_ssib_name ());
9694 mem = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx, 32));
9695 set_mem_alias_set (mem, alpha_sr_alias_set);
9697 FRP (emit_move_insn (gen_rtx_REG (DImode, 5),
9698 gen_rtx_SYMBOL_REF (Pmode, ssib_name)));
9699 FRP (emit_move_insn (mem, gen_rtx_REG (DImode, 5)));
9701 /* Save the CIW index. */
9703 mem = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx, 24));
9704 set_mem_alias_set (mem, alpha_sr_alias_set);
9705 FRP (emit_move_insn (mem, gen_rtx_REG (DImode, 25)));
9707 emit_insn (gen_blockage ());
9709 /* Set the new frame pointer. */
9711 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
9712 stack_pointer_rtx, GEN_INT (64))));
9717 /* Increment the frame pointer register to indicate that we do not
9720 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
9721 hard_frame_pointer_rtx, GEN_INT (1))));
9725 #define SSIB_PREFIX "__SSIB_"
9726 #define SSIB_PREFIX_LEN 7
9728 /* Generate the name of the SSIB section for the current function. */
9731 unicosmk_ssib_name ()
9733 /* This is ok since CAM won't be able to deal with names longer than that
9736 static char name[256];
9742 x = DECL_RTL (cfun->decl);
9743 if (GET_CODE (x) != MEM)
9746 if (GET_CODE (x) != SYMBOL_REF)
9748 fnname = alpha_strip_name_encoding (XSTR (x, 0));
9750 len = strlen (fnname);
9751 if (len + SSIB_PREFIX_LEN > 255)
9752 len = 255 - SSIB_PREFIX_LEN;
9754 strcpy (name, SSIB_PREFIX);
9755 strncpy (name + SSIB_PREFIX_LEN, fnname, len);
9756 name[len + SSIB_PREFIX_LEN] = 0;
9761 /* Output the static subroutine information block for the current
9765 unicosmk_output_ssib (file, fnname)
9773 struct machine_function *machine = cfun->machine;
9776 fprintf (file, "\t.endp\n\n\t.psect\t%s%s,data\n", user_label_prefix,
9777 unicosmk_ssib_name ());
9779 /* Some required stuff and the function name length. */
9781 len = strlen (fnname);
9782 fprintf (file, "\t.quad\t^X20008%2.2X28\n", len);
9785 ??? We don't do that yet. */
9787 fputs ("\t.quad\t0\n", file);
9789 /* Function address. */
9791 fputs ("\t.quad\t", file);
9792 assemble_name (file, fnname);
9795 fputs ("\t.quad\t0\n", file);
9796 fputs ("\t.quad\t0\n", file);
9799 ??? We do it the same way Cray CC does it but this could be
9802 for( i = 0; i < len; i++ )
9803 fprintf (file, "\t.byte\t%d\n", (int)(fnname[i]));
9804 if( (len % 8) == 0 )
9805 fputs ("\t.quad\t0\n", file);
9807 fprintf (file, "\t.bits\t%d : 0\n", (8 - (len % 8))*8);
9809 /* All call information words used in the function. */
9811 for (x = machine->first_ciw; x; x = XEXP (x, 1))
9814 fprintf (file, "\t.quad\t");
9815 #if HOST_BITS_PER_WIDE_INT == 32
9816 fprintf (file, HOST_WIDE_INT_PRINT_DOUBLE_HEX,
9817 CONST_DOUBLE_HIGH (ciw), CONST_DOUBLE_LOW (ciw));
9819 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (ciw));
9821 fprintf (file, "\n");
9825 /* Add a call information word (CIW) to the list of the current function's
9826 CIWs and return its index.
9828 X is a CONST_INT or CONST_DOUBLE representing the CIW. */
9831 unicosmk_add_call_info_word (x)
9835 struct machine_function *machine = cfun->machine;
9837 node = gen_rtx_EXPR_LIST (VOIDmode, x, NULL_RTX);
9838 if (machine->first_ciw == NULL_RTX)
9839 machine->first_ciw = node;
9841 XEXP (machine->last_ciw, 1) = node;
9843 machine->last_ciw = node;
9844 ++machine->ciw_count;
9846 return GEN_INT (machine->ciw_count
9847 + strlen (current_function_name)/8 + 5);
9850 static char unicosmk_section_buf[100];
9853 unicosmk_text_section ()
9855 static int count = 0;
9856 sprintf (unicosmk_section_buf, "\t.endp\n\n\t.psect\tgcc@text___%d,code",
9858 return unicosmk_section_buf;
9862 unicosmk_data_section ()
9864 static int count = 1;
9865 sprintf (unicosmk_section_buf, "\t.endp\n\n\t.psect\tgcc@data___%d,data",
9867 return unicosmk_section_buf;
9870 /* The Cray assembler doesn't accept extern declarations for symbols which
9871 are defined in the same file. We have to keep track of all global
9872 symbols which are referenced and/or defined in a source file and output
9873 extern declarations for those which are referenced but not defined at
9876 /* List of identifiers for which an extern declaration might have to be
9879 struct unicosmk_extern_list
9881 struct unicosmk_extern_list *next;
9885 static struct unicosmk_extern_list *unicosmk_extern_head = 0;
9887 /* Output extern declarations which are required for every asm file. */
9890 unicosmk_output_default_externs (file)
9893 static const char *const externs[] =
9894 { "__T3E_MISMATCH" };
9899 n = ARRAY_SIZE (externs);
9901 for (i = 0; i < n; i++)
9902 fprintf (file, "\t.extern\t%s\n", externs[i]);
9905 /* Output extern declarations for global symbols which are have been
9906 referenced but not defined. */
9909 unicosmk_output_externs (file)
9912 struct unicosmk_extern_list *p;
9913 const char *real_name;
9917 len = strlen (user_label_prefix);
9918 for (p = unicosmk_extern_head; p != 0; p = p->next)
9920 /* We have to strip the encoding and possibly remove user_label_prefix
9921 from the identifier in order to handle -fleading-underscore and
9922 explicit asm names correctly (cf. gcc.dg/asm-names-1.c). */
9923 real_name = alpha_strip_name_encoding (p->name);
9924 if (len && p->name[0] == '*'
9925 && !memcmp (real_name, user_label_prefix, len))
9928 name_tree = get_identifier (real_name);
9929 if (! TREE_ASM_WRITTEN (name_tree))
9931 TREE_ASM_WRITTEN (name_tree) = 1;
9932 fputs ("\t.extern\t", file);
9933 assemble_name (file, p->name);
9939 /* Record an extern. */
9942 unicosmk_add_extern (name)
9945 struct unicosmk_extern_list *p;
9947 p = (struct unicosmk_extern_list *)
9948 xmalloc (sizeof (struct unicosmk_extern_list));
9949 p->next = unicosmk_extern_head;
9951 unicosmk_extern_head = p;
9954 /* The Cray assembler generates incorrect code if identifiers which
9955 conflict with register names are used as instruction operands. We have
9956 to replace such identifiers with DEX expressions. */
9958 /* Structure to collect identifiers which have been replaced by DEX
9961 struct unicosmk_dex {
9962 struct unicosmk_dex *next;
9966 /* List of identifiers which have been replaced by DEX expressions. The DEX
9967 number is determined by the position in the list. */
9969 static struct unicosmk_dex *unicosmk_dex_list = NULL;
9971 /* The number of elements in the DEX list. */
9973 static int unicosmk_dex_count = 0;
9975 /* Check if NAME must be replaced by a DEX expression. */
9978 unicosmk_special_name (name)
9987 if (name[0] != 'r' && name[0] != 'f' && name[0] != 'R' && name[0] != 'F')
9993 return (name[2] == '\0' || (ISDIGIT (name[2]) && name[3] == '\0'));
9996 return (name[2] == '\0'
9997 || ((name[2] == '0' || name[2] == '1') && name[3] == '\0'));
10000 return (ISDIGIT (name[1]) && name[2] == '\0');
10004 /* Return the DEX number if X must be replaced by a DEX expression and 0
10008 unicosmk_need_dex (x)
10011 struct unicosmk_dex *dex;
10015 if (GET_CODE (x) != SYMBOL_REF)
10019 if (! unicosmk_special_name (name))
10022 i = unicosmk_dex_count;
10023 for (dex = unicosmk_dex_list; dex; dex = dex->next)
10025 if (! strcmp (name, dex->name))
10030 dex = (struct unicosmk_dex *) xmalloc (sizeof (struct unicosmk_dex));
10032 dex->next = unicosmk_dex_list;
10033 unicosmk_dex_list = dex;
10035 ++unicosmk_dex_count;
10036 return unicosmk_dex_count;
10039 /* Output the DEX definitions for this file. */
10042 unicosmk_output_dex (file)
10045 struct unicosmk_dex *dex;
10048 if (unicosmk_dex_list == NULL)
10051 fprintf (file, "\t.dexstart\n");
10053 i = unicosmk_dex_count;
10054 for (dex = unicosmk_dex_list; dex; dex = dex->next)
10056 fprintf (file, "\tDEX (%d) = ", i);
10057 assemble_name (file, dex->name);
10062 fprintf (file, "\t.dexend\n");
10068 unicosmk_output_deferred_case_vectors (file)
10069 FILE *file ATTRIBUTE_UNUSED;
10073 unicosmk_gen_dsib (imaskP)
10074 unsigned long * imaskP ATTRIBUTE_UNUSED;
10078 unicosmk_output_ssib (file, fnname)
10079 FILE * file ATTRIBUTE_UNUSED;
10080 const char * fnname ATTRIBUTE_UNUSED;
10084 unicosmk_add_call_info_word (x)
10085 rtx x ATTRIBUTE_UNUSED;
10091 unicosmk_need_dex (x)
10092 rtx x ATTRIBUTE_UNUSED;
10097 #endif /* TARGET_ABI_UNICOSMK */
10099 #include "gt-alpha.h"