1 /* Subroutines used for code generation on the DEC Alpha.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
26 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
47 #include "integrate.h"
50 #include "target-def.h"
52 #include "langhooks.h"
53 #include <splay-tree.h>
54 #include "cfglayout.h"
55 #include "tree-gimple.h"
57 /* Specify which cpu to schedule for. */
59 enum processor_type alpha_cpu;
60 static const char * const alpha_cpu_name[] =
65 /* Specify how accurate floating-point traps need to be. */
67 enum alpha_trap_precision alpha_tp;
69 /* Specify the floating-point rounding mode. */
71 enum alpha_fp_rounding_mode alpha_fprm;
73 /* Specify which things cause traps. */
75 enum alpha_fp_trap_mode alpha_fptm;
77 /* Specify bit size of immediate TLS offsets. */
79 int alpha_tls_size = 32;
81 /* Strings decoded into the above options. */
83 const char *alpha_cpu_string; /* -mcpu= */
84 const char *alpha_tune_string; /* -mtune= */
85 const char *alpha_tp_string; /* -mtrap-precision=[p|s|i] */
86 const char *alpha_fprm_string; /* -mfp-rounding-mode=[n|m|c|d] */
87 const char *alpha_fptm_string; /* -mfp-trap-mode=[n|u|su|sui] */
88 const char *alpha_mlat_string; /* -mmemory-latency= */
89 const char *alpha_tls_size_string; /* -mtls-size=[16|32|64] */
91 /* Save information from a "cmpxx" operation until the branch or scc is
94 struct alpha_compare alpha_compare;
96 /* Nonzero if inside of a function, because the Alpha asm can't
97 handle .files inside of functions. */
99 static int inside_function = FALSE;
101 /* The number of cycles of latency we should assume on memory reads. */
103 int alpha_memory_latency = 3;
105 /* Whether the function needs the GP. */
107 static int alpha_function_needs_gp;
109 /* The alias set for prologue/epilogue register save/restore. */
111 static GTY(()) int alpha_sr_alias_set;
113 /* The assembler name of the current function. */
115 static const char *alpha_fnname;
117 /* The next explicit relocation sequence number. */
118 extern GTY(()) int alpha_next_sequence_number;
119 int alpha_next_sequence_number = 1;
121 /* The literal and gpdisp sequence numbers for this insn, as printed
122 by %# and %* respectively. */
123 extern GTY(()) int alpha_this_literal_sequence_number;
124 extern GTY(()) int alpha_this_gpdisp_sequence_number;
125 int alpha_this_literal_sequence_number;
126 int alpha_this_gpdisp_sequence_number;
128 /* Costs of various operations on the different architectures. */
130 struct alpha_rtx_cost_data
132 unsigned char fp_add;
133 unsigned char fp_mult;
134 unsigned char fp_div_sf;
135 unsigned char fp_div_df;
136 unsigned char int_mult_si;
137 unsigned char int_mult_di;
138 unsigned char int_shift;
139 unsigned char int_cmov;
140 unsigned short int_div;
143 static struct alpha_rtx_cost_data const alpha_rtx_cost_data[PROCESSOR_MAX] =
146 COSTS_N_INSNS (6), /* fp_add */
147 COSTS_N_INSNS (6), /* fp_mult */
148 COSTS_N_INSNS (34), /* fp_div_sf */
149 COSTS_N_INSNS (63), /* fp_div_df */
150 COSTS_N_INSNS (23), /* int_mult_si */
151 COSTS_N_INSNS (23), /* int_mult_di */
152 COSTS_N_INSNS (2), /* int_shift */
153 COSTS_N_INSNS (2), /* int_cmov */
154 COSTS_N_INSNS (70), /* int_div */
157 COSTS_N_INSNS (4), /* fp_add */
158 COSTS_N_INSNS (4), /* fp_mult */
159 COSTS_N_INSNS (15), /* fp_div_sf */
160 COSTS_N_INSNS (22), /* fp_div_df */
161 COSTS_N_INSNS (8), /* int_mult_si */
162 COSTS_N_INSNS (12), /* int_mult_di */
163 COSTS_N_INSNS (1) + 1, /* int_shift */
164 COSTS_N_INSNS (1), /* int_cmov */
165 COSTS_N_INSNS (45), /* int_div */
168 COSTS_N_INSNS (4), /* fp_add */
169 COSTS_N_INSNS (4), /* fp_mult */
170 COSTS_N_INSNS (12), /* fp_div_sf */
171 COSTS_N_INSNS (15), /* fp_div_df */
172 COSTS_N_INSNS (7), /* int_mult_si */
173 COSTS_N_INSNS (7), /* int_mult_di */
174 COSTS_N_INSNS (1), /* int_shift */
175 COSTS_N_INSNS (2), /* int_cmov */
176 COSTS_N_INSNS (25), /* int_div */
180 /* Similar but tuned for code size instead of execution latency. The
181 extra +N is fractional cost tuning based on latency. It's used to
182 encourage use of cheaper insns like shift, but only if there's just
185 static struct alpha_rtx_cost_data const alpha_rtx_cost_size =
187 COSTS_N_INSNS (1), /* fp_add */
188 COSTS_N_INSNS (1), /* fp_mult */
189 COSTS_N_INSNS (1), /* fp_div_sf */
190 COSTS_N_INSNS (1) + 1, /* fp_div_df */
191 COSTS_N_INSNS (1) + 1, /* int_mult_si */
192 COSTS_N_INSNS (1) + 2, /* int_mult_di */
193 COSTS_N_INSNS (1), /* int_shift */
194 COSTS_N_INSNS (1), /* int_cmov */
195 COSTS_N_INSNS (6), /* int_div */
198 /* Get the number of args of a function in one of two ways. */
199 #if TARGET_ABI_OPEN_VMS || TARGET_ABI_UNICOSMK
200 #define NUM_ARGS current_function_args_info.num_args
202 #define NUM_ARGS current_function_args_info
208 /* Declarations of static functions. */
209 static struct machine_function *alpha_init_machine_status (void);
210 static rtx alpha_emit_xfloating_compare (enum rtx_code, rtx, rtx);
212 #if TARGET_ABI_OPEN_VMS
213 static void alpha_write_linkage (FILE *, const char *, tree);
216 static void unicosmk_output_deferred_case_vectors (FILE *);
217 static void unicosmk_gen_dsib (unsigned long *);
218 static void unicosmk_output_ssib (FILE *, const char *);
219 static int unicosmk_need_dex (rtx);
221 /* Parse target option strings. */
224 override_options (void)
227 static const struct cpu_table {
228 const char *const name;
229 const enum processor_type processor;
232 #define EV5_MASK (MASK_CPU_EV5)
233 #define EV6_MASK (MASK_CPU_EV6|MASK_BWX|MASK_MAX|MASK_FIX)
234 { "ev4", PROCESSOR_EV4, 0 },
235 { "ev45", PROCESSOR_EV4, 0 },
236 { "21064", PROCESSOR_EV4, 0 },
237 { "ev5", PROCESSOR_EV5, EV5_MASK },
238 { "21164", PROCESSOR_EV5, EV5_MASK },
239 { "ev56", PROCESSOR_EV5, EV5_MASK|MASK_BWX },
240 { "21164a", PROCESSOR_EV5, EV5_MASK|MASK_BWX },
241 { "pca56", PROCESSOR_EV5, EV5_MASK|MASK_BWX|MASK_MAX },
242 { "21164PC",PROCESSOR_EV5, EV5_MASK|MASK_BWX|MASK_MAX },
243 { "21164pc",PROCESSOR_EV5, EV5_MASK|MASK_BWX|MASK_MAX },
244 { "ev6", PROCESSOR_EV6, EV6_MASK },
245 { "21264", PROCESSOR_EV6, EV6_MASK },
246 { "ev67", PROCESSOR_EV6, EV6_MASK|MASK_CIX },
247 { "21264a", PROCESSOR_EV6, EV6_MASK|MASK_CIX },
251 /* Unicos/Mk doesn't have shared libraries. */
252 if (TARGET_ABI_UNICOSMK && flag_pic)
254 warning ("-f%s ignored for Unicos/Mk (not supported)",
255 (flag_pic > 1) ? "PIC" : "pic");
259 /* On Unicos/Mk, the native compiler consistently generates /d suffices for
260 floating-point instructions. Make that the default for this target. */
261 if (TARGET_ABI_UNICOSMK)
262 alpha_fprm = ALPHA_FPRM_DYN;
264 alpha_fprm = ALPHA_FPRM_NORM;
266 alpha_tp = ALPHA_TP_PROG;
267 alpha_fptm = ALPHA_FPTM_N;
269 /* We cannot use su and sui qualifiers for conversion instructions on
270 Unicos/Mk. I'm not sure if this is due to assembler or hardware
271 limitations. Right now, we issue a warning if -mieee is specified
272 and then ignore it; eventually, we should either get it right or
273 disable the option altogether. */
277 if (TARGET_ABI_UNICOSMK)
278 warning ("-mieee not supported on Unicos/Mk");
281 alpha_tp = ALPHA_TP_INSN;
282 alpha_fptm = ALPHA_FPTM_SU;
286 if (TARGET_IEEE_WITH_INEXACT)
288 if (TARGET_ABI_UNICOSMK)
289 warning ("-mieee-with-inexact not supported on Unicos/Mk");
292 alpha_tp = ALPHA_TP_INSN;
293 alpha_fptm = ALPHA_FPTM_SUI;
299 if (! strcmp (alpha_tp_string, "p"))
300 alpha_tp = ALPHA_TP_PROG;
301 else if (! strcmp (alpha_tp_string, "f"))
302 alpha_tp = ALPHA_TP_FUNC;
303 else if (! strcmp (alpha_tp_string, "i"))
304 alpha_tp = ALPHA_TP_INSN;
306 error ("bad value `%s' for -mtrap-precision switch", alpha_tp_string);
309 if (alpha_fprm_string)
311 if (! strcmp (alpha_fprm_string, "n"))
312 alpha_fprm = ALPHA_FPRM_NORM;
313 else if (! strcmp (alpha_fprm_string, "m"))
314 alpha_fprm = ALPHA_FPRM_MINF;
315 else if (! strcmp (alpha_fprm_string, "c"))
316 alpha_fprm = ALPHA_FPRM_CHOP;
317 else if (! strcmp (alpha_fprm_string,"d"))
318 alpha_fprm = ALPHA_FPRM_DYN;
320 error ("bad value `%s' for -mfp-rounding-mode switch",
324 if (alpha_fptm_string)
326 if (strcmp (alpha_fptm_string, "n") == 0)
327 alpha_fptm = ALPHA_FPTM_N;
328 else if (strcmp (alpha_fptm_string, "u") == 0)
329 alpha_fptm = ALPHA_FPTM_U;
330 else if (strcmp (alpha_fptm_string, "su") == 0)
331 alpha_fptm = ALPHA_FPTM_SU;
332 else if (strcmp (alpha_fptm_string, "sui") == 0)
333 alpha_fptm = ALPHA_FPTM_SUI;
335 error ("bad value `%s' for -mfp-trap-mode switch", alpha_fptm_string);
338 if (alpha_tls_size_string)
340 if (strcmp (alpha_tls_size_string, "16") == 0)
342 else if (strcmp (alpha_tls_size_string, "32") == 0)
344 else if (strcmp (alpha_tls_size_string, "64") == 0)
347 error ("bad value `%s' for -mtls-size switch", alpha_tls_size_string);
351 = TARGET_CPU_DEFAULT & MASK_CPU_EV6 ? PROCESSOR_EV6
352 : (TARGET_CPU_DEFAULT & MASK_CPU_EV5 ? PROCESSOR_EV5 : PROCESSOR_EV4);
354 if (alpha_cpu_string)
356 for (i = 0; cpu_table [i].name; i++)
357 if (! strcmp (alpha_cpu_string, cpu_table [i].name))
359 alpha_cpu = cpu_table [i].processor;
360 target_flags &= ~ (MASK_BWX | MASK_MAX | MASK_FIX | MASK_CIX
361 | MASK_CPU_EV5 | MASK_CPU_EV6);
362 target_flags |= cpu_table [i].flags;
365 if (! cpu_table [i].name)
366 error ("bad value `%s' for -mcpu switch", alpha_cpu_string);
369 if (alpha_tune_string)
371 for (i = 0; cpu_table [i].name; i++)
372 if (! strcmp (alpha_tune_string, cpu_table [i].name))
374 alpha_cpu = cpu_table [i].processor;
377 if (! cpu_table [i].name)
378 error ("bad value `%s' for -mcpu switch", alpha_tune_string);
381 /* Do some sanity checks on the above options. */
383 if (TARGET_ABI_UNICOSMK && alpha_fptm != ALPHA_FPTM_N)
385 warning ("trap mode not supported on Unicos/Mk");
386 alpha_fptm = ALPHA_FPTM_N;
389 if ((alpha_fptm == ALPHA_FPTM_SU || alpha_fptm == ALPHA_FPTM_SUI)
390 && alpha_tp != ALPHA_TP_INSN && ! TARGET_CPU_EV6)
392 warning ("fp software completion requires -mtrap-precision=i");
393 alpha_tp = ALPHA_TP_INSN;
398 /* Except for EV6 pass 1 (not released), we always have precise
399 arithmetic traps. Which means we can do software completion
400 without minding trap shadows. */
401 alpha_tp = ALPHA_TP_PROG;
404 if (TARGET_FLOAT_VAX)
406 if (alpha_fprm == ALPHA_FPRM_MINF || alpha_fprm == ALPHA_FPRM_DYN)
408 warning ("rounding mode not supported for VAX floats");
409 alpha_fprm = ALPHA_FPRM_NORM;
411 if (alpha_fptm == ALPHA_FPTM_SUI)
413 warning ("trap mode not supported for VAX floats");
414 alpha_fptm = ALPHA_FPTM_SU;
416 if (target_flags_explicit & MASK_LONG_DOUBLE_128)
417 warning ("128-bit long double not supported for VAX floats");
418 target_flags &= ~MASK_LONG_DOUBLE_128;
425 if (!alpha_mlat_string)
426 alpha_mlat_string = "L1";
428 if (ISDIGIT ((unsigned char)alpha_mlat_string[0])
429 && (lat = strtol (alpha_mlat_string, &end, 10), *end == '\0'))
431 else if ((alpha_mlat_string[0] == 'L' || alpha_mlat_string[0] == 'l')
432 && ISDIGIT ((unsigned char)alpha_mlat_string[1])
433 && alpha_mlat_string[2] == '\0')
435 static int const cache_latency[][4] =
437 { 3, 30, -1 }, /* ev4 -- Bcache is a guess */
438 { 2, 12, 38 }, /* ev5 -- Bcache from PC164 LMbench numbers */
439 { 3, 12, 30 }, /* ev6 -- Bcache from DS20 LMbench. */
442 lat = alpha_mlat_string[1] - '0';
443 if (lat <= 0 || lat > 3 || cache_latency[alpha_cpu][lat-1] == -1)
445 warning ("L%d cache latency unknown for %s",
446 lat, alpha_cpu_name[alpha_cpu]);
450 lat = cache_latency[alpha_cpu][lat-1];
452 else if (! strcmp (alpha_mlat_string, "main"))
454 /* Most current memories have about 370ns latency. This is
455 a reasonable guess for a fast cpu. */
460 warning ("bad value `%s' for -mmemory-latency", alpha_mlat_string);
464 alpha_memory_latency = lat;
467 /* Default the definition of "small data" to 8 bytes. */
471 /* Infer TARGET_SMALL_DATA from -fpic/-fPIC. */
473 target_flags |= MASK_SMALL_DATA;
474 else if (flag_pic == 2)
475 target_flags &= ~MASK_SMALL_DATA;
477 /* Align labels and loops for optimal branching. */
478 /* ??? Kludge these by not doing anything if we don't optimize and also if
479 we are writing ECOFF symbols to work around a bug in DEC's assembler. */
480 if (optimize > 0 && write_symbols != SDB_DEBUG)
482 if (align_loops <= 0)
484 if (align_jumps <= 0)
487 if (align_functions <= 0)
488 align_functions = 16;
490 /* Acquire a unique set number for our register saves and restores. */
491 alpha_sr_alias_set = new_alias_set ();
493 /* Register variables and functions with the garbage collector. */
495 /* Set up function hooks. */
496 init_machine_status = alpha_init_machine_status;
498 /* Tell the compiler when we're using VAX floating point. */
499 if (TARGET_FLOAT_VAX)
501 REAL_MODE_FORMAT (SFmode) = &vax_f_format;
502 REAL_MODE_FORMAT (DFmode) = &vax_g_format;
503 REAL_MODE_FORMAT (TFmode) = NULL;
507 /* Returns 1 if VALUE is a mask that contains full bytes of zero or ones. */
510 zap_mask (HOST_WIDE_INT value)
514 for (i = 0; i < HOST_BITS_PER_WIDE_INT / HOST_BITS_PER_CHAR;
516 if ((value & 0xff) != 0 && (value & 0xff) != 0xff)
522 /* Returns 1 if OP is either the constant zero or a register. If a
523 register, it must be in the proper mode unless MODE is VOIDmode. */
526 reg_or_0_operand (rtx op, enum machine_mode mode)
528 return op == CONST0_RTX (mode) || register_operand (op, mode);
531 /* Return 1 if OP is a constant in the range of 0-63 (for a shift) or
535 reg_or_6bit_operand (rtx op, enum machine_mode mode)
537 return ((GET_CODE (op) == CONST_INT
538 && (unsigned HOST_WIDE_INT) INTVAL (op) < 64)
539 || register_operand (op, mode));
543 /* Return 1 if OP is an 8-bit constant or any register. */
546 reg_or_8bit_operand (rtx op, enum machine_mode mode)
548 return ((GET_CODE (op) == CONST_INT
549 && (unsigned HOST_WIDE_INT) INTVAL (op) < 0x100)
550 || register_operand (op, mode));
553 /* Return 1 if OP is a constant or any register. */
556 reg_or_const_int_operand (rtx op, enum machine_mode mode)
558 return GET_CODE (op) == CONST_INT || register_operand (op, mode);
561 /* Return 1 if OP is an 8-bit constant. */
564 cint8_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
566 return ((GET_CODE (op) == CONST_INT
567 && (unsigned HOST_WIDE_INT) INTVAL (op) < 0x100));
570 /* Return 1 if the operand is a valid second operand to an add insn. */
573 add_operand (rtx op, enum machine_mode mode)
575 if (GET_CODE (op) == CONST_INT)
576 /* Constraints I, J, O and P are covered by K. */
577 return (CONST_OK_FOR_LETTER_P (INTVAL (op), 'K')
578 || CONST_OK_FOR_LETTER_P (INTVAL (op), 'L'));
580 return register_operand (op, mode);
583 /* Return 1 if the operand is a valid second operand to a sign-extending
587 sext_add_operand (rtx op, enum machine_mode mode)
589 if (GET_CODE (op) == CONST_INT)
590 return (CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')
591 || CONST_OK_FOR_LETTER_P (INTVAL (op), 'O'));
593 return reg_not_elim_operand (op, mode);
596 /* Return 1 if OP is the constant 4 or 8. */
599 const48_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
601 return (GET_CODE (op) == CONST_INT
602 && (INTVAL (op) == 4 || INTVAL (op) == 8));
605 /* Return 1 if OP is a valid first operand to an AND insn. */
608 and_operand (rtx op, enum machine_mode mode)
610 if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == VOIDmode)
611 return (zap_mask (CONST_DOUBLE_LOW (op))
612 && zap_mask (CONST_DOUBLE_HIGH (op)));
614 if (GET_CODE (op) == CONST_INT)
615 return ((unsigned HOST_WIDE_INT) INTVAL (op) < 0x100
616 || (unsigned HOST_WIDE_INT) ~ INTVAL (op) < 0x100
617 || zap_mask (INTVAL (op)));
619 return register_operand (op, mode);
622 /* Return 1 if OP is a valid first operand to an IOR or XOR insn. */
625 or_operand (rtx op, enum machine_mode mode)
627 if (GET_CODE (op) == CONST_INT)
628 return ((unsigned HOST_WIDE_INT) INTVAL (op) < 0x100
629 || (unsigned HOST_WIDE_INT) ~ INTVAL (op) < 0x100);
631 return register_operand (op, mode);
634 /* Return 1 if OP is a constant that is the width, in bits, of an integral
635 mode smaller than DImode. */
638 mode_width_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
640 return (GET_CODE (op) == CONST_INT
641 && (INTVAL (op) == 8 || INTVAL (op) == 16
642 || INTVAL (op) == 32 || INTVAL (op) == 64));
645 /* Return 1 if OP is a constant that is the width of an integral machine mode
646 smaller than an integer. */
649 mode_mask_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
651 if (GET_CODE (op) == CONST_INT)
653 HOST_WIDE_INT value = INTVAL (op);
659 if (value == 0xffffffff)
664 else if (HOST_BITS_PER_WIDE_INT == 32 && GET_CODE (op) == CONST_DOUBLE)
666 if (CONST_DOUBLE_LOW (op) == 0xffffffff && CONST_DOUBLE_HIGH (op) == 0)
673 /* Return 1 if OP is a multiple of 8 less than 64. */
676 mul8_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
678 return (GET_CODE (op) == CONST_INT
679 && (unsigned HOST_WIDE_INT) INTVAL (op) < 64
680 && (INTVAL (op) & 7) == 0);
683 /* Return 1 if OP is the zero constant for MODE. */
686 const0_operand (rtx op, enum machine_mode mode)
688 return op == CONST0_RTX (mode);
691 /* Return 1 if OP is a hard floating-point register. */
694 hard_fp_register_operand (rtx op, enum machine_mode mode)
696 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
699 if (GET_CODE (op) == SUBREG)
700 op = SUBREG_REG (op);
701 return GET_CODE (op) == REG && REGNO_REG_CLASS (REGNO (op)) == FLOAT_REGS;
704 /* Return 1 if OP is a hard general register. */
707 hard_int_register_operand (rtx op, enum machine_mode mode)
709 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
712 if (GET_CODE (op) == SUBREG)
713 op = SUBREG_REG (op);
714 return GET_CODE (op) == REG && REGNO_REG_CLASS (REGNO (op)) == GENERAL_REGS;
717 /* Return 1 if OP is a register or a constant integer. */
721 reg_or_cint_operand (rtx op, enum machine_mode mode)
723 return (GET_CODE (op) == CONST_INT
724 || register_operand (op, mode));
727 /* Return 1 if OP is something that can be reloaded into a register;
728 if it is a MEM, it need not be valid. */
731 some_operand (rtx op, enum machine_mode mode)
733 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
736 switch (GET_CODE (op))
750 return some_operand (SUBREG_REG (op), VOIDmode);
759 /* Likewise, but don't accept constants. */
762 some_ni_operand (rtx op, enum machine_mode mode)
764 if (GET_MODE (op) != mode && mode != VOIDmode)
767 if (GET_CODE (op) == SUBREG)
768 op = SUBREG_REG (op);
770 return (GET_CODE (op) == REG || GET_CODE (op) == MEM);
773 /* Return 1 if OP is a valid operand for the source of a move insn. */
776 input_operand (rtx op, enum machine_mode mode)
778 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
781 if (GET_MODE_CLASS (mode) == MODE_FLOAT && GET_MODE (op) != mode)
784 switch (GET_CODE (op))
789 if (TARGET_EXPLICIT_RELOCS)
791 /* We don't split symbolic operands into something unintelligable
792 until after reload, but we do not wish non-small, non-global
793 symbolic operands to be reconstructed from their high/lo_sum
795 return (small_symbolic_operand (op, mode)
796 || global_symbolic_operand (op, mode)
797 || gotdtp_symbolic_operand (op, mode)
798 || gottp_symbolic_operand (op, mode));
801 /* This handles both the Windows/NT and OSF cases. */
802 return mode == ptr_mode || mode == DImode;
805 return (TARGET_EXPLICIT_RELOCS
806 && local_symbolic_operand (XEXP (op, 0), mode));
812 if (register_operand (op, mode))
814 /* ... fall through ... */
816 return ((TARGET_BWX || (mode != HImode && mode != QImode))
817 && general_operand (op, mode));
821 return op == CONST0_RTX (mode);
824 return mode == QImode || mode == HImode || add_operand (op, mode);
833 /* Return 1 if OP is a SYMBOL_REF for a function known to be in this
834 file, and in the same section as the current function. */
837 samegp_function_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
839 if (GET_CODE (op) != SYMBOL_REF)
842 /* Easy test for recursion. */
843 if (op == XEXP (DECL_RTL (current_function_decl), 0))
846 /* Functions that are not local can be overridden, and thus may
847 not share the same gp. */
848 if (! SYMBOL_REF_LOCAL_P (op))
851 /* If -msmall-data is in effect, assume that there is only one GP
852 for the module, and so any local symbol has this property. We
853 need explicit relocations to be able to enforce this for symbols
854 not defined in this unit of translation, however. */
855 if (TARGET_EXPLICIT_RELOCS && TARGET_SMALL_DATA)
858 /* Functions that are not external are defined in this UoT,
859 and thus must share the same gp. */
860 return ! SYMBOL_REF_EXTERNAL_P (op);
863 /* Return 1 if OP is a SYMBOL_REF for which we can make a call via bsr. */
866 direct_call_operand (rtx op, enum machine_mode mode)
868 tree op_decl, cfun_sec, op_sec;
870 /* Must share the same GP. */
871 if (!samegp_function_operand (op, mode))
874 /* If profiling is implemented via linker tricks, we can't jump
875 to the nogp alternate entry point. Note that current_function_profile
876 would not be correct, since that doesn't indicate if the target
877 function uses profiling. */
878 /* ??? TARGET_PROFILING_NEEDS_GP isn't really the right test,
879 but is approximately correct for the OSF ABIs. Don't know
880 what to do for VMS, NT, or UMK. */
881 if (!TARGET_PROFILING_NEEDS_GP && profile_flag)
884 /* Must be a function. In some cases folks create thunks in static
885 data structures and then make calls to them. If we allow the
886 direct call, we'll get an error from the linker about !samegp reloc
887 against a symbol without a .prologue directive. */
888 if (!SYMBOL_REF_FUNCTION_P (op))
891 /* Must be "near" so that the branch is assumed to reach. With
892 -msmall-text, this is assumed true of all local symbols. Since
893 we've already checked samegp, locality is already assured. */
894 if (TARGET_SMALL_TEXT)
897 /* Otherwise, a decl is "near" if it is defined in the same section. */
898 if (flag_function_sections)
901 op_decl = SYMBOL_REF_DECL (op);
902 if (DECL_ONE_ONLY (current_function_decl)
903 || (op_decl && DECL_ONE_ONLY (op_decl)))
906 cfun_sec = DECL_SECTION_NAME (current_function_decl);
907 op_sec = op_decl ? DECL_SECTION_NAME (op_decl) : NULL;
908 return ((!cfun_sec && !op_sec)
909 || (cfun_sec && op_sec
910 && strcmp (TREE_STRING_POINTER (cfun_sec),
911 TREE_STRING_POINTER (op_sec)) == 0));
914 /* Return true if OP is a LABEL_REF, or SYMBOL_REF or CONST referencing
915 a (non-tls) variable known to be defined in this file. */
918 local_symbolic_operand (rtx op, enum machine_mode mode)
920 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
923 if (GET_CODE (op) == LABEL_REF)
926 if (GET_CODE (op) == CONST
927 && GET_CODE (XEXP (op, 0)) == PLUS
928 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT)
929 op = XEXP (XEXP (op, 0), 0);
931 if (GET_CODE (op) != SYMBOL_REF)
934 return SYMBOL_REF_LOCAL_P (op) && !SYMBOL_REF_TLS_MODEL (op);
937 /* Return true if OP is a SYMBOL_REF or CONST referencing a variable
938 known to be defined in this file in the small data area. */
941 small_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
943 if (! TARGET_SMALL_DATA)
946 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
949 if (GET_CODE (op) == CONST
950 && GET_CODE (XEXP (op, 0)) == PLUS
951 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT)
952 op = XEXP (XEXP (op, 0), 0);
954 if (GET_CODE (op) != SYMBOL_REF)
957 /* ??? There's no encode_section_info equivalent for the rtl
958 constant pool, so SYMBOL_FLAG_SMALL never gets set. */
959 if (CONSTANT_POOL_ADDRESS_P (op))
960 return GET_MODE_SIZE (get_pool_mode (op)) <= g_switch_value;
962 return (SYMBOL_REF_LOCAL_P (op)
963 && SYMBOL_REF_SMALL_P (op)
964 && SYMBOL_REF_TLS_MODEL (op) == 0);
967 /* Return true if OP is a SYMBOL_REF or CONST referencing a variable
968 not known (or known not) to be defined in this file. */
971 global_symbolic_operand (rtx op, enum machine_mode mode)
973 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
976 if (GET_CODE (op) == CONST
977 && GET_CODE (XEXP (op, 0)) == PLUS
978 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT)
979 op = XEXP (XEXP (op, 0), 0);
981 if (GET_CODE (op) != SYMBOL_REF)
984 return !SYMBOL_REF_LOCAL_P (op) && !SYMBOL_REF_TLS_MODEL (op);
987 /* Return 1 if OP is a valid operand for the MEM of a CALL insn. */
990 call_operand (rtx op, enum machine_mode mode)
995 if (GET_CODE (op) == REG)
999 /* Disallow virtual registers to cope with pathological test cases
1000 such as compile/930117-1.c in which the virtual reg decomposes
1001 to the frame pointer. Which is a hard reg that is not $27. */
1002 return (REGNO (op) == 27 || REGNO (op) > LAST_VIRTUAL_REGISTER);
1007 if (TARGET_ABI_UNICOSMK)
1009 if (GET_CODE (op) == SYMBOL_REF)
1015 /* Returns 1 if OP is a symbolic operand, i.e. a symbol_ref or a label_ref,
1016 possibly with an offset. */
1019 symbolic_operand (rtx op, enum machine_mode mode)
1021 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
1023 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
1025 if (GET_CODE (op) == CONST
1026 && GET_CODE (XEXP (op,0)) == PLUS
1027 && GET_CODE (XEXP (XEXP (op,0), 0)) == SYMBOL_REF
1028 && GET_CODE (XEXP (XEXP (op,0), 1)) == CONST_INT)
1033 /* Return true if OP is valid for a particular TLS relocation. */
1036 tls_symbolic_operand_1 (rtx op, enum machine_mode mode, int size, int unspec)
1038 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
1041 if (GET_CODE (op) != CONST)
1045 if (GET_CODE (op) != UNSPEC || XINT (op, 1) != unspec)
1047 op = XVECEXP (op, 0, 0);
1049 if (GET_CODE (op) != SYMBOL_REF)
1052 if (SYMBOL_REF_LOCAL_P (op))
1054 if (alpha_tls_size > size)
1063 switch (SYMBOL_REF_TLS_MODEL (op))
1065 case TLS_MODEL_LOCAL_DYNAMIC:
1066 return unspec == UNSPEC_DTPREL;
1067 case TLS_MODEL_INITIAL_EXEC:
1068 return unspec == UNSPEC_TPREL && size == 64;
1069 case TLS_MODEL_LOCAL_EXEC:
1070 return unspec == UNSPEC_TPREL;
1076 /* Return true if OP is valid for 16-bit DTP relative relocations. */
1079 dtp16_symbolic_operand (rtx op, enum machine_mode mode)
1081 return tls_symbolic_operand_1 (op, mode, 16, UNSPEC_DTPREL);
1084 /* Return true if OP is valid for 32-bit DTP relative relocations. */
1087 dtp32_symbolic_operand (rtx op, enum machine_mode mode)
1089 return tls_symbolic_operand_1 (op, mode, 32, UNSPEC_DTPREL);
1092 /* Return true if OP is valid for 64-bit DTP relative relocations. */
1095 gotdtp_symbolic_operand (rtx op, enum machine_mode mode)
1097 return tls_symbolic_operand_1 (op, mode, 64, UNSPEC_DTPREL);
1100 /* Return true if OP is valid for 16-bit TP relative relocations. */
1103 tp16_symbolic_operand (rtx op, enum machine_mode mode)
1105 return tls_symbolic_operand_1 (op, mode, 16, UNSPEC_TPREL);
1108 /* Return true if OP is valid for 32-bit TP relative relocations. */
1111 tp32_symbolic_operand (rtx op, enum machine_mode mode)
1113 return tls_symbolic_operand_1 (op, mode, 32, UNSPEC_TPREL);
1116 /* Return true if OP is valid for 64-bit TP relative relocations. */
1119 gottp_symbolic_operand (rtx op, enum machine_mode mode)
1121 return tls_symbolic_operand_1 (op, mode, 64, UNSPEC_TPREL);
1124 /* Return 1 if OP is a valid Alpha comparison operator. Here we know which
1125 comparisons are valid in which insn. */
1128 alpha_comparison_operator (rtx op, enum machine_mode mode)
1130 enum rtx_code code = GET_CODE (op);
1132 if (mode != GET_MODE (op) && mode != VOIDmode)
1135 return (code == EQ || code == LE || code == LT
1136 || code == LEU || code == LTU);
1139 /* Return 1 if OP is a valid Alpha comparison operator against zero.
1140 Here we know which comparisons are valid in which insn. */
1143 alpha_zero_comparison_operator (rtx op, enum machine_mode mode)
1145 enum rtx_code code = GET_CODE (op);
1147 if (mode != GET_MODE (op) && mode != VOIDmode)
1150 return (code == EQ || code == NE || code == LE || code == LT
1151 || code == LEU || code == LTU);
1154 /* Return 1 if OP is a valid Alpha swapped comparison operator. */
1157 alpha_swapped_comparison_operator (rtx op, enum machine_mode mode)
1161 if ((mode != GET_MODE (op) && mode != VOIDmode)
1162 || !COMPARISON_P (op))
1165 code = swap_condition (GET_CODE (op));
1166 return (code == EQ || code == LE || code == LT
1167 || code == LEU || code == LTU);
1170 /* Return 1 if OP is a signed comparison operation. */
1173 signed_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1175 enum rtx_code code = GET_CODE (op);
1177 if (mode != GET_MODE (op) && mode != VOIDmode)
1180 return (code == EQ || code == NE
1181 || code == LE || code == LT
1182 || code == GE || code == GT);
1185 /* Return 1 if OP is a valid Alpha floating point comparison operator.
1186 Here we know which comparisons are valid in which insn. */
1189 alpha_fp_comparison_operator (rtx op, enum machine_mode mode)
1191 enum rtx_code code = GET_CODE (op);
1193 if (mode != GET_MODE (op) && mode != VOIDmode)
1196 return (code == EQ || code == LE || code == LT || code == UNORDERED);
1199 /* Return 1 if this is a divide or modulus operator. */
1202 divmod_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1204 enum rtx_code code = GET_CODE (op);
1206 return (code == DIV || code == MOD || code == UDIV || code == UMOD);
1209 /* Return 1 if this is a float->int conversion operator. */
1212 fix_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1214 enum rtx_code code = GET_CODE (op);
1216 return (code == FIX || code == UNSIGNED_FIX);
1219 /* Return 1 if this memory address is a known aligned register plus
1220 a constant. It must be a valid address. This means that we can do
1221 this as an aligned reference plus some offset.
1223 Take into account what reload will do. */
1226 aligned_memory_operand (rtx op, enum machine_mode mode)
1230 if (reload_in_progress)
1233 if (GET_CODE (tmp) == SUBREG)
1234 tmp = SUBREG_REG (tmp);
1235 if (GET_CODE (tmp) == REG
1236 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER)
1238 op = reg_equiv_memory_loc[REGNO (tmp)];
1244 if (GET_CODE (op) != MEM)
1246 if (MEM_ALIGN (op) >= 32)
1250 /* LEGITIMIZE_RELOAD_ADDRESS creates (plus (plus reg const_hi) const_lo)
1251 sorts of constructs. Dig for the real base register. */
1252 if (reload_in_progress
1253 && GET_CODE (op) == PLUS
1254 && GET_CODE (XEXP (op, 0)) == PLUS)
1255 base = XEXP (XEXP (op, 0), 0);
1258 if (! memory_address_p (mode, op))
1260 base = (GET_CODE (op) == PLUS ? XEXP (op, 0) : op);
1263 return (GET_CODE (base) == REG && REGNO_POINTER_ALIGN (REGNO (base)) >= 32);
1266 /* Similar, but return 1 if OP is a MEM which is not alignable. */
1269 unaligned_memory_operand (rtx op, enum machine_mode mode)
1273 if (reload_in_progress)
1276 if (GET_CODE (tmp) == SUBREG)
1277 tmp = SUBREG_REG (tmp);
1278 if (GET_CODE (tmp) == REG
1279 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER)
1281 op = reg_equiv_memory_loc[REGNO (tmp)];
1287 if (GET_CODE (op) != MEM)
1289 if (MEM_ALIGN (op) >= 32)
1293 /* LEGITIMIZE_RELOAD_ADDRESS creates (plus (plus reg const_hi) const_lo)
1294 sorts of constructs. Dig for the real base register. */
1295 if (reload_in_progress
1296 && GET_CODE (op) == PLUS
1297 && GET_CODE (XEXP (op, 0)) == PLUS)
1298 base = XEXP (XEXP (op, 0), 0);
1301 if (! memory_address_p (mode, op))
1303 base = (GET_CODE (op) == PLUS ? XEXP (op, 0) : op);
1306 return (GET_CODE (base) == REG && REGNO_POINTER_ALIGN (REGNO (base)) < 32);
1309 /* Return 1 if OP is either a register or an unaligned memory location. */
1312 reg_or_unaligned_mem_operand (rtx op, enum machine_mode mode)
1314 return register_operand (op, mode) || unaligned_memory_operand (op, mode);
1317 /* Return 1 if OP is any memory location. During reload a pseudo matches. */
1320 any_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1322 return (GET_CODE (op) == MEM
1323 || (GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == REG)
1324 || (reload_in_progress && GET_CODE (op) == REG
1325 && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1326 || (reload_in_progress && GET_CODE (op) == SUBREG
1327 && GET_CODE (SUBREG_REG (op)) == REG
1328 && REGNO (SUBREG_REG (op)) >= FIRST_PSEUDO_REGISTER));
1331 /* Returns 1 if OP is not an eliminable register.
1333 This exists to cure a pathological abort in the s8addq (et al) patterns,
1335 long foo () { long t; bar(); return (long) &t * 26107; }
1337 which run afoul of a hack in reload to cure a (presumably) similar
1338 problem with lea-type instructions on other targets. But there is
1339 one of us and many of them, so work around the problem by selectively
1340 preventing combine from making the optimization. */
1343 reg_not_elim_operand (rtx op, enum machine_mode mode)
1346 if (GET_CODE (op) == SUBREG)
1347 inner = SUBREG_REG (op);
1348 if (inner == frame_pointer_rtx || inner == arg_pointer_rtx)
1351 return register_operand (op, mode);
1354 /* Return 1 is OP is a memory location that is not a reference (using
1355 an AND) to an unaligned location. Take into account what reload
1359 normal_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1361 if (reload_in_progress)
1364 if (GET_CODE (tmp) == SUBREG)
1365 tmp = SUBREG_REG (tmp);
1366 if (GET_CODE (tmp) == REG
1367 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER)
1369 op = reg_equiv_memory_loc[REGNO (tmp)];
1371 /* This may not have been assigned an equivalent address if it will
1372 be eliminated. In that case, it doesn't matter what we do. */
1378 return GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) != AND;
1381 /* Accept a register, but not a subreg of any kind. This allows us to
1382 avoid pathological cases in reload wrt data movement common in
1383 int->fp conversion. */
1386 reg_no_subreg_operand (rtx op, enum machine_mode mode)
1388 if (GET_CODE (op) != REG)
1390 return register_operand (op, mode);
1393 /* Recognize an addition operation that includes a constant. Used to
1394 convince reload to canonize (plus (plus reg c1) c2) during register
1398 addition_operation (rtx op, enum machine_mode mode)
1400 if (GET_MODE (op) != mode && mode != VOIDmode)
1402 if (GET_CODE (op) == PLUS
1403 && register_operand (XEXP (op, 0), mode)
1404 && GET_CODE (XEXP (op, 1)) == CONST_INT
1405 && CONST_OK_FOR_LETTER_P (INTVAL (XEXP (op, 1)), 'K'))
1410 /* Implements CONST_OK_FOR_LETTER_P. Return true if the value matches
1411 the range defined for C in [I-P]. */
1414 alpha_const_ok_for_letter_p (HOST_WIDE_INT value, int c)
1419 /* An unsigned 8 bit constant. */
1420 return (unsigned HOST_WIDE_INT) value < 0x100;
1422 /* The constant zero. */
1425 /* A signed 16 bit constant. */
1426 return (unsigned HOST_WIDE_INT) (value + 0x8000) < 0x10000;
1428 /* A shifted signed 16 bit constant appropriate for LDAH. */
1429 return ((value & 0xffff) == 0
1430 && ((value) >> 31 == -1 || value >> 31 == 0));
1432 /* A constant that can be AND'ed with using a ZAP insn. */
1433 return zap_mask (value);
1435 /* A complemented unsigned 8 bit constant. */
1436 return (unsigned HOST_WIDE_INT) (~ value) < 0x100;
1438 /* A negated unsigned 8 bit constant. */
1439 return (unsigned HOST_WIDE_INT) (- value) < 0x100;
1441 /* The constant 1, 2 or 3. */
1442 return value == 1 || value == 2 || value == 3;
1449 /* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
1450 matches for C in [GH]. */
1453 alpha_const_double_ok_for_letter_p (rtx value, int c)
1458 /* The floating point zero constant. */
1459 return (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT
1460 && value == CONST0_RTX (GET_MODE (value)));
1463 /* A valid operand of a ZAP insn. */
1464 return (GET_MODE (value) == VOIDmode
1465 && zap_mask (CONST_DOUBLE_LOW (value))
1466 && zap_mask (CONST_DOUBLE_HIGH (value)));
1473 /* Implements CONST_DOUBLE_OK_FOR_LETTER_P. Return true if VALUE
1477 alpha_extra_constraint (rtx value, int c)
1482 return normal_memory_operand (value, VOIDmode);
1484 return direct_call_operand (value, Pmode);
1486 return (GET_CODE (value) == CONST_INT
1487 && (unsigned HOST_WIDE_INT) INTVAL (value) < 64);
1489 return GET_CODE (value) == HIGH;
1491 return TARGET_ABI_UNICOSMK && symbolic_operand (value, VOIDmode);
1493 return (GET_CODE (value) == CONST_VECTOR
1494 && value == CONST0_RTX (GET_MODE (value)));
1500 /* Return 1 if this function can directly return via $26. */
1503 direct_return (void)
1505 return (! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK
1507 && alpha_sa_size () == 0
1508 && get_frame_size () == 0
1509 && current_function_outgoing_args_size == 0
1510 && current_function_pretend_args_size == 0);
1513 /* Return the ADDR_VEC associated with a tablejump insn. */
1516 alpha_tablejump_addr_vec (rtx insn)
1520 tmp = JUMP_LABEL (insn);
1523 tmp = NEXT_INSN (tmp);
1526 if (GET_CODE (tmp) == JUMP_INSN
1527 && GET_CODE (PATTERN (tmp)) == ADDR_DIFF_VEC)
1528 return PATTERN (tmp);
1532 /* Return the label of the predicted edge, or CONST0_RTX if we don't know. */
1535 alpha_tablejump_best_label (rtx insn)
1537 rtx jump_table = alpha_tablejump_addr_vec (insn);
1538 rtx best_label = NULL_RTX;
1540 /* ??? Once the CFG doesn't keep getting completely rebuilt, look
1541 there for edge frequency counts from profile data. */
1545 int n_labels = XVECLEN (jump_table, 1);
1546 int best_count = -1;
1549 for (i = 0; i < n_labels; i++)
1553 for (j = i + 1; j < n_labels; j++)
1554 if (XEXP (XVECEXP (jump_table, 1, i), 0)
1555 == XEXP (XVECEXP (jump_table, 1, j), 0))
1558 if (count > best_count)
1559 best_count = count, best_label = XVECEXP (jump_table, 1, i);
1563 return best_label ? best_label : const0_rtx;
1566 /* Return the TLS model to use for SYMBOL. */
1568 static enum tls_model
1569 tls_symbolic_operand_type (rtx symbol)
1571 enum tls_model model;
1573 if (GET_CODE (symbol) != SYMBOL_REF)
1575 model = SYMBOL_REF_TLS_MODEL (symbol);
1577 /* Local-exec with a 64-bit size is the same code as initial-exec. */
1578 if (model == TLS_MODEL_LOCAL_EXEC && alpha_tls_size == 64)
1579 model = TLS_MODEL_INITIAL_EXEC;
1584 /* Return true if the function DECL will share the same GP as any
1585 function in the current unit of translation. */
1588 decl_has_samegp (tree decl)
1590 /* Functions that are not local can be overridden, and thus may
1591 not share the same gp. */
1592 if (!(*targetm.binds_local_p) (decl))
1595 /* If -msmall-data is in effect, assume that there is only one GP
1596 for the module, and so any local symbol has this property. We
1597 need explicit relocations to be able to enforce this for symbols
1598 not defined in this unit of translation, however. */
1599 if (TARGET_EXPLICIT_RELOCS && TARGET_SMALL_DATA)
1602 /* Functions that are not external are defined in this UoT. */
1603 /* ??? Irritatingly, static functions not yet emitted are still
1604 marked "external". Apply this to non-static functions only. */
1605 return !TREE_PUBLIC (decl) || !DECL_EXTERNAL (decl);
1608 /* Return true if EXP should be placed in the small data section. */
1611 alpha_in_small_data_p (tree exp)
1613 /* We want to merge strings, so we never consider them small data. */
1614 if (TREE_CODE (exp) == STRING_CST)
1617 /* Functions are never in the small data area. Duh. */
1618 if (TREE_CODE (exp) == FUNCTION_DECL)
1621 if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp))
1623 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp));
1624 if (strcmp (section, ".sdata") == 0
1625 || strcmp (section, ".sbss") == 0)
1630 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp));
1632 /* If this is an incomplete type with size 0, then we can't put it
1633 in sdata because it might be too big when completed. */
1634 if (size > 0 && (unsigned HOST_WIDE_INT) size <= g_switch_value)
1641 #if TARGET_ABI_OPEN_VMS
1643 alpha_linkage_symbol_p (const char *symname)
1645 int symlen = strlen (symname);
1648 return strcmp (&symname [symlen - 4], "..lk") == 0;
1653 #define LINKAGE_SYMBOL_REF_P(X) \
1654 ((GET_CODE (X) == SYMBOL_REF \
1655 && alpha_linkage_symbol_p (XSTR (X, 0))) \
1656 || (GET_CODE (X) == CONST \
1657 && GET_CODE (XEXP (X, 0)) == PLUS \
1658 && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF \
1659 && alpha_linkage_symbol_p (XSTR (XEXP (XEXP (X, 0), 0), 0))))
1662 /* legitimate_address_p recognizes an RTL expression that is a valid
1663 memory address for an instruction. The MODE argument is the
1664 machine mode for the MEM expression that wants to use this address.
1666 For Alpha, we have either a constant address or the sum of a
1667 register and a constant address, or just a register. For DImode,
1668 any of those forms can be surrounded with an AND that clear the
1669 low-order three bits; this is an "unaligned" access. */
1672 alpha_legitimate_address_p (enum machine_mode mode, rtx x, int strict)
1674 /* If this is an ldq_u type address, discard the outer AND. */
1676 && GET_CODE (x) == AND
1677 && GET_CODE (XEXP (x, 1)) == CONST_INT
1678 && INTVAL (XEXP (x, 1)) == -8)
1681 /* Discard non-paradoxical subregs. */
1682 if (GET_CODE (x) == SUBREG
1683 && (GET_MODE_SIZE (GET_MODE (x))
1684 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
1687 /* Unadorned general registers are valid. */
1690 ? STRICT_REG_OK_FOR_BASE_P (x)
1691 : NONSTRICT_REG_OK_FOR_BASE_P (x)))
1694 /* Constant addresses (i.e. +/- 32k) are valid. */
1695 if (CONSTANT_ADDRESS_P (x))
1698 #if TARGET_ABI_OPEN_VMS
1699 if (LINKAGE_SYMBOL_REF_P (x))
1703 /* Register plus a small constant offset is valid. */
1704 if (GET_CODE (x) == PLUS)
1706 rtx ofs = XEXP (x, 1);
1709 /* Discard non-paradoxical subregs. */
1710 if (GET_CODE (x) == SUBREG
1711 && (GET_MODE_SIZE (GET_MODE (x))
1712 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
1718 && NONSTRICT_REG_OK_FP_BASE_P (x)
1719 && GET_CODE (ofs) == CONST_INT)
1722 ? STRICT_REG_OK_FOR_BASE_P (x)
1723 : NONSTRICT_REG_OK_FOR_BASE_P (x))
1724 && CONSTANT_ADDRESS_P (ofs))
1729 /* If we're managing explicit relocations, LO_SUM is valid, as
1730 are small data symbols. */
1731 else if (TARGET_EXPLICIT_RELOCS)
1733 if (small_symbolic_operand (x, Pmode))
1736 if (GET_CODE (x) == LO_SUM)
1738 rtx ofs = XEXP (x, 1);
1741 /* Discard non-paradoxical subregs. */
1742 if (GET_CODE (x) == SUBREG
1743 && (GET_MODE_SIZE (GET_MODE (x))
1744 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
1747 /* Must have a valid base register. */
1750 ? STRICT_REG_OK_FOR_BASE_P (x)
1751 : NONSTRICT_REG_OK_FOR_BASE_P (x))))
1754 /* The symbol must be local. */
1755 if (local_symbolic_operand (ofs, Pmode)
1756 || dtp32_symbolic_operand (ofs, Pmode)
1757 || tp32_symbolic_operand (ofs, Pmode))
1765 /* Build the SYMBOL_REF for __tls_get_addr. */
1767 static GTY(()) rtx tls_get_addr_libfunc;
1770 get_tls_get_addr (void)
1772 if (!tls_get_addr_libfunc)
1773 tls_get_addr_libfunc = init_one_libfunc ("__tls_get_addr");
1774 return tls_get_addr_libfunc;
1777 /* Try machine-dependent ways of modifying an illegitimate address
1778 to be legitimate. If we find one, return the new, valid address. */
1781 alpha_legitimize_address (rtx x, rtx scratch,
1782 enum machine_mode mode ATTRIBUTE_UNUSED)
1784 HOST_WIDE_INT addend;
1786 /* If the address is (plus reg const_int) and the CONST_INT is not a
1787 valid offset, compute the high part of the constant and add it to
1788 the register. Then our address is (plus temp low-part-const). */
1789 if (GET_CODE (x) == PLUS
1790 && GET_CODE (XEXP (x, 0)) == REG
1791 && GET_CODE (XEXP (x, 1)) == CONST_INT
1792 && ! CONSTANT_ADDRESS_P (XEXP (x, 1)))
1794 addend = INTVAL (XEXP (x, 1));
1799 /* If the address is (const (plus FOO const_int)), find the low-order
1800 part of the CONST_INT. Then load FOO plus any high-order part of the
1801 CONST_INT into a register. Our address is (plus reg low-part-const).
1802 This is done to reduce the number of GOT entries. */
1804 && GET_CODE (x) == CONST
1805 && GET_CODE (XEXP (x, 0)) == PLUS
1806 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
1808 addend = INTVAL (XEXP (XEXP (x, 0), 1));
1809 x = force_reg (Pmode, XEXP (XEXP (x, 0), 0));
1813 /* If we have a (plus reg const), emit the load as in (2), then add
1814 the two registers, and finally generate (plus reg low-part-const) as
1817 && GET_CODE (x) == PLUS
1818 && GET_CODE (XEXP (x, 0)) == REG
1819 && GET_CODE (XEXP (x, 1)) == CONST
1820 && GET_CODE (XEXP (XEXP (x, 1), 0)) == PLUS
1821 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == CONST_INT)
1823 addend = INTVAL (XEXP (XEXP (XEXP (x, 1), 0), 1));
1824 x = expand_simple_binop (Pmode, PLUS, XEXP (x, 0),
1825 XEXP (XEXP (XEXP (x, 1), 0), 0),
1826 NULL_RTX, 1, OPTAB_LIB_WIDEN);
1830 /* If this is a local symbol, split the address into HIGH/LO_SUM parts. */
1831 if (TARGET_EXPLICIT_RELOCS && symbolic_operand (x, Pmode))
1833 rtx r0, r16, eqv, tga, tp, insn, dest, seq;
1835 switch (tls_symbolic_operand_type (x))
1837 case TLS_MODEL_GLOBAL_DYNAMIC:
1840 r0 = gen_rtx_REG (Pmode, 0);
1841 r16 = gen_rtx_REG (Pmode, 16);
1842 tga = get_tls_get_addr ();
1843 dest = gen_reg_rtx (Pmode);
1844 seq = GEN_INT (alpha_next_sequence_number++);
1846 emit_insn (gen_movdi_er_tlsgd (r16, pic_offset_table_rtx, x, seq));
1847 insn = gen_call_value_osf_tlsgd (r0, tga, seq);
1848 insn = emit_call_insn (insn);
1849 CONST_OR_PURE_CALL_P (insn) = 1;
1850 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r16);
1852 insn = get_insns ();
1855 emit_libcall_block (insn, dest, r0, x);
1858 case TLS_MODEL_LOCAL_DYNAMIC:
1861 r0 = gen_rtx_REG (Pmode, 0);
1862 r16 = gen_rtx_REG (Pmode, 16);
1863 tga = get_tls_get_addr ();
1864 scratch = gen_reg_rtx (Pmode);
1865 seq = GEN_INT (alpha_next_sequence_number++);
1867 emit_insn (gen_movdi_er_tlsldm (r16, pic_offset_table_rtx, seq));
1868 insn = gen_call_value_osf_tlsldm (r0, tga, seq);
1869 insn = emit_call_insn (insn);
1870 CONST_OR_PURE_CALL_P (insn) = 1;
1871 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r16);
1873 insn = get_insns ();
1876 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
1877 UNSPEC_TLSLDM_CALL);
1878 emit_libcall_block (insn, scratch, r0, eqv);
1880 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_DTPREL);
1881 eqv = gen_rtx_CONST (Pmode, eqv);
1883 if (alpha_tls_size == 64)
1885 dest = gen_reg_rtx (Pmode);
1886 emit_insn (gen_rtx_SET (VOIDmode, dest, eqv));
1887 emit_insn (gen_adddi3 (dest, dest, scratch));
1890 if (alpha_tls_size == 32)
1892 insn = gen_rtx_HIGH (Pmode, eqv);
1893 insn = gen_rtx_PLUS (Pmode, scratch, insn);
1894 scratch = gen_reg_rtx (Pmode);
1895 emit_insn (gen_rtx_SET (VOIDmode, scratch, insn));
1897 return gen_rtx_LO_SUM (Pmode, scratch, eqv);
1899 case TLS_MODEL_INITIAL_EXEC:
1900 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_TPREL);
1901 eqv = gen_rtx_CONST (Pmode, eqv);
1902 tp = gen_reg_rtx (Pmode);
1903 scratch = gen_reg_rtx (Pmode);
1904 dest = gen_reg_rtx (Pmode);
1906 emit_insn (gen_load_tp (tp));
1907 emit_insn (gen_rtx_SET (VOIDmode, scratch, eqv));
1908 emit_insn (gen_adddi3 (dest, tp, scratch));
1911 case TLS_MODEL_LOCAL_EXEC:
1912 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_TPREL);
1913 eqv = gen_rtx_CONST (Pmode, eqv);
1914 tp = gen_reg_rtx (Pmode);
1916 emit_insn (gen_load_tp (tp));
1917 if (alpha_tls_size == 32)
1919 insn = gen_rtx_HIGH (Pmode, eqv);
1920 insn = gen_rtx_PLUS (Pmode, tp, insn);
1921 tp = gen_reg_rtx (Pmode);
1922 emit_insn (gen_rtx_SET (VOIDmode, tp, insn));
1924 return gen_rtx_LO_SUM (Pmode, tp, eqv);
1927 if (local_symbolic_operand (x, Pmode))
1929 if (small_symbolic_operand (x, Pmode))
1933 if (!no_new_pseudos)
1934 scratch = gen_reg_rtx (Pmode);
1935 emit_insn (gen_rtx_SET (VOIDmode, scratch,
1936 gen_rtx_HIGH (Pmode, x)));
1937 return gen_rtx_LO_SUM (Pmode, scratch, x);
1946 HOST_WIDE_INT low, high;
1948 low = ((addend & 0xffff) ^ 0x8000) - 0x8000;
1950 high = ((addend & 0xffffffff) ^ 0x80000000) - 0x80000000;
1954 x = expand_simple_binop (Pmode, PLUS, x, GEN_INT (addend),
1955 (no_new_pseudos ? scratch : NULL_RTX),
1956 1, OPTAB_LIB_WIDEN);
1958 x = expand_simple_binop (Pmode, PLUS, x, GEN_INT (high),
1959 (no_new_pseudos ? scratch : NULL_RTX),
1960 1, OPTAB_LIB_WIDEN);
1962 return plus_constant (x, low);
1966 /* We do not allow indirect calls to be optimized into sibling calls, nor
1967 can we allow a call to a function with a different GP to be optimized
1971 alpha_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
1973 /* Can't do indirect tail calls, since we don't know if the target
1974 uses the same GP. */
1978 /* Otherwise, we can make a tail call if the target function shares
1980 return decl_has_samegp (decl);
1983 /* For TARGET_EXPLICIT_RELOCS, we don't obfuscate a SYMBOL_REF to a
1984 small symbolic operand until after reload. At which point we need
1985 to replace (mem (symbol_ref)) with (mem (lo_sum $29 symbol_ref))
1986 so that sched2 has the proper dependency information. */
1989 some_small_symbolic_operand_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
1993 /* Don't re-split. */
1994 if (GET_CODE (x) == LO_SUM)
1997 return small_symbolic_operand (x, Pmode) != 0;
2001 some_small_symbolic_operand (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
2003 return for_each_rtx (&x, some_small_symbolic_operand_1, NULL);
2007 split_small_symbolic_operand_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
2011 /* Don't re-split. */
2012 if (GET_CODE (x) == LO_SUM)
2015 if (small_symbolic_operand (x, Pmode))
2017 x = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, x);
2026 split_small_symbolic_operand (rtx x)
2029 for_each_rtx (&x, split_small_symbolic_operand_1, NULL);
2033 /* Indicate that INSN cannot be duplicated. This is true for any insn
2034 that we've marked with gpdisp relocs, since those have to stay in
2035 1-1 correspondence with one another.
2037 Technically we could copy them if we could set up a mapping from one
2038 sequence number to another, across the set of insns to be duplicated.
2039 This seems overly complicated and error-prone since interblock motion
2040 from sched-ebb could move one of the pair of insns to a different block.
2042 Also cannot allow jsr insns to be duplicated. If they throw exceptions,
2043 then they'll be in a different block from their ldgp. Which could lead
2044 the bb reorder code to think that it would be ok to copy just the block
2045 containing the call and branch to the block containing the ldgp. */
2048 alpha_cannot_copy_insn_p (rtx insn)
2050 if (!reload_completed || !TARGET_EXPLICIT_RELOCS)
2052 if (recog_memoized (insn) >= 0)
2053 return get_attr_cannot_copy (insn);
2059 /* Try a machine-dependent way of reloading an illegitimate address
2060 operand. If we find one, push the reload and return the new rtx. */
2063 alpha_legitimize_reload_address (rtx x,
2064 enum machine_mode mode ATTRIBUTE_UNUSED,
2065 int opnum, int type,
2066 int ind_levels ATTRIBUTE_UNUSED)
2068 /* We must recognize output that we have already generated ourselves. */
2069 if (GET_CODE (x) == PLUS
2070 && GET_CODE (XEXP (x, 0)) == PLUS
2071 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
2072 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2073 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2075 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
2076 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
2081 /* We wish to handle large displacements off a base register by
2082 splitting the addend across an ldah and the mem insn. This
2083 cuts number of extra insns needed from 3 to 1. */
2084 if (GET_CODE (x) == PLUS
2085 && GET_CODE (XEXP (x, 0)) == REG
2086 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2087 && REGNO_OK_FOR_BASE_P (REGNO (XEXP (x, 0)))
2088 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2090 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
2091 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
2093 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
2095 /* Check for 32-bit overflow. */
2096 if (high + low != val)
2099 /* Reload the high part into a base reg; leave the low part
2100 in the mem directly. */
2101 x = gen_rtx_PLUS (GET_MODE (x),
2102 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
2106 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
2107 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
2115 /* Compute a (partial) cost for rtx X. Return true if the complete
2116 cost has been computed, and false if subexpressions should be
2117 scanned. In either case, *TOTAL contains the cost result. */
2120 alpha_rtx_costs (rtx x, int code, int outer_code, int *total)
2122 enum machine_mode mode = GET_MODE (x);
2123 bool float_mode_p = FLOAT_MODE_P (mode);
2124 const struct alpha_rtx_cost_data *cost_data;
2127 cost_data = &alpha_rtx_cost_size;
2129 cost_data = &alpha_rtx_cost_data[alpha_cpu];
2134 /* If this is an 8-bit constant, return zero since it can be used
2135 nearly anywhere with no cost. If it is a valid operand for an
2136 ADD or AND, likewise return 0 if we know it will be used in that
2137 context. Otherwise, return 2 since it might be used there later.
2138 All other constants take at least two insns. */
2139 if (INTVAL (x) >= 0 && INTVAL (x) < 256)
2147 if (x == CONST0_RTX (mode))
2149 else if ((outer_code == PLUS && add_operand (x, VOIDmode))
2150 || (outer_code == AND && and_operand (x, VOIDmode)))
2152 else if (add_operand (x, VOIDmode) || and_operand (x, VOIDmode))
2155 *total = COSTS_N_INSNS (2);
2161 if (TARGET_EXPLICIT_RELOCS && small_symbolic_operand (x, VOIDmode))
2162 *total = COSTS_N_INSNS (outer_code != MEM);
2163 else if (TARGET_EXPLICIT_RELOCS && local_symbolic_operand (x, VOIDmode))
2164 *total = COSTS_N_INSNS (1 + (outer_code != MEM));
2165 else if (tls_symbolic_operand_type (x))
2166 /* Estimate of cost for call_pal rduniq. */
2167 /* ??? How many insns do we emit here? More than one... */
2168 *total = COSTS_N_INSNS (15);
2170 /* Otherwise we do a load from the GOT. */
2171 *total = COSTS_N_INSNS (optimize_size ? 1 : alpha_memory_latency);
2177 *total = cost_data->fp_add;
2178 else if (GET_CODE (XEXP (x, 0)) == MULT
2179 && const48_operand (XEXP (XEXP (x, 0), 1), VOIDmode))
2181 *total = (rtx_cost (XEXP (XEXP (x, 0), 0), outer_code)
2182 + rtx_cost (XEXP (x, 1), outer_code) + COSTS_N_INSNS (1));
2189 *total = cost_data->fp_mult;
2190 else if (mode == DImode)
2191 *total = cost_data->int_mult_di;
2193 *total = cost_data->int_mult_si;
2197 if (GET_CODE (XEXP (x, 1)) == CONST_INT
2198 && INTVAL (XEXP (x, 1)) <= 3)
2200 *total = COSTS_N_INSNS (1);
2207 *total = cost_data->int_shift;
2212 *total = cost_data->fp_add;
2214 *total = cost_data->int_cmov;
2222 *total = cost_data->int_div;
2223 else if (mode == SFmode)
2224 *total = cost_data->fp_div_sf;
2226 *total = cost_data->fp_div_df;
2230 *total = COSTS_N_INSNS (optimize_size ? 1 : alpha_memory_latency);
2236 *total = COSTS_N_INSNS (1);
2244 *total = COSTS_N_INSNS (1) + cost_data->int_cmov;
2250 case UNSIGNED_FLOAT:
2254 case FLOAT_TRUNCATE:
2255 *total = cost_data->fp_add;
2263 /* REF is an alignable memory location. Place an aligned SImode
2264 reference into *PALIGNED_MEM and the number of bits to shift into
2265 *PBITNUM. SCRATCH is a free register for use in reloading out
2266 of range stack slots. */
2269 get_aligned_mem (rtx ref, rtx *paligned_mem, rtx *pbitnum)
2272 HOST_WIDE_INT offset = 0;
2274 if (GET_CODE (ref) != MEM)
2277 if (reload_in_progress
2278 && ! memory_address_p (GET_MODE (ref), XEXP (ref, 0)))
2280 base = find_replacement (&XEXP (ref, 0));
2282 if (! memory_address_p (GET_MODE (ref), base))
2287 base = XEXP (ref, 0);
2290 if (GET_CODE (base) == PLUS)
2291 offset += INTVAL (XEXP (base, 1)), base = XEXP (base, 0);
2294 = widen_memory_access (ref, SImode, (offset & ~3) - offset);
2296 if (WORDS_BIG_ENDIAN)
2297 *pbitnum = GEN_INT (32 - (GET_MODE_BITSIZE (GET_MODE (ref))
2298 + (offset & 3) * 8));
2300 *pbitnum = GEN_INT ((offset & 3) * 8);
2303 /* Similar, but just get the address. Handle the two reload cases.
2304 Add EXTRA_OFFSET to the address we return. */
2307 get_unaligned_address (rtx ref, int extra_offset)
2310 HOST_WIDE_INT offset = 0;
2312 if (GET_CODE (ref) != MEM)
2315 if (reload_in_progress
2316 && ! memory_address_p (GET_MODE (ref), XEXP (ref, 0)))
2318 base = find_replacement (&XEXP (ref, 0));
2320 if (! memory_address_p (GET_MODE (ref), base))
2325 base = XEXP (ref, 0);
2328 if (GET_CODE (base) == PLUS)
2329 offset += INTVAL (XEXP (base, 1)), base = XEXP (base, 0);
2331 return plus_constant (base, offset + extra_offset);
2334 /* On the Alpha, all (non-symbolic) constants except zero go into
2335 a floating-point register via memory. Note that we cannot
2336 return anything that is not a subset of CLASS, and that some
2337 symbolic constants cannot be dropped to memory. */
2340 alpha_preferred_reload_class(rtx x, enum reg_class class)
2342 /* Zero is present in any register class. */
2343 if (x == CONST0_RTX (GET_MODE (x)))
2346 /* These sorts of constants we can easily drop to memory. */
2347 if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
2349 if (class == FLOAT_REGS)
2351 if (class == ALL_REGS)
2352 return GENERAL_REGS;
2356 /* All other kinds of constants should not (and in the case of HIGH
2357 cannot) be dropped to memory -- instead we use a GENERAL_REGS
2358 secondary reload. */
2360 return (class == ALL_REGS ? GENERAL_REGS : class);
2365 /* Loading and storing HImode or QImode values to and from memory
2366 usually requires a scratch register. The exceptions are loading
2367 QImode and HImode from an aligned address to a general register
2368 unless byte instructions are permitted.
2370 We also cannot load an unaligned address or a paradoxical SUBREG
2371 into an FP register.
2373 We also cannot do integral arithmetic into FP regs, as might result
2374 from register elimination into a DImode fp register. */
2377 secondary_reload_class (enum reg_class class, enum machine_mode mode,
2380 if ((mode == QImode || mode == HImode) && ! TARGET_BWX)
2382 if (GET_CODE (x) == MEM
2383 || (GET_CODE (x) == REG && REGNO (x) >= FIRST_PSEUDO_REGISTER)
2384 || (GET_CODE (x) == SUBREG
2385 && (GET_CODE (SUBREG_REG (x)) == MEM
2386 || (GET_CODE (SUBREG_REG (x)) == REG
2387 && REGNO (SUBREG_REG (x)) >= FIRST_PSEUDO_REGISTER))))
2389 if (!in || !aligned_memory_operand(x, mode))
2390 return GENERAL_REGS;
2394 if (class == FLOAT_REGS)
2396 if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == AND)
2397 return GENERAL_REGS;
2399 if (GET_CODE (x) == SUBREG
2400 && (GET_MODE_SIZE (GET_MODE (x))
2401 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
2402 return GENERAL_REGS;
2404 if (in && INTEGRAL_MODE_P (mode)
2405 && ! (memory_operand (x, mode) || x == const0_rtx))
2406 return GENERAL_REGS;
2412 /* Subfunction of the following function. Update the flags of any MEM
2413 found in part of X. */
2416 alpha_set_memflags_1 (rtx x, int in_struct_p, int volatile_p, int unchanging_p)
2420 switch (GET_CODE (x))
2426 for (i = XVECLEN (x, 0) - 1; i >= 0; i--)
2427 alpha_set_memflags_1 (XVECEXP (x, 0, i), in_struct_p, volatile_p,
2432 alpha_set_memflags_1 (PATTERN (x), in_struct_p, volatile_p,
2437 alpha_set_memflags_1 (SET_DEST (x), in_struct_p, volatile_p,
2439 alpha_set_memflags_1 (SET_SRC (x), in_struct_p, volatile_p,
2444 MEM_IN_STRUCT_P (x) = in_struct_p;
2445 MEM_VOLATILE_P (x) = volatile_p;
2446 RTX_UNCHANGING_P (x) = unchanging_p;
2447 /* Sadly, we cannot use alias sets because the extra aliasing
2448 produced by the AND interferes. Given that two-byte quantities
2449 are the only thing we would be able to differentiate anyway,
2450 there does not seem to be any point in convoluting the early
2451 out of the alias check. */
2459 /* Given INSN, which is an INSN list or the PATTERN of a single insn
2460 generated to perform a memory operation, look for any MEMs in either
2461 a SET_DEST or a SET_SRC and copy the in-struct, unchanging, and
2462 volatile flags from REF into each of the MEMs found. If REF is not
2463 a MEM, don't do anything. */
2466 alpha_set_memflags (rtx insn, rtx ref)
2468 int in_struct_p, volatile_p, unchanging_p;
2470 if (GET_CODE (ref) != MEM)
2473 in_struct_p = MEM_IN_STRUCT_P (ref);
2474 volatile_p = MEM_VOLATILE_P (ref);
2475 unchanging_p = RTX_UNCHANGING_P (ref);
2477 /* This is only called from alpha.md, after having had something
2478 generated from one of the insn patterns. So if everything is
2479 zero, the pattern is already up-to-date. */
2480 if (! in_struct_p && ! volatile_p && ! unchanging_p)
2483 alpha_set_memflags_1 (insn, in_struct_p, volatile_p, unchanging_p);
2486 /* Internal routine for alpha_emit_set_const to check for N or below insns. */
2489 alpha_emit_set_const_1 (rtx target, enum machine_mode mode,
2490 HOST_WIDE_INT c, int n)
2494 /* Use a pseudo if highly optimizing and still generating RTL. */
2496 = (flag_expensive_optimizations && !no_new_pseudos ? 0 : target);
2499 /* If this is a sign-extended 32-bit constant, we can do this in at most
2500 three insns, so do it if we have enough insns left. We always have
2501 a sign-extended 32-bit constant when compiling on a narrow machine. */
2503 if (HOST_BITS_PER_WIDE_INT != 64
2504 || c >> 31 == -1 || c >> 31 == 0)
2506 HOST_WIDE_INT low = ((c & 0xffff) ^ 0x8000) - 0x8000;
2507 HOST_WIDE_INT tmp1 = c - low;
2508 HOST_WIDE_INT high = (((tmp1 >> 16) & 0xffff) ^ 0x8000) - 0x8000;
2509 HOST_WIDE_INT extra = 0;
2511 /* If HIGH will be interpreted as negative but the constant is
2512 positive, we must adjust it to do two ldha insns. */
2514 if ((high & 0x8000) != 0 && c >= 0)
2518 high = ((tmp1 >> 16) & 0xffff) - 2 * ((tmp1 >> 16) & 0x8000);
2521 if (c == low || (low == 0 && extra == 0))
2523 /* We used to use copy_to_suggested_reg (GEN_INT (c), target, mode)
2524 but that meant that we can't handle INT_MIN on 32-bit machines
2525 (like NT/Alpha), because we recurse indefinitely through
2526 emit_move_insn to gen_movdi. So instead, since we know exactly
2527 what we want, create it explicitly. */
2530 target = gen_reg_rtx (mode);
2531 emit_insn (gen_rtx_SET (VOIDmode, target, GEN_INT (c)));
2534 else if (n >= 2 + (extra != 0))
2538 emit_insn (gen_rtx_SET (VOIDmode, target, GEN_INT (high << 16)));
2542 temp = copy_to_suggested_reg (GEN_INT (high << 16),
2545 /* As of 2002-02-23, addsi3 is only available when not optimizing.
2546 This means that if we go through expand_binop, we'll try to
2547 generate extensions, etc, which will require new pseudos, which
2548 will fail during some split phases. The SImode add patterns
2549 still exist, but are not named. So build the insns by hand. */
2554 subtarget = gen_reg_rtx (mode);
2555 insn = gen_rtx_PLUS (mode, temp, GEN_INT (extra << 16));
2556 insn = gen_rtx_SET (VOIDmode, subtarget, insn);
2562 target = gen_reg_rtx (mode);
2563 insn = gen_rtx_PLUS (mode, temp, GEN_INT (low));
2564 insn = gen_rtx_SET (VOIDmode, target, insn);
2570 /* If we couldn't do it that way, try some other methods. But if we have
2571 no instructions left, don't bother. Likewise, if this is SImode and
2572 we can't make pseudos, we can't do anything since the expand_binop
2573 and expand_unop calls will widen and try to make pseudos. */
2575 if (n == 1 || (mode == SImode && no_new_pseudos))
2578 /* Next, see if we can load a related constant and then shift and possibly
2579 negate it to get the constant we want. Try this once each increasing
2580 numbers of insns. */
2582 for (i = 1; i < n; i++)
2584 /* First, see if minus some low bits, we've an easy load of
2587 new = ((c & 0xffff) ^ 0x8000) - 0x8000;
2589 && (temp = alpha_emit_set_const (subtarget, mode, c - new, i)) != 0)
2590 return expand_binop (mode, add_optab, temp, GEN_INT (new),
2591 target, 0, OPTAB_WIDEN);
2593 /* Next try complementing. */
2594 if ((temp = alpha_emit_set_const (subtarget, mode, ~ c, i)) != 0)
2595 return expand_unop (mode, one_cmpl_optab, temp, target, 0);
2597 /* Next try to form a constant and do a left shift. We can do this
2598 if some low-order bits are zero; the exact_log2 call below tells
2599 us that information. The bits we are shifting out could be any
2600 value, but here we'll just try the 0- and sign-extended forms of
2601 the constant. To try to increase the chance of having the same
2602 constant in more than one insn, start at the highest number of
2603 bits to shift, but try all possibilities in case a ZAPNOT will
2606 if ((bits = exact_log2 (c & - c)) > 0)
2607 for (; bits > 0; bits--)
2608 if ((temp = (alpha_emit_set_const
2609 (subtarget, mode, c >> bits, i))) != 0
2610 || ((temp = (alpha_emit_set_const
2612 ((unsigned HOST_WIDE_INT) c) >> bits, i)))
2614 return expand_binop (mode, ashl_optab, temp, GEN_INT (bits),
2615 target, 0, OPTAB_WIDEN);
2617 /* Now try high-order zero bits. Here we try the shifted-in bits as
2618 all zero and all ones. Be careful to avoid shifting outside the
2619 mode and to avoid shifting outside the host wide int size. */
2620 /* On narrow hosts, don't shift a 1 into the high bit, since we'll
2621 confuse the recursive call and set all of the high 32 bits. */
2623 if ((bits = (MIN (HOST_BITS_PER_WIDE_INT, GET_MODE_SIZE (mode) * 8)
2624 - floor_log2 (c) - 1 - (HOST_BITS_PER_WIDE_INT < 64))) > 0)
2625 for (; bits > 0; bits--)
2626 if ((temp = alpha_emit_set_const (subtarget, mode,
2628 || ((temp = (alpha_emit_set_const
2630 ((c << bits) | (((HOST_WIDE_INT) 1 << bits) - 1)),
2633 return expand_binop (mode, lshr_optab, temp, GEN_INT (bits),
2634 target, 1, OPTAB_WIDEN);
2636 /* Now try high-order 1 bits. We get that with a sign-extension.
2637 But one bit isn't enough here. Be careful to avoid shifting outside
2638 the mode and to avoid shifting outside the host wide int size. */
2640 if ((bits = (MIN (HOST_BITS_PER_WIDE_INT, GET_MODE_SIZE (mode) * 8)
2641 - floor_log2 (~ c) - 2)) > 0)
2642 for (; bits > 0; bits--)
2643 if ((temp = alpha_emit_set_const (subtarget, mode,
2645 || ((temp = (alpha_emit_set_const
2647 ((c << bits) | (((HOST_WIDE_INT) 1 << bits) - 1)),
2650 return expand_binop (mode, ashr_optab, temp, GEN_INT (bits),
2651 target, 0, OPTAB_WIDEN);
2654 #if HOST_BITS_PER_WIDE_INT == 64
2655 /* Finally, see if can load a value into the target that is the same as the
2656 constant except that all bytes that are 0 are changed to be 0xff. If we
2657 can, then we can do a ZAPNOT to obtain the desired constant. */
2660 for (i = 0; i < 64; i += 8)
2661 if ((new & ((HOST_WIDE_INT) 0xff << i)) == 0)
2662 new |= (HOST_WIDE_INT) 0xff << i;
2664 /* We are only called for SImode and DImode. If this is SImode, ensure that
2665 we are sign extended to a full word. */
2668 new = ((new & 0xffffffff) ^ 0x80000000) - 0x80000000;
2670 if (new != c && new != -1
2671 && (temp = alpha_emit_set_const (subtarget, mode, new, n - 1)) != 0)
2672 return expand_binop (mode, and_optab, temp, GEN_INT (c | ~ new),
2673 target, 0, OPTAB_WIDEN);
2679 /* Try to output insns to set TARGET equal to the constant C if it can be
2680 done in less than N insns. Do all computations in MODE. Returns the place
2681 where the output has been placed if it can be done and the insns have been
2682 emitted. If it would take more than N insns, zero is returned and no
2683 insns and emitted. */
2686 alpha_emit_set_const (rtx target, enum machine_mode mode,
2687 HOST_WIDE_INT c, int n)
2690 rtx orig_target = target;
2693 /* If we can't make any pseudos, TARGET is an SImode hard register, we
2694 can't load this constant in one insn, do this in DImode. */
2695 if (no_new_pseudos && mode == SImode
2696 && GET_CODE (target) == REG && REGNO (target) < FIRST_PSEUDO_REGISTER
2697 && (result = alpha_emit_set_const_1 (target, mode, c, 1)) == 0)
2699 target = gen_lowpart (DImode, target);
2703 /* Try 1 insn, then 2, then up to N. */
2704 for (i = 1; i <= n; i++)
2706 result = alpha_emit_set_const_1 (target, mode, c, i);
2709 rtx insn = get_last_insn ();
2710 rtx set = single_set (insn);
2711 if (! CONSTANT_P (SET_SRC (set)))
2712 set_unique_reg_note (get_last_insn (), REG_EQUAL, GEN_INT (c));
2717 /* Allow for the case where we changed the mode of TARGET. */
2718 if (result == target)
2719 result = orig_target;
2724 /* Having failed to find a 3 insn sequence in alpha_emit_set_const,
2725 fall back to a straight forward decomposition. We do this to avoid
2726 exponential run times encountered when looking for longer sequences
2727 with alpha_emit_set_const. */
2730 alpha_emit_set_long_const (rtx target, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
2732 HOST_WIDE_INT d1, d2, d3, d4;
2734 /* Decompose the entire word */
2735 #if HOST_BITS_PER_WIDE_INT >= 64
2736 if (c2 != -(c1 < 0))
2738 d1 = ((c1 & 0xffff) ^ 0x8000) - 0x8000;
2740 d2 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000;
2741 c1 = (c1 - d2) >> 32;
2742 d3 = ((c1 & 0xffff) ^ 0x8000) - 0x8000;
2744 d4 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000;
2748 d1 = ((c1 & 0xffff) ^ 0x8000) - 0x8000;
2750 d2 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000;
2754 d3 = ((c2 & 0xffff) ^ 0x8000) - 0x8000;
2756 d4 = ((c2 & 0xffffffff) ^ 0x80000000) - 0x80000000;
2761 /* Construct the high word */
2764 emit_move_insn (target, GEN_INT (d4));
2766 emit_move_insn (target, gen_rtx_PLUS (DImode, target, GEN_INT (d3)));
2769 emit_move_insn (target, GEN_INT (d3));
2771 /* Shift it into place */
2772 emit_move_insn (target, gen_rtx_ASHIFT (DImode, target, GEN_INT (32)));
2774 /* Add in the low bits. */
2776 emit_move_insn (target, gen_rtx_PLUS (DImode, target, GEN_INT (d2)));
2778 emit_move_insn (target, gen_rtx_PLUS (DImode, target, GEN_INT (d1)));
2783 /* Expand a move instruction; return true if all work is done.
2784 We don't handle non-bwx subword loads here. */
2787 alpha_expand_mov (enum machine_mode mode, rtx *operands)
2789 /* If the output is not a register, the input must be. */
2790 if (GET_CODE (operands[0]) == MEM
2791 && ! reg_or_0_operand (operands[1], mode))
2792 operands[1] = force_reg (mode, operands[1]);
2794 /* Allow legitimize_address to perform some simplifications. */
2795 if (mode == Pmode && symbolic_operand (operands[1], mode))
2799 /* With RTL inlining, at -O3, rtl is generated, stored, then actually
2800 compiled at the end of compilation. In the meantime, someone can
2801 re-encode-section-info on some symbol changing it e.g. from global
2802 to local-not-small. If this happens, we'd have emitted a plain
2803 load rather than a high+losum load and not recognize the insn.
2805 So if rtl inlining is in effect, we delay the global/not-global
2806 decision until rest_of_compilation by wrapping it in an
2808 if (TARGET_EXPLICIT_RELOCS && flag_inline_functions
2809 && rtx_equal_function_value_matters
2810 && global_symbolic_operand (operands[1], mode))
2812 emit_insn (gen_movdi_er_maybe_g (operands[0], operands[1]));
2816 tmp = alpha_legitimize_address (operands[1], operands[0], mode);
2819 if (tmp == operands[0])
2826 /* Early out for non-constants and valid constants. */
2827 if (! CONSTANT_P (operands[1]) || input_operand (operands[1], mode))
2830 /* Split large integers. */
2831 if (GET_CODE (operands[1]) == CONST_INT
2832 || GET_CODE (operands[1]) == CONST_DOUBLE)
2834 HOST_WIDE_INT i0, i1;
2835 rtx temp = NULL_RTX;
2837 if (GET_CODE (operands[1]) == CONST_INT)
2839 i0 = INTVAL (operands[1]);
2842 else if (HOST_BITS_PER_WIDE_INT >= 64)
2844 i0 = CONST_DOUBLE_LOW (operands[1]);
2849 i0 = CONST_DOUBLE_LOW (operands[1]);
2850 i1 = CONST_DOUBLE_HIGH (operands[1]);
2853 if (HOST_BITS_PER_WIDE_INT >= 64 || i1 == -(i0 < 0))
2854 temp = alpha_emit_set_const (operands[0], mode, i0, 3);
2856 if (!temp && TARGET_BUILD_CONSTANTS)
2857 temp = alpha_emit_set_long_const (operands[0], i0, i1);
2861 if (rtx_equal_p (operands[0], temp))
2868 /* Otherwise we've nothing left but to drop the thing to memory. */
2869 operands[1] = force_const_mem (mode, operands[1]);
2870 if (reload_in_progress)
2872 emit_move_insn (operands[0], XEXP (operands[1], 0));
2873 operands[1] = copy_rtx (operands[1]);
2874 XEXP (operands[1], 0) = operands[0];
2877 operands[1] = validize_mem (operands[1]);
2881 /* Expand a non-bwx QImode or HImode move instruction;
2882 return true if all work is done. */
2885 alpha_expand_mov_nobwx (enum machine_mode mode, rtx *operands)
2887 /* If the output is not a register, the input must be. */
2888 if (GET_CODE (operands[0]) == MEM)
2889 operands[1] = force_reg (mode, operands[1]);
2891 /* Handle four memory cases, unaligned and aligned for either the input
2892 or the output. The only case where we can be called during reload is
2893 for aligned loads; all other cases require temporaries. */
2895 if (GET_CODE (operands[1]) == MEM
2896 || (GET_CODE (operands[1]) == SUBREG
2897 && GET_CODE (SUBREG_REG (operands[1])) == MEM)
2898 || (reload_in_progress && GET_CODE (operands[1]) == REG
2899 && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
2900 || (reload_in_progress && GET_CODE (operands[1]) == SUBREG
2901 && GET_CODE (SUBREG_REG (operands[1])) == REG
2902 && REGNO (SUBREG_REG (operands[1])) >= FIRST_PSEUDO_REGISTER))
2904 if (aligned_memory_operand (operands[1], mode))
2906 if (reload_in_progress)
2908 emit_insn ((mode == QImode
2909 ? gen_reload_inqi_help
2910 : gen_reload_inhi_help)
2911 (operands[0], operands[1],
2912 gen_rtx_REG (SImode, REGNO (operands[0]))));
2916 rtx aligned_mem, bitnum;
2917 rtx scratch = gen_reg_rtx (SImode);
2921 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
2923 subtarget = operands[0];
2924 if (GET_CODE (subtarget) == REG)
2925 subtarget = gen_lowpart (DImode, subtarget), copyout = false;
2927 subtarget = gen_reg_rtx (DImode), copyout = true;
2929 emit_insn ((mode == QImode
2930 ? gen_aligned_loadqi
2931 : gen_aligned_loadhi)
2932 (subtarget, aligned_mem, bitnum, scratch));
2935 emit_move_insn (operands[0], gen_lowpart (mode, subtarget));
2940 /* Don't pass these as parameters since that makes the generated
2941 code depend on parameter evaluation order which will cause
2942 bootstrap failures. */
2944 rtx temp1, temp2, seq, subtarget;
2947 temp1 = gen_reg_rtx (DImode);
2948 temp2 = gen_reg_rtx (DImode);
2950 subtarget = operands[0];
2951 if (GET_CODE (subtarget) == REG)
2952 subtarget = gen_lowpart (DImode, subtarget), copyout = false;
2954 subtarget = gen_reg_rtx (DImode), copyout = true;
2956 seq = ((mode == QImode
2957 ? gen_unaligned_loadqi
2958 : gen_unaligned_loadhi)
2959 (subtarget, get_unaligned_address (operands[1], 0),
2961 alpha_set_memflags (seq, operands[1]);
2965 emit_move_insn (operands[0], gen_lowpart (mode, subtarget));
2970 if (GET_CODE (operands[0]) == MEM
2971 || (GET_CODE (operands[0]) == SUBREG
2972 && GET_CODE (SUBREG_REG (operands[0])) == MEM)
2973 || (reload_in_progress && GET_CODE (operands[0]) == REG
2974 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)
2975 || (reload_in_progress && GET_CODE (operands[0]) == SUBREG
2976 && GET_CODE (SUBREG_REG (operands[0])) == REG
2977 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))
2979 if (aligned_memory_operand (operands[0], mode))
2981 rtx aligned_mem, bitnum;
2982 rtx temp1 = gen_reg_rtx (SImode);
2983 rtx temp2 = gen_reg_rtx (SImode);
2985 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
2987 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
2992 rtx temp1 = gen_reg_rtx (DImode);
2993 rtx temp2 = gen_reg_rtx (DImode);
2994 rtx temp3 = gen_reg_rtx (DImode);
2995 rtx seq = ((mode == QImode
2996 ? gen_unaligned_storeqi
2997 : gen_unaligned_storehi)
2998 (get_unaligned_address (operands[0], 0),
2999 operands[1], temp1, temp2, temp3));
3001 alpha_set_memflags (seq, operands[0]);
3010 /* Generate an unsigned DImode to FP conversion. This is the same code
3011 optabs would emit if we didn't have TFmode patterns.
3013 For SFmode, this is the only construction I've found that can pass
3014 gcc.c-torture/execute/ieee/rbug.c. No scenario that uses DFmode
3015 intermediates will work, because you'll get intermediate rounding
3016 that ruins the end result. Some of this could be fixed by turning
3017 on round-to-positive-infinity, but that requires diddling the fpsr,
3018 which kills performance. I tried turning this around and converting
3019 to a negative number, so that I could turn on /m, but either I did
3020 it wrong or there's something else cause I wound up with the exact
3021 same single-bit error. There is a branch-less form of this same code:
3032 fcmoveq $f10,$f11,$f0
3034 I'm not using it because it's the same number of instructions as
3035 this branch-full form, and it has more serialized long latency
3036 instructions on the critical path.
3038 For DFmode, we can avoid rounding errors by breaking up the word
3039 into two pieces, converting them separately, and adding them back:
3041 LC0: .long 0,0x5f800000
3046 cpyse $f11,$f31,$f10
3047 cpyse $f31,$f11,$f11
3055 This doesn't seem to be a clear-cut win over the optabs form.
3056 It probably all depends on the distribution of numbers being
3057 converted -- in the optabs form, all but high-bit-set has a
3058 much lower minimum execution time. */
3061 alpha_emit_floatuns (rtx operands[2])
3063 rtx neglab, donelab, i0, i1, f0, in, out;
3064 enum machine_mode mode;
3067 in = force_reg (DImode, operands[1]);
3068 mode = GET_MODE (out);
3069 neglab = gen_label_rtx ();
3070 donelab = gen_label_rtx ();
3071 i0 = gen_reg_rtx (DImode);
3072 i1 = gen_reg_rtx (DImode);
3073 f0 = gen_reg_rtx (mode);
3075 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, DImode, 0, neglab);
3077 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_FLOAT (mode, in)));
3078 emit_jump_insn (gen_jump (donelab));
3081 emit_label (neglab);
3083 emit_insn (gen_lshrdi3 (i0, in, const1_rtx));
3084 emit_insn (gen_anddi3 (i1, in, const1_rtx));
3085 emit_insn (gen_iordi3 (i0, i0, i1));
3086 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_FLOAT (mode, i0)));
3087 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
3089 emit_label (donelab);
3092 /* Generate the comparison for a conditional branch. */
3095 alpha_emit_conditional_branch (enum rtx_code code)
3097 enum rtx_code cmp_code, branch_code;
3098 enum machine_mode cmp_mode, branch_mode = VOIDmode;
3099 rtx op0 = alpha_compare.op0, op1 = alpha_compare.op1;
3102 if (alpha_compare.fp_p && GET_MODE (op0) == TFmode)
3104 if (! TARGET_HAS_XFLOATING_LIBS)
3107 /* X_floating library comparison functions return
3111 Convert the compare against the raw return value. */
3133 op0 = alpha_emit_xfloating_compare (cmp_code, op0, op1);
3135 alpha_compare.fp_p = 0;
3138 /* The general case: fold the comparison code to the types of compares
3139 that we have, choosing the branch as necessary. */
3142 case EQ: case LE: case LT: case LEU: case LTU:
3144 /* We have these compares: */
3145 cmp_code = code, branch_code = NE;
3150 /* These must be reversed. */
3151 cmp_code = reverse_condition (code), branch_code = EQ;
3154 case GE: case GT: case GEU: case GTU:
3155 /* For FP, we swap them, for INT, we reverse them. */
3156 if (alpha_compare.fp_p)
3158 cmp_code = swap_condition (code);
3160 tem = op0, op0 = op1, op1 = tem;
3164 cmp_code = reverse_condition (code);
3173 if (alpha_compare.fp_p)
3176 if (flag_unsafe_math_optimizations)
3178 /* When we are not as concerned about non-finite values, and we
3179 are comparing against zero, we can branch directly. */
3180 if (op1 == CONST0_RTX (DFmode))
3181 cmp_code = NIL, branch_code = code;
3182 else if (op0 == CONST0_RTX (DFmode))
3184 /* Undo the swap we probably did just above. */
3185 tem = op0, op0 = op1, op1 = tem;
3186 branch_code = swap_condition (cmp_code);
3192 /* ??? We mark the branch mode to be CCmode to prevent the
3193 compare and branch from being combined, since the compare
3194 insn follows IEEE rules that the branch does not. */
3195 branch_mode = CCmode;
3202 /* The following optimizations are only for signed compares. */
3203 if (code != LEU && code != LTU && code != GEU && code != GTU)
3205 /* Whee. Compare and branch against 0 directly. */
3206 if (op1 == const0_rtx)
3207 cmp_code = NIL, branch_code = code;
3209 /* If the constants doesn't fit into an immediate, but can
3210 be generated by lda/ldah, we adjust the argument and
3211 compare against zero, so we can use beq/bne directly. */
3212 /* ??? Don't do this when comparing against symbols, otherwise
3213 we'll reduce (&x == 0x1234) to (&x-0x1234 == 0), which will
3214 be declared false out of hand (at least for non-weak). */
3215 else if (GET_CODE (op1) == CONST_INT
3216 && (code == EQ || code == NE)
3217 && !(symbolic_operand (op0, VOIDmode)
3218 || (GET_CODE (op0) == REG && REG_POINTER (op0))))
3220 HOST_WIDE_INT v = INTVAL (op1), n = -v;
3222 if (! CONST_OK_FOR_LETTER_P (v, 'I')
3223 && (CONST_OK_FOR_LETTER_P (n, 'K')
3224 || CONST_OK_FOR_LETTER_P (n, 'L')))
3226 cmp_code = PLUS, branch_code = code;
3232 if (!reg_or_0_operand (op0, DImode))
3233 op0 = force_reg (DImode, op0);
3234 if (cmp_code != PLUS && !reg_or_8bit_operand (op1, DImode))
3235 op1 = force_reg (DImode, op1);
3238 /* Emit an initial compare instruction, if necessary. */
3240 if (cmp_code != NIL)
3242 tem = gen_reg_rtx (cmp_mode);
3243 emit_move_insn (tem, gen_rtx_fmt_ee (cmp_code, cmp_mode, op0, op1));
3246 /* Zero the operands. */
3247 memset (&alpha_compare, 0, sizeof (alpha_compare));
3249 /* Return the branch comparison. */
3250 return gen_rtx_fmt_ee (branch_code, branch_mode, tem, CONST0_RTX (cmp_mode));
3253 /* Certain simplifications can be done to make invalid setcc operations
3254 valid. Return the final comparison, or NULL if we can't work. */
3257 alpha_emit_setcc (enum rtx_code code)
3259 enum rtx_code cmp_code;
3260 rtx op0 = alpha_compare.op0, op1 = alpha_compare.op1;
3261 int fp_p = alpha_compare.fp_p;
3264 /* Zero the operands. */
3265 memset (&alpha_compare, 0, sizeof (alpha_compare));
3267 if (fp_p && GET_MODE (op0) == TFmode)
3269 if (! TARGET_HAS_XFLOATING_LIBS)
3272 /* X_floating library comparison functions return
3276 Convert the compare against the raw return value. */
3278 if (code == UNORDERED || code == ORDERED)
3283 op0 = alpha_emit_xfloating_compare (cmp_code, op0, op1);
3287 if (code == UNORDERED)
3289 else if (code == ORDERED)
3295 if (fp_p && !TARGET_FIX)
3298 /* The general case: fold the comparison code to the types of compares
3299 that we have, choosing the branch as necessary. */
3304 case EQ: case LE: case LT: case LEU: case LTU:
3306 /* We have these compares. */
3308 cmp_code = code, code = NE;
3312 if (!fp_p && op1 == const0_rtx)
3317 cmp_code = reverse_condition (code);
3321 case GE: case GT: case GEU: case GTU:
3322 /* These normally need swapping, but for integer zero we have
3323 special patterns that recognize swapped operands. */
3324 if (!fp_p && op1 == const0_rtx)
3326 code = swap_condition (code);
3328 cmp_code = code, code = NE;
3329 tmp = op0, op0 = op1, op1 = tmp;
3338 if (!register_operand (op0, DImode))
3339 op0 = force_reg (DImode, op0);
3340 if (!reg_or_8bit_operand (op1, DImode))
3341 op1 = force_reg (DImode, op1);
3344 /* Emit an initial compare instruction, if necessary. */
3345 if (cmp_code != NIL)
3347 enum machine_mode mode = fp_p ? DFmode : DImode;
3349 tmp = gen_reg_rtx (mode);
3350 emit_insn (gen_rtx_SET (VOIDmode, tmp,
3351 gen_rtx_fmt_ee (cmp_code, mode, op0, op1)));
3353 op0 = fp_p ? gen_lowpart (DImode, tmp) : tmp;
3357 /* Return the setcc comparison. */
3358 return gen_rtx_fmt_ee (code, DImode, op0, op1);
3362 /* Rewrite a comparison against zero CMP of the form
3363 (CODE (cc0) (const_int 0)) so it can be written validly in
3364 a conditional move (if_then_else CMP ...).
3365 If both of the operands that set cc0 are nonzero we must emit
3366 an insn to perform the compare (it can't be done within
3367 the conditional move). */
3370 alpha_emit_conditional_move (rtx cmp, enum machine_mode mode)
3372 enum rtx_code code = GET_CODE (cmp);
3373 enum rtx_code cmov_code = NE;
3374 rtx op0 = alpha_compare.op0;
3375 rtx op1 = alpha_compare.op1;
3376 int fp_p = alpha_compare.fp_p;
3377 enum machine_mode cmp_mode
3378 = (GET_MODE (op0) == VOIDmode ? DImode : GET_MODE (op0));
3379 enum machine_mode cmp_op_mode = fp_p ? DFmode : DImode;
3380 enum machine_mode cmov_mode = VOIDmode;
3381 int local_fast_math = flag_unsafe_math_optimizations;
3384 /* Zero the operands. */
3385 memset (&alpha_compare, 0, sizeof (alpha_compare));
3387 if (fp_p != FLOAT_MODE_P (mode))
3389 enum rtx_code cmp_code;
3394 /* If we have fp<->int register move instructions, do a cmov by
3395 performing the comparison in fp registers, and move the
3396 zero/nonzero value to integer registers, where we can then
3397 use a normal cmov, or vice-versa. */
3401 case EQ: case LE: case LT: case LEU: case LTU:
3402 /* We have these compares. */
3403 cmp_code = code, code = NE;
3407 /* This must be reversed. */
3408 cmp_code = EQ, code = EQ;
3411 case GE: case GT: case GEU: case GTU:
3412 /* These normally need swapping, but for integer zero we have
3413 special patterns that recognize swapped operands. */
3414 if (!fp_p && op1 == const0_rtx)
3415 cmp_code = code, code = NE;
3418 cmp_code = swap_condition (code);
3420 tem = op0, op0 = op1, op1 = tem;
3428 tem = gen_reg_rtx (cmp_op_mode);
3429 emit_insn (gen_rtx_SET (VOIDmode, tem,
3430 gen_rtx_fmt_ee (cmp_code, cmp_op_mode,
3433 cmp_mode = cmp_op_mode = fp_p ? DImode : DFmode;
3434 op0 = gen_lowpart (cmp_op_mode, tem);
3435 op1 = CONST0_RTX (cmp_op_mode);
3437 local_fast_math = 1;
3440 /* We may be able to use a conditional move directly.
3441 This avoids emitting spurious compares. */
3442 if (signed_comparison_operator (cmp, VOIDmode)
3443 && (!fp_p || local_fast_math)
3444 && (op0 == CONST0_RTX (cmp_mode) || op1 == CONST0_RTX (cmp_mode)))
3445 return gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
3447 /* We can't put the comparison inside the conditional move;
3448 emit a compare instruction and put that inside the
3449 conditional move. Make sure we emit only comparisons we have;
3450 swap or reverse as necessary. */
3457 case EQ: case LE: case LT: case LEU: case LTU:
3458 /* We have these compares: */
3462 /* This must be reversed. */
3463 code = reverse_condition (code);
3467 case GE: case GT: case GEU: case GTU:
3468 /* These must be swapped. */
3469 if (op1 != CONST0_RTX (cmp_mode))
3471 code = swap_condition (code);
3472 tem = op0, op0 = op1, op1 = tem;
3482 if (!reg_or_0_operand (op0, DImode))
3483 op0 = force_reg (DImode, op0);
3484 if (!reg_or_8bit_operand (op1, DImode))
3485 op1 = force_reg (DImode, op1);
3488 /* ??? We mark the branch mode to be CCmode to prevent the compare
3489 and cmov from being combined, since the compare insn follows IEEE
3490 rules that the cmov does not. */
3491 if (fp_p && !local_fast_math)
3494 tem = gen_reg_rtx (cmp_op_mode);
3495 emit_move_insn (tem, gen_rtx_fmt_ee (code, cmp_op_mode, op0, op1));
3496 return gen_rtx_fmt_ee (cmov_code, cmov_mode, tem, CONST0_RTX (cmp_op_mode));
3499 /* Simplify a conditional move of two constants into a setcc with
3500 arithmetic. This is done with a splitter since combine would
3501 just undo the work if done during code generation. It also catches
3502 cases we wouldn't have before cse. */
3505 alpha_split_conditional_move (enum rtx_code code, rtx dest, rtx cond,
3506 rtx t_rtx, rtx f_rtx)
3508 HOST_WIDE_INT t, f, diff;
3509 enum machine_mode mode;
3510 rtx target, subtarget, tmp;
3512 mode = GET_MODE (dest);
3517 if (((code == NE || code == EQ) && diff < 0)
3518 || (code == GE || code == GT))
3520 code = reverse_condition (code);
3521 diff = t, t = f, f = diff;
3525 subtarget = target = dest;
3528 target = gen_lowpart (DImode, dest);
3529 if (! no_new_pseudos)
3530 subtarget = gen_reg_rtx (DImode);
3534 /* Below, we must be careful to use copy_rtx on target and subtarget
3535 in intermediate insns, as they may be a subreg rtx, which may not
3538 if (f == 0 && exact_log2 (diff) > 0
3539 /* On EV6, we've got enough shifters to make non-arithmetic shifts
3540 viable over a longer latency cmove. On EV5, the E0 slot is a
3541 scarce resource, and on EV4 shift has the same latency as a cmove. */
3542 && (diff <= 8 || alpha_cpu == PROCESSOR_EV6))
3544 tmp = gen_rtx_fmt_ee (code, DImode, cond, const0_rtx);
3545 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (subtarget), tmp));
3547 tmp = gen_rtx_ASHIFT (DImode, copy_rtx (subtarget),
3548 GEN_INT (exact_log2 (t)));
3549 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
3551 else if (f == 0 && t == -1)
3553 tmp = gen_rtx_fmt_ee (code, DImode, cond, const0_rtx);
3554 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (subtarget), tmp));
3556 emit_insn (gen_negdi2 (target, copy_rtx (subtarget)));
3558 else if (diff == 1 || diff == 4 || diff == 8)
3562 tmp = gen_rtx_fmt_ee (code, DImode, cond, const0_rtx);
3563 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (subtarget), tmp));
3566 emit_insn (gen_adddi3 (target, copy_rtx (subtarget), GEN_INT (f)));
3569 add_op = GEN_INT (f);
3570 if (sext_add_operand (add_op, mode))
3572 tmp = gen_rtx_MULT (DImode, copy_rtx (subtarget),
3574 tmp = gen_rtx_PLUS (DImode, tmp, add_op);
3575 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
3587 /* Look up the function X_floating library function name for the
3590 struct xfloating_op GTY(())
3592 const enum rtx_code code;
3593 const char *const GTY((skip)) osf_func;
3594 const char *const GTY((skip)) vms_func;
3598 static GTY(()) struct xfloating_op xfloating_ops[] =
3600 { PLUS, "_OtsAddX", "OTS$ADD_X", 0 },
3601 { MINUS, "_OtsSubX", "OTS$SUB_X", 0 },
3602 { MULT, "_OtsMulX", "OTS$MUL_X", 0 },
3603 { DIV, "_OtsDivX", "OTS$DIV_X", 0 },
3604 { EQ, "_OtsEqlX", "OTS$EQL_X", 0 },
3605 { NE, "_OtsNeqX", "OTS$NEQ_X", 0 },
3606 { LT, "_OtsLssX", "OTS$LSS_X", 0 },
3607 { LE, "_OtsLeqX", "OTS$LEQ_X", 0 },
3608 { GT, "_OtsGtrX", "OTS$GTR_X", 0 },
3609 { GE, "_OtsGeqX", "OTS$GEQ_X", 0 },
3610 { FIX, "_OtsCvtXQ", "OTS$CVTXQ", 0 },
3611 { FLOAT, "_OtsCvtQX", "OTS$CVTQX", 0 },
3612 { UNSIGNED_FLOAT, "_OtsCvtQUX", "OTS$CVTQUX", 0 },
3613 { FLOAT_EXTEND, "_OtsConvertFloatTX", "OTS$CVT_FLOAT_T_X", 0 },
3614 { FLOAT_TRUNCATE, "_OtsConvertFloatXT", "OTS$CVT_FLOAT_X_T", 0 }
3617 static GTY(()) struct xfloating_op vax_cvt_ops[] =
3619 { FLOAT_EXTEND, "_OtsConvertFloatGX", "OTS$CVT_FLOAT_G_X", 0 },
3620 { FLOAT_TRUNCATE, "_OtsConvertFloatXG", "OTS$CVT_FLOAT_X_G", 0 }
3624 alpha_lookup_xfloating_lib_func (enum rtx_code code)
3626 struct xfloating_op *ops = xfloating_ops;
3627 long n = ARRAY_SIZE (xfloating_ops);
3630 /* How irritating. Nothing to key off for the main table. */
3631 if (TARGET_FLOAT_VAX && (code == FLOAT_EXTEND || code == FLOAT_TRUNCATE))
3634 n = ARRAY_SIZE (vax_cvt_ops);
3637 for (i = 0; i < n; ++i, ++ops)
3638 if (ops->code == code)
3640 rtx func = ops->libcall;
3643 func = init_one_libfunc (TARGET_ABI_OPEN_VMS
3644 ? ops->vms_func : ops->osf_func);
3645 ops->libcall = func;
3653 /* Most X_floating operations take the rounding mode as an argument.
3654 Compute that here. */
3657 alpha_compute_xfloating_mode_arg (enum rtx_code code,
3658 enum alpha_fp_rounding_mode round)
3664 case ALPHA_FPRM_NORM:
3667 case ALPHA_FPRM_MINF:
3670 case ALPHA_FPRM_CHOP:
3673 case ALPHA_FPRM_DYN:
3679 /* XXX For reference, round to +inf is mode = 3. */
3682 if (code == FLOAT_TRUNCATE && alpha_fptm == ALPHA_FPTM_N)
3688 /* Emit an X_floating library function call.
3690 Note that these functions do not follow normal calling conventions:
3691 TFmode arguments are passed in two integer registers (as opposed to
3692 indirect); TFmode return values appear in R16+R17.
3694 FUNC is the function to call.
3695 TARGET is where the output belongs.
3696 OPERANDS are the inputs.
3697 NOPERANDS is the count of inputs.
3698 EQUIV is the expression equivalent for the function.
3702 alpha_emit_xfloating_libcall (rtx func, rtx target, rtx operands[],
3703 int noperands, rtx equiv)
3705 rtx usage = NULL_RTX, tmp, reg;
3710 for (i = 0; i < noperands; ++i)
3712 switch (GET_MODE (operands[i]))
3715 reg = gen_rtx_REG (TFmode, regno);
3720 reg = gen_rtx_REG (DFmode, regno + 32);
3725 if (GET_CODE (operands[i]) != CONST_INT)
3729 reg = gen_rtx_REG (DImode, regno);
3737 emit_move_insn (reg, operands[i]);
3738 usage = alloc_EXPR_LIST (0, gen_rtx_USE (VOIDmode, reg), usage);
3741 switch (GET_MODE (target))
3744 reg = gen_rtx_REG (TFmode, 16);
3747 reg = gen_rtx_REG (DFmode, 32);
3750 reg = gen_rtx_REG (DImode, 0);
3756 tmp = gen_rtx_MEM (QImode, func);
3757 tmp = emit_call_insn (GEN_CALL_VALUE (reg, tmp, const0_rtx,
3758 const0_rtx, const0_rtx));
3759 CALL_INSN_FUNCTION_USAGE (tmp) = usage;
3760 CONST_OR_PURE_CALL_P (tmp) = 1;
3765 emit_libcall_block (tmp, target, reg, equiv);
3768 /* Emit an X_floating library function call for arithmetic (+,-,*,/). */
3771 alpha_emit_xfloating_arith (enum rtx_code code, rtx operands[])
3775 rtx out_operands[3];
3777 func = alpha_lookup_xfloating_lib_func (code);
3778 mode = alpha_compute_xfloating_mode_arg (code, alpha_fprm);
3780 out_operands[0] = operands[1];
3781 out_operands[1] = operands[2];
3782 out_operands[2] = GEN_INT (mode);
3783 alpha_emit_xfloating_libcall (func, operands[0], out_operands, 3,
3784 gen_rtx_fmt_ee (code, TFmode, operands[1],
3788 /* Emit an X_floating library function call for a comparison. */
3791 alpha_emit_xfloating_compare (enum rtx_code code, rtx op0, rtx op1)
3794 rtx out, operands[2];
3796 func = alpha_lookup_xfloating_lib_func (code);
3800 out = gen_reg_rtx (DImode);
3802 /* ??? Strange mode for equiv because what's actually returned
3803 is -1,0,1, not a proper boolean value. */
3804 alpha_emit_xfloating_libcall (func, out, operands, 2,
3805 gen_rtx_fmt_ee (code, CCmode, op0, op1));
3810 /* Emit an X_floating library function call for a conversion. */
3813 alpha_emit_xfloating_cvt (enum rtx_code orig_code, rtx operands[])
3815 int noperands = 1, mode;
3816 rtx out_operands[2];
3818 enum rtx_code code = orig_code;
3820 if (code == UNSIGNED_FIX)
3823 func = alpha_lookup_xfloating_lib_func (code);
3825 out_operands[0] = operands[1];
3830 mode = alpha_compute_xfloating_mode_arg (code, ALPHA_FPRM_CHOP);
3831 out_operands[1] = GEN_INT (mode);
3834 case FLOAT_TRUNCATE:
3835 mode = alpha_compute_xfloating_mode_arg (code, alpha_fprm);
3836 out_operands[1] = GEN_INT (mode);
3843 alpha_emit_xfloating_libcall (func, operands[0], out_operands, noperands,
3844 gen_rtx_fmt_e (orig_code,
3845 GET_MODE (operands[0]),
3849 /* Split a TFmode OP[1] into DImode OP[2,3] and likewise for
3850 OP[0] into OP[0,1]. Naturally, output operand ordering is
3854 alpha_split_tfmode_pair (rtx operands[4])
3856 if (GET_CODE (operands[1]) == REG)
3858 operands[3] = gen_rtx_REG (DImode, REGNO (operands[1]) + 1);
3859 operands[2] = gen_rtx_REG (DImode, REGNO (operands[1]));
3861 else if (GET_CODE (operands[1]) == MEM)
3863 operands[3] = adjust_address (operands[1], DImode, 8);
3864 operands[2] = adjust_address (operands[1], DImode, 0);
3866 else if (operands[1] == CONST0_RTX (TFmode))
3867 operands[2] = operands[3] = const0_rtx;
3871 if (GET_CODE (operands[0]) == REG)
3873 operands[1] = gen_rtx_REG (DImode, REGNO (operands[0]) + 1);
3874 operands[0] = gen_rtx_REG (DImode, REGNO (operands[0]));
3876 else if (GET_CODE (operands[0]) == MEM)
3878 operands[1] = adjust_address (operands[0], DImode, 8);
3879 operands[0] = adjust_address (operands[0], DImode, 0);
3885 /* Implement negtf2 or abstf2. Op0 is destination, op1 is source,
3886 op2 is a register containing the sign bit, operation is the
3887 logical operation to be performed. */
3890 alpha_split_tfmode_frobsign (rtx operands[3], rtx (*operation) (rtx, rtx, rtx))
3892 rtx high_bit = operands[2];
3896 alpha_split_tfmode_pair (operands);
3898 /* Detect three flavors of operand overlap. */
3900 if (rtx_equal_p (operands[0], operands[2]))
3902 else if (rtx_equal_p (operands[1], operands[2]))
3904 if (rtx_equal_p (operands[0], high_bit))
3911 emit_move_insn (operands[0], operands[2]);
3913 /* ??? If the destination overlaps both source tf and high_bit, then
3914 assume source tf is dead in its entirety and use the other half
3915 for a scratch register. Otherwise "scratch" is just the proper
3916 destination register. */
3917 scratch = operands[move < 2 ? 1 : 3];
3919 emit_insn ((*operation) (scratch, high_bit, operands[3]));
3923 emit_move_insn (operands[0], operands[2]);
3925 emit_move_insn (operands[1], scratch);
3929 /* Use ext[wlq][lh] as the Architecture Handbook describes for extracting
3933 word: ldq_u r1,X(r11) ldq_u r1,X(r11)
3934 ldq_u r2,X+1(r11) ldq_u r2,X+1(r11)
3935 lda r3,X(r11) lda r3,X+2(r11)
3936 extwl r1,r3,r1 extql r1,r3,r1
3937 extwh r2,r3,r2 extqh r2,r3,r2
3938 or r1.r2.r1 or r1,r2,r1
3941 long: ldq_u r1,X(r11) ldq_u r1,X(r11)
3942 ldq_u r2,X+3(r11) ldq_u r2,X+3(r11)
3943 lda r3,X(r11) lda r3,X(r11)
3944 extll r1,r3,r1 extll r1,r3,r1
3945 extlh r2,r3,r2 extlh r2,r3,r2
3946 or r1.r2.r1 addl r1,r2,r1
3948 quad: ldq_u r1,X(r11)
3957 alpha_expand_unaligned_load (rtx tgt, rtx mem, HOST_WIDE_INT size,
3958 HOST_WIDE_INT ofs, int sign)
3960 rtx meml, memh, addr, extl, exth, tmp, mema;
3961 enum machine_mode mode;
3963 meml = gen_reg_rtx (DImode);
3964 memh = gen_reg_rtx (DImode);
3965 addr = gen_reg_rtx (DImode);
3966 extl = gen_reg_rtx (DImode);
3967 exth = gen_reg_rtx (DImode);
3969 mema = XEXP (mem, 0);
3970 if (GET_CODE (mema) == LO_SUM)
3971 mema = force_reg (Pmode, mema);
3973 /* AND addresses cannot be in any alias set, since they may implicitly
3974 alias surrounding code. Ideally we'd have some alias set that
3975 covered all types except those with alignment 8 or higher. */
3977 tmp = change_address (mem, DImode,
3978 gen_rtx_AND (DImode,
3979 plus_constant (mema, ofs),
3981 set_mem_alias_set (tmp, 0);
3982 emit_move_insn (meml, tmp);
3984 tmp = change_address (mem, DImode,
3985 gen_rtx_AND (DImode,
3986 plus_constant (mema, ofs + size - 1),
3988 set_mem_alias_set (tmp, 0);
3989 emit_move_insn (memh, tmp);
3991 if (WORDS_BIG_ENDIAN && sign && (size == 2 || size == 4))
3993 emit_move_insn (addr, plus_constant (mema, -1));
3995 emit_insn (gen_extqh_be (extl, meml, addr));
3996 emit_insn (gen_extxl_be (exth, memh, GEN_INT (64), addr));
3998 addr = expand_binop (DImode, ior_optab, extl, exth, tgt, 1, OPTAB_WIDEN);
3999 addr = expand_binop (DImode, ashr_optab, addr, GEN_INT (64 - size*8),
4000 addr, 1, OPTAB_WIDEN);
4002 else if (sign && size == 2)
4004 emit_move_insn (addr, plus_constant (mema, ofs+2));
4006 emit_insn (gen_extxl_le (extl, meml, GEN_INT (64), addr));
4007 emit_insn (gen_extqh_le (exth, memh, addr));
4009 /* We must use tgt here for the target. Alpha-vms port fails if we use
4010 addr for the target, because addr is marked as a pointer and combine
4011 knows that pointers are always sign-extended 32 bit values. */
4012 addr = expand_binop (DImode, ior_optab, extl, exth, tgt, 1, OPTAB_WIDEN);
4013 addr = expand_binop (DImode, ashr_optab, addr, GEN_INT (48),
4014 addr, 1, OPTAB_WIDEN);
4018 if (WORDS_BIG_ENDIAN)
4020 emit_move_insn (addr, plus_constant (mema, ofs+size-1));
4024 emit_insn (gen_extwh_be (extl, meml, addr));
4029 emit_insn (gen_extlh_be (extl, meml, addr));
4034 emit_insn (gen_extqh_be (extl, meml, addr));
4041 emit_insn (gen_extxl_be (exth, memh, GEN_INT (size*8), addr));
4045 emit_move_insn (addr, plus_constant (mema, ofs));
4046 emit_insn (gen_extxl_le (extl, meml, GEN_INT (size*8), addr));
4050 emit_insn (gen_extwh_le (exth, memh, addr));
4055 emit_insn (gen_extlh_le (exth, memh, addr));
4060 emit_insn (gen_extqh_le (exth, memh, addr));
4069 addr = expand_binop (mode, ior_optab, gen_lowpart (mode, extl),
4070 gen_lowpart (mode, exth), gen_lowpart (mode, tgt),
4075 emit_move_insn (tgt, gen_lowpart(GET_MODE (tgt), addr));
4078 /* Similarly, use ins and msk instructions to perform unaligned stores. */
4081 alpha_expand_unaligned_store (rtx dst, rtx src,
4082 HOST_WIDE_INT size, HOST_WIDE_INT ofs)
4084 rtx dstl, dsth, addr, insl, insh, meml, memh, dsta;
4086 dstl = gen_reg_rtx (DImode);
4087 dsth = gen_reg_rtx (DImode);
4088 insl = gen_reg_rtx (DImode);
4089 insh = gen_reg_rtx (DImode);
4091 dsta = XEXP (dst, 0);
4092 if (GET_CODE (dsta) == LO_SUM)
4093 dsta = force_reg (Pmode, dsta);
4095 /* AND addresses cannot be in any alias set, since they may implicitly
4096 alias surrounding code. Ideally we'd have some alias set that
4097 covered all types except those with alignment 8 or higher. */
4099 meml = change_address (dst, DImode,
4100 gen_rtx_AND (DImode,
4101 plus_constant (dsta, ofs),
4103 set_mem_alias_set (meml, 0);
4105 memh = change_address (dst, DImode,
4106 gen_rtx_AND (DImode,
4107 plus_constant (dsta, ofs + size - 1),
4109 set_mem_alias_set (memh, 0);
4111 emit_move_insn (dsth, memh);
4112 emit_move_insn (dstl, meml);
4113 if (WORDS_BIG_ENDIAN)
4115 addr = copy_addr_to_reg (plus_constant (dsta, ofs+size-1));
4117 if (src != const0_rtx)
4122 emit_insn (gen_inswl_be (insh, gen_lowpart (HImode,src), addr));
4125 emit_insn (gen_insll_be (insh, gen_lowpart (SImode,src), addr));
4128 emit_insn (gen_insql_be (insh, gen_lowpart (DImode,src), addr));
4131 emit_insn (gen_insxh (insl, gen_lowpart (DImode, src),
4132 GEN_INT (size*8), addr));
4138 emit_insn (gen_mskxl_be (dsth, dsth, GEN_INT (0xffff), addr));
4142 rtx msk = immed_double_const (0xffffffff, 0, DImode);
4143 emit_insn (gen_mskxl_be (dsth, dsth, msk, addr));
4147 emit_insn (gen_mskxl_be (dsth, dsth, constm1_rtx, addr));
4151 emit_insn (gen_mskxh (dstl, dstl, GEN_INT (size*8), addr));
4155 addr = copy_addr_to_reg (plus_constant (dsta, ofs));
4157 if (src != const0_rtx)
4159 emit_insn (gen_insxh (insh, gen_lowpart (DImode, src),
4160 GEN_INT (size*8), addr));
4165 emit_insn (gen_inswl_le (insl, gen_lowpart (HImode, src), addr));
4168 emit_insn (gen_insll_le (insl, gen_lowpart (SImode, src), addr));
4171 emit_insn (gen_insql_le (insl, src, addr));
4176 emit_insn (gen_mskxh (dsth, dsth, GEN_INT (size*8), addr));
4181 emit_insn (gen_mskxl_le (dstl, dstl, GEN_INT (0xffff), addr));
4185 rtx msk = immed_double_const (0xffffffff, 0, DImode);
4186 emit_insn (gen_mskxl_le (dstl, dstl, msk, addr));
4190 emit_insn (gen_mskxl_le (dstl, dstl, constm1_rtx, addr));
4195 if (src != const0_rtx)
4197 dsth = expand_binop (DImode, ior_optab, insh, dsth, dsth, 0, OPTAB_WIDEN);
4198 dstl = expand_binop (DImode, ior_optab, insl, dstl, dstl, 0, OPTAB_WIDEN);
4201 if (WORDS_BIG_ENDIAN)
4203 emit_move_insn (meml, dstl);
4204 emit_move_insn (memh, dsth);
4208 /* Must store high before low for degenerate case of aligned. */
4209 emit_move_insn (memh, dsth);
4210 emit_move_insn (meml, dstl);
4214 /* The block move code tries to maximize speed by separating loads and
4215 stores at the expense of register pressure: we load all of the data
4216 before we store it back out. There are two secondary effects worth
4217 mentioning, that this speeds copying to/from aligned and unaligned
4218 buffers, and that it makes the code significantly easier to write. */
4220 #define MAX_MOVE_WORDS 8
4222 /* Load an integral number of consecutive unaligned quadwords. */
4225 alpha_expand_unaligned_load_words (rtx *out_regs, rtx smem,
4226 HOST_WIDE_INT words, HOST_WIDE_INT ofs)
4228 rtx const im8 = GEN_INT (-8);
4229 rtx const i64 = GEN_INT (64);
4230 rtx ext_tmps[MAX_MOVE_WORDS], data_regs[MAX_MOVE_WORDS+1];
4231 rtx sreg, areg, tmp, smema;
4234 smema = XEXP (smem, 0);
4235 if (GET_CODE (smema) == LO_SUM)
4236 smema = force_reg (Pmode, smema);
4238 /* Generate all the tmp registers we need. */
4239 for (i = 0; i < words; ++i)
4241 data_regs[i] = out_regs[i];
4242 ext_tmps[i] = gen_reg_rtx (DImode);
4244 data_regs[words] = gen_reg_rtx (DImode);
4247 smem = adjust_address (smem, GET_MODE (smem), ofs);
4249 /* Load up all of the source data. */
4250 for (i = 0; i < words; ++i)
4252 tmp = change_address (smem, DImode,
4253 gen_rtx_AND (DImode,
4254 plus_constant (smema, 8*i),
4256 set_mem_alias_set (tmp, 0);
4257 emit_move_insn (data_regs[i], tmp);
4260 tmp = change_address (smem, DImode,
4261 gen_rtx_AND (DImode,
4262 plus_constant (smema, 8*words - 1),
4264 set_mem_alias_set (tmp, 0);
4265 emit_move_insn (data_regs[words], tmp);
4267 /* Extract the half-word fragments. Unfortunately DEC decided to make
4268 extxh with offset zero a noop instead of zeroing the register, so
4269 we must take care of that edge condition ourselves with cmov. */
4271 sreg = copy_addr_to_reg (smema);
4272 areg = expand_binop (DImode, and_optab, sreg, GEN_INT (7), NULL,
4274 if (WORDS_BIG_ENDIAN)
4275 emit_move_insn (sreg, plus_constant (sreg, 7));
4276 for (i = 0; i < words; ++i)
4278 if (WORDS_BIG_ENDIAN)
4280 emit_insn (gen_extqh_be (data_regs[i], data_regs[i], sreg));
4281 emit_insn (gen_extxl_be (ext_tmps[i], data_regs[i+1], i64, sreg));
4285 emit_insn (gen_extxl_le (data_regs[i], data_regs[i], i64, sreg));
4286 emit_insn (gen_extqh_le (ext_tmps[i], data_regs[i+1], sreg));
4288 emit_insn (gen_rtx_SET (VOIDmode, ext_tmps[i],
4289 gen_rtx_IF_THEN_ELSE (DImode,
4290 gen_rtx_EQ (DImode, areg,
4292 const0_rtx, ext_tmps[i])));
4295 /* Merge the half-words into whole words. */
4296 for (i = 0; i < words; ++i)
4298 out_regs[i] = expand_binop (DImode, ior_optab, data_regs[i],
4299 ext_tmps[i], data_regs[i], 1, OPTAB_WIDEN);
4303 /* Store an integral number of consecutive unaligned quadwords. DATA_REGS
4304 may be NULL to store zeros. */
4307 alpha_expand_unaligned_store_words (rtx *data_regs, rtx dmem,
4308 HOST_WIDE_INT words, HOST_WIDE_INT ofs)
4310 rtx const im8 = GEN_INT (-8);
4311 rtx const i64 = GEN_INT (64);
4312 rtx ins_tmps[MAX_MOVE_WORDS];
4313 rtx st_tmp_1, st_tmp_2, dreg;
4314 rtx st_addr_1, st_addr_2, dmema;
4317 dmema = XEXP (dmem, 0);
4318 if (GET_CODE (dmema) == LO_SUM)
4319 dmema = force_reg (Pmode, dmema);
4321 /* Generate all the tmp registers we need. */
4322 if (data_regs != NULL)
4323 for (i = 0; i < words; ++i)
4324 ins_tmps[i] = gen_reg_rtx(DImode);
4325 st_tmp_1 = gen_reg_rtx(DImode);
4326 st_tmp_2 = gen_reg_rtx(DImode);
4329 dmem = adjust_address (dmem, GET_MODE (dmem), ofs);
4331 st_addr_2 = change_address (dmem, DImode,
4332 gen_rtx_AND (DImode,
4333 plus_constant (dmema, words*8 - 1),
4335 set_mem_alias_set (st_addr_2, 0);
4337 st_addr_1 = change_address (dmem, DImode,
4338 gen_rtx_AND (DImode, dmema, im8));
4339 set_mem_alias_set (st_addr_1, 0);
4341 /* Load up the destination end bits. */
4342 emit_move_insn (st_tmp_2, st_addr_2);
4343 emit_move_insn (st_tmp_1, st_addr_1);
4345 /* Shift the input data into place. */
4346 dreg = copy_addr_to_reg (dmema);
4347 if (WORDS_BIG_ENDIAN)
4348 emit_move_insn (dreg, plus_constant (dreg, 7));
4349 if (data_regs != NULL)
4351 for (i = words-1; i >= 0; --i)
4353 if (WORDS_BIG_ENDIAN)
4355 emit_insn (gen_insql_be (ins_tmps[i], data_regs[i], dreg));
4356 emit_insn (gen_insxh (data_regs[i], data_regs[i], i64, dreg));
4360 emit_insn (gen_insxh (ins_tmps[i], data_regs[i], i64, dreg));
4361 emit_insn (gen_insql_le (data_regs[i], data_regs[i], dreg));
4364 for (i = words-1; i > 0; --i)
4366 ins_tmps[i-1] = expand_binop (DImode, ior_optab, data_regs[i],
4367 ins_tmps[i-1], ins_tmps[i-1], 1,
4372 /* Split and merge the ends with the destination data. */
4373 if (WORDS_BIG_ENDIAN)
4375 emit_insn (gen_mskxl_be (st_tmp_2, st_tmp_2, constm1_rtx, dreg));
4376 emit_insn (gen_mskxh (st_tmp_1, st_tmp_1, i64, dreg));
4380 emit_insn (gen_mskxh (st_tmp_2, st_tmp_2, i64, dreg));
4381 emit_insn (gen_mskxl_le (st_tmp_1, st_tmp_1, constm1_rtx, dreg));
4384 if (data_regs != NULL)
4386 st_tmp_2 = expand_binop (DImode, ior_optab, st_tmp_2, ins_tmps[words-1],
4387 st_tmp_2, 1, OPTAB_WIDEN);
4388 st_tmp_1 = expand_binop (DImode, ior_optab, st_tmp_1, data_regs[0],
4389 st_tmp_1, 1, OPTAB_WIDEN);
4393 if (WORDS_BIG_ENDIAN)
4394 emit_move_insn (st_addr_1, st_tmp_1);
4396 emit_move_insn (st_addr_2, st_tmp_2);
4397 for (i = words-1; i > 0; --i)
4399 rtx tmp = change_address (dmem, DImode,
4400 gen_rtx_AND (DImode,
4401 plus_constant(dmema,
4402 WORDS_BIG_ENDIAN ? i*8-1 : i*8),
4404 set_mem_alias_set (tmp, 0);
4405 emit_move_insn (tmp, data_regs ? ins_tmps[i-1] : const0_rtx);
4407 if (WORDS_BIG_ENDIAN)
4408 emit_move_insn (st_addr_2, st_tmp_2);
4410 emit_move_insn (st_addr_1, st_tmp_1);
4414 /* Expand string/block move operations.
4416 operands[0] is the pointer to the destination.
4417 operands[1] is the pointer to the source.
4418 operands[2] is the number of bytes to move.
4419 operands[3] is the alignment. */
4422 alpha_expand_block_move (rtx operands[])
4424 rtx bytes_rtx = operands[2];
4425 rtx align_rtx = operands[3];
4426 HOST_WIDE_INT orig_bytes = INTVAL (bytes_rtx);
4427 HOST_WIDE_INT bytes = orig_bytes;
4428 HOST_WIDE_INT src_align = INTVAL (align_rtx) * BITS_PER_UNIT;
4429 HOST_WIDE_INT dst_align = src_align;
4430 rtx orig_src = operands[1];
4431 rtx orig_dst = operands[0];
4432 rtx data_regs[2 * MAX_MOVE_WORDS + 16];
4434 unsigned int i, words, ofs, nregs = 0;
4436 if (orig_bytes <= 0)
4438 else if (orig_bytes > MAX_MOVE_WORDS * UNITS_PER_WORD)
4441 /* Look for additional alignment information from recorded register info. */
4443 tmp = XEXP (orig_src, 0);
4444 if (GET_CODE (tmp) == REG)
4445 src_align = MAX (src_align, REGNO_POINTER_ALIGN (REGNO (tmp)));
4446 else if (GET_CODE (tmp) == PLUS
4447 && GET_CODE (XEXP (tmp, 0)) == REG
4448 && GET_CODE (XEXP (tmp, 1)) == CONST_INT)
4450 unsigned HOST_WIDE_INT c = INTVAL (XEXP (tmp, 1));
4451 unsigned int a = REGNO_POINTER_ALIGN (REGNO (XEXP (tmp, 0)));
4455 if (a >= 64 && c % 8 == 0)
4457 else if (a >= 32 && c % 4 == 0)
4459 else if (a >= 16 && c % 2 == 0)
4464 tmp = XEXP (orig_dst, 0);
4465 if (GET_CODE (tmp) == REG)
4466 dst_align = MAX (dst_align, REGNO_POINTER_ALIGN (REGNO (tmp)));
4467 else if (GET_CODE (tmp) == PLUS
4468 && GET_CODE (XEXP (tmp, 0)) == REG
4469 && GET_CODE (XEXP (tmp, 1)) == CONST_INT)
4471 unsigned HOST_WIDE_INT c = INTVAL (XEXP (tmp, 1));
4472 unsigned int a = REGNO_POINTER_ALIGN (REGNO (XEXP (tmp, 0)));
4476 if (a >= 64 && c % 8 == 0)
4478 else if (a >= 32 && c % 4 == 0)
4480 else if (a >= 16 && c % 2 == 0)
4486 if (src_align >= 64 && bytes >= 8)
4490 for (i = 0; i < words; ++i)
4491 data_regs[nregs + i] = gen_reg_rtx (DImode);
4493 for (i = 0; i < words; ++i)
4494 emit_move_insn (data_regs[nregs + i],
4495 adjust_address (orig_src, DImode, ofs + i * 8));
4502 if (src_align >= 32 && bytes >= 4)
4506 for (i = 0; i < words; ++i)
4507 data_regs[nregs + i] = gen_reg_rtx (SImode);
4509 for (i = 0; i < words; ++i)
4510 emit_move_insn (data_regs[nregs + i],
4511 adjust_address (orig_src, SImode, ofs + i * 4));
4522 for (i = 0; i < words+1; ++i)
4523 data_regs[nregs + i] = gen_reg_rtx (DImode);
4525 alpha_expand_unaligned_load_words (data_regs + nregs, orig_src,
4533 if (! TARGET_BWX && bytes >= 4)
4535 data_regs[nregs++] = tmp = gen_reg_rtx (SImode);
4536 alpha_expand_unaligned_load (tmp, orig_src, 4, ofs, 0);
4543 if (src_align >= 16)
4546 data_regs[nregs++] = tmp = gen_reg_rtx (HImode);
4547 emit_move_insn (tmp, adjust_address (orig_src, HImode, ofs));
4550 } while (bytes >= 2);
4552 else if (! TARGET_BWX)
4554 data_regs[nregs++] = tmp = gen_reg_rtx (HImode);
4555 alpha_expand_unaligned_load (tmp, orig_src, 2, ofs, 0);
4563 data_regs[nregs++] = tmp = gen_reg_rtx (QImode);
4564 emit_move_insn (tmp, adjust_address (orig_src, QImode, ofs));
4569 if (nregs > ARRAY_SIZE (data_regs))
4572 /* Now save it back out again. */
4576 /* Write out the data in whatever chunks reading the source allowed. */
4577 if (dst_align >= 64)
4579 while (i < nregs && GET_MODE (data_regs[i]) == DImode)
4581 emit_move_insn (adjust_address (orig_dst, DImode, ofs),
4588 if (dst_align >= 32)
4590 /* If the source has remaining DImode regs, write them out in
4592 while (i < nregs && GET_MODE (data_regs[i]) == DImode)
4594 tmp = expand_binop (DImode, lshr_optab, data_regs[i], GEN_INT (32),
4595 NULL_RTX, 1, OPTAB_WIDEN);
4597 emit_move_insn (adjust_address (orig_dst, SImode, ofs),
4598 gen_lowpart (SImode, data_regs[i]));
4599 emit_move_insn (adjust_address (orig_dst, SImode, ofs + 4),
4600 gen_lowpart (SImode, tmp));
4605 while (i < nregs && GET_MODE (data_regs[i]) == SImode)
4607 emit_move_insn (adjust_address (orig_dst, SImode, ofs),
4614 if (i < nregs && GET_MODE (data_regs[i]) == DImode)
4616 /* Write out a remaining block of words using unaligned methods. */
4618 for (words = 1; i + words < nregs; words++)
4619 if (GET_MODE (data_regs[i + words]) != DImode)
4623 alpha_expand_unaligned_store (orig_dst, data_regs[i], 8, ofs);
4625 alpha_expand_unaligned_store_words (data_regs + i, orig_dst,
4632 /* Due to the above, this won't be aligned. */
4633 /* ??? If we have more than one of these, consider constructing full
4634 words in registers and using alpha_expand_unaligned_store_words. */
4635 while (i < nregs && GET_MODE (data_regs[i]) == SImode)
4637 alpha_expand_unaligned_store (orig_dst, data_regs[i], 4, ofs);
4642 if (dst_align >= 16)
4643 while (i < nregs && GET_MODE (data_regs[i]) == HImode)
4645 emit_move_insn (adjust_address (orig_dst, HImode, ofs), data_regs[i]);
4650 while (i < nregs && GET_MODE (data_regs[i]) == HImode)
4652 alpha_expand_unaligned_store (orig_dst, data_regs[i], 2, ofs);
4657 while (i < nregs && GET_MODE (data_regs[i]) == QImode)
4659 emit_move_insn (adjust_address (orig_dst, QImode, ofs), data_regs[i]);
4671 alpha_expand_block_clear (rtx operands[])
4673 rtx bytes_rtx = operands[1];
4674 rtx align_rtx = operands[2];
4675 HOST_WIDE_INT orig_bytes = INTVAL (bytes_rtx);
4676 HOST_WIDE_INT bytes = orig_bytes;
4677 HOST_WIDE_INT align = INTVAL (align_rtx) * BITS_PER_UNIT;
4678 HOST_WIDE_INT alignofs = 0;
4679 rtx orig_dst = operands[0];
4681 int i, words, ofs = 0;
4683 if (orig_bytes <= 0)
4685 if (orig_bytes > MAX_MOVE_WORDS * UNITS_PER_WORD)
4688 /* Look for stricter alignment. */
4689 tmp = XEXP (orig_dst, 0);
4690 if (GET_CODE (tmp) == REG)
4691 align = MAX (align, REGNO_POINTER_ALIGN (REGNO (tmp)));
4692 else if (GET_CODE (tmp) == PLUS
4693 && GET_CODE (XEXP (tmp, 0)) == REG
4694 && GET_CODE (XEXP (tmp, 1)) == CONST_INT)
4696 HOST_WIDE_INT c = INTVAL (XEXP (tmp, 1));
4697 int a = REGNO_POINTER_ALIGN (REGNO (XEXP (tmp, 0)));
4702 align = a, alignofs = 8 - c % 8;
4704 align = a, alignofs = 4 - c % 4;
4706 align = a, alignofs = 2 - c % 2;
4710 /* Handle an unaligned prefix first. */
4714 #if HOST_BITS_PER_WIDE_INT >= 64
4715 /* Given that alignofs is bounded by align, the only time BWX could
4716 generate three stores is for a 7 byte fill. Prefer two individual
4717 stores over a load/mask/store sequence. */
4718 if ((!TARGET_BWX || alignofs == 7)
4720 && !(alignofs == 4 && bytes >= 4))
4722 enum machine_mode mode = (align >= 64 ? DImode : SImode);
4723 int inv_alignofs = (align >= 64 ? 8 : 4) - alignofs;
4727 mem = adjust_address (orig_dst, mode, ofs - inv_alignofs);
4728 set_mem_alias_set (mem, 0);
4730 mask = ~(~(HOST_WIDE_INT)0 << (inv_alignofs * 8));
4731 if (bytes < alignofs)
4733 mask |= ~(HOST_WIDE_INT)0 << ((inv_alignofs + bytes) * 8);
4744 tmp = expand_binop (mode, and_optab, mem, GEN_INT (mask),
4745 NULL_RTX, 1, OPTAB_WIDEN);
4747 emit_move_insn (mem, tmp);
4751 if (TARGET_BWX && (alignofs & 1) && bytes >= 1)
4753 emit_move_insn (adjust_address (orig_dst, QImode, ofs), const0_rtx);
4758 if (TARGET_BWX && align >= 16 && (alignofs & 3) == 2 && bytes >= 2)
4760 emit_move_insn (adjust_address (orig_dst, HImode, ofs), const0_rtx);
4765 if (alignofs == 4 && bytes >= 4)
4767 emit_move_insn (adjust_address (orig_dst, SImode, ofs), const0_rtx);
4773 /* If we've not used the extra lead alignment information by now,
4774 we won't be able to. Downgrade align to match what's left over. */
4777 alignofs = alignofs & -alignofs;
4778 align = MIN (align, alignofs * BITS_PER_UNIT);
4782 /* Handle a block of contiguous long-words. */
4784 if (align >= 64 && bytes >= 8)
4788 for (i = 0; i < words; ++i)
4789 emit_move_insn (adjust_address (orig_dst, DImode, ofs + i * 8),
4796 /* If the block is large and appropriately aligned, emit a single
4797 store followed by a sequence of stq_u insns. */
4799 if (align >= 32 && bytes > 16)
4803 emit_move_insn (adjust_address (orig_dst, SImode, ofs), const0_rtx);
4807 orig_dsta = XEXP (orig_dst, 0);
4808 if (GET_CODE (orig_dsta) == LO_SUM)
4809 orig_dsta = force_reg (Pmode, orig_dsta);
4812 for (i = 0; i < words; ++i)
4815 = change_address (orig_dst, DImode,
4816 gen_rtx_AND (DImode,
4817 plus_constant (orig_dsta, ofs + i*8),
4819 set_mem_alias_set (mem, 0);
4820 emit_move_insn (mem, const0_rtx);
4823 /* Depending on the alignment, the first stq_u may have overlapped
4824 with the initial stl, which means that the last stq_u didn't
4825 write as much as it would appear. Leave those questionable bytes
4827 bytes -= words * 8 - 4;
4828 ofs += words * 8 - 4;
4831 /* Handle a smaller block of aligned words. */
4833 if ((align >= 64 && bytes == 4)
4834 || (align == 32 && bytes >= 4))
4838 for (i = 0; i < words; ++i)
4839 emit_move_insn (adjust_address (orig_dst, SImode, ofs + i * 4),
4846 /* An unaligned block uses stq_u stores for as many as possible. */
4852 alpha_expand_unaligned_store_words (NULL, orig_dst, words, ofs);
4858 /* Next clean up any trailing pieces. */
4860 #if HOST_BITS_PER_WIDE_INT >= 64
4861 /* Count the number of bits in BYTES for which aligned stores could
4864 for (i = (TARGET_BWX ? 1 : 4); i * BITS_PER_UNIT <= align ; i <<= 1)
4868 /* If we have appropriate alignment (and it wouldn't take too many
4869 instructions otherwise), mask out the bytes we need. */
4870 if (TARGET_BWX ? words > 2 : bytes > 0)
4877 mem = adjust_address (orig_dst, DImode, ofs);
4878 set_mem_alias_set (mem, 0);
4880 mask = ~(HOST_WIDE_INT)0 << (bytes * 8);
4882 tmp = expand_binop (DImode, and_optab, mem, GEN_INT (mask),
4883 NULL_RTX, 1, OPTAB_WIDEN);
4885 emit_move_insn (mem, tmp);
4888 else if (align >= 32 && bytes < 4)
4893 mem = adjust_address (orig_dst, SImode, ofs);
4894 set_mem_alias_set (mem, 0);
4896 mask = ~(HOST_WIDE_INT)0 << (bytes * 8);
4898 tmp = expand_binop (SImode, and_optab, mem, GEN_INT (mask),
4899 NULL_RTX, 1, OPTAB_WIDEN);
4901 emit_move_insn (mem, tmp);
4907 if (!TARGET_BWX && bytes >= 4)
4909 alpha_expand_unaligned_store (orig_dst, const0_rtx, 4, ofs);
4919 emit_move_insn (adjust_address (orig_dst, HImode, ofs),
4923 } while (bytes >= 2);
4925 else if (! TARGET_BWX)
4927 alpha_expand_unaligned_store (orig_dst, const0_rtx, 2, ofs);
4935 emit_move_insn (adjust_address (orig_dst, QImode, ofs), const0_rtx);
4943 /* Returns a mask so that zap(x, value) == x & mask. */
4946 alpha_expand_zap_mask (HOST_WIDE_INT value)
4951 if (HOST_BITS_PER_WIDE_INT >= 64)
4953 HOST_WIDE_INT mask = 0;
4955 for (i = 7; i >= 0; --i)
4958 if (!((value >> i) & 1))
4962 result = gen_int_mode (mask, DImode);
4964 else if (HOST_BITS_PER_WIDE_INT == 32)
4966 HOST_WIDE_INT mask_lo = 0, mask_hi = 0;
4968 for (i = 7; i >= 4; --i)
4971 if (!((value >> i) & 1))
4975 for (i = 3; i >= 0; --i)
4978 if (!((value >> i) & 1))
4982 result = immed_double_const (mask_lo, mask_hi, DImode);
4991 alpha_expand_builtin_vector_binop (rtx (*gen) (rtx, rtx, rtx),
4992 enum machine_mode mode,
4993 rtx op0, rtx op1, rtx op2)
4995 op0 = gen_lowpart (mode, op0);
4997 if (op1 == const0_rtx)
4998 op1 = CONST0_RTX (mode);
5000 op1 = gen_lowpart (mode, op1);
5002 if (op2 == const0_rtx)
5003 op2 = CONST0_RTX (mode);
5005 op2 = gen_lowpart (mode, op2);
5007 emit_insn ((*gen) (op0, op1, op2));
5010 /* Adjust the cost of a scheduling dependency. Return the new cost of
5011 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
5014 alpha_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
5016 enum attr_type insn_type, dep_insn_type;
5018 /* If the dependence is an anti-dependence, there is no cost. For an
5019 output dependence, there is sometimes a cost, but it doesn't seem
5020 worth handling those few cases. */
5021 if (REG_NOTE_KIND (link) != 0)
5024 /* If we can't recognize the insns, we can't really do anything. */
5025 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
5028 insn_type = get_attr_type (insn);
5029 dep_insn_type = get_attr_type (dep_insn);
5031 /* Bring in the user-defined memory latency. */
5032 if (dep_insn_type == TYPE_ILD
5033 || dep_insn_type == TYPE_FLD
5034 || dep_insn_type == TYPE_LDSYM)
5035 cost += alpha_memory_latency-1;
5037 /* Everything else handled in DFA bypasses now. */
5042 /* The number of instructions that can be issued per cycle. */
5045 alpha_issue_rate (void)
5047 return (alpha_cpu == PROCESSOR_EV4 ? 2 : 4);
5050 /* How many alternative schedules to try. This should be as wide as the
5051 scheduling freedom in the DFA, but no wider. Making this value too
5052 large results extra work for the scheduler.
5054 For EV4, loads can be issued to either IB0 or IB1, thus we have 2
5055 alternative schedules. For EV5, we can choose between E0/E1 and
5056 FA/FM. For EV6, an arithmetic insn can be issued to U0/U1/L0/L1. */
5059 alpha_multipass_dfa_lookahead (void)
5061 return (alpha_cpu == PROCESSOR_EV6 ? 4 : 2);
5064 /* Machine-specific function data. */
5066 struct machine_function GTY(())
5069 /* List of call information words for calls from this function. */
5070 struct rtx_def *first_ciw;
5071 struct rtx_def *last_ciw;
5074 /* List of deferred case vectors. */
5075 struct rtx_def *addr_list;
5078 const char *some_ld_name;
5080 /* For TARGET_LD_BUGGY_LDGP. */
5081 struct rtx_def *gp_save_rtx;
5084 /* How to allocate a 'struct machine_function'. */
5086 static struct machine_function *
5087 alpha_init_machine_status (void)
5089 return ((struct machine_function *)
5090 ggc_alloc_cleared (sizeof (struct machine_function)));
5093 /* Functions to save and restore alpha_return_addr_rtx. */
5095 /* Start the ball rolling with RETURN_ADDR_RTX. */
5098 alpha_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
5103 return get_hard_reg_initial_val (Pmode, REG_RA);
5106 /* Return or create a memory slot containing the gp value for the current
5107 function. Needed only if TARGET_LD_BUGGY_LDGP. */
5110 alpha_gp_save_rtx (void)
5112 rtx seq, m = cfun->machine->gp_save_rtx;
5118 m = assign_stack_local (DImode, UNITS_PER_WORD, BITS_PER_WORD);
5119 m = validize_mem (m);
5120 emit_move_insn (m, pic_offset_table_rtx);
5124 emit_insn_after (seq, entry_of_function ());
5126 cfun->machine->gp_save_rtx = m;
5133 alpha_ra_ever_killed (void)
5137 if (!has_hard_reg_initial_val (Pmode, REG_RA))
5138 return regs_ever_live[REG_RA];
5140 push_topmost_sequence ();
5142 pop_topmost_sequence ();
5144 return reg_set_between_p (gen_rtx_REG (Pmode, REG_RA), top, NULL_RTX);
5148 /* Return the trap mode suffix applicable to the current
5149 instruction, or NULL. */
5152 get_trap_mode_suffix (void)
5154 enum attr_trap_suffix s = get_attr_trap_suffix (current_output_insn);
5158 case TRAP_SUFFIX_NONE:
5161 case TRAP_SUFFIX_SU:
5162 if (alpha_fptm >= ALPHA_FPTM_SU)
5166 case TRAP_SUFFIX_SUI:
5167 if (alpha_fptm >= ALPHA_FPTM_SUI)
5171 case TRAP_SUFFIX_V_SV:
5179 case ALPHA_FPTM_SUI:
5184 case TRAP_SUFFIX_V_SV_SVI:
5193 case ALPHA_FPTM_SUI:
5198 case TRAP_SUFFIX_U_SU_SUI:
5207 case ALPHA_FPTM_SUI:
5215 /* Return the rounding mode suffix applicable to the current
5216 instruction, or NULL. */
5219 get_round_mode_suffix (void)
5221 enum attr_round_suffix s = get_attr_round_suffix (current_output_insn);
5225 case ROUND_SUFFIX_NONE:
5227 case ROUND_SUFFIX_NORMAL:
5230 case ALPHA_FPRM_NORM:
5232 case ALPHA_FPRM_MINF:
5234 case ALPHA_FPRM_CHOP:
5236 case ALPHA_FPRM_DYN:
5241 case ROUND_SUFFIX_C:
5247 /* Locate some local-dynamic symbol still in use by this function
5248 so that we can print its name in some movdi_er_tlsldm pattern. */
5251 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
5255 if (GET_CODE (x) == SYMBOL_REF
5256 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
5258 cfun->machine->some_ld_name = XSTR (x, 0);
5266 get_some_local_dynamic_name (void)
5270 if (cfun->machine->some_ld_name)
5271 return cfun->machine->some_ld_name;
5273 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
5275 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
5276 return cfun->machine->some_ld_name;
5281 /* Print an operand. Recognize special options, documented below. */
5284 print_operand (FILE *file, rtx x, int code)
5291 /* Print the assembler name of the current function. */
5292 assemble_name (file, alpha_fnname);
5296 assemble_name (file, get_some_local_dynamic_name ());
5301 const char *trap = get_trap_mode_suffix ();
5302 const char *round = get_round_mode_suffix ();
5305 fprintf (file, (TARGET_AS_SLASH_BEFORE_SUFFIX ? "/%s%s" : "%s%s"),
5306 (trap ? trap : ""), (round ? round : ""));
5311 /* Generates single precision instruction suffix. */
5312 fputc ((TARGET_FLOAT_VAX ? 'f' : 's'), file);
5316 /* Generates double precision instruction suffix. */
5317 fputc ((TARGET_FLOAT_VAX ? 'g' : 't'), file);
5321 /* Generates a nop after a noreturn call at the very end of the
5323 if (next_real_insn (current_output_insn) == 0)
5324 fprintf (file, "\n\tnop");
5328 if (alpha_this_literal_sequence_number == 0)
5329 alpha_this_literal_sequence_number = alpha_next_sequence_number++;
5330 fprintf (file, "%d", alpha_this_literal_sequence_number);
5334 if (alpha_this_gpdisp_sequence_number == 0)
5335 alpha_this_gpdisp_sequence_number = alpha_next_sequence_number++;
5336 fprintf (file, "%d", alpha_this_gpdisp_sequence_number);
5340 if (GET_CODE (x) == HIGH)
5341 output_addr_const (file, XEXP (x, 0));
5343 output_operand_lossage ("invalid %%H value");
5350 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSGD_CALL)
5352 x = XVECEXP (x, 0, 0);
5353 lituse = "lituse_tlsgd";
5355 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSLDM_CALL)
5357 x = XVECEXP (x, 0, 0);
5358 lituse = "lituse_tlsldm";
5360 else if (GET_CODE (x) == CONST_INT)
5361 lituse = "lituse_jsr";
5364 output_operand_lossage ("invalid %%J value");
5368 if (x != const0_rtx)
5369 fprintf (file, "\t\t!%s!%d", lituse, (int) INTVAL (x));
5374 /* If this operand is the constant zero, write it as "$31". */
5375 if (GET_CODE (x) == REG)
5376 fprintf (file, "%s", reg_names[REGNO (x)]);
5377 else if (x == CONST0_RTX (GET_MODE (x)))
5378 fprintf (file, "$31");
5380 output_operand_lossage ("invalid %%r value");
5384 /* Similar, but for floating-point. */
5385 if (GET_CODE (x) == REG)
5386 fprintf (file, "%s", reg_names[REGNO (x)]);
5387 else if (x == CONST0_RTX (GET_MODE (x)))
5388 fprintf (file, "$f31");
5390 output_operand_lossage ("invalid %%R value");
5394 /* Write the 1's complement of a constant. */
5395 if (GET_CODE (x) != CONST_INT)
5396 output_operand_lossage ("invalid %%N value");
5398 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INTVAL (x));
5402 /* Write 1 << C, for a constant C. */
5403 if (GET_CODE (x) != CONST_INT)
5404 output_operand_lossage ("invalid %%P value");
5406 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (HOST_WIDE_INT) 1 << INTVAL (x));
5410 /* Write the high-order 16 bits of a constant, sign-extended. */
5411 if (GET_CODE (x) != CONST_INT)
5412 output_operand_lossage ("invalid %%h value");
5414 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) >> 16);
5418 /* Write the low-order 16 bits of a constant, sign-extended. */
5419 if (GET_CODE (x) != CONST_INT)
5420 output_operand_lossage ("invalid %%L value");
5422 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5423 (INTVAL (x) & 0xffff) - 2 * (INTVAL (x) & 0x8000));
5427 /* Write mask for ZAP insn. */
5428 if (GET_CODE (x) == CONST_DOUBLE)
5430 HOST_WIDE_INT mask = 0;
5431 HOST_WIDE_INT value;
5433 value = CONST_DOUBLE_LOW (x);
5434 for (i = 0; i < HOST_BITS_PER_WIDE_INT / HOST_BITS_PER_CHAR;
5439 value = CONST_DOUBLE_HIGH (x);
5440 for (i = 0; i < HOST_BITS_PER_WIDE_INT / HOST_BITS_PER_CHAR;
5443 mask |= (1 << (i + sizeof (int)));
5445 fprintf (file, HOST_WIDE_INT_PRINT_DEC, mask & 0xff);
5448 else if (GET_CODE (x) == CONST_INT)
5450 HOST_WIDE_INT mask = 0, value = INTVAL (x);
5452 for (i = 0; i < 8; i++, value >>= 8)
5456 fprintf (file, HOST_WIDE_INT_PRINT_DEC, mask);
5459 output_operand_lossage ("invalid %%m value");
5463 /* 'b', 'w', 'l', or 'q' as the value of the constant. */
5464 if (GET_CODE (x) != CONST_INT
5465 || (INTVAL (x) != 8 && INTVAL (x) != 16
5466 && INTVAL (x) != 32 && INTVAL (x) != 64))
5467 output_operand_lossage ("invalid %%M value");
5469 fprintf (file, "%s",
5470 (INTVAL (x) == 8 ? "b"
5471 : INTVAL (x) == 16 ? "w"
5472 : INTVAL (x) == 32 ? "l"
5477 /* Similar, except do it from the mask. */
5478 if (GET_CODE (x) == CONST_INT)
5480 HOST_WIDE_INT value = INTVAL (x);
5487 if (value == 0xffff)
5492 if (value == 0xffffffff)
5503 else if (HOST_BITS_PER_WIDE_INT == 32
5504 && GET_CODE (x) == CONST_DOUBLE
5505 && CONST_DOUBLE_LOW (x) == 0xffffffff
5506 && CONST_DOUBLE_HIGH (x) == 0)
5511 output_operand_lossage ("invalid %%U value");
5515 /* Write the constant value divided by 8 for little-endian mode or
5516 (56 - value) / 8 for big-endian mode. */
5518 if (GET_CODE (x) != CONST_INT
5519 || (unsigned HOST_WIDE_INT) INTVAL (x) >= (WORDS_BIG_ENDIAN
5522 || (INTVAL (x) & 7) != 0)
5523 output_operand_lossage ("invalid %%s value");
5525 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5527 ? (56 - INTVAL (x)) / 8
5532 /* Same, except compute (64 - c) / 8 */
5534 if (GET_CODE (x) != CONST_INT
5535 && (unsigned HOST_WIDE_INT) INTVAL (x) >= 64
5536 && (INTVAL (x) & 7) != 8)
5537 output_operand_lossage ("invalid %%s value");
5539 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (64 - INTVAL (x)) / 8);
5544 /* On Unicos/Mk systems: use a DEX expression if the symbol
5545 clashes with a register name. */
5546 int dex = unicosmk_need_dex (x);
5548 fprintf (file, "DEX(%d)", dex);
5550 output_addr_const (file, x);
5554 case 'C': case 'D': case 'c': case 'd':
5555 /* Write out comparison name. */
5557 enum rtx_code c = GET_CODE (x);
5559 if (!COMPARISON_P (x))
5560 output_operand_lossage ("invalid %%C value");
5562 else if (code == 'D')
5563 c = reverse_condition (c);
5564 else if (code == 'c')
5565 c = swap_condition (c);
5566 else if (code == 'd')
5567 c = swap_condition (reverse_condition (c));
5570 fprintf (file, "ule");
5572 fprintf (file, "ult");
5573 else if (c == UNORDERED)
5574 fprintf (file, "un");
5576 fprintf (file, "%s", GET_RTX_NAME (c));
5581 /* Write the divide or modulus operator. */
5582 switch (GET_CODE (x))
5585 fprintf (file, "div%s", GET_MODE (x) == SImode ? "l" : "q");
5588 fprintf (file, "div%su", GET_MODE (x) == SImode ? "l" : "q");
5591 fprintf (file, "rem%s", GET_MODE (x) == SImode ? "l" : "q");
5594 fprintf (file, "rem%su", GET_MODE (x) == SImode ? "l" : "q");
5597 output_operand_lossage ("invalid %%E value");
5603 /* Write "_u" for unaligned access. */
5604 if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == AND)
5605 fprintf (file, "_u");
5609 if (GET_CODE (x) == REG)
5610 fprintf (file, "%s", reg_names[REGNO (x)]);
5611 else if (GET_CODE (x) == MEM)
5612 output_address (XEXP (x, 0));
5613 else if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == UNSPEC)
5615 switch (XINT (XEXP (x, 0), 1))
5619 output_addr_const (file, XVECEXP (XEXP (x, 0), 0, 0));
5622 output_operand_lossage ("unknown relocation unspec");
5627 output_addr_const (file, x);
5631 output_operand_lossage ("invalid %%xn code");
5636 print_operand_address (FILE *file, rtx addr)
5639 HOST_WIDE_INT offset = 0;
5641 if (GET_CODE (addr) == AND)
5642 addr = XEXP (addr, 0);
5644 if (GET_CODE (addr) == PLUS
5645 && GET_CODE (XEXP (addr, 1)) == CONST_INT)
5647 offset = INTVAL (XEXP (addr, 1));
5648 addr = XEXP (addr, 0);
5651 if (GET_CODE (addr) == LO_SUM)
5653 const char *reloc16, *reloclo;
5654 rtx op1 = XEXP (addr, 1);
5656 if (GET_CODE (op1) == CONST && GET_CODE (XEXP (op1, 0)) == UNSPEC)
5658 op1 = XEXP (op1, 0);
5659 switch (XINT (op1, 1))
5663 reloclo = (alpha_tls_size == 16 ? "dtprel" : "dtprello");
5667 reloclo = (alpha_tls_size == 16 ? "tprel" : "tprello");
5670 output_operand_lossage ("unknown relocation unspec");
5674 output_addr_const (file, XVECEXP (op1, 0, 0));
5679 reloclo = "gprellow";
5680 output_addr_const (file, op1);
5684 fprintf (file, "+" HOST_WIDE_INT_PRINT_DEC, offset);
5686 addr = XEXP (addr, 0);
5687 if (GET_CODE (addr) == REG)
5688 basereg = REGNO (addr);
5689 else if (GET_CODE (addr) == SUBREG
5690 && GET_CODE (SUBREG_REG (addr)) == REG)
5691 basereg = subreg_regno (addr);
5695 fprintf (file, "($%d)\t\t!%s", basereg,
5696 (basereg == 29 ? reloc16 : reloclo));
5700 if (GET_CODE (addr) == REG)
5701 basereg = REGNO (addr);
5702 else if (GET_CODE (addr) == SUBREG
5703 && GET_CODE (SUBREG_REG (addr)) == REG)
5704 basereg = subreg_regno (addr);
5705 else if (GET_CODE (addr) == CONST_INT)
5706 offset = INTVAL (addr);
5708 #if TARGET_ABI_OPEN_VMS
5709 else if (GET_CODE (addr) == SYMBOL_REF)
5711 fprintf (file, "%s", XSTR (addr, 0));
5714 else if (GET_CODE (addr) == CONST
5715 && GET_CODE (XEXP (addr, 0)) == PLUS
5716 && GET_CODE (XEXP (XEXP (addr, 0), 0)) == SYMBOL_REF)
5718 fprintf (file, "%s+" HOST_WIDE_INT_PRINT_DEC,
5719 XSTR (XEXP (XEXP (addr, 0), 0), 0),
5720 INTVAL (XEXP (XEXP (addr, 0), 1)));
5728 fprintf (file, HOST_WIDE_INT_PRINT_DEC "($%d)", offset, basereg);
5731 /* Emit RTL insns to initialize the variable parts of a trampoline at
5732 TRAMP. FNADDR is an RTX for the address of the function's pure
5733 code. CXT is an RTX for the static chain value for the function.
5735 The three offset parameters are for the individual template's
5736 layout. A JMPOFS < 0 indicates that the trampoline does not
5737 contain instructions at all.
5739 We assume here that a function will be called many more times than
5740 its address is taken (e.g., it might be passed to qsort), so we
5741 take the trouble to initialize the "hint" field in the JMP insn.
5742 Note that the hint field is PC (new) + 4 * bits 13:0. */
5745 alpha_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt,
5746 int fnofs, int cxtofs, int jmpofs)
5748 rtx temp, temp1, addr;
5749 /* VMS really uses DImode pointers in memory at this point. */
5750 enum machine_mode mode = TARGET_ABI_OPEN_VMS ? Pmode : ptr_mode;
5752 #ifdef POINTERS_EXTEND_UNSIGNED
5753 fnaddr = convert_memory_address (mode, fnaddr);
5754 cxt = convert_memory_address (mode, cxt);
5757 /* Store function address and CXT. */
5758 addr = memory_address (mode, plus_constant (tramp, fnofs));
5759 emit_move_insn (gen_rtx_MEM (mode, addr), fnaddr);
5760 addr = memory_address (mode, plus_constant (tramp, cxtofs));
5761 emit_move_insn (gen_rtx_MEM (mode, addr), cxt);
5763 /* This has been disabled since the hint only has a 32k range, and in
5764 no existing OS is the stack within 32k of the text segment. */
5765 if (0 && jmpofs >= 0)
5767 /* Compute hint value. */
5768 temp = force_operand (plus_constant (tramp, jmpofs+4), NULL_RTX);
5769 temp = expand_binop (DImode, sub_optab, fnaddr, temp, temp, 1,
5771 temp = expand_shift (RSHIFT_EXPR, Pmode, temp,
5772 build_int_2 (2, 0), NULL_RTX, 1);
5773 temp = expand_and (SImode, gen_lowpart (SImode, temp),
5774 GEN_INT (0x3fff), 0);
5776 /* Merge in the hint. */
5777 addr = memory_address (SImode, plus_constant (tramp, jmpofs));
5778 temp1 = force_reg (SImode, gen_rtx_MEM (SImode, addr));
5779 temp1 = expand_and (SImode, temp1, GEN_INT (0xffffc000), NULL_RTX);
5780 temp1 = expand_binop (SImode, ior_optab, temp1, temp, temp1, 1,
5782 emit_move_insn (gen_rtx_MEM (SImode, addr), temp1);
5785 #ifdef ENABLE_EXECUTE_STACK
5786 emit_library_call (init_one_libfunc ("__enable_execute_stack"),
5787 0, VOIDmode, 1, tramp, Pmode);
5791 emit_insn (gen_imb ());
5794 /* Determine where to put an argument to a function.
5795 Value is zero to push the argument on the stack,
5796 or a hard register in which to store the argument.
5798 MODE is the argument's machine mode.
5799 TYPE is the data type of the argument (as a tree).
5800 This is null for libcalls where that information may
5802 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5803 the preceding args and about the function being called.
5804 NAMED is nonzero if this argument is a named parameter
5805 (otherwise it is an extra parameter matching an ellipsis).
5807 On Alpha the first 6 words of args are normally in registers
5808 and the rest are pushed. */
5811 function_arg (CUMULATIVE_ARGS cum, enum machine_mode mode, tree type,
5812 int named ATTRIBUTE_UNUSED)
5817 /* Don't get confused and pass small structures in FP registers. */
5818 if (type && AGGREGATE_TYPE_P (type))
5822 #ifdef ENABLE_CHECKING
5823 /* With alpha_split_complex_arg, we shouldn't see any raw complex
5825 if (COMPLEX_MODE_P (mode))
5829 /* Set up defaults for FP operands passed in FP registers, and
5830 integral operands passed in integer registers. */
5831 if (TARGET_FPREGS && GET_MODE_CLASS (mode) == MODE_FLOAT)
5837 /* ??? Irritatingly, the definition of CUMULATIVE_ARGS is different for
5838 the three platforms, so we can't avoid conditional compilation. */
5839 #if TARGET_ABI_OPEN_VMS
5841 if (mode == VOIDmode)
5842 return alpha_arg_info_reg_val (cum);
5844 num_args = cum.num_args;
5846 || targetm.calls.must_pass_in_stack (mode, type))
5849 #elif TARGET_ABI_UNICOSMK
5853 /* If this is the last argument, generate the call info word (CIW). */
5854 /* ??? We don't include the caller's line number in the CIW because
5855 I don't know how to determine it if debug infos are turned off. */
5856 if (mode == VOIDmode)
5865 for (i = 0; i < cum.num_reg_words && i < 5; i++)
5866 if (cum.reg_args_type[i])
5867 lo |= (1 << (7 - i));
5869 if (cum.num_reg_words == 6 && cum.reg_args_type[5])
5872 lo |= cum.num_reg_words;
5874 #if HOST_BITS_PER_WIDE_INT == 32
5875 hi = (cum.num_args << 20) | cum.num_arg_words;
5877 lo = lo | ((HOST_WIDE_INT) cum.num_args << 52)
5878 | ((HOST_WIDE_INT) cum.num_arg_words << 32);
5881 ciw = immed_double_const (lo, hi, DImode);
5883 return gen_rtx_UNSPEC (DImode, gen_rtvec (1, ciw),
5884 UNSPEC_UMK_LOAD_CIW);
5887 size = ALPHA_ARG_SIZE (mode, type, named);
5888 num_args = cum.num_reg_words;
5890 || cum.num_reg_words + size > 6
5891 || targetm.calls.must_pass_in_stack (mode, type))
5893 else if (type && TYPE_MODE (type) == BLKmode)
5897 reg1 = gen_rtx_REG (DImode, num_args + 16);
5898 reg1 = gen_rtx_EXPR_LIST (DImode, reg1, const0_rtx);
5900 /* The argument fits in two registers. Note that we still need to
5901 reserve a register for empty structures. */
5905 return gen_rtx_PARALLEL (mode, gen_rtvec (1, reg1));
5908 reg2 = gen_rtx_REG (DImode, num_args + 17);
5909 reg2 = gen_rtx_EXPR_LIST (DImode, reg2, GEN_INT (8));
5910 return gen_rtx_PARALLEL (mode, gen_rtvec (2, reg1, reg2));
5914 #elif TARGET_ABI_OSF
5920 /* VOID is passed as a special flag for "last argument". */
5921 if (type == void_type_node)
5923 else if (targetm.calls.must_pass_in_stack (mode, type))
5927 #error Unhandled ABI
5930 return gen_rtx_REG (mode, num_args + basereg);
5933 /* Return true if TYPE must be returned in memory, instead of in registers. */
5936 alpha_return_in_memory (tree type, tree fndecl ATTRIBUTE_UNUSED)
5938 enum machine_mode mode = VOIDmode;
5943 mode = TYPE_MODE (type);
5945 /* All aggregates are returned in memory. */
5946 if (AGGREGATE_TYPE_P (type))
5950 size = GET_MODE_SIZE (mode);
5951 switch (GET_MODE_CLASS (mode))
5953 case MODE_VECTOR_FLOAT:
5954 /* Pass all float vectors in memory, like an aggregate. */
5957 case MODE_COMPLEX_FLOAT:
5958 /* We judge complex floats on the size of their element,
5959 not the size of the whole type. */
5960 size = GET_MODE_UNIT_SIZE (mode);
5965 case MODE_COMPLEX_INT:
5966 case MODE_VECTOR_INT:
5970 /* ??? We get called on all sorts of random stuff from
5971 aggregate_value_p. We can't abort, but it's not clear
5972 what's safe to return. Pretend it's a struct I guess. */
5976 /* Otherwise types must fit in one register. */
5977 return size > UNITS_PER_WORD;
5980 /* Return true if TYPE should be passed by invisible reference. */
5983 alpha_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED,
5984 enum machine_mode mode,
5985 tree type ATTRIBUTE_UNUSED,
5986 bool named ATTRIBUTE_UNUSED)
5988 return mode == TFmode || mode == TCmode;
5991 /* Define how to find the value returned by a function. VALTYPE is the
5992 data type of the value (as a tree). If the precise function being
5993 called is known, FUNC is its FUNCTION_DECL; otherwise, FUNC is 0.
5994 MODE is set instead of VALTYPE for libcalls.
5996 On Alpha the value is found in $0 for integer functions and
5997 $f0 for floating-point functions. */
6000 function_value (tree valtype, tree func ATTRIBUTE_UNUSED,
6001 enum machine_mode mode)
6003 unsigned int regnum;
6004 enum mode_class class;
6006 #ifdef ENABLE_CHECKING
6007 if (valtype && alpha_return_in_memory (valtype, func))
6012 mode = TYPE_MODE (valtype);
6014 class = GET_MODE_CLASS (mode);
6018 /* Do the same thing as PROMOTE_MODE. */
6022 case MODE_COMPLEX_INT:
6023 case MODE_VECTOR_INT:
6031 case MODE_COMPLEX_FLOAT:
6033 enum machine_mode cmode = GET_MODE_INNER (mode);
6035 return gen_rtx_PARALLEL
6038 gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (cmode, 32),
6040 gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (cmode, 33),
6041 GEN_INT (GET_MODE_SIZE (cmode)))));
6048 return gen_rtx_REG (mode, regnum);
6051 /* TCmode complex values are passed by invisible reference. We
6052 should not split these values. */
6055 alpha_split_complex_arg (tree type)
6057 return TYPE_MODE (type) != TCmode;
6061 alpha_build_builtin_va_list (void)
6063 tree base, ofs, space, record, type_decl;
6065 if (TARGET_ABI_OPEN_VMS || TARGET_ABI_UNICOSMK)
6066 return ptr_type_node;
6068 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
6069 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
6070 TREE_CHAIN (record) = type_decl;
6071 TYPE_NAME (record) = type_decl;
6073 /* C++? SET_IS_AGGR_TYPE (record, 1); */
6075 /* Dummy field to prevent alignment warnings. */
6076 space = build_decl (FIELD_DECL, NULL_TREE, integer_type_node);
6077 DECL_FIELD_CONTEXT (space) = record;
6078 DECL_ARTIFICIAL (space) = 1;
6079 DECL_IGNORED_P (space) = 1;
6081 ofs = build_decl (FIELD_DECL, get_identifier ("__offset"),
6083 DECL_FIELD_CONTEXT (ofs) = record;
6084 TREE_CHAIN (ofs) = space;
6086 base = build_decl (FIELD_DECL, get_identifier ("__base"),
6088 DECL_FIELD_CONTEXT (base) = record;
6089 TREE_CHAIN (base) = ofs;
6091 TYPE_FIELDS (record) = base;
6092 layout_type (record);
6097 /* Perform any needed actions needed for a function that is receiving a
6098 variable number of arguments. */
6101 alpha_setup_incoming_varargs (CUMULATIVE_ARGS *pcum,
6102 enum machine_mode mode ATTRIBUTE_UNUSED,
6103 tree type ATTRIBUTE_UNUSED,
6104 int *pretend_size, int no_rtl)
6106 #if TARGET_ABI_UNICOSMK
6107 /* On Unicos/Mk, the standard subroutine __T3E_MISMATCH stores all register
6108 arguments on the stack. Unfortunately, it doesn't always store the first
6109 one (i.e. the one that arrives in $16 or $f16). This is not a problem
6110 with stdargs as we always have at least one named argument there. */
6111 int num_reg_words = pcum->num_reg_words;
6112 if (num_reg_words < 6)
6116 emit_insn (gen_umk_mismatch_args (GEN_INT (num_reg_words + 1)));
6117 emit_insn (gen_arg_home_umk ());
6121 #elif TARGET_ABI_OPEN_VMS
6122 /* For VMS, we allocate space for all 6 arg registers plus a count.
6124 However, if NO registers need to be saved, don't allocate any space.
6125 This is not only because we won't need the space, but because AP
6126 includes the current_pretend_args_size and we don't want to mess up
6127 any ap-relative addresses already made. */
6128 if (pcum->num_args < 6)
6132 emit_move_insn (gen_rtx_REG (DImode, 1), virtual_incoming_args_rtx);
6133 emit_insn (gen_arg_home ());
6135 *pretend_size = 7 * UNITS_PER_WORD;
6138 /* On OSF/1 and friends, we allocate space for all 12 arg registers, but
6139 only push those that are remaining. However, if NO registers need to
6140 be saved, don't allocate any space. This is not only because we won't
6141 need the space, but because AP includes the current_pretend_args_size
6142 and we don't want to mess up any ap-relative addresses already made.
6144 If we are not to use the floating-point registers, save the integer
6145 registers where we would put the floating-point registers. This is
6146 not the most efficient way to implement varargs with just one register
6147 class, but it isn't worth doing anything more efficient in this rare
6149 CUMULATIVE_ARGS cum = *pcum;
6156 int set = get_varargs_alias_set ();
6159 tmp = gen_rtx_MEM (BLKmode,
6160 plus_constant (virtual_incoming_args_rtx,
6161 (cum + 6) * UNITS_PER_WORD));
6162 set_mem_alias_set (tmp, set);
6163 move_block_from_reg (16 + cum, tmp, 6 - cum);
6165 tmp = gen_rtx_MEM (BLKmode,
6166 plus_constant (virtual_incoming_args_rtx,
6167 cum * UNITS_PER_WORD));
6168 set_mem_alias_set (tmp, set);
6169 move_block_from_reg (16 + (TARGET_FPREGS ? 32 : 0) + cum, tmp,
6172 *pretend_size = 12 * UNITS_PER_WORD;
6177 alpha_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
6179 HOST_WIDE_INT offset;
6180 tree t, offset_field, base_field;
6182 if (TREE_CODE (TREE_TYPE (valist)) == ERROR_MARK)
6185 if (TARGET_ABI_UNICOSMK)
6186 std_expand_builtin_va_start (valist, nextarg);
6188 /* For Unix, TARGET_SETUP_INCOMING_VARARGS moves the starting address base
6189 up by 48, storing fp arg registers in the first 48 bytes, and the
6190 integer arg registers in the next 48 bytes. This is only done,
6191 however, if any integer registers need to be stored.
6193 If no integer registers need be stored, then we must subtract 48
6194 in order to account for the integer arg registers which are counted
6195 in argsize above, but which are not actually stored on the stack.
6196 Must further be careful here about structures straddling the last
6197 integer argument register; that futzes with pretend_args_size,
6198 which changes the meaning of AP. */
6201 offset = TARGET_ABI_OPEN_VMS ? UNITS_PER_WORD : 6 * UNITS_PER_WORD;
6203 offset = -6 * UNITS_PER_WORD + current_function_pretend_args_size;
6205 if (TARGET_ABI_OPEN_VMS)
6207 nextarg = plus_constant (nextarg, offset);
6208 nextarg = plus_constant (nextarg, NUM_ARGS * UNITS_PER_WORD);
6209 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist,
6210 make_tree (ptr_type_node, nextarg));
6211 TREE_SIDE_EFFECTS (t) = 1;
6213 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6217 base_field = TYPE_FIELDS (TREE_TYPE (valist));
6218 offset_field = TREE_CHAIN (base_field);
6220 base_field = build (COMPONENT_REF, TREE_TYPE (base_field),
6221 valist, base_field, NULL_TREE);
6222 offset_field = build (COMPONENT_REF, TREE_TYPE (offset_field),
6223 valist, offset_field, NULL_TREE);
6225 t = make_tree (ptr_type_node, virtual_incoming_args_rtx);
6226 t = build (PLUS_EXPR, ptr_type_node, t, build_int_2 (offset, 0));
6227 t = build (MODIFY_EXPR, TREE_TYPE (base_field), base_field, t);
6228 TREE_SIDE_EFFECTS (t) = 1;
6229 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6231 t = build_int_2 (NUM_ARGS * UNITS_PER_WORD, 0);
6232 t = build (MODIFY_EXPR, TREE_TYPE (offset_field), offset_field, t);
6233 TREE_SIDE_EFFECTS (t) = 1;
6234 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6239 alpha_gimplify_va_arg_1 (tree type, tree base, tree offset, tree *pre_p)
6241 tree type_size, ptr_type, addend, t, addr, internal_post;
6243 /* If the type could not be passed in registers, skip the block
6244 reserved for the registers. */
6245 if (targetm.calls.must_pass_in_stack (TYPE_MODE (type), type))
6247 t = fold_convert (TREE_TYPE (offset), build_int_2 (6*8, 0));
6248 t = build (MODIFY_EXPR, TREE_TYPE (offset), offset,
6249 build (MAX_EXPR, TREE_TYPE (offset), offset, t));
6250 gimplify_and_add (t, pre_p);
6254 ptr_type = build_pointer_type (type);
6256 if (TREE_CODE (type) == COMPLEX_TYPE)
6258 tree real_part, imag_part, real_temp;
6260 real_part = alpha_gimplify_va_arg_1 (TREE_TYPE (type), base,
6263 /* Copy the value into a new temporary, lest the formal temporary
6264 be reused out from under us. */
6265 real_temp = get_initialized_tmp_var (real_part, pre_p, NULL);
6267 imag_part = alpha_gimplify_va_arg_1 (TREE_TYPE (type), base,
6270 return build (COMPLEX_EXPR, type, real_temp, imag_part);
6272 else if (TREE_CODE (type) == REAL_TYPE)
6274 tree fpaddend, cond, fourtyeight;
6276 fourtyeight = fold_convert (TREE_TYPE (addend), build_int_2 (6*8, 0));
6277 fpaddend = fold (build (MINUS_EXPR, TREE_TYPE (addend),
6278 addend, fourtyeight));
6279 cond = fold (build (LT_EXPR, boolean_type_node, addend, fourtyeight));
6280 addend = fold (build (COND_EXPR, TREE_TYPE (addend), cond,
6284 /* Build the final address and force that value into a temporary. */
6285 addr = build (PLUS_EXPR, ptr_type, fold_convert (ptr_type, base),
6286 fold_convert (ptr_type, addend));
6287 internal_post = NULL;
6288 gimplify_expr (&addr, pre_p, &internal_post, is_gimple_val, fb_rvalue);
6289 append_to_statement_list (internal_post, pre_p);
6291 /* Update the offset field. */
6292 type_size = TYPE_SIZE_UNIT (TYPE_MAIN_VARIANT (type));
6293 if (type_size == NULL || TREE_OVERFLOW (type_size))
6297 t = size_binop (PLUS_EXPR, type_size, size_int (7));
6298 t = size_binop (TRUNC_DIV_EXPR, t, size_int (8));
6299 t = size_binop (MULT_EXPR, t, size_int (8));
6301 t = fold_convert (TREE_TYPE (offset), t);
6302 t = build (MODIFY_EXPR, void_type_node, offset,
6303 build (PLUS_EXPR, TREE_TYPE (offset), offset, t));
6304 gimplify_and_add (t, pre_p);
6306 return build_fold_indirect_ref (addr);
6310 alpha_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
6312 tree offset_field, base_field, offset, base, t, r;
6315 if (TARGET_ABI_OPEN_VMS || TARGET_ABI_UNICOSMK)
6316 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
6318 base_field = TYPE_FIELDS (va_list_type_node);
6319 offset_field = TREE_CHAIN (base_field);
6320 base_field = build (COMPONENT_REF, TREE_TYPE (base_field),
6321 valist, base_field, NULL_TREE);
6322 offset_field = build (COMPONENT_REF, TREE_TYPE (offset_field),
6323 valist, offset_field, NULL_TREE);
6325 /* Pull the fields of the structure out into temporaries. Since we never
6326 modify the base field, we can use a formal temporary. Sign-extend the
6327 offset field so that it's the proper width for pointer arithmetic. */
6328 base = get_formal_tmp_var (base_field, pre_p);
6330 t = fold_convert (lang_hooks.types.type_for_size (64, 0), offset_field);
6331 offset = get_initialized_tmp_var (t, pre_p, NULL);
6333 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, false);
6335 type = build_pointer_type (type);
6337 /* Find the value. Note that this will be a stable indirection, or
6338 a composite of stable indirections in the case of complex. */
6339 r = alpha_gimplify_va_arg_1 (type, base, offset, pre_p);
6341 /* Stuff the offset temporary back into its field. */
6342 t = build (MODIFY_EXPR, void_type_node, offset_field,
6343 fold_convert (TREE_TYPE (offset_field), offset));
6344 gimplify_and_add (t, pre_p);
6347 r = build_fold_indirect_ref (r);
6356 ALPHA_BUILTIN_CMPBGE,
6357 ALPHA_BUILTIN_EXTBL,
6358 ALPHA_BUILTIN_EXTWL,
6359 ALPHA_BUILTIN_EXTLL,
6360 ALPHA_BUILTIN_EXTQL,
6361 ALPHA_BUILTIN_EXTWH,
6362 ALPHA_BUILTIN_EXTLH,
6363 ALPHA_BUILTIN_EXTQH,
6364 ALPHA_BUILTIN_INSBL,
6365 ALPHA_BUILTIN_INSWL,
6366 ALPHA_BUILTIN_INSLL,
6367 ALPHA_BUILTIN_INSQL,
6368 ALPHA_BUILTIN_INSWH,
6369 ALPHA_BUILTIN_INSLH,
6370 ALPHA_BUILTIN_INSQH,
6371 ALPHA_BUILTIN_MSKBL,
6372 ALPHA_BUILTIN_MSKWL,
6373 ALPHA_BUILTIN_MSKLL,
6374 ALPHA_BUILTIN_MSKQL,
6375 ALPHA_BUILTIN_MSKWH,
6376 ALPHA_BUILTIN_MSKLH,
6377 ALPHA_BUILTIN_MSKQH,
6378 ALPHA_BUILTIN_UMULH,
6380 ALPHA_BUILTIN_ZAPNOT,
6381 ALPHA_BUILTIN_AMASK,
6382 ALPHA_BUILTIN_IMPLVER,
6384 ALPHA_BUILTIN_THREAD_POINTER,
6385 ALPHA_BUILTIN_SET_THREAD_POINTER,
6388 ALPHA_BUILTIN_MINUB8,
6389 ALPHA_BUILTIN_MINSB8,
6390 ALPHA_BUILTIN_MINUW4,
6391 ALPHA_BUILTIN_MINSW4,
6392 ALPHA_BUILTIN_MAXUB8,
6393 ALPHA_BUILTIN_MAXSB8,
6394 ALPHA_BUILTIN_MAXUW4,
6395 ALPHA_BUILTIN_MAXSW4,
6399 ALPHA_BUILTIN_UNPKBL,
6400 ALPHA_BUILTIN_UNPKBW,
6405 ALPHA_BUILTIN_CTPOP,
6410 static unsigned int const code_for_builtin[ALPHA_BUILTIN_max] = {
6411 CODE_FOR_builtin_cmpbge,
6412 CODE_FOR_builtin_extbl,
6413 CODE_FOR_builtin_extwl,
6414 CODE_FOR_builtin_extll,
6415 CODE_FOR_builtin_extql,
6416 CODE_FOR_builtin_extwh,
6417 CODE_FOR_builtin_extlh,
6418 CODE_FOR_builtin_extqh,
6419 CODE_FOR_builtin_insbl,
6420 CODE_FOR_builtin_inswl,
6421 CODE_FOR_builtin_insll,
6422 CODE_FOR_builtin_insql,
6423 CODE_FOR_builtin_inswh,
6424 CODE_FOR_builtin_inslh,
6425 CODE_FOR_builtin_insqh,
6426 CODE_FOR_builtin_mskbl,
6427 CODE_FOR_builtin_mskwl,
6428 CODE_FOR_builtin_mskll,
6429 CODE_FOR_builtin_mskql,
6430 CODE_FOR_builtin_mskwh,
6431 CODE_FOR_builtin_msklh,
6432 CODE_FOR_builtin_mskqh,
6433 CODE_FOR_umuldi3_highpart,
6434 CODE_FOR_builtin_zap,
6435 CODE_FOR_builtin_zapnot,
6436 CODE_FOR_builtin_amask,
6437 CODE_FOR_builtin_implver,
6438 CODE_FOR_builtin_rpcc,
6443 CODE_FOR_builtin_minub8,
6444 CODE_FOR_builtin_minsb8,
6445 CODE_FOR_builtin_minuw4,
6446 CODE_FOR_builtin_minsw4,
6447 CODE_FOR_builtin_maxub8,
6448 CODE_FOR_builtin_maxsb8,
6449 CODE_FOR_builtin_maxuw4,
6450 CODE_FOR_builtin_maxsw4,
6451 CODE_FOR_builtin_perr,
6452 CODE_FOR_builtin_pklb,
6453 CODE_FOR_builtin_pkwb,
6454 CODE_FOR_builtin_unpkbl,
6455 CODE_FOR_builtin_unpkbw,
6458 CODE_FOR_builtin_cttz,
6459 CODE_FOR_builtin_ctlz,
6460 CODE_FOR_builtin_ctpop
6463 struct alpha_builtin_def
6466 enum alpha_builtin code;
6467 unsigned int target_mask;
6470 static struct alpha_builtin_def const zero_arg_builtins[] = {
6471 { "__builtin_alpha_implver", ALPHA_BUILTIN_IMPLVER, 0 },
6472 { "__builtin_alpha_rpcc", ALPHA_BUILTIN_RPCC, 0 }
6475 static struct alpha_builtin_def const one_arg_builtins[] = {
6476 { "__builtin_alpha_amask", ALPHA_BUILTIN_AMASK, 0 },
6477 { "__builtin_alpha_pklb", ALPHA_BUILTIN_PKLB, MASK_MAX },
6478 { "__builtin_alpha_pkwb", ALPHA_BUILTIN_PKWB, MASK_MAX },
6479 { "__builtin_alpha_unpkbl", ALPHA_BUILTIN_UNPKBL, MASK_MAX },
6480 { "__builtin_alpha_unpkbw", ALPHA_BUILTIN_UNPKBW, MASK_MAX },
6481 { "__builtin_alpha_cttz", ALPHA_BUILTIN_CTTZ, MASK_CIX },
6482 { "__builtin_alpha_ctlz", ALPHA_BUILTIN_CTLZ, MASK_CIX },
6483 { "__builtin_alpha_ctpop", ALPHA_BUILTIN_CTPOP, MASK_CIX }
6486 static struct alpha_builtin_def const two_arg_builtins[] = {
6487 { "__builtin_alpha_cmpbge", ALPHA_BUILTIN_CMPBGE, 0 },
6488 { "__builtin_alpha_extbl", ALPHA_BUILTIN_EXTBL, 0 },
6489 { "__builtin_alpha_extwl", ALPHA_BUILTIN_EXTWL, 0 },
6490 { "__builtin_alpha_extll", ALPHA_BUILTIN_EXTLL, 0 },
6491 { "__builtin_alpha_extql", ALPHA_BUILTIN_EXTQL, 0 },
6492 { "__builtin_alpha_extwh", ALPHA_BUILTIN_EXTWH, 0 },
6493 { "__builtin_alpha_extlh", ALPHA_BUILTIN_EXTLH, 0 },
6494 { "__builtin_alpha_extqh", ALPHA_BUILTIN_EXTQH, 0 },
6495 { "__builtin_alpha_insbl", ALPHA_BUILTIN_INSBL, 0 },
6496 { "__builtin_alpha_inswl", ALPHA_BUILTIN_INSWL, 0 },
6497 { "__builtin_alpha_insll", ALPHA_BUILTIN_INSLL, 0 },
6498 { "__builtin_alpha_insql", ALPHA_BUILTIN_INSQL, 0 },
6499 { "__builtin_alpha_inswh", ALPHA_BUILTIN_INSWH, 0 },
6500 { "__builtin_alpha_inslh", ALPHA_BUILTIN_INSLH, 0 },
6501 { "__builtin_alpha_insqh", ALPHA_BUILTIN_INSQH, 0 },
6502 { "__builtin_alpha_mskbl", ALPHA_BUILTIN_MSKBL, 0 },
6503 { "__builtin_alpha_mskwl", ALPHA_BUILTIN_MSKWL, 0 },
6504 { "__builtin_alpha_mskll", ALPHA_BUILTIN_MSKLL, 0 },
6505 { "__builtin_alpha_mskql", ALPHA_BUILTIN_MSKQL, 0 },
6506 { "__builtin_alpha_mskwh", ALPHA_BUILTIN_MSKWH, 0 },
6507 { "__builtin_alpha_msklh", ALPHA_BUILTIN_MSKLH, 0 },
6508 { "__builtin_alpha_mskqh", ALPHA_BUILTIN_MSKQH, 0 },
6509 { "__builtin_alpha_umulh", ALPHA_BUILTIN_UMULH, 0 },
6510 { "__builtin_alpha_zap", ALPHA_BUILTIN_ZAP, 0 },
6511 { "__builtin_alpha_zapnot", ALPHA_BUILTIN_ZAPNOT, 0 },
6512 { "__builtin_alpha_minub8", ALPHA_BUILTIN_MINUB8, MASK_MAX },
6513 { "__builtin_alpha_minsb8", ALPHA_BUILTIN_MINSB8, MASK_MAX },
6514 { "__builtin_alpha_minuw4", ALPHA_BUILTIN_MINUW4, MASK_MAX },
6515 { "__builtin_alpha_minsw4", ALPHA_BUILTIN_MINSW4, MASK_MAX },
6516 { "__builtin_alpha_maxub8", ALPHA_BUILTIN_MAXUB8, MASK_MAX },
6517 { "__builtin_alpha_maxsb8", ALPHA_BUILTIN_MAXSB8, MASK_MAX },
6518 { "__builtin_alpha_maxuw4", ALPHA_BUILTIN_MAXUW4, MASK_MAX },
6519 { "__builtin_alpha_maxsw4", ALPHA_BUILTIN_MAXSW4, MASK_MAX },
6520 { "__builtin_alpha_perr", ALPHA_BUILTIN_PERR, MASK_MAX }
6524 alpha_init_builtins (void)
6526 const struct alpha_builtin_def *p;
6530 ftype = build_function_type (long_integer_type_node, void_list_node);
6532 p = zero_arg_builtins;
6533 for (i = 0; i < ARRAY_SIZE (zero_arg_builtins); ++i, ++p)
6534 if ((target_flags & p->target_mask) == p->target_mask)
6535 lang_hooks.builtin_function (p->name, ftype, p->code, BUILT_IN_MD,
6538 ftype = build_function_type_list (long_integer_type_node,
6539 long_integer_type_node, NULL_TREE);
6541 p = one_arg_builtins;
6542 for (i = 0; i < ARRAY_SIZE (one_arg_builtins); ++i, ++p)
6543 if ((target_flags & p->target_mask) == p->target_mask)
6544 lang_hooks.builtin_function (p->name, ftype, p->code, BUILT_IN_MD,
6547 ftype = build_function_type_list (long_integer_type_node,
6548 long_integer_type_node,
6549 long_integer_type_node, NULL_TREE);
6551 p = two_arg_builtins;
6552 for (i = 0; i < ARRAY_SIZE (two_arg_builtins); ++i, ++p)
6553 if ((target_flags & p->target_mask) == p->target_mask)
6554 lang_hooks.builtin_function (p->name, ftype, p->code, BUILT_IN_MD,
6557 ftype = build_function_type (ptr_type_node, void_list_node);
6558 lang_hooks.builtin_function ("__builtin_thread_pointer", ftype,
6559 ALPHA_BUILTIN_THREAD_POINTER, BUILT_IN_MD,
6562 ftype = build_function_type_list (void_type_node, ptr_type_node, NULL_TREE);
6563 lang_hooks.builtin_function ("__builtin_set_thread_pointer", ftype,
6564 ALPHA_BUILTIN_SET_THREAD_POINTER, BUILT_IN_MD,
6568 /* Expand an expression EXP that calls a built-in function,
6569 with result going to TARGET if that's convenient
6570 (and in mode MODE if that's convenient).
6571 SUBTARGET may be used as the target for computing one of EXP's operands.
6572 IGNORE is nonzero if the value is to be ignored. */
6575 alpha_expand_builtin (tree exp, rtx target,
6576 rtx subtarget ATTRIBUTE_UNUSED,
6577 enum machine_mode mode ATTRIBUTE_UNUSED,
6578 int ignore ATTRIBUTE_UNUSED)
6582 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6583 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6584 tree arglist = TREE_OPERAND (exp, 1);
6585 enum insn_code icode;
6586 rtx op[MAX_ARGS], pat;
6590 if (fcode >= ALPHA_BUILTIN_max)
6591 internal_error ("bad builtin fcode");
6592 icode = code_for_builtin[fcode];
6594 internal_error ("bad builtin fcode");
6596 nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
6598 for (arglist = TREE_OPERAND (exp, 1), arity = 0;
6600 arglist = TREE_CHAIN (arglist), arity++)
6602 const struct insn_operand_data *insn_op;
6604 tree arg = TREE_VALUE (arglist);
6605 if (arg == error_mark_node)
6607 if (arity > MAX_ARGS)
6610 insn_op = &insn_data[icode].operand[arity + nonvoid];
6612 op[arity] = expand_expr (arg, NULL_RTX, insn_op->mode, 0);
6614 if (!(*insn_op->predicate) (op[arity], insn_op->mode))
6615 op[arity] = copy_to_mode_reg (insn_op->mode, op[arity]);
6620 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6622 || GET_MODE (target) != tmode
6623 || !(*insn_data[icode].operand[0].predicate) (target, tmode))
6624 target = gen_reg_rtx (tmode);
6630 pat = GEN_FCN (icode) (target);
6634 pat = GEN_FCN (icode) (target, op[0]);
6636 pat = GEN_FCN (icode) (op[0]);
6639 pat = GEN_FCN (icode) (target, op[0], op[1]);
6654 /* This page contains routines that are used to determine what the function
6655 prologue and epilogue code will do and write them out. */
6657 /* Compute the size of the save area in the stack. */
6659 /* These variables are used for communication between the following functions.
6660 They indicate various things about the current function being compiled
6661 that are used to tell what kind of prologue, epilogue and procedure
6662 descriptor to generate. */
6664 /* Nonzero if we need a stack procedure. */
6665 enum alpha_procedure_types {PT_NULL = 0, PT_REGISTER = 1, PT_STACK = 2};
6666 static enum alpha_procedure_types alpha_procedure_type;
6668 /* Register number (either FP or SP) that is used to unwind the frame. */
6669 static int vms_unwind_regno;
6671 /* Register number used to save FP. We need not have one for RA since
6672 we don't modify it for register procedures. This is only defined
6673 for register frame procedures. */
6674 static int vms_save_fp_regno;
6676 /* Register number used to reference objects off our PV. */
6677 static int vms_base_regno;
6679 /* Compute register masks for saved registers. */
6682 alpha_sa_mask (unsigned long *imaskP, unsigned long *fmaskP)
6684 unsigned long imask = 0;
6685 unsigned long fmask = 0;
6688 /* When outputting a thunk, we don't have valid register life info,
6689 but assemble_start_function wants to output .frame and .mask
6691 if (current_function_is_thunk)
6698 if (TARGET_ABI_OPEN_VMS && alpha_procedure_type == PT_STACK)
6699 imask |= (1UL << HARD_FRAME_POINTER_REGNUM);
6701 /* One for every register we have to save. */
6702 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
6703 if (! fixed_regs[i] && ! call_used_regs[i]
6704 && regs_ever_live[i] && i != REG_RA
6705 && (!TARGET_ABI_UNICOSMK || i != HARD_FRAME_POINTER_REGNUM))
6708 imask |= (1UL << i);
6710 fmask |= (1UL << (i - 32));
6713 /* We need to restore these for the handler. */
6714 if (current_function_calls_eh_return)
6718 unsigned regno = EH_RETURN_DATA_REGNO (i);
6719 if (regno == INVALID_REGNUM)
6721 imask |= 1UL << regno;
6724 /* Glibc likes to use $31 as an unwind stopper for crt0. To
6725 avoid hackery in unwind-dw2.c, we need to actively store a
6726 zero in the prologue of _Unwind_RaiseException et al. */
6730 /* If any register spilled, then spill the return address also. */
6731 /* ??? This is required by the Digital stack unwind specification
6732 and isn't needed if we're doing Dwarf2 unwinding. */
6733 if (imask || fmask || alpha_ra_ever_killed ())
6734 imask |= (1UL << REG_RA);
6741 alpha_sa_size (void)
6743 unsigned long mask[2];
6747 alpha_sa_mask (&mask[0], &mask[1]);
6749 if (TARGET_ABI_UNICOSMK)
6751 if (mask[0] || mask[1])
6756 for (j = 0; j < 2; ++j)
6757 for (i = 0; i < 32; ++i)
6758 if ((mask[j] >> i) & 1)
6762 if (TARGET_ABI_UNICOSMK)
6764 /* We might not need to generate a frame if we don't make any calls
6765 (including calls to __T3E_MISMATCH if this is a vararg function),
6766 don't have any local variables which require stack slots, don't
6767 use alloca and have not determined that we need a frame for other
6770 alpha_procedure_type
6771 = (sa_size || get_frame_size() != 0
6772 || current_function_outgoing_args_size
6773 || current_function_stdarg || current_function_calls_alloca
6774 || frame_pointer_needed)
6775 ? PT_STACK : PT_REGISTER;
6777 /* Always reserve space for saving callee-saved registers if we
6778 need a frame as required by the calling convention. */
6779 if (alpha_procedure_type == PT_STACK)
6782 else if (TARGET_ABI_OPEN_VMS)
6784 /* Start by assuming we can use a register procedure if we don't
6785 make any calls (REG_RA not used) or need to save any
6786 registers and a stack procedure if we do. */
6787 if ((mask[0] >> REG_RA) & 1)
6788 alpha_procedure_type = PT_STACK;
6789 else if (get_frame_size() != 0)
6790 alpha_procedure_type = PT_REGISTER;
6792 alpha_procedure_type = PT_NULL;
6794 /* Don't reserve space for saving FP & RA yet. Do that later after we've
6795 made the final decision on stack procedure vs register procedure. */
6796 if (alpha_procedure_type == PT_STACK)
6799 /* Decide whether to refer to objects off our PV via FP or PV.
6800 If we need FP for something else or if we receive a nonlocal
6801 goto (which expects PV to contain the value), we must use PV.
6802 Otherwise, start by assuming we can use FP. */
6805 = (frame_pointer_needed
6806 || current_function_has_nonlocal_label
6807 || alpha_procedure_type == PT_STACK
6808 || current_function_outgoing_args_size)
6809 ? REG_PV : HARD_FRAME_POINTER_REGNUM;
6811 /* If we want to copy PV into FP, we need to find some register
6812 in which to save FP. */
6814 vms_save_fp_regno = -1;
6815 if (vms_base_regno == HARD_FRAME_POINTER_REGNUM)
6816 for (i = 0; i < 32; i++)
6817 if (! fixed_regs[i] && call_used_regs[i] && ! regs_ever_live[i])
6818 vms_save_fp_regno = i;
6820 if (vms_save_fp_regno == -1 && alpha_procedure_type == PT_REGISTER)
6821 vms_base_regno = REG_PV, alpha_procedure_type = PT_STACK;
6822 else if (alpha_procedure_type == PT_NULL)
6823 vms_base_regno = REG_PV;
6825 /* Stack unwinding should be done via FP unless we use it for PV. */
6826 vms_unwind_regno = (vms_base_regno == REG_PV
6827 ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM);
6829 /* If this is a stack procedure, allow space for saving FP and RA. */
6830 if (alpha_procedure_type == PT_STACK)
6835 /* Our size must be even (multiple of 16 bytes). */
6843 /* Define the offset between two registers, one to be eliminated,
6844 and the other its replacement, at the start of a routine. */
6847 alpha_initial_elimination_offset (unsigned int from,
6848 unsigned int to ATTRIBUTE_UNUSED)
6852 ret = alpha_sa_size ();
6853 ret += ALPHA_ROUND (current_function_outgoing_args_size);
6855 if (from == FRAME_POINTER_REGNUM)
6857 else if (from == ARG_POINTER_REGNUM)
6858 ret += (ALPHA_ROUND (get_frame_size ()
6859 + current_function_pretend_args_size)
6860 - current_function_pretend_args_size);
6868 alpha_pv_save_size (void)
6871 return alpha_procedure_type == PT_STACK ? 8 : 0;
6875 alpha_using_fp (void)
6878 return vms_unwind_regno == HARD_FRAME_POINTER_REGNUM;
6881 #if TARGET_ABI_OPEN_VMS
6883 const struct attribute_spec vms_attribute_table[] =
6885 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
6886 { "overlaid", 0, 0, true, false, false, NULL },
6887 { "global", 0, 0, true, false, false, NULL },
6888 { "initialize", 0, 0, true, false, false, NULL },
6889 { NULL, 0, 0, false, false, false, NULL }
6895 find_lo_sum_using_gp (rtx *px, void *data ATTRIBUTE_UNUSED)
6897 return GET_CODE (*px) == LO_SUM && XEXP (*px, 0) == pic_offset_table_rtx;
6901 alpha_find_lo_sum_using_gp (rtx insn)
6903 return for_each_rtx (&PATTERN (insn), find_lo_sum_using_gp, NULL) > 0;
6907 alpha_does_function_need_gp (void)
6911 /* The GP being variable is an OSF abi thing. */
6912 if (! TARGET_ABI_OSF)
6915 /* We need the gp to load the address of __mcount. */
6916 if (TARGET_PROFILING_NEEDS_GP && current_function_profile)
6919 /* The code emitted by alpha_output_mi_thunk_osf uses the gp. */
6920 if (current_function_is_thunk)
6923 /* The nonlocal receiver pattern assumes that the gp is valid for
6924 the nested function. Reasonable because it's almost always set
6925 correctly already. For the cases where that's wrong, make sure
6926 the nested function loads its gp on entry. */
6927 if (current_function_has_nonlocal_goto)
6930 /* If we need a GP (we have a LDSYM insn or a CALL_INSN), load it first.
6931 Even if we are a static function, we still need to do this in case
6932 our address is taken and passed to something like qsort. */
6934 push_topmost_sequence ();
6935 insn = get_insns ();
6936 pop_topmost_sequence ();
6938 for (; insn; insn = NEXT_INSN (insn))
6940 && GET_CODE (PATTERN (insn)) != USE
6941 && GET_CODE (PATTERN (insn)) != CLOBBER
6942 && get_attr_usegp (insn))
6949 /* Helper function to set RTX_FRAME_RELATED_P on instructions, including
6953 set_frame_related_p (void)
6955 rtx seq = get_insns ();
6966 while (insn != NULL_RTX)
6968 RTX_FRAME_RELATED_P (insn) = 1;
6969 insn = NEXT_INSN (insn);
6971 seq = emit_insn (seq);
6975 seq = emit_insn (seq);
6976 RTX_FRAME_RELATED_P (seq) = 1;
6981 #define FRP(exp) (start_sequence (), exp, set_frame_related_p ())
6983 /* Write function prologue. */
6985 /* On vms we have two kinds of functions:
6987 - stack frame (PROC_STACK)
6988 these are 'normal' functions with local vars and which are
6989 calling other functions
6990 - register frame (PROC_REGISTER)
6991 keeps all data in registers, needs no stack
6993 We must pass this to the assembler so it can generate the
6994 proper pdsc (procedure descriptor)
6995 This is done with the '.pdesc' command.
6997 On not-vms, we don't really differentiate between the two, as we can
6998 simply allocate stack without saving registers. */
7001 alpha_expand_prologue (void)
7003 /* Registers to save. */
7004 unsigned long imask = 0;
7005 unsigned long fmask = 0;
7006 /* Stack space needed for pushing registers clobbered by us. */
7007 HOST_WIDE_INT sa_size;
7008 /* Complete stack size needed. */
7009 HOST_WIDE_INT frame_size;
7010 /* Offset from base reg to register save area. */
7011 HOST_WIDE_INT reg_offset;
7015 sa_size = alpha_sa_size ();
7017 frame_size = get_frame_size ();
7018 if (TARGET_ABI_OPEN_VMS)
7019 frame_size = ALPHA_ROUND (sa_size
7020 + (alpha_procedure_type == PT_STACK ? 8 : 0)
7022 + current_function_pretend_args_size);
7023 else if (TARGET_ABI_UNICOSMK)
7024 /* We have to allocate space for the DSIB if we generate a frame. */
7025 frame_size = ALPHA_ROUND (sa_size
7026 + (alpha_procedure_type == PT_STACK ? 48 : 0))
7027 + ALPHA_ROUND (frame_size
7028 + current_function_outgoing_args_size);
7030 frame_size = (ALPHA_ROUND (current_function_outgoing_args_size)
7032 + ALPHA_ROUND (frame_size
7033 + current_function_pretend_args_size));
7035 if (TARGET_ABI_OPEN_VMS)
7038 reg_offset = ALPHA_ROUND (current_function_outgoing_args_size);
7040 alpha_sa_mask (&imask, &fmask);
7042 /* Emit an insn to reload GP, if needed. */
7045 alpha_function_needs_gp = alpha_does_function_need_gp ();
7046 if (alpha_function_needs_gp)
7047 emit_insn (gen_prologue_ldgp ());
7050 /* TARGET_PROFILING_NEEDS_GP actually implies that we need to insert
7051 the call to mcount ourselves, rather than having the linker do it
7052 magically in response to -pg. Since _mcount has special linkage,
7053 don't represent the call as a call. */
7054 if (TARGET_PROFILING_NEEDS_GP && current_function_profile)
7055 emit_insn (gen_prologue_mcount ());
7057 if (TARGET_ABI_UNICOSMK)
7058 unicosmk_gen_dsib (&imask);
7060 /* Adjust the stack by the frame size. If the frame size is > 4096
7061 bytes, we need to be sure we probe somewhere in the first and last
7062 4096 bytes (we can probably get away without the latter test) and
7063 every 8192 bytes in between. If the frame size is > 32768, we
7064 do this in a loop. Otherwise, we generate the explicit probe
7067 Note that we are only allowed to adjust sp once in the prologue. */
7069 if (frame_size <= 32768)
7071 if (frame_size > 4096)
7076 emit_insn (gen_probe_stack (GEN_INT (TARGET_ABI_UNICOSMK
7079 while ((probed += 8192) < frame_size);
7081 /* We only have to do this probe if we aren't saving registers. */
7082 if (sa_size == 0 && probed + 4096 < frame_size)
7083 emit_insn (gen_probe_stack (GEN_INT (-frame_size)));
7086 if (frame_size != 0)
7087 FRP (emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx,
7088 GEN_INT (TARGET_ABI_UNICOSMK
7094 /* Here we generate code to set R22 to SP + 4096 and set R23 to the
7095 number of 8192 byte blocks to probe. We then probe each block
7096 in the loop and then set SP to the proper location. If the
7097 amount remaining is > 4096, we have to do one more probe if we
7098 are not saving any registers. */
7100 HOST_WIDE_INT blocks = (frame_size + 4096) / 8192;
7101 HOST_WIDE_INT leftover = frame_size + 4096 - blocks * 8192;
7102 rtx ptr = gen_rtx_REG (DImode, 22);
7103 rtx count = gen_rtx_REG (DImode, 23);
7106 emit_move_insn (count, GEN_INT (blocks));
7107 emit_insn (gen_adddi3 (ptr, stack_pointer_rtx,
7108 GEN_INT (TARGET_ABI_UNICOSMK ? 4096 - 64 : 4096)));
7110 /* Because of the difficulty in emitting a new basic block this
7111 late in the compilation, generate the loop as a single insn. */
7112 emit_insn (gen_prologue_stack_probe_loop (count, ptr));
7114 if (leftover > 4096 && sa_size == 0)
7116 rtx last = gen_rtx_MEM (DImode, plus_constant (ptr, -leftover));
7117 MEM_VOLATILE_P (last) = 1;
7118 emit_move_insn (last, const0_rtx);
7121 if (TARGET_ABI_WINDOWS_NT)
7123 /* For NT stack unwind (done by 'reverse execution'), it's
7124 not OK to take the result of a loop, even though the value
7125 is already in ptr, so we reload it via a single operation
7126 and subtract it to sp.
7128 Yes, that's correct -- we have to reload the whole constant
7129 into a temporary via ldah+lda then subtract from sp. */
7131 HOST_WIDE_INT lo, hi;
7132 lo = ((frame_size & 0xffff) ^ 0x8000) - 0x8000;
7133 hi = frame_size - lo;
7135 emit_move_insn (ptr, GEN_INT (hi));
7136 emit_insn (gen_adddi3 (ptr, ptr, GEN_INT (lo)));
7137 seq = emit_insn (gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx,
7142 seq = emit_insn (gen_adddi3 (stack_pointer_rtx, ptr,
7143 GEN_INT (-leftover)));
7146 /* This alternative is special, because the DWARF code cannot
7147 possibly intuit through the loop above. So we invent this
7148 note it looks at instead. */
7149 RTX_FRAME_RELATED_P (seq) = 1;
7151 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
7152 gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7153 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
7154 GEN_INT (TARGET_ABI_UNICOSMK
7160 if (!TARGET_ABI_UNICOSMK)
7162 /* Cope with very large offsets to the register save area. */
7163 sa_reg = stack_pointer_rtx;
7164 if (reg_offset + sa_size > 0x8000)
7166 int low = ((reg_offset & 0xffff) ^ 0x8000) - 0x8000;
7169 if (low + sa_size <= 0x8000)
7170 bias = reg_offset - low, reg_offset = low;
7172 bias = reg_offset, reg_offset = 0;
7174 sa_reg = gen_rtx_REG (DImode, 24);
7175 FRP (emit_insn (gen_adddi3 (sa_reg, stack_pointer_rtx,
7179 /* Save regs in stack order. Beginning with VMS PV. */
7180 if (TARGET_ABI_OPEN_VMS && alpha_procedure_type == PT_STACK)
7182 mem = gen_rtx_MEM (DImode, stack_pointer_rtx);
7183 set_mem_alias_set (mem, alpha_sr_alias_set);
7184 FRP (emit_move_insn (mem, gen_rtx_REG (DImode, REG_PV)));
7187 /* Save register RA next. */
7188 if (imask & (1UL << REG_RA))
7190 mem = gen_rtx_MEM (DImode, plus_constant (sa_reg, reg_offset));
7191 set_mem_alias_set (mem, alpha_sr_alias_set);
7192 FRP (emit_move_insn (mem, gen_rtx_REG (DImode, REG_RA)));
7193 imask &= ~(1UL << REG_RA);
7197 /* Now save any other registers required to be saved. */
7198 for (i = 0; i < 31; i++)
7199 if (imask & (1UL << i))
7201 mem = gen_rtx_MEM (DImode, plus_constant (sa_reg, reg_offset));
7202 set_mem_alias_set (mem, alpha_sr_alias_set);
7203 FRP (emit_move_insn (mem, gen_rtx_REG (DImode, i)));
7207 /* Store a zero if requested for unwinding. */
7208 if (imask & (1UL << 31))
7212 mem = gen_rtx_MEM (DImode, plus_constant (sa_reg, reg_offset));
7213 set_mem_alias_set (mem, alpha_sr_alias_set);
7214 insn = emit_move_insn (mem, const0_rtx);
7216 RTX_FRAME_RELATED_P (insn) = 1;
7217 t = gen_rtx_REG (Pmode, 31);
7218 t = gen_rtx_SET (VOIDmode, mem, t);
7219 t = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, t, REG_NOTES (insn));
7220 REG_NOTES (insn) = t;
7225 for (i = 0; i < 31; i++)
7226 if (fmask & (1UL << i))
7228 mem = gen_rtx_MEM (DFmode, plus_constant (sa_reg, reg_offset));
7229 set_mem_alias_set (mem, alpha_sr_alias_set);
7230 FRP (emit_move_insn (mem, gen_rtx_REG (DFmode, i+32)));
7234 else if (TARGET_ABI_UNICOSMK && alpha_procedure_type == PT_STACK)
7236 /* The standard frame on the T3E includes space for saving registers.
7237 We just have to use it. We don't have to save the return address and
7238 the old frame pointer here - they are saved in the DSIB. */
7241 for (i = 9; i < 15; i++)
7242 if (imask & (1UL << i))
7244 mem = gen_rtx_MEM (DImode, plus_constant(hard_frame_pointer_rtx,
7246 set_mem_alias_set (mem, alpha_sr_alias_set);
7247 FRP (emit_move_insn (mem, gen_rtx_REG (DImode, i)));
7250 for (i = 2; i < 10; i++)
7251 if (fmask & (1UL << i))
7253 mem = gen_rtx_MEM (DFmode, plus_constant (hard_frame_pointer_rtx,
7255 set_mem_alias_set (mem, alpha_sr_alias_set);
7256 FRP (emit_move_insn (mem, gen_rtx_REG (DFmode, i+32)));
7261 if (TARGET_ABI_OPEN_VMS)
7263 if (alpha_procedure_type == PT_REGISTER)
7264 /* Register frame procedures save the fp.
7265 ?? Ought to have a dwarf2 save for this. */
7266 emit_move_insn (gen_rtx_REG (DImode, vms_save_fp_regno),
7267 hard_frame_pointer_rtx);
7269 if (alpha_procedure_type != PT_NULL && vms_base_regno != REG_PV)
7270 emit_insn (gen_force_movdi (gen_rtx_REG (DImode, vms_base_regno),
7271 gen_rtx_REG (DImode, REG_PV)));
7273 if (alpha_procedure_type != PT_NULL
7274 && vms_unwind_regno == HARD_FRAME_POINTER_REGNUM)
7275 FRP (emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx));
7277 /* If we have to allocate space for outgoing args, do it now. */
7278 if (current_function_outgoing_args_size != 0)
7281 = emit_move_insn (stack_pointer_rtx,
7283 (hard_frame_pointer_rtx,
7285 (current_function_outgoing_args_size))));
7287 /* Only set FRAME_RELATED_P on the stack adjustment we just emitted
7288 if ! frame_pointer_needed. Setting the bit will change the CFA
7289 computation rule to use sp again, which would be wrong if we had
7290 frame_pointer_needed, as this means sp might move unpredictably
7294 frame_pointer_needed
7295 => vms_unwind_regno == HARD_FRAME_POINTER_REGNUM
7297 current_function_outgoing_args_size != 0
7298 => alpha_procedure_type != PT_NULL,
7300 so when we are not setting the bit here, we are guaranteed to
7301 have emitted an FRP frame pointer update just before. */
7302 RTX_FRAME_RELATED_P (seq) = ! frame_pointer_needed;
7305 else if (!TARGET_ABI_UNICOSMK)
7307 /* If we need a frame pointer, set it from the stack pointer. */
7308 if (frame_pointer_needed)
7310 if (TARGET_CAN_FAULT_IN_PROLOGUE)
7311 FRP (emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx));
7313 /* This must always be the last instruction in the
7314 prologue, thus we emit a special move + clobber. */
7315 FRP (emit_insn (gen_init_fp (hard_frame_pointer_rtx,
7316 stack_pointer_rtx, sa_reg)));
7320 /* The ABIs for VMS and OSF/1 say that while we can schedule insns into
7321 the prologue, for exception handling reasons, we cannot do this for
7322 any insn that might fault. We could prevent this for mems with a
7323 (clobber:BLK (scratch)), but this doesn't work for fp insns. So we
7324 have to prevent all such scheduling with a blockage.
7326 Linux, on the other hand, never bothered to implement OSF/1's
7327 exception handling, and so doesn't care about such things. Anyone
7328 planning to use dwarf2 frame-unwind info can also omit the blockage. */
7330 if (! TARGET_CAN_FAULT_IN_PROLOGUE)
7331 emit_insn (gen_blockage ());
7334 /* Output the textual info surrounding the prologue. */
7337 alpha_start_function (FILE *file, const char *fnname,
7338 tree decl ATTRIBUTE_UNUSED)
7340 unsigned long imask = 0;
7341 unsigned long fmask = 0;
7342 /* Stack space needed for pushing registers clobbered by us. */
7343 HOST_WIDE_INT sa_size;
7344 /* Complete stack size needed. */
7345 unsigned HOST_WIDE_INT frame_size;
7346 /* Offset from base reg to register save area. */
7347 HOST_WIDE_INT reg_offset;
7348 char *entry_label = (char *) alloca (strlen (fnname) + 6);
7351 /* Don't emit an extern directive for functions defined in the same file. */
7352 if (TARGET_ABI_UNICOSMK)
7355 name_tree = get_identifier (fnname);
7356 TREE_ASM_WRITTEN (name_tree) = 1;
7359 alpha_fnname = fnname;
7360 sa_size = alpha_sa_size ();
7362 frame_size = get_frame_size ();
7363 if (TARGET_ABI_OPEN_VMS)
7364 frame_size = ALPHA_ROUND (sa_size
7365 + (alpha_procedure_type == PT_STACK ? 8 : 0)
7367 + current_function_pretend_args_size);
7368 else if (TARGET_ABI_UNICOSMK)
7369 frame_size = ALPHA_ROUND (sa_size
7370 + (alpha_procedure_type == PT_STACK ? 48 : 0))
7371 + ALPHA_ROUND (frame_size
7372 + current_function_outgoing_args_size);
7374 frame_size = (ALPHA_ROUND (current_function_outgoing_args_size)
7376 + ALPHA_ROUND (frame_size
7377 + current_function_pretend_args_size));
7379 if (TARGET_ABI_OPEN_VMS)
7382 reg_offset = ALPHA_ROUND (current_function_outgoing_args_size);
7384 alpha_sa_mask (&imask, &fmask);
7386 /* Ecoff can handle multiple .file directives, so put out file and lineno.
7387 We have to do that before the .ent directive as we cannot switch
7388 files within procedures with native ecoff because line numbers are
7389 linked to procedure descriptors.
7390 Outputting the lineno helps debugging of one line functions as they
7391 would otherwise get no line number at all. Please note that we would
7392 like to put out last_linenum from final.c, but it is not accessible. */
7394 if (write_symbols == SDB_DEBUG)
7396 #ifdef ASM_OUTPUT_SOURCE_FILENAME
7397 ASM_OUTPUT_SOURCE_FILENAME (file,
7398 DECL_SOURCE_FILE (current_function_decl));
7400 #ifdef ASM_OUTPUT_SOURCE_LINE
7401 if (debug_info_level != DINFO_LEVEL_TERSE)
7402 ASM_OUTPUT_SOURCE_LINE (file,
7403 DECL_SOURCE_LINE (current_function_decl), 0);
7407 /* Issue function start and label. */
7408 if (TARGET_ABI_OPEN_VMS
7409 || (!TARGET_ABI_UNICOSMK && !flag_inhibit_size_directive))
7411 fputs ("\t.ent ", file);
7412 assemble_name (file, fnname);
7415 /* If the function needs GP, we'll write the "..ng" label there.
7416 Otherwise, do it here. */
7418 && ! alpha_function_needs_gp
7419 && ! current_function_is_thunk)
7422 assemble_name (file, fnname);
7423 fputs ("..ng:\n", file);
7427 strcpy (entry_label, fnname);
7428 if (TARGET_ABI_OPEN_VMS)
7429 strcat (entry_label, "..en");
7431 /* For public functions, the label must be globalized by appending an
7432 additional colon. */
7433 if (TARGET_ABI_UNICOSMK && TREE_PUBLIC (decl))
7434 strcat (entry_label, ":");
7436 ASM_OUTPUT_LABEL (file, entry_label);
7437 inside_function = TRUE;
7439 if (TARGET_ABI_OPEN_VMS)
7440 fprintf (file, "\t.base $%d\n", vms_base_regno);
7442 if (!TARGET_ABI_OPEN_VMS && !TARGET_ABI_UNICOSMK && TARGET_IEEE_CONFORMANT
7443 && !flag_inhibit_size_directive)
7445 /* Set flags in procedure descriptor to request IEEE-conformant
7446 math-library routines. The value we set it to is PDSC_EXC_IEEE
7447 (/usr/include/pdsc.h). */
7448 fputs ("\t.eflag 48\n", file);
7451 /* Set up offsets to alpha virtual arg/local debugging pointer. */
7452 alpha_auto_offset = -frame_size + current_function_pretend_args_size;
7453 alpha_arg_offset = -frame_size + 48;
7455 /* Describe our frame. If the frame size is larger than an integer,
7456 print it as zero to avoid an assembler error. We won't be
7457 properly describing such a frame, but that's the best we can do. */
7458 if (TARGET_ABI_UNICOSMK)
7460 else if (TARGET_ABI_OPEN_VMS)
7461 fprintf (file, "\t.frame $%d," HOST_WIDE_INT_PRINT_DEC ",$26,"
7462 HOST_WIDE_INT_PRINT_DEC "\n",
7464 frame_size >= (1UL << 31) ? 0 : frame_size,
7466 else if (!flag_inhibit_size_directive)
7467 fprintf (file, "\t.frame $%d," HOST_WIDE_INT_PRINT_DEC ",$26,%d\n",
7468 (frame_pointer_needed
7469 ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM),
7470 frame_size >= (1UL << 31) ? 0 : frame_size,
7471 current_function_pretend_args_size);
7473 /* Describe which registers were spilled. */
7474 if (TARGET_ABI_UNICOSMK)
7476 else if (TARGET_ABI_OPEN_VMS)
7479 /* ??? Does VMS care if mask contains ra? The old code didn't
7480 set it, so I don't here. */
7481 fprintf (file, "\t.mask 0x%lx,0\n", imask & ~(1UL << REG_RA));
7483 fprintf (file, "\t.fmask 0x%lx,0\n", fmask);
7484 if (alpha_procedure_type == PT_REGISTER)
7485 fprintf (file, "\t.fp_save $%d\n", vms_save_fp_regno);
7487 else if (!flag_inhibit_size_directive)
7491 fprintf (file, "\t.mask 0x%lx," HOST_WIDE_INT_PRINT_DEC "\n", imask,
7492 frame_size >= (1UL << 31) ? 0 : reg_offset - frame_size);
7494 for (i = 0; i < 32; ++i)
7495 if (imask & (1UL << i))
7500 fprintf (file, "\t.fmask 0x%lx," HOST_WIDE_INT_PRINT_DEC "\n", fmask,
7501 frame_size >= (1UL << 31) ? 0 : reg_offset - frame_size);
7504 #if TARGET_ABI_OPEN_VMS
7505 /* Ifdef'ed cause link_section are only available then. */
7506 readonly_data_section ();
7507 fprintf (file, "\t.align 3\n");
7508 assemble_name (file, fnname); fputs ("..na:\n", file);
7509 fputs ("\t.ascii \"", file);
7510 assemble_name (file, fnname);
7511 fputs ("\\0\"\n", file);
7512 alpha_need_linkage (fnname, 1);
7517 /* Emit the .prologue note at the scheduled end of the prologue. */
7520 alpha_output_function_end_prologue (FILE *file)
7522 if (TARGET_ABI_UNICOSMK)
7524 else if (TARGET_ABI_OPEN_VMS)
7525 fputs ("\t.prologue\n", file);
7526 else if (TARGET_ABI_WINDOWS_NT)
7527 fputs ("\t.prologue 0\n", file);
7528 else if (!flag_inhibit_size_directive)
7529 fprintf (file, "\t.prologue %d\n",
7530 alpha_function_needs_gp || current_function_is_thunk);
7533 /* Write function epilogue. */
7535 /* ??? At some point we will want to support full unwind, and so will
7536 need to mark the epilogue as well. At the moment, we just confuse
7539 #define FRP(exp) exp
7542 alpha_expand_epilogue (void)
7544 /* Registers to save. */
7545 unsigned long imask = 0;
7546 unsigned long fmask = 0;
7547 /* Stack space needed for pushing registers clobbered by us. */
7548 HOST_WIDE_INT sa_size;
7549 /* Complete stack size needed. */
7550 HOST_WIDE_INT frame_size;
7551 /* Offset from base reg to register save area. */
7552 HOST_WIDE_INT reg_offset;
7553 int fp_is_frame_pointer, fp_offset;
7554 rtx sa_reg, sa_reg_exp = NULL;
7555 rtx sp_adj1, sp_adj2, mem;
7559 sa_size = alpha_sa_size ();
7561 frame_size = get_frame_size ();
7562 if (TARGET_ABI_OPEN_VMS)
7563 frame_size = ALPHA_ROUND (sa_size
7564 + (alpha_procedure_type == PT_STACK ? 8 : 0)
7566 + current_function_pretend_args_size);
7567 else if (TARGET_ABI_UNICOSMK)
7568 frame_size = ALPHA_ROUND (sa_size
7569 + (alpha_procedure_type == PT_STACK ? 48 : 0))
7570 + ALPHA_ROUND (frame_size
7571 + current_function_outgoing_args_size);
7573 frame_size = (ALPHA_ROUND (current_function_outgoing_args_size)
7575 + ALPHA_ROUND (frame_size
7576 + current_function_pretend_args_size));
7578 if (TARGET_ABI_OPEN_VMS)
7580 if (alpha_procedure_type == PT_STACK)
7586 reg_offset = ALPHA_ROUND (current_function_outgoing_args_size);
7588 alpha_sa_mask (&imask, &fmask);
7591 = ((TARGET_ABI_OPEN_VMS && alpha_procedure_type == PT_STACK)
7592 || (!TARGET_ABI_OPEN_VMS && frame_pointer_needed));
7594 sa_reg = stack_pointer_rtx;
7596 if (current_function_calls_eh_return)
7597 eh_ofs = EH_RETURN_STACKADJ_RTX;
7601 if (!TARGET_ABI_UNICOSMK && sa_size)
7603 /* If we have a frame pointer, restore SP from it. */
7604 if ((TARGET_ABI_OPEN_VMS
7605 && vms_unwind_regno == HARD_FRAME_POINTER_REGNUM)
7606 || (!TARGET_ABI_OPEN_VMS && frame_pointer_needed))
7607 FRP (emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx));
7609 /* Cope with very large offsets to the register save area. */
7610 if (reg_offset + sa_size > 0x8000)
7612 int low = ((reg_offset & 0xffff) ^ 0x8000) - 0x8000;
7615 if (low + sa_size <= 0x8000)
7616 bias = reg_offset - low, reg_offset = low;
7618 bias = reg_offset, reg_offset = 0;
7620 sa_reg = gen_rtx_REG (DImode, 22);
7621 sa_reg_exp = plus_constant (stack_pointer_rtx, bias);
7623 FRP (emit_move_insn (sa_reg, sa_reg_exp));
7626 /* Restore registers in order, excepting a true frame pointer. */
7628 mem = gen_rtx_MEM (DImode, plus_constant (sa_reg, reg_offset));
7630 set_mem_alias_set (mem, alpha_sr_alias_set);
7631 FRP (emit_move_insn (gen_rtx_REG (DImode, REG_RA), mem));
7634 imask &= ~(1UL << REG_RA);
7636 for (i = 0; i < 31; ++i)
7637 if (imask & (1UL << i))
7639 if (i == HARD_FRAME_POINTER_REGNUM && fp_is_frame_pointer)
7640 fp_offset = reg_offset;
7643 mem = gen_rtx_MEM (DImode, plus_constant(sa_reg, reg_offset));
7644 set_mem_alias_set (mem, alpha_sr_alias_set);
7645 FRP (emit_move_insn (gen_rtx_REG (DImode, i), mem));
7650 if (imask & (1UL << 31))
7653 for (i = 0; i < 31; ++i)
7654 if (fmask & (1UL << i))
7656 mem = gen_rtx_MEM (DFmode, plus_constant(sa_reg, reg_offset));
7657 set_mem_alias_set (mem, alpha_sr_alias_set);
7658 FRP (emit_move_insn (gen_rtx_REG (DFmode, i+32), mem));
7662 else if (TARGET_ABI_UNICOSMK && alpha_procedure_type == PT_STACK)
7664 /* Restore callee-saved general-purpose registers. */
7668 for (i = 9; i < 15; i++)
7669 if (imask & (1UL << i))
7671 mem = gen_rtx_MEM (DImode, plus_constant(hard_frame_pointer_rtx,
7673 set_mem_alias_set (mem, alpha_sr_alias_set);
7674 FRP (emit_move_insn (gen_rtx_REG (DImode, i), mem));
7678 for (i = 2; i < 10; i++)
7679 if (fmask & (1UL << i))
7681 mem = gen_rtx_MEM (DFmode, plus_constant(hard_frame_pointer_rtx,
7683 set_mem_alias_set (mem, alpha_sr_alias_set);
7684 FRP (emit_move_insn (gen_rtx_REG (DFmode, i+32), mem));
7688 /* Restore the return address from the DSIB. */
7690 mem = gen_rtx_MEM (DImode, plus_constant(hard_frame_pointer_rtx, -8));
7691 set_mem_alias_set (mem, alpha_sr_alias_set);
7692 FRP (emit_move_insn (gen_rtx_REG (DImode, REG_RA), mem));
7695 if (frame_size || eh_ofs)
7697 sp_adj1 = stack_pointer_rtx;
7701 sp_adj1 = gen_rtx_REG (DImode, 23);
7702 emit_move_insn (sp_adj1,
7703 gen_rtx_PLUS (Pmode, stack_pointer_rtx, eh_ofs));
7706 /* If the stack size is large, begin computation into a temporary
7707 register so as not to interfere with a potential fp restore,
7708 which must be consecutive with an SP restore. */
7709 if (frame_size < 32768
7710 && ! (TARGET_ABI_UNICOSMK && current_function_calls_alloca))
7711 sp_adj2 = GEN_INT (frame_size);
7712 else if (TARGET_ABI_UNICOSMK)
7714 sp_adj1 = gen_rtx_REG (DImode, 23);
7715 FRP (emit_move_insn (sp_adj1, hard_frame_pointer_rtx));
7716 sp_adj2 = const0_rtx;
7718 else if (frame_size < 0x40007fffL)
7720 int low = ((frame_size & 0xffff) ^ 0x8000) - 0x8000;
7722 sp_adj2 = plus_constant (sp_adj1, frame_size - low);
7723 if (sa_reg_exp && rtx_equal_p (sa_reg_exp, sp_adj2))
7727 sp_adj1 = gen_rtx_REG (DImode, 23);
7728 FRP (emit_move_insn (sp_adj1, sp_adj2));
7730 sp_adj2 = GEN_INT (low);
7734 rtx tmp = gen_rtx_REG (DImode, 23);
7735 FRP (sp_adj2 = alpha_emit_set_const (tmp, DImode, frame_size, 3));
7738 /* We can't drop new things to memory this late, afaik,
7739 so build it up by pieces. */
7740 FRP (sp_adj2 = alpha_emit_set_long_const (tmp, frame_size,
7741 -(frame_size < 0)));
7747 /* From now on, things must be in order. So emit blockages. */
7749 /* Restore the frame pointer. */
7750 if (TARGET_ABI_UNICOSMK)
7752 emit_insn (gen_blockage ());
7753 mem = gen_rtx_MEM (DImode,
7754 plus_constant (hard_frame_pointer_rtx, -16));
7755 set_mem_alias_set (mem, alpha_sr_alias_set);
7756 FRP (emit_move_insn (hard_frame_pointer_rtx, mem));
7758 else if (fp_is_frame_pointer)
7760 emit_insn (gen_blockage ());
7761 mem = gen_rtx_MEM (DImode, plus_constant (sa_reg, fp_offset));
7762 set_mem_alias_set (mem, alpha_sr_alias_set);
7763 FRP (emit_move_insn (hard_frame_pointer_rtx, mem));
7765 else if (TARGET_ABI_OPEN_VMS)
7767 emit_insn (gen_blockage ());
7768 FRP (emit_move_insn (hard_frame_pointer_rtx,
7769 gen_rtx_REG (DImode, vms_save_fp_regno)));
7772 /* Restore the stack pointer. */
7773 emit_insn (gen_blockage ());
7774 if (sp_adj2 == const0_rtx)
7775 FRP (emit_move_insn (stack_pointer_rtx, sp_adj1));
7777 FRP (emit_move_insn (stack_pointer_rtx,
7778 gen_rtx_PLUS (DImode, sp_adj1, sp_adj2)));
7782 if (TARGET_ABI_OPEN_VMS && alpha_procedure_type == PT_REGISTER)
7784 emit_insn (gen_blockage ());
7785 FRP (emit_move_insn (hard_frame_pointer_rtx,
7786 gen_rtx_REG (DImode, vms_save_fp_regno)));
7788 else if (TARGET_ABI_UNICOSMK && alpha_procedure_type != PT_STACK)
7790 /* Decrement the frame pointer if the function does not have a
7793 emit_insn (gen_blockage ());
7794 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
7795 hard_frame_pointer_rtx, constm1_rtx)));
7800 /* Output the rest of the textual info surrounding the epilogue. */
7803 alpha_end_function (FILE *file, const char *fnname, tree decl ATTRIBUTE_UNUSED)
7805 #if TARGET_ABI_OPEN_VMS
7806 alpha_write_linkage (file, fnname, decl);
7809 /* End the function. */
7810 if (!TARGET_ABI_UNICOSMK && !flag_inhibit_size_directive)
7812 fputs ("\t.end ", file);
7813 assemble_name (file, fnname);
7816 inside_function = FALSE;
7818 /* Output jump tables and the static subroutine information block. */
7819 if (TARGET_ABI_UNICOSMK)
7821 unicosmk_output_ssib (file, fnname);
7822 unicosmk_output_deferred_case_vectors (file);
7827 /* Emit a tail call to FUNCTION after adjusting THIS by DELTA.
7829 In order to avoid the hordes of differences between generated code
7830 with and without TARGET_EXPLICIT_RELOCS, and to avoid duplicating
7831 lots of code loading up large constants, generate rtl and emit it
7832 instead of going straight to text.
7834 Not sure why this idea hasn't been explored before... */
7837 alpha_output_mi_thunk_osf (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
7838 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
7841 HOST_WIDE_INT hi, lo;
7842 rtx this, insn, funexp;
7844 reset_block_changes ();
7846 /* We always require a valid GP. */
7847 emit_insn (gen_prologue_ldgp ());
7848 emit_note (NOTE_INSN_PROLOGUE_END);
7850 /* Find the "this" pointer. If the function returns a structure,
7851 the structure return pointer is in $16. */
7852 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
7853 this = gen_rtx_REG (Pmode, 17);
7855 this = gen_rtx_REG (Pmode, 16);
7857 /* Add DELTA. When possible we use ldah+lda. Otherwise load the
7858 entire constant for the add. */
7859 lo = ((delta & 0xffff) ^ 0x8000) - 0x8000;
7860 hi = (((delta - lo) & 0xffffffff) ^ 0x80000000) - 0x80000000;
7861 if (hi + lo == delta)
7864 emit_insn (gen_adddi3 (this, this, GEN_INT (hi)));
7866 emit_insn (gen_adddi3 (this, this, GEN_INT (lo)));
7870 rtx tmp = alpha_emit_set_long_const (gen_rtx_REG (Pmode, 0),
7871 delta, -(delta < 0));
7872 emit_insn (gen_adddi3 (this, this, tmp));
7875 /* Add a delta stored in the vtable at VCALL_OFFSET. */
7880 tmp = gen_rtx_REG (Pmode, 0);
7881 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this));
7883 lo = ((vcall_offset & 0xffff) ^ 0x8000) - 0x8000;
7884 hi = (((vcall_offset - lo) & 0xffffffff) ^ 0x80000000) - 0x80000000;
7885 if (hi + lo == vcall_offset)
7888 emit_insn (gen_adddi3 (tmp, tmp, GEN_INT (hi)));
7892 tmp2 = alpha_emit_set_long_const (gen_rtx_REG (Pmode, 1),
7893 vcall_offset, -(vcall_offset < 0));
7894 emit_insn (gen_adddi3 (tmp, tmp, tmp2));
7898 tmp2 = gen_rtx_PLUS (Pmode, tmp, GEN_INT (lo));
7901 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp2));
7903 emit_insn (gen_adddi3 (this, this, tmp));
7906 /* Generate a tail call to the target function. */
7907 if (! TREE_USED (function))
7909 assemble_external (function);
7910 TREE_USED (function) = 1;
7912 funexp = XEXP (DECL_RTL (function), 0);
7913 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
7914 insn = emit_call_insn (gen_sibcall (funexp, const0_rtx));
7915 SIBLING_CALL_P (insn) = 1;
7917 /* Run just enough of rest_of_compilation to get the insns emitted.
7918 There's not really enough bulk here to make other passes such as
7919 instruction scheduling worth while. Note that use_thunk calls
7920 assemble_start_function and assemble_end_function. */
7921 insn = get_insns ();
7922 insn_locators_initialize ();
7923 shorten_branches (insn);
7924 final_start_function (insn, file, 1);
7925 final (insn, file, 1, 0);
7926 final_end_function ();
7928 #endif /* TARGET_ABI_OSF */
7930 /* Debugging support. */
7934 /* Count the number of sdb related labels are generated (to find block
7935 start and end boundaries). */
7937 int sdb_label_count = 0;
7939 /* Next label # for each statement. */
7941 static int sym_lineno = 0;
7943 /* Count the number of .file directives, so that .loc is up to date. */
7945 static int num_source_filenames = 0;
7947 /* Name of the file containing the current function. */
7949 static const char *current_function_file = "";
7951 /* Offsets to alpha virtual arg/local debugging pointers. */
7953 long alpha_arg_offset;
7954 long alpha_auto_offset;
7956 /* Emit a new filename to a stream. */
7959 alpha_output_filename (FILE *stream, const char *name)
7961 static int first_time = TRUE;
7962 char ltext_label_name[100];
7967 ++num_source_filenames;
7968 current_function_file = name;
7969 fprintf (stream, "\t.file\t%d ", num_source_filenames);
7970 output_quoted_string (stream, name);
7971 fprintf (stream, "\n");
7972 if (!TARGET_GAS && write_symbols == DBX_DEBUG)
7973 fprintf (stream, "\t#@stabs\n");
7976 else if (write_symbols == DBX_DEBUG)
7978 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name, "Ltext", 0);
7979 fprintf (stream, "%s", ASM_STABS_OP);
7980 output_quoted_string (stream, name);
7981 fprintf (stream, ",%d,0,0,%s\n", N_SOL, <ext_label_name[1]);
7984 else if (name != current_function_file
7985 && strcmp (name, current_function_file) != 0)
7987 if (inside_function && ! TARGET_GAS)
7988 fprintf (stream, "\t#.file\t%d ", num_source_filenames);
7991 ++num_source_filenames;
7992 current_function_file = name;
7993 fprintf (stream, "\t.file\t%d ", num_source_filenames);
7996 output_quoted_string (stream, name);
7997 fprintf (stream, "\n");
8001 /* Emit a linenumber to a stream. */
8004 alpha_output_lineno (FILE *stream, int line)
8006 if (write_symbols == DBX_DEBUG)
8008 /* mips-tfile doesn't understand .stabd directives. */
8010 fprintf (stream, "$LM%d:\n%s%d,0,%d,$LM%d\n",
8011 sym_lineno, ASM_STABN_OP, N_SLINE, line, sym_lineno);
8014 fprintf (stream, "\n\t.loc\t%d %d\n", num_source_filenames, line);
8017 /* Structure to show the current status of registers and memory. */
8019 struct shadow_summary
8022 unsigned int i : 31; /* Mask of int regs */
8023 unsigned int fp : 31; /* Mask of fp regs */
8024 unsigned int mem : 1; /* mem == imem | fpmem */
8028 /* Summary the effects of expression X on the machine. Update SUM, a pointer
8029 to the summary structure. SET is nonzero if the insn is setting the
8030 object, otherwise zero. */
8033 summarize_insn (rtx x, struct shadow_summary *sum, int set)
8035 const char *format_ptr;
8041 switch (GET_CODE (x))
8043 /* ??? Note that this case would be incorrect if the Alpha had a
8044 ZERO_EXTRACT in SET_DEST. */
8046 summarize_insn (SET_SRC (x), sum, 0);
8047 summarize_insn (SET_DEST (x), sum, 1);
8051 summarize_insn (XEXP (x, 0), sum, 1);
8055 summarize_insn (XEXP (x, 0), sum, 0);
8059 for (i = ASM_OPERANDS_INPUT_LENGTH (x) - 1; i >= 0; i--)
8060 summarize_insn (ASM_OPERANDS_INPUT (x, i), sum, 0);
8064 for (i = XVECLEN (x, 0) - 1; i >= 0; i--)
8065 summarize_insn (XVECEXP (x, 0, i), sum, 0);
8069 summarize_insn (SUBREG_REG (x), sum, 0);
8074 int regno = REGNO (x);
8075 unsigned long mask = ((unsigned long) 1) << (regno % 32);
8077 if (regno == 31 || regno == 63)
8083 sum->defd.i |= mask;
8085 sum->defd.fp |= mask;
8090 sum->used.i |= mask;
8092 sum->used.fp |= mask;
8103 /* Find the regs used in memory address computation: */
8104 summarize_insn (XEXP (x, 0), sum, 0);
8107 case CONST_INT: case CONST_DOUBLE:
8108 case SYMBOL_REF: case LABEL_REF: case CONST:
8109 case SCRATCH: case ASM_INPUT:
8112 /* Handle common unary and binary ops for efficiency. */
8113 case COMPARE: case PLUS: case MINUS: case MULT: case DIV:
8114 case MOD: case UDIV: case UMOD: case AND: case IOR:
8115 case XOR: case ASHIFT: case ROTATE: case ASHIFTRT: case LSHIFTRT:
8116 case ROTATERT: case SMIN: case SMAX: case UMIN: case UMAX:
8117 case NE: case EQ: case GE: case GT: case LE:
8118 case LT: case GEU: case GTU: case LEU: case LTU:
8119 summarize_insn (XEXP (x, 0), sum, 0);
8120 summarize_insn (XEXP (x, 1), sum, 0);
8123 case NEG: case NOT: case SIGN_EXTEND: case ZERO_EXTEND:
8124 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: case FLOAT:
8125 case FIX: case UNSIGNED_FLOAT: case UNSIGNED_FIX: case ABS:
8126 case SQRT: case FFS:
8127 summarize_insn (XEXP (x, 0), sum, 0);
8131 format_ptr = GET_RTX_FORMAT (GET_CODE (x));
8132 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
8133 switch (format_ptr[i])
8136 summarize_insn (XEXP (x, i), sum, 0);
8140 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8141 summarize_insn (XVECEXP (x, i, j), sum, 0);
8153 /* Ensure a sufficient number of `trapb' insns are in the code when
8154 the user requests code with a trap precision of functions or
8157 In naive mode, when the user requests a trap-precision of
8158 "instruction", a trapb is needed after every instruction that may
8159 generate a trap. This ensures that the code is resumption safe but
8162 When optimizations are turned on, we delay issuing a trapb as long
8163 as possible. In this context, a trap shadow is the sequence of
8164 instructions that starts with a (potentially) trap generating
8165 instruction and extends to the next trapb or call_pal instruction
8166 (but GCC never generates call_pal by itself). We can delay (and
8167 therefore sometimes omit) a trapb subject to the following
8170 (a) On entry to the trap shadow, if any Alpha register or memory
8171 location contains a value that is used as an operand value by some
8172 instruction in the trap shadow (live on entry), then no instruction
8173 in the trap shadow may modify the register or memory location.
8175 (b) Within the trap shadow, the computation of the base register
8176 for a memory load or store instruction may not involve using the
8177 result of an instruction that might generate an UNPREDICTABLE
8180 (c) Within the trap shadow, no register may be used more than once
8181 as a destination register. (This is to make life easier for the
8184 (d) The trap shadow may not include any branch instructions. */
8187 alpha_handle_trap_shadows (void)
8189 struct shadow_summary shadow;
8190 int trap_pending, exception_nesting;
8194 exception_nesting = 0;
8197 shadow.used.mem = 0;
8198 shadow.defd = shadow.used;
8200 for (i = get_insns (); i ; i = NEXT_INSN (i))
8202 if (GET_CODE (i) == NOTE)
8204 switch (NOTE_LINE_NUMBER (i))
8206 case NOTE_INSN_EH_REGION_BEG:
8207 exception_nesting++;
8212 case NOTE_INSN_EH_REGION_END:
8213 exception_nesting--;
8218 case NOTE_INSN_EPILOGUE_BEG:
8219 if (trap_pending && alpha_tp >= ALPHA_TP_FUNC)
8224 else if (trap_pending)
8226 if (alpha_tp == ALPHA_TP_FUNC)
8228 if (GET_CODE (i) == JUMP_INSN
8229 && GET_CODE (PATTERN (i)) == RETURN)
8232 else if (alpha_tp == ALPHA_TP_INSN)
8236 struct shadow_summary sum;
8241 sum.defd = sum.used;
8243 switch (GET_CODE (i))
8246 /* Annoyingly, get_attr_trap will abort on these. */
8247 if (GET_CODE (PATTERN (i)) == USE
8248 || GET_CODE (PATTERN (i)) == CLOBBER)
8251 summarize_insn (PATTERN (i), &sum, 0);
8253 if ((sum.defd.i & shadow.defd.i)
8254 || (sum.defd.fp & shadow.defd.fp))
8256 /* (c) would be violated */
8260 /* Combine shadow with summary of current insn: */
8261 shadow.used.i |= sum.used.i;
8262 shadow.used.fp |= sum.used.fp;
8263 shadow.used.mem |= sum.used.mem;
8264 shadow.defd.i |= sum.defd.i;
8265 shadow.defd.fp |= sum.defd.fp;
8266 shadow.defd.mem |= sum.defd.mem;
8268 if ((sum.defd.i & shadow.used.i)
8269 || (sum.defd.fp & shadow.used.fp)
8270 || (sum.defd.mem & shadow.used.mem))
8272 /* (a) would be violated (also takes care of (b)) */
8273 if (get_attr_trap (i) == TRAP_YES
8274 && ((sum.defd.i & sum.used.i)
8275 || (sum.defd.fp & sum.used.fp)))
8294 n = emit_insn_before (gen_trapb (), i);
8295 PUT_MODE (n, TImode);
8296 PUT_MODE (i, TImode);
8300 shadow.used.mem = 0;
8301 shadow.defd = shadow.used;
8306 if ((exception_nesting > 0 || alpha_tp >= ALPHA_TP_FUNC)
8307 && GET_CODE (i) == INSN
8308 && GET_CODE (PATTERN (i)) != USE
8309 && GET_CODE (PATTERN (i)) != CLOBBER
8310 && get_attr_trap (i) == TRAP_YES)
8312 if (optimize && !trap_pending)
8313 summarize_insn (PATTERN (i), &shadow, 0);
8319 /* Alpha can only issue instruction groups simultaneously if they are
8320 suitably aligned. This is very processor-specific. */
8322 enum alphaev4_pipe {
8329 enum alphaev5_pipe {
8340 static enum alphaev4_pipe
8341 alphaev4_insn_pipe (rtx insn)
8343 if (recog_memoized (insn) < 0)
8345 if (get_attr_length (insn) != 4)
8348 switch (get_attr_type (insn))
8382 static enum alphaev5_pipe
8383 alphaev5_insn_pipe (rtx insn)
8385 if (recog_memoized (insn) < 0)
8387 if (get_attr_length (insn) != 4)
8390 switch (get_attr_type (insn))
8431 /* IN_USE is a mask of the slots currently filled within the insn group.
8432 The mask bits come from alphaev4_pipe above. If EV4_IBX is set, then
8433 the insn in EV4_IB0 can be swapped by the hardware into EV4_IB1.
8435 LEN is, of course, the length of the group in bytes. */
8438 alphaev4_next_group (rtx insn, int *pin_use, int *plen)
8445 || GET_CODE (PATTERN (insn)) == CLOBBER
8446 || GET_CODE (PATTERN (insn)) == USE)
8451 enum alphaev4_pipe pipe;
8453 pipe = alphaev4_insn_pipe (insn);
8457 /* Force complex instructions to start new groups. */
8461 /* If this is a completely unrecognized insn, its an asm.
8462 We don't know how long it is, so record length as -1 to
8463 signal a needed realignment. */
8464 if (recog_memoized (insn) < 0)
8467 len = get_attr_length (insn);
8471 if (in_use & EV4_IB0)
8473 if (in_use & EV4_IB1)
8478 in_use |= EV4_IB0 | EV4_IBX;
8482 if (in_use & EV4_IB0)
8484 if (!(in_use & EV4_IBX) || (in_use & EV4_IB1))
8492 if (in_use & EV4_IB1)
8502 /* Haifa doesn't do well scheduling branches. */
8503 if (GET_CODE (insn) == JUMP_INSN)
8507 insn = next_nonnote_insn (insn);
8509 if (!insn || ! INSN_P (insn))
8512 /* Let Haifa tell us where it thinks insn group boundaries are. */
8513 if (GET_MODE (insn) == TImode)
8516 if (GET_CODE (insn) == CLOBBER || GET_CODE (insn) == USE)
8521 insn = next_nonnote_insn (insn);
8529 /* IN_USE is a mask of the slots currently filled within the insn group.
8530 The mask bits come from alphaev5_pipe above. If EV5_E01 is set, then
8531 the insn in EV5_E0 can be swapped by the hardware into EV5_E1.
8533 LEN is, of course, the length of the group in bytes. */
8536 alphaev5_next_group (rtx insn, int *pin_use, int *plen)
8543 || GET_CODE (PATTERN (insn)) == CLOBBER
8544 || GET_CODE (PATTERN (insn)) == USE)
8549 enum alphaev5_pipe pipe;
8551 pipe = alphaev5_insn_pipe (insn);
8555 /* Force complex instructions to start new groups. */
8559 /* If this is a completely unrecognized insn, its an asm.
8560 We don't know how long it is, so record length as -1 to
8561 signal a needed realignment. */
8562 if (recog_memoized (insn) < 0)
8565 len = get_attr_length (insn);
8568 /* ??? Most of the places below, we would like to abort, as
8569 it would indicate an error either in Haifa, or in the
8570 scheduling description. Unfortunately, Haifa never
8571 schedules the last instruction of the BB, so we don't
8572 have an accurate TI bit to go off. */
8574 if (in_use & EV5_E0)
8576 if (in_use & EV5_E1)
8581 in_use |= EV5_E0 | EV5_E01;
8585 if (in_use & EV5_E0)
8587 if (!(in_use & EV5_E01) || (in_use & EV5_E1))
8595 if (in_use & EV5_E1)
8601 if (in_use & EV5_FA)
8603 if (in_use & EV5_FM)
8608 in_use |= EV5_FA | EV5_FAM;
8612 if (in_use & EV5_FA)
8618 if (in_use & EV5_FM)
8631 /* Haifa doesn't do well scheduling branches. */
8632 /* ??? If this is predicted not-taken, slotting continues, except
8633 that no more IBR, FBR, or JSR insns may be slotted. */
8634 if (GET_CODE (insn) == JUMP_INSN)
8638 insn = next_nonnote_insn (insn);
8640 if (!insn || ! INSN_P (insn))
8643 /* Let Haifa tell us where it thinks insn group boundaries are. */
8644 if (GET_MODE (insn) == TImode)
8647 if (GET_CODE (insn) == CLOBBER || GET_CODE (insn) == USE)
8652 insn = next_nonnote_insn (insn);
8661 alphaev4_next_nop (int *pin_use)
8663 int in_use = *pin_use;
8666 if (!(in_use & EV4_IB0))
8671 else if ((in_use & (EV4_IBX|EV4_IB1)) == EV4_IBX)
8676 else if (TARGET_FP && !(in_use & EV4_IB1))
8689 alphaev5_next_nop (int *pin_use)
8691 int in_use = *pin_use;
8694 if (!(in_use & EV5_E1))
8699 else if (TARGET_FP && !(in_use & EV5_FA))
8704 else if (TARGET_FP && !(in_use & EV5_FM))
8716 /* The instruction group alignment main loop. */
8719 alpha_align_insns (unsigned int max_align,
8720 rtx (*next_group) (rtx, int *, int *),
8721 rtx (*next_nop) (int *))
8723 /* ALIGN is the known alignment for the insn group. */
8725 /* OFS is the offset of the current insn in the insn group. */
8727 int prev_in_use, in_use, len;
8730 /* Let shorten branches care for assigning alignments to code labels. */
8731 shorten_branches (get_insns ());
8733 if (align_functions < 4)
8735 else if ((unsigned int) align_functions < max_align)
8736 align = align_functions;
8740 ofs = prev_in_use = 0;
8742 if (GET_CODE (i) == NOTE)
8743 i = next_nonnote_insn (i);
8747 next = (*next_group) (i, &in_use, &len);
8749 /* When we see a label, resync alignment etc. */
8750 if (GET_CODE (i) == CODE_LABEL)
8752 unsigned int new_align = 1 << label_to_alignment (i);
8754 if (new_align >= align)
8756 align = new_align < max_align ? new_align : max_align;
8760 else if (ofs & (new_align-1))
8761 ofs = (ofs | (new_align-1)) + 1;
8766 /* Handle complex instructions special. */
8767 else if (in_use == 0)
8769 /* Asms will have length < 0. This is a signal that we have
8770 lost alignment knowledge. Assume, however, that the asm
8771 will not mis-align instructions. */
8780 /* If the known alignment is smaller than the recognized insn group,
8781 realign the output. */
8782 else if ((int) align < len)
8784 unsigned int new_log_align = len > 8 ? 4 : 3;
8787 where = prev = prev_nonnote_insn (i);
8788 if (!where || GET_CODE (where) != CODE_LABEL)
8791 /* Can't realign between a call and its gp reload. */
8792 if (! (TARGET_EXPLICIT_RELOCS
8793 && prev && GET_CODE (prev) == CALL_INSN))
8795 emit_insn_before (gen_realign (GEN_INT (new_log_align)), where);
8796 align = 1 << new_log_align;
8801 /* If the group won't fit in the same INT16 as the previous,
8802 we need to add padding to keep the group together. Rather
8803 than simply leaving the insn filling to the assembler, we
8804 can make use of the knowledge of what sorts of instructions
8805 were issued in the previous group to make sure that all of
8806 the added nops are really free. */
8807 else if (ofs + len > (int) align)
8809 int nop_count = (align - ofs) / 4;
8812 /* Insert nops before labels, branches, and calls to truly merge
8813 the execution of the nops with the previous instruction group. */
8814 where = prev_nonnote_insn (i);
8817 if (GET_CODE (where) == CODE_LABEL)
8819 rtx where2 = prev_nonnote_insn (where);
8820 if (where2 && GET_CODE (where2) == JUMP_INSN)
8823 else if (GET_CODE (where) == INSN)
8830 emit_insn_before ((*next_nop)(&prev_in_use), where);
8831 while (--nop_count);
8835 ofs = (ofs + len) & (align - 1);
8836 prev_in_use = in_use;
8841 /* Machine dependent reorg pass. */
8846 if (alpha_tp != ALPHA_TP_PROG || flag_exceptions)
8847 alpha_handle_trap_shadows ();
8849 /* Due to the number of extra trapb insns, don't bother fixing up
8850 alignment when trap precision is instruction. Moreover, we can
8851 only do our job when sched2 is run. */
8852 if (optimize && !optimize_size
8853 && alpha_tp != ALPHA_TP_INSN
8854 && flag_schedule_insns_after_reload)
8856 if (alpha_cpu == PROCESSOR_EV4)
8857 alpha_align_insns (8, alphaev4_next_group, alphaev4_next_nop);
8858 else if (alpha_cpu == PROCESSOR_EV5)
8859 alpha_align_insns (16, alphaev5_next_group, alphaev5_next_nop);
8863 #if !TARGET_ABI_UNICOSMK
8870 alpha_file_start (void)
8872 #ifdef OBJECT_FORMAT_ELF
8873 /* If emitting dwarf2 debug information, we cannot generate a .file
8874 directive to start the file, as it will conflict with dwarf2out
8875 file numbers. So it's only useful when emitting mdebug output. */
8876 targetm.file_start_file_directive = (write_symbols == DBX_DEBUG);
8879 default_file_start ();
8881 fprintf (asm_out_file, "\t.verstamp %d %d\n", MS_STAMP, LS_STAMP);
8884 fputs ("\t.set noreorder\n", asm_out_file);
8885 fputs ("\t.set volatile\n", asm_out_file);
8886 if (!TARGET_ABI_OPEN_VMS)
8887 fputs ("\t.set noat\n", asm_out_file);
8888 if (TARGET_EXPLICIT_RELOCS)
8889 fputs ("\t.set nomacro\n", asm_out_file);
8890 if (TARGET_SUPPORT_ARCH | TARGET_BWX | TARGET_MAX | TARGET_FIX | TARGET_CIX)
8891 fprintf (asm_out_file,
8893 TARGET_CPU_EV6 ? "ev6"
8895 ? (TARGET_MAX ? "pca56" : TARGET_BWX ? "ev56" : "ev5")
8900 #ifdef OBJECT_FORMAT_ELF
8902 /* Switch to the section to which we should output X. The only thing
8903 special we do here is to honor small data. */
8906 alpha_elf_select_rtx_section (enum machine_mode mode, rtx x,
8907 unsigned HOST_WIDE_INT align)
8909 if (TARGET_SMALL_DATA && GET_MODE_SIZE (mode) <= g_switch_value)
8910 /* ??? Consider using mergeable sdata sections. */
8913 default_elf_select_rtx_section (mode, x, align);
8916 #endif /* OBJECT_FORMAT_ELF */
8918 /* Structure to collect function names for final output in link section. */
8919 /* Note that items marked with GTY can't be ifdef'ed out. */
8921 enum links_kind {KIND_UNUSED, KIND_LOCAL, KIND_EXTERN};
8922 enum reloc_kind {KIND_LINKAGE, KIND_CODEADDR};
8924 struct alpha_links GTY(())
8928 enum links_kind lkind;
8929 enum reloc_kind rkind;
8932 struct alpha_funcs GTY(())
8935 splay_tree GTY ((param1_is (char *), param2_is (struct alpha_links *)))
8939 static GTY ((param1_is (char *), param2_is (struct alpha_links *)))
8940 splay_tree alpha_links_tree;
8941 static GTY ((param1_is (tree), param2_is (struct alpha_funcs *)))
8942 splay_tree alpha_funcs_tree;
8944 static GTY(()) int alpha_funcs_num;
8946 #if TARGET_ABI_OPEN_VMS
8948 /* Return the VMS argument type corresponding to MODE. */
8951 alpha_arg_type (enum machine_mode mode)
8956 return TARGET_FLOAT_VAX ? FF : FS;
8958 return TARGET_FLOAT_VAX ? FD : FT;
8964 /* Return an rtx for an integer representing the VMS Argument Information
8968 alpha_arg_info_reg_val (CUMULATIVE_ARGS cum)
8970 unsigned HOST_WIDE_INT regval = cum.num_args;
8973 for (i = 0; i < 6; i++)
8974 regval |= ((int) cum.atypes[i]) << (i * 3 + 8);
8976 return GEN_INT (regval);
8979 /* Make (or fake) .linkage entry for function call.
8981 IS_LOCAL is 0 if name is used in call, 1 if name is used in definition.
8983 Return an SYMBOL_REF rtx for the linkage. */
8986 alpha_need_linkage (const char *name, int is_local)
8988 splay_tree_node node;
8989 struct alpha_links *al;
8996 struct alpha_funcs *cfaf;
8998 if (!alpha_funcs_tree)
8999 alpha_funcs_tree = splay_tree_new_ggc ((splay_tree_compare_fn)
9000 splay_tree_compare_pointers);
9002 cfaf = (struct alpha_funcs *) ggc_alloc (sizeof (struct alpha_funcs));
9005 cfaf->num = ++alpha_funcs_num;
9007 splay_tree_insert (alpha_funcs_tree,
9008 (splay_tree_key) current_function_decl,
9009 (splay_tree_value) cfaf);
9012 if (alpha_links_tree)
9014 /* Is this name already defined? */
9016 node = splay_tree_lookup (alpha_links_tree, (splay_tree_key) name);
9019 al = (struct alpha_links *) node->value;
9022 /* Defined here but external assumed. */
9023 if (al->lkind == KIND_EXTERN)
9024 al->lkind = KIND_LOCAL;
9028 /* Used here but unused assumed. */
9029 if (al->lkind == KIND_UNUSED)
9030 al->lkind = KIND_LOCAL;
9036 alpha_links_tree = splay_tree_new_ggc ((splay_tree_compare_fn) strcmp);
9038 al = (struct alpha_links *) ggc_alloc (sizeof (struct alpha_links));
9039 name = ggc_strdup (name);
9041 /* Assume external if no definition. */
9042 al->lkind = (is_local ? KIND_UNUSED : KIND_EXTERN);
9044 /* Ensure we have an IDENTIFIER so assemble_name can mark it used. */
9045 get_identifier (name);
9047 /* Construct a SYMBOL_REF for us to call. */
9049 size_t name_len = strlen (name);
9050 char *linksym = alloca (name_len + 6);
9052 memcpy (linksym + 1, name, name_len);
9053 memcpy (linksym + 1 + name_len, "..lk", 5);
9054 al->linkage = gen_rtx_SYMBOL_REF (Pmode,
9055 ggc_alloc_string (linksym, name_len + 5));
9058 splay_tree_insert (alpha_links_tree, (splay_tree_key) name,
9059 (splay_tree_value) al);
9065 alpha_use_linkage (rtx linkage, tree cfundecl, int lflag, int rflag)
9067 splay_tree_node cfunnode;
9068 struct alpha_funcs *cfaf;
9069 struct alpha_links *al;
9070 const char *name = XSTR (linkage, 0);
9072 cfaf = (struct alpha_funcs *) 0;
9073 al = (struct alpha_links *) 0;
9075 cfunnode = splay_tree_lookup (alpha_funcs_tree, (splay_tree_key) cfundecl);
9076 cfaf = (struct alpha_funcs *) cfunnode->value;
9080 splay_tree_node lnode;
9082 /* Is this name already defined? */
9084 lnode = splay_tree_lookup (cfaf->links, (splay_tree_key) name);
9086 al = (struct alpha_links *) lnode->value;
9089 cfaf->links = splay_tree_new_ggc ((splay_tree_compare_fn) strcmp);
9097 splay_tree_node node = 0;
9098 struct alpha_links *anl;
9103 name_len = strlen (name);
9105 al = (struct alpha_links *) ggc_alloc (sizeof (struct alpha_links));
9106 al->num = cfaf->num;
9108 node = splay_tree_lookup (alpha_links_tree, (splay_tree_key) name);
9111 anl = (struct alpha_links *) node->value;
9112 al->lkind = anl->lkind;
9115 sprintf (buf, "$%d..%s..lk", cfaf->num, name);
9116 buflen = strlen (buf);
9117 linksym = alloca (buflen + 1);
9118 memcpy (linksym, buf, buflen + 1);
9120 al->linkage = gen_rtx_SYMBOL_REF
9121 (Pmode, ggc_alloc_string (linksym, buflen + 1));
9123 splay_tree_insert (cfaf->links, (splay_tree_key) name,
9124 (splay_tree_value) al);
9128 al->rkind = KIND_CODEADDR;
9130 al->rkind = KIND_LINKAGE;
9133 return gen_rtx_MEM (Pmode, plus_constant (al->linkage, 8));
9139 alpha_write_one_linkage (splay_tree_node node, void *data)
9141 const char *const name = (const char *) node->key;
9142 struct alpha_links *link = (struct alpha_links *) node->value;
9143 FILE *stream = (FILE *) data;
9145 fprintf (stream, "$%d..%s..lk:\n", link->num, name);
9146 if (link->rkind == KIND_CODEADDR)
9148 if (link->lkind == KIND_LOCAL)
9150 /* Local and used */
9151 fprintf (stream, "\t.quad %s..en\n", name);
9155 /* External and used, request code address. */
9156 fprintf (stream, "\t.code_address %s\n", name);
9161 if (link->lkind == KIND_LOCAL)
9163 /* Local and used, build linkage pair. */
9164 fprintf (stream, "\t.quad %s..en\n", name);
9165 fprintf (stream, "\t.quad %s\n", name);
9169 /* External and used, request linkage pair. */
9170 fprintf (stream, "\t.linkage %s\n", name);
9178 alpha_write_linkage (FILE *stream, const char *funname, tree fundecl)
9180 splay_tree_node node;
9181 struct alpha_funcs *func;
9184 fprintf (stream, "\t.align 3\n");
9185 node = splay_tree_lookup (alpha_funcs_tree, (splay_tree_key) fundecl);
9186 func = (struct alpha_funcs *) node->value;
9188 fputs ("\t.name ", stream);
9189 assemble_name (stream, funname);
9190 fputs ("..na\n", stream);
9191 ASM_OUTPUT_LABEL (stream, funname);
9192 fprintf (stream, "\t.pdesc ");
9193 assemble_name (stream, funname);
9194 fprintf (stream, "..en,%s\n",
9195 alpha_procedure_type == PT_STACK ? "stack"
9196 : alpha_procedure_type == PT_REGISTER ? "reg" : "null");
9200 splay_tree_foreach (func->links, alpha_write_one_linkage, stream);
9201 /* splay_tree_delete (func->links); */
9205 /* Given a decl, a section name, and whether the decl initializer
9206 has relocs, choose attributes for the section. */
9208 #define SECTION_VMS_OVERLAY SECTION_FORGET
9209 #define SECTION_VMS_GLOBAL SECTION_MACH_DEP
9210 #define SECTION_VMS_INITIALIZE (SECTION_VMS_GLOBAL << 1)
9213 vms_section_type_flags (tree decl, const char *name, int reloc)
9215 unsigned int flags = default_section_type_flags (decl, name, reloc);
9217 if (decl && DECL_ATTRIBUTES (decl)
9218 && lookup_attribute ("overlaid", DECL_ATTRIBUTES (decl)))
9219 flags |= SECTION_VMS_OVERLAY;
9220 if (decl && DECL_ATTRIBUTES (decl)
9221 && lookup_attribute ("global", DECL_ATTRIBUTES (decl)))
9222 flags |= SECTION_VMS_GLOBAL;
9223 if (decl && DECL_ATTRIBUTES (decl)
9224 && lookup_attribute ("initialize", DECL_ATTRIBUTES (decl)))
9225 flags |= SECTION_VMS_INITIALIZE;
9230 /* Switch to an arbitrary section NAME with attributes as specified
9231 by FLAGS. ALIGN specifies any known alignment requirements for
9232 the section; 0 if the default should be used. */
9235 vms_asm_named_section (const char *name, unsigned int flags)
9237 fputc ('\n', asm_out_file);
9238 fprintf (asm_out_file, ".section\t%s", name);
9240 if (flags & SECTION_VMS_OVERLAY)
9241 fprintf (asm_out_file, ",OVR");
9242 if (flags & SECTION_VMS_GLOBAL)
9243 fprintf (asm_out_file, ",GBL");
9244 if (flags & SECTION_VMS_INITIALIZE)
9245 fprintf (asm_out_file, ",NOMOD");
9246 if (flags & SECTION_DEBUG)
9247 fprintf (asm_out_file, ",NOWRT");
9249 fputc ('\n', asm_out_file);
9252 /* Record an element in the table of global constructors. SYMBOL is
9253 a SYMBOL_REF of the function to be called; PRIORITY is a number
9254 between 0 and MAX_INIT_PRIORITY.
9256 Differs from default_ctors_section_asm_out_constructor in that the
9257 width of the .ctors entry is always 64 bits, rather than the 32 bits
9258 used by a normal pointer. */
9261 vms_asm_out_constructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
9264 assemble_align (BITS_PER_WORD);
9265 assemble_integer (symbol, UNITS_PER_WORD, BITS_PER_WORD, 1);
9269 vms_asm_out_destructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
9272 assemble_align (BITS_PER_WORD);
9273 assemble_integer (symbol, UNITS_PER_WORD, BITS_PER_WORD, 1);
9278 alpha_need_linkage (const char *name ATTRIBUTE_UNUSED,
9279 int is_local ATTRIBUTE_UNUSED)
9285 alpha_use_linkage (rtx linkage ATTRIBUTE_UNUSED,
9286 tree cfundecl ATTRIBUTE_UNUSED,
9287 int lflag ATTRIBUTE_UNUSED,
9288 int rflag ATTRIBUTE_UNUSED)
9293 #endif /* TARGET_ABI_OPEN_VMS */
9295 #if TARGET_ABI_UNICOSMK
9297 /* This evaluates to true if we do not know how to pass TYPE solely in
9298 registers. This is the case for all arguments that do not fit in two
9302 unicosmk_must_pass_in_stack (enum machine_mode mode, tree type)
9307 if (TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
9309 if (TREE_ADDRESSABLE (type))
9312 return ALPHA_ARG_SIZE (mode, type, 0) > 2;
9315 /* Define the offset between two registers, one to be eliminated, and the
9316 other its replacement, at the start of a routine. */
9319 unicosmk_initial_elimination_offset (int from, int to)
9323 fixed_size = alpha_sa_size();
9324 if (fixed_size != 0)
9327 if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
9329 else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
9331 else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
9332 return (ALPHA_ROUND (current_function_outgoing_args_size)
9333 + ALPHA_ROUND (get_frame_size()));
9334 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
9335 return (ALPHA_ROUND (fixed_size)
9336 + ALPHA_ROUND (get_frame_size()
9337 + current_function_outgoing_args_size));
9342 /* Output the module name for .ident and .end directives. We have to strip
9343 directories and add make sure that the module name starts with a letter
9347 unicosmk_output_module_name (FILE *file)
9349 const char *name = lbasename (main_input_filename);
9350 unsigned len = strlen (name);
9351 char *clean_name = alloca (len + 2);
9352 char *ptr = clean_name;
9354 /* CAM only accepts module names that start with a letter or '$'. We
9355 prefix the module name with a '$' if necessary. */
9357 if (!ISALPHA (*name))
9359 memcpy (ptr, name, len + 1);
9360 clean_symbol_name (clean_name);
9361 fputs (clean_name, file);
9364 /* Output the definition of a common variable. */
9367 unicosmk_output_common (FILE *file, const char *name, int size, int align)
9370 printf ("T3E__: common %s\n", name);
9373 fputs("\t.endp\n\n\t.psect ", file);
9374 assemble_name(file, name);
9375 fprintf(file, ",%d,common\n", floor_log2 (align / BITS_PER_UNIT));
9376 fprintf(file, "\t.byte\t0:%d\n", size);
9378 /* Mark the symbol as defined in this module. */
9379 name_tree = get_identifier (name);
9380 TREE_ASM_WRITTEN (name_tree) = 1;
9383 #define SECTION_PUBLIC SECTION_MACH_DEP
9384 #define SECTION_MAIN (SECTION_PUBLIC << 1)
9385 static int current_section_align;
9388 unicosmk_section_type_flags (tree decl, const char *name,
9389 int reloc ATTRIBUTE_UNUSED)
9391 unsigned int flags = default_section_type_flags (decl, name, reloc);
9396 if (TREE_CODE (decl) == FUNCTION_DECL)
9398 current_section_align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
9399 if (align_functions_log > current_section_align)
9400 current_section_align = align_functions_log;
9402 if (! strcmp (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl)), "main"))
9403 flags |= SECTION_MAIN;
9406 current_section_align = floor_log2 (DECL_ALIGN (decl) / BITS_PER_UNIT);
9408 if (TREE_PUBLIC (decl))
9409 flags |= SECTION_PUBLIC;
9414 /* Generate a section name for decl and associate it with the
9418 unicosmk_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
9426 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
9427 name = default_strip_name_encoding (name);
9428 len = strlen (name);
9430 if (TREE_CODE (decl) == FUNCTION_DECL)
9434 /* It is essential that we prefix the section name here because
9435 otherwise the section names generated for constructors and
9436 destructors confuse collect2. */
9438 string = alloca (len + 6);
9439 sprintf (string, "code@%s", name);
9440 DECL_SECTION_NAME (decl) = build_string (len + 5, string);
9442 else if (TREE_PUBLIC (decl))
9443 DECL_SECTION_NAME (decl) = build_string (len, name);
9448 string = alloca (len + 6);
9449 sprintf (string, "data@%s", name);
9450 DECL_SECTION_NAME (decl) = build_string (len + 5, string);
9454 /* Switch to an arbitrary section NAME with attributes as specified
9455 by FLAGS. ALIGN specifies any known alignment requirements for
9456 the section; 0 if the default should be used. */
9459 unicosmk_asm_named_section (const char *name, unsigned int flags)
9463 /* Close the previous section. */
9465 fputs ("\t.endp\n\n", asm_out_file);
9467 /* Find out what kind of section we are opening. */
9469 if (flags & SECTION_MAIN)
9470 fputs ("\t.start\tmain\n", asm_out_file);
9472 if (flags & SECTION_CODE)
9474 else if (flags & SECTION_PUBLIC)
9479 if (current_section_align != 0)
9480 fprintf (asm_out_file, "\t.psect\t%s,%d,%s\n", name,
9481 current_section_align, kind);
9483 fprintf (asm_out_file, "\t.psect\t%s,%s\n", name, kind);
9487 unicosmk_insert_attributes (tree decl, tree *attr_ptr ATTRIBUTE_UNUSED)
9490 && (TREE_PUBLIC (decl) || TREE_CODE (decl) == FUNCTION_DECL))
9491 unicosmk_unique_section (decl, 0);
9494 /* Output an alignment directive. We have to use the macro 'gcc@code@align'
9495 in code sections because .align fill unused space with zeroes. */
9498 unicosmk_output_align (FILE *file, int align)
9500 if (inside_function)
9501 fprintf (file, "\tgcc@code@align\t%d\n", align);
9503 fprintf (file, "\t.align\t%d\n", align);
9506 /* Add a case vector to the current function's list of deferred case
9507 vectors. Case vectors have to be put into a separate section because CAM
9508 does not allow data definitions in code sections. */
9511 unicosmk_defer_case_vector (rtx lab, rtx vec)
9513 struct machine_function *machine = cfun->machine;
9515 vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec);
9516 machine->addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec,
9517 machine->addr_list);
9520 /* Output a case vector. */
9523 unicosmk_output_addr_vec (FILE *file, rtx vec)
9525 rtx lab = XEXP (vec, 0);
9526 rtx body = XEXP (vec, 1);
9527 int vlen = XVECLEN (body, 0);
9530 (*targetm.asm_out.internal_label) (file, "L", CODE_LABEL_NUMBER (lab));
9532 for (idx = 0; idx < vlen; idx++)
9534 ASM_OUTPUT_ADDR_VEC_ELT
9535 (file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0)));
9539 /* Output current function's deferred case vectors. */
9542 unicosmk_output_deferred_case_vectors (FILE *file)
9544 struct machine_function *machine = cfun->machine;
9547 if (machine->addr_list == NULL_RTX)
9551 for (t = machine->addr_list; t; t = XEXP (t, 1))
9552 unicosmk_output_addr_vec (file, XEXP (t, 0));
9555 /* Generate the name of the SSIB section for the current function. */
9557 #define SSIB_PREFIX "__SSIB_"
9558 #define SSIB_PREFIX_LEN 7
9561 unicosmk_ssib_name (void)
9563 /* This is ok since CAM won't be able to deal with names longer than that
9566 static char name[256];
9572 x = DECL_RTL (cfun->decl);
9573 if (GET_CODE (x) != MEM)
9576 if (GET_CODE (x) != SYMBOL_REF)
9578 fnname = XSTR (x, 0);
9580 len = strlen (fnname);
9581 if (len + SSIB_PREFIX_LEN > 255)
9582 len = 255 - SSIB_PREFIX_LEN;
9584 strcpy (name, SSIB_PREFIX);
9585 strncpy (name + SSIB_PREFIX_LEN, fnname, len);
9586 name[len + SSIB_PREFIX_LEN] = 0;
9591 /* Set up the dynamic subprogram information block (DSIB) and update the
9592 frame pointer register ($15) for subroutines which have a frame. If the
9593 subroutine doesn't have a frame, simply increment $15. */
9596 unicosmk_gen_dsib (unsigned long *imaskP)
9598 if (alpha_procedure_type == PT_STACK)
9600 const char *ssib_name;
9603 /* Allocate 64 bytes for the DSIB. */
9605 FRP (emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx,
9607 emit_insn (gen_blockage ());
9609 /* Save the return address. */
9611 mem = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx, 56));
9612 set_mem_alias_set (mem, alpha_sr_alias_set);
9613 FRP (emit_move_insn (mem, gen_rtx_REG (DImode, REG_RA)));
9614 (*imaskP) &= ~(1UL << REG_RA);
9616 /* Save the old frame pointer. */
9618 mem = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx, 48));
9619 set_mem_alias_set (mem, alpha_sr_alias_set);
9620 FRP (emit_move_insn (mem, hard_frame_pointer_rtx));
9621 (*imaskP) &= ~(1UL << HARD_FRAME_POINTER_REGNUM);
9623 emit_insn (gen_blockage ());
9625 /* Store the SSIB pointer. */
9627 ssib_name = ggc_strdup (unicosmk_ssib_name ());
9628 mem = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx, 32));
9629 set_mem_alias_set (mem, alpha_sr_alias_set);
9631 FRP (emit_move_insn (gen_rtx_REG (DImode, 5),
9632 gen_rtx_SYMBOL_REF (Pmode, ssib_name)));
9633 FRP (emit_move_insn (mem, gen_rtx_REG (DImode, 5)));
9635 /* Save the CIW index. */
9637 mem = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx, 24));
9638 set_mem_alias_set (mem, alpha_sr_alias_set);
9639 FRP (emit_move_insn (mem, gen_rtx_REG (DImode, 25)));
9641 emit_insn (gen_blockage ());
9643 /* Set the new frame pointer. */
9645 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
9646 stack_pointer_rtx, GEN_INT (64))));
9651 /* Increment the frame pointer register to indicate that we do not
9654 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
9655 hard_frame_pointer_rtx, const1_rtx)));
9659 /* Output the static subroutine information block for the current
9663 unicosmk_output_ssib (FILE *file, const char *fnname)
9669 struct machine_function *machine = cfun->machine;
9672 fprintf (file, "\t.endp\n\n\t.psect\t%s%s,data\n", user_label_prefix,
9673 unicosmk_ssib_name ());
9675 /* Some required stuff and the function name length. */
9677 len = strlen (fnname);
9678 fprintf (file, "\t.quad\t^X20008%2.2X28\n", len);
9681 ??? We don't do that yet. */
9683 fputs ("\t.quad\t0\n", file);
9685 /* Function address. */
9687 fputs ("\t.quad\t", file);
9688 assemble_name (file, fnname);
9691 fputs ("\t.quad\t0\n", file);
9692 fputs ("\t.quad\t0\n", file);
9695 ??? We do it the same way Cray CC does it but this could be
9698 for( i = 0; i < len; i++ )
9699 fprintf (file, "\t.byte\t%d\n", (int)(fnname[i]));
9700 if( (len % 8) == 0 )
9701 fputs ("\t.quad\t0\n", file);
9703 fprintf (file, "\t.bits\t%d : 0\n", (8 - (len % 8))*8);
9705 /* All call information words used in the function. */
9707 for (x = machine->first_ciw; x; x = XEXP (x, 1))
9710 #if HOST_BITS_PER_WIDE_INT == 32
9711 fprintf (file, "\t.quad\t" HOST_WIDE_INT_PRINT_DOUBLE_HEX "\n",
9712 CONST_DOUBLE_HIGH (ciw), CONST_DOUBLE_LOW (ciw));
9714 fprintf (file, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX "\n", INTVAL (ciw));
9719 /* Add a call information word (CIW) to the list of the current function's
9720 CIWs and return its index.
9722 X is a CONST_INT or CONST_DOUBLE representing the CIW. */
9725 unicosmk_add_call_info_word (rtx x)
9728 struct machine_function *machine = cfun->machine;
9730 node = gen_rtx_EXPR_LIST (VOIDmode, x, NULL_RTX);
9731 if (machine->first_ciw == NULL_RTX)
9732 machine->first_ciw = node;
9734 XEXP (machine->last_ciw, 1) = node;
9736 machine->last_ciw = node;
9737 ++machine->ciw_count;
9739 return GEN_INT (machine->ciw_count
9740 + strlen (current_function_name ())/8 + 5);
9743 static char unicosmk_section_buf[100];
9746 unicosmk_text_section (void)
9748 static int count = 0;
9749 sprintf (unicosmk_section_buf, "\t.endp\n\n\t.psect\tgcc@text___%d,code",
9751 return unicosmk_section_buf;
9755 unicosmk_data_section (void)
9757 static int count = 1;
9758 sprintf (unicosmk_section_buf, "\t.endp\n\n\t.psect\tgcc@data___%d,data",
9760 return unicosmk_section_buf;
9763 /* The Cray assembler doesn't accept extern declarations for symbols which
9764 are defined in the same file. We have to keep track of all global
9765 symbols which are referenced and/or defined in a source file and output
9766 extern declarations for those which are referenced but not defined at
9769 /* List of identifiers for which an extern declaration might have to be
9771 /* FIXME: needs to use GC, so it can be saved and restored for PCH. */
9773 struct unicosmk_extern_list
9775 struct unicosmk_extern_list *next;
9779 static struct unicosmk_extern_list *unicosmk_extern_head = 0;
9781 /* Output extern declarations which are required for every asm file. */
9784 unicosmk_output_default_externs (FILE *file)
9786 static const char *const externs[] =
9787 { "__T3E_MISMATCH" };
9792 n = ARRAY_SIZE (externs);
9794 for (i = 0; i < n; i++)
9795 fprintf (file, "\t.extern\t%s\n", externs[i]);
9798 /* Output extern declarations for global symbols which are have been
9799 referenced but not defined. */
9802 unicosmk_output_externs (FILE *file)
9804 struct unicosmk_extern_list *p;
9805 const char *real_name;
9809 len = strlen (user_label_prefix);
9810 for (p = unicosmk_extern_head; p != 0; p = p->next)
9812 /* We have to strip the encoding and possibly remove user_label_prefix
9813 from the identifier in order to handle -fleading-underscore and
9814 explicit asm names correctly (cf. gcc.dg/asm-names-1.c). */
9815 real_name = default_strip_name_encoding (p->name);
9816 if (len && p->name[0] == '*'
9817 && !memcmp (real_name, user_label_prefix, len))
9820 name_tree = get_identifier (real_name);
9821 if (! TREE_ASM_WRITTEN (name_tree))
9823 TREE_ASM_WRITTEN (name_tree) = 1;
9824 fputs ("\t.extern\t", file);
9825 assemble_name (file, p->name);
9831 /* Record an extern. */
9834 unicosmk_add_extern (const char *name)
9836 struct unicosmk_extern_list *p;
9838 p = (struct unicosmk_extern_list *)
9839 xmalloc (sizeof (struct unicosmk_extern_list));
9840 p->next = unicosmk_extern_head;
9842 unicosmk_extern_head = p;
9845 /* The Cray assembler generates incorrect code if identifiers which
9846 conflict with register names are used as instruction operands. We have
9847 to replace such identifiers with DEX expressions. */
9849 /* Structure to collect identifiers which have been replaced by DEX
9851 /* FIXME: needs to use GC, so it can be saved and restored for PCH. */
9853 struct unicosmk_dex {
9854 struct unicosmk_dex *next;
9858 /* List of identifiers which have been replaced by DEX expressions. The DEX
9859 number is determined by the position in the list. */
9861 static struct unicosmk_dex *unicosmk_dex_list = NULL;
9863 /* The number of elements in the DEX list. */
9865 static int unicosmk_dex_count = 0;
9867 /* Check if NAME must be replaced by a DEX expression. */
9870 unicosmk_special_name (const char *name)
9878 if (name[0] != 'r' && name[0] != 'f' && name[0] != 'R' && name[0] != 'F')
9884 return (name[2] == '\0' || (ISDIGIT (name[2]) && name[3] == '\0'));
9887 return (name[2] == '\0'
9888 || ((name[2] == '0' || name[2] == '1') && name[3] == '\0'));
9891 return (ISDIGIT (name[1]) && name[2] == '\0');
9895 /* Return the DEX number if X must be replaced by a DEX expression and 0
9899 unicosmk_need_dex (rtx x)
9901 struct unicosmk_dex *dex;
9905 if (GET_CODE (x) != SYMBOL_REF)
9909 if (! unicosmk_special_name (name))
9912 i = unicosmk_dex_count;
9913 for (dex = unicosmk_dex_list; dex; dex = dex->next)
9915 if (! strcmp (name, dex->name))
9920 dex = (struct unicosmk_dex *) xmalloc (sizeof (struct unicosmk_dex));
9922 dex->next = unicosmk_dex_list;
9923 unicosmk_dex_list = dex;
9925 ++unicosmk_dex_count;
9926 return unicosmk_dex_count;
9929 /* Output the DEX definitions for this file. */
9932 unicosmk_output_dex (FILE *file)
9934 struct unicosmk_dex *dex;
9937 if (unicosmk_dex_list == NULL)
9940 fprintf (file, "\t.dexstart\n");
9942 i = unicosmk_dex_count;
9943 for (dex = unicosmk_dex_list; dex; dex = dex->next)
9945 fprintf (file, "\tDEX (%d) = ", i);
9946 assemble_name (file, dex->name);
9951 fprintf (file, "\t.dexend\n");
9954 /* Output text that to appear at the beginning of an assembler file. */
9957 unicosmk_file_start (void)
9961 fputs ("\t.ident\t", asm_out_file);
9962 unicosmk_output_module_name (asm_out_file);
9963 fputs ("\n\n", asm_out_file);
9965 /* The Unicos/Mk assembler uses different register names. Instead of trying
9966 to support them, we simply use micro definitions. */
9968 /* CAM has different register names: rN for the integer register N and fN
9969 for the floating-point register N. Instead of trying to use these in
9970 alpha.md, we define the symbols $N and $fN to refer to the appropriate
9973 for (i = 0; i < 32; ++i)
9974 fprintf (asm_out_file, "$%d <- r%d\n", i, i);
9976 for (i = 0; i < 32; ++i)
9977 fprintf (asm_out_file, "$f%d <- f%d\n", i, i);
9979 putc ('\n', asm_out_file);
9981 /* The .align directive fill unused space with zeroes which does not work
9982 in code sections. We define the macro 'gcc@code@align' which uses nops
9983 instead. Note that it assumes that code sections always have the
9984 biggest possible alignment since . refers to the current offset from
9985 the beginning of the section. */
9987 fputs ("\t.macro gcc@code@align n\n", asm_out_file);
9988 fputs ("gcc@n@bytes = 1 << n\n", asm_out_file);
9989 fputs ("gcc@here = . % gcc@n@bytes\n", asm_out_file);
9990 fputs ("\t.if ne, gcc@here, 0\n", asm_out_file);
9991 fputs ("\t.repeat (gcc@n@bytes - gcc@here) / 4\n", asm_out_file);
9992 fputs ("\tbis r31,r31,r31\n", asm_out_file);
9993 fputs ("\t.endr\n", asm_out_file);
9994 fputs ("\t.endif\n", asm_out_file);
9995 fputs ("\t.endm gcc@code@align\n\n", asm_out_file);
9997 /* Output extern declarations which should always be visible. */
9998 unicosmk_output_default_externs (asm_out_file);
10000 /* Open a dummy section. We always need to be inside a section for the
10001 section-switching code to work correctly.
10002 ??? This should be a module id or something like that. I still have to
10003 figure out what the rules for those are. */
10004 fputs ("\n\t.psect\t$SG00000,data\n", asm_out_file);
10007 /* Output text to appear at the end of an assembler file. This includes all
10008 pending extern declarations and DEX expressions. */
10011 unicosmk_file_end (void)
10013 fputs ("\t.endp\n\n", asm_out_file);
10015 /* Output all pending externs. */
10017 unicosmk_output_externs (asm_out_file);
10019 /* Output dex definitions used for functions whose names conflict with
10022 unicosmk_output_dex (asm_out_file);
10024 fputs ("\t.end\t", asm_out_file);
10025 unicosmk_output_module_name (asm_out_file);
10026 putc ('\n', asm_out_file);
10032 unicosmk_output_deferred_case_vectors (FILE *file ATTRIBUTE_UNUSED)
10036 unicosmk_gen_dsib (unsigned long *imaskP ATTRIBUTE_UNUSED)
10040 unicosmk_output_ssib (FILE * file ATTRIBUTE_UNUSED,
10041 const char * fnname ATTRIBUTE_UNUSED)
10045 unicosmk_add_call_info_word (rtx x ATTRIBUTE_UNUSED)
10051 unicosmk_need_dex (rtx x ATTRIBUTE_UNUSED)
10056 #endif /* TARGET_ABI_UNICOSMK */
10059 alpha_init_libfuncs (void)
10061 if (TARGET_ABI_UNICOSMK)
10063 /* Prevent gcc from generating calls to __divsi3. */
10064 set_optab_libfunc (sdiv_optab, SImode, 0);
10065 set_optab_libfunc (udiv_optab, SImode, 0);
10067 /* Use the functions provided by the system library
10068 for DImode integer division. */
10069 set_optab_libfunc (sdiv_optab, DImode, "$sldiv");
10070 set_optab_libfunc (udiv_optab, DImode, "$uldiv");
10072 else if (TARGET_ABI_OPEN_VMS)
10074 /* Use the VMS runtime library functions for division and
10076 set_optab_libfunc (sdiv_optab, SImode, "OTS$DIV_I");
10077 set_optab_libfunc (sdiv_optab, DImode, "OTS$DIV_L");
10078 set_optab_libfunc (udiv_optab, SImode, "OTS$DIV_UI");
10079 set_optab_libfunc (udiv_optab, DImode, "OTS$DIV_UL");
10080 set_optab_libfunc (smod_optab, SImode, "OTS$REM_I");
10081 set_optab_libfunc (smod_optab, DImode, "OTS$REM_L");
10082 set_optab_libfunc (umod_optab, SImode, "OTS$REM_UI");
10083 set_optab_libfunc (umod_optab, DImode, "OTS$REM_UL");
10088 /* Initialize the GCC target structure. */
10089 #if TARGET_ABI_OPEN_VMS
10090 # undef TARGET_ATTRIBUTE_TABLE
10091 # define TARGET_ATTRIBUTE_TABLE vms_attribute_table
10092 # undef TARGET_SECTION_TYPE_FLAGS
10093 # define TARGET_SECTION_TYPE_FLAGS vms_section_type_flags
10096 #undef TARGET_IN_SMALL_DATA_P
10097 #define TARGET_IN_SMALL_DATA_P alpha_in_small_data_p
10099 #if TARGET_ABI_UNICOSMK
10100 # undef TARGET_INSERT_ATTRIBUTES
10101 # define TARGET_INSERT_ATTRIBUTES unicosmk_insert_attributes
10102 # undef TARGET_SECTION_TYPE_FLAGS
10103 # define TARGET_SECTION_TYPE_FLAGS unicosmk_section_type_flags
10104 # undef TARGET_ASM_UNIQUE_SECTION
10105 # define TARGET_ASM_UNIQUE_SECTION unicosmk_unique_section
10106 # undef TARGET_ASM_GLOBALIZE_LABEL
10107 # define TARGET_ASM_GLOBALIZE_LABEL hook_void_FILEptr_constcharptr
10108 # undef TARGET_MUST_PASS_IN_STACK
10109 # define TARGET_MUST_PASS_IN_STACK unicosmk_must_pass_in_stack
10112 #undef TARGET_ASM_ALIGNED_HI_OP
10113 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
10114 #undef TARGET_ASM_ALIGNED_DI_OP
10115 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
10117 /* Default unaligned ops are provided for ELF systems. To get unaligned
10118 data for non-ELF systems, we have to turn off auto alignment. */
10119 #ifndef OBJECT_FORMAT_ELF
10120 #undef TARGET_ASM_UNALIGNED_HI_OP
10121 #define TARGET_ASM_UNALIGNED_HI_OP "\t.align 0\n\t.word\t"
10122 #undef TARGET_ASM_UNALIGNED_SI_OP
10123 #define TARGET_ASM_UNALIGNED_SI_OP "\t.align 0\n\t.long\t"
10124 #undef TARGET_ASM_UNALIGNED_DI_OP
10125 #define TARGET_ASM_UNALIGNED_DI_OP "\t.align 0\n\t.quad\t"
10128 #ifdef OBJECT_FORMAT_ELF
10129 #undef TARGET_ASM_SELECT_RTX_SECTION
10130 #define TARGET_ASM_SELECT_RTX_SECTION alpha_elf_select_rtx_section
10133 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
10134 #define TARGET_ASM_FUNCTION_END_PROLOGUE alpha_output_function_end_prologue
10136 #undef TARGET_INIT_LIBFUNCS
10137 #define TARGET_INIT_LIBFUNCS alpha_init_libfuncs
10139 #if TARGET_ABI_UNICOSMK
10140 #undef TARGET_ASM_FILE_START
10141 #define TARGET_ASM_FILE_START unicosmk_file_start
10142 #undef TARGET_ASM_FILE_END
10143 #define TARGET_ASM_FILE_END unicosmk_file_end
10145 #undef TARGET_ASM_FILE_START
10146 #define TARGET_ASM_FILE_START alpha_file_start
10147 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
10148 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
10151 #undef TARGET_SCHED_ADJUST_COST
10152 #define TARGET_SCHED_ADJUST_COST alpha_adjust_cost
10153 #undef TARGET_SCHED_ISSUE_RATE
10154 #define TARGET_SCHED_ISSUE_RATE alpha_issue_rate
10155 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
10156 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
10157 alpha_multipass_dfa_lookahead
10159 #undef TARGET_HAVE_TLS
10160 #define TARGET_HAVE_TLS HAVE_AS_TLS
10162 #undef TARGET_INIT_BUILTINS
10163 #define TARGET_INIT_BUILTINS alpha_init_builtins
10164 #undef TARGET_EXPAND_BUILTIN
10165 #define TARGET_EXPAND_BUILTIN alpha_expand_builtin
10167 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
10168 #define TARGET_FUNCTION_OK_FOR_SIBCALL alpha_function_ok_for_sibcall
10169 #undef TARGET_CANNOT_COPY_INSN_P
10170 #define TARGET_CANNOT_COPY_INSN_P alpha_cannot_copy_insn_p
10173 #undef TARGET_ASM_OUTPUT_MI_THUNK
10174 #define TARGET_ASM_OUTPUT_MI_THUNK alpha_output_mi_thunk_osf
10175 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
10176 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
10179 #undef TARGET_RTX_COSTS
10180 #define TARGET_RTX_COSTS alpha_rtx_costs
10181 #undef TARGET_ADDRESS_COST
10182 #define TARGET_ADDRESS_COST hook_int_rtx_0
10184 #undef TARGET_MACHINE_DEPENDENT_REORG
10185 #define TARGET_MACHINE_DEPENDENT_REORG alpha_reorg
10187 #undef TARGET_PROMOTE_FUNCTION_ARGS
10188 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
10189 #undef TARGET_PROMOTE_FUNCTION_RETURN
10190 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
10191 #undef TARGET_PROMOTE_PROTOTYPES
10192 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_false
10193 #undef TARGET_RETURN_IN_MEMORY
10194 #define TARGET_RETURN_IN_MEMORY alpha_return_in_memory
10195 #undef TARGET_PASS_BY_REFERENCE
10196 #define TARGET_PASS_BY_REFERENCE alpha_pass_by_reference
10197 #undef TARGET_SETUP_INCOMING_VARARGS
10198 #define TARGET_SETUP_INCOMING_VARARGS alpha_setup_incoming_varargs
10199 #undef TARGET_STRICT_ARGUMENT_NAMING
10200 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
10201 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
10202 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
10203 #undef TARGET_SPLIT_COMPLEX_ARG
10204 #define TARGET_SPLIT_COMPLEX_ARG alpha_split_complex_arg
10205 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
10206 #define TARGET_GIMPLIFY_VA_ARG_EXPR alpha_gimplify_va_arg
10208 #undef TARGET_BUILD_BUILTIN_VA_LIST
10209 #define TARGET_BUILD_BUILTIN_VA_LIST alpha_build_builtin_va_list
10211 struct gcc_target targetm = TARGET_INITIALIZER;
10214 #include "gt-alpha.h"