1 /* Subroutines used for code generation on the DEC Alpha.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
26 #include "coretypes.h"
31 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-attr.h"
44 #include "diagnostic-core.h"
47 #include "integrate.h"
50 #include "target-def.h"
52 #include "langhooks.h"
53 #include <splay-tree.h>
54 #include "cfglayout.h"
56 #include "tree-flow.h"
57 #include "tree-stdarg.h"
58 #include "tm-constrs.h"
62 /* Specify which cpu to schedule for. */
63 enum processor_type alpha_tune;
65 /* Which cpu we're generating code for. */
66 enum processor_type alpha_cpu;
68 static const char * const alpha_cpu_name[] =
73 /* Specify how accurate floating-point traps need to be. */
75 enum alpha_trap_precision alpha_tp;
77 /* Specify the floating-point rounding mode. */
79 enum alpha_fp_rounding_mode alpha_fprm;
81 /* Specify which things cause traps. */
83 enum alpha_fp_trap_mode alpha_fptm;
85 /* Nonzero if inside of a function, because the Alpha asm can't
86 handle .files inside of functions. */
88 static int inside_function = FALSE;
90 /* The number of cycles of latency we should assume on memory reads. */
92 int alpha_memory_latency = 3;
94 /* Whether the function needs the GP. */
96 static int alpha_function_needs_gp;
98 /* The alias set for prologue/epilogue register save/restore. */
100 static GTY(()) alias_set_type alpha_sr_alias_set;
102 /* The assembler name of the current function. */
104 static const char *alpha_fnname;
106 /* The next explicit relocation sequence number. */
107 extern GTY(()) int alpha_next_sequence_number;
108 int alpha_next_sequence_number = 1;
110 /* The literal and gpdisp sequence numbers for this insn, as printed
111 by %# and %* respectively. */
112 extern GTY(()) int alpha_this_literal_sequence_number;
113 extern GTY(()) int alpha_this_gpdisp_sequence_number;
114 int alpha_this_literal_sequence_number;
115 int alpha_this_gpdisp_sequence_number;
117 /* Costs of various operations on the different architectures. */
119 struct alpha_rtx_cost_data
121 unsigned char fp_add;
122 unsigned char fp_mult;
123 unsigned char fp_div_sf;
124 unsigned char fp_div_df;
125 unsigned char int_mult_si;
126 unsigned char int_mult_di;
127 unsigned char int_shift;
128 unsigned char int_cmov;
129 unsigned short int_div;
132 static struct alpha_rtx_cost_data const alpha_rtx_cost_data[PROCESSOR_MAX] =
135 COSTS_N_INSNS (6), /* fp_add */
136 COSTS_N_INSNS (6), /* fp_mult */
137 COSTS_N_INSNS (34), /* fp_div_sf */
138 COSTS_N_INSNS (63), /* fp_div_df */
139 COSTS_N_INSNS (23), /* int_mult_si */
140 COSTS_N_INSNS (23), /* int_mult_di */
141 COSTS_N_INSNS (2), /* int_shift */
142 COSTS_N_INSNS (2), /* int_cmov */
143 COSTS_N_INSNS (97), /* int_div */
146 COSTS_N_INSNS (4), /* fp_add */
147 COSTS_N_INSNS (4), /* fp_mult */
148 COSTS_N_INSNS (15), /* fp_div_sf */
149 COSTS_N_INSNS (22), /* fp_div_df */
150 COSTS_N_INSNS (8), /* int_mult_si */
151 COSTS_N_INSNS (12), /* int_mult_di */
152 COSTS_N_INSNS (1) + 1, /* int_shift */
153 COSTS_N_INSNS (1), /* int_cmov */
154 COSTS_N_INSNS (83), /* int_div */
157 COSTS_N_INSNS (4), /* fp_add */
158 COSTS_N_INSNS (4), /* fp_mult */
159 COSTS_N_INSNS (12), /* fp_div_sf */
160 COSTS_N_INSNS (15), /* fp_div_df */
161 COSTS_N_INSNS (7), /* int_mult_si */
162 COSTS_N_INSNS (7), /* int_mult_di */
163 COSTS_N_INSNS (1), /* int_shift */
164 COSTS_N_INSNS (2), /* int_cmov */
165 COSTS_N_INSNS (86), /* int_div */
169 /* Similar but tuned for code size instead of execution latency. The
170 extra +N is fractional cost tuning based on latency. It's used to
171 encourage use of cheaper insns like shift, but only if there's just
174 static struct alpha_rtx_cost_data const alpha_rtx_cost_size =
176 COSTS_N_INSNS (1), /* fp_add */
177 COSTS_N_INSNS (1), /* fp_mult */
178 COSTS_N_INSNS (1), /* fp_div_sf */
179 COSTS_N_INSNS (1) + 1, /* fp_div_df */
180 COSTS_N_INSNS (1) + 1, /* int_mult_si */
181 COSTS_N_INSNS (1) + 2, /* int_mult_di */
182 COSTS_N_INSNS (1), /* int_shift */
183 COSTS_N_INSNS (1), /* int_cmov */
184 COSTS_N_INSNS (6), /* int_div */
187 /* Get the number of args of a function in one of two ways. */
188 #if TARGET_ABI_OPEN_VMS || TARGET_ABI_UNICOSMK
189 #define NUM_ARGS crtl->args.info.num_args
191 #define NUM_ARGS crtl->args.info
197 /* Declarations of static functions. */
198 static struct machine_function *alpha_init_machine_status (void);
199 static rtx alpha_emit_xfloating_compare (enum rtx_code *, rtx, rtx);
201 #if TARGET_ABI_OPEN_VMS
202 static void alpha_write_linkage (FILE *, const char *, tree);
203 static bool vms_valid_pointer_mode (enum machine_mode);
206 static void unicosmk_output_deferred_case_vectors (FILE *);
207 static void unicosmk_gen_dsib (unsigned long *);
208 static void unicosmk_output_ssib (FILE *, const char *);
209 static int unicosmk_need_dex (rtx);
211 /* Implement TARGET_HANDLE_OPTION. */
214 alpha_handle_option (size_t code, const char *arg, int value)
220 target_flags |= MASK_SOFT_FP;
224 case OPT_mieee_with_inexact:
225 target_flags |= MASK_IEEE_CONFORMANT;
229 if (value != 16 && value != 32 && value != 64)
230 error ("bad value %qs for -mtls-size switch", arg);
237 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
238 /* Implement TARGET_MANGLE_TYPE. */
241 alpha_mangle_type (const_tree type)
243 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
244 && TARGET_LONG_DOUBLE_128)
247 /* For all other types, use normal C++ mangling. */
252 /* Parse target option strings. */
255 override_options (void)
257 static const struct cpu_table {
258 const char *const name;
259 const enum processor_type processor;
262 { "ev4", PROCESSOR_EV4, 0 },
263 { "ev45", PROCESSOR_EV4, 0 },
264 { "21064", PROCESSOR_EV4, 0 },
265 { "ev5", PROCESSOR_EV5, 0 },
266 { "21164", PROCESSOR_EV5, 0 },
267 { "ev56", PROCESSOR_EV5, MASK_BWX },
268 { "21164a", PROCESSOR_EV5, MASK_BWX },
269 { "pca56", PROCESSOR_EV5, MASK_BWX|MASK_MAX },
270 { "21164PC",PROCESSOR_EV5, MASK_BWX|MASK_MAX },
271 { "21164pc",PROCESSOR_EV5, MASK_BWX|MASK_MAX },
272 { "ev6", PROCESSOR_EV6, MASK_BWX|MASK_MAX|MASK_FIX },
273 { "21264", PROCESSOR_EV6, MASK_BWX|MASK_MAX|MASK_FIX },
274 { "ev67", PROCESSOR_EV6, MASK_BWX|MASK_MAX|MASK_FIX|MASK_CIX },
275 { "21264a", PROCESSOR_EV6, MASK_BWX|MASK_MAX|MASK_FIX|MASK_CIX }
278 int const ct_size = ARRAY_SIZE (cpu_table);
281 /* Unicos/Mk doesn't have shared libraries. */
282 if (TARGET_ABI_UNICOSMK && flag_pic)
284 warning (0, "-f%s ignored for Unicos/Mk (not supported)",
285 (flag_pic > 1) ? "PIC" : "pic");
289 /* On Unicos/Mk, the native compiler consistently generates /d suffices for
290 floating-point instructions. Make that the default for this target. */
291 if (TARGET_ABI_UNICOSMK)
292 alpha_fprm = ALPHA_FPRM_DYN;
294 alpha_fprm = ALPHA_FPRM_NORM;
296 alpha_tp = ALPHA_TP_PROG;
297 alpha_fptm = ALPHA_FPTM_N;
299 /* We cannot use su and sui qualifiers for conversion instructions on
300 Unicos/Mk. I'm not sure if this is due to assembler or hardware
301 limitations. Right now, we issue a warning if -mieee is specified
302 and then ignore it; eventually, we should either get it right or
303 disable the option altogether. */
307 if (TARGET_ABI_UNICOSMK)
308 warning (0, "-mieee not supported on Unicos/Mk");
311 alpha_tp = ALPHA_TP_INSN;
312 alpha_fptm = ALPHA_FPTM_SU;
316 if (TARGET_IEEE_WITH_INEXACT)
318 if (TARGET_ABI_UNICOSMK)
319 warning (0, "-mieee-with-inexact not supported on Unicos/Mk");
322 alpha_tp = ALPHA_TP_INSN;
323 alpha_fptm = ALPHA_FPTM_SUI;
329 if (! strcmp (alpha_tp_string, "p"))
330 alpha_tp = ALPHA_TP_PROG;
331 else if (! strcmp (alpha_tp_string, "f"))
332 alpha_tp = ALPHA_TP_FUNC;
333 else if (! strcmp (alpha_tp_string, "i"))
334 alpha_tp = ALPHA_TP_INSN;
336 error ("bad value %qs for -mtrap-precision switch", alpha_tp_string);
339 if (alpha_fprm_string)
341 if (! strcmp (alpha_fprm_string, "n"))
342 alpha_fprm = ALPHA_FPRM_NORM;
343 else if (! strcmp (alpha_fprm_string, "m"))
344 alpha_fprm = ALPHA_FPRM_MINF;
345 else if (! strcmp (alpha_fprm_string, "c"))
346 alpha_fprm = ALPHA_FPRM_CHOP;
347 else if (! strcmp (alpha_fprm_string,"d"))
348 alpha_fprm = ALPHA_FPRM_DYN;
350 error ("bad value %qs for -mfp-rounding-mode switch",
354 if (alpha_fptm_string)
356 if (strcmp (alpha_fptm_string, "n") == 0)
357 alpha_fptm = ALPHA_FPTM_N;
358 else if (strcmp (alpha_fptm_string, "u") == 0)
359 alpha_fptm = ALPHA_FPTM_U;
360 else if (strcmp (alpha_fptm_string, "su") == 0)
361 alpha_fptm = ALPHA_FPTM_SU;
362 else if (strcmp (alpha_fptm_string, "sui") == 0)
363 alpha_fptm = ALPHA_FPTM_SUI;
365 error ("bad value %qs for -mfp-trap-mode switch", alpha_fptm_string);
368 if (alpha_cpu_string)
370 for (i = 0; i < ct_size; i++)
371 if (! strcmp (alpha_cpu_string, cpu_table [i].name))
373 alpha_tune = alpha_cpu = cpu_table [i].processor;
374 target_flags &= ~ (MASK_BWX | MASK_MAX | MASK_FIX | MASK_CIX);
375 target_flags |= cpu_table [i].flags;
379 error ("bad value %qs for -mcpu switch", alpha_cpu_string);
382 if (alpha_tune_string)
384 for (i = 0; i < ct_size; i++)
385 if (! strcmp (alpha_tune_string, cpu_table [i].name))
387 alpha_tune = cpu_table [i].processor;
391 error ("bad value %qs for -mtune switch", alpha_tune_string);
394 /* Do some sanity checks on the above options. */
396 if (TARGET_ABI_UNICOSMK && alpha_fptm != ALPHA_FPTM_N)
398 warning (0, "trap mode not supported on Unicos/Mk");
399 alpha_fptm = ALPHA_FPTM_N;
402 if ((alpha_fptm == ALPHA_FPTM_SU || alpha_fptm == ALPHA_FPTM_SUI)
403 && alpha_tp != ALPHA_TP_INSN && alpha_cpu != PROCESSOR_EV6)
405 warning (0, "fp software completion requires -mtrap-precision=i");
406 alpha_tp = ALPHA_TP_INSN;
409 if (alpha_cpu == PROCESSOR_EV6)
411 /* Except for EV6 pass 1 (not released), we always have precise
412 arithmetic traps. Which means we can do software completion
413 without minding trap shadows. */
414 alpha_tp = ALPHA_TP_PROG;
417 if (TARGET_FLOAT_VAX)
419 if (alpha_fprm == ALPHA_FPRM_MINF || alpha_fprm == ALPHA_FPRM_DYN)
421 warning (0, "rounding mode not supported for VAX floats");
422 alpha_fprm = ALPHA_FPRM_NORM;
424 if (alpha_fptm == ALPHA_FPTM_SUI)
426 warning (0, "trap mode not supported for VAX floats");
427 alpha_fptm = ALPHA_FPTM_SU;
429 if (target_flags_explicit & MASK_LONG_DOUBLE_128)
430 warning (0, "128-bit long double not supported for VAX floats");
431 target_flags &= ~MASK_LONG_DOUBLE_128;
438 if (!alpha_mlat_string)
439 alpha_mlat_string = "L1";
441 if (ISDIGIT ((unsigned char)alpha_mlat_string[0])
442 && (lat = strtol (alpha_mlat_string, &end, 10), *end == '\0'))
444 else if ((alpha_mlat_string[0] == 'L' || alpha_mlat_string[0] == 'l')
445 && ISDIGIT ((unsigned char)alpha_mlat_string[1])
446 && alpha_mlat_string[2] == '\0')
448 static int const cache_latency[][4] =
450 { 3, 30, -1 }, /* ev4 -- Bcache is a guess */
451 { 2, 12, 38 }, /* ev5 -- Bcache from PC164 LMbench numbers */
452 { 3, 12, 30 }, /* ev6 -- Bcache from DS20 LMbench. */
455 lat = alpha_mlat_string[1] - '0';
456 if (lat <= 0 || lat > 3 || cache_latency[alpha_tune][lat-1] == -1)
458 warning (0, "L%d cache latency unknown for %s",
459 lat, alpha_cpu_name[alpha_tune]);
463 lat = cache_latency[alpha_tune][lat-1];
465 else if (! strcmp (alpha_mlat_string, "main"))
467 /* Most current memories have about 370ns latency. This is
468 a reasonable guess for a fast cpu. */
473 warning (0, "bad value %qs for -mmemory-latency", alpha_mlat_string);
477 alpha_memory_latency = lat;
480 /* Default the definition of "small data" to 8 bytes. */
484 /* Infer TARGET_SMALL_DATA from -fpic/-fPIC. */
486 target_flags |= MASK_SMALL_DATA;
487 else if (flag_pic == 2)
488 target_flags &= ~MASK_SMALL_DATA;
490 /* Align labels and loops for optimal branching. */
491 /* ??? Kludge these by not doing anything if we don't optimize and also if
492 we are writing ECOFF symbols to work around a bug in DEC's assembler. */
493 if (optimize > 0 && write_symbols != SDB_DEBUG)
495 if (align_loops <= 0)
497 if (align_jumps <= 0)
500 if (align_functions <= 0)
501 align_functions = 16;
503 /* Acquire a unique set number for our register saves and restores. */
504 alpha_sr_alias_set = new_alias_set ();
506 /* Register variables and functions with the garbage collector. */
508 /* Set up function hooks. */
509 init_machine_status = alpha_init_machine_status;
511 /* Tell the compiler when we're using VAX floating point. */
512 if (TARGET_FLOAT_VAX)
514 REAL_MODE_FORMAT (SFmode) = &vax_f_format;
515 REAL_MODE_FORMAT (DFmode) = &vax_g_format;
516 REAL_MODE_FORMAT (TFmode) = NULL;
519 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
520 if (!(target_flags_explicit & MASK_LONG_DOUBLE_128))
521 target_flags |= MASK_LONG_DOUBLE_128;
524 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
525 can be optimized to ap = __builtin_next_arg (0). */
526 if (TARGET_ABI_UNICOSMK)
527 targetm.expand_builtin_va_start = NULL;
530 /* Returns 1 if VALUE is a mask that contains full bytes of zero or ones. */
533 zap_mask (HOST_WIDE_INT value)
537 for (i = 0; i < HOST_BITS_PER_WIDE_INT / HOST_BITS_PER_CHAR;
539 if ((value & 0xff) != 0 && (value & 0xff) != 0xff)
545 /* Return true if OP is valid for a particular TLS relocation.
546 We are already guaranteed that OP is a CONST. */
549 tls_symbolic_operand_1 (rtx op, int size, int unspec)
553 if (GET_CODE (op) != UNSPEC || XINT (op, 1) != unspec)
555 op = XVECEXP (op, 0, 0);
557 if (GET_CODE (op) != SYMBOL_REF)
560 switch (SYMBOL_REF_TLS_MODEL (op))
562 case TLS_MODEL_LOCAL_DYNAMIC:
563 return unspec == UNSPEC_DTPREL && size == alpha_tls_size;
564 case TLS_MODEL_INITIAL_EXEC:
565 return unspec == UNSPEC_TPREL && size == 64;
566 case TLS_MODEL_LOCAL_EXEC:
567 return unspec == UNSPEC_TPREL && size == alpha_tls_size;
573 /* Used by aligned_memory_operand and unaligned_memory_operand to
574 resolve what reload is going to do with OP if it's a register. */
577 resolve_reload_operand (rtx op)
579 if (reload_in_progress)
582 if (GET_CODE (tmp) == SUBREG)
583 tmp = SUBREG_REG (tmp);
585 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER)
587 op = reg_equiv_memory_loc[REGNO (tmp)];
595 /* The scalar modes supported differs from the default check-what-c-supports
596 version in that sometimes TFmode is available even when long double
597 indicates only DFmode. On unicosmk, we have the situation that HImode
598 doesn't map to any C type, but of course we still support that. */
601 alpha_scalar_mode_supported_p (enum machine_mode mode)
609 case TImode: /* via optabs.c */
617 return TARGET_HAS_XFLOATING_LIBS;
624 /* Alpha implements a couple of integer vector mode operations when
625 TARGET_MAX is enabled. We do not check TARGET_MAX here, however,
626 which allows the vectorizer to operate on e.g. move instructions,
627 or when expand_vector_operations can do something useful. */
630 alpha_vector_mode_supported_p (enum machine_mode mode)
632 return mode == V8QImode || mode == V4HImode || mode == V2SImode;
635 /* Return 1 if this function can directly return via $26. */
640 return (! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK
642 && alpha_sa_size () == 0
643 && get_frame_size () == 0
644 && crtl->outgoing_args_size == 0
645 && crtl->args.pretend_args_size == 0);
648 /* Return the ADDR_VEC associated with a tablejump insn. */
651 alpha_tablejump_addr_vec (rtx insn)
655 tmp = JUMP_LABEL (insn);
658 tmp = NEXT_INSN (tmp);
662 && GET_CODE (PATTERN (tmp)) == ADDR_DIFF_VEC)
663 return PATTERN (tmp);
667 /* Return the label of the predicted edge, or CONST0_RTX if we don't know. */
670 alpha_tablejump_best_label (rtx insn)
672 rtx jump_table = alpha_tablejump_addr_vec (insn);
673 rtx best_label = NULL_RTX;
675 /* ??? Once the CFG doesn't keep getting completely rebuilt, look
676 there for edge frequency counts from profile data. */
680 int n_labels = XVECLEN (jump_table, 1);
684 for (i = 0; i < n_labels; i++)
688 for (j = i + 1; j < n_labels; j++)
689 if (XEXP (XVECEXP (jump_table, 1, i), 0)
690 == XEXP (XVECEXP (jump_table, 1, j), 0))
693 if (count > best_count)
694 best_count = count, best_label = XVECEXP (jump_table, 1, i);
698 return best_label ? best_label : const0_rtx;
701 /* Return the TLS model to use for SYMBOL. */
703 static enum tls_model
704 tls_symbolic_operand_type (rtx symbol)
706 enum tls_model model;
708 if (GET_CODE (symbol) != SYMBOL_REF)
709 return TLS_MODEL_NONE;
710 model = SYMBOL_REF_TLS_MODEL (symbol);
712 /* Local-exec with a 64-bit size is the same code as initial-exec. */
713 if (model == TLS_MODEL_LOCAL_EXEC && alpha_tls_size == 64)
714 model = TLS_MODEL_INITIAL_EXEC;
719 /* Return true if the function DECL will share the same GP as any
720 function in the current unit of translation. */
723 decl_has_samegp (const_tree decl)
725 /* Functions that are not local can be overridden, and thus may
726 not share the same gp. */
727 if (!(*targetm.binds_local_p) (decl))
730 /* If -msmall-data is in effect, assume that there is only one GP
731 for the module, and so any local symbol has this property. We
732 need explicit relocations to be able to enforce this for symbols
733 not defined in this unit of translation, however. */
734 if (TARGET_EXPLICIT_RELOCS && TARGET_SMALL_DATA)
737 /* Functions that are not external are defined in this UoT. */
738 /* ??? Irritatingly, static functions not yet emitted are still
739 marked "external". Apply this to non-static functions only. */
740 return !TREE_PUBLIC (decl) || !DECL_EXTERNAL (decl);
743 /* Return true if EXP should be placed in the small data section. */
746 alpha_in_small_data_p (const_tree exp)
748 /* We want to merge strings, so we never consider them small data. */
749 if (TREE_CODE (exp) == STRING_CST)
752 /* Functions are never in the small data area. Duh. */
753 if (TREE_CODE (exp) == FUNCTION_DECL)
756 if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp))
758 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp));
759 if (strcmp (section, ".sdata") == 0
760 || strcmp (section, ".sbss") == 0)
765 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp));
767 /* If this is an incomplete type with size 0, then we can't put it
768 in sdata because it might be too big when completed. */
769 if (size > 0 && (unsigned HOST_WIDE_INT) size <= g_switch_value)
776 #if TARGET_ABI_OPEN_VMS
778 vms_valid_pointer_mode (enum machine_mode mode)
780 return (mode == SImode || mode == DImode);
784 alpha_linkage_symbol_p (const char *symname)
786 int symlen = strlen (symname);
789 return strcmp (&symname [symlen - 4], "..lk") == 0;
794 #define LINKAGE_SYMBOL_REF_P(X) \
795 ((GET_CODE (X) == SYMBOL_REF \
796 && alpha_linkage_symbol_p (XSTR (X, 0))) \
797 || (GET_CODE (X) == CONST \
798 && GET_CODE (XEXP (X, 0)) == PLUS \
799 && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF \
800 && alpha_linkage_symbol_p (XSTR (XEXP (XEXP (X, 0), 0), 0))))
803 /* legitimate_address_p recognizes an RTL expression that is a valid
804 memory address for an instruction. The MODE argument is the
805 machine mode for the MEM expression that wants to use this address.
807 For Alpha, we have either a constant address or the sum of a
808 register and a constant address, or just a register. For DImode,
809 any of those forms can be surrounded with an AND that clear the
810 low-order three bits; this is an "unaligned" access. */
813 alpha_legitimate_address_p (enum machine_mode mode, rtx x, bool strict)
815 /* If this is an ldq_u type address, discard the outer AND. */
817 && GET_CODE (x) == AND
818 && CONST_INT_P (XEXP (x, 1))
819 && INTVAL (XEXP (x, 1)) == -8)
822 /* Discard non-paradoxical subregs. */
823 if (GET_CODE (x) == SUBREG
824 && (GET_MODE_SIZE (GET_MODE (x))
825 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
828 /* Unadorned general registers are valid. */
831 ? STRICT_REG_OK_FOR_BASE_P (x)
832 : NONSTRICT_REG_OK_FOR_BASE_P (x)))
835 /* Constant addresses (i.e. +/- 32k) are valid. */
836 if (CONSTANT_ADDRESS_P (x))
839 #if TARGET_ABI_OPEN_VMS
840 if (LINKAGE_SYMBOL_REF_P (x))
844 /* Register plus a small constant offset is valid. */
845 if (GET_CODE (x) == PLUS)
847 rtx ofs = XEXP (x, 1);
850 /* Discard non-paradoxical subregs. */
851 if (GET_CODE (x) == SUBREG
852 && (GET_MODE_SIZE (GET_MODE (x))
853 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
859 && NONSTRICT_REG_OK_FP_BASE_P (x)
860 && CONST_INT_P (ofs))
863 ? STRICT_REG_OK_FOR_BASE_P (x)
864 : NONSTRICT_REG_OK_FOR_BASE_P (x))
865 && CONSTANT_ADDRESS_P (ofs))
870 /* If we're managing explicit relocations, LO_SUM is valid, as are small
871 data symbols. Avoid explicit relocations of modes larger than word
872 mode since i.e. $LC0+8($1) can fold around +/- 32k offset. */
873 else if (TARGET_EXPLICIT_RELOCS
874 && GET_MODE_SIZE (mode) <= UNITS_PER_WORD)
876 if (small_symbolic_operand (x, Pmode))
879 if (GET_CODE (x) == LO_SUM)
881 rtx ofs = XEXP (x, 1);
884 /* Discard non-paradoxical subregs. */
885 if (GET_CODE (x) == SUBREG
886 && (GET_MODE_SIZE (GET_MODE (x))
887 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
890 /* Must have a valid base register. */
893 ? STRICT_REG_OK_FOR_BASE_P (x)
894 : NONSTRICT_REG_OK_FOR_BASE_P (x))))
897 /* The symbol must be local. */
898 if (local_symbolic_operand (ofs, Pmode)
899 || dtp32_symbolic_operand (ofs, Pmode)
900 || tp32_symbolic_operand (ofs, Pmode))
908 /* Build the SYMBOL_REF for __tls_get_addr. */
910 static GTY(()) rtx tls_get_addr_libfunc;
913 get_tls_get_addr (void)
915 if (!tls_get_addr_libfunc)
916 tls_get_addr_libfunc = init_one_libfunc ("__tls_get_addr");
917 return tls_get_addr_libfunc;
920 /* Try machine-dependent ways of modifying an illegitimate address
921 to be legitimate. If we find one, return the new, valid address. */
924 alpha_legitimize_address_1 (rtx x, rtx scratch, enum machine_mode mode)
926 HOST_WIDE_INT addend;
928 /* If the address is (plus reg const_int) and the CONST_INT is not a
929 valid offset, compute the high part of the constant and add it to
930 the register. Then our address is (plus temp low-part-const). */
931 if (GET_CODE (x) == PLUS
932 && REG_P (XEXP (x, 0))
933 && CONST_INT_P (XEXP (x, 1))
934 && ! CONSTANT_ADDRESS_P (XEXP (x, 1)))
936 addend = INTVAL (XEXP (x, 1));
941 /* If the address is (const (plus FOO const_int)), find the low-order
942 part of the CONST_INT. Then load FOO plus any high-order part of the
943 CONST_INT into a register. Our address is (plus reg low-part-const).
944 This is done to reduce the number of GOT entries. */
945 if (can_create_pseudo_p ()
946 && GET_CODE (x) == CONST
947 && GET_CODE (XEXP (x, 0)) == PLUS
948 && CONST_INT_P (XEXP (XEXP (x, 0), 1)))
950 addend = INTVAL (XEXP (XEXP (x, 0), 1));
951 x = force_reg (Pmode, XEXP (XEXP (x, 0), 0));
955 /* If we have a (plus reg const), emit the load as in (2), then add
956 the two registers, and finally generate (plus reg low-part-const) as
958 if (can_create_pseudo_p ()
959 && GET_CODE (x) == PLUS
960 && REG_P (XEXP (x, 0))
961 && GET_CODE (XEXP (x, 1)) == CONST
962 && GET_CODE (XEXP (XEXP (x, 1), 0)) == PLUS
963 && CONST_INT_P (XEXP (XEXP (XEXP (x, 1), 0), 1)))
965 addend = INTVAL (XEXP (XEXP (XEXP (x, 1), 0), 1));
966 x = expand_simple_binop (Pmode, PLUS, XEXP (x, 0),
967 XEXP (XEXP (XEXP (x, 1), 0), 0),
968 NULL_RTX, 1, OPTAB_LIB_WIDEN);
972 /* If this is a local symbol, split the address into HIGH/LO_SUM parts.
973 Avoid modes larger than word mode since i.e. $LC0+8($1) can fold
974 around +/- 32k offset. */
975 if (TARGET_EXPLICIT_RELOCS
976 && GET_MODE_SIZE (mode) <= UNITS_PER_WORD
977 && symbolic_operand (x, Pmode))
979 rtx r0, r16, eqv, tga, tp, insn, dest, seq;
981 switch (tls_symbolic_operand_type (x))
986 case TLS_MODEL_GLOBAL_DYNAMIC:
989 r0 = gen_rtx_REG (Pmode, 0);
990 r16 = gen_rtx_REG (Pmode, 16);
991 tga = get_tls_get_addr ();
992 dest = gen_reg_rtx (Pmode);
993 seq = GEN_INT (alpha_next_sequence_number++);
995 emit_insn (gen_movdi_er_tlsgd (r16, pic_offset_table_rtx, x, seq));
996 insn = gen_call_value_osf_tlsgd (r0, tga, seq);
997 insn = emit_call_insn (insn);
998 RTL_CONST_CALL_P (insn) = 1;
999 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r16);
1001 insn = get_insns ();
1004 emit_libcall_block (insn, dest, r0, x);
1007 case TLS_MODEL_LOCAL_DYNAMIC:
1010 r0 = gen_rtx_REG (Pmode, 0);
1011 r16 = gen_rtx_REG (Pmode, 16);
1012 tga = get_tls_get_addr ();
1013 scratch = gen_reg_rtx (Pmode);
1014 seq = GEN_INT (alpha_next_sequence_number++);
1016 emit_insn (gen_movdi_er_tlsldm (r16, pic_offset_table_rtx, seq));
1017 insn = gen_call_value_osf_tlsldm (r0, tga, seq);
1018 insn = emit_call_insn (insn);
1019 RTL_CONST_CALL_P (insn) = 1;
1020 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r16);
1022 insn = get_insns ();
1025 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
1026 UNSPEC_TLSLDM_CALL);
1027 emit_libcall_block (insn, scratch, r0, eqv);
1029 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_DTPREL);
1030 eqv = gen_rtx_CONST (Pmode, eqv);
1032 if (alpha_tls_size == 64)
1034 dest = gen_reg_rtx (Pmode);
1035 emit_insn (gen_rtx_SET (VOIDmode, dest, eqv));
1036 emit_insn (gen_adddi3 (dest, dest, scratch));
1039 if (alpha_tls_size == 32)
1041 insn = gen_rtx_HIGH (Pmode, eqv);
1042 insn = gen_rtx_PLUS (Pmode, scratch, insn);
1043 scratch = gen_reg_rtx (Pmode);
1044 emit_insn (gen_rtx_SET (VOIDmode, scratch, insn));
1046 return gen_rtx_LO_SUM (Pmode, scratch, eqv);
1048 case TLS_MODEL_INITIAL_EXEC:
1049 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_TPREL);
1050 eqv = gen_rtx_CONST (Pmode, eqv);
1051 tp = gen_reg_rtx (Pmode);
1052 scratch = gen_reg_rtx (Pmode);
1053 dest = gen_reg_rtx (Pmode);
1055 emit_insn (gen_load_tp (tp));
1056 emit_insn (gen_rtx_SET (VOIDmode, scratch, eqv));
1057 emit_insn (gen_adddi3 (dest, tp, scratch));
1060 case TLS_MODEL_LOCAL_EXEC:
1061 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_TPREL);
1062 eqv = gen_rtx_CONST (Pmode, eqv);
1063 tp = gen_reg_rtx (Pmode);
1065 emit_insn (gen_load_tp (tp));
1066 if (alpha_tls_size == 32)
1068 insn = gen_rtx_HIGH (Pmode, eqv);
1069 insn = gen_rtx_PLUS (Pmode, tp, insn);
1070 tp = gen_reg_rtx (Pmode);
1071 emit_insn (gen_rtx_SET (VOIDmode, tp, insn));
1073 return gen_rtx_LO_SUM (Pmode, tp, eqv);
1079 if (local_symbolic_operand (x, Pmode))
1081 if (small_symbolic_operand (x, Pmode))
1085 if (can_create_pseudo_p ())
1086 scratch = gen_reg_rtx (Pmode);
1087 emit_insn (gen_rtx_SET (VOIDmode, scratch,
1088 gen_rtx_HIGH (Pmode, x)));
1089 return gen_rtx_LO_SUM (Pmode, scratch, x);
1098 HOST_WIDE_INT low, high;
1100 low = ((addend & 0xffff) ^ 0x8000) - 0x8000;
1102 high = ((addend & 0xffffffff) ^ 0x80000000) - 0x80000000;
1106 x = expand_simple_binop (Pmode, PLUS, x, GEN_INT (addend),
1107 (!can_create_pseudo_p () ? scratch : NULL_RTX),
1108 1, OPTAB_LIB_WIDEN);
1110 x = expand_simple_binop (Pmode, PLUS, x, GEN_INT (high),
1111 (!can_create_pseudo_p () ? scratch : NULL_RTX),
1112 1, OPTAB_LIB_WIDEN);
1114 return plus_constant (x, low);
1119 /* Try machine-dependent ways of modifying an illegitimate address
1120 to be legitimate. Return X or the new, valid address. */
1123 alpha_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
1124 enum machine_mode mode)
1126 rtx new_x = alpha_legitimize_address_1 (x, NULL_RTX, mode);
1127 return new_x ? new_x : x;
1130 /* Primarily this is required for TLS symbols, but given that our move
1131 patterns *ought* to be able to handle any symbol at any time, we
1132 should never be spilling symbolic operands to the constant pool, ever. */
1135 alpha_cannot_force_const_mem (rtx x)
1137 enum rtx_code code = GET_CODE (x);
1138 return code == SYMBOL_REF || code == LABEL_REF || code == CONST;
1141 /* We do not allow indirect calls to be optimized into sibling calls, nor
1142 can we allow a call to a function with a different GP to be optimized
1146 alpha_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
1148 /* Can't do indirect tail calls, since we don't know if the target
1149 uses the same GP. */
1153 /* Otherwise, we can make a tail call if the target function shares
1155 return decl_has_samegp (decl);
1159 some_small_symbolic_operand_int (rtx *px, void *data ATTRIBUTE_UNUSED)
1163 /* Don't re-split. */
1164 if (GET_CODE (x) == LO_SUM)
1167 return small_symbolic_operand (x, Pmode) != 0;
1171 split_small_symbolic_operand_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
1175 /* Don't re-split. */
1176 if (GET_CODE (x) == LO_SUM)
1179 if (small_symbolic_operand (x, Pmode))
1181 x = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, x);
1190 split_small_symbolic_operand (rtx x)
1193 for_each_rtx (&x, split_small_symbolic_operand_1, NULL);
1197 /* Indicate that INSN cannot be duplicated. This is true for any insn
1198 that we've marked with gpdisp relocs, since those have to stay in
1199 1-1 correspondence with one another.
1201 Technically we could copy them if we could set up a mapping from one
1202 sequence number to another, across the set of insns to be duplicated.
1203 This seems overly complicated and error-prone since interblock motion
1204 from sched-ebb could move one of the pair of insns to a different block.
1206 Also cannot allow jsr insns to be duplicated. If they throw exceptions,
1207 then they'll be in a different block from their ldgp. Which could lead
1208 the bb reorder code to think that it would be ok to copy just the block
1209 containing the call and branch to the block containing the ldgp. */
1212 alpha_cannot_copy_insn_p (rtx insn)
1214 if (!reload_completed || !TARGET_EXPLICIT_RELOCS)
1216 if (recog_memoized (insn) >= 0)
1217 return get_attr_cannot_copy (insn);
1223 /* Try a machine-dependent way of reloading an illegitimate address
1224 operand. If we find one, push the reload and return the new rtx. */
1227 alpha_legitimize_reload_address (rtx x,
1228 enum machine_mode mode ATTRIBUTE_UNUSED,
1229 int opnum, int type,
1230 int ind_levels ATTRIBUTE_UNUSED)
1232 /* We must recognize output that we have already generated ourselves. */
1233 if (GET_CODE (x) == PLUS
1234 && GET_CODE (XEXP (x, 0)) == PLUS
1235 && REG_P (XEXP (XEXP (x, 0), 0))
1236 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
1237 && CONST_INT_P (XEXP (x, 1)))
1239 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
1240 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
1241 opnum, (enum reload_type) type);
1245 /* We wish to handle large displacements off a base register by
1246 splitting the addend across an ldah and the mem insn. This
1247 cuts number of extra insns needed from 3 to 1. */
1248 if (GET_CODE (x) == PLUS
1249 && REG_P (XEXP (x, 0))
1250 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
1251 && REGNO_OK_FOR_BASE_P (REGNO (XEXP (x, 0)))
1252 && GET_CODE (XEXP (x, 1)) == CONST_INT)
1254 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
1255 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1257 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
1259 /* Check for 32-bit overflow. */
1260 if (high + low != val)
1263 /* Reload the high part into a base reg; leave the low part
1264 in the mem directly. */
1265 x = gen_rtx_PLUS (GET_MODE (x),
1266 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
1270 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
1271 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
1272 opnum, (enum reload_type) type);
1279 /* Compute a (partial) cost for rtx X. Return true if the complete
1280 cost has been computed, and false if subexpressions should be
1281 scanned. In either case, *TOTAL contains the cost result. */
1284 alpha_rtx_costs (rtx x, int code, int outer_code, int *total,
1287 enum machine_mode mode = GET_MODE (x);
1288 bool float_mode_p = FLOAT_MODE_P (mode);
1289 const struct alpha_rtx_cost_data *cost_data;
1292 cost_data = &alpha_rtx_cost_size;
1294 cost_data = &alpha_rtx_cost_data[alpha_tune];
1299 /* If this is an 8-bit constant, return zero since it can be used
1300 nearly anywhere with no cost. If it is a valid operand for an
1301 ADD or AND, likewise return 0 if we know it will be used in that
1302 context. Otherwise, return 2 since it might be used there later.
1303 All other constants take at least two insns. */
1304 if (INTVAL (x) >= 0 && INTVAL (x) < 256)
1312 if (x == CONST0_RTX (mode))
1314 else if ((outer_code == PLUS && add_operand (x, VOIDmode))
1315 || (outer_code == AND && and_operand (x, VOIDmode)))
1317 else if (add_operand (x, VOIDmode) || and_operand (x, VOIDmode))
1320 *total = COSTS_N_INSNS (2);
1326 if (TARGET_EXPLICIT_RELOCS && small_symbolic_operand (x, VOIDmode))
1327 *total = COSTS_N_INSNS (outer_code != MEM);
1328 else if (TARGET_EXPLICIT_RELOCS && local_symbolic_operand (x, VOIDmode))
1329 *total = COSTS_N_INSNS (1 + (outer_code != MEM));
1330 else if (tls_symbolic_operand_type (x))
1331 /* Estimate of cost for call_pal rduniq. */
1332 /* ??? How many insns do we emit here? More than one... */
1333 *total = COSTS_N_INSNS (15);
1335 /* Otherwise we do a load from the GOT. */
1336 *total = COSTS_N_INSNS (!speed ? 1 : alpha_memory_latency);
1340 /* This is effectively an add_operand. */
1347 *total = cost_data->fp_add;
1348 else if (GET_CODE (XEXP (x, 0)) == MULT
1349 && const48_operand (XEXP (XEXP (x, 0), 1), VOIDmode))
1351 *total = (rtx_cost (XEXP (XEXP (x, 0), 0),
1352 (enum rtx_code) outer_code, speed)
1353 + rtx_cost (XEXP (x, 1),
1354 (enum rtx_code) outer_code, speed)
1355 + COSTS_N_INSNS (1));
1362 *total = cost_data->fp_mult;
1363 else if (mode == DImode)
1364 *total = cost_data->int_mult_di;
1366 *total = cost_data->int_mult_si;
1370 if (CONST_INT_P (XEXP (x, 1))
1371 && INTVAL (XEXP (x, 1)) <= 3)
1373 *total = COSTS_N_INSNS (1);
1380 *total = cost_data->int_shift;
1385 *total = cost_data->fp_add;
1387 *total = cost_data->int_cmov;
1395 *total = cost_data->int_div;
1396 else if (mode == SFmode)
1397 *total = cost_data->fp_div_sf;
1399 *total = cost_data->fp_div_df;
1403 *total = COSTS_N_INSNS (!speed ? 1 : alpha_memory_latency);
1409 *total = COSTS_N_INSNS (1);
1417 *total = COSTS_N_INSNS (1) + cost_data->int_cmov;
1423 case UNSIGNED_FLOAT:
1426 case FLOAT_TRUNCATE:
1427 *total = cost_data->fp_add;
1431 if (MEM_P (XEXP (x, 0)))
1434 *total = cost_data->fp_add;
1442 /* REF is an alignable memory location. Place an aligned SImode
1443 reference into *PALIGNED_MEM and the number of bits to shift into
1444 *PBITNUM. SCRATCH is a free register for use in reloading out
1445 of range stack slots. */
1448 get_aligned_mem (rtx ref, rtx *paligned_mem, rtx *pbitnum)
1451 HOST_WIDE_INT disp, offset;
1453 gcc_assert (MEM_P (ref));
1455 if (reload_in_progress
1456 && ! memory_address_p (GET_MODE (ref), XEXP (ref, 0)))
1458 base = find_replacement (&XEXP (ref, 0));
1459 gcc_assert (memory_address_p (GET_MODE (ref), base));
1462 base = XEXP (ref, 0);
1464 if (GET_CODE (base) == PLUS)
1465 disp = INTVAL (XEXP (base, 1)), base = XEXP (base, 0);
1469 /* Find the byte offset within an aligned word. If the memory itself is
1470 claimed to be aligned, believe it. Otherwise, aligned_memory_operand
1471 will have examined the base register and determined it is aligned, and
1472 thus displacements from it are naturally alignable. */
1473 if (MEM_ALIGN (ref) >= 32)
1478 /* The location should not cross aligned word boundary. */
1479 gcc_assert (offset + GET_MODE_SIZE (GET_MODE (ref))
1480 <= GET_MODE_SIZE (SImode));
1482 /* Access the entire aligned word. */
1483 *paligned_mem = widen_memory_access (ref, SImode, -offset);
1485 /* Convert the byte offset within the word to a bit offset. */
1486 if (WORDS_BIG_ENDIAN)
1487 offset = 32 - (GET_MODE_BITSIZE (GET_MODE (ref)) + offset * 8);
1490 *pbitnum = GEN_INT (offset);
1493 /* Similar, but just get the address. Handle the two reload cases.
1494 Add EXTRA_OFFSET to the address we return. */
1497 get_unaligned_address (rtx ref)
1500 HOST_WIDE_INT offset = 0;
1502 gcc_assert (MEM_P (ref));
1504 if (reload_in_progress
1505 && ! memory_address_p (GET_MODE (ref), XEXP (ref, 0)))
1507 base = find_replacement (&XEXP (ref, 0));
1509 gcc_assert (memory_address_p (GET_MODE (ref), base));
1512 base = XEXP (ref, 0);
1514 if (GET_CODE (base) == PLUS)
1515 offset += INTVAL (XEXP (base, 1)), base = XEXP (base, 0);
1517 return plus_constant (base, offset);
1520 /* Compute a value X, such that X & 7 == (ADDR + OFS) & 7.
1521 X is always returned in a register. */
1524 get_unaligned_offset (rtx addr, HOST_WIDE_INT ofs)
1526 if (GET_CODE (addr) == PLUS)
1528 ofs += INTVAL (XEXP (addr, 1));
1529 addr = XEXP (addr, 0);
1532 return expand_simple_binop (Pmode, PLUS, addr, GEN_INT (ofs & 7),
1533 NULL_RTX, 1, OPTAB_LIB_WIDEN);
1536 /* On the Alpha, all (non-symbolic) constants except zero go into
1537 a floating-point register via memory. Note that we cannot
1538 return anything that is not a subset of RCLASS, and that some
1539 symbolic constants cannot be dropped to memory. */
1542 alpha_preferred_reload_class(rtx x, enum reg_class rclass)
1544 /* Zero is present in any register class. */
1545 if (x == CONST0_RTX (GET_MODE (x)))
1548 /* These sorts of constants we can easily drop to memory. */
1550 || GET_CODE (x) == CONST_DOUBLE
1551 || GET_CODE (x) == CONST_VECTOR)
1553 if (rclass == FLOAT_REGS)
1555 if (rclass == ALL_REGS)
1556 return GENERAL_REGS;
1560 /* All other kinds of constants should not (and in the case of HIGH
1561 cannot) be dropped to memory -- instead we use a GENERAL_REGS
1562 secondary reload. */
1564 return (rclass == ALL_REGS ? GENERAL_REGS : rclass);
1569 /* Inform reload about cases where moving X with a mode MODE to a register in
1570 RCLASS requires an extra scratch or immediate register. Return the class
1571 needed for the immediate register. */
1574 alpha_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
1575 enum machine_mode mode, secondary_reload_info *sri)
1577 enum reg_class rclass = (enum reg_class) rclass_i;
1579 /* Loading and storing HImode or QImode values to and from memory
1580 usually requires a scratch register. */
1581 if (!TARGET_BWX && (mode == QImode || mode == HImode || mode == CQImode))
1583 if (any_memory_operand (x, mode))
1587 if (!aligned_memory_operand (x, mode))
1588 sri->icode = direct_optab_handler (reload_in_optab, mode);
1591 sri->icode = direct_optab_handler (reload_out_optab, mode);
1596 /* We also cannot do integral arithmetic into FP regs, as might result
1597 from register elimination into a DImode fp register. */
1598 if (rclass == FLOAT_REGS)
1600 if (MEM_P (x) && GET_CODE (XEXP (x, 0)) == AND)
1601 return GENERAL_REGS;
1602 if (in_p && INTEGRAL_MODE_P (mode)
1603 && !MEM_P (x) && !REG_P (x) && !CONST_INT_P (x))
1604 return GENERAL_REGS;
1610 /* Subfunction of the following function. Update the flags of any MEM
1611 found in part of X. */
1614 alpha_set_memflags_1 (rtx *xp, void *data)
1616 rtx x = *xp, orig = (rtx) data;
1621 MEM_VOLATILE_P (x) = MEM_VOLATILE_P (orig);
1622 MEM_IN_STRUCT_P (x) = MEM_IN_STRUCT_P (orig);
1623 MEM_SCALAR_P (x) = MEM_SCALAR_P (orig);
1624 MEM_NOTRAP_P (x) = MEM_NOTRAP_P (orig);
1625 MEM_READONLY_P (x) = MEM_READONLY_P (orig);
1627 /* Sadly, we cannot use alias sets because the extra aliasing
1628 produced by the AND interferes. Given that two-byte quantities
1629 are the only thing we would be able to differentiate anyway,
1630 there does not seem to be any point in convoluting the early
1631 out of the alias check. */
1636 /* Given SEQ, which is an INSN list, look for any MEMs in either
1637 a SET_DEST or a SET_SRC and copy the in-struct, unchanging, and
1638 volatile flags from REF into each of the MEMs found. If REF is not
1639 a MEM, don't do anything. */
1642 alpha_set_memflags (rtx seq, rtx ref)
1649 /* This is only called from alpha.md, after having had something
1650 generated from one of the insn patterns. So if everything is
1651 zero, the pattern is already up-to-date. */
1652 if (!MEM_VOLATILE_P (ref)
1653 && !MEM_IN_STRUCT_P (ref)
1654 && !MEM_SCALAR_P (ref)
1655 && !MEM_NOTRAP_P (ref)
1656 && !MEM_READONLY_P (ref))
1659 for (insn = seq; insn; insn = NEXT_INSN (insn))
1661 for_each_rtx (&PATTERN (insn), alpha_set_memflags_1, (void *) ref);
1666 static rtx alpha_emit_set_const (rtx, enum machine_mode, HOST_WIDE_INT,
1669 /* Internal routine for alpha_emit_set_const to check for N or below insns.
1670 If NO_OUTPUT is true, then we only check to see if N insns are possible,
1671 and return pc_rtx if successful. */
1674 alpha_emit_set_const_1 (rtx target, enum machine_mode mode,
1675 HOST_WIDE_INT c, int n, bool no_output)
1677 HOST_WIDE_INT new_const;
1679 /* Use a pseudo if highly optimizing and still generating RTL. */
1681 = (flag_expensive_optimizations && can_create_pseudo_p () ? 0 : target);
1684 /* If this is a sign-extended 32-bit constant, we can do this in at most
1685 three insns, so do it if we have enough insns left. We always have
1686 a sign-extended 32-bit constant when compiling on a narrow machine. */
1688 if (HOST_BITS_PER_WIDE_INT != 64
1689 || c >> 31 == -1 || c >> 31 == 0)
1691 HOST_WIDE_INT low = ((c & 0xffff) ^ 0x8000) - 0x8000;
1692 HOST_WIDE_INT tmp1 = c - low;
1693 HOST_WIDE_INT high = (((tmp1 >> 16) & 0xffff) ^ 0x8000) - 0x8000;
1694 HOST_WIDE_INT extra = 0;
1696 /* If HIGH will be interpreted as negative but the constant is
1697 positive, we must adjust it to do two ldha insns. */
1699 if ((high & 0x8000) != 0 && c >= 0)
1703 high = ((tmp1 >> 16) & 0xffff) - 2 * ((tmp1 >> 16) & 0x8000);
1706 if (c == low || (low == 0 && extra == 0))
1708 /* We used to use copy_to_suggested_reg (GEN_INT (c), target, mode)
1709 but that meant that we can't handle INT_MIN on 32-bit machines
1710 (like NT/Alpha), because we recurse indefinitely through
1711 emit_move_insn to gen_movdi. So instead, since we know exactly
1712 what we want, create it explicitly. */
1717 target = gen_reg_rtx (mode);
1718 emit_insn (gen_rtx_SET (VOIDmode, target, GEN_INT (c)));
1721 else if (n >= 2 + (extra != 0))
1725 if (!can_create_pseudo_p ())
1727 emit_insn (gen_rtx_SET (VOIDmode, target, GEN_INT (high << 16)));
1731 temp = copy_to_suggested_reg (GEN_INT (high << 16),
1734 /* As of 2002-02-23, addsi3 is only available when not optimizing.
1735 This means that if we go through expand_binop, we'll try to
1736 generate extensions, etc, which will require new pseudos, which
1737 will fail during some split phases. The SImode add patterns
1738 still exist, but are not named. So build the insns by hand. */
1743 subtarget = gen_reg_rtx (mode);
1744 insn = gen_rtx_PLUS (mode, temp, GEN_INT (extra << 16));
1745 insn = gen_rtx_SET (VOIDmode, subtarget, insn);
1751 target = gen_reg_rtx (mode);
1752 insn = gen_rtx_PLUS (mode, temp, GEN_INT (low));
1753 insn = gen_rtx_SET (VOIDmode, target, insn);
1759 /* If we couldn't do it that way, try some other methods. But if we have
1760 no instructions left, don't bother. Likewise, if this is SImode and
1761 we can't make pseudos, we can't do anything since the expand_binop
1762 and expand_unop calls will widen and try to make pseudos. */
1764 if (n == 1 || (mode == SImode && !can_create_pseudo_p ()))
1767 /* Next, see if we can load a related constant and then shift and possibly
1768 negate it to get the constant we want. Try this once each increasing
1769 numbers of insns. */
1771 for (i = 1; i < n; i++)
1773 /* First, see if minus some low bits, we've an easy load of
1776 new_const = ((c & 0xffff) ^ 0x8000) - 0x8000;
1779 temp = alpha_emit_set_const (subtarget, mode, c - new_const, i, no_output);
1784 return expand_binop (mode, add_optab, temp, GEN_INT (new_const),
1785 target, 0, OPTAB_WIDEN);
1789 /* Next try complementing. */
1790 temp = alpha_emit_set_const (subtarget, mode, ~c, i, no_output);
1795 return expand_unop (mode, one_cmpl_optab, temp, target, 0);
1798 /* Next try to form a constant and do a left shift. We can do this
1799 if some low-order bits are zero; the exact_log2 call below tells
1800 us that information. The bits we are shifting out could be any
1801 value, but here we'll just try the 0- and sign-extended forms of
1802 the constant. To try to increase the chance of having the same
1803 constant in more than one insn, start at the highest number of
1804 bits to shift, but try all possibilities in case a ZAPNOT will
1807 bits = exact_log2 (c & -c);
1809 for (; bits > 0; bits--)
1811 new_const = c >> bits;
1812 temp = alpha_emit_set_const (subtarget, mode, new_const, i, no_output);
1815 new_const = (unsigned HOST_WIDE_INT)c >> bits;
1816 temp = alpha_emit_set_const (subtarget, mode, new_const,
1823 return expand_binop (mode, ashl_optab, temp, GEN_INT (bits),
1824 target, 0, OPTAB_WIDEN);
1828 /* Now try high-order zero bits. Here we try the shifted-in bits as
1829 all zero and all ones. Be careful to avoid shifting outside the
1830 mode and to avoid shifting outside the host wide int size. */
1831 /* On narrow hosts, don't shift a 1 into the high bit, since we'll
1832 confuse the recursive call and set all of the high 32 bits. */
1834 bits = (MIN (HOST_BITS_PER_WIDE_INT, GET_MODE_SIZE (mode) * 8)
1835 - floor_log2 (c) - 1 - (HOST_BITS_PER_WIDE_INT < 64));
1837 for (; bits > 0; bits--)
1839 new_const = c << bits;
1840 temp = alpha_emit_set_const (subtarget, mode, new_const, i, no_output);
1843 new_const = (c << bits) | (((HOST_WIDE_INT) 1 << bits) - 1);
1844 temp = alpha_emit_set_const (subtarget, mode, new_const,
1851 return expand_binop (mode, lshr_optab, temp, GEN_INT (bits),
1852 target, 1, OPTAB_WIDEN);
1856 /* Now try high-order 1 bits. We get that with a sign-extension.
1857 But one bit isn't enough here. Be careful to avoid shifting outside
1858 the mode and to avoid shifting outside the host wide int size. */
1860 bits = (MIN (HOST_BITS_PER_WIDE_INT, GET_MODE_SIZE (mode) * 8)
1861 - floor_log2 (~ c) - 2);
1863 for (; bits > 0; bits--)
1865 new_const = c << bits;
1866 temp = alpha_emit_set_const (subtarget, mode, new_const, i, no_output);
1869 new_const = (c << bits) | (((HOST_WIDE_INT) 1 << bits) - 1);
1870 temp = alpha_emit_set_const (subtarget, mode, new_const,
1877 return expand_binop (mode, ashr_optab, temp, GEN_INT (bits),
1878 target, 0, OPTAB_WIDEN);
1883 #if HOST_BITS_PER_WIDE_INT == 64
1884 /* Finally, see if can load a value into the target that is the same as the
1885 constant except that all bytes that are 0 are changed to be 0xff. If we
1886 can, then we can do a ZAPNOT to obtain the desired constant. */
1889 for (i = 0; i < 64; i += 8)
1890 if ((new_const & ((HOST_WIDE_INT) 0xff << i)) == 0)
1891 new_const |= (HOST_WIDE_INT) 0xff << i;
1893 /* We are only called for SImode and DImode. If this is SImode, ensure that
1894 we are sign extended to a full word. */
1897 new_const = ((new_const & 0xffffffff) ^ 0x80000000) - 0x80000000;
1901 temp = alpha_emit_set_const (subtarget, mode, new_const, n - 1, no_output);
1906 return expand_binop (mode, and_optab, temp, GEN_INT (c | ~ new_const),
1907 target, 0, OPTAB_WIDEN);
1915 /* Try to output insns to set TARGET equal to the constant C if it can be
1916 done in less than N insns. Do all computations in MODE. Returns the place
1917 where the output has been placed if it can be done and the insns have been
1918 emitted. If it would take more than N insns, zero is returned and no
1919 insns and emitted. */
1922 alpha_emit_set_const (rtx target, enum machine_mode mode,
1923 HOST_WIDE_INT c, int n, bool no_output)
1925 enum machine_mode orig_mode = mode;
1926 rtx orig_target = target;
1930 /* If we can't make any pseudos, TARGET is an SImode hard register, we
1931 can't load this constant in one insn, do this in DImode. */
1932 if (!can_create_pseudo_p () && mode == SImode
1933 && REG_P (target) && REGNO (target) < FIRST_PSEUDO_REGISTER)
1935 result = alpha_emit_set_const_1 (target, mode, c, 1, no_output);
1939 target = no_output ? NULL : gen_lowpart (DImode, target);
1942 else if (mode == V8QImode || mode == V4HImode || mode == V2SImode)
1944 target = no_output ? NULL : gen_lowpart (DImode, target);
1948 /* Try 1 insn, then 2, then up to N. */
1949 for (i = 1; i <= n; i++)
1951 result = alpha_emit_set_const_1 (target, mode, c, i, no_output);
1959 insn = get_last_insn ();
1960 set = single_set (insn);
1961 if (! CONSTANT_P (SET_SRC (set)))
1962 set_unique_reg_note (get_last_insn (), REG_EQUAL, GEN_INT (c));
1967 /* Allow for the case where we changed the mode of TARGET. */
1970 if (result == target)
1971 result = orig_target;
1972 else if (mode != orig_mode)
1973 result = gen_lowpart (orig_mode, result);
1979 /* Having failed to find a 3 insn sequence in alpha_emit_set_const,
1980 fall back to a straight forward decomposition. We do this to avoid
1981 exponential run times encountered when looking for longer sequences
1982 with alpha_emit_set_const. */
1985 alpha_emit_set_long_const (rtx target, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
1987 HOST_WIDE_INT d1, d2, d3, d4;
1989 /* Decompose the entire word */
1990 #if HOST_BITS_PER_WIDE_INT >= 64
1991 gcc_assert (c2 == -(c1 < 0));
1992 d1 = ((c1 & 0xffff) ^ 0x8000) - 0x8000;
1994 d2 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000;
1995 c1 = (c1 - d2) >> 32;
1996 d3 = ((c1 & 0xffff) ^ 0x8000) - 0x8000;
1998 d4 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000;
1999 gcc_assert (c1 == d4);
2001 d1 = ((c1 & 0xffff) ^ 0x8000) - 0x8000;
2003 d2 = ((c1 & 0xffffffff) ^ 0x80000000) - 0x80000000;
2004 gcc_assert (c1 == d2);
2006 d3 = ((c2 & 0xffff) ^ 0x8000) - 0x8000;
2008 d4 = ((c2 & 0xffffffff) ^ 0x80000000) - 0x80000000;
2009 gcc_assert (c2 == d4);
2012 /* Construct the high word */
2015 emit_move_insn (target, GEN_INT (d4));
2017 emit_move_insn (target, gen_rtx_PLUS (DImode, target, GEN_INT (d3)));
2020 emit_move_insn (target, GEN_INT (d3));
2022 /* Shift it into place */
2023 emit_move_insn (target, gen_rtx_ASHIFT (DImode, target, GEN_INT (32)));
2025 /* Add in the low bits. */
2027 emit_move_insn (target, gen_rtx_PLUS (DImode, target, GEN_INT (d2)));
2029 emit_move_insn (target, gen_rtx_PLUS (DImode, target, GEN_INT (d1)));
2034 /* Given an integral CONST_INT, CONST_DOUBLE, or CONST_VECTOR, return
2038 alpha_extract_integer (rtx x, HOST_WIDE_INT *p0, HOST_WIDE_INT *p1)
2040 HOST_WIDE_INT i0, i1;
2042 if (GET_CODE (x) == CONST_VECTOR)
2043 x = simplify_subreg (DImode, x, GET_MODE (x), 0);
2046 if (CONST_INT_P (x))
2051 else if (HOST_BITS_PER_WIDE_INT >= 64)
2053 i0 = CONST_DOUBLE_LOW (x);
2058 i0 = CONST_DOUBLE_LOW (x);
2059 i1 = CONST_DOUBLE_HIGH (x);
2066 /* Implement LEGITIMATE_CONSTANT_P. This is all constants for which we
2067 are willing to load the value into a register via a move pattern.
2068 Normally this is all symbolic constants, integral constants that
2069 take three or fewer instructions, and floating-point zero. */
2072 alpha_legitimate_constant_p (rtx x)
2074 enum machine_mode mode = GET_MODE (x);
2075 HOST_WIDE_INT i0, i1;
2077 switch (GET_CODE (x))
2084 if (GET_CODE (XEXP (x, 0)) == PLUS
2085 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
2086 x = XEXP (XEXP (x, 0), 0);
2090 if (GET_CODE (x) != SYMBOL_REF)
2096 /* TLS symbols are never valid. */
2097 return SYMBOL_REF_TLS_MODEL (x) == 0;
2100 if (x == CONST0_RTX (mode))
2102 if (FLOAT_MODE_P (mode))
2107 if (x == CONST0_RTX (mode))
2109 if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT)
2111 if (GET_MODE_SIZE (mode) != 8)
2117 if (TARGET_BUILD_CONSTANTS)
2119 alpha_extract_integer (x, &i0, &i1);
2120 if (HOST_BITS_PER_WIDE_INT >= 64 || i1 == (-i0 < 0))
2121 return alpha_emit_set_const_1 (x, mode, i0, 3, true) != NULL;
2129 /* Operand 1 is known to be a constant, and should require more than one
2130 instruction to load. Emit that multi-part load. */
2133 alpha_split_const_mov (enum machine_mode mode, rtx *operands)
2135 HOST_WIDE_INT i0, i1;
2136 rtx temp = NULL_RTX;
2138 alpha_extract_integer (operands[1], &i0, &i1);
2140 if (HOST_BITS_PER_WIDE_INT >= 64 || i1 == -(i0 < 0))
2141 temp = alpha_emit_set_const (operands[0], mode, i0, 3, false);
2143 if (!temp && TARGET_BUILD_CONSTANTS)
2144 temp = alpha_emit_set_long_const (operands[0], i0, i1);
2148 if (!rtx_equal_p (operands[0], temp))
2149 emit_move_insn (operands[0], temp);
2156 /* Expand a move instruction; return true if all work is done.
2157 We don't handle non-bwx subword loads here. */
2160 alpha_expand_mov (enum machine_mode mode, rtx *operands)
2164 /* If the output is not a register, the input must be. */
2165 if (MEM_P (operands[0])
2166 && ! reg_or_0_operand (operands[1], mode))
2167 operands[1] = force_reg (mode, operands[1]);
2169 /* Allow legitimize_address to perform some simplifications. */
2170 if (mode == Pmode && symbolic_operand (operands[1], mode))
2172 tmp = alpha_legitimize_address_1 (operands[1], operands[0], mode);
2175 if (tmp == operands[0])
2182 /* Early out for non-constants and valid constants. */
2183 if (! CONSTANT_P (operands[1]) || input_operand (operands[1], mode))
2186 /* Split large integers. */
2187 if (CONST_INT_P (operands[1])
2188 || GET_CODE (operands[1]) == CONST_DOUBLE
2189 || GET_CODE (operands[1]) == CONST_VECTOR)
2191 if (alpha_split_const_mov (mode, operands))
2195 /* Otherwise we've nothing left but to drop the thing to memory. */
2196 tmp = force_const_mem (mode, operands[1]);
2198 if (tmp == NULL_RTX)
2201 if (reload_in_progress)
2203 emit_move_insn (operands[0], XEXP (tmp, 0));
2204 operands[1] = replace_equiv_address (tmp, operands[0]);
2207 operands[1] = validize_mem (tmp);
2211 /* Expand a non-bwx QImode or HImode move instruction;
2212 return true if all work is done. */
2215 alpha_expand_mov_nobwx (enum machine_mode mode, rtx *operands)
2219 /* If the output is not a register, the input must be. */
2220 if (MEM_P (operands[0]))
2221 operands[1] = force_reg (mode, operands[1]);
2223 /* Handle four memory cases, unaligned and aligned for either the input
2224 or the output. The only case where we can be called during reload is
2225 for aligned loads; all other cases require temporaries. */
2227 if (any_memory_operand (operands[1], mode))
2229 if (aligned_memory_operand (operands[1], mode))
2231 if (reload_in_progress)
2234 seq = gen_reload_inqi_aligned (operands[0], operands[1]);
2236 seq = gen_reload_inhi_aligned (operands[0], operands[1]);
2241 rtx aligned_mem, bitnum;
2242 rtx scratch = gen_reg_rtx (SImode);
2246 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
2248 subtarget = operands[0];
2249 if (REG_P (subtarget))
2250 subtarget = gen_lowpart (DImode, subtarget), copyout = false;
2252 subtarget = gen_reg_rtx (DImode), copyout = true;
2255 seq = gen_aligned_loadqi (subtarget, aligned_mem,
2258 seq = gen_aligned_loadhi (subtarget, aligned_mem,
2263 emit_move_insn (operands[0], gen_lowpart (mode, subtarget));
2268 /* Don't pass these as parameters since that makes the generated
2269 code depend on parameter evaluation order which will cause
2270 bootstrap failures. */
2272 rtx temp1, temp2, subtarget, ua;
2275 temp1 = gen_reg_rtx (DImode);
2276 temp2 = gen_reg_rtx (DImode);
2278 subtarget = operands[0];
2279 if (REG_P (subtarget))
2280 subtarget = gen_lowpart (DImode, subtarget), copyout = false;
2282 subtarget = gen_reg_rtx (DImode), copyout = true;
2284 ua = get_unaligned_address (operands[1]);
2286 seq = gen_unaligned_loadqi (subtarget, ua, temp1, temp2);
2288 seq = gen_unaligned_loadhi (subtarget, ua, temp1, temp2);
2290 alpha_set_memflags (seq, operands[1]);
2294 emit_move_insn (operands[0], gen_lowpart (mode, subtarget));
2299 if (any_memory_operand (operands[0], mode))
2301 if (aligned_memory_operand (operands[0], mode))
2303 rtx aligned_mem, bitnum;
2304 rtx temp1 = gen_reg_rtx (SImode);
2305 rtx temp2 = gen_reg_rtx (SImode);
2307 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
2309 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
2314 rtx temp1 = gen_reg_rtx (DImode);
2315 rtx temp2 = gen_reg_rtx (DImode);
2316 rtx temp3 = gen_reg_rtx (DImode);
2317 rtx ua = get_unaligned_address (operands[0]);
2320 seq = gen_unaligned_storeqi (ua, operands[1], temp1, temp2, temp3);
2322 seq = gen_unaligned_storehi (ua, operands[1], temp1, temp2, temp3);
2324 alpha_set_memflags (seq, operands[0]);
2333 /* Implement the movmisalign patterns. One of the operands is a memory
2334 that is not naturally aligned. Emit instructions to load it. */
2337 alpha_expand_movmisalign (enum machine_mode mode, rtx *operands)
2339 /* Honor misaligned loads, for those we promised to do so. */
2340 if (MEM_P (operands[1]))
2344 if (register_operand (operands[0], mode))
2347 tmp = gen_reg_rtx (mode);
2349 alpha_expand_unaligned_load (tmp, operands[1], 8, 0, 0);
2350 if (tmp != operands[0])
2351 emit_move_insn (operands[0], tmp);
2353 else if (MEM_P (operands[0]))
2355 if (!reg_or_0_operand (operands[1], mode))
2356 operands[1] = force_reg (mode, operands[1]);
2357 alpha_expand_unaligned_store (operands[0], operands[1], 8, 0);
2363 /* Generate an unsigned DImode to FP conversion. This is the same code
2364 optabs would emit if we didn't have TFmode patterns.
2366 For SFmode, this is the only construction I've found that can pass
2367 gcc.c-torture/execute/ieee/rbug.c. No scenario that uses DFmode
2368 intermediates will work, because you'll get intermediate rounding
2369 that ruins the end result. Some of this could be fixed by turning
2370 on round-to-positive-infinity, but that requires diddling the fpsr,
2371 which kills performance. I tried turning this around and converting
2372 to a negative number, so that I could turn on /m, but either I did
2373 it wrong or there's something else cause I wound up with the exact
2374 same single-bit error. There is a branch-less form of this same code:
2385 fcmoveq $f10,$f11,$f0
2387 I'm not using it because it's the same number of instructions as
2388 this branch-full form, and it has more serialized long latency
2389 instructions on the critical path.
2391 For DFmode, we can avoid rounding errors by breaking up the word
2392 into two pieces, converting them separately, and adding them back:
2394 LC0: .long 0,0x5f800000
2399 cpyse $f11,$f31,$f10
2400 cpyse $f31,$f11,$f11
2408 This doesn't seem to be a clear-cut win over the optabs form.
2409 It probably all depends on the distribution of numbers being
2410 converted -- in the optabs form, all but high-bit-set has a
2411 much lower minimum execution time. */
2414 alpha_emit_floatuns (rtx operands[2])
2416 rtx neglab, donelab, i0, i1, f0, in, out;
2417 enum machine_mode mode;
2420 in = force_reg (DImode, operands[1]);
2421 mode = GET_MODE (out);
2422 neglab = gen_label_rtx ();
2423 donelab = gen_label_rtx ();
2424 i0 = gen_reg_rtx (DImode);
2425 i1 = gen_reg_rtx (DImode);
2426 f0 = gen_reg_rtx (mode);
2428 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, DImode, 0, neglab);
2430 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_FLOAT (mode, in)));
2431 emit_jump_insn (gen_jump (donelab));
2434 emit_label (neglab);
2436 emit_insn (gen_lshrdi3 (i0, in, const1_rtx));
2437 emit_insn (gen_anddi3 (i1, in, const1_rtx));
2438 emit_insn (gen_iordi3 (i0, i0, i1));
2439 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_FLOAT (mode, i0)));
2440 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
2442 emit_label (donelab);
2445 /* Generate the comparison for a conditional branch. */
2448 alpha_emit_conditional_branch (rtx operands[], enum machine_mode cmp_mode)
2450 enum rtx_code cmp_code, branch_code;
2451 enum machine_mode branch_mode = VOIDmode;
2452 enum rtx_code code = GET_CODE (operands[0]);
2453 rtx op0 = operands[1], op1 = operands[2];
2456 if (cmp_mode == TFmode)
2458 op0 = alpha_emit_xfloating_compare (&code, op0, op1);
2463 /* The general case: fold the comparison code to the types of compares
2464 that we have, choosing the branch as necessary. */
2467 case EQ: case LE: case LT: case LEU: case LTU:
2469 /* We have these compares: */
2470 cmp_code = code, branch_code = NE;
2475 /* These must be reversed. */
2476 cmp_code = reverse_condition (code), branch_code = EQ;
2479 case GE: case GT: case GEU: case GTU:
2480 /* For FP, we swap them, for INT, we reverse them. */
2481 if (cmp_mode == DFmode)
2483 cmp_code = swap_condition (code);
2485 tem = op0, op0 = op1, op1 = tem;
2489 cmp_code = reverse_condition (code);
2498 if (cmp_mode == DFmode)
2500 if (flag_unsafe_math_optimizations && cmp_code != UNORDERED)
2502 /* When we are not as concerned about non-finite values, and we
2503 are comparing against zero, we can branch directly. */
2504 if (op1 == CONST0_RTX (DFmode))
2505 cmp_code = UNKNOWN, branch_code = code;
2506 else if (op0 == CONST0_RTX (DFmode))
2508 /* Undo the swap we probably did just above. */
2509 tem = op0, op0 = op1, op1 = tem;
2510 branch_code = swap_condition (cmp_code);
2516 /* ??? We mark the branch mode to be CCmode to prevent the
2517 compare and branch from being combined, since the compare
2518 insn follows IEEE rules that the branch does not. */
2519 branch_mode = CCmode;
2524 /* The following optimizations are only for signed compares. */
2525 if (code != LEU && code != LTU && code != GEU && code != GTU)
2527 /* Whee. Compare and branch against 0 directly. */
2528 if (op1 == const0_rtx)
2529 cmp_code = UNKNOWN, branch_code = code;
2531 /* If the constants doesn't fit into an immediate, but can
2532 be generated by lda/ldah, we adjust the argument and
2533 compare against zero, so we can use beq/bne directly. */
2534 /* ??? Don't do this when comparing against symbols, otherwise
2535 we'll reduce (&x == 0x1234) to (&x-0x1234 == 0), which will
2536 be declared false out of hand (at least for non-weak). */
2537 else if (CONST_INT_P (op1)
2538 && (code == EQ || code == NE)
2539 && !(symbolic_operand (op0, VOIDmode)
2540 || (REG_P (op0) && REG_POINTER (op0))))
2542 rtx n_op1 = GEN_INT (-INTVAL (op1));
2544 if (! satisfies_constraint_I (op1)
2545 && (satisfies_constraint_K (n_op1)
2546 || satisfies_constraint_L (n_op1)))
2547 cmp_code = PLUS, branch_code = code, op1 = n_op1;
2551 if (!reg_or_0_operand (op0, DImode))
2552 op0 = force_reg (DImode, op0);
2553 if (cmp_code != PLUS && !reg_or_8bit_operand (op1, DImode))
2554 op1 = force_reg (DImode, op1);
2557 /* Emit an initial compare instruction, if necessary. */
2559 if (cmp_code != UNKNOWN)
2561 tem = gen_reg_rtx (cmp_mode);
2562 emit_move_insn (tem, gen_rtx_fmt_ee (cmp_code, cmp_mode, op0, op1));
2565 /* Emit the branch instruction. */
2566 tem = gen_rtx_SET (VOIDmode, pc_rtx,
2567 gen_rtx_IF_THEN_ELSE (VOIDmode,
2568 gen_rtx_fmt_ee (branch_code,
2570 CONST0_RTX (cmp_mode)),
2571 gen_rtx_LABEL_REF (VOIDmode,
2574 emit_jump_insn (tem);
2577 /* Certain simplifications can be done to make invalid setcc operations
2578 valid. Return the final comparison, or NULL if we can't work. */
2581 alpha_emit_setcc (rtx operands[], enum machine_mode cmp_mode)
2583 enum rtx_code cmp_code;
2584 enum rtx_code code = GET_CODE (operands[1]);
2585 rtx op0 = operands[2], op1 = operands[3];
2588 if (cmp_mode == TFmode)
2590 op0 = alpha_emit_xfloating_compare (&code, op0, op1);
2595 if (cmp_mode == DFmode && !TARGET_FIX)
2598 /* The general case: fold the comparison code to the types of compares
2599 that we have, choosing the branch as necessary. */
2604 case EQ: case LE: case LT: case LEU: case LTU:
2606 /* We have these compares. */
2607 if (cmp_mode == DFmode)
2608 cmp_code = code, code = NE;
2612 if (cmp_mode == DImode && op1 == const0_rtx)
2617 cmp_code = reverse_condition (code);
2621 case GE: case GT: case GEU: case GTU:
2622 /* These normally need swapping, but for integer zero we have
2623 special patterns that recognize swapped operands. */
2624 if (cmp_mode == DImode && op1 == const0_rtx)
2626 code = swap_condition (code);
2627 if (cmp_mode == DFmode)
2628 cmp_code = code, code = NE;
2629 tmp = op0, op0 = op1, op1 = tmp;
2636 if (cmp_mode == DImode)
2638 if (!register_operand (op0, DImode))
2639 op0 = force_reg (DImode, op0);
2640 if (!reg_or_8bit_operand (op1, DImode))
2641 op1 = force_reg (DImode, op1);
2644 /* Emit an initial compare instruction, if necessary. */
2645 if (cmp_code != UNKNOWN)
2647 tmp = gen_reg_rtx (cmp_mode);
2648 emit_insn (gen_rtx_SET (VOIDmode, tmp,
2649 gen_rtx_fmt_ee (cmp_code, cmp_mode, op0, op1)));
2651 op0 = cmp_mode != DImode ? gen_lowpart (DImode, tmp) : tmp;
2655 /* Emit the setcc instruction. */
2656 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2657 gen_rtx_fmt_ee (code, DImode, op0, op1)));
2662 /* Rewrite a comparison against zero CMP of the form
2663 (CODE (cc0) (const_int 0)) so it can be written validly in
2664 a conditional move (if_then_else CMP ...).
2665 If both of the operands that set cc0 are nonzero we must emit
2666 an insn to perform the compare (it can't be done within
2667 the conditional move). */
2670 alpha_emit_conditional_move (rtx cmp, enum machine_mode mode)
2672 enum rtx_code code = GET_CODE (cmp);
2673 enum rtx_code cmov_code = NE;
2674 rtx op0 = XEXP (cmp, 0);
2675 rtx op1 = XEXP (cmp, 1);
2676 enum machine_mode cmp_mode
2677 = (GET_MODE (op0) == VOIDmode ? DImode : GET_MODE (op0));
2678 enum machine_mode cmov_mode = VOIDmode;
2679 int local_fast_math = flag_unsafe_math_optimizations;
2682 if (cmp_mode == TFmode)
2684 op0 = alpha_emit_xfloating_compare (&code, op0, op1);
2689 gcc_assert (cmp_mode == DFmode || cmp_mode == DImode);
2691 if (FLOAT_MODE_P (cmp_mode) != FLOAT_MODE_P (mode))
2693 enum rtx_code cmp_code;
2698 /* If we have fp<->int register move instructions, do a cmov by
2699 performing the comparison in fp registers, and move the
2700 zero/nonzero value to integer registers, where we can then
2701 use a normal cmov, or vice-versa. */
2705 case EQ: case LE: case LT: case LEU: case LTU:
2706 /* We have these compares. */
2707 cmp_code = code, code = NE;
2711 /* This must be reversed. */
2712 cmp_code = EQ, code = EQ;
2715 case GE: case GT: case GEU: case GTU:
2716 /* These normally need swapping, but for integer zero we have
2717 special patterns that recognize swapped operands. */
2718 if (cmp_mode == DImode && op1 == const0_rtx)
2719 cmp_code = code, code = NE;
2722 cmp_code = swap_condition (code);
2724 tem = op0, op0 = op1, op1 = tem;
2732 tem = gen_reg_rtx (cmp_mode);
2733 emit_insn (gen_rtx_SET (VOIDmode, tem,
2734 gen_rtx_fmt_ee (cmp_code, cmp_mode,
2737 cmp_mode = cmp_mode == DImode ? DFmode : DImode;
2738 op0 = gen_lowpart (cmp_mode, tem);
2739 op1 = CONST0_RTX (cmp_mode);
2740 local_fast_math = 1;
2743 /* We may be able to use a conditional move directly.
2744 This avoids emitting spurious compares. */
2745 if (signed_comparison_operator (cmp, VOIDmode)
2746 && (cmp_mode == DImode || local_fast_math)
2747 && (op0 == CONST0_RTX (cmp_mode) || op1 == CONST0_RTX (cmp_mode)))
2748 return gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
2750 /* We can't put the comparison inside the conditional move;
2751 emit a compare instruction and put that inside the
2752 conditional move. Make sure we emit only comparisons we have;
2753 swap or reverse as necessary. */
2755 if (!can_create_pseudo_p ())
2760 case EQ: case LE: case LT: case LEU: case LTU:
2761 /* We have these compares: */
2765 /* This must be reversed. */
2766 code = reverse_condition (code);
2770 case GE: case GT: case GEU: case GTU:
2771 /* These must be swapped. */
2772 if (op1 != CONST0_RTX (cmp_mode))
2774 code = swap_condition (code);
2775 tem = op0, op0 = op1, op1 = tem;
2783 if (cmp_mode == DImode)
2785 if (!reg_or_0_operand (op0, DImode))
2786 op0 = force_reg (DImode, op0);
2787 if (!reg_or_8bit_operand (op1, DImode))
2788 op1 = force_reg (DImode, op1);
2791 /* ??? We mark the branch mode to be CCmode to prevent the compare
2792 and cmov from being combined, since the compare insn follows IEEE
2793 rules that the cmov does not. */
2794 if (cmp_mode == DFmode && !local_fast_math)
2797 tem = gen_reg_rtx (cmp_mode);
2798 emit_move_insn (tem, gen_rtx_fmt_ee (code, cmp_mode, op0, op1));
2799 return gen_rtx_fmt_ee (cmov_code, cmov_mode, tem, CONST0_RTX (cmp_mode));
2802 /* Simplify a conditional move of two constants into a setcc with
2803 arithmetic. This is done with a splitter since combine would
2804 just undo the work if done during code generation. It also catches
2805 cases we wouldn't have before cse. */
2808 alpha_split_conditional_move (enum rtx_code code, rtx dest, rtx cond,
2809 rtx t_rtx, rtx f_rtx)
2811 HOST_WIDE_INT t, f, diff;
2812 enum machine_mode mode;
2813 rtx target, subtarget, tmp;
2815 mode = GET_MODE (dest);
2820 if (((code == NE || code == EQ) && diff < 0)
2821 || (code == GE || code == GT))
2823 code = reverse_condition (code);
2824 diff = t, t = f, f = diff;
2828 subtarget = target = dest;
2831 target = gen_lowpart (DImode, dest);
2832 if (can_create_pseudo_p ())
2833 subtarget = gen_reg_rtx (DImode);
2837 /* Below, we must be careful to use copy_rtx on target and subtarget
2838 in intermediate insns, as they may be a subreg rtx, which may not
2841 if (f == 0 && exact_log2 (diff) > 0
2842 /* On EV6, we've got enough shifters to make non-arithmetic shifts
2843 viable over a longer latency cmove. On EV5, the E0 slot is a
2844 scarce resource, and on EV4 shift has the same latency as a cmove. */
2845 && (diff <= 8 || alpha_tune == PROCESSOR_EV6))
2847 tmp = gen_rtx_fmt_ee (code, DImode, cond, const0_rtx);
2848 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (subtarget), tmp));
2850 tmp = gen_rtx_ASHIFT (DImode, copy_rtx (subtarget),
2851 GEN_INT (exact_log2 (t)));
2852 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
2854 else if (f == 0 && t == -1)
2856 tmp = gen_rtx_fmt_ee (code, DImode, cond, const0_rtx);
2857 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (subtarget), tmp));
2859 emit_insn (gen_negdi2 (target, copy_rtx (subtarget)));
2861 else if (diff == 1 || diff == 4 || diff == 8)
2865 tmp = gen_rtx_fmt_ee (code, DImode, cond, const0_rtx);
2866 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (subtarget), tmp));
2869 emit_insn (gen_adddi3 (target, copy_rtx (subtarget), GEN_INT (f)));
2872 add_op = GEN_INT (f);
2873 if (sext_add_operand (add_op, mode))
2875 tmp = gen_rtx_MULT (DImode, copy_rtx (subtarget),
2877 tmp = gen_rtx_PLUS (DImode, tmp, add_op);
2878 emit_insn (gen_rtx_SET (VOIDmode, target, tmp));
2890 /* Look up the function X_floating library function name for the
2893 struct GTY(()) xfloating_op
2895 const enum rtx_code code;
2896 const char *const GTY((skip)) osf_func;
2897 const char *const GTY((skip)) vms_func;
2901 static GTY(()) struct xfloating_op xfloating_ops[] =
2903 { PLUS, "_OtsAddX", "OTS$ADD_X", 0 },
2904 { MINUS, "_OtsSubX", "OTS$SUB_X", 0 },
2905 { MULT, "_OtsMulX", "OTS$MUL_X", 0 },
2906 { DIV, "_OtsDivX", "OTS$DIV_X", 0 },
2907 { EQ, "_OtsEqlX", "OTS$EQL_X", 0 },
2908 { NE, "_OtsNeqX", "OTS$NEQ_X", 0 },
2909 { LT, "_OtsLssX", "OTS$LSS_X", 0 },
2910 { LE, "_OtsLeqX", "OTS$LEQ_X", 0 },
2911 { GT, "_OtsGtrX", "OTS$GTR_X", 0 },
2912 { GE, "_OtsGeqX", "OTS$GEQ_X", 0 },
2913 { FIX, "_OtsCvtXQ", "OTS$CVTXQ", 0 },
2914 { FLOAT, "_OtsCvtQX", "OTS$CVTQX", 0 },
2915 { UNSIGNED_FLOAT, "_OtsCvtQUX", "OTS$CVTQUX", 0 },
2916 { FLOAT_EXTEND, "_OtsConvertFloatTX", "OTS$CVT_FLOAT_T_X", 0 },
2917 { FLOAT_TRUNCATE, "_OtsConvertFloatXT", "OTS$CVT_FLOAT_X_T", 0 }
2920 static GTY(()) struct xfloating_op vax_cvt_ops[] =
2922 { FLOAT_EXTEND, "_OtsConvertFloatGX", "OTS$CVT_FLOAT_G_X", 0 },
2923 { FLOAT_TRUNCATE, "_OtsConvertFloatXG", "OTS$CVT_FLOAT_X_G", 0 }
2927 alpha_lookup_xfloating_lib_func (enum rtx_code code)
2929 struct xfloating_op *ops = xfloating_ops;
2930 long n = ARRAY_SIZE (xfloating_ops);
2933 gcc_assert (TARGET_HAS_XFLOATING_LIBS);
2935 /* How irritating. Nothing to key off for the main table. */
2936 if (TARGET_FLOAT_VAX && (code == FLOAT_EXTEND || code == FLOAT_TRUNCATE))
2939 n = ARRAY_SIZE (vax_cvt_ops);
2942 for (i = 0; i < n; ++i, ++ops)
2943 if (ops->code == code)
2945 rtx func = ops->libcall;
2948 func = init_one_libfunc (TARGET_ABI_OPEN_VMS
2949 ? ops->vms_func : ops->osf_func);
2950 ops->libcall = func;
2958 /* Most X_floating operations take the rounding mode as an argument.
2959 Compute that here. */
2962 alpha_compute_xfloating_mode_arg (enum rtx_code code,
2963 enum alpha_fp_rounding_mode round)
2969 case ALPHA_FPRM_NORM:
2972 case ALPHA_FPRM_MINF:
2975 case ALPHA_FPRM_CHOP:
2978 case ALPHA_FPRM_DYN:
2984 /* XXX For reference, round to +inf is mode = 3. */
2987 if (code == FLOAT_TRUNCATE && alpha_fptm == ALPHA_FPTM_N)
2993 /* Emit an X_floating library function call.
2995 Note that these functions do not follow normal calling conventions:
2996 TFmode arguments are passed in two integer registers (as opposed to
2997 indirect); TFmode return values appear in R16+R17.
2999 FUNC is the function to call.
3000 TARGET is where the output belongs.
3001 OPERANDS are the inputs.
3002 NOPERANDS is the count of inputs.
3003 EQUIV is the expression equivalent for the function.
3007 alpha_emit_xfloating_libcall (rtx func, rtx target, rtx operands[],
3008 int noperands, rtx equiv)
3010 rtx usage = NULL_RTX, tmp, reg;
3015 for (i = 0; i < noperands; ++i)
3017 switch (GET_MODE (operands[i]))
3020 reg = gen_rtx_REG (TFmode, regno);
3025 reg = gen_rtx_REG (DFmode, regno + 32);
3030 gcc_assert (CONST_INT_P (operands[i]));
3033 reg = gen_rtx_REG (DImode, regno);
3041 emit_move_insn (reg, operands[i]);
3042 usage = alloc_EXPR_LIST (0, gen_rtx_USE (VOIDmode, reg), usage);
3045 switch (GET_MODE (target))
3048 reg = gen_rtx_REG (TFmode, 16);
3051 reg = gen_rtx_REG (DFmode, 32);
3054 reg = gen_rtx_REG (DImode, 0);
3060 tmp = gen_rtx_MEM (QImode, func);
3061 tmp = emit_call_insn (GEN_CALL_VALUE (reg, tmp, const0_rtx,
3062 const0_rtx, const0_rtx));
3063 CALL_INSN_FUNCTION_USAGE (tmp) = usage;
3064 RTL_CONST_CALL_P (tmp) = 1;
3069 emit_libcall_block (tmp, target, reg, equiv);
3072 /* Emit an X_floating library function call for arithmetic (+,-,*,/). */
3075 alpha_emit_xfloating_arith (enum rtx_code code, rtx operands[])
3079 rtx out_operands[3];
3081 func = alpha_lookup_xfloating_lib_func (code);
3082 mode = alpha_compute_xfloating_mode_arg (code, alpha_fprm);
3084 out_operands[0] = operands[1];
3085 out_operands[1] = operands[2];
3086 out_operands[2] = GEN_INT (mode);
3087 alpha_emit_xfloating_libcall (func, operands[0], out_operands, 3,
3088 gen_rtx_fmt_ee (code, TFmode, operands[1],
3092 /* Emit an X_floating library function call for a comparison. */
3095 alpha_emit_xfloating_compare (enum rtx_code *pcode, rtx op0, rtx op1)
3097 enum rtx_code cmp_code, res_code;
3098 rtx func, out, operands[2], note;
3100 /* X_floating library comparison functions return
3104 Convert the compare against the raw return value. */
3132 func = alpha_lookup_xfloating_lib_func (cmp_code);
3136 out = gen_reg_rtx (DImode);
3138 /* What's actually returned is -1,0,1, not a proper boolean value,
3139 so use an EXPR_LIST as with a generic libcall instead of a
3140 comparison type expression. */
3141 note = gen_rtx_EXPR_LIST (VOIDmode, op1, NULL_RTX);
3142 note = gen_rtx_EXPR_LIST (VOIDmode, op0, note);
3143 note = gen_rtx_EXPR_LIST (VOIDmode, func, note);
3144 alpha_emit_xfloating_libcall (func, out, operands, 2, note);
3149 /* Emit an X_floating library function call for a conversion. */
3152 alpha_emit_xfloating_cvt (enum rtx_code orig_code, rtx operands[])
3154 int noperands = 1, mode;
3155 rtx out_operands[2];
3157 enum rtx_code code = orig_code;
3159 if (code == UNSIGNED_FIX)
3162 func = alpha_lookup_xfloating_lib_func (code);
3164 out_operands[0] = operands[1];
3169 mode = alpha_compute_xfloating_mode_arg (code, ALPHA_FPRM_CHOP);
3170 out_operands[1] = GEN_INT (mode);
3173 case FLOAT_TRUNCATE:
3174 mode = alpha_compute_xfloating_mode_arg (code, alpha_fprm);
3175 out_operands[1] = GEN_INT (mode);
3182 alpha_emit_xfloating_libcall (func, operands[0], out_operands, noperands,
3183 gen_rtx_fmt_e (orig_code,
3184 GET_MODE (operands[0]),
3188 /* Split a TImode or TFmode move from OP[1] to OP[0] into a pair of
3189 DImode moves from OP[2,3] to OP[0,1]. If FIXUP_OVERLAP is true,
3190 guarantee that the sequence
3193 is valid. Naturally, output operand ordering is little-endian.
3194 This is used by *movtf_internal and *movti_internal. */
3197 alpha_split_tmode_pair (rtx operands[4], enum machine_mode mode,
3200 switch (GET_CODE (operands[1]))
3203 operands[3] = gen_rtx_REG (DImode, REGNO (operands[1]) + 1);
3204 operands[2] = gen_rtx_REG (DImode, REGNO (operands[1]));
3208 operands[3] = adjust_address (operands[1], DImode, 8);
3209 operands[2] = adjust_address (operands[1], DImode, 0);
3214 gcc_assert (operands[1] == CONST0_RTX (mode));
3215 operands[2] = operands[3] = const0_rtx;
3222 switch (GET_CODE (operands[0]))
3225 operands[1] = gen_rtx_REG (DImode, REGNO (operands[0]) + 1);
3226 operands[0] = gen_rtx_REG (DImode, REGNO (operands[0]));
3230 operands[1] = adjust_address (operands[0], DImode, 8);
3231 operands[0] = adjust_address (operands[0], DImode, 0);
3238 if (fixup_overlap && reg_overlap_mentioned_p (operands[0], operands[3]))
3241 tmp = operands[0], operands[0] = operands[1], operands[1] = tmp;
3242 tmp = operands[2], operands[2] = operands[3], operands[3] = tmp;
3246 /* Implement negtf2 or abstf2. Op0 is destination, op1 is source,
3247 op2 is a register containing the sign bit, operation is the
3248 logical operation to be performed. */
3251 alpha_split_tfmode_frobsign (rtx operands[3], rtx (*operation) (rtx, rtx, rtx))
3253 rtx high_bit = operands[2];
3257 alpha_split_tmode_pair (operands, TFmode, false);
3259 /* Detect three flavors of operand overlap. */
3261 if (rtx_equal_p (operands[0], operands[2]))
3263 else if (rtx_equal_p (operands[1], operands[2]))
3265 if (rtx_equal_p (operands[0], high_bit))
3272 emit_move_insn (operands[0], operands[2]);
3274 /* ??? If the destination overlaps both source tf and high_bit, then
3275 assume source tf is dead in its entirety and use the other half
3276 for a scratch register. Otherwise "scratch" is just the proper
3277 destination register. */
3278 scratch = operands[move < 2 ? 1 : 3];
3280 emit_insn ((*operation) (scratch, high_bit, operands[3]));
3284 emit_move_insn (operands[0], operands[2]);
3286 emit_move_insn (operands[1], scratch);
3290 /* Use ext[wlq][lh] as the Architecture Handbook describes for extracting
3294 word: ldq_u r1,X(r11) ldq_u r1,X(r11)
3295 ldq_u r2,X+1(r11) ldq_u r2,X+1(r11)
3296 lda r3,X(r11) lda r3,X+2(r11)
3297 extwl r1,r3,r1 extql r1,r3,r1
3298 extwh r2,r3,r2 extqh r2,r3,r2
3299 or r1.r2.r1 or r1,r2,r1
3302 long: ldq_u r1,X(r11) ldq_u r1,X(r11)
3303 ldq_u r2,X+3(r11) ldq_u r2,X+3(r11)
3304 lda r3,X(r11) lda r3,X(r11)
3305 extll r1,r3,r1 extll r1,r3,r1
3306 extlh r2,r3,r2 extlh r2,r3,r2
3307 or r1.r2.r1 addl r1,r2,r1
3309 quad: ldq_u r1,X(r11)
3318 alpha_expand_unaligned_load (rtx tgt, rtx mem, HOST_WIDE_INT size,
3319 HOST_WIDE_INT ofs, int sign)
3321 rtx meml, memh, addr, extl, exth, tmp, mema;
3322 enum machine_mode mode;
3324 if (TARGET_BWX && size == 2)
3326 meml = adjust_address (mem, QImode, ofs);
3327 memh = adjust_address (mem, QImode, ofs+1);
3328 if (BYTES_BIG_ENDIAN)
3329 tmp = meml, meml = memh, memh = tmp;
3330 extl = gen_reg_rtx (DImode);
3331 exth = gen_reg_rtx (DImode);
3332 emit_insn (gen_zero_extendqidi2 (extl, meml));
3333 emit_insn (gen_zero_extendqidi2 (exth, memh));
3334 exth = expand_simple_binop (DImode, ASHIFT, exth, GEN_INT (8),
3335 NULL, 1, OPTAB_LIB_WIDEN);
3336 addr = expand_simple_binop (DImode, IOR, extl, exth,
3337 NULL, 1, OPTAB_LIB_WIDEN);
3339 if (sign && GET_MODE (tgt) != HImode)
3341 addr = gen_lowpart (HImode, addr);
3342 emit_insn (gen_extend_insn (tgt, addr, GET_MODE (tgt), HImode, 0));
3346 if (GET_MODE (tgt) != DImode)
3347 addr = gen_lowpart (GET_MODE (tgt), addr);
3348 emit_move_insn (tgt, addr);
3353 meml = gen_reg_rtx (DImode);
3354 memh = gen_reg_rtx (DImode);
3355 addr = gen_reg_rtx (DImode);
3356 extl = gen_reg_rtx (DImode);
3357 exth = gen_reg_rtx (DImode);
3359 mema = XEXP (mem, 0);
3360 if (GET_CODE (mema) == LO_SUM)
3361 mema = force_reg (Pmode, mema);
3363 /* AND addresses cannot be in any alias set, since they may implicitly
3364 alias surrounding code. Ideally we'd have some alias set that
3365 covered all types except those with alignment 8 or higher. */
3367 tmp = change_address (mem, DImode,
3368 gen_rtx_AND (DImode,
3369 plus_constant (mema, ofs),
3371 set_mem_alias_set (tmp, 0);
3372 emit_move_insn (meml, tmp);
3374 tmp = change_address (mem, DImode,
3375 gen_rtx_AND (DImode,
3376 plus_constant (mema, ofs + size - 1),
3378 set_mem_alias_set (tmp, 0);
3379 emit_move_insn (memh, tmp);
3381 if (WORDS_BIG_ENDIAN && sign && (size == 2 || size == 4))
3383 emit_move_insn (addr, plus_constant (mema, -1));
3385 emit_insn (gen_extqh_be (extl, meml, addr));
3386 emit_insn (gen_extxl_be (exth, memh, GEN_INT (64), addr));
3388 addr = expand_binop (DImode, ior_optab, extl, exth, tgt, 1, OPTAB_WIDEN);
3389 addr = expand_binop (DImode, ashr_optab, addr, GEN_INT (64 - size*8),
3390 addr, 1, OPTAB_WIDEN);
3392 else if (sign && size == 2)
3394 emit_move_insn (addr, plus_constant (mema, ofs+2));
3396 emit_insn (gen_extxl_le (extl, meml, GEN_INT (64), addr));
3397 emit_insn (gen_extqh_le (exth, memh, addr));
3399 /* We must use tgt here for the target. Alpha-vms port fails if we use
3400 addr for the target, because addr is marked as a pointer and combine
3401 knows that pointers are always sign-extended 32-bit values. */
3402 addr = expand_binop (DImode, ior_optab, extl, exth, tgt, 1, OPTAB_WIDEN);
3403 addr = expand_binop (DImode, ashr_optab, addr, GEN_INT (48),
3404 addr, 1, OPTAB_WIDEN);
3408 if (WORDS_BIG_ENDIAN)
3410 emit_move_insn (addr, plus_constant (mema, ofs+size-1));
3414 emit_insn (gen_extwh_be (extl, meml, addr));
3419 emit_insn (gen_extlh_be (extl, meml, addr));
3424 emit_insn (gen_extqh_be (extl, meml, addr));
3431 emit_insn (gen_extxl_be (exth, memh, GEN_INT (size*8), addr));
3435 emit_move_insn (addr, plus_constant (mema, ofs));
3436 emit_insn (gen_extxl_le (extl, meml, GEN_INT (size*8), addr));
3440 emit_insn (gen_extwh_le (exth, memh, addr));
3445 emit_insn (gen_extlh_le (exth, memh, addr));
3450 emit_insn (gen_extqh_le (exth, memh, addr));
3459 addr = expand_binop (mode, ior_optab, gen_lowpart (mode, extl),
3460 gen_lowpart (mode, exth), gen_lowpart (mode, tgt),
3465 emit_move_insn (tgt, gen_lowpart (GET_MODE (tgt), addr));
3468 /* Similarly, use ins and msk instructions to perform unaligned stores. */
3471 alpha_expand_unaligned_store (rtx dst, rtx src,
3472 HOST_WIDE_INT size, HOST_WIDE_INT ofs)
3474 rtx dstl, dsth, addr, insl, insh, meml, memh, dsta;
3476 if (TARGET_BWX && size == 2)
3478 if (src != const0_rtx)
3480 dstl = gen_lowpart (QImode, src);
3481 dsth = expand_simple_binop (DImode, LSHIFTRT, src, GEN_INT (8),
3482 NULL, 1, OPTAB_LIB_WIDEN);
3483 dsth = gen_lowpart (QImode, dsth);
3486 dstl = dsth = const0_rtx;
3488 meml = adjust_address (dst, QImode, ofs);
3489 memh = adjust_address (dst, QImode, ofs+1);
3490 if (BYTES_BIG_ENDIAN)
3491 addr = meml, meml = memh, memh = addr;
3493 emit_move_insn (meml, dstl);
3494 emit_move_insn (memh, dsth);
3498 dstl = gen_reg_rtx (DImode);
3499 dsth = gen_reg_rtx (DImode);
3500 insl = gen_reg_rtx (DImode);
3501 insh = gen_reg_rtx (DImode);
3503 dsta = XEXP (dst, 0);
3504 if (GET_CODE (dsta) == LO_SUM)
3505 dsta = force_reg (Pmode, dsta);
3507 /* AND addresses cannot be in any alias set, since they may implicitly
3508 alias surrounding code. Ideally we'd have some alias set that
3509 covered all types except those with alignment 8 or higher. */
3511 meml = change_address (dst, DImode,
3512 gen_rtx_AND (DImode,
3513 plus_constant (dsta, ofs),
3515 set_mem_alias_set (meml, 0);
3517 memh = change_address (dst, DImode,
3518 gen_rtx_AND (DImode,
3519 plus_constant (dsta, ofs + size - 1),
3521 set_mem_alias_set (memh, 0);
3523 emit_move_insn (dsth, memh);
3524 emit_move_insn (dstl, meml);
3525 if (WORDS_BIG_ENDIAN)
3527 addr = copy_addr_to_reg (plus_constant (dsta, ofs+size-1));
3529 if (src != const0_rtx)
3534 emit_insn (gen_inswl_be (insh, gen_lowpart (HImode,src), addr));
3537 emit_insn (gen_insll_be (insh, gen_lowpart (SImode,src), addr));
3540 emit_insn (gen_insql_be (insh, gen_lowpart (DImode,src), addr));
3543 emit_insn (gen_insxh (insl, gen_lowpart (DImode, src),
3544 GEN_INT (size*8), addr));
3550 emit_insn (gen_mskxl_be (dsth, dsth, GEN_INT (0xffff), addr));
3554 rtx msk = immed_double_const (0xffffffff, 0, DImode);
3555 emit_insn (gen_mskxl_be (dsth, dsth, msk, addr));
3559 emit_insn (gen_mskxl_be (dsth, dsth, constm1_rtx, addr));
3563 emit_insn (gen_mskxh (dstl, dstl, GEN_INT (size*8), addr));
3567 addr = copy_addr_to_reg (plus_constant (dsta, ofs));
3569 if (src != CONST0_RTX (GET_MODE (src)))
3571 emit_insn (gen_insxh (insh, gen_lowpart (DImode, src),
3572 GEN_INT (size*8), addr));
3577 emit_insn (gen_inswl_le (insl, gen_lowpart (HImode, src), addr));
3580 emit_insn (gen_insll_le (insl, gen_lowpart (SImode, src), addr));
3583 emit_insn (gen_insql_le (insl, gen_lowpart (DImode, src), addr));
3588 emit_insn (gen_mskxh (dsth, dsth, GEN_INT (size*8), addr));
3593 emit_insn (gen_mskxl_le (dstl, dstl, GEN_INT (0xffff), addr));
3597 rtx msk = immed_double_const (0xffffffff, 0, DImode);
3598 emit_insn (gen_mskxl_le (dstl, dstl, msk, addr));
3602 emit_insn (gen_mskxl_le (dstl, dstl, constm1_rtx, addr));
3607 if (src != CONST0_RTX (GET_MODE (src)))
3609 dsth = expand_binop (DImode, ior_optab, insh, dsth, dsth, 0, OPTAB_WIDEN);
3610 dstl = expand_binop (DImode, ior_optab, insl, dstl, dstl, 0, OPTAB_WIDEN);
3613 if (WORDS_BIG_ENDIAN)
3615 emit_move_insn (meml, dstl);
3616 emit_move_insn (memh, dsth);
3620 /* Must store high before low for degenerate case of aligned. */
3621 emit_move_insn (memh, dsth);
3622 emit_move_insn (meml, dstl);
3626 /* The block move code tries to maximize speed by separating loads and
3627 stores at the expense of register pressure: we load all of the data
3628 before we store it back out. There are two secondary effects worth
3629 mentioning, that this speeds copying to/from aligned and unaligned
3630 buffers, and that it makes the code significantly easier to write. */
3632 #define MAX_MOVE_WORDS 8
3634 /* Load an integral number of consecutive unaligned quadwords. */
3637 alpha_expand_unaligned_load_words (rtx *out_regs, rtx smem,
3638 HOST_WIDE_INT words, HOST_WIDE_INT ofs)
3640 rtx const im8 = GEN_INT (-8);
3641 rtx const i64 = GEN_INT (64);
3642 rtx ext_tmps[MAX_MOVE_WORDS], data_regs[MAX_MOVE_WORDS+1];
3643 rtx sreg, areg, tmp, smema;
3646 smema = XEXP (smem, 0);
3647 if (GET_CODE (smema) == LO_SUM)
3648 smema = force_reg (Pmode, smema);
3650 /* Generate all the tmp registers we need. */
3651 for (i = 0; i < words; ++i)
3653 data_regs[i] = out_regs[i];
3654 ext_tmps[i] = gen_reg_rtx (DImode);
3656 data_regs[words] = gen_reg_rtx (DImode);
3659 smem = adjust_address (smem, GET_MODE (smem), ofs);
3661 /* Load up all of the source data. */
3662 for (i = 0; i < words; ++i)
3664 tmp = change_address (smem, DImode,
3665 gen_rtx_AND (DImode,
3666 plus_constant (smema, 8*i),
3668 set_mem_alias_set (tmp, 0);
3669 emit_move_insn (data_regs[i], tmp);
3672 tmp = change_address (smem, DImode,
3673 gen_rtx_AND (DImode,
3674 plus_constant (smema, 8*words - 1),
3676 set_mem_alias_set (tmp, 0);
3677 emit_move_insn (data_regs[words], tmp);
3679 /* Extract the half-word fragments. Unfortunately DEC decided to make
3680 extxh with offset zero a noop instead of zeroing the register, so
3681 we must take care of that edge condition ourselves with cmov. */
3683 sreg = copy_addr_to_reg (smema);
3684 areg = expand_binop (DImode, and_optab, sreg, GEN_INT (7), NULL,
3686 if (WORDS_BIG_ENDIAN)
3687 emit_move_insn (sreg, plus_constant (sreg, 7));
3688 for (i = 0; i < words; ++i)
3690 if (WORDS_BIG_ENDIAN)
3692 emit_insn (gen_extqh_be (data_regs[i], data_regs[i], sreg));
3693 emit_insn (gen_extxl_be (ext_tmps[i], data_regs[i+1], i64, sreg));
3697 emit_insn (gen_extxl_le (data_regs[i], data_regs[i], i64, sreg));
3698 emit_insn (gen_extqh_le (ext_tmps[i], data_regs[i+1], sreg));
3700 emit_insn (gen_rtx_SET (VOIDmode, ext_tmps[i],
3701 gen_rtx_IF_THEN_ELSE (DImode,
3702 gen_rtx_EQ (DImode, areg,
3704 const0_rtx, ext_tmps[i])));
3707 /* Merge the half-words into whole words. */
3708 for (i = 0; i < words; ++i)
3710 out_regs[i] = expand_binop (DImode, ior_optab, data_regs[i],
3711 ext_tmps[i], data_regs[i], 1, OPTAB_WIDEN);
3715 /* Store an integral number of consecutive unaligned quadwords. DATA_REGS
3716 may be NULL to store zeros. */
3719 alpha_expand_unaligned_store_words (rtx *data_regs, rtx dmem,
3720 HOST_WIDE_INT words, HOST_WIDE_INT ofs)
3722 rtx const im8 = GEN_INT (-8);
3723 rtx const i64 = GEN_INT (64);
3724 rtx ins_tmps[MAX_MOVE_WORDS];
3725 rtx st_tmp_1, st_tmp_2, dreg;
3726 rtx st_addr_1, st_addr_2, dmema;
3729 dmema = XEXP (dmem, 0);
3730 if (GET_CODE (dmema) == LO_SUM)
3731 dmema = force_reg (Pmode, dmema);
3733 /* Generate all the tmp registers we need. */
3734 if (data_regs != NULL)
3735 for (i = 0; i < words; ++i)
3736 ins_tmps[i] = gen_reg_rtx(DImode);
3737 st_tmp_1 = gen_reg_rtx(DImode);
3738 st_tmp_2 = gen_reg_rtx(DImode);
3741 dmem = adjust_address (dmem, GET_MODE (dmem), ofs);
3743 st_addr_2 = change_address (dmem, DImode,
3744 gen_rtx_AND (DImode,
3745 plus_constant (dmema, words*8 - 1),
3747 set_mem_alias_set (st_addr_2, 0);
3749 st_addr_1 = change_address (dmem, DImode,
3750 gen_rtx_AND (DImode, dmema, im8));
3751 set_mem_alias_set (st_addr_1, 0);
3753 /* Load up the destination end bits. */
3754 emit_move_insn (st_tmp_2, st_addr_2);
3755 emit_move_insn (st_tmp_1, st_addr_1);
3757 /* Shift the input data into place. */
3758 dreg = copy_addr_to_reg (dmema);
3759 if (WORDS_BIG_ENDIAN)
3760 emit_move_insn (dreg, plus_constant (dreg, 7));
3761 if (data_regs != NULL)
3763 for (i = words-1; i >= 0; --i)
3765 if (WORDS_BIG_ENDIAN)
3767 emit_insn (gen_insql_be (ins_tmps[i], data_regs[i], dreg));
3768 emit_insn (gen_insxh (data_regs[i], data_regs[i], i64, dreg));
3772 emit_insn (gen_insxh (ins_tmps[i], data_regs[i], i64, dreg));
3773 emit_insn (gen_insql_le (data_regs[i], data_regs[i], dreg));
3776 for (i = words-1; i > 0; --i)
3778 ins_tmps[i-1] = expand_binop (DImode, ior_optab, data_regs[i],
3779 ins_tmps[i-1], ins_tmps[i-1], 1,
3784 /* Split and merge the ends with the destination data. */
3785 if (WORDS_BIG_ENDIAN)
3787 emit_insn (gen_mskxl_be (st_tmp_2, st_tmp_2, constm1_rtx, dreg));
3788 emit_insn (gen_mskxh (st_tmp_1, st_tmp_1, i64, dreg));
3792 emit_insn (gen_mskxh (st_tmp_2, st_tmp_2, i64, dreg));
3793 emit_insn (gen_mskxl_le (st_tmp_1, st_tmp_1, constm1_rtx, dreg));
3796 if (data_regs != NULL)
3798 st_tmp_2 = expand_binop (DImode, ior_optab, st_tmp_2, ins_tmps[words-1],
3799 st_tmp_2, 1, OPTAB_WIDEN);
3800 st_tmp_1 = expand_binop (DImode, ior_optab, st_tmp_1, data_regs[0],
3801 st_tmp_1, 1, OPTAB_WIDEN);
3805 if (WORDS_BIG_ENDIAN)
3806 emit_move_insn (st_addr_1, st_tmp_1);
3808 emit_move_insn (st_addr_2, st_tmp_2);
3809 for (i = words-1; i > 0; --i)
3811 rtx tmp = change_address (dmem, DImode,
3812 gen_rtx_AND (DImode,
3813 plus_constant(dmema,
3814 WORDS_BIG_ENDIAN ? i*8-1 : i*8),
3816 set_mem_alias_set (tmp, 0);
3817 emit_move_insn (tmp, data_regs ? ins_tmps[i-1] : const0_rtx);
3819 if (WORDS_BIG_ENDIAN)
3820 emit_move_insn (st_addr_2, st_tmp_2);
3822 emit_move_insn (st_addr_1, st_tmp_1);
3826 /* Expand string/block move operations.
3828 operands[0] is the pointer to the destination.
3829 operands[1] is the pointer to the source.
3830 operands[2] is the number of bytes to move.
3831 operands[3] is the alignment. */
3834 alpha_expand_block_move (rtx operands[])
3836 rtx bytes_rtx = operands[2];
3837 rtx align_rtx = operands[3];
3838 HOST_WIDE_INT orig_bytes = INTVAL (bytes_rtx);
3839 HOST_WIDE_INT bytes = orig_bytes;
3840 HOST_WIDE_INT src_align = INTVAL (align_rtx) * BITS_PER_UNIT;
3841 HOST_WIDE_INT dst_align = src_align;
3842 rtx orig_src = operands[1];
3843 rtx orig_dst = operands[0];
3844 rtx data_regs[2 * MAX_MOVE_WORDS + 16];
3846 unsigned int i, words, ofs, nregs = 0;
3848 if (orig_bytes <= 0)
3850 else if (orig_bytes > MAX_MOVE_WORDS * UNITS_PER_WORD)
3853 /* Look for additional alignment information from recorded register info. */
3855 tmp = XEXP (orig_src, 0);
3857 src_align = MAX (src_align, REGNO_POINTER_ALIGN (REGNO (tmp)));
3858 else if (GET_CODE (tmp) == PLUS
3859 && REG_P (XEXP (tmp, 0))
3860 && CONST_INT_P (XEXP (tmp, 1)))
3862 unsigned HOST_WIDE_INT c = INTVAL (XEXP (tmp, 1));
3863 unsigned int a = REGNO_POINTER_ALIGN (REGNO (XEXP (tmp, 0)));
3867 if (a >= 64 && c % 8 == 0)
3869 else if (a >= 32 && c % 4 == 0)
3871 else if (a >= 16 && c % 2 == 0)
3876 tmp = XEXP (orig_dst, 0);
3878 dst_align = MAX (dst_align, REGNO_POINTER_ALIGN (REGNO (tmp)));
3879 else if (GET_CODE (tmp) == PLUS
3880 && REG_P (XEXP (tmp, 0))
3881 && CONST_INT_P (XEXP (tmp, 1)))
3883 unsigned HOST_WIDE_INT c = INTVAL (XEXP (tmp, 1));
3884 unsigned int a = REGNO_POINTER_ALIGN (REGNO (XEXP (tmp, 0)));
3888 if (a >= 64 && c % 8 == 0)
3890 else if (a >= 32 && c % 4 == 0)
3892 else if (a >= 16 && c % 2 == 0)
3898 if (src_align >= 64 && bytes >= 8)
3902 for (i = 0; i < words; ++i)
3903 data_regs[nregs + i] = gen_reg_rtx (DImode);
3905 for (i = 0; i < words; ++i)
3906 emit_move_insn (data_regs[nregs + i],
3907 adjust_address (orig_src, DImode, ofs + i * 8));
3914 if (src_align >= 32 && bytes >= 4)
3918 for (i = 0; i < words; ++i)
3919 data_regs[nregs + i] = gen_reg_rtx (SImode);
3921 for (i = 0; i < words; ++i)
3922 emit_move_insn (data_regs[nregs + i],
3923 adjust_address (orig_src, SImode, ofs + i * 4));
3934 for (i = 0; i < words+1; ++i)
3935 data_regs[nregs + i] = gen_reg_rtx (DImode);
3937 alpha_expand_unaligned_load_words (data_regs + nregs, orig_src,
3945 if (! TARGET_BWX && bytes >= 4)
3947 data_regs[nregs++] = tmp = gen_reg_rtx (SImode);
3948 alpha_expand_unaligned_load (tmp, orig_src, 4, ofs, 0);
3955 if (src_align >= 16)
3958 data_regs[nregs++] = tmp = gen_reg_rtx (HImode);
3959 emit_move_insn (tmp, adjust_address (orig_src, HImode, ofs));
3962 } while (bytes >= 2);
3964 else if (! TARGET_BWX)
3966 data_regs[nregs++] = tmp = gen_reg_rtx (HImode);
3967 alpha_expand_unaligned_load (tmp, orig_src, 2, ofs, 0);
3975 data_regs[nregs++] = tmp = gen_reg_rtx (QImode);
3976 emit_move_insn (tmp, adjust_address (orig_src, QImode, ofs));
3981 gcc_assert (nregs <= ARRAY_SIZE (data_regs));
3983 /* Now save it back out again. */
3987 /* Write out the data in whatever chunks reading the source allowed. */
3988 if (dst_align >= 64)
3990 while (i < nregs && GET_MODE (data_regs[i]) == DImode)
3992 emit_move_insn (adjust_address (orig_dst, DImode, ofs),
3999 if (dst_align >= 32)
4001 /* If the source has remaining DImode regs, write them out in
4003 while (i < nregs && GET_MODE (data_regs[i]) == DImode)
4005 tmp = expand_binop (DImode, lshr_optab, data_regs[i], GEN_INT (32),
4006 NULL_RTX, 1, OPTAB_WIDEN);
4008 emit_move_insn (adjust_address (orig_dst, SImode, ofs),
4009 gen_lowpart (SImode, data_regs[i]));
4010 emit_move_insn (adjust_address (orig_dst, SImode, ofs + 4),
4011 gen_lowpart (SImode, tmp));
4016 while (i < nregs && GET_MODE (data_regs[i]) == SImode)
4018 emit_move_insn (adjust_address (orig_dst, SImode, ofs),
4025 if (i < nregs && GET_MODE (data_regs[i]) == DImode)
4027 /* Write out a remaining block of words using unaligned methods. */
4029 for (words = 1; i + words < nregs; words++)
4030 if (GET_MODE (data_regs[i + words]) != DImode)
4034 alpha_expand_unaligned_store (orig_dst, data_regs[i], 8, ofs);
4036 alpha_expand_unaligned_store_words (data_regs + i, orig_dst,
4043 /* Due to the above, this won't be aligned. */
4044 /* ??? If we have more than one of these, consider constructing full
4045 words in registers and using alpha_expand_unaligned_store_words. */
4046 while (i < nregs && GET_MODE (data_regs[i]) == SImode)
4048 alpha_expand_unaligned_store (orig_dst, data_regs[i], 4, ofs);
4053 if (dst_align >= 16)
4054 while (i < nregs && GET_MODE (data_regs[i]) == HImode)
4056 emit_move_insn (adjust_address (orig_dst, HImode, ofs), data_regs[i]);
4061 while (i < nregs && GET_MODE (data_regs[i]) == HImode)
4063 alpha_expand_unaligned_store (orig_dst, data_regs[i], 2, ofs);
4068 /* The remainder must be byte copies. */
4071 gcc_assert (GET_MODE (data_regs[i]) == QImode);
4072 emit_move_insn (adjust_address (orig_dst, QImode, ofs), data_regs[i]);
4081 alpha_expand_block_clear (rtx operands[])
4083 rtx bytes_rtx = operands[1];
4084 rtx align_rtx = operands[3];
4085 HOST_WIDE_INT orig_bytes = INTVAL (bytes_rtx);
4086 HOST_WIDE_INT bytes = orig_bytes;
4087 HOST_WIDE_INT align = INTVAL (align_rtx) * BITS_PER_UNIT;
4088 HOST_WIDE_INT alignofs = 0;
4089 rtx orig_dst = operands[0];
4091 int i, words, ofs = 0;
4093 if (orig_bytes <= 0)
4095 if (orig_bytes > MAX_MOVE_WORDS * UNITS_PER_WORD)
4098 /* Look for stricter alignment. */
4099 tmp = XEXP (orig_dst, 0);
4101 align = MAX (align, REGNO_POINTER_ALIGN (REGNO (tmp)));
4102 else if (GET_CODE (tmp) == PLUS
4103 && REG_P (XEXP (tmp, 0))
4104 && CONST_INT_P (XEXP (tmp, 1)))
4106 HOST_WIDE_INT c = INTVAL (XEXP (tmp, 1));
4107 int a = REGNO_POINTER_ALIGN (REGNO (XEXP (tmp, 0)));
4112 align = a, alignofs = 8 - c % 8;
4114 align = a, alignofs = 4 - c % 4;
4116 align = a, alignofs = 2 - c % 2;
4120 /* Handle an unaligned prefix first. */
4124 #if HOST_BITS_PER_WIDE_INT >= 64
4125 /* Given that alignofs is bounded by align, the only time BWX could
4126 generate three stores is for a 7 byte fill. Prefer two individual
4127 stores over a load/mask/store sequence. */
4128 if ((!TARGET_BWX || alignofs == 7)
4130 && !(alignofs == 4 && bytes >= 4))
4132 enum machine_mode mode = (align >= 64 ? DImode : SImode);
4133 int inv_alignofs = (align >= 64 ? 8 : 4) - alignofs;
4137 mem = adjust_address (orig_dst, mode, ofs - inv_alignofs);
4138 set_mem_alias_set (mem, 0);
4140 mask = ~(~(HOST_WIDE_INT)0 << (inv_alignofs * 8));
4141 if (bytes < alignofs)
4143 mask |= ~(HOST_WIDE_INT)0 << ((inv_alignofs + bytes) * 8);
4154 tmp = expand_binop (mode, and_optab, mem, GEN_INT (mask),
4155 NULL_RTX, 1, OPTAB_WIDEN);
4157 emit_move_insn (mem, tmp);
4161 if (TARGET_BWX && (alignofs & 1) && bytes >= 1)
4163 emit_move_insn (adjust_address (orig_dst, QImode, ofs), const0_rtx);
4168 if (TARGET_BWX && align >= 16 && (alignofs & 3) == 2 && bytes >= 2)
4170 emit_move_insn (adjust_address (orig_dst, HImode, ofs), const0_rtx);
4175 if (alignofs == 4 && bytes >= 4)
4177 emit_move_insn (adjust_address (orig_dst, SImode, ofs), const0_rtx);
4183 /* If we've not used the extra lead alignment information by now,
4184 we won't be able to. Downgrade align to match what's left over. */
4187 alignofs = alignofs & -alignofs;
4188 align = MIN (align, alignofs * BITS_PER_UNIT);
4192 /* Handle a block of contiguous long-words. */
4194 if (align >= 64 && bytes >= 8)
4198 for (i = 0; i < words; ++i)
4199 emit_move_insn (adjust_address (orig_dst, DImode, ofs + i * 8),
4206 /* If the block is large and appropriately aligned, emit a single
4207 store followed by a sequence of stq_u insns. */
4209 if (align >= 32 && bytes > 16)
4213 emit_move_insn (adjust_address (orig_dst, SImode, ofs), const0_rtx);
4217 orig_dsta = XEXP (orig_dst, 0);
4218 if (GET_CODE (orig_dsta) == LO_SUM)
4219 orig_dsta = force_reg (Pmode, orig_dsta);
4222 for (i = 0; i < words; ++i)
4225 = change_address (orig_dst, DImode,
4226 gen_rtx_AND (DImode,
4227 plus_constant (orig_dsta, ofs + i*8),
4229 set_mem_alias_set (mem, 0);
4230 emit_move_insn (mem, const0_rtx);
4233 /* Depending on the alignment, the first stq_u may have overlapped
4234 with the initial stl, which means that the last stq_u didn't
4235 write as much as it would appear. Leave those questionable bytes
4237 bytes -= words * 8 - 4;
4238 ofs += words * 8 - 4;
4241 /* Handle a smaller block of aligned words. */
4243 if ((align >= 64 && bytes == 4)
4244 || (align == 32 && bytes >= 4))
4248 for (i = 0; i < words; ++i)
4249 emit_move_insn (adjust_address (orig_dst, SImode, ofs + i * 4),
4256 /* An unaligned block uses stq_u stores for as many as possible. */
4262 alpha_expand_unaligned_store_words (NULL, orig_dst, words, ofs);
4268 /* Next clean up any trailing pieces. */
4270 #if HOST_BITS_PER_WIDE_INT >= 64
4271 /* Count the number of bits in BYTES for which aligned stores could
4274 for (i = (TARGET_BWX ? 1 : 4); i * BITS_PER_UNIT <= align ; i <<= 1)
4278 /* If we have appropriate alignment (and it wouldn't take too many
4279 instructions otherwise), mask out the bytes we need. */
4280 if (TARGET_BWX ? words > 2 : bytes > 0)
4287 mem = adjust_address (orig_dst, DImode, ofs);
4288 set_mem_alias_set (mem, 0);
4290 mask = ~(HOST_WIDE_INT)0 << (bytes * 8);
4292 tmp = expand_binop (DImode, and_optab, mem, GEN_INT (mask),
4293 NULL_RTX, 1, OPTAB_WIDEN);
4295 emit_move_insn (mem, tmp);
4298 else if (align >= 32 && bytes < 4)
4303 mem = adjust_address (orig_dst, SImode, ofs);
4304 set_mem_alias_set (mem, 0);
4306 mask = ~(HOST_WIDE_INT)0 << (bytes * 8);
4308 tmp = expand_binop (SImode, and_optab, mem, GEN_INT (mask),
4309 NULL_RTX, 1, OPTAB_WIDEN);
4311 emit_move_insn (mem, tmp);
4317 if (!TARGET_BWX && bytes >= 4)
4319 alpha_expand_unaligned_store (orig_dst, const0_rtx, 4, ofs);
4329 emit_move_insn (adjust_address (orig_dst, HImode, ofs),
4333 } while (bytes >= 2);
4335 else if (! TARGET_BWX)
4337 alpha_expand_unaligned_store (orig_dst, const0_rtx, 2, ofs);
4345 emit_move_insn (adjust_address (orig_dst, QImode, ofs), const0_rtx);
4353 /* Returns a mask so that zap(x, value) == x & mask. */
4356 alpha_expand_zap_mask (HOST_WIDE_INT value)
4361 if (HOST_BITS_PER_WIDE_INT >= 64)
4363 HOST_WIDE_INT mask = 0;
4365 for (i = 7; i >= 0; --i)
4368 if (!((value >> i) & 1))
4372 result = gen_int_mode (mask, DImode);
4376 HOST_WIDE_INT mask_lo = 0, mask_hi = 0;
4378 gcc_assert (HOST_BITS_PER_WIDE_INT == 32);
4380 for (i = 7; i >= 4; --i)
4383 if (!((value >> i) & 1))
4387 for (i = 3; i >= 0; --i)
4390 if (!((value >> i) & 1))
4394 result = immed_double_const (mask_lo, mask_hi, DImode);
4401 alpha_expand_builtin_vector_binop (rtx (*gen) (rtx, rtx, rtx),
4402 enum machine_mode mode,
4403 rtx op0, rtx op1, rtx op2)
4405 op0 = gen_lowpart (mode, op0);
4407 if (op1 == const0_rtx)
4408 op1 = CONST0_RTX (mode);
4410 op1 = gen_lowpart (mode, op1);
4412 if (op2 == const0_rtx)
4413 op2 = CONST0_RTX (mode);
4415 op2 = gen_lowpart (mode, op2);
4417 emit_insn ((*gen) (op0, op1, op2));
4420 /* A subroutine of the atomic operation splitters. Jump to LABEL if
4421 COND is true. Mark the jump as unlikely to be taken. */
4424 emit_unlikely_jump (rtx cond, rtx label)
4426 rtx very_unlikely = GEN_INT (REG_BR_PROB_BASE / 100 - 1);
4429 x = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, label, pc_rtx);
4430 x = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, x));
4431 add_reg_note (x, REG_BR_PROB, very_unlikely);
4434 /* A subroutine of the atomic operation splitters. Emit a load-locked
4435 instruction in MODE. */
4438 emit_load_locked (enum machine_mode mode, rtx reg, rtx mem)
4440 rtx (*fn) (rtx, rtx) = NULL;
4442 fn = gen_load_locked_si;
4443 else if (mode == DImode)
4444 fn = gen_load_locked_di;
4445 emit_insn (fn (reg, mem));
4448 /* A subroutine of the atomic operation splitters. Emit a store-conditional
4449 instruction in MODE. */
4452 emit_store_conditional (enum machine_mode mode, rtx res, rtx mem, rtx val)
4454 rtx (*fn) (rtx, rtx, rtx) = NULL;
4456 fn = gen_store_conditional_si;
4457 else if (mode == DImode)
4458 fn = gen_store_conditional_di;
4459 emit_insn (fn (res, mem, val));
4462 /* A subroutine of the atomic operation splitters. Emit an insxl
4463 instruction in MODE. */
4466 emit_insxl (enum machine_mode mode, rtx op1, rtx op2)
4468 rtx ret = gen_reg_rtx (DImode);
4469 rtx (*fn) (rtx, rtx, rtx);
4471 if (WORDS_BIG_ENDIAN)
4485 /* The insbl and inswl patterns require a register operand. */
4486 op1 = force_reg (mode, op1);
4487 emit_insn (fn (ret, op1, op2));
4492 /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation
4493 to perform. MEM is the memory on which to operate. VAL is the second
4494 operand of the binary operator. BEFORE and AFTER are optional locations to
4495 return the value of MEM either before of after the operation. SCRATCH is
4496 a scratch register. */
4499 alpha_split_atomic_op (enum rtx_code code, rtx mem, rtx val,
4500 rtx before, rtx after, rtx scratch)
4502 enum machine_mode mode = GET_MODE (mem);
4503 rtx label, x, cond = gen_rtx_REG (DImode, REGNO (scratch));
4505 emit_insn (gen_memory_barrier ());
4507 label = gen_label_rtx ();
4509 label = gen_rtx_LABEL_REF (DImode, label);
4513 emit_load_locked (mode, before, mem);
4517 x = gen_rtx_AND (mode, before, val);
4518 emit_insn (gen_rtx_SET (VOIDmode, val, x));
4520 x = gen_rtx_NOT (mode, val);
4523 x = gen_rtx_fmt_ee (code, mode, before, val);
4525 emit_insn (gen_rtx_SET (VOIDmode, after, copy_rtx (x)));
4526 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
4528 emit_store_conditional (mode, cond, mem, scratch);
4530 x = gen_rtx_EQ (DImode, cond, const0_rtx);
4531 emit_unlikely_jump (x, label);
4533 emit_insn (gen_memory_barrier ());
4536 /* Expand a compare and swap operation. */
4539 alpha_split_compare_and_swap (rtx retval, rtx mem, rtx oldval, rtx newval,
4542 enum machine_mode mode = GET_MODE (mem);
4543 rtx label1, label2, x, cond = gen_lowpart (DImode, scratch);
4545 emit_insn (gen_memory_barrier ());
4547 label1 = gen_rtx_LABEL_REF (DImode, gen_label_rtx ());
4548 label2 = gen_rtx_LABEL_REF (DImode, gen_label_rtx ());
4549 emit_label (XEXP (label1, 0));
4551 emit_load_locked (mode, retval, mem);
4553 x = gen_lowpart (DImode, retval);
4554 if (oldval == const0_rtx)
4555 x = gen_rtx_NE (DImode, x, const0_rtx);
4558 x = gen_rtx_EQ (DImode, x, oldval);
4559 emit_insn (gen_rtx_SET (VOIDmode, cond, x));
4560 x = gen_rtx_EQ (DImode, cond, const0_rtx);
4562 emit_unlikely_jump (x, label2);
4564 emit_move_insn (scratch, newval);
4565 emit_store_conditional (mode, cond, mem, scratch);
4567 x = gen_rtx_EQ (DImode, cond, const0_rtx);
4568 emit_unlikely_jump (x, label1);
4570 emit_insn (gen_memory_barrier ());
4571 emit_label (XEXP (label2, 0));
4575 alpha_expand_compare_and_swap_12 (rtx dst, rtx mem, rtx oldval, rtx newval)
4577 enum machine_mode mode = GET_MODE (mem);
4578 rtx addr, align, wdst;
4579 rtx (*fn5) (rtx, rtx, rtx, rtx, rtx);
4581 addr = force_reg (DImode, XEXP (mem, 0));
4582 align = expand_simple_binop (Pmode, AND, addr, GEN_INT (-8),
4583 NULL_RTX, 1, OPTAB_DIRECT);
4585 oldval = convert_modes (DImode, mode, oldval, 1);
4586 newval = emit_insxl (mode, newval, addr);
4588 wdst = gen_reg_rtx (DImode);
4590 fn5 = gen_sync_compare_and_swapqi_1;
4592 fn5 = gen_sync_compare_and_swaphi_1;
4593 emit_insn (fn5 (wdst, addr, oldval, newval, align));
4595 emit_move_insn (dst, gen_lowpart (mode, wdst));
4599 alpha_split_compare_and_swap_12 (enum machine_mode mode, rtx dest, rtx addr,
4600 rtx oldval, rtx newval, rtx align,
4601 rtx scratch, rtx cond)
4603 rtx label1, label2, mem, width, mask, x;
4605 mem = gen_rtx_MEM (DImode, align);
4606 MEM_VOLATILE_P (mem) = 1;
4608 emit_insn (gen_memory_barrier ());
4609 label1 = gen_rtx_LABEL_REF (DImode, gen_label_rtx ());
4610 label2 = gen_rtx_LABEL_REF (DImode, gen_label_rtx ());
4611 emit_label (XEXP (label1, 0));
4613 emit_load_locked (DImode, scratch, mem);
4615 width = GEN_INT (GET_MODE_BITSIZE (mode));
4616 mask = GEN_INT (mode == QImode ? 0xff : 0xffff);
4617 if (WORDS_BIG_ENDIAN)
4618 emit_insn (gen_extxl_be (dest, scratch, width, addr));
4620 emit_insn (gen_extxl_le (dest, scratch, width, addr));
4622 if (oldval == const0_rtx)
4623 x = gen_rtx_NE (DImode, dest, const0_rtx);
4626 x = gen_rtx_EQ (DImode, dest, oldval);
4627 emit_insn (gen_rtx_SET (VOIDmode, cond, x));
4628 x = gen_rtx_EQ (DImode, cond, const0_rtx);
4630 emit_unlikely_jump (x, label2);
4632 if (WORDS_BIG_ENDIAN)
4633 emit_insn (gen_mskxl_be (scratch, scratch, mask, addr));
4635 emit_insn (gen_mskxl_le (scratch, scratch, mask, addr));
4636 emit_insn (gen_iordi3 (scratch, scratch, newval));
4638 emit_store_conditional (DImode, scratch, mem, scratch);
4640 x = gen_rtx_EQ (DImode, scratch, const0_rtx);
4641 emit_unlikely_jump (x, label1);
4643 emit_insn (gen_memory_barrier ());
4644 emit_label (XEXP (label2, 0));
4647 /* Expand an atomic exchange operation. */
4650 alpha_split_lock_test_and_set (rtx retval, rtx mem, rtx val, rtx scratch)
4652 enum machine_mode mode = GET_MODE (mem);
4653 rtx label, x, cond = gen_lowpart (DImode, scratch);
4655 label = gen_rtx_LABEL_REF (DImode, gen_label_rtx ());
4656 emit_label (XEXP (label, 0));
4658 emit_load_locked (mode, retval, mem);
4659 emit_move_insn (scratch, val);
4660 emit_store_conditional (mode, cond, mem, scratch);
4662 x = gen_rtx_EQ (DImode, cond, const0_rtx);
4663 emit_unlikely_jump (x, label);
4665 emit_insn (gen_memory_barrier ());
4669 alpha_expand_lock_test_and_set_12 (rtx dst, rtx mem, rtx val)
4671 enum machine_mode mode = GET_MODE (mem);
4672 rtx addr, align, wdst;
4673 rtx (*fn4) (rtx, rtx, rtx, rtx);
4675 /* Force the address into a register. */
4676 addr = force_reg (DImode, XEXP (mem, 0));
4678 /* Align it to a multiple of 8. */
4679 align = expand_simple_binop (Pmode, AND, addr, GEN_INT (-8),
4680 NULL_RTX, 1, OPTAB_DIRECT);
4682 /* Insert val into the correct byte location within the word. */
4683 val = emit_insxl (mode, val, addr);
4685 wdst = gen_reg_rtx (DImode);
4687 fn4 = gen_sync_lock_test_and_setqi_1;
4689 fn4 = gen_sync_lock_test_and_sethi_1;
4690 emit_insn (fn4 (wdst, addr, val, align));
4692 emit_move_insn (dst, gen_lowpart (mode, wdst));
4696 alpha_split_lock_test_and_set_12 (enum machine_mode mode, rtx dest, rtx addr,
4697 rtx val, rtx align, rtx scratch)
4699 rtx label, mem, width, mask, x;
4701 mem = gen_rtx_MEM (DImode, align);
4702 MEM_VOLATILE_P (mem) = 1;
4704 label = gen_rtx_LABEL_REF (DImode, gen_label_rtx ());
4705 emit_label (XEXP (label, 0));
4707 emit_load_locked (DImode, scratch, mem);
4709 width = GEN_INT (GET_MODE_BITSIZE (mode));
4710 mask = GEN_INT (mode == QImode ? 0xff : 0xffff);
4711 if (WORDS_BIG_ENDIAN)
4713 emit_insn (gen_extxl_be (dest, scratch, width, addr));
4714 emit_insn (gen_mskxl_be (scratch, scratch, mask, addr));
4718 emit_insn (gen_extxl_le (dest, scratch, width, addr));
4719 emit_insn (gen_mskxl_le (scratch, scratch, mask, addr));
4721 emit_insn (gen_iordi3 (scratch, scratch, val));
4723 emit_store_conditional (DImode, scratch, mem, scratch);
4725 x = gen_rtx_EQ (DImode, scratch, const0_rtx);
4726 emit_unlikely_jump (x, label);
4728 emit_insn (gen_memory_barrier ());
4731 /* Adjust the cost of a scheduling dependency. Return the new cost of
4732 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
4735 alpha_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
4737 enum attr_type dep_insn_type;
4739 /* If the dependence is an anti-dependence, there is no cost. For an
4740 output dependence, there is sometimes a cost, but it doesn't seem
4741 worth handling those few cases. */
4742 if (REG_NOTE_KIND (link) != 0)
4745 /* If we can't recognize the insns, we can't really do anything. */
4746 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
4749 dep_insn_type = get_attr_type (dep_insn);
4751 /* Bring in the user-defined memory latency. */
4752 if (dep_insn_type == TYPE_ILD
4753 || dep_insn_type == TYPE_FLD
4754 || dep_insn_type == TYPE_LDSYM)
4755 cost += alpha_memory_latency-1;
4757 /* Everything else handled in DFA bypasses now. */
4762 /* The number of instructions that can be issued per cycle. */
4765 alpha_issue_rate (void)
4767 return (alpha_tune == PROCESSOR_EV4 ? 2 : 4);
4770 /* How many alternative schedules to try. This should be as wide as the
4771 scheduling freedom in the DFA, but no wider. Making this value too
4772 large results extra work for the scheduler.
4774 For EV4, loads can be issued to either IB0 or IB1, thus we have 2
4775 alternative schedules. For EV5, we can choose between E0/E1 and
4776 FA/FM. For EV6, an arithmetic insn can be issued to U0/U1/L0/L1. */
4779 alpha_multipass_dfa_lookahead (void)
4781 return (alpha_tune == PROCESSOR_EV6 ? 4 : 2);
4784 /* Machine-specific function data. */
4786 struct GTY(()) machine_function
4789 /* List of call information words for calls from this function. */
4790 struct rtx_def *first_ciw;
4791 struct rtx_def *last_ciw;
4794 /* List of deferred case vectors. */
4795 struct rtx_def *addr_list;
4798 const char *some_ld_name;
4800 /* For TARGET_LD_BUGGY_LDGP. */
4801 struct rtx_def *gp_save_rtx;
4803 /* For VMS condition handlers. */
4804 bool uses_condition_handler;
4807 /* How to allocate a 'struct machine_function'. */
4809 static struct machine_function *
4810 alpha_init_machine_status (void)
4812 return ggc_alloc_cleared_machine_function ();
4815 /* Support for frame based VMS condition handlers. */
4817 /* A VMS condition handler may be established for a function with a call to
4818 __builtin_establish_vms_condition_handler, and cancelled with a call to
4819 __builtin_revert_vms_condition_handler.
4821 The VMS Condition Handling Facility knows about the existence of a handler
4822 from the procedure descriptor .handler field. As the VMS native compilers,
4823 we store the user specified handler's address at a fixed location in the
4824 stack frame and point the procedure descriptor at a common wrapper which
4825 fetches the real handler's address and issues an indirect call.
4827 The indirection wrapper is "__gcc_shell_handler", provided by libgcc.
4829 We force the procedure kind to PT_STACK, and the fixed frame location is
4830 fp+8, just before the register save area. We use the handler_data field in
4831 the procedure descriptor to state the fp offset at which the installed
4832 handler address can be found. */
4834 #define VMS_COND_HANDLER_FP_OFFSET 8
4836 /* Expand code to store the currently installed user VMS condition handler
4837 into TARGET and install HANDLER as the new condition handler. */
4840 alpha_expand_builtin_establish_vms_condition_handler (rtx target, rtx handler)
4842 rtx handler_slot_address
4843 = plus_constant (hard_frame_pointer_rtx, VMS_COND_HANDLER_FP_OFFSET);
4846 = gen_rtx_MEM (DImode, handler_slot_address);
4848 emit_move_insn (target, handler_slot);
4849 emit_move_insn (handler_slot, handler);
4851 /* Notify the start/prologue/epilogue emitters that the condition handler
4852 slot is needed. In addition to reserving the slot space, this will force
4853 the procedure kind to PT_STACK so ensure that the hard_frame_pointer_rtx
4854 use above is correct. */
4855 cfun->machine->uses_condition_handler = true;
4858 /* Expand code to store the current VMS condition handler into TARGET and
4862 alpha_expand_builtin_revert_vms_condition_handler (rtx target)
4864 /* We implement this by establishing a null condition handler, with the tiny
4865 side effect of setting uses_condition_handler. This is a little bit
4866 pessimistic if no actual builtin_establish call is ever issued, which is
4867 not a real problem and expected never to happen anyway. */
4869 alpha_expand_builtin_establish_vms_condition_handler (target, const0_rtx);
4872 /* Functions to save and restore alpha_return_addr_rtx. */
4874 /* Start the ball rolling with RETURN_ADDR_RTX. */
4877 alpha_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
4882 return get_hard_reg_initial_val (Pmode, REG_RA);
4885 /* Return or create a memory slot containing the gp value for the current
4886 function. Needed only if TARGET_LD_BUGGY_LDGP. */
4889 alpha_gp_save_rtx (void)
4891 rtx seq, m = cfun->machine->gp_save_rtx;
4897 m = assign_stack_local (DImode, UNITS_PER_WORD, BITS_PER_WORD);
4898 m = validize_mem (m);
4899 emit_move_insn (m, pic_offset_table_rtx);
4904 /* We used to simply emit the sequence after entry_of_function.
4905 However this breaks the CFG if the first instruction in the
4906 first block is not the NOTE_INSN_BASIC_BLOCK, for example a
4907 label. Emit the sequence properly on the edge. We are only
4908 invoked from dw2_build_landing_pads and finish_eh_generation
4909 will call commit_edge_insertions thanks to a kludge. */
4910 insert_insn_on_edge (seq, single_succ_edge (ENTRY_BLOCK_PTR));
4912 cfun->machine->gp_save_rtx = m;
4919 alpha_ra_ever_killed (void)
4923 if (!has_hard_reg_initial_val (Pmode, REG_RA))
4924 return (int)df_regs_ever_live_p (REG_RA);
4926 push_topmost_sequence ();
4928 pop_topmost_sequence ();
4930 return reg_set_between_p (gen_rtx_REG (Pmode, REG_RA), top, NULL_RTX);
4934 /* Return the trap mode suffix applicable to the current
4935 instruction, or NULL. */
4938 get_trap_mode_suffix (void)
4940 enum attr_trap_suffix s = get_attr_trap_suffix (current_output_insn);
4944 case TRAP_SUFFIX_NONE:
4947 case TRAP_SUFFIX_SU:
4948 if (alpha_fptm >= ALPHA_FPTM_SU)
4952 case TRAP_SUFFIX_SUI:
4953 if (alpha_fptm >= ALPHA_FPTM_SUI)
4957 case TRAP_SUFFIX_V_SV:
4965 case ALPHA_FPTM_SUI:
4971 case TRAP_SUFFIX_V_SV_SVI:
4980 case ALPHA_FPTM_SUI:
4987 case TRAP_SUFFIX_U_SU_SUI:
4996 case ALPHA_FPTM_SUI:
5009 /* Return the rounding mode suffix applicable to the current
5010 instruction, or NULL. */
5013 get_round_mode_suffix (void)
5015 enum attr_round_suffix s = get_attr_round_suffix (current_output_insn);
5019 case ROUND_SUFFIX_NONE:
5021 case ROUND_SUFFIX_NORMAL:
5024 case ALPHA_FPRM_NORM:
5026 case ALPHA_FPRM_MINF:
5028 case ALPHA_FPRM_CHOP:
5030 case ALPHA_FPRM_DYN:
5037 case ROUND_SUFFIX_C:
5046 /* Locate some local-dynamic symbol still in use by this function
5047 so that we can print its name in some movdi_er_tlsldm pattern. */
5050 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
5054 if (GET_CODE (x) == SYMBOL_REF
5055 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
5057 cfun->machine->some_ld_name = XSTR (x, 0);
5065 get_some_local_dynamic_name (void)
5069 if (cfun->machine->some_ld_name)
5070 return cfun->machine->some_ld_name;
5072 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
5074 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
5075 return cfun->machine->some_ld_name;
5080 /* Print an operand. Recognize special options, documented below. */
5083 print_operand (FILE *file, rtx x, int code)
5090 /* Print the assembler name of the current function. */
5091 assemble_name (file, alpha_fnname);
5095 assemble_name (file, get_some_local_dynamic_name ());
5100 const char *trap = get_trap_mode_suffix ();
5101 const char *round = get_round_mode_suffix ();
5104 fprintf (file, (TARGET_AS_SLASH_BEFORE_SUFFIX ? "/%s%s" : "%s%s"),
5105 (trap ? trap : ""), (round ? round : ""));
5110 /* Generates single precision instruction suffix. */
5111 fputc ((TARGET_FLOAT_VAX ? 'f' : 's'), file);
5115 /* Generates double precision instruction suffix. */
5116 fputc ((TARGET_FLOAT_VAX ? 'g' : 't'), file);
5120 if (alpha_this_literal_sequence_number == 0)
5121 alpha_this_literal_sequence_number = alpha_next_sequence_number++;
5122 fprintf (file, "%d", alpha_this_literal_sequence_number);
5126 if (alpha_this_gpdisp_sequence_number == 0)
5127 alpha_this_gpdisp_sequence_number = alpha_next_sequence_number++;
5128 fprintf (file, "%d", alpha_this_gpdisp_sequence_number);
5132 if (GET_CODE (x) == HIGH)
5133 output_addr_const (file, XEXP (x, 0));
5135 output_operand_lossage ("invalid %%H value");
5142 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSGD_CALL)
5144 x = XVECEXP (x, 0, 0);
5145 lituse = "lituse_tlsgd";
5147 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSLDM_CALL)
5149 x = XVECEXP (x, 0, 0);
5150 lituse = "lituse_tlsldm";
5152 else if (CONST_INT_P (x))
5153 lituse = "lituse_jsr";
5156 output_operand_lossage ("invalid %%J value");
5160 if (x != const0_rtx)
5161 fprintf (file, "\t\t!%s!%d", lituse, (int) INTVAL (x));
5169 #ifdef HAVE_AS_JSRDIRECT_RELOCS
5170 lituse = "lituse_jsrdirect";
5172 lituse = "lituse_jsr";
5175 gcc_assert (INTVAL (x) != 0);
5176 fprintf (file, "\t\t!%s!%d", lituse, (int) INTVAL (x));
5180 /* If this operand is the constant zero, write it as "$31". */
5182 fprintf (file, "%s", reg_names[REGNO (x)]);
5183 else if (x == CONST0_RTX (GET_MODE (x)))
5184 fprintf (file, "$31");
5186 output_operand_lossage ("invalid %%r value");
5190 /* Similar, but for floating-point. */
5192 fprintf (file, "%s", reg_names[REGNO (x)]);
5193 else if (x == CONST0_RTX (GET_MODE (x)))
5194 fprintf (file, "$f31");
5196 output_operand_lossage ("invalid %%R value");
5200 /* Write the 1's complement of a constant. */
5201 if (!CONST_INT_P (x))
5202 output_operand_lossage ("invalid %%N value");
5204 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INTVAL (x));
5208 /* Write 1 << C, for a constant C. */
5209 if (!CONST_INT_P (x))
5210 output_operand_lossage ("invalid %%P value");
5212 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (HOST_WIDE_INT) 1 << INTVAL (x));
5216 /* Write the high-order 16 bits of a constant, sign-extended. */
5217 if (!CONST_INT_P (x))
5218 output_operand_lossage ("invalid %%h value");
5220 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) >> 16);
5224 /* Write the low-order 16 bits of a constant, sign-extended. */
5225 if (!CONST_INT_P (x))
5226 output_operand_lossage ("invalid %%L value");
5228 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5229 (INTVAL (x) & 0xffff) - 2 * (INTVAL (x) & 0x8000));
5233 /* Write mask for ZAP insn. */
5234 if (GET_CODE (x) == CONST_DOUBLE)
5236 HOST_WIDE_INT mask = 0;
5237 HOST_WIDE_INT value;
5239 value = CONST_DOUBLE_LOW (x);
5240 for (i = 0; i < HOST_BITS_PER_WIDE_INT / HOST_BITS_PER_CHAR;
5245 value = CONST_DOUBLE_HIGH (x);
5246 for (i = 0; i < HOST_BITS_PER_WIDE_INT / HOST_BITS_PER_CHAR;
5249 mask |= (1 << (i + sizeof (int)));
5251 fprintf (file, HOST_WIDE_INT_PRINT_DEC, mask & 0xff);
5254 else if (CONST_INT_P (x))
5256 HOST_WIDE_INT mask = 0, value = INTVAL (x);
5258 for (i = 0; i < 8; i++, value >>= 8)
5262 fprintf (file, HOST_WIDE_INT_PRINT_DEC, mask);
5265 output_operand_lossage ("invalid %%m value");
5269 /* 'b', 'w', 'l', or 'q' as the value of the constant. */
5270 if (!CONST_INT_P (x)
5271 || (INTVAL (x) != 8 && INTVAL (x) != 16
5272 && INTVAL (x) != 32 && INTVAL (x) != 64))
5273 output_operand_lossage ("invalid %%M value");
5275 fprintf (file, "%s",
5276 (INTVAL (x) == 8 ? "b"
5277 : INTVAL (x) == 16 ? "w"
5278 : INTVAL (x) == 32 ? "l"
5283 /* Similar, except do it from the mask. */
5284 if (CONST_INT_P (x))
5286 HOST_WIDE_INT value = INTVAL (x);
5293 if (value == 0xffff)
5298 if (value == 0xffffffff)
5309 else if (HOST_BITS_PER_WIDE_INT == 32
5310 && GET_CODE (x) == CONST_DOUBLE
5311 && CONST_DOUBLE_LOW (x) == 0xffffffff
5312 && CONST_DOUBLE_HIGH (x) == 0)
5317 output_operand_lossage ("invalid %%U value");
5321 /* Write the constant value divided by 8 for little-endian mode or
5322 (56 - value) / 8 for big-endian mode. */
5324 if (!CONST_INT_P (x)
5325 || (unsigned HOST_WIDE_INT) INTVAL (x) >= (WORDS_BIG_ENDIAN
5328 || (INTVAL (x) & 7) != 0)
5329 output_operand_lossage ("invalid %%s value");
5331 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5333 ? (56 - INTVAL (x)) / 8
5338 /* Same, except compute (64 - c) / 8 */
5340 if (!CONST_INT_P (x)
5341 && (unsigned HOST_WIDE_INT) INTVAL (x) >= 64
5342 && (INTVAL (x) & 7) != 8)
5343 output_operand_lossage ("invalid %%s value");
5345 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (64 - INTVAL (x)) / 8);
5350 /* On Unicos/Mk systems: use a DEX expression if the symbol
5351 clashes with a register name. */
5352 int dex = unicosmk_need_dex (x);
5354 fprintf (file, "DEX(%d)", dex);
5356 output_addr_const (file, x);
5360 case 'C': case 'D': case 'c': case 'd':
5361 /* Write out comparison name. */
5363 enum rtx_code c = GET_CODE (x);
5365 if (!COMPARISON_P (x))
5366 output_operand_lossage ("invalid %%C value");
5368 else if (code == 'D')
5369 c = reverse_condition (c);
5370 else if (code == 'c')
5371 c = swap_condition (c);
5372 else if (code == 'd')
5373 c = swap_condition (reverse_condition (c));
5376 fprintf (file, "ule");
5378 fprintf (file, "ult");
5379 else if (c == UNORDERED)
5380 fprintf (file, "un");
5382 fprintf (file, "%s", GET_RTX_NAME (c));
5387 /* Write the divide or modulus operator. */
5388 switch (GET_CODE (x))
5391 fprintf (file, "div%s", GET_MODE (x) == SImode ? "l" : "q");
5394 fprintf (file, "div%su", GET_MODE (x) == SImode ? "l" : "q");
5397 fprintf (file, "rem%s", GET_MODE (x) == SImode ? "l" : "q");
5400 fprintf (file, "rem%su", GET_MODE (x) == SImode ? "l" : "q");
5403 output_operand_lossage ("invalid %%E value");
5409 /* Write "_u" for unaligned access. */
5410 if (MEM_P (x) && GET_CODE (XEXP (x, 0)) == AND)
5411 fprintf (file, "_u");
5416 fprintf (file, "%s", reg_names[REGNO (x)]);
5418 output_address (XEXP (x, 0));
5419 else if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == UNSPEC)
5421 switch (XINT (XEXP (x, 0), 1))
5425 output_addr_const (file, XVECEXP (XEXP (x, 0), 0, 0));
5428 output_operand_lossage ("unknown relocation unspec");
5433 output_addr_const (file, x);
5437 output_operand_lossage ("invalid %%xn code");
5442 print_operand_address (FILE *file, rtx addr)
5445 HOST_WIDE_INT offset = 0;
5447 if (GET_CODE (addr) == AND)
5448 addr = XEXP (addr, 0);
5450 if (GET_CODE (addr) == PLUS
5451 && CONST_INT_P (XEXP (addr, 1)))
5453 offset = INTVAL (XEXP (addr, 1));
5454 addr = XEXP (addr, 0);
5457 if (GET_CODE (addr) == LO_SUM)
5459 const char *reloc16, *reloclo;
5460 rtx op1 = XEXP (addr, 1);
5462 if (GET_CODE (op1) == CONST && GET_CODE (XEXP (op1, 0)) == UNSPEC)
5464 op1 = XEXP (op1, 0);
5465 switch (XINT (op1, 1))
5469 reloclo = (alpha_tls_size == 16 ? "dtprel" : "dtprello");
5473 reloclo = (alpha_tls_size == 16 ? "tprel" : "tprello");
5476 output_operand_lossage ("unknown relocation unspec");
5480 output_addr_const (file, XVECEXP (op1, 0, 0));
5485 reloclo = "gprellow";
5486 output_addr_const (file, op1);
5490 fprintf (file, "+" HOST_WIDE_INT_PRINT_DEC, offset);
5492 addr = XEXP (addr, 0);
5493 switch (GET_CODE (addr))
5496 basereg = REGNO (addr);
5500 basereg = subreg_regno (addr);
5507 fprintf (file, "($%d)\t\t!%s", basereg,
5508 (basereg == 29 ? reloc16 : reloclo));
5512 switch (GET_CODE (addr))
5515 basereg = REGNO (addr);
5519 basereg = subreg_regno (addr);
5523 offset = INTVAL (addr);
5526 #if TARGET_ABI_OPEN_VMS
5528 fprintf (file, "%s", XSTR (addr, 0));
5532 gcc_assert (GET_CODE (XEXP (addr, 0)) == PLUS
5533 && GET_CODE (XEXP (XEXP (addr, 0), 0)) == SYMBOL_REF);
5534 fprintf (file, "%s+" HOST_WIDE_INT_PRINT_DEC,
5535 XSTR (XEXP (XEXP (addr, 0), 0), 0),
5536 INTVAL (XEXP (XEXP (addr, 0), 1)));
5544 fprintf (file, HOST_WIDE_INT_PRINT_DEC "($%d)", offset, basereg);
5547 /* Emit RTL insns to initialize the variable parts of a trampoline at
5548 M_TRAMP. FNDECL is target function's decl. CHAIN_VALUE is an rtx
5549 for the static chain value for the function. */
5552 alpha_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
5554 rtx fnaddr, mem, word1, word2;
5556 fnaddr = XEXP (DECL_RTL (fndecl), 0);
5558 #ifdef POINTERS_EXTEND_UNSIGNED
5559 fnaddr = convert_memory_address (Pmode, fnaddr);
5560 chain_value = convert_memory_address (Pmode, chain_value);
5563 if (TARGET_ABI_OPEN_VMS)
5568 /* Construct the name of the trampoline entry point. */
5569 fnname = XSTR (fnaddr, 0);
5570 trname = (char *) alloca (strlen (fnname) + 5);
5571 strcpy (trname, fnname);
5572 strcat (trname, "..tr");
5573 fnname = ggc_alloc_string (trname, strlen (trname) + 1);
5574 word2 = gen_rtx_SYMBOL_REF (Pmode, fnname);
5576 /* Trampoline (or "bounded") procedure descriptor is constructed from
5577 the function's procedure descriptor with certain fields zeroed IAW
5578 the VMS calling standard. This is stored in the first quadword. */
5579 word1 = force_reg (DImode, gen_const_mem (DImode, fnaddr));
5580 word1 = expand_and (DImode, word1, GEN_INT (0xffff0fff0000fff0), NULL);
5584 /* These 4 instructions are:
5589 We don't bother setting the HINT field of the jump; the nop
5590 is merely there for padding. */
5591 word1 = GEN_INT (0xa77b0010a43b0018);
5592 word2 = GEN_INT (0x47ff041f6bfb0000);
5595 /* Store the first two words, as computed above. */
5596 mem = adjust_address (m_tramp, DImode, 0);
5597 emit_move_insn (mem, word1);
5598 mem = adjust_address (m_tramp, DImode, 8);
5599 emit_move_insn (mem, word2);
5601 /* Store function address and static chain value. */
5602 mem = adjust_address (m_tramp, Pmode, 16);
5603 emit_move_insn (mem, fnaddr);
5604 mem = adjust_address (m_tramp, Pmode, 24);
5605 emit_move_insn (mem, chain_value);
5607 if (!TARGET_ABI_OPEN_VMS)
5609 emit_insn (gen_imb ());
5610 #ifdef ENABLE_EXECUTE_STACK
5611 emit_library_call (init_one_libfunc ("__enable_execute_stack"),
5612 LCT_NORMAL, VOIDmode, 1, XEXP (m_tramp, 0), Pmode);
5617 /* Determine where to put an argument to a function.
5618 Value is zero to push the argument on the stack,
5619 or a hard register in which to store the argument.
5621 MODE is the argument's machine mode.
5622 TYPE is the data type of the argument (as a tree).
5623 This is null for libcalls where that information may
5625 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5626 the preceding args and about the function being called.
5627 NAMED is nonzero if this argument is a named parameter
5628 (otherwise it is an extra parameter matching an ellipsis).
5630 On Alpha the first 6 words of args are normally in registers
5631 and the rest are pushed. */
5634 function_arg (CUMULATIVE_ARGS cum, enum machine_mode mode, tree type,
5635 int named ATTRIBUTE_UNUSED)
5640 /* Don't get confused and pass small structures in FP registers. */
5641 if (type && AGGREGATE_TYPE_P (type))
5645 #ifdef ENABLE_CHECKING
5646 /* With alpha_split_complex_arg, we shouldn't see any raw complex
5648 gcc_assert (!COMPLEX_MODE_P (mode));
5651 /* Set up defaults for FP operands passed in FP registers, and
5652 integral operands passed in integer registers. */
5653 if (TARGET_FPREGS && GET_MODE_CLASS (mode) == MODE_FLOAT)
5659 /* ??? Irritatingly, the definition of CUMULATIVE_ARGS is different for
5660 the three platforms, so we can't avoid conditional compilation. */
5661 #if TARGET_ABI_OPEN_VMS
5663 if (mode == VOIDmode)
5664 return alpha_arg_info_reg_val (cum);
5666 num_args = cum.num_args;
5668 || targetm.calls.must_pass_in_stack (mode, type))
5671 #elif TARGET_ABI_UNICOSMK
5675 /* If this is the last argument, generate the call info word (CIW). */
5676 /* ??? We don't include the caller's line number in the CIW because
5677 I don't know how to determine it if debug infos are turned off. */
5678 if (mode == VOIDmode)
5687 for (i = 0; i < cum.num_reg_words && i < 5; i++)
5688 if (cum.reg_args_type[i])
5689 lo |= (1 << (7 - i));
5691 if (cum.num_reg_words == 6 && cum.reg_args_type[5])
5694 lo |= cum.num_reg_words;
5696 #if HOST_BITS_PER_WIDE_INT == 32
5697 hi = (cum.num_args << 20) | cum.num_arg_words;
5699 lo = lo | ((HOST_WIDE_INT) cum.num_args << 52)
5700 | ((HOST_WIDE_INT) cum.num_arg_words << 32);
5703 ciw = immed_double_const (lo, hi, DImode);
5705 return gen_rtx_UNSPEC (DImode, gen_rtvec (1, ciw),
5706 UNSPEC_UMK_LOAD_CIW);
5709 size = ALPHA_ARG_SIZE (mode, type, named);
5710 num_args = cum.num_reg_words;
5712 || cum.num_reg_words + size > 6
5713 || targetm.calls.must_pass_in_stack (mode, type))
5715 else if (type && TYPE_MODE (type) == BLKmode)
5719 reg1 = gen_rtx_REG (DImode, num_args + 16);
5720 reg1 = gen_rtx_EXPR_LIST (DImode, reg1, const0_rtx);
5722 /* The argument fits in two registers. Note that we still need to
5723 reserve a register for empty structures. */
5727 return gen_rtx_PARALLEL (mode, gen_rtvec (1, reg1));
5730 reg2 = gen_rtx_REG (DImode, num_args + 17);
5731 reg2 = gen_rtx_EXPR_LIST (DImode, reg2, GEN_INT (8));
5732 return gen_rtx_PARALLEL (mode, gen_rtvec (2, reg1, reg2));
5736 #elif TARGET_ABI_OSF
5742 /* VOID is passed as a special flag for "last argument". */
5743 if (type == void_type_node)
5745 else if (targetm.calls.must_pass_in_stack (mode, type))
5749 #error Unhandled ABI
5752 return gen_rtx_REG (mode, num_args + basereg);
5756 alpha_arg_partial_bytes (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
5757 enum machine_mode mode ATTRIBUTE_UNUSED,
5758 tree type ATTRIBUTE_UNUSED,
5759 bool named ATTRIBUTE_UNUSED)
5763 #if TARGET_ABI_OPEN_VMS
5764 if (cum->num_args < 6
5765 && 6 < cum->num_args + ALPHA_ARG_SIZE (mode, type, named))
5766 words = 6 - cum->num_args;
5767 #elif TARGET_ABI_UNICOSMK
5768 /* Never any split arguments. */
5769 #elif TARGET_ABI_OSF
5770 if (*cum < 6 && 6 < *cum + ALPHA_ARG_SIZE (mode, type, named))
5773 #error Unhandled ABI
5776 return words * UNITS_PER_WORD;
5780 /* Return true if TYPE must be returned in memory, instead of in registers. */
5783 alpha_return_in_memory (const_tree type, const_tree fndecl ATTRIBUTE_UNUSED)
5785 enum machine_mode mode = VOIDmode;
5790 mode = TYPE_MODE (type);
5792 /* All aggregates are returned in memory, except on OpenVMS where
5793 records that fit 64 bits should be returned by immediate value
5794 as required by section 3.8.7.1 of the OpenVMS Calling Standard. */
5795 if (TARGET_ABI_OPEN_VMS
5796 && TREE_CODE (type) != ARRAY_TYPE
5797 && (unsigned HOST_WIDE_INT) int_size_in_bytes(type) <= 8)
5800 if (AGGREGATE_TYPE_P (type))
5804 size = GET_MODE_SIZE (mode);
5805 switch (GET_MODE_CLASS (mode))
5807 case MODE_VECTOR_FLOAT:
5808 /* Pass all float vectors in memory, like an aggregate. */
5811 case MODE_COMPLEX_FLOAT:
5812 /* We judge complex floats on the size of their element,
5813 not the size of the whole type. */
5814 size = GET_MODE_UNIT_SIZE (mode);
5819 case MODE_COMPLEX_INT:
5820 case MODE_VECTOR_INT:
5824 /* ??? We get called on all sorts of random stuff from
5825 aggregate_value_p. We must return something, but it's not
5826 clear what's safe to return. Pretend it's a struct I
5831 /* Otherwise types must fit in one register. */
5832 return size > UNITS_PER_WORD;
5835 /* Return true if TYPE should be passed by invisible reference. */
5838 alpha_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED,
5839 enum machine_mode mode,
5840 const_tree type ATTRIBUTE_UNUSED,
5841 bool named ATTRIBUTE_UNUSED)
5843 return mode == TFmode || mode == TCmode;
5846 /* Define how to find the value returned by a function. VALTYPE is the
5847 data type of the value (as a tree). If the precise function being
5848 called is known, FUNC is its FUNCTION_DECL; otherwise, FUNC is 0.
5849 MODE is set instead of VALTYPE for libcalls.
5851 On Alpha the value is found in $0 for integer functions and
5852 $f0 for floating-point functions. */
5855 function_value (const_tree valtype, const_tree func ATTRIBUTE_UNUSED,
5856 enum machine_mode mode)
5858 unsigned int regnum, dummy ATTRIBUTE_UNUSED;
5859 enum mode_class mclass;
5861 gcc_assert (!valtype || !alpha_return_in_memory (valtype, func));
5864 mode = TYPE_MODE (valtype);
5866 mclass = GET_MODE_CLASS (mode);
5870 /* Do the same thing as PROMOTE_MODE except for libcalls on VMS,
5871 where we have them returning both SImode and DImode. */
5872 if (!(TARGET_ABI_OPEN_VMS && valtype && AGGREGATE_TYPE_P (valtype)))
5873 PROMOTE_MODE (mode, dummy, valtype);
5876 case MODE_COMPLEX_INT:
5877 case MODE_VECTOR_INT:
5885 case MODE_COMPLEX_FLOAT:
5887 enum machine_mode cmode = GET_MODE_INNER (mode);
5889 return gen_rtx_PARALLEL
5892 gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (cmode, 32),
5894 gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (cmode, 33),
5895 GEN_INT (GET_MODE_SIZE (cmode)))));
5899 /* We should only reach here for BLKmode on VMS. */
5900 gcc_assert (TARGET_ABI_OPEN_VMS && mode == BLKmode);
5908 return gen_rtx_REG (mode, regnum);
5911 /* TCmode complex values are passed by invisible reference. We
5912 should not split these values. */
5915 alpha_split_complex_arg (const_tree type)
5917 return TYPE_MODE (type) != TCmode;
5921 alpha_build_builtin_va_list (void)
5923 tree base, ofs, space, record, type_decl;
5925 if (TARGET_ABI_OPEN_VMS || TARGET_ABI_UNICOSMK)
5926 return ptr_type_node;
5928 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
5929 type_decl = build_decl (BUILTINS_LOCATION,
5930 TYPE_DECL, get_identifier ("__va_list_tag"), record);
5931 TREE_CHAIN (record) = type_decl;
5932 TYPE_NAME (record) = type_decl;
5934 /* C++? SET_IS_AGGR_TYPE (record, 1); */
5936 /* Dummy field to prevent alignment warnings. */
5937 space = build_decl (BUILTINS_LOCATION,
5938 FIELD_DECL, NULL_TREE, integer_type_node);
5939 DECL_FIELD_CONTEXT (space) = record;
5940 DECL_ARTIFICIAL (space) = 1;
5941 DECL_IGNORED_P (space) = 1;
5943 ofs = build_decl (BUILTINS_LOCATION,
5944 FIELD_DECL, get_identifier ("__offset"),
5946 DECL_FIELD_CONTEXT (ofs) = record;
5947 DECL_CHAIN (ofs) = space;
5949 base = build_decl (BUILTINS_LOCATION,
5950 FIELD_DECL, get_identifier ("__base"),
5952 DECL_FIELD_CONTEXT (base) = record;
5953 DECL_CHAIN (base) = ofs;
5955 TYPE_FIELDS (record) = base;
5956 layout_type (record);
5958 va_list_gpr_counter_field = ofs;
5963 /* Helper function for alpha_stdarg_optimize_hook. Skip over casts
5964 and constant additions. */
5967 va_list_skip_additions (tree lhs)
5973 enum tree_code code;
5975 stmt = SSA_NAME_DEF_STMT (lhs);
5977 if (gimple_code (stmt) == GIMPLE_PHI)
5980 if (!is_gimple_assign (stmt)
5981 || gimple_assign_lhs (stmt) != lhs)
5984 if (TREE_CODE (gimple_assign_rhs1 (stmt)) != SSA_NAME)
5986 code = gimple_assign_rhs_code (stmt);
5987 if (!CONVERT_EXPR_CODE_P (code)
5988 && ((code != PLUS_EXPR && code != POINTER_PLUS_EXPR)
5989 || TREE_CODE (gimple_assign_rhs2 (stmt)) != INTEGER_CST
5990 || !host_integerp (gimple_assign_rhs2 (stmt), 1)))
5993 lhs = gimple_assign_rhs1 (stmt);
5997 /* Check if LHS = RHS statement is
5998 LHS = *(ap.__base + ap.__offset + cst)
6001 + ((ap.__offset + cst <= 47)
6002 ? ap.__offset + cst - 48 : ap.__offset + cst) + cst2).
6003 If the former, indicate that GPR registers are needed,
6004 if the latter, indicate that FPR registers are needed.
6006 Also look for LHS = (*ptr).field, where ptr is one of the forms
6009 On alpha, cfun->va_list_gpr_size is used as size of the needed
6010 regs and cfun->va_list_fpr_size is a bitmask, bit 0 set if GPR
6011 registers are needed and bit 1 set if FPR registers are needed.
6012 Return true if va_list references should not be scanned for the
6013 current statement. */
6016 alpha_stdarg_optimize_hook (struct stdarg_info *si, const_gimple stmt)
6018 tree base, offset, rhs;
6022 if (get_gimple_rhs_class (gimple_assign_rhs_code (stmt))
6023 != GIMPLE_SINGLE_RHS)
6026 rhs = gimple_assign_rhs1 (stmt);
6027 while (handled_component_p (rhs))
6028 rhs = TREE_OPERAND (rhs, 0);
6029 if (TREE_CODE (rhs) != MEM_REF
6030 || TREE_CODE (TREE_OPERAND (rhs, 0)) != SSA_NAME)
6033 stmt = va_list_skip_additions (TREE_OPERAND (rhs, 0));
6035 || !is_gimple_assign (stmt)
6036 || gimple_assign_rhs_code (stmt) != POINTER_PLUS_EXPR)
6039 base = gimple_assign_rhs1 (stmt);
6040 if (TREE_CODE (base) == SSA_NAME)
6042 base_stmt = va_list_skip_additions (base);
6044 && is_gimple_assign (base_stmt)
6045 && gimple_assign_rhs_code (base_stmt) == COMPONENT_REF)
6046 base = gimple_assign_rhs1 (base_stmt);
6049 if (TREE_CODE (base) != COMPONENT_REF
6050 || TREE_OPERAND (base, 1) != TYPE_FIELDS (va_list_type_node))
6052 base = gimple_assign_rhs2 (stmt);
6053 if (TREE_CODE (base) == SSA_NAME)
6055 base_stmt = va_list_skip_additions (base);
6057 && is_gimple_assign (base_stmt)
6058 && gimple_assign_rhs_code (base_stmt) == COMPONENT_REF)
6059 base = gimple_assign_rhs1 (base_stmt);
6062 if (TREE_CODE (base) != COMPONENT_REF
6063 || TREE_OPERAND (base, 1) != TYPE_FIELDS (va_list_type_node))
6069 base = get_base_address (base);
6070 if (TREE_CODE (base) != VAR_DECL
6071 || !bitmap_bit_p (si->va_list_vars, DECL_UID (base)))
6074 offset = gimple_op (stmt, 1 + offset_arg);
6075 if (TREE_CODE (offset) == SSA_NAME)
6077 gimple offset_stmt = va_list_skip_additions (offset);
6080 && gimple_code (offset_stmt) == GIMPLE_PHI)
6083 gimple arg1_stmt, arg2_stmt;
6085 enum tree_code code1, code2;
6087 if (gimple_phi_num_args (offset_stmt) != 2)
6091 = va_list_skip_additions (gimple_phi_arg_def (offset_stmt, 0));
6093 = va_list_skip_additions (gimple_phi_arg_def (offset_stmt, 1));
6094 if (arg1_stmt == NULL
6095 || !is_gimple_assign (arg1_stmt)
6096 || arg2_stmt == NULL
6097 || !is_gimple_assign (arg2_stmt))
6100 code1 = gimple_assign_rhs_code (arg1_stmt);
6101 code2 = gimple_assign_rhs_code (arg2_stmt);
6102 if (code1 == COMPONENT_REF
6103 && (code2 == MINUS_EXPR || code2 == PLUS_EXPR))
6105 else if (code2 == COMPONENT_REF
6106 && (code1 == MINUS_EXPR || code1 == PLUS_EXPR))
6108 gimple tem = arg1_stmt;
6110 arg1_stmt = arg2_stmt;
6116 if (!host_integerp (gimple_assign_rhs2 (arg2_stmt), 0))
6119 sub = tree_low_cst (gimple_assign_rhs2 (arg2_stmt), 0);
6120 if (code2 == MINUS_EXPR)
6122 if (sub < -48 || sub > -32)
6125 arg1 = gimple_assign_rhs1 (arg1_stmt);
6126 arg2 = gimple_assign_rhs1 (arg2_stmt);
6127 if (TREE_CODE (arg2) == SSA_NAME)
6129 arg2_stmt = va_list_skip_additions (arg2);
6130 if (arg2_stmt == NULL
6131 || !is_gimple_assign (arg2_stmt)
6132 || gimple_assign_rhs_code (arg2_stmt) != COMPONENT_REF)
6134 arg2 = gimple_assign_rhs1 (arg2_stmt);
6139 if (TREE_CODE (arg1) != COMPONENT_REF
6140 || TREE_OPERAND (arg1, 1) != va_list_gpr_counter_field
6141 || get_base_address (arg1) != base)
6144 /* Need floating point regs. */
6145 cfun->va_list_fpr_size |= 2;
6149 && is_gimple_assign (offset_stmt)
6150 && gimple_assign_rhs_code (offset_stmt) == COMPONENT_REF)
6151 offset = gimple_assign_rhs1 (offset_stmt);
6153 if (TREE_CODE (offset) != COMPONENT_REF
6154 || TREE_OPERAND (offset, 1) != va_list_gpr_counter_field
6155 || get_base_address (offset) != base)
6158 /* Need general regs. */
6159 cfun->va_list_fpr_size |= 1;
6163 si->va_list_escapes = true;
6168 /* Perform any needed actions needed for a function that is receiving a
6169 variable number of arguments. */
6172 alpha_setup_incoming_varargs (CUMULATIVE_ARGS *pcum, enum machine_mode mode,
6173 tree type, int *pretend_size, int no_rtl)
6175 CUMULATIVE_ARGS cum = *pcum;
6177 /* Skip the current argument. */
6178 FUNCTION_ARG_ADVANCE (cum, mode, type, 1);
6180 #if TARGET_ABI_UNICOSMK
6181 /* On Unicos/Mk, the standard subroutine __T3E_MISMATCH stores all register
6182 arguments on the stack. Unfortunately, it doesn't always store the first
6183 one (i.e. the one that arrives in $16 or $f16). This is not a problem
6184 with stdargs as we always have at least one named argument there. */
6185 if (cum.num_reg_words < 6)
6189 emit_insn (gen_umk_mismatch_args (GEN_INT (cum.num_reg_words)));
6190 emit_insn (gen_arg_home_umk ());
6194 #elif TARGET_ABI_OPEN_VMS
6195 /* For VMS, we allocate space for all 6 arg registers plus a count.
6197 However, if NO registers need to be saved, don't allocate any space.
6198 This is not only because we won't need the space, but because AP
6199 includes the current_pretend_args_size and we don't want to mess up
6200 any ap-relative addresses already made. */
6201 if (cum.num_args < 6)
6205 emit_move_insn (gen_rtx_REG (DImode, 1), virtual_incoming_args_rtx);
6206 emit_insn (gen_arg_home ());
6208 *pretend_size = 7 * UNITS_PER_WORD;
6211 /* On OSF/1 and friends, we allocate space for all 12 arg registers, but
6212 only push those that are remaining. However, if NO registers need to
6213 be saved, don't allocate any space. This is not only because we won't
6214 need the space, but because AP includes the current_pretend_args_size
6215 and we don't want to mess up any ap-relative addresses already made.
6217 If we are not to use the floating-point registers, save the integer
6218 registers where we would put the floating-point registers. This is
6219 not the most efficient way to implement varargs with just one register
6220 class, but it isn't worth doing anything more efficient in this rare
6228 alias_set_type set = get_varargs_alias_set ();
6231 count = cfun->va_list_gpr_size / UNITS_PER_WORD;
6232 if (count > 6 - cum)
6235 /* Detect whether integer registers or floating-point registers
6236 are needed by the detected va_arg statements. See above for
6237 how these values are computed. Note that the "escape" value
6238 is VA_LIST_MAX_FPR_SIZE, which is 255, which has both of
6240 gcc_assert ((VA_LIST_MAX_FPR_SIZE & 3) == 3);
6242 if (cfun->va_list_fpr_size & 1)
6244 tmp = gen_rtx_MEM (BLKmode,
6245 plus_constant (virtual_incoming_args_rtx,
6246 (cum + 6) * UNITS_PER_WORD));
6247 MEM_NOTRAP_P (tmp) = 1;
6248 set_mem_alias_set (tmp, set);
6249 move_block_from_reg (16 + cum, tmp, count);
6252 if (cfun->va_list_fpr_size & 2)
6254 tmp = gen_rtx_MEM (BLKmode,
6255 plus_constant (virtual_incoming_args_rtx,
6256 cum * UNITS_PER_WORD));
6257 MEM_NOTRAP_P (tmp) = 1;
6258 set_mem_alias_set (tmp, set);
6259 move_block_from_reg (16 + cum + TARGET_FPREGS*32, tmp, count);
6262 *pretend_size = 12 * UNITS_PER_WORD;
6267 alpha_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
6269 HOST_WIDE_INT offset;
6270 tree t, offset_field, base_field;
6272 if (TREE_CODE (TREE_TYPE (valist)) == ERROR_MARK)
6275 if (TARGET_ABI_UNICOSMK)
6276 std_expand_builtin_va_start (valist, nextarg);
6278 /* For Unix, TARGET_SETUP_INCOMING_VARARGS moves the starting address base
6279 up by 48, storing fp arg registers in the first 48 bytes, and the
6280 integer arg registers in the next 48 bytes. This is only done,
6281 however, if any integer registers need to be stored.
6283 If no integer registers need be stored, then we must subtract 48
6284 in order to account for the integer arg registers which are counted
6285 in argsize above, but which are not actually stored on the stack.
6286 Must further be careful here about structures straddling the last
6287 integer argument register; that futzes with pretend_args_size,
6288 which changes the meaning of AP. */
6291 offset = TARGET_ABI_OPEN_VMS ? UNITS_PER_WORD : 6 * UNITS_PER_WORD;
6293 offset = -6 * UNITS_PER_WORD + crtl->args.pretend_args_size;
6295 if (TARGET_ABI_OPEN_VMS)
6297 t = make_tree (ptr_type_node, virtual_incoming_args_rtx);
6298 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t,
6299 size_int (offset + NUM_ARGS * UNITS_PER_WORD));
6300 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
6301 TREE_SIDE_EFFECTS (t) = 1;
6302 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6306 base_field = TYPE_FIELDS (TREE_TYPE (valist));
6307 offset_field = DECL_CHAIN (base_field);
6309 base_field = build3 (COMPONENT_REF, TREE_TYPE (base_field),
6310 valist, base_field, NULL_TREE);
6311 offset_field = build3 (COMPONENT_REF, TREE_TYPE (offset_field),
6312 valist, offset_field, NULL_TREE);
6314 t = make_tree (ptr_type_node, virtual_incoming_args_rtx);
6315 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t,
6317 t = build2 (MODIFY_EXPR, TREE_TYPE (base_field), base_field, t);
6318 TREE_SIDE_EFFECTS (t) = 1;
6319 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6321 t = build_int_cst (NULL_TREE, NUM_ARGS * UNITS_PER_WORD);
6322 t = build2 (MODIFY_EXPR, TREE_TYPE (offset_field), offset_field, t);
6323 TREE_SIDE_EFFECTS (t) = 1;
6324 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6329 alpha_gimplify_va_arg_1 (tree type, tree base, tree offset,
6332 tree type_size, ptr_type, addend, t, addr;
6333 gimple_seq internal_post;
6335 /* If the type could not be passed in registers, skip the block
6336 reserved for the registers. */
6337 if (targetm.calls.must_pass_in_stack (TYPE_MODE (type), type))
6339 t = build_int_cst (TREE_TYPE (offset), 6*8);
6340 gimplify_assign (offset,
6341 build2 (MAX_EXPR, TREE_TYPE (offset), offset, t),
6346 ptr_type = build_pointer_type_for_mode (type, ptr_mode, true);
6348 if (TREE_CODE (type) == COMPLEX_TYPE)
6350 tree real_part, imag_part, real_temp;
6352 real_part = alpha_gimplify_va_arg_1 (TREE_TYPE (type), base,
6355 /* Copy the value into a new temporary, lest the formal temporary
6356 be reused out from under us. */
6357 real_temp = get_initialized_tmp_var (real_part, pre_p, NULL);
6359 imag_part = alpha_gimplify_va_arg_1 (TREE_TYPE (type), base,
6362 return build2 (COMPLEX_EXPR, type, real_temp, imag_part);
6364 else if (TREE_CODE (type) == REAL_TYPE)
6366 tree fpaddend, cond, fourtyeight;
6368 fourtyeight = build_int_cst (TREE_TYPE (addend), 6*8);
6369 fpaddend = fold_build2 (MINUS_EXPR, TREE_TYPE (addend),
6370 addend, fourtyeight);
6371 cond = fold_build2 (LT_EXPR, boolean_type_node, addend, fourtyeight);
6372 addend = fold_build3 (COND_EXPR, TREE_TYPE (addend), cond,
6376 /* Build the final address and force that value into a temporary. */
6377 addr = build2 (POINTER_PLUS_EXPR, ptr_type, fold_convert (ptr_type, base),
6378 fold_convert (sizetype, addend));
6379 internal_post = NULL;
6380 gimplify_expr (&addr, pre_p, &internal_post, is_gimple_val, fb_rvalue);
6381 gimple_seq_add_seq (pre_p, internal_post);
6383 /* Update the offset field. */
6384 type_size = TYPE_SIZE_UNIT (TYPE_MAIN_VARIANT (type));
6385 if (type_size == NULL || TREE_OVERFLOW (type_size))
6389 t = size_binop (PLUS_EXPR, type_size, size_int (7));
6390 t = size_binop (TRUNC_DIV_EXPR, t, size_int (8));
6391 t = size_binop (MULT_EXPR, t, size_int (8));
6393 t = fold_convert (TREE_TYPE (offset), t);
6394 gimplify_assign (offset, build2 (PLUS_EXPR, TREE_TYPE (offset), offset, t),
6397 return build_va_arg_indirect_ref (addr);
6401 alpha_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
6404 tree offset_field, base_field, offset, base, t, r;
6407 if (TARGET_ABI_OPEN_VMS || TARGET_ABI_UNICOSMK)
6408 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
6410 base_field = TYPE_FIELDS (va_list_type_node);
6411 offset_field = DECL_CHAIN (base_field);
6412 base_field = build3 (COMPONENT_REF, TREE_TYPE (base_field),
6413 valist, base_field, NULL_TREE);
6414 offset_field = build3 (COMPONENT_REF, TREE_TYPE (offset_field),
6415 valist, offset_field, NULL_TREE);
6417 /* Pull the fields of the structure out into temporaries. Since we never
6418 modify the base field, we can use a formal temporary. Sign-extend the
6419 offset field so that it's the proper width for pointer arithmetic. */
6420 base = get_formal_tmp_var (base_field, pre_p);
6422 t = fold_convert (lang_hooks.types.type_for_size (64, 0), offset_field);
6423 offset = get_initialized_tmp_var (t, pre_p, NULL);
6425 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, false);
6427 type = build_pointer_type_for_mode (type, ptr_mode, true);
6429 /* Find the value. Note that this will be a stable indirection, or
6430 a composite of stable indirections in the case of complex. */
6431 r = alpha_gimplify_va_arg_1 (type, base, offset, pre_p);
6433 /* Stuff the offset temporary back into its field. */
6434 gimplify_assign (unshare_expr (offset_field),
6435 fold_convert (TREE_TYPE (offset_field), offset), pre_p);
6438 r = build_va_arg_indirect_ref (r);
6447 ALPHA_BUILTIN_CMPBGE,
6448 ALPHA_BUILTIN_EXTBL,
6449 ALPHA_BUILTIN_EXTWL,
6450 ALPHA_BUILTIN_EXTLL,
6451 ALPHA_BUILTIN_EXTQL,
6452 ALPHA_BUILTIN_EXTWH,
6453 ALPHA_BUILTIN_EXTLH,
6454 ALPHA_BUILTIN_EXTQH,
6455 ALPHA_BUILTIN_INSBL,
6456 ALPHA_BUILTIN_INSWL,
6457 ALPHA_BUILTIN_INSLL,
6458 ALPHA_BUILTIN_INSQL,
6459 ALPHA_BUILTIN_INSWH,
6460 ALPHA_BUILTIN_INSLH,
6461 ALPHA_BUILTIN_INSQH,
6462 ALPHA_BUILTIN_MSKBL,
6463 ALPHA_BUILTIN_MSKWL,
6464 ALPHA_BUILTIN_MSKLL,
6465 ALPHA_BUILTIN_MSKQL,
6466 ALPHA_BUILTIN_MSKWH,
6467 ALPHA_BUILTIN_MSKLH,
6468 ALPHA_BUILTIN_MSKQH,
6469 ALPHA_BUILTIN_UMULH,
6471 ALPHA_BUILTIN_ZAPNOT,
6472 ALPHA_BUILTIN_AMASK,
6473 ALPHA_BUILTIN_IMPLVER,
6475 ALPHA_BUILTIN_THREAD_POINTER,
6476 ALPHA_BUILTIN_SET_THREAD_POINTER,
6477 ALPHA_BUILTIN_ESTABLISH_VMS_CONDITION_HANDLER,
6478 ALPHA_BUILTIN_REVERT_VMS_CONDITION_HANDLER,
6481 ALPHA_BUILTIN_MINUB8,
6482 ALPHA_BUILTIN_MINSB8,
6483 ALPHA_BUILTIN_MINUW4,
6484 ALPHA_BUILTIN_MINSW4,
6485 ALPHA_BUILTIN_MAXUB8,
6486 ALPHA_BUILTIN_MAXSB8,
6487 ALPHA_BUILTIN_MAXUW4,
6488 ALPHA_BUILTIN_MAXSW4,
6492 ALPHA_BUILTIN_UNPKBL,
6493 ALPHA_BUILTIN_UNPKBW,
6498 ALPHA_BUILTIN_CTPOP,
6503 static enum insn_code const code_for_builtin[ALPHA_BUILTIN_max] = {
6504 CODE_FOR_builtin_cmpbge,
6505 CODE_FOR_builtin_extbl,
6506 CODE_FOR_builtin_extwl,
6507 CODE_FOR_builtin_extll,
6508 CODE_FOR_builtin_extql,
6509 CODE_FOR_builtin_extwh,
6510 CODE_FOR_builtin_extlh,
6511 CODE_FOR_builtin_extqh,
6512 CODE_FOR_builtin_insbl,
6513 CODE_FOR_builtin_inswl,
6514 CODE_FOR_builtin_insll,
6515 CODE_FOR_builtin_insql,
6516 CODE_FOR_builtin_inswh,
6517 CODE_FOR_builtin_inslh,
6518 CODE_FOR_builtin_insqh,
6519 CODE_FOR_builtin_mskbl,
6520 CODE_FOR_builtin_mskwl,
6521 CODE_FOR_builtin_mskll,
6522 CODE_FOR_builtin_mskql,
6523 CODE_FOR_builtin_mskwh,
6524 CODE_FOR_builtin_msklh,
6525 CODE_FOR_builtin_mskqh,
6526 CODE_FOR_umuldi3_highpart,
6527 CODE_FOR_builtin_zap,
6528 CODE_FOR_builtin_zapnot,
6529 CODE_FOR_builtin_amask,
6530 CODE_FOR_builtin_implver,
6531 CODE_FOR_builtin_rpcc,
6534 CODE_FOR_builtin_establish_vms_condition_handler,
6535 CODE_FOR_builtin_revert_vms_condition_handler,
6538 CODE_FOR_builtin_minub8,
6539 CODE_FOR_builtin_minsb8,
6540 CODE_FOR_builtin_minuw4,
6541 CODE_FOR_builtin_minsw4,
6542 CODE_FOR_builtin_maxub8,
6543 CODE_FOR_builtin_maxsb8,
6544 CODE_FOR_builtin_maxuw4,
6545 CODE_FOR_builtin_maxsw4,
6546 CODE_FOR_builtin_perr,
6547 CODE_FOR_builtin_pklb,
6548 CODE_FOR_builtin_pkwb,
6549 CODE_FOR_builtin_unpkbl,
6550 CODE_FOR_builtin_unpkbw,
6555 CODE_FOR_popcountdi2
6558 struct alpha_builtin_def
6561 enum alpha_builtin code;
6562 unsigned int target_mask;
6566 static struct alpha_builtin_def const zero_arg_builtins[] = {
6567 { "__builtin_alpha_implver", ALPHA_BUILTIN_IMPLVER, 0, true },
6568 { "__builtin_alpha_rpcc", ALPHA_BUILTIN_RPCC, 0, false }
6571 static struct alpha_builtin_def const one_arg_builtins[] = {
6572 { "__builtin_alpha_amask", ALPHA_BUILTIN_AMASK, 0, true },
6573 { "__builtin_alpha_pklb", ALPHA_BUILTIN_PKLB, MASK_MAX, true },
6574 { "__builtin_alpha_pkwb", ALPHA_BUILTIN_PKWB, MASK_MAX, true },
6575 { "__builtin_alpha_unpkbl", ALPHA_BUILTIN_UNPKBL, MASK_MAX, true },
6576 { "__builtin_alpha_unpkbw", ALPHA_BUILTIN_UNPKBW, MASK_MAX, true },
6577 { "__builtin_alpha_cttz", ALPHA_BUILTIN_CTTZ, MASK_CIX, true },
6578 { "__builtin_alpha_ctlz", ALPHA_BUILTIN_CTLZ, MASK_CIX, true },
6579 { "__builtin_alpha_ctpop", ALPHA_BUILTIN_CTPOP, MASK_CIX, true }
6582 static struct alpha_builtin_def const two_arg_builtins[] = {
6583 { "__builtin_alpha_cmpbge", ALPHA_BUILTIN_CMPBGE, 0, true },
6584 { "__builtin_alpha_extbl", ALPHA_BUILTIN_EXTBL, 0, true },
6585 { "__builtin_alpha_extwl", ALPHA_BUILTIN_EXTWL, 0, true },
6586 { "__builtin_alpha_extll", ALPHA_BUILTIN_EXTLL, 0, true },
6587 { "__builtin_alpha_extql", ALPHA_BUILTIN_EXTQL, 0, true },
6588 { "__builtin_alpha_extwh", ALPHA_BUILTIN_EXTWH, 0, true },
6589 { "__builtin_alpha_extlh", ALPHA_BUILTIN_EXTLH, 0, true },
6590 { "__builtin_alpha_extqh", ALPHA_BUILTIN_EXTQH, 0, true },
6591 { "__builtin_alpha_insbl", ALPHA_BUILTIN_INSBL, 0, true },
6592 { "__builtin_alpha_inswl", ALPHA_BUILTIN_INSWL, 0, true },
6593 { "__builtin_alpha_insll", ALPHA_BUILTIN_INSLL, 0, true },
6594 { "__builtin_alpha_insql", ALPHA_BUILTIN_INSQL, 0, true },
6595 { "__builtin_alpha_inswh", ALPHA_BUILTIN_INSWH, 0, true },
6596 { "__builtin_alpha_inslh", ALPHA_BUILTIN_INSLH, 0, true },
6597 { "__builtin_alpha_insqh", ALPHA_BUILTIN_INSQH, 0, true },
6598 { "__builtin_alpha_mskbl", ALPHA_BUILTIN_MSKBL, 0, true },
6599 { "__builtin_alpha_mskwl", ALPHA_BUILTIN_MSKWL, 0, true },
6600 { "__builtin_alpha_mskll", ALPHA_BUILTIN_MSKLL, 0, true },
6601 { "__builtin_alpha_mskql", ALPHA_BUILTIN_MSKQL, 0, true },
6602 { "__builtin_alpha_mskwh", ALPHA_BUILTIN_MSKWH, 0, true },
6603 { "__builtin_alpha_msklh", ALPHA_BUILTIN_MSKLH, 0, true },
6604 { "__builtin_alpha_mskqh", ALPHA_BUILTIN_MSKQH, 0, true },
6605 { "__builtin_alpha_umulh", ALPHA_BUILTIN_UMULH, 0, true },
6606 { "__builtin_alpha_zap", ALPHA_BUILTIN_ZAP, 0, true },
6607 { "__builtin_alpha_zapnot", ALPHA_BUILTIN_ZAPNOT, 0, true },
6608 { "__builtin_alpha_minub8", ALPHA_BUILTIN_MINUB8, MASK_MAX, true },
6609 { "__builtin_alpha_minsb8", ALPHA_BUILTIN_MINSB8, MASK_MAX, true },
6610 { "__builtin_alpha_minuw4", ALPHA_BUILTIN_MINUW4, MASK_MAX, true },
6611 { "__builtin_alpha_minsw4", ALPHA_BUILTIN_MINSW4, MASK_MAX, true },
6612 { "__builtin_alpha_maxub8", ALPHA_BUILTIN_MAXUB8, MASK_MAX, true },
6613 { "__builtin_alpha_maxsb8", ALPHA_BUILTIN_MAXSB8, MASK_MAX, true },
6614 { "__builtin_alpha_maxuw4", ALPHA_BUILTIN_MAXUW4, MASK_MAX, true },
6615 { "__builtin_alpha_maxsw4", ALPHA_BUILTIN_MAXSW4, MASK_MAX, true },
6616 { "__builtin_alpha_perr", ALPHA_BUILTIN_PERR, MASK_MAX, true }
6619 static GTY(()) tree alpha_v8qi_u;
6620 static GTY(()) tree alpha_v8qi_s;
6621 static GTY(()) tree alpha_v4hi_u;
6622 static GTY(()) tree alpha_v4hi_s;
6624 /* Helper function of alpha_init_builtins. Add the COUNT built-in
6625 functions pointed to by P, with function type FTYPE. */
6628 alpha_add_builtins (const struct alpha_builtin_def *p, size_t count,
6634 for (i = 0; i < count; ++i, ++p)
6635 if ((target_flags & p->target_mask) == p->target_mask)
6637 decl = add_builtin_function (p->name, ftype, p->code, BUILT_IN_MD,
6640 TREE_READONLY (decl) = 1;
6641 TREE_NOTHROW (decl) = 1;
6647 alpha_init_builtins (void)
6649 tree dimode_integer_type_node;
6652 dimode_integer_type_node = lang_hooks.types.type_for_mode (DImode, 0);
6654 /* Fwrite on VMS is non-standard. */
6655 #if TARGET_ABI_OPEN_VMS
6656 implicit_built_in_decls[(int) BUILT_IN_FWRITE] = NULL_TREE;
6657 implicit_built_in_decls[(int) BUILT_IN_FWRITE_UNLOCKED] = NULL_TREE;
6660 ftype = build_function_type (dimode_integer_type_node, void_list_node);
6661 alpha_add_builtins (zero_arg_builtins, ARRAY_SIZE (zero_arg_builtins),
6664 ftype = build_function_type_list (dimode_integer_type_node,
6665 dimode_integer_type_node, NULL_TREE);
6666 alpha_add_builtins (one_arg_builtins, ARRAY_SIZE (one_arg_builtins),
6669 ftype = build_function_type_list (dimode_integer_type_node,
6670 dimode_integer_type_node,
6671 dimode_integer_type_node, NULL_TREE);
6672 alpha_add_builtins (two_arg_builtins, ARRAY_SIZE (two_arg_builtins),
6675 ftype = build_function_type (ptr_type_node, void_list_node);
6676 decl = add_builtin_function ("__builtin_thread_pointer", ftype,
6677 ALPHA_BUILTIN_THREAD_POINTER, BUILT_IN_MD,
6679 TREE_NOTHROW (decl) = 1;
6681 ftype = build_function_type_list (void_type_node, ptr_type_node, NULL_TREE);
6682 decl = add_builtin_function ("__builtin_set_thread_pointer", ftype,
6683 ALPHA_BUILTIN_SET_THREAD_POINTER, BUILT_IN_MD,
6685 TREE_NOTHROW (decl) = 1;
6687 if (TARGET_ABI_OPEN_VMS)
6689 ftype = build_function_type_list (ptr_type_node, ptr_type_node,
6691 add_builtin_function ("__builtin_establish_vms_condition_handler", ftype,
6692 ALPHA_BUILTIN_ESTABLISH_VMS_CONDITION_HANDLER,
6693 BUILT_IN_MD, NULL, NULL_TREE);
6695 ftype = build_function_type_list (ptr_type_node, void_type_node,
6697 add_builtin_function ("__builtin_revert_vms_condition_handler", ftype,
6698 ALPHA_BUILTIN_REVERT_VMS_CONDITION_HANDLER,
6699 BUILT_IN_MD, NULL, NULL_TREE);
6702 alpha_v8qi_u = build_vector_type (unsigned_intQI_type_node, 8);
6703 alpha_v8qi_s = build_vector_type (intQI_type_node, 8);
6704 alpha_v4hi_u = build_vector_type (unsigned_intHI_type_node, 4);
6705 alpha_v4hi_s = build_vector_type (intHI_type_node, 4);
6708 /* Expand an expression EXP that calls a built-in function,
6709 with result going to TARGET if that's convenient
6710 (and in mode MODE if that's convenient).
6711 SUBTARGET may be used as the target for computing one of EXP's operands.
6712 IGNORE is nonzero if the value is to be ignored. */
6715 alpha_expand_builtin (tree exp, rtx target,
6716 rtx subtarget ATTRIBUTE_UNUSED,
6717 enum machine_mode mode ATTRIBUTE_UNUSED,
6718 int ignore ATTRIBUTE_UNUSED)
6722 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
6723 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6725 call_expr_arg_iterator iter;
6726 enum insn_code icode;
6727 rtx op[MAX_ARGS], pat;
6731 if (fcode >= ALPHA_BUILTIN_max)
6732 internal_error ("bad builtin fcode");
6733 icode = code_for_builtin[fcode];
6735 internal_error ("bad builtin fcode");
6737 nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
6740 FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
6742 const struct insn_operand_data *insn_op;
6744 if (arg == error_mark_node)
6746 if (arity > MAX_ARGS)
6749 insn_op = &insn_data[icode].operand[arity + nonvoid];
6751 op[arity] = expand_expr (arg, NULL_RTX, insn_op->mode, EXPAND_NORMAL);
6753 if (!(*insn_op->predicate) (op[arity], insn_op->mode))
6754 op[arity] = copy_to_mode_reg (insn_op->mode, op[arity]);
6760 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6762 || GET_MODE (target) != tmode
6763 || !(*insn_data[icode].operand[0].predicate) (target, tmode))
6764 target = gen_reg_rtx (tmode);
6770 pat = GEN_FCN (icode) (target);
6774 pat = GEN_FCN (icode) (target, op[0]);
6776 pat = GEN_FCN (icode) (op[0]);
6779 pat = GEN_FCN (icode) (target, op[0], op[1]);
6795 /* Several bits below assume HWI >= 64 bits. This should be enforced
6797 #if HOST_BITS_PER_WIDE_INT < 64
6798 # error "HOST_WIDE_INT too small"
6801 /* Fold the builtin for the CMPBGE instruction. This is a vector comparison
6802 with an 8-bit output vector. OPINT contains the integer operands; bit N
6803 of OP_CONST is set if OPINT[N] is valid. */
6806 alpha_fold_builtin_cmpbge (unsigned HOST_WIDE_INT opint[], long op_const)
6811 for (i = 0, val = 0; i < 8; ++i)
6813 unsigned HOST_WIDE_INT c0 = (opint[0] >> (i * 8)) & 0xff;
6814 unsigned HOST_WIDE_INT c1 = (opint[1] >> (i * 8)) & 0xff;
6818 return build_int_cst (long_integer_type_node, val);
6820 else if (op_const == 2 && opint[1] == 0)
6821 return build_int_cst (long_integer_type_node, 0xff);
6825 /* Fold the builtin for the ZAPNOT instruction. This is essentially a
6826 specialized form of an AND operation. Other byte manipulation instructions
6827 are defined in terms of this instruction, so this is also used as a
6828 subroutine for other builtins.
6830 OP contains the tree operands; OPINT contains the extracted integer values.
6831 Bit N of OP_CONST it set if OPINT[N] is valid. OP may be null if only
6832 OPINT may be considered. */
6835 alpha_fold_builtin_zapnot (tree *op, unsigned HOST_WIDE_INT opint[],
6840 unsigned HOST_WIDE_INT mask = 0;
6843 for (i = 0; i < 8; ++i)
6844 if ((opint[1] >> i) & 1)
6845 mask |= (unsigned HOST_WIDE_INT)0xff << (i * 8);
6848 return build_int_cst (long_integer_type_node, opint[0] & mask);
6851 return fold_build2 (BIT_AND_EXPR, long_integer_type_node, op[0],
6852 build_int_cst (long_integer_type_node, mask));
6854 else if ((op_const & 1) && opint[0] == 0)
6855 return build_int_cst (long_integer_type_node, 0);
6859 /* Fold the builtins for the EXT family of instructions. */
6862 alpha_fold_builtin_extxx (tree op[], unsigned HOST_WIDE_INT opint[],
6863 long op_const, unsigned HOST_WIDE_INT bytemask,
6867 tree *zap_op = NULL;
6871 unsigned HOST_WIDE_INT loc;
6874 if (BYTES_BIG_ENDIAN)
6882 unsigned HOST_WIDE_INT temp = opint[0];
6895 opint[1] = bytemask;
6896 return alpha_fold_builtin_zapnot (zap_op, opint, zap_const);
6899 /* Fold the builtins for the INS family of instructions. */
6902 alpha_fold_builtin_insxx (tree op[], unsigned HOST_WIDE_INT opint[],
6903 long op_const, unsigned HOST_WIDE_INT bytemask,
6906 if ((op_const & 1) && opint[0] == 0)
6907 return build_int_cst (long_integer_type_node, 0);
6911 unsigned HOST_WIDE_INT temp, loc, byteloc;
6912 tree *zap_op = NULL;
6915 if (BYTES_BIG_ENDIAN)
6922 byteloc = (64 - (loc * 8)) & 0x3f;
6939 opint[1] = bytemask;
6940 return alpha_fold_builtin_zapnot (zap_op, opint, op_const);
6947 alpha_fold_builtin_mskxx (tree op[], unsigned HOST_WIDE_INT opint[],
6948 long op_const, unsigned HOST_WIDE_INT bytemask,
6953 unsigned HOST_WIDE_INT loc;
6956 if (BYTES_BIG_ENDIAN)
6963 opint[1] = bytemask ^ 0xff;
6966 return alpha_fold_builtin_zapnot (op, opint, op_const);
6970 alpha_fold_builtin_umulh (unsigned HOST_WIDE_INT opint[], long op_const)
6976 unsigned HOST_WIDE_INT l;
6979 mul_double (opint[0], 0, opint[1], 0, &l, &h);
6981 #if HOST_BITS_PER_WIDE_INT > 64
6985 return build_int_cst (long_integer_type_node, h);
6989 opint[1] = opint[0];
6992 /* Note that (X*1) >> 64 == 0. */
6993 if (opint[1] == 0 || opint[1] == 1)
6994 return build_int_cst (long_integer_type_node, 0);
7001 alpha_fold_vector_minmax (enum tree_code code, tree op[], tree vtype)
7003 tree op0 = fold_convert (vtype, op[0]);
7004 tree op1 = fold_convert (vtype, op[1]);
7005 tree val = fold_build2 (code, vtype, op0, op1);
7006 return fold_build1 (VIEW_CONVERT_EXPR, long_integer_type_node, val);
7010 alpha_fold_builtin_perr (unsigned HOST_WIDE_INT opint[], long op_const)
7012 unsigned HOST_WIDE_INT temp = 0;
7018 for (i = 0; i < 8; ++i)
7020 unsigned HOST_WIDE_INT a = (opint[0] >> (i * 8)) & 0xff;
7021 unsigned HOST_WIDE_INT b = (opint[1] >> (i * 8)) & 0xff;
7028 return build_int_cst (long_integer_type_node, temp);
7032 alpha_fold_builtin_pklb (unsigned HOST_WIDE_INT opint[], long op_const)
7034 unsigned HOST_WIDE_INT temp;
7039 temp = opint[0] & 0xff;
7040 temp |= (opint[0] >> 24) & 0xff00;
7042 return build_int_cst (long_integer_type_node, temp);
7046 alpha_fold_builtin_pkwb (unsigned HOST_WIDE_INT opint[], long op_const)
7048 unsigned HOST_WIDE_INT temp;
7053 temp = opint[0] & 0xff;
7054 temp |= (opint[0] >> 8) & 0xff00;
7055 temp |= (opint[0] >> 16) & 0xff0000;
7056 temp |= (opint[0] >> 24) & 0xff000000;
7058 return build_int_cst (long_integer_type_node, temp);
7062 alpha_fold_builtin_unpkbl (unsigned HOST_WIDE_INT opint[], long op_const)
7064 unsigned HOST_WIDE_INT temp;
7069 temp = opint[0] & 0xff;
7070 temp |= (opint[0] & 0xff00) << 24;
7072 return build_int_cst (long_integer_type_node, temp);
7076 alpha_fold_builtin_unpkbw (unsigned HOST_WIDE_INT opint[], long op_const)
7078 unsigned HOST_WIDE_INT temp;
7083 temp = opint[0] & 0xff;
7084 temp |= (opint[0] & 0x0000ff00) << 8;
7085 temp |= (opint[0] & 0x00ff0000) << 16;
7086 temp |= (opint[0] & 0xff000000) << 24;
7088 return build_int_cst (long_integer_type_node, temp);
7092 alpha_fold_builtin_cttz (unsigned HOST_WIDE_INT opint[], long op_const)
7094 unsigned HOST_WIDE_INT temp;
7102 temp = exact_log2 (opint[0] & -opint[0]);
7104 return build_int_cst (long_integer_type_node, temp);
7108 alpha_fold_builtin_ctlz (unsigned HOST_WIDE_INT opint[], long op_const)
7110 unsigned HOST_WIDE_INT temp;
7118 temp = 64 - floor_log2 (opint[0]) - 1;
7120 return build_int_cst (long_integer_type_node, temp);
7124 alpha_fold_builtin_ctpop (unsigned HOST_WIDE_INT opint[], long op_const)
7126 unsigned HOST_WIDE_INT temp, op;
7134 temp++, op &= op - 1;
7136 return build_int_cst (long_integer_type_node, temp);
7139 /* Fold one of our builtin functions. */
7142 alpha_fold_builtin (tree fndecl, int n_args, tree *op,
7143 bool ignore ATTRIBUTE_UNUSED)
7145 unsigned HOST_WIDE_INT opint[MAX_ARGS];
7149 if (n_args >= MAX_ARGS)
7152 for (i = 0; i < n_args; i++)
7155 if (arg == error_mark_node)
7159 if (TREE_CODE (arg) == INTEGER_CST)
7161 op_const |= 1L << i;
7162 opint[i] = int_cst_value (arg);
7166 switch (DECL_FUNCTION_CODE (fndecl))
7168 case ALPHA_BUILTIN_CMPBGE:
7169 return alpha_fold_builtin_cmpbge (opint, op_const);
7171 case ALPHA_BUILTIN_EXTBL:
7172 return alpha_fold_builtin_extxx (op, opint, op_const, 0x01, false);
7173 case ALPHA_BUILTIN_EXTWL:
7174 return alpha_fold_builtin_extxx (op, opint, op_const, 0x03, false);
7175 case ALPHA_BUILTIN_EXTLL:
7176 return alpha_fold_builtin_extxx (op, opint, op_const, 0x0f, false);
7177 case ALPHA_BUILTIN_EXTQL:
7178 return alpha_fold_builtin_extxx (op, opint, op_const, 0xff, false);
7179 case ALPHA_BUILTIN_EXTWH:
7180 return alpha_fold_builtin_extxx (op, opint, op_const, 0x03, true);
7181 case ALPHA_BUILTIN_EXTLH:
7182 return alpha_fold_builtin_extxx (op, opint, op_const, 0x0f, true);
7183 case ALPHA_BUILTIN_EXTQH:
7184 return alpha_fold_builtin_extxx (op, opint, op_const, 0xff, true);
7186 case ALPHA_BUILTIN_INSBL:
7187 return alpha_fold_builtin_insxx (op, opint, op_const, 0x01, false);
7188 case ALPHA_BUILTIN_INSWL:
7189 return alpha_fold_builtin_insxx (op, opint, op_const, 0x03, false);
7190 case ALPHA_BUILTIN_INSLL:
7191 return alpha_fold_builtin_insxx (op, opint, op_const, 0x0f, false);
7192 case ALPHA_BUILTIN_INSQL:
7193 return alpha_fold_builtin_insxx (op, opint, op_const, 0xff, false);
7194 case ALPHA_BUILTIN_INSWH:
7195 return alpha_fold_builtin_insxx (op, opint, op_const, 0x03, true);
7196 case ALPHA_BUILTIN_INSLH:
7197 return alpha_fold_builtin_insxx (op, opint, op_const, 0x0f, true);
7198 case ALPHA_BUILTIN_INSQH:
7199 return alpha_fold_builtin_insxx (op, opint, op_const, 0xff, true);
7201 case ALPHA_BUILTIN_MSKBL:
7202 return alpha_fold_builtin_mskxx (op, opint, op_const, 0x01, false);
7203 case ALPHA_BUILTIN_MSKWL:
7204 return alpha_fold_builtin_mskxx (op, opint, op_const, 0x03, false);
7205 case ALPHA_BUILTIN_MSKLL:
7206 return alpha_fold_builtin_mskxx (op, opint, op_const, 0x0f, false);
7207 case ALPHA_BUILTIN_MSKQL:
7208 return alpha_fold_builtin_mskxx (op, opint, op_const, 0xff, false);
7209 case ALPHA_BUILTIN_MSKWH:
7210 return alpha_fold_builtin_mskxx (op, opint, op_const, 0x03, true);
7211 case ALPHA_BUILTIN_MSKLH:
7212 return alpha_fold_builtin_mskxx (op, opint, op_const, 0x0f, true);
7213 case ALPHA_BUILTIN_MSKQH:
7214 return alpha_fold_builtin_mskxx (op, opint, op_const, 0xff, true);
7216 case ALPHA_BUILTIN_UMULH:
7217 return alpha_fold_builtin_umulh (opint, op_const);
7219 case ALPHA_BUILTIN_ZAP:
7222 case ALPHA_BUILTIN_ZAPNOT:
7223 return alpha_fold_builtin_zapnot (op, opint, op_const);
7225 case ALPHA_BUILTIN_MINUB8:
7226 return alpha_fold_vector_minmax (MIN_EXPR, op, alpha_v8qi_u);
7227 case ALPHA_BUILTIN_MINSB8:
7228 return alpha_fold_vector_minmax (MIN_EXPR, op, alpha_v8qi_s);
7229 case ALPHA_BUILTIN_MINUW4:
7230 return alpha_fold_vector_minmax (MIN_EXPR, op, alpha_v4hi_u);
7231 case ALPHA_BUILTIN_MINSW4:
7232 return alpha_fold_vector_minmax (MIN_EXPR, op, alpha_v4hi_s);
7233 case ALPHA_BUILTIN_MAXUB8:
7234 return alpha_fold_vector_minmax (MAX_EXPR, op, alpha_v8qi_u);
7235 case ALPHA_BUILTIN_MAXSB8:
7236 return alpha_fold_vector_minmax (MAX_EXPR, op, alpha_v8qi_s);
7237 case ALPHA_BUILTIN_MAXUW4:
7238 return alpha_fold_vector_minmax (MAX_EXPR, op, alpha_v4hi_u);
7239 case ALPHA_BUILTIN_MAXSW4:
7240 return alpha_fold_vector_minmax (MAX_EXPR, op, alpha_v4hi_s);
7242 case ALPHA_BUILTIN_PERR:
7243 return alpha_fold_builtin_perr (opint, op_const);
7244 case ALPHA_BUILTIN_PKLB:
7245 return alpha_fold_builtin_pklb (opint, op_const);
7246 case ALPHA_BUILTIN_PKWB:
7247 return alpha_fold_builtin_pkwb (opint, op_const);
7248 case ALPHA_BUILTIN_UNPKBL:
7249 return alpha_fold_builtin_unpkbl (opint, op_const);
7250 case ALPHA_BUILTIN_UNPKBW:
7251 return alpha_fold_builtin_unpkbw (opint, op_const);
7253 case ALPHA_BUILTIN_CTTZ:
7254 return alpha_fold_builtin_cttz (opint, op_const);
7255 case ALPHA_BUILTIN_CTLZ:
7256 return alpha_fold_builtin_ctlz (opint, op_const);
7257 case ALPHA_BUILTIN_CTPOP:
7258 return alpha_fold_builtin_ctpop (opint, op_const);
7260 case ALPHA_BUILTIN_AMASK:
7261 case ALPHA_BUILTIN_IMPLVER:
7262 case ALPHA_BUILTIN_RPCC:
7263 case ALPHA_BUILTIN_THREAD_POINTER:
7264 case ALPHA_BUILTIN_SET_THREAD_POINTER:
7265 /* None of these are foldable at compile-time. */
7271 /* This page contains routines that are used to determine what the function
7272 prologue and epilogue code will do and write them out. */
7274 /* Compute the size of the save area in the stack. */
7276 /* These variables are used for communication between the following functions.
7277 They indicate various things about the current function being compiled
7278 that are used to tell what kind of prologue, epilogue and procedure
7279 descriptor to generate. */
7281 /* Nonzero if we need a stack procedure. */
7282 enum alpha_procedure_types {PT_NULL = 0, PT_REGISTER = 1, PT_STACK = 2};
7283 static enum alpha_procedure_types alpha_procedure_type;
7285 /* Register number (either FP or SP) that is used to unwind the frame. */
7286 static int vms_unwind_regno;
7288 /* Register number used to save FP. We need not have one for RA since
7289 we don't modify it for register procedures. This is only defined
7290 for register frame procedures. */
7291 static int vms_save_fp_regno;
7293 /* Register number used to reference objects off our PV. */
7294 static int vms_base_regno;
7296 /* Compute register masks for saved registers. */
7299 alpha_sa_mask (unsigned long *imaskP, unsigned long *fmaskP)
7301 unsigned long imask = 0;
7302 unsigned long fmask = 0;
7305 /* When outputting a thunk, we don't have valid register life info,
7306 but assemble_start_function wants to output .frame and .mask
7315 if (TARGET_ABI_OPEN_VMS && alpha_procedure_type == PT_STACK)
7316 imask |= (1UL << HARD_FRAME_POINTER_REGNUM);
7318 /* One for every register we have to save. */
7319 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
7320 if (! fixed_regs[i] && ! call_used_regs[i]
7321 && df_regs_ever_live_p (i) && i != REG_RA
7322 && (!TARGET_ABI_UNICOSMK || i != HARD_FRAME_POINTER_REGNUM))
7325 imask |= (1UL << i);
7327 fmask |= (1UL << (i - 32));
7330 /* We need to restore these for the handler. */
7331 if (crtl->calls_eh_return)
7335 unsigned regno = EH_RETURN_DATA_REGNO (i);
7336 if (regno == INVALID_REGNUM)
7338 imask |= 1UL << regno;
7342 /* If any register spilled, then spill the return address also. */
7343 /* ??? This is required by the Digital stack unwind specification
7344 and isn't needed if we're doing Dwarf2 unwinding. */
7345 if (imask || fmask || alpha_ra_ever_killed ())
7346 imask |= (1UL << REG_RA);
7353 alpha_sa_size (void)
7355 unsigned long mask[2];
7359 alpha_sa_mask (&mask[0], &mask[1]);
7361 if (TARGET_ABI_UNICOSMK)
7363 if (mask[0] || mask[1])
7368 for (j = 0; j < 2; ++j)
7369 for (i = 0; i < 32; ++i)
7370 if ((mask[j] >> i) & 1)
7374 if (TARGET_ABI_UNICOSMK)
7376 /* We might not need to generate a frame if we don't make any calls
7377 (including calls to __T3E_MISMATCH if this is a vararg function),
7378 don't have any local variables which require stack slots, don't
7379 use alloca and have not determined that we need a frame for other
7382 alpha_procedure_type
7383 = (sa_size || get_frame_size() != 0
7384 || crtl->outgoing_args_size
7385 || cfun->stdarg || cfun->calls_alloca
7386 || frame_pointer_needed)
7387 ? PT_STACK : PT_REGISTER;
7389 /* Always reserve space for saving callee-saved registers if we
7390 need a frame as required by the calling convention. */
7391 if (alpha_procedure_type == PT_STACK)
7394 else if (TARGET_ABI_OPEN_VMS)
7396 /* Start with a stack procedure if we make any calls (REG_RA used), or
7397 need a frame pointer, with a register procedure if we otherwise need
7398 at least a slot, and with a null procedure in other cases. */
7399 if ((mask[0] >> REG_RA) & 1 || frame_pointer_needed)
7400 alpha_procedure_type = PT_STACK;
7401 else if (get_frame_size() != 0)
7402 alpha_procedure_type = PT_REGISTER;
7404 alpha_procedure_type = PT_NULL;
7406 /* Don't reserve space for saving FP & RA yet. Do that later after we've
7407 made the final decision on stack procedure vs register procedure. */
7408 if (alpha_procedure_type == PT_STACK)
7411 /* Decide whether to refer to objects off our PV via FP or PV.
7412 If we need FP for something else or if we receive a nonlocal
7413 goto (which expects PV to contain the value), we must use PV.
7414 Otherwise, start by assuming we can use FP. */
7417 = (frame_pointer_needed
7418 || cfun->has_nonlocal_label
7419 || alpha_procedure_type == PT_STACK
7420 || crtl->outgoing_args_size)
7421 ? REG_PV : HARD_FRAME_POINTER_REGNUM;
7423 /* If we want to copy PV into FP, we need to find some register
7424 in which to save FP. */
7426 vms_save_fp_regno = -1;
7427 if (vms_base_regno == HARD_FRAME_POINTER_REGNUM)
7428 for (i = 0; i < 32; i++)
7429 if (! fixed_regs[i] && call_used_regs[i] && ! df_regs_ever_live_p (i))
7430 vms_save_fp_regno = i;
7432 /* A VMS condition handler requires a stack procedure in our
7433 implementation. (not required by the calling standard). */
7434 if ((vms_save_fp_regno == -1 && alpha_procedure_type == PT_REGISTER)
7435 || cfun->machine->uses_condition_handler)
7436 vms_base_regno = REG_PV, alpha_procedure_type = PT_STACK;
7437 else if (alpha_procedure_type == PT_NULL)
7438 vms_base_regno = REG_PV;
7440 /* Stack unwinding should be done via FP unless we use it for PV. */
7441 vms_unwind_regno = (vms_base_regno == REG_PV
7442 ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM);
7444 /* If this is a stack procedure, allow space for saving FP, RA and
7445 a condition handler slot if needed. */
7446 if (alpha_procedure_type == PT_STACK)
7447 sa_size += 2 + cfun->machine->uses_condition_handler;
7451 /* Our size must be even (multiple of 16 bytes). */
7459 /* Define the offset between two registers, one to be eliminated,
7460 and the other its replacement, at the start of a routine. */
7463 alpha_initial_elimination_offset (unsigned int from,
7464 unsigned int to ATTRIBUTE_UNUSED)
7468 ret = alpha_sa_size ();
7469 ret += ALPHA_ROUND (crtl->outgoing_args_size);
7473 case FRAME_POINTER_REGNUM:
7476 case ARG_POINTER_REGNUM:
7477 ret += (ALPHA_ROUND (get_frame_size ()
7478 + crtl->args.pretend_args_size)
7479 - crtl->args.pretend_args_size);
7489 #if TARGET_ABI_OPEN_VMS
7491 /* Worker function for TARGET_CAN_ELIMINATE. */
7494 alpha_vms_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
7496 /* We need the alpha_procedure_type to decide. Evaluate it now. */
7499 switch (alpha_procedure_type)
7502 /* NULL procedures have no frame of their own and we only
7503 know how to resolve from the current stack pointer. */
7504 return to == STACK_POINTER_REGNUM;
7508 /* We always eliminate except to the stack pointer if there is no
7509 usable frame pointer at hand. */
7510 return (to != STACK_POINTER_REGNUM
7511 || vms_unwind_regno != HARD_FRAME_POINTER_REGNUM);
7517 /* FROM is to be eliminated for TO. Return the offset so that TO+offset
7518 designates the same location as FROM. */
7521 alpha_vms_initial_elimination_offset (unsigned int from, unsigned int to)
7523 /* The only possible attempts we ever expect are ARG or FRAME_PTR to
7524 HARD_FRAME or STACK_PTR. We need the alpha_procedure_type to decide
7525 on the proper computations and will need the register save area size
7528 HOST_WIDE_INT sa_size = alpha_sa_size ();
7530 /* PT_NULL procedures have no frame of their own and we only allow
7531 elimination to the stack pointer. This is the argument pointer and we
7532 resolve the soft frame pointer to that as well. */
7534 if (alpha_procedure_type == PT_NULL)
7537 /* For a PT_STACK procedure the frame layout looks as follows
7539 -----> decreasing addresses
7541 < size rounded up to 16 | likewise >
7542 --------------#------------------------------+++--------------+++-------#
7543 incoming args # pretended args | "frame" | regs sa | PV | outgoing args #
7544 --------------#---------------------------------------------------------#
7546 ARG_PTR FRAME_PTR HARD_FRAME_PTR STACK_PTR
7549 PT_REGISTER procedures are similar in that they may have a frame of their
7550 own. They have no regs-sa/pv/outgoing-args area.
7552 We first compute offset to HARD_FRAME_PTR, then add what we need to get
7553 to STACK_PTR if need be. */
7556 HOST_WIDE_INT offset;
7557 HOST_WIDE_INT pv_save_size = alpha_procedure_type == PT_STACK ? 8 : 0;
7561 case FRAME_POINTER_REGNUM:
7562 offset = ALPHA_ROUND (sa_size + pv_save_size);
7564 case ARG_POINTER_REGNUM:
7565 offset = (ALPHA_ROUND (sa_size + pv_save_size
7567 + crtl->args.pretend_args_size)
7568 - crtl->args.pretend_args_size);
7574 if (to == STACK_POINTER_REGNUM)
7575 offset += ALPHA_ROUND (crtl->outgoing_args_size);
7581 #define COMMON_OBJECT "common_object"
7584 common_object_handler (tree *node, tree name ATTRIBUTE_UNUSED,
7585 tree args ATTRIBUTE_UNUSED, int flags ATTRIBUTE_UNUSED,
7586 bool *no_add_attrs ATTRIBUTE_UNUSED)
7589 gcc_assert (DECL_P (decl));
7591 DECL_COMMON (decl) = 1;
7595 static const struct attribute_spec vms_attribute_table[] =
7597 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
7598 { COMMON_OBJECT, 0, 1, true, false, false, common_object_handler },
7599 { NULL, 0, 0, false, false, false, NULL }
7603 vms_output_aligned_decl_common(FILE *file, tree decl, const char *name,
7604 unsigned HOST_WIDE_INT size,
7607 tree attr = DECL_ATTRIBUTES (decl);
7608 fprintf (file, "%s", COMMON_ASM_OP);
7609 assemble_name (file, name);
7610 fprintf (file, "," HOST_WIDE_INT_PRINT_UNSIGNED, size);
7611 /* ??? Unlike on OSF/1, the alignment factor is not in log units. */
7612 fprintf (file, ",%u", align / BITS_PER_UNIT);
7615 attr = lookup_attribute (COMMON_OBJECT, attr);
7617 fprintf (file, ",%s",
7618 IDENTIFIER_POINTER (TREE_VALUE (TREE_VALUE (attr))));
7623 #undef COMMON_OBJECT
7628 find_lo_sum_using_gp (rtx *px, void *data ATTRIBUTE_UNUSED)
7630 return GET_CODE (*px) == LO_SUM && XEXP (*px, 0) == pic_offset_table_rtx;
7634 alpha_find_lo_sum_using_gp (rtx insn)
7636 return for_each_rtx (&PATTERN (insn), find_lo_sum_using_gp, NULL) > 0;
7640 alpha_does_function_need_gp (void)
7644 /* The GP being variable is an OSF abi thing. */
7645 if (! TARGET_ABI_OSF)
7648 /* We need the gp to load the address of __mcount. */
7649 if (TARGET_PROFILING_NEEDS_GP && crtl->profile)
7652 /* The code emitted by alpha_output_mi_thunk_osf uses the gp. */
7656 /* The nonlocal receiver pattern assumes that the gp is valid for
7657 the nested function. Reasonable because it's almost always set
7658 correctly already. For the cases where that's wrong, make sure
7659 the nested function loads its gp on entry. */
7660 if (crtl->has_nonlocal_goto)
7663 /* If we need a GP (we have a LDSYM insn or a CALL_INSN), load it first.
7664 Even if we are a static function, we still need to do this in case
7665 our address is taken and passed to something like qsort. */
7667 push_topmost_sequence ();
7668 insn = get_insns ();
7669 pop_topmost_sequence ();
7671 for (; insn; insn = NEXT_INSN (insn))
7672 if (NONDEBUG_INSN_P (insn)
7673 && ! JUMP_TABLE_DATA_P (insn)
7674 && GET_CODE (PATTERN (insn)) != USE
7675 && GET_CODE (PATTERN (insn)) != CLOBBER
7676 && get_attr_usegp (insn))
7683 /* Helper function to set RTX_FRAME_RELATED_P on instructions, including
7687 set_frame_related_p (void)
7689 rtx seq = get_insns ();
7700 while (insn != NULL_RTX)
7702 RTX_FRAME_RELATED_P (insn) = 1;
7703 insn = NEXT_INSN (insn);
7705 seq = emit_insn (seq);
7709 seq = emit_insn (seq);
7710 RTX_FRAME_RELATED_P (seq) = 1;
7715 #define FRP(exp) (start_sequence (), exp, set_frame_related_p ())
7717 /* Generates a store with the proper unwind info attached. VALUE is
7718 stored at BASE_REG+BASE_OFS. If FRAME_BIAS is nonzero, then BASE_REG
7719 contains SP+FRAME_BIAS, and that is the unwind info that should be
7720 generated. If FRAME_REG != VALUE, then VALUE is being stored on
7721 behalf of FRAME_REG, and FRAME_REG should be present in the unwind. */
7724 emit_frame_store_1 (rtx value, rtx base_reg, HOST_WIDE_INT frame_bias,
7725 HOST_WIDE_INT base_ofs, rtx frame_reg)
7727 rtx addr, mem, insn;
7729 addr = plus_constant (base_reg, base_ofs);
7730 mem = gen_rtx_MEM (DImode, addr);
7731 set_mem_alias_set (mem, alpha_sr_alias_set);
7733 insn = emit_move_insn (mem, value);
7734 RTX_FRAME_RELATED_P (insn) = 1;
7736 if (frame_bias || value != frame_reg)
7740 addr = plus_constant (stack_pointer_rtx, frame_bias + base_ofs);
7741 mem = gen_rtx_MEM (DImode, addr);
7744 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
7745 gen_rtx_SET (VOIDmode, mem, frame_reg));
7750 emit_frame_store (unsigned int regno, rtx base_reg,
7751 HOST_WIDE_INT frame_bias, HOST_WIDE_INT base_ofs)
7753 rtx reg = gen_rtx_REG (DImode, regno);
7754 emit_frame_store_1 (reg, base_reg, frame_bias, base_ofs, reg);
7757 /* Write function prologue. */
7759 /* On vms we have two kinds of functions:
7761 - stack frame (PROC_STACK)
7762 these are 'normal' functions with local vars and which are
7763 calling other functions
7764 - register frame (PROC_REGISTER)
7765 keeps all data in registers, needs no stack
7767 We must pass this to the assembler so it can generate the
7768 proper pdsc (procedure descriptor)
7769 This is done with the '.pdesc' command.
7771 On not-vms, we don't really differentiate between the two, as we can
7772 simply allocate stack without saving registers. */
7775 alpha_expand_prologue (void)
7777 /* Registers to save. */
7778 unsigned long imask = 0;
7779 unsigned long fmask = 0;
7780 /* Stack space needed for pushing registers clobbered by us. */
7781 HOST_WIDE_INT sa_size;
7782 /* Complete stack size needed. */
7783 HOST_WIDE_INT frame_size;
7784 /* Offset from base reg to register save area. */
7785 HOST_WIDE_INT reg_offset;
7789 sa_size = alpha_sa_size ();
7791 frame_size = get_frame_size ();
7792 if (TARGET_ABI_OPEN_VMS)
7793 frame_size = ALPHA_ROUND (sa_size
7794 + (alpha_procedure_type == PT_STACK ? 8 : 0)
7796 + crtl->args.pretend_args_size);
7797 else if (TARGET_ABI_UNICOSMK)
7798 /* We have to allocate space for the DSIB if we generate a frame. */
7799 frame_size = ALPHA_ROUND (sa_size
7800 + (alpha_procedure_type == PT_STACK ? 48 : 0))
7801 + ALPHA_ROUND (frame_size
7802 + crtl->outgoing_args_size);
7804 frame_size = (ALPHA_ROUND (crtl->outgoing_args_size)
7806 + ALPHA_ROUND (frame_size
7807 + crtl->args.pretend_args_size));
7809 if (TARGET_ABI_OPEN_VMS)
7810 reg_offset = 8 + 8 * cfun->machine->uses_condition_handler;
7812 reg_offset = ALPHA_ROUND (crtl->outgoing_args_size);
7814 alpha_sa_mask (&imask, &fmask);
7816 /* Emit an insn to reload GP, if needed. */
7819 alpha_function_needs_gp = alpha_does_function_need_gp ();
7820 if (alpha_function_needs_gp)
7821 emit_insn (gen_prologue_ldgp ());
7824 /* TARGET_PROFILING_NEEDS_GP actually implies that we need to insert
7825 the call to mcount ourselves, rather than having the linker do it
7826 magically in response to -pg. Since _mcount has special linkage,
7827 don't represent the call as a call. */
7828 if (TARGET_PROFILING_NEEDS_GP && crtl->profile)
7829 emit_insn (gen_prologue_mcount ());
7831 if (TARGET_ABI_UNICOSMK)
7832 unicosmk_gen_dsib (&imask);
7834 /* Adjust the stack by the frame size. If the frame size is > 4096
7835 bytes, we need to be sure we probe somewhere in the first and last
7836 4096 bytes (we can probably get away without the latter test) and
7837 every 8192 bytes in between. If the frame size is > 32768, we
7838 do this in a loop. Otherwise, we generate the explicit probe
7841 Note that we are only allowed to adjust sp once in the prologue. */
7843 if (frame_size <= 32768)
7845 if (frame_size > 4096)
7849 for (probed = 4096; probed < frame_size; probed += 8192)
7850 emit_insn (gen_probe_stack (GEN_INT (TARGET_ABI_UNICOSMK
7854 /* We only have to do this probe if we aren't saving registers. */
7855 if (sa_size == 0 && frame_size > probed - 4096)
7856 emit_insn (gen_probe_stack (GEN_INT (-frame_size)));
7859 if (frame_size != 0)
7860 FRP (emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx,
7861 GEN_INT (TARGET_ABI_UNICOSMK
7867 /* Here we generate code to set R22 to SP + 4096 and set R23 to the
7868 number of 8192 byte blocks to probe. We then probe each block
7869 in the loop and then set SP to the proper location. If the
7870 amount remaining is > 4096, we have to do one more probe if we
7871 are not saving any registers. */
7873 HOST_WIDE_INT blocks = (frame_size + 4096) / 8192;
7874 HOST_WIDE_INT leftover = frame_size + 4096 - blocks * 8192;
7875 rtx ptr = gen_rtx_REG (DImode, 22);
7876 rtx count = gen_rtx_REG (DImode, 23);
7879 emit_move_insn (count, GEN_INT (blocks));
7880 emit_insn (gen_adddi3 (ptr, stack_pointer_rtx,
7881 GEN_INT (TARGET_ABI_UNICOSMK ? 4096 - 64 : 4096)));
7883 /* Because of the difficulty in emitting a new basic block this
7884 late in the compilation, generate the loop as a single insn. */
7885 emit_insn (gen_prologue_stack_probe_loop (count, ptr));
7887 if (leftover > 4096 && sa_size == 0)
7889 rtx last = gen_rtx_MEM (DImode, plus_constant (ptr, -leftover));
7890 MEM_VOLATILE_P (last) = 1;
7891 emit_move_insn (last, const0_rtx);
7894 if (TARGET_ABI_WINDOWS_NT)
7896 /* For NT stack unwind (done by 'reverse execution'), it's
7897 not OK to take the result of a loop, even though the value
7898 is already in ptr, so we reload it via a single operation
7899 and subtract it to sp.
7901 Yes, that's correct -- we have to reload the whole constant
7902 into a temporary via ldah+lda then subtract from sp. */
7904 HOST_WIDE_INT lo, hi;
7905 lo = ((frame_size & 0xffff) ^ 0x8000) - 0x8000;
7906 hi = frame_size - lo;
7908 emit_move_insn (ptr, GEN_INT (hi));
7909 emit_insn (gen_adddi3 (ptr, ptr, GEN_INT (lo)));
7910 seq = emit_insn (gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx,
7915 seq = emit_insn (gen_adddi3 (stack_pointer_rtx, ptr,
7916 GEN_INT (-leftover)));
7919 /* This alternative is special, because the DWARF code cannot
7920 possibly intuit through the loop above. So we invent this
7921 note it looks at instead. */
7922 RTX_FRAME_RELATED_P (seq) = 1;
7923 add_reg_note (seq, REG_FRAME_RELATED_EXPR,
7924 gen_rtx_SET (VOIDmode, stack_pointer_rtx,
7925 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
7926 GEN_INT (TARGET_ABI_UNICOSMK
7931 if (!TARGET_ABI_UNICOSMK)
7933 HOST_WIDE_INT sa_bias = 0;
7935 /* Cope with very large offsets to the register save area. */
7936 sa_reg = stack_pointer_rtx;
7937 if (reg_offset + sa_size > 0x8000)
7939 int low = ((reg_offset & 0xffff) ^ 0x8000) - 0x8000;
7942 if (low + sa_size <= 0x8000)
7943 sa_bias = reg_offset - low, reg_offset = low;
7945 sa_bias = reg_offset, reg_offset = 0;
7947 sa_reg = gen_rtx_REG (DImode, 24);
7948 sa_bias_rtx = GEN_INT (sa_bias);
7950 if (add_operand (sa_bias_rtx, DImode))
7951 emit_insn (gen_adddi3 (sa_reg, stack_pointer_rtx, sa_bias_rtx));
7954 emit_move_insn (sa_reg, sa_bias_rtx);
7955 emit_insn (gen_adddi3 (sa_reg, stack_pointer_rtx, sa_reg));
7959 /* Save regs in stack order. Beginning with VMS PV. */
7960 if (TARGET_ABI_OPEN_VMS && alpha_procedure_type == PT_STACK)
7961 emit_frame_store (REG_PV, stack_pointer_rtx, 0, 0);
7963 /* Save register RA next. */
7964 if (imask & (1UL << REG_RA))
7966 emit_frame_store (REG_RA, sa_reg, sa_bias, reg_offset);
7967 imask &= ~(1UL << REG_RA);
7971 /* Now save any other registers required to be saved. */
7972 for (i = 0; i < 31; i++)
7973 if (imask & (1UL << i))
7975 emit_frame_store (i, sa_reg, sa_bias, reg_offset);
7979 for (i = 0; i < 31; i++)
7980 if (fmask & (1UL << i))
7982 emit_frame_store (i+32, sa_reg, sa_bias, reg_offset);
7986 else if (TARGET_ABI_UNICOSMK && alpha_procedure_type == PT_STACK)
7988 /* The standard frame on the T3E includes space for saving registers.
7989 We just have to use it. We don't have to save the return address and
7990 the old frame pointer here - they are saved in the DSIB. */
7993 for (i = 9; i < 15; i++)
7994 if (imask & (1UL << i))
7996 emit_frame_store (i, hard_frame_pointer_rtx, 0, reg_offset);
7999 for (i = 2; i < 10; i++)
8000 if (fmask & (1UL << i))
8002 emit_frame_store (i+32, hard_frame_pointer_rtx, 0, reg_offset);
8007 if (TARGET_ABI_OPEN_VMS)
8009 /* Register frame procedures save the fp. */
8010 if (alpha_procedure_type == PT_REGISTER)
8012 rtx insn = emit_move_insn (gen_rtx_REG (DImode, vms_save_fp_regno),
8013 hard_frame_pointer_rtx);
8014 add_reg_note (insn, REG_CFA_REGISTER, NULL);
8015 RTX_FRAME_RELATED_P (insn) = 1;
8018 if (alpha_procedure_type != PT_NULL && vms_base_regno != REG_PV)
8019 emit_insn (gen_force_movdi (gen_rtx_REG (DImode, vms_base_regno),
8020 gen_rtx_REG (DImode, REG_PV)));
8022 if (alpha_procedure_type != PT_NULL
8023 && vms_unwind_regno == HARD_FRAME_POINTER_REGNUM)
8024 FRP (emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx));
8026 /* If we have to allocate space for outgoing args, do it now. */
8027 if (crtl->outgoing_args_size != 0)
8030 = emit_move_insn (stack_pointer_rtx,
8032 (hard_frame_pointer_rtx,
8034 (crtl->outgoing_args_size))));
8036 /* Only set FRAME_RELATED_P on the stack adjustment we just emitted
8037 if ! frame_pointer_needed. Setting the bit will change the CFA
8038 computation rule to use sp again, which would be wrong if we had
8039 frame_pointer_needed, as this means sp might move unpredictably
8043 frame_pointer_needed
8044 => vms_unwind_regno == HARD_FRAME_POINTER_REGNUM
8046 crtl->outgoing_args_size != 0
8047 => alpha_procedure_type != PT_NULL,
8049 so when we are not setting the bit here, we are guaranteed to
8050 have emitted an FRP frame pointer update just before. */
8051 RTX_FRAME_RELATED_P (seq) = ! frame_pointer_needed;
8054 else if (!TARGET_ABI_UNICOSMK)
8056 /* If we need a frame pointer, set it from the stack pointer. */
8057 if (frame_pointer_needed)
8059 if (TARGET_CAN_FAULT_IN_PROLOGUE)
8060 FRP (emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx));
8062 /* This must always be the last instruction in the
8063 prologue, thus we emit a special move + clobber. */
8064 FRP (emit_insn (gen_init_fp (hard_frame_pointer_rtx,
8065 stack_pointer_rtx, sa_reg)));
8069 /* The ABIs for VMS and OSF/1 say that while we can schedule insns into
8070 the prologue, for exception handling reasons, we cannot do this for
8071 any insn that might fault. We could prevent this for mems with a
8072 (clobber:BLK (scratch)), but this doesn't work for fp insns. So we
8073 have to prevent all such scheduling with a blockage.
8075 Linux, on the other hand, never bothered to implement OSF/1's
8076 exception handling, and so doesn't care about such things. Anyone
8077 planning to use dwarf2 frame-unwind info can also omit the blockage. */
8079 if (! TARGET_CAN_FAULT_IN_PROLOGUE)
8080 emit_insn (gen_blockage ());
8083 /* Count the number of .file directives, so that .loc is up to date. */
8084 int num_source_filenames = 0;
8086 /* Output the textual info surrounding the prologue. */
8089 alpha_start_function (FILE *file, const char *fnname,
8090 tree decl ATTRIBUTE_UNUSED)
8092 unsigned long imask = 0;
8093 unsigned long fmask = 0;
8094 /* Stack space needed for pushing registers clobbered by us. */
8095 HOST_WIDE_INT sa_size;
8096 /* Complete stack size needed. */
8097 unsigned HOST_WIDE_INT frame_size;
8098 /* The maximum debuggable frame size (512 Kbytes using Tru64 as). */
8099 unsigned HOST_WIDE_INT max_frame_size = TARGET_ABI_OSF && !TARGET_GAS
8102 /* Offset from base reg to register save area. */
8103 HOST_WIDE_INT reg_offset;
8104 char *entry_label = (char *) alloca (strlen (fnname) + 6);
8105 char *tramp_label = (char *) alloca (strlen (fnname) + 6);
8108 /* Don't emit an extern directive for functions defined in the same file. */
8109 if (TARGET_ABI_UNICOSMK)
8112 name_tree = get_identifier (fnname);
8113 TREE_ASM_WRITTEN (name_tree) = 1;
8116 #if TARGET_ABI_OPEN_VMS
8118 && strncmp (vms_debug_main, fnname, strlen (vms_debug_main)) == 0)
8120 targetm.asm_out.globalize_label (asm_out_file, VMS_DEBUG_MAIN_POINTER);
8121 ASM_OUTPUT_DEF (asm_out_file, VMS_DEBUG_MAIN_POINTER, fnname);
8122 switch_to_section (text_section);
8123 vms_debug_main = NULL;
8127 alpha_fnname = fnname;
8128 sa_size = alpha_sa_size ();
8130 frame_size = get_frame_size ();
8131 if (TARGET_ABI_OPEN_VMS)
8132 frame_size = ALPHA_ROUND (sa_size
8133 + (alpha_procedure_type == PT_STACK ? 8 : 0)
8135 + crtl->args.pretend_args_size);
8136 else if (TARGET_ABI_UNICOSMK)
8137 frame_size = ALPHA_ROUND (sa_size
8138 + (alpha_procedure_type == PT_STACK ? 48 : 0))
8139 + ALPHA_ROUND (frame_size
8140 + crtl->outgoing_args_size);
8142 frame_size = (ALPHA_ROUND (crtl->outgoing_args_size)
8144 + ALPHA_ROUND (frame_size
8145 + crtl->args.pretend_args_size));
8147 if (TARGET_ABI_OPEN_VMS)
8148 reg_offset = 8 + 8 * cfun->machine->uses_condition_handler;
8150 reg_offset = ALPHA_ROUND (crtl->outgoing_args_size);
8152 alpha_sa_mask (&imask, &fmask);
8154 /* Ecoff can handle multiple .file directives, so put out file and lineno.
8155 We have to do that before the .ent directive as we cannot switch
8156 files within procedures with native ecoff because line numbers are
8157 linked to procedure descriptors.
8158 Outputting the lineno helps debugging of one line functions as they
8159 would otherwise get no line number at all. Please note that we would
8160 like to put out last_linenum from final.c, but it is not accessible. */
8162 if (write_symbols == SDB_DEBUG)
8164 #ifdef ASM_OUTPUT_SOURCE_FILENAME
8165 ASM_OUTPUT_SOURCE_FILENAME (file,
8166 DECL_SOURCE_FILE (current_function_decl));
8168 #ifdef SDB_OUTPUT_SOURCE_LINE
8169 if (debug_info_level != DINFO_LEVEL_TERSE)
8170 SDB_OUTPUT_SOURCE_LINE (file,
8171 DECL_SOURCE_LINE (current_function_decl));
8175 /* Issue function start and label. */
8176 if (TARGET_ABI_OPEN_VMS
8177 || (!TARGET_ABI_UNICOSMK && !flag_inhibit_size_directive))
8179 fputs ("\t.ent ", file);
8180 assemble_name (file, fnname);
8183 /* If the function needs GP, we'll write the "..ng" label there.
8184 Otherwise, do it here. */
8186 && ! alpha_function_needs_gp
8187 && ! cfun->is_thunk)
8190 assemble_name (file, fnname);
8191 fputs ("..ng:\n", file);
8194 /* Nested functions on VMS that are potentially called via trampoline
8195 get a special transfer entry point that loads the called functions
8196 procedure descriptor and static chain. */
8197 if (TARGET_ABI_OPEN_VMS
8198 && !TREE_PUBLIC (decl)
8199 && DECL_CONTEXT (decl)
8200 && !TYPE_P (DECL_CONTEXT (decl)))
8202 strcpy (tramp_label, fnname);
8203 strcat (tramp_label, "..tr");
8204 ASM_OUTPUT_LABEL (file, tramp_label);
8205 fprintf (file, "\tldq $1,24($27)\n");
8206 fprintf (file, "\tldq $27,16($27)\n");
8209 strcpy (entry_label, fnname);
8210 if (TARGET_ABI_OPEN_VMS)
8211 strcat (entry_label, "..en");
8213 /* For public functions, the label must be globalized by appending an
8214 additional colon. */
8215 if (TARGET_ABI_UNICOSMK && TREE_PUBLIC (decl))
8216 strcat (entry_label, ":");
8218 ASM_OUTPUT_LABEL (file, entry_label);
8219 inside_function = TRUE;
8221 if (TARGET_ABI_OPEN_VMS)
8222 fprintf (file, "\t.base $%d\n", vms_base_regno);
8224 if (!TARGET_ABI_OPEN_VMS && !TARGET_ABI_UNICOSMK && TARGET_IEEE_CONFORMANT
8225 && !flag_inhibit_size_directive)
8227 /* Set flags in procedure descriptor to request IEEE-conformant
8228 math-library routines. The value we set it to is PDSC_EXC_IEEE
8229 (/usr/include/pdsc.h). */
8230 fputs ("\t.eflag 48\n", file);
8233 /* Set up offsets to alpha virtual arg/local debugging pointer. */
8234 alpha_auto_offset = -frame_size + crtl->args.pretend_args_size;
8235 alpha_arg_offset = -frame_size + 48;
8237 /* Describe our frame. If the frame size is larger than an integer,
8238 print it as zero to avoid an assembler error. We won't be
8239 properly describing such a frame, but that's the best we can do. */
8240 if (TARGET_ABI_UNICOSMK)
8242 else if (TARGET_ABI_OPEN_VMS)
8243 fprintf (file, "\t.frame $%d," HOST_WIDE_INT_PRINT_DEC ",$26,"
8244 HOST_WIDE_INT_PRINT_DEC "\n",
8246 frame_size >= (1UL << 31) ? 0 : frame_size,
8248 else if (!flag_inhibit_size_directive)
8249 fprintf (file, "\t.frame $%d," HOST_WIDE_INT_PRINT_DEC ",$26,%d\n",
8250 (frame_pointer_needed
8251 ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM),
8252 frame_size >= max_frame_size ? 0 : frame_size,
8253 crtl->args.pretend_args_size);
8255 /* Describe which registers were spilled. */
8256 if (TARGET_ABI_UNICOSMK)
8258 else if (TARGET_ABI_OPEN_VMS)
8261 /* ??? Does VMS care if mask contains ra? The old code didn't
8262 set it, so I don't here. */
8263 fprintf (file, "\t.mask 0x%lx,0\n", imask & ~(1UL << REG_RA));
8265 fprintf (file, "\t.fmask 0x%lx,0\n", fmask);
8266 if (alpha_procedure_type == PT_REGISTER)
8267 fprintf (file, "\t.fp_save $%d\n", vms_save_fp_regno);
8269 else if (!flag_inhibit_size_directive)
8273 fprintf (file, "\t.mask 0x%lx," HOST_WIDE_INT_PRINT_DEC "\n", imask,
8274 frame_size >= max_frame_size ? 0 : reg_offset - frame_size);
8276 for (i = 0; i < 32; ++i)
8277 if (imask & (1UL << i))
8282 fprintf (file, "\t.fmask 0x%lx," HOST_WIDE_INT_PRINT_DEC "\n", fmask,
8283 frame_size >= max_frame_size ? 0 : reg_offset - frame_size);
8286 #if TARGET_ABI_OPEN_VMS
8287 /* If a user condition handler has been installed at some point, emit
8288 the procedure descriptor bits to point the Condition Handling Facility
8289 at the indirection wrapper, and state the fp offset at which the user
8290 handler may be found. */
8291 if (cfun->machine->uses_condition_handler)
8293 fprintf (file, "\t.handler __gcc_shell_handler\n");
8294 fprintf (file, "\t.handler_data %d\n", VMS_COND_HANDLER_FP_OFFSET);
8297 /* Ifdef'ed cause link_section are only available then. */
8298 switch_to_section (readonly_data_section);
8299 fprintf (file, "\t.align 3\n");
8300 assemble_name (file, fnname); fputs ("..na:\n", file);
8301 fputs ("\t.ascii \"", file);
8302 assemble_name (file, fnname);
8303 fputs ("\\0\"\n", file);
8304 alpha_need_linkage (fnname, 1);
8305 switch_to_section (text_section);
8309 /* Emit the .prologue note at the scheduled end of the prologue. */
8312 alpha_output_function_end_prologue (FILE *file)
8314 if (TARGET_ABI_UNICOSMK)
8316 else if (TARGET_ABI_OPEN_VMS)
8317 fputs ("\t.prologue\n", file);
8318 else if (TARGET_ABI_WINDOWS_NT)
8319 fputs ("\t.prologue 0\n", file);
8320 else if (!flag_inhibit_size_directive)
8321 fprintf (file, "\t.prologue %d\n",
8322 alpha_function_needs_gp || cfun->is_thunk);
8325 /* Write function epilogue. */
8328 alpha_expand_epilogue (void)
8330 /* Registers to save. */
8331 unsigned long imask = 0;
8332 unsigned long fmask = 0;
8333 /* Stack space needed for pushing registers clobbered by us. */
8334 HOST_WIDE_INT sa_size;
8335 /* Complete stack size needed. */
8336 HOST_WIDE_INT frame_size;
8337 /* Offset from base reg to register save area. */
8338 HOST_WIDE_INT reg_offset;
8339 int fp_is_frame_pointer, fp_offset;
8340 rtx sa_reg, sa_reg_exp = NULL;
8341 rtx sp_adj1, sp_adj2, mem, reg, insn;
8343 rtx cfa_restores = NULL_RTX;
8346 sa_size = alpha_sa_size ();
8348 frame_size = get_frame_size ();
8349 if (TARGET_ABI_OPEN_VMS)
8350 frame_size = ALPHA_ROUND (sa_size
8351 + (alpha_procedure_type == PT_STACK ? 8 : 0)
8353 + crtl->args.pretend_args_size);
8354 else if (TARGET_ABI_UNICOSMK)
8355 frame_size = ALPHA_ROUND (sa_size
8356 + (alpha_procedure_type == PT_STACK ? 48 : 0))
8357 + ALPHA_ROUND (frame_size
8358 + crtl->outgoing_args_size);
8360 frame_size = (ALPHA_ROUND (crtl->outgoing_args_size)
8362 + ALPHA_ROUND (frame_size
8363 + crtl->args.pretend_args_size));
8365 if (TARGET_ABI_OPEN_VMS)
8367 if (alpha_procedure_type == PT_STACK)
8368 reg_offset = 8 + 8 * cfun->machine->uses_condition_handler;
8373 reg_offset = ALPHA_ROUND (crtl->outgoing_args_size);
8375 alpha_sa_mask (&imask, &fmask);
8378 = ((TARGET_ABI_OPEN_VMS && alpha_procedure_type == PT_STACK)
8379 || (!TARGET_ABI_OPEN_VMS && frame_pointer_needed));
8381 sa_reg = stack_pointer_rtx;
8383 if (crtl->calls_eh_return)
8384 eh_ofs = EH_RETURN_STACKADJ_RTX;
8388 if (!TARGET_ABI_UNICOSMK && sa_size)
8390 /* If we have a frame pointer, restore SP from it. */
8391 if ((TARGET_ABI_OPEN_VMS
8392 && vms_unwind_regno == HARD_FRAME_POINTER_REGNUM)
8393 || (!TARGET_ABI_OPEN_VMS && frame_pointer_needed))
8394 emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
8396 /* Cope with very large offsets to the register save area. */
8397 if (reg_offset + sa_size > 0x8000)
8399 int low = ((reg_offset & 0xffff) ^ 0x8000) - 0x8000;
8402 if (low + sa_size <= 0x8000)
8403 bias = reg_offset - low, reg_offset = low;
8405 bias = reg_offset, reg_offset = 0;
8407 sa_reg = gen_rtx_REG (DImode, 22);
8408 sa_reg_exp = plus_constant (stack_pointer_rtx, bias);
8410 emit_move_insn (sa_reg, sa_reg_exp);
8413 /* Restore registers in order, excepting a true frame pointer. */
8415 mem = gen_rtx_MEM (DImode, plus_constant (sa_reg, reg_offset));
8417 set_mem_alias_set (mem, alpha_sr_alias_set);
8418 reg = gen_rtx_REG (DImode, REG_RA);
8419 emit_move_insn (reg, mem);
8420 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
8423 imask &= ~(1UL << REG_RA);
8425 for (i = 0; i < 31; ++i)
8426 if (imask & (1UL << i))
8428 if (i == HARD_FRAME_POINTER_REGNUM && fp_is_frame_pointer)
8429 fp_offset = reg_offset;
8432 mem = gen_rtx_MEM (DImode, plus_constant(sa_reg, reg_offset));
8433 set_mem_alias_set (mem, alpha_sr_alias_set);
8434 reg = gen_rtx_REG (DImode, i);
8435 emit_move_insn (reg, mem);
8436 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg,
8442 for (i = 0; i < 31; ++i)
8443 if (fmask & (1UL << i))
8445 mem = gen_rtx_MEM (DFmode, plus_constant(sa_reg, reg_offset));
8446 set_mem_alias_set (mem, alpha_sr_alias_set);
8447 reg = gen_rtx_REG (DFmode, i+32);
8448 emit_move_insn (reg, mem);
8449 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
8453 else if (TARGET_ABI_UNICOSMK && alpha_procedure_type == PT_STACK)
8455 /* Restore callee-saved general-purpose registers. */
8459 for (i = 9; i < 15; i++)
8460 if (imask & (1UL << i))
8462 mem = gen_rtx_MEM (DImode, plus_constant(hard_frame_pointer_rtx,
8464 set_mem_alias_set (mem, alpha_sr_alias_set);
8465 reg = gen_rtx_REG (DImode, i);
8466 emit_move_insn (reg, mem);
8467 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
8471 for (i = 2; i < 10; i++)
8472 if (fmask & (1UL << i))
8474 mem = gen_rtx_MEM (DFmode, plus_constant(hard_frame_pointer_rtx,
8476 set_mem_alias_set (mem, alpha_sr_alias_set);
8477 reg = gen_rtx_REG (DFmode, i+32);
8478 emit_move_insn (reg, mem);
8479 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
8483 /* Restore the return address from the DSIB. */
8484 mem = gen_rtx_MEM (DImode, plus_constant (hard_frame_pointer_rtx, -8));
8485 set_mem_alias_set (mem, alpha_sr_alias_set);
8486 reg = gen_rtx_REG (DImode, REG_RA);
8487 emit_move_insn (reg, mem);
8488 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
8491 if (frame_size || eh_ofs)
8493 sp_adj1 = stack_pointer_rtx;
8497 sp_adj1 = gen_rtx_REG (DImode, 23);
8498 emit_move_insn (sp_adj1,
8499 gen_rtx_PLUS (Pmode, stack_pointer_rtx, eh_ofs));
8502 /* If the stack size is large, begin computation into a temporary
8503 register so as not to interfere with a potential fp restore,
8504 which must be consecutive with an SP restore. */
8505 if (frame_size < 32768
8506 && ! (TARGET_ABI_UNICOSMK && cfun->calls_alloca))
8507 sp_adj2 = GEN_INT (frame_size);
8508 else if (TARGET_ABI_UNICOSMK)
8510 sp_adj1 = gen_rtx_REG (DImode, 23);
8511 emit_move_insn (sp_adj1, hard_frame_pointer_rtx);
8512 sp_adj2 = const0_rtx;
8514 else if (frame_size < 0x40007fffL)
8516 int low = ((frame_size & 0xffff) ^ 0x8000) - 0x8000;
8518 sp_adj2 = plus_constant (sp_adj1, frame_size - low);
8519 if (sa_reg_exp && rtx_equal_p (sa_reg_exp, sp_adj2))
8523 sp_adj1 = gen_rtx_REG (DImode, 23);
8524 emit_move_insn (sp_adj1, sp_adj2);
8526 sp_adj2 = GEN_INT (low);
8530 rtx tmp = gen_rtx_REG (DImode, 23);
8531 sp_adj2 = alpha_emit_set_const (tmp, DImode, frame_size, 3, false);
8534 /* We can't drop new things to memory this late, afaik,
8535 so build it up by pieces. */
8536 sp_adj2 = alpha_emit_set_long_const (tmp, frame_size,
8538 gcc_assert (sp_adj2);
8542 /* From now on, things must be in order. So emit blockages. */
8544 /* Restore the frame pointer. */
8545 if (TARGET_ABI_UNICOSMK)
8547 emit_insn (gen_blockage ());
8548 mem = gen_rtx_MEM (DImode,
8549 plus_constant (hard_frame_pointer_rtx, -16));
8550 set_mem_alias_set (mem, alpha_sr_alias_set);
8551 emit_move_insn (hard_frame_pointer_rtx, mem);
8552 cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
8553 hard_frame_pointer_rtx, cfa_restores);
8555 else if (fp_is_frame_pointer)
8557 emit_insn (gen_blockage ());
8558 mem = gen_rtx_MEM (DImode, plus_constant (sa_reg, fp_offset));
8559 set_mem_alias_set (mem, alpha_sr_alias_set);
8560 emit_move_insn (hard_frame_pointer_rtx, mem);
8561 cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
8562 hard_frame_pointer_rtx, cfa_restores);
8564 else if (TARGET_ABI_OPEN_VMS)
8566 emit_insn (gen_blockage ());
8567 emit_move_insn (hard_frame_pointer_rtx,
8568 gen_rtx_REG (DImode, vms_save_fp_regno));
8569 cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
8570 hard_frame_pointer_rtx, cfa_restores);
8573 /* Restore the stack pointer. */
8574 emit_insn (gen_blockage ());
8575 if (sp_adj2 == const0_rtx)
8576 insn = emit_move_insn (stack_pointer_rtx, sp_adj1);
8578 insn = emit_move_insn (stack_pointer_rtx,
8579 gen_rtx_PLUS (DImode, sp_adj1, sp_adj2));
8580 REG_NOTES (insn) = cfa_restores;
8581 add_reg_note (insn, REG_CFA_DEF_CFA, stack_pointer_rtx);
8582 RTX_FRAME_RELATED_P (insn) = 1;
8586 gcc_assert (cfa_restores == NULL);
8588 if (TARGET_ABI_OPEN_VMS && alpha_procedure_type == PT_REGISTER)
8590 emit_insn (gen_blockage ());
8591 insn = emit_move_insn (hard_frame_pointer_rtx,
8592 gen_rtx_REG (DImode, vms_save_fp_regno));
8593 add_reg_note (insn, REG_CFA_RESTORE, hard_frame_pointer_rtx);
8594 RTX_FRAME_RELATED_P (insn) = 1;
8596 else if (TARGET_ABI_UNICOSMK && alpha_procedure_type != PT_STACK)
8598 /* Decrement the frame pointer if the function does not have a
8600 emit_insn (gen_blockage ());
8601 emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
8602 hard_frame_pointer_rtx, constm1_rtx));
8607 /* Output the rest of the textual info surrounding the epilogue. */
8610 alpha_end_function (FILE *file, const char *fnname, tree decl ATTRIBUTE_UNUSED)
8614 /* We output a nop after noreturn calls at the very end of the function to
8615 ensure that the return address always remains in the caller's code range,
8616 as not doing so might confuse unwinding engines. */
8617 insn = get_last_insn ();
8619 insn = prev_active_insn (insn);
8620 if (insn && CALL_P (insn))
8621 output_asm_insn (get_insn_template (CODE_FOR_nop, NULL), NULL);
8623 #if TARGET_ABI_OPEN_VMS
8624 alpha_write_linkage (file, fnname, decl);
8627 /* End the function. */
8628 if (!TARGET_ABI_UNICOSMK && !flag_inhibit_size_directive)
8630 fputs ("\t.end ", file);
8631 assemble_name (file, fnname);
8634 inside_function = FALSE;
8636 /* Output jump tables and the static subroutine information block. */
8637 if (TARGET_ABI_UNICOSMK)
8639 unicosmk_output_ssib (file, fnname);
8640 unicosmk_output_deferred_case_vectors (file);
8644 #if TARGET_ABI_OPEN_VMS
8645 void avms_asm_output_external (FILE *file, tree decl ATTRIBUTE_UNUSED, const char *name)
8647 #ifdef DO_CRTL_NAMES
8654 /* Emit a tail call to FUNCTION after adjusting THIS by DELTA.
8656 In order to avoid the hordes of differences between generated code
8657 with and without TARGET_EXPLICIT_RELOCS, and to avoid duplicating
8658 lots of code loading up large constants, generate rtl and emit it
8659 instead of going straight to text.
8661 Not sure why this idea hasn't been explored before... */
8664 alpha_output_mi_thunk_osf (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
8665 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
8668 HOST_WIDE_INT hi, lo;
8669 rtx this_rtx, insn, funexp;
8671 /* We always require a valid GP. */
8672 emit_insn (gen_prologue_ldgp ());
8673 emit_note (NOTE_INSN_PROLOGUE_END);
8675 /* Find the "this" pointer. If the function returns a structure,
8676 the structure return pointer is in $16. */
8677 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
8678 this_rtx = gen_rtx_REG (Pmode, 17);
8680 this_rtx = gen_rtx_REG (Pmode, 16);
8682 /* Add DELTA. When possible we use ldah+lda. Otherwise load the
8683 entire constant for the add. */
8684 lo = ((delta & 0xffff) ^ 0x8000) - 0x8000;
8685 hi = (((delta - lo) & 0xffffffff) ^ 0x80000000) - 0x80000000;
8686 if (hi + lo == delta)
8689 emit_insn (gen_adddi3 (this_rtx, this_rtx, GEN_INT (hi)));
8691 emit_insn (gen_adddi3 (this_rtx, this_rtx, GEN_INT (lo)));
8695 rtx tmp = alpha_emit_set_long_const (gen_rtx_REG (Pmode, 0),
8696 delta, -(delta < 0));
8697 emit_insn (gen_adddi3 (this_rtx, this_rtx, tmp));
8700 /* Add a delta stored in the vtable at VCALL_OFFSET. */
8705 tmp = gen_rtx_REG (Pmode, 0);
8706 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this_rtx));
8708 lo = ((vcall_offset & 0xffff) ^ 0x8000) - 0x8000;
8709 hi = (((vcall_offset - lo) & 0xffffffff) ^ 0x80000000) - 0x80000000;
8710 if (hi + lo == vcall_offset)
8713 emit_insn (gen_adddi3 (tmp, tmp, GEN_INT (hi)));
8717 tmp2 = alpha_emit_set_long_const (gen_rtx_REG (Pmode, 1),
8718 vcall_offset, -(vcall_offset < 0));
8719 emit_insn (gen_adddi3 (tmp, tmp, tmp2));
8723 tmp2 = gen_rtx_PLUS (Pmode, tmp, GEN_INT (lo));
8726 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp2));
8728 emit_insn (gen_adddi3 (this_rtx, this_rtx, tmp));
8731 /* Generate a tail call to the target function. */
8732 if (! TREE_USED (function))
8734 assemble_external (function);
8735 TREE_USED (function) = 1;
8737 funexp = XEXP (DECL_RTL (function), 0);
8738 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
8739 insn = emit_call_insn (gen_sibcall (funexp, const0_rtx));
8740 SIBLING_CALL_P (insn) = 1;
8742 /* Run just enough of rest_of_compilation to get the insns emitted.
8743 There's not really enough bulk here to make other passes such as
8744 instruction scheduling worth while. Note that use_thunk calls
8745 assemble_start_function and assemble_end_function. */
8746 insn = get_insns ();
8747 insn_locators_alloc ();
8748 shorten_branches (insn);
8749 final_start_function (insn, file, 1);
8750 final (insn, file, 1);
8751 final_end_function ();
8753 #endif /* TARGET_ABI_OSF */
8755 /* Debugging support. */
8759 /* Count the number of sdb related labels are generated (to find block
8760 start and end boundaries). */
8762 int sdb_label_count = 0;
8764 /* Name of the file containing the current function. */
8766 static const char *current_function_file = "";
8768 /* Offsets to alpha virtual arg/local debugging pointers. */
8770 long alpha_arg_offset;
8771 long alpha_auto_offset;
8773 /* Emit a new filename to a stream. */
8776 alpha_output_filename (FILE *stream, const char *name)
8778 static int first_time = TRUE;
8783 ++num_source_filenames;
8784 current_function_file = name;
8785 fprintf (stream, "\t.file\t%d ", num_source_filenames);
8786 output_quoted_string (stream, name);
8787 fprintf (stream, "\n");
8788 if (!TARGET_GAS && write_symbols == DBX_DEBUG)
8789 fprintf (stream, "\t#@stabs\n");
8792 else if (write_symbols == DBX_DEBUG)
8793 /* dbxout.c will emit an appropriate .stabs directive. */
8796 else if (name != current_function_file
8797 && strcmp (name, current_function_file) != 0)
8799 if (inside_function && ! TARGET_GAS)
8800 fprintf (stream, "\t#.file\t%d ", num_source_filenames);
8803 ++num_source_filenames;
8804 current_function_file = name;
8805 fprintf (stream, "\t.file\t%d ", num_source_filenames);
8808 output_quoted_string (stream, name);
8809 fprintf (stream, "\n");
8813 /* Structure to show the current status of registers and memory. */
8815 struct shadow_summary
8818 unsigned int i : 31; /* Mask of int regs */
8819 unsigned int fp : 31; /* Mask of fp regs */
8820 unsigned int mem : 1; /* mem == imem | fpmem */
8824 /* Summary the effects of expression X on the machine. Update SUM, a pointer
8825 to the summary structure. SET is nonzero if the insn is setting the
8826 object, otherwise zero. */
8829 summarize_insn (rtx x, struct shadow_summary *sum, int set)
8831 const char *format_ptr;
8837 switch (GET_CODE (x))
8839 /* ??? Note that this case would be incorrect if the Alpha had a
8840 ZERO_EXTRACT in SET_DEST. */
8842 summarize_insn (SET_SRC (x), sum, 0);
8843 summarize_insn (SET_DEST (x), sum, 1);
8847 summarize_insn (XEXP (x, 0), sum, 1);
8851 summarize_insn (XEXP (x, 0), sum, 0);
8855 for (i = ASM_OPERANDS_INPUT_LENGTH (x) - 1; i >= 0; i--)
8856 summarize_insn (ASM_OPERANDS_INPUT (x, i), sum, 0);
8860 for (i = XVECLEN (x, 0) - 1; i >= 0; i--)
8861 summarize_insn (XVECEXP (x, 0, i), sum, 0);
8865 summarize_insn (SUBREG_REG (x), sum, 0);
8870 int regno = REGNO (x);
8871 unsigned long mask = ((unsigned long) 1) << (regno % 32);
8873 if (regno == 31 || regno == 63)
8879 sum->defd.i |= mask;
8881 sum->defd.fp |= mask;
8886 sum->used.i |= mask;
8888 sum->used.fp |= mask;
8899 /* Find the regs used in memory address computation: */
8900 summarize_insn (XEXP (x, 0), sum, 0);
8903 case CONST_INT: case CONST_DOUBLE:
8904 case SYMBOL_REF: case LABEL_REF: case CONST:
8905 case SCRATCH: case ASM_INPUT:
8908 /* Handle common unary and binary ops for efficiency. */
8909 case COMPARE: case PLUS: case MINUS: case MULT: case DIV:
8910 case MOD: case UDIV: case UMOD: case AND: case IOR:
8911 case XOR: case ASHIFT: case ROTATE: case ASHIFTRT: case LSHIFTRT:
8912 case ROTATERT: case SMIN: case SMAX: case UMIN: case UMAX:
8913 case NE: case EQ: case GE: case GT: case LE:
8914 case LT: case GEU: case GTU: case LEU: case LTU:
8915 summarize_insn (XEXP (x, 0), sum, 0);
8916 summarize_insn (XEXP (x, 1), sum, 0);
8919 case NEG: case NOT: case SIGN_EXTEND: case ZERO_EXTEND:
8920 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: case FLOAT:
8921 case FIX: case UNSIGNED_FLOAT: case UNSIGNED_FIX: case ABS:
8922 case SQRT: case FFS:
8923 summarize_insn (XEXP (x, 0), sum, 0);
8927 format_ptr = GET_RTX_FORMAT (GET_CODE (x));
8928 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
8929 switch (format_ptr[i])
8932 summarize_insn (XEXP (x, i), sum, 0);
8936 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8937 summarize_insn (XVECEXP (x, i, j), sum, 0);
8949 /* Ensure a sufficient number of `trapb' insns are in the code when
8950 the user requests code with a trap precision of functions or
8953 In naive mode, when the user requests a trap-precision of
8954 "instruction", a trapb is needed after every instruction that may
8955 generate a trap. This ensures that the code is resumption safe but
8958 When optimizations are turned on, we delay issuing a trapb as long
8959 as possible. In this context, a trap shadow is the sequence of
8960 instructions that starts with a (potentially) trap generating
8961 instruction and extends to the next trapb or call_pal instruction
8962 (but GCC never generates call_pal by itself). We can delay (and
8963 therefore sometimes omit) a trapb subject to the following
8966 (a) On entry to the trap shadow, if any Alpha register or memory
8967 location contains a value that is used as an operand value by some
8968 instruction in the trap shadow (live on entry), then no instruction
8969 in the trap shadow may modify the register or memory location.
8971 (b) Within the trap shadow, the computation of the base register
8972 for a memory load or store instruction may not involve using the
8973 result of an instruction that might generate an UNPREDICTABLE
8976 (c) Within the trap shadow, no register may be used more than once
8977 as a destination register. (This is to make life easier for the
8980 (d) The trap shadow may not include any branch instructions. */
8983 alpha_handle_trap_shadows (void)
8985 struct shadow_summary shadow;
8986 int trap_pending, exception_nesting;
8990 exception_nesting = 0;
8993 shadow.used.mem = 0;
8994 shadow.defd = shadow.used;
8996 for (i = get_insns (); i ; i = NEXT_INSN (i))
9000 switch (NOTE_KIND (i))
9002 case NOTE_INSN_EH_REGION_BEG:
9003 exception_nesting++;
9008 case NOTE_INSN_EH_REGION_END:
9009 exception_nesting--;
9014 case NOTE_INSN_EPILOGUE_BEG:
9015 if (trap_pending && alpha_tp >= ALPHA_TP_FUNC)
9020 else if (trap_pending)
9022 if (alpha_tp == ALPHA_TP_FUNC)
9025 && GET_CODE (PATTERN (i)) == RETURN)
9028 else if (alpha_tp == ALPHA_TP_INSN)
9032 struct shadow_summary sum;
9037 sum.defd = sum.used;
9039 switch (GET_CODE (i))
9042 /* Annoyingly, get_attr_trap will die on these. */
9043 if (GET_CODE (PATTERN (i)) == USE
9044 || GET_CODE (PATTERN (i)) == CLOBBER)
9047 summarize_insn (PATTERN (i), &sum, 0);
9049 if ((sum.defd.i & shadow.defd.i)
9050 || (sum.defd.fp & shadow.defd.fp))
9052 /* (c) would be violated */
9056 /* Combine shadow with summary of current insn: */
9057 shadow.used.i |= sum.used.i;
9058 shadow.used.fp |= sum.used.fp;
9059 shadow.used.mem |= sum.used.mem;
9060 shadow.defd.i |= sum.defd.i;
9061 shadow.defd.fp |= sum.defd.fp;
9062 shadow.defd.mem |= sum.defd.mem;
9064 if ((sum.defd.i & shadow.used.i)
9065 || (sum.defd.fp & shadow.used.fp)
9066 || (sum.defd.mem & shadow.used.mem))
9068 /* (a) would be violated (also takes care of (b)) */
9069 gcc_assert (get_attr_trap (i) != TRAP_YES
9070 || (!(sum.defd.i & sum.used.i)
9071 && !(sum.defd.fp & sum.used.fp)));
9089 n = emit_insn_before (gen_trapb (), i);
9090 PUT_MODE (n, TImode);
9091 PUT_MODE (i, TImode);
9095 shadow.used.mem = 0;
9096 shadow.defd = shadow.used;
9101 if ((exception_nesting > 0 || alpha_tp >= ALPHA_TP_FUNC)
9102 && NONJUMP_INSN_P (i)
9103 && GET_CODE (PATTERN (i)) != USE
9104 && GET_CODE (PATTERN (i)) != CLOBBER
9105 && get_attr_trap (i) == TRAP_YES)
9107 if (optimize && !trap_pending)
9108 summarize_insn (PATTERN (i), &shadow, 0);
9114 /* Alpha can only issue instruction groups simultaneously if they are
9115 suitably aligned. This is very processor-specific. */
9116 /* There are a number of entries in alphaev4_insn_pipe and alphaev5_insn_pipe
9117 that are marked "fake". These instructions do not exist on that target,
9118 but it is possible to see these insns with deranged combinations of
9119 command-line options, such as "-mtune=ev4 -mmax". Instead of aborting,
9120 choose a result at random. */
9122 enum alphaev4_pipe {
9129 enum alphaev5_pipe {
9140 static enum alphaev4_pipe
9141 alphaev4_insn_pipe (rtx insn)
9143 if (recog_memoized (insn) < 0)
9145 if (get_attr_length (insn) != 4)
9148 switch (get_attr_type (insn))
9164 case TYPE_MVI: /* fake */
9179 case TYPE_FSQRT: /* fake */
9180 case TYPE_FTOI: /* fake */
9181 case TYPE_ITOF: /* fake */
9189 static enum alphaev5_pipe
9190 alphaev5_insn_pipe (rtx insn)
9192 if (recog_memoized (insn) < 0)
9194 if (get_attr_length (insn) != 4)
9197 switch (get_attr_type (insn))
9217 case TYPE_FTOI: /* fake */
9218 case TYPE_ITOF: /* fake */
9233 case TYPE_FSQRT: /* fake */
9244 /* IN_USE is a mask of the slots currently filled within the insn group.
9245 The mask bits come from alphaev4_pipe above. If EV4_IBX is set, then
9246 the insn in EV4_IB0 can be swapped by the hardware into EV4_IB1.
9248 LEN is, of course, the length of the group in bytes. */
9251 alphaev4_next_group (rtx insn, int *pin_use, int *plen)
9258 || GET_CODE (PATTERN (insn)) == CLOBBER
9259 || GET_CODE (PATTERN (insn)) == USE)
9264 enum alphaev4_pipe pipe;
9266 pipe = alphaev4_insn_pipe (insn);
9270 /* Force complex instructions to start new groups. */
9274 /* If this is a completely unrecognized insn, it's an asm.
9275 We don't know how long it is, so record length as -1 to
9276 signal a needed realignment. */
9277 if (recog_memoized (insn) < 0)
9280 len = get_attr_length (insn);
9284 if (in_use & EV4_IB0)
9286 if (in_use & EV4_IB1)
9291 in_use |= EV4_IB0 | EV4_IBX;
9295 if (in_use & EV4_IB0)
9297 if (!(in_use & EV4_IBX) || (in_use & EV4_IB1))
9305 if (in_use & EV4_IB1)
9315 /* Haifa doesn't do well scheduling branches. */
9320 insn = next_nonnote_insn (insn);
9322 if (!insn || ! INSN_P (insn))
9325 /* Let Haifa tell us where it thinks insn group boundaries are. */
9326 if (GET_MODE (insn) == TImode)
9329 if (GET_CODE (insn) == CLOBBER || GET_CODE (insn) == USE)
9334 insn = next_nonnote_insn (insn);
9342 /* IN_USE is a mask of the slots currently filled within the insn group.
9343 The mask bits come from alphaev5_pipe above. If EV5_E01 is set, then
9344 the insn in EV5_E0 can be swapped by the hardware into EV5_E1.
9346 LEN is, of course, the length of the group in bytes. */
9349 alphaev5_next_group (rtx insn, int *pin_use, int *plen)
9356 || GET_CODE (PATTERN (insn)) == CLOBBER
9357 || GET_CODE (PATTERN (insn)) == USE)
9362 enum alphaev5_pipe pipe;
9364 pipe = alphaev5_insn_pipe (insn);
9368 /* Force complex instructions to start new groups. */
9372 /* If this is a completely unrecognized insn, it's an asm.
9373 We don't know how long it is, so record length as -1 to
9374 signal a needed realignment. */
9375 if (recog_memoized (insn) < 0)
9378 len = get_attr_length (insn);
9381 /* ??? Most of the places below, we would like to assert never
9382 happen, as it would indicate an error either in Haifa, or
9383 in the scheduling description. Unfortunately, Haifa never
9384 schedules the last instruction of the BB, so we don't have
9385 an accurate TI bit to go off. */
9387 if (in_use & EV5_E0)
9389 if (in_use & EV5_E1)
9394 in_use |= EV5_E0 | EV5_E01;
9398 if (in_use & EV5_E0)
9400 if (!(in_use & EV5_E01) || (in_use & EV5_E1))
9408 if (in_use & EV5_E1)
9414 if (in_use & EV5_FA)
9416 if (in_use & EV5_FM)
9421 in_use |= EV5_FA | EV5_FAM;
9425 if (in_use & EV5_FA)
9431 if (in_use & EV5_FM)
9444 /* Haifa doesn't do well scheduling branches. */
9445 /* ??? If this is predicted not-taken, slotting continues, except
9446 that no more IBR, FBR, or JSR insns may be slotted. */
9451 insn = next_nonnote_insn (insn);
9453 if (!insn || ! INSN_P (insn))
9456 /* Let Haifa tell us where it thinks insn group boundaries are. */
9457 if (GET_MODE (insn) == TImode)
9460 if (GET_CODE (insn) == CLOBBER || GET_CODE (insn) == USE)
9465 insn = next_nonnote_insn (insn);
9474 alphaev4_next_nop (int *pin_use)
9476 int in_use = *pin_use;
9479 if (!(in_use & EV4_IB0))
9484 else if ((in_use & (EV4_IBX|EV4_IB1)) == EV4_IBX)
9489 else if (TARGET_FP && !(in_use & EV4_IB1))
9502 alphaev5_next_nop (int *pin_use)
9504 int in_use = *pin_use;
9507 if (!(in_use & EV5_E1))
9512 else if (TARGET_FP && !(in_use & EV5_FA))
9517 else if (TARGET_FP && !(in_use & EV5_FM))
9529 /* The instruction group alignment main loop. */
9532 alpha_align_insns (unsigned int max_align,
9533 rtx (*next_group) (rtx, int *, int *),
9534 rtx (*next_nop) (int *))
9536 /* ALIGN is the known alignment for the insn group. */
9538 /* OFS is the offset of the current insn in the insn group. */
9540 int prev_in_use, in_use, len, ldgp;
9543 /* Let shorten branches care for assigning alignments to code labels. */
9544 shorten_branches (get_insns ());
9546 if (align_functions < 4)
9548 else if ((unsigned int) align_functions < max_align)
9549 align = align_functions;
9553 ofs = prev_in_use = 0;
9556 i = next_nonnote_insn (i);
9558 ldgp = alpha_function_needs_gp ? 8 : 0;
9562 next = (*next_group) (i, &in_use, &len);
9564 /* When we see a label, resync alignment etc. */
9567 unsigned int new_align = 1 << label_to_alignment (i);
9569 if (new_align >= align)
9571 align = new_align < max_align ? new_align : max_align;
9575 else if (ofs & (new_align-1))
9576 ofs = (ofs | (new_align-1)) + 1;
9580 /* Handle complex instructions special. */
9581 else if (in_use == 0)
9583 /* Asms will have length < 0. This is a signal that we have
9584 lost alignment knowledge. Assume, however, that the asm
9585 will not mis-align instructions. */
9594 /* If the known alignment is smaller than the recognized insn group,
9595 realign the output. */
9596 else if ((int) align < len)
9598 unsigned int new_log_align = len > 8 ? 4 : 3;
9601 where = prev = prev_nonnote_insn (i);
9602 if (!where || !LABEL_P (where))
9605 /* Can't realign between a call and its gp reload. */
9606 if (! (TARGET_EXPLICIT_RELOCS
9607 && prev && CALL_P (prev)))
9609 emit_insn_before (gen_realign (GEN_INT (new_log_align)), where);
9610 align = 1 << new_log_align;
9615 /* We may not insert padding inside the initial ldgp sequence. */
9619 /* If the group won't fit in the same INT16 as the previous,
9620 we need to add padding to keep the group together. Rather
9621 than simply leaving the insn filling to the assembler, we
9622 can make use of the knowledge of what sorts of instructions
9623 were issued in the previous group to make sure that all of
9624 the added nops are really free. */
9625 else if (ofs + len > (int) align)
9627 int nop_count = (align - ofs) / 4;
9630 /* Insert nops before labels, branches, and calls to truly merge
9631 the execution of the nops with the previous instruction group. */
9632 where = prev_nonnote_insn (i);
9635 if (LABEL_P (where))
9637 rtx where2 = prev_nonnote_insn (where);
9638 if (where2 && JUMP_P (where2))
9641 else if (NONJUMP_INSN_P (where))
9648 emit_insn_before ((*next_nop)(&prev_in_use), where);
9649 while (--nop_count);
9653 ofs = (ofs + len) & (align - 1);
9654 prev_in_use = in_use;
9659 /* Insert an unop between a noreturn function call and GP load. */
9662 alpha_pad_noreturn (void)
9666 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
9669 || !find_reg_note (insn, REG_NORETURN, NULL_RTX))
9672 next = next_active_insn (insn);
9676 rtx pat = PATTERN (next);
9678 if (GET_CODE (pat) == SET
9679 && GET_CODE (SET_SRC (pat)) == UNSPEC_VOLATILE
9680 && XINT (SET_SRC (pat), 1) == UNSPECV_LDGP1)
9681 emit_insn_after (gen_unop (), insn);
9686 /* Machine dependent reorg pass. */
9691 /* Workaround for a linker error that triggers when an
9692 exception handler immediatelly follows a noreturn function.
9694 The instruction stream from an object file:
9696 54: 00 40 5b 6b jsr ra,(t12),58 <__func+0x58>
9697 58: 00 00 ba 27 ldah gp,0(ra)
9698 5c: 00 00 bd 23 lda gp,0(gp)
9699 60: 00 00 7d a7 ldq t12,0(gp)
9700 64: 00 40 5b 6b jsr ra,(t12),68 <__func+0x68>
9702 was converted in the final link pass to:
9704 fdb24: a0 03 40 d3 bsr ra,fe9a8 <_called_func+0x8>
9705 fdb28: 00 00 fe 2f unop
9706 fdb2c: 00 00 fe 2f unop
9707 fdb30: 30 82 7d a7 ldq t12,-32208(gp)
9708 fdb34: 00 40 5b 6b jsr ra,(t12),fdb38 <__func+0x68>
9710 GP load instructions were wrongly cleared by the linker relaxation
9711 pass. This workaround prevents removal of GP loads by inserting
9712 an unop instruction between a noreturn function call and
9713 exception handler prologue. */
9715 if (current_function_has_exception_handlers ())
9716 alpha_pad_noreturn ();
9718 if (alpha_tp != ALPHA_TP_PROG || flag_exceptions)
9719 alpha_handle_trap_shadows ();
9721 /* Due to the number of extra trapb insns, don't bother fixing up
9722 alignment when trap precision is instruction. Moreover, we can
9723 only do our job when sched2 is run. */
9724 if (optimize && !optimize_size
9725 && alpha_tp != ALPHA_TP_INSN
9726 && flag_schedule_insns_after_reload)
9728 if (alpha_tune == PROCESSOR_EV4)
9729 alpha_align_insns (8, alphaev4_next_group, alphaev4_next_nop);
9730 else if (alpha_tune == PROCESSOR_EV5)
9731 alpha_align_insns (16, alphaev5_next_group, alphaev5_next_nop);
9735 #if !TARGET_ABI_UNICOSMK
9742 alpha_file_start (void)
9744 #ifdef OBJECT_FORMAT_ELF
9745 /* If emitting dwarf2 debug information, we cannot generate a .file
9746 directive to start the file, as it will conflict with dwarf2out
9747 file numbers. So it's only useful when emitting mdebug output. */
9748 targetm.asm_file_start_file_directive = (write_symbols == DBX_DEBUG);
9751 default_file_start ();
9753 fprintf (asm_out_file, "\t.verstamp %d %d\n", MS_STAMP, LS_STAMP);
9756 fputs ("\t.set noreorder\n", asm_out_file);
9757 fputs ("\t.set volatile\n", asm_out_file);
9758 if (!TARGET_ABI_OPEN_VMS)
9759 fputs ("\t.set noat\n", asm_out_file);
9760 if (TARGET_EXPLICIT_RELOCS)
9761 fputs ("\t.set nomacro\n", asm_out_file);
9762 if (TARGET_SUPPORT_ARCH | TARGET_BWX | TARGET_MAX | TARGET_FIX | TARGET_CIX)
9766 if (alpha_cpu == PROCESSOR_EV6 || TARGET_FIX || TARGET_CIX)
9768 else if (TARGET_MAX)
9770 else if (TARGET_BWX)
9772 else if (alpha_cpu == PROCESSOR_EV5)
9777 fprintf (asm_out_file, "\t.arch %s\n", arch);
9782 #ifdef OBJECT_FORMAT_ELF
9783 /* Since we don't have a .dynbss section, we should not allow global
9784 relocations in the .rodata section. */
9787 alpha_elf_reloc_rw_mask (void)
9789 return flag_pic ? 3 : 2;
9792 /* Return a section for X. The only special thing we do here is to
9793 honor small data. */
9796 alpha_elf_select_rtx_section (enum machine_mode mode, rtx x,
9797 unsigned HOST_WIDE_INT align)
9799 if (TARGET_SMALL_DATA && GET_MODE_SIZE (mode) <= g_switch_value)
9800 /* ??? Consider using mergeable sdata sections. */
9801 return sdata_section;
9803 return default_elf_select_rtx_section (mode, x, align);
9807 alpha_elf_section_type_flags (tree decl, const char *name, int reloc)
9809 unsigned int flags = 0;
9811 if (strcmp (name, ".sdata") == 0
9812 || strncmp (name, ".sdata.", 7) == 0
9813 || strncmp (name, ".gnu.linkonce.s.", 16) == 0
9814 || strcmp (name, ".sbss") == 0
9815 || strncmp (name, ".sbss.", 6) == 0
9816 || strncmp (name, ".gnu.linkonce.sb.", 17) == 0)
9817 flags = SECTION_SMALL;
9819 flags |= default_section_type_flags (decl, name, reloc);
9822 #endif /* OBJECT_FORMAT_ELF */
9824 /* Structure to collect function names for final output in link section. */
9825 /* Note that items marked with GTY can't be ifdef'ed out. */
9827 enum links_kind {KIND_UNUSED, KIND_LOCAL, KIND_EXTERN};
9828 enum reloc_kind {KIND_LINKAGE, KIND_CODEADDR};
9830 struct GTY(()) alpha_links
9835 enum links_kind lkind;
9836 enum reloc_kind rkind;
9839 struct GTY(()) alpha_funcs
9842 splay_tree GTY ((param1_is (char *), param2_is (struct alpha_links *)))
9846 static GTY ((param1_is (char *), param2_is (struct alpha_links *)))
9847 splay_tree alpha_links_tree;
9848 static GTY ((param1_is (tree), param2_is (struct alpha_funcs *)))
9849 splay_tree alpha_funcs_tree;
9851 static GTY(()) int alpha_funcs_num;
9853 #if TARGET_ABI_OPEN_VMS
9855 /* Return the VMS argument type corresponding to MODE. */
9858 alpha_arg_type (enum machine_mode mode)
9863 return TARGET_FLOAT_VAX ? FF : FS;
9865 return TARGET_FLOAT_VAX ? FD : FT;
9871 /* Return an rtx for an integer representing the VMS Argument Information
9875 alpha_arg_info_reg_val (CUMULATIVE_ARGS cum)
9877 unsigned HOST_WIDE_INT regval = cum.num_args;
9880 for (i = 0; i < 6; i++)
9881 regval |= ((int) cum.atypes[i]) << (i * 3 + 8);
9883 return GEN_INT (regval);
9886 /* Register the need for a (fake) .linkage entry for calls to function NAME.
9887 IS_LOCAL is 1 if this is for a definition, 0 if this is for a real call.
9888 Return a SYMBOL_REF suited to the call instruction. */
9891 alpha_need_linkage (const char *name, int is_local)
9893 splay_tree_node node;
9894 struct alpha_links *al;
9903 struct alpha_funcs *cfaf;
9905 if (!alpha_funcs_tree)
9906 alpha_funcs_tree = splay_tree_new_ggc
9907 (splay_tree_compare_pointers,
9908 ggc_alloc_splay_tree_tree_node_tree_node_splay_tree_s,
9909 ggc_alloc_splay_tree_tree_node_tree_node_splay_tree_node_s);
9912 cfaf = ggc_alloc_alpha_funcs ();
9915 cfaf->num = ++alpha_funcs_num;
9917 splay_tree_insert (alpha_funcs_tree,
9918 (splay_tree_key) current_function_decl,
9919 (splay_tree_value) cfaf);
9922 if (alpha_links_tree)
9924 /* Is this name already defined? */
9926 node = splay_tree_lookup (alpha_links_tree, (splay_tree_key) name);
9929 al = (struct alpha_links *) node->value;
9932 /* Defined here but external assumed. */
9933 if (al->lkind == KIND_EXTERN)
9934 al->lkind = KIND_LOCAL;
9938 /* Used here but unused assumed. */
9939 if (al->lkind == KIND_UNUSED)
9940 al->lkind = KIND_LOCAL;
9946 alpha_links_tree = splay_tree_new_ggc
9947 ((splay_tree_compare_fn) strcmp,
9948 ggc_alloc_splay_tree_str_alpha_links_splay_tree_s,
9949 ggc_alloc_splay_tree_str_alpha_links_splay_tree_node_s);
9951 al = ggc_alloc_alpha_links ();
9952 name = ggc_strdup (name);
9954 /* Assume external if no definition. */
9955 al->lkind = (is_local ? KIND_UNUSED : KIND_EXTERN);
9957 /* Ensure we have an IDENTIFIER so assemble_name can mark it used
9958 and find the ultimate alias target like assemble_name. */
9959 id = get_identifier (name);
9961 while (IDENTIFIER_TRANSPARENT_ALIAS (id))
9963 id = TREE_CHAIN (id);
9964 target = IDENTIFIER_POINTER (id);
9967 al->target = target ? target : name;
9968 al->linkage = gen_rtx_SYMBOL_REF (Pmode, name);
9970 splay_tree_insert (alpha_links_tree, (splay_tree_key) name,
9971 (splay_tree_value) al);
9976 /* Return a SYMBOL_REF representing the reference to the .linkage entry
9977 of function FUNC built for calls made from CFUNDECL. LFLAG is 1 if
9978 this is the reference to the linkage pointer value, 0 if this is the
9979 reference to the function entry value. RFLAG is 1 if this a reduced
9980 reference (code address only), 0 if this is a full reference. */
9983 alpha_use_linkage (rtx func, tree cfundecl, int lflag, int rflag)
9985 splay_tree_node cfunnode;
9986 struct alpha_funcs *cfaf;
9987 struct alpha_links *al;
9988 const char *name = XSTR (func, 0);
9990 cfaf = (struct alpha_funcs *) 0;
9991 al = (struct alpha_links *) 0;
9993 cfunnode = splay_tree_lookup (alpha_funcs_tree, (splay_tree_key) cfundecl);
9994 cfaf = (struct alpha_funcs *) cfunnode->value;
9998 splay_tree_node lnode;
10000 /* Is this name already defined? */
10002 lnode = splay_tree_lookup (cfaf->links, (splay_tree_key) name);
10004 al = (struct alpha_links *) lnode->value;
10007 cfaf->links = splay_tree_new_ggc
10008 ((splay_tree_compare_fn) strcmp,
10009 ggc_alloc_splay_tree_str_alpha_links_splay_tree_s,
10010 ggc_alloc_splay_tree_str_alpha_links_splay_tree_node_s);
10017 splay_tree_node node = 0;
10018 struct alpha_links *anl;
10020 if (name[0] == '*')
10023 name_len = strlen (name);
10024 linksym = (char *) alloca (name_len + 50);
10026 al = ggc_alloc_alpha_links ();
10027 al->num = cfaf->num;
10029 node = splay_tree_lookup (alpha_links_tree, (splay_tree_key) name);
10032 anl = (struct alpha_links *) node->value;
10033 al->lkind = anl->lkind;
10034 name = anl->target;
10037 sprintf (linksym, "$%d..%s..lk", cfaf->num, name);
10038 buflen = strlen (linksym);
10040 al->linkage = gen_rtx_SYMBOL_REF
10041 (Pmode, ggc_alloc_string (linksym, buflen + 1));
10043 splay_tree_insert (cfaf->links, (splay_tree_key) name,
10044 (splay_tree_value) al);
10048 al->rkind = KIND_CODEADDR;
10050 al->rkind = KIND_LINKAGE;
10053 return gen_rtx_MEM (Pmode, plus_constant (al->linkage, 8));
10055 return al->linkage;
10059 alpha_write_one_linkage (splay_tree_node node, void *data)
10061 const char *const name = (const char *) node->key;
10062 struct alpha_links *link = (struct alpha_links *) node->value;
10063 FILE *stream = (FILE *) data;
10065 fprintf (stream, "$%d..%s..lk:\n", link->num, name);
10066 if (link->rkind == KIND_CODEADDR)
10068 if (link->lkind == KIND_LOCAL)
10070 /* Local and used */
10071 fprintf (stream, "\t.quad %s..en\n", name);
10075 /* External and used, request code address. */
10076 fprintf (stream, "\t.code_address %s\n", name);
10081 if (link->lkind == KIND_LOCAL)
10083 /* Local and used, build linkage pair. */
10084 fprintf (stream, "\t.quad %s..en\n", name);
10085 fprintf (stream, "\t.quad %s\n", name);
10089 /* External and used, request linkage pair. */
10090 fprintf (stream, "\t.linkage %s\n", name);
10098 alpha_write_linkage (FILE *stream, const char *funname, tree fundecl)
10100 splay_tree_node node;
10101 struct alpha_funcs *func;
10103 fprintf (stream, "\t.link\n");
10104 fprintf (stream, "\t.align 3\n");
10107 node = splay_tree_lookup (alpha_funcs_tree, (splay_tree_key) fundecl);
10108 func = (struct alpha_funcs *) node->value;
10110 fputs ("\t.name ", stream);
10111 assemble_name (stream, funname);
10112 fputs ("..na\n", stream);
10113 ASM_OUTPUT_LABEL (stream, funname);
10114 fprintf (stream, "\t.pdesc ");
10115 assemble_name (stream, funname);
10116 fprintf (stream, "..en,%s\n",
10117 alpha_procedure_type == PT_STACK ? "stack"
10118 : alpha_procedure_type == PT_REGISTER ? "reg" : "null");
10122 splay_tree_foreach (func->links, alpha_write_one_linkage, stream);
10123 /* splay_tree_delete (func->links); */
10127 /* Switch to an arbitrary section NAME with attributes as specified
10128 by FLAGS. ALIGN specifies any known alignment requirements for
10129 the section; 0 if the default should be used. */
10132 vms_asm_named_section (const char *name, unsigned int flags,
10133 tree decl ATTRIBUTE_UNUSED)
10135 fputc ('\n', asm_out_file);
10136 fprintf (asm_out_file, ".section\t%s", name);
10138 if (flags & SECTION_DEBUG)
10139 fprintf (asm_out_file, ",NOWRT");
10141 fputc ('\n', asm_out_file);
10144 /* Record an element in the table of global constructors. SYMBOL is
10145 a SYMBOL_REF of the function to be called; PRIORITY is a number
10146 between 0 and MAX_INIT_PRIORITY.
10148 Differs from default_ctors_section_asm_out_constructor in that the
10149 width of the .ctors entry is always 64 bits, rather than the 32 bits
10150 used by a normal pointer. */
10153 vms_asm_out_constructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
10155 switch_to_section (ctors_section);
10156 assemble_align (BITS_PER_WORD);
10157 assemble_integer (symbol, UNITS_PER_WORD, BITS_PER_WORD, 1);
10161 vms_asm_out_destructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
10163 switch_to_section (dtors_section);
10164 assemble_align (BITS_PER_WORD);
10165 assemble_integer (symbol, UNITS_PER_WORD, BITS_PER_WORD, 1);
10170 alpha_need_linkage (const char *name ATTRIBUTE_UNUSED,
10171 int is_local ATTRIBUTE_UNUSED)
10177 alpha_use_linkage (rtx func ATTRIBUTE_UNUSED,
10178 tree cfundecl ATTRIBUTE_UNUSED,
10179 int lflag ATTRIBUTE_UNUSED,
10180 int rflag ATTRIBUTE_UNUSED)
10185 #endif /* TARGET_ABI_OPEN_VMS */
10187 #if TARGET_ABI_UNICOSMK
10189 /* This evaluates to true if we do not know how to pass TYPE solely in
10190 registers. This is the case for all arguments that do not fit in two
10194 unicosmk_must_pass_in_stack (enum machine_mode mode, const_tree type)
10199 if (TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
10201 if (TREE_ADDRESSABLE (type))
10204 return ALPHA_ARG_SIZE (mode, type, 0) > 2;
10207 /* Define the offset between two registers, one to be eliminated, and the
10208 other its replacement, at the start of a routine. */
10211 unicosmk_initial_elimination_offset (int from, int to)
10215 fixed_size = alpha_sa_size();
10216 if (fixed_size != 0)
10219 if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
10220 return -fixed_size;
10221 else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
10223 else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
10224 return (ALPHA_ROUND (crtl->outgoing_args_size)
10225 + ALPHA_ROUND (get_frame_size()));
10226 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
10227 return (ALPHA_ROUND (fixed_size)
10228 + ALPHA_ROUND (get_frame_size()
10229 + crtl->outgoing_args_size));
10231 gcc_unreachable ();
10234 /* Output the module name for .ident and .end directives. We have to strip
10235 directories and add make sure that the module name starts with a letter
10239 unicosmk_output_module_name (FILE *file)
10241 const char *name = lbasename (main_input_filename);
10242 unsigned len = strlen (name);
10243 char *clean_name = alloca (len + 2);
10244 char *ptr = clean_name;
10246 /* CAM only accepts module names that start with a letter or '$'. We
10247 prefix the module name with a '$' if necessary. */
10249 if (!ISALPHA (*name))
10251 memcpy (ptr, name, len + 1);
10252 clean_symbol_name (clean_name);
10253 fputs (clean_name, file);
10256 /* Output the definition of a common variable. */
10259 unicosmk_output_common (FILE *file, const char *name, int size, int align)
10262 printf ("T3E__: common %s\n", name);
10265 fputs("\t.endp\n\n\t.psect ", file);
10266 assemble_name(file, name);
10267 fprintf(file, ",%d,common\n", floor_log2 (align / BITS_PER_UNIT));
10268 fprintf(file, "\t.byte\t0:%d\n", size);
10270 /* Mark the symbol as defined in this module. */
10271 name_tree = get_identifier (name);
10272 TREE_ASM_WRITTEN (name_tree) = 1;
10275 #define SECTION_PUBLIC SECTION_MACH_DEP
10276 #define SECTION_MAIN (SECTION_PUBLIC << 1)
10277 static int current_section_align;
10279 /* A get_unnamed_section callback for switching to the text section. */
10282 unicosmk_output_text_section_asm_op (const void *data ATTRIBUTE_UNUSED)
10284 static int count = 0;
10285 fprintf (asm_out_file, "\t.endp\n\n\t.psect\tgcc@text___%d,code\n", count++);
10288 /* A get_unnamed_section callback for switching to the data section. */
10291 unicosmk_output_data_section_asm_op (const void *data ATTRIBUTE_UNUSED)
10293 static int count = 1;
10294 fprintf (asm_out_file, "\t.endp\n\n\t.psect\tgcc@data___%d,data\n", count++);
10297 /* Implement TARGET_ASM_INIT_SECTIONS.
10299 The Cray assembler is really weird with respect to sections. It has only
10300 named sections and you can't reopen a section once it has been closed.
10301 This means that we have to generate unique names whenever we want to
10302 reenter the text or the data section. */
10305 unicosmk_init_sections (void)
10307 text_section = get_unnamed_section (SECTION_CODE,
10308 unicosmk_output_text_section_asm_op,
10310 data_section = get_unnamed_section (SECTION_WRITE,
10311 unicosmk_output_data_section_asm_op,
10313 readonly_data_section = data_section;
10316 static unsigned int
10317 unicosmk_section_type_flags (tree decl, const char *name,
10318 int reloc ATTRIBUTE_UNUSED)
10320 unsigned int flags = default_section_type_flags (decl, name, reloc);
10325 if (TREE_CODE (decl) == FUNCTION_DECL)
10327 current_section_align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
10328 if (align_functions_log > current_section_align)
10329 current_section_align = align_functions_log;
10331 if (! strcmp (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl)), "main"))
10332 flags |= SECTION_MAIN;
10335 current_section_align = floor_log2 (DECL_ALIGN (decl) / BITS_PER_UNIT);
10337 if (TREE_PUBLIC (decl))
10338 flags |= SECTION_PUBLIC;
10343 /* Generate a section name for decl and associate it with the
10347 unicosmk_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
10354 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
10355 name = default_strip_name_encoding (name);
10356 len = strlen (name);
10358 if (TREE_CODE (decl) == FUNCTION_DECL)
10362 /* It is essential that we prefix the section name here because
10363 otherwise the section names generated for constructors and
10364 destructors confuse collect2. */
10366 string = alloca (len + 6);
10367 sprintf (string, "code@%s", name);
10368 DECL_SECTION_NAME (decl) = build_string (len + 5, string);
10370 else if (TREE_PUBLIC (decl))
10371 DECL_SECTION_NAME (decl) = build_string (len, name);
10376 string = alloca (len + 6);
10377 sprintf (string, "data@%s", name);
10378 DECL_SECTION_NAME (decl) = build_string (len + 5, string);
10382 /* Switch to an arbitrary section NAME with attributes as specified
10383 by FLAGS. ALIGN specifies any known alignment requirements for
10384 the section; 0 if the default should be used. */
10387 unicosmk_asm_named_section (const char *name, unsigned int flags,
10388 tree decl ATTRIBUTE_UNUSED)
10392 /* Close the previous section. */
10394 fputs ("\t.endp\n\n", asm_out_file);
10396 /* Find out what kind of section we are opening. */
10398 if (flags & SECTION_MAIN)
10399 fputs ("\t.start\tmain\n", asm_out_file);
10401 if (flags & SECTION_CODE)
10403 else if (flags & SECTION_PUBLIC)
10408 if (current_section_align != 0)
10409 fprintf (asm_out_file, "\t.psect\t%s,%d,%s\n", name,
10410 current_section_align, kind);
10412 fprintf (asm_out_file, "\t.psect\t%s,%s\n", name, kind);
10416 unicosmk_insert_attributes (tree decl, tree *attr_ptr ATTRIBUTE_UNUSED)
10419 && (TREE_PUBLIC (decl) || TREE_CODE (decl) == FUNCTION_DECL))
10420 unicosmk_unique_section (decl, 0);
10423 /* Output an alignment directive. We have to use the macro 'gcc@code@align'
10424 in code sections because .align fill unused space with zeroes. */
10427 unicosmk_output_align (FILE *file, int align)
10429 if (inside_function)
10430 fprintf (file, "\tgcc@code@align\t%d\n", align);
10432 fprintf (file, "\t.align\t%d\n", align);
10435 /* Add a case vector to the current function's list of deferred case
10436 vectors. Case vectors have to be put into a separate section because CAM
10437 does not allow data definitions in code sections. */
10440 unicosmk_defer_case_vector (rtx lab, rtx vec)
10442 struct machine_function *machine = cfun->machine;
10444 vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec);
10445 machine->addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec,
10446 machine->addr_list);
10449 /* Output a case vector. */
10452 unicosmk_output_addr_vec (FILE *file, rtx vec)
10454 rtx lab = XEXP (vec, 0);
10455 rtx body = XEXP (vec, 1);
10456 int vlen = XVECLEN (body, 0);
10459 (*targetm.asm_out.internal_label) (file, "L", CODE_LABEL_NUMBER (lab));
10461 for (idx = 0; idx < vlen; idx++)
10463 ASM_OUTPUT_ADDR_VEC_ELT
10464 (file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0)));
10468 /* Output current function's deferred case vectors. */
10471 unicosmk_output_deferred_case_vectors (FILE *file)
10473 struct machine_function *machine = cfun->machine;
10476 if (machine->addr_list == NULL_RTX)
10479 switch_to_section (data_section);
10480 for (t = machine->addr_list; t; t = XEXP (t, 1))
10481 unicosmk_output_addr_vec (file, XEXP (t, 0));
10484 /* Generate the name of the SSIB section for the current function. */
10486 #define SSIB_PREFIX "__SSIB_"
10487 #define SSIB_PREFIX_LEN 7
10489 static const char *
10490 unicosmk_ssib_name (void)
10492 /* This is ok since CAM won't be able to deal with names longer than that
10495 static char name[256];
10498 const char *fnname;
10501 x = DECL_RTL (cfun->decl);
10502 gcc_assert (MEM_P (x));
10504 gcc_assert (GET_CODE (x) == SYMBOL_REF);
10505 fnname = XSTR (x, 0);
10507 len = strlen (fnname);
10508 if (len + SSIB_PREFIX_LEN > 255)
10509 len = 255 - SSIB_PREFIX_LEN;
10511 strcpy (name, SSIB_PREFIX);
10512 strncpy (name + SSIB_PREFIX_LEN, fnname, len);
10513 name[len + SSIB_PREFIX_LEN] = 0;
10518 /* Set up the dynamic subprogram information block (DSIB) and update the
10519 frame pointer register ($15) for subroutines which have a frame. If the
10520 subroutine doesn't have a frame, simply increment $15. */
10523 unicosmk_gen_dsib (unsigned long *imaskP)
10525 if (alpha_procedure_type == PT_STACK)
10527 const char *ssib_name;
10530 /* Allocate 64 bytes for the DSIB. */
10532 FRP (emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx,
10534 emit_insn (gen_blockage ());
10536 /* Save the return address. */
10538 mem = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx, 56));
10539 set_mem_alias_set (mem, alpha_sr_alias_set);
10540 FRP (emit_move_insn (mem, gen_rtx_REG (DImode, REG_RA)));
10541 (*imaskP) &= ~(1UL << REG_RA);
10543 /* Save the old frame pointer. */
10545 mem = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx, 48));
10546 set_mem_alias_set (mem, alpha_sr_alias_set);
10547 FRP (emit_move_insn (mem, hard_frame_pointer_rtx));
10548 (*imaskP) &= ~(1UL << HARD_FRAME_POINTER_REGNUM);
10550 emit_insn (gen_blockage ());
10552 /* Store the SSIB pointer. */
10554 ssib_name = ggc_strdup (unicosmk_ssib_name ());
10555 mem = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx, 32));
10556 set_mem_alias_set (mem, alpha_sr_alias_set);
10558 FRP (emit_move_insn (gen_rtx_REG (DImode, 5),
10559 gen_rtx_SYMBOL_REF (Pmode, ssib_name)));
10560 FRP (emit_move_insn (mem, gen_rtx_REG (DImode, 5)));
10562 /* Save the CIW index. */
10564 mem = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx, 24));
10565 set_mem_alias_set (mem, alpha_sr_alias_set);
10566 FRP (emit_move_insn (mem, gen_rtx_REG (DImode, 25)));
10568 emit_insn (gen_blockage ());
10570 /* Set the new frame pointer. */
10571 FRP (emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
10572 stack_pointer_rtx, GEN_INT (64))));
10576 /* Increment the frame pointer register to indicate that we do not
10578 emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
10579 hard_frame_pointer_rtx, const1_rtx));
10583 /* Output the static subroutine information block for the current
10587 unicosmk_output_ssib (FILE *file, const char *fnname)
10593 struct machine_function *machine = cfun->machine;
10596 fprintf (file, "\t.endp\n\n\t.psect\t%s%s,data\n", user_label_prefix,
10597 unicosmk_ssib_name ());
10599 /* Some required stuff and the function name length. */
10601 len = strlen (fnname);
10602 fprintf (file, "\t.quad\t^X20008%2.2X28\n", len);
10605 ??? We don't do that yet. */
10607 fputs ("\t.quad\t0\n", file);
10609 /* Function address. */
10611 fputs ("\t.quad\t", file);
10612 assemble_name (file, fnname);
10615 fputs ("\t.quad\t0\n", file);
10616 fputs ("\t.quad\t0\n", file);
10619 ??? We do it the same way Cray CC does it but this could be
10622 for( i = 0; i < len; i++ )
10623 fprintf (file, "\t.byte\t%d\n", (int)(fnname[i]));
10624 if( (len % 8) == 0 )
10625 fputs ("\t.quad\t0\n", file);
10627 fprintf (file, "\t.bits\t%d : 0\n", (8 - (len % 8))*8);
10629 /* All call information words used in the function. */
10631 for (x = machine->first_ciw; x; x = XEXP (x, 1))
10634 #if HOST_BITS_PER_WIDE_INT == 32
10635 fprintf (file, "\t.quad\t" HOST_WIDE_INT_PRINT_DOUBLE_HEX "\n",
10636 CONST_DOUBLE_HIGH (ciw), CONST_DOUBLE_LOW (ciw));
10638 fprintf (file, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX "\n", INTVAL (ciw));
10643 /* Add a call information word (CIW) to the list of the current function's
10644 CIWs and return its index.
10646 X is a CONST_INT or CONST_DOUBLE representing the CIW. */
10649 unicosmk_add_call_info_word (rtx x)
10652 struct machine_function *machine = cfun->machine;
10654 node = gen_rtx_EXPR_LIST (VOIDmode, x, NULL_RTX);
10655 if (machine->first_ciw == NULL_RTX)
10656 machine->first_ciw = node;
10658 XEXP (machine->last_ciw, 1) = node;
10660 machine->last_ciw = node;
10661 ++machine->ciw_count;
10663 return GEN_INT (machine->ciw_count
10664 + strlen (current_function_name ())/8 + 5);
10667 /* The Cray assembler doesn't accept extern declarations for symbols which
10668 are defined in the same file. We have to keep track of all global
10669 symbols which are referenced and/or defined in a source file and output
10670 extern declarations for those which are referenced but not defined at
10671 the end of file. */
10673 /* List of identifiers for which an extern declaration might have to be
10675 /* FIXME: needs to use GC, so it can be saved and restored for PCH. */
10677 struct unicosmk_extern_list
10679 struct unicosmk_extern_list *next;
10683 static struct unicosmk_extern_list *unicosmk_extern_head = 0;
10685 /* Output extern declarations which are required for every asm file. */
10688 unicosmk_output_default_externs (FILE *file)
10690 static const char *const externs[] =
10691 { "__T3E_MISMATCH" };
10696 n = ARRAY_SIZE (externs);
10698 for (i = 0; i < n; i++)
10699 fprintf (file, "\t.extern\t%s\n", externs[i]);
10702 /* Output extern declarations for global symbols which are have been
10703 referenced but not defined. */
10706 unicosmk_output_externs (FILE *file)
10708 struct unicosmk_extern_list *p;
10709 const char *real_name;
10713 len = strlen (user_label_prefix);
10714 for (p = unicosmk_extern_head; p != 0; p = p->next)
10716 /* We have to strip the encoding and possibly remove user_label_prefix
10717 from the identifier in order to handle -fleading-underscore and
10718 explicit asm names correctly (cf. gcc.dg/asm-names-1.c). */
10719 real_name = default_strip_name_encoding (p->name);
10720 if (len && p->name[0] == '*'
10721 && !memcmp (real_name, user_label_prefix, len))
10724 name_tree = get_identifier (real_name);
10725 if (! TREE_ASM_WRITTEN (name_tree))
10727 TREE_ASM_WRITTEN (name_tree) = 1;
10728 fputs ("\t.extern\t", file);
10729 assemble_name (file, p->name);
10735 /* Record an extern. */
10738 unicosmk_add_extern (const char *name)
10740 struct unicosmk_extern_list *p;
10742 p = (struct unicosmk_extern_list *)
10743 xmalloc (sizeof (struct unicosmk_extern_list));
10744 p->next = unicosmk_extern_head;
10746 unicosmk_extern_head = p;
10749 /* The Cray assembler generates incorrect code if identifiers which
10750 conflict with register names are used as instruction operands. We have
10751 to replace such identifiers with DEX expressions. */
10753 /* Structure to collect identifiers which have been replaced by DEX
10755 /* FIXME: needs to use GC, so it can be saved and restored for PCH. */
10757 struct unicosmk_dex {
10758 struct unicosmk_dex *next;
10762 /* List of identifiers which have been replaced by DEX expressions. The DEX
10763 number is determined by the position in the list. */
10765 static struct unicosmk_dex *unicosmk_dex_list = NULL;
10767 /* The number of elements in the DEX list. */
10769 static int unicosmk_dex_count = 0;
10771 /* Check if NAME must be replaced by a DEX expression. */
10774 unicosmk_special_name (const char *name)
10776 if (name[0] == '*')
10779 if (name[0] == '$')
10782 if (name[0] != 'r' && name[0] != 'f' && name[0] != 'R' && name[0] != 'F')
10787 case '1': case '2':
10788 return (name[2] == '\0' || (ISDIGIT (name[2]) && name[3] == '\0'));
10791 return (name[2] == '\0'
10792 || ((name[2] == '0' || name[2] == '1') && name[3] == '\0'));
10795 return (ISDIGIT (name[1]) && name[2] == '\0');
10799 /* Return the DEX number if X must be replaced by a DEX expression and 0
10803 unicosmk_need_dex (rtx x)
10805 struct unicosmk_dex *dex;
10809 if (GET_CODE (x) != SYMBOL_REF)
10813 if (! unicosmk_special_name (name))
10816 i = unicosmk_dex_count;
10817 for (dex = unicosmk_dex_list; dex; dex = dex->next)
10819 if (! strcmp (name, dex->name))
10824 dex = (struct unicosmk_dex *) xmalloc (sizeof (struct unicosmk_dex));
10826 dex->next = unicosmk_dex_list;
10827 unicosmk_dex_list = dex;
10829 ++unicosmk_dex_count;
10830 return unicosmk_dex_count;
10833 /* Output the DEX definitions for this file. */
10836 unicosmk_output_dex (FILE *file)
10838 struct unicosmk_dex *dex;
10841 if (unicosmk_dex_list == NULL)
10844 fprintf (file, "\t.dexstart\n");
10846 i = unicosmk_dex_count;
10847 for (dex = unicosmk_dex_list; dex; dex = dex->next)
10849 fprintf (file, "\tDEX (%d) = ", i);
10850 assemble_name (file, dex->name);
10855 fprintf (file, "\t.dexend\n");
10858 /* Output text that to appear at the beginning of an assembler file. */
10861 unicosmk_file_start (void)
10865 fputs ("\t.ident\t", asm_out_file);
10866 unicosmk_output_module_name (asm_out_file);
10867 fputs ("\n\n", asm_out_file);
10869 /* The Unicos/Mk assembler uses different register names. Instead of trying
10870 to support them, we simply use micro definitions. */
10872 /* CAM has different register names: rN for the integer register N and fN
10873 for the floating-point register N. Instead of trying to use these in
10874 alpha.md, we define the symbols $N and $fN to refer to the appropriate
10877 for (i = 0; i < 32; ++i)
10878 fprintf (asm_out_file, "$%d <- r%d\n", i, i);
10880 for (i = 0; i < 32; ++i)
10881 fprintf (asm_out_file, "$f%d <- f%d\n", i, i);
10883 putc ('\n', asm_out_file);
10885 /* The .align directive fill unused space with zeroes which does not work
10886 in code sections. We define the macro 'gcc@code@align' which uses nops
10887 instead. Note that it assumes that code sections always have the
10888 biggest possible alignment since . refers to the current offset from
10889 the beginning of the section. */
10891 fputs ("\t.macro gcc@code@align n\n", asm_out_file);
10892 fputs ("gcc@n@bytes = 1 << n\n", asm_out_file);
10893 fputs ("gcc@here = . % gcc@n@bytes\n", asm_out_file);
10894 fputs ("\t.if ne, gcc@here, 0\n", asm_out_file);
10895 fputs ("\t.repeat (gcc@n@bytes - gcc@here) / 4\n", asm_out_file);
10896 fputs ("\tbis r31,r31,r31\n", asm_out_file);
10897 fputs ("\t.endr\n", asm_out_file);
10898 fputs ("\t.endif\n", asm_out_file);
10899 fputs ("\t.endm gcc@code@align\n\n", asm_out_file);
10901 /* Output extern declarations which should always be visible. */
10902 unicosmk_output_default_externs (asm_out_file);
10904 /* Open a dummy section. We always need to be inside a section for the
10905 section-switching code to work correctly.
10906 ??? This should be a module id or something like that. I still have to
10907 figure out what the rules for those are. */
10908 fputs ("\n\t.psect\t$SG00000,data\n", asm_out_file);
10911 /* Output text to appear at the end of an assembler file. This includes all
10912 pending extern declarations and DEX expressions. */
10915 unicosmk_file_end (void)
10917 fputs ("\t.endp\n\n", asm_out_file);
10919 /* Output all pending externs. */
10921 unicosmk_output_externs (asm_out_file);
10923 /* Output dex definitions used for functions whose names conflict with
10926 unicosmk_output_dex (asm_out_file);
10928 fputs ("\t.end\t", asm_out_file);
10929 unicosmk_output_module_name (asm_out_file);
10930 putc ('\n', asm_out_file);
10936 unicosmk_output_deferred_case_vectors (FILE *file ATTRIBUTE_UNUSED)
10940 unicosmk_gen_dsib (unsigned long *imaskP ATTRIBUTE_UNUSED)
10944 unicosmk_output_ssib (FILE * file ATTRIBUTE_UNUSED,
10945 const char * fnname ATTRIBUTE_UNUSED)
10949 unicosmk_add_call_info_word (rtx x ATTRIBUTE_UNUSED)
10955 unicosmk_need_dex (rtx x ATTRIBUTE_UNUSED)
10960 #endif /* TARGET_ABI_UNICOSMK */
10963 alpha_init_libfuncs (void)
10965 if (TARGET_ABI_UNICOSMK)
10967 /* Prevent gcc from generating calls to __divsi3. */
10968 set_optab_libfunc (sdiv_optab, SImode, 0);
10969 set_optab_libfunc (udiv_optab, SImode, 0);
10971 /* Use the functions provided by the system library
10972 for DImode integer division. */
10973 set_optab_libfunc (sdiv_optab, DImode, "$sldiv");
10974 set_optab_libfunc (udiv_optab, DImode, "$uldiv");
10976 else if (TARGET_ABI_OPEN_VMS)
10978 /* Use the VMS runtime library functions for division and
10980 set_optab_libfunc (sdiv_optab, SImode, "OTS$DIV_I");
10981 set_optab_libfunc (sdiv_optab, DImode, "OTS$DIV_L");
10982 set_optab_libfunc (udiv_optab, SImode, "OTS$DIV_UI");
10983 set_optab_libfunc (udiv_optab, DImode, "OTS$DIV_UL");
10984 set_optab_libfunc (smod_optab, SImode, "OTS$REM_I");
10985 set_optab_libfunc (smod_optab, DImode, "OTS$REM_L");
10986 set_optab_libfunc (umod_optab, SImode, "OTS$REM_UI");
10987 set_optab_libfunc (umod_optab, DImode, "OTS$REM_UL");
10988 abort_libfunc = init_one_libfunc ("decc$abort");
10989 memcmp_libfunc = init_one_libfunc ("decc$memcmp");
10990 #ifdef MEM_LIBFUNCS_INIT
10997 /* Initialize the GCC target structure. */
10998 #if TARGET_ABI_OPEN_VMS
10999 # undef TARGET_ATTRIBUTE_TABLE
11000 # define TARGET_ATTRIBUTE_TABLE vms_attribute_table
11001 # undef TARGET_CAN_ELIMINATE
11002 # define TARGET_CAN_ELIMINATE alpha_vms_can_eliminate
11005 #undef TARGET_IN_SMALL_DATA_P
11006 #define TARGET_IN_SMALL_DATA_P alpha_in_small_data_p
11008 #if TARGET_ABI_UNICOSMK
11009 # undef TARGET_INSERT_ATTRIBUTES
11010 # define TARGET_INSERT_ATTRIBUTES unicosmk_insert_attributes
11011 # undef TARGET_SECTION_TYPE_FLAGS
11012 # define TARGET_SECTION_TYPE_FLAGS unicosmk_section_type_flags
11013 # undef TARGET_ASM_UNIQUE_SECTION
11014 # define TARGET_ASM_UNIQUE_SECTION unicosmk_unique_section
11015 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
11016 #define TARGET_ASM_FUNCTION_RODATA_SECTION default_no_function_rodata_section
11017 # undef TARGET_ASM_GLOBALIZE_LABEL
11018 # define TARGET_ASM_GLOBALIZE_LABEL hook_void_FILEptr_constcharptr
11019 # undef TARGET_MUST_PASS_IN_STACK
11020 # define TARGET_MUST_PASS_IN_STACK unicosmk_must_pass_in_stack
11023 #undef TARGET_ASM_ALIGNED_HI_OP
11024 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
11025 #undef TARGET_ASM_ALIGNED_DI_OP
11026 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
11028 /* Default unaligned ops are provided for ELF systems. To get unaligned
11029 data for non-ELF systems, we have to turn off auto alignment. */
11030 #if !defined (OBJECT_FORMAT_ELF) || TARGET_ABI_OPEN_VMS
11031 #undef TARGET_ASM_UNALIGNED_HI_OP
11032 #define TARGET_ASM_UNALIGNED_HI_OP "\t.align 0\n\t.word\t"
11033 #undef TARGET_ASM_UNALIGNED_SI_OP
11034 #define TARGET_ASM_UNALIGNED_SI_OP "\t.align 0\n\t.long\t"
11035 #undef TARGET_ASM_UNALIGNED_DI_OP
11036 #define TARGET_ASM_UNALIGNED_DI_OP "\t.align 0\n\t.quad\t"
11039 #ifdef OBJECT_FORMAT_ELF
11040 #undef TARGET_ASM_RELOC_RW_MASK
11041 #define TARGET_ASM_RELOC_RW_MASK alpha_elf_reloc_rw_mask
11042 #undef TARGET_ASM_SELECT_RTX_SECTION
11043 #define TARGET_ASM_SELECT_RTX_SECTION alpha_elf_select_rtx_section
11044 #undef TARGET_SECTION_TYPE_FLAGS
11045 #define TARGET_SECTION_TYPE_FLAGS alpha_elf_section_type_flags
11048 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
11049 #define TARGET_ASM_FUNCTION_END_PROLOGUE alpha_output_function_end_prologue
11051 #undef TARGET_INIT_LIBFUNCS
11052 #define TARGET_INIT_LIBFUNCS alpha_init_libfuncs
11054 #undef TARGET_LEGITIMIZE_ADDRESS
11055 #define TARGET_LEGITIMIZE_ADDRESS alpha_legitimize_address
11057 #if TARGET_ABI_UNICOSMK
11058 #undef TARGET_ASM_FILE_START
11059 #define TARGET_ASM_FILE_START unicosmk_file_start
11060 #undef TARGET_ASM_FILE_END
11061 #define TARGET_ASM_FILE_END unicosmk_file_end
11063 #undef TARGET_ASM_FILE_START
11064 #define TARGET_ASM_FILE_START alpha_file_start
11065 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
11066 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
11069 #undef TARGET_SCHED_ADJUST_COST
11070 #define TARGET_SCHED_ADJUST_COST alpha_adjust_cost
11071 #undef TARGET_SCHED_ISSUE_RATE
11072 #define TARGET_SCHED_ISSUE_RATE alpha_issue_rate
11073 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
11074 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
11075 alpha_multipass_dfa_lookahead
11077 #undef TARGET_HAVE_TLS
11078 #define TARGET_HAVE_TLS HAVE_AS_TLS
11080 #undef TARGET_INIT_BUILTINS
11081 #define TARGET_INIT_BUILTINS alpha_init_builtins
11082 #undef TARGET_EXPAND_BUILTIN
11083 #define TARGET_EXPAND_BUILTIN alpha_expand_builtin
11084 #undef TARGET_FOLD_BUILTIN
11085 #define TARGET_FOLD_BUILTIN alpha_fold_builtin
11087 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
11088 #define TARGET_FUNCTION_OK_FOR_SIBCALL alpha_function_ok_for_sibcall
11089 #undef TARGET_CANNOT_COPY_INSN_P
11090 #define TARGET_CANNOT_COPY_INSN_P alpha_cannot_copy_insn_p
11091 #undef TARGET_CANNOT_FORCE_CONST_MEM
11092 #define TARGET_CANNOT_FORCE_CONST_MEM alpha_cannot_force_const_mem
11095 #undef TARGET_ASM_OUTPUT_MI_THUNK
11096 #define TARGET_ASM_OUTPUT_MI_THUNK alpha_output_mi_thunk_osf
11097 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
11098 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
11099 #undef TARGET_STDARG_OPTIMIZE_HOOK
11100 #define TARGET_STDARG_OPTIMIZE_HOOK alpha_stdarg_optimize_hook
11103 #undef TARGET_RTX_COSTS
11104 #define TARGET_RTX_COSTS alpha_rtx_costs
11105 #undef TARGET_ADDRESS_COST
11106 #define TARGET_ADDRESS_COST hook_int_rtx_bool_0
11108 #undef TARGET_MACHINE_DEPENDENT_REORG
11109 #define TARGET_MACHINE_DEPENDENT_REORG alpha_reorg
11111 #undef TARGET_PROMOTE_FUNCTION_MODE
11112 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
11113 #undef TARGET_PROMOTE_PROTOTYPES
11114 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_false
11115 #undef TARGET_RETURN_IN_MEMORY
11116 #define TARGET_RETURN_IN_MEMORY alpha_return_in_memory
11117 #undef TARGET_PASS_BY_REFERENCE
11118 #define TARGET_PASS_BY_REFERENCE alpha_pass_by_reference
11119 #undef TARGET_SETUP_INCOMING_VARARGS
11120 #define TARGET_SETUP_INCOMING_VARARGS alpha_setup_incoming_varargs
11121 #undef TARGET_STRICT_ARGUMENT_NAMING
11122 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
11123 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
11124 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
11125 #undef TARGET_SPLIT_COMPLEX_ARG
11126 #define TARGET_SPLIT_COMPLEX_ARG alpha_split_complex_arg
11127 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
11128 #define TARGET_GIMPLIFY_VA_ARG_EXPR alpha_gimplify_va_arg
11129 #undef TARGET_ARG_PARTIAL_BYTES
11130 #define TARGET_ARG_PARTIAL_BYTES alpha_arg_partial_bytes
11131 #undef TARGET_TRAMPOLINE_INIT
11132 #define TARGET_TRAMPOLINE_INIT alpha_trampoline_init
11134 #undef TARGET_SECONDARY_RELOAD
11135 #define TARGET_SECONDARY_RELOAD alpha_secondary_reload
11137 #undef TARGET_SCALAR_MODE_SUPPORTED_P
11138 #define TARGET_SCALAR_MODE_SUPPORTED_P alpha_scalar_mode_supported_p
11139 #undef TARGET_VECTOR_MODE_SUPPORTED_P
11140 #define TARGET_VECTOR_MODE_SUPPORTED_P alpha_vector_mode_supported_p
11142 #undef TARGET_BUILD_BUILTIN_VA_LIST
11143 #define TARGET_BUILD_BUILTIN_VA_LIST alpha_build_builtin_va_list
11145 #undef TARGET_EXPAND_BUILTIN_VA_START
11146 #define TARGET_EXPAND_BUILTIN_VA_START alpha_va_start
11148 /* The Alpha architecture does not require sequential consistency. See
11149 http://www.cs.umd.edu/~pugh/java/memoryModel/AlphaReordering.html
11150 for an example of how it can be violated in practice. */
11151 #undef TARGET_RELAXED_ORDERING
11152 #define TARGET_RELAXED_ORDERING true
11154 #undef TARGET_DEFAULT_TARGET_FLAGS
11155 #define TARGET_DEFAULT_TARGET_FLAGS \
11156 (TARGET_DEFAULT | TARGET_CPU_DEFAULT | TARGET_DEFAULT_EXPLICIT_RELOCS)
11157 #undef TARGET_HANDLE_OPTION
11158 #define TARGET_HANDLE_OPTION alpha_handle_option
11160 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
11161 #undef TARGET_MANGLE_TYPE
11162 #define TARGET_MANGLE_TYPE alpha_mangle_type
11165 #undef TARGET_LEGITIMATE_ADDRESS_P
11166 #define TARGET_LEGITIMATE_ADDRESS_P alpha_legitimate_address_p
11168 struct gcc_target targetm = TARGET_INITIALIZER;
11171 #include "gt-alpha.h"