1 /* Definitions of target machine for GNU compiler, for AMD Am29000 CPU.
2 Copyright (C) 1988, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 2000, 2001, 2002 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@nyu.edu)
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
24 /* Names to predefine in the preprocessor for this target machine. */
26 #define CPP_PREDEFINES "-D_AM29K -D_AM29000 -D_EPI -Acpu=a29k -Amachine=a29k"
28 /* Print subsidiary information on the compiler version in use. */
29 #define TARGET_VERSION
31 /* Pass -w to assembler. */
34 /* Run-time compilation parameters selecting different hardware subsets. */
36 extern int target_flags;
38 /* Macro to define tables used to set the flags.
39 This is a list in braces of pairs in braces,
40 each pair being { "NAME", VALUE }
41 where VALUE is the bits to set or minus the bits to clear.
42 An empty string NAME is used to identify the default VALUE. */
44 /* This means that the DW bit will be enabled, to allow direct loads
47 #define TARGET_DW_ENABLE (target_flags & 1)
49 /* This means that the external hardware does supports byte writes. */
51 #define TARGET_BYTE_WRITES (target_flags & 2)
53 /* This means that a "small memory model" has been selected where all
54 function addresses are known to be within 256K. This allows CALL to be
57 #define TARGET_SMALL_MEMORY (target_flags & 4)
59 /* This means that we must always used on indirect call, even when
60 calling a function in the same file, since the file might be > 256KB. */
62 #define TARGET_LARGE_MEMORY (target_flags & 8)
64 /* This means that we are compiling for a 29050. */
66 #define TARGET_29050 (target_flags & 16)
68 /* This means that we are compiling for the kernel which means that we use
69 gr64-gr95 instead of gr96-126. */
71 #define TARGET_KERNEL_REGISTERS (target_flags & 32)
73 /* This means that a call to "__msp_check" should be inserted after each stack
74 adjustment to check for stack overflow. */
76 #define TARGET_STACK_CHECK (target_flags & 64)
78 /* This handles 29k processors which cannot handle the separation
79 of a mtsrim insns and a storem insn (most 29000 chips to date, but
82 #define TARGET_NO_STOREM_BUG (target_flags & 128)
84 /* This forces the compiler not to use incoming argument registers except
85 for copying out arguments. It helps detect problems when a function is
86 called with fewer arguments than it is declared with. */
88 #define TARGET_NO_REUSE_ARGS (target_flags & 256)
90 /* This means that neither builtin nor emulated float operations are
91 available, and that GCC should generate libcalls instead. */
93 #define TARGET_SOFT_FLOAT (target_flags & 512)
95 /* This means that we should not emit the multm or mutmu instructions
96 that some embedded systems' trap handlers don't support. */
98 #define TARGET_MULTM ((target_flags & 1024) == 0)
100 #define TARGET_SWITCHES \
101 { {"dw", 1, N_("Generate code assuming DW bit is set")}, \
102 {"ndw", -1, N_("Generate code assuming DW bit is not set")}, \
103 {"bw", 2, N_("Generate code using byte writes")}, \
104 {"nbw", - (1|2), N_("Do not generate byte writes")}, \
105 {"small", 4, N_("Use small memory model")}, \
106 {"normal", - (4|8), N_("Use normal memory model")}, \
107 {"large", 8, N_("Use large memory model")}, \
108 {"29050", 16+128, N_("Generate 29050 code")}, \
109 {"29000", -16, N_("Generate 29000 code")}, \
110 {"kernel-registers", 32, N_("Use kernel global registers")}, \
111 {"user-registers", -32, N_("Use user global registers")}, \
112 {"stack-check", 64, N_("Emit stack checking code")}, \
113 {"no-stack-check", - 74, N_("Do not emit stack checking code")}, \
114 {"storem-bug", -128, N_("Work around storem hardware bug")}, \
115 {"no-storem-bug", 128, N_("Do not work around storem hardware bug")}, \
116 {"reuse-arg-regs", -256, N_("Store locals in argument registers")}, \
117 {"no-reuse-arg-regs", 256, N_("Do not store locals in arg registers")}, \
118 {"soft-float", 512, N_("Use software floating point")}, \
119 {"no-multm", 1024, N_("Do not generate multm instructions")}, \
120 {"", TARGET_DEFAULT, NULL}}
122 #define TARGET_DEFAULT 3
124 /* Show we can debug even without a frame pointer. */
125 #define CAN_DEBUG_WITHOUT_FP
127 /* target machine storage layout */
129 /* Define the types for size_t, ptrdiff_t, and wchar_t. These are the
130 same as those used by EPI. The type for wchar_t does not make much
131 sense, but is what is used. */
133 #define SIZE_TYPE "unsigned int"
134 #define PTRDIFF_TYPE "int"
135 #define WCHAR_TYPE "char"
136 #define WCHAR_TYPE_SIZE BITS_PER_UNIT
138 /* Define this macro if it is advisable to hold scalars in registers
139 in a wider mode than that declared by the program. In such cases,
140 the value is constrained to be within the bounds of the declared
141 type, but kept valid in the wider mode. The signedness of the
142 extension may differ from that of the type. */
144 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
145 if (GET_MODE_CLASS (MODE) == MODE_INT \
146 && GET_MODE_SIZE (MODE) < 4) \
149 /* Define this if most significant bit is lowest numbered
150 in instructions that operate on numbered bit-fields.
151 This is arbitrary on the 29k since it has no actual bit-field insns.
152 It is better to define this as TRUE because BYTES_BIG_ENDIAN is TRUE
153 and we want to be able to convert BP position to bit position with
155 #define BITS_BIG_ENDIAN 1
157 /* Define this if most significant byte of a word is the lowest numbered.
158 This is true on 29k. */
159 #define BYTES_BIG_ENDIAN 1
161 /* Define this if most significant word of a multiword number is lowest
164 For 29k we can decide arbitrarily since there are no machine instructions
165 for them. Might as well be consistent with bytes. */
166 #define WORDS_BIG_ENDIAN 1
168 /* Width of a word, in units (bytes). */
169 #define UNITS_PER_WORD 4
171 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
172 #define PARM_BOUNDARY 32
174 /* Boundary (in *bits*) on which stack pointer should be aligned. */
175 #define STACK_BOUNDARY 64
177 /* Allocation boundary (in *bits*) for the code of a function. */
178 #define FUNCTION_BOUNDARY 32
180 /* Alignment of field after `int : 0' in a structure. */
181 #define EMPTY_FIELD_BOUNDARY 32
183 /* Every structure's size must be a multiple of this. */
184 #define STRUCTURE_SIZE_BOUNDARY 8
186 /* A bitfield declared as `int' forces `int' alignment for the struct. */
187 #define PCC_BITFIELD_TYPE_MATTERS 1
189 /* No data type wants to be aligned rounder than this. */
190 #define BIGGEST_ALIGNMENT 32
192 /* Make strings word-aligned so strcpy from constants will be faster. */
193 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
194 (TREE_CODE (EXP) == STRING_CST \
195 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
197 /* Make arrays of chars word-aligned for the same reasons. */
198 #define DATA_ALIGNMENT(TYPE, ALIGN) \
199 (TREE_CODE (TYPE) == ARRAY_TYPE \
200 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
201 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
203 /* Set this non-zero if move instructions will actually fail to work
204 when given unaligned data. */
205 #define STRICT_ALIGNMENT 0
207 /* Set this non-zero if unaligned move instructions are extremely slow.
209 On the 29k, they trap. */
210 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
212 /* Standard register usage. */
214 /* Number of actual hardware registers.
215 The hardware registers are assigned numbers for the compiler
216 from 0 to just below FIRST_PSEUDO_REGISTER.
217 All registers that the compiler knows about must be given numbers,
218 even those that are not normally considered general registers.
220 29k has 256 registers, of which 62 are not defined. gr0 and gr1 are
221 not produced in generated RTL so we can start at gr96, and call it
224 So 0-31 are gr96-gr127, lr0-lr127 are 32-159. To represent the input
225 arguments, whose register numbers we won't know until we are done,
226 use register 160-175. They cannot be modified. Similarly, 176 is used
227 for the frame pointer. It is assigned the last local register number
228 once the number of registers used is known.
230 We use 177, 178, 179, and 180 for the special registers BP, FC, CR, and Q,
231 respectively. Registers 181 through 199 are used for the other special
232 registers that may be used by the programmer, but are never used by the
235 Registers 200-203 are the four floating-point accumulator register in
238 Registers 204-235 are the 32 global registers for kernel mode when
239 -mkernel-registers is not specified, and the 32 global user registers
242 When -mkernel-registers is specified, we still use the same register
243 map but change the names so 0-31 print as gr64-gr95. */
245 #define FIRST_PSEUDO_REGISTER 236
247 /* Because of the large number of registers on the 29k, we define macros
248 to refer to each group of registers and then define the number for some
249 registers used in the calling sequence. */
251 #define R_GR(N) ((N) - 96) /* gr96 is register number 0 */
252 #define R_LR(N) ((N) + 32) /* lr0 is register number 32 */
253 #define R_FP 176 /* frame pointer is register 176 */
254 #define R_AR(N) ((N) + 160) /* first incoming arg reg is 160 */
255 #define R_KR(N) ((N) + 204) /* kernel registers (gr64 to gr95) */
257 /* Define the numbers of the special registers. */
263 /* These special registers are not used by the compiler, but may be referenced
264 by the programmer via asm declarations. */
286 /* Define the number for floating-point accumulator N. */
287 #define R_ACU(N) ((N) + 200)
289 /* Now define the registers used in the calling sequence. */
290 #define R_TAV R_GR (121)
291 #define R_TPC R_GR (122)
292 #define R_LRP R_GR (123)
293 #define R_SLP R_GR (124)
294 #define R_MSP R_GR (125)
295 #define R_RAB R_GR (126)
296 #define R_RFB R_GR (127)
298 /* 1 for registers that have pervasive standard uses
299 and are not available for the register allocator. */
301 #define FIXED_REGISTERS \
302 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
303 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, \
304 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
305 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
306 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
307 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
308 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
309 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
310 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
311 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
312 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
313 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
314 1, 1, 1, 1, 1, 1, 1, 1, \
316 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
317 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }
319 /* 1 for registers not available across function calls.
320 These must include the FIXED_REGISTERS and also any
321 registers that can be used without being saved.
322 The latter must include the registers where values are returned
323 and the register where structure-value addresses are passed.
324 Aside from that, you can include as many other registers as you like. */
325 #define CALL_USED_REGISTERS \
326 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
327 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
328 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
329 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
330 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
331 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
332 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
333 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
334 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
335 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
336 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
337 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
338 1, 1, 1, 1, 1, 1, 1, 1, \
340 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
341 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }
343 /* List the order in which to allocate registers. Each register must be
344 listed once, even those in FIXED_REGISTERS.
346 We allocate in the following order:
347 gr116-gr120 (not used for anything but temps)
348 gr96-gr111 (function return values, reverse order)
349 argument registers (160-175)
350 lr0-lr127 (locals, saved)
351 acc3-0 (acc0 special)
354 #define REG_ALLOC_ORDER \
355 {R_GR (116), R_GR (117), R_GR (118), R_GR (119), R_GR (120), \
356 R_GR (111), R_GR (110), R_GR (109), R_GR (108), R_GR (107), \
357 R_GR (106), R_GR (105), R_GR (104), R_GR (103), R_GR (102), \
358 R_GR (101), R_GR (100), R_GR (99), R_GR (98), R_GR (97), R_GR (96), \
359 R_AR (0), R_AR (1), R_AR (2), R_AR (3), R_AR (4), R_AR (5), \
360 R_AR (6), R_AR (7), R_AR (8), R_AR (9), R_AR (10), R_AR (11), \
361 R_AR (12), R_AR (13), R_AR (14), R_AR (15), \
362 R_LR (0), R_LR (1), R_LR (2), R_LR (3), R_LR (4), R_LR (5), \
363 R_LR (6), R_LR (7), R_LR (8), R_LR (9), R_LR (10), R_LR (11), \
364 R_LR (12), R_LR (13), R_LR (14), R_LR (15), R_LR (16), R_LR (17), \
365 R_LR (18), R_LR (19), R_LR (20), R_LR (21), R_LR (22), R_LR (23), \
366 R_LR (24), R_LR (25), R_LR (26), R_LR (27), R_LR (28), R_LR (29), \
367 R_LR (30), R_LR (31), R_LR (32), R_LR (33), R_LR (34), R_LR (35), \
368 R_LR (36), R_LR (37), R_LR (38), R_LR (39), R_LR (40), R_LR (41), \
369 R_LR (42), R_LR (43), R_LR (44), R_LR (45), R_LR (46), R_LR (47), \
370 R_LR (48), R_LR (49), R_LR (50), R_LR (51), R_LR (52), R_LR (53), \
371 R_LR (54), R_LR (55), R_LR (56), R_LR (57), R_LR (58), R_LR (59), \
372 R_LR (60), R_LR (61), R_LR (62), R_LR (63), R_LR (64), R_LR (65), \
373 R_LR (66), R_LR (67), R_LR (68), R_LR (69), R_LR (70), R_LR (71), \
374 R_LR (72), R_LR (73), R_LR (74), R_LR (75), R_LR (76), R_LR (77), \
375 R_LR (78), R_LR (79), R_LR (80), R_LR (81), R_LR (82), R_LR (83), \
376 R_LR (84), R_LR (85), R_LR (86), R_LR (87), R_LR (88), R_LR (89), \
377 R_LR (90), R_LR (91), R_LR (92), R_LR (93), R_LR (94), R_LR (95), \
378 R_LR (96), R_LR (97), R_LR (98), R_LR (99), R_LR (100), R_LR (101), \
379 R_LR (102), R_LR (103), R_LR (104), R_LR (105), R_LR (106), \
380 R_LR (107), R_LR (108), R_LR (109), R_LR (110), R_LR (111), \
381 R_LR (112), R_LR (113), R_LR (114), R_LR (115), R_LR (116), \
382 R_LR (117), R_LR (118), R_LR (119), R_LR (120), R_LR (121), \
383 R_LR (122), R_LR (123), R_LR (124), R_LR (124), R_LR (126), \
385 R_ACU (3), R_ACU (2), R_ACU (1), R_ACU (0), \
386 R_GR (112), R_GR (113), R_GR (114), R_GR (115), R_GR (121), \
387 R_GR (122), R_GR (123), R_GR (124), R_GR (125), R_GR (126), \
389 R_FP, R_BP, R_FC, R_CR, R_Q, \
390 R_VAB, R_OPS, R_CPS, R_CFG, R_CHA, R_CHD, R_CHC, R_RBP, R_TMC, \
391 R_TMR, R_PC0, R_PC1, R_PC2, R_MMU, R_LRU, R_FPE, R_INT, R_FPS, \
393 R_KR (0), R_KR (1), R_KR (2), R_KR (3), R_KR (4), R_KR (5), \
394 R_KR (6), R_KR (7), R_KR (8), R_KR (9), R_KR (10), R_KR (11), \
395 R_KR (12), R_KR (13), R_KR (14), R_KR (15), R_KR (16), R_KR (17), \
396 R_KR (18), R_KR (19), R_KR (20), R_KR (21), R_KR (22), R_KR (23), \
397 R_KR (24), R_KR (25), R_KR (26), R_KR (27), R_KR (28), R_KR (29), \
398 R_KR (30), R_KR (31) }
400 /* Return number of consecutive hard regs needed starting at reg REGNO
401 to hold something of mode MODE.
402 This is ordinarily the length in words of a value of mode MODE
403 but can be less for certain modes in special long registers. */
405 #define HARD_REGNO_NREGS(REGNO, MODE) \
406 ((REGNO) >= R_ACU (0) && (REGNO) <= R_ACU (3)? 1 \
407 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
409 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
410 On 29k, the cpu registers can hold any mode. But a double-precision
411 floating-point value should start at an even register. The special
412 registers cannot hold floating-point values, BP, CR, and FC cannot
413 hold integer or floating-point values, and the accumulators cannot
416 DImode and larger values should start at an even register just like
417 DFmode values, even though the instruction set doesn't require it, in order
418 to prevent reload from aborting due to a modes_equiv_for_class_p failure.
420 (I'd like to use the "?:" syntax to make this more readable, but Sun's
421 compiler doesn't seem to accept it.) */
422 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
423 (((REGNO) >= R_ACU (0) && (REGNO) <= R_ACU (3) \
424 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
425 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)) \
426 || ((REGNO) >= R_BP && (REGNO) <= R_CR \
427 && GET_MODE_CLASS (MODE) == MODE_PARTIAL_INT) \
428 || ((REGNO) >= R_Q && (REGNO) < R_ACU (0) \
429 && GET_MODE_CLASS (MODE) != MODE_FLOAT \
430 && GET_MODE_CLASS (MODE) != MODE_COMPLEX_FLOAT) \
431 || (((REGNO) < R_BP || (REGNO) >= R_KR (0)) \
432 && ((((REGNO) & 1) == 0) \
433 || GET_MODE_UNIT_SIZE (MODE) <= UNITS_PER_WORD)))
435 /* Value is 1 if it is a good idea to tie two pseudo registers
436 when one has mode MODE1 and one has mode MODE2.
437 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
438 for any hard reg, then this must be 0 for correct output.
440 On the 29k, normally we'd just have problems with DFmode because of the
441 even alignment. However, we also have to be a bit concerned about
442 the special register's restriction to non-floating and the floating-point
443 accumulator's restriction to only floating. This probably won't
444 cause any great inefficiencies in practice. */
446 #define MODES_TIEABLE_P(MODE1, MODE2) \
447 ((MODE1) == (MODE2) \
448 || (GET_MODE_CLASS (MODE1) == MODE_INT \
449 && GET_MODE_CLASS (MODE2) == MODE_INT))
451 /* Specify the registers used for certain standard purposes.
452 The values of these macros are register numbers. */
454 /* 29k pc isn't overloaded on a register that the compiler knows about. */
455 /* #define PC_REGNUM */
457 /* Register to use for pushing function arguments. */
458 #define STACK_POINTER_REGNUM R_GR (125)
460 /* Base register for access to local variables of the function. */
461 #define FRAME_POINTER_REGNUM R_FP
463 /* Value should be nonzero if functions must have frame pointers.
464 Zero means the frame pointer need not be set up (and parms
465 may be accessed via the stack pointer) in functions that seem suitable.
466 This is computed in `reload', in reload1.c. */
467 #define FRAME_POINTER_REQUIRED 0
469 /* Base register for access to arguments of the function. */
470 #define ARG_POINTER_REGNUM R_FP
472 /* Register in which static-chain is passed to a function. */
473 #define STATIC_CHAIN_REGNUM R_SLP
475 /* Register in which address to store a structure value
476 is passed to a function. */
477 #define STRUCT_VALUE_REGNUM R_LRP
479 /* Define the classes of registers for register constraints in the
480 machine description. Also define ranges of constants.
482 One of the classes must always be named ALL_REGS and include all hard regs.
483 If there is more than one class, another class must be named NO_REGS
484 and contain no registers.
486 The name GENERAL_REGS must be the name of a class (or an alias for
487 another name such as ALL_REGS). This is the class of registers
488 that is allowed by "g" or "r" in a register constraint.
489 Also, registers outside this class are allocated only when
490 instructions express preferences for them.
492 The classes must be numbered in nondecreasing order; that is,
493 a larger-numbered class must never be contained completely
494 in a smaller-numbered class.
496 For any two classes, it is very desirable that there be another
497 class that represents their union.
499 The 29k has nine registers classes: LR0_REGS, GENERAL_REGS, SPECIAL_REGS,
500 BP_REGS, FC_REGS, CR_REGS, Q_REGS, ACCUM_REGS, and ACCUM0_REGS.
501 LR0_REGS, BP_REGS, FC_REGS, CR_REGS, and Q_REGS contain just the single
502 register. The latter two classes are used to represent the floating-point
503 accumulator registers in the 29050. We also define the union class
504 FLOAT_REGS to represent any register that can be used to hold a
505 floating-point value. The union of SPECIAL_REGS and ACCUM_REGS isn't
506 useful as the former cannot contain floating-point and the latter can only
507 contain floating-point. */
509 enum reg_class { NO_REGS, LR0_REGS, GENERAL_REGS, BP_REGS, FC_REGS, CR_REGS,
510 Q_REGS, SPECIAL_REGS, ACCUM0_REGS, ACCUM_REGS, FLOAT_REGS,
511 ALL_REGS, LIM_REG_CLASSES };
513 #define N_REG_CLASSES (int) LIM_REG_CLASSES
515 /* Give names of register classes as strings for dump file. */
517 #define REG_CLASS_NAMES \
518 {"NO_REGS", "LR0_REGS", "GENERAL_REGS", "BP_REGS", "FC_REGS", "CR_REGS", \
519 "Q_REGS", "SPECIAL_REGS", "ACCUM0_REGS", "ACCUM_REGS", "FLOAT_REGS", \
522 /* Define which registers fit in which classes.
523 This is an initializer for a vector of HARD_REG_SET
524 of length N_REG_CLASSES. */
526 #define REG_CLASS_CONTENTS \
527 { {0, 0, 0, 0, 0, 0, 0, 0}, \
528 {0, 1, 0, 0, 0, 0, 0, 0}, \
529 {~0, ~0, ~0, ~0, ~0, ~ 0xfffe0000, ~ 0xfff, 0xfff}, \
530 {0, 0, 0, 0, 0, 0x20000, 0, 0}, \
531 {0, 0, 0, 0, 0, 0x40000, 0, 0}, \
532 {0, 0, 0, 0, 0, 0x80000, 0, 0}, \
533 {0, 0, 0, 0, 0, 0x100000, 0, 0}, \
534 {0, 0, 0, 0, 0, 0xfffe0000, 0xff, 0}, \
535 {0, 0, 0, 0, 0, 0, 0x100, 0}, \
536 {0, 0, 0, 0, 0, 0, 0xf00, 0}, \
537 {~0, ~0, ~0, ~0, ~0, ~ 0xfffe0000, ~ 0xff, 0xfff}, \
538 {~0, ~0, ~0, ~0, ~0, ~0, ~0, 0xfff} }
540 /* The same information, inverted:
541 Return the class number of the smallest class containing
542 reg number REGNO. This could be a conditional expression
543 or could index an array. */
545 #define REGNO_REG_CLASS(REGNO) \
546 ((REGNO) == R_BP ? BP_REGS \
547 : (REGNO) == R_FC ? FC_REGS \
548 : (REGNO) == R_CR ? CR_REGS \
549 : (REGNO) == R_Q ? Q_REGS \
550 : (REGNO) > R_BP && (REGNO) <= R_EXO ? SPECIAL_REGS \
551 : (REGNO) == R_ACU (0) ? ACCUM0_REGS \
552 : (REGNO) >= R_KR (0) ? GENERAL_REGS \
553 : (REGNO) > R_ACU (0) ? ACCUM_REGS \
554 : (REGNO) == R_LR (0) ? LR0_REGS \
557 /* The class value for index registers, and the one for base regs. */
558 #define INDEX_REG_CLASS NO_REGS
559 #define BASE_REG_CLASS GENERAL_REGS
561 /* Get reg_class from a letter such as appears in the machine description. */
563 #define REG_CLASS_FROM_LETTER(C) \
564 ((C) == 'r' ? GENERAL_REGS \
565 : (C) == 'l' ? LR0_REGS \
566 : (C) == 'b' ? BP_REGS \
567 : (C) == 'f' ? FC_REGS \
568 : (C) == 'c' ? CR_REGS \
569 : (C) == 'q' ? Q_REGS \
570 : (C) == 'h' ? SPECIAL_REGS \
571 : (C) == 'a' ? ACCUM_REGS \
572 : (C) == 'A' ? ACCUM0_REGS \
573 : (C) == 'f' ? FLOAT_REGS \
576 /* Define this macro to change register usage conditional on target flags.
578 On the 29k, we use this to change the register names for kernel mapping. */
580 #define CONDITIONAL_REGISTER_USAGE \
585 if (TARGET_KERNEL_REGISTERS) \
586 for (i = 0; i < 32; i++) \
589 reg_names[i] = reg_names[R_KR (i)]; \
590 reg_names[R_KR (i)] = p; \
594 /* The letters I, J, K, L, M, N, O, and P in a register constraint string
595 can be used to stand for particular ranges of immediate operands.
596 This macro defines what the ranges are.
597 C is the letter, and VALUE is a constant value.
598 Return 1 if VALUE is in the range specified by C.
601 `I' is used for the range of constants most insns can contain.
602 `J' is for the few 16-bit insns.
603 `K' is a constant whose high-order 24 bits are all one
604 `L' is a HImode constant whose high-order 8 bits are all one
605 `M' is a 32-bit constant whose high-order 16 bits are all one (for CONSTN)
606 `N' is a 32-bit constant whose negative is 8 bits
607 `O' is the 32-bit constant 0x80000000, any constant with low-order
608 16 bits zero for 29050.
609 `P' is a HImode constant whose negative is 8 bits */
611 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
612 ((C) == 'I' ? (unsigned) (VALUE) < 0x100 \
613 : (C) == 'J' ? (unsigned) (VALUE) < 0x10000 \
614 : (C) == 'K' ? ((VALUE) & 0xffffff00) == 0xffffff00 \
615 : (C) == 'L' ? ((VALUE) & 0xff00) == 0xff00 \
616 : (C) == 'M' ? ((VALUE) & 0xffff0000) == 0xffff0000 \
617 : (C) == 'N' ? ((VALUE) < 0 && (VALUE) > -256) \
618 : (C) == 'O' ? ((VALUE) == 0x80000000 \
619 || (TARGET_29050 && ((VALUE) & 0xffff) == 0)) \
620 : (C) == 'P' ? (((VALUE) | 0xffff0000) < 0 \
621 && ((VALUE) | 0xffff0000) > -256) \
624 /* Similar, but for floating constants, and defining letters G and H.
625 Here VALUE is the CONST_DOUBLE rtx itself.
626 All floating-point constants are valid on 29k. */
628 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) 1
630 /* Given an rtx X being reloaded into a reg required to be
631 in class CLASS, return the class of reg to actually use.
632 In general this is just CLASS; but on some machines
633 in some cases it is preferable to use a more restrictive class. */
635 #define PREFERRED_RELOAD_CLASS(X,CLASS) CLASS
637 /* Return the register class of a scratch register needed to copy IN into
638 or out of a register in CLASS in MODE. If it can be done directly,
639 NO_REGS is returned. */
641 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
642 secondary_reload_class (CLASS, MODE, IN)
644 /* Return the maximum number of consecutive registers
645 needed to represent mode MODE in a register of class CLASS.
647 On 29k, this is the size of MODE in words except that the floating-point
648 accumulators only require one word for anything they can hold. */
650 #define CLASS_MAX_NREGS(CLASS, MODE) \
651 (((CLASS) == ACCUM_REGS || (CLASS) == ACCUM0_REGS) ? 1 \
652 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
654 /* Define the cost of moving between registers of various classes. Everything
655 involving a general register is cheap, but moving between the other types
656 (even within a class) is two insns. */
658 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
659 ((CLASS1) == GENERAL_REGS || (CLASS2) == GENERAL_REGS ? 2 : 4)
661 /* A C expressions returning the cost of moving data of MODE from a register to
664 It takes extra insns on the 29k to form addresses, so we want to make
665 this higher. In addition, we need to keep it more expensive than the
666 most expensive register-register copy. */
668 #define MEMORY_MOVE_COST(MODE,CLASS,IN) 6
670 /* Stack layout; function entry, exit and calling. */
672 /* Define this if pushing a word on the stack
673 makes the stack pointer a smaller address. */
674 #define STACK_GROWS_DOWNWARD
676 /* Define this if the nominal address of the stack frame
677 is at the high-address end of the local variables;
678 that is, each additional local variable allocated
679 goes at a more negative offset in the frame. */
680 #define FRAME_GROWS_DOWNWARD
682 /* Offset within stack frame to start allocating local variables at.
683 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
684 first local allocated. Otherwise, it is the offset to the BEGINNING
685 of the first local allocated. */
687 #define STARTING_FRAME_OFFSET (- current_function_pretend_args_size)
689 /* If we generate an insn to push BYTES bytes,
690 this says how many the stack pointer really advances by.
691 On 29k, don't define this because there are no push insns. */
692 /* #define PUSH_ROUNDING(BYTES) */
694 /* Define this if the maximum size of all the outgoing args is to be
695 accumulated and pushed during the prologue. The amount can be
696 found in the variable current_function_outgoing_args_size. */
697 #define ACCUMULATE_OUTGOING_ARGS 1
699 /* Offset of first parameter from the argument pointer register value. */
701 #define FIRST_PARM_OFFSET(FNDECL) (- current_function_pretend_args_size)
703 /* Define this if stack space is still allocated for a parameter passed
705 /* #define REG_PARM_STACK_SPACE */
707 /* Value is the number of bytes of arguments automatically
708 popped when returning from a subroutine call.
709 FUNDECL is the declaration node of the function (as a tree),
710 FUNTYPE is the data type of the function (as a tree),
711 or for a library call it is an identifier node for the subroutine name.
712 SIZE is the number of bytes of arguments passed on the stack. */
714 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
716 /* Define how to find the value returned by a function.
717 VALTYPE is the data type of the value (as a tree).
718 If the precise function being called is known, FUNC is its FUNCTION_DECL;
719 otherwise, FUNC is 0.
721 On 29k the value is found in gr96. */
723 #define FUNCTION_VALUE(VALTYPE, FUNC) \
724 gen_rtx_REG (TYPE_MODE (VALTYPE), R_GR (96))
726 /* Define how to find the value returned by a library function
727 assuming the value has mode MODE. */
729 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, R_GR (96))
731 /* 1 if N is a possible register number for a function value
732 as seen by the caller.
733 On 29k, gr96-gr111 are used. */
735 #define FUNCTION_VALUE_REGNO_P(N) ((N) == R_GR (96))
737 /* 1 if N is a possible register number for function argument passing.
738 On 29k, these are lr2-lr17. */
740 #define FUNCTION_ARG_REGNO_P(N) ((N) <= R_LR (17) && (N) >= R_LR (2))
742 /* Define a data type for recording info about an argument list
743 during the scan of that argument list. This data type should
744 hold all necessary information about the function itself
745 and about the args processed so far, enough to enable macros
746 such as FUNCTION_ARG to determine where the next arg should go.
748 On 29k, this is a single integer, which is a number of words
749 of arguments scanned so far.
750 Thus 16 or more means all following args should go on the stack. */
752 #define CUMULATIVE_ARGS int
754 /* Initialize a variable CUM of type CUMULATIVE_ARGS
755 for a call to a function whose data type is FNTYPE.
756 For a library call, FNTYPE is 0. */
758 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) (CUM) = 0
760 /* Same, but called for incoming args.
762 On the 29k, we use this to set all argument registers to fixed and
763 set the last 16 local regs, less two, (lr110-lr125) to available. Some
764 will later be changed to call-saved by FUNCTION_INCOMING_ARG.
765 lr126,lr127 are always fixed, they are place holders for the caller's
768 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM,FNTYPE,IGNORE) \
770 for (i = R_AR (0) - 2; i < R_AR (16); i++) \
772 fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1; \
773 SET_HARD_REG_BIT (fixed_reg_set, i); \
774 SET_HARD_REG_BIT (call_used_reg_set, i); \
775 SET_HARD_REG_BIT (call_fixed_reg_set, i); \
777 for (i = R_LR (110); i < R_LR (126); i++) \
779 fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 0; \
780 CLEAR_HARD_REG_BIT (fixed_reg_set, i); \
781 CLEAR_HARD_REG_BIT (call_used_reg_set, i); \
782 CLEAR_HARD_REG_BIT (call_fixed_reg_set, i); \
787 /* Define intermediate macro to compute the size (in registers) of an argument
790 #define A29K_ARG_SIZE(MODE, TYPE, NAMED) \
792 : (MODE) != BLKmode \
793 ? (GET_MODE_SIZE (MODE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD \
794 : (int_size_in_bytes (TYPE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
796 /* Update the data in CUM to advance over an argument
797 of mode MODE and data type TYPE.
798 (TYPE is null for libcalls where that information may not be available.) */
800 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
801 if (MUST_PASS_IN_STACK (MODE, TYPE)) \
804 (CUM) += A29K_ARG_SIZE (MODE, TYPE, NAMED)
806 /* Determine where to put an argument to a function.
807 Value is zero to push the argument on the stack,
808 or a hard register in which to store the argument.
810 MODE is the argument's machine mode.
811 TYPE is the data type of the argument (as a tree).
812 This is null for libcalls where that information may
814 CUM is a variable of type CUMULATIVE_ARGS which gives info about
815 the preceding args and about the function being called.
816 NAMED is nonzero if this argument is a named parameter
817 (otherwise it is an extra parameter matching an ellipsis).
819 On 29k the first 16 words of args are normally in registers
820 and the rest are pushed. */
822 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
823 ((CUM) < 16 && (NAMED) && ! MUST_PASS_IN_STACK (MODE, TYPE) \
824 ? gen_rtx_REG ((MODE), R_LR (2) + (CUM)) : 0)
826 /* Define where a function finds its arguments.
827 This is different from FUNCTION_ARG because of register windows.
829 On the 29k, we hack this to call a function that sets the used registers
830 as non-fixed and not used by calls. */
832 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
833 ((CUM) < 16 && (NAMED) && ! MUST_PASS_IN_STACK (MODE, TYPE) \
834 ? gen_rtx_REG (MODE, \
835 incoming_reg (CUM, A29K_ARG_SIZE (MODE, TYPE, NAMED))) \
838 /* This indicates that an argument is to be passed with an invisible reference
839 (i.e., a pointer to the object is passed).
841 On the 29k, we do this if it must be passed on the stack. */
843 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
844 (MUST_PASS_IN_STACK (MODE, TYPE))
846 /* Specify the padding direction of arguments.
848 On the 29k, we must pad upwards in order to be able to pass args in
851 #define FUNCTION_ARG_PADDING(MODE, TYPE) upward
853 /* For an arg passed partly in registers and partly in memory,
854 this is the number of registers used.
855 For args passed entirely in registers or entirely in memory, zero. */
857 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
858 ((CUM) < 16 && 16 < (CUM) + A29K_ARG_SIZE (MODE, TYPE, NAMED) && (NAMED) \
861 /* Perform any needed actions needed for a function that is receiving a
862 variable number of arguments.
866 MODE and TYPE are the mode and type of the current parameter.
868 PRETEND_SIZE is a variable that should be set to the amount of stack
869 that must be pushed by the prolog to pretend that our caller pushed
872 Normally, this macro will push all remaining incoming registers on the
873 stack and set PRETEND_SIZE to the length of the registers pushed. */
875 #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
878 int first_reg_offset = (CUM); \
880 if (MUST_PASS_IN_STACK (MODE, TYPE)) \
881 first_reg_offset += A29K_ARG_SIZE (TYPE_MODE (TYPE), TYPE, 1); \
883 if (first_reg_offset > 16) \
884 first_reg_offset = 16; \
886 if (! (NO_RTL) && first_reg_offset != 16) \
887 move_block_from_reg \
888 (R_AR (0) + first_reg_offset, \
889 gen_rtx_MEM (BLKmode, virtual_incoming_args_rtx), \
890 16 - first_reg_offset, (16 - first_reg_offset) * UNITS_PER_WORD); \
891 PRETEND_SIZE = (16 - first_reg_offset) * UNITS_PER_WORD; \
895 /* Define the information needed to generate branch and scc insns. This is
896 stored from the compare operation. Note that we can't use "rtx" here
897 since it hasn't been defined! */
899 extern struct rtx_def *a29k_compare_op0, *a29k_compare_op1;
900 extern int a29k_compare_fp_p;
902 /* This macro produces the initial definition of a function name.
904 For the 29k, we need the prolog to contain one or two words prior to
905 the declaration of the function name. So just store away the name and
906 write it as part of the prolog. This also computes the register names,
907 which can't be done until after register allocation, but must be done
908 before final_start_function is called. */
910 extern const char *a29k_function_name;
912 #define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL) \
913 a29k_function_name = NAME; \
914 a29k_compute_reg_names ();
916 /* Output assembler code to FILE to increment profiler label # LABELNO
917 for profiling a function entry. */
919 #define FUNCTION_PROFILER(FILE, LABELNO)
921 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
922 the stack pointer does not matter. The value is tested only in
923 functions that have frame pointers.
924 No definition is equivalent to always zero. */
926 #define EXIT_IGNORE_STACK 1
928 /* Define the number of delay slots needed for the function epilogue.
930 On the 29k, we need a slot except when we have a register stack adjustment,
931 have a memory stack adjustment, and have no frame pointer. */
933 #define DELAY_SLOTS_FOR_EPILOGUE \
934 (! (needs_regstack_p () \
935 && (get_frame_size () + current_function_pretend_args_size \
936 + current_function_outgoing_args_size) != 0 \
937 && ! frame_pointer_needed))
939 /* Define whether INSN can be placed in delay slot N for the epilogue.
941 On the 29k, we must be able to place it in a delay slot, it must
942 not use sp if the frame pointer cannot be eliminated, and it cannot
943 use local regs if we need to push the register stack.
944 If this is a SET with a memory as source, it might load from
945 a stack slot, unless the address is constant. */
947 #define ELIGIBLE_FOR_EPILOGUE_DELAY(INSN,N) \
948 (get_attr_in_delay_slot (INSN) == IN_DELAY_SLOT_YES \
949 && ! (frame_pointer_needed \
950 && reg_mentioned_p (stack_pointer_rtx, PATTERN (INSN))) \
951 && ! (needs_regstack_p () && uses_local_reg_p (PATTERN (INSN))) \
952 && (GET_CODE (PATTERN (INSN)) != SET \
953 || GET_CODE (SET_SRC (PATTERN (INSN))) != MEM \
954 || ! rtx_varies_p (XEXP (SET_SRC (PATTERN (INSN)), 0), 0)))
956 /* Output assembler code for a block containing the constant parts
957 of a trampoline, leaving space for the variable parts.
959 The trampoline should set the static chain pointer to value placed
960 into the trampoline and should branch to the specified routine. We
961 use gr121 (tav) as a temporary. */
963 #define TRAMPOLINE_TEMPLATE(FILE) \
965 fprintf (FILE, "\tconst %s,0\n", reg_names[R_TAV]); \
966 fprintf (FILE, "\tconsth %s,0\n", reg_names[R_TAV]); \
967 fprintf (FILE, "\tconst %s,0\n", reg_names[R_SLP]); \
968 fprintf (FILE, "\tjmpi %s\n", reg_names[R_TAV]); \
969 fprintf (FILE, "\tconsth %s,0\n", reg_names[R_SLP]); \
972 /* Length in units of the trampoline for entering a nested function. */
974 #define TRAMPOLINE_SIZE 20
976 /* Emit RTL insns to initialize the variable parts of a trampoline.
977 FNADDR is an RTX for the address of the function's pure code.
978 CXT is an RTX for the static chain value for the function.
980 We do this on the 29k by writing the bytes of the addresses into the
981 trampoline one byte at a time. */
983 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
985 INITIALIZE_TRAMPOLINE_VALUE (TRAMP, FNADDR, 0, 4); \
986 INITIALIZE_TRAMPOLINE_VALUE (TRAMP, CXT, 8, 16); \
989 /* Define a sub-macro to initialize one value into the trampoline.
990 We specify the offsets of the CONST and CONSTH instructions, respectively
991 and copy the value a byte at a time into these instructions. */
993 #define INITIALIZE_TRAMPOLINE_VALUE(TRAMP, VALUE, CONST, CONSTH) \
996 rtx _val = force_reg (SImode, VALUE); \
998 _addr = memory_address (QImode, plus_constant (TRAMP, (CONST) + 3)); \
999 emit_move_insn (gen_rtx_MEM (QImode, _addr), \
1000 gen_lowpart (QImode, _val)); \
1002 _temp = expand_shift (RSHIFT_EXPR, SImode, _val, \
1003 build_int_2 (8, 0), 0, 1); \
1004 _addr = memory_address (QImode, plus_constant (TRAMP, (CONST) + 1)); \
1005 emit_move_insn (gen_rtx_MEM (QImode, _addr), \
1006 gen_lowpart (QImode, _temp)); \
1008 _temp = expand_shift (RSHIFT_EXPR, SImode, _temp, \
1009 build_int_2 (8, 0), _temp, 1); \
1010 _addr = memory_address (QImode, plus_constant (TRAMP, (CONSTH) + 3)); \
1011 emit_move_insn (gen_rtx_MEM (QImode, _addr), \
1012 gen_lowpart (QImode, _temp)); \
1014 _temp = expand_shift (RSHIFT_EXPR, SImode, _temp, \
1015 build_int_2 (8, 0), _temp, 1); \
1016 _addr = memory_address (QImode, plus_constant (TRAMP, (CONSTH) + 1)); \
1017 emit_move_insn (gen_rtx_MEM (QImode, _addr), \
1018 gen_lowpart (QImode, _temp)); \
1021 /* Addressing modes, and classification of registers for them. */
1023 /* #define HAVE_POST_INCREMENT 0 */
1024 /* #define HAVE_POST_DECREMENT 0 */
1026 /* #define HAVE_PRE_DECREMENT 0 */
1027 /* #define HAVE_PRE_INCREMENT 0 */
1029 /* Macros to check register numbers against specific register classes. */
1031 /* These assume that REGNO is a hard or pseudo reg number.
1032 They give nonzero only if REGNO is a hard reg of the suitable class
1033 or a pseudo reg currently allocated to a suitable hard reg.
1034 Since they use reg_renumber, they are safe only once reg_renumber
1035 has been allocated, which happens in local-alloc.c. */
1037 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
1038 #define REGNO_OK_FOR_BASE_P(REGNO) 1
1040 /* Given the value returned from get_frame_size, compute the actual size
1041 of the frame we will allocate. We include the pretend and outgoing
1042 arg sizes and round to a doubleword. */
1044 #define ACTUAL_FRAME_SIZE(SIZE) \
1045 (((SIZE) + current_function_pretend_args_size \
1046 + current_function_outgoing_args_size + 7) & ~7)
1048 /* Define the initial offset between the frame and stack pointer. */
1050 #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \
1051 (DEPTH) = ACTUAL_FRAME_SIZE (get_frame_size ())
1053 /* Maximum number of registers that can appear in a valid memory address. */
1054 #define MAX_REGS_PER_ADDRESS 1
1056 /* Recognize any constant value that is a valid address. */
1058 #define CONSTANT_ADDRESS_P(X) \
1059 (GET_CODE (X) == CONST_INT && (unsigned) INTVAL (X) < 0x100)
1061 /* Include all constant integers and constant doubles */
1062 #define LEGITIMATE_CONSTANT_P(X) 1
1064 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1065 and check its validity for a certain class.
1066 We have two alternate definitions for each of them.
1067 The usual definition accepts all pseudo regs; the other rejects
1068 them unless they have been allocated suitable hard regs.
1069 The symbol REG_OK_STRICT causes the latter definition to be used.
1071 Most source files want to accept pseudo regs in the hope that
1072 they will get allocated to the class that the insn wants them to be in.
1073 Source files for reload pass need to be strict.
1074 After reload, it makes no difference, since pseudo regs have
1075 been eliminated by then. */
1077 #ifndef REG_OK_STRICT
1079 /* Nonzero if X is a hard reg that can be used as an index
1080 or if it is a pseudo reg. */
1081 #define REG_OK_FOR_INDEX_P(X) 0
1082 /* Nonzero if X is a hard reg that can be used as a base reg
1083 or if it is a pseudo reg. */
1084 #define REG_OK_FOR_BASE_P(X) 1
1088 /* Nonzero if X is a hard reg that can be used as an index. */
1089 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1090 /* Nonzero if X is a hard reg that can be used as a base reg. */
1091 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1095 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1096 that is a valid memory address for an instruction.
1097 The MODE argument is the machine mode for the MEM expression
1098 that wants to use this address.
1100 On the 29k, a legitimate address is a register and so is a
1101 constant of less than 256. */
1103 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1104 { if (REG_P (X) && REG_OK_FOR_BASE_P (X)) \
1106 if (GET_CODE (X) == CONST_INT \
1107 && (unsigned) INTVAL (X) < 0x100) \
1111 /* Try machine-dependent ways of modifying an illegitimate address
1112 to be legitimate. If we find one, return the new, valid address.
1113 This macro is used in only one place: `memory_address' in explow.c.
1115 OLDX is the address as it was before break_out_memory_refs was called.
1116 In some cases it is useful to look at this to decide what needs to be done.
1118 MODE and WIN are passed so that this macro can use
1119 GO_IF_LEGITIMATE_ADDRESS.
1121 It is always safe for this macro to do nothing. It exists to recognize
1122 opportunities to optimize the output.
1124 For the 29k, we need not do anything. However, if we don't,
1125 `memory_address' will try lots of things to get a valid address, most of
1126 which will result in dead code and extra pseudos. So we make the address
1129 This is easy: The only valid addresses are an offset from a register
1130 and we know the address isn't valid. So just call either `force_operand'
1131 or `force_reg' unless this is a (plus (reg ...) (const_int 0)). */
1133 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1134 { if (GET_CODE (X) == PLUS && XEXP (X, 1) == const0_rtx) \
1136 if (GET_CODE (X) == MULT || GET_CODE (X) == PLUS) \
1137 X = force_operand (X, 0); \
1139 X = force_reg (Pmode, X); \
1143 /* Go to LABEL if ADDR (a legitimate address expression)
1144 has an effect that depends on the machine mode it is used for.
1145 On the 29k this is never true. */
1147 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
1149 /* Compute the cost of an address. For the 29k, all valid addresses are
1152 #define ADDRESS_COST(X) 0
1154 /* Define this if some processing needs to be done immediately before
1155 emitting code for an insn. */
1157 /* #define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) */
1159 /* Specify the machine mode that this machine uses
1160 for the index in the tablejump instruction. */
1161 #define CASE_VECTOR_MODE SImode
1163 /* Define as C expression which evaluates to nonzero if the tablejump
1164 instruction expects the table to contain offsets from the address of the
1166 Do not define this if the table should contain absolute addresses. */
1167 /* #define CASE_VECTOR_PC_RELATIVE 1 */
1169 /* Define this as 1 if `char' should by default be signed; else as 0. */
1170 #define DEFAULT_SIGNED_CHAR 0
1172 /* This flag, if defined, says the same insns that convert to a signed fixnum
1173 also convert validly to an unsigned one.
1175 We actually lie a bit here as overflow conditions are different. But
1176 they aren't being checked anyway. */
1178 #define FIXUNS_TRUNC_LIKE_FIX_TRUNC
1180 /* Max number of bytes we can move to of from memory
1181 in one reasonably fast instruction.
1183 For the 29k, we will define movti, so put this at 4 words. */
1186 /* Largest number of bytes of an object that can be placed in a register.
1187 On the 29k we have plenty of registers, so use TImode. */
1188 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode)
1190 /* Nonzero if access to memory by bytes is no faster than for words.
1191 Also non-zero if doing byte operations (specifically shifts) in registers
1194 On the 29k, large masks are expensive, so we want to use bytes to
1195 manipulate fields. */
1196 #define SLOW_BYTE_ACCESS 0
1198 /* Define if operations between registers always perform the operation
1199 on the full register even if a narrower mode is specified. */
1200 #define WORD_REGISTER_OPERATIONS
1202 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1203 will either zero-extend or sign-extend. The value of this macro should
1204 be the code that says which one of the two operations is implicitly
1205 done, NIL if none. */
1206 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1208 /* Define if the object format being used is COFF or a superset. */
1209 #define OBJECT_FORMAT_COFF
1211 /* This uses COFF, so it wants SDB format. */
1212 #define SDB_DEBUGGING_INFO
1214 /* Define this to be the delimiter between SDB sub-sections. The default
1216 #define SDB_DELIM "\n"
1218 /* Do not break .stabs pseudos into continuations. */
1219 #define DBX_CONTIN_LENGTH 0
1221 /* Don't try to use the `x' type-cross-reference character in DBX data.
1222 Also has the consequence of putting each struct, union or enum
1223 into a separate .stabs, containing only cross-refs to the others. */
1224 #define DBX_NO_XREFS
1226 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1227 is done just by pretending it is already truncated. */
1228 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1230 /* We assume that the store-condition-codes instructions store 0 for false
1231 and some other value for true. This is the value stored for true, which
1232 is just the sign bit. */
1234 #define STORE_FLAG_VALUE (-2147483647 - 1)
1236 /* Specify the machine mode that pointers have.
1237 After generation of rtl, the compiler makes no further distinction
1238 between pointers and any other objects of this machine mode. */
1239 #define Pmode SImode
1241 /* Mode of a function address in a call instruction (for indexing purposes).
1243 Doesn't matter on 29k. */
1244 #define FUNCTION_MODE SImode
1246 /* Define this if addresses of constant functions
1247 shouldn't be put through pseudo regs where they can be cse'd.
1248 Desirable on machines where ordinary constants are expensive
1249 but a CALL with constant address is cheap. */
1250 #define NO_FUNCTION_CSE
1252 /* Define this to be nonzero if shift instructions ignore all but the low-order
1254 #define SHIFT_COUNT_TRUNCATED 1
1256 /* Compute the cost of computing a constant rtl expression RTX
1257 whose rtx-code is CODE. The body of this macro is a portion
1258 of a switch statement. If the code is computed here,
1259 return it with a return statement. Otherwise, break from the switch.
1261 We only care about the cost if it is valid in an insn. The only
1262 constants that cause an insn to generate more than one machine
1263 instruction are those involving floating-point or address. So
1264 only these need be expensive. */
1266 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
1273 case CONST_DOUBLE: \
1274 return GET_MODE (RTX) == SFmode ? 6 : 8;
1276 /* Provide the costs of a rtl expression. This is in the body of a
1279 All MEMs cost the same if they are valid. This is used to ensure
1280 that (mem (symbol_ref ...)) is placed into a CALL when valid.
1282 The multiply cost depends on whether this is a 29050 or not. */
1284 #define RTX_COSTS(X,CODE,OUTER_CODE) \
1286 return TARGET_29050 ? COSTS_N_INSNS (2) : COSTS_N_INSNS (40); \
1291 return COSTS_N_INSNS (50); \
1293 return COSTS_N_INSNS (2);
1295 /* Control the assembler format that we output. */
1297 /* Output at beginning of assembler file. */
1299 #define ASM_FILE_START(FILE) \
1300 { const char *p, *after_dir = main_input_filename; \
1302 fprintf (FILE, "\t.cputype 29050\n"); \
1303 for (p = main_input_filename; *p; p++) \
1305 after_dir = p + 1; \
1306 fprintf (FILE, "\t.file "); \
1307 output_quoted_string (FILE, after_dir); \
1308 fprintf (FILE, "\n"); \
1309 fprintf (FILE, "\t.sect .lit,lit\n"); }
1311 /* Output to assembler file text saying following lines
1312 may contain character constants, extra white space, comments, etc. */
1314 #define ASM_APP_ON ""
1316 /* Output to assembler file text saying following lines
1317 no longer contain unusual constructs. */
1319 #define ASM_APP_OFF ""
1321 /* The next few macros don't have tabs on most machines, but
1322 at least one 29K assembler wants them. */
1324 /* Output before instructions. */
1326 #define TEXT_SECTION_ASM_OP "\t.text"
1328 /* Output before read-only data. */
1330 #define READONLY_DATA_SECTION_ASM_OP "\t.use .lit"
1332 /* Output before writable data. */
1334 #define DATA_SECTION_ASM_OP "\t.data"
1336 /* If we are referencing a function that is static or is known to be
1337 in this file, make the SYMBOL_REF special. We can use this to indicate
1338 that we can branch to this function without emitting a no-op after the
1341 #define ENCODE_SECTION_INFO(DECL, FIRST) \
1342 if (TREE_CODE (DECL) == FUNCTION_DECL \
1343 && (TREE_ASM_WRITTEN (DECL) || ! TREE_PUBLIC (DECL))) \
1344 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1;
1346 /* How to refer to registers in assembler output.
1347 This sequence is indexed by compiler's hard-register-number (see above). */
1349 #define REGISTER_NAMES \
1350 {"gr96", "gr97", "gr98", "gr99", "gr100", "gr101", "gr102", "gr103", "gr104", \
1351 "gr105", "gr106", "gr107", "gr108", "gr109", "gr110", "gr111", "gr112", \
1352 "gr113", "gr114", "gr115", "gr116", "gr117", "gr118", "gr119", "gr120", \
1353 "gr121", "gr122", "gr123", "gr124", "gr125", "gr126", "gr127", \
1354 "lr0", "lr1", "lr2", "lr3", "lr4", "lr5", "lr6", "lr7", "lr8", "lr9", \
1355 "lr10", "lr11", "lr12", "lr13", "lr14", "lr15", "lr16", "lr17", "lr18", \
1356 "lr19", "lr20", "lr21", "lr22", "lr23", "lr24", "lr25", "lr26", "lr27", \
1357 "lr28", "lr29", "lr30", "lr31", "lr32", "lr33", "lr34", "lr35", "lr36", \
1358 "lr37", "lr38", "lr39", "lr40", "lr41", "lr42", "lr43", "lr44", "lr45", \
1359 "lr46", "lr47", "lr48", "lr49", "lr50", "lr51", "lr52", "lr53", "lr54", \
1360 "lr55", "lr56", "lr57", "lr58", "lr59", "lr60", "lr61", "lr62", "lr63", \
1361 "lr64", "lr65", "lr66", "lr67", "lr68", "lr69", "lr70", "lr71", "lr72", \
1362 "lr73", "lr74", "lr75", "lr76", "lr77", "lr78", "lr79", "lr80", "lr81", \
1363 "lr82", "lr83", "lr84", "lr85", "lr86", "lr87", "lr88", "lr89", "lr90", \
1364 "lr91", "lr92", "lr93", "lr94", "lr95", "lr96", "lr97", "lr98", "lr99", \
1365 "lr100", "lr101", "lr102", "lr103", "lr104", "lr105", "lr106", "lr107", \
1366 "lr108", "lr109", "lr110", "lr111", "lr112", "lr113", "lr114", "lr115", \
1367 "lr116", "lr117", "lr118", "lr119", "lr120", "lr121", "lr122", "lr123", \
1368 "lr124", "lr125", "lr126", "lr127", \
1369 "AI0", "AI1", "AI2", "AI3", "AI4", "AI5", "AI6", "AI7", "AI8", "AI9", \
1370 "AI10", "AI11", "AI12", "AI13", "AI14", "AI15", "FP", \
1371 "bp", "fc", "cr", "q", \
1372 "vab", "ops", "cps", "cfg", "cha", "chd", "chc", "rbp", "tmc", "tmr", \
1373 "pc0", "pc1", "pc2", "mmu", "lru", "fpe", "int", "fps", "exo", \
1374 "0", "1", "2", "3", \
1375 "gr64", "gr65", "gr66", "gr67", "gr68", "gr69", "gr70", "gr71", \
1376 "gr72", "gr73", "gr74", "gr75", "gr76", "gr77", "gr78", "gr79", \
1377 "gr80", "gr81", "gr82", "gr83", "gr84", "gr85", "gr86", "gr87", \
1378 "gr88", "gr89", "gr90", "gr91", "gr92", "gr93", "gr94", "gr95" }
1380 /* How to renumber registers for dbx and gdb. */
1382 extern int a29k_debug_reg_map[FIRST_PSEUDO_REGISTER];
1383 #define DBX_REGISTER_NUMBER(REGNO) a29k_debug_reg_map[REGNO]
1385 /* Switch into a generic section. */
1386 #define TARGET_ASM_NAMED_SECTION a29k_asm_named_section
1388 /* This is how to output the definition of a user-level label named NAME,
1389 such as the label on a static function or variable NAME. */
1391 #define ASM_OUTPUT_LABEL(FILE,NAME) \
1392 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
1394 /* This is how to output a command to make the user-level label named NAME
1395 defined for reference from other files. */
1397 #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
1398 do { fputs ("\t.global ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
1400 /* The prefix to add to user-visible assembler symbols. */
1402 #undef USER_LABEL_PREFIX
1403 #define USER_LABEL_PREFIX "_"
1405 /* This is how to output an internal numbered label where
1406 PREFIX is the class of label and NUM is the number within the class. */
1408 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1409 fprintf (FILE, "%s%d:\n", PREFIX, NUM)
1411 /* This is how to output a label for a jump table. Arguments are the same as
1412 for ASM_OUTPUT_INTERNAL_LABEL, except the insn for the jump table is
1415 #define ASM_OUTPUT_CASE_LABEL(FILE,PREFIX,NUM,TABLEINSN) \
1416 { ASM_OUTPUT_ALIGN (FILE, 2); ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); }
1418 /* This is how to store into the string LABEL
1419 the symbol_ref name of an internal numbered label where
1420 PREFIX is the class of label and NUM is the number within the class.
1421 This is suitable for output with `assemble_name'. */
1423 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1424 sprintf (LABEL, "*%s%d", PREFIX, NUM)
1426 /* This is how to output an insn to push a register on the stack.
1427 It need not be very fast code. */
1429 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
1430 fprintf (FILE, "\tsub %s,%s,4\n\tstore 0,0,%s,%s\n", \
1431 reg_names[R_MSP], reg_names[R_MSP], reg_names[REGNO], \
1434 /* This is how to output an insn to pop a register from the stack.
1435 It need not be very fast code. */
1437 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
1438 fprintf (FILE, "\tload 0,0,%s,%s\n\tadd %s,%s,4\n", \
1439 reg_names[REGNO], reg_names[R_MSP], reg_names[R_MSP], \
1442 /* This is how to output an element of a case-vector that is absolute. */
1444 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1445 fprintf (FILE, "\t.word L%d\n", VALUE)
1447 /* This is how to output an element of a case-vector that is relative.
1448 Don't define this if it is not supported. */
1450 /* #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) */
1452 /* This is how to output an assembler line
1453 that says to advance the location counter
1454 to a multiple of 2**LOG bytes. */
1456 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1458 fprintf (FILE, "\t.align %d\n", 1 << (LOG))
1460 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1461 fprintf (FILE, "\t.block %d\n", (SIZE))
1463 /* This says how to output an assembler line
1464 to define a global common symbol. */
1466 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1467 ( fputs ("\t.comm ", (FILE)), \
1468 assemble_name ((FILE), (NAME)), \
1469 fprintf ((FILE), ",%d\n", (SIZE)))
1471 /* This says how to output an assembler line
1472 to define a local common symbol. */
1474 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE,ROUNDED) \
1475 ( fputs ("\t.lcomm ", (FILE)), \
1476 assemble_name ((FILE), (NAME)), \
1477 fprintf ((FILE), ",%d\n", (SIZE)))
1479 /* Store in OUTPUT a string (made with alloca) containing
1480 an assembler-name for a local static variable named NAME.
1481 LABELNO is an integer which is different for each call. */
1483 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
1484 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
1485 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
1487 /* Print operand X (an rtx) in assembler syntax to file FILE.
1488 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1489 For `%' followed by punctuation, CODE is the punctuation and X is null. */
1491 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
1493 /* Determine which codes are valid without a following integer. These must
1496 We support `#' which is null if a delay slot exists, otherwise
1497 "\n\tnop" and `*' which prints the register name for TPC (gr122). */
1499 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '#' || (CODE) == '*')
1501 /* Print a memory address as an operand to reference that memory location. */
1503 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1504 { register rtx addr = ADDR; \
1506 && ! (GET_CODE (addr) == CONST_INT \
1507 && INTVAL (addr) >= 0 && INTVAL (addr) < 256)) \
1509 output_operand (addr, 0); \
1511 /* Define the codes that are matched by predicates in a29k.c. */
1513 #define PREDICATE_CODES \
1514 {"cint_8_operand", {CONST_INT}}, \
1515 {"cint_16_operand", {CONST_INT}}, \
1516 {"long_const_operand", {CONST_INT, CONST, CONST_DOUBLE, \
1517 LABEL_REF, SYMBOL_REF}}, \
1518 {"const_0_operand", {CONST_INT, ASHIFT}}, \
1519 {"const_8_operand", {CONST_INT, ASHIFT}}, \
1520 {"const_16_operand", {CONST_INT, ASHIFT}}, \
1521 {"const_24_operand", {CONST_INT, ASHIFT}}, \
1522 {"float_const_operand", {CONST_DOUBLE}}, \
1523 {"gpc_reg_operand", {SUBREG, REG}}, \
1524 {"gpc_reg_or_float_constant_operand", {SUBREG, REG, CONST_DOUBLE}}, \
1525 {"gpc_reg_or_integer_constant_operand", {SUBREG, REG, \
1526 CONST_INT, CONST_DOUBLE}}, \
1527 {"gpc_reg_or_immediate_operand", {SUBREG, REG, CONST_INT, \
1528 CONST_DOUBLE, CONST, \
1529 SYMBOL_REF, LABEL_REF}}, \
1530 {"spec_reg_operand", {REG}}, \
1531 {"accum_reg_operand", {REG}}, \
1532 {"srcb_operand", {SUBREG, REG, CONST_INT}}, \
1533 {"cmplsrcb_operand", {SUBREG, REG, CONST_INT}}, \
1534 {"reg_or_immediate_operand", {SUBREG, REG, CONST_INT, CONST, \
1535 CONST_DOUBLE, CONST, SYMBOL_REF, LABEL_REF}}, \
1536 {"reg_or_u_short_operand", {SUBREG, REG, CONST_INT}}, \
1537 {"and_operand", {SUBREG, REG, CONST_INT}}, \
1538 {"add_operand", {SUBREG, REG, CONST_INT}}, \
1539 {"call_operand", {SYMBOL_REF, CONST_INT}}, \
1540 {"in_operand", {SUBREG, MEM, REG, CONST_INT, CONST, SYMBOL_REF, \
1541 LABEL_REF, CONST_DOUBLE}}, \
1542 {"out_operand", {SUBREG, REG, MEM}}, \
1543 {"reload_memory_operand", {SUBREG, REG, MEM}}, \
1544 {"fp_comparison_operator", {EQ, GT, GE}}, \
1545 {"branch_operator", {GE, LT}}, \
1546 {"load_multiple_operation", {PARALLEL}}, \
1547 {"store_multiple_operation", {PARALLEL}}, \
1548 {"epilogue_operand", {CODE_LABEL}},