1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
57 removed because there is no way to know which register it was
60 To simplify substitution, we combine only when the earlier insn(s)
61 consist of only a single assignment. To simplify updating afterward,
62 we never combine when a subroutine call appears in the middle.
64 Since we do not represent assignments to CC0 explicitly except when that
65 is all an insn does, there is no LOG_LINKS entry in an insn that uses
66 the condition code for the insn that set the condition code.
67 Fortunately, these two insns must be consecutive.
68 Therefore, every JUMP_INSN is taken to have an implicit logical link
69 to the preceding insn. This is not quite right, since non-jumps can
70 also use the condition code; but in practice such insns would not
75 #include "coretypes.h"
82 #include "hard-reg-set.h"
83 #include "basic-block.h"
84 #include "insn-config.h"
86 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
88 #include "insn-attr.h"
94 #ifndef SHIFT_COUNT_TRUNCATED
95 #define SHIFT_COUNT_TRUNCATED 0
98 /* Number of attempts to combine instructions in this function. */
100 static int combine_attempts;
102 /* Number of attempts that got as far as substitution in this function. */
104 static int combine_merges;
106 /* Number of instructions combined with added SETs in this function. */
108 static int combine_extras;
110 /* Number of instructions combined in this function. */
112 static int combine_successes;
114 /* Totals over entire compilation. */
116 static int total_attempts, total_merges, total_extras, total_successes;
119 /* Vector mapping INSN_UIDs to cuids.
120 The cuids are like uids but increase monotonically always.
121 Combine always uses cuids so that it can compare them.
122 But actually renumbering the uids, which we used to do,
123 proves to be a bad idea because it makes it hard to compare
124 the dumps produced by earlier passes with those from later passes. */
126 static int *uid_cuid;
127 static int max_uid_cuid;
129 /* Get the cuid of an insn. */
131 #define INSN_CUID(INSN) \
132 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
134 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
135 BITS_PER_WORD would invoke undefined behavior. Work around it. */
137 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
138 (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
140 #define nonzero_bits(X, M) \
141 cached_nonzero_bits (X, M, NULL_RTX, VOIDmode, 0)
143 #define num_sign_bit_copies(X, M) \
144 cached_num_sign_bit_copies (X, M, NULL_RTX, VOIDmode, 0)
146 /* Maximum register number, which is the size of the tables below. */
148 static unsigned int combine_max_regno;
150 /* Record last point of death of (hard or pseudo) register n. */
152 static rtx *reg_last_death;
154 /* Record last point of modification of (hard or pseudo) register n. */
156 static rtx *reg_last_set;
158 /* Record the cuid of the last insn that invalidated memory
159 (anything that writes memory, and subroutine calls, but not pushes). */
161 static int mem_last_set;
163 /* Record the cuid of the last CALL_INSN
164 so we can tell whether a potential combination crosses any calls. */
166 static int last_call_cuid;
168 /* When `subst' is called, this is the insn that is being modified
169 (by combining in a previous insn). The PATTERN of this insn
170 is still the old pattern partially modified and it should not be
171 looked at, but this may be used to examine the successors of the insn
172 to judge whether a simplification is valid. */
174 static rtx subst_insn;
176 /* This is the lowest CUID that `subst' is currently dealing with.
177 get_last_value will not return a value if the register was set at or
178 after this CUID. If not for this mechanism, we could get confused if
179 I2 or I1 in try_combine were an insn that used the old value of a register
180 to obtain a new value. In that case, we might erroneously get the
181 new value of the register when we wanted the old one. */
183 static int subst_low_cuid;
185 /* This contains any hard registers that are used in newpat; reg_dead_at_p
186 must consider all these registers to be always live. */
188 static HARD_REG_SET newpat_used_regs;
190 /* This is an insn to which a LOG_LINKS entry has been added. If this
191 insn is the earlier than I2 or I3, combine should rescan starting at
194 static rtx added_links_insn;
196 /* Basic block in which we are performing combines. */
197 static basic_block this_basic_block;
199 /* A bitmap indicating which blocks had registers go dead at entry.
200 After combine, we'll need to re-do global life analysis with
201 those blocks as starting points. */
202 static sbitmap refresh_blocks;
204 /* The next group of arrays allows the recording of the last value assigned
205 to (hard or pseudo) register n. We use this information to see if an
206 operation being processed is redundant given a prior operation performed
207 on the register. For example, an `and' with a constant is redundant if
208 all the zero bits are already known to be turned off.
210 We use an approach similar to that used by cse, but change it in the
213 (1) We do not want to reinitialize at each label.
214 (2) It is useful, but not critical, to know the actual value assigned
215 to a register. Often just its form is helpful.
217 Therefore, we maintain the following arrays:
219 reg_last_set_value the last value assigned
220 reg_last_set_label records the value of label_tick when the
221 register was assigned
222 reg_last_set_table_tick records the value of label_tick when a
223 value using the register is assigned
224 reg_last_set_invalid set to nonzero when it is not valid
225 to use the value of this register in some
228 To understand the usage of these tables, it is important to understand
229 the distinction between the value in reg_last_set_value being valid
230 and the register being validly contained in some other expression in the
233 Entry I in reg_last_set_value is valid if it is nonzero, and either
234 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
236 Register I may validly appear in any expression returned for the value
237 of another register if reg_n_sets[i] is 1. It may also appear in the
238 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
239 reg_last_set_invalid[j] is zero.
241 If an expression is found in the table containing a register which may
242 not validly appear in an expression, the register is replaced by
243 something that won't match, (clobber (const_int 0)).
245 reg_last_set_invalid[i] is set nonzero when register I is being assigned
246 to and reg_last_set_table_tick[i] == label_tick. */
248 /* Record last value assigned to (hard or pseudo) register n. */
250 static rtx *reg_last_set_value;
252 /* Record the value of label_tick when the value for register n is placed in
253 reg_last_set_value[n]. */
255 static int *reg_last_set_label;
257 /* Record the value of label_tick when an expression involving register n
258 is placed in reg_last_set_value. */
260 static int *reg_last_set_table_tick;
262 /* Set nonzero if references to register n in expressions should not be
265 static char *reg_last_set_invalid;
267 /* Incremented for each label. */
269 static int label_tick;
271 /* Some registers that are set more than once and used in more than one
272 basic block are nevertheless always set in similar ways. For example,
273 a QImode register may be loaded from memory in two places on a machine
274 where byte loads zero extend.
276 We record in the following array what we know about the nonzero
277 bits of a register, specifically which bits are known to be zero.
279 If an entry is zero, it means that we don't know anything special. */
281 static unsigned HOST_WIDE_INT *reg_nonzero_bits;
283 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
284 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
286 static enum machine_mode nonzero_bits_mode;
288 /* Nonzero if we know that a register has some leading bits that are always
289 equal to the sign bit. */
291 static unsigned char *reg_sign_bit_copies;
293 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
294 It is zero while computing them and after combine has completed. This
295 former test prevents propagating values based on previously set values,
296 which can be incorrect if a variable is modified in a loop. */
298 static int nonzero_sign_valid;
300 /* These arrays are maintained in parallel with reg_last_set_value
301 and are used to store the mode in which the register was last set,
302 the bits that were known to be zero when it was last set, and the
303 number of sign bits copies it was known to have when it was last set. */
305 static enum machine_mode *reg_last_set_mode;
306 static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits;
307 static char *reg_last_set_sign_bit_copies;
309 /* Record one modification to rtl structure
310 to be undone by storing old_contents into *where.
311 is_int is 1 if the contents are an int. */
317 union {rtx r; int i;} old_contents;
318 union {rtx *r; int *i;} where;
321 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
322 num_undo says how many are currently recorded.
324 other_insn is nonzero if we have modified some other insn in the process
325 of working on subst_insn. It must be verified too. */
334 static struct undobuf undobuf;
336 /* Number of times the pseudo being substituted for
337 was found and replaced. */
339 static int n_occurrences;
341 static void do_SUBST (rtx *, rtx);
342 static void do_SUBST_INT (int *, int);
343 static void init_reg_last_arrays (void);
344 static void setup_incoming_promotions (void);
345 static void set_nonzero_bits_and_sign_copies (rtx, rtx, void *);
346 static int cant_combine_insn_p (rtx);
347 static int can_combine_p (rtx, rtx, rtx, rtx, rtx *, rtx *);
348 static int combinable_i3pat (rtx, rtx *, rtx, rtx, int, rtx *);
349 static int contains_muldiv (rtx);
350 static rtx try_combine (rtx, rtx, rtx, int *);
351 static void undo_all (void);
352 static void undo_commit (void);
353 static rtx *find_split_point (rtx *, rtx);
354 static rtx subst (rtx, rtx, rtx, int, int);
355 static rtx combine_simplify_rtx (rtx, enum machine_mode, int, int);
356 static rtx simplify_if_then_else (rtx);
357 static rtx simplify_set (rtx);
358 static rtx simplify_logical (rtx, int);
359 static rtx expand_compound_operation (rtx);
360 static rtx expand_field_assignment (rtx);
361 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
362 rtx, unsigned HOST_WIDE_INT, int, int, int);
363 static rtx extract_left_shift (rtx, int);
364 static rtx make_compound_operation (rtx, enum rtx_code);
365 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
366 unsigned HOST_WIDE_INT *);
367 static rtx force_to_mode (rtx, enum machine_mode,
368 unsigned HOST_WIDE_INT, rtx, int);
369 static rtx if_then_else_cond (rtx, rtx *, rtx *);
370 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
371 static int rtx_equal_for_field_assignment_p (rtx, rtx);
372 static rtx make_field_assignment (rtx);
373 static rtx apply_distributive_law (rtx);
374 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
375 unsigned HOST_WIDE_INT);
376 static unsigned HOST_WIDE_INT cached_nonzero_bits (rtx, enum machine_mode,
377 rtx, enum machine_mode,
378 unsigned HOST_WIDE_INT);
379 static unsigned HOST_WIDE_INT nonzero_bits1 (rtx, enum machine_mode, rtx,
381 unsigned HOST_WIDE_INT);
382 static unsigned int cached_num_sign_bit_copies (rtx, enum machine_mode, rtx,
385 static unsigned int num_sign_bit_copies1 (rtx, enum machine_mode, rtx,
386 enum machine_mode, unsigned int);
387 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
388 HOST_WIDE_INT, enum machine_mode, int *);
389 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
391 static int recog_for_combine (rtx *, rtx, rtx *);
392 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
393 static rtx gen_binary (enum rtx_code, enum machine_mode, rtx, rtx);
394 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
395 static void update_table_tick (rtx);
396 static void record_value_for_reg (rtx, rtx, rtx);
397 static void check_promoted_subreg (rtx, rtx);
398 static void record_dead_and_set_regs_1 (rtx, rtx, void *);
399 static void record_dead_and_set_regs (rtx);
400 static int get_last_value_validate (rtx *, rtx, int, int);
401 static rtx get_last_value (rtx);
402 static int use_crosses_set_p (rtx, int);
403 static void reg_dead_at_p_1 (rtx, rtx, void *);
404 static int reg_dead_at_p (rtx, rtx);
405 static void move_deaths (rtx, rtx, int, rtx, rtx *);
406 static int reg_bitfield_target_p (rtx, rtx);
407 static void distribute_notes (rtx, rtx, rtx, rtx);
408 static void distribute_links (rtx);
409 static void mark_used_regs_combine (rtx);
410 static int insn_cuid (rtx);
411 static void record_promoted_value (rtx, rtx);
412 static rtx reversed_comparison (rtx, enum machine_mode, rtx, rtx);
413 static enum rtx_code combine_reversed_comparison_code (rtx);
415 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
416 insn. The substitution can be undone by undo_all. If INTO is already
417 set to NEWVAL, do not record this change. Because computing NEWVAL might
418 also call SUBST, we have to compute it before we put anything into
422 do_SUBST (rtx *into, rtx newval)
427 if (oldval == newval)
430 /* We'd like to catch as many invalid transformations here as
431 possible. Unfortunately, there are way too many mode changes
432 that are perfectly valid, so we'd waste too much effort for
433 little gain doing the checks here. Focus on catching invalid
434 transformations involving integer constants. */
435 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
436 && GET_CODE (newval) == CONST_INT)
438 /* Sanity check that we're replacing oldval with a CONST_INT
439 that is a valid sign-extension for the original mode. */
440 if (INTVAL (newval) != trunc_int_for_mode (INTVAL (newval),
444 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
445 CONST_INT is not valid, because after the replacement, the
446 original mode would be gone. Unfortunately, we can't tell
447 when do_SUBST is called to replace the operand thereof, so we
448 perform this test on oldval instead, checking whether an
449 invalid replacement took place before we got here. */
450 if ((GET_CODE (oldval) == SUBREG
451 && GET_CODE (SUBREG_REG (oldval)) == CONST_INT)
452 || (GET_CODE (oldval) == ZERO_EXTEND
453 && GET_CODE (XEXP (oldval, 0)) == CONST_INT))
458 buf = undobuf.frees, undobuf.frees = buf->next;
460 buf = xmalloc (sizeof (struct undo));
464 buf->old_contents.r = oldval;
467 buf->next = undobuf.undos, undobuf.undos = buf;
470 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
472 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
473 for the value of a HOST_WIDE_INT value (including CONST_INT) is
477 do_SUBST_INT (int *into, int newval)
482 if (oldval == newval)
486 buf = undobuf.frees, undobuf.frees = buf->next;
488 buf = xmalloc (sizeof (struct undo));
492 buf->old_contents.i = oldval;
495 buf->next = undobuf.undos, undobuf.undos = buf;
498 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
500 /* Main entry point for combiner. F is the first insn of the function.
501 NREGS is the first unused pseudo-reg number.
503 Return nonzero if the combiner has turned an indirect jump
504 instruction into a direct jump. */
506 combine_instructions (rtx f, unsigned int nregs)
513 rtx links, nextlinks;
515 int new_direct_jump_p = 0;
517 combine_attempts = 0;
520 combine_successes = 0;
522 combine_max_regno = nregs;
524 /* It is not safe to use ordinary gen_lowpart in combine.
525 See comments in gen_lowpart_for_combine. */
526 gen_lowpart = gen_lowpart_for_combine;
528 reg_nonzero_bits = xcalloc (nregs, sizeof (unsigned HOST_WIDE_INT));
529 reg_sign_bit_copies = xcalloc (nregs, sizeof (unsigned char));
531 reg_last_death = xmalloc (nregs * sizeof (rtx));
532 reg_last_set = xmalloc (nregs * sizeof (rtx));
533 reg_last_set_value = xmalloc (nregs * sizeof (rtx));
534 reg_last_set_table_tick = xmalloc (nregs * sizeof (int));
535 reg_last_set_label = xmalloc (nregs * sizeof (int));
536 reg_last_set_invalid = xmalloc (nregs * sizeof (char));
537 reg_last_set_mode = xmalloc (nregs * sizeof (enum machine_mode));
538 reg_last_set_nonzero_bits = xmalloc (nregs * sizeof (HOST_WIDE_INT));
539 reg_last_set_sign_bit_copies = xmalloc (nregs * sizeof (char));
541 init_reg_last_arrays ();
543 init_recog_no_volatile ();
545 /* Compute maximum uid value so uid_cuid can be allocated. */
547 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
548 if (INSN_UID (insn) > i)
551 uid_cuid = xmalloc ((i + 1) * sizeof (int));
554 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
556 /* Don't use reg_nonzero_bits when computing it. This can cause problems
557 when, for example, we have j <<= 1 in a loop. */
559 nonzero_sign_valid = 0;
561 /* Compute the mapping from uids to cuids.
562 Cuids are numbers assigned to insns, like uids,
563 except that cuids increase monotonically through the code.
565 Scan all SETs and see if we can deduce anything about what
566 bits are known to be zero for some registers and how many copies
567 of the sign bit are known to exist for those registers.
569 Also set any known values so that we can use it while searching
570 for what bits are known to be set. */
574 setup_incoming_promotions ();
576 refresh_blocks = sbitmap_alloc (last_basic_block);
577 sbitmap_zero (refresh_blocks);
579 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
581 uid_cuid[INSN_UID (insn)] = ++i;
587 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
589 record_dead_and_set_regs (insn);
592 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
593 if (REG_NOTE_KIND (links) == REG_INC)
594 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
599 if (GET_CODE (insn) == CODE_LABEL)
603 nonzero_sign_valid = 1;
605 /* Now scan all the insns in forward order. */
610 init_reg_last_arrays ();
611 setup_incoming_promotions ();
613 FOR_EACH_BB (this_basic_block)
615 for (insn = BB_HEAD (this_basic_block);
616 insn != NEXT_INSN (BB_END (this_basic_block));
617 insn = next ? next : NEXT_INSN (insn))
621 if (GET_CODE (insn) == CODE_LABEL)
624 else if (INSN_P (insn))
626 /* See if we know about function return values before this
627 insn based upon SUBREG flags. */
628 check_promoted_subreg (insn, PATTERN (insn));
630 /* Try this insn with each insn it links back to. */
632 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
633 if ((next = try_combine (insn, XEXP (links, 0),
634 NULL_RTX, &new_direct_jump_p)) != 0)
637 /* Try each sequence of three linked insns ending with this one. */
639 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
641 rtx link = XEXP (links, 0);
643 /* If the linked insn has been replaced by a note, then there
644 is no point in pursuing this chain any further. */
645 if (GET_CODE (link) == NOTE)
648 for (nextlinks = LOG_LINKS (link);
650 nextlinks = XEXP (nextlinks, 1))
651 if ((next = try_combine (insn, link,
653 &new_direct_jump_p)) != 0)
658 /* Try to combine a jump insn that uses CC0
659 with a preceding insn that sets CC0, and maybe with its
660 logical predecessor as well.
661 This is how we make decrement-and-branch insns.
662 We need this special code because data flow connections
663 via CC0 do not get entered in LOG_LINKS. */
665 if (GET_CODE (insn) == JUMP_INSN
666 && (prev = prev_nonnote_insn (insn)) != 0
667 && GET_CODE (prev) == INSN
668 && sets_cc0_p (PATTERN (prev)))
670 if ((next = try_combine (insn, prev,
671 NULL_RTX, &new_direct_jump_p)) != 0)
674 for (nextlinks = LOG_LINKS (prev); nextlinks;
675 nextlinks = XEXP (nextlinks, 1))
676 if ((next = try_combine (insn, prev,
678 &new_direct_jump_p)) != 0)
682 /* Do the same for an insn that explicitly references CC0. */
683 if (GET_CODE (insn) == INSN
684 && (prev = prev_nonnote_insn (insn)) != 0
685 && GET_CODE (prev) == INSN
686 && sets_cc0_p (PATTERN (prev))
687 && GET_CODE (PATTERN (insn)) == SET
688 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
690 if ((next = try_combine (insn, prev,
691 NULL_RTX, &new_direct_jump_p)) != 0)
694 for (nextlinks = LOG_LINKS (prev); nextlinks;
695 nextlinks = XEXP (nextlinks, 1))
696 if ((next = try_combine (insn, prev,
698 &new_direct_jump_p)) != 0)
702 /* Finally, see if any of the insns that this insn links to
703 explicitly references CC0. If so, try this insn, that insn,
704 and its predecessor if it sets CC0. */
705 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
706 if (GET_CODE (XEXP (links, 0)) == INSN
707 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
708 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
709 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
710 && GET_CODE (prev) == INSN
711 && sets_cc0_p (PATTERN (prev))
712 && (next = try_combine (insn, XEXP (links, 0),
713 prev, &new_direct_jump_p)) != 0)
717 /* Try combining an insn with two different insns whose results it
719 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
720 for (nextlinks = XEXP (links, 1); nextlinks;
721 nextlinks = XEXP (nextlinks, 1))
722 if ((next = try_combine (insn, XEXP (links, 0),
724 &new_direct_jump_p)) != 0)
727 if (GET_CODE (insn) != NOTE)
728 record_dead_and_set_regs (insn);
737 EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks, 0, i,
738 BASIC_BLOCK (i)->flags |= BB_DIRTY);
739 new_direct_jump_p |= purge_all_dead_edges (0);
740 delete_noop_moves (f);
742 update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES,
743 PROP_DEATH_NOTES | PROP_SCAN_DEAD_CODE
744 | PROP_KILL_DEAD_CODE);
747 sbitmap_free (refresh_blocks);
748 free (reg_nonzero_bits);
749 free (reg_sign_bit_copies);
750 free (reg_last_death);
752 free (reg_last_set_value);
753 free (reg_last_set_table_tick);
754 free (reg_last_set_label);
755 free (reg_last_set_invalid);
756 free (reg_last_set_mode);
757 free (reg_last_set_nonzero_bits);
758 free (reg_last_set_sign_bit_copies);
762 struct undo *undo, *next;
763 for (undo = undobuf.frees; undo; undo = next)
771 total_attempts += combine_attempts;
772 total_merges += combine_merges;
773 total_extras += combine_extras;
774 total_successes += combine_successes;
776 nonzero_sign_valid = 0;
777 gen_lowpart = gen_lowpart_general;
779 /* Make recognizer allow volatile MEMs again. */
782 return new_direct_jump_p;
785 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
788 init_reg_last_arrays (void)
790 unsigned int nregs = combine_max_regno;
792 memset (reg_last_death, 0, nregs * sizeof (rtx));
793 memset (reg_last_set, 0, nregs * sizeof (rtx));
794 memset (reg_last_set_value, 0, nregs * sizeof (rtx));
795 memset (reg_last_set_table_tick, 0, nregs * sizeof (int));
796 memset (reg_last_set_label, 0, nregs * sizeof (int));
797 memset (reg_last_set_invalid, 0, nregs * sizeof (char));
798 memset (reg_last_set_mode, 0, nregs * sizeof (enum machine_mode));
799 memset (reg_last_set_nonzero_bits, 0, nregs * sizeof (HOST_WIDE_INT));
800 memset (reg_last_set_sign_bit_copies, 0, nregs * sizeof (char));
803 /* Set up any promoted values for incoming argument registers. */
806 setup_incoming_promotions (void)
810 enum machine_mode mode;
812 rtx first = get_insns ();
814 if (targetm.calls.promote_function_args (TREE_TYPE (cfun->decl)))
816 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
817 /* Check whether this register can hold an incoming pointer
818 argument. FUNCTION_ARG_REGNO_P tests outgoing register
819 numbers, so translate if necessary due to register windows. */
820 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno))
821 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
824 (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
827 gen_rtx_CLOBBER (mode, const0_rtx)));
832 /* Called via note_stores. If X is a pseudo that is narrower than
833 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
835 If we are setting only a portion of X and we can't figure out what
836 portion, assume all bits will be used since we don't know what will
839 Similarly, set how many bits of X are known to be copies of the sign bit
840 at all locations in the function. This is the smallest number implied
844 set_nonzero_bits_and_sign_copies (rtx x, rtx set,
845 void *data ATTRIBUTE_UNUSED)
849 if (GET_CODE (x) == REG
850 && REGNO (x) >= FIRST_PSEUDO_REGISTER
851 /* If this register is undefined at the start of the file, we can't
852 say what its contents were. */
853 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, REGNO (x))
854 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
856 if (set == 0 || GET_CODE (set) == CLOBBER)
858 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
859 reg_sign_bit_copies[REGNO (x)] = 1;
863 /* If this is a complex assignment, see if we can convert it into a
864 simple assignment. */
865 set = expand_field_assignment (set);
867 /* If this is a simple assignment, or we have a paradoxical SUBREG,
868 set what we know about X. */
870 if (SET_DEST (set) == x
871 || (GET_CODE (SET_DEST (set)) == SUBREG
872 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
873 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
874 && SUBREG_REG (SET_DEST (set)) == x))
876 rtx src = SET_SRC (set);
878 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
879 /* If X is narrower than a word and SRC is a non-negative
880 constant that would appear negative in the mode of X,
881 sign-extend it for use in reg_nonzero_bits because some
882 machines (maybe most) will actually do the sign-extension
883 and this is the conservative approach.
885 ??? For 2.5, try to tighten up the MD files in this regard
886 instead of this kludge. */
888 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
889 && GET_CODE (src) == CONST_INT
891 && 0 != (INTVAL (src)
893 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
894 src = GEN_INT (INTVAL (src)
895 | ((HOST_WIDE_INT) (-1)
896 << GET_MODE_BITSIZE (GET_MODE (x))));
899 /* Don't call nonzero_bits if it cannot change anything. */
900 if (reg_nonzero_bits[REGNO (x)] != ~(unsigned HOST_WIDE_INT) 0)
901 reg_nonzero_bits[REGNO (x)]
902 |= nonzero_bits (src, nonzero_bits_mode);
903 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
904 if (reg_sign_bit_copies[REGNO (x)] == 0
905 || reg_sign_bit_copies[REGNO (x)] > num)
906 reg_sign_bit_copies[REGNO (x)] = num;
910 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
911 reg_sign_bit_copies[REGNO (x)] = 1;
916 /* See if INSN can be combined into I3. PRED and SUCC are optionally
917 insns that were previously combined into I3 or that will be combined
918 into the merger of INSN and I3.
920 Return 0 if the combination is not allowed for any reason.
922 If the combination is allowed, *PDEST will be set to the single
923 destination of INSN and *PSRC to the single source, and this function
927 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED, rtx succ,
928 rtx *pdest, rtx *psrc)
931 rtx set = 0, src, dest;
936 int all_adjacent = (succ ? (next_active_insn (insn) == succ
937 && next_active_insn (succ) == i3)
938 : next_active_insn (insn) == i3);
940 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
941 or a PARALLEL consisting of such a SET and CLOBBERs.
943 If INSN has CLOBBER parallel parts, ignore them for our processing.
944 By definition, these happen during the execution of the insn. When it
945 is merged with another insn, all bets are off. If they are, in fact,
946 needed and aren't also supplied in I3, they may be added by
947 recog_for_combine. Otherwise, it won't match.
949 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
952 Get the source and destination of INSN. If more than one, can't
955 if (GET_CODE (PATTERN (insn)) == SET)
956 set = PATTERN (insn);
957 else if (GET_CODE (PATTERN (insn)) == PARALLEL
958 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
960 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
962 rtx elt = XVECEXP (PATTERN (insn), 0, i);
964 switch (GET_CODE (elt))
966 /* This is important to combine floating point insns
969 /* Combining an isolated USE doesn't make sense.
970 We depend here on combinable_i3pat to reject them. */
971 /* The code below this loop only verifies that the inputs of
972 the SET in INSN do not change. We call reg_set_between_p
973 to verify that the REG in the USE does not change between
975 If the USE in INSN was for a pseudo register, the matching
976 insn pattern will likely match any register; combining this
977 with any other USE would only be safe if we knew that the
978 used registers have identical values, or if there was
979 something to tell them apart, e.g. different modes. For
980 now, we forgo such complicated tests and simply disallow
981 combining of USES of pseudo registers with any other USE. */
982 if (GET_CODE (XEXP (elt, 0)) == REG
983 && GET_CODE (PATTERN (i3)) == PARALLEL)
985 rtx i3pat = PATTERN (i3);
986 int i = XVECLEN (i3pat, 0) - 1;
987 unsigned int regno = REGNO (XEXP (elt, 0));
991 rtx i3elt = XVECEXP (i3pat, 0, i);
993 if (GET_CODE (i3elt) == USE
994 && GET_CODE (XEXP (i3elt, 0)) == REG
995 && (REGNO (XEXP (i3elt, 0)) == regno
996 ? reg_set_between_p (XEXP (elt, 0),
997 PREV_INSN (insn), i3)
998 : regno >= FIRST_PSEUDO_REGISTER))
1005 /* We can ignore CLOBBERs. */
1010 /* Ignore SETs whose result isn't used but not those that
1011 have side-effects. */
1012 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1013 && ! side_effects_p (elt))
1016 /* If we have already found a SET, this is a second one and
1017 so we cannot combine with this insn. */
1025 /* Anything else means we can't combine. */
1031 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1032 so don't do anything with it. */
1033 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1042 set = expand_field_assignment (set);
1043 src = SET_SRC (set), dest = SET_DEST (set);
1045 /* Don't eliminate a store in the stack pointer. */
1046 if (dest == stack_pointer_rtx
1047 /* Don't combine with an insn that sets a register to itself if it has
1048 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1049 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1050 /* Can't merge an ASM_OPERANDS. */
1051 || GET_CODE (src) == ASM_OPERANDS
1052 /* Can't merge a function call. */
1053 || GET_CODE (src) == CALL
1054 /* Don't eliminate a function call argument. */
1055 || (GET_CODE (i3) == CALL_INSN
1056 && (find_reg_fusage (i3, USE, dest)
1057 || (GET_CODE (dest) == REG
1058 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1059 && global_regs[REGNO (dest)])))
1060 /* Don't substitute into an incremented register. */
1061 || FIND_REG_INC_NOTE (i3, dest)
1062 || (succ && FIND_REG_INC_NOTE (succ, dest))
1064 /* Don't combine the end of a libcall into anything. */
1065 /* ??? This gives worse code, and appears to be unnecessary, since no
1066 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1067 use REG_RETVAL notes for noconflict blocks, but other code here
1068 makes sure that those insns don't disappear. */
1069 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
1071 /* Make sure that DEST is not used after SUCC but before I3. */
1072 || (succ && ! all_adjacent
1073 && reg_used_between_p (dest, succ, i3))
1074 /* Make sure that the value that is to be substituted for the register
1075 does not use any registers whose values alter in between. However,
1076 If the insns are adjacent, a use can't cross a set even though we
1077 think it might (this can happen for a sequence of insns each setting
1078 the same destination; reg_last_set of that register might point to
1079 a NOTE). If INSN has a REG_EQUIV note, the register is always
1080 equivalent to the memory so the substitution is valid even if there
1081 are intervening stores. Also, don't move a volatile asm or
1082 UNSPEC_VOLATILE across any other insns. */
1084 && (((GET_CODE (src) != MEM
1085 || ! find_reg_note (insn, REG_EQUIV, src))
1086 && use_crosses_set_p (src, INSN_CUID (insn)))
1087 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1088 || GET_CODE (src) == UNSPEC_VOLATILE))
1089 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1090 better register allocation by not doing the combine. */
1091 || find_reg_note (i3, REG_NO_CONFLICT, dest)
1092 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
1093 /* Don't combine across a CALL_INSN, because that would possibly
1094 change whether the life span of some REGs crosses calls or not,
1095 and it is a pain to update that information.
1096 Exception: if source is a constant, moving it later can't hurt.
1097 Accept that special case, because it helps -fforce-addr a lot. */
1098 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
1101 /* DEST must either be a REG or CC0. */
1102 if (GET_CODE (dest) == REG)
1104 /* If register alignment is being enforced for multi-word items in all
1105 cases except for parameters, it is possible to have a register copy
1106 insn referencing a hard register that is not allowed to contain the
1107 mode being copied and which would not be valid as an operand of most
1108 insns. Eliminate this problem by not combining with such an insn.
1110 Also, on some machines we don't want to extend the life of a hard
1113 if (GET_CODE (src) == REG
1114 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1115 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1116 /* Don't extend the life of a hard register unless it is
1117 user variable (if we have few registers) or it can't
1118 fit into the desired register (meaning something special
1120 Also avoid substituting a return register into I3, because
1121 reload can't handle a conflict with constraints of other
1123 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1124 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1127 else if (GET_CODE (dest) != CC0)
1130 /* Don't substitute for a register intended as a clobberable operand.
1131 Similarly, don't substitute an expression containing a register that
1132 will be clobbered in I3. */
1133 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1134 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1135 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
1136 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0),
1138 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)))
1141 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1142 or not), reject, unless nothing volatile comes between it and I3 */
1144 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1146 /* Make sure succ doesn't contain a volatile reference. */
1147 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1150 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1151 if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1155 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1156 to be an explicit register variable, and was chosen for a reason. */
1158 if (GET_CODE (src) == ASM_OPERANDS
1159 && GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1162 /* If there are any volatile insns between INSN and I3, reject, because
1163 they might affect machine state. */
1165 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1166 if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1169 /* If INSN or I2 contains an autoincrement or autodecrement,
1170 make sure that register is not used between there and I3,
1171 and not already used in I3 either.
1172 Also insist that I3 not be a jump; if it were one
1173 and the incremented register were spilled, we would lose. */
1176 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1177 if (REG_NOTE_KIND (link) == REG_INC
1178 && (GET_CODE (i3) == JUMP_INSN
1179 || reg_used_between_p (XEXP (link, 0), insn, i3)
1180 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1185 /* Don't combine an insn that follows a CC0-setting insn.
1186 An insn that uses CC0 must not be separated from the one that sets it.
1187 We do, however, allow I2 to follow a CC0-setting insn if that insn
1188 is passed as I1; in that case it will be deleted also.
1189 We also allow combining in this case if all the insns are adjacent
1190 because that would leave the two CC0 insns adjacent as well.
1191 It would be more logical to test whether CC0 occurs inside I1 or I2,
1192 but that would be much slower, and this ought to be equivalent. */
1194 p = prev_nonnote_insn (insn);
1195 if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
1200 /* If we get here, we have passed all the tests and the combination is
1209 /* LOC is the location within I3 that contains its pattern or the component
1210 of a PARALLEL of the pattern. We validate that it is valid for combining.
1212 One problem is if I3 modifies its output, as opposed to replacing it
1213 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1214 so would produce an insn that is not equivalent to the original insns.
1218 (set (reg:DI 101) (reg:DI 100))
1219 (set (subreg:SI (reg:DI 101) 0) <foo>)
1221 This is NOT equivalent to:
1223 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1224 (set (reg:DI 101) (reg:DI 100))])
1226 Not only does this modify 100 (in which case it might still be valid
1227 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1229 We can also run into a problem if I2 sets a register that I1
1230 uses and I1 gets directly substituted into I3 (not via I2). In that
1231 case, we would be getting the wrong value of I2DEST into I3, so we
1232 must reject the combination. This case occurs when I2 and I1 both
1233 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1234 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1235 of a SET must prevent combination from occurring.
1237 Before doing the above check, we first try to expand a field assignment
1238 into a set of logical operations.
1240 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1241 we place a register that is both set and used within I3. If more than one
1242 such register is detected, we fail.
1244 Return 1 if the combination is valid, zero otherwise. */
1247 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest,
1248 int i1_not_in_src, rtx *pi3dest_killed)
1252 if (GET_CODE (x) == SET)
1255 rtx dest = SET_DEST (set);
1256 rtx src = SET_SRC (set);
1257 rtx inner_dest = dest;
1259 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1260 || GET_CODE (inner_dest) == SUBREG
1261 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1262 inner_dest = XEXP (inner_dest, 0);
1264 /* Check for the case where I3 modifies its output, as discussed
1265 above. We don't want to prevent pseudos from being combined
1266 into the address of a MEM, so only prevent the combination if
1267 i1 or i2 set the same MEM. */
1268 if ((inner_dest != dest &&
1269 (GET_CODE (inner_dest) != MEM
1270 || rtx_equal_p (i2dest, inner_dest)
1271 || (i1dest && rtx_equal_p (i1dest, inner_dest)))
1272 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1273 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1275 /* This is the same test done in can_combine_p except we can't test
1276 all_adjacent; we don't have to, since this instruction will stay
1277 in place, thus we are not considering increasing the lifetime of
1280 Also, if this insn sets a function argument, combining it with
1281 something that might need a spill could clobber a previous
1282 function argument; the all_adjacent test in can_combine_p also
1283 checks this; here, we do a more specific test for this case. */
1285 || (GET_CODE (inner_dest) == REG
1286 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1287 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1288 GET_MODE (inner_dest))))
1289 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1292 /* If DEST is used in I3, it is being killed in this insn,
1293 so record that for later.
1294 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1295 STACK_POINTER_REGNUM, since these are always considered to be
1296 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1297 if (pi3dest_killed && GET_CODE (dest) == REG
1298 && reg_referenced_p (dest, PATTERN (i3))
1299 && REGNO (dest) != FRAME_POINTER_REGNUM
1300 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1301 && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
1303 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1304 && (REGNO (dest) != ARG_POINTER_REGNUM
1305 || ! fixed_regs [REGNO (dest)])
1307 && REGNO (dest) != STACK_POINTER_REGNUM)
1309 if (*pi3dest_killed)
1312 *pi3dest_killed = dest;
1316 else if (GET_CODE (x) == PARALLEL)
1320 for (i = 0; i < XVECLEN (x, 0); i++)
1321 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1322 i1_not_in_src, pi3dest_killed))
1329 /* Return 1 if X is an arithmetic expression that contains a multiplication
1330 and division. We don't count multiplications by powers of two here. */
1333 contains_muldiv (rtx x)
1335 switch (GET_CODE (x))
1337 case MOD: case DIV: case UMOD: case UDIV:
1341 return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1342 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1344 switch (GET_RTX_CLASS (GET_CODE (x)))
1346 case 'c': case '<': case '2':
1347 return contains_muldiv (XEXP (x, 0))
1348 || contains_muldiv (XEXP (x, 1));
1351 return contains_muldiv (XEXP (x, 0));
1359 /* Determine whether INSN can be used in a combination. Return nonzero if
1360 not. This is used in try_combine to detect early some cases where we
1361 can't perform combinations. */
1364 cant_combine_insn_p (rtx insn)
1369 /* If this isn't really an insn, we can't do anything.
1370 This can occur when flow deletes an insn that it has merged into an
1371 auto-increment address. */
1372 if (! INSN_P (insn))
1375 /* Never combine loads and stores involving hard regs that are likely
1376 to be spilled. The register allocator can usually handle such
1377 reg-reg moves by tying. If we allow the combiner to make
1378 substitutions of likely-spilled regs, we may abort in reload.
1379 As an exception, we allow combinations involving fixed regs; these are
1380 not available to the register allocator so there's no risk involved. */
1382 set = single_set (insn);
1385 src = SET_SRC (set);
1386 dest = SET_DEST (set);
1387 if (GET_CODE (src) == SUBREG)
1388 src = SUBREG_REG (src);
1389 if (GET_CODE (dest) == SUBREG)
1390 dest = SUBREG_REG (dest);
1391 if (REG_P (src) && REG_P (dest)
1392 && ((REGNO (src) < FIRST_PSEUDO_REGISTER
1393 && ! fixed_regs[REGNO (src)]
1394 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src))))
1395 || (REGNO (dest) < FIRST_PSEUDO_REGISTER
1396 && ! fixed_regs[REGNO (dest)]
1397 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest))))))
1403 /* Adjust INSN after we made a change to its destination.
1405 Changing the destination can invalidate notes that say something about
1406 the results of the insn and a LOG_LINK pointing to the insn. */
1409 adjust_for_new_dest (rtx insn)
1413 /* For notes, be conservative and simply remove them. */
1414 loc = ®_NOTES (insn);
1417 enum reg_note kind = REG_NOTE_KIND (*loc);
1418 if (kind == REG_EQUAL || kind == REG_EQUIV)
1419 *loc = XEXP (*loc, 1);
1421 loc = &XEXP (*loc, 1);
1424 /* The new insn will have a destination that was previously the destination
1425 of an insn just above it. Call distribute_links to make a LOG_LINK from
1426 the next use of that destination. */
1427 distribute_links (gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX));
1430 /* Try to combine the insns I1 and I2 into I3.
1431 Here I1 and I2 appear earlier than I3.
1432 I1 can be zero; then we combine just I2 into I3.
1434 If we are combining three insns and the resulting insn is not recognized,
1435 try splitting it into two insns. If that happens, I2 and I3 are retained
1436 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1439 Return 0 if the combination does not work. Then nothing is changed.
1440 If we did the combination, return the insn at which combine should
1443 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
1444 new direct jump instruction. */
1447 try_combine (rtx i3, rtx i2, rtx i1, int *new_direct_jump_p)
1449 /* New patterns for I3 and I2, respectively. */
1450 rtx newpat, newi2pat = 0;
1451 int substed_i2 = 0, substed_i1 = 0;
1452 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1453 int added_sets_1, added_sets_2;
1454 /* Total number of SETs to put into I3. */
1456 /* Nonzero is I2's body now appears in I3. */
1458 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1459 int insn_code_number, i2_code_number = 0, other_code_number = 0;
1460 /* Contains I3 if the destination of I3 is used in its source, which means
1461 that the old life of I3 is being killed. If that usage is placed into
1462 I2 and not in I3, a REG_DEAD note must be made. */
1463 rtx i3dest_killed = 0;
1464 /* SET_DEST and SET_SRC of I2 and I1. */
1465 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1466 /* PATTERN (I2), or a copy of it in certain cases. */
1468 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1469 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1470 int i1_feeds_i3 = 0;
1471 /* Notes that must be added to REG_NOTES in I3 and I2. */
1472 rtx new_i3_notes, new_i2_notes;
1473 /* Notes that we substituted I3 into I2 instead of the normal case. */
1474 int i3_subst_into_i2 = 0;
1475 /* Notes that I1, I2 or I3 is a MULT operation. */
1483 /* Exit early if one of the insns involved can't be used for
1485 if (cant_combine_insn_p (i3)
1486 || cant_combine_insn_p (i2)
1487 || (i1 && cant_combine_insn_p (i1))
1488 /* We also can't do anything if I3 has a
1489 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1492 /* ??? This gives worse code, and appears to be unnecessary, since no
1493 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1494 || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1500 undobuf.other_insn = 0;
1502 /* Reset the hard register usage information. */
1503 CLEAR_HARD_REG_SET (newpat_used_regs);
1505 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1506 code below, set I1 to be the earlier of the two insns. */
1507 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1508 temp = i1, i1 = i2, i2 = temp;
1510 added_links_insn = 0;
1512 /* First check for one important special-case that the code below will
1513 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1514 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1515 we may be able to replace that destination with the destination of I3.
1516 This occurs in the common code where we compute both a quotient and
1517 remainder into a structure, in which case we want to do the computation
1518 directly into the structure to avoid register-register copies.
1520 Note that this case handles both multiple sets in I2 and also
1521 cases where I2 has a number of CLOBBER or PARALLELs.
1523 We make very conservative checks below and only try to handle the
1524 most common cases of this. For example, we only handle the case
1525 where I2 and I3 are adjacent to avoid making difficult register
1528 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1529 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1530 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1531 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1532 && GET_CODE (PATTERN (i2)) == PARALLEL
1533 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1534 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1535 below would need to check what is inside (and reg_overlap_mentioned_p
1536 doesn't support those codes anyway). Don't allow those destinations;
1537 the resulting insn isn't likely to be recognized anyway. */
1538 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1539 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1540 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1541 SET_DEST (PATTERN (i3)))
1542 && next_real_insn (i2) == i3)
1544 rtx p2 = PATTERN (i2);
1546 /* Make sure that the destination of I3,
1547 which we are going to substitute into one output of I2,
1548 is not used within another output of I2. We must avoid making this:
1549 (parallel [(set (mem (reg 69)) ...)
1550 (set (reg 69) ...)])
1551 which is not well-defined as to order of actions.
1552 (Besides, reload can't handle output reloads for this.)
1554 The problem can also happen if the dest of I3 is a memory ref,
1555 if another dest in I2 is an indirect memory ref. */
1556 for (i = 0; i < XVECLEN (p2, 0); i++)
1557 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1558 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1559 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1560 SET_DEST (XVECEXP (p2, 0, i))))
1563 if (i == XVECLEN (p2, 0))
1564 for (i = 0; i < XVECLEN (p2, 0); i++)
1565 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1566 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1567 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1572 subst_low_cuid = INSN_CUID (i2);
1574 added_sets_2 = added_sets_1 = 0;
1575 i2dest = SET_SRC (PATTERN (i3));
1577 /* Replace the dest in I2 with our dest and make the resulting
1578 insn the new pattern for I3. Then skip to where we
1579 validate the pattern. Everything was set up above. */
1580 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1581 SET_DEST (PATTERN (i3)));
1584 i3_subst_into_i2 = 1;
1585 goto validate_replacement;
1589 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1590 one of those words to another constant, merge them by making a new
1593 && (temp = single_set (i2)) != 0
1594 && (GET_CODE (SET_SRC (temp)) == CONST_INT
1595 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
1596 && GET_CODE (SET_DEST (temp)) == REG
1597 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp))) == MODE_INT
1598 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp))) == 2 * UNITS_PER_WORD
1599 && GET_CODE (PATTERN (i3)) == SET
1600 && GET_CODE (SET_DEST (PATTERN (i3))) == SUBREG
1601 && SUBREG_REG (SET_DEST (PATTERN (i3))) == SET_DEST (temp)
1602 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3)))) == MODE_INT
1603 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3)))) == UNITS_PER_WORD
1604 && GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT)
1606 HOST_WIDE_INT lo, hi;
1608 if (GET_CODE (SET_SRC (temp)) == CONST_INT)
1609 lo = INTVAL (SET_SRC (temp)), hi = lo < 0 ? -1 : 0;
1612 lo = CONST_DOUBLE_LOW (SET_SRC (temp));
1613 hi = CONST_DOUBLE_HIGH (SET_SRC (temp));
1616 if (subreg_lowpart_p (SET_DEST (PATTERN (i3))))
1618 /* We don't handle the case of the target word being wider
1619 than a host wide int. */
1620 if (HOST_BITS_PER_WIDE_INT < BITS_PER_WORD)
1623 lo &= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1624 lo |= (INTVAL (SET_SRC (PATTERN (i3)))
1625 & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1627 else if (HOST_BITS_PER_WIDE_INT == BITS_PER_WORD)
1628 hi = INTVAL (SET_SRC (PATTERN (i3)));
1629 else if (HOST_BITS_PER_WIDE_INT >= 2 * BITS_PER_WORD)
1631 int sign = -(int) ((unsigned HOST_WIDE_INT) lo
1632 >> (HOST_BITS_PER_WIDE_INT - 1));
1634 lo &= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1635 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1636 lo |= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1637 (INTVAL (SET_SRC (PATTERN (i3)))));
1639 hi = lo < 0 ? -1 : 0;
1642 /* We don't handle the case of the higher word not fitting
1643 entirely in either hi or lo. */
1648 subst_low_cuid = INSN_CUID (i2);
1649 added_sets_2 = added_sets_1 = 0;
1650 i2dest = SET_DEST (temp);
1652 SUBST (SET_SRC (temp),
1653 immed_double_const (lo, hi, GET_MODE (SET_DEST (temp))));
1655 newpat = PATTERN (i2);
1656 goto validate_replacement;
1660 /* If we have no I1 and I2 looks like:
1661 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1663 make up a dummy I1 that is
1666 (set (reg:CC X) (compare:CC Y (const_int 0)))
1668 (We can ignore any trailing CLOBBERs.)
1670 This undoes a previous combination and allows us to match a branch-and-
1673 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1674 && XVECLEN (PATTERN (i2), 0) >= 2
1675 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1676 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1678 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1679 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1680 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1681 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1682 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1683 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1685 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1686 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1691 /* We make I1 with the same INSN_UID as I2. This gives it
1692 the same INSN_CUID for value tracking. Our fake I1 will
1693 never appear in the insn stream so giving it the same INSN_UID
1694 as I2 will not cause a problem. */
1696 i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
1697 BLOCK_FOR_INSN (i2), INSN_LOCATOR (i2),
1698 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
1701 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1702 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1703 SET_DEST (PATTERN (i1)));
1708 /* Verify that I2 and I1 are valid for combining. */
1709 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1710 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1716 /* Record whether I2DEST is used in I2SRC and similarly for the other
1717 cases. Knowing this will help in register status updating below. */
1718 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1719 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1720 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1722 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1724 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1726 /* Ensure that I3's pattern can be the destination of combines. */
1727 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1728 i1 && i2dest_in_i1src && i1_feeds_i3,
1735 /* See if any of the insns is a MULT operation. Unless one is, we will
1736 reject a combination that is, since it must be slower. Be conservative
1738 if (GET_CODE (i2src) == MULT
1739 || (i1 != 0 && GET_CODE (i1src) == MULT)
1740 || (GET_CODE (PATTERN (i3)) == SET
1741 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
1744 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1745 We used to do this EXCEPT in one case: I3 has a post-inc in an
1746 output operand. However, that exception can give rise to insns like
1748 which is a famous insn on the PDP-11 where the value of r3 used as the
1749 source was model-dependent. Avoid this sort of thing. */
1752 if (!(GET_CODE (PATTERN (i3)) == SET
1753 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1754 && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1755 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1756 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1757 /* It's not the exception. */
1760 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1761 if (REG_NOTE_KIND (link) == REG_INC
1762 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1764 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1771 /* See if the SETs in I1 or I2 need to be kept around in the merged
1772 instruction: whenever the value set there is still needed past I3.
1773 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1775 For the SET in I1, we have two cases: If I1 and I2 independently
1776 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1777 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1778 in I1 needs to be kept around unless I1DEST dies or is set in either
1779 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1780 I1DEST. If so, we know I1 feeds into I2. */
1782 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1785 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1786 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1788 /* If the set in I2 needs to be kept around, we must make a copy of
1789 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1790 PATTERN (I2), we are only substituting for the original I1DEST, not into
1791 an already-substituted copy. This also prevents making self-referential
1792 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1795 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1796 ? gen_rtx_SET (VOIDmode, i2dest, i2src)
1800 i2pat = copy_rtx (i2pat);
1804 /* Substitute in the latest insn for the regs set by the earlier ones. */
1806 maxreg = max_reg_num ();
1810 /* It is possible that the source of I2 or I1 may be performing an
1811 unneeded operation, such as a ZERO_EXTEND of something that is known
1812 to have the high part zero. Handle that case by letting subst look at
1813 the innermost one of them.
1815 Another way to do this would be to have a function that tries to
1816 simplify a single insn instead of merging two or more insns. We don't
1817 do this because of the potential of infinite loops and because
1818 of the potential extra memory required. However, doing it the way
1819 we are is a bit of a kludge and doesn't catch all cases.
1821 But only do this if -fexpensive-optimizations since it slows things down
1822 and doesn't usually win. */
1824 if (flag_expensive_optimizations)
1826 /* Pass pc_rtx so no substitutions are done, just simplifications.
1827 The cases that we are interested in here do not involve the few
1828 cases were is_replaced is checked. */
1831 subst_low_cuid = INSN_CUID (i1);
1832 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1836 subst_low_cuid = INSN_CUID (i2);
1837 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1842 /* Many machines that don't use CC0 have insns that can both perform an
1843 arithmetic operation and set the condition code. These operations will
1844 be represented as a PARALLEL with the first element of the vector
1845 being a COMPARE of an arithmetic operation with the constant zero.
1846 The second element of the vector will set some pseudo to the result
1847 of the same arithmetic operation. If we simplify the COMPARE, we won't
1848 match such a pattern and so will generate an extra insn. Here we test
1849 for this case, where both the comparison and the operation result are
1850 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1851 I2SRC. Later we will make the PARALLEL that contains I2. */
1853 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1854 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1855 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1856 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1858 #ifdef SELECT_CC_MODE
1860 enum machine_mode compare_mode;
1863 newpat = PATTERN (i3);
1864 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1868 #ifdef SELECT_CC_MODE
1869 /* See if a COMPARE with the operand we substituted in should be done
1870 with the mode that is currently being used. If not, do the same
1871 processing we do in `subst' for a SET; namely, if the destination
1872 is used only once, try to replace it with a register of the proper
1873 mode and also replace the COMPARE. */
1874 if (undobuf.other_insn == 0
1875 && (cc_use = find_single_use (SET_DEST (newpat), i3,
1876 &undobuf.other_insn))
1877 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
1879 != GET_MODE (SET_DEST (newpat))))
1881 unsigned int regno = REGNO (SET_DEST (newpat));
1882 rtx new_dest = gen_rtx_REG (compare_mode, regno);
1884 if (regno < FIRST_PSEUDO_REGISTER
1885 || (REG_N_SETS (regno) == 1 && ! added_sets_2
1886 && ! REG_USERVAR_P (SET_DEST (newpat))))
1888 if (regno >= FIRST_PSEUDO_REGISTER)
1889 SUBST (regno_reg_rtx[regno], new_dest);
1891 SUBST (SET_DEST (newpat), new_dest);
1892 SUBST (XEXP (*cc_use, 0), new_dest);
1893 SUBST (SET_SRC (newpat),
1894 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
1897 undobuf.other_insn = 0;
1904 n_occurrences = 0; /* `subst' counts here */
1906 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1907 need to make a unique copy of I2SRC each time we substitute it
1908 to avoid self-referential rtl. */
1910 subst_low_cuid = INSN_CUID (i2);
1911 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1912 ! i1_feeds_i3 && i1dest_in_i1src);
1915 /* Record whether i2's body now appears within i3's body. */
1916 i2_is_used = n_occurrences;
1919 /* If we already got a failure, don't try to do more. Otherwise,
1920 try to substitute in I1 if we have it. */
1922 if (i1 && GET_CODE (newpat) != CLOBBER)
1924 /* Before we can do this substitution, we must redo the test done
1925 above (see detailed comments there) that ensures that I1DEST
1926 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1928 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
1936 subst_low_cuid = INSN_CUID (i1);
1937 newpat = subst (newpat, i1dest, i1src, 0, 0);
1941 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1942 to count all the ways that I2SRC and I1SRC can be used. */
1943 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
1944 && i2_is_used + added_sets_2 > 1)
1945 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
1946 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
1948 /* Fail if we tried to make a new register (we used to abort, but there's
1949 really no reason to). */
1950 || max_reg_num () != maxreg
1951 /* Fail if we couldn't do something and have a CLOBBER. */
1952 || GET_CODE (newpat) == CLOBBER
1953 /* Fail if this new pattern is a MULT and we didn't have one before
1954 at the outer level. */
1955 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
1962 /* If the actions of the earlier insns must be kept
1963 in addition to substituting them into the latest one,
1964 we must make a new PARALLEL for the latest insn
1965 to hold additional the SETs. */
1967 if (added_sets_1 || added_sets_2)
1971 if (GET_CODE (newpat) == PARALLEL)
1973 rtvec old = XVEC (newpat, 0);
1974 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
1975 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
1976 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
1977 sizeof (old->elem[0]) * old->num_elem);
1982 total_sets = 1 + added_sets_1 + added_sets_2;
1983 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
1984 XVECEXP (newpat, 0, 0) = old;
1988 XVECEXP (newpat, 0, --total_sets)
1989 = (GET_CODE (PATTERN (i1)) == PARALLEL
1990 ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
1994 /* If there is no I1, use I2's body as is. We used to also not do
1995 the subst call below if I2 was substituted into I3,
1996 but that could lose a simplification. */
1998 XVECEXP (newpat, 0, --total_sets) = i2pat;
2000 /* See comment where i2pat is assigned. */
2001 XVECEXP (newpat, 0, --total_sets)
2002 = subst (i2pat, i1dest, i1src, 0, 0);
2006 /* We come here when we are replacing a destination in I2 with the
2007 destination of I3. */
2008 validate_replacement:
2010 /* Note which hard regs this insn has as inputs. */
2011 mark_used_regs_combine (newpat);
2013 /* Is the result of combination a valid instruction? */
2014 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2016 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2017 the second SET's destination is a register that is unused and isn't
2018 marked as an instruction that might trap in an EH region. In that case,
2019 we just need the first SET. This can occur when simplifying a divmod
2020 insn. We *must* test for this case here because the code below that
2021 splits two independent SETs doesn't handle this case correctly when it
2022 updates the register status. Also check the case where the first
2023 SET's destination is unused. That would not cause incorrect code, but
2024 does cause an unneeded insn to remain. */
2026 if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
2027 && XVECLEN (newpat, 0) == 2
2028 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2029 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2030 && asm_noperands (newpat) < 0)
2032 rtx set0 = XVECEXP (newpat, 0, 0);
2033 rtx set1 = XVECEXP (newpat, 0, 1);
2036 if (((GET_CODE (SET_DEST (set1)) == REG
2037 && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
2038 || (GET_CODE (SET_DEST (set1)) == SUBREG
2039 && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
2040 && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2041 || INTVAL (XEXP (note, 0)) <= 0)
2042 && ! side_effects_p (SET_SRC (set1)))
2045 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2048 else if (((GET_CODE (SET_DEST (set0)) == REG
2049 && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
2050 || (GET_CODE (SET_DEST (set0)) == SUBREG
2051 && find_reg_note (i3, REG_UNUSED,
2052 SUBREG_REG (SET_DEST (set0)))))
2053 && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2054 || INTVAL (XEXP (note, 0)) <= 0)
2055 && ! side_effects_p (SET_SRC (set0)))
2058 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2060 if (insn_code_number >= 0)
2062 /* If we will be able to accept this, we have made a
2063 change to the destination of I3. This requires us to
2064 do a few adjustments. */
2066 PATTERN (i3) = newpat;
2067 adjust_for_new_dest (i3);
2072 /* If we were combining three insns and the result is a simple SET
2073 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2074 insns. There are two ways to do this. It can be split using a
2075 machine-specific method (like when you have an addition of a large
2076 constant) or by combine in the function find_split_point. */
2078 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2079 && asm_noperands (newpat) < 0)
2081 rtx m_split, *split;
2082 rtx ni2dest = i2dest;
2084 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2085 use I2DEST as a scratch register will help. In the latter case,
2086 convert I2DEST to the mode of the source of NEWPAT if we can. */
2088 m_split = split_insns (newpat, i3);
2090 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2091 inputs of NEWPAT. */
2093 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2094 possible to try that as a scratch reg. This would require adding
2095 more code to make it work though. */
2097 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
2099 /* If I2DEST is a hard register or the only use of a pseudo,
2100 we can change its mode. */
2101 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
2102 && GET_MODE (SET_DEST (newpat)) != VOIDmode
2103 && GET_CODE (i2dest) == REG
2104 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2105 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2106 && ! REG_USERVAR_P (i2dest))))
2107 ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)),
2110 m_split = split_insns (gen_rtx_PARALLEL
2112 gen_rtvec (2, newpat,
2113 gen_rtx_CLOBBER (VOIDmode,
2116 /* If the split with the mode-changed register didn't work, try
2117 the original register. */
2118 if (! m_split && ni2dest != i2dest)
2121 m_split = split_insns (gen_rtx_PARALLEL
2123 gen_rtvec (2, newpat,
2124 gen_rtx_CLOBBER (VOIDmode,
2130 if (m_split && NEXT_INSN (m_split) == NULL_RTX)
2132 m_split = PATTERN (m_split);
2133 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
2134 if (insn_code_number >= 0)
2137 else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
2138 && (next_real_insn (i2) == i3
2139 || ! use_crosses_set_p (PATTERN (m_split), INSN_CUID (i2))))
2142 rtx newi3pat = PATTERN (NEXT_INSN (m_split));
2143 newi2pat = PATTERN (m_split);
2145 i3set = single_set (NEXT_INSN (m_split));
2146 i2set = single_set (m_split);
2148 /* In case we changed the mode of I2DEST, replace it in the
2149 pseudo-register table here. We can't do it above in case this
2150 code doesn't get executed and we do a split the other way. */
2152 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2153 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
2155 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2157 /* If I2 or I3 has multiple SETs, we won't know how to track
2158 register status, so don't use these insns. If I2's destination
2159 is used between I2 and I3, we also can't use these insns. */
2161 if (i2_code_number >= 0 && i2set && i3set
2162 && (next_real_insn (i2) == i3
2163 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
2164 insn_code_number = recog_for_combine (&newi3pat, i3,
2166 if (insn_code_number >= 0)
2169 /* It is possible that both insns now set the destination of I3.
2170 If so, we must show an extra use of it. */
2172 if (insn_code_number >= 0)
2174 rtx new_i3_dest = SET_DEST (i3set);
2175 rtx new_i2_dest = SET_DEST (i2set);
2177 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
2178 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
2179 || GET_CODE (new_i3_dest) == SUBREG)
2180 new_i3_dest = XEXP (new_i3_dest, 0);
2182 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
2183 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
2184 || GET_CODE (new_i2_dest) == SUBREG)
2185 new_i2_dest = XEXP (new_i2_dest, 0);
2187 if (GET_CODE (new_i3_dest) == REG
2188 && GET_CODE (new_i2_dest) == REG
2189 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
2190 REG_N_SETS (REGNO (new_i2_dest))++;
2194 /* If we can split it and use I2DEST, go ahead and see if that
2195 helps things be recognized. Verify that none of the registers
2196 are set between I2 and I3. */
2197 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
2199 && GET_CODE (i2dest) == REG
2201 /* We need I2DEST in the proper mode. If it is a hard register
2202 or the only use of a pseudo, we can change its mode. */
2203 && (GET_MODE (*split) == GET_MODE (i2dest)
2204 || GET_MODE (*split) == VOIDmode
2205 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2206 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2207 && ! REG_USERVAR_P (i2dest)))
2208 && (next_real_insn (i2) == i3
2209 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
2210 /* We can't overwrite I2DEST if its value is still used by
2212 && ! reg_referenced_p (i2dest, newpat))
2214 rtx newdest = i2dest;
2215 enum rtx_code split_code = GET_CODE (*split);
2216 enum machine_mode split_mode = GET_MODE (*split);
2218 /* Get NEWDEST as a register in the proper mode. We have already
2219 validated that we can do this. */
2220 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2222 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
2224 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2225 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
2228 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2229 an ASHIFT. This can occur if it was inside a PLUS and hence
2230 appeared to be a memory address. This is a kludge. */
2231 if (split_code == MULT
2232 && GET_CODE (XEXP (*split, 1)) == CONST_INT
2233 && INTVAL (XEXP (*split, 1)) > 0
2234 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
2236 SUBST (*split, gen_rtx_ASHIFT (split_mode,
2237 XEXP (*split, 0), GEN_INT (i)));
2238 /* Update split_code because we may not have a multiply
2240 split_code = GET_CODE (*split);
2243 #ifdef INSN_SCHEDULING
2244 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2245 be written as a ZERO_EXTEND. */
2246 if (split_code == SUBREG && GET_CODE (SUBREG_REG (*split)) == MEM)
2248 #ifdef LOAD_EXTEND_OP
2249 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
2250 what it really is. */
2251 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
2253 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
2254 SUBREG_REG (*split)));
2257 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
2258 SUBREG_REG (*split)));
2262 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
2263 SUBST (*split, newdest);
2264 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2266 /* If the split point was a MULT and we didn't have one before,
2267 don't use one now. */
2268 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
2269 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2273 /* Check for a case where we loaded from memory in a narrow mode and
2274 then sign extended it, but we need both registers. In that case,
2275 we have a PARALLEL with both loads from the same memory location.
2276 We can split this into a load from memory followed by a register-register
2277 copy. This saves at least one insn, more if register allocation can
2280 We cannot do this if the destination of the first assignment is a
2281 condition code register or cc0. We eliminate this case by making sure
2282 the SET_DEST and SET_SRC have the same mode.
2284 We cannot do this if the destination of the second assignment is
2285 a register that we have already assumed is zero-extended. Similarly
2286 for a SUBREG of such a register. */
2288 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2289 && GET_CODE (newpat) == PARALLEL
2290 && XVECLEN (newpat, 0) == 2
2291 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2292 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2293 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
2294 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
2295 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2296 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2297 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2298 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2300 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2301 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2302 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2303 (GET_CODE (temp) == REG
2304 && reg_nonzero_bits[REGNO (temp)] != 0
2305 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2306 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2307 && (reg_nonzero_bits[REGNO (temp)]
2308 != GET_MODE_MASK (word_mode))))
2309 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2310 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2311 (GET_CODE (temp) == REG
2312 && reg_nonzero_bits[REGNO (temp)] != 0
2313 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2314 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2315 && (reg_nonzero_bits[REGNO (temp)]
2316 != GET_MODE_MASK (word_mode)))))
2317 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2318 SET_SRC (XVECEXP (newpat, 0, 1)))
2319 && ! find_reg_note (i3, REG_UNUSED,
2320 SET_DEST (XVECEXP (newpat, 0, 0))))
2324 newi2pat = XVECEXP (newpat, 0, 0);
2325 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2326 newpat = XVECEXP (newpat, 0, 1);
2327 SUBST (SET_SRC (newpat),
2328 gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
2329 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2331 if (i2_code_number >= 0)
2332 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2334 if (insn_code_number >= 0)
2339 /* If we will be able to accept this, we have made a change to the
2340 destination of I3. This requires us to do a few adjustments. */
2341 PATTERN (i3) = newpat;
2342 adjust_for_new_dest (i3);
2344 /* I3 now uses what used to be its destination and which is
2345 now I2's destination. That means we need a LOG_LINK from
2346 I3 to I2. But we used to have one, so we still will.
2348 However, some later insn might be using I2's dest and have
2349 a LOG_LINK pointing at I3. We must remove this link.
2350 The simplest way to remove the link is to point it at I1,
2351 which we know will be a NOTE. */
2353 for (insn = NEXT_INSN (i3);
2354 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
2355 || insn != BB_HEAD (this_basic_block->next_bb));
2356 insn = NEXT_INSN (insn))
2358 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
2360 for (link = LOG_LINKS (insn); link;
2361 link = XEXP (link, 1))
2362 if (XEXP (link, 0) == i3)
2363 XEXP (link, 0) = i1;
2371 /* Similarly, check for a case where we have a PARALLEL of two independent
2372 SETs but we started with three insns. In this case, we can do the sets
2373 as two separate insns. This case occurs when some SET allows two
2374 other insns to combine, but the destination of that SET is still live. */
2376 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2377 && GET_CODE (newpat) == PARALLEL
2378 && XVECLEN (newpat, 0) == 2
2379 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2380 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2381 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2382 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2383 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2384 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2385 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2387 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2388 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2389 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2390 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2391 XVECEXP (newpat, 0, 0))
2392 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2393 XVECEXP (newpat, 0, 1))
2394 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
2395 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
2397 /* Normally, it doesn't matter which of the two is done first,
2398 but it does if one references cc0. In that case, it has to
2401 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2403 newi2pat = XVECEXP (newpat, 0, 0);
2404 newpat = XVECEXP (newpat, 0, 1);
2409 newi2pat = XVECEXP (newpat, 0, 1);
2410 newpat = XVECEXP (newpat, 0, 0);
2413 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2415 if (i2_code_number >= 0)
2416 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2419 /* If it still isn't recognized, fail and change things back the way they
2421 if ((insn_code_number < 0
2422 /* Is the result a reasonable ASM_OPERANDS? */
2423 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2429 /* If we had to change another insn, make sure it is valid also. */
2430 if (undobuf.other_insn)
2432 rtx other_pat = PATTERN (undobuf.other_insn);
2433 rtx new_other_notes;
2436 CLEAR_HARD_REG_SET (newpat_used_regs);
2438 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2441 if (other_code_number < 0 && ! check_asm_operands (other_pat))
2447 PATTERN (undobuf.other_insn) = other_pat;
2449 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2450 are still valid. Then add any non-duplicate notes added by
2451 recog_for_combine. */
2452 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2454 next = XEXP (note, 1);
2456 if (REG_NOTE_KIND (note) == REG_UNUSED
2457 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2459 if (GET_CODE (XEXP (note, 0)) == REG)
2460 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2462 remove_note (undobuf.other_insn, note);
2466 for (note = new_other_notes; note; note = XEXP (note, 1))
2467 if (GET_CODE (XEXP (note, 0)) == REG)
2468 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2470 distribute_notes (new_other_notes, undobuf.other_insn,
2471 undobuf.other_insn, NULL_RTX);
2474 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
2475 they are adjacent to each other or not. */
2477 rtx p = prev_nonnote_insn (i3);
2478 if (p && p != i2 && GET_CODE (p) == INSN && newi2pat
2479 && sets_cc0_p (newi2pat))
2487 /* We now know that we can do this combination. Merge the insns and
2488 update the status of registers and LOG_LINKS. */
2491 rtx i3notes, i2notes, i1notes = 0;
2492 rtx i3links, i2links, i1links = 0;
2496 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2498 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2499 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2501 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2503 /* Ensure that we do not have something that should not be shared but
2504 occurs multiple times in the new insns. Check this by first
2505 resetting all the `used' flags and then copying anything is shared. */
2507 reset_used_flags (i3notes);
2508 reset_used_flags (i2notes);
2509 reset_used_flags (i1notes);
2510 reset_used_flags (newpat);
2511 reset_used_flags (newi2pat);
2512 if (undobuf.other_insn)
2513 reset_used_flags (PATTERN (undobuf.other_insn));
2515 i3notes = copy_rtx_if_shared (i3notes);
2516 i2notes = copy_rtx_if_shared (i2notes);
2517 i1notes = copy_rtx_if_shared (i1notes);
2518 newpat = copy_rtx_if_shared (newpat);
2519 newi2pat = copy_rtx_if_shared (newi2pat);
2520 if (undobuf.other_insn)
2521 reset_used_flags (PATTERN (undobuf.other_insn));
2523 INSN_CODE (i3) = insn_code_number;
2524 PATTERN (i3) = newpat;
2526 if (GET_CODE (i3) == CALL_INSN && CALL_INSN_FUNCTION_USAGE (i3))
2528 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
2530 reset_used_flags (call_usage);
2531 call_usage = copy_rtx (call_usage);
2534 replace_rtx (call_usage, i2dest, i2src);
2537 replace_rtx (call_usage, i1dest, i1src);
2539 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
2542 if (undobuf.other_insn)
2543 INSN_CODE (undobuf.other_insn) = other_code_number;
2545 /* We had one special case above where I2 had more than one set and
2546 we replaced a destination of one of those sets with the destination
2547 of I3. In that case, we have to update LOG_LINKS of insns later
2548 in this basic block. Note that this (expensive) case is rare.
2550 Also, in this case, we must pretend that all REG_NOTEs for I2
2551 actually came from I3, so that REG_UNUSED notes from I2 will be
2552 properly handled. */
2554 if (i3_subst_into_i2)
2556 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2557 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != USE
2558 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
2559 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2560 && ! find_reg_note (i2, REG_UNUSED,
2561 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2562 for (temp = NEXT_INSN (i2);
2563 temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
2564 || BB_HEAD (this_basic_block) != temp);
2565 temp = NEXT_INSN (temp))
2566 if (temp != i3 && INSN_P (temp))
2567 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2568 if (XEXP (link, 0) == i2)
2569 XEXP (link, 0) = i3;
2574 while (XEXP (link, 1))
2575 link = XEXP (link, 1);
2576 XEXP (link, 1) = i2notes;
2590 INSN_CODE (i2) = i2_code_number;
2591 PATTERN (i2) = newi2pat;
2595 PUT_CODE (i2, NOTE);
2596 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
2597 NOTE_SOURCE_FILE (i2) = 0;
2604 PUT_CODE (i1, NOTE);
2605 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
2606 NOTE_SOURCE_FILE (i1) = 0;
2609 /* Get death notes for everything that is now used in either I3 or
2610 I2 and used to die in a previous insn. If we built two new
2611 patterns, move from I1 to I2 then I2 to I3 so that we get the
2612 proper movement on registers that I2 modifies. */
2616 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
2617 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
2620 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
2623 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2625 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX);
2627 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX);
2629 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX);
2631 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX);
2633 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2634 know these are REG_UNUSED and want them to go to the desired insn,
2635 so we always pass it as i3. We have not counted the notes in
2636 reg_n_deaths yet, so we need to do so now. */
2638 if (newi2pat && new_i2_notes)
2640 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2641 if (GET_CODE (XEXP (temp, 0)) == REG)
2642 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2644 distribute_notes (new_i2_notes, i2, i2, NULL_RTX);
2649 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2650 if (GET_CODE (XEXP (temp, 0)) == REG)
2651 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2653 distribute_notes (new_i3_notes, i3, i3, NULL_RTX);
2656 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2657 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2658 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2659 in that case, it might delete I2. Similarly for I2 and I1.
2660 Show an additional death due to the REG_DEAD note we make here. If
2661 we discard it in distribute_notes, we will decrement it again. */
2665 if (GET_CODE (i3dest_killed) == REG)
2666 REG_N_DEATHS (REGNO (i3dest_killed))++;
2668 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
2669 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2671 NULL_RTX, i2, NULL_RTX);
2673 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2675 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX);
2678 if (i2dest_in_i2src)
2680 if (GET_CODE (i2dest) == REG)
2681 REG_N_DEATHS (REGNO (i2dest))++;
2683 if (newi2pat && reg_set_p (i2dest, newi2pat))
2684 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2685 NULL_RTX, i2, NULL_RTX);
2687 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2688 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX);
2691 if (i1dest_in_i1src)
2693 if (GET_CODE (i1dest) == REG)
2694 REG_N_DEATHS (REGNO (i1dest))++;
2696 if (newi2pat && reg_set_p (i1dest, newi2pat))
2697 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2698 NULL_RTX, i2, NULL_RTX);
2700 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2701 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX);
2704 distribute_links (i3links);
2705 distribute_links (i2links);
2706 distribute_links (i1links);
2708 if (GET_CODE (i2dest) == REG)
2711 rtx i2_insn = 0, i2_val = 0, set;
2713 /* The insn that used to set this register doesn't exist, and
2714 this life of the register may not exist either. See if one of
2715 I3's links points to an insn that sets I2DEST. If it does,
2716 that is now the last known value for I2DEST. If we don't update
2717 this and I2 set the register to a value that depended on its old
2718 contents, we will get confused. If this insn is used, thing
2719 will be set correctly in combine_instructions. */
2721 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2722 if ((set = single_set (XEXP (link, 0))) != 0
2723 && rtx_equal_p (i2dest, SET_DEST (set)))
2724 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2726 record_value_for_reg (i2dest, i2_insn, i2_val);
2728 /* If the reg formerly set in I2 died only once and that was in I3,
2729 zero its use count so it won't make `reload' do any work. */
2731 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
2732 && ! i2dest_in_i2src)
2734 regno = REGNO (i2dest);
2735 REG_N_SETS (regno)--;
2739 if (i1 && GET_CODE (i1dest) == REG)
2742 rtx i1_insn = 0, i1_val = 0, set;
2744 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2745 if ((set = single_set (XEXP (link, 0))) != 0
2746 && rtx_equal_p (i1dest, SET_DEST (set)))
2747 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2749 record_value_for_reg (i1dest, i1_insn, i1_val);
2751 regno = REGNO (i1dest);
2752 if (! added_sets_1 && ! i1dest_in_i1src)
2753 REG_N_SETS (regno)--;
2756 /* Update reg_nonzero_bits et al for any changes that may have been made
2757 to this insn. The order of set_nonzero_bits_and_sign_copies() is
2758 important. Because newi2pat can affect nonzero_bits of newpat */
2760 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
2761 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
2763 /* Set new_direct_jump_p if a new return or simple jump instruction
2766 If I3 is now an unconditional jump, ensure that it has a
2767 BARRIER following it since it may have initially been a
2768 conditional jump. It may also be the last nonnote insn. */
2770 if (returnjump_p (i3) || any_uncondjump_p (i3))
2772 *new_direct_jump_p = 1;
2773 mark_jump_label (PATTERN (i3), i3, 0);
2775 if ((temp = next_nonnote_insn (i3)) == NULL_RTX
2776 || GET_CODE (temp) != BARRIER)
2777 emit_barrier_after (i3);
2780 if (undobuf.other_insn != NULL_RTX
2781 && (returnjump_p (undobuf.other_insn)
2782 || any_uncondjump_p (undobuf.other_insn)))
2784 *new_direct_jump_p = 1;
2786 if ((temp = next_nonnote_insn (undobuf.other_insn)) == NULL_RTX
2787 || GET_CODE (temp) != BARRIER)
2788 emit_barrier_after (undobuf.other_insn);
2791 /* An NOOP jump does not need barrier, but it does need cleaning up
2793 if (GET_CODE (newpat) == SET
2794 && SET_SRC (newpat) == pc_rtx
2795 && SET_DEST (newpat) == pc_rtx)
2796 *new_direct_jump_p = 1;
2799 combine_successes++;
2802 if (added_links_insn
2803 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
2804 && INSN_CUID (added_links_insn) < INSN_CUID (i3))
2805 return added_links_insn;
2807 return newi2pat ? i2 : i3;
2810 /* Undo all the modifications recorded in undobuf. */
2815 struct undo *undo, *next;
2817 for (undo = undobuf.undos; undo; undo = next)
2821 *undo->where.i = undo->old_contents.i;
2823 *undo->where.r = undo->old_contents.r;
2825 undo->next = undobuf.frees;
2826 undobuf.frees = undo;
2832 /* We've committed to accepting the changes we made. Move all
2833 of the undos to the free list. */
2838 struct undo *undo, *next;
2840 for (undo = undobuf.undos; undo; undo = next)
2843 undo->next = undobuf.frees;
2844 undobuf.frees = undo;
2850 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2851 where we have an arithmetic expression and return that point. LOC will
2854 try_combine will call this function to see if an insn can be split into
2858 find_split_point (rtx *loc, rtx insn)
2861 enum rtx_code code = GET_CODE (x);
2863 unsigned HOST_WIDE_INT len = 0;
2864 HOST_WIDE_INT pos = 0;
2866 rtx inner = NULL_RTX;
2868 /* First special-case some codes. */
2872 #ifdef INSN_SCHEDULING
2873 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2875 if (GET_CODE (SUBREG_REG (x)) == MEM)
2878 return find_split_point (&SUBREG_REG (x), insn);
2882 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2883 using LO_SUM and HIGH. */
2884 if (GET_CODE (XEXP (x, 0)) == CONST
2885 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
2888 gen_rtx_LO_SUM (Pmode,
2889 gen_rtx_HIGH (Pmode, XEXP (x, 0)),
2891 return &XEXP (XEXP (x, 0), 0);
2895 /* If we have a PLUS whose second operand is a constant and the
2896 address is not valid, perhaps will can split it up using
2897 the machine-specific way to split large constants. We use
2898 the first pseudo-reg (one of the virtual regs) as a placeholder;
2899 it will not remain in the result. */
2900 if (GET_CODE (XEXP (x, 0)) == PLUS
2901 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2902 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
2904 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
2905 rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
2908 /* This should have produced two insns, each of which sets our
2909 placeholder. If the source of the second is a valid address,
2910 we can make put both sources together and make a split point
2914 && NEXT_INSN (seq) != NULL_RTX
2915 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
2916 && GET_CODE (seq) == INSN
2917 && GET_CODE (PATTERN (seq)) == SET
2918 && SET_DEST (PATTERN (seq)) == reg
2919 && ! reg_mentioned_p (reg,
2920 SET_SRC (PATTERN (seq)))
2921 && GET_CODE (NEXT_INSN (seq)) == INSN
2922 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
2923 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
2924 && memory_address_p (GET_MODE (x),
2925 SET_SRC (PATTERN (NEXT_INSN (seq)))))
2927 rtx src1 = SET_SRC (PATTERN (seq));
2928 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
2930 /* Replace the placeholder in SRC2 with SRC1. If we can
2931 find where in SRC2 it was placed, that can become our
2932 split point and we can replace this address with SRC2.
2933 Just try two obvious places. */
2935 src2 = replace_rtx (src2, reg, src1);
2937 if (XEXP (src2, 0) == src1)
2938 split = &XEXP (src2, 0);
2939 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
2940 && XEXP (XEXP (src2, 0), 0) == src1)
2941 split = &XEXP (XEXP (src2, 0), 0);
2945 SUBST (XEXP (x, 0), src2);
2950 /* If that didn't work, perhaps the first operand is complex and
2951 needs to be computed separately, so make a split point there.
2952 This will occur on machines that just support REG + CONST
2953 and have a constant moved through some previous computation. */
2955 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o'
2956 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
2957 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0))))
2959 return &XEXP (XEXP (x, 0), 0);
2965 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2966 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2967 we need to put the operand into a register. So split at that
2970 if (SET_DEST (x) == cc0_rtx
2971 && GET_CODE (SET_SRC (x)) != COMPARE
2972 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
2973 && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
2974 && ! (GET_CODE (SET_SRC (x)) == SUBREG
2975 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
2976 return &SET_SRC (x);
2979 /* See if we can split SET_SRC as it stands. */
2980 split = find_split_point (&SET_SRC (x), insn);
2981 if (split && split != &SET_SRC (x))
2984 /* See if we can split SET_DEST as it stands. */
2985 split = find_split_point (&SET_DEST (x), insn);
2986 if (split && split != &SET_DEST (x))
2989 /* See if this is a bitfield assignment with everything constant. If
2990 so, this is an IOR of an AND, so split it into that. */
2991 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
2992 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
2993 <= HOST_BITS_PER_WIDE_INT)
2994 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
2995 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
2996 && GET_CODE (SET_SRC (x)) == CONST_INT
2997 && ((INTVAL (XEXP (SET_DEST (x), 1))
2998 + INTVAL (XEXP (SET_DEST (x), 2)))
2999 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
3000 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
3002 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
3003 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
3004 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
3005 rtx dest = XEXP (SET_DEST (x), 0);
3006 enum machine_mode mode = GET_MODE (dest);
3007 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
3009 if (BITS_BIG_ENDIAN)
3010 pos = GET_MODE_BITSIZE (mode) - len - pos;
3014 gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
3017 gen_binary (IOR, mode,
3018 gen_binary (AND, mode, dest,
3019 gen_int_mode (~(mask << pos),
3021 GEN_INT (src << pos)));
3023 SUBST (SET_DEST (x), dest);
3025 split = find_split_point (&SET_SRC (x), insn);
3026 if (split && split != &SET_SRC (x))
3030 /* Otherwise, see if this is an operation that we can split into two.
3031 If so, try to split that. */
3032 code = GET_CODE (SET_SRC (x));
3037 /* If we are AND'ing with a large constant that is only a single
3038 bit and the result is only being used in a context where we
3039 need to know if it is zero or nonzero, replace it with a bit
3040 extraction. This will avoid the large constant, which might
3041 have taken more than one insn to make. If the constant were
3042 not a valid argument to the AND but took only one insn to make,
3043 this is no worse, but if it took more than one insn, it will
3046 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3047 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
3048 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
3049 && GET_CODE (SET_DEST (x)) == REG
3050 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
3051 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
3052 && XEXP (*split, 0) == SET_DEST (x)
3053 && XEXP (*split, 1) == const0_rtx)
3055 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
3056 XEXP (SET_SRC (x), 0),
3057 pos, NULL_RTX, 1, 1, 0, 0);
3058 if (extraction != 0)
3060 SUBST (SET_SRC (x), extraction);
3061 return find_split_point (loc, insn);
3067 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3068 is known to be on, this can be converted into a NEG of a shift. */
3069 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
3070 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
3071 && 1 <= (pos = exact_log2
3072 (nonzero_bits (XEXP (SET_SRC (x), 0),
3073 GET_MODE (XEXP (SET_SRC (x), 0))))))
3075 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
3079 gen_rtx_LSHIFTRT (mode,
3080 XEXP (SET_SRC (x), 0),
3083 split = find_split_point (&SET_SRC (x), insn);
3084 if (split && split != &SET_SRC (x))
3090 inner = XEXP (SET_SRC (x), 0);
3092 /* We can't optimize if either mode is a partial integer
3093 mode as we don't know how many bits are significant
3095 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
3096 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
3100 len = GET_MODE_BITSIZE (GET_MODE (inner));
3106 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3107 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
3109 inner = XEXP (SET_SRC (x), 0);
3110 len = INTVAL (XEXP (SET_SRC (x), 1));
3111 pos = INTVAL (XEXP (SET_SRC (x), 2));
3113 if (BITS_BIG_ENDIAN)
3114 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
3115 unsignedp = (code == ZERO_EXTRACT);
3123 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
3125 enum machine_mode mode = GET_MODE (SET_SRC (x));
3127 /* For unsigned, we have a choice of a shift followed by an
3128 AND or two shifts. Use two shifts for field sizes where the
3129 constant might be too large. We assume here that we can
3130 always at least get 8-bit constants in an AND insn, which is
3131 true for every current RISC. */
3133 if (unsignedp && len <= 8)
3138 (mode, gen_lowpart (mode, inner),
3140 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
3142 split = find_split_point (&SET_SRC (x), insn);
3143 if (split && split != &SET_SRC (x))
3150 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
3151 gen_rtx_ASHIFT (mode,
3152 gen_lowpart (mode, inner),
3153 GEN_INT (GET_MODE_BITSIZE (mode)
3155 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
3157 split = find_split_point (&SET_SRC (x), insn);
3158 if (split && split != &SET_SRC (x))
3163 /* See if this is a simple operation with a constant as the second
3164 operand. It might be that this constant is out of range and hence
3165 could be used as a split point. */
3166 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3167 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3168 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
3169 && CONSTANT_P (XEXP (SET_SRC (x), 1))
3170 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
3171 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
3172 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
3174 return &XEXP (SET_SRC (x), 1);
3176 /* Finally, see if this is a simple operation with its first operand
3177 not in a register. The operation might require this operand in a
3178 register, so return it as a split point. We can always do this
3179 because if the first operand were another operation, we would have
3180 already found it as a split point. */
3181 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3182 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3183 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
3184 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
3185 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
3186 return &XEXP (SET_SRC (x), 0);
3192 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3193 it is better to write this as (not (ior A B)) so we can split it.
3194 Similarly for IOR. */
3195 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
3198 gen_rtx_NOT (GET_MODE (x),
3199 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
3201 XEXP (XEXP (x, 0), 0),
3202 XEXP (XEXP (x, 1), 0))));
3203 return find_split_point (loc, insn);
3206 /* Many RISC machines have a large set of logical insns. If the
3207 second operand is a NOT, put it first so we will try to split the
3208 other operand first. */
3209 if (GET_CODE (XEXP (x, 1)) == NOT)
3211 rtx tem = XEXP (x, 0);
3212 SUBST (XEXP (x, 0), XEXP (x, 1));
3213 SUBST (XEXP (x, 1), tem);
3221 /* Otherwise, select our actions depending on our rtx class. */
3222 switch (GET_RTX_CLASS (code))
3224 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3226 split = find_split_point (&XEXP (x, 2), insn);
3229 /* ... fall through ... */
3233 split = find_split_point (&XEXP (x, 1), insn);
3236 /* ... fall through ... */
3238 /* Some machines have (and (shift ...) ...) insns. If X is not
3239 an AND, but XEXP (X, 0) is, use it as our split point. */
3240 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
3241 return &XEXP (x, 0);
3243 split = find_split_point (&XEXP (x, 0), insn);
3249 /* Otherwise, we don't have a split point. */
3253 /* Throughout X, replace FROM with TO, and return the result.
3254 The result is TO if X is FROM;
3255 otherwise the result is X, but its contents may have been modified.
3256 If they were modified, a record was made in undobuf so that
3257 undo_all will (among other things) return X to its original state.
3259 If the number of changes necessary is too much to record to undo,
3260 the excess changes are not made, so the result is invalid.
3261 The changes already made can still be undone.
3262 undobuf.num_undo is incremented for such changes, so by testing that
3263 the caller can tell whether the result is valid.
3265 `n_occurrences' is incremented each time FROM is replaced.
3267 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
3269 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
3270 by copying if `n_occurrences' is nonzero. */
3273 subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy)
3275 enum rtx_code code = GET_CODE (x);
3276 enum machine_mode op0_mode = VOIDmode;
3281 /* Two expressions are equal if they are identical copies of a shared
3282 RTX or if they are both registers with the same register number
3285 #define COMBINE_RTX_EQUAL_P(X,Y) \
3287 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3288 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3290 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3293 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3296 /* If X and FROM are the same register but different modes, they will
3297 not have been seen as equal above. However, flow.c will make a
3298 LOG_LINKS entry for that case. If we do nothing, we will try to
3299 rerecognize our original insn and, when it succeeds, we will
3300 delete the feeding insn, which is incorrect.
3302 So force this insn not to match in this (rare) case. */
3303 if (! in_dest && code == REG && GET_CODE (from) == REG
3304 && REGNO (x) == REGNO (from))
3305 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
3307 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3308 of which may contain things that can be combined. */
3309 if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
3312 /* It is possible to have a subexpression appear twice in the insn.
3313 Suppose that FROM is a register that appears within TO.
3314 Then, after that subexpression has been scanned once by `subst',
3315 the second time it is scanned, TO may be found. If we were
3316 to scan TO here, we would find FROM within it and create a
3317 self-referent rtl structure which is completely wrong. */
3318 if (COMBINE_RTX_EQUAL_P (x, to))
3321 /* Parallel asm_operands need special attention because all of the
3322 inputs are shared across the arms. Furthermore, unsharing the
3323 rtl results in recognition failures. Failure to handle this case
3324 specially can result in circular rtl.
3326 Solve this by doing a normal pass across the first entry of the
3327 parallel, and only processing the SET_DESTs of the subsequent
3330 if (code == PARALLEL
3331 && GET_CODE (XVECEXP (x, 0, 0)) == SET
3332 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
3334 new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3336 /* If this substitution failed, this whole thing fails. */
3337 if (GET_CODE (new) == CLOBBER
3338 && XEXP (new, 0) == const0_rtx)
3341 SUBST (XVECEXP (x, 0, 0), new);
3343 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
3345 rtx dest = SET_DEST (XVECEXP (x, 0, i));
3347 if (GET_CODE (dest) != REG
3348 && GET_CODE (dest) != CC0
3349 && GET_CODE (dest) != PC)
3351 new = subst (dest, from, to, 0, unique_copy);
3353 /* If this substitution failed, this whole thing fails. */
3354 if (GET_CODE (new) == CLOBBER
3355 && XEXP (new, 0) == const0_rtx)
3358 SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
3364 len = GET_RTX_LENGTH (code);
3365 fmt = GET_RTX_FORMAT (code);
3367 /* We don't need to process a SET_DEST that is a register, CC0,
3368 or PC, so set up to skip this common case. All other cases
3369 where we want to suppress replacing something inside a
3370 SET_SRC are handled via the IN_DEST operand. */
3372 && (GET_CODE (SET_DEST (x)) == REG
3373 || GET_CODE (SET_DEST (x)) == CC0
3374 || GET_CODE (SET_DEST (x)) == PC))
3377 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3380 op0_mode = GET_MODE (XEXP (x, 0));
3382 for (i = 0; i < len; i++)
3387 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3389 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3391 new = (unique_copy && n_occurrences
3392 ? copy_rtx (to) : to);
3397 new = subst (XVECEXP (x, i, j), from, to, 0,
3400 /* If this substitution failed, this whole thing
3402 if (GET_CODE (new) == CLOBBER
3403 && XEXP (new, 0) == const0_rtx)
3407 SUBST (XVECEXP (x, i, j), new);
3410 else if (fmt[i] == 'e')
3412 /* If this is a register being set, ignore it. */
3415 && (code == SUBREG || code == STRICT_LOW_PART
3416 || code == ZERO_EXTRACT)
3418 && GET_CODE (new) == REG)
3421 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
3423 /* In general, don't install a subreg involving two
3424 modes not tieable. It can worsen register
3425 allocation, and can even make invalid reload
3426 insns, since the reg inside may need to be copied
3427 from in the outside mode, and that may be invalid
3428 if it is an fp reg copied in integer mode.
3430 We allow two exceptions to this: It is valid if
3431 it is inside another SUBREG and the mode of that
3432 SUBREG and the mode of the inside of TO is
3433 tieable and it is valid if X is a SET that copies
3436 if (GET_CODE (to) == SUBREG
3437 && ! MODES_TIEABLE_P (GET_MODE (to),
3438 GET_MODE (SUBREG_REG (to)))
3439 && ! (code == SUBREG
3440 && MODES_TIEABLE_P (GET_MODE (x),
3441 GET_MODE (SUBREG_REG (to))))
3443 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
3446 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3448 #ifdef CANNOT_CHANGE_MODE_CLASS
3450 && GET_CODE (to) == REG
3451 && REGNO (to) < FIRST_PSEUDO_REGISTER
3452 && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
3455 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3458 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3462 /* If we are in a SET_DEST, suppress most cases unless we
3463 have gone inside a MEM, in which case we want to
3464 simplify the address. We assume here that things that
3465 are actually part of the destination have their inner
3466 parts in the first expression. This is true for SUBREG,
3467 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3468 things aside from REG and MEM that should appear in a
3470 new = subst (XEXP (x, i), from, to,
3472 && (code == SUBREG || code == STRICT_LOW_PART
3473 || code == ZERO_EXTRACT))
3475 && i == 0), unique_copy);
3477 /* If we found that we will have to reject this combination,
3478 indicate that by returning the CLOBBER ourselves, rather than
3479 an expression containing it. This will speed things up as
3480 well as prevent accidents where two CLOBBERs are considered
3481 to be equal, thus producing an incorrect simplification. */
3483 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3486 if (GET_CODE (x) == SUBREG
3487 && (GET_CODE (new) == CONST_INT
3488 || GET_CODE (new) == CONST_DOUBLE))
3490 enum machine_mode mode = GET_MODE (x);
3492 x = simplify_subreg (GET_MODE (x), new,
3493 GET_MODE (SUBREG_REG (x)),
3496 x = gen_rtx_CLOBBER (mode, const0_rtx);
3498 else if (GET_CODE (new) == CONST_INT
3499 && GET_CODE (x) == ZERO_EXTEND)
3501 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
3502 new, GET_MODE (XEXP (x, 0)));
3507 SUBST (XEXP (x, i), new);
3512 /* Try to simplify X. If the simplification changed the code, it is likely
3513 that further simplification will help, so loop, but limit the number
3514 of repetitions that will be performed. */
3516 for (i = 0; i < 4; i++)
3518 /* If X is sufficiently simple, don't bother trying to do anything
3520 if (code != CONST_INT && code != REG && code != CLOBBER)
3521 x = combine_simplify_rtx (x, op0_mode, i == 3, in_dest);
3523 if (GET_CODE (x) == code)
3526 code = GET_CODE (x);
3528 /* We no longer know the original mode of operand 0 since we
3529 have changed the form of X) */
3530 op0_mode = VOIDmode;
3536 /* Simplify X, a piece of RTL. We just operate on the expression at the
3537 outer level; call `subst' to simplify recursively. Return the new
3540 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3541 will be the iteration even if an expression with a code different from
3542 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3545 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int last,
3548 enum rtx_code code = GET_CODE (x);
3549 enum machine_mode mode = GET_MODE (x);
3554 /* If this is a commutative operation, put a constant last and a complex
3555 expression first. We don't need to do this for comparisons here. */
3556 if (GET_RTX_CLASS (code) == 'c'
3557 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
3560 SUBST (XEXP (x, 0), XEXP (x, 1));
3561 SUBST (XEXP (x, 1), temp);
3564 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3565 sign extension of a PLUS with a constant, reverse the order of the sign
3566 extension and the addition. Note that this not the same as the original
3567 code, but overflow is undefined for signed values. Also note that the
3568 PLUS will have been partially moved "inside" the sign-extension, so that
3569 the first operand of X will really look like:
3570 (ashiftrt (plus (ashift A C4) C5) C4).
3572 (plus (ashiftrt (ashift A C4) C2) C4)
3573 and replace the first operand of X with that expression. Later parts
3574 of this function may simplify the expression further.
3576 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3577 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3578 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3580 We do this to simplify address expressions. */
3582 if ((code == PLUS || code == MINUS || code == MULT)
3583 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3584 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
3585 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
3586 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
3587 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3588 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
3589 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3590 && (temp = simplify_binary_operation (ASHIFTRT, mode,
3591 XEXP (XEXP (XEXP (x, 0), 0), 1),
3592 XEXP (XEXP (x, 0), 1))) != 0)
3595 = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3596 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
3597 INTVAL (XEXP (XEXP (x, 0), 1)));
3599 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
3600 INTVAL (XEXP (XEXP (x, 0), 1)));
3602 SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
3605 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3606 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3607 things. Check for cases where both arms are testing the same
3610 Don't do anything if all operands are very simple. */
3612 if (((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c'
3613 || GET_RTX_CLASS (code) == '<')
3614 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3615 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3616 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3618 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o'
3619 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3620 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 1))))
3622 || (GET_RTX_CLASS (code) == '1'
3623 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3624 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3625 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3628 rtx cond, true_rtx, false_rtx;
3630 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
3632 /* If everything is a comparison, what we have is highly unlikely
3633 to be simpler, so don't use it. */
3634 && ! (GET_RTX_CLASS (code) == '<'
3635 && (GET_RTX_CLASS (GET_CODE (true_rtx)) == '<'
3636 || GET_RTX_CLASS (GET_CODE (false_rtx)) == '<')))
3638 rtx cop1 = const0_rtx;
3639 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3641 if (cond_code == NE && GET_RTX_CLASS (GET_CODE (cond)) == '<')
3644 /* Simplify the alternative arms; this may collapse the true and
3645 false arms to store-flag values. Be careful to use copy_rtx
3646 here since true_rtx or false_rtx might share RTL with x as a
3647 result of the if_then_else_cond call above. */
3648 true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0);
3649 false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0);
3651 /* If true_rtx and false_rtx are not general_operands, an if_then_else
3652 is unlikely to be simpler. */
3653 if (general_operand (true_rtx, VOIDmode)
3654 && general_operand (false_rtx, VOIDmode))
3656 enum rtx_code reversed;
3658 /* Restarting if we generate a store-flag expression will cause
3659 us to loop. Just drop through in this case. */
3661 /* If the result values are STORE_FLAG_VALUE and zero, we can
3662 just make the comparison operation. */
3663 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
3664 x = gen_binary (cond_code, mode, cond, cop1);
3665 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
3666 && ((reversed = reversed_comparison_code_parts
3667 (cond_code, cond, cop1, NULL))
3669 x = gen_binary (reversed, mode, cond, cop1);
3671 /* Likewise, we can make the negate of a comparison operation
3672 if the result values are - STORE_FLAG_VALUE and zero. */
3673 else if (GET_CODE (true_rtx) == CONST_INT
3674 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
3675 && false_rtx == const0_rtx)
3676 x = simplify_gen_unary (NEG, mode,
3677 gen_binary (cond_code, mode, cond,
3680 else if (GET_CODE (false_rtx) == CONST_INT
3681 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
3682 && true_rtx == const0_rtx
3683 && ((reversed = reversed_comparison_code_parts
3684 (cond_code, cond, cop1, NULL))
3686 x = simplify_gen_unary (NEG, mode,
3687 gen_binary (reversed, mode,
3691 return gen_rtx_IF_THEN_ELSE (mode,
3692 gen_binary (cond_code, VOIDmode,
3694 true_rtx, false_rtx);
3696 code = GET_CODE (x);
3697 op0_mode = VOIDmode;
3702 /* Try to fold this expression in case we have constants that weren't
3705 switch (GET_RTX_CLASS (code))
3708 if (op0_mode == VOIDmode)
3709 op0_mode = GET_MODE (XEXP (x, 0));
3710 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
3714 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
3715 if (cmp_mode == VOIDmode)
3717 cmp_mode = GET_MODE (XEXP (x, 1));
3718 if (cmp_mode == VOIDmode)
3719 cmp_mode = op0_mode;
3721 temp = simplify_relational_operation (code, cmp_mode,
3722 XEXP (x, 0), XEXP (x, 1));
3724 #ifdef FLOAT_STORE_FLAG_VALUE
3725 if (temp != 0 && GET_MODE_CLASS (mode) == MODE_FLOAT)
3727 if (temp == const0_rtx)
3728 temp = CONST0_RTX (mode);
3730 temp = CONST_DOUBLE_FROM_REAL_VALUE (FLOAT_STORE_FLAG_VALUE (mode),
3737 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3741 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
3742 XEXP (x, 1), XEXP (x, 2));
3749 code = GET_CODE (temp);
3750 op0_mode = VOIDmode;
3751 mode = GET_MODE (temp);
3754 /* First see if we can apply the inverse distributive law. */
3755 if (code == PLUS || code == MINUS
3756 || code == AND || code == IOR || code == XOR)
3758 x = apply_distributive_law (x);
3759 code = GET_CODE (x);
3760 op0_mode = VOIDmode;
3763 /* If CODE is an associative operation not otherwise handled, see if we
3764 can associate some operands. This can win if they are constants or
3765 if they are logically related (i.e. (a & b) & a). */
3766 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
3767 || code == AND || code == IOR || code == XOR
3768 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
3769 && ((INTEGRAL_MODE_P (mode) && code != DIV)
3770 || (flag_unsafe_math_optimizations && FLOAT_MODE_P (mode))))
3772 if (GET_CODE (XEXP (x, 0)) == code)
3774 rtx other = XEXP (XEXP (x, 0), 0);
3775 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
3776 rtx inner_op1 = XEXP (x, 1);
3779 /* Make sure we pass the constant operand if any as the second
3780 one if this is a commutative operation. */
3781 if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
3783 rtx tem = inner_op0;
3784 inner_op0 = inner_op1;
3787 inner = simplify_binary_operation (code == MINUS ? PLUS
3788 : code == DIV ? MULT
3790 mode, inner_op0, inner_op1);
3792 /* For commutative operations, try the other pair if that one
3794 if (inner == 0 && GET_RTX_CLASS (code) == 'c')
3796 other = XEXP (XEXP (x, 0), 1);
3797 inner = simplify_binary_operation (code, mode,
3798 XEXP (XEXP (x, 0), 0),
3803 return gen_binary (code, mode, other, inner);
3807 /* A little bit of algebraic simplification here. */
3811 /* Ensure that our address has any ASHIFTs converted to MULT in case
3812 address-recognizing predicates are called later. */
3813 temp = make_compound_operation (XEXP (x, 0), MEM);
3814 SUBST (XEXP (x, 0), temp);
3818 if (op0_mode == VOIDmode)
3819 op0_mode = GET_MODE (SUBREG_REG (x));
3821 /* See if this can be moved to simplify_subreg. */
3822 if (CONSTANT_P (SUBREG_REG (x))
3823 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
3824 /* Don't call gen_lowpart if the inner mode
3825 is VOIDmode and we cannot simplify it, as SUBREG without
3826 inner mode is invalid. */
3827 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
3828 || gen_lowpart_common (mode, SUBREG_REG (x))))
3829 return gen_lowpart (mode, SUBREG_REG (x));
3831 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
3835 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
3841 /* Don't change the mode of the MEM if that would change the meaning
3843 if (GET_CODE (SUBREG_REG (x)) == MEM
3844 && (MEM_VOLATILE_P (SUBREG_REG (x))
3845 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
3846 return gen_rtx_CLOBBER (mode, const0_rtx);
3848 /* Note that we cannot do any narrowing for non-constants since
3849 we might have been counting on using the fact that some bits were
3850 zero. We now do this in the SET. */
3855 if (GET_CODE (XEXP (x, 0)) == SUBREG
3856 && subreg_lowpart_p (XEXP (x, 0))
3857 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3858 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
3859 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
3860 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3862 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3864 x = gen_rtx_ROTATE (inner_mode,
3865 simplify_gen_unary (NOT, inner_mode, const1_rtx,
3867 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
3868 return gen_lowpart (mode, x);
3871 /* Apply De Morgan's laws to reduce number of patterns for machines
3872 with negating logical insns (and-not, nand, etc.). If result has
3873 only one NOT, put it first, since that is how the patterns are
3876 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
3878 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
3879 enum machine_mode op_mode;
3881 op_mode = GET_MODE (in1);
3882 in1 = simplify_gen_unary (NOT, op_mode, in1, op_mode);
3884 op_mode = GET_MODE (in2);
3885 if (op_mode == VOIDmode)
3887 in2 = simplify_gen_unary (NOT, op_mode, in2, op_mode);
3889 if (GET_CODE (in2) == NOT && GET_CODE (in1) != NOT)
3892 in2 = in1; in1 = tem;
3895 return gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
3901 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
3902 if (GET_CODE (XEXP (x, 0)) == XOR
3903 && XEXP (XEXP (x, 0), 1) == const1_rtx
3904 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
3905 return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3907 temp = expand_compound_operation (XEXP (x, 0));
3909 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3910 replaced by (lshiftrt X C). This will convert
3911 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
3913 if (GET_CODE (temp) == ASHIFTRT
3914 && GET_CODE (XEXP (temp, 1)) == CONST_INT
3915 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
3916 return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
3917 INTVAL (XEXP (temp, 1)));
3919 /* If X has only a single bit that might be nonzero, say, bit I, convert
3920 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
3921 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
3922 (sign_extract X 1 Y). But only do this if TEMP isn't a register
3923 or a SUBREG of one since we'd be making the expression more
3924 complex if it was just a register. */
3926 if (GET_CODE (temp) != REG
3927 && ! (GET_CODE (temp) == SUBREG
3928 && GET_CODE (SUBREG_REG (temp)) == REG)
3929 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
3931 rtx temp1 = simplify_shift_const
3932 (NULL_RTX, ASHIFTRT, mode,
3933 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
3934 GET_MODE_BITSIZE (mode) - 1 - i),
3935 GET_MODE_BITSIZE (mode) - 1 - i);
3937 /* If all we did was surround TEMP with the two shifts, we
3938 haven't improved anything, so don't use it. Otherwise,
3939 we are better off with TEMP1. */
3940 if (GET_CODE (temp1) != ASHIFTRT
3941 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
3942 || XEXP (XEXP (temp1, 0), 0) != temp)
3948 /* We can't handle truncation to a partial integer mode here
3949 because we don't know the real bitsize of the partial
3951 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
3954 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3955 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
3956 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
3958 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
3959 GET_MODE_MASK (mode), NULL_RTX, 0));
3961 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
3962 if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
3963 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
3964 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
3965 return XEXP (XEXP (x, 0), 0);
3967 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
3968 (OP:SI foo:SI) if OP is NEG or ABS. */
3969 if ((GET_CODE (XEXP (x, 0)) == ABS
3970 || GET_CODE (XEXP (x, 0)) == NEG)
3971 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
3972 || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
3973 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
3974 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
3975 XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
3977 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
3979 if (GET_CODE (XEXP (x, 0)) == SUBREG
3980 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE
3981 && subreg_lowpart_p (XEXP (x, 0)))
3982 return SUBREG_REG (XEXP (x, 0));
3984 /* If we know that the value is already truncated, we can
3985 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
3986 is nonzero for the corresponding modes. But don't do this
3987 for an (LSHIFTRT (MULT ...)) since this will cause problems
3988 with the umulXi3_highpart patterns. */
3989 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
3990 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
3991 && num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
3992 >= (unsigned int) (GET_MODE_BITSIZE (mode) + 1)
3993 && ! (GET_CODE (XEXP (x, 0)) == LSHIFTRT
3994 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT))
3995 return gen_lowpart (mode, XEXP (x, 0));
3997 /* A truncate of a comparison can be replaced with a subreg if
3998 STORE_FLAG_VALUE permits. This is like the previous test,
3999 but it works even if the comparison is done in a mode larger
4000 than HOST_BITS_PER_WIDE_INT. */
4001 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4002 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4003 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0)
4004 return gen_lowpart (mode, XEXP (x, 0));
4006 /* Similarly, a truncate of a register whose value is a
4007 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4009 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4010 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
4011 && (temp = get_last_value (XEXP (x, 0)))
4012 && GET_RTX_CLASS (GET_CODE (temp)) == '<')
4013 return gen_lowpart (mode, XEXP (x, 0));
4017 case FLOAT_TRUNCATE:
4018 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4019 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
4020 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4021 return XEXP (XEXP (x, 0), 0);
4023 /* (float_truncate:SF (float_truncate:DF foo:XF))
4024 = (float_truncate:SF foo:XF).
4025 This may eliminate double rounding, so it is unsafe.
4027 (float_truncate:SF (float_extend:XF foo:DF))
4028 = (float_truncate:SF foo:DF).
4030 (float_truncate:DF (float_extend:XF foo:SF))
4031 = (float_extend:SF foo:DF). */
4032 if ((GET_CODE (XEXP (x, 0)) == FLOAT_TRUNCATE
4033 && flag_unsafe_math_optimizations)
4034 || GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND)
4035 return simplify_gen_unary (GET_MODE_SIZE (GET_MODE (XEXP (XEXP (x, 0),
4037 > GET_MODE_SIZE (mode)
4038 ? FLOAT_TRUNCATE : FLOAT_EXTEND,
4040 XEXP (XEXP (x, 0), 0), mode);
4042 /* (float_truncate (float x)) is (float x) */
4043 if (GET_CODE (XEXP (x, 0)) == FLOAT
4044 && (flag_unsafe_math_optimizations
4045 || ((unsigned)significand_size (GET_MODE (XEXP (x, 0)))
4046 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x, 0), 0)))
4047 - num_sign_bit_copies (XEXP (XEXP (x, 0), 0),
4048 GET_MODE (XEXP (XEXP (x, 0), 0)))))))
4049 return simplify_gen_unary (FLOAT, mode,
4050 XEXP (XEXP (x, 0), 0),
4051 GET_MODE (XEXP (XEXP (x, 0), 0)));
4053 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4054 (OP:SF foo:SF) if OP is NEG or ABS. */
4055 if ((GET_CODE (XEXP (x, 0)) == ABS
4056 || GET_CODE (XEXP (x, 0)) == NEG)
4057 && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
4058 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4059 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4060 XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
4062 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4063 is (float_truncate:SF x). */
4064 if (GET_CODE (XEXP (x, 0)) == SUBREG
4065 && subreg_lowpart_p (XEXP (x, 0))
4066 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
4067 return SUBREG_REG (XEXP (x, 0));
4070 /* (float_extend (float_extend x)) is (float_extend x)
4072 (float_extend (float x)) is (float x) assuming that double
4073 rounding can't happen.
4075 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
4076 || (GET_CODE (XEXP (x, 0)) == FLOAT
4077 && ((unsigned)significand_size (GET_MODE (XEXP (x, 0)))
4078 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x, 0), 0)))
4079 - num_sign_bit_copies (XEXP (XEXP (x, 0), 0),
4080 GET_MODE (XEXP (XEXP (x, 0), 0)))))))
4081 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4082 XEXP (XEXP (x, 0), 0),
4083 GET_MODE (XEXP (XEXP (x, 0), 0)));
4088 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4089 using cc0, in which case we want to leave it as a COMPARE
4090 so we can distinguish it from a register-register-copy. */
4091 if (XEXP (x, 1) == const0_rtx)
4094 /* x - 0 is the same as x unless x's mode has signed zeros and
4095 allows rounding towards -infinity. Under those conditions,
4097 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x, 0)))
4098 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x, 0))))
4099 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4105 /* (const (const X)) can become (const X). Do it this way rather than
4106 returning the inner CONST since CONST can be shared with a
4108 if (GET_CODE (XEXP (x, 0)) == CONST)
4109 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4114 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4115 can add in an offset. find_split_point will split this address up
4116 again if it doesn't match. */
4117 if (GET_CODE (XEXP (x, 0)) == HIGH
4118 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4124 /* Canonicalize (plus (mult (neg B) C) A) to (minus A (mult B C)).
4126 if (GET_CODE (XEXP (x, 0)) == MULT
4127 && GET_CODE (XEXP (XEXP (x, 0), 0)) == NEG)
4131 in1 = XEXP (XEXP (XEXP (x, 0), 0), 0);
4132 in2 = XEXP (XEXP (x, 0), 1);
4133 return gen_binary (MINUS, mode, XEXP (x, 1),
4134 gen_binary (MULT, mode, in1, in2));
4137 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4138 outermost. That's because that's the way indexed addresses are
4139 supposed to appear. This code used to check many more cases, but
4140 they are now checked elsewhere. */
4141 if (GET_CODE (XEXP (x, 0)) == PLUS
4142 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
4143 return gen_binary (PLUS, mode,
4144 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
4146 XEXP (XEXP (x, 0), 1));
4148 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4149 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4150 bit-field and can be replaced by either a sign_extend or a
4151 sign_extract. The `and' may be a zero_extend and the two
4152 <c>, -<c> constants may be reversed. */
4153 if (GET_CODE (XEXP (x, 0)) == XOR
4154 && GET_CODE (XEXP (x, 1)) == CONST_INT
4155 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4156 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
4157 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4158 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4159 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4160 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4161 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4162 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4163 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4164 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4165 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4166 == (unsigned int) i + 1))))
4167 return simplify_shift_const
4168 (NULL_RTX, ASHIFTRT, mode,
4169 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4170 XEXP (XEXP (XEXP (x, 0), 0), 0),
4171 GET_MODE_BITSIZE (mode) - (i + 1)),
4172 GET_MODE_BITSIZE (mode) - (i + 1));
4174 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4175 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4176 is 1. This produces better code than the alternative immediately
4178 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4179 && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
4180 || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx))
4181 && (reversed = reversed_comparison (XEXP (x, 0), mode,
4182 XEXP (XEXP (x, 0), 0),
4183 XEXP (XEXP (x, 0), 1))))
4185 simplify_gen_unary (NEG, mode, reversed, mode);
4187 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4188 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4189 the bitsize of the mode - 1. This allows simplification of
4190 "a = (b & 8) == 0;" */
4191 if (XEXP (x, 1) == constm1_rtx
4192 && GET_CODE (XEXP (x, 0)) != REG
4193 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4194 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
4195 && nonzero_bits (XEXP (x, 0), mode) == 1)
4196 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4197 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4198 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
4199 GET_MODE_BITSIZE (mode) - 1),
4200 GET_MODE_BITSIZE (mode) - 1);
4202 /* If we are adding two things that have no bits in common, convert
4203 the addition into an IOR. This will often be further simplified,
4204 for example in cases like ((a & 1) + (a & 2)), which can
4207 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4208 && (nonzero_bits (XEXP (x, 0), mode)
4209 & nonzero_bits (XEXP (x, 1), mode)) == 0)
4211 /* Try to simplify the expression further. */
4212 rtx tor = gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4213 temp = combine_simplify_rtx (tor, mode, last, in_dest);
4215 /* If we could, great. If not, do not go ahead with the IOR
4216 replacement, since PLUS appears in many special purpose
4217 address arithmetic instructions. */
4218 if (GET_CODE (temp) != CLOBBER && temp != tor)
4224 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4225 by reversing the comparison code if valid. */
4226 if (STORE_FLAG_VALUE == 1
4227 && XEXP (x, 0) == const1_rtx
4228 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<'
4229 && (reversed = reversed_comparison (XEXP (x, 1), mode,
4230 XEXP (XEXP (x, 1), 0),
4231 XEXP (XEXP (x, 1), 1))))
4234 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4235 (and <foo> (const_int pow2-1)) */
4236 if (GET_CODE (XEXP (x, 1)) == AND
4237 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4238 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4239 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4240 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4241 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4243 /* Canonicalize (minus A (mult (neg B) C)) to (plus (mult B C) A).
4245 if (GET_CODE (XEXP (x, 1)) == MULT
4246 && GET_CODE (XEXP (XEXP (x, 1), 0)) == NEG)
4250 in1 = XEXP (XEXP (XEXP (x, 1), 0), 0);
4251 in2 = XEXP (XEXP (x, 1), 1);
4252 return gen_binary (PLUS, mode, gen_binary (MULT, mode, in1, in2),
4256 /* Canonicalize (minus (neg A) (mult B C)) to
4257 (minus (mult (neg B) C) A). */
4258 if (GET_CODE (XEXP (x, 1)) == MULT
4259 && GET_CODE (XEXP (x, 0)) == NEG)
4263 in1 = simplify_gen_unary (NEG, mode, XEXP (XEXP (x, 1), 0), mode);
4264 in2 = XEXP (XEXP (x, 1), 1);
4265 return gen_binary (MINUS, mode, gen_binary (MULT, mode, in1, in2),
4266 XEXP (XEXP (x, 0), 0));
4269 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4271 if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
4272 return gen_binary (MINUS, mode,
4273 gen_binary (MINUS, mode, XEXP (x, 0),
4274 XEXP (XEXP (x, 1), 0)),
4275 XEXP (XEXP (x, 1), 1));
4279 /* If we have (mult (plus A B) C), apply the distributive law and then
4280 the inverse distributive law to see if things simplify. This
4281 occurs mostly in addresses, often when unrolling loops. */
4283 if (GET_CODE (XEXP (x, 0)) == PLUS)
4285 x = apply_distributive_law
4286 (gen_binary (PLUS, mode,
4287 gen_binary (MULT, mode,
4288 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
4289 gen_binary (MULT, mode,
4290 XEXP (XEXP (x, 0), 1),
4291 copy_rtx (XEXP (x, 1)))));
4293 if (GET_CODE (x) != MULT)
4296 /* Try simplify a*(b/c) as (a*b)/c. */
4297 if (FLOAT_MODE_P (mode) && flag_unsafe_math_optimizations
4298 && GET_CODE (XEXP (x, 0)) == DIV)
4300 rtx tem = simplify_binary_operation (MULT, mode,
4301 XEXP (XEXP (x, 0), 0),
4304 return gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
4309 /* If this is a divide by a power of two, treat it as a shift if
4310 its first operand is a shift. */
4311 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4312 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4313 && (GET_CODE (XEXP (x, 0)) == ASHIFT
4314 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4315 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4316 || GET_CODE (XEXP (x, 0)) == ROTATE
4317 || GET_CODE (XEXP (x, 0)) == ROTATERT))
4318 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
4322 case GT: case GTU: case GE: case GEU:
4323 case LT: case LTU: case LE: case LEU:
4324 case UNEQ: case LTGT:
4325 case UNGT: case UNGE:
4326 case UNLT: case UNLE:
4327 case UNORDERED: case ORDERED:
4328 /* If the first operand is a condition code, we can't do anything
4330 if (GET_CODE (XEXP (x, 0)) == COMPARE
4331 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4332 && ! CC0_P (XEXP (x, 0))))
4334 rtx op0 = XEXP (x, 0);
4335 rtx op1 = XEXP (x, 1);
4336 enum rtx_code new_code;
4338 if (GET_CODE (op0) == COMPARE)
4339 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4341 /* Simplify our comparison, if possible. */
4342 new_code = simplify_comparison (code, &op0, &op1);
4344 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4345 if only the low-order bit is possibly nonzero in X (such as when
4346 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4347 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4348 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4351 Remove any ZERO_EXTRACT we made when thinking this was a
4352 comparison. It may now be simpler to use, e.g., an AND. If a
4353 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4354 the call to make_compound_operation in the SET case. */
4356 if (STORE_FLAG_VALUE == 1
4357 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4358 && op1 == const0_rtx
4359 && mode == GET_MODE (op0)
4360 && nonzero_bits (op0, mode) == 1)
4361 return gen_lowpart (mode,
4362 expand_compound_operation (op0));
4364 else if (STORE_FLAG_VALUE == 1
4365 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4366 && op1 == const0_rtx
4367 && mode == GET_MODE (op0)
4368 && (num_sign_bit_copies (op0, mode)
4369 == GET_MODE_BITSIZE (mode)))
4371 op0 = expand_compound_operation (op0);
4372 return simplify_gen_unary (NEG, mode,
4373 gen_lowpart (mode, op0),
4377 else if (STORE_FLAG_VALUE == 1
4378 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4379 && op1 == const0_rtx
4380 && mode == GET_MODE (op0)
4381 && nonzero_bits (op0, mode) == 1)
4383 op0 = expand_compound_operation (op0);
4384 return gen_binary (XOR, mode,
4385 gen_lowpart (mode, op0),
4389 else if (STORE_FLAG_VALUE == 1
4390 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4391 && op1 == const0_rtx
4392 && mode == GET_MODE (op0)
4393 && (num_sign_bit_copies (op0, mode)
4394 == GET_MODE_BITSIZE (mode)))
4396 op0 = expand_compound_operation (op0);
4397 return plus_constant (gen_lowpart (mode, op0), 1);
4400 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4402 if (STORE_FLAG_VALUE == -1
4403 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4404 && op1 == const0_rtx
4405 && (num_sign_bit_copies (op0, mode)
4406 == GET_MODE_BITSIZE (mode)))
4407 return gen_lowpart (mode,
4408 expand_compound_operation (op0));
4410 else if (STORE_FLAG_VALUE == -1
4411 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4412 && op1 == const0_rtx
4413 && mode == GET_MODE (op0)
4414 && nonzero_bits (op0, mode) == 1)
4416 op0 = expand_compound_operation (op0);
4417 return simplify_gen_unary (NEG, mode,
4418 gen_lowpart (mode, op0),
4422 else if (STORE_FLAG_VALUE == -1
4423 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4424 && op1 == const0_rtx
4425 && mode == GET_MODE (op0)
4426 && (num_sign_bit_copies (op0, mode)
4427 == GET_MODE_BITSIZE (mode)))
4429 op0 = expand_compound_operation (op0);
4430 return simplify_gen_unary (NOT, mode,
4431 gen_lowpart (mode, op0),
4435 /* If X is 0/1, (eq X 0) is X-1. */
4436 else if (STORE_FLAG_VALUE == -1
4437 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4438 && op1 == const0_rtx
4439 && mode == GET_MODE (op0)
4440 && nonzero_bits (op0, mode) == 1)
4442 op0 = expand_compound_operation (op0);
4443 return plus_constant (gen_lowpart (mode, op0), -1);
4446 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4447 one bit that might be nonzero, we can convert (ne x 0) to
4448 (ashift x c) where C puts the bit in the sign bit. Remove any
4449 AND with STORE_FLAG_VALUE when we are done, since we are only
4450 going to test the sign bit. */
4451 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4452 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4453 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4454 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
4455 && op1 == const0_rtx
4456 && mode == GET_MODE (op0)
4457 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4459 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4460 expand_compound_operation (op0),
4461 GET_MODE_BITSIZE (mode) - 1 - i);
4462 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4468 /* If the code changed, return a whole new comparison. */
4469 if (new_code != code)
4470 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
4472 /* Otherwise, keep this operation, but maybe change its operands.
4473 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4474 SUBST (XEXP (x, 0), op0);
4475 SUBST (XEXP (x, 1), op1);
4480 return simplify_if_then_else (x);
4486 /* If we are processing SET_DEST, we are done. */
4490 return expand_compound_operation (x);
4493 return simplify_set (x);
4498 return simplify_logical (x, last);
4501 /* (abs (neg <foo>)) -> (abs <foo>) */
4502 if (GET_CODE (XEXP (x, 0)) == NEG)
4503 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4505 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4507 if (GET_MODE (XEXP (x, 0)) == VOIDmode)
4510 /* If operand is something known to be positive, ignore the ABS. */
4511 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4512 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4513 <= HOST_BITS_PER_WIDE_INT)
4514 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4515 & ((HOST_WIDE_INT) 1
4516 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4520 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4521 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4522 return gen_rtx_NEG (mode, XEXP (x, 0));
4527 /* (ffs (*_extend <X>)) = (ffs <X>) */
4528 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4529 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4530 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4535 /* (pop* (zero_extend <X>)) = (pop* <X>) */
4536 if (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4537 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4541 /* (float (sign_extend <X>)) = (float <X>). */
4542 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4543 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4551 /* If this is a shift by a constant amount, simplify it. */
4552 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4553 return simplify_shift_const (x, code, mode, XEXP (x, 0),
4554 INTVAL (XEXP (x, 1)));
4556 else if (SHIFT_COUNT_TRUNCATED && GET_CODE (XEXP (x, 1)) != REG)
4558 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
4560 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4567 rtx op0 = XEXP (x, 0);
4568 rtx op1 = XEXP (x, 1);
4571 if (GET_CODE (op1) != PARALLEL)
4573 len = XVECLEN (op1, 0);
4575 && GET_CODE (XVECEXP (op1, 0, 0)) == CONST_INT
4576 && GET_CODE (op0) == VEC_CONCAT)
4578 int offset = INTVAL (XVECEXP (op1, 0, 0)) * GET_MODE_SIZE (GET_MODE (x));
4580 /* Try to find the element in the VEC_CONCAT. */
4583 if (GET_MODE (op0) == GET_MODE (x))
4585 if (GET_CODE (op0) == VEC_CONCAT)
4587 HOST_WIDE_INT op0_size = GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)));
4588 if (op0_size < offset)
4589 op0 = XEXP (op0, 0);
4593 op0 = XEXP (op0, 1);
4611 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4614 simplify_if_then_else (rtx x)
4616 enum machine_mode mode = GET_MODE (x);
4617 rtx cond = XEXP (x, 0);
4618 rtx true_rtx = XEXP (x, 1);
4619 rtx false_rtx = XEXP (x, 2);
4620 enum rtx_code true_code = GET_CODE (cond);
4621 int comparison_p = GET_RTX_CLASS (true_code) == '<';
4624 enum rtx_code false_code;
4627 /* Simplify storing of the truth value. */
4628 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
4629 return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1));
4631 /* Also when the truth value has to be reversed. */
4633 && true_rtx == const0_rtx && false_rtx == const_true_rtx
4634 && (reversed = reversed_comparison (cond, mode, XEXP (cond, 0),
4638 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4639 in it is being compared against certain values. Get the true and false
4640 comparisons and see if that says anything about the value of each arm. */
4643 && ((false_code = combine_reversed_comparison_code (cond))
4645 && GET_CODE (XEXP (cond, 0)) == REG)
4648 rtx from = XEXP (cond, 0);
4649 rtx true_val = XEXP (cond, 1);
4650 rtx false_val = true_val;
4653 /* If FALSE_CODE is EQ, swap the codes and arms. */
4655 if (false_code == EQ)
4657 swapped = 1, true_code = EQ, false_code = NE;
4658 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4661 /* If we are comparing against zero and the expression being tested has
4662 only a single bit that might be nonzero, that is its value when it is
4663 not equal to zero. Similarly if it is known to be -1 or 0. */
4665 if (true_code == EQ && true_val == const0_rtx
4666 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4667 false_code = EQ, false_val = GEN_INT (nzb);
4668 else if (true_code == EQ && true_val == const0_rtx
4669 && (num_sign_bit_copies (from, GET_MODE (from))
4670 == GET_MODE_BITSIZE (GET_MODE (from))))
4671 false_code = EQ, false_val = constm1_rtx;
4673 /* Now simplify an arm if we know the value of the register in the
4674 branch and it is used in the arm. Be careful due to the potential
4675 of locally-shared RTL. */
4677 if (reg_mentioned_p (from, true_rtx))
4678 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
4680 pc_rtx, pc_rtx, 0, 0);
4681 if (reg_mentioned_p (from, false_rtx))
4682 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
4684 pc_rtx, pc_rtx, 0, 0);
4686 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
4687 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
4689 true_rtx = XEXP (x, 1);
4690 false_rtx = XEXP (x, 2);
4691 true_code = GET_CODE (cond);
4694 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4695 reversed, do so to avoid needing two sets of patterns for
4696 subtract-and-branch insns. Similarly if we have a constant in the true
4697 arm, the false arm is the same as the first operand of the comparison, or
4698 the false arm is more complicated than the true arm. */
4701 && combine_reversed_comparison_code (cond) != UNKNOWN
4702 && (true_rtx == pc_rtx
4703 || (CONSTANT_P (true_rtx)
4704 && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx)
4705 || true_rtx == const0_rtx
4706 || (GET_RTX_CLASS (GET_CODE (true_rtx)) == 'o'
4707 && GET_RTX_CLASS (GET_CODE (false_rtx)) != 'o')
4708 || (GET_CODE (true_rtx) == SUBREG
4709 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true_rtx))) == 'o'
4710 && GET_RTX_CLASS (GET_CODE (false_rtx)) != 'o')
4711 || reg_mentioned_p (true_rtx, false_rtx)
4712 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
4714 true_code = reversed_comparison_code (cond, NULL);
4716 reversed_comparison (cond, GET_MODE (cond), XEXP (cond, 0),
4719 SUBST (XEXP (x, 1), false_rtx);
4720 SUBST (XEXP (x, 2), true_rtx);
4722 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4725 /* It is possible that the conditional has been simplified out. */
4726 true_code = GET_CODE (cond);
4727 comparison_p = GET_RTX_CLASS (true_code) == '<';
4730 /* If the two arms are identical, we don't need the comparison. */
4732 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
4735 /* Convert a == b ? b : a to "a". */
4736 if (true_code == EQ && ! side_effects_p (cond)
4737 && !HONOR_NANS (mode)
4738 && rtx_equal_p (XEXP (cond, 0), false_rtx)
4739 && rtx_equal_p (XEXP (cond, 1), true_rtx))
4741 else if (true_code == NE && ! side_effects_p (cond)
4742 && !HONOR_NANS (mode)
4743 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4744 && rtx_equal_p (XEXP (cond, 1), false_rtx))
4747 /* Look for cases where we have (abs x) or (neg (abs X)). */
4749 if (GET_MODE_CLASS (mode) == MODE_INT
4750 && GET_CODE (false_rtx) == NEG
4751 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
4753 && rtx_equal_p (true_rtx, XEXP (cond, 0))
4754 && ! side_effects_p (true_rtx))
4759 return simplify_gen_unary (ABS, mode, true_rtx, mode);
4763 simplify_gen_unary (NEG, mode,
4764 simplify_gen_unary (ABS, mode, true_rtx, mode),
4770 /* Look for MIN or MAX. */
4772 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4774 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4775 && rtx_equal_p (XEXP (cond, 1), false_rtx)
4776 && ! side_effects_p (cond))
4781 return gen_binary (SMAX, mode, true_rtx, false_rtx);
4784 return gen_binary (SMIN, mode, true_rtx, false_rtx);
4787 return gen_binary (UMAX, mode, true_rtx, false_rtx);
4790 return gen_binary (UMIN, mode, true_rtx, false_rtx);
4795 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4796 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4797 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4798 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4799 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4800 neither 1 or -1, but it isn't worth checking for. */
4802 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4804 && GET_MODE_CLASS (mode) == MODE_INT
4805 && ! side_effects_p (x))
4807 rtx t = make_compound_operation (true_rtx, SET);
4808 rtx f = make_compound_operation (false_rtx, SET);
4809 rtx cond_op0 = XEXP (cond, 0);
4810 rtx cond_op1 = XEXP (cond, 1);
4811 enum rtx_code op = NIL, extend_op = NIL;
4812 enum machine_mode m = mode;
4813 rtx z = 0, c1 = NULL_RTX;
4815 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4816 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4817 || GET_CODE (t) == ASHIFT
4818 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4819 && rtx_equal_p (XEXP (t, 0), f))
4820 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4822 /* If an identity-zero op is commutative, check whether there
4823 would be a match if we swapped the operands. */
4824 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4825 || GET_CODE (t) == XOR)
4826 && rtx_equal_p (XEXP (t, 1), f))
4827 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4828 else if (GET_CODE (t) == SIGN_EXTEND
4829 && (GET_CODE (XEXP (t, 0)) == PLUS
4830 || GET_CODE (XEXP (t, 0)) == MINUS
4831 || GET_CODE (XEXP (t, 0)) == IOR
4832 || GET_CODE (XEXP (t, 0)) == XOR
4833 || GET_CODE (XEXP (t, 0)) == ASHIFT
4834 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4835 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4836 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4837 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4838 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4839 && (num_sign_bit_copies (f, GET_MODE (f))
4841 (GET_MODE_BITSIZE (mode)
4842 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
4844 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4845 extend_op = SIGN_EXTEND;
4846 m = GET_MODE (XEXP (t, 0));
4848 else if (GET_CODE (t) == SIGN_EXTEND
4849 && (GET_CODE (XEXP (t, 0)) == PLUS
4850 || GET_CODE (XEXP (t, 0)) == IOR
4851 || GET_CODE (XEXP (t, 0)) == XOR)
4852 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4853 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4854 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4855 && (num_sign_bit_copies (f, GET_MODE (f))
4857 (GET_MODE_BITSIZE (mode)
4858 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
4860 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4861 extend_op = SIGN_EXTEND;
4862 m = GET_MODE (XEXP (t, 0));
4864 else if (GET_CODE (t) == ZERO_EXTEND
4865 && (GET_CODE (XEXP (t, 0)) == PLUS
4866 || GET_CODE (XEXP (t, 0)) == MINUS
4867 || GET_CODE (XEXP (t, 0)) == IOR
4868 || GET_CODE (XEXP (t, 0)) == XOR
4869 || GET_CODE (XEXP (t, 0)) == ASHIFT
4870 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4871 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4872 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4873 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4874 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4875 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4876 && ((nonzero_bits (f, GET_MODE (f))
4877 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
4880 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4881 extend_op = ZERO_EXTEND;
4882 m = GET_MODE (XEXP (t, 0));
4884 else if (GET_CODE (t) == ZERO_EXTEND
4885 && (GET_CODE (XEXP (t, 0)) == PLUS
4886 || GET_CODE (XEXP (t, 0)) == IOR
4887 || GET_CODE (XEXP (t, 0)) == XOR)
4888 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4889 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4890 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4891 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4892 && ((nonzero_bits (f, GET_MODE (f))
4893 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
4896 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4897 extend_op = ZERO_EXTEND;
4898 m = GET_MODE (XEXP (t, 0));
4903 temp = subst (gen_binary (true_code, m, cond_op0, cond_op1),
4904 pc_rtx, pc_rtx, 0, 0);
4905 temp = gen_binary (MULT, m, temp,
4906 gen_binary (MULT, m, c1, const_true_rtx));
4907 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
4908 temp = gen_binary (op, m, gen_lowpart (m, z), temp);
4910 if (extend_op != NIL)
4911 temp = simplify_gen_unary (extend_op, mode, temp, m);
4917 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4918 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4919 negation of a single bit, we can convert this operation to a shift. We
4920 can actually do this more generally, but it doesn't seem worth it. */
4922 if (true_code == NE && XEXP (cond, 1) == const0_rtx
4923 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
4924 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
4925 && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
4926 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
4927 == GET_MODE_BITSIZE (mode))
4928 && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
4930 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4931 gen_lowpart (mode, XEXP (cond, 0)), i);
4933 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
4934 if (true_code == NE && XEXP (cond, 1) == const0_rtx
4935 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
4936 && GET_MODE (XEXP (cond, 0)) == mode
4937 && (INTVAL (true_rtx) & GET_MODE_MASK (mode))
4938 == nonzero_bits (XEXP (cond, 0), mode)
4939 && (i = exact_log2 (INTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
4940 return XEXP (cond, 0);
4945 /* Simplify X, a SET expression. Return the new expression. */
4948 simplify_set (rtx x)
4950 rtx src = SET_SRC (x);
4951 rtx dest = SET_DEST (x);
4952 enum machine_mode mode
4953 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
4957 /* (set (pc) (return)) gets written as (return). */
4958 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
4961 /* Now that we know for sure which bits of SRC we are using, see if we can
4962 simplify the expression for the object knowing that we only need the
4965 if (GET_MODE_CLASS (mode) == MODE_INT
4966 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
4968 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, NULL_RTX, 0);
4969 SUBST (SET_SRC (x), src);
4972 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4973 the comparison result and try to simplify it unless we already have used
4974 undobuf.other_insn. */
4975 if ((GET_MODE_CLASS (mode) == MODE_CC
4976 || GET_CODE (src) == COMPARE
4978 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
4979 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
4980 && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
4981 && rtx_equal_p (XEXP (*cc_use, 0), dest))
4983 enum rtx_code old_code = GET_CODE (*cc_use);
4984 enum rtx_code new_code;
4986 int other_changed = 0;
4987 enum machine_mode compare_mode = GET_MODE (dest);
4988 enum machine_mode tmp_mode;
4990 if (GET_CODE (src) == COMPARE)
4991 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
4993 op0 = src, op1 = const0_rtx;
4995 /* Check whether the comparison is known at compile time. */
4996 if (GET_MODE (op0) != VOIDmode)
4997 tmp_mode = GET_MODE (op0);
4998 else if (GET_MODE (op1) != VOIDmode)
4999 tmp_mode = GET_MODE (op1);
5001 tmp_mode = compare_mode;
5002 tmp = simplify_relational_operation (old_code, tmp_mode, op0, op1);
5003 if (tmp != NULL_RTX)
5005 rtx pat = PATTERN (other_insn);
5006 undobuf.other_insn = other_insn;
5007 SUBST (*cc_use, tmp);
5009 /* Attempt to simplify CC user. */
5010 if (GET_CODE (pat) == SET)
5012 rtx new = simplify_rtx (SET_SRC (pat));
5013 if (new != NULL_RTX)
5014 SUBST (SET_SRC (pat), new);
5017 /* Convert X into a no-op move. */
5018 SUBST (SET_DEST (x), pc_rtx);
5019 SUBST (SET_SRC (x), pc_rtx);
5023 /* Simplify our comparison, if possible. */
5024 new_code = simplify_comparison (old_code, &op0, &op1);
5026 #ifdef SELECT_CC_MODE
5027 /* If this machine has CC modes other than CCmode, check to see if we
5028 need to use a different CC mode here. */
5029 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5032 /* If the mode changed, we have to change SET_DEST, the mode in the
5033 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5034 a hard register, just build new versions with the proper mode. If it
5035 is a pseudo, we lose unless it is only time we set the pseudo, in
5036 which case we can safely change its mode. */
5037 if (compare_mode != GET_MODE (dest))
5039 unsigned int regno = REGNO (dest);
5040 rtx new_dest = gen_rtx_REG (compare_mode, regno);
5042 if (regno < FIRST_PSEUDO_REGISTER
5043 || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest)))
5045 if (regno >= FIRST_PSEUDO_REGISTER)
5046 SUBST (regno_reg_rtx[regno], new_dest);
5048 SUBST (SET_DEST (x), new_dest);
5049 SUBST (XEXP (*cc_use, 0), new_dest);
5056 #endif /* SELECT_CC_MODE */
5058 /* If the code changed, we have to build a new comparison in
5059 undobuf.other_insn. */
5060 if (new_code != old_code)
5062 int other_changed_previously = other_changed;
5063 unsigned HOST_WIDE_INT mask;
5065 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5069 /* If the only change we made was to change an EQ into an NE or
5070 vice versa, OP0 has only one bit that might be nonzero, and OP1
5071 is zero, check if changing the user of the condition code will
5072 produce a valid insn. If it won't, we can keep the original code
5073 in that insn by surrounding our operation with an XOR. */
5075 if (((old_code == NE && new_code == EQ)
5076 || (old_code == EQ && new_code == NE))
5077 && ! other_changed_previously && op1 == const0_rtx
5078 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5079 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5081 rtx pat = PATTERN (other_insn), note = 0;
5083 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
5084 && ! check_asm_operands (pat)))
5086 PUT_CODE (*cc_use, old_code);
5089 op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask));
5095 undobuf.other_insn = other_insn;
5098 /* If we are now comparing against zero, change our source if
5099 needed. If we do not use cc0, we always have a COMPARE. */
5100 if (op1 == const0_rtx && dest == cc0_rtx)
5102 SUBST (SET_SRC (x), op0);
5108 /* Otherwise, if we didn't previously have a COMPARE in the
5109 correct mode, we need one. */
5110 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5112 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5117 /* Otherwise, update the COMPARE if needed. */
5118 SUBST (XEXP (src, 0), op0);
5119 SUBST (XEXP (src, 1), op1);
5124 /* Get SET_SRC in a form where we have placed back any
5125 compound expressions. Then do the checks below. */
5126 src = make_compound_operation (src, SET);
5127 SUBST (SET_SRC (x), src);
5130 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5131 and X being a REG or (subreg (reg)), we may be able to convert this to
5132 (set (subreg:m2 x) (op)).
5134 We can always do this if M1 is narrower than M2 because that means that
5135 we only care about the low bits of the result.
5137 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5138 perform a narrower operation than requested since the high-order bits will
5139 be undefined. On machine where it is defined, this transformation is safe
5140 as long as M1 and M2 have the same number of words. */
5142 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5143 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src))) != 'o'
5144 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5146 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5147 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5148 #ifndef WORD_REGISTER_OPERATIONS
5149 && (GET_MODE_SIZE (GET_MODE (src))
5150 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5152 #ifdef CANNOT_CHANGE_MODE_CLASS
5153 && ! (GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER
5154 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
5155 GET_MODE (SUBREG_REG (src)),
5158 && (GET_CODE (dest) == REG
5159 || (GET_CODE (dest) == SUBREG
5160 && GET_CODE (SUBREG_REG (dest)) == REG)))
5162 SUBST (SET_DEST (x),
5163 gen_lowpart (GET_MODE (SUBREG_REG (src)),
5165 SUBST (SET_SRC (x), SUBREG_REG (src));
5167 src = SET_SRC (x), dest = SET_DEST (x);
5171 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5174 && GET_CODE (src) == SUBREG
5175 && subreg_lowpart_p (src)
5176 && (GET_MODE_BITSIZE (GET_MODE (src))
5177 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
5179 rtx inner = SUBREG_REG (src);
5180 enum machine_mode inner_mode = GET_MODE (inner);
5182 /* Here we make sure that we don't have a sign bit on. */
5183 if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
5184 && (nonzero_bits (inner, inner_mode)
5185 < ((unsigned HOST_WIDE_INT) 1
5186 << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
5188 SUBST (SET_SRC (x), inner);
5194 #ifdef LOAD_EXTEND_OP
5195 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5196 would require a paradoxical subreg. Replace the subreg with a
5197 zero_extend to avoid the reload that would otherwise be required. */
5199 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5200 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL
5201 && SUBREG_BYTE (src) == 0
5202 && (GET_MODE_SIZE (GET_MODE (src))
5203 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5204 && GET_CODE (SUBREG_REG (src)) == MEM)
5207 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5208 GET_MODE (src), SUBREG_REG (src)));
5214 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5215 are comparing an item known to be 0 or -1 against 0, use a logical
5216 operation instead. Check for one of the arms being an IOR of the other
5217 arm with some value. We compute three terms to be IOR'ed together. In
5218 practice, at most two will be nonzero. Then we do the IOR's. */
5220 if (GET_CODE (dest) != PC
5221 && GET_CODE (src) == IF_THEN_ELSE
5222 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5223 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5224 && XEXP (XEXP (src, 0), 1) == const0_rtx
5225 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5226 #ifdef HAVE_conditional_move
5227 && ! can_conditionally_move_p (GET_MODE (src))
5229 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5230 GET_MODE (XEXP (XEXP (src, 0), 0)))
5231 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5232 && ! side_effects_p (src))
5234 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
5235 ? XEXP (src, 1) : XEXP (src, 2));
5236 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
5237 ? XEXP (src, 2) : XEXP (src, 1));
5238 rtx term1 = const0_rtx, term2, term3;
5240 if (GET_CODE (true_rtx) == IOR
5241 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
5242 term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
5243 else if (GET_CODE (true_rtx) == IOR
5244 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
5245 term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
5246 else if (GET_CODE (false_rtx) == IOR
5247 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
5248 term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
5249 else if (GET_CODE (false_rtx) == IOR
5250 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
5251 term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
5253 term2 = gen_binary (AND, GET_MODE (src),
5254 XEXP (XEXP (src, 0), 0), true_rtx);
5255 term3 = gen_binary (AND, GET_MODE (src),
5256 simplify_gen_unary (NOT, GET_MODE (src),
5257 XEXP (XEXP (src, 0), 0),
5262 gen_binary (IOR, GET_MODE (src),
5263 gen_binary (IOR, GET_MODE (src), term1, term2),
5269 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5270 whole thing fail. */
5271 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5273 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5276 /* Convert this into a field assignment operation, if possible. */
5277 return make_field_assignment (x);
5280 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5281 result. LAST is nonzero if this is the last retry. */
5284 simplify_logical (rtx x, int last)
5286 enum machine_mode mode = GET_MODE (x);
5287 rtx op0 = XEXP (x, 0);
5288 rtx op1 = XEXP (x, 1);
5291 switch (GET_CODE (x))
5294 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5295 insn (and may simplify more). */
5296 if (GET_CODE (op0) == XOR
5297 && rtx_equal_p (XEXP (op0, 0), op1)
5298 && ! side_effects_p (op1))
5299 x = gen_binary (AND, mode,
5300 simplify_gen_unary (NOT, mode, XEXP (op0, 1), mode),
5303 if (GET_CODE (op0) == XOR
5304 && rtx_equal_p (XEXP (op0, 1), op1)
5305 && ! side_effects_p (op1))
5306 x = gen_binary (AND, mode,
5307 simplify_gen_unary (NOT, mode, XEXP (op0, 0), mode),
5310 /* Similarly for (~(A ^ B)) & A. */
5311 if (GET_CODE (op0) == NOT
5312 && GET_CODE (XEXP (op0, 0)) == XOR
5313 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
5314 && ! side_effects_p (op1))
5315 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
5317 if (GET_CODE (op0) == NOT
5318 && GET_CODE (XEXP (op0, 0)) == XOR
5319 && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
5320 && ! side_effects_p (op1))
5321 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
5323 /* We can call simplify_and_const_int only if we don't lose
5324 any (sign) bits when converting INTVAL (op1) to
5325 "unsigned HOST_WIDE_INT". */
5326 if (GET_CODE (op1) == CONST_INT
5327 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5328 || INTVAL (op1) > 0))
5330 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5332 /* If we have (ior (and (X C1) C2)) and the next restart would be
5333 the last, simplify this by making C1 as small as possible
5336 && GET_CODE (x) == IOR && GET_CODE (op0) == AND
5337 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5338 && GET_CODE (op1) == CONST_INT)
5339 return gen_binary (IOR, mode,
5340 gen_binary (AND, mode, XEXP (op0, 0),
5341 GEN_INT (INTVAL (XEXP (op0, 1))
5342 & ~INTVAL (op1))), op1);
5344 if (GET_CODE (x) != AND)
5347 if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
5348 || GET_RTX_CLASS (GET_CODE (x)) == '2')
5349 op0 = XEXP (x, 0), op1 = XEXP (x, 1);
5352 /* Convert (A | B) & A to A. */
5353 if (GET_CODE (op0) == IOR
5354 && (rtx_equal_p (XEXP (op0, 0), op1)
5355 || rtx_equal_p (XEXP (op0, 1), op1))
5356 && ! side_effects_p (XEXP (op0, 0))
5357 && ! side_effects_p (XEXP (op0, 1)))
5360 /* In the following group of tests (and those in case IOR below),
5361 we start with some combination of logical operations and apply
5362 the distributive law followed by the inverse distributive law.
5363 Most of the time, this results in no change. However, if some of
5364 the operands are the same or inverses of each other, simplifications
5367 For example, (and (ior A B) (not B)) can occur as the result of
5368 expanding a bit field assignment. When we apply the distributive
5369 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5370 which then simplifies to (and (A (not B))).
5372 If we have (and (ior A B) C), apply the distributive law and then
5373 the inverse distributive law to see if things simplify. */
5375 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5377 x = apply_distributive_law
5378 (gen_binary (GET_CODE (op0), mode,
5379 gen_binary (AND, mode, XEXP (op0, 0), op1),
5380 gen_binary (AND, mode, XEXP (op0, 1),
5382 if (GET_CODE (x) != AND)
5386 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5387 return apply_distributive_law
5388 (gen_binary (GET_CODE (op1), mode,
5389 gen_binary (AND, mode, XEXP (op1, 0), op0),
5390 gen_binary (AND, mode, XEXP (op1, 1),
5393 /* Similarly, taking advantage of the fact that
5394 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5396 if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR)
5397 return apply_distributive_law
5398 (gen_binary (XOR, mode,
5399 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)),
5400 gen_binary (IOR, mode, copy_rtx (XEXP (op0, 0)),
5403 else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR)
5404 return apply_distributive_law
5405 (gen_binary (XOR, mode,
5406 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)),
5407 gen_binary (IOR, mode, copy_rtx (XEXP (op1, 0)), XEXP (op0, 1))));
5411 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5412 if (GET_CODE (op1) == CONST_INT
5413 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5414 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
5417 /* Convert (A & B) | A to A. */
5418 if (GET_CODE (op0) == AND
5419 && (rtx_equal_p (XEXP (op0, 0), op1)
5420 || rtx_equal_p (XEXP (op0, 1), op1))
5421 && ! side_effects_p (XEXP (op0, 0))
5422 && ! side_effects_p (XEXP (op0, 1)))
5425 /* If we have (ior (and A B) C), apply the distributive law and then
5426 the inverse distributive law to see if things simplify. */
5428 if (GET_CODE (op0) == AND)
5430 x = apply_distributive_law
5431 (gen_binary (AND, mode,
5432 gen_binary (IOR, mode, XEXP (op0, 0), op1),
5433 gen_binary (IOR, mode, XEXP (op0, 1),
5436 if (GET_CODE (x) != IOR)
5440 if (GET_CODE (op1) == AND)
5442 x = apply_distributive_law
5443 (gen_binary (AND, mode,
5444 gen_binary (IOR, mode, XEXP (op1, 0), op0),
5445 gen_binary (IOR, mode, XEXP (op1, 1),
5448 if (GET_CODE (x) != IOR)
5452 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5453 mode size to (rotate A CX). */
5455 if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
5456 || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
5457 && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
5458 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5459 && GET_CODE (XEXP (op1, 1)) == CONST_INT
5460 && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
5461 == GET_MODE_BITSIZE (mode)))
5462 return gen_rtx_ROTATE (mode, XEXP (op0, 0),
5463 (GET_CODE (op0) == ASHIFT
5464 ? XEXP (op0, 1) : XEXP (op1, 1)));
5466 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5467 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5468 does not affect any of the bits in OP1, it can really be done
5469 as a PLUS and we can associate. We do this by seeing if OP1
5470 can be safely shifted left C bits. */
5471 if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
5472 && GET_CODE (XEXP (op0, 0)) == PLUS
5473 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
5474 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5475 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
5477 int count = INTVAL (XEXP (op0, 1));
5478 HOST_WIDE_INT mask = INTVAL (op1) << count;
5480 if (mask >> count == INTVAL (op1)
5481 && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
5483 SUBST (XEXP (XEXP (op0, 0), 1),
5484 GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
5491 /* If we are XORing two things that have no bits in common,
5492 convert them into an IOR. This helps to detect rotation encoded
5493 using those methods and possibly other simplifications. */
5495 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5496 && (nonzero_bits (op0, mode)
5497 & nonzero_bits (op1, mode)) == 0)
5498 return (gen_binary (IOR, mode, op0, op1));
5500 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5501 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5504 int num_negated = 0;
5506 if (GET_CODE (op0) == NOT)
5507 num_negated++, op0 = XEXP (op0, 0);
5508 if (GET_CODE (op1) == NOT)
5509 num_negated++, op1 = XEXP (op1, 0);
5511 if (num_negated == 2)
5513 SUBST (XEXP (x, 0), op0);
5514 SUBST (XEXP (x, 1), op1);
5516 else if (num_negated == 1)
5518 simplify_gen_unary (NOT, mode, gen_binary (XOR, mode, op0, op1),
5522 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5523 correspond to a machine insn or result in further simplifications
5524 if B is a constant. */
5526 if (GET_CODE (op0) == AND
5527 && rtx_equal_p (XEXP (op0, 1), op1)
5528 && ! side_effects_p (op1))
5529 return gen_binary (AND, mode,
5530 simplify_gen_unary (NOT, mode, XEXP (op0, 0), mode),
5533 else if (GET_CODE (op0) == AND
5534 && rtx_equal_p (XEXP (op0, 0), op1)
5535 && ! side_effects_p (op1))
5536 return gen_binary (AND, mode,
5537 simplify_gen_unary (NOT, mode, XEXP (op0, 1), mode),
5540 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5541 comparison if STORE_FLAG_VALUE is 1. */
5542 if (STORE_FLAG_VALUE == 1
5543 && op1 == const1_rtx
5544 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5545 && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0),
5549 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5550 is (lt foo (const_int 0)), so we can perform the above
5551 simplification if STORE_FLAG_VALUE is 1. */
5553 if (STORE_FLAG_VALUE == 1
5554 && op1 == const1_rtx
5555 && GET_CODE (op0) == LSHIFTRT
5556 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5557 && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
5558 return gen_rtx_GE (mode, XEXP (op0, 0), const0_rtx);
5560 /* (xor (comparison foo bar) (const_int sign-bit))
5561 when STORE_FLAG_VALUE is the sign bit. */
5562 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5563 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5564 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5565 && op1 == const_true_rtx
5566 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5567 && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0),
5580 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5581 operations" because they can be replaced with two more basic operations.
5582 ZERO_EXTEND is also considered "compound" because it can be replaced with
5583 an AND operation, which is simpler, though only one operation.
5585 The function expand_compound_operation is called with an rtx expression
5586 and will convert it to the appropriate shifts and AND operations,
5587 simplifying at each stage.
5589 The function make_compound_operation is called to convert an expression
5590 consisting of shifts and ANDs into the equivalent compound expression.
5591 It is the inverse of this function, loosely speaking. */
5594 expand_compound_operation (rtx x)
5596 unsigned HOST_WIDE_INT pos = 0, len;
5598 unsigned int modewidth;
5601 switch (GET_CODE (x))
5606 /* We can't necessarily use a const_int for a multiword mode;
5607 it depends on implicitly extending the value.
5608 Since we don't know the right way to extend it,
5609 we can't tell whether the implicit way is right.
5611 Even for a mode that is no wider than a const_int,
5612 we can't win, because we need to sign extend one of its bits through
5613 the rest of it, and we don't know which bit. */
5614 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5617 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5618 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5619 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5620 reloaded. If not for that, MEM's would very rarely be safe.
5622 Reject MODEs bigger than a word, because we might not be able
5623 to reference a two-register group starting with an arbitrary register
5624 (and currently gen_lowpart might crash for a SUBREG). */
5626 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5629 /* Reject MODEs that aren't scalar integers because turning vector
5630 or complex modes into shifts causes problems. */
5632 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5635 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5636 /* If the inner object has VOIDmode (the only way this can happen
5637 is if it is an ASM_OPERANDS), we can't do anything since we don't
5638 know how much masking to do. */
5647 /* If the operand is a CLOBBER, just return it. */
5648 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5651 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5652 || GET_CODE (XEXP (x, 2)) != CONST_INT
5653 || GET_MODE (XEXP (x, 0)) == VOIDmode)
5656 /* Reject MODEs that aren't scalar integers because turning vector
5657 or complex modes into shifts causes problems. */
5659 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5662 len = INTVAL (XEXP (x, 1));
5663 pos = INTVAL (XEXP (x, 2));
5665 /* If this goes outside the object being extracted, replace the object
5666 with a (use (mem ...)) construct that only combine understands
5667 and is used only for this purpose. */
5668 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5669 SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0)));
5671 if (BITS_BIG_ENDIAN)
5672 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5679 /* Convert sign extension to zero extension, if we know that the high
5680 bit is not set, as this is easier to optimize. It will be converted
5681 back to cheaper alternative in make_extraction. */
5682 if (GET_CODE (x) == SIGN_EXTEND
5683 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5684 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
5685 & ~(((unsigned HOST_WIDE_INT)
5686 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5690 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
5691 rtx temp2 = expand_compound_operation (temp);
5693 /* Make sure this is a profitable operation. */
5694 if (rtx_cost (x, SET) > rtx_cost (temp2, SET))
5696 else if (rtx_cost (x, SET) > rtx_cost (temp, SET))
5702 /* We can optimize some special cases of ZERO_EXTEND. */
5703 if (GET_CODE (x) == ZERO_EXTEND)
5705 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5706 know that the last value didn't have any inappropriate bits
5708 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5709 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5710 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5711 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5712 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5713 return XEXP (XEXP (x, 0), 0);
5715 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5716 if (GET_CODE (XEXP (x, 0)) == SUBREG
5717 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5718 && subreg_lowpart_p (XEXP (x, 0))
5719 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5720 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5721 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5722 return SUBREG_REG (XEXP (x, 0));
5724 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5725 is a comparison and STORE_FLAG_VALUE permits. This is like
5726 the first case, but it works even when GET_MODE (x) is larger
5727 than HOST_WIDE_INT. */
5728 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5729 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5730 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) == '<'
5731 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5732 <= HOST_BITS_PER_WIDE_INT)
5733 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5734 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5735 return XEXP (XEXP (x, 0), 0);
5737 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5738 if (GET_CODE (XEXP (x, 0)) == SUBREG
5739 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5740 && subreg_lowpart_p (XEXP (x, 0))
5741 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == '<'
5742 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5743 <= HOST_BITS_PER_WIDE_INT)
5744 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5745 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5746 return SUBREG_REG (XEXP (x, 0));
5750 /* If we reach here, we want to return a pair of shifts. The inner
5751 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5752 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5753 logical depending on the value of UNSIGNEDP.
5755 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5756 converted into an AND of a shift.
5758 We must check for the case where the left shift would have a negative
5759 count. This can happen in a case like (x >> 31) & 255 on machines
5760 that can't shift by a constant. On those machines, we would first
5761 combine the shift with the AND to produce a variable-position
5762 extraction. Then the constant of 31 would be substituted in to produce
5763 a such a position. */
5765 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5766 if (modewidth + len >= pos)
5767 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5769 simplify_shift_const (NULL_RTX, ASHIFT,
5772 modewidth - pos - len),
5775 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5776 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5777 simplify_shift_const (NULL_RTX, LSHIFTRT,
5780 ((HOST_WIDE_INT) 1 << len) - 1);
5782 /* Any other cases we can't handle. */
5785 /* If we couldn't do this for some reason, return the original
5787 if (GET_CODE (tem) == CLOBBER)
5793 /* X is a SET which contains an assignment of one object into
5794 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5795 or certain SUBREGS). If possible, convert it into a series of
5798 We half-heartedly support variable positions, but do not at all
5799 support variable lengths. */
5802 expand_field_assignment (rtx x)
5805 rtx pos; /* Always counts from low bit. */
5808 enum machine_mode compute_mode;
5810 /* Loop until we find something we can't simplify. */
5813 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5814 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5816 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5817 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5818 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
5820 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5821 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5823 inner = XEXP (SET_DEST (x), 0);
5824 len = INTVAL (XEXP (SET_DEST (x), 1));
5825 pos = XEXP (SET_DEST (x), 2);
5827 /* If the position is constant and spans the width of INNER,
5828 surround INNER with a USE to indicate this. */
5829 if (GET_CODE (pos) == CONST_INT
5830 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5831 inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner);
5833 if (BITS_BIG_ENDIAN)
5835 if (GET_CODE (pos) == CONST_INT)
5836 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5838 else if (GET_CODE (pos) == MINUS
5839 && GET_CODE (XEXP (pos, 1)) == CONST_INT
5840 && (INTVAL (XEXP (pos, 1))
5841 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5842 /* If position is ADJUST - X, new position is X. */
5843 pos = XEXP (pos, 0);
5845 pos = gen_binary (MINUS, GET_MODE (pos),
5846 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
5852 /* A SUBREG between two modes that occupy the same numbers of words
5853 can be done by moving the SUBREG to the source. */
5854 else if (GET_CODE (SET_DEST (x)) == SUBREG
5855 /* We need SUBREGs to compute nonzero_bits properly. */
5856 && nonzero_sign_valid
5857 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5858 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5859 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5860 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5862 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
5864 (GET_MODE (SUBREG_REG (SET_DEST (x))),
5871 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5872 inner = SUBREG_REG (inner);
5874 compute_mode = GET_MODE (inner);
5876 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
5877 if (! SCALAR_INT_MODE_P (compute_mode))
5879 enum machine_mode imode;
5881 /* Don't do anything for vector or complex integral types. */
5882 if (! FLOAT_MODE_P (compute_mode))
5885 /* Try to find an integral mode to pun with. */
5886 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
5887 if (imode == BLKmode)
5890 compute_mode = imode;
5891 inner = gen_lowpart (imode, inner);
5894 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5895 if (len < HOST_BITS_PER_WIDE_INT)
5896 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
5900 /* Now compute the equivalent expression. Make a copy of INNER
5901 for the SET_DEST in case it is a MEM into which we will substitute;
5902 we don't want shared RTL in that case. */
5904 (VOIDmode, copy_rtx (inner),
5905 gen_binary (IOR, compute_mode,
5906 gen_binary (AND, compute_mode,
5907 simplify_gen_unary (NOT, compute_mode,
5913 gen_binary (ASHIFT, compute_mode,
5914 gen_binary (AND, compute_mode,
5916 (compute_mode, SET_SRC (x)),
5924 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5925 it is an RTX that represents a variable starting position; otherwise,
5926 POS is the (constant) starting bit position (counted from the LSB).
5928 INNER may be a USE. This will occur when we started with a bitfield
5929 that went outside the boundary of the object in memory, which is
5930 allowed on most machines. To isolate this case, we produce a USE
5931 whose mode is wide enough and surround the MEM with it. The only
5932 code that understands the USE is this routine. If it is not removed,
5933 it will cause the resulting insn not to match.
5935 UNSIGNEDP is nonzero for an unsigned reference and zero for a
5938 IN_DEST is nonzero if this is a reference in the destination of a
5939 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
5940 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5943 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
5944 ZERO_EXTRACT should be built even for bits starting at bit 0.
5946 MODE is the desired mode of the result (if IN_DEST == 0).
5948 The result is an RTX for the extraction or NULL_RTX if the target
5952 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
5953 rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
5954 int in_dest, int in_compare)
5956 /* This mode describes the size of the storage area
5957 to fetch the overall value from. Within that, we
5958 ignore the POS lowest bits, etc. */
5959 enum machine_mode is_mode = GET_MODE (inner);
5960 enum machine_mode inner_mode;
5961 enum machine_mode wanted_inner_mode = byte_mode;
5962 enum machine_mode wanted_inner_reg_mode = word_mode;
5963 enum machine_mode pos_mode = word_mode;
5964 enum machine_mode extraction_mode = word_mode;
5965 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
5968 rtx orig_pos_rtx = pos_rtx;
5969 HOST_WIDE_INT orig_pos;
5971 /* Get some information about INNER and get the innermost object. */
5972 if (GET_CODE (inner) == USE)
5973 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
5974 /* We don't need to adjust the position because we set up the USE
5975 to pretend that it was a full-word object. */
5976 spans_byte = 1, inner = XEXP (inner, 0);
5977 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5979 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5980 consider just the QI as the memory to extract from.
5981 The subreg adds or removes high bits; its mode is
5982 irrelevant to the meaning of this extraction,
5983 since POS and LEN count from the lsb. */
5984 if (GET_CODE (SUBREG_REG (inner)) == MEM)
5985 is_mode = GET_MODE (SUBREG_REG (inner));
5986 inner = SUBREG_REG (inner);
5988 else if (GET_CODE (inner) == ASHIFT
5989 && GET_CODE (XEXP (inner, 1)) == CONST_INT
5990 && pos_rtx == 0 && pos == 0
5991 && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1)))
5993 /* We're extracting the least significant bits of an rtx
5994 (ashift X (const_int C)), where LEN > C. Extract the
5995 least significant (LEN - C) bits of X, giving an rtx
5996 whose mode is MODE, then shift it left C times. */
5997 new = make_extraction (mode, XEXP (inner, 0),
5998 0, 0, len - INTVAL (XEXP (inner, 1)),
5999 unsignedp, in_dest, in_compare);
6001 return gen_rtx_ASHIFT (mode, new, XEXP (inner, 1));
6004 inner_mode = GET_MODE (inner);
6006 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
6007 pos = INTVAL (pos_rtx), pos_rtx = 0;
6009 /* See if this can be done without an extraction. We never can if the
6010 width of the field is not the same as that of some integer mode. For
6011 registers, we can only avoid the extraction if the position is at the
6012 low-order bit and this is either not in the destination or we have the
6013 appropriate STRICT_LOW_PART operation available.
6015 For MEM, we can avoid an extract if the field starts on an appropriate
6016 boundary and we can change the mode of the memory reference. However,
6017 we cannot directly access the MEM if we have a USE and the underlying
6018 MEM is not TMODE. This combination means that MEM was being used in a
6019 context where bits outside its mode were being referenced; that is only
6020 valid in bit-field insns. */
6022 if (tmode != BLKmode
6023 && ! (spans_byte && inner_mode != tmode)
6024 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
6025 && GET_CODE (inner) != MEM
6027 || (GET_CODE (inner) == REG
6028 && have_insn_for (STRICT_LOW_PART, tmode))))
6029 || (GET_CODE (inner) == MEM && pos_rtx == 0
6031 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
6032 : BITS_PER_UNIT)) == 0
6033 /* We can't do this if we are widening INNER_MODE (it
6034 may not be aligned, for one thing). */
6035 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
6036 && (inner_mode == tmode
6037 || (! mode_dependent_address_p (XEXP (inner, 0))
6038 && ! MEM_VOLATILE_P (inner))))))
6040 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6041 field. If the original and current mode are the same, we need not
6042 adjust the offset. Otherwise, we do if bytes big endian.
6044 If INNER is not a MEM, get a piece consisting of just the field
6045 of interest (in this case POS % BITS_PER_WORD must be 0). */
6047 if (GET_CODE (inner) == MEM)
6049 HOST_WIDE_INT offset;
6051 /* POS counts from lsb, but make OFFSET count in memory order. */
6052 if (BYTES_BIG_ENDIAN)
6053 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
6055 offset = pos / BITS_PER_UNIT;
6057 new = adjust_address_nv (inner, tmode, offset);
6059 else if (GET_CODE (inner) == REG)
6061 if (tmode != inner_mode)
6063 /* We can't call gen_lowpart in a DEST since we
6064 always want a SUBREG (see below) and it would sometimes
6065 return a new hard register. */
6068 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
6070 if (WORDS_BIG_ENDIAN
6071 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
6072 final_word = ((GET_MODE_SIZE (inner_mode)
6073 - GET_MODE_SIZE (tmode))
6074 / UNITS_PER_WORD) - final_word;
6076 final_word *= UNITS_PER_WORD;
6077 if (BYTES_BIG_ENDIAN &&
6078 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
6079 final_word += (GET_MODE_SIZE (inner_mode)
6080 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
6082 /* Avoid creating invalid subregs, for example when
6083 simplifying (x>>32)&255. */
6084 if (final_word >= GET_MODE_SIZE (inner_mode))
6087 new = gen_rtx_SUBREG (tmode, inner, final_word);
6090 new = gen_lowpart (tmode, inner);
6096 new = force_to_mode (inner, tmode,
6097 len >= HOST_BITS_PER_WIDE_INT
6098 ? ~(unsigned HOST_WIDE_INT) 0
6099 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6102 /* If this extraction is going into the destination of a SET,
6103 make a STRICT_LOW_PART unless we made a MEM. */
6106 return (GET_CODE (new) == MEM ? new
6107 : (GET_CODE (new) != SUBREG
6108 ? gen_rtx_CLOBBER (tmode, const0_rtx)
6109 : gen_rtx_STRICT_LOW_PART (VOIDmode, new)));
6114 if (GET_CODE (new) == CONST_INT)
6115 return gen_int_mode (INTVAL (new), mode);
6117 /* If we know that no extraneous bits are set, and that the high
6118 bit is not set, convert the extraction to the cheaper of
6119 sign and zero extension, that are equivalent in these cases. */
6120 if (flag_expensive_optimizations
6121 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6122 && ((nonzero_bits (new, tmode)
6123 & ~(((unsigned HOST_WIDE_INT)
6124 GET_MODE_MASK (tmode))
6128 rtx temp = gen_rtx_ZERO_EXTEND (mode, new);
6129 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new);
6131 /* Prefer ZERO_EXTENSION, since it gives more information to
6133 if (rtx_cost (temp, SET) <= rtx_cost (temp1, SET))
6138 /* Otherwise, sign- or zero-extend unless we already are in the
6141 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6145 /* Unless this is a COMPARE or we have a funny memory reference,
6146 don't do anything with zero-extending field extracts starting at
6147 the low-order bit since they are simple AND operations. */
6148 if (pos_rtx == 0 && pos == 0 && ! in_dest
6149 && ! in_compare && ! spans_byte && unsignedp)
6152 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6153 we would be spanning bytes or if the position is not a constant and the
6154 length is not 1. In all other cases, we would only be going outside
6155 our object in cases when an original shift would have been
6157 if (! spans_byte && GET_CODE (inner) == MEM
6158 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6159 || (pos_rtx != 0 && len != 1)))
6162 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6163 and the mode for the result. */
6164 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6166 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6167 pos_mode = mode_for_extraction (EP_insv, 2);
6168 extraction_mode = mode_for_extraction (EP_insv, 3);
6171 if (! in_dest && unsignedp
6172 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6174 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6175 pos_mode = mode_for_extraction (EP_extzv, 3);
6176 extraction_mode = mode_for_extraction (EP_extzv, 0);
6179 if (! in_dest && ! unsignedp
6180 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6182 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6183 pos_mode = mode_for_extraction (EP_extv, 3);
6184 extraction_mode = mode_for_extraction (EP_extv, 0);
6187 /* Never narrow an object, since that might not be safe. */
6189 if (mode != VOIDmode
6190 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6191 extraction_mode = mode;
6193 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6194 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6195 pos_mode = GET_MODE (pos_rtx);
6197 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6198 if we have to change the mode of memory and cannot, the desired mode is
6200 if (GET_CODE (inner) != MEM)
6201 wanted_inner_mode = wanted_inner_reg_mode;
6202 else if (inner_mode != wanted_inner_mode
6203 && (mode_dependent_address_p (XEXP (inner, 0))
6204 || MEM_VOLATILE_P (inner)))
6205 wanted_inner_mode = extraction_mode;
6209 if (BITS_BIG_ENDIAN)
6211 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6212 BITS_BIG_ENDIAN style. If position is constant, compute new
6213 position. Otherwise, build subtraction.
6214 Note that POS is relative to the mode of the original argument.
6215 If it's a MEM we need to recompute POS relative to that.
6216 However, if we're extracting from (or inserting into) a register,
6217 we want to recompute POS relative to wanted_inner_mode. */
6218 int width = (GET_CODE (inner) == MEM
6219 ? GET_MODE_BITSIZE (is_mode)
6220 : GET_MODE_BITSIZE (wanted_inner_mode));
6223 pos = width - len - pos;
6226 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6227 /* POS may be less than 0 now, but we check for that below.
6228 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
6231 /* If INNER has a wider mode, make it smaller. If this is a constant
6232 extract, try to adjust the byte to point to the byte containing
6234 if (wanted_inner_mode != VOIDmode
6235 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6236 && ((GET_CODE (inner) == MEM
6237 && (inner_mode == wanted_inner_mode
6238 || (! mode_dependent_address_p (XEXP (inner, 0))
6239 && ! MEM_VOLATILE_P (inner))))))
6243 /* The computations below will be correct if the machine is big
6244 endian in both bits and bytes or little endian in bits and bytes.
6245 If it is mixed, we must adjust. */
6247 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6248 adjust OFFSET to compensate. */
6249 if (BYTES_BIG_ENDIAN
6251 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6252 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6254 /* If this is a constant position, we can move to the desired byte. */
6257 offset += pos / BITS_PER_UNIT;
6258 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6261 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6263 && is_mode != wanted_inner_mode)
6264 offset = (GET_MODE_SIZE (is_mode)
6265 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6267 if (offset != 0 || inner_mode != wanted_inner_mode)
6268 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6271 /* If INNER is not memory, we can always get it into the proper mode. If we
6272 are changing its mode, POS must be a constant and smaller than the size
6274 else if (GET_CODE (inner) != MEM)
6276 if (GET_MODE (inner) != wanted_inner_mode
6278 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6281 inner = force_to_mode (inner, wanted_inner_mode,
6283 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6284 ? ~(unsigned HOST_WIDE_INT) 0
6285 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6290 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6291 have to zero extend. Otherwise, we can just use a SUBREG. */
6293 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6295 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6297 /* If we know that no extraneous bits are set, and that the high
6298 bit is not set, convert extraction to cheaper one - either
6299 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6301 if (flag_expensive_optimizations
6302 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6303 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6304 & ~(((unsigned HOST_WIDE_INT)
6305 GET_MODE_MASK (GET_MODE (pos_rtx)))
6309 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6311 /* Prefer ZERO_EXTENSION, since it gives more information to
6313 if (rtx_cost (temp1, SET) < rtx_cost (temp, SET))
6318 else if (pos_rtx != 0
6319 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6320 pos_rtx = gen_lowpart (pos_mode, pos_rtx);
6322 /* Make POS_RTX unless we already have it and it is correct. If we don't
6323 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6325 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6326 pos_rtx = orig_pos_rtx;
6328 else if (pos_rtx == 0)
6329 pos_rtx = GEN_INT (pos);
6331 /* Make the required operation. See if we can use existing rtx. */
6332 new = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6333 extraction_mode, inner, GEN_INT (len), pos_rtx);
6335 new = gen_lowpart (mode, new);
6340 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6341 with any other operations in X. Return X without that shift if so. */
6344 extract_left_shift (rtx x, int count)
6346 enum rtx_code code = GET_CODE (x);
6347 enum machine_mode mode = GET_MODE (x);
6353 /* This is the shift itself. If it is wide enough, we will return
6354 either the value being shifted if the shift count is equal to
6355 COUNT or a shift for the difference. */
6356 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6357 && INTVAL (XEXP (x, 1)) >= count)
6358 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6359 INTVAL (XEXP (x, 1)) - count);
6363 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6364 return simplify_gen_unary (code, mode, tem, mode);
6368 case PLUS: case IOR: case XOR: case AND:
6369 /* If we can safely shift this constant and we find the inner shift,
6370 make a new operation. */
6371 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6372 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6373 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6374 return gen_binary (code, mode, tem,
6375 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6386 /* Look at the expression rooted at X. Look for expressions
6387 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6388 Form these expressions.
6390 Return the new rtx, usually just X.
6392 Also, for machines like the VAX that don't have logical shift insns,
6393 try to convert logical to arithmetic shift operations in cases where
6394 they are equivalent. This undoes the canonicalizations to logical
6395 shifts done elsewhere.
6397 We try, as much as possible, to re-use rtl expressions to save memory.
6399 IN_CODE says what kind of expression we are processing. Normally, it is
6400 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6401 being kludges), it is MEM. When processing the arguments of a comparison
6402 or a COMPARE against zero, it is COMPARE. */
6405 make_compound_operation (rtx x, enum rtx_code in_code)
6407 enum rtx_code code = GET_CODE (x);
6408 enum machine_mode mode = GET_MODE (x);
6409 int mode_width = GET_MODE_BITSIZE (mode);
6411 enum rtx_code next_code;
6417 /* Select the code to be used in recursive calls. Once we are inside an
6418 address, we stay there. If we have a comparison, set to COMPARE,
6419 but once inside, go back to our default of SET. */
6421 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6422 : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
6423 && XEXP (x, 1) == const0_rtx) ? COMPARE
6424 : in_code == COMPARE ? SET : in_code);
6426 /* Process depending on the code of this operation. If NEW is set
6427 nonzero, it will be returned. */
6432 /* Convert shifts by constants into multiplications if inside
6434 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6435 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6436 && INTVAL (XEXP (x, 1)) >= 0)
6438 new = make_compound_operation (XEXP (x, 0), next_code);
6439 new = gen_rtx_MULT (mode, new,
6440 GEN_INT ((HOST_WIDE_INT) 1
6441 << INTVAL (XEXP (x, 1))));
6446 /* If the second operand is not a constant, we can't do anything
6448 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6451 /* If the constant is a power of two minus one and the first operand
6452 is a logical right shift, make an extraction. */
6453 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6454 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6456 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6457 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6458 0, in_code == COMPARE);
6461 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6462 else if (GET_CODE (XEXP (x, 0)) == SUBREG
6463 && subreg_lowpart_p (XEXP (x, 0))
6464 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6465 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6467 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6469 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6470 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6471 0, in_code == COMPARE);
6473 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6474 else if ((GET_CODE (XEXP (x, 0)) == XOR
6475 || GET_CODE (XEXP (x, 0)) == IOR)
6476 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6477 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6478 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6480 /* Apply the distributive law, and then try to make extractions. */
6481 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
6482 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6484 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6486 new = make_compound_operation (new, in_code);
6489 /* If we are have (and (rotate X C) M) and C is larger than the number
6490 of bits in M, this is an extraction. */
6492 else if (GET_CODE (XEXP (x, 0)) == ROTATE
6493 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6494 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6495 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6497 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6498 new = make_extraction (mode, new,
6499 (GET_MODE_BITSIZE (mode)
6500 - INTVAL (XEXP (XEXP (x, 0), 1))),
6501 NULL_RTX, i, 1, 0, in_code == COMPARE);
6504 /* On machines without logical shifts, if the operand of the AND is
6505 a logical shift and our mask turns off all the propagated sign
6506 bits, we can replace the logical shift with an arithmetic shift. */
6507 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6508 && !have_insn_for (LSHIFTRT, mode)
6509 && have_insn_for (ASHIFTRT, mode)
6510 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6511 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6512 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6513 && mode_width <= HOST_BITS_PER_WIDE_INT)
6515 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6517 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6518 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6520 gen_rtx_ASHIFTRT (mode,
6521 make_compound_operation
6522 (XEXP (XEXP (x, 0), 0), next_code),
6523 XEXP (XEXP (x, 0), 1)));
6526 /* If the constant is one less than a power of two, this might be
6527 representable by an extraction even if no shift is present.
6528 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6529 we are in a COMPARE. */
6530 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6531 new = make_extraction (mode,
6532 make_compound_operation (XEXP (x, 0),
6534 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6536 /* If we are in a comparison and this is an AND with a power of two,
6537 convert this into the appropriate bit extract. */
6538 else if (in_code == COMPARE
6539 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6540 new = make_extraction (mode,
6541 make_compound_operation (XEXP (x, 0),
6543 i, NULL_RTX, 1, 1, 0, 1);
6548 /* If the sign bit is known to be zero, replace this with an
6549 arithmetic shift. */
6550 if (have_insn_for (ASHIFTRT, mode)
6551 && ! have_insn_for (LSHIFTRT, mode)
6552 && mode_width <= HOST_BITS_PER_WIDE_INT
6553 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6555 new = gen_rtx_ASHIFTRT (mode,
6556 make_compound_operation (XEXP (x, 0),
6562 /* ... fall through ... */
6568 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6569 this is a SIGN_EXTRACT. */
6570 if (GET_CODE (rhs) == CONST_INT
6571 && GET_CODE (lhs) == ASHIFT
6572 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6573 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6575 new = make_compound_operation (XEXP (lhs, 0), next_code);
6576 new = make_extraction (mode, new,
6577 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6578 NULL_RTX, mode_width - INTVAL (rhs),
6579 code == LSHIFTRT, 0, in_code == COMPARE);
6583 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6584 If so, try to merge the shifts into a SIGN_EXTEND. We could
6585 also do this for some cases of SIGN_EXTRACT, but it doesn't
6586 seem worth the effort; the case checked for occurs on Alpha. */
6588 if (GET_RTX_CLASS (GET_CODE (lhs)) != 'o'
6589 && ! (GET_CODE (lhs) == SUBREG
6590 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs))) == 'o'))
6591 && GET_CODE (rhs) == CONST_INT
6592 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6593 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6594 new = make_extraction (mode, make_compound_operation (new, next_code),
6595 0, NULL_RTX, mode_width - INTVAL (rhs),
6596 code == LSHIFTRT, 0, in_code == COMPARE);
6601 /* Call ourselves recursively on the inner expression. If we are
6602 narrowing the object and it has a different RTL code from
6603 what it originally did, do this SUBREG as a force_to_mode. */
6605 tem = make_compound_operation (SUBREG_REG (x), in_code);
6606 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6607 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6608 && subreg_lowpart_p (x))
6610 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
6613 /* If we have something other than a SUBREG, we might have
6614 done an expansion, so rerun ourselves. */
6615 if (GET_CODE (newer) != SUBREG)
6616 newer = make_compound_operation (newer, in_code);
6621 /* If this is a paradoxical subreg, and the new code is a sign or
6622 zero extension, omit the subreg and widen the extension. If it
6623 is a regular subreg, we can still get rid of the subreg by not
6624 widening so much, or in fact removing the extension entirely. */
6625 if ((GET_CODE (tem) == SIGN_EXTEND
6626 || GET_CODE (tem) == ZERO_EXTEND)
6627 && subreg_lowpart_p (x))
6629 if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (tem))
6630 || (GET_MODE_SIZE (mode) >
6631 GET_MODE_SIZE (GET_MODE (XEXP (tem, 0)))))
6633 if (! SCALAR_INT_MODE_P (mode))
6635 tem = gen_rtx_fmt_e (GET_CODE (tem), mode, XEXP (tem, 0));
6638 tem = gen_lowpart (mode, XEXP (tem, 0));
6649 x = gen_lowpart (mode, new);
6650 code = GET_CODE (x);
6653 /* Now recursively process each operand of this operation. */
6654 fmt = GET_RTX_FORMAT (code);
6655 for (i = 0; i < GET_RTX_LENGTH (code); i++)
6658 new = make_compound_operation (XEXP (x, i), next_code);
6659 SUBST (XEXP (x, i), new);
6665 /* Given M see if it is a value that would select a field of bits
6666 within an item, but not the entire word. Return -1 if not.
6667 Otherwise, return the starting position of the field, where 0 is the
6670 *PLEN is set to the length of the field. */
6673 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
6675 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6676 int pos = exact_log2 (m & -m);
6682 /* Now shift off the low-order zero bits and see if we have a power of
6684 len = exact_log2 ((m >> pos) + 1);
6693 /* See if X can be simplified knowing that we will only refer to it in
6694 MODE and will only refer to those bits that are nonzero in MASK.
6695 If other bits are being computed or if masking operations are done
6696 that select a superset of the bits in MASK, they can sometimes be
6699 Return a possibly simplified expression, but always convert X to
6700 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6702 Also, if REG is nonzero and X is a register equal in value to REG,
6705 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6706 are all off in X. This is used when X will be complemented, by either
6707 NOT, NEG, or XOR. */
6710 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
6711 rtx reg, int just_select)
6713 enum rtx_code code = GET_CODE (x);
6714 int next_select = just_select || code == XOR || code == NOT || code == NEG;
6715 enum machine_mode op_mode;
6716 unsigned HOST_WIDE_INT fuller_mask, nonzero;
6719 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6720 code below will do the wrong thing since the mode of such an
6721 expression is VOIDmode.
6723 Also do nothing if X is a CLOBBER; this can happen if X was
6724 the return value from a call to gen_lowpart. */
6725 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
6728 /* We want to perform the operation is its present mode unless we know
6729 that the operation is valid in MODE, in which case we do the operation
6731 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6732 && have_insn_for (code, mode))
6733 ? mode : GET_MODE (x));
6735 /* It is not valid to do a right-shift in a narrower mode
6736 than the one it came in with. */
6737 if ((code == LSHIFTRT || code == ASHIFTRT)
6738 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6739 op_mode = GET_MODE (x);
6741 /* Truncate MASK to fit OP_MODE. */
6743 mask &= GET_MODE_MASK (op_mode);
6745 /* When we have an arithmetic operation, or a shift whose count we
6746 do not know, we need to assume that all bits up to the highest-order
6747 bit in MASK will be needed. This is how we form such a mask. */
6748 if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
6749 fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
6751 fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
6754 /* Determine what bits of X are guaranteed to be (non)zero. */
6755 nonzero = nonzero_bits (x, mode);
6757 /* If none of the bits in X are needed, return a zero. */
6758 if (! just_select && (nonzero & mask) == 0)
6761 /* If X is a CONST_INT, return a new one. Do this here since the
6762 test below will fail. */
6763 if (GET_CODE (x) == CONST_INT)
6765 if (SCALAR_INT_MODE_P (mode))
6766 return gen_int_mode (INTVAL (x) & mask, mode);
6769 x = GEN_INT (INTVAL (x) & mask);
6770 return gen_lowpart_common (mode, x);
6774 /* If X is narrower than MODE and we want all the bits in X's mode, just
6775 get X in the proper mode. */
6776 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6777 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
6778 return gen_lowpart (mode, x);
6780 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6781 MASK are already known to be zero in X, we need not do anything. */
6782 if (GET_MODE (x) == mode && code != SUBREG && (~mask & nonzero) == 0)
6788 /* If X is a (clobber (const_int)), return it since we know we are
6789 generating something that won't match. */
6793 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6794 spanned the boundary of the MEM. If we are now masking so it is
6795 within that boundary, we don't need the USE any more. */
6796 if (! BITS_BIG_ENDIAN
6797 && (mask & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6798 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6805 x = expand_compound_operation (x);
6806 if (GET_CODE (x) != code)
6807 return force_to_mode (x, mode, mask, reg, next_select);
6811 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
6812 || rtx_equal_p (reg, get_last_value (x))))
6817 if (subreg_lowpart_p (x)
6818 /* We can ignore the effect of this SUBREG if it narrows the mode or
6819 if the constant masks to zero all the bits the mode doesn't
6821 && ((GET_MODE_SIZE (GET_MODE (x))
6822 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6824 & GET_MODE_MASK (GET_MODE (x))
6825 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6826 return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
6830 /* If this is an AND with a constant, convert it into an AND
6831 whose constant is the AND of that constant with MASK. If it
6832 remains an AND of MASK, delete it since it is redundant. */
6834 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6836 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6837 mask & INTVAL (XEXP (x, 1)));
6839 /* If X is still an AND, see if it is an AND with a mask that
6840 is just some low-order bits. If so, and it is MASK, we don't
6843 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6844 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
6848 /* If it remains an AND, try making another AND with the bits
6849 in the mode mask that aren't in MASK turned on. If the
6850 constant in the AND is wide enough, this might make a
6851 cheaper constant. */
6853 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6854 && GET_MODE_MASK (GET_MODE (x)) != mask
6855 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
6857 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6858 | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
6859 int width = GET_MODE_BITSIZE (GET_MODE (x));
6862 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6863 number, sign extend it. */
6864 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6865 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6866 cval |= (HOST_WIDE_INT) -1 << width;
6868 y = gen_binary (AND, GET_MODE (x), XEXP (x, 0), GEN_INT (cval));
6869 if (rtx_cost (y, SET) < rtx_cost (x, SET))
6879 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6880 low-order bits (as in an alignment operation) and FOO is already
6881 aligned to that boundary, mask C1 to that boundary as well.
6882 This may eliminate that PLUS and, later, the AND. */
6885 unsigned int width = GET_MODE_BITSIZE (mode);
6886 unsigned HOST_WIDE_INT smask = mask;
6888 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6889 number, sign extend it. */
6891 if (width < HOST_BITS_PER_WIDE_INT
6892 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6893 smask |= (HOST_WIDE_INT) -1 << width;
6895 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6896 && exact_log2 (- smask) >= 0
6897 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
6898 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
6899 return force_to_mode (plus_constant (XEXP (x, 0),
6900 (INTVAL (XEXP (x, 1)) & smask)),
6901 mode, smask, reg, next_select);
6904 /* ... fall through ... */
6907 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6908 most significant bit in MASK since carries from those bits will
6909 affect the bits we are interested in. */
6914 /* If X is (minus C Y) where C's least set bit is larger than any bit
6915 in the mask, then we may replace with (neg Y). */
6916 if (GET_CODE (XEXP (x, 0)) == CONST_INT
6917 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
6918 & -INTVAL (XEXP (x, 0))))
6921 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
6923 return force_to_mode (x, mode, mask, reg, next_select);
6926 /* Similarly, if C contains every bit in the fuller_mask, then we may
6927 replace with (not Y). */
6928 if (GET_CODE (XEXP (x, 0)) == CONST_INT
6929 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask)
6930 == INTVAL (XEXP (x, 0))))
6932 x = simplify_gen_unary (NOT, GET_MODE (x),
6933 XEXP (x, 1), GET_MODE (x));
6934 return force_to_mode (x, mode, mask, reg, next_select);
6942 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6943 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6944 operation which may be a bitfield extraction. Ensure that the
6945 constant we form is not wider than the mode of X. */
6947 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6948 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6949 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6950 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6951 && GET_CODE (XEXP (x, 1)) == CONST_INT
6952 && ((INTVAL (XEXP (XEXP (x, 0), 1))
6953 + floor_log2 (INTVAL (XEXP (x, 1))))
6954 < GET_MODE_BITSIZE (GET_MODE (x)))
6955 && (INTVAL (XEXP (x, 1))
6956 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
6958 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
6959 << INTVAL (XEXP (XEXP (x, 0), 1)));
6960 temp = gen_binary (GET_CODE (x), GET_MODE (x),
6961 XEXP (XEXP (x, 0), 0), temp);
6962 x = gen_binary (LSHIFTRT, GET_MODE (x), temp,
6963 XEXP (XEXP (x, 0), 1));
6964 return force_to_mode (x, mode, mask, reg, next_select);
6968 /* For most binary operations, just propagate into the operation and
6969 change the mode if we have an operation of that mode. */
6971 op0 = gen_lowpart (op_mode,
6972 force_to_mode (XEXP (x, 0), mode, mask,
6974 op1 = gen_lowpart (op_mode,
6975 force_to_mode (XEXP (x, 1), mode, mask,
6978 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6979 x = gen_binary (code, op_mode, op0, op1);
6983 /* For left shifts, do the same, but just for the first operand.
6984 However, we cannot do anything with shifts where we cannot
6985 guarantee that the counts are smaller than the size of the mode
6986 because such a count will have a different meaning in a
6989 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
6990 && INTVAL (XEXP (x, 1)) >= 0
6991 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
6992 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
6993 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
6994 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
6997 /* If the shift count is a constant and we can do arithmetic in
6998 the mode of the shift, refine which bits we need. Otherwise, use the
6999 conservative form of the mask. */
7000 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7001 && INTVAL (XEXP (x, 1)) >= 0
7002 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
7003 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7004 mask >>= INTVAL (XEXP (x, 1));
7008 op0 = gen_lowpart (op_mode,
7009 force_to_mode (XEXP (x, 0), op_mode,
7010 mask, reg, next_select));
7012 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7013 x = gen_binary (code, op_mode, op0, XEXP (x, 1));
7017 /* Here we can only do something if the shift count is a constant,
7018 this shift constant is valid for the host, and we can do arithmetic
7021 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7022 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7023 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7025 rtx inner = XEXP (x, 0);
7026 unsigned HOST_WIDE_INT inner_mask;
7028 /* Select the mask of the bits we need for the shift operand. */
7029 inner_mask = mask << INTVAL (XEXP (x, 1));
7031 /* We can only change the mode of the shift if we can do arithmetic
7032 in the mode of the shift and INNER_MASK is no wider than the
7033 width of OP_MODE. */
7034 if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT
7035 || (inner_mask & ~GET_MODE_MASK (op_mode)) != 0)
7036 op_mode = GET_MODE (x);
7038 inner = force_to_mode (inner, op_mode, inner_mask, reg, next_select);
7040 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
7041 x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
7044 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7045 shift and AND produces only copies of the sign bit (C2 is one less
7046 than a power of two), we can do this with just a shift. */
7048 if (GET_CODE (x) == LSHIFTRT
7049 && GET_CODE (XEXP (x, 1)) == CONST_INT
7050 /* The shift puts one of the sign bit copies in the least significant
7052 && ((INTVAL (XEXP (x, 1))
7053 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7054 >= GET_MODE_BITSIZE (GET_MODE (x)))
7055 && exact_log2 (mask + 1) >= 0
7056 /* Number of bits left after the shift must be more than the mask
7058 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7059 <= GET_MODE_BITSIZE (GET_MODE (x)))
7060 /* Must be more sign bit copies than the mask needs. */
7061 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7062 >= exact_log2 (mask + 1)))
7063 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7064 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7065 - exact_log2 (mask + 1)));
7070 /* If we are just looking for the sign bit, we don't need this shift at
7071 all, even if it has a variable count. */
7072 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7073 && (mask == ((unsigned HOST_WIDE_INT) 1
7074 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7075 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7077 /* If this is a shift by a constant, get a mask that contains those bits
7078 that are not copies of the sign bit. We then have two cases: If
7079 MASK only includes those bits, this can be a logical shift, which may
7080 allow simplifications. If MASK is a single-bit field not within
7081 those bits, we are requesting a copy of the sign bit and hence can
7082 shift the sign bit to the appropriate location. */
7084 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
7085 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7089 /* If the considered data is wider than HOST_WIDE_INT, we can't
7090 represent a mask for all its bits in a single scalar.
7091 But we only care about the lower bits, so calculate these. */
7093 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7095 nonzero = ~(HOST_WIDE_INT) 0;
7097 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7098 is the number of bits a full-width mask would have set.
7099 We need only shift if these are fewer than nonzero can
7100 hold. If not, we must keep all bits set in nonzero. */
7102 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7103 < HOST_BITS_PER_WIDE_INT)
7104 nonzero >>= INTVAL (XEXP (x, 1))
7105 + HOST_BITS_PER_WIDE_INT
7106 - GET_MODE_BITSIZE (GET_MODE (x)) ;
7110 nonzero = GET_MODE_MASK (GET_MODE (x));
7111 nonzero >>= INTVAL (XEXP (x, 1));
7114 if ((mask & ~nonzero) == 0
7115 || (i = exact_log2 (mask)) >= 0)
7117 x = simplify_shift_const
7118 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7119 i < 0 ? INTVAL (XEXP (x, 1))
7120 : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7122 if (GET_CODE (x) != ASHIFTRT)
7123 return force_to_mode (x, mode, mask, reg, next_select);
7127 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7128 even if the shift count isn't a constant. */
7130 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1));
7134 /* If this is a zero- or sign-extension operation that just affects bits
7135 we don't care about, remove it. Be sure the call above returned
7136 something that is still a shift. */
7138 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7139 && GET_CODE (XEXP (x, 1)) == CONST_INT
7140 && INTVAL (XEXP (x, 1)) >= 0
7141 && (INTVAL (XEXP (x, 1))
7142 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7143 && GET_CODE (XEXP (x, 0)) == ASHIFT
7144 && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
7145 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7152 /* If the shift count is constant and we can do computations
7153 in the mode of X, compute where the bits we care about are.
7154 Otherwise, we can't do anything. Don't change the mode of
7155 the shift or propagate MODE into the shift, though. */
7156 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7157 && INTVAL (XEXP (x, 1)) >= 0)
7159 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7160 GET_MODE (x), GEN_INT (mask),
7162 if (temp && GET_CODE (temp) == CONST_INT)
7164 force_to_mode (XEXP (x, 0), GET_MODE (x),
7165 INTVAL (temp), reg, next_select));
7170 /* If we just want the low-order bit, the NEG isn't needed since it
7171 won't change the low-order bit. */
7173 return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
7175 /* We need any bits less significant than the most significant bit in
7176 MASK since carries from those bits will affect the bits we are
7182 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7183 same as the XOR case above. Ensure that the constant we form is not
7184 wider than the mode of X. */
7186 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7187 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7188 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7189 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7190 < GET_MODE_BITSIZE (GET_MODE (x)))
7191 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7193 temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
7195 temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp);
7196 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1));
7198 return force_to_mode (x, mode, mask, reg, next_select);
7201 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7202 use the full mask inside the NOT. */
7206 op0 = gen_lowpart (op_mode,
7207 force_to_mode (XEXP (x, 0), mode, mask,
7209 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7210 x = simplify_gen_unary (code, op_mode, op0, op_mode);
7214 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7215 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7216 which is equal to STORE_FLAG_VALUE. */
7217 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7218 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7219 && (nonzero_bits (XEXP (x, 0), mode)
7220 == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
7221 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7226 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7227 written in a narrower mode. We play it safe and do not do so. */
7230 gen_lowpart (GET_MODE (x),
7231 force_to_mode (XEXP (x, 1), mode,
7232 mask, reg, next_select)));
7234 gen_lowpart (GET_MODE (x),
7235 force_to_mode (XEXP (x, 2), mode,
7236 mask, reg, next_select)));
7243 /* Ensure we return a value of the proper mode. */
7244 return gen_lowpart (mode, x);
7247 /* Return nonzero if X is an expression that has one of two values depending on
7248 whether some other value is zero or nonzero. In that case, we return the
7249 value that is being tested, *PTRUE is set to the value if the rtx being
7250 returned has a nonzero value, and *PFALSE is set to the other alternative.
7252 If we return zero, we set *PTRUE and *PFALSE to X. */
7255 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
7257 enum machine_mode mode = GET_MODE (x);
7258 enum rtx_code code = GET_CODE (x);
7259 rtx cond0, cond1, true0, true1, false0, false1;
7260 unsigned HOST_WIDE_INT nz;
7262 /* If we are comparing a value against zero, we are done. */
7263 if ((code == NE || code == EQ)
7264 && XEXP (x, 1) == const0_rtx)
7266 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7267 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7271 /* If this is a unary operation whose operand has one of two values, apply
7272 our opcode to compute those values. */
7273 else if (GET_RTX_CLASS (code) == '1'
7274 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7276 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
7277 *pfalse = simplify_gen_unary (code, mode, false0,
7278 GET_MODE (XEXP (x, 0)));
7282 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7283 make can't possibly match and would suppress other optimizations. */
7284 else if (code == COMPARE)
7287 /* If this is a binary operation, see if either side has only one of two
7288 values. If either one does or if both do and they are conditional on
7289 the same value, compute the new true and false values. */
7290 else if (GET_RTX_CLASS (code) == 'c' || GET_RTX_CLASS (code) == '2'
7291 || GET_RTX_CLASS (code) == '<')
7293 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7294 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7296 if ((cond0 != 0 || cond1 != 0)
7297 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7299 /* If if_then_else_cond returned zero, then true/false are the
7300 same rtl. We must copy one of them to prevent invalid rtl
7303 true0 = copy_rtx (true0);
7304 else if (cond1 == 0)
7305 true1 = copy_rtx (true1);
7307 *ptrue = gen_binary (code, mode, true0, true1);
7308 *pfalse = gen_binary (code, mode, false0, false1);
7309 return cond0 ? cond0 : cond1;
7312 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7313 operands is zero when the other is nonzero, and vice-versa,
7314 and STORE_FLAG_VALUE is 1 or -1. */
7316 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7317 && (code == PLUS || code == IOR || code == XOR || code == MINUS
7319 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7321 rtx op0 = XEXP (XEXP (x, 0), 1);
7322 rtx op1 = XEXP (XEXP (x, 1), 1);
7324 cond0 = XEXP (XEXP (x, 0), 0);
7325 cond1 = XEXP (XEXP (x, 1), 0);
7327 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7328 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7329 && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1)
7330 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7331 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7332 || ((swap_condition (GET_CODE (cond0))
7333 == combine_reversed_comparison_code (cond1))
7334 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7335 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7336 && ! side_effects_p (x))
7338 *ptrue = gen_binary (MULT, mode, op0, const_true_rtx);
7339 *pfalse = gen_binary (MULT, mode,
7341 ? simplify_gen_unary (NEG, mode, op1,
7349 /* Similarly for MULT, AND and UMIN, except that for these the result
7351 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7352 && (code == MULT || code == AND || code == UMIN)
7353 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7355 cond0 = XEXP (XEXP (x, 0), 0);
7356 cond1 = XEXP (XEXP (x, 1), 0);
7358 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7359 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7360 && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1)
7361 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7362 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7363 || ((swap_condition (GET_CODE (cond0))
7364 == combine_reversed_comparison_code (cond1))
7365 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7366 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7367 && ! side_effects_p (x))
7369 *ptrue = *pfalse = const0_rtx;
7375 else if (code == IF_THEN_ELSE)
7377 /* If we have IF_THEN_ELSE already, extract the condition and
7378 canonicalize it if it is NE or EQ. */
7379 cond0 = XEXP (x, 0);
7380 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7381 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7382 return XEXP (cond0, 0);
7383 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7385 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7386 return XEXP (cond0, 0);
7392 /* If X is a SUBREG, we can narrow both the true and false values
7393 if the inner expression, if there is a condition. */
7394 else if (code == SUBREG
7395 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7398 *ptrue = simplify_gen_subreg (mode, true0,
7399 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7400 *pfalse = simplify_gen_subreg (mode, false0,
7401 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7406 /* If X is a constant, this isn't special and will cause confusions
7407 if we treat it as such. Likewise if it is equivalent to a constant. */
7408 else if (CONSTANT_P (x)
7409 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7412 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7413 will be least confusing to the rest of the compiler. */
7414 else if (mode == BImode)
7416 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
7420 /* If X is known to be either 0 or -1, those are the true and
7421 false values when testing X. */
7422 else if (x == constm1_rtx || x == const0_rtx
7423 || (mode != VOIDmode
7424 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
7426 *ptrue = constm1_rtx, *pfalse = const0_rtx;
7430 /* Likewise for 0 or a single bit. */
7431 else if (SCALAR_INT_MODE_P (mode)
7432 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7433 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7435 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
7439 /* Otherwise fail; show no condition with true and false values the same. */
7440 *ptrue = *pfalse = x;
7444 /* Return the value of expression X given the fact that condition COND
7445 is known to be true when applied to REG as its first operand and VAL
7446 as its second. X is known to not be shared and so can be modified in
7449 We only handle the simplest cases, and specifically those cases that
7450 arise with IF_THEN_ELSE expressions. */
7453 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
7455 enum rtx_code code = GET_CODE (x);
7460 if (side_effects_p (x))
7463 /* If either operand of the condition is a floating point value,
7464 then we have to avoid collapsing an EQ comparison. */
7466 && rtx_equal_p (x, reg)
7467 && ! FLOAT_MODE_P (GET_MODE (x))
7468 && ! FLOAT_MODE_P (GET_MODE (val)))
7471 if (cond == UNEQ && rtx_equal_p (x, reg))
7474 /* If X is (abs REG) and we know something about REG's relationship
7475 with zero, we may be able to simplify this. */
7477 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
7480 case GE: case GT: case EQ:
7483 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
7485 GET_MODE (XEXP (x, 0)));
7490 /* The only other cases we handle are MIN, MAX, and comparisons if the
7491 operands are the same as REG and VAL. */
7493 else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
7495 if (rtx_equal_p (XEXP (x, 0), val))
7496 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
7498 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
7500 if (GET_RTX_CLASS (code) == '<')
7502 if (comparison_dominates_p (cond, code))
7503 return const_true_rtx;
7505 code = combine_reversed_comparison_code (x);
7507 && comparison_dominates_p (cond, code))
7512 else if (code == SMAX || code == SMIN
7513 || code == UMIN || code == UMAX)
7515 int unsignedp = (code == UMIN || code == UMAX);
7517 /* Do not reverse the condition when it is NE or EQ.
7518 This is because we cannot conclude anything about
7519 the value of 'SMAX (x, y)' when x is not equal to y,
7520 but we can when x equals y. */
7521 if ((code == SMAX || code == UMAX)
7522 && ! (cond == EQ || cond == NE))
7523 cond = reverse_condition (cond);
7528 return unsignedp ? x : XEXP (x, 1);
7530 return unsignedp ? x : XEXP (x, 0);
7532 return unsignedp ? XEXP (x, 1) : x;
7534 return unsignedp ? XEXP (x, 0) : x;
7541 else if (code == SUBREG)
7543 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
7544 rtx new, r = known_cond (SUBREG_REG (x), cond, reg, val);
7546 if (SUBREG_REG (x) != r)
7548 /* We must simplify subreg here, before we lose track of the
7549 original inner_mode. */
7550 new = simplify_subreg (GET_MODE (x), r,
7551 inner_mode, SUBREG_BYTE (x));
7555 SUBST (SUBREG_REG (x), r);
7560 /* We don't have to handle SIGN_EXTEND here, because even in the
7561 case of replacing something with a modeless CONST_INT, a
7562 CONST_INT is already (supposed to be) a valid sign extension for
7563 its narrower mode, which implies it's already properly
7564 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
7565 story is different. */
7566 else if (code == ZERO_EXTEND)
7568 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
7569 rtx new, r = known_cond (XEXP (x, 0), cond, reg, val);
7571 if (XEXP (x, 0) != r)
7573 /* We must simplify the zero_extend here, before we lose
7574 track of the original inner_mode. */
7575 new = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
7580 SUBST (XEXP (x, 0), r);
7586 fmt = GET_RTX_FORMAT (code);
7587 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7590 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7591 else if (fmt[i] == 'E')
7592 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7593 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7600 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7601 assignment as a field assignment. */
7604 rtx_equal_for_field_assignment_p (rtx x, rtx y)
7606 if (x == y || rtx_equal_p (x, y))
7609 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7612 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7613 Note that all SUBREGs of MEM are paradoxical; otherwise they
7614 would have been rewritten. */
7615 if (GET_CODE (x) == MEM && GET_CODE (y) == SUBREG
7616 && GET_CODE (SUBREG_REG (y)) == MEM
7617 && rtx_equal_p (SUBREG_REG (y),
7618 gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
7621 if (GET_CODE (y) == MEM && GET_CODE (x) == SUBREG
7622 && GET_CODE (SUBREG_REG (x)) == MEM
7623 && rtx_equal_p (SUBREG_REG (x),
7624 gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
7627 /* We used to see if get_last_value of X and Y were the same but that's
7628 not correct. In one direction, we'll cause the assignment to have
7629 the wrong destination and in the case, we'll import a register into this
7630 insn that might have already have been dead. So fail if none of the
7631 above cases are true. */
7635 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7636 Return that assignment if so.
7638 We only handle the most common cases. */
7641 make_field_assignment (rtx x)
7643 rtx dest = SET_DEST (x);
7644 rtx src = SET_SRC (x);
7649 unsigned HOST_WIDE_INT len;
7651 enum machine_mode mode;
7653 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7654 a clear of a one-bit field. We will have changed it to
7655 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7658 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7659 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7660 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7661 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7663 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7666 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7670 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7671 && subreg_lowpart_p (XEXP (src, 0))
7672 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7673 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7674 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7675 && GET_CODE (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == CONST_INT
7676 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7677 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7679 assign = make_extraction (VOIDmode, dest, 0,
7680 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7683 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7687 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7689 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7690 && XEXP (XEXP (src, 0), 0) == const1_rtx
7691 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7693 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7696 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
7700 /* The other case we handle is assignments into a constant-position
7701 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7702 a mask that has all one bits except for a group of zero bits and
7703 OTHER is known to have zeros where C1 has ones, this is such an
7704 assignment. Compute the position and length from C1. Shift OTHER
7705 to the appropriate position, force it to the required mode, and
7706 make the extraction. Check for the AND in both operands. */
7708 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
7711 rhs = expand_compound_operation (XEXP (src, 0));
7712 lhs = expand_compound_operation (XEXP (src, 1));
7714 if (GET_CODE (rhs) == AND
7715 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7716 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7717 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7718 else if (GET_CODE (lhs) == AND
7719 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7720 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7721 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
7725 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
7726 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
7727 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7728 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
7731 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
7735 /* The mode to use for the source is the mode of the assignment, or of
7736 what is inside a possible STRICT_LOW_PART. */
7737 mode = (GET_CODE (assign) == STRICT_LOW_PART
7738 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
7740 /* Shift OTHER right POS places and make it the source, restricting it
7741 to the proper length and mode. */
7743 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
7744 GET_MODE (src), other, pos),
7746 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7747 ? ~(unsigned HOST_WIDE_INT) 0
7748 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7751 /* If SRC is masked by an AND that does not make a difference in
7752 the value being stored, strip it. */
7753 if (GET_CODE (assign) == ZERO_EXTRACT
7754 && GET_CODE (XEXP (assign, 1)) == CONST_INT
7755 && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
7756 && GET_CODE (src) == AND
7757 && GET_CODE (XEXP (src, 1)) == CONST_INT
7758 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (src, 1))
7759 == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1))
7760 src = XEXP (src, 0);
7762 return gen_rtx_SET (VOIDmode, assign, src);
7765 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7769 apply_distributive_law (rtx x)
7771 enum rtx_code code = GET_CODE (x);
7772 enum rtx_code inner_code;
7773 rtx lhs, rhs, other;
7776 /* Distributivity is not true for floating point as it can change the
7777 value. So we don't do it unless -funsafe-math-optimizations. */
7778 if (FLOAT_MODE_P (GET_MODE (x))
7779 && ! flag_unsafe_math_optimizations)
7782 /* The outer operation can only be one of the following: */
7783 if (code != IOR && code != AND && code != XOR
7784 && code != PLUS && code != MINUS)
7790 /* If either operand is a primitive we can't do anything, so get out
7792 if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
7793 || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
7796 lhs = expand_compound_operation (lhs);
7797 rhs = expand_compound_operation (rhs);
7798 inner_code = GET_CODE (lhs);
7799 if (inner_code != GET_CODE (rhs))
7802 /* See if the inner and outer operations distribute. */
7809 /* These all distribute except over PLUS. */
7810 if (code == PLUS || code == MINUS)
7815 if (code != PLUS && code != MINUS)
7820 /* This is also a multiply, so it distributes over everything. */
7824 /* Non-paradoxical SUBREGs distributes over all operations, provided
7825 the inner modes and byte offsets are the same, this is an extraction
7826 of a low-order part, we don't convert an fp operation to int or
7827 vice versa, and we would not be converting a single-word
7828 operation into a multi-word operation. The latter test is not
7829 required, but it prevents generating unneeded multi-word operations.
7830 Some of the previous tests are redundant given the latter test, but
7831 are retained because they are required for correctness.
7833 We produce the result slightly differently in this case. */
7835 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7836 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
7837 || ! subreg_lowpart_p (lhs)
7838 || (GET_MODE_CLASS (GET_MODE (lhs))
7839 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
7840 || (GET_MODE_SIZE (GET_MODE (lhs))
7841 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
7842 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
7845 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
7846 SUBREG_REG (lhs), SUBREG_REG (rhs));
7847 return gen_lowpart (GET_MODE (x), tem);
7853 /* Set LHS and RHS to the inner operands (A and B in the example
7854 above) and set OTHER to the common operand (C in the example).
7855 These is only one way to do this unless the inner operation is
7857 if (GET_RTX_CLASS (inner_code) == 'c'
7858 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
7859 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
7860 else if (GET_RTX_CLASS (inner_code) == 'c'
7861 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
7862 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
7863 else if (GET_RTX_CLASS (inner_code) == 'c'
7864 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
7865 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
7866 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
7867 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
7871 /* Form the new inner operation, seeing if it simplifies first. */
7872 tem = gen_binary (code, GET_MODE (x), lhs, rhs);
7874 /* There is one exception to the general way of distributing:
7875 (a | c) ^ (b | c) -> (a ^ b) & ~c */
7876 if (code == XOR && inner_code == IOR)
7879 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
7882 /* We may be able to continuing distributing the result, so call
7883 ourselves recursively on the inner operation before forming the
7884 outer operation, which we return. */
7885 return gen_binary (inner_code, GET_MODE (x),
7886 apply_distributive_law (tem), other);
7889 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7892 Return an equivalent form, if different from X. Otherwise, return X. If
7893 X is zero, we are to always construct the equivalent form. */
7896 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
7897 unsigned HOST_WIDE_INT constop)
7899 unsigned HOST_WIDE_INT nonzero;
7902 /* Simplify VAROP knowing that we will be only looking at some of the
7905 Note by passing in CONSTOP, we guarantee that the bits not set in
7906 CONSTOP are not significant and will never be examined. We must
7907 ensure that is the case by explicitly masking out those bits
7908 before returning. */
7909 varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
7911 /* If VAROP is a CLOBBER, we will fail so return it. */
7912 if (GET_CODE (varop) == CLOBBER)
7915 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
7916 to VAROP and return the new constant. */
7917 if (GET_CODE (varop) == CONST_INT)
7918 return GEN_INT (trunc_int_for_mode (INTVAL (varop) & constop, mode));
7920 /* See what bits may be nonzero in VAROP. Unlike the general case of
7921 a call to nonzero_bits, here we don't care about bits outside
7924 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
7926 /* Turn off all bits in the constant that are known to already be zero.
7927 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7928 which is tested below. */
7932 /* If we don't have any bits left, return zero. */
7936 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7937 a power of two, we can replace this with an ASHIFT. */
7938 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
7939 && (i = exact_log2 (constop)) >= 0)
7940 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
7942 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7943 or XOR, then try to apply the distributive law. This may eliminate
7944 operations if either branch can be simplified because of the AND.
7945 It may also make some cases more complex, but those cases probably
7946 won't match a pattern either with or without this. */
7948 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
7952 apply_distributive_law
7953 (gen_binary (GET_CODE (varop), GET_MODE (varop),
7954 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7955 XEXP (varop, 0), constop),
7956 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7957 XEXP (varop, 1), constop))));
7959 /* If VAROP is PLUS, and the constant is a mask of low bite, distribute
7960 the AND and see if one of the operands simplifies to zero. If so, we
7961 may eliminate it. */
7963 if (GET_CODE (varop) == PLUS
7964 && exact_log2 (constop + 1) >= 0)
7968 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
7969 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
7970 if (o0 == const0_rtx)
7972 if (o1 == const0_rtx)
7976 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
7977 if we already had one (just check for the simplest cases). */
7978 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
7979 && GET_MODE (XEXP (x, 0)) == mode
7980 && SUBREG_REG (XEXP (x, 0)) == varop)
7981 varop = XEXP (x, 0);
7983 varop = gen_lowpart (mode, varop);
7985 /* If we can't make the SUBREG, try to return what we were given. */
7986 if (GET_CODE (varop) == CLOBBER)
7987 return x ? x : varop;
7989 /* If we are only masking insignificant bits, return VAROP. */
7990 if (constop == nonzero)
7994 /* Otherwise, return an AND. */
7995 constop = trunc_int_for_mode (constop, mode);
7996 /* See how much, if any, of X we can use. */
7997 if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
7998 x = gen_binary (AND, mode, varop, GEN_INT (constop));
8002 if (GET_CODE (XEXP (x, 1)) != CONST_INT
8003 || (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) != constop)
8004 SUBST (XEXP (x, 1), GEN_INT (constop));
8006 SUBST (XEXP (x, 0), varop);
8013 #define nonzero_bits_with_known(X, MODE) \
8014 cached_nonzero_bits (X, MODE, known_x, known_mode, known_ret)
8016 /* The function cached_nonzero_bits is a wrapper around nonzero_bits1.
8017 It avoids exponential behavior in nonzero_bits1 when X has
8018 identical subexpressions on the first or the second level. */
8020 static unsigned HOST_WIDE_INT
8021 cached_nonzero_bits (rtx x, enum machine_mode mode, rtx known_x,
8022 enum machine_mode known_mode,
8023 unsigned HOST_WIDE_INT known_ret)
8025 if (x == known_x && mode == known_mode)
8028 /* Try to find identical subexpressions. If found call
8029 nonzero_bits1 on X with the subexpressions as KNOWN_X and the
8030 precomputed value for the subexpression as KNOWN_RET. */
8032 if (GET_RTX_CLASS (GET_CODE (x)) == '2'
8033 || GET_RTX_CLASS (GET_CODE (x)) == 'c')
8035 rtx x0 = XEXP (x, 0);
8036 rtx x1 = XEXP (x, 1);
8038 /* Check the first level. */
8040 return nonzero_bits1 (x, mode, x0, mode,
8041 nonzero_bits_with_known (x0, mode));
8043 /* Check the second level. */
8044 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
8045 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
8046 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
8047 return nonzero_bits1 (x, mode, x1, mode,
8048 nonzero_bits_with_known (x1, mode));
8050 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
8051 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
8052 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
8053 return nonzero_bits1 (x, mode, x0, mode,
8054 nonzero_bits_with_known (x0, mode));
8057 return nonzero_bits1 (x, mode, known_x, known_mode, known_ret);
8060 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
8061 We don't let nonzero_bits recur into num_sign_bit_copies, because that
8062 is less useful. We can't allow both, because that results in exponential
8063 run time recursion. There is a nullstone testcase that triggered
8064 this. This macro avoids accidental uses of num_sign_bit_copies. */
8065 #define cached_num_sign_bit_copies()
8067 /* Given an expression, X, compute which bits in X can be nonzero.
8068 We don't care about bits outside of those defined in MODE.
8070 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8071 a shift, AND, or zero_extract, we can do better. */
8073 static unsigned HOST_WIDE_INT
8074 nonzero_bits1 (rtx x, enum machine_mode mode, rtx known_x,
8075 enum machine_mode known_mode,
8076 unsigned HOST_WIDE_INT known_ret)
8078 unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);
8079 unsigned HOST_WIDE_INT inner_nz;
8081 unsigned int mode_width = GET_MODE_BITSIZE (mode);
8084 /* For floating-point values, assume all bits are needed. */
8085 if (FLOAT_MODE_P (GET_MODE (x)) || FLOAT_MODE_P (mode))
8088 /* If X is wider than MODE, use its mode instead. */
8089 if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
8091 mode = GET_MODE (x);
8092 nonzero = GET_MODE_MASK (mode);
8093 mode_width = GET_MODE_BITSIZE (mode);
8096 if (mode_width > HOST_BITS_PER_WIDE_INT)
8097 /* Our only callers in this case look for single bit values. So
8098 just return the mode mask. Those tests will then be false. */
8101 #ifndef WORD_REGISTER_OPERATIONS
8102 /* If MODE is wider than X, but both are a single word for both the host
8103 and target machines, we can compute this from which bits of the
8104 object might be nonzero in its own mode, taking into account the fact
8105 that on many CISC machines, accessing an object in a wider mode
8106 causes the high-order bits to become undefined. So they are
8107 not known to be zero. */
8109 if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode
8110 && GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD
8111 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
8112 && GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (GET_MODE (x)))
8114 nonzero &= nonzero_bits_with_known (x, GET_MODE (x));
8115 nonzero |= GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x));
8120 code = GET_CODE (x);
8124 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8125 /* If pointers extend unsigned and this is a pointer in Pmode, say that
8126 all the bits above ptr_mode are known to be zero. */
8127 if (POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
8129 nonzero &= GET_MODE_MASK (ptr_mode);
8132 /* Include declared information about alignment of pointers. */
8133 /* ??? We don't properly preserve REG_POINTER changes across
8134 pointer-to-integer casts, so we can't trust it except for
8135 things that we know must be pointers. See execute/960116-1.c. */
8136 if ((x == stack_pointer_rtx
8137 || x == frame_pointer_rtx
8138 || x == arg_pointer_rtx)
8139 && REGNO_POINTER_ALIGN (REGNO (x)))
8141 unsigned HOST_WIDE_INT alignment
8142 = REGNO_POINTER_ALIGN (REGNO (x)) / BITS_PER_UNIT;
8144 #ifdef PUSH_ROUNDING
8145 /* If PUSH_ROUNDING is defined, it is possible for the
8146 stack to be momentarily aligned only to that amount,
8147 so we pick the least alignment. */
8148 if (x == stack_pointer_rtx && PUSH_ARGS)
8149 alignment = MIN ((unsigned HOST_WIDE_INT) PUSH_ROUNDING (1),
8153 nonzero &= ~(alignment - 1);
8156 /* If X is a register whose nonzero bits value is current, use it.
8157 Otherwise, if X is a register whose value we can find, use that
8158 value. Otherwise, use the previously-computed global nonzero bits
8159 for this register. */
8161 if (reg_last_set_value[REGNO (x)] != 0
8162 && (reg_last_set_mode[REGNO (x)] == mode
8163 || (GET_MODE_CLASS (reg_last_set_mode[REGNO (x)]) == MODE_INT
8164 && GET_MODE_CLASS (mode) == MODE_INT))
8165 && (reg_last_set_label[REGNO (x)] == label_tick
8166 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8167 && REG_N_SETS (REGNO (x)) == 1
8168 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start,
8170 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
8171 return reg_last_set_nonzero_bits[REGNO (x)] & nonzero;
8173 tem = get_last_value (x);
8177 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8178 /* If X is narrower than MODE and TEM is a non-negative
8179 constant that would appear negative in the mode of X,
8180 sign-extend it for use in reg_nonzero_bits because some
8181 machines (maybe most) will actually do the sign-extension
8182 and this is the conservative approach.
8184 ??? For 2.5, try to tighten up the MD files in this regard
8185 instead of this kludge. */
8187 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width
8188 && GET_CODE (tem) == CONST_INT
8190 && 0 != (INTVAL (tem)
8191 & ((HOST_WIDE_INT) 1
8192 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8193 tem = GEN_INT (INTVAL (tem)
8194 | ((HOST_WIDE_INT) (-1)
8195 << GET_MODE_BITSIZE (GET_MODE (x))));
8197 return nonzero_bits_with_known (tem, mode) & nonzero;
8199 else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)])
8201 unsigned HOST_WIDE_INT mask = reg_nonzero_bits[REGNO (x)];
8203 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width)
8204 /* We don't know anything about the upper bits. */
8205 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
8206 return nonzero & mask;
8212 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8213 /* If X is negative in MODE, sign-extend the value. */
8214 if (INTVAL (x) > 0 && mode_width < BITS_PER_WORD
8215 && 0 != (INTVAL (x) & ((HOST_WIDE_INT) 1 << (mode_width - 1))))
8216 return (INTVAL (x) | ((HOST_WIDE_INT) (-1) << mode_width));
8222 #ifdef LOAD_EXTEND_OP
8223 /* In many, if not most, RISC machines, reading a byte from memory
8224 zeros the rest of the register. Noticing that fact saves a lot
8225 of extra zero-extends. */
8226 if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND)
8227 nonzero &= GET_MODE_MASK (GET_MODE (x));
8232 case UNEQ: case LTGT:
8233 case GT: case GTU: case UNGT:
8234 case LT: case LTU: case UNLT:
8235 case GE: case GEU: case UNGE:
8236 case LE: case LEU: case UNLE:
8237 case UNORDERED: case ORDERED:
8239 /* If this produces an integer result, we know which bits are set.
8240 Code here used to clear bits outside the mode of X, but that is
8243 if (GET_MODE_CLASS (mode) == MODE_INT
8244 && mode_width <= HOST_BITS_PER_WIDE_INT)
8245 nonzero = STORE_FLAG_VALUE;
8250 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8251 and num_sign_bit_copies. */
8252 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
8253 == GET_MODE_BITSIZE (GET_MODE (x)))
8257 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
8258 nonzero |= (GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x)));
8263 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8264 and num_sign_bit_copies. */
8265 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
8266 == GET_MODE_BITSIZE (GET_MODE (x)))
8272 nonzero &= (nonzero_bits_with_known (XEXP (x, 0), mode)
8273 & GET_MODE_MASK (mode));
8277 nonzero &= nonzero_bits_with_known (XEXP (x, 0), mode);
8278 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
8279 nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
8283 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
8284 Otherwise, show all the bits in the outer mode but not the inner
8286 inner_nz = nonzero_bits_with_known (XEXP (x, 0), mode);
8287 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
8289 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
8291 & (((HOST_WIDE_INT) 1
8292 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
8293 inner_nz |= (GET_MODE_MASK (mode)
8294 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
8297 nonzero &= inner_nz;
8301 nonzero &= (nonzero_bits_with_known (XEXP (x, 0), mode)
8302 & nonzero_bits_with_known (XEXP (x, 1), mode));
8306 case UMIN: case UMAX: case SMIN: case SMAX:
8308 unsigned HOST_WIDE_INT nonzero0 =
8309 nonzero_bits_with_known (XEXP (x, 0), mode);
8311 /* Don't call nonzero_bits for the second time if it cannot change
8313 if ((nonzero & nonzero0) != nonzero)
8314 nonzero &= (nonzero0
8315 | nonzero_bits_with_known (XEXP (x, 1), mode));
8319 case PLUS: case MINUS:
8321 case DIV: case UDIV:
8322 case MOD: case UMOD:
8323 /* We can apply the rules of arithmetic to compute the number of
8324 high- and low-order zero bits of these operations. We start by
8325 computing the width (position of the highest-order nonzero bit)
8326 and the number of low-order zero bits for each value. */
8328 unsigned HOST_WIDE_INT nz0 =
8329 nonzero_bits_with_known (XEXP (x, 0), mode);
8330 unsigned HOST_WIDE_INT nz1 =
8331 nonzero_bits_with_known (XEXP (x, 1), mode);
8332 int sign_index = GET_MODE_BITSIZE (GET_MODE (x)) - 1;
8333 int width0 = floor_log2 (nz0) + 1;
8334 int width1 = floor_log2 (nz1) + 1;
8335 int low0 = floor_log2 (nz0 & -nz0);
8336 int low1 = floor_log2 (nz1 & -nz1);
8337 HOST_WIDE_INT op0_maybe_minusp
8338 = (nz0 & ((HOST_WIDE_INT) 1 << sign_index));
8339 HOST_WIDE_INT op1_maybe_minusp
8340 = (nz1 & ((HOST_WIDE_INT) 1 << sign_index));
8341 unsigned int result_width = mode_width;
8347 result_width = MAX (width0, width1) + 1;
8348 result_low = MIN (low0, low1);
8351 result_low = MIN (low0, low1);
8354 result_width = width0 + width1;
8355 result_low = low0 + low1;
8360 if (! op0_maybe_minusp && ! op1_maybe_minusp)
8361 result_width = width0;
8366 result_width = width0;
8371 if (! op0_maybe_minusp && ! op1_maybe_minusp)
8372 result_width = MIN (width0, width1);
8373 result_low = MIN (low0, low1);
8378 result_width = MIN (width0, width1);
8379 result_low = MIN (low0, low1);
8385 if (result_width < mode_width)
8386 nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1;
8389 nonzero &= ~(((HOST_WIDE_INT) 1 << result_low) - 1);
8391 #ifdef POINTERS_EXTEND_UNSIGNED
8392 /* If pointers extend unsigned and this is an addition or subtraction
8393 to a pointer in Pmode, all the bits above ptr_mode are known to be
8395 if (POINTERS_EXTEND_UNSIGNED > 0 && GET_MODE (x) == Pmode
8396 && (code == PLUS || code == MINUS)
8397 && GET_CODE (XEXP (x, 0)) == REG && REG_POINTER (XEXP (x, 0)))
8398 nonzero &= GET_MODE_MASK (ptr_mode);
8404 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8405 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8406 nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1;
8410 /* If this is a SUBREG formed for a promoted variable that has
8411 been zero-extended, we know that at least the high-order bits
8412 are zero, though others might be too. */
8414 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x) > 0)
8415 nonzero = (GET_MODE_MASK (GET_MODE (x))
8416 & nonzero_bits_with_known (SUBREG_REG (x), GET_MODE (x)));
8418 /* If the inner mode is a single word for both the host and target
8419 machines, we can compute this from which bits of the inner
8420 object might be nonzero. */
8421 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
8422 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8423 <= HOST_BITS_PER_WIDE_INT))
8425 nonzero &= nonzero_bits_with_known (SUBREG_REG (x), mode);
8427 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
8428 /* If this is a typical RISC machine, we only have to worry
8429 about the way loads are extended. */
8430 if ((LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
8432 & (((unsigned HOST_WIDE_INT) 1
8433 << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) - 1))))
8435 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) != ZERO_EXTEND)
8436 || GET_CODE (SUBREG_REG (x)) != MEM)
8439 /* On many CISC machines, accessing an object in a wider mode
8440 causes the high-order bits to become undefined. So they are
8441 not known to be zero. */
8442 if (GET_MODE_SIZE (GET_MODE (x))
8443 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8444 nonzero |= (GET_MODE_MASK (GET_MODE (x))
8445 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
8454 /* The nonzero bits are in two classes: any bits within MODE
8455 that aren't in GET_MODE (x) are always significant. The rest of the
8456 nonzero bits are those that are significant in the operand of
8457 the shift when shifted the appropriate number of bits. This
8458 shows that high-order bits are cleared by the right shift and
8459 low-order bits by left shifts. */
8460 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8461 && INTVAL (XEXP (x, 1)) >= 0
8462 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8464 enum machine_mode inner_mode = GET_MODE (x);
8465 unsigned int width = GET_MODE_BITSIZE (inner_mode);
8466 int count = INTVAL (XEXP (x, 1));
8467 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
8468 unsigned HOST_WIDE_INT op_nonzero =
8469 nonzero_bits_with_known (XEXP (x, 0), mode);
8470 unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask;
8471 unsigned HOST_WIDE_INT outer = 0;
8473 if (mode_width > width)
8474 outer = (op_nonzero & nonzero & ~mode_mask);
8476 if (code == LSHIFTRT)
8478 else if (code == ASHIFTRT)
8482 /* If the sign bit may have been nonzero before the shift, we
8483 need to mark all the places it could have been copied to
8484 by the shift as possibly nonzero. */
8485 if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count)))
8486 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count);
8488 else if (code == ASHIFT)
8491 inner = ((inner << (count % width)
8492 | (inner >> (width - (count % width)))) & mode_mask);
8494 nonzero &= (outer | inner);
8500 /* This is at most the number of bits in the mode. */
8501 nonzero = ((HOST_WIDE_INT) 2 << (floor_log2 (mode_width))) - 1;
8505 /* If CLZ has a known value at zero, then the nonzero bits are
8506 that value, plus the number of bits in the mode minus one. */
8507 if (CLZ_DEFINED_VALUE_AT_ZERO (mode, nonzero))
8508 nonzero |= ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width))) - 1;
8514 /* If CTZ has a known value at zero, then the nonzero bits are
8515 that value, plus the number of bits in the mode minus one. */
8516 if (CTZ_DEFINED_VALUE_AT_ZERO (mode, nonzero))
8517 nonzero |= ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width))) - 1;
8527 nonzero &= (nonzero_bits_with_known (XEXP (x, 1), mode)
8528 | nonzero_bits_with_known (XEXP (x, 2), mode));
8538 /* See the macro definition above. */
8539 #undef cached_num_sign_bit_copies
8541 #define num_sign_bit_copies_with_known(X, M) \
8542 cached_num_sign_bit_copies (X, M, known_x, known_mode, known_ret)
8544 /* The function cached_num_sign_bit_copies is a wrapper around
8545 num_sign_bit_copies1. It avoids exponential behavior in
8546 num_sign_bit_copies1 when X has identical subexpressions on the
8547 first or the second level. */
8550 cached_num_sign_bit_copies (rtx x, enum machine_mode mode, rtx known_x,
8551 enum machine_mode known_mode,
8552 unsigned int known_ret)
8554 if (x == known_x && mode == known_mode)
8557 /* Try to find identical subexpressions. If found call
8558 num_sign_bit_copies1 on X with the subexpressions as KNOWN_X and
8559 the precomputed value for the subexpression as KNOWN_RET. */
8561 if (GET_RTX_CLASS (GET_CODE (x)) == '2'
8562 || GET_RTX_CLASS (GET_CODE (x)) == 'c')
8564 rtx x0 = XEXP (x, 0);
8565 rtx x1 = XEXP (x, 1);
8567 /* Check the first level. */
8570 num_sign_bit_copies1 (x, mode, x0, mode,
8571 num_sign_bit_copies_with_known (x0, mode));
8573 /* Check the second level. */
8574 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
8575 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
8576 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
8578 num_sign_bit_copies1 (x, mode, x1, mode,
8579 num_sign_bit_copies_with_known (x1, mode));
8581 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
8582 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
8583 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
8585 num_sign_bit_copies1 (x, mode, x0, mode,
8586 num_sign_bit_copies_with_known (x0, mode));
8589 return num_sign_bit_copies1 (x, mode, known_x, known_mode, known_ret);
8592 /* Return the number of bits at the high-order end of X that are known to
8593 be equal to the sign bit. X will be used in mode MODE; if MODE is
8594 VOIDmode, X will be used in its own mode. The returned value will always
8595 be between 1 and the number of bits in MODE. */
8598 num_sign_bit_copies1 (rtx x, enum machine_mode mode, rtx known_x,
8599 enum machine_mode known_mode,
8600 unsigned int known_ret)
8602 enum rtx_code code = GET_CODE (x);
8603 unsigned int bitwidth;
8604 int num0, num1, result;
8605 unsigned HOST_WIDE_INT nonzero;
8608 /* If we weren't given a mode, use the mode of X. If the mode is still
8609 VOIDmode, we don't know anything. Likewise if one of the modes is
8612 if (mode == VOIDmode)
8613 mode = GET_MODE (x);
8615 if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x)))
8618 bitwidth = GET_MODE_BITSIZE (mode);
8620 /* For a smaller object, just ignore the high bits. */
8621 if (bitwidth < GET_MODE_BITSIZE (GET_MODE (x)))
8623 num0 = num_sign_bit_copies_with_known (x, GET_MODE (x));
8625 num0 - (int) (GET_MODE_BITSIZE (GET_MODE (x)) - bitwidth));
8628 if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_BITSIZE (GET_MODE (x)))
8630 #ifndef WORD_REGISTER_OPERATIONS
8631 /* If this machine does not do all register operations on the entire
8632 register and MODE is wider than the mode of X, we can say nothing
8633 at all about the high-order bits. */
8636 /* Likewise on machines that do, if the mode of the object is smaller
8637 than a word and loads of that size don't sign extend, we can say
8638 nothing about the high order bits. */
8639 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
8640 #ifdef LOAD_EXTEND_OP
8641 && LOAD_EXTEND_OP (GET_MODE (x)) != SIGN_EXTEND
8652 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8653 /* If pointers extend signed and this is a pointer in Pmode, say that
8654 all the bits above ptr_mode are known to be sign bit copies. */
8655 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode && mode == Pmode
8657 return GET_MODE_BITSIZE (Pmode) - GET_MODE_BITSIZE (ptr_mode) + 1;
8660 if (reg_last_set_value[REGNO (x)] != 0
8661 && reg_last_set_mode[REGNO (x)] == mode
8662 && (reg_last_set_label[REGNO (x)] == label_tick
8663 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8664 && REG_N_SETS (REGNO (x)) == 1
8665 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start,
8667 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
8668 return reg_last_set_sign_bit_copies[REGNO (x)];
8670 tem = get_last_value (x);
8672 return num_sign_bit_copies_with_known (tem, mode);
8674 if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0
8675 && GET_MODE_BITSIZE (GET_MODE (x)) == bitwidth)
8676 return reg_sign_bit_copies[REGNO (x)];
8680 #ifdef LOAD_EXTEND_OP
8681 /* Some RISC machines sign-extend all loads of smaller than a word. */
8682 if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND)
8683 return MAX (1, ((int) bitwidth
8684 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1));
8689 /* If the constant is negative, take its 1's complement and remask.
8690 Then see how many zero bits we have. */
8691 nonzero = INTVAL (x) & GET_MODE_MASK (mode);
8692 if (bitwidth <= HOST_BITS_PER_WIDE_INT
8693 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8694 nonzero = (~nonzero) & GET_MODE_MASK (mode);
8696 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
8699 /* If this is a SUBREG for a promoted object that is sign-extended
8700 and we are looking at it in a wider mode, we know that at least the
8701 high-order bits are known to be sign bit copies. */
8703 if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
8705 num0 = num_sign_bit_copies_with_known (SUBREG_REG (x), mode);
8706 return MAX ((int) bitwidth
8707 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1,
8711 /* For a smaller object, just ignore the high bits. */
8712 if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
8714 num0 = num_sign_bit_copies_with_known (SUBREG_REG (x), VOIDmode);
8715 return MAX (1, (num0
8716 - (int) (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8720 #ifdef WORD_REGISTER_OPERATIONS
8721 #ifdef LOAD_EXTEND_OP
8722 /* For paradoxical SUBREGs on machines where all register operations
8723 affect the entire register, just look inside. Note that we are
8724 passing MODE to the recursive call, so the number of sign bit copies
8725 will remain relative to that mode, not the inner mode. */
8727 /* This works only if loads sign extend. Otherwise, if we get a
8728 reload for the inner part, it may be loaded from the stack, and
8729 then we lose all sign bit copies that existed before the store
8732 if ((GET_MODE_SIZE (GET_MODE (x))
8733 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8734 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
8735 && GET_CODE (SUBREG_REG (x)) == MEM)
8736 return num_sign_bit_copies_with_known (SUBREG_REG (x), mode);
8742 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
8743 return MAX (1, (int) bitwidth - INTVAL (XEXP (x, 1)));
8747 return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8748 + num_sign_bit_copies_with_known (XEXP (x, 0), VOIDmode));
8751 /* For a smaller object, just ignore the high bits. */
8752 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), VOIDmode);
8753 return MAX (1, (num0 - (int) (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8757 return num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8759 case ROTATE: case ROTATERT:
8760 /* If we are rotating left by a number of bits less than the number
8761 of sign bit copies, we can just subtract that amount from the
8763 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8764 && INTVAL (XEXP (x, 1)) >= 0
8765 && INTVAL (XEXP (x, 1)) < (int) bitwidth)
8767 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8768 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
8769 : (int) bitwidth - INTVAL (XEXP (x, 1))));
8774 /* In general, this subtracts one sign bit copy. But if the value
8775 is known to be positive, the number of sign bit copies is the
8776 same as that of the input. Finally, if the input has just one bit
8777 that might be nonzero, all the bits are copies of the sign bit. */
8778 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8779 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8780 return num0 > 1 ? num0 - 1 : 1;
8782 nonzero = nonzero_bits (XEXP (x, 0), mode);
8787 && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero))
8792 case IOR: case AND: case XOR:
8793 case SMIN: case SMAX: case UMIN: case UMAX:
8794 /* Logical operations will preserve the number of sign-bit copies.
8795 MIN and MAX operations always return one of the operands. */
8796 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8797 num1 = num_sign_bit_copies_with_known (XEXP (x, 1), mode);
8798 return MIN (num0, num1);
8800 case PLUS: case MINUS:
8801 /* For addition and subtraction, we can have a 1-bit carry. However,
8802 if we are subtracting 1 from a positive number, there will not
8803 be such a carry. Furthermore, if the positive number is known to
8804 be 0 or 1, we know the result is either -1 or 0. */
8806 if (code == PLUS && XEXP (x, 1) == constm1_rtx
8807 && bitwidth <= HOST_BITS_PER_WIDE_INT)
8809 nonzero = nonzero_bits (XEXP (x, 0), mode);
8810 if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0)
8811 return (nonzero == 1 || nonzero == 0 ? bitwidth
8812 : bitwidth - floor_log2 (nonzero) - 1);
8815 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8816 num1 = num_sign_bit_copies_with_known (XEXP (x, 1), mode);
8817 result = MAX (1, MIN (num0, num1) - 1);
8819 #ifdef POINTERS_EXTEND_UNSIGNED
8820 /* If pointers extend signed and this is an addition or subtraction
8821 to a pointer in Pmode, all the bits above ptr_mode are known to be
8823 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
8824 && (code == PLUS || code == MINUS)
8825 && GET_CODE (XEXP (x, 0)) == REG && REG_POINTER (XEXP (x, 0)))
8826 result = MAX ((int) (GET_MODE_BITSIZE (Pmode)
8827 - GET_MODE_BITSIZE (ptr_mode) + 1),
8833 /* The number of bits of the product is the sum of the number of
8834 bits of both terms. However, unless one of the terms if known
8835 to be positive, we must allow for an additional bit since negating
8836 a negative number can remove one sign bit copy. */
8838 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8839 num1 = num_sign_bit_copies_with_known (XEXP (x, 1), mode);
8841 result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
8843 && (bitwidth > HOST_BITS_PER_WIDE_INT
8844 || (((nonzero_bits (XEXP (x, 0), mode)
8845 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8846 && ((nonzero_bits (XEXP (x, 1), mode)
8847 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))))
8850 return MAX (1, result);
8853 /* The result must be <= the first operand. If the first operand
8854 has the high bit set, we know nothing about the number of sign
8856 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8858 else if ((nonzero_bits (XEXP (x, 0), mode)
8859 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8862 return num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8865 /* The result must be <= the second operand. */
8866 return num_sign_bit_copies_with_known (XEXP (x, 1), mode);
8869 /* Similar to unsigned division, except that we have to worry about
8870 the case where the divisor is negative, in which case we have
8872 result = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8874 && (bitwidth > HOST_BITS_PER_WIDE_INT
8875 || (nonzero_bits (XEXP (x, 1), mode)
8876 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8882 result = num_sign_bit_copies_with_known (XEXP (x, 1), mode);
8884 && (bitwidth > HOST_BITS_PER_WIDE_INT
8885 || (nonzero_bits (XEXP (x, 1), mode)
8886 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8892 /* Shifts by a constant add to the number of bits equal to the
8894 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8895 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8896 && INTVAL (XEXP (x, 1)) > 0)
8897 num0 = MIN ((int) bitwidth, num0 + INTVAL (XEXP (x, 1)));
8902 /* Left shifts destroy copies. */
8903 if (GET_CODE (XEXP (x, 1)) != CONST_INT
8904 || INTVAL (XEXP (x, 1)) < 0
8905 || INTVAL (XEXP (x, 1)) >= (int) bitwidth)
8908 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8909 return MAX (1, num0 - INTVAL (XEXP (x, 1)));
8912 num0 = num_sign_bit_copies_with_known (XEXP (x, 1), mode);
8913 num1 = num_sign_bit_copies_with_known (XEXP (x, 2), mode);
8914 return MIN (num0, num1);
8916 case EQ: case NE: case GE: case GT: case LE: case LT:
8917 case UNEQ: case LTGT: case UNGE: case UNGT: case UNLE: case UNLT:
8918 case GEU: case GTU: case LEU: case LTU:
8919 case UNORDERED: case ORDERED:
8920 /* If the constant is negative, take its 1's complement and remask.
8921 Then see how many zero bits we have. */
8922 nonzero = STORE_FLAG_VALUE;
8923 if (bitwidth <= HOST_BITS_PER_WIDE_INT
8924 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8925 nonzero = (~nonzero) & GET_MODE_MASK (mode);
8927 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
8934 /* If we haven't been able to figure it out by one of the above rules,
8935 see if some of the high-order bits are known to be zero. If so,
8936 count those bits and return one less than that amount. If we can't
8937 safely compute the mask for this mode, always return BITWIDTH. */
8939 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8942 nonzero = nonzero_bits (x, mode);
8943 return (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))
8944 ? 1 : bitwidth - floor_log2 (nonzero) - 1);
8947 /* Return the number of "extended" bits there are in X, when interpreted
8948 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8949 unsigned quantities, this is the number of high-order zero bits.
8950 For signed quantities, this is the number of copies of the sign bit
8951 minus 1. In both case, this function returns the number of "spare"
8952 bits. For example, if two quantities for which this function returns
8953 at least 1 are added, the addition is known not to overflow.
8955 This function will always return 0 unless called during combine, which
8956 implies that it must be called from a define_split. */
8959 extended_count (rtx x, enum machine_mode mode, int unsignedp)
8961 if (nonzero_sign_valid == 0)
8965 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8966 ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
8967 - floor_log2 (nonzero_bits (x, mode)))
8969 : num_sign_bit_copies (x, mode) - 1);
8972 /* This function is called from `simplify_shift_const' to merge two
8973 outer operations. Specifically, we have already found that we need
8974 to perform operation *POP0 with constant *PCONST0 at the outermost
8975 position. We would now like to also perform OP1 with constant CONST1
8976 (with *POP0 being done last).
8978 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8979 the resulting operation. *PCOMP_P is set to 1 if we would need to
8980 complement the innermost operand, otherwise it is unchanged.
8982 MODE is the mode in which the operation will be done. No bits outside
8983 the width of this mode matter. It is assumed that the width of this mode
8984 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8986 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
8987 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8988 result is simply *PCONST0.
8990 If the resulting operation cannot be expressed as one operation, we
8991 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8994 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
8996 enum rtx_code op0 = *pop0;
8997 HOST_WIDE_INT const0 = *pconst0;
8999 const0 &= GET_MODE_MASK (mode);
9000 const1 &= GET_MODE_MASK (mode);
9002 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9006 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
9009 if (op1 == NIL || op0 == SET)
9012 else if (op0 == NIL)
9013 op0 = op1, const0 = const1;
9015 else if (op0 == op1)
9039 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9040 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
9043 /* If the two constants aren't the same, we can't do anything. The
9044 remaining six cases can all be done. */
9045 else if (const0 != const1)
9053 /* (a & b) | b == b */
9055 else /* op1 == XOR */
9056 /* (a ^ b) | b == a | b */
9062 /* (a & b) ^ b == (~a) & b */
9063 op0 = AND, *pcomp_p = 1;
9064 else /* op1 == IOR */
9065 /* (a | b) ^ b == a & ~b */
9066 op0 = AND, const0 = ~const0;
9071 /* (a | b) & b == b */
9073 else /* op1 == XOR */
9074 /* (a ^ b) & b) == (~a) & b */
9081 /* Check for NO-OP cases. */
9082 const0 &= GET_MODE_MASK (mode);
9084 && (op0 == IOR || op0 == XOR || op0 == PLUS))
9086 else if (const0 == 0 && op0 == AND)
9088 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
9092 /* ??? Slightly redundant with the above mask, but not entirely.
9093 Moving this above means we'd have to sign-extend the mode mask
9094 for the final test. */
9095 const0 = trunc_int_for_mode (const0, mode);
9103 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9104 The result of the shift is RESULT_MODE. X, if nonzero, is an expression
9105 that we started with.
9107 The shift is normally computed in the widest mode we find in VAROP, as
9108 long as it isn't a different number of words than RESULT_MODE. Exceptions
9109 are ASHIFTRT and ROTATE, which are always done in their original mode, */
9112 simplify_shift_const (rtx x, enum rtx_code code,
9113 enum machine_mode result_mode, rtx varop,
9116 enum rtx_code orig_code = code;
9119 enum machine_mode mode = result_mode;
9120 enum machine_mode shift_mode, tmode;
9121 unsigned int mode_words
9122 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
9123 /* We form (outer_op (code varop count) (outer_const)). */
9124 enum rtx_code outer_op = NIL;
9125 HOST_WIDE_INT outer_const = 0;
9127 int complement_p = 0;
9130 /* Make sure and truncate the "natural" shift on the way in. We don't
9131 want to do this inside the loop as it makes it more difficult to
9133 if (SHIFT_COUNT_TRUNCATED)
9134 orig_count &= GET_MODE_BITSIZE (mode) - 1;
9136 /* If we were given an invalid count, don't do anything except exactly
9137 what was requested. */
9139 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
9144 return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (orig_count));
9149 /* Unless one of the branches of the `if' in this loop does a `continue',
9150 we will `break' the loop after the `if'. */
9154 /* If we have an operand of (clobber (const_int 0)), just return that
9156 if (GET_CODE (varop) == CLOBBER)
9159 /* If we discovered we had to complement VAROP, leave. Making a NOT
9160 here would cause an infinite loop. */
9164 /* Convert ROTATERT to ROTATE. */
9165 if (code == ROTATERT)
9167 unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
9169 if (VECTOR_MODE_P (result_mode))
9170 count = bitsize / GET_MODE_NUNITS (result_mode) - count;
9172 count = bitsize - count;
9175 /* We need to determine what mode we will do the shift in. If the
9176 shift is a right shift or a ROTATE, we must always do it in the mode
9177 it was originally done in. Otherwise, we can do it in MODE, the
9178 widest mode encountered. */
9180 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9181 ? result_mode : mode);
9183 /* Handle cases where the count is greater than the size of the mode
9184 minus 1. For ASHIFT, use the size minus one as the count (this can
9185 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9186 take the count modulo the size. For other shifts, the result is
9189 Since these shifts are being produced by the compiler by combining
9190 multiple operations, each of which are defined, we know what the
9191 result is supposed to be. */
9193 if (count > (unsigned int) (GET_MODE_BITSIZE (shift_mode) - 1))
9195 if (code == ASHIFTRT)
9196 count = GET_MODE_BITSIZE (shift_mode) - 1;
9197 else if (code == ROTATE || code == ROTATERT)
9198 count %= GET_MODE_BITSIZE (shift_mode);
9201 /* We can't simply return zero because there may be an
9209 /* An arithmetic right shift of a quantity known to be -1 or 0
9211 if (code == ASHIFTRT
9212 && (num_sign_bit_copies (varop, shift_mode)
9213 == GET_MODE_BITSIZE (shift_mode)))
9219 /* If we are doing an arithmetic right shift and discarding all but
9220 the sign bit copies, this is equivalent to doing a shift by the
9221 bitsize minus one. Convert it into that shift because it will often
9222 allow other simplifications. */
9224 if (code == ASHIFTRT
9225 && (count + num_sign_bit_copies (varop, shift_mode)
9226 >= GET_MODE_BITSIZE (shift_mode)))
9227 count = GET_MODE_BITSIZE (shift_mode) - 1;
9229 /* We simplify the tests below and elsewhere by converting
9230 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9231 `make_compound_operation' will convert it to an ASHIFTRT for
9232 those machines (such as VAX) that don't have an LSHIFTRT. */
9233 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9235 && ((nonzero_bits (varop, shift_mode)
9236 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
9240 if (code == LSHIFTRT
9241 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9242 && !(nonzero_bits (varop, shift_mode) >> count))
9245 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9246 && !((nonzero_bits (varop, shift_mode) << count)
9247 & GET_MODE_MASK (shift_mode)))
9250 switch (GET_CODE (varop))
9256 new = expand_compound_operation (varop);
9265 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9266 minus the width of a smaller mode, we can do this with a
9267 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9268 if ((code == ASHIFTRT || code == LSHIFTRT)
9269 && ! mode_dependent_address_p (XEXP (varop, 0))
9270 && ! MEM_VOLATILE_P (varop)
9271 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9272 MODE_INT, 1)) != BLKmode)
9274 new = adjust_address_nv (varop, tmode,
9275 BYTES_BIG_ENDIAN ? 0
9276 : count / BITS_PER_UNIT);
9278 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9279 : ZERO_EXTEND, mode, new);
9286 /* Similar to the case above, except that we can only do this if
9287 the resulting mode is the same as that of the underlying
9288 MEM and adjust the address depending on the *bits* endianness
9289 because of the way that bit-field extract insns are defined. */
9290 if ((code == ASHIFTRT || code == LSHIFTRT)
9291 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9292 MODE_INT, 1)) != BLKmode
9293 && tmode == GET_MODE (XEXP (varop, 0)))
9295 if (BITS_BIG_ENDIAN)
9296 new = XEXP (varop, 0);
9299 new = copy_rtx (XEXP (varop, 0));
9300 SUBST (XEXP (new, 0),
9301 plus_constant (XEXP (new, 0),
9302 count / BITS_PER_UNIT));
9305 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9306 : ZERO_EXTEND, mode, new);
9313 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9314 the same number of words as what we've seen so far. Then store
9315 the widest mode in MODE. */
9316 if (subreg_lowpart_p (varop)
9317 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9318 > GET_MODE_SIZE (GET_MODE (varop)))
9319 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9320 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9323 varop = SUBREG_REG (varop);
9324 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
9325 mode = GET_MODE (varop);
9331 /* Some machines use MULT instead of ASHIFT because MULT
9332 is cheaper. But it is still better on those machines to
9333 merge two shifts into one. */
9334 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9335 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9338 = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
9339 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
9345 /* Similar, for when divides are cheaper. */
9346 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9347 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9350 = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
9351 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
9357 /* If we are extracting just the sign bit of an arithmetic
9358 right shift, that shift is not needed. However, the sign
9359 bit of a wider mode may be different from what would be
9360 interpreted as the sign bit in a narrower mode, so, if
9361 the result is narrower, don't discard the shift. */
9362 if (code == LSHIFTRT
9363 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9364 && (GET_MODE_BITSIZE (result_mode)
9365 >= GET_MODE_BITSIZE (GET_MODE (varop))))
9367 varop = XEXP (varop, 0);
9371 /* ... fall through ... */
9376 /* Here we have two nested shifts. The result is usually the
9377 AND of a new shift with a mask. We compute the result below. */
9378 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9379 && INTVAL (XEXP (varop, 1)) >= 0
9380 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
9381 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9382 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9384 enum rtx_code first_code = GET_CODE (varop);
9385 unsigned int first_count = INTVAL (XEXP (varop, 1));
9386 unsigned HOST_WIDE_INT mask;
9389 /* We have one common special case. We can't do any merging if
9390 the inner code is an ASHIFTRT of a smaller mode. However, if
9391 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9392 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9393 we can convert it to
9394 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9395 This simplifies certain SIGN_EXTEND operations. */
9396 if (code == ASHIFT && first_code == ASHIFTRT
9397 && count == (unsigned int)
9398 (GET_MODE_BITSIZE (result_mode)
9399 - GET_MODE_BITSIZE (GET_MODE (varop))))
9401 /* C3 has the low-order C1 bits zero. */
9403 mask = (GET_MODE_MASK (mode)
9404 & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
9406 varop = simplify_and_const_int (NULL_RTX, result_mode,
9407 XEXP (varop, 0), mask);
9408 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
9410 count = first_count;
9415 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9416 than C1 high-order bits equal to the sign bit, we can convert
9417 this to either an ASHIFT or an ASHIFTRT depending on the
9420 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9422 if (code == ASHIFTRT && first_code == ASHIFT
9423 && GET_MODE (varop) == shift_mode
9424 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
9427 varop = XEXP (varop, 0);
9429 signed_count = count - first_count;
9430 if (signed_count < 0)
9431 count = -signed_count, code = ASHIFT;
9433 count = signed_count;
9438 /* There are some cases we can't do. If CODE is ASHIFTRT,
9439 we can only do this if FIRST_CODE is also ASHIFTRT.
9441 We can't do the case when CODE is ROTATE and FIRST_CODE is
9444 If the mode of this shift is not the mode of the outer shift,
9445 we can't do this if either shift is a right shift or ROTATE.
9447 Finally, we can't do any of these if the mode is too wide
9448 unless the codes are the same.
9450 Handle the case where the shift codes are the same
9453 if (code == first_code)
9455 if (GET_MODE (varop) != result_mode
9456 && (code == ASHIFTRT || code == LSHIFTRT
9460 count += first_count;
9461 varop = XEXP (varop, 0);
9465 if (code == ASHIFTRT
9466 || (code == ROTATE && first_code == ASHIFTRT)
9467 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
9468 || (GET_MODE (varop) != result_mode
9469 && (first_code == ASHIFTRT || first_code == LSHIFTRT
9470 || first_code == ROTATE
9471 || code == ROTATE)))
9474 /* To compute the mask to apply after the shift, shift the
9475 nonzero bits of the inner shift the same way the
9476 outer shift will. */
9478 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
9481 = simplify_binary_operation (code, result_mode, mask_rtx,
9484 /* Give up if we can't compute an outer operation to use. */
9486 || GET_CODE (mask_rtx) != CONST_INT
9487 || ! merge_outer_ops (&outer_op, &outer_const, AND,
9489 result_mode, &complement_p))
9492 /* If the shifts are in the same direction, we add the
9493 counts. Otherwise, we subtract them. */
9494 signed_count = count;
9495 if ((code == ASHIFTRT || code == LSHIFTRT)
9496 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
9497 signed_count += first_count;
9499 signed_count -= first_count;
9501 /* If COUNT is positive, the new shift is usually CODE,
9502 except for the two exceptions below, in which case it is
9503 FIRST_CODE. If the count is negative, FIRST_CODE should
9505 if (signed_count > 0
9506 && ((first_code == ROTATE && code == ASHIFT)
9507 || (first_code == ASHIFTRT && code == LSHIFTRT)))
9508 code = first_code, count = signed_count;
9509 else if (signed_count < 0)
9510 code = first_code, count = -signed_count;
9512 count = signed_count;
9514 varop = XEXP (varop, 0);
9518 /* If we have (A << B << C) for any shift, we can convert this to
9519 (A << C << B). This wins if A is a constant. Only try this if
9520 B is not a constant. */
9522 else if (GET_CODE (varop) == code
9523 && GET_CODE (XEXP (varop, 1)) != CONST_INT
9525 = simplify_binary_operation (code, mode,
9529 varop = gen_rtx_fmt_ee (code, mode, new, XEXP (varop, 1));
9536 /* Make this fit the case below. */
9537 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
9538 GEN_INT (GET_MODE_MASK (mode)));
9544 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9545 with C the size of VAROP - 1 and the shift is logical if
9546 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9547 we have an (le X 0) operation. If we have an arithmetic shift
9548 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9549 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9551 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
9552 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
9553 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9554 && (code == LSHIFTRT || code == ASHIFTRT)
9555 && count == (unsigned int)
9556 (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9557 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9560 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
9563 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9564 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9569 /* If we have (shift (logical)), move the logical to the outside
9570 to allow it to possibly combine with another logical and the
9571 shift to combine with another shift. This also canonicalizes to
9572 what a ZERO_EXTRACT looks like. Also, some machines have
9573 (and (shift)) insns. */
9575 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9576 /* We can't do this if we have (ashiftrt (xor)) and the
9577 constant has its sign bit set in shift_mode. */
9578 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
9579 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
9581 && (new = simplify_binary_operation (code, result_mode,
9583 GEN_INT (count))) != 0
9584 && GET_CODE (new) == CONST_INT
9585 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
9586 INTVAL (new), result_mode, &complement_p))
9588 varop = XEXP (varop, 0);
9592 /* If we can't do that, try to simplify the shift in each arm of the
9593 logical expression, make a new logical expression, and apply
9594 the inverse distributive law. This also can't be done
9595 for some (ashiftrt (xor)). */
9596 if (code != ASHIFTRT || GET_CODE (varop)!= XOR
9597 || 0 <= trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
9600 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9601 XEXP (varop, 0), count);
9602 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9603 XEXP (varop, 1), count);
9605 varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs);
9606 varop = apply_distributive_law (varop);
9613 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9614 says that the sign bit can be tested, FOO has mode MODE, C is
9615 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9616 that may be nonzero. */
9617 if (code == LSHIFTRT
9618 && XEXP (varop, 1) == const0_rtx
9619 && GET_MODE (XEXP (varop, 0)) == result_mode
9620 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9621 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9622 && ((STORE_FLAG_VALUE
9623 & ((HOST_WIDE_INT) 1
9624 < (GET_MODE_BITSIZE (result_mode) - 1))))
9625 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9626 && merge_outer_ops (&outer_op, &outer_const, XOR,
9627 (HOST_WIDE_INT) 1, result_mode,
9630 varop = XEXP (varop, 0);
9637 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9638 than the number of bits in the mode is equivalent to A. */
9639 if (code == LSHIFTRT
9640 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9641 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9643 varop = XEXP (varop, 0);
9648 /* NEG commutes with ASHIFT since it is multiplication. Move the
9649 NEG outside to allow shifts to combine. */
9651 && merge_outer_ops (&outer_op, &outer_const, NEG,
9652 (HOST_WIDE_INT) 0, result_mode,
9655 varop = XEXP (varop, 0);
9661 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9662 is one less than the number of bits in the mode is
9663 equivalent to (xor A 1). */
9664 if (code == LSHIFTRT
9665 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9666 && XEXP (varop, 1) == constm1_rtx
9667 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9668 && merge_outer_ops (&outer_op, &outer_const, XOR,
9669 (HOST_WIDE_INT) 1, result_mode,
9673 varop = XEXP (varop, 0);
9677 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9678 that might be nonzero in BAR are those being shifted out and those
9679 bits are known zero in FOO, we can replace the PLUS with FOO.
9680 Similarly in the other operand order. This code occurs when
9681 we are computing the size of a variable-size array. */
9683 if ((code == ASHIFTRT || code == LSHIFTRT)
9684 && count < HOST_BITS_PER_WIDE_INT
9685 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9686 && (nonzero_bits (XEXP (varop, 1), result_mode)
9687 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9689 varop = XEXP (varop, 0);
9692 else if ((code == ASHIFTRT || code == LSHIFTRT)
9693 && count < HOST_BITS_PER_WIDE_INT
9694 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9695 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9697 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9698 & nonzero_bits (XEXP (varop, 1),
9701 varop = XEXP (varop, 1);
9705 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9707 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9708 && (new = simplify_binary_operation (ASHIFT, result_mode,
9710 GEN_INT (count))) != 0
9711 && GET_CODE (new) == CONST_INT
9712 && merge_outer_ops (&outer_op, &outer_const, PLUS,
9713 INTVAL (new), result_mode, &complement_p))
9715 varop = XEXP (varop, 0);
9721 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9722 with C the size of VAROP - 1 and the shift is logical if
9723 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9724 we have a (gt X 0) operation. If the shift is arithmetic with
9725 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9726 we have a (neg (gt X 0)) operation. */
9728 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9729 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9730 && count == (unsigned int)
9731 (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9732 && (code == LSHIFTRT || code == ASHIFTRT)
9733 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9734 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (varop, 0), 1))
9736 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9739 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9742 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9743 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9750 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9751 if the truncate does not affect the value. */
9752 if (code == LSHIFTRT
9753 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9754 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9755 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9756 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9757 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9759 rtx varop_inner = XEXP (varop, 0);
9762 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9763 XEXP (varop_inner, 0),
9765 (count + INTVAL (XEXP (varop_inner, 1))));
9766 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9779 /* We need to determine what mode to do the shift in. If the shift is
9780 a right shift or ROTATE, we must always do it in the mode it was
9781 originally done in. Otherwise, we can do it in MODE, the widest mode
9782 encountered. The code we care about is that of the shift that will
9783 actually be done, not the shift that was originally requested. */
9785 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9786 ? result_mode : mode);
9788 /* We have now finished analyzing the shift. The result should be
9789 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9790 OUTER_OP is non-NIL, it is an operation that needs to be applied
9791 to the result of the shift. OUTER_CONST is the relevant constant,
9792 but we must turn off all bits turned off in the shift.
9794 If we were passed a value for X, see if we can use any pieces of
9795 it. If not, make new rtx. */
9797 if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
9798 && GET_CODE (XEXP (x, 1)) == CONST_INT
9799 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) == count)
9800 const_rtx = XEXP (x, 1);
9802 const_rtx = GEN_INT (count);
9804 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
9805 && GET_MODE (XEXP (x, 0)) == shift_mode
9806 && SUBREG_REG (XEXP (x, 0)) == varop)
9807 varop = XEXP (x, 0);
9808 else if (GET_MODE (varop) != shift_mode)
9809 varop = gen_lowpart (shift_mode, varop);
9811 /* If we can't make the SUBREG, try to return what we were given. */
9812 if (GET_CODE (varop) == CLOBBER)
9813 return x ? x : varop;
9815 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
9819 x = gen_rtx_fmt_ee (code, shift_mode, varop, const_rtx);
9821 /* If we have an outer operation and we just made a shift, it is
9822 possible that we could have simplified the shift were it not
9823 for the outer operation. So try to do the simplification
9826 if (outer_op != NIL && GET_CODE (x) == code
9827 && GET_CODE (XEXP (x, 1)) == CONST_INT)
9828 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
9829 INTVAL (XEXP (x, 1)));
9831 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9832 turn off all the bits that the shift would have turned off. */
9833 if (orig_code == LSHIFTRT && result_mode != shift_mode)
9834 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9835 GET_MODE_MASK (result_mode) >> orig_count);
9837 /* Do the remainder of the processing in RESULT_MODE. */
9838 x = gen_lowpart (result_mode, x);
9840 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9843 x = simplify_gen_unary (NOT, result_mode, x, result_mode);
9845 if (outer_op != NIL)
9847 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9848 outer_const = trunc_int_for_mode (outer_const, result_mode);
9850 if (outer_op == AND)
9851 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9852 else if (outer_op == SET)
9853 /* This means that we have determined that the result is
9854 equivalent to a constant. This should be rare. */
9855 x = GEN_INT (outer_const);
9856 else if (GET_RTX_CLASS (outer_op) == '1')
9857 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
9859 x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
9865 /* Like recog, but we receive the address of a pointer to a new pattern.
9866 We try to match the rtx that the pointer points to.
9867 If that fails, we may try to modify or replace the pattern,
9868 storing the replacement into the same pointer object.
9870 Modifications include deletion or addition of CLOBBERs.
9872 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9873 the CLOBBERs are placed.
9875 The value is the final insn code from the pattern ultimately matched,
9879 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
9882 int insn_code_number;
9883 int num_clobbers_to_add = 0;
9886 rtx old_notes, old_pat;
9888 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9889 we use to indicate that something didn't match. If we find such a
9890 thing, force rejection. */
9891 if (GET_CODE (pat) == PARALLEL)
9892 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9893 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9894 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9897 old_pat = PATTERN (insn);
9898 old_notes = REG_NOTES (insn);
9899 PATTERN (insn) = pat;
9900 REG_NOTES (insn) = 0;
9902 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9904 /* If it isn't, there is the possibility that we previously had an insn
9905 that clobbered some register as a side effect, but the combined
9906 insn doesn't need to do that. So try once more without the clobbers
9907 unless this represents an ASM insn. */
9909 if (insn_code_number < 0 && ! check_asm_operands (pat)
9910 && GET_CODE (pat) == PARALLEL)
9914 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9915 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9918 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9922 SUBST_INT (XVECLEN (pat, 0), pos);
9925 pat = XVECEXP (pat, 0, 0);
9927 PATTERN (insn) = pat;
9928 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9930 PATTERN (insn) = old_pat;
9931 REG_NOTES (insn) = old_notes;
9933 /* Recognize all noop sets, these will be killed by followup pass. */
9934 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
9935 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
9937 /* If we had any clobbers to add, make a new pattern than contains
9938 them. Then check to make sure that all of them are dead. */
9939 if (num_clobbers_to_add)
9941 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9942 rtvec_alloc (GET_CODE (pat) == PARALLEL
9944 + num_clobbers_to_add)
9945 : num_clobbers_to_add + 1));
9947 if (GET_CODE (pat) == PARALLEL)
9948 for (i = 0; i < XVECLEN (pat, 0); i++)
9949 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9951 XVECEXP (newpat, 0, 0) = pat;
9953 add_clobbers (newpat, insn_code_number);
9955 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9956 i < XVECLEN (newpat, 0); i++)
9958 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
9959 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9961 notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9962 XEXP (XVECEXP (newpat, 0, i), 0), notes);
9970 return insn_code_number;
9973 /* Like gen_lowpart_general but for use by combine. In combine it
9974 is not possible to create any new pseudoregs. However, it is
9975 safe to create invalid memory addresses, because combine will
9976 try to recognize them and all they will do is make the combine
9979 If for some reason this cannot do its job, an rtx
9980 (clobber (const_int 0)) is returned.
9981 An insn containing that will not be recognized. */
9984 gen_lowpart_for_combine (enum machine_mode mode, rtx x)
9988 if (GET_MODE (x) == mode)
9991 /* Return identity if this is a CONST or symbolic
9994 && (GET_CODE (x) == CONST
9995 || GET_CODE (x) == SYMBOL_REF
9996 || GET_CODE (x) == LABEL_REF))
9999 /* We can only support MODE being wider than a word if X is a
10000 constant integer or has a mode the same size. */
10002 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
10003 && ! ((GET_MODE (x) == VOIDmode
10004 && (GET_CODE (x) == CONST_INT
10005 || GET_CODE (x) == CONST_DOUBLE))
10006 || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
10007 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
10009 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10010 won't know what to do. So we will strip off the SUBREG here and
10011 process normally. */
10012 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
10014 x = SUBREG_REG (x);
10015 if (GET_MODE (x) == mode)
10019 result = gen_lowpart_common (mode, x);
10020 #ifdef CANNOT_CHANGE_MODE_CLASS
10022 && GET_CODE (result) == SUBREG
10023 && GET_CODE (SUBREG_REG (result)) == REG
10024 && REGNO (SUBREG_REG (result)) >= FIRST_PSEUDO_REGISTER)
10025 bitmap_set_bit (&subregs_of_mode, REGNO (SUBREG_REG (result))
10027 + GET_MODE (result));
10033 if (GET_CODE (x) == MEM)
10037 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10039 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
10040 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
10042 /* If we want to refer to something bigger than the original memref,
10043 generate a perverse subreg instead. That will force a reload
10044 of the original memref X. */
10045 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
10046 return gen_rtx_SUBREG (mode, x, 0);
10048 if (WORDS_BIG_ENDIAN)
10049 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
10050 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
10052 if (BYTES_BIG_ENDIAN)
10054 /* Adjust the address so that the address-after-the-data is
10056 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
10057 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
10060 return adjust_address_nv (x, mode, offset);
10063 /* If X is a comparison operator, rewrite it in a new mode. This
10064 probably won't match, but may allow further simplifications. */
10065 else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
10066 return gen_rtx_fmt_ee (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
10068 /* If we couldn't simplify X any other way, just enclose it in a
10069 SUBREG. Normally, this SUBREG won't match, but some patterns may
10070 include an explicit SUBREG or we may simplify it further in combine. */
10075 enum machine_mode sub_mode = GET_MODE (x);
10077 offset = subreg_lowpart_offset (mode, sub_mode);
10078 if (sub_mode == VOIDmode)
10080 sub_mode = int_mode_for_mode (mode);
10081 x = gen_lowpart_common (sub_mode, x);
10083 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
10085 res = simplify_gen_subreg (mode, x, sub_mode, offset);
10088 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
10092 /* These routines make binary and unary operations by first seeing if they
10093 fold; if not, a new expression is allocated. */
10096 gen_binary (enum rtx_code code, enum machine_mode mode, rtx op0, rtx op1)
10101 if (GET_CODE (op0) == CLOBBER)
10103 else if (GET_CODE (op1) == CLOBBER)
10106 if (GET_RTX_CLASS (code) == 'c'
10107 && swap_commutative_operands_p (op0, op1))
10108 tem = op0, op0 = op1, op1 = tem;
10110 if (GET_RTX_CLASS (code) == '<')
10112 enum machine_mode op_mode = GET_MODE (op0);
10114 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
10115 just (REL_OP X Y). */
10116 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
10118 op1 = XEXP (op0, 1);
10119 op0 = XEXP (op0, 0);
10120 op_mode = GET_MODE (op0);
10123 if (op_mode == VOIDmode)
10124 op_mode = GET_MODE (op1);
10125 result = simplify_relational_operation (code, op_mode, op0, op1);
10128 result = simplify_binary_operation (code, mode, op0, op1);
10133 /* Put complex operands first and constants second. */
10134 if (GET_RTX_CLASS (code) == 'c'
10135 && swap_commutative_operands_p (op0, op1))
10136 return gen_rtx_fmt_ee (code, mode, op1, op0);
10138 /* If we are turning off bits already known off in OP0, we need not do
10140 else if (code == AND && GET_CODE (op1) == CONST_INT
10141 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
10142 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
10145 return gen_rtx_fmt_ee (code, mode, op0, op1);
10148 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10149 comparison code that will be tested.
10151 The result is a possibly different comparison code to use. *POP0 and
10152 *POP1 may be updated.
10154 It is possible that we might detect that a comparison is either always
10155 true or always false. However, we do not perform general constant
10156 folding in combine, so this knowledge isn't useful. Such tautologies
10157 should have been detected earlier. Hence we ignore all such cases. */
10159 static enum rtx_code
10160 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
10166 enum machine_mode mode, tmode;
10168 /* Try a few ways of applying the same transformation to both operands. */
10171 #ifndef WORD_REGISTER_OPERATIONS
10172 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10173 so check specially. */
10174 if (code != GTU && code != GEU && code != LTU && code != LEU
10175 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
10176 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10177 && GET_CODE (XEXP (op1, 0)) == ASHIFT
10178 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
10179 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
10180 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
10181 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
10182 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10183 && XEXP (op0, 1) == XEXP (op1, 1)
10184 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10185 && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
10186 && (INTVAL (XEXP (op0, 1))
10187 == (GET_MODE_BITSIZE (GET_MODE (op0))
10188 - (GET_MODE_BITSIZE
10189 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
10191 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
10192 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
10196 /* If both operands are the same constant shift, see if we can ignore the
10197 shift. We can if the shift is a rotate or if the bits shifted out of
10198 this shift are known to be zero for both inputs and if the type of
10199 comparison is compatible with the shift. */
10200 if (GET_CODE (op0) == GET_CODE (op1)
10201 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10202 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
10203 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
10204 && (code != GT && code != LT && code != GE && code != LE))
10205 || (GET_CODE (op0) == ASHIFTRT
10206 && (code != GTU && code != LTU
10207 && code != GEU && code != LEU)))
10208 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10209 && INTVAL (XEXP (op0, 1)) >= 0
10210 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10211 && XEXP (op0, 1) == XEXP (op1, 1))
10213 enum machine_mode mode = GET_MODE (op0);
10214 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10215 int shift_count = INTVAL (XEXP (op0, 1));
10217 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
10218 mask &= (mask >> shift_count) << shift_count;
10219 else if (GET_CODE (op0) == ASHIFT)
10220 mask = (mask & (mask << shift_count)) >> shift_count;
10222 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
10223 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
10224 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
10229 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10230 SUBREGs are of the same mode, and, in both cases, the AND would
10231 be redundant if the comparison was done in the narrower mode,
10232 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10233 and the operand's possibly nonzero bits are 0xffffff01; in that case
10234 if we only care about QImode, we don't need the AND). This case
10235 occurs if the output mode of an scc insn is not SImode and
10236 STORE_FLAG_VALUE == 1 (e.g., the 386).
10238 Similarly, check for a case where the AND's are ZERO_EXTEND
10239 operations from some narrower mode even though a SUBREG is not
10242 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
10243 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10244 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
10246 rtx inner_op0 = XEXP (op0, 0);
10247 rtx inner_op1 = XEXP (op1, 0);
10248 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
10249 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
10252 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
10253 && (GET_MODE_SIZE (GET_MODE (inner_op0))
10254 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
10255 && (GET_MODE (SUBREG_REG (inner_op0))
10256 == GET_MODE (SUBREG_REG (inner_op1)))
10257 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
10258 <= HOST_BITS_PER_WIDE_INT)
10259 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
10260 GET_MODE (SUBREG_REG (inner_op0)))))
10261 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
10262 GET_MODE (SUBREG_REG (inner_op1))))))
10264 op0 = SUBREG_REG (inner_op0);
10265 op1 = SUBREG_REG (inner_op1);
10267 /* The resulting comparison is always unsigned since we masked
10268 off the original sign bit. */
10269 code = unsigned_condition (code);
10275 for (tmode = GET_CLASS_NARROWEST_MODE
10276 (GET_MODE_CLASS (GET_MODE (op0)));
10277 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
10278 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
10280 op0 = gen_lowpart (tmode, inner_op0);
10281 op1 = gen_lowpart (tmode, inner_op1);
10282 code = unsigned_condition (code);
10291 /* If both operands are NOT, we can strip off the outer operation
10292 and adjust the comparison code for swapped operands; similarly for
10293 NEG, except that this must be an equality comparison. */
10294 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
10295 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
10296 && (code == EQ || code == NE)))
10297 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
10303 /* If the first operand is a constant, swap the operands and adjust the
10304 comparison code appropriately, but don't do this if the second operand
10305 is already a constant integer. */
10306 if (swap_commutative_operands_p (op0, op1))
10308 tem = op0, op0 = op1, op1 = tem;
10309 code = swap_condition (code);
10312 /* We now enter a loop during which we will try to simplify the comparison.
10313 For the most part, we only are concerned with comparisons with zero,
10314 but some things may really be comparisons with zero but not start
10315 out looking that way. */
10317 while (GET_CODE (op1) == CONST_INT)
10319 enum machine_mode mode = GET_MODE (op0);
10320 unsigned int mode_width = GET_MODE_BITSIZE (mode);
10321 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10322 int equality_comparison_p;
10323 int sign_bit_comparison_p;
10324 int unsigned_comparison_p;
10325 HOST_WIDE_INT const_op;
10327 /* We only want to handle integral modes. This catches VOIDmode,
10328 CCmode, and the floating-point modes. An exception is that we
10329 can handle VOIDmode if OP0 is a COMPARE or a comparison
10332 if (GET_MODE_CLASS (mode) != MODE_INT
10333 && ! (mode == VOIDmode
10334 && (GET_CODE (op0) == COMPARE
10335 || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
10338 /* Get the constant we are comparing against and turn off all bits
10339 not on in our mode. */
10340 const_op = INTVAL (op1);
10341 if (mode != VOIDmode)
10342 const_op = trunc_int_for_mode (const_op, mode);
10343 op1 = GEN_INT (const_op);
10345 /* If we are comparing against a constant power of two and the value
10346 being compared can only have that single bit nonzero (e.g., it was
10347 `and'ed with that bit), we can replace this with a comparison
10350 && (code == EQ || code == NE || code == GE || code == GEU
10351 || code == LT || code == LTU)
10352 && mode_width <= HOST_BITS_PER_WIDE_INT
10353 && exact_log2 (const_op) >= 0
10354 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
10356 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10357 op1 = const0_rtx, const_op = 0;
10360 /* Similarly, if we are comparing a value known to be either -1 or
10361 0 with -1, change it to the opposite comparison against zero. */
10364 && (code == EQ || code == NE || code == GT || code == LE
10365 || code == GEU || code == LTU)
10366 && num_sign_bit_copies (op0, mode) == mode_width)
10368 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10369 op1 = const0_rtx, const_op = 0;
10372 /* Do some canonicalizations based on the comparison code. We prefer
10373 comparisons against zero and then prefer equality comparisons.
10374 If we can reduce the size of a constant, we will do that too. */
10379 /* < C is equivalent to <= (C - 1) */
10383 op1 = GEN_INT (const_op);
10385 /* ... fall through to LE case below. */
10391 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10395 op1 = GEN_INT (const_op);
10399 /* If we are doing a <= 0 comparison on a value known to have
10400 a zero sign bit, we can replace this with == 0. */
10401 else if (const_op == 0
10402 && mode_width <= HOST_BITS_PER_WIDE_INT
10403 && (nonzero_bits (op0, mode)
10404 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10409 /* >= C is equivalent to > (C - 1). */
10413 op1 = GEN_INT (const_op);
10415 /* ... fall through to GT below. */
10421 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10425 op1 = GEN_INT (const_op);
10429 /* If we are doing a > 0 comparison on a value known to have
10430 a zero sign bit, we can replace this with != 0. */
10431 else if (const_op == 0
10432 && mode_width <= HOST_BITS_PER_WIDE_INT
10433 && (nonzero_bits (op0, mode)
10434 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10439 /* < C is equivalent to <= (C - 1). */
10443 op1 = GEN_INT (const_op);
10445 /* ... fall through ... */
10448 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10449 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10450 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10452 const_op = 0, op1 = const0_rtx;
10460 /* unsigned <= 0 is equivalent to == 0 */
10464 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10465 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10466 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10468 const_op = 0, op1 = const0_rtx;
10474 /* >= C is equivalent to < (C - 1). */
10478 op1 = GEN_INT (const_op);
10480 /* ... fall through ... */
10483 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10484 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10485 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10487 const_op = 0, op1 = const0_rtx;
10495 /* unsigned > 0 is equivalent to != 0 */
10499 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10500 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10501 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10503 const_op = 0, op1 = const0_rtx;
10512 /* Compute some predicates to simplify code below. */
10514 equality_comparison_p = (code == EQ || code == NE);
10515 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
10516 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
10519 /* If this is a sign bit comparison and we can do arithmetic in
10520 MODE, say that we will only be needing the sign bit of OP0. */
10521 if (sign_bit_comparison_p
10522 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10523 op0 = force_to_mode (op0, mode,
10525 << (GET_MODE_BITSIZE (mode) - 1)),
10528 /* Now try cases based on the opcode of OP0. If none of the cases
10529 does a "continue", we exit this loop immediately after the
10532 switch (GET_CODE (op0))
10535 /* If we are extracting a single bit from a variable position in
10536 a constant that has only a single bit set and are comparing it
10537 with zero, we can convert this into an equality comparison
10538 between the position and the location of the single bit. */
10539 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
10540 have already reduced the shift count modulo the word size. */
10541 if (!SHIFT_COUNT_TRUNCATED
10542 && GET_CODE (XEXP (op0, 0)) == CONST_INT
10543 && XEXP (op0, 1) == const1_rtx
10544 && equality_comparison_p && const_op == 0
10545 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
10547 if (BITS_BIG_ENDIAN)
10549 enum machine_mode new_mode
10550 = mode_for_extraction (EP_extzv, 1);
10551 if (new_mode == MAX_MACHINE_MODE)
10552 i = BITS_PER_WORD - 1 - i;
10556 i = (GET_MODE_BITSIZE (mode) - 1 - i);
10560 op0 = XEXP (op0, 2);
10564 /* Result is nonzero iff shift count is equal to I. */
10565 code = reverse_condition (code);
10569 /* ... fall through ... */
10572 tem = expand_compound_operation (op0);
10581 /* If testing for equality, we can take the NOT of the constant. */
10582 if (equality_comparison_p
10583 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
10585 op0 = XEXP (op0, 0);
10590 /* If just looking at the sign bit, reverse the sense of the
10592 if (sign_bit_comparison_p)
10594 op0 = XEXP (op0, 0);
10595 code = (code == GE ? LT : GE);
10601 /* If testing for equality, we can take the NEG of the constant. */
10602 if (equality_comparison_p
10603 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
10605 op0 = XEXP (op0, 0);
10610 /* The remaining cases only apply to comparisons with zero. */
10614 /* When X is ABS or is known positive,
10615 (neg X) is < 0 if and only if X != 0. */
10617 if (sign_bit_comparison_p
10618 && (GET_CODE (XEXP (op0, 0)) == ABS
10619 || (mode_width <= HOST_BITS_PER_WIDE_INT
10620 && (nonzero_bits (XEXP (op0, 0), mode)
10621 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
10623 op0 = XEXP (op0, 0);
10624 code = (code == LT ? NE : EQ);
10628 /* If we have NEG of something whose two high-order bits are the
10629 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10630 if (num_sign_bit_copies (op0, mode) >= 2)
10632 op0 = XEXP (op0, 0);
10633 code = swap_condition (code);
10639 /* If we are testing equality and our count is a constant, we
10640 can perform the inverse operation on our RHS. */
10641 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10642 && (tem = simplify_binary_operation (ROTATERT, mode,
10643 op1, XEXP (op0, 1))) != 0)
10645 op0 = XEXP (op0, 0);
10650 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10651 a particular bit. Convert it to an AND of a constant of that
10652 bit. This will be converted into a ZERO_EXTRACT. */
10653 if (const_op == 0 && sign_bit_comparison_p
10654 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10655 && mode_width <= HOST_BITS_PER_WIDE_INT)
10657 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10660 - INTVAL (XEXP (op0, 1)))));
10661 code = (code == LT ? NE : EQ);
10665 /* Fall through. */
10668 /* ABS is ignorable inside an equality comparison with zero. */
10669 if (const_op == 0 && equality_comparison_p)
10671 op0 = XEXP (op0, 0);
10677 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10678 to (compare FOO CONST) if CONST fits in FOO's mode and we
10679 are either testing inequality or have an unsigned comparison
10680 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10681 if (! unsigned_comparison_p
10682 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10683 <= HOST_BITS_PER_WIDE_INT)
10684 && ((unsigned HOST_WIDE_INT) const_op
10685 < (((unsigned HOST_WIDE_INT) 1
10686 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
10688 op0 = XEXP (op0, 0);
10694 /* Check for the case where we are comparing A - C1 with C2,
10695 both constants are smaller than 1/2 the maximum positive
10696 value in MODE, and the comparison is equality or unsigned.
10697 In that case, if A is either zero-extended to MODE or has
10698 sufficient sign bits so that the high-order bit in MODE
10699 is a copy of the sign in the inner mode, we can prove that it is
10700 safe to do the operation in the wider mode. This simplifies
10701 many range checks. */
10703 if (mode_width <= HOST_BITS_PER_WIDE_INT
10704 && subreg_lowpart_p (op0)
10705 && GET_CODE (SUBREG_REG (op0)) == PLUS
10706 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
10707 && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
10708 && (-INTVAL (XEXP (SUBREG_REG (op0), 1))
10709 < (HOST_WIDE_INT) (GET_MODE_MASK (mode) / 2))
10710 && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2
10711 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0),
10712 GET_MODE (SUBREG_REG (op0)))
10713 & ~GET_MODE_MASK (mode))
10714 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
10715 GET_MODE (SUBREG_REG (op0)))
10717 (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10718 - GET_MODE_BITSIZE (mode)))))
10720 op0 = SUBREG_REG (op0);
10724 /* If the inner mode is narrower and we are extracting the low part,
10725 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10726 if (subreg_lowpart_p (op0)
10727 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10728 /* Fall through */ ;
10732 /* ... fall through ... */
10735 if ((unsigned_comparison_p || equality_comparison_p)
10736 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10737 <= HOST_BITS_PER_WIDE_INT)
10738 && ((unsigned HOST_WIDE_INT) const_op
10739 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
10741 op0 = XEXP (op0, 0);
10747 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10748 this for equality comparisons due to pathological cases involving
10750 if (equality_comparison_p
10751 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10752 op1, XEXP (op0, 1))))
10754 op0 = XEXP (op0, 0);
10759 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10760 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10761 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10763 op0 = XEXP (XEXP (op0, 0), 0);
10764 code = (code == LT ? EQ : NE);
10770 /* We used to optimize signed comparisons against zero, but that
10771 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10772 arrive here as equality comparisons, or (GEU, LTU) are
10773 optimized away. No need to special-case them. */
10775 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10776 (eq B (minus A C)), whichever simplifies. We can only do
10777 this for equality comparisons due to pathological cases involving
10779 if (equality_comparison_p
10780 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10781 XEXP (op0, 1), op1)))
10783 op0 = XEXP (op0, 0);
10788 if (equality_comparison_p
10789 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10790 XEXP (op0, 0), op1)))
10792 op0 = XEXP (op0, 1);
10797 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10798 of bits in X minus 1, is one iff X > 0. */
10799 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10800 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10801 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1))
10803 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10805 op0 = XEXP (op0, 1);
10806 code = (code == GE ? LE : GT);
10812 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10813 if C is zero or B is a constant. */
10814 if (equality_comparison_p
10815 && 0 != (tem = simplify_binary_operation (XOR, mode,
10816 XEXP (op0, 1), op1)))
10818 op0 = XEXP (op0, 0);
10825 case UNEQ: case LTGT:
10826 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
10827 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
10828 case UNORDERED: case ORDERED:
10829 /* We can't do anything if OP0 is a condition code value, rather
10830 than an actual data value. */
10832 || CC0_P (XEXP (op0, 0))
10833 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10836 /* Get the two operands being compared. */
10837 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10838 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10840 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10842 /* Check for the cases where we simply want the result of the
10843 earlier test or the opposite of that result. */
10844 if (code == NE || code == EQ
10845 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10846 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10847 && (STORE_FLAG_VALUE
10848 & (((HOST_WIDE_INT) 1
10849 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10850 && (code == LT || code == GE)))
10852 enum rtx_code new_code;
10853 if (code == LT || code == NE)
10854 new_code = GET_CODE (op0);
10856 new_code = combine_reversed_comparison_code (op0);
10858 if (new_code != UNKNOWN)
10869 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10871 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10872 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10873 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10875 op0 = XEXP (op0, 1);
10876 code = (code == GE ? GT : LE);
10882 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10883 will be converted to a ZERO_EXTRACT later. */
10884 if (const_op == 0 && equality_comparison_p
10885 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10886 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10888 op0 = simplify_and_const_int
10889 (op0, mode, gen_rtx_LSHIFTRT (mode,
10891 XEXP (XEXP (op0, 0), 1)),
10892 (HOST_WIDE_INT) 1);
10896 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10897 zero and X is a comparison and C1 and C2 describe only bits set
10898 in STORE_FLAG_VALUE, we can compare with X. */
10899 if (const_op == 0 && equality_comparison_p
10900 && mode_width <= HOST_BITS_PER_WIDE_INT
10901 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10902 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10903 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10904 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10905 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10907 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10908 << INTVAL (XEXP (XEXP (op0, 0), 1)));
10909 if ((~STORE_FLAG_VALUE & mask) == 0
10910 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
10911 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10912 && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
10914 op0 = XEXP (XEXP (op0, 0), 0);
10919 /* If we are doing an equality comparison of an AND of a bit equal
10920 to the sign bit, replace this with a LT or GE comparison of
10921 the underlying value. */
10922 if (equality_comparison_p
10924 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10925 && mode_width <= HOST_BITS_PER_WIDE_INT
10926 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10927 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10929 op0 = XEXP (op0, 0);
10930 code = (code == EQ ? GE : LT);
10934 /* If this AND operation is really a ZERO_EXTEND from a narrower
10935 mode, the constant fits within that mode, and this is either an
10936 equality or unsigned comparison, try to do this comparison in
10937 the narrower mode. */
10938 if ((equality_comparison_p || unsigned_comparison_p)
10939 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10940 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10941 & GET_MODE_MASK (mode))
10943 && const_op >> i == 0
10944 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
10946 op0 = gen_lowpart (tmode, XEXP (op0, 0));
10950 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
10951 fits in both M1 and M2 and the SUBREG is either paradoxical
10952 or represents the low part, permute the SUBREG and the AND
10954 if (GET_CODE (XEXP (op0, 0)) == SUBREG)
10956 unsigned HOST_WIDE_INT c1;
10957 tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
10958 /* Require an integral mode, to avoid creating something like
10960 if (SCALAR_INT_MODE_P (tmode)
10961 /* It is unsafe to commute the AND into the SUBREG if the
10962 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
10963 not defined. As originally written the upper bits
10964 have a defined value due to the AND operation.
10965 However, if we commute the AND inside the SUBREG then
10966 they no longer have defined values and the meaning of
10967 the code has been changed. */
10969 #ifdef WORD_REGISTER_OPERATIONS
10970 || (mode_width > GET_MODE_BITSIZE (tmode)
10971 && mode_width <= BITS_PER_WORD)
10973 || (mode_width <= GET_MODE_BITSIZE (tmode)
10974 && subreg_lowpart_p (XEXP (op0, 0))))
10975 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10976 && mode_width <= HOST_BITS_PER_WIDE_INT
10977 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
10978 && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
10979 && (c1 & ~GET_MODE_MASK (tmode)) == 0
10981 && c1 != GET_MODE_MASK (tmode))
10983 op0 = gen_binary (AND, tmode,
10984 SUBREG_REG (XEXP (op0, 0)),
10985 gen_int_mode (c1, tmode));
10986 op0 = gen_lowpart (mode, op0);
10991 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
10992 if (const_op == 0 && equality_comparison_p
10993 && XEXP (op0, 1) == const1_rtx
10994 && GET_CODE (XEXP (op0, 0)) == NOT)
10996 op0 = simplify_and_const_int
10997 (NULL_RTX, mode, XEXP (XEXP (op0, 0), 0), (HOST_WIDE_INT) 1);
10998 code = (code == NE ? EQ : NE);
11002 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11003 (eq (and (lshiftrt X) 1) 0).
11004 Also handle the case where (not X) is expressed using xor. */
11005 if (const_op == 0 && equality_comparison_p
11006 && XEXP (op0, 1) == const1_rtx
11007 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
11009 rtx shift_op = XEXP (XEXP (op0, 0), 0);
11010 rtx shift_count = XEXP (XEXP (op0, 0), 1);
11012 if (GET_CODE (shift_op) == NOT
11013 || (GET_CODE (shift_op) == XOR
11014 && GET_CODE (XEXP (shift_op, 1)) == CONST_INT
11015 && GET_CODE (shift_count) == CONST_INT
11016 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
11017 && (INTVAL (XEXP (shift_op, 1))
11018 == (HOST_WIDE_INT) 1 << INTVAL (shift_count))))
11020 op0 = simplify_and_const_int
11022 gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count),
11023 (HOST_WIDE_INT) 1);
11024 code = (code == NE ? EQ : NE);
11031 /* If we have (compare (ashift FOO N) (const_int C)) and
11032 the high order N bits of FOO (N+1 if an inequality comparison)
11033 are known to be zero, we can do this by comparing FOO with C
11034 shifted right N bits so long as the low-order N bits of C are
11036 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
11037 && INTVAL (XEXP (op0, 1)) >= 0
11038 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
11039 < HOST_BITS_PER_WIDE_INT)
11041 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
11042 && mode_width <= HOST_BITS_PER_WIDE_INT
11043 && (nonzero_bits (XEXP (op0, 0), mode)
11044 & ~(mask >> (INTVAL (XEXP (op0, 1))
11045 + ! equality_comparison_p))) == 0)
11047 /* We must perform a logical shift, not an arithmetic one,
11048 as we want the top N bits of C to be zero. */
11049 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
11051 temp >>= INTVAL (XEXP (op0, 1));
11052 op1 = gen_int_mode (temp, mode);
11053 op0 = XEXP (op0, 0);
11057 /* If we are doing a sign bit comparison, it means we are testing
11058 a particular bit. Convert it to the appropriate AND. */
11059 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
11060 && mode_width <= HOST_BITS_PER_WIDE_INT)
11062 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11065 - INTVAL (XEXP (op0, 1)))));
11066 code = (code == LT ? NE : EQ);
11070 /* If this an equality comparison with zero and we are shifting
11071 the low bit to the sign bit, we can convert this to an AND of the
11073 if (const_op == 0 && equality_comparison_p
11074 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11075 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
11078 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11079 (HOST_WIDE_INT) 1);
11085 /* If this is an equality comparison with zero, we can do this
11086 as a logical shift, which might be much simpler. */
11087 if (equality_comparison_p && const_op == 0
11088 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
11090 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
11092 INTVAL (XEXP (op0, 1)));
11096 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11097 do the comparison in a narrower mode. */
11098 if (! unsigned_comparison_p
11099 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11100 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11101 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
11102 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11103 MODE_INT, 1)) != BLKmode
11104 && (((unsigned HOST_WIDE_INT) const_op
11105 + (GET_MODE_MASK (tmode) >> 1) + 1)
11106 <= GET_MODE_MASK (tmode)))
11108 op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
11112 /* Likewise if OP0 is a PLUS of a sign extension with a
11113 constant, which is usually represented with the PLUS
11114 between the shifts. */
11115 if (! unsigned_comparison_p
11116 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11117 && GET_CODE (XEXP (op0, 0)) == PLUS
11118 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
11119 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
11120 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
11121 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11122 MODE_INT, 1)) != BLKmode
11123 && (((unsigned HOST_WIDE_INT) const_op
11124 + (GET_MODE_MASK (tmode) >> 1) + 1)
11125 <= GET_MODE_MASK (tmode)))
11127 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
11128 rtx add_const = XEXP (XEXP (op0, 0), 1);
11129 rtx new_const = gen_binary (ASHIFTRT, GET_MODE (op0), add_const,
11132 op0 = gen_binary (PLUS, tmode,
11133 gen_lowpart (tmode, inner),
11138 /* ... fall through ... */
11140 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11141 the low order N bits of FOO are known to be zero, we can do this
11142 by comparing FOO with C shifted left N bits so long as no
11143 overflow occurs. */
11144 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
11145 && INTVAL (XEXP (op0, 1)) >= 0
11146 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11147 && mode_width <= HOST_BITS_PER_WIDE_INT
11148 && (nonzero_bits (XEXP (op0, 0), mode)
11149 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
11150 && (((unsigned HOST_WIDE_INT) const_op
11151 + (GET_CODE (op0) != LSHIFTRT
11152 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
11155 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
11157 /* If the shift was logical, then we must make the condition
11159 if (GET_CODE (op0) == LSHIFTRT)
11160 code = unsigned_condition (code);
11162 const_op <<= INTVAL (XEXP (op0, 1));
11163 op1 = GEN_INT (const_op);
11164 op0 = XEXP (op0, 0);
11168 /* If we are using this shift to extract just the sign bit, we
11169 can replace this with an LT or GE comparison. */
11171 && (equality_comparison_p || sign_bit_comparison_p)
11172 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11173 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
11176 op0 = XEXP (op0, 0);
11177 code = (code == NE || code == GT ? LT : GE);
11189 /* Now make any compound operations involved in this comparison. Then,
11190 check for an outmost SUBREG on OP0 that is not doing anything or is
11191 paradoxical. The latter transformation must only be performed when
11192 it is known that the "extra" bits will be the same in op0 and op1 or
11193 that they don't matter. There are three cases to consider:
11195 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11196 care bits and we can assume they have any convenient value. So
11197 making the transformation is safe.
11199 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11200 In this case the upper bits of op0 are undefined. We should not make
11201 the simplification in that case as we do not know the contents of
11204 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11205 NIL. In that case we know those bits are zeros or ones. We must
11206 also be sure that they are the same as the upper bits of op1.
11208 We can never remove a SUBREG for a non-equality comparison because
11209 the sign bit is in a different place in the underlying object. */
11211 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
11212 op1 = make_compound_operation (op1, SET);
11214 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
11215 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11216 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
11217 && (code == NE || code == EQ))
11219 if (GET_MODE_SIZE (GET_MODE (op0))
11220 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
11222 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
11224 if (GET_CODE (SUBREG_REG (op0)) == REG)
11226 op0 = SUBREG_REG (op0);
11227 op1 = gen_lowpart (GET_MODE (op0), op1);
11230 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
11231 <= HOST_BITS_PER_WIDE_INT)
11232 && (nonzero_bits (SUBREG_REG (op0),
11233 GET_MODE (SUBREG_REG (op0)))
11234 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11236 tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
11238 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
11239 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11240 op0 = SUBREG_REG (op0), op1 = tem;
11244 /* We now do the opposite procedure: Some machines don't have compare
11245 insns in all modes. If OP0's mode is an integer mode smaller than a
11246 word and we can't do a compare in that mode, see if there is a larger
11247 mode for which we can do the compare. There are a number of cases in
11248 which we can use the wider mode. */
11250 mode = GET_MODE (op0);
11251 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11252 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
11253 && ! have_insn_for (COMPARE, mode))
11254 for (tmode = GET_MODE_WIDER_MODE (mode);
11256 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
11257 tmode = GET_MODE_WIDER_MODE (tmode))
11258 if (have_insn_for (COMPARE, tmode))
11262 /* If the only nonzero bits in OP0 and OP1 are those in the
11263 narrower mode and this is an equality or unsigned comparison,
11264 we can use the wider mode. Similarly for sign-extended
11265 values, in which case it is true for all comparisons. */
11266 zero_extended = ((code == EQ || code == NE
11267 || code == GEU || code == GTU
11268 || code == LEU || code == LTU)
11269 && (nonzero_bits (op0, tmode)
11270 & ~GET_MODE_MASK (mode)) == 0
11271 && ((GET_CODE (op1) == CONST_INT
11272 || (nonzero_bits (op1, tmode)
11273 & ~GET_MODE_MASK (mode)) == 0)));
11276 || ((num_sign_bit_copies (op0, tmode)
11277 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11278 - GET_MODE_BITSIZE (mode)))
11279 && (num_sign_bit_copies (op1, tmode)
11280 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11281 - GET_MODE_BITSIZE (mode)))))
11283 /* If OP0 is an AND and we don't have an AND in MODE either,
11284 make a new AND in the proper mode. */
11285 if (GET_CODE (op0) == AND
11286 && !have_insn_for (AND, mode))
11287 op0 = gen_binary (AND, tmode,
11288 gen_lowpart (tmode,
11290 gen_lowpart (tmode,
11293 op0 = gen_lowpart (tmode, op0);
11294 if (zero_extended && GET_CODE (op1) == CONST_INT)
11295 op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode));
11296 op1 = gen_lowpart (tmode, op1);
11300 /* If this is a test for negative, we can make an explicit
11301 test of the sign bit. */
11303 if (op1 == const0_rtx && (code == LT || code == GE)
11304 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11306 op0 = gen_binary (AND, tmode,
11307 gen_lowpart (tmode, op0),
11308 GEN_INT ((HOST_WIDE_INT) 1
11309 << (GET_MODE_BITSIZE (mode) - 1)));
11310 code = (code == LT) ? NE : EQ;
11315 #ifdef CANONICALIZE_COMPARISON
11316 /* If this machine only supports a subset of valid comparisons, see if we
11317 can convert an unsupported one into a supported one. */
11318 CANONICALIZE_COMPARISON (code, op0, op1);
11327 /* Like jump.c' reversed_comparison_code, but use combine infrastructure for
11328 searching backward. */
11329 static enum rtx_code
11330 combine_reversed_comparison_code (rtx exp)
11332 enum rtx_code code1 = reversed_comparison_code (exp, NULL);
11335 if (code1 != UNKNOWN
11336 || GET_MODE_CLASS (GET_MODE (XEXP (exp, 0))) != MODE_CC)
11338 /* Otherwise try and find where the condition codes were last set and
11340 x = get_last_value (XEXP (exp, 0));
11341 if (!x || GET_CODE (x) != COMPARE)
11343 return reversed_comparison_code_parts (GET_CODE (exp),
11344 XEXP (x, 0), XEXP (x, 1), NULL);
11347 /* Return comparison with reversed code of EXP and operands OP0 and OP1.
11348 Return NULL_RTX in case we fail to do the reversal. */
11350 reversed_comparison (rtx exp, enum machine_mode mode, rtx op0, rtx op1)
11352 enum rtx_code reversed_code = combine_reversed_comparison_code (exp);
11353 if (reversed_code == UNKNOWN)
11356 return gen_binary (reversed_code, mode, op0, op1);
11359 /* Utility function for following routine. Called when X is part of a value
11360 being stored into reg_last_set_value. Sets reg_last_set_table_tick
11361 for each register mentioned. Similar to mention_regs in cse.c */
11364 update_table_tick (rtx x)
11366 enum rtx_code code = GET_CODE (x);
11367 const char *fmt = GET_RTX_FORMAT (code);
11372 unsigned int regno = REGNO (x);
11373 unsigned int endregno
11374 = regno + (regno < FIRST_PSEUDO_REGISTER
11375 ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
11378 for (r = regno; r < endregno; r++)
11379 reg_last_set_table_tick[r] = label_tick;
11384 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11385 /* Note that we can't have an "E" in values stored; see
11386 get_last_value_validate. */
11389 /* Check for identical subexpressions. If x contains
11390 identical subexpression we only have to traverse one of
11393 && (GET_RTX_CLASS (code) == '2'
11394 || GET_RTX_CLASS (code) == 'c'))
11396 /* Note that at this point x1 has already been
11398 rtx x0 = XEXP (x, 0);
11399 rtx x1 = XEXP (x, 1);
11401 /* If x0 and x1 are identical then there is no need to
11406 /* If x0 is identical to a subexpression of x1 then while
11407 processing x1, x0 has already been processed. Thus we
11408 are done with x. */
11409 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
11410 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
11411 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11414 /* If x1 is identical to a subexpression of x0 then we
11415 still have to process the rest of x0. */
11416 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
11417 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
11418 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11420 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
11425 update_table_tick (XEXP (x, i));
11429 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11430 are saying that the register is clobbered and we no longer know its
11431 value. If INSN is zero, don't update reg_last_set; this is only permitted
11432 with VALUE also zero and is used to invalidate the register. */
11435 record_value_for_reg (rtx reg, rtx insn, rtx value)
11437 unsigned int regno = REGNO (reg);
11438 unsigned int endregno
11439 = regno + (regno < FIRST_PSEUDO_REGISTER
11440 ? hard_regno_nregs[regno][GET_MODE (reg)] : 1);
11443 /* If VALUE contains REG and we have a previous value for REG, substitute
11444 the previous value. */
11445 if (value && insn && reg_overlap_mentioned_p (reg, value))
11449 /* Set things up so get_last_value is allowed to see anything set up to
11451 subst_low_cuid = INSN_CUID (insn);
11452 tem = get_last_value (reg);
11454 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11455 it isn't going to be useful and will take a lot of time to process,
11456 so just use the CLOBBER. */
11460 if ((GET_RTX_CLASS (GET_CODE (tem)) == '2'
11461 || GET_RTX_CLASS (GET_CODE (tem)) == 'c')
11462 && GET_CODE (XEXP (tem, 0)) == CLOBBER
11463 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
11464 tem = XEXP (tem, 0);
11466 value = replace_rtx (copy_rtx (value), reg, tem);
11470 /* For each register modified, show we don't know its value, that
11471 we don't know about its bitwise content, that its value has been
11472 updated, and that we don't know the location of the death of the
11474 for (i = regno; i < endregno; i++)
11477 reg_last_set[i] = insn;
11479 reg_last_set_value[i] = 0;
11480 reg_last_set_mode[i] = 0;
11481 reg_last_set_nonzero_bits[i] = 0;
11482 reg_last_set_sign_bit_copies[i] = 0;
11483 reg_last_death[i] = 0;
11486 /* Mark registers that are being referenced in this value. */
11488 update_table_tick (value);
11490 /* Now update the status of each register being set.
11491 If someone is using this register in this block, set this register
11492 to invalid since we will get confused between the two lives in this
11493 basic block. This makes using this register always invalid. In cse, we
11494 scan the table to invalidate all entries using this register, but this
11495 is too much work for us. */
11497 for (i = regno; i < endregno; i++)
11499 reg_last_set_label[i] = label_tick;
11500 if (value && reg_last_set_table_tick[i] == label_tick)
11501 reg_last_set_invalid[i] = 1;
11503 reg_last_set_invalid[i] = 0;
11506 /* The value being assigned might refer to X (like in "x++;"). In that
11507 case, we must replace it with (clobber (const_int 0)) to prevent
11509 if (value && ! get_last_value_validate (&value, insn,
11510 reg_last_set_label[regno], 0))
11512 value = copy_rtx (value);
11513 if (! get_last_value_validate (&value, insn,
11514 reg_last_set_label[regno], 1))
11518 /* For the main register being modified, update the value, the mode, the
11519 nonzero bits, and the number of sign bit copies. */
11521 reg_last_set_value[regno] = value;
11525 enum machine_mode mode = GET_MODE (reg);
11526 subst_low_cuid = INSN_CUID (insn);
11527 reg_last_set_mode[regno] = mode;
11528 if (GET_MODE_CLASS (mode) == MODE_INT
11529 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11530 mode = nonzero_bits_mode;
11531 reg_last_set_nonzero_bits[regno] = nonzero_bits (value, mode);
11532 reg_last_set_sign_bit_copies[regno]
11533 = num_sign_bit_copies (value, GET_MODE (reg));
11537 /* Called via note_stores from record_dead_and_set_regs to handle one
11538 SET or CLOBBER in an insn. DATA is the instruction in which the
11539 set is occurring. */
11542 record_dead_and_set_regs_1 (rtx dest, rtx setter, void *data)
11544 rtx record_dead_insn = (rtx) data;
11546 if (GET_CODE (dest) == SUBREG)
11547 dest = SUBREG_REG (dest);
11549 if (GET_CODE (dest) == REG)
11551 /* If we are setting the whole register, we know its value. Otherwise
11552 show that we don't know the value. We can handle SUBREG in
11554 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
11555 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
11556 else if (GET_CODE (setter) == SET
11557 && GET_CODE (SET_DEST (setter)) == SUBREG
11558 && SUBREG_REG (SET_DEST (setter)) == dest
11559 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
11560 && subreg_lowpart_p (SET_DEST (setter)))
11561 record_value_for_reg (dest, record_dead_insn,
11562 gen_lowpart (GET_MODE (dest),
11563 SET_SRC (setter)));
11565 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
11567 else if (GET_CODE (dest) == MEM
11568 /* Ignore pushes, they clobber nothing. */
11569 && ! push_operand (dest, GET_MODE (dest)))
11570 mem_last_set = INSN_CUID (record_dead_insn);
11573 /* Update the records of when each REG was most recently set or killed
11574 for the things done by INSN. This is the last thing done in processing
11575 INSN in the combiner loop.
11577 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
11578 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
11579 and also the similar information mem_last_set (which insn most recently
11580 modified memory) and last_call_cuid (which insn was the most recent
11581 subroutine call). */
11584 record_dead_and_set_regs (rtx insn)
11589 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11591 if (REG_NOTE_KIND (link) == REG_DEAD
11592 && GET_CODE (XEXP (link, 0)) == REG)
11594 unsigned int regno = REGNO (XEXP (link, 0));
11595 unsigned int endregno
11596 = regno + (regno < FIRST_PSEUDO_REGISTER
11597 ? hard_regno_nregs[regno][GET_MODE (XEXP (link, 0))]
11600 for (i = regno; i < endregno; i++)
11601 reg_last_death[i] = insn;
11603 else if (REG_NOTE_KIND (link) == REG_INC)
11604 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11607 if (GET_CODE (insn) == CALL_INSN)
11609 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11610 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
11612 reg_last_set_value[i] = 0;
11613 reg_last_set_mode[i] = 0;
11614 reg_last_set_nonzero_bits[i] = 0;
11615 reg_last_set_sign_bit_copies[i] = 0;
11616 reg_last_death[i] = 0;
11619 last_call_cuid = mem_last_set = INSN_CUID (insn);
11621 /* Don't bother recording what this insn does. It might set the
11622 return value register, but we can't combine into a call
11623 pattern anyway, so there's no point trying (and it may cause
11624 a crash, if e.g. we wind up asking for last_set_value of a
11625 SUBREG of the return value register). */
11629 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11632 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11633 register present in the SUBREG, so for each such SUBREG go back and
11634 adjust nonzero and sign bit information of the registers that are
11635 known to have some zero/sign bits set.
11637 This is needed because when combine blows the SUBREGs away, the
11638 information on zero/sign bits is lost and further combines can be
11639 missed because of that. */
11642 record_promoted_value (rtx insn, rtx subreg)
11645 unsigned int regno = REGNO (SUBREG_REG (subreg));
11646 enum machine_mode mode = GET_MODE (subreg);
11648 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11651 for (links = LOG_LINKS (insn); links;)
11653 insn = XEXP (links, 0);
11654 set = single_set (insn);
11656 if (! set || GET_CODE (SET_DEST (set)) != REG
11657 || REGNO (SET_DEST (set)) != regno
11658 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11660 links = XEXP (links, 1);
11664 if (reg_last_set[regno] == insn)
11666 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
11667 reg_last_set_nonzero_bits[regno] &= GET_MODE_MASK (mode);
11670 if (GET_CODE (SET_SRC (set)) == REG)
11672 regno = REGNO (SET_SRC (set));
11673 links = LOG_LINKS (insn);
11680 /* Scan X for promoted SUBREGs. For each one found,
11681 note what it implies to the registers used in it. */
11684 check_promoted_subreg (rtx insn, rtx x)
11686 if (GET_CODE (x) == SUBREG && SUBREG_PROMOTED_VAR_P (x)
11687 && GET_CODE (SUBREG_REG (x)) == REG)
11688 record_promoted_value (insn, x);
11691 const char *format = GET_RTX_FORMAT (GET_CODE (x));
11694 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11698 check_promoted_subreg (insn, XEXP (x, i));
11702 if (XVEC (x, i) != 0)
11703 for (j = 0; j < XVECLEN (x, i); j++)
11704 check_promoted_subreg (insn, XVECEXP (x, i, j));
11710 /* Utility routine for the following function. Verify that all the registers
11711 mentioned in *LOC are valid when *LOC was part of a value set when
11712 label_tick == TICK. Return 0 if some are not.
11714 If REPLACE is nonzero, replace the invalid reference with
11715 (clobber (const_int 0)) and return 1. This replacement is useful because
11716 we often can get useful information about the form of a value (e.g., if
11717 it was produced by a shift that always produces -1 or 0) even though
11718 we don't know exactly what registers it was produced from. */
11721 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
11724 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11725 int len = GET_RTX_LENGTH (GET_CODE (x));
11728 if (GET_CODE (x) == REG)
11730 unsigned int regno = REGNO (x);
11731 unsigned int endregno
11732 = regno + (regno < FIRST_PSEUDO_REGISTER
11733 ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
11736 for (j = regno; j < endregno; j++)
11737 if (reg_last_set_invalid[j]
11738 /* If this is a pseudo-register that was only set once and not
11739 live at the beginning of the function, it is always valid. */
11740 || (! (regno >= FIRST_PSEUDO_REGISTER
11741 && REG_N_SETS (regno) == 1
11742 && (! REGNO_REG_SET_P
11743 (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, regno)))
11744 && reg_last_set_label[j] > tick))
11747 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11753 /* If this is a memory reference, make sure that there were
11754 no stores after it that might have clobbered the value. We don't
11755 have alias info, so we assume any store invalidates it. */
11756 else if (GET_CODE (x) == MEM && ! RTX_UNCHANGING_P (x)
11757 && INSN_CUID (insn) <= mem_last_set)
11760 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11764 for (i = 0; i < len; i++)
11768 /* Check for identical subexpressions. If x contains
11769 identical subexpression we only have to traverse one of
11772 && (GET_RTX_CLASS (GET_CODE (x)) == '2'
11773 || GET_RTX_CLASS (GET_CODE (x)) == 'c'))
11775 /* Note that at this point x0 has already been checked
11776 and found valid. */
11777 rtx x0 = XEXP (x, 0);
11778 rtx x1 = XEXP (x, 1);
11780 /* If x0 and x1 are identical then x is also valid. */
11784 /* If x1 is identical to a subexpression of x0 then
11785 while checking x0, x1 has already been checked. Thus
11786 it is valid and so as x. */
11787 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
11788 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
11789 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11792 /* If x0 is identical to a subexpression of x1 then x is
11793 valid iff the rest of x1 is valid. */
11794 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
11795 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
11796 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11798 get_last_value_validate (&XEXP (x1,
11799 x0 == XEXP (x1, 0) ? 1 : 0),
11800 insn, tick, replace);
11803 if (get_last_value_validate (&XEXP (x, i), insn, tick,
11807 /* Don't bother with these. They shouldn't occur anyway. */
11808 else if (fmt[i] == 'E')
11812 /* If we haven't found a reason for it to be invalid, it is valid. */
11816 /* Get the last value assigned to X, if known. Some registers
11817 in the value may be replaced with (clobber (const_int 0)) if their value
11818 is known longer known reliably. */
11821 get_last_value (rtx x)
11823 unsigned int regno;
11826 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11827 then convert it to the desired mode. If this is a paradoxical SUBREG,
11828 we cannot predict what values the "extra" bits might have. */
11829 if (GET_CODE (x) == SUBREG
11830 && subreg_lowpart_p (x)
11831 && (GET_MODE_SIZE (GET_MODE (x))
11832 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11833 && (value = get_last_value (SUBREG_REG (x))) != 0)
11834 return gen_lowpart (GET_MODE (x), value);
11836 if (GET_CODE (x) != REG)
11840 value = reg_last_set_value[regno];
11842 /* If we don't have a value, or if it isn't for this basic block and
11843 it's either a hard register, set more than once, or it's a live
11844 at the beginning of the function, return 0.
11846 Because if it's not live at the beginning of the function then the reg
11847 is always set before being used (is never used without being set).
11848 And, if it's set only once, and it's always set before use, then all
11849 uses must have the same last value, even if it's not from this basic
11853 || (reg_last_set_label[regno] != label_tick
11854 && (regno < FIRST_PSEUDO_REGISTER
11855 || REG_N_SETS (regno) != 1
11856 || (REGNO_REG_SET_P
11857 (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, regno)))))
11860 /* If the value was set in a later insn than the ones we are processing,
11861 we can't use it even if the register was only set once. */
11862 if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)
11865 /* If the value has all its registers valid, return it. */
11866 if (get_last_value_validate (&value, reg_last_set[regno],
11867 reg_last_set_label[regno], 0))
11870 /* Otherwise, make a copy and replace any invalid register with
11871 (clobber (const_int 0)). If that fails for some reason, return 0. */
11873 value = copy_rtx (value);
11874 if (get_last_value_validate (&value, reg_last_set[regno],
11875 reg_last_set_label[regno], 1))
11881 /* Return nonzero if expression X refers to a REG or to memory
11882 that is set in an instruction more recent than FROM_CUID. */
11885 use_crosses_set_p (rtx x, int from_cuid)
11889 enum rtx_code code = GET_CODE (x);
11893 unsigned int regno = REGNO (x);
11894 unsigned endreg = regno + (regno < FIRST_PSEUDO_REGISTER
11895 ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
11897 #ifdef PUSH_ROUNDING
11898 /* Don't allow uses of the stack pointer to be moved,
11899 because we don't know whether the move crosses a push insn. */
11900 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11903 for (; regno < endreg; regno++)
11904 if (reg_last_set[regno]
11905 && INSN_CUID (reg_last_set[regno]) > from_cuid)
11910 if (code == MEM && mem_last_set > from_cuid)
11913 fmt = GET_RTX_FORMAT (code);
11915 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11920 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11921 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
11924 else if (fmt[i] == 'e'
11925 && use_crosses_set_p (XEXP (x, i), from_cuid))
11931 /* Define three variables used for communication between the following
11934 static unsigned int reg_dead_regno, reg_dead_endregno;
11935 static int reg_dead_flag;
11937 /* Function called via note_stores from reg_dead_at_p.
11939 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11940 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11943 reg_dead_at_p_1 (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
11945 unsigned int regno, endregno;
11947 if (GET_CODE (dest) != REG)
11950 regno = REGNO (dest);
11951 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
11952 ? hard_regno_nregs[regno][GET_MODE (dest)] : 1);
11954 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11955 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11958 /* Return nonzero if REG is known to be dead at INSN.
11960 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11961 referencing REG, it is dead. If we hit a SET referencing REG, it is
11962 live. Otherwise, see if it is live or dead at the start of the basic
11963 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11964 must be assumed to be always live. */
11967 reg_dead_at_p (rtx reg, rtx insn)
11972 /* Set variables for reg_dead_at_p_1. */
11973 reg_dead_regno = REGNO (reg);
11974 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
11975 ? hard_regno_nregs[reg_dead_regno]
11981 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
11982 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11984 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11985 if (TEST_HARD_REG_BIT (newpat_used_regs, i))
11989 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11990 beginning of function. */
11991 for (; insn && GET_CODE (insn) != CODE_LABEL && GET_CODE (insn) != BARRIER;
11992 insn = prev_nonnote_insn (insn))
11994 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
11996 return reg_dead_flag == 1 ? 1 : 0;
11998 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
12002 /* Get the basic block that we were in. */
12004 block = ENTRY_BLOCK_PTR->next_bb;
12007 FOR_EACH_BB (block)
12008 if (insn == BB_HEAD (block))
12011 if (block == EXIT_BLOCK_PTR)
12015 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12016 if (REGNO_REG_SET_P (block->global_live_at_start, i))
12022 /* Note hard registers in X that are used. This code is similar to
12023 that in flow.c, but much simpler since we don't care about pseudos. */
12026 mark_used_regs_combine (rtx x)
12028 RTX_CODE code = GET_CODE (x);
12029 unsigned int regno;
12042 case ADDR_DIFF_VEC:
12045 /* CC0 must die in the insn after it is set, so we don't need to take
12046 special note of it here. */
12052 /* If we are clobbering a MEM, mark any hard registers inside the
12053 address as used. */
12054 if (GET_CODE (XEXP (x, 0)) == MEM)
12055 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
12060 /* A hard reg in a wide mode may really be multiple registers.
12061 If so, mark all of them just like the first. */
12062 if (regno < FIRST_PSEUDO_REGISTER)
12064 unsigned int endregno, r;
12066 /* None of this applies to the stack, frame or arg pointers. */
12067 if (regno == STACK_POINTER_REGNUM
12068 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
12069 || regno == HARD_FRAME_POINTER_REGNUM
12071 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12072 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
12074 || regno == FRAME_POINTER_REGNUM)
12077 endregno = regno + hard_regno_nregs[regno][GET_MODE (x)];
12078 for (r = regno; r < endregno; r++)
12079 SET_HARD_REG_BIT (newpat_used_regs, r);
12085 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12087 rtx testreg = SET_DEST (x);
12089 while (GET_CODE (testreg) == SUBREG
12090 || GET_CODE (testreg) == ZERO_EXTRACT
12091 || GET_CODE (testreg) == SIGN_EXTRACT
12092 || GET_CODE (testreg) == STRICT_LOW_PART)
12093 testreg = XEXP (testreg, 0);
12095 if (GET_CODE (testreg) == MEM)
12096 mark_used_regs_combine (XEXP (testreg, 0));
12098 mark_used_regs_combine (SET_SRC (x));
12106 /* Recursively scan the operands of this expression. */
12109 const char *fmt = GET_RTX_FORMAT (code);
12111 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12114 mark_used_regs_combine (XEXP (x, i));
12115 else if (fmt[i] == 'E')
12119 for (j = 0; j < XVECLEN (x, i); j++)
12120 mark_used_regs_combine (XVECEXP (x, i, j));
12126 /* Remove register number REGNO from the dead registers list of INSN.
12128 Return the note used to record the death, if there was one. */
12131 remove_death (unsigned int regno, rtx insn)
12133 rtx note = find_regno_note (insn, REG_DEAD, regno);
12137 REG_N_DEATHS (regno)--;
12138 remove_note (insn, note);
12144 /* For each register (hardware or pseudo) used within expression X, if its
12145 death is in an instruction with cuid between FROM_CUID (inclusive) and
12146 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12147 list headed by PNOTES.
12149 That said, don't move registers killed by maybe_kill_insn.
12151 This is done when X is being merged by combination into TO_INSN. These
12152 notes will then be distributed as needed. */
12155 move_deaths (rtx x, rtx maybe_kill_insn, int from_cuid, rtx to_insn,
12160 enum rtx_code code = GET_CODE (x);
12164 unsigned int regno = REGNO (x);
12165 rtx where_dead = reg_last_death[regno];
12166 rtx before_dead, after_dead;
12168 /* Don't move the register if it gets killed in between from and to. */
12169 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
12170 && ! reg_referenced_p (x, maybe_kill_insn))
12173 /* WHERE_DEAD could be a USE insn made by combine, so first we
12174 make sure that we have insns with valid INSN_CUID values. */
12175 before_dead = where_dead;
12176 while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
12177 before_dead = PREV_INSN (before_dead);
12179 after_dead = where_dead;
12180 while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
12181 after_dead = NEXT_INSN (after_dead);
12183 if (before_dead && after_dead
12184 && INSN_CUID (before_dead) >= from_cuid
12185 && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
12186 || (where_dead != after_dead
12187 && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
12189 rtx note = remove_death (regno, where_dead);
12191 /* It is possible for the call above to return 0. This can occur
12192 when reg_last_death points to I2 or I1 that we combined with.
12193 In that case make a new note.
12195 We must also check for the case where X is a hard register
12196 and NOTE is a death note for a range of hard registers
12197 including X. In that case, we must put REG_DEAD notes for
12198 the remaining registers in place of NOTE. */
12200 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
12201 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12202 > GET_MODE_SIZE (GET_MODE (x))))
12204 unsigned int deadregno = REGNO (XEXP (note, 0));
12205 unsigned int deadend
12206 = (deadregno + hard_regno_nregs[deadregno]
12207 [GET_MODE (XEXP (note, 0))]);
12208 unsigned int ourend
12209 = regno + hard_regno_nregs[regno][GET_MODE (x)];
12212 for (i = deadregno; i < deadend; i++)
12213 if (i < regno || i >= ourend)
12214 REG_NOTES (where_dead)
12215 = gen_rtx_EXPR_LIST (REG_DEAD,
12217 REG_NOTES (where_dead));
12220 /* If we didn't find any note, or if we found a REG_DEAD note that
12221 covers only part of the given reg, and we have a multi-reg hard
12222 register, then to be safe we must check for REG_DEAD notes
12223 for each register other than the first. They could have
12224 their own REG_DEAD notes lying around. */
12225 else if ((note == 0
12227 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12228 < GET_MODE_SIZE (GET_MODE (x)))))
12229 && regno < FIRST_PSEUDO_REGISTER
12230 && hard_regno_nregs[regno][GET_MODE (x)] > 1)
12232 unsigned int ourend
12233 = regno + hard_regno_nregs[regno][GET_MODE (x)];
12234 unsigned int i, offset;
12238 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
12242 for (i = regno + offset; i < ourend; i++)
12243 move_deaths (regno_reg_rtx[i],
12244 maybe_kill_insn, from_cuid, to_insn, &oldnotes);
12247 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
12249 XEXP (note, 1) = *pnotes;
12253 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
12255 REG_N_DEATHS (regno)++;
12261 else if (GET_CODE (x) == SET)
12263 rtx dest = SET_DEST (x);
12265 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
12267 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12268 that accesses one word of a multi-word item, some
12269 piece of everything register in the expression is used by
12270 this insn, so remove any old death. */
12271 /* ??? So why do we test for equality of the sizes? */
12273 if (GET_CODE (dest) == ZERO_EXTRACT
12274 || GET_CODE (dest) == STRICT_LOW_PART
12275 || (GET_CODE (dest) == SUBREG
12276 && (((GET_MODE_SIZE (GET_MODE (dest))
12277 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
12278 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
12279 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
12281 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
12285 /* If this is some other SUBREG, we know it replaces the entire
12286 value, so use that as the destination. */
12287 if (GET_CODE (dest) == SUBREG)
12288 dest = SUBREG_REG (dest);
12290 /* If this is a MEM, adjust deaths of anything used in the address.
12291 For a REG (the only other possibility), the entire value is
12292 being replaced so the old value is not used in this insn. */
12294 if (GET_CODE (dest) == MEM)
12295 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
12300 else if (GET_CODE (x) == CLOBBER)
12303 len = GET_RTX_LENGTH (code);
12304 fmt = GET_RTX_FORMAT (code);
12306 for (i = 0; i < len; i++)
12311 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12312 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
12315 else if (fmt[i] == 'e')
12316 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
12320 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12321 pattern of an insn. X must be a REG. */
12324 reg_bitfield_target_p (rtx x, rtx body)
12328 if (GET_CODE (body) == SET)
12330 rtx dest = SET_DEST (body);
12332 unsigned int regno, tregno, endregno, endtregno;
12334 if (GET_CODE (dest) == ZERO_EXTRACT)
12335 target = XEXP (dest, 0);
12336 else if (GET_CODE (dest) == STRICT_LOW_PART)
12337 target = SUBREG_REG (XEXP (dest, 0));
12341 if (GET_CODE (target) == SUBREG)
12342 target = SUBREG_REG (target);
12344 if (GET_CODE (target) != REG)
12347 tregno = REGNO (target), regno = REGNO (x);
12348 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
12349 return target == x;
12351 endtregno = tregno + hard_regno_nregs[tregno][GET_MODE (target)];
12352 endregno = regno + hard_regno_nregs[regno][GET_MODE (x)];
12354 return endregno > tregno && regno < endtregno;
12357 else if (GET_CODE (body) == PARALLEL)
12358 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
12359 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
12365 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12366 as appropriate. I3 and I2 are the insns resulting from the combination
12367 insns including FROM (I2 may be zero).
12369 Each note in the list is either ignored or placed on some insns, depending
12370 on the type of note. */
12373 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2)
12375 rtx note, next_note;
12378 for (note = notes; note; note = next_note)
12380 rtx place = 0, place2 = 0;
12382 /* If this NOTE references a pseudo register, ensure it references
12383 the latest copy of that register. */
12384 if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
12385 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
12386 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
12388 next_note = XEXP (note, 1);
12389 switch (REG_NOTE_KIND (note))
12393 /* Doesn't matter much where we put this, as long as it's somewhere.
12394 It is preferable to keep these notes on branches, which is most
12395 likely to be i3. */
12399 case REG_VALUE_PROFILE:
12400 /* Just get rid of this note, as it is unused later anyway. */
12403 case REG_VTABLE_REF:
12404 /* ??? Should remain with *a particular* memory load. Given the
12405 nature of vtable data, the last insn seems relatively safe. */
12409 case REG_NON_LOCAL_GOTO:
12410 if (GET_CODE (i3) == JUMP_INSN)
12412 else if (i2 && GET_CODE (i2) == JUMP_INSN)
12418 case REG_EH_REGION:
12419 /* These notes must remain with the call or trapping instruction. */
12420 if (GET_CODE (i3) == CALL_INSN)
12422 else if (i2 && GET_CODE (i2) == CALL_INSN)
12424 else if (flag_non_call_exceptions)
12426 if (may_trap_p (i3))
12428 else if (i2 && may_trap_p (i2))
12430 /* ??? Otherwise assume we've combined things such that we
12431 can now prove that the instructions can't trap. Drop the
12432 note in this case. */
12438 case REG_ALWAYS_RETURN:
12441 /* These notes must remain with the call. It should not be
12442 possible for both I2 and I3 to be a call. */
12443 if (GET_CODE (i3) == CALL_INSN)
12445 else if (i2 && GET_CODE (i2) == CALL_INSN)
12452 /* Any clobbers for i3 may still exist, and so we must process
12453 REG_UNUSED notes from that insn.
12455 Any clobbers from i2 or i1 can only exist if they were added by
12456 recog_for_combine. In that case, recog_for_combine created the
12457 necessary REG_UNUSED notes. Trying to keep any original
12458 REG_UNUSED notes from these insns can cause incorrect output
12459 if it is for the same register as the original i3 dest.
12460 In that case, we will notice that the register is set in i3,
12461 and then add a REG_UNUSED note for the destination of i3, which
12462 is wrong. However, it is possible to have REG_UNUSED notes from
12463 i2 or i1 for register which were both used and clobbered, so
12464 we keep notes from i2 or i1 if they will turn into REG_DEAD
12467 /* If this register is set or clobbered in I3, put the note there
12468 unless there is one already. */
12469 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
12471 if (from_insn != i3)
12474 if (! (GET_CODE (XEXP (note, 0)) == REG
12475 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
12476 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
12479 /* Otherwise, if this register is used by I3, then this register
12480 now dies here, so we must put a REG_DEAD note here unless there
12482 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
12483 && ! (GET_CODE (XEXP (note, 0)) == REG
12484 ? find_regno_note (i3, REG_DEAD,
12485 REGNO (XEXP (note, 0)))
12486 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
12488 PUT_REG_NOTE_KIND (note, REG_DEAD);
12496 /* These notes say something about results of an insn. We can
12497 only support them if they used to be on I3 in which case they
12498 remain on I3. Otherwise they are ignored.
12500 If the note refers to an expression that is not a constant, we
12501 must also ignore the note since we cannot tell whether the
12502 equivalence is still true. It might be possible to do
12503 slightly better than this (we only have a problem if I2DEST
12504 or I1DEST is present in the expression), but it doesn't
12505 seem worth the trouble. */
12507 if (from_insn == i3
12508 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
12513 case REG_NO_CONFLICT:
12514 /* These notes say something about how a register is used. They must
12515 be present on any use of the register in I2 or I3. */
12516 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
12519 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
12529 /* This can show up in several ways -- either directly in the
12530 pattern, or hidden off in the constant pool with (or without?)
12531 a REG_EQUAL note. */
12532 /* ??? Ignore the without-reg_equal-note problem for now. */
12533 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
12534 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
12535 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12536 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
12540 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
12541 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
12542 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12543 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12551 /* Don't attach REG_LABEL note to a JUMP_INSN which has
12552 JUMP_LABEL already. Instead, decrement LABEL_NUSES. */
12553 if (place && GET_CODE (place) == JUMP_INSN && JUMP_LABEL (place))
12555 if (JUMP_LABEL (place) != XEXP (note, 0))
12557 if (GET_CODE (JUMP_LABEL (place)) == CODE_LABEL)
12558 LABEL_NUSES (JUMP_LABEL (place))--;
12561 if (place2 && GET_CODE (place2) == JUMP_INSN && JUMP_LABEL (place2))
12563 if (JUMP_LABEL (place2) != XEXP (note, 0))
12565 if (GET_CODE (JUMP_LABEL (place2)) == CODE_LABEL)
12566 LABEL_NUSES (JUMP_LABEL (place2))--;
12572 /* This note says something about the value of a register prior
12573 to the execution of an insn. It is too much trouble to see
12574 if the note is still correct in all situations. It is better
12575 to simply delete it. */
12579 /* If the insn previously containing this note still exists,
12580 put it back where it was. Otherwise move it to the previous
12581 insn. Adjust the corresponding REG_LIBCALL note. */
12582 if (GET_CODE (from_insn) != NOTE)
12586 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
12587 place = prev_real_insn (from_insn);
12589 XEXP (tem, 0) = place;
12590 /* If we're deleting the last remaining instruction of a
12591 libcall sequence, don't add the notes. */
12592 else if (XEXP (note, 0) == from_insn)
12598 /* This is handled similarly to REG_RETVAL. */
12599 if (GET_CODE (from_insn) != NOTE)
12603 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
12604 place = next_real_insn (from_insn);
12606 XEXP (tem, 0) = place;
12607 /* If we're deleting the last remaining instruction of a
12608 libcall sequence, don't add the notes. */
12609 else if (XEXP (note, 0) == from_insn)
12615 /* If the register is used as an input in I3, it dies there.
12616 Similarly for I2, if it is nonzero and adjacent to I3.
12618 If the register is not used as an input in either I3 or I2
12619 and it is not one of the registers we were supposed to eliminate,
12620 there are two possibilities. We might have a non-adjacent I2
12621 or we might have somehow eliminated an additional register
12622 from a computation. For example, we might have had A & B where
12623 we discover that B will always be zero. In this case we will
12624 eliminate the reference to A.
12626 In both cases, we must search to see if we can find a previous
12627 use of A and put the death note there. */
12630 && GET_CODE (from_insn) == CALL_INSN
12631 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12633 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12635 else if (i2 != 0 && next_nonnote_insn (i2) == i3
12636 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12641 basic_block bb = this_basic_block;
12643 for (tem = PREV_INSN (i3); place == 0; tem = PREV_INSN (tem))
12645 if (! INSN_P (tem))
12647 if (tem == BB_HEAD (bb))
12652 /* If the register is being set at TEM, see if that is all
12653 TEM is doing. If so, delete TEM. Otherwise, make this
12654 into a REG_UNUSED note instead. */
12655 if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
12657 rtx set = single_set (tem);
12658 rtx inner_dest = 0;
12660 rtx cc0_setter = NULL_RTX;
12664 for (inner_dest = SET_DEST (set);
12665 (GET_CODE (inner_dest) == STRICT_LOW_PART
12666 || GET_CODE (inner_dest) == SUBREG
12667 || GET_CODE (inner_dest) == ZERO_EXTRACT);
12668 inner_dest = XEXP (inner_dest, 0))
12671 /* Verify that it was the set, and not a clobber that
12672 modified the register.
12674 CC0 targets must be careful to maintain setter/user
12675 pairs. If we cannot delete the setter due to side
12676 effects, mark the user with an UNUSED note instead
12679 if (set != 0 && ! side_effects_p (SET_SRC (set))
12680 && rtx_equal_p (XEXP (note, 0), inner_dest)
12682 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12683 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12684 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12688 /* Move the notes and links of TEM elsewhere.
12689 This might delete other dead insns recursively.
12690 First set the pattern to something that won't use
12692 rtx old_notes = REG_NOTES (tem);
12694 PATTERN (tem) = pc_rtx;
12695 REG_NOTES (tem) = NULL;
12697 distribute_notes (old_notes, tem, tem, NULL_RTX);
12698 distribute_links (LOG_LINKS (tem));
12700 PUT_CODE (tem, NOTE);
12701 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
12702 NOTE_SOURCE_FILE (tem) = 0;
12705 /* Delete the setter too. */
12708 PATTERN (cc0_setter) = pc_rtx;
12709 old_notes = REG_NOTES (cc0_setter);
12710 REG_NOTES (cc0_setter) = NULL;
12712 distribute_notes (old_notes, cc0_setter,
12713 cc0_setter, NULL_RTX);
12714 distribute_links (LOG_LINKS (cc0_setter));
12716 PUT_CODE (cc0_setter, NOTE);
12717 NOTE_LINE_NUMBER (cc0_setter)
12718 = NOTE_INSN_DELETED;
12719 NOTE_SOURCE_FILE (cc0_setter) = 0;
12723 /* If the register is both set and used here, put the
12724 REG_DEAD note here, but place a REG_UNUSED note
12725 here too unless there already is one. */
12726 else if (reg_referenced_p (XEXP (note, 0),
12731 if (! find_regno_note (tem, REG_UNUSED,
12732 REGNO (XEXP (note, 0))))
12734 = gen_rtx_EXPR_LIST (REG_UNUSED, XEXP (note, 0),
12739 PUT_REG_NOTE_KIND (note, REG_UNUSED);
12741 /* If there isn't already a REG_UNUSED note, put one
12743 if (! find_regno_note (tem, REG_UNUSED,
12744 REGNO (XEXP (note, 0))))
12749 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12750 || (GET_CODE (tem) == CALL_INSN
12751 && find_reg_fusage (tem, USE, XEXP (note, 0))))
12755 /* If we are doing a 3->2 combination, and we have a
12756 register which formerly died in i3 and was not used
12757 by i2, which now no longer dies in i3 and is used in
12758 i2 but does not die in i2, and place is between i2
12759 and i3, then we may need to move a link from place to
12761 if (i2 && INSN_UID (place) <= max_uid_cuid
12762 && INSN_CUID (place) > INSN_CUID (i2)
12764 && INSN_CUID (from_insn) > INSN_CUID (i2)
12765 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12767 rtx links = LOG_LINKS (place);
12768 LOG_LINKS (place) = 0;
12769 distribute_links (links);
12774 if (tem == BB_HEAD (bb))
12778 /* We haven't found an insn for the death note and it
12779 is still a REG_DEAD note, but we have hit the beginning
12780 of the block. If the existing life info says the reg
12781 was dead, there's nothing left to do. Otherwise, we'll
12782 need to do a global life update after combine. */
12783 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0
12784 && REGNO_REG_SET_P (bb->global_live_at_start,
12785 REGNO (XEXP (note, 0))))
12786 SET_BIT (refresh_blocks, this_basic_block->index);
12789 /* If the register is set or already dead at PLACE, we needn't do
12790 anything with this note if it is still a REG_DEAD note.
12791 We can here if it is set at all, not if is it totally replace,
12792 which is what `dead_or_set_p' checks, so also check for it being
12795 if (place && REG_NOTE_KIND (note) == REG_DEAD)
12797 unsigned int regno = REGNO (XEXP (note, 0));
12799 /* Similarly, if the instruction on which we want to place
12800 the note is a noop, we'll need do a global live update
12801 after we remove them in delete_noop_moves. */
12802 if (noop_move_p (place))
12803 SET_BIT (refresh_blocks, this_basic_block->index);
12805 if (dead_or_set_p (place, XEXP (note, 0))
12806 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12808 /* Unless the register previously died in PLACE, clear
12809 reg_last_death. [I no longer understand why this is
12811 if (reg_last_death[regno] != place)
12812 reg_last_death[regno] = 0;
12816 reg_last_death[regno] = place;
12818 /* If this is a death note for a hard reg that is occupying
12819 multiple registers, ensure that we are still using all
12820 parts of the object. If we find a piece of the object
12821 that is unused, we must arrange for an appropriate REG_DEAD
12822 note to be added for it. However, we can't just emit a USE
12823 and tag the note to it, since the register might actually
12824 be dead; so we recourse, and the recursive call then finds
12825 the previous insn that used this register. */
12827 if (place && regno < FIRST_PSEUDO_REGISTER
12828 && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
12830 unsigned int endregno
12831 = regno + hard_regno_nregs[regno]
12832 [GET_MODE (XEXP (note, 0))];
12836 for (i = regno; i < endregno; i++)
12837 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12838 && ! find_regno_fusage (place, USE, i))
12839 || dead_or_set_regno_p (place, i))
12844 /* Put only REG_DEAD notes for pieces that are
12845 not already dead or set. */
12847 for (i = regno; i < endregno;
12848 i += hard_regno_nregs[i][reg_raw_mode[i]])
12850 rtx piece = regno_reg_rtx[i];
12851 basic_block bb = this_basic_block;
12853 if (! dead_or_set_p (place, piece)
12854 && ! reg_bitfield_target_p (piece,
12858 = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX);
12860 distribute_notes (new_note, place, place,
12863 else if (! refers_to_regno_p (i, i + 1,
12864 PATTERN (place), 0)
12865 && ! find_regno_fusage (place, USE, i))
12866 for (tem = PREV_INSN (place); ;
12867 tem = PREV_INSN (tem))
12869 if (! INSN_P (tem))
12871 if (tem == BB_HEAD (bb))
12873 SET_BIT (refresh_blocks,
12874 this_basic_block->index);
12879 if (dead_or_set_p (tem, piece)
12880 || reg_bitfield_target_p (piece,
12884 = gen_rtx_EXPR_LIST (REG_UNUSED, piece,
12899 /* Any other notes should not be present at this point in the
12906 XEXP (note, 1) = REG_NOTES (place);
12907 REG_NOTES (place) = note;
12909 else if ((REG_NOTE_KIND (note) == REG_DEAD
12910 || REG_NOTE_KIND (note) == REG_UNUSED)
12911 && GET_CODE (XEXP (note, 0)) == REG)
12912 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
12916 if ((REG_NOTE_KIND (note) == REG_DEAD
12917 || REG_NOTE_KIND (note) == REG_UNUSED)
12918 && GET_CODE (XEXP (note, 0)) == REG)
12919 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
12921 REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
12922 REG_NOTE_KIND (note),
12924 REG_NOTES (place2));
12929 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12930 I3, I2, and I1 to new locations. This is also called to add a link
12931 pointing at I3 when I3's destination is changed. */
12934 distribute_links (rtx links)
12936 rtx link, next_link;
12938 for (link = links; link; link = next_link)
12944 next_link = XEXP (link, 1);
12946 /* If the insn that this link points to is a NOTE or isn't a single
12947 set, ignore it. In the latter case, it isn't clear what we
12948 can do other than ignore the link, since we can't tell which
12949 register it was for. Such links wouldn't be used by combine
12952 It is not possible for the destination of the target of the link to
12953 have been changed by combine. The only potential of this is if we
12954 replace I3, I2, and I1 by I3 and I2. But in that case the
12955 destination of I2 also remains unchanged. */
12957 if (GET_CODE (XEXP (link, 0)) == NOTE
12958 || (set = single_set (XEXP (link, 0))) == 0)
12961 reg = SET_DEST (set);
12962 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12963 || GET_CODE (reg) == SIGN_EXTRACT
12964 || GET_CODE (reg) == STRICT_LOW_PART)
12965 reg = XEXP (reg, 0);
12967 /* A LOG_LINK is defined as being placed on the first insn that uses
12968 a register and points to the insn that sets the register. Start
12969 searching at the next insn after the target of the link and stop
12970 when we reach a set of the register or the end of the basic block.
12972 Note that this correctly handles the link that used to point from
12973 I3 to I2. Also note that not much searching is typically done here
12974 since most links don't point very far away. */
12976 for (insn = NEXT_INSN (XEXP (link, 0));
12977 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
12978 || BB_HEAD (this_basic_block->next_bb) != insn));
12979 insn = NEXT_INSN (insn))
12980 if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12982 if (reg_referenced_p (reg, PATTERN (insn)))
12986 else if (GET_CODE (insn) == CALL_INSN
12987 && find_reg_fusage (insn, USE, reg))
12992 else if (INSN_P (insn) && reg_set_p (reg, insn))
12995 /* If we found a place to put the link, place it there unless there
12996 is already a link to the same insn as LINK at that point. */
13002 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
13003 if (XEXP (link2, 0) == XEXP (link, 0))
13008 XEXP (link, 1) = LOG_LINKS (place);
13009 LOG_LINKS (place) = link;
13011 /* Set added_links_insn to the earliest insn we added a
13013 if (added_links_insn == 0
13014 || INSN_CUID (added_links_insn) > INSN_CUID (place))
13015 added_links_insn = place;
13021 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
13024 insn_cuid (rtx insn)
13026 while (insn != 0 && INSN_UID (insn) > max_uid_cuid
13027 && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE)
13028 insn = NEXT_INSN (insn);
13030 if (INSN_UID (insn) > max_uid_cuid)
13033 return INSN_CUID (insn);
13037 dump_combine_stats (FILE *file)
13041 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13042 combine_attempts, combine_merges, combine_extras, combine_successes);
13046 dump_combine_total_stats (FILE *file)
13050 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13051 total_attempts, total_merges, total_extras, total_successes);