1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
57 removed because there is no way to know which register it was
60 To simplify substitution, we combine only when the earlier insn(s)
61 consist of only a single assignment. To simplify updating afterward,
62 we never combine when a subroutine call appears in the middle.
64 Since we do not represent assignments to CC0 explicitly except when that
65 is all an insn does, there is no LOG_LINKS entry in an insn that uses
66 the condition code for the insn that set the condition code.
67 Fortunately, these two insns must be consecutive.
68 Therefore, every JUMP_INSN is taken to have an implicit logical link
69 to the preceding insn. This is not quite right, since non-jumps can
70 also use the condition code; but in practice such insns would not
75 #include "coretypes.h"
81 #include "hard-reg-set.h"
82 #include "basic-block.h"
83 #include "insn-config.h"
85 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
87 #include "insn-attr.h"
92 /* It is not safe to use ordinary gen_lowpart in combine.
93 Use gen_lowpart_for_combine instead. See comments there. */
94 #define gen_lowpart dont_use_gen_lowpart_you_dummy
96 /* Number of attempts to combine instructions in this function. */
98 static int combine_attempts;
100 /* Number of attempts that got as far as substitution in this function. */
102 static int combine_merges;
104 /* Number of instructions combined with added SETs in this function. */
106 static int combine_extras;
108 /* Number of instructions combined in this function. */
110 static int combine_successes;
112 /* Totals over entire compilation. */
114 static int total_attempts, total_merges, total_extras, total_successes;
117 /* Vector mapping INSN_UIDs to cuids.
118 The cuids are like uids but increase monotonically always.
119 Combine always uses cuids so that it can compare them.
120 But actually renumbering the uids, which we used to do,
121 proves to be a bad idea because it makes it hard to compare
122 the dumps produced by earlier passes with those from later passes. */
124 static int *uid_cuid;
125 static int max_uid_cuid;
127 /* Get the cuid of an insn. */
129 #define INSN_CUID(INSN) \
130 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
132 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
133 BITS_PER_WORD would invoke undefined behavior. Work around it. */
135 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
136 (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
138 #define nonzero_bits(X, M) \
139 cached_nonzero_bits (X, M, NULL_RTX, VOIDmode, 0)
141 #define num_sign_bit_copies(X, M) \
142 cached_num_sign_bit_copies (X, M, NULL_RTX, VOIDmode, 0)
144 /* Maximum register number, which is the size of the tables below. */
146 static unsigned int combine_max_regno;
148 /* Record last point of death of (hard or pseudo) register n. */
150 static rtx *reg_last_death;
152 /* Record last point of modification of (hard or pseudo) register n. */
154 static rtx *reg_last_set;
156 /* Record the cuid of the last insn that invalidated memory
157 (anything that writes memory, and subroutine calls, but not pushes). */
159 static int mem_last_set;
161 /* Record the cuid of the last CALL_INSN
162 so we can tell whether a potential combination crosses any calls. */
164 static int last_call_cuid;
166 /* When `subst' is called, this is the insn that is being modified
167 (by combining in a previous insn). The PATTERN of this insn
168 is still the old pattern partially modified and it should not be
169 looked at, but this may be used to examine the successors of the insn
170 to judge whether a simplification is valid. */
172 static rtx subst_insn;
174 /* This is the lowest CUID that `subst' is currently dealing with.
175 get_last_value will not return a value if the register was set at or
176 after this CUID. If not for this mechanism, we could get confused if
177 I2 or I1 in try_combine were an insn that used the old value of a register
178 to obtain a new value. In that case, we might erroneously get the
179 new value of the register when we wanted the old one. */
181 static int subst_low_cuid;
183 /* This contains any hard registers that are used in newpat; reg_dead_at_p
184 must consider all these registers to be always live. */
186 static HARD_REG_SET newpat_used_regs;
188 /* This is an insn to which a LOG_LINKS entry has been added. If this
189 insn is the earlier than I2 or I3, combine should rescan starting at
192 static rtx added_links_insn;
194 /* Basic block in which we are performing combines. */
195 static basic_block this_basic_block;
197 /* A bitmap indicating which blocks had registers go dead at entry.
198 After combine, we'll need to re-do global life analysis with
199 those blocks as starting points. */
200 static sbitmap refresh_blocks;
202 /* The next group of arrays allows the recording of the last value assigned
203 to (hard or pseudo) register n. We use this information to see if an
204 operation being processed is redundant given a prior operation performed
205 on the register. For example, an `and' with a constant is redundant if
206 all the zero bits are already known to be turned off.
208 We use an approach similar to that used by cse, but change it in the
211 (1) We do not want to reinitialize at each label.
212 (2) It is useful, but not critical, to know the actual value assigned
213 to a register. Often just its form is helpful.
215 Therefore, we maintain the following arrays:
217 reg_last_set_value the last value assigned
218 reg_last_set_label records the value of label_tick when the
219 register was assigned
220 reg_last_set_table_tick records the value of label_tick when a
221 value using the register is assigned
222 reg_last_set_invalid set to nonzero when it is not valid
223 to use the value of this register in some
226 To understand the usage of these tables, it is important to understand
227 the distinction between the value in reg_last_set_value being valid
228 and the register being validly contained in some other expression in the
231 Entry I in reg_last_set_value is valid if it is nonzero, and either
232 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
234 Register I may validly appear in any expression returned for the value
235 of another register if reg_n_sets[i] is 1. It may also appear in the
236 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
237 reg_last_set_invalid[j] is zero.
239 If an expression is found in the table containing a register which may
240 not validly appear in an expression, the register is replaced by
241 something that won't match, (clobber (const_int 0)).
243 reg_last_set_invalid[i] is set nonzero when register I is being assigned
244 to and reg_last_set_table_tick[i] == label_tick. */
246 /* Record last value assigned to (hard or pseudo) register n. */
248 static rtx *reg_last_set_value;
250 /* Record the value of label_tick when the value for register n is placed in
251 reg_last_set_value[n]. */
253 static int *reg_last_set_label;
255 /* Record the value of label_tick when an expression involving register n
256 is placed in reg_last_set_value. */
258 static int *reg_last_set_table_tick;
260 /* Set nonzero if references to register n in expressions should not be
263 static char *reg_last_set_invalid;
265 /* Incremented for each label. */
267 static int label_tick;
269 /* Some registers that are set more than once and used in more than one
270 basic block are nevertheless always set in similar ways. For example,
271 a QImode register may be loaded from memory in two places on a machine
272 where byte loads zero extend.
274 We record in the following array what we know about the nonzero
275 bits of a register, specifically which bits are known to be zero.
277 If an entry is zero, it means that we don't know anything special. */
279 static unsigned HOST_WIDE_INT *reg_nonzero_bits;
281 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
282 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
284 static enum machine_mode nonzero_bits_mode;
286 /* Nonzero if we know that a register has some leading bits that are always
287 equal to the sign bit. */
289 static unsigned char *reg_sign_bit_copies;
291 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
292 It is zero while computing them and after combine has completed. This
293 former test prevents propagating values based on previously set values,
294 which can be incorrect if a variable is modified in a loop. */
296 static int nonzero_sign_valid;
298 /* These arrays are maintained in parallel with reg_last_set_value
299 and are used to store the mode in which the register was last set,
300 the bits that were known to be zero when it was last set, and the
301 number of sign bits copies it was known to have when it was last set. */
303 static enum machine_mode *reg_last_set_mode;
304 static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits;
305 static char *reg_last_set_sign_bit_copies;
307 /* Record one modification to rtl structure
308 to be undone by storing old_contents into *where.
309 is_int is 1 if the contents are an int. */
315 union {rtx r; int i;} old_contents;
316 union {rtx *r; int *i;} where;
319 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
320 num_undo says how many are currently recorded.
322 other_insn is nonzero if we have modified some other insn in the process
323 of working on subst_insn. It must be verified too. */
332 static struct undobuf undobuf;
334 /* Number of times the pseudo being substituted for
335 was found and replaced. */
337 static int n_occurrences;
339 static void do_SUBST (rtx *, rtx);
340 static void do_SUBST_INT (int *, int);
341 static void init_reg_last_arrays (void);
342 static void setup_incoming_promotions (void);
343 static void set_nonzero_bits_and_sign_copies (rtx, rtx, void *);
344 static int cant_combine_insn_p (rtx);
345 static int can_combine_p (rtx, rtx, rtx, rtx, rtx *, rtx *);
346 static int sets_function_arg_p (rtx);
347 static int combinable_i3pat (rtx, rtx *, rtx, rtx, int, rtx *);
348 static int contains_muldiv (rtx);
349 static rtx try_combine (rtx, rtx, rtx, int *);
350 static void undo_all (void);
351 static void undo_commit (void);
352 static rtx *find_split_point (rtx *, rtx);
353 static rtx subst (rtx, rtx, rtx, int, int);
354 static rtx combine_simplify_rtx (rtx, enum machine_mode, int, int);
355 static rtx simplify_if_then_else (rtx);
356 static rtx simplify_set (rtx);
357 static rtx simplify_logical (rtx, int);
358 static rtx expand_compound_operation (rtx);
359 static rtx expand_field_assignment (rtx);
360 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
361 rtx, unsigned HOST_WIDE_INT, int, int, int);
362 static rtx extract_left_shift (rtx, int);
363 static rtx make_compound_operation (rtx, enum rtx_code);
364 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
365 unsigned HOST_WIDE_INT *);
366 static rtx force_to_mode (rtx, enum machine_mode,
367 unsigned HOST_WIDE_INT, rtx, int);
368 static rtx if_then_else_cond (rtx, rtx *, rtx *);
369 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
370 static int rtx_equal_for_field_assignment_p (rtx, rtx);
371 static rtx make_field_assignment (rtx);
372 static rtx apply_distributive_law (rtx);
373 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
374 unsigned HOST_WIDE_INT);
375 static unsigned HOST_WIDE_INT cached_nonzero_bits (rtx, enum machine_mode,
376 rtx, enum machine_mode,
377 unsigned HOST_WIDE_INT);
378 static unsigned HOST_WIDE_INT nonzero_bits1 (rtx, enum machine_mode, rtx,
380 unsigned HOST_WIDE_INT);
381 static unsigned int cached_num_sign_bit_copies (rtx, enum machine_mode, rtx,
384 static unsigned int num_sign_bit_copies1 (rtx, enum machine_mode, rtx,
385 enum machine_mode, unsigned int);
386 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
387 HOST_WIDE_INT, enum machine_mode, int *);
388 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
390 static int recog_for_combine (rtx *, rtx, rtx *);
391 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
392 static rtx gen_binary (enum rtx_code, enum machine_mode, rtx, rtx);
393 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
394 static void update_table_tick (rtx);
395 static void record_value_for_reg (rtx, rtx, rtx);
396 static void check_promoted_subreg (rtx, rtx);
397 static void record_dead_and_set_regs_1 (rtx, rtx, void *);
398 static void record_dead_and_set_regs (rtx);
399 static int get_last_value_validate (rtx *, rtx, int, int);
400 static rtx get_last_value (rtx);
401 static int use_crosses_set_p (rtx, int);
402 static void reg_dead_at_p_1 (rtx, rtx, void *);
403 static int reg_dead_at_p (rtx, rtx);
404 static void move_deaths (rtx, rtx, int, rtx, rtx *);
405 static int reg_bitfield_target_p (rtx, rtx);
406 static void distribute_notes (rtx, rtx, rtx, rtx);
407 static void distribute_links (rtx);
408 static void mark_used_regs_combine (rtx);
409 static int insn_cuid (rtx);
410 static void record_promoted_value (rtx, rtx);
411 static rtx reversed_comparison (rtx, enum machine_mode, rtx, rtx);
412 static enum rtx_code combine_reversed_comparison_code (rtx);
414 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
415 insn. The substitution can be undone by undo_all. If INTO is already
416 set to NEWVAL, do not record this change. Because computing NEWVAL might
417 also call SUBST, we have to compute it before we put anything into
421 do_SUBST (rtx *into, rtx newval)
426 if (oldval == newval)
429 /* We'd like to catch as many invalid transformations here as
430 possible. Unfortunately, there are way too many mode changes
431 that are perfectly valid, so we'd waste too much effort for
432 little gain doing the checks here. Focus on catching invalid
433 transformations involving integer constants. */
434 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
435 && GET_CODE (newval) == CONST_INT)
437 /* Sanity check that we're replacing oldval with a CONST_INT
438 that is a valid sign-extension for the original mode. */
439 if (INTVAL (newval) != trunc_int_for_mode (INTVAL (newval),
443 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
444 CONST_INT is not valid, because after the replacement, the
445 original mode would be gone. Unfortunately, we can't tell
446 when do_SUBST is called to replace the operand thereof, so we
447 perform this test on oldval instead, checking whether an
448 invalid replacement took place before we got here. */
449 if ((GET_CODE (oldval) == SUBREG
450 && GET_CODE (SUBREG_REG (oldval)) == CONST_INT)
451 || (GET_CODE (oldval) == ZERO_EXTEND
452 && GET_CODE (XEXP (oldval, 0)) == CONST_INT))
457 buf = undobuf.frees, undobuf.frees = buf->next;
459 buf = (struct undo *) xmalloc (sizeof (struct undo));
463 buf->old_contents.r = oldval;
466 buf->next = undobuf.undos, undobuf.undos = buf;
469 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
471 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
472 for the value of a HOST_WIDE_INT value (including CONST_INT) is
476 do_SUBST_INT (int *into, int newval)
481 if (oldval == newval)
485 buf = undobuf.frees, undobuf.frees = buf->next;
487 buf = (struct undo *) xmalloc (sizeof (struct undo));
491 buf->old_contents.i = oldval;
494 buf->next = undobuf.undos, undobuf.undos = buf;
497 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
499 /* Main entry point for combiner. F is the first insn of the function.
500 NREGS is the first unused pseudo-reg number.
502 Return nonzero if the combiner has turned an indirect jump
503 instruction into a direct jump. */
505 combine_instructions (rtx f, unsigned int nregs)
512 rtx links, nextlinks;
514 int new_direct_jump_p = 0;
516 combine_attempts = 0;
519 combine_successes = 0;
521 combine_max_regno = nregs;
523 reg_nonzero_bits = ((unsigned HOST_WIDE_INT *)
524 xcalloc (nregs, sizeof (unsigned HOST_WIDE_INT)));
526 = (unsigned char *) xcalloc (nregs, sizeof (unsigned char));
528 reg_last_death = (rtx *) xmalloc (nregs * sizeof (rtx));
529 reg_last_set = (rtx *) xmalloc (nregs * sizeof (rtx));
530 reg_last_set_value = (rtx *) xmalloc (nregs * sizeof (rtx));
531 reg_last_set_table_tick = (int *) xmalloc (nregs * sizeof (int));
532 reg_last_set_label = (int *) xmalloc (nregs * sizeof (int));
533 reg_last_set_invalid = (char *) xmalloc (nregs * sizeof (char));
535 = (enum machine_mode *) xmalloc (nregs * sizeof (enum machine_mode));
536 reg_last_set_nonzero_bits
537 = (unsigned HOST_WIDE_INT *) xmalloc (nregs * sizeof (HOST_WIDE_INT));
538 reg_last_set_sign_bit_copies
539 = (char *) xmalloc (nregs * sizeof (char));
541 init_reg_last_arrays ();
543 init_recog_no_volatile ();
545 /* Compute maximum uid value so uid_cuid can be allocated. */
547 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
548 if (INSN_UID (insn) > i)
551 uid_cuid = (int *) xmalloc ((i + 1) * sizeof (int));
554 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
556 /* Don't use reg_nonzero_bits when computing it. This can cause problems
557 when, for example, we have j <<= 1 in a loop. */
559 nonzero_sign_valid = 0;
561 /* Compute the mapping from uids to cuids.
562 Cuids are numbers assigned to insns, like uids,
563 except that cuids increase monotonically through the code.
565 Scan all SETs and see if we can deduce anything about what
566 bits are known to be zero for some registers and how many copies
567 of the sign bit are known to exist for those registers.
569 Also set any known values so that we can use it while searching
570 for what bits are known to be set. */
574 setup_incoming_promotions ();
576 refresh_blocks = sbitmap_alloc (last_basic_block);
577 sbitmap_zero (refresh_blocks);
579 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
581 uid_cuid[INSN_UID (insn)] = ++i;
587 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
589 record_dead_and_set_regs (insn);
592 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
593 if (REG_NOTE_KIND (links) == REG_INC)
594 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
599 if (GET_CODE (insn) == CODE_LABEL)
603 nonzero_sign_valid = 1;
605 /* Now scan all the insns in forward order. */
610 init_reg_last_arrays ();
611 setup_incoming_promotions ();
613 FOR_EACH_BB (this_basic_block)
615 for (insn = this_basic_block->head;
616 insn != NEXT_INSN (this_basic_block->end);
617 insn = next ? next : NEXT_INSN (insn))
621 if (GET_CODE (insn) == CODE_LABEL)
624 else if (INSN_P (insn))
626 /* See if we know about function return values before this
627 insn based upon SUBREG flags. */
628 check_promoted_subreg (insn, PATTERN (insn));
630 /* Try this insn with each insn it links back to. */
632 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
633 if ((next = try_combine (insn, XEXP (links, 0),
634 NULL_RTX, &new_direct_jump_p)) != 0)
637 /* Try each sequence of three linked insns ending with this one. */
639 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
641 rtx link = XEXP (links, 0);
643 /* If the linked insn has been replaced by a note, then there
644 is no point in pursuing this chain any further. */
645 if (GET_CODE (link) == NOTE)
648 for (nextlinks = LOG_LINKS (link);
650 nextlinks = XEXP (nextlinks, 1))
651 if ((next = try_combine (insn, link,
653 &new_direct_jump_p)) != 0)
658 /* Try to combine a jump insn that uses CC0
659 with a preceding insn that sets CC0, and maybe with its
660 logical predecessor as well.
661 This is how we make decrement-and-branch insns.
662 We need this special code because data flow connections
663 via CC0 do not get entered in LOG_LINKS. */
665 if (GET_CODE (insn) == JUMP_INSN
666 && (prev = prev_nonnote_insn (insn)) != 0
667 && GET_CODE (prev) == INSN
668 && sets_cc0_p (PATTERN (prev)))
670 if ((next = try_combine (insn, prev,
671 NULL_RTX, &new_direct_jump_p)) != 0)
674 for (nextlinks = LOG_LINKS (prev); nextlinks;
675 nextlinks = XEXP (nextlinks, 1))
676 if ((next = try_combine (insn, prev,
678 &new_direct_jump_p)) != 0)
682 /* Do the same for an insn that explicitly references CC0. */
683 if (GET_CODE (insn) == INSN
684 && (prev = prev_nonnote_insn (insn)) != 0
685 && GET_CODE (prev) == INSN
686 && sets_cc0_p (PATTERN (prev))
687 && GET_CODE (PATTERN (insn)) == SET
688 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
690 if ((next = try_combine (insn, prev,
691 NULL_RTX, &new_direct_jump_p)) != 0)
694 for (nextlinks = LOG_LINKS (prev); nextlinks;
695 nextlinks = XEXP (nextlinks, 1))
696 if ((next = try_combine (insn, prev,
698 &new_direct_jump_p)) != 0)
702 /* Finally, see if any of the insns that this insn links to
703 explicitly references CC0. If so, try this insn, that insn,
704 and its predecessor if it sets CC0. */
705 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
706 if (GET_CODE (XEXP (links, 0)) == INSN
707 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
708 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
709 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
710 && GET_CODE (prev) == INSN
711 && sets_cc0_p (PATTERN (prev))
712 && (next = try_combine (insn, XEXP (links, 0),
713 prev, &new_direct_jump_p)) != 0)
717 /* Try combining an insn with two different insns whose results it
719 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
720 for (nextlinks = XEXP (links, 1); nextlinks;
721 nextlinks = XEXP (nextlinks, 1))
722 if ((next = try_combine (insn, XEXP (links, 0),
724 &new_direct_jump_p)) != 0)
727 if (GET_CODE (insn) != NOTE)
728 record_dead_and_set_regs (insn);
737 EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks, 0, i,
738 BASIC_BLOCK (i)->flags |= BB_DIRTY);
739 new_direct_jump_p |= purge_all_dead_edges (0);
740 delete_noop_moves (f);
742 update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES,
743 PROP_DEATH_NOTES | PROP_SCAN_DEAD_CODE
744 | PROP_KILL_DEAD_CODE);
747 sbitmap_free (refresh_blocks);
748 free (reg_nonzero_bits);
749 free (reg_sign_bit_copies);
750 free (reg_last_death);
752 free (reg_last_set_value);
753 free (reg_last_set_table_tick);
754 free (reg_last_set_label);
755 free (reg_last_set_invalid);
756 free (reg_last_set_mode);
757 free (reg_last_set_nonzero_bits);
758 free (reg_last_set_sign_bit_copies);
762 struct undo *undo, *next;
763 for (undo = undobuf.frees; undo; undo = next)
771 total_attempts += combine_attempts;
772 total_merges += combine_merges;
773 total_extras += combine_extras;
774 total_successes += combine_successes;
776 nonzero_sign_valid = 0;
778 /* Make recognizer allow volatile MEMs again. */
781 return new_direct_jump_p;
784 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
787 init_reg_last_arrays (void)
789 unsigned int nregs = combine_max_regno;
791 memset ((char *) reg_last_death, 0, nregs * sizeof (rtx));
792 memset ((char *) reg_last_set, 0, nregs * sizeof (rtx));
793 memset ((char *) reg_last_set_value, 0, nregs * sizeof (rtx));
794 memset ((char *) reg_last_set_table_tick, 0, nregs * sizeof (int));
795 memset ((char *) reg_last_set_label, 0, nregs * sizeof (int));
796 memset (reg_last_set_invalid, 0, nregs * sizeof (char));
797 memset ((char *) reg_last_set_mode, 0, nregs * sizeof (enum machine_mode));
798 memset ((char *) reg_last_set_nonzero_bits, 0, nregs * sizeof (HOST_WIDE_INT));
799 memset (reg_last_set_sign_bit_copies, 0, nregs * sizeof (char));
802 /* Set up any promoted values for incoming argument registers. */
805 setup_incoming_promotions (void)
807 #ifdef PROMOTE_FUNCTION_ARGS
810 enum machine_mode mode;
812 rtx first = get_insns ();
814 #ifndef OUTGOING_REGNO
815 #define OUTGOING_REGNO(N) N
817 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
818 /* Check whether this register can hold an incoming pointer
819 argument. FUNCTION_ARG_REGNO_P tests outgoing register
820 numbers, so translate if necessary due to register windows. */
821 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno))
822 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
825 (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
828 gen_rtx_CLOBBER (mode, const0_rtx)));
833 /* Called via note_stores. If X is a pseudo that is narrower than
834 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
836 If we are setting only a portion of X and we can't figure out what
837 portion, assume all bits will be used since we don't know what will
840 Similarly, set how many bits of X are known to be copies of the sign bit
841 at all locations in the function. This is the smallest number implied
845 set_nonzero_bits_and_sign_copies (rtx x, rtx set,
846 void *data ATTRIBUTE_UNUSED)
850 if (GET_CODE (x) == REG
851 && REGNO (x) >= FIRST_PSEUDO_REGISTER
852 /* If this register is undefined at the start of the file, we can't
853 say what its contents were. */
854 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, REGNO (x))
855 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
857 if (set == 0 || GET_CODE (set) == CLOBBER)
859 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
860 reg_sign_bit_copies[REGNO (x)] = 1;
864 /* If this is a complex assignment, see if we can convert it into a
865 simple assignment. */
866 set = expand_field_assignment (set);
868 /* If this is a simple assignment, or we have a paradoxical SUBREG,
869 set what we know about X. */
871 if (SET_DEST (set) == x
872 || (GET_CODE (SET_DEST (set)) == SUBREG
873 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
874 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
875 && SUBREG_REG (SET_DEST (set)) == x))
877 rtx src = SET_SRC (set);
879 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
880 /* If X is narrower than a word and SRC is a non-negative
881 constant that would appear negative in the mode of X,
882 sign-extend it for use in reg_nonzero_bits because some
883 machines (maybe most) will actually do the sign-extension
884 and this is the conservative approach.
886 ??? For 2.5, try to tighten up the MD files in this regard
887 instead of this kludge. */
889 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
890 && GET_CODE (src) == CONST_INT
892 && 0 != (INTVAL (src)
894 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
895 src = GEN_INT (INTVAL (src)
896 | ((HOST_WIDE_INT) (-1)
897 << GET_MODE_BITSIZE (GET_MODE (x))));
900 /* Don't call nonzero_bits if it cannot change anything. */
901 if (reg_nonzero_bits[REGNO (x)] != ~(unsigned HOST_WIDE_INT) 0)
902 reg_nonzero_bits[REGNO (x)]
903 |= nonzero_bits (src, nonzero_bits_mode);
904 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
905 if (reg_sign_bit_copies[REGNO (x)] == 0
906 || reg_sign_bit_copies[REGNO (x)] > num)
907 reg_sign_bit_copies[REGNO (x)] = num;
911 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
912 reg_sign_bit_copies[REGNO (x)] = 1;
917 /* See if INSN can be combined into I3. PRED and SUCC are optionally
918 insns that were previously combined into I3 or that will be combined
919 into the merger of INSN and I3.
921 Return 0 if the combination is not allowed for any reason.
923 If the combination is allowed, *PDEST will be set to the single
924 destination of INSN and *PSRC to the single source, and this function
928 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED, rtx succ,
929 rtx *pdest, rtx *psrc)
932 rtx set = 0, src, dest;
937 int all_adjacent = (succ ? (next_active_insn (insn) == succ
938 && next_active_insn (succ) == i3)
939 : next_active_insn (insn) == i3);
941 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
942 or a PARALLEL consisting of such a SET and CLOBBERs.
944 If INSN has CLOBBER parallel parts, ignore them for our processing.
945 By definition, these happen during the execution of the insn. When it
946 is merged with another insn, all bets are off. If they are, in fact,
947 needed and aren't also supplied in I3, they may be added by
948 recog_for_combine. Otherwise, it won't match.
950 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
953 Get the source and destination of INSN. If more than one, can't
956 if (GET_CODE (PATTERN (insn)) == SET)
957 set = PATTERN (insn);
958 else if (GET_CODE (PATTERN (insn)) == PARALLEL
959 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
961 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
963 rtx elt = XVECEXP (PATTERN (insn), 0, i);
965 switch (GET_CODE (elt))
967 /* This is important to combine floating point insns
970 /* Combining an isolated USE doesn't make sense.
971 We depend here on combinable_i3pat to reject them. */
972 /* The code below this loop only verifies that the inputs of
973 the SET in INSN do not change. We call reg_set_between_p
974 to verify that the REG in the USE does not change between
976 If the USE in INSN was for a pseudo register, the matching
977 insn pattern will likely match any register; combining this
978 with any other USE would only be safe if we knew that the
979 used registers have identical values, or if there was
980 something to tell them apart, e.g. different modes. For
981 now, we forgo such complicated tests and simply disallow
982 combining of USES of pseudo registers with any other USE. */
983 if (GET_CODE (XEXP (elt, 0)) == REG
984 && GET_CODE (PATTERN (i3)) == PARALLEL)
986 rtx i3pat = PATTERN (i3);
987 int i = XVECLEN (i3pat, 0) - 1;
988 unsigned int regno = REGNO (XEXP (elt, 0));
992 rtx i3elt = XVECEXP (i3pat, 0, i);
994 if (GET_CODE (i3elt) == USE
995 && GET_CODE (XEXP (i3elt, 0)) == REG
996 && (REGNO (XEXP (i3elt, 0)) == regno
997 ? reg_set_between_p (XEXP (elt, 0),
998 PREV_INSN (insn), i3)
999 : regno >= FIRST_PSEUDO_REGISTER))
1006 /* We can ignore CLOBBERs. */
1011 /* Ignore SETs whose result isn't used but not those that
1012 have side-effects. */
1013 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1014 && ! side_effects_p (elt))
1017 /* If we have already found a SET, this is a second one and
1018 so we cannot combine with this insn. */
1026 /* Anything else means we can't combine. */
1032 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1033 so don't do anything with it. */
1034 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1043 set = expand_field_assignment (set);
1044 src = SET_SRC (set), dest = SET_DEST (set);
1046 /* Don't eliminate a store in the stack pointer. */
1047 if (dest == stack_pointer_rtx
1048 /* Don't combine with an insn that sets a register to itself if it has
1049 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1050 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1051 /* Can't merge an ASM_OPERANDS. */
1052 || GET_CODE (src) == ASM_OPERANDS
1053 /* Can't merge a function call. */
1054 || GET_CODE (src) == CALL
1055 /* Don't eliminate a function call argument. */
1056 || (GET_CODE (i3) == CALL_INSN
1057 && (find_reg_fusage (i3, USE, dest)
1058 || (GET_CODE (dest) == REG
1059 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1060 && global_regs[REGNO (dest)])))
1061 /* Don't substitute into an incremented register. */
1062 || FIND_REG_INC_NOTE (i3, dest)
1063 || (succ && FIND_REG_INC_NOTE (succ, dest))
1065 /* Don't combine the end of a libcall into anything. */
1066 /* ??? This gives worse code, and appears to be unnecessary, since no
1067 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1068 use REG_RETVAL notes for noconflict blocks, but other code here
1069 makes sure that those insns don't disappear. */
1070 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
1072 /* Make sure that DEST is not used after SUCC but before I3. */
1073 || (succ && ! all_adjacent
1074 && reg_used_between_p (dest, succ, i3))
1075 /* Make sure that the value that is to be substituted for the register
1076 does not use any registers whose values alter in between. However,
1077 If the insns are adjacent, a use can't cross a set even though we
1078 think it might (this can happen for a sequence of insns each setting
1079 the same destination; reg_last_set of that register might point to
1080 a NOTE). If INSN has a REG_EQUIV note, the register is always
1081 equivalent to the memory so the substitution is valid even if there
1082 are intervening stores. Also, don't move a volatile asm or
1083 UNSPEC_VOLATILE across any other insns. */
1085 && (((GET_CODE (src) != MEM
1086 || ! find_reg_note (insn, REG_EQUIV, src))
1087 && use_crosses_set_p (src, INSN_CUID (insn)))
1088 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1089 || GET_CODE (src) == UNSPEC_VOLATILE))
1090 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1091 better register allocation by not doing the combine. */
1092 || find_reg_note (i3, REG_NO_CONFLICT, dest)
1093 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
1094 /* Don't combine across a CALL_INSN, because that would possibly
1095 change whether the life span of some REGs crosses calls or not,
1096 and it is a pain to update that information.
1097 Exception: if source is a constant, moving it later can't hurt.
1098 Accept that special case, because it helps -fforce-addr a lot. */
1099 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
1102 /* DEST must either be a REG or CC0. */
1103 if (GET_CODE (dest) == REG)
1105 /* If register alignment is being enforced for multi-word items in all
1106 cases except for parameters, it is possible to have a register copy
1107 insn referencing a hard register that is not allowed to contain the
1108 mode being copied and which would not be valid as an operand of most
1109 insns. Eliminate this problem by not combining with such an insn.
1111 Also, on some machines we don't want to extend the life of a hard
1114 if (GET_CODE (src) == REG
1115 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1116 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1117 /* Don't extend the life of a hard register unless it is
1118 user variable (if we have few registers) or it can't
1119 fit into the desired register (meaning something special
1121 Also avoid substituting a return register into I3, because
1122 reload can't handle a conflict with constraints of other
1124 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1125 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1128 else if (GET_CODE (dest) != CC0)
1131 /* Don't substitute for a register intended as a clobberable operand.
1132 Similarly, don't substitute an expression containing a register that
1133 will be clobbered in I3. */
1134 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1135 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1136 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
1137 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0),
1139 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)))
1142 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1143 or not), reject, unless nothing volatile comes between it and I3 */
1145 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1147 /* Make sure succ doesn't contain a volatile reference. */
1148 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1151 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1152 if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1156 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1157 to be an explicit register variable, and was chosen for a reason. */
1159 if (GET_CODE (src) == ASM_OPERANDS
1160 && GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1163 /* If there are any volatile insns between INSN and I3, reject, because
1164 they might affect machine state. */
1166 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1167 if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1170 /* If INSN or I2 contains an autoincrement or autodecrement,
1171 make sure that register is not used between there and I3,
1172 and not already used in I3 either.
1173 Also insist that I3 not be a jump; if it were one
1174 and the incremented register were spilled, we would lose. */
1177 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1178 if (REG_NOTE_KIND (link) == REG_INC
1179 && (GET_CODE (i3) == JUMP_INSN
1180 || reg_used_between_p (XEXP (link, 0), insn, i3)
1181 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1186 /* Don't combine an insn that follows a CC0-setting insn.
1187 An insn that uses CC0 must not be separated from the one that sets it.
1188 We do, however, allow I2 to follow a CC0-setting insn if that insn
1189 is passed as I1; in that case it will be deleted also.
1190 We also allow combining in this case if all the insns are adjacent
1191 because that would leave the two CC0 insns adjacent as well.
1192 It would be more logical to test whether CC0 occurs inside I1 or I2,
1193 but that would be much slower, and this ought to be equivalent. */
1195 p = prev_nonnote_insn (insn);
1196 if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
1201 /* If we get here, we have passed all the tests and the combination is
1210 /* Check if PAT is an insn - or a part of it - used to set up an
1211 argument for a function in a hard register. */
1214 sets_function_arg_p (rtx pat)
1219 switch (GET_CODE (pat))
1222 return sets_function_arg_p (PATTERN (pat));
1225 for (i = XVECLEN (pat, 0); --i >= 0;)
1226 if (sets_function_arg_p (XVECEXP (pat, 0, i)))
1232 inner_dest = SET_DEST (pat);
1233 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1234 || GET_CODE (inner_dest) == SUBREG
1235 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1236 inner_dest = XEXP (inner_dest, 0);
1238 return (GET_CODE (inner_dest) == REG
1239 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1240 && FUNCTION_ARG_REGNO_P (REGNO (inner_dest)));
1249 /* LOC is the location within I3 that contains its pattern or the component
1250 of a PARALLEL of the pattern. We validate that it is valid for combining.
1252 One problem is if I3 modifies its output, as opposed to replacing it
1253 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1254 so would produce an insn that is not equivalent to the original insns.
1258 (set (reg:DI 101) (reg:DI 100))
1259 (set (subreg:SI (reg:DI 101) 0) <foo>)
1261 This is NOT equivalent to:
1263 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1264 (set (reg:DI 101) (reg:DI 100))])
1266 Not only does this modify 100 (in which case it might still be valid
1267 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1269 We can also run into a problem if I2 sets a register that I1
1270 uses and I1 gets directly substituted into I3 (not via I2). In that
1271 case, we would be getting the wrong value of I2DEST into I3, so we
1272 must reject the combination. This case occurs when I2 and I1 both
1273 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1274 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1275 of a SET must prevent combination from occurring.
1277 Before doing the above check, we first try to expand a field assignment
1278 into a set of logical operations.
1280 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1281 we place a register that is both set and used within I3. If more than one
1282 such register is detected, we fail.
1284 Return 1 if the combination is valid, zero otherwise. */
1287 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest,
1288 int i1_not_in_src, rtx *pi3dest_killed)
1292 if (GET_CODE (x) == SET)
1295 rtx dest = SET_DEST (set);
1296 rtx src = SET_SRC (set);
1297 rtx inner_dest = dest;
1299 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1300 || GET_CODE (inner_dest) == SUBREG
1301 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1302 inner_dest = XEXP (inner_dest, 0);
1304 /* Check for the case where I3 modifies its output, as discussed
1305 above. We don't want to prevent pseudos from being combined
1306 into the address of a MEM, so only prevent the combination if
1307 i1 or i2 set the same MEM. */
1308 if ((inner_dest != dest &&
1309 (GET_CODE (inner_dest) != MEM
1310 || rtx_equal_p (i2dest, inner_dest)
1311 || (i1dest && rtx_equal_p (i1dest, inner_dest)))
1312 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1313 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1315 /* This is the same test done in can_combine_p except we can't test
1316 all_adjacent; we don't have to, since this instruction will stay
1317 in place, thus we are not considering increasing the lifetime of
1320 Also, if this insn sets a function argument, combining it with
1321 something that might need a spill could clobber a previous
1322 function argument; the all_adjacent test in can_combine_p also
1323 checks this; here, we do a more specific test for this case. */
1325 || (GET_CODE (inner_dest) == REG
1326 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1327 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1328 GET_MODE (inner_dest))))
1329 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1332 /* If DEST is used in I3, it is being killed in this insn,
1333 so record that for later.
1334 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1335 STACK_POINTER_REGNUM, since these are always considered to be
1336 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1337 if (pi3dest_killed && GET_CODE (dest) == REG
1338 && reg_referenced_p (dest, PATTERN (i3))
1339 && REGNO (dest) != FRAME_POINTER_REGNUM
1340 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1341 && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
1343 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1344 && (REGNO (dest) != ARG_POINTER_REGNUM
1345 || ! fixed_regs [REGNO (dest)])
1347 && REGNO (dest) != STACK_POINTER_REGNUM)
1349 if (*pi3dest_killed)
1352 *pi3dest_killed = dest;
1356 else if (GET_CODE (x) == PARALLEL)
1360 for (i = 0; i < XVECLEN (x, 0); i++)
1361 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1362 i1_not_in_src, pi3dest_killed))
1369 /* Return 1 if X is an arithmetic expression that contains a multiplication
1370 and division. We don't count multiplications by powers of two here. */
1373 contains_muldiv (rtx x)
1375 switch (GET_CODE (x))
1377 case MOD: case DIV: case UMOD: case UDIV:
1381 return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1382 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1384 switch (GET_RTX_CLASS (GET_CODE (x)))
1386 case 'c': case '<': case '2':
1387 return contains_muldiv (XEXP (x, 0))
1388 || contains_muldiv (XEXP (x, 1));
1391 return contains_muldiv (XEXP (x, 0));
1399 /* Determine whether INSN can be used in a combination. Return nonzero if
1400 not. This is used in try_combine to detect early some cases where we
1401 can't perform combinations. */
1404 cant_combine_insn_p (rtx insn)
1409 /* If this isn't really an insn, we can't do anything.
1410 This can occur when flow deletes an insn that it has merged into an
1411 auto-increment address. */
1412 if (! INSN_P (insn))
1415 /* Never combine loads and stores involving hard regs that are likely
1416 to be spilled. The register allocator can usually handle such
1417 reg-reg moves by tying. If we allow the combiner to make
1418 substitutions of likely-spilled regs, we may abort in reload.
1419 As an exception, we allow combinations involving fixed regs; these are
1420 not available to the register allocator so there's no risk involved. */
1422 set = single_set (insn);
1425 src = SET_SRC (set);
1426 dest = SET_DEST (set);
1427 if (GET_CODE (src) == SUBREG)
1428 src = SUBREG_REG (src);
1429 if (GET_CODE (dest) == SUBREG)
1430 dest = SUBREG_REG (dest);
1431 if (REG_P (src) && REG_P (dest)
1432 && ((REGNO (src) < FIRST_PSEUDO_REGISTER
1433 && ! fixed_regs[REGNO (src)]
1434 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src))))
1435 || (REGNO (dest) < FIRST_PSEUDO_REGISTER
1436 && ! fixed_regs[REGNO (dest)]
1437 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest))))))
1443 /* Try to combine the insns I1 and I2 into I3.
1444 Here I1 and I2 appear earlier than I3.
1445 I1 can be zero; then we combine just I2 into I3.
1447 If we are combining three insns and the resulting insn is not recognized,
1448 try splitting it into two insns. If that happens, I2 and I3 are retained
1449 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1452 Return 0 if the combination does not work. Then nothing is changed.
1453 If we did the combination, return the insn at which combine should
1456 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
1457 new direct jump instruction. */
1460 try_combine (rtx i3, rtx i2, rtx i1, int *new_direct_jump_p)
1462 /* New patterns for I3 and I2, respectively. */
1463 rtx newpat, newi2pat = 0;
1464 int substed_i2 = 0, substed_i1 = 0;
1465 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1466 int added_sets_1, added_sets_2;
1467 /* Total number of SETs to put into I3. */
1469 /* Nonzero is I2's body now appears in I3. */
1471 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1472 int insn_code_number, i2_code_number = 0, other_code_number = 0;
1473 /* Contains I3 if the destination of I3 is used in its source, which means
1474 that the old life of I3 is being killed. If that usage is placed into
1475 I2 and not in I3, a REG_DEAD note must be made. */
1476 rtx i3dest_killed = 0;
1477 /* SET_DEST and SET_SRC of I2 and I1. */
1478 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1479 /* PATTERN (I2), or a copy of it in certain cases. */
1481 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1482 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1483 int i1_feeds_i3 = 0;
1484 /* Notes that must be added to REG_NOTES in I3 and I2. */
1485 rtx new_i3_notes, new_i2_notes;
1486 /* Notes that we substituted I3 into I2 instead of the normal case. */
1487 int i3_subst_into_i2 = 0;
1488 /* Notes that I1, I2 or I3 is a MULT operation. */
1496 /* Exit early if one of the insns involved can't be used for
1498 if (cant_combine_insn_p (i3)
1499 || cant_combine_insn_p (i2)
1500 || (i1 && cant_combine_insn_p (i1))
1501 /* We also can't do anything if I3 has a
1502 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1505 /* ??? This gives worse code, and appears to be unnecessary, since no
1506 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1507 || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1513 undobuf.other_insn = 0;
1515 /* Reset the hard register usage information. */
1516 CLEAR_HARD_REG_SET (newpat_used_regs);
1518 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1519 code below, set I1 to be the earlier of the two insns. */
1520 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1521 temp = i1, i1 = i2, i2 = temp;
1523 added_links_insn = 0;
1525 /* First check for one important special-case that the code below will
1526 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1527 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1528 we may be able to replace that destination with the destination of I3.
1529 This occurs in the common code where we compute both a quotient and
1530 remainder into a structure, in which case we want to do the computation
1531 directly into the structure to avoid register-register copies.
1533 Note that this case handles both multiple sets in I2 and also
1534 cases where I2 has a number of CLOBBER or PARALLELs.
1536 We make very conservative checks below and only try to handle the
1537 most common cases of this. For example, we only handle the case
1538 where I2 and I3 are adjacent to avoid making difficult register
1541 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1542 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1543 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1544 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1545 && GET_CODE (PATTERN (i2)) == PARALLEL
1546 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1547 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1548 below would need to check what is inside (and reg_overlap_mentioned_p
1549 doesn't support those codes anyway). Don't allow those destinations;
1550 the resulting insn isn't likely to be recognized anyway. */
1551 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1552 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1553 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1554 SET_DEST (PATTERN (i3)))
1555 && next_real_insn (i2) == i3)
1557 rtx p2 = PATTERN (i2);
1559 /* Make sure that the destination of I3,
1560 which we are going to substitute into one output of I2,
1561 is not used within another output of I2. We must avoid making this:
1562 (parallel [(set (mem (reg 69)) ...)
1563 (set (reg 69) ...)])
1564 which is not well-defined as to order of actions.
1565 (Besides, reload can't handle output reloads for this.)
1567 The problem can also happen if the dest of I3 is a memory ref,
1568 if another dest in I2 is an indirect memory ref. */
1569 for (i = 0; i < XVECLEN (p2, 0); i++)
1570 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1571 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1572 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1573 SET_DEST (XVECEXP (p2, 0, i))))
1576 if (i == XVECLEN (p2, 0))
1577 for (i = 0; i < XVECLEN (p2, 0); i++)
1578 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1579 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1580 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1585 subst_low_cuid = INSN_CUID (i2);
1587 added_sets_2 = added_sets_1 = 0;
1588 i2dest = SET_SRC (PATTERN (i3));
1590 /* Replace the dest in I2 with our dest and make the resulting
1591 insn the new pattern for I3. Then skip to where we
1592 validate the pattern. Everything was set up above. */
1593 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1594 SET_DEST (PATTERN (i3)));
1597 i3_subst_into_i2 = 1;
1598 goto validate_replacement;
1602 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1603 one of those words to another constant, merge them by making a new
1606 && (temp = single_set (i2)) != 0
1607 && (GET_CODE (SET_SRC (temp)) == CONST_INT
1608 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
1609 && GET_CODE (SET_DEST (temp)) == REG
1610 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp))) == MODE_INT
1611 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp))) == 2 * UNITS_PER_WORD
1612 && GET_CODE (PATTERN (i3)) == SET
1613 && GET_CODE (SET_DEST (PATTERN (i3))) == SUBREG
1614 && SUBREG_REG (SET_DEST (PATTERN (i3))) == SET_DEST (temp)
1615 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3)))) == MODE_INT
1616 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3)))) == UNITS_PER_WORD
1617 && GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT)
1619 HOST_WIDE_INT lo, hi;
1621 if (GET_CODE (SET_SRC (temp)) == CONST_INT)
1622 lo = INTVAL (SET_SRC (temp)), hi = lo < 0 ? -1 : 0;
1625 lo = CONST_DOUBLE_LOW (SET_SRC (temp));
1626 hi = CONST_DOUBLE_HIGH (SET_SRC (temp));
1629 if (subreg_lowpart_p (SET_DEST (PATTERN (i3))))
1631 /* We don't handle the case of the target word being wider
1632 than a host wide int. */
1633 if (HOST_BITS_PER_WIDE_INT < BITS_PER_WORD)
1636 lo &= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1637 lo |= (INTVAL (SET_SRC (PATTERN (i3)))
1638 & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1640 else if (HOST_BITS_PER_WIDE_INT == BITS_PER_WORD)
1641 hi = INTVAL (SET_SRC (PATTERN (i3)));
1642 else if (HOST_BITS_PER_WIDE_INT >= 2 * BITS_PER_WORD)
1644 int sign = -(int) ((unsigned HOST_WIDE_INT) lo
1645 >> (HOST_BITS_PER_WIDE_INT - 1));
1647 lo &= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1648 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1649 lo |= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1650 (INTVAL (SET_SRC (PATTERN (i3)))));
1652 hi = lo < 0 ? -1 : 0;
1655 /* We don't handle the case of the higher word not fitting
1656 entirely in either hi or lo. */
1661 subst_low_cuid = INSN_CUID (i2);
1662 added_sets_2 = added_sets_1 = 0;
1663 i2dest = SET_DEST (temp);
1665 SUBST (SET_SRC (temp),
1666 immed_double_const (lo, hi, GET_MODE (SET_DEST (temp))));
1668 newpat = PATTERN (i2);
1669 goto validate_replacement;
1673 /* If we have no I1 and I2 looks like:
1674 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1676 make up a dummy I1 that is
1679 (set (reg:CC X) (compare:CC Y (const_int 0)))
1681 (We can ignore any trailing CLOBBERs.)
1683 This undoes a previous combination and allows us to match a branch-and-
1686 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1687 && XVECLEN (PATTERN (i2), 0) >= 2
1688 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1689 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1691 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1692 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1693 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1694 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1695 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1696 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1698 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1699 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1704 /* We make I1 with the same INSN_UID as I2. This gives it
1705 the same INSN_CUID for value tracking. Our fake I1 will
1706 never appear in the insn stream so giving it the same INSN_UID
1707 as I2 will not cause a problem. */
1709 i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
1710 BLOCK_FOR_INSN (i2), INSN_LOCATOR (i2),
1711 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
1714 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1715 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1716 SET_DEST (PATTERN (i1)));
1721 /* Verify that I2 and I1 are valid for combining. */
1722 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1723 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1729 /* Record whether I2DEST is used in I2SRC and similarly for the other
1730 cases. Knowing this will help in register status updating below. */
1731 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1732 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1733 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1735 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1737 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1739 /* Ensure that I3's pattern can be the destination of combines. */
1740 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1741 i1 && i2dest_in_i1src && i1_feeds_i3,
1748 /* See if any of the insns is a MULT operation. Unless one is, we will
1749 reject a combination that is, since it must be slower. Be conservative
1751 if (GET_CODE (i2src) == MULT
1752 || (i1 != 0 && GET_CODE (i1src) == MULT)
1753 || (GET_CODE (PATTERN (i3)) == SET
1754 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
1757 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1758 We used to do this EXCEPT in one case: I3 has a post-inc in an
1759 output operand. However, that exception can give rise to insns like
1761 which is a famous insn on the PDP-11 where the value of r3 used as the
1762 source was model-dependent. Avoid this sort of thing. */
1765 if (!(GET_CODE (PATTERN (i3)) == SET
1766 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1767 && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1768 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1769 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1770 /* It's not the exception. */
1773 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1774 if (REG_NOTE_KIND (link) == REG_INC
1775 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1777 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1784 /* See if the SETs in I1 or I2 need to be kept around in the merged
1785 instruction: whenever the value set there is still needed past I3.
1786 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1788 For the SET in I1, we have two cases: If I1 and I2 independently
1789 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1790 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1791 in I1 needs to be kept around unless I1DEST dies or is set in either
1792 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1793 I1DEST. If so, we know I1 feeds into I2. */
1795 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1798 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1799 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1801 /* If the set in I2 needs to be kept around, we must make a copy of
1802 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1803 PATTERN (I2), we are only substituting for the original I1DEST, not into
1804 an already-substituted copy. This also prevents making self-referential
1805 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1808 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1809 ? gen_rtx_SET (VOIDmode, i2dest, i2src)
1813 i2pat = copy_rtx (i2pat);
1817 /* Substitute in the latest insn for the regs set by the earlier ones. */
1819 maxreg = max_reg_num ();
1823 /* It is possible that the source of I2 or I1 may be performing an
1824 unneeded operation, such as a ZERO_EXTEND of something that is known
1825 to have the high part zero. Handle that case by letting subst look at
1826 the innermost one of them.
1828 Another way to do this would be to have a function that tries to
1829 simplify a single insn instead of merging two or more insns. We don't
1830 do this because of the potential of infinite loops and because
1831 of the potential extra memory required. However, doing it the way
1832 we are is a bit of a kludge and doesn't catch all cases.
1834 But only do this if -fexpensive-optimizations since it slows things down
1835 and doesn't usually win. */
1837 if (flag_expensive_optimizations)
1839 /* Pass pc_rtx so no substitutions are done, just simplifications.
1840 The cases that we are interested in here do not involve the few
1841 cases were is_replaced is checked. */
1844 subst_low_cuid = INSN_CUID (i1);
1845 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1849 subst_low_cuid = INSN_CUID (i2);
1850 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1855 /* Many machines that don't use CC0 have insns that can both perform an
1856 arithmetic operation and set the condition code. These operations will
1857 be represented as a PARALLEL with the first element of the vector
1858 being a COMPARE of an arithmetic operation with the constant zero.
1859 The second element of the vector will set some pseudo to the result
1860 of the same arithmetic operation. If we simplify the COMPARE, we won't
1861 match such a pattern and so will generate an extra insn. Here we test
1862 for this case, where both the comparison and the operation result are
1863 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1864 I2SRC. Later we will make the PARALLEL that contains I2. */
1866 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1867 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1868 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1869 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1871 #ifdef EXTRA_CC_MODES
1873 enum machine_mode compare_mode;
1876 newpat = PATTERN (i3);
1877 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1881 #ifdef EXTRA_CC_MODES
1882 /* See if a COMPARE with the operand we substituted in should be done
1883 with the mode that is currently being used. If not, do the same
1884 processing we do in `subst' for a SET; namely, if the destination
1885 is used only once, try to replace it with a register of the proper
1886 mode and also replace the COMPARE. */
1887 if (undobuf.other_insn == 0
1888 && (cc_use = find_single_use (SET_DEST (newpat), i3,
1889 &undobuf.other_insn))
1890 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
1892 != GET_MODE (SET_DEST (newpat))))
1894 unsigned int regno = REGNO (SET_DEST (newpat));
1895 rtx new_dest = gen_rtx_REG (compare_mode, regno);
1897 if (regno < FIRST_PSEUDO_REGISTER
1898 || (REG_N_SETS (regno) == 1 && ! added_sets_2
1899 && ! REG_USERVAR_P (SET_DEST (newpat))))
1901 if (regno >= FIRST_PSEUDO_REGISTER)
1902 SUBST (regno_reg_rtx[regno], new_dest);
1904 SUBST (SET_DEST (newpat), new_dest);
1905 SUBST (XEXP (*cc_use, 0), new_dest);
1906 SUBST (SET_SRC (newpat),
1907 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
1910 undobuf.other_insn = 0;
1917 n_occurrences = 0; /* `subst' counts here */
1919 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1920 need to make a unique copy of I2SRC each time we substitute it
1921 to avoid self-referential rtl. */
1923 subst_low_cuid = INSN_CUID (i2);
1924 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1925 ! i1_feeds_i3 && i1dest_in_i1src);
1928 /* Record whether i2's body now appears within i3's body. */
1929 i2_is_used = n_occurrences;
1932 /* If we already got a failure, don't try to do more. Otherwise,
1933 try to substitute in I1 if we have it. */
1935 if (i1 && GET_CODE (newpat) != CLOBBER)
1937 /* Before we can do this substitution, we must redo the test done
1938 above (see detailed comments there) that ensures that I1DEST
1939 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1941 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
1949 subst_low_cuid = INSN_CUID (i1);
1950 newpat = subst (newpat, i1dest, i1src, 0, 0);
1954 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1955 to count all the ways that I2SRC and I1SRC can be used. */
1956 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
1957 && i2_is_used + added_sets_2 > 1)
1958 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
1959 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
1961 /* Fail if we tried to make a new register (we used to abort, but there's
1962 really no reason to). */
1963 || max_reg_num () != maxreg
1964 /* Fail if we couldn't do something and have a CLOBBER. */
1965 || GET_CODE (newpat) == CLOBBER
1966 /* Fail if this new pattern is a MULT and we didn't have one before
1967 at the outer level. */
1968 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
1975 /* If the actions of the earlier insns must be kept
1976 in addition to substituting them into the latest one,
1977 we must make a new PARALLEL for the latest insn
1978 to hold additional the SETs. */
1980 if (added_sets_1 || added_sets_2)
1984 if (GET_CODE (newpat) == PARALLEL)
1986 rtvec old = XVEC (newpat, 0);
1987 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
1988 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
1989 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
1990 sizeof (old->elem[0]) * old->num_elem);
1995 total_sets = 1 + added_sets_1 + added_sets_2;
1996 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
1997 XVECEXP (newpat, 0, 0) = old;
2001 XVECEXP (newpat, 0, --total_sets)
2002 = (GET_CODE (PATTERN (i1)) == PARALLEL
2003 ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
2007 /* If there is no I1, use I2's body as is. We used to also not do
2008 the subst call below if I2 was substituted into I3,
2009 but that could lose a simplification. */
2011 XVECEXP (newpat, 0, --total_sets) = i2pat;
2013 /* See comment where i2pat is assigned. */
2014 XVECEXP (newpat, 0, --total_sets)
2015 = subst (i2pat, i1dest, i1src, 0, 0);
2019 /* We come here when we are replacing a destination in I2 with the
2020 destination of I3. */
2021 validate_replacement:
2023 /* Note which hard regs this insn has as inputs. */
2024 mark_used_regs_combine (newpat);
2026 /* Is the result of combination a valid instruction? */
2027 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2029 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2030 the second SET's destination is a register that is unused. In that case,
2031 we just need the first SET. This can occur when simplifying a divmod
2032 insn. We *must* test for this case here because the code below that
2033 splits two independent SETs doesn't handle this case correctly when it
2034 updates the register status. Also check the case where the first
2035 SET's destination is unused. That would not cause incorrect code, but
2036 does cause an unneeded insn to remain. */
2038 if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
2039 && XVECLEN (newpat, 0) == 2
2040 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2041 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2042 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
2043 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
2044 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
2045 && asm_noperands (newpat) < 0)
2047 newpat = XVECEXP (newpat, 0, 0);
2048 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2051 else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
2052 && XVECLEN (newpat, 0) == 2
2053 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2054 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2055 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
2056 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
2057 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
2058 && asm_noperands (newpat) < 0)
2060 newpat = XVECEXP (newpat, 0, 1);
2061 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2064 /* If we were combining three insns and the result is a simple SET
2065 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2066 insns. There are two ways to do this. It can be split using a
2067 machine-specific method (like when you have an addition of a large
2068 constant) or by combine in the function find_split_point. */
2070 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2071 && asm_noperands (newpat) < 0)
2073 rtx m_split, *split;
2074 rtx ni2dest = i2dest;
2076 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2077 use I2DEST as a scratch register will help. In the latter case,
2078 convert I2DEST to the mode of the source of NEWPAT if we can. */
2080 m_split = split_insns (newpat, i3);
2082 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2083 inputs of NEWPAT. */
2085 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2086 possible to try that as a scratch reg. This would require adding
2087 more code to make it work though. */
2089 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
2091 /* If I2DEST is a hard register or the only use of a pseudo,
2092 we can change its mode. */
2093 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
2094 && GET_MODE (SET_DEST (newpat)) != VOIDmode
2095 && GET_CODE (i2dest) == REG
2096 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2097 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2098 && ! REG_USERVAR_P (i2dest))))
2099 ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)),
2102 m_split = split_insns (gen_rtx_PARALLEL
2104 gen_rtvec (2, newpat,
2105 gen_rtx_CLOBBER (VOIDmode,
2108 /* If the split with the mode-changed register didn't work, try
2109 the original register. */
2110 if (! m_split && ni2dest != i2dest)
2113 m_split = split_insns (gen_rtx_PARALLEL
2115 gen_rtvec (2, newpat,
2116 gen_rtx_CLOBBER (VOIDmode,
2122 if (m_split && NEXT_INSN (m_split) == NULL_RTX)
2124 m_split = PATTERN (m_split);
2125 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
2126 if (insn_code_number >= 0)
2129 else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
2130 && (next_real_insn (i2) == i3
2131 || ! use_crosses_set_p (PATTERN (m_split), INSN_CUID (i2))))
2134 rtx newi3pat = PATTERN (NEXT_INSN (m_split));
2135 newi2pat = PATTERN (m_split);
2137 i3set = single_set (NEXT_INSN (m_split));
2138 i2set = single_set (m_split);
2140 /* In case we changed the mode of I2DEST, replace it in the
2141 pseudo-register table here. We can't do it above in case this
2142 code doesn't get executed and we do a split the other way. */
2144 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2145 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
2147 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2149 /* If I2 or I3 has multiple SETs, we won't know how to track
2150 register status, so don't use these insns. If I2's destination
2151 is used between I2 and I3, we also can't use these insns. */
2153 if (i2_code_number >= 0 && i2set && i3set
2154 && (next_real_insn (i2) == i3
2155 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
2156 insn_code_number = recog_for_combine (&newi3pat, i3,
2158 if (insn_code_number >= 0)
2161 /* It is possible that both insns now set the destination of I3.
2162 If so, we must show an extra use of it. */
2164 if (insn_code_number >= 0)
2166 rtx new_i3_dest = SET_DEST (i3set);
2167 rtx new_i2_dest = SET_DEST (i2set);
2169 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
2170 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
2171 || GET_CODE (new_i3_dest) == SUBREG)
2172 new_i3_dest = XEXP (new_i3_dest, 0);
2174 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
2175 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
2176 || GET_CODE (new_i2_dest) == SUBREG)
2177 new_i2_dest = XEXP (new_i2_dest, 0);
2179 if (GET_CODE (new_i3_dest) == REG
2180 && GET_CODE (new_i2_dest) == REG
2181 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
2182 REG_N_SETS (REGNO (new_i2_dest))++;
2186 /* If we can split it and use I2DEST, go ahead and see if that
2187 helps things be recognized. Verify that none of the registers
2188 are set between I2 and I3. */
2189 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
2191 && GET_CODE (i2dest) == REG
2193 /* We need I2DEST in the proper mode. If it is a hard register
2194 or the only use of a pseudo, we can change its mode. */
2195 && (GET_MODE (*split) == GET_MODE (i2dest)
2196 || GET_MODE (*split) == VOIDmode
2197 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2198 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2199 && ! REG_USERVAR_P (i2dest)))
2200 && (next_real_insn (i2) == i3
2201 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
2202 /* We can't overwrite I2DEST if its value is still used by
2204 && ! reg_referenced_p (i2dest, newpat))
2206 rtx newdest = i2dest;
2207 enum rtx_code split_code = GET_CODE (*split);
2208 enum machine_mode split_mode = GET_MODE (*split);
2210 /* Get NEWDEST as a register in the proper mode. We have already
2211 validated that we can do this. */
2212 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2214 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
2216 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2217 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
2220 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2221 an ASHIFT. This can occur if it was inside a PLUS and hence
2222 appeared to be a memory address. This is a kludge. */
2223 if (split_code == MULT
2224 && GET_CODE (XEXP (*split, 1)) == CONST_INT
2225 && INTVAL (XEXP (*split, 1)) > 0
2226 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
2228 SUBST (*split, gen_rtx_ASHIFT (split_mode,
2229 XEXP (*split, 0), GEN_INT (i)));
2230 /* Update split_code because we may not have a multiply
2232 split_code = GET_CODE (*split);
2235 #ifdef INSN_SCHEDULING
2236 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2237 be written as a ZERO_EXTEND. */
2238 if (split_code == SUBREG && GET_CODE (SUBREG_REG (*split)) == MEM)
2240 #ifdef LOAD_EXTEND_OP
2241 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
2242 what it really is. */
2243 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
2245 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
2246 SUBREG_REG (*split)));
2249 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
2250 SUBREG_REG (*split)));
2254 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
2255 SUBST (*split, newdest);
2256 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2258 /* If the split point was a MULT and we didn't have one before,
2259 don't use one now. */
2260 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
2261 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2265 /* Check for a case where we loaded from memory in a narrow mode and
2266 then sign extended it, but we need both registers. In that case,
2267 we have a PARALLEL with both loads from the same memory location.
2268 We can split this into a load from memory followed by a register-register
2269 copy. This saves at least one insn, more if register allocation can
2272 We cannot do this if the destination of the first assignment is a
2273 condition code register or cc0. We eliminate this case by making sure
2274 the SET_DEST and SET_SRC have the same mode.
2276 We cannot do this if the destination of the second assignment is
2277 a register that we have already assumed is zero-extended. Similarly
2278 for a SUBREG of such a register. */
2280 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2281 && GET_CODE (newpat) == PARALLEL
2282 && XVECLEN (newpat, 0) == 2
2283 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2284 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2285 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
2286 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
2287 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2288 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2289 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2290 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2292 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2293 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2294 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2295 (GET_CODE (temp) == REG
2296 && reg_nonzero_bits[REGNO (temp)] != 0
2297 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2298 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2299 && (reg_nonzero_bits[REGNO (temp)]
2300 != GET_MODE_MASK (word_mode))))
2301 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2302 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2303 (GET_CODE (temp) == REG
2304 && reg_nonzero_bits[REGNO (temp)] != 0
2305 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2306 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2307 && (reg_nonzero_bits[REGNO (temp)]
2308 != GET_MODE_MASK (word_mode)))))
2309 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2310 SET_SRC (XVECEXP (newpat, 0, 1)))
2311 && ! find_reg_note (i3, REG_UNUSED,
2312 SET_DEST (XVECEXP (newpat, 0, 0))))
2316 newi2pat = XVECEXP (newpat, 0, 0);
2317 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2318 newpat = XVECEXP (newpat, 0, 1);
2319 SUBST (SET_SRC (newpat),
2320 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest));
2321 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2323 if (i2_code_number >= 0)
2324 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2326 if (insn_code_number >= 0)
2331 /* If we will be able to accept this, we have made a change to the
2332 destination of I3. This can invalidate a LOG_LINKS pointing
2333 to I3. No other part of combine.c makes such a transformation.
2335 The new I3 will have a destination that was previously the
2336 destination of I1 or I2 and which was used in i2 or I3. Call
2337 distribute_links to make a LOG_LINK from the next use of
2338 that destination. */
2340 PATTERN (i3) = newpat;
2341 distribute_links (gen_rtx_INSN_LIST (VOIDmode, i3, NULL_RTX));
2343 /* I3 now uses what used to be its destination and which is
2344 now I2's destination. That means we need a LOG_LINK from
2345 I3 to I2. But we used to have one, so we still will.
2347 However, some later insn might be using I2's dest and have
2348 a LOG_LINK pointing at I3. We must remove this link.
2349 The simplest way to remove the link is to point it at I1,
2350 which we know will be a NOTE. */
2352 for (insn = NEXT_INSN (i3);
2353 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
2354 || insn != this_basic_block->next_bb->head);
2355 insn = NEXT_INSN (insn))
2357 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
2359 for (link = LOG_LINKS (insn); link;
2360 link = XEXP (link, 1))
2361 if (XEXP (link, 0) == i3)
2362 XEXP (link, 0) = i1;
2370 /* Similarly, check for a case where we have a PARALLEL of two independent
2371 SETs but we started with three insns. In this case, we can do the sets
2372 as two separate insns. This case occurs when some SET allows two
2373 other insns to combine, but the destination of that SET is still live. */
2375 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2376 && GET_CODE (newpat) == PARALLEL
2377 && XVECLEN (newpat, 0) == 2
2378 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2379 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2380 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2381 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2382 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2383 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2384 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2386 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2387 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2388 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2389 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2390 XVECEXP (newpat, 0, 0))
2391 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2392 XVECEXP (newpat, 0, 1))
2393 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
2394 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
2396 /* Normally, it doesn't matter which of the two is done first,
2397 but it does if one references cc0. In that case, it has to
2400 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2402 newi2pat = XVECEXP (newpat, 0, 0);
2403 newpat = XVECEXP (newpat, 0, 1);
2408 newi2pat = XVECEXP (newpat, 0, 1);
2409 newpat = XVECEXP (newpat, 0, 0);
2412 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2414 if (i2_code_number >= 0)
2415 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2418 /* If it still isn't recognized, fail and change things back the way they
2420 if ((insn_code_number < 0
2421 /* Is the result a reasonable ASM_OPERANDS? */
2422 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2428 /* If we had to change another insn, make sure it is valid also. */
2429 if (undobuf.other_insn)
2431 rtx other_pat = PATTERN (undobuf.other_insn);
2432 rtx new_other_notes;
2435 CLEAR_HARD_REG_SET (newpat_used_regs);
2437 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2440 if (other_code_number < 0 && ! check_asm_operands (other_pat))
2446 PATTERN (undobuf.other_insn) = other_pat;
2448 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2449 are still valid. Then add any non-duplicate notes added by
2450 recog_for_combine. */
2451 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2453 next = XEXP (note, 1);
2455 if (REG_NOTE_KIND (note) == REG_UNUSED
2456 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2458 if (GET_CODE (XEXP (note, 0)) == REG)
2459 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2461 remove_note (undobuf.other_insn, note);
2465 for (note = new_other_notes; note; note = XEXP (note, 1))
2466 if (GET_CODE (XEXP (note, 0)) == REG)
2467 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2469 distribute_notes (new_other_notes, undobuf.other_insn,
2470 undobuf.other_insn, NULL_RTX);
2473 /* If I2 is the setter CC0 and I3 is the user CC0 then check whether
2474 they are adjacent to each other or not. */
2476 rtx p = prev_nonnote_insn (i3);
2477 if (p && p != i2 && GET_CODE (p) == INSN && newi2pat
2478 && sets_cc0_p (newi2pat))
2486 /* We now know that we can do this combination. Merge the insns and
2487 update the status of registers and LOG_LINKS. */
2490 rtx i3notes, i2notes, i1notes = 0;
2491 rtx i3links, i2links, i1links = 0;
2495 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2497 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2498 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2500 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2502 /* Ensure that we do not have something that should not be shared but
2503 occurs multiple times in the new insns. Check this by first
2504 resetting all the `used' flags and then copying anything is shared. */
2506 reset_used_flags (i3notes);
2507 reset_used_flags (i2notes);
2508 reset_used_flags (i1notes);
2509 reset_used_flags (newpat);
2510 reset_used_flags (newi2pat);
2511 if (undobuf.other_insn)
2512 reset_used_flags (PATTERN (undobuf.other_insn));
2514 i3notes = copy_rtx_if_shared (i3notes);
2515 i2notes = copy_rtx_if_shared (i2notes);
2516 i1notes = copy_rtx_if_shared (i1notes);
2517 newpat = copy_rtx_if_shared (newpat);
2518 newi2pat = copy_rtx_if_shared (newi2pat);
2519 if (undobuf.other_insn)
2520 reset_used_flags (PATTERN (undobuf.other_insn));
2522 INSN_CODE (i3) = insn_code_number;
2523 PATTERN (i3) = newpat;
2525 if (GET_CODE (i3) == CALL_INSN && CALL_INSN_FUNCTION_USAGE (i3))
2527 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
2529 reset_used_flags (call_usage);
2530 call_usage = copy_rtx (call_usage);
2533 replace_rtx (call_usage, i2dest, i2src);
2536 replace_rtx (call_usage, i1dest, i1src);
2538 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
2541 if (undobuf.other_insn)
2542 INSN_CODE (undobuf.other_insn) = other_code_number;
2544 /* We had one special case above where I2 had more than one set and
2545 we replaced a destination of one of those sets with the destination
2546 of I3. In that case, we have to update LOG_LINKS of insns later
2547 in this basic block. Note that this (expensive) case is rare.
2549 Also, in this case, we must pretend that all REG_NOTEs for I2
2550 actually came from I3, so that REG_UNUSED notes from I2 will be
2551 properly handled. */
2553 if (i3_subst_into_i2)
2555 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2556 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != USE
2557 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
2558 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2559 && ! find_reg_note (i2, REG_UNUSED,
2560 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2561 for (temp = NEXT_INSN (i2);
2562 temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
2563 || this_basic_block->head != temp);
2564 temp = NEXT_INSN (temp))
2565 if (temp != i3 && INSN_P (temp))
2566 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2567 if (XEXP (link, 0) == i2)
2568 XEXP (link, 0) = i3;
2573 while (XEXP (link, 1))
2574 link = XEXP (link, 1);
2575 XEXP (link, 1) = i2notes;
2589 INSN_CODE (i2) = i2_code_number;
2590 PATTERN (i2) = newi2pat;
2594 PUT_CODE (i2, NOTE);
2595 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
2596 NOTE_SOURCE_FILE (i2) = 0;
2603 PUT_CODE (i1, NOTE);
2604 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
2605 NOTE_SOURCE_FILE (i1) = 0;
2608 /* Get death notes for everything that is now used in either I3 or
2609 I2 and used to die in a previous insn. If we built two new
2610 patterns, move from I1 to I2 then I2 to I3 so that we get the
2611 proper movement on registers that I2 modifies. */
2615 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
2616 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
2619 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
2622 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2624 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX);
2626 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX);
2628 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX);
2630 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX);
2632 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2633 know these are REG_UNUSED and want them to go to the desired insn,
2634 so we always pass it as i3. We have not counted the notes in
2635 reg_n_deaths yet, so we need to do so now. */
2637 if (newi2pat && new_i2_notes)
2639 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2640 if (GET_CODE (XEXP (temp, 0)) == REG)
2641 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2643 distribute_notes (new_i2_notes, i2, i2, NULL_RTX);
2648 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2649 if (GET_CODE (XEXP (temp, 0)) == REG)
2650 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2652 distribute_notes (new_i3_notes, i3, i3, NULL_RTX);
2655 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2656 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2657 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2658 in that case, it might delete I2. Similarly for I2 and I1.
2659 Show an additional death due to the REG_DEAD note we make here. If
2660 we discard it in distribute_notes, we will decrement it again. */
2664 if (GET_CODE (i3dest_killed) == REG)
2665 REG_N_DEATHS (REGNO (i3dest_killed))++;
2667 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
2668 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2670 NULL_RTX, i2, NULL_RTX);
2672 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2674 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX);
2677 if (i2dest_in_i2src)
2679 if (GET_CODE (i2dest) == REG)
2680 REG_N_DEATHS (REGNO (i2dest))++;
2682 if (newi2pat && reg_set_p (i2dest, newi2pat))
2683 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2684 NULL_RTX, i2, NULL_RTX);
2686 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2687 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX);
2690 if (i1dest_in_i1src)
2692 if (GET_CODE (i1dest) == REG)
2693 REG_N_DEATHS (REGNO (i1dest))++;
2695 if (newi2pat && reg_set_p (i1dest, newi2pat))
2696 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2697 NULL_RTX, i2, NULL_RTX);
2699 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2700 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX);
2703 distribute_links (i3links);
2704 distribute_links (i2links);
2705 distribute_links (i1links);
2707 if (GET_CODE (i2dest) == REG)
2710 rtx i2_insn = 0, i2_val = 0, set;
2712 /* The insn that used to set this register doesn't exist, and
2713 this life of the register may not exist either. See if one of
2714 I3's links points to an insn that sets I2DEST. If it does,
2715 that is now the last known value for I2DEST. If we don't update
2716 this and I2 set the register to a value that depended on its old
2717 contents, we will get confused. If this insn is used, thing
2718 will be set correctly in combine_instructions. */
2720 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2721 if ((set = single_set (XEXP (link, 0))) != 0
2722 && rtx_equal_p (i2dest, SET_DEST (set)))
2723 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2725 record_value_for_reg (i2dest, i2_insn, i2_val);
2727 /* If the reg formerly set in I2 died only once and that was in I3,
2728 zero its use count so it won't make `reload' do any work. */
2730 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
2731 && ! i2dest_in_i2src)
2733 regno = REGNO (i2dest);
2734 REG_N_SETS (regno)--;
2738 if (i1 && GET_CODE (i1dest) == REG)
2741 rtx i1_insn = 0, i1_val = 0, set;
2743 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2744 if ((set = single_set (XEXP (link, 0))) != 0
2745 && rtx_equal_p (i1dest, SET_DEST (set)))
2746 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2748 record_value_for_reg (i1dest, i1_insn, i1_val);
2750 regno = REGNO (i1dest);
2751 if (! added_sets_1 && ! i1dest_in_i1src)
2752 REG_N_SETS (regno)--;
2755 /* Update reg_nonzero_bits et al for any changes that may have been made
2756 to this insn. The order of set_nonzero_bits_and_sign_copies() is
2757 important. Because newi2pat can affect nonzero_bits of newpat */
2759 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
2760 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
2762 /* Set new_direct_jump_p if a new return or simple jump instruction
2765 If I3 is now an unconditional jump, ensure that it has a
2766 BARRIER following it since it may have initially been a
2767 conditional jump. It may also be the last nonnote insn. */
2769 if (returnjump_p (i3) || any_uncondjump_p (i3))
2771 *new_direct_jump_p = 1;
2773 if ((temp = next_nonnote_insn (i3)) == NULL_RTX
2774 || GET_CODE (temp) != BARRIER)
2775 emit_barrier_after (i3);
2778 if (undobuf.other_insn != NULL_RTX
2779 && (returnjump_p (undobuf.other_insn)
2780 || any_uncondjump_p (undobuf.other_insn)))
2782 *new_direct_jump_p = 1;
2784 if ((temp = next_nonnote_insn (undobuf.other_insn)) == NULL_RTX
2785 || GET_CODE (temp) != BARRIER)
2786 emit_barrier_after (undobuf.other_insn);
2789 /* An NOOP jump does not need barrier, but it does need cleaning up
2791 if (GET_CODE (newpat) == SET
2792 && SET_SRC (newpat) == pc_rtx
2793 && SET_DEST (newpat) == pc_rtx)
2794 *new_direct_jump_p = 1;
2797 combine_successes++;
2800 if (added_links_insn
2801 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
2802 && INSN_CUID (added_links_insn) < INSN_CUID (i3))
2803 return added_links_insn;
2805 return newi2pat ? i2 : i3;
2808 /* Undo all the modifications recorded in undobuf. */
2813 struct undo *undo, *next;
2815 for (undo = undobuf.undos; undo; undo = next)
2819 *undo->where.i = undo->old_contents.i;
2821 *undo->where.r = undo->old_contents.r;
2823 undo->next = undobuf.frees;
2824 undobuf.frees = undo;
2830 /* We've committed to accepting the changes we made. Move all
2831 of the undos to the free list. */
2836 struct undo *undo, *next;
2838 for (undo = undobuf.undos; undo; undo = next)
2841 undo->next = undobuf.frees;
2842 undobuf.frees = undo;
2848 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2849 where we have an arithmetic expression and return that point. LOC will
2852 try_combine will call this function to see if an insn can be split into
2856 find_split_point (rtx *loc, rtx insn)
2859 enum rtx_code code = GET_CODE (x);
2861 unsigned HOST_WIDE_INT len = 0;
2862 HOST_WIDE_INT pos = 0;
2864 rtx inner = NULL_RTX;
2866 /* First special-case some codes. */
2870 #ifdef INSN_SCHEDULING
2871 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2873 if (GET_CODE (SUBREG_REG (x)) == MEM)
2876 return find_split_point (&SUBREG_REG (x), insn);
2880 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2881 using LO_SUM and HIGH. */
2882 if (GET_CODE (XEXP (x, 0)) == CONST
2883 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
2886 gen_rtx_LO_SUM (Pmode,
2887 gen_rtx_HIGH (Pmode, XEXP (x, 0)),
2889 return &XEXP (XEXP (x, 0), 0);
2893 /* If we have a PLUS whose second operand is a constant and the
2894 address is not valid, perhaps will can split it up using
2895 the machine-specific way to split large constants. We use
2896 the first pseudo-reg (one of the virtual regs) as a placeholder;
2897 it will not remain in the result. */
2898 if (GET_CODE (XEXP (x, 0)) == PLUS
2899 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2900 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
2902 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
2903 rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
2906 /* This should have produced two insns, each of which sets our
2907 placeholder. If the source of the second is a valid address,
2908 we can make put both sources together and make a split point
2912 && NEXT_INSN (seq) != NULL_RTX
2913 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
2914 && GET_CODE (seq) == INSN
2915 && GET_CODE (PATTERN (seq)) == SET
2916 && SET_DEST (PATTERN (seq)) == reg
2917 && ! reg_mentioned_p (reg,
2918 SET_SRC (PATTERN (seq)))
2919 && GET_CODE (NEXT_INSN (seq)) == INSN
2920 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
2921 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
2922 && memory_address_p (GET_MODE (x),
2923 SET_SRC (PATTERN (NEXT_INSN (seq)))))
2925 rtx src1 = SET_SRC (PATTERN (seq));
2926 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
2928 /* Replace the placeholder in SRC2 with SRC1. If we can
2929 find where in SRC2 it was placed, that can become our
2930 split point and we can replace this address with SRC2.
2931 Just try two obvious places. */
2933 src2 = replace_rtx (src2, reg, src1);
2935 if (XEXP (src2, 0) == src1)
2936 split = &XEXP (src2, 0);
2937 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
2938 && XEXP (XEXP (src2, 0), 0) == src1)
2939 split = &XEXP (XEXP (src2, 0), 0);
2943 SUBST (XEXP (x, 0), src2);
2948 /* If that didn't work, perhaps the first operand is complex and
2949 needs to be computed separately, so make a split point there.
2950 This will occur on machines that just support REG + CONST
2951 and have a constant moved through some previous computation. */
2953 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o'
2954 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
2955 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0))))
2957 return &XEXP (XEXP (x, 0), 0);
2963 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2964 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2965 we need to put the operand into a register. So split at that
2968 if (SET_DEST (x) == cc0_rtx
2969 && GET_CODE (SET_SRC (x)) != COMPARE
2970 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
2971 && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
2972 && ! (GET_CODE (SET_SRC (x)) == SUBREG
2973 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
2974 return &SET_SRC (x);
2977 /* See if we can split SET_SRC as it stands. */
2978 split = find_split_point (&SET_SRC (x), insn);
2979 if (split && split != &SET_SRC (x))
2982 /* See if we can split SET_DEST as it stands. */
2983 split = find_split_point (&SET_DEST (x), insn);
2984 if (split && split != &SET_DEST (x))
2987 /* See if this is a bitfield assignment with everything constant. If
2988 so, this is an IOR of an AND, so split it into that. */
2989 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
2990 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
2991 <= HOST_BITS_PER_WIDE_INT)
2992 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
2993 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
2994 && GET_CODE (SET_SRC (x)) == CONST_INT
2995 && ((INTVAL (XEXP (SET_DEST (x), 1))
2996 + INTVAL (XEXP (SET_DEST (x), 2)))
2997 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
2998 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
3000 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
3001 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
3002 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
3003 rtx dest = XEXP (SET_DEST (x), 0);
3004 enum machine_mode mode = GET_MODE (dest);
3005 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
3007 if (BITS_BIG_ENDIAN)
3008 pos = GET_MODE_BITSIZE (mode) - len - pos;
3012 gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
3015 gen_binary (IOR, mode,
3016 gen_binary (AND, mode, dest,
3017 gen_int_mode (~(mask << pos),
3019 GEN_INT (src << pos)));
3021 SUBST (SET_DEST (x), dest);
3023 split = find_split_point (&SET_SRC (x), insn);
3024 if (split && split != &SET_SRC (x))
3028 /* Otherwise, see if this is an operation that we can split into two.
3029 If so, try to split that. */
3030 code = GET_CODE (SET_SRC (x));
3035 /* If we are AND'ing with a large constant that is only a single
3036 bit and the result is only being used in a context where we
3037 need to know if it is zero or nonzero, replace it with a bit
3038 extraction. This will avoid the large constant, which might
3039 have taken more than one insn to make. If the constant were
3040 not a valid argument to the AND but took only one insn to make,
3041 this is no worse, but if it took more than one insn, it will
3044 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3045 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
3046 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
3047 && GET_CODE (SET_DEST (x)) == REG
3048 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
3049 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
3050 && XEXP (*split, 0) == SET_DEST (x)
3051 && XEXP (*split, 1) == const0_rtx)
3053 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
3054 XEXP (SET_SRC (x), 0),
3055 pos, NULL_RTX, 1, 1, 0, 0);
3056 if (extraction != 0)
3058 SUBST (SET_SRC (x), extraction);
3059 return find_split_point (loc, insn);
3065 /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3066 is known to be on, this can be converted into a NEG of a shift. */
3067 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
3068 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
3069 && 1 <= (pos = exact_log2
3070 (nonzero_bits (XEXP (SET_SRC (x), 0),
3071 GET_MODE (XEXP (SET_SRC (x), 0))))))
3073 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
3077 gen_rtx_LSHIFTRT (mode,
3078 XEXP (SET_SRC (x), 0),
3081 split = find_split_point (&SET_SRC (x), insn);
3082 if (split && split != &SET_SRC (x))
3088 inner = XEXP (SET_SRC (x), 0);
3090 /* We can't optimize if either mode is a partial integer
3091 mode as we don't know how many bits are significant
3093 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
3094 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
3098 len = GET_MODE_BITSIZE (GET_MODE (inner));
3104 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3105 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
3107 inner = XEXP (SET_SRC (x), 0);
3108 len = INTVAL (XEXP (SET_SRC (x), 1));
3109 pos = INTVAL (XEXP (SET_SRC (x), 2));
3111 if (BITS_BIG_ENDIAN)
3112 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
3113 unsignedp = (code == ZERO_EXTRACT);
3121 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
3123 enum machine_mode mode = GET_MODE (SET_SRC (x));
3125 /* For unsigned, we have a choice of a shift followed by an
3126 AND or two shifts. Use two shifts for field sizes where the
3127 constant might be too large. We assume here that we can
3128 always at least get 8-bit constants in an AND insn, which is
3129 true for every current RISC. */
3131 if (unsignedp && len <= 8)
3136 (mode, gen_lowpart_for_combine (mode, inner),
3138 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
3140 split = find_split_point (&SET_SRC (x), insn);
3141 if (split && split != &SET_SRC (x))
3148 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
3149 gen_rtx_ASHIFT (mode,
3150 gen_lowpart_for_combine (mode, inner),
3151 GEN_INT (GET_MODE_BITSIZE (mode)
3153 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
3155 split = find_split_point (&SET_SRC (x), insn);
3156 if (split && split != &SET_SRC (x))
3161 /* See if this is a simple operation with a constant as the second
3162 operand. It might be that this constant is out of range and hence
3163 could be used as a split point. */
3164 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3165 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3166 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
3167 && CONSTANT_P (XEXP (SET_SRC (x), 1))
3168 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
3169 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
3170 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
3172 return &XEXP (SET_SRC (x), 1);
3174 /* Finally, see if this is a simple operation with its first operand
3175 not in a register. The operation might require this operand in a
3176 register, so return it as a split point. We can always do this
3177 because if the first operand were another operation, we would have
3178 already found it as a split point. */
3179 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3180 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3181 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
3182 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
3183 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
3184 return &XEXP (SET_SRC (x), 0);
3190 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3191 it is better to write this as (not (ior A B)) so we can split it.
3192 Similarly for IOR. */
3193 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
3196 gen_rtx_NOT (GET_MODE (x),
3197 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
3199 XEXP (XEXP (x, 0), 0),
3200 XEXP (XEXP (x, 1), 0))));
3201 return find_split_point (loc, insn);
3204 /* Many RISC machines have a large set of logical insns. If the
3205 second operand is a NOT, put it first so we will try to split the
3206 other operand first. */
3207 if (GET_CODE (XEXP (x, 1)) == NOT)
3209 rtx tem = XEXP (x, 0);
3210 SUBST (XEXP (x, 0), XEXP (x, 1));
3211 SUBST (XEXP (x, 1), tem);
3219 /* Otherwise, select our actions depending on our rtx class. */
3220 switch (GET_RTX_CLASS (code))
3222 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3224 split = find_split_point (&XEXP (x, 2), insn);
3227 /* ... fall through ... */
3231 split = find_split_point (&XEXP (x, 1), insn);
3234 /* ... fall through ... */
3236 /* Some machines have (and (shift ...) ...) insns. If X is not
3237 an AND, but XEXP (X, 0) is, use it as our split point. */
3238 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
3239 return &XEXP (x, 0);
3241 split = find_split_point (&XEXP (x, 0), insn);
3247 /* Otherwise, we don't have a split point. */
3251 /* Throughout X, replace FROM with TO, and return the result.
3252 The result is TO if X is FROM;
3253 otherwise the result is X, but its contents may have been modified.
3254 If they were modified, a record was made in undobuf so that
3255 undo_all will (among other things) return X to its original state.
3257 If the number of changes necessary is too much to record to undo,
3258 the excess changes are not made, so the result is invalid.
3259 The changes already made can still be undone.
3260 undobuf.num_undo is incremented for such changes, so by testing that
3261 the caller can tell whether the result is valid.
3263 `n_occurrences' is incremented each time FROM is replaced.
3265 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
3267 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
3268 by copying if `n_occurrences' is nonzero. */
3271 subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy)
3273 enum rtx_code code = GET_CODE (x);
3274 enum machine_mode op0_mode = VOIDmode;
3279 /* Two expressions are equal if they are identical copies of a shared
3280 RTX or if they are both registers with the same register number
3283 #define COMBINE_RTX_EQUAL_P(X,Y) \
3285 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3286 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3288 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3291 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3294 /* If X and FROM are the same register but different modes, they will
3295 not have been seen as equal above. However, flow.c will make a
3296 LOG_LINKS entry for that case. If we do nothing, we will try to
3297 rerecognize our original insn and, when it succeeds, we will
3298 delete the feeding insn, which is incorrect.
3300 So force this insn not to match in this (rare) case. */
3301 if (! in_dest && code == REG && GET_CODE (from) == REG
3302 && REGNO (x) == REGNO (from))
3303 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
3305 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3306 of which may contain things that can be combined. */
3307 if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
3310 /* It is possible to have a subexpression appear twice in the insn.
3311 Suppose that FROM is a register that appears within TO.
3312 Then, after that subexpression has been scanned once by `subst',
3313 the second time it is scanned, TO may be found. If we were
3314 to scan TO here, we would find FROM within it and create a
3315 self-referent rtl structure which is completely wrong. */
3316 if (COMBINE_RTX_EQUAL_P (x, to))
3319 /* Parallel asm_operands need special attention because all of the
3320 inputs are shared across the arms. Furthermore, unsharing the
3321 rtl results in recognition failures. Failure to handle this case
3322 specially can result in circular rtl.
3324 Solve this by doing a normal pass across the first entry of the
3325 parallel, and only processing the SET_DESTs of the subsequent
3328 if (code == PARALLEL
3329 && GET_CODE (XVECEXP (x, 0, 0)) == SET
3330 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
3332 new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3334 /* If this substitution failed, this whole thing fails. */
3335 if (GET_CODE (new) == CLOBBER
3336 && XEXP (new, 0) == const0_rtx)
3339 SUBST (XVECEXP (x, 0, 0), new);
3341 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
3343 rtx dest = SET_DEST (XVECEXP (x, 0, i));
3345 if (GET_CODE (dest) != REG
3346 && GET_CODE (dest) != CC0
3347 && GET_CODE (dest) != PC)
3349 new = subst (dest, from, to, 0, unique_copy);
3351 /* If this substitution failed, this whole thing fails. */
3352 if (GET_CODE (new) == CLOBBER
3353 && XEXP (new, 0) == const0_rtx)
3356 SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
3362 len = GET_RTX_LENGTH (code);
3363 fmt = GET_RTX_FORMAT (code);
3365 /* We don't need to process a SET_DEST that is a register, CC0,
3366 or PC, so set up to skip this common case. All other cases
3367 where we want to suppress replacing something inside a
3368 SET_SRC are handled via the IN_DEST operand. */
3370 && (GET_CODE (SET_DEST (x)) == REG
3371 || GET_CODE (SET_DEST (x)) == CC0
3372 || GET_CODE (SET_DEST (x)) == PC))
3375 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3378 op0_mode = GET_MODE (XEXP (x, 0));
3380 for (i = 0; i < len; i++)
3385 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3387 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3389 new = (unique_copy && n_occurrences
3390 ? copy_rtx (to) : to);
3395 new = subst (XVECEXP (x, i, j), from, to, 0,
3398 /* If this substitution failed, this whole thing
3400 if (GET_CODE (new) == CLOBBER
3401 && XEXP (new, 0) == const0_rtx)
3405 SUBST (XVECEXP (x, i, j), new);
3408 else if (fmt[i] == 'e')
3410 /* If this is a register being set, ignore it. */
3413 && (code == SUBREG || code == STRICT_LOW_PART
3414 || code == ZERO_EXTRACT)
3416 && GET_CODE (new) == REG)
3419 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
3421 /* In general, don't install a subreg involving two
3422 modes not tieable. It can worsen register
3423 allocation, and can even make invalid reload
3424 insns, since the reg inside may need to be copied
3425 from in the outside mode, and that may be invalid
3426 if it is an fp reg copied in integer mode.
3428 We allow two exceptions to this: It is valid if
3429 it is inside another SUBREG and the mode of that
3430 SUBREG and the mode of the inside of TO is
3431 tieable and it is valid if X is a SET that copies
3434 if (GET_CODE (to) == SUBREG
3435 && ! MODES_TIEABLE_P (GET_MODE (to),
3436 GET_MODE (SUBREG_REG (to)))
3437 && ! (code == SUBREG
3438 && MODES_TIEABLE_P (GET_MODE (x),
3439 GET_MODE (SUBREG_REG (to))))
3441 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
3444 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3446 #ifdef CANNOT_CHANGE_MODE_CLASS
3448 && GET_CODE (to) == REG
3449 && REGNO (to) < FIRST_PSEUDO_REGISTER
3450 && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
3453 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3456 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3460 /* If we are in a SET_DEST, suppress most cases unless we
3461 have gone inside a MEM, in which case we want to
3462 simplify the address. We assume here that things that
3463 are actually part of the destination have their inner
3464 parts in the first expression. This is true for SUBREG,
3465 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3466 things aside from REG and MEM that should appear in a
3468 new = subst (XEXP (x, i), from, to,
3470 && (code == SUBREG || code == STRICT_LOW_PART
3471 || code == ZERO_EXTRACT))
3473 && i == 0), unique_copy);
3475 /* If we found that we will have to reject this combination,
3476 indicate that by returning the CLOBBER ourselves, rather than
3477 an expression containing it. This will speed things up as
3478 well as prevent accidents where two CLOBBERs are considered
3479 to be equal, thus producing an incorrect simplification. */
3481 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3484 if (GET_CODE (x) == SUBREG
3485 && (GET_CODE (new) == CONST_INT
3486 || GET_CODE (new) == CONST_DOUBLE))
3488 enum machine_mode mode = GET_MODE (x);
3490 x = simplify_subreg (GET_MODE (x), new,
3491 GET_MODE (SUBREG_REG (x)),
3494 x = gen_rtx_CLOBBER (mode, const0_rtx);
3496 else if (GET_CODE (new) == CONST_INT
3497 && GET_CODE (x) == ZERO_EXTEND)
3499 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
3500 new, GET_MODE (XEXP (x, 0)));
3505 SUBST (XEXP (x, i), new);
3510 /* Try to simplify X. If the simplification changed the code, it is likely
3511 that further simplification will help, so loop, but limit the number
3512 of repetitions that will be performed. */
3514 for (i = 0; i < 4; i++)
3516 /* If X is sufficiently simple, don't bother trying to do anything
3518 if (code != CONST_INT && code != REG && code != CLOBBER)
3519 x = combine_simplify_rtx (x, op0_mode, i == 3, in_dest);
3521 if (GET_CODE (x) == code)
3524 code = GET_CODE (x);
3526 /* We no longer know the original mode of operand 0 since we
3527 have changed the form of X) */
3528 op0_mode = VOIDmode;
3534 /* Simplify X, a piece of RTL. We just operate on the expression at the
3535 outer level; call `subst' to simplify recursively. Return the new
3538 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3539 will be the iteration even if an expression with a code different from
3540 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3543 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int last,
3546 enum rtx_code code = GET_CODE (x);
3547 enum machine_mode mode = GET_MODE (x);
3552 /* If this is a commutative operation, put a constant last and a complex
3553 expression first. We don't need to do this for comparisons here. */
3554 if (GET_RTX_CLASS (code) == 'c'
3555 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
3558 SUBST (XEXP (x, 0), XEXP (x, 1));
3559 SUBST (XEXP (x, 1), temp);
3562 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3563 sign extension of a PLUS with a constant, reverse the order of the sign
3564 extension and the addition. Note that this not the same as the original
3565 code, but overflow is undefined for signed values. Also note that the
3566 PLUS will have been partially moved "inside" the sign-extension, so that
3567 the first operand of X will really look like:
3568 (ashiftrt (plus (ashift A C4) C5) C4).
3570 (plus (ashiftrt (ashift A C4) C2) C4)
3571 and replace the first operand of X with that expression. Later parts
3572 of this function may simplify the expression further.
3574 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3575 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3576 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3578 We do this to simplify address expressions. */
3580 if ((code == PLUS || code == MINUS || code == MULT)
3581 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3582 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
3583 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
3584 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
3585 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3586 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
3587 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3588 && (temp = simplify_binary_operation (ASHIFTRT, mode,
3589 XEXP (XEXP (XEXP (x, 0), 0), 1),
3590 XEXP (XEXP (x, 0), 1))) != 0)
3593 = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3594 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
3595 INTVAL (XEXP (XEXP (x, 0), 1)));
3597 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
3598 INTVAL (XEXP (XEXP (x, 0), 1)));
3600 SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
3603 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3604 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3605 things. Check for cases where both arms are testing the same
3608 Don't do anything if all operands are very simple. */
3610 if (((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c'
3611 || GET_RTX_CLASS (code) == '<')
3612 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3613 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3614 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3616 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o'
3617 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3618 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 1))))
3620 || (GET_RTX_CLASS (code) == '1'
3621 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3622 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3623 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3626 rtx cond, true_rtx, false_rtx;
3628 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
3630 /* If everything is a comparison, what we have is highly unlikely
3631 to be simpler, so don't use it. */
3632 && ! (GET_RTX_CLASS (code) == '<'
3633 && (GET_RTX_CLASS (GET_CODE (true_rtx)) == '<'
3634 || GET_RTX_CLASS (GET_CODE (false_rtx)) == '<')))
3636 rtx cop1 = const0_rtx;
3637 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3639 if (cond_code == NE && GET_RTX_CLASS (GET_CODE (cond)) == '<')
3642 /* Simplify the alternative arms; this may collapse the true and
3643 false arms to store-flag values. */
3644 true_rtx = subst (true_rtx, pc_rtx, pc_rtx, 0, 0);
3645 false_rtx = subst (false_rtx, pc_rtx, pc_rtx, 0, 0);
3647 /* If true_rtx and false_rtx are not general_operands, an if_then_else
3648 is unlikely to be simpler. */
3649 if (general_operand (true_rtx, VOIDmode)
3650 && general_operand (false_rtx, VOIDmode))
3652 enum rtx_code reversed;
3654 /* Restarting if we generate a store-flag expression will cause
3655 us to loop. Just drop through in this case. */
3657 /* If the result values are STORE_FLAG_VALUE and zero, we can
3658 just make the comparison operation. */
3659 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
3660 x = gen_binary (cond_code, mode, cond, cop1);
3661 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
3662 && ((reversed = reversed_comparison_code_parts
3663 (cond_code, cond, cop1, NULL))
3665 x = gen_binary (reversed, mode, cond, cop1);
3667 /* Likewise, we can make the negate of a comparison operation
3668 if the result values are - STORE_FLAG_VALUE and zero. */
3669 else if (GET_CODE (true_rtx) == CONST_INT
3670 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
3671 && false_rtx == const0_rtx)
3672 x = simplify_gen_unary (NEG, mode,
3673 gen_binary (cond_code, mode, cond,
3676 else if (GET_CODE (false_rtx) == CONST_INT
3677 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
3678 && true_rtx == const0_rtx
3679 && ((reversed = reversed_comparison_code_parts
3680 (cond_code, cond, cop1, NULL))
3682 x = simplify_gen_unary (NEG, mode,
3683 gen_binary (reversed, mode,
3687 return gen_rtx_IF_THEN_ELSE (mode,
3688 gen_binary (cond_code, VOIDmode,
3690 true_rtx, false_rtx);
3692 code = GET_CODE (x);
3693 op0_mode = VOIDmode;
3698 /* Try to fold this expression in case we have constants that weren't
3701 switch (GET_RTX_CLASS (code))
3704 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
3708 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
3709 if (cmp_mode == VOIDmode)
3711 cmp_mode = GET_MODE (XEXP (x, 1));
3712 if (cmp_mode == VOIDmode)
3713 cmp_mode = op0_mode;
3715 temp = simplify_relational_operation (code, cmp_mode,
3716 XEXP (x, 0), XEXP (x, 1));
3718 #ifdef FLOAT_STORE_FLAG_VALUE
3719 if (temp != 0 && GET_MODE_CLASS (mode) == MODE_FLOAT)
3721 if (temp == const0_rtx)
3722 temp = CONST0_RTX (mode);
3724 temp = CONST_DOUBLE_FROM_REAL_VALUE (FLOAT_STORE_FLAG_VALUE (mode),
3731 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3735 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
3736 XEXP (x, 1), XEXP (x, 2));
3743 code = GET_CODE (temp);
3744 op0_mode = VOIDmode;
3745 mode = GET_MODE (temp);
3748 /* First see if we can apply the inverse distributive law. */
3749 if (code == PLUS || code == MINUS
3750 || code == AND || code == IOR || code == XOR)
3752 x = apply_distributive_law (x);
3753 code = GET_CODE (x);
3754 op0_mode = VOIDmode;
3757 /* If CODE is an associative operation not otherwise handled, see if we
3758 can associate some operands. This can win if they are constants or
3759 if they are logically related (i.e. (a & b) & a). */
3760 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
3761 || code == AND || code == IOR || code == XOR
3762 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
3763 && ((INTEGRAL_MODE_P (mode) && code != DIV)
3764 || (flag_unsafe_math_optimizations && FLOAT_MODE_P (mode))))
3766 if (GET_CODE (XEXP (x, 0)) == code)
3768 rtx other = XEXP (XEXP (x, 0), 0);
3769 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
3770 rtx inner_op1 = XEXP (x, 1);
3773 /* Make sure we pass the constant operand if any as the second
3774 one if this is a commutative operation. */
3775 if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
3777 rtx tem = inner_op0;
3778 inner_op0 = inner_op1;
3781 inner = simplify_binary_operation (code == MINUS ? PLUS
3782 : code == DIV ? MULT
3784 mode, inner_op0, inner_op1);
3786 /* For commutative operations, try the other pair if that one
3788 if (inner == 0 && GET_RTX_CLASS (code) == 'c')
3790 other = XEXP (XEXP (x, 0), 1);
3791 inner = simplify_binary_operation (code, mode,
3792 XEXP (XEXP (x, 0), 0),
3797 return gen_binary (code, mode, other, inner);
3801 /* A little bit of algebraic simplification here. */
3805 /* Ensure that our address has any ASHIFTs converted to MULT in case
3806 address-recognizing predicates are called later. */
3807 temp = make_compound_operation (XEXP (x, 0), MEM);
3808 SUBST (XEXP (x, 0), temp);
3812 if (op0_mode == VOIDmode)
3813 op0_mode = GET_MODE (SUBREG_REG (x));
3815 /* simplify_subreg can't use gen_lowpart_for_combine. */
3816 if (CONSTANT_P (SUBREG_REG (x))
3817 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
3818 /* Don't call gen_lowpart_for_combine if the inner mode
3819 is VOIDmode and we cannot simplify it, as SUBREG without
3820 inner mode is invalid. */
3821 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
3822 || gen_lowpart_common (mode, SUBREG_REG (x))))
3823 return gen_lowpart_for_combine (mode, SUBREG_REG (x));
3825 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
3829 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
3835 /* Don't change the mode of the MEM if that would change the meaning
3837 if (GET_CODE (SUBREG_REG (x)) == MEM
3838 && (MEM_VOLATILE_P (SUBREG_REG (x))
3839 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
3840 return gen_rtx_CLOBBER (mode, const0_rtx);
3842 /* Note that we cannot do any narrowing for non-constants since
3843 we might have been counting on using the fact that some bits were
3844 zero. We now do this in the SET. */
3849 /* (not (plus X -1)) can become (neg X). */
3850 if (GET_CODE (XEXP (x, 0)) == PLUS
3851 && XEXP (XEXP (x, 0), 1) == constm1_rtx)
3852 return gen_rtx_NEG (mode, XEXP (XEXP (x, 0), 0));
3854 /* Similarly, (not (neg X)) is (plus X -1). */
3855 if (GET_CODE (XEXP (x, 0)) == NEG)
3856 return gen_rtx_PLUS (mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3858 /* (not (xor X C)) for C constant is (xor X D) with D = ~C. */
3859 if (GET_CODE (XEXP (x, 0)) == XOR
3860 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3861 && (temp = simplify_unary_operation (NOT, mode,
3862 XEXP (XEXP (x, 0), 1),
3864 return gen_binary (XOR, mode, XEXP (XEXP (x, 0), 0), temp);
3866 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3867 other than 1, but that is not valid. We could do a similar
3868 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3869 but this doesn't seem common enough to bother with. */
3870 if (GET_CODE (XEXP (x, 0)) == ASHIFT
3871 && XEXP (XEXP (x, 0), 0) == const1_rtx)
3872 return gen_rtx_ROTATE (mode, simplify_gen_unary (NOT, mode,
3874 XEXP (XEXP (x, 0), 1));
3876 if (GET_CODE (XEXP (x, 0)) == SUBREG
3877 && subreg_lowpart_p (XEXP (x, 0))
3878 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3879 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
3880 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
3881 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3883 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3885 x = gen_rtx_ROTATE (inner_mode,
3886 simplify_gen_unary (NOT, inner_mode, const1_rtx,
3888 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
3889 return gen_lowpart_for_combine (mode, x);
3892 /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
3893 reversing the comparison code if valid. */
3894 if (STORE_FLAG_VALUE == -1
3895 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3896 && (reversed = reversed_comparison (x, mode, XEXP (XEXP (x, 0), 0),
3897 XEXP (XEXP (x, 0), 1))))
3900 /* (not (ashiftrt foo C)) where C is the number of bits in FOO minus 1
3901 is (ge foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
3902 perform the above simplification. */
3904 if (STORE_FLAG_VALUE == -1
3905 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3906 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3907 && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
3908 return gen_rtx_GE (mode, XEXP (XEXP (x, 0), 0), const0_rtx);
3910 /* Apply De Morgan's laws to reduce number of patterns for machines
3911 with negating logical insns (and-not, nand, etc.). If result has
3912 only one NOT, put it first, since that is how the patterns are
3915 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
3917 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
3918 enum machine_mode op_mode;
3920 op_mode = GET_MODE (in1);
3921 in1 = simplify_gen_unary (NOT, op_mode, in1, op_mode);
3923 op_mode = GET_MODE (in2);
3924 if (op_mode == VOIDmode)
3926 in2 = simplify_gen_unary (NOT, op_mode, in2, op_mode);
3928 if (GET_CODE (in2) == NOT && GET_CODE (in1) != NOT)
3931 in2 = in1; in1 = tem;
3934 return gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
3940 /* (neg (plus X 1)) can become (not X). */
3941 if (GET_CODE (XEXP (x, 0)) == PLUS
3942 && XEXP (XEXP (x, 0), 1) == const1_rtx)
3943 return gen_rtx_NOT (mode, XEXP (XEXP (x, 0), 0));
3945 /* Similarly, (neg (not X)) is (plus X 1). */
3946 if (GET_CODE (XEXP (x, 0)) == NOT)
3947 return plus_constant (XEXP (XEXP (x, 0), 0), 1);
3949 /* (neg (minus X Y)) can become (minus Y X). This transformation
3950 isn't safe for modes with signed zeros, since if X and Y are
3951 both +0, (minus Y X) is the same as (minus X Y). If the rounding
3952 mode is towards +infinity (or -infinity) then the two expressions
3953 will be rounded differently. */
3954 if (GET_CODE (XEXP (x, 0)) == MINUS
3955 && !HONOR_SIGNED_ZEROS (mode)
3956 && !HONOR_SIGN_DEPENDENT_ROUNDING (mode))
3957 return gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
3958 XEXP (XEXP (x, 0), 0));
3960 /* (neg (plus A B)) is canonicalized to (minus (neg A) B). */
3961 if (GET_CODE (XEXP (x, 0)) == PLUS
3962 && !HONOR_SIGNED_ZEROS (mode)
3963 && !HONOR_SIGN_DEPENDENT_ROUNDING (mode))
3965 temp = simplify_gen_unary (NEG, mode, XEXP (XEXP (x, 0), 0), mode);
3966 temp = combine_simplify_rtx (temp, mode, last, in_dest);
3967 return gen_binary (MINUS, mode, temp, XEXP (XEXP (x, 0), 1));
3970 /* (neg (mult A B)) becomes (mult (neg A) B).
3971 This works even for floating-point values. */
3972 if (GET_CODE (XEXP (x, 0)) == MULT)
3974 temp = simplify_gen_unary (NEG, mode, XEXP (XEXP (x, 0), 0), mode);
3975 return gen_binary (MULT, mode, temp, XEXP (XEXP (x, 0), 1));
3978 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
3979 if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx
3980 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
3981 return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3983 /* NEG commutes with ASHIFT since it is multiplication. Only do this
3984 if we can then eliminate the NEG (e.g.,
3985 if the operand is a constant). */
3987 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
3989 temp = simplify_unary_operation (NEG, mode,
3990 XEXP (XEXP (x, 0), 0), mode);
3992 return gen_binary (ASHIFT, mode, temp, XEXP (XEXP (x, 0), 1));
3995 temp = expand_compound_operation (XEXP (x, 0));
3997 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3998 replaced by (lshiftrt X C). This will convert
3999 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
4001 if (GET_CODE (temp) == ASHIFTRT
4002 && GET_CODE (XEXP (temp, 1)) == CONST_INT
4003 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
4004 return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
4005 INTVAL (XEXP (temp, 1)));
4007 /* If X has only a single bit that might be nonzero, say, bit I, convert
4008 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4009 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4010 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4011 or a SUBREG of one since we'd be making the expression more
4012 complex if it was just a register. */
4014 if (GET_CODE (temp) != REG
4015 && ! (GET_CODE (temp) == SUBREG
4016 && GET_CODE (SUBREG_REG (temp)) == REG)
4017 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
4019 rtx temp1 = simplify_shift_const
4020 (NULL_RTX, ASHIFTRT, mode,
4021 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
4022 GET_MODE_BITSIZE (mode) - 1 - i),
4023 GET_MODE_BITSIZE (mode) - 1 - i);
4025 /* If all we did was surround TEMP with the two shifts, we
4026 haven't improved anything, so don't use it. Otherwise,
4027 we are better off with TEMP1. */
4028 if (GET_CODE (temp1) != ASHIFTRT
4029 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
4030 || XEXP (XEXP (temp1, 0), 0) != temp)
4036 /* We can't handle truncation to a partial integer mode here
4037 because we don't know the real bitsize of the partial
4039 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
4042 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4043 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4044 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4046 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
4047 GET_MODE_MASK (mode), NULL_RTX, 0));
4049 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
4050 if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4051 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4052 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4053 return XEXP (XEXP (x, 0), 0);
4055 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
4056 (OP:SI foo:SI) if OP is NEG or ABS. */
4057 if ((GET_CODE (XEXP (x, 0)) == ABS
4058 || GET_CODE (XEXP (x, 0)) == NEG)
4059 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
4060 || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
4061 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4062 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4063 XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
4065 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
4067 if (GET_CODE (XEXP (x, 0)) == SUBREG
4068 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE
4069 && subreg_lowpart_p (XEXP (x, 0)))
4070 return SUBREG_REG (XEXP (x, 0));
4072 /* If we know that the value is already truncated, we can
4073 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
4074 is nonzero for the corresponding modes. But don't do this
4075 for an (LSHIFTRT (MULT ...)) since this will cause problems
4076 with the umulXi3_highpart patterns. */
4077 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4078 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
4079 && num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4080 >= (unsigned int) (GET_MODE_BITSIZE (mode) + 1)
4081 && ! (GET_CODE (XEXP (x, 0)) == LSHIFTRT
4082 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT))
4083 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4085 /* A truncate of a comparison can be replaced with a subreg if
4086 STORE_FLAG_VALUE permits. This is like the previous test,
4087 but it works even if the comparison is done in a mode larger
4088 than HOST_BITS_PER_WIDE_INT. */
4089 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4090 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4091 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0)
4092 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4094 /* Similarly, a truncate of a register whose value is a
4095 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4097 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4098 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
4099 && (temp = get_last_value (XEXP (x, 0)))
4100 && GET_RTX_CLASS (GET_CODE (temp)) == '<')
4101 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4105 case FLOAT_TRUNCATE:
4106 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4107 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
4108 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4109 return XEXP (XEXP (x, 0), 0);
4111 /* (float_truncate:SF (float_truncate:DF foo:XF))
4112 = (float_truncate:SF foo:XF).
4113 This may eliminate double rounding, so it is unsafe.
4115 (float_truncate:SF (float_extend:XF foo:DF))
4116 = (float_truncate:SF foo:DF).
4118 (float_truncate:DF (float_extend:XF foo:SF))
4119 = (float_extend:SF foo:DF). */
4120 if ((GET_CODE (XEXP (x, 0)) == FLOAT_TRUNCATE
4121 && flag_unsafe_math_optimizations)
4122 || GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND)
4123 return simplify_gen_unary (GET_MODE_SIZE (GET_MODE (XEXP (XEXP (x, 0),
4125 > GET_MODE_SIZE (mode)
4126 ? FLOAT_TRUNCATE : FLOAT_EXTEND,
4128 XEXP (XEXP (x, 0), 0), mode);
4130 /* (float_truncate (float x)) is (float x) */
4131 if (GET_CODE (XEXP (x, 0)) == FLOAT
4132 && (flag_unsafe_math_optimizations
4133 || ((unsigned)significand_size (GET_MODE (XEXP (x, 0)))
4134 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x, 0), 0)))
4135 - num_sign_bit_copies (XEXP (XEXP (x, 0), 0),
4136 GET_MODE (XEXP (XEXP (x, 0), 0)))))))
4137 return simplify_gen_unary (FLOAT, mode,
4138 XEXP (XEXP (x, 0), 0),
4139 GET_MODE (XEXP (XEXP (x, 0), 0)));
4141 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4142 (OP:SF foo:SF) if OP is NEG or ABS. */
4143 if ((GET_CODE (XEXP (x, 0)) == ABS
4144 || GET_CODE (XEXP (x, 0)) == NEG)
4145 && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
4146 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4147 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4148 XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
4150 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4151 is (float_truncate:SF x). */
4152 if (GET_CODE (XEXP (x, 0)) == SUBREG
4153 && subreg_lowpart_p (XEXP (x, 0))
4154 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
4155 return SUBREG_REG (XEXP (x, 0));
4158 /* (float_extend (float_extend x)) is (float_extend x)
4160 (float_extend (float x)) is (float x) assuming that double
4161 rounding can't happen.
4163 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
4164 || (GET_CODE (XEXP (x, 0)) == FLOAT
4165 && ((unsigned)significand_size (GET_MODE (XEXP (x, 0)))
4166 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x, 0), 0)))
4167 - num_sign_bit_copies (XEXP (XEXP (x, 0), 0),
4168 GET_MODE (XEXP (XEXP (x, 0), 0)))))))
4169 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4170 XEXP (XEXP (x, 0), 0),
4171 GET_MODE (XEXP (XEXP (x, 0), 0)));
4176 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4177 using cc0, in which case we want to leave it as a COMPARE
4178 so we can distinguish it from a register-register-copy. */
4179 if (XEXP (x, 1) == const0_rtx)
4182 /* x - 0 is the same as x unless x's mode has signed zeros and
4183 allows rounding towards -infinity. Under those conditions,
4185 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x, 0)))
4186 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x, 0))))
4187 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4193 /* (const (const X)) can become (const X). Do it this way rather than
4194 returning the inner CONST since CONST can be shared with a
4196 if (GET_CODE (XEXP (x, 0)) == CONST)
4197 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4202 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4203 can add in an offset. find_split_point will split this address up
4204 again if it doesn't match. */
4205 if (GET_CODE (XEXP (x, 0)) == HIGH
4206 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4212 /* Canonicalize (plus (mult (neg B) C) A) to (minus A (mult B C)).
4214 if (GET_CODE (XEXP (x, 0)) == MULT
4215 && GET_CODE (XEXP (XEXP (x, 0), 0)) == NEG)
4219 in1 = XEXP (XEXP (XEXP (x, 0), 0), 0);
4220 in2 = XEXP (XEXP (x, 0), 1);
4221 return gen_binary (MINUS, mode, XEXP (x, 1),
4222 gen_binary (MULT, mode, in1, in2));
4225 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4226 outermost. That's because that's the way indexed addresses are
4227 supposed to appear. This code used to check many more cases, but
4228 they are now checked elsewhere. */
4229 if (GET_CODE (XEXP (x, 0)) == PLUS
4230 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
4231 return gen_binary (PLUS, mode,
4232 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
4234 XEXP (XEXP (x, 0), 1));
4236 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4237 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4238 bit-field and can be replaced by either a sign_extend or a
4239 sign_extract. The `and' may be a zero_extend and the two
4240 <c>, -<c> constants may be reversed. */
4241 if (GET_CODE (XEXP (x, 0)) == XOR
4242 && GET_CODE (XEXP (x, 1)) == CONST_INT
4243 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4244 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
4245 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4246 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4247 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4248 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4249 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4250 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4251 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4252 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4253 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4254 == (unsigned int) i + 1))))
4255 return simplify_shift_const
4256 (NULL_RTX, ASHIFTRT, mode,
4257 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4258 XEXP (XEXP (XEXP (x, 0), 0), 0),
4259 GET_MODE_BITSIZE (mode) - (i + 1)),
4260 GET_MODE_BITSIZE (mode) - (i + 1));
4262 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4263 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4264 is 1. This produces better code than the alternative immediately
4266 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4267 && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
4268 || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx))
4269 && (reversed = reversed_comparison (XEXP (x, 0), mode,
4270 XEXP (XEXP (x, 0), 0),
4271 XEXP (XEXP (x, 0), 1))))
4273 simplify_gen_unary (NEG, mode, reversed, mode);
4275 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4276 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4277 the bitsize of the mode - 1. This allows simplification of
4278 "a = (b & 8) == 0;" */
4279 if (XEXP (x, 1) == constm1_rtx
4280 && GET_CODE (XEXP (x, 0)) != REG
4281 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4282 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
4283 && nonzero_bits (XEXP (x, 0), mode) == 1)
4284 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4285 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4286 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
4287 GET_MODE_BITSIZE (mode) - 1),
4288 GET_MODE_BITSIZE (mode) - 1);
4290 /* If we are adding two things that have no bits in common, convert
4291 the addition into an IOR. This will often be further simplified,
4292 for example in cases like ((a & 1) + (a & 2)), which can
4295 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4296 && (nonzero_bits (XEXP (x, 0), mode)
4297 & nonzero_bits (XEXP (x, 1), mode)) == 0)
4299 /* Try to simplify the expression further. */
4300 rtx tor = gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4301 temp = combine_simplify_rtx (tor, mode, last, in_dest);
4303 /* If we could, great. If not, do not go ahead with the IOR
4304 replacement, since PLUS appears in many special purpose
4305 address arithmetic instructions. */
4306 if (GET_CODE (temp) != CLOBBER && temp != tor)
4312 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4313 by reversing the comparison code if valid. */
4314 if (STORE_FLAG_VALUE == 1
4315 && XEXP (x, 0) == const1_rtx
4316 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<'
4317 && (reversed = reversed_comparison (XEXP (x, 1), mode,
4318 XEXP (XEXP (x, 1), 0),
4319 XEXP (XEXP (x, 1), 1))))
4322 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4323 (and <foo> (const_int pow2-1)) */
4324 if (GET_CODE (XEXP (x, 1)) == AND
4325 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4326 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4327 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4328 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4329 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4331 /* Canonicalize (minus A (mult (neg B) C)) to (plus (mult B C) A).
4333 if (GET_CODE (XEXP (x, 1)) == MULT
4334 && GET_CODE (XEXP (XEXP (x, 1), 0)) == NEG)
4338 in1 = XEXP (XEXP (XEXP (x, 1), 0), 0);
4339 in2 = XEXP (XEXP (x, 1), 1);
4340 return gen_binary (PLUS, mode, gen_binary (MULT, mode, in1, in2),
4344 /* Canonicalize (minus (neg A) (mult B C)) to
4345 (minus (mult (neg B) C) A). */
4346 if (GET_CODE (XEXP (x, 1)) == MULT
4347 && GET_CODE (XEXP (x, 0)) == NEG)
4351 in1 = simplify_gen_unary (NEG, mode, XEXP (XEXP (x, 1), 0), mode);
4352 in2 = XEXP (XEXP (x, 1), 1);
4353 return gen_binary (MINUS, mode, gen_binary (MULT, mode, in1, in2),
4354 XEXP (XEXP (x, 0), 0));
4357 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4359 if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
4360 return gen_binary (MINUS, mode,
4361 gen_binary (MINUS, mode, XEXP (x, 0),
4362 XEXP (XEXP (x, 1), 0)),
4363 XEXP (XEXP (x, 1), 1));
4367 /* If we have (mult (plus A B) C), apply the distributive law and then
4368 the inverse distributive law to see if things simplify. This
4369 occurs mostly in addresses, often when unrolling loops. */
4371 if (GET_CODE (XEXP (x, 0)) == PLUS)
4373 x = apply_distributive_law
4374 (gen_binary (PLUS, mode,
4375 gen_binary (MULT, mode,
4376 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
4377 gen_binary (MULT, mode,
4378 XEXP (XEXP (x, 0), 1),
4379 copy_rtx (XEXP (x, 1)))));
4381 if (GET_CODE (x) != MULT)
4384 /* Try simplify a*(b/c) as (a*b)/c. */
4385 if (FLOAT_MODE_P (mode) && flag_unsafe_math_optimizations
4386 && GET_CODE (XEXP (x, 0)) == DIV)
4388 rtx tem = simplify_binary_operation (MULT, mode,
4389 XEXP (XEXP (x, 0), 0),
4392 return gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
4397 /* If this is a divide by a power of two, treat it as a shift if
4398 its first operand is a shift. */
4399 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4400 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4401 && (GET_CODE (XEXP (x, 0)) == ASHIFT
4402 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4403 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4404 || GET_CODE (XEXP (x, 0)) == ROTATE
4405 || GET_CODE (XEXP (x, 0)) == ROTATERT))
4406 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
4410 case GT: case GTU: case GE: case GEU:
4411 case LT: case LTU: case LE: case LEU:
4412 case UNEQ: case LTGT:
4413 case UNGT: case UNGE:
4414 case UNLT: case UNLE:
4415 case UNORDERED: case ORDERED:
4416 /* If the first operand is a condition code, we can't do anything
4418 if (GET_CODE (XEXP (x, 0)) == COMPARE
4419 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4420 && ! CC0_P (XEXP (x, 0))))
4422 rtx op0 = XEXP (x, 0);
4423 rtx op1 = XEXP (x, 1);
4424 enum rtx_code new_code;
4426 if (GET_CODE (op0) == COMPARE)
4427 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4429 /* Simplify our comparison, if possible. */
4430 new_code = simplify_comparison (code, &op0, &op1);
4432 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4433 if only the low-order bit is possibly nonzero in X (such as when
4434 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4435 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4436 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4439 Remove any ZERO_EXTRACT we made when thinking this was a
4440 comparison. It may now be simpler to use, e.g., an AND. If a
4441 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4442 the call to make_compound_operation in the SET case. */
4444 if (STORE_FLAG_VALUE == 1
4445 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4446 && op1 == const0_rtx
4447 && mode == GET_MODE (op0)
4448 && nonzero_bits (op0, mode) == 1)
4449 return gen_lowpart_for_combine (mode,
4450 expand_compound_operation (op0));
4452 else if (STORE_FLAG_VALUE == 1
4453 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4454 && op1 == const0_rtx
4455 && mode == GET_MODE (op0)
4456 && (num_sign_bit_copies (op0, mode)
4457 == GET_MODE_BITSIZE (mode)))
4459 op0 = expand_compound_operation (op0);
4460 return simplify_gen_unary (NEG, mode,
4461 gen_lowpart_for_combine (mode, op0),
4465 else if (STORE_FLAG_VALUE == 1
4466 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4467 && op1 == const0_rtx
4468 && mode == GET_MODE (op0)
4469 && nonzero_bits (op0, mode) == 1)
4471 op0 = expand_compound_operation (op0);
4472 return gen_binary (XOR, mode,
4473 gen_lowpart_for_combine (mode, op0),
4477 else if (STORE_FLAG_VALUE == 1
4478 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4479 && op1 == const0_rtx
4480 && mode == GET_MODE (op0)
4481 && (num_sign_bit_copies (op0, mode)
4482 == GET_MODE_BITSIZE (mode)))
4484 op0 = expand_compound_operation (op0);
4485 return plus_constant (gen_lowpart_for_combine (mode, op0), 1);
4488 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4490 if (STORE_FLAG_VALUE == -1
4491 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4492 && op1 == const0_rtx
4493 && (num_sign_bit_copies (op0, mode)
4494 == GET_MODE_BITSIZE (mode)))
4495 return gen_lowpart_for_combine (mode,
4496 expand_compound_operation (op0));
4498 else if (STORE_FLAG_VALUE == -1
4499 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4500 && op1 == const0_rtx
4501 && mode == GET_MODE (op0)
4502 && nonzero_bits (op0, mode) == 1)
4504 op0 = expand_compound_operation (op0);
4505 return simplify_gen_unary (NEG, mode,
4506 gen_lowpart_for_combine (mode, op0),
4510 else if (STORE_FLAG_VALUE == -1
4511 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4512 && op1 == const0_rtx
4513 && mode == GET_MODE (op0)
4514 && (num_sign_bit_copies (op0, mode)
4515 == GET_MODE_BITSIZE (mode)))
4517 op0 = expand_compound_operation (op0);
4518 return simplify_gen_unary (NOT, mode,
4519 gen_lowpart_for_combine (mode, op0),
4523 /* If X is 0/1, (eq X 0) is X-1. */
4524 else if (STORE_FLAG_VALUE == -1
4525 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4526 && op1 == const0_rtx
4527 && mode == GET_MODE (op0)
4528 && nonzero_bits (op0, mode) == 1)
4530 op0 = expand_compound_operation (op0);
4531 return plus_constant (gen_lowpart_for_combine (mode, op0), -1);
4534 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4535 one bit that might be nonzero, we can convert (ne x 0) to
4536 (ashift x c) where C puts the bit in the sign bit. Remove any
4537 AND with STORE_FLAG_VALUE when we are done, since we are only
4538 going to test the sign bit. */
4539 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4540 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4541 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4542 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
4543 && op1 == const0_rtx
4544 && mode == GET_MODE (op0)
4545 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4547 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4548 expand_compound_operation (op0),
4549 GET_MODE_BITSIZE (mode) - 1 - i);
4550 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4556 /* If the code changed, return a whole new comparison. */
4557 if (new_code != code)
4558 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
4560 /* Otherwise, keep this operation, but maybe change its operands.
4561 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4562 SUBST (XEXP (x, 0), op0);
4563 SUBST (XEXP (x, 1), op1);
4568 return simplify_if_then_else (x);
4574 /* If we are processing SET_DEST, we are done. */
4578 return expand_compound_operation (x);
4581 return simplify_set (x);
4586 return simplify_logical (x, last);
4589 /* (abs (neg <foo>)) -> (abs <foo>) */
4590 if (GET_CODE (XEXP (x, 0)) == NEG)
4591 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4593 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4595 if (GET_MODE (XEXP (x, 0)) == VOIDmode)
4598 /* If operand is something known to be positive, ignore the ABS. */
4599 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4600 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4601 <= HOST_BITS_PER_WIDE_INT)
4602 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4603 & ((HOST_WIDE_INT) 1
4604 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4608 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4609 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4610 return gen_rtx_NEG (mode, XEXP (x, 0));
4615 /* (ffs (*_extend <X>)) = (ffs <X>) */
4616 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4617 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4618 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4623 /* (pop* (zero_extend <X>)) = (pop* <X>) */
4624 if (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4625 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4629 /* (float (sign_extend <X>)) = (float <X>). */
4630 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4631 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4639 /* If this is a shift by a constant amount, simplify it. */
4640 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4641 return simplify_shift_const (x, code, mode, XEXP (x, 0),
4642 INTVAL (XEXP (x, 1)));
4644 #ifdef SHIFT_COUNT_TRUNCATED
4645 else if (SHIFT_COUNT_TRUNCATED && GET_CODE (XEXP (x, 1)) != REG)
4647 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
4649 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4658 rtx op0 = XEXP (x, 0);
4659 rtx op1 = XEXP (x, 1);
4662 if (GET_CODE (op1) != PARALLEL)
4664 len = XVECLEN (op1, 0);
4666 && GET_CODE (XVECEXP (op1, 0, 0)) == CONST_INT
4667 && GET_CODE (op0) == VEC_CONCAT)
4669 int offset = INTVAL (XVECEXP (op1, 0, 0)) * GET_MODE_SIZE (GET_MODE (x));
4671 /* Try to find the element in the VEC_CONCAT. */
4674 if (GET_MODE (op0) == GET_MODE (x))
4676 if (GET_CODE (op0) == VEC_CONCAT)
4678 HOST_WIDE_INT op0_size = GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)));
4679 if (op0_size < offset)
4680 op0 = XEXP (op0, 0);
4684 op0 = XEXP (op0, 1);
4702 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4705 simplify_if_then_else (rtx x)
4707 enum machine_mode mode = GET_MODE (x);
4708 rtx cond = XEXP (x, 0);
4709 rtx true_rtx = XEXP (x, 1);
4710 rtx false_rtx = XEXP (x, 2);
4711 enum rtx_code true_code = GET_CODE (cond);
4712 int comparison_p = GET_RTX_CLASS (true_code) == '<';
4715 enum rtx_code false_code;
4718 /* Simplify storing of the truth value. */
4719 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
4720 return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1));
4722 /* Also when the truth value has to be reversed. */
4724 && true_rtx == const0_rtx && false_rtx == const_true_rtx
4725 && (reversed = reversed_comparison (cond, mode, XEXP (cond, 0),
4729 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4730 in it is being compared against certain values. Get the true and false
4731 comparisons and see if that says anything about the value of each arm. */
4734 && ((false_code = combine_reversed_comparison_code (cond))
4736 && GET_CODE (XEXP (cond, 0)) == REG)
4739 rtx from = XEXP (cond, 0);
4740 rtx true_val = XEXP (cond, 1);
4741 rtx false_val = true_val;
4744 /* If FALSE_CODE is EQ, swap the codes and arms. */
4746 if (false_code == EQ)
4748 swapped = 1, true_code = EQ, false_code = NE;
4749 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4752 /* If we are comparing against zero and the expression being tested has
4753 only a single bit that might be nonzero, that is its value when it is
4754 not equal to zero. Similarly if it is known to be -1 or 0. */
4756 if (true_code == EQ && true_val == const0_rtx
4757 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4758 false_code = EQ, false_val = GEN_INT (nzb);
4759 else if (true_code == EQ && true_val == const0_rtx
4760 && (num_sign_bit_copies (from, GET_MODE (from))
4761 == GET_MODE_BITSIZE (GET_MODE (from))))
4762 false_code = EQ, false_val = constm1_rtx;
4764 /* Now simplify an arm if we know the value of the register in the
4765 branch and it is used in the arm. Be careful due to the potential
4766 of locally-shared RTL. */
4768 if (reg_mentioned_p (from, true_rtx))
4769 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
4771 pc_rtx, pc_rtx, 0, 0);
4772 if (reg_mentioned_p (from, false_rtx))
4773 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
4775 pc_rtx, pc_rtx, 0, 0);
4777 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
4778 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
4780 true_rtx = XEXP (x, 1);
4781 false_rtx = XEXP (x, 2);
4782 true_code = GET_CODE (cond);
4785 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4786 reversed, do so to avoid needing two sets of patterns for
4787 subtract-and-branch insns. Similarly if we have a constant in the true
4788 arm, the false arm is the same as the first operand of the comparison, or
4789 the false arm is more complicated than the true arm. */
4792 && combine_reversed_comparison_code (cond) != UNKNOWN
4793 && (true_rtx == pc_rtx
4794 || (CONSTANT_P (true_rtx)
4795 && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx)
4796 || true_rtx == const0_rtx
4797 || (GET_RTX_CLASS (GET_CODE (true_rtx)) == 'o'
4798 && GET_RTX_CLASS (GET_CODE (false_rtx)) != 'o')
4799 || (GET_CODE (true_rtx) == SUBREG
4800 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true_rtx))) == 'o'
4801 && GET_RTX_CLASS (GET_CODE (false_rtx)) != 'o')
4802 || reg_mentioned_p (true_rtx, false_rtx)
4803 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
4805 true_code = reversed_comparison_code (cond, NULL);
4807 reversed_comparison (cond, GET_MODE (cond), XEXP (cond, 0),
4810 SUBST (XEXP (x, 1), false_rtx);
4811 SUBST (XEXP (x, 2), true_rtx);
4813 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4816 /* It is possible that the conditional has been simplified out. */
4817 true_code = GET_CODE (cond);
4818 comparison_p = GET_RTX_CLASS (true_code) == '<';
4821 /* If the two arms are identical, we don't need the comparison. */
4823 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
4826 /* Convert a == b ? b : a to "a". */
4827 if (true_code == EQ && ! side_effects_p (cond)
4828 && !HONOR_NANS (mode)
4829 && rtx_equal_p (XEXP (cond, 0), false_rtx)
4830 && rtx_equal_p (XEXP (cond, 1), true_rtx))
4832 else if (true_code == NE && ! side_effects_p (cond)
4833 && !HONOR_NANS (mode)
4834 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4835 && rtx_equal_p (XEXP (cond, 1), false_rtx))
4838 /* Look for cases where we have (abs x) or (neg (abs X)). */
4840 if (GET_MODE_CLASS (mode) == MODE_INT
4841 && GET_CODE (false_rtx) == NEG
4842 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
4844 && rtx_equal_p (true_rtx, XEXP (cond, 0))
4845 && ! side_effects_p (true_rtx))
4850 return simplify_gen_unary (ABS, mode, true_rtx, mode);
4854 simplify_gen_unary (NEG, mode,
4855 simplify_gen_unary (ABS, mode, true_rtx, mode),
4861 /* Look for MIN or MAX. */
4863 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4865 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4866 && rtx_equal_p (XEXP (cond, 1), false_rtx)
4867 && ! side_effects_p (cond))
4872 return gen_binary (SMAX, mode, true_rtx, false_rtx);
4875 return gen_binary (SMIN, mode, true_rtx, false_rtx);
4878 return gen_binary (UMAX, mode, true_rtx, false_rtx);
4881 return gen_binary (UMIN, mode, true_rtx, false_rtx);
4886 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4887 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4888 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4889 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4890 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4891 neither 1 or -1, but it isn't worth checking for. */
4893 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4895 && GET_MODE_CLASS (mode) == MODE_INT
4896 && ! side_effects_p (x))
4898 rtx t = make_compound_operation (true_rtx, SET);
4899 rtx f = make_compound_operation (false_rtx, SET);
4900 rtx cond_op0 = XEXP (cond, 0);
4901 rtx cond_op1 = XEXP (cond, 1);
4902 enum rtx_code op = NIL, extend_op = NIL;
4903 enum machine_mode m = mode;
4904 rtx z = 0, c1 = NULL_RTX;
4906 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4907 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4908 || GET_CODE (t) == ASHIFT
4909 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4910 && rtx_equal_p (XEXP (t, 0), f))
4911 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4913 /* If an identity-zero op is commutative, check whether there
4914 would be a match if we swapped the operands. */
4915 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4916 || GET_CODE (t) == XOR)
4917 && rtx_equal_p (XEXP (t, 1), f))
4918 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4919 else if (GET_CODE (t) == SIGN_EXTEND
4920 && (GET_CODE (XEXP (t, 0)) == PLUS
4921 || GET_CODE (XEXP (t, 0)) == MINUS
4922 || GET_CODE (XEXP (t, 0)) == IOR
4923 || GET_CODE (XEXP (t, 0)) == XOR
4924 || GET_CODE (XEXP (t, 0)) == ASHIFT
4925 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4926 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4927 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4928 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4929 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4930 && (num_sign_bit_copies (f, GET_MODE (f))
4932 (GET_MODE_BITSIZE (mode)
4933 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
4935 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4936 extend_op = SIGN_EXTEND;
4937 m = GET_MODE (XEXP (t, 0));
4939 else if (GET_CODE (t) == SIGN_EXTEND
4940 && (GET_CODE (XEXP (t, 0)) == PLUS
4941 || GET_CODE (XEXP (t, 0)) == IOR
4942 || GET_CODE (XEXP (t, 0)) == XOR)
4943 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4944 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4945 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4946 && (num_sign_bit_copies (f, GET_MODE (f))
4948 (GET_MODE_BITSIZE (mode)
4949 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
4951 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4952 extend_op = SIGN_EXTEND;
4953 m = GET_MODE (XEXP (t, 0));
4955 else if (GET_CODE (t) == ZERO_EXTEND
4956 && (GET_CODE (XEXP (t, 0)) == PLUS
4957 || GET_CODE (XEXP (t, 0)) == MINUS
4958 || GET_CODE (XEXP (t, 0)) == IOR
4959 || GET_CODE (XEXP (t, 0)) == XOR
4960 || GET_CODE (XEXP (t, 0)) == ASHIFT
4961 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4962 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4963 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4964 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4965 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4966 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4967 && ((nonzero_bits (f, GET_MODE (f))
4968 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
4971 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4972 extend_op = ZERO_EXTEND;
4973 m = GET_MODE (XEXP (t, 0));
4975 else if (GET_CODE (t) == ZERO_EXTEND
4976 && (GET_CODE (XEXP (t, 0)) == PLUS
4977 || GET_CODE (XEXP (t, 0)) == IOR
4978 || GET_CODE (XEXP (t, 0)) == XOR)
4979 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4980 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4981 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4982 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4983 && ((nonzero_bits (f, GET_MODE (f))
4984 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
4987 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4988 extend_op = ZERO_EXTEND;
4989 m = GET_MODE (XEXP (t, 0));
4994 temp = subst (gen_binary (true_code, m, cond_op0, cond_op1),
4995 pc_rtx, pc_rtx, 0, 0);
4996 temp = gen_binary (MULT, m, temp,
4997 gen_binary (MULT, m, c1, const_true_rtx));
4998 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
4999 temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp);
5001 if (extend_op != NIL)
5002 temp = simplify_gen_unary (extend_op, mode, temp, m);
5008 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5009 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5010 negation of a single bit, we can convert this operation to a shift. We
5011 can actually do this more generally, but it doesn't seem worth it. */
5013 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5014 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5015 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
5016 && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
5017 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
5018 == GET_MODE_BITSIZE (mode))
5019 && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
5021 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5022 gen_lowpart_for_combine (mode, XEXP (cond, 0)), i);
5024 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
5025 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5026 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5027 && (INTVAL (true_rtx) & GET_MODE_MASK (mode))
5028 == nonzero_bits (XEXP (cond, 0), mode)
5029 && (i = exact_log2 (INTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
5030 return XEXP (cond, 0);
5035 /* Simplify X, a SET expression. Return the new expression. */
5038 simplify_set (rtx x)
5040 rtx src = SET_SRC (x);
5041 rtx dest = SET_DEST (x);
5042 enum machine_mode mode
5043 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
5047 /* (set (pc) (return)) gets written as (return). */
5048 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
5051 /* Now that we know for sure which bits of SRC we are using, see if we can
5052 simplify the expression for the object knowing that we only need the
5055 if (GET_MODE_CLASS (mode) == MODE_INT
5056 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5058 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, NULL_RTX, 0);
5059 SUBST (SET_SRC (x), src);
5062 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5063 the comparison result and try to simplify it unless we already have used
5064 undobuf.other_insn. */
5065 if ((GET_MODE_CLASS (mode) == MODE_CC
5066 || GET_CODE (src) == COMPARE
5068 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
5069 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
5070 && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
5071 && rtx_equal_p (XEXP (*cc_use, 0), dest))
5073 enum rtx_code old_code = GET_CODE (*cc_use);
5074 enum rtx_code new_code;
5076 int other_changed = 0;
5077 enum machine_mode compare_mode = GET_MODE (dest);
5078 enum machine_mode tmp_mode;
5080 if (GET_CODE (src) == COMPARE)
5081 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
5083 op0 = src, op1 = const0_rtx;
5085 /* Check whether the comparison is known at compile time. */
5086 if (GET_MODE (op0) != VOIDmode)
5087 tmp_mode = GET_MODE (op0);
5088 else if (GET_MODE (op1) != VOIDmode)
5089 tmp_mode = GET_MODE (op1);
5091 tmp_mode = compare_mode;
5092 tmp = simplify_relational_operation (old_code, tmp_mode, op0, op1);
5093 if (tmp != NULL_RTX)
5095 rtx pat = PATTERN (other_insn);
5096 undobuf.other_insn = other_insn;
5097 SUBST (*cc_use, tmp);
5099 /* Attempt to simplify CC user. */
5100 if (GET_CODE (pat) == SET)
5102 rtx new = simplify_rtx (SET_SRC (pat));
5103 if (new != NULL_RTX)
5104 SUBST (SET_SRC (pat), new);
5107 /* Convert X into a no-op move. */
5108 SUBST (SET_DEST (x), pc_rtx);
5109 SUBST (SET_SRC (x), pc_rtx);
5113 /* Simplify our comparison, if possible. */
5114 new_code = simplify_comparison (old_code, &op0, &op1);
5116 #ifdef EXTRA_CC_MODES
5117 /* If this machine has CC modes other than CCmode, check to see if we
5118 need to use a different CC mode here. */
5119 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5120 #endif /* EXTRA_CC_MODES */
5122 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
5123 /* If the mode changed, we have to change SET_DEST, the mode in the
5124 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5125 a hard register, just build new versions with the proper mode. If it
5126 is a pseudo, we lose unless it is only time we set the pseudo, in
5127 which case we can safely change its mode. */
5128 if (compare_mode != GET_MODE (dest))
5130 unsigned int regno = REGNO (dest);
5131 rtx new_dest = gen_rtx_REG (compare_mode, regno);
5133 if (regno < FIRST_PSEUDO_REGISTER
5134 || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest)))
5136 if (regno >= FIRST_PSEUDO_REGISTER)
5137 SUBST (regno_reg_rtx[regno], new_dest);
5139 SUBST (SET_DEST (x), new_dest);
5140 SUBST (XEXP (*cc_use, 0), new_dest);
5148 /* If the code changed, we have to build a new comparison in
5149 undobuf.other_insn. */
5150 if (new_code != old_code)
5152 unsigned HOST_WIDE_INT mask;
5154 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5157 /* If the only change we made was to change an EQ into an NE or
5158 vice versa, OP0 has only one bit that might be nonzero, and OP1
5159 is zero, check if changing the user of the condition code will
5160 produce a valid insn. If it won't, we can keep the original code
5161 in that insn by surrounding our operation with an XOR. */
5163 if (((old_code == NE && new_code == EQ)
5164 || (old_code == EQ && new_code == NE))
5165 && ! other_changed && op1 == const0_rtx
5166 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5167 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5169 rtx pat = PATTERN (other_insn), note = 0;
5171 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
5172 && ! check_asm_operands (pat)))
5174 PUT_CODE (*cc_use, old_code);
5177 op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask));
5185 undobuf.other_insn = other_insn;
5188 /* If we are now comparing against zero, change our source if
5189 needed. If we do not use cc0, we always have a COMPARE. */
5190 if (op1 == const0_rtx && dest == cc0_rtx)
5192 SUBST (SET_SRC (x), op0);
5198 /* Otherwise, if we didn't previously have a COMPARE in the
5199 correct mode, we need one. */
5200 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5202 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5207 /* Otherwise, update the COMPARE if needed. */
5208 SUBST (XEXP (src, 0), op0);
5209 SUBST (XEXP (src, 1), op1);
5214 /* Get SET_SRC in a form where we have placed back any
5215 compound expressions. Then do the checks below. */
5216 src = make_compound_operation (src, SET);
5217 SUBST (SET_SRC (x), src);
5220 #ifdef WORD_REGISTER_OPERATIONS
5221 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5222 and X being a REG or (subreg (reg)), we may be able to convert this to
5223 (set (subreg:m2 x) (op)).
5225 On a machine where WORD_REGISTER_OPERATIONS is defined, this
5226 transformation is safe as long as M1 and M2 have the same number
5229 However, on a machine without WORD_REGISTER_OPERATIONS defined,
5230 we cannot apply this transformation because it would create a
5231 paradoxical subreg in SET_DEST. */
5233 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5234 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src))) != 'o'
5235 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5237 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5238 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5239 #ifdef CANNOT_CHANGE_MODE_CLASS
5240 && ! (GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER
5241 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
5242 GET_MODE (SUBREG_REG (src)),
5245 && (GET_CODE (dest) == REG
5246 || (GET_CODE (dest) == SUBREG
5247 && GET_CODE (SUBREG_REG (dest)) == REG)))
5249 SUBST (SET_DEST (x),
5250 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src)),
5252 SUBST (SET_SRC (x), SUBREG_REG (src));
5254 src = SET_SRC (x), dest = SET_DEST (x);
5259 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5262 && GET_CODE (src) == SUBREG
5263 && subreg_lowpart_p (src)
5264 && (GET_MODE_BITSIZE (GET_MODE (src))
5265 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
5267 rtx inner = SUBREG_REG (src);
5268 enum machine_mode inner_mode = GET_MODE (inner);
5270 /* Here we make sure that we don't have a sign bit on. */
5271 if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
5272 && (nonzero_bits (inner, inner_mode)
5273 < ((unsigned HOST_WIDE_INT) 1
5274 << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
5276 SUBST (SET_SRC (x), inner);
5282 #ifdef LOAD_EXTEND_OP
5283 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5284 would require a paradoxical subreg. Replace the subreg with a
5285 zero_extend to avoid the reload that would otherwise be required. */
5287 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5288 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL
5289 && SUBREG_BYTE (src) == 0
5290 && (GET_MODE_SIZE (GET_MODE (src))
5291 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5292 && GET_CODE (SUBREG_REG (src)) == MEM)
5295 gen_rtx (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5296 GET_MODE (src), SUBREG_REG (src)));
5302 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5303 are comparing an item known to be 0 or -1 against 0, use a logical
5304 operation instead. Check for one of the arms being an IOR of the other
5305 arm with some value. We compute three terms to be IOR'ed together. In
5306 practice, at most two will be nonzero. Then we do the IOR's. */
5308 if (GET_CODE (dest) != PC
5309 && GET_CODE (src) == IF_THEN_ELSE
5310 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5311 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5312 && XEXP (XEXP (src, 0), 1) == const0_rtx
5313 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5314 #ifdef HAVE_conditional_move
5315 && ! can_conditionally_move_p (GET_MODE (src))
5317 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5318 GET_MODE (XEXP (XEXP (src, 0), 0)))
5319 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5320 && ! side_effects_p (src))
5322 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
5323 ? XEXP (src, 1) : XEXP (src, 2));
5324 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
5325 ? XEXP (src, 2) : XEXP (src, 1));
5326 rtx term1 = const0_rtx, term2, term3;
5328 if (GET_CODE (true_rtx) == IOR
5329 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
5330 term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
5331 else if (GET_CODE (true_rtx) == IOR
5332 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
5333 term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
5334 else if (GET_CODE (false_rtx) == IOR
5335 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
5336 term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
5337 else if (GET_CODE (false_rtx) == IOR
5338 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
5339 term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
5341 term2 = gen_binary (AND, GET_MODE (src),
5342 XEXP (XEXP (src, 0), 0), true_rtx);
5343 term3 = gen_binary (AND, GET_MODE (src),
5344 simplify_gen_unary (NOT, GET_MODE (src),
5345 XEXP (XEXP (src, 0), 0),
5350 gen_binary (IOR, GET_MODE (src),
5351 gen_binary (IOR, GET_MODE (src), term1, term2),
5357 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5358 whole thing fail. */
5359 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5361 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5364 /* Convert this into a field assignment operation, if possible. */
5365 return make_field_assignment (x);
5368 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5369 result. LAST is nonzero if this is the last retry. */
5372 simplify_logical (rtx x, int last)
5374 enum machine_mode mode = GET_MODE (x);
5375 rtx op0 = XEXP (x, 0);
5376 rtx op1 = XEXP (x, 1);
5379 switch (GET_CODE (x))
5382 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5383 insn (and may simplify more). */
5384 if (GET_CODE (op0) == XOR
5385 && rtx_equal_p (XEXP (op0, 0), op1)
5386 && ! side_effects_p (op1))
5387 x = gen_binary (AND, mode,
5388 simplify_gen_unary (NOT, mode, XEXP (op0, 1), mode),
5391 if (GET_CODE (op0) == XOR
5392 && rtx_equal_p (XEXP (op0, 1), op1)
5393 && ! side_effects_p (op1))
5394 x = gen_binary (AND, mode,
5395 simplify_gen_unary (NOT, mode, XEXP (op0, 0), mode),
5398 /* Similarly for (~(A ^ B)) & A. */
5399 if (GET_CODE (op0) == NOT
5400 && GET_CODE (XEXP (op0, 0)) == XOR
5401 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
5402 && ! side_effects_p (op1))
5403 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
5405 if (GET_CODE (op0) == NOT
5406 && GET_CODE (XEXP (op0, 0)) == XOR
5407 && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
5408 && ! side_effects_p (op1))
5409 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
5411 /* We can call simplify_and_const_int only if we don't lose
5412 any (sign) bits when converting INTVAL (op1) to
5413 "unsigned HOST_WIDE_INT". */
5414 if (GET_CODE (op1) == CONST_INT
5415 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5416 || INTVAL (op1) > 0))
5418 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5420 /* If we have (ior (and (X C1) C2)) and the next restart would be
5421 the last, simplify this by making C1 as small as possible
5424 && GET_CODE (x) == IOR && GET_CODE (op0) == AND
5425 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5426 && GET_CODE (op1) == CONST_INT)
5427 return gen_binary (IOR, mode,
5428 gen_binary (AND, mode, XEXP (op0, 0),
5429 GEN_INT (INTVAL (XEXP (op0, 1))
5430 & ~INTVAL (op1))), op1);
5432 if (GET_CODE (x) != AND)
5435 if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
5436 || GET_RTX_CLASS (GET_CODE (x)) == '2')
5437 op0 = XEXP (x, 0), op1 = XEXP (x, 1);
5440 /* Convert (A | B) & A to A. */
5441 if (GET_CODE (op0) == IOR
5442 && (rtx_equal_p (XEXP (op0, 0), op1)
5443 || rtx_equal_p (XEXP (op0, 1), op1))
5444 && ! side_effects_p (XEXP (op0, 0))
5445 && ! side_effects_p (XEXP (op0, 1)))
5448 /* In the following group of tests (and those in case IOR below),
5449 we start with some combination of logical operations and apply
5450 the distributive law followed by the inverse distributive law.
5451 Most of the time, this results in no change. However, if some of
5452 the operands are the same or inverses of each other, simplifications
5455 For example, (and (ior A B) (not B)) can occur as the result of
5456 expanding a bit field assignment. When we apply the distributive
5457 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5458 which then simplifies to (and (A (not B))).
5460 If we have (and (ior A B) C), apply the distributive law and then
5461 the inverse distributive law to see if things simplify. */
5463 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5465 x = apply_distributive_law
5466 (gen_binary (GET_CODE (op0), mode,
5467 gen_binary (AND, mode, XEXP (op0, 0), op1),
5468 gen_binary (AND, mode, XEXP (op0, 1),
5470 if (GET_CODE (x) != AND)
5474 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5475 return apply_distributive_law
5476 (gen_binary (GET_CODE (op1), mode,
5477 gen_binary (AND, mode, XEXP (op1, 0), op0),
5478 gen_binary (AND, mode, XEXP (op1, 1),
5481 /* Similarly, taking advantage of the fact that
5482 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5484 if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR)
5485 return apply_distributive_law
5486 (gen_binary (XOR, mode,
5487 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)),
5488 gen_binary (IOR, mode, copy_rtx (XEXP (op0, 0)),
5491 else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR)
5492 return apply_distributive_law
5493 (gen_binary (XOR, mode,
5494 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)),
5495 gen_binary (IOR, mode, copy_rtx (XEXP (op1, 0)), XEXP (op0, 1))));
5499 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5500 if (GET_CODE (op1) == CONST_INT
5501 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5502 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
5505 /* Convert (A & B) | A to A. */
5506 if (GET_CODE (op0) == AND
5507 && (rtx_equal_p (XEXP (op0, 0), op1)
5508 || rtx_equal_p (XEXP (op0, 1), op1))
5509 && ! side_effects_p (XEXP (op0, 0))
5510 && ! side_effects_p (XEXP (op0, 1)))
5513 /* If we have (ior (and A B) C), apply the distributive law and then
5514 the inverse distributive law to see if things simplify. */
5516 if (GET_CODE (op0) == AND)
5518 x = apply_distributive_law
5519 (gen_binary (AND, mode,
5520 gen_binary (IOR, mode, XEXP (op0, 0), op1),
5521 gen_binary (IOR, mode, XEXP (op0, 1),
5524 if (GET_CODE (x) != IOR)
5528 if (GET_CODE (op1) == AND)
5530 x = apply_distributive_law
5531 (gen_binary (AND, mode,
5532 gen_binary (IOR, mode, XEXP (op1, 0), op0),
5533 gen_binary (IOR, mode, XEXP (op1, 1),
5536 if (GET_CODE (x) != IOR)
5540 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5541 mode size to (rotate A CX). */
5543 if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
5544 || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
5545 && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
5546 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5547 && GET_CODE (XEXP (op1, 1)) == CONST_INT
5548 && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
5549 == GET_MODE_BITSIZE (mode)))
5550 return gen_rtx_ROTATE (mode, XEXP (op0, 0),
5551 (GET_CODE (op0) == ASHIFT
5552 ? XEXP (op0, 1) : XEXP (op1, 1)));
5554 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5555 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5556 does not affect any of the bits in OP1, it can really be done
5557 as a PLUS and we can associate. We do this by seeing if OP1
5558 can be safely shifted left C bits. */
5559 if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
5560 && GET_CODE (XEXP (op0, 0)) == PLUS
5561 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
5562 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5563 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
5565 int count = INTVAL (XEXP (op0, 1));
5566 HOST_WIDE_INT mask = INTVAL (op1) << count;
5568 if (mask >> count == INTVAL (op1)
5569 && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
5571 SUBST (XEXP (XEXP (op0, 0), 1),
5572 GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
5579 /* If we are XORing two things that have no bits in common,
5580 convert them into an IOR. This helps to detect rotation encoded
5581 using those methods and possibly other simplifications. */
5583 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5584 && (nonzero_bits (op0, mode)
5585 & nonzero_bits (op1, mode)) == 0)
5586 return (gen_binary (IOR, mode, op0, op1));
5588 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5589 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5592 int num_negated = 0;
5594 if (GET_CODE (op0) == NOT)
5595 num_negated++, op0 = XEXP (op0, 0);
5596 if (GET_CODE (op1) == NOT)
5597 num_negated++, op1 = XEXP (op1, 0);
5599 if (num_negated == 2)
5601 SUBST (XEXP (x, 0), op0);
5602 SUBST (XEXP (x, 1), op1);
5604 else if (num_negated == 1)
5606 simplify_gen_unary (NOT, mode, gen_binary (XOR, mode, op0, op1),
5610 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5611 correspond to a machine insn or result in further simplifications
5612 if B is a constant. */
5614 if (GET_CODE (op0) == AND
5615 && rtx_equal_p (XEXP (op0, 1), op1)
5616 && ! side_effects_p (op1))
5617 return gen_binary (AND, mode,
5618 simplify_gen_unary (NOT, mode, XEXP (op0, 0), mode),
5621 else if (GET_CODE (op0) == AND
5622 && rtx_equal_p (XEXP (op0, 0), op1)
5623 && ! side_effects_p (op1))
5624 return gen_binary (AND, mode,
5625 simplify_gen_unary (NOT, mode, XEXP (op0, 1), mode),
5628 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5629 comparison if STORE_FLAG_VALUE is 1. */
5630 if (STORE_FLAG_VALUE == 1
5631 && op1 == const1_rtx
5632 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5633 && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0),
5637 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5638 is (lt foo (const_int 0)), so we can perform the above
5639 simplification if STORE_FLAG_VALUE is 1. */
5641 if (STORE_FLAG_VALUE == 1
5642 && op1 == const1_rtx
5643 && GET_CODE (op0) == LSHIFTRT
5644 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5645 && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
5646 return gen_rtx_GE (mode, XEXP (op0, 0), const0_rtx);
5648 /* (xor (comparison foo bar) (const_int sign-bit))
5649 when STORE_FLAG_VALUE is the sign bit. */
5650 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5651 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5652 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5653 && op1 == const_true_rtx
5654 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5655 && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0),
5668 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5669 operations" because they can be replaced with two more basic operations.
5670 ZERO_EXTEND is also considered "compound" because it can be replaced with
5671 an AND operation, which is simpler, though only one operation.
5673 The function expand_compound_operation is called with an rtx expression
5674 and will convert it to the appropriate shifts and AND operations,
5675 simplifying at each stage.
5677 The function make_compound_operation is called to convert an expression
5678 consisting of shifts and ANDs into the equivalent compound expression.
5679 It is the inverse of this function, loosely speaking. */
5682 expand_compound_operation (rtx x)
5684 unsigned HOST_WIDE_INT pos = 0, len;
5686 unsigned int modewidth;
5689 switch (GET_CODE (x))
5694 /* We can't necessarily use a const_int for a multiword mode;
5695 it depends on implicitly extending the value.
5696 Since we don't know the right way to extend it,
5697 we can't tell whether the implicit way is right.
5699 Even for a mode that is no wider than a const_int,
5700 we can't win, because we need to sign extend one of its bits through
5701 the rest of it, and we don't know which bit. */
5702 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5705 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5706 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5707 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5708 reloaded. If not for that, MEM's would very rarely be safe.
5710 Reject MODEs bigger than a word, because we might not be able
5711 to reference a two-register group starting with an arbitrary register
5712 (and currently gen_lowpart might crash for a SUBREG). */
5714 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5717 /* Reject MODEs that aren't scalar integers because turning vector
5718 or complex modes into shifts causes problems. */
5720 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5723 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5724 /* If the inner object has VOIDmode (the only way this can happen
5725 is if it is an ASM_OPERANDS), we can't do anything since we don't
5726 know how much masking to do. */
5735 /* If the operand is a CLOBBER, just return it. */
5736 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5739 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5740 || GET_CODE (XEXP (x, 2)) != CONST_INT
5741 || GET_MODE (XEXP (x, 0)) == VOIDmode)
5744 /* Reject MODEs that aren't scalar integers because turning vector
5745 or complex modes into shifts causes problems. */
5747 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5750 len = INTVAL (XEXP (x, 1));
5751 pos = INTVAL (XEXP (x, 2));
5753 /* If this goes outside the object being extracted, replace the object
5754 with a (use (mem ...)) construct that only combine understands
5755 and is used only for this purpose. */
5756 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5757 SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0)));
5759 if (BITS_BIG_ENDIAN)
5760 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5767 /* Convert sign extension to zero extension, if we know that the high
5768 bit is not set, as this is easier to optimize. It will be converted
5769 back to cheaper alternative in make_extraction. */
5770 if (GET_CODE (x) == SIGN_EXTEND
5771 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5772 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
5773 & ~(((unsigned HOST_WIDE_INT)
5774 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5778 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
5779 rtx temp2 = expand_compound_operation (temp);
5781 /* Make sure this is a profitable operation. */
5782 if (rtx_cost (x, SET) > rtx_cost (temp2, SET))
5784 else if (rtx_cost (x, SET) > rtx_cost (temp, SET))
5790 /* We can optimize some special cases of ZERO_EXTEND. */
5791 if (GET_CODE (x) == ZERO_EXTEND)
5793 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5794 know that the last value didn't have any inappropriate bits
5796 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5797 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5798 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5799 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5800 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5801 return XEXP (XEXP (x, 0), 0);
5803 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5804 if (GET_CODE (XEXP (x, 0)) == SUBREG
5805 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5806 && subreg_lowpart_p (XEXP (x, 0))
5807 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5808 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5809 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5810 return SUBREG_REG (XEXP (x, 0));
5812 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5813 is a comparison and STORE_FLAG_VALUE permits. This is like
5814 the first case, but it works even when GET_MODE (x) is larger
5815 than HOST_WIDE_INT. */
5816 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5817 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5818 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) == '<'
5819 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5820 <= HOST_BITS_PER_WIDE_INT)
5821 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5822 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5823 return XEXP (XEXP (x, 0), 0);
5825 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5826 if (GET_CODE (XEXP (x, 0)) == SUBREG
5827 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5828 && subreg_lowpart_p (XEXP (x, 0))
5829 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == '<'
5830 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5831 <= HOST_BITS_PER_WIDE_INT)
5832 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5833 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5834 return SUBREG_REG (XEXP (x, 0));
5838 /* If we reach here, we want to return a pair of shifts. The inner
5839 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5840 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5841 logical depending on the value of UNSIGNEDP.
5843 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5844 converted into an AND of a shift.
5846 We must check for the case where the left shift would have a negative
5847 count. This can happen in a case like (x >> 31) & 255 on machines
5848 that can't shift by a constant. On those machines, we would first
5849 combine the shift with the AND to produce a variable-position
5850 extraction. Then the constant of 31 would be substituted in to produce
5851 a such a position. */
5853 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5854 if (modewidth + len >= pos)
5855 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5857 simplify_shift_const (NULL_RTX, ASHIFT,
5860 modewidth - pos - len),
5863 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5864 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5865 simplify_shift_const (NULL_RTX, LSHIFTRT,
5868 ((HOST_WIDE_INT) 1 << len) - 1);
5870 /* Any other cases we can't handle. */
5873 /* If we couldn't do this for some reason, return the original
5875 if (GET_CODE (tem) == CLOBBER)
5881 /* X is a SET which contains an assignment of one object into
5882 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5883 or certain SUBREGS). If possible, convert it into a series of
5886 We half-heartedly support variable positions, but do not at all
5887 support variable lengths. */
5890 expand_field_assignment (rtx x)
5893 rtx pos; /* Always counts from low bit. */
5896 enum machine_mode compute_mode;
5898 /* Loop until we find something we can't simplify. */
5901 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5902 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5904 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5905 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5906 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
5908 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5909 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5911 inner = XEXP (SET_DEST (x), 0);
5912 len = INTVAL (XEXP (SET_DEST (x), 1));
5913 pos = XEXP (SET_DEST (x), 2);
5915 /* If the position is constant and spans the width of INNER,
5916 surround INNER with a USE to indicate this. */
5917 if (GET_CODE (pos) == CONST_INT
5918 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5919 inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner);
5921 if (BITS_BIG_ENDIAN)
5923 if (GET_CODE (pos) == CONST_INT)
5924 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5926 else if (GET_CODE (pos) == MINUS
5927 && GET_CODE (XEXP (pos, 1)) == CONST_INT
5928 && (INTVAL (XEXP (pos, 1))
5929 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5930 /* If position is ADJUST - X, new position is X. */
5931 pos = XEXP (pos, 0);
5933 pos = gen_binary (MINUS, GET_MODE (pos),
5934 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
5940 /* A SUBREG between two modes that occupy the same numbers of words
5941 can be done by moving the SUBREG to the source. */
5942 else if (GET_CODE (SET_DEST (x)) == SUBREG
5943 /* We need SUBREGs to compute nonzero_bits properly. */
5944 && nonzero_sign_valid
5945 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5946 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5947 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5948 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5950 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
5951 gen_lowpart_for_combine
5952 (GET_MODE (SUBREG_REG (SET_DEST (x))),
5959 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5960 inner = SUBREG_REG (inner);
5962 compute_mode = GET_MODE (inner);
5964 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
5965 if (! SCALAR_INT_MODE_P (compute_mode))
5967 enum machine_mode imode;
5969 /* Don't do anything for vector or complex integral types. */
5970 if (! FLOAT_MODE_P (compute_mode))
5973 /* Try to find an integral mode to pun with. */
5974 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
5975 if (imode == BLKmode)
5978 compute_mode = imode;
5979 inner = gen_lowpart_for_combine (imode, inner);
5982 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5983 if (len < HOST_BITS_PER_WIDE_INT)
5984 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
5988 /* Now compute the equivalent expression. Make a copy of INNER
5989 for the SET_DEST in case it is a MEM into which we will substitute;
5990 we don't want shared RTL in that case. */
5992 (VOIDmode, copy_rtx (inner),
5993 gen_binary (IOR, compute_mode,
5994 gen_binary (AND, compute_mode,
5995 simplify_gen_unary (NOT, compute_mode,
6001 gen_binary (ASHIFT, compute_mode,
6002 gen_binary (AND, compute_mode,
6003 gen_lowpart_for_combine
6004 (compute_mode, SET_SRC (x)),
6012 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6013 it is an RTX that represents a variable starting position; otherwise,
6014 POS is the (constant) starting bit position (counted from the LSB).
6016 INNER may be a USE. This will occur when we started with a bitfield
6017 that went outside the boundary of the object in memory, which is
6018 allowed on most machines. To isolate this case, we produce a USE
6019 whose mode is wide enough and surround the MEM with it. The only
6020 code that understands the USE is this routine. If it is not removed,
6021 it will cause the resulting insn not to match.
6023 UNSIGNEDP is nonzero for an unsigned reference and zero for a
6026 IN_DEST is nonzero if this is a reference in the destination of a
6027 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6028 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6031 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
6032 ZERO_EXTRACT should be built even for bits starting at bit 0.
6034 MODE is the desired mode of the result (if IN_DEST == 0).
6036 The result is an RTX for the extraction or NULL_RTX if the target
6040 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
6041 rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
6042 int in_dest, int in_compare)
6044 /* This mode describes the size of the storage area
6045 to fetch the overall value from. Within that, we
6046 ignore the POS lowest bits, etc. */
6047 enum machine_mode is_mode = GET_MODE (inner);
6048 enum machine_mode inner_mode;
6049 enum machine_mode wanted_inner_mode = byte_mode;
6050 enum machine_mode wanted_inner_reg_mode = word_mode;
6051 enum machine_mode pos_mode = word_mode;
6052 enum machine_mode extraction_mode = word_mode;
6053 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
6056 rtx orig_pos_rtx = pos_rtx;
6057 HOST_WIDE_INT orig_pos;
6059 /* Get some information about INNER and get the innermost object. */
6060 if (GET_CODE (inner) == USE)
6061 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
6062 /* We don't need to adjust the position because we set up the USE
6063 to pretend that it was a full-word object. */
6064 spans_byte = 1, inner = XEXP (inner, 0);
6065 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6067 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
6068 consider just the QI as the memory to extract from.
6069 The subreg adds or removes high bits; its mode is
6070 irrelevant to the meaning of this extraction,
6071 since POS and LEN count from the lsb. */
6072 if (GET_CODE (SUBREG_REG (inner)) == MEM)
6073 is_mode = GET_MODE (SUBREG_REG (inner));
6074 inner = SUBREG_REG (inner);
6076 else if (GET_CODE (inner) == ASHIFT
6077 && GET_CODE (XEXP (inner, 1)) == CONST_INT
6078 && pos_rtx == 0 && pos == 0
6079 && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1)))
6081 /* We're extracting the least significant bits of an rtx
6082 (ashift X (const_int C)), where LEN > C. Extract the
6083 least significant (LEN - C) bits of X, giving an rtx
6084 whose mode is MODE, then shift it left C times. */
6085 new = make_extraction (mode, XEXP (inner, 0),
6086 0, 0, len - INTVAL (XEXP (inner, 1)),
6087 unsignedp, in_dest, in_compare);
6089 return gen_rtx_ASHIFT (mode, new, XEXP (inner, 1));
6092 inner_mode = GET_MODE (inner);
6094 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
6095 pos = INTVAL (pos_rtx), pos_rtx = 0;
6097 /* See if this can be done without an extraction. We never can if the
6098 width of the field is not the same as that of some integer mode. For
6099 registers, we can only avoid the extraction if the position is at the
6100 low-order bit and this is either not in the destination or we have the
6101 appropriate STRICT_LOW_PART operation available.
6103 For MEM, we can avoid an extract if the field starts on an appropriate
6104 boundary and we can change the mode of the memory reference. However,
6105 we cannot directly access the MEM if we have a USE and the underlying
6106 MEM is not TMODE. This combination means that MEM was being used in a
6107 context where bits outside its mode were being referenced; that is only
6108 valid in bit-field insns. */
6110 if (tmode != BLKmode
6111 && ! (spans_byte && inner_mode != tmode)
6112 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
6113 && GET_CODE (inner) != MEM
6115 || (GET_CODE (inner) == REG
6116 && have_insn_for (STRICT_LOW_PART, tmode))))
6117 || (GET_CODE (inner) == MEM && pos_rtx == 0
6119 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
6120 : BITS_PER_UNIT)) == 0
6121 /* We can't do this if we are widening INNER_MODE (it
6122 may not be aligned, for one thing). */
6123 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
6124 && (inner_mode == tmode
6125 || (! mode_dependent_address_p (XEXP (inner, 0))
6126 && ! MEM_VOLATILE_P (inner))))))
6128 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6129 field. If the original and current mode are the same, we need not
6130 adjust the offset. Otherwise, we do if bytes big endian.
6132 If INNER is not a MEM, get a piece consisting of just the field
6133 of interest (in this case POS % BITS_PER_WORD must be 0). */
6135 if (GET_CODE (inner) == MEM)
6137 HOST_WIDE_INT offset;
6139 /* POS counts from lsb, but make OFFSET count in memory order. */
6140 if (BYTES_BIG_ENDIAN)
6141 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
6143 offset = pos / BITS_PER_UNIT;
6145 new = adjust_address_nv (inner, tmode, offset);
6147 else if (GET_CODE (inner) == REG)
6149 if (tmode != inner_mode)
6153 /* We can't call gen_lowpart_for_combine here since we always want
6154 a SUBREG and it would sometimes return a new hard register. */
6155 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
6157 if (WORDS_BIG_ENDIAN
6158 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
6159 final_word = ((GET_MODE_SIZE (inner_mode)
6160 - GET_MODE_SIZE (tmode))
6161 / UNITS_PER_WORD) - final_word;
6163 final_word *= UNITS_PER_WORD;
6164 if (BYTES_BIG_ENDIAN &&
6165 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
6166 final_word += (GET_MODE_SIZE (inner_mode)
6167 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
6169 /* Avoid creating invalid subregs, for example when
6170 simplifying (x>>32)&255. */
6171 if (final_word >= GET_MODE_SIZE (inner_mode))
6174 new = gen_rtx_SUBREG (tmode, inner, final_word);
6177 new = gen_lowpart_for_combine (tmode, inner);
6183 new = force_to_mode (inner, tmode,
6184 len >= HOST_BITS_PER_WIDE_INT
6185 ? ~(unsigned HOST_WIDE_INT) 0
6186 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6189 /* If this extraction is going into the destination of a SET,
6190 make a STRICT_LOW_PART unless we made a MEM. */
6193 return (GET_CODE (new) == MEM ? new
6194 : (GET_CODE (new) != SUBREG
6195 ? gen_rtx_CLOBBER (tmode, const0_rtx)
6196 : gen_rtx_STRICT_LOW_PART (VOIDmode, new)));
6201 if (GET_CODE (new) == CONST_INT)
6202 return gen_int_mode (INTVAL (new), mode);
6204 /* If we know that no extraneous bits are set, and that the high
6205 bit is not set, convert the extraction to the cheaper of
6206 sign and zero extension, that are equivalent in these cases. */
6207 if (flag_expensive_optimizations
6208 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6209 && ((nonzero_bits (new, tmode)
6210 & ~(((unsigned HOST_WIDE_INT)
6211 GET_MODE_MASK (tmode))
6215 rtx temp = gen_rtx_ZERO_EXTEND (mode, new);
6216 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new);
6218 /* Prefer ZERO_EXTENSION, since it gives more information to
6220 if (rtx_cost (temp, SET) <= rtx_cost (temp1, SET))
6225 /* Otherwise, sign- or zero-extend unless we already are in the
6228 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6232 /* Unless this is a COMPARE or we have a funny memory reference,
6233 don't do anything with zero-extending field extracts starting at
6234 the low-order bit since they are simple AND operations. */
6235 if (pos_rtx == 0 && pos == 0 && ! in_dest
6236 && ! in_compare && ! spans_byte && unsignedp)
6239 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6240 we would be spanning bytes or if the position is not a constant and the
6241 length is not 1. In all other cases, we would only be going outside
6242 our object in cases when an original shift would have been
6244 if (! spans_byte && GET_CODE (inner) == MEM
6245 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6246 || (pos_rtx != 0 && len != 1)))
6249 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6250 and the mode for the result. */
6251 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6253 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6254 pos_mode = mode_for_extraction (EP_insv, 2);
6255 extraction_mode = mode_for_extraction (EP_insv, 3);
6258 if (! in_dest && unsignedp
6259 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6261 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6262 pos_mode = mode_for_extraction (EP_extzv, 3);
6263 extraction_mode = mode_for_extraction (EP_extzv, 0);
6266 if (! in_dest && ! unsignedp
6267 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6269 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6270 pos_mode = mode_for_extraction (EP_extv, 3);
6271 extraction_mode = mode_for_extraction (EP_extv, 0);
6274 /* Never narrow an object, since that might not be safe. */
6276 if (mode != VOIDmode
6277 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6278 extraction_mode = mode;
6280 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6281 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6282 pos_mode = GET_MODE (pos_rtx);
6284 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6285 if we have to change the mode of memory and cannot, the desired mode is
6287 if (GET_CODE (inner) != MEM)
6288 wanted_inner_mode = wanted_inner_reg_mode;
6289 else if (inner_mode != wanted_inner_mode
6290 && (mode_dependent_address_p (XEXP (inner, 0))
6291 || MEM_VOLATILE_P (inner)))
6292 wanted_inner_mode = extraction_mode;
6296 if (BITS_BIG_ENDIAN)
6298 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6299 BITS_BIG_ENDIAN style. If position is constant, compute new
6300 position. Otherwise, build subtraction.
6301 Note that POS is relative to the mode of the original argument.
6302 If it's a MEM we need to recompute POS relative to that.
6303 However, if we're extracting from (or inserting into) a register,
6304 we want to recompute POS relative to wanted_inner_mode. */
6305 int width = (GET_CODE (inner) == MEM
6306 ? GET_MODE_BITSIZE (is_mode)
6307 : GET_MODE_BITSIZE (wanted_inner_mode));
6310 pos = width - len - pos;
6313 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6314 /* POS may be less than 0 now, but we check for that below.
6315 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
6318 /* If INNER has a wider mode, make it smaller. If this is a constant
6319 extract, try to adjust the byte to point to the byte containing
6321 if (wanted_inner_mode != VOIDmode
6322 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6323 && ((GET_CODE (inner) == MEM
6324 && (inner_mode == wanted_inner_mode
6325 || (! mode_dependent_address_p (XEXP (inner, 0))
6326 && ! MEM_VOLATILE_P (inner))))))
6330 /* The computations below will be correct if the machine is big
6331 endian in both bits and bytes or little endian in bits and bytes.
6332 If it is mixed, we must adjust. */
6334 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6335 adjust OFFSET to compensate. */
6336 if (BYTES_BIG_ENDIAN
6338 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6339 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6341 /* If this is a constant position, we can move to the desired byte. */
6344 offset += pos / BITS_PER_UNIT;
6345 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6348 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6350 && is_mode != wanted_inner_mode)
6351 offset = (GET_MODE_SIZE (is_mode)
6352 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6354 if (offset != 0 || inner_mode != wanted_inner_mode)
6355 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6358 /* If INNER is not memory, we can always get it into the proper mode. If we
6359 are changing its mode, POS must be a constant and smaller than the size
6361 else if (GET_CODE (inner) != MEM)
6363 if (GET_MODE (inner) != wanted_inner_mode
6365 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6368 inner = force_to_mode (inner, wanted_inner_mode,
6370 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6371 ? ~(unsigned HOST_WIDE_INT) 0
6372 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6377 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6378 have to zero extend. Otherwise, we can just use a SUBREG. */
6380 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6382 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6384 /* If we know that no extraneous bits are set, and that the high
6385 bit is not set, convert extraction to cheaper one - either
6386 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6388 if (flag_expensive_optimizations
6389 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6390 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6391 & ~(((unsigned HOST_WIDE_INT)
6392 GET_MODE_MASK (GET_MODE (pos_rtx)))
6396 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6398 /* Prefer ZERO_EXTENSION, since it gives more information to
6400 if (rtx_cost (temp1, SET) < rtx_cost (temp, SET))
6405 else if (pos_rtx != 0
6406 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6407 pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
6409 /* Make POS_RTX unless we already have it and it is correct. If we don't
6410 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6412 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6413 pos_rtx = orig_pos_rtx;
6415 else if (pos_rtx == 0)
6416 pos_rtx = GEN_INT (pos);
6418 /* Make the required operation. See if we can use existing rtx. */
6419 new = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6420 extraction_mode, inner, GEN_INT (len), pos_rtx);
6422 new = gen_lowpart_for_combine (mode, new);
6427 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6428 with any other operations in X. Return X without that shift if so. */
6431 extract_left_shift (rtx x, int count)
6433 enum rtx_code code = GET_CODE (x);
6434 enum machine_mode mode = GET_MODE (x);
6440 /* This is the shift itself. If it is wide enough, we will return
6441 either the value being shifted if the shift count is equal to
6442 COUNT or a shift for the difference. */
6443 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6444 && INTVAL (XEXP (x, 1)) >= count)
6445 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6446 INTVAL (XEXP (x, 1)) - count);
6450 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6451 return simplify_gen_unary (code, mode, tem, mode);
6455 case PLUS: case IOR: case XOR: case AND:
6456 /* If we can safely shift this constant and we find the inner shift,
6457 make a new operation. */
6458 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6459 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6460 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6461 return gen_binary (code, mode, tem,
6462 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6473 /* Look at the expression rooted at X. Look for expressions
6474 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6475 Form these expressions.
6477 Return the new rtx, usually just X.
6479 Also, for machines like the VAX that don't have logical shift insns,
6480 try to convert logical to arithmetic shift operations in cases where
6481 they are equivalent. This undoes the canonicalizations to logical
6482 shifts done elsewhere.
6484 We try, as much as possible, to re-use rtl expressions to save memory.
6486 IN_CODE says what kind of expression we are processing. Normally, it is
6487 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6488 being kludges), it is MEM. When processing the arguments of a comparison
6489 or a COMPARE against zero, it is COMPARE. */
6492 make_compound_operation (rtx x, enum rtx_code in_code)
6494 enum rtx_code code = GET_CODE (x);
6495 enum machine_mode mode = GET_MODE (x);
6496 int mode_width = GET_MODE_BITSIZE (mode);
6498 enum rtx_code next_code;
6504 /* Select the code to be used in recursive calls. Once we are inside an
6505 address, we stay there. If we have a comparison, set to COMPARE,
6506 but once inside, go back to our default of SET. */
6508 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6509 : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
6510 && XEXP (x, 1) == const0_rtx) ? COMPARE
6511 : in_code == COMPARE ? SET : in_code);
6513 /* Process depending on the code of this operation. If NEW is set
6514 nonzero, it will be returned. */
6519 /* Convert shifts by constants into multiplications if inside
6521 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6522 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6523 && INTVAL (XEXP (x, 1)) >= 0)
6525 new = make_compound_operation (XEXP (x, 0), next_code);
6526 new = gen_rtx_MULT (mode, new,
6527 GEN_INT ((HOST_WIDE_INT) 1
6528 << INTVAL (XEXP (x, 1))));
6533 /* If the second operand is not a constant, we can't do anything
6535 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6538 /* If the constant is a power of two minus one and the first operand
6539 is a logical right shift, make an extraction. */
6540 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6541 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6543 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6544 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6545 0, in_code == COMPARE);
6548 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6549 else if (GET_CODE (XEXP (x, 0)) == SUBREG
6550 && subreg_lowpart_p (XEXP (x, 0))
6551 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6552 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6554 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6556 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6557 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6558 0, in_code == COMPARE);
6560 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6561 else if ((GET_CODE (XEXP (x, 0)) == XOR
6562 || GET_CODE (XEXP (x, 0)) == IOR)
6563 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6564 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6565 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6567 /* Apply the distributive law, and then try to make extractions. */
6568 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
6569 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6571 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6573 new = make_compound_operation (new, in_code);
6576 /* If we are have (and (rotate X C) M) and C is larger than the number
6577 of bits in M, this is an extraction. */
6579 else if (GET_CODE (XEXP (x, 0)) == ROTATE
6580 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6581 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6582 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6584 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6585 new = make_extraction (mode, new,
6586 (GET_MODE_BITSIZE (mode)
6587 - INTVAL (XEXP (XEXP (x, 0), 1))),
6588 NULL_RTX, i, 1, 0, in_code == COMPARE);
6591 /* On machines without logical shifts, if the operand of the AND is
6592 a logical shift and our mask turns off all the propagated sign
6593 bits, we can replace the logical shift with an arithmetic shift. */
6594 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6595 && !have_insn_for (LSHIFTRT, mode)
6596 && have_insn_for (ASHIFTRT, mode)
6597 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6598 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6599 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6600 && mode_width <= HOST_BITS_PER_WIDE_INT)
6602 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6604 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6605 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6607 gen_rtx_ASHIFTRT (mode,
6608 make_compound_operation
6609 (XEXP (XEXP (x, 0), 0), next_code),
6610 XEXP (XEXP (x, 0), 1)));
6613 /* If the constant is one less than a power of two, this might be
6614 representable by an extraction even if no shift is present.
6615 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6616 we are in a COMPARE. */
6617 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6618 new = make_extraction (mode,
6619 make_compound_operation (XEXP (x, 0),
6621 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6623 /* If we are in a comparison and this is an AND with a power of two,
6624 convert this into the appropriate bit extract. */
6625 else if (in_code == COMPARE
6626 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6627 new = make_extraction (mode,
6628 make_compound_operation (XEXP (x, 0),
6630 i, NULL_RTX, 1, 1, 0, 1);
6635 /* If the sign bit is known to be zero, replace this with an
6636 arithmetic shift. */
6637 if (have_insn_for (ASHIFTRT, mode)
6638 && ! have_insn_for (LSHIFTRT, mode)
6639 && mode_width <= HOST_BITS_PER_WIDE_INT
6640 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6642 new = gen_rtx_ASHIFTRT (mode,
6643 make_compound_operation (XEXP (x, 0),
6649 /* ... fall through ... */
6655 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6656 this is a SIGN_EXTRACT. */
6657 if (GET_CODE (rhs) == CONST_INT
6658 && GET_CODE (lhs) == ASHIFT
6659 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6660 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6662 new = make_compound_operation (XEXP (lhs, 0), next_code);
6663 new = make_extraction (mode, new,
6664 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6665 NULL_RTX, mode_width - INTVAL (rhs),
6666 code == LSHIFTRT, 0, in_code == COMPARE);
6670 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6671 If so, try to merge the shifts into a SIGN_EXTEND. We could
6672 also do this for some cases of SIGN_EXTRACT, but it doesn't
6673 seem worth the effort; the case checked for occurs on Alpha. */
6675 if (GET_RTX_CLASS (GET_CODE (lhs)) != 'o'
6676 && ! (GET_CODE (lhs) == SUBREG
6677 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs))) == 'o'))
6678 && GET_CODE (rhs) == CONST_INT
6679 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6680 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6681 new = make_extraction (mode, make_compound_operation (new, next_code),
6682 0, NULL_RTX, mode_width - INTVAL (rhs),
6683 code == LSHIFTRT, 0, in_code == COMPARE);
6688 /* Call ourselves recursively on the inner expression. If we are
6689 narrowing the object and it has a different RTL code from
6690 what it originally did, do this SUBREG as a force_to_mode. */
6692 tem = make_compound_operation (SUBREG_REG (x), in_code);
6693 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6694 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6695 && subreg_lowpart_p (x))
6697 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
6700 /* If we have something other than a SUBREG, we might have
6701 done an expansion, so rerun ourselves. */
6702 if (GET_CODE (newer) != SUBREG)
6703 newer = make_compound_operation (newer, in_code);
6708 /* If this is a paradoxical subreg, and the new code is a sign or
6709 zero extension, omit the subreg and widen the extension. If it
6710 is a regular subreg, we can still get rid of the subreg by not
6711 widening so much, or in fact removing the extension entirely. */
6712 if ((GET_CODE (tem) == SIGN_EXTEND
6713 || GET_CODE (tem) == ZERO_EXTEND)
6714 && subreg_lowpart_p (x))
6716 if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (tem))
6717 || (GET_MODE_SIZE (mode) >
6718 GET_MODE_SIZE (GET_MODE (XEXP (tem, 0)))))
6720 if (! SCALAR_INT_MODE_P (mode))
6722 tem = gen_rtx_fmt_e (GET_CODE (tem), mode, XEXP (tem, 0));
6725 tem = gen_lowpart_for_combine (mode, XEXP (tem, 0));
6736 x = gen_lowpart_for_combine (mode, new);
6737 code = GET_CODE (x);
6740 /* Now recursively process each operand of this operation. */
6741 fmt = GET_RTX_FORMAT (code);
6742 for (i = 0; i < GET_RTX_LENGTH (code); i++)
6745 new = make_compound_operation (XEXP (x, i), next_code);
6746 SUBST (XEXP (x, i), new);
6752 /* Given M see if it is a value that would select a field of bits
6753 within an item, but not the entire word. Return -1 if not.
6754 Otherwise, return the starting position of the field, where 0 is the
6757 *PLEN is set to the length of the field. */
6760 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
6762 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6763 int pos = exact_log2 (m & -m);
6769 /* Now shift off the low-order zero bits and see if we have a power of
6771 len = exact_log2 ((m >> pos) + 1);
6780 /* See if X can be simplified knowing that we will only refer to it in
6781 MODE and will only refer to those bits that are nonzero in MASK.
6782 If other bits are being computed or if masking operations are done
6783 that select a superset of the bits in MASK, they can sometimes be
6786 Return a possibly simplified expression, but always convert X to
6787 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6789 Also, if REG is nonzero and X is a register equal in value to REG,
6792 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6793 are all off in X. This is used when X will be complemented, by either
6794 NOT, NEG, or XOR. */
6797 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
6798 rtx reg, int just_select)
6800 enum rtx_code code = GET_CODE (x);
6801 int next_select = just_select || code == XOR || code == NOT || code == NEG;
6802 enum machine_mode op_mode;
6803 unsigned HOST_WIDE_INT fuller_mask, nonzero;
6806 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6807 code below will do the wrong thing since the mode of such an
6808 expression is VOIDmode.
6810 Also do nothing if X is a CLOBBER; this can happen if X was
6811 the return value from a call to gen_lowpart_for_combine. */
6812 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
6815 /* We want to perform the operation is its present mode unless we know
6816 that the operation is valid in MODE, in which case we do the operation
6818 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6819 && have_insn_for (code, mode))
6820 ? mode : GET_MODE (x));
6822 /* It is not valid to do a right-shift in a narrower mode
6823 than the one it came in with. */
6824 if ((code == LSHIFTRT || code == ASHIFTRT)
6825 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6826 op_mode = GET_MODE (x);
6828 /* Truncate MASK to fit OP_MODE. */
6830 mask &= GET_MODE_MASK (op_mode);
6832 /* When we have an arithmetic operation, or a shift whose count we
6833 do not know, we need to assume that all bit the up to the highest-order
6834 bit in MASK will be needed. This is how we form such a mask. */
6836 fuller_mask = (GET_MODE_BITSIZE (op_mode) >= HOST_BITS_PER_WIDE_INT
6837 ? GET_MODE_MASK (op_mode)
6838 : (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
6841 fuller_mask = ~(HOST_WIDE_INT) 0;
6843 /* Determine what bits of X are guaranteed to be (non)zero. */
6844 nonzero = nonzero_bits (x, mode);
6846 /* If none of the bits in X are needed, return a zero. */
6847 if (! just_select && (nonzero & mask) == 0)
6850 /* If X is a CONST_INT, return a new one. Do this here since the
6851 test below will fail. */
6852 if (GET_CODE (x) == CONST_INT)
6854 if (SCALAR_INT_MODE_P (mode))
6855 return gen_int_mode (INTVAL (x) & mask, mode);
6858 x = GEN_INT (INTVAL (x) & mask);
6859 return gen_lowpart_common (mode, x);
6863 /* If X is narrower than MODE and we want all the bits in X's mode, just
6864 get X in the proper mode. */
6865 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6866 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
6867 return gen_lowpart_for_combine (mode, x);
6869 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6870 MASK are already known to be zero in X, we need not do anything. */
6871 if (GET_MODE (x) == mode && code != SUBREG && (~mask & nonzero) == 0)
6877 /* If X is a (clobber (const_int)), return it since we know we are
6878 generating something that won't match. */
6882 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6883 spanned the boundary of the MEM. If we are now masking so it is
6884 within that boundary, we don't need the USE any more. */
6885 if (! BITS_BIG_ENDIAN
6886 && (mask & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6887 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6894 x = expand_compound_operation (x);
6895 if (GET_CODE (x) != code)
6896 return force_to_mode (x, mode, mask, reg, next_select);
6900 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
6901 || rtx_equal_p (reg, get_last_value (x))))
6906 if (subreg_lowpart_p (x)
6907 /* We can ignore the effect of this SUBREG if it narrows the mode or
6908 if the constant masks to zero all the bits the mode doesn't
6910 && ((GET_MODE_SIZE (GET_MODE (x))
6911 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6913 & GET_MODE_MASK (GET_MODE (x))
6914 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6915 return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
6919 /* If this is an AND with a constant, convert it into an AND
6920 whose constant is the AND of that constant with MASK. If it
6921 remains an AND of MASK, delete it since it is redundant. */
6923 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6925 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6926 mask & INTVAL (XEXP (x, 1)));
6928 /* If X is still an AND, see if it is an AND with a mask that
6929 is just some low-order bits. If so, and it is MASK, we don't
6932 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6933 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
6937 /* If it remains an AND, try making another AND with the bits
6938 in the mode mask that aren't in MASK turned on. If the
6939 constant in the AND is wide enough, this might make a
6940 cheaper constant. */
6942 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6943 && GET_MODE_MASK (GET_MODE (x)) != mask
6944 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
6946 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6947 | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
6948 int width = GET_MODE_BITSIZE (GET_MODE (x));
6951 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6952 number, sign extend it. */
6953 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6954 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6955 cval |= (HOST_WIDE_INT) -1 << width;
6957 y = gen_binary (AND, GET_MODE (x), XEXP (x, 0), GEN_INT (cval));
6958 if (rtx_cost (y, SET) < rtx_cost (x, SET))
6968 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6969 low-order bits (as in an alignment operation) and FOO is already
6970 aligned to that boundary, mask C1 to that boundary as well.
6971 This may eliminate that PLUS and, later, the AND. */
6974 unsigned int width = GET_MODE_BITSIZE (mode);
6975 unsigned HOST_WIDE_INT smask = mask;
6977 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6978 number, sign extend it. */
6980 if (width < HOST_BITS_PER_WIDE_INT
6981 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6982 smask |= (HOST_WIDE_INT) -1 << width;
6984 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6985 && exact_log2 (- smask) >= 0
6986 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
6987 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
6988 return force_to_mode (plus_constant (XEXP (x, 0),
6989 (INTVAL (XEXP (x, 1)) & smask)),
6990 mode, smask, reg, next_select);
6993 /* ... fall through ... */
6996 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6997 most significant bit in MASK since carries from those bits will
6998 affect the bits we are interested in. */
7003 /* If X is (minus C Y) where C's least set bit is larger than any bit
7004 in the mask, then we may replace with (neg Y). */
7005 if (GET_CODE (XEXP (x, 0)) == CONST_INT
7006 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
7007 & -INTVAL (XEXP (x, 0))))
7010 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
7012 return force_to_mode (x, mode, mask, reg, next_select);
7015 /* Similarly, if C contains every bit in the fuller_mask, then we may
7016 replace with (not Y). */
7017 if (GET_CODE (XEXP (x, 0)) == CONST_INT
7018 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask)
7019 == INTVAL (XEXP (x, 0))))
7021 x = simplify_gen_unary (NOT, GET_MODE (x),
7022 XEXP (x, 1), GET_MODE (x));
7023 return force_to_mode (x, mode, mask, reg, next_select);
7031 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7032 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7033 operation which may be a bitfield extraction. Ensure that the
7034 constant we form is not wider than the mode of X. */
7036 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7037 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7038 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7039 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7040 && GET_CODE (XEXP (x, 1)) == CONST_INT
7041 && ((INTVAL (XEXP (XEXP (x, 0), 1))
7042 + floor_log2 (INTVAL (XEXP (x, 1))))
7043 < GET_MODE_BITSIZE (GET_MODE (x)))
7044 && (INTVAL (XEXP (x, 1))
7045 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
7047 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
7048 << INTVAL (XEXP (XEXP (x, 0), 1)));
7049 temp = gen_binary (GET_CODE (x), GET_MODE (x),
7050 XEXP (XEXP (x, 0), 0), temp);
7051 x = gen_binary (LSHIFTRT, GET_MODE (x), temp,
7052 XEXP (XEXP (x, 0), 1));
7053 return force_to_mode (x, mode, mask, reg, next_select);
7057 /* For most binary operations, just propagate into the operation and
7058 change the mode if we have an operation of that mode. */
7060 op0 = gen_lowpart_for_combine (op_mode,
7061 force_to_mode (XEXP (x, 0), mode, mask,
7063 op1 = gen_lowpart_for_combine (op_mode,
7064 force_to_mode (XEXP (x, 1), mode, mask,
7067 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7068 x = gen_binary (code, op_mode, op0, op1);
7072 /* For left shifts, do the same, but just for the first operand.
7073 However, we cannot do anything with shifts where we cannot
7074 guarantee that the counts are smaller than the size of the mode
7075 because such a count will have a different meaning in a
7078 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
7079 && INTVAL (XEXP (x, 1)) >= 0
7080 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
7081 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
7082 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
7083 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
7086 /* If the shift count is a constant and we can do arithmetic in
7087 the mode of the shift, refine which bits we need. Otherwise, use the
7088 conservative form of the mask. */
7089 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7090 && INTVAL (XEXP (x, 1)) >= 0
7091 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
7092 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7093 mask >>= INTVAL (XEXP (x, 1));
7097 op0 = gen_lowpart_for_combine (op_mode,
7098 force_to_mode (XEXP (x, 0), op_mode,
7099 mask, reg, next_select));
7101 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7102 x = gen_binary (code, op_mode, op0, XEXP (x, 1));
7106 /* Here we can only do something if the shift count is a constant,
7107 this shift constant is valid for the host, and we can do arithmetic
7110 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7111 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7112 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7114 rtx inner = XEXP (x, 0);
7115 unsigned HOST_WIDE_INT inner_mask;
7117 /* Select the mask of the bits we need for the shift operand. */
7118 inner_mask = mask << INTVAL (XEXP (x, 1));
7120 /* We can only change the mode of the shift if we can do arithmetic
7121 in the mode of the shift and INNER_MASK is no wider than the
7122 width of OP_MODE. */
7123 if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT
7124 || (inner_mask & ~GET_MODE_MASK (op_mode)) != 0)
7125 op_mode = GET_MODE (x);
7127 inner = force_to_mode (inner, op_mode, inner_mask, reg, next_select);
7129 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
7130 x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
7133 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7134 shift and AND produces only copies of the sign bit (C2 is one less
7135 than a power of two), we can do this with just a shift. */
7137 if (GET_CODE (x) == LSHIFTRT
7138 && GET_CODE (XEXP (x, 1)) == CONST_INT
7139 /* The shift puts one of the sign bit copies in the least significant
7141 && ((INTVAL (XEXP (x, 1))
7142 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7143 >= GET_MODE_BITSIZE (GET_MODE (x)))
7144 && exact_log2 (mask + 1) >= 0
7145 /* Number of bits left after the shift must be more than the mask
7147 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7148 <= GET_MODE_BITSIZE (GET_MODE (x)))
7149 /* Must be more sign bit copies than the mask needs. */
7150 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7151 >= exact_log2 (mask + 1)))
7152 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7153 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7154 - exact_log2 (mask + 1)));
7159 /* If we are just looking for the sign bit, we don't need this shift at
7160 all, even if it has a variable count. */
7161 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7162 && (mask == ((unsigned HOST_WIDE_INT) 1
7163 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7164 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7166 /* If this is a shift by a constant, get a mask that contains those bits
7167 that are not copies of the sign bit. We then have two cases: If
7168 MASK only includes those bits, this can be a logical shift, which may
7169 allow simplifications. If MASK is a single-bit field not within
7170 those bits, we are requesting a copy of the sign bit and hence can
7171 shift the sign bit to the appropriate location. */
7173 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
7174 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7178 /* If the considered data is wider than HOST_WIDE_INT, we can't
7179 represent a mask for all its bits in a single scalar.
7180 But we only care about the lower bits, so calculate these. */
7182 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7184 nonzero = ~(HOST_WIDE_INT) 0;
7186 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7187 is the number of bits a full-width mask would have set.
7188 We need only shift if these are fewer than nonzero can
7189 hold. If not, we must keep all bits set in nonzero. */
7191 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7192 < HOST_BITS_PER_WIDE_INT)
7193 nonzero >>= INTVAL (XEXP (x, 1))
7194 + HOST_BITS_PER_WIDE_INT
7195 - GET_MODE_BITSIZE (GET_MODE (x)) ;
7199 nonzero = GET_MODE_MASK (GET_MODE (x));
7200 nonzero >>= INTVAL (XEXP (x, 1));
7203 if ((mask & ~nonzero) == 0
7204 || (i = exact_log2 (mask)) >= 0)
7206 x = simplify_shift_const
7207 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7208 i < 0 ? INTVAL (XEXP (x, 1))
7209 : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7211 if (GET_CODE (x) != ASHIFTRT)
7212 return force_to_mode (x, mode, mask, reg, next_select);
7216 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7217 even if the shift count isn't a constant. */
7219 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1));
7223 /* If this is a zero- or sign-extension operation that just affects bits
7224 we don't care about, remove it. Be sure the call above returned
7225 something that is still a shift. */
7227 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7228 && GET_CODE (XEXP (x, 1)) == CONST_INT
7229 && INTVAL (XEXP (x, 1)) >= 0
7230 && (INTVAL (XEXP (x, 1))
7231 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7232 && GET_CODE (XEXP (x, 0)) == ASHIFT
7233 && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
7234 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7241 /* If the shift count is constant and we can do computations
7242 in the mode of X, compute where the bits we care about are.
7243 Otherwise, we can't do anything. Don't change the mode of
7244 the shift or propagate MODE into the shift, though. */
7245 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7246 && INTVAL (XEXP (x, 1)) >= 0)
7248 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7249 GET_MODE (x), GEN_INT (mask),
7251 if (temp && GET_CODE (temp) == CONST_INT)
7253 force_to_mode (XEXP (x, 0), GET_MODE (x),
7254 INTVAL (temp), reg, next_select));
7259 /* If we just want the low-order bit, the NEG isn't needed since it
7260 won't change the low-order bit. */
7262 return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
7264 /* We need any bits less significant than the most significant bit in
7265 MASK since carries from those bits will affect the bits we are
7271 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7272 same as the XOR case above. Ensure that the constant we form is not
7273 wider than the mode of X. */
7275 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7276 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7277 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7278 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7279 < GET_MODE_BITSIZE (GET_MODE (x)))
7280 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7282 temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
7284 temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp);
7285 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1));
7287 return force_to_mode (x, mode, mask, reg, next_select);
7290 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7291 use the full mask inside the NOT. */
7295 op0 = gen_lowpart_for_combine (op_mode,
7296 force_to_mode (XEXP (x, 0), mode, mask,
7298 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7299 x = simplify_gen_unary (code, op_mode, op0, op_mode);
7303 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7304 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7305 which is equal to STORE_FLAG_VALUE. */
7306 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7307 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7308 && (nonzero_bits (XEXP (x, 0), mode)
7309 == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
7310 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7315 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7316 written in a narrower mode. We play it safe and do not do so. */
7319 gen_lowpart_for_combine (GET_MODE (x),
7320 force_to_mode (XEXP (x, 1), mode,
7321 mask, reg, next_select)));
7323 gen_lowpart_for_combine (GET_MODE (x),
7324 force_to_mode (XEXP (x, 2), mode,
7325 mask, reg, next_select)));
7332 /* Ensure we return a value of the proper mode. */
7333 return gen_lowpart_for_combine (mode, x);
7336 /* Return nonzero if X is an expression that has one of two values depending on
7337 whether some other value is zero or nonzero. In that case, we return the
7338 value that is being tested, *PTRUE is set to the value if the rtx being
7339 returned has a nonzero value, and *PFALSE is set to the other alternative.
7341 If we return zero, we set *PTRUE and *PFALSE to X. */
7344 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
7346 enum machine_mode mode = GET_MODE (x);
7347 enum rtx_code code = GET_CODE (x);
7348 rtx cond0, cond1, true0, true1, false0, false1;
7349 unsigned HOST_WIDE_INT nz;
7351 /* If we are comparing a value against zero, we are done. */
7352 if ((code == NE || code == EQ)
7353 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 0)
7355 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7356 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7360 /* If this is a unary operation whose operand has one of two values, apply
7361 our opcode to compute those values. */
7362 else if (GET_RTX_CLASS (code) == '1'
7363 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7365 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
7366 *pfalse = simplify_gen_unary (code, mode, false0,
7367 GET_MODE (XEXP (x, 0)));
7371 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7372 make can't possibly match and would suppress other optimizations. */
7373 else if (code == COMPARE)
7376 /* If this is a binary operation, see if either side has only one of two
7377 values. If either one does or if both do and they are conditional on
7378 the same value, compute the new true and false values. */
7379 else if (GET_RTX_CLASS (code) == 'c' || GET_RTX_CLASS (code) == '2'
7380 || GET_RTX_CLASS (code) == '<')
7382 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7383 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7385 if ((cond0 != 0 || cond1 != 0)
7386 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7388 /* If if_then_else_cond returned zero, then true/false are the
7389 same rtl. We must copy one of them to prevent invalid rtl
7392 true0 = copy_rtx (true0);
7393 else if (cond1 == 0)
7394 true1 = copy_rtx (true1);
7396 *ptrue = gen_binary (code, mode, true0, true1);
7397 *pfalse = gen_binary (code, mode, false0, false1);
7398 return cond0 ? cond0 : cond1;
7401 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7402 operands is zero when the other is nonzero, and vice-versa,
7403 and STORE_FLAG_VALUE is 1 or -1. */
7405 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7406 && (code == PLUS || code == IOR || code == XOR || code == MINUS
7408 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7410 rtx op0 = XEXP (XEXP (x, 0), 1);
7411 rtx op1 = XEXP (XEXP (x, 1), 1);
7413 cond0 = XEXP (XEXP (x, 0), 0);
7414 cond1 = XEXP (XEXP (x, 1), 0);
7416 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7417 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7418 && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1)
7419 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7420 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7421 || ((swap_condition (GET_CODE (cond0))
7422 == combine_reversed_comparison_code (cond1))
7423 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7424 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7425 && ! side_effects_p (x))
7427 *ptrue = gen_binary (MULT, mode, op0, const_true_rtx);
7428 *pfalse = gen_binary (MULT, mode,
7430 ? simplify_gen_unary (NEG, mode, op1,
7438 /* Similarly for MULT, AND and UMIN, except that for these the result
7440 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7441 && (code == MULT || code == AND || code == UMIN)
7442 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7444 cond0 = XEXP (XEXP (x, 0), 0);
7445 cond1 = XEXP (XEXP (x, 1), 0);
7447 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7448 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7449 && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1)
7450 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7451 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7452 || ((swap_condition (GET_CODE (cond0))
7453 == combine_reversed_comparison_code (cond1))
7454 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7455 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7456 && ! side_effects_p (x))
7458 *ptrue = *pfalse = const0_rtx;
7464 else if (code == IF_THEN_ELSE)
7466 /* If we have IF_THEN_ELSE already, extract the condition and
7467 canonicalize it if it is NE or EQ. */
7468 cond0 = XEXP (x, 0);
7469 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7470 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7471 return XEXP (cond0, 0);
7472 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7474 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7475 return XEXP (cond0, 0);
7481 /* If X is a SUBREG, we can narrow both the true and false values
7482 if the inner expression, if there is a condition. */
7483 else if (code == SUBREG
7484 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7487 *ptrue = simplify_gen_subreg (mode, true0,
7488 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7489 *pfalse = simplify_gen_subreg (mode, false0,
7490 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7495 /* If X is a constant, this isn't special and will cause confusions
7496 if we treat it as such. Likewise if it is equivalent to a constant. */
7497 else if (CONSTANT_P (x)
7498 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7501 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7502 will be least confusing to the rest of the compiler. */
7503 else if (mode == BImode)
7505 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
7509 /* If X is known to be either 0 or -1, those are the true and
7510 false values when testing X. */
7511 else if (x == constm1_rtx || x == const0_rtx
7512 || (mode != VOIDmode
7513 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
7515 *ptrue = constm1_rtx, *pfalse = const0_rtx;
7519 /* Likewise for 0 or a single bit. */
7520 else if (mode != VOIDmode
7521 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7522 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7524 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
7528 /* Otherwise fail; show no condition with true and false values the same. */
7529 *ptrue = *pfalse = x;
7533 /* Return the value of expression X given the fact that condition COND
7534 is known to be true when applied to REG as its first operand and VAL
7535 as its second. X is known to not be shared and so can be modified in
7538 We only handle the simplest cases, and specifically those cases that
7539 arise with IF_THEN_ELSE expressions. */
7542 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
7544 enum rtx_code code = GET_CODE (x);
7549 if (side_effects_p (x))
7552 /* If either operand of the condition is a floating point value,
7553 then we have to avoid collapsing an EQ comparison. */
7555 && rtx_equal_p (x, reg)
7556 && ! FLOAT_MODE_P (GET_MODE (x))
7557 && ! FLOAT_MODE_P (GET_MODE (val)))
7560 if (cond == UNEQ && rtx_equal_p (x, reg))
7563 /* If X is (abs REG) and we know something about REG's relationship
7564 with zero, we may be able to simplify this. */
7566 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
7569 case GE: case GT: case EQ:
7572 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
7574 GET_MODE (XEXP (x, 0)));
7579 /* The only other cases we handle are MIN, MAX, and comparisons if the
7580 operands are the same as REG and VAL. */
7582 else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
7584 if (rtx_equal_p (XEXP (x, 0), val))
7585 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
7587 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
7589 if (GET_RTX_CLASS (code) == '<')
7591 if (comparison_dominates_p (cond, code))
7592 return const_true_rtx;
7594 code = combine_reversed_comparison_code (x);
7596 && comparison_dominates_p (cond, code))
7601 else if (code == SMAX || code == SMIN
7602 || code == UMIN || code == UMAX)
7604 int unsignedp = (code == UMIN || code == UMAX);
7606 /* Do not reverse the condition when it is NE or EQ.
7607 This is because we cannot conclude anything about
7608 the value of 'SMAX (x, y)' when x is not equal to y,
7609 but we can when x equals y. */
7610 if ((code == SMAX || code == UMAX)
7611 && ! (cond == EQ || cond == NE))
7612 cond = reverse_condition (cond);
7617 return unsignedp ? x : XEXP (x, 1);
7619 return unsignedp ? x : XEXP (x, 0);
7621 return unsignedp ? XEXP (x, 1) : x;
7623 return unsignedp ? XEXP (x, 0) : x;
7630 else if (code == SUBREG)
7632 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
7633 rtx new, r = known_cond (SUBREG_REG (x), cond, reg, val);
7635 if (SUBREG_REG (x) != r)
7637 /* We must simplify subreg here, before we lose track of the
7638 original inner_mode. */
7639 new = simplify_subreg (GET_MODE (x), r,
7640 inner_mode, SUBREG_BYTE (x));
7644 SUBST (SUBREG_REG (x), r);
7649 /* We don't have to handle SIGN_EXTEND here, because even in the
7650 case of replacing something with a modeless CONST_INT, a
7651 CONST_INT is already (supposed to be) a valid sign extension for
7652 its narrower mode, which implies it's already properly
7653 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
7654 story is different. */
7655 else if (code == ZERO_EXTEND)
7657 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
7658 rtx new, r = known_cond (XEXP (x, 0), cond, reg, val);
7660 if (XEXP (x, 0) != r)
7662 /* We must simplify the zero_extend here, before we lose
7663 track of the original inner_mode. */
7664 new = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
7669 SUBST (XEXP (x, 0), r);
7675 fmt = GET_RTX_FORMAT (code);
7676 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7679 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7680 else if (fmt[i] == 'E')
7681 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7682 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7689 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7690 assignment as a field assignment. */
7693 rtx_equal_for_field_assignment_p (rtx x, rtx y)
7695 if (x == y || rtx_equal_p (x, y))
7698 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7701 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7702 Note that all SUBREGs of MEM are paradoxical; otherwise they
7703 would have been rewritten. */
7704 if (GET_CODE (x) == MEM && GET_CODE (y) == SUBREG
7705 && GET_CODE (SUBREG_REG (y)) == MEM
7706 && rtx_equal_p (SUBREG_REG (y),
7707 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y)), x)))
7710 if (GET_CODE (y) == MEM && GET_CODE (x) == SUBREG
7711 && GET_CODE (SUBREG_REG (x)) == MEM
7712 && rtx_equal_p (SUBREG_REG (x),
7713 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x)), y)))
7716 /* We used to see if get_last_value of X and Y were the same but that's
7717 not correct. In one direction, we'll cause the assignment to have
7718 the wrong destination and in the case, we'll import a register into this
7719 insn that might have already have been dead. So fail if none of the
7720 above cases are true. */
7724 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7725 Return that assignment if so.
7727 We only handle the most common cases. */
7730 make_field_assignment (rtx x)
7732 rtx dest = SET_DEST (x);
7733 rtx src = SET_SRC (x);
7738 unsigned HOST_WIDE_INT len;
7740 enum machine_mode mode;
7742 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7743 a clear of a one-bit field. We will have changed it to
7744 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7747 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7748 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7749 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7750 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7752 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7755 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7759 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7760 && subreg_lowpart_p (XEXP (src, 0))
7761 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7762 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7763 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7764 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7765 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7767 assign = make_extraction (VOIDmode, dest, 0,
7768 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7771 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7775 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7777 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7778 && XEXP (XEXP (src, 0), 0) == const1_rtx
7779 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7781 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7784 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
7788 /* The other case we handle is assignments into a constant-position
7789 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7790 a mask that has all one bits except for a group of zero bits and
7791 OTHER is known to have zeros where C1 has ones, this is such an
7792 assignment. Compute the position and length from C1. Shift OTHER
7793 to the appropriate position, force it to the required mode, and
7794 make the extraction. Check for the AND in both operands. */
7796 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
7799 rhs = expand_compound_operation (XEXP (src, 0));
7800 lhs = expand_compound_operation (XEXP (src, 1));
7802 if (GET_CODE (rhs) == AND
7803 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7804 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7805 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7806 else if (GET_CODE (lhs) == AND
7807 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7808 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7809 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
7813 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
7814 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
7815 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7816 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
7819 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
7823 /* The mode to use for the source is the mode of the assignment, or of
7824 what is inside a possible STRICT_LOW_PART. */
7825 mode = (GET_CODE (assign) == STRICT_LOW_PART
7826 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
7828 /* Shift OTHER right POS places and make it the source, restricting it
7829 to the proper length and mode. */
7831 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
7832 GET_MODE (src), other, pos),
7834 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7835 ? ~(unsigned HOST_WIDE_INT) 0
7836 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7839 /* If SRC is masked by an AND that does not make a difference in
7840 the value being stored, strip it. */
7841 if (GET_CODE (assign) == ZERO_EXTRACT
7842 && GET_CODE (XEXP (assign, 1)) == CONST_INT
7843 && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
7844 && GET_CODE (src) == AND
7845 && GET_CODE (XEXP (src, 1)) == CONST_INT
7846 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (src, 1))
7847 == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1))
7848 src = XEXP (src, 0);
7850 return gen_rtx_SET (VOIDmode, assign, src);
7853 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7857 apply_distributive_law (rtx x)
7859 enum rtx_code code = GET_CODE (x);
7860 rtx lhs, rhs, other;
7862 enum rtx_code inner_code;
7864 /* Distributivity is not true for floating point.
7865 It can change the value. So don't do it.
7866 -- rms and moshier@world.std.com. */
7867 if (FLOAT_MODE_P (GET_MODE (x)))
7870 /* The outer operation can only be one of the following: */
7871 if (code != IOR && code != AND && code != XOR
7872 && code != PLUS && code != MINUS)
7875 lhs = XEXP (x, 0), rhs = XEXP (x, 1);
7877 /* If either operand is a primitive we can't do anything, so get out
7879 if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
7880 || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
7883 lhs = expand_compound_operation (lhs);
7884 rhs = expand_compound_operation (rhs);
7885 inner_code = GET_CODE (lhs);
7886 if (inner_code != GET_CODE (rhs))
7889 /* See if the inner and outer operations distribute. */
7896 /* These all distribute except over PLUS. */
7897 if (code == PLUS || code == MINUS)
7902 if (code != PLUS && code != MINUS)
7907 /* This is also a multiply, so it distributes over everything. */
7911 /* Non-paradoxical SUBREGs distributes over all operations, provided
7912 the inner modes and byte offsets are the same, this is an extraction
7913 of a low-order part, we don't convert an fp operation to int or
7914 vice versa, and we would not be converting a single-word
7915 operation into a multi-word operation. The latter test is not
7916 required, but it prevents generating unneeded multi-word operations.
7917 Some of the previous tests are redundant given the latter test, but
7918 are retained because they are required for correctness.
7920 We produce the result slightly differently in this case. */
7922 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7923 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
7924 || ! subreg_lowpart_p (lhs)
7925 || (GET_MODE_CLASS (GET_MODE (lhs))
7926 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
7927 || (GET_MODE_SIZE (GET_MODE (lhs))
7928 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
7929 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
7932 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
7933 SUBREG_REG (lhs), SUBREG_REG (rhs));
7934 return gen_lowpart_for_combine (GET_MODE (x), tem);
7940 /* Set LHS and RHS to the inner operands (A and B in the example
7941 above) and set OTHER to the common operand (C in the example).
7942 These is only one way to do this unless the inner operation is
7944 if (GET_RTX_CLASS (inner_code) == 'c'
7945 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
7946 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
7947 else if (GET_RTX_CLASS (inner_code) == 'c'
7948 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
7949 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
7950 else if (GET_RTX_CLASS (inner_code) == 'c'
7951 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
7952 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
7953 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
7954 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
7958 /* Form the new inner operation, seeing if it simplifies first. */
7959 tem = gen_binary (code, GET_MODE (x), lhs, rhs);
7961 /* There is one exception to the general way of distributing:
7962 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
7963 if (code == XOR && inner_code == IOR)
7966 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
7969 /* We may be able to continuing distributing the result, so call
7970 ourselves recursively on the inner operation before forming the
7971 outer operation, which we return. */
7972 return gen_binary (inner_code, GET_MODE (x),
7973 apply_distributive_law (tem), other);
7976 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7979 Return an equivalent form, if different from X. Otherwise, return X. If
7980 X is zero, we are to always construct the equivalent form. */
7983 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
7984 unsigned HOST_WIDE_INT constop)
7986 unsigned HOST_WIDE_INT nonzero;
7989 /* Simplify VAROP knowing that we will be only looking at some of the
7992 Note by passing in CONSTOP, we guarantee that the bits not set in
7993 CONSTOP are not significant and will never be examined. We must
7994 ensure that is the case by explicitly masking out those bits
7995 before returning. */
7996 varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
7998 /* If VAROP is a CLOBBER, we will fail so return it. */
7999 if (GET_CODE (varop) == CLOBBER)
8002 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
8003 to VAROP and return the new constant. */
8004 if (GET_CODE (varop) == CONST_INT)
8005 return GEN_INT (trunc_int_for_mode (INTVAL (varop) & constop, mode));
8007 /* See what bits may be nonzero in VAROP. Unlike the general case of
8008 a call to nonzero_bits, here we don't care about bits outside
8011 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
8013 /* Turn off all bits in the constant that are known to already be zero.
8014 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8015 which is tested below. */
8019 /* If we don't have any bits left, return zero. */
8023 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8024 a power of two, we can replace this with an ASHIFT. */
8025 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
8026 && (i = exact_log2 (constop)) >= 0)
8027 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
8029 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8030 or XOR, then try to apply the distributive law. This may eliminate
8031 operations if either branch can be simplified because of the AND.
8032 It may also make some cases more complex, but those cases probably
8033 won't match a pattern either with or without this. */
8035 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
8037 gen_lowpart_for_combine
8039 apply_distributive_law
8040 (gen_binary (GET_CODE (varop), GET_MODE (varop),
8041 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
8042 XEXP (varop, 0), constop),
8043 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
8044 XEXP (varop, 1), constop))));
8046 /* If VAROP is PLUS, and the constant is a mask of low bite, distribute
8047 the AND and see if one of the operands simplifies to zero. If so, we
8048 may eliminate it. */
8050 if (GET_CODE (varop) == PLUS
8051 && exact_log2 (constop + 1) >= 0)
8055 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
8056 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
8057 if (o0 == const0_rtx)
8059 if (o1 == const0_rtx)
8063 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
8064 if we already had one (just check for the simplest cases). */
8065 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
8066 && GET_MODE (XEXP (x, 0)) == mode
8067 && SUBREG_REG (XEXP (x, 0)) == varop)
8068 varop = XEXP (x, 0);
8070 varop = gen_lowpart_for_combine (mode, varop);
8072 /* If we can't make the SUBREG, try to return what we were given. */
8073 if (GET_CODE (varop) == CLOBBER)
8074 return x ? x : varop;
8076 /* If we are only masking insignificant bits, return VAROP. */
8077 if (constop == nonzero)
8081 /* Otherwise, return an AND. */
8082 constop = trunc_int_for_mode (constop, mode);
8083 /* See how much, if any, of X we can use. */
8084 if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
8085 x = gen_binary (AND, mode, varop, GEN_INT (constop));
8089 if (GET_CODE (XEXP (x, 1)) != CONST_INT
8090 || (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) != constop)
8091 SUBST (XEXP (x, 1), GEN_INT (constop));
8093 SUBST (XEXP (x, 0), varop);
8100 #define nonzero_bits_with_known(X, MODE) \
8101 cached_nonzero_bits (X, MODE, known_x, known_mode, known_ret)
8103 /* The function cached_nonzero_bits is a wrapper around nonzero_bits1.
8104 It avoids exponential behavior in nonzero_bits1 when X has
8105 identical subexpressions on the first or the second level. */
8107 static unsigned HOST_WIDE_INT
8108 cached_nonzero_bits (rtx x, enum machine_mode mode, rtx known_x,
8109 enum machine_mode known_mode,
8110 unsigned HOST_WIDE_INT known_ret)
8112 if (x == known_x && mode == known_mode)
8115 /* Try to find identical subexpressions. If found call
8116 nonzero_bits1 on X with the subexpressions as KNOWN_X and the
8117 precomputed value for the subexpression as KNOWN_RET. */
8119 if (GET_RTX_CLASS (GET_CODE (x)) == '2'
8120 || GET_RTX_CLASS (GET_CODE (x)) == 'c')
8122 rtx x0 = XEXP (x, 0);
8123 rtx x1 = XEXP (x, 1);
8125 /* Check the first level. */
8127 return nonzero_bits1 (x, mode, x0, mode,
8128 nonzero_bits_with_known (x0, mode));
8130 /* Check the second level. */
8131 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
8132 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
8133 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
8134 return nonzero_bits1 (x, mode, x1, mode,
8135 nonzero_bits_with_known (x1, mode));
8137 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
8138 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
8139 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
8140 return nonzero_bits1 (x, mode, x0, mode,
8141 nonzero_bits_with_known (x0, mode));
8144 return nonzero_bits1 (x, mode, known_x, known_mode, known_ret);
8147 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
8148 We don't let nonzero_bits recur into num_sign_bit_copies, because that
8149 is less useful. We can't allow both, because that results in exponential
8150 run time recursion. There is a nullstone testcase that triggered
8151 this. This macro avoids accidental uses of num_sign_bit_copies. */
8152 #define cached_num_sign_bit_copies()
8154 /* Given an expression, X, compute which bits in X can be nonzero.
8155 We don't care about bits outside of those defined in MODE.
8157 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8158 a shift, AND, or zero_extract, we can do better. */
8160 static unsigned HOST_WIDE_INT
8161 nonzero_bits1 (rtx x, enum machine_mode mode, rtx known_x,
8162 enum machine_mode known_mode,
8163 unsigned HOST_WIDE_INT known_ret)
8165 unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);
8166 unsigned HOST_WIDE_INT inner_nz;
8168 unsigned int mode_width = GET_MODE_BITSIZE (mode);
8171 /* For floating-point values, assume all bits are needed. */
8172 if (FLOAT_MODE_P (GET_MODE (x)) || FLOAT_MODE_P (mode))
8175 /* If X is wider than MODE, use its mode instead. */
8176 if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
8178 mode = GET_MODE (x);
8179 nonzero = GET_MODE_MASK (mode);
8180 mode_width = GET_MODE_BITSIZE (mode);
8183 if (mode_width > HOST_BITS_PER_WIDE_INT)
8184 /* Our only callers in this case look for single bit values. So
8185 just return the mode mask. Those tests will then be false. */
8188 #ifndef WORD_REGISTER_OPERATIONS
8189 /* If MODE is wider than X, but both are a single word for both the host
8190 and target machines, we can compute this from which bits of the
8191 object might be nonzero in its own mode, taking into account the fact
8192 that on many CISC machines, accessing an object in a wider mode
8193 causes the high-order bits to become undefined. So they are
8194 not known to be zero. */
8196 if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode
8197 && GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD
8198 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
8199 && GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (GET_MODE (x)))
8201 nonzero &= nonzero_bits_with_known (x, GET_MODE (x));
8202 nonzero |= GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x));
8207 code = GET_CODE (x);
8211 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8212 /* If pointers extend unsigned and this is a pointer in Pmode, say that
8213 all the bits above ptr_mode are known to be zero. */
8214 if (POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
8216 nonzero &= GET_MODE_MASK (ptr_mode);
8219 /* Include declared information about alignment of pointers. */
8220 /* ??? We don't properly preserve REG_POINTER changes across
8221 pointer-to-integer casts, so we can't trust it except for
8222 things that we know must be pointers. See execute/960116-1.c. */
8223 if ((x == stack_pointer_rtx
8224 || x == frame_pointer_rtx
8225 || x == arg_pointer_rtx)
8226 && REGNO_POINTER_ALIGN (REGNO (x)))
8228 unsigned HOST_WIDE_INT alignment
8229 = REGNO_POINTER_ALIGN (REGNO (x)) / BITS_PER_UNIT;
8231 #ifdef PUSH_ROUNDING
8232 /* If PUSH_ROUNDING is defined, it is possible for the
8233 stack to be momentarily aligned only to that amount,
8234 so we pick the least alignment. */
8235 if (x == stack_pointer_rtx && PUSH_ARGS)
8236 alignment = MIN ((unsigned HOST_WIDE_INT) PUSH_ROUNDING (1),
8240 nonzero &= ~(alignment - 1);
8243 /* If X is a register whose nonzero bits value is current, use it.
8244 Otherwise, if X is a register whose value we can find, use that
8245 value. Otherwise, use the previously-computed global nonzero bits
8246 for this register. */
8248 if (reg_last_set_value[REGNO (x)] != 0
8249 && (reg_last_set_mode[REGNO (x)] == mode
8250 || (GET_MODE_CLASS (reg_last_set_mode[REGNO (x)]) == MODE_INT
8251 && GET_MODE_CLASS (mode) == MODE_INT))
8252 && (reg_last_set_label[REGNO (x)] == label_tick
8253 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8254 && REG_N_SETS (REGNO (x)) == 1
8255 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start,
8257 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
8258 return reg_last_set_nonzero_bits[REGNO (x)] & nonzero;
8260 tem = get_last_value (x);
8264 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8265 /* If X is narrower than MODE and TEM is a non-negative
8266 constant that would appear negative in the mode of X,
8267 sign-extend it for use in reg_nonzero_bits because some
8268 machines (maybe most) will actually do the sign-extension
8269 and this is the conservative approach.
8271 ??? For 2.5, try to tighten up the MD files in this regard
8272 instead of this kludge. */
8274 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width
8275 && GET_CODE (tem) == CONST_INT
8277 && 0 != (INTVAL (tem)
8278 & ((HOST_WIDE_INT) 1
8279 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8280 tem = GEN_INT (INTVAL (tem)
8281 | ((HOST_WIDE_INT) (-1)
8282 << GET_MODE_BITSIZE (GET_MODE (x))));
8284 return nonzero_bits_with_known (tem, mode) & nonzero;
8286 else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)])
8288 unsigned HOST_WIDE_INT mask = reg_nonzero_bits[REGNO (x)];
8290 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width)
8291 /* We don't know anything about the upper bits. */
8292 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
8293 return nonzero & mask;
8299 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8300 /* If X is negative in MODE, sign-extend the value. */
8301 if (INTVAL (x) > 0 && mode_width < BITS_PER_WORD
8302 && 0 != (INTVAL (x) & ((HOST_WIDE_INT) 1 << (mode_width - 1))))
8303 return (INTVAL (x) | ((HOST_WIDE_INT) (-1) << mode_width));
8309 #ifdef LOAD_EXTEND_OP
8310 /* In many, if not most, RISC machines, reading a byte from memory
8311 zeros the rest of the register. Noticing that fact saves a lot
8312 of extra zero-extends. */
8313 if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND)
8314 nonzero &= GET_MODE_MASK (GET_MODE (x));
8319 case UNEQ: case LTGT:
8320 case GT: case GTU: case UNGT:
8321 case LT: case LTU: case UNLT:
8322 case GE: case GEU: case UNGE:
8323 case LE: case LEU: case UNLE:
8324 case UNORDERED: case ORDERED:
8326 /* If this produces an integer result, we know which bits are set.
8327 Code here used to clear bits outside the mode of X, but that is
8330 if (GET_MODE_CLASS (mode) == MODE_INT
8331 && mode_width <= HOST_BITS_PER_WIDE_INT)
8332 nonzero = STORE_FLAG_VALUE;
8337 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8338 and num_sign_bit_copies. */
8339 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
8340 == GET_MODE_BITSIZE (GET_MODE (x)))
8344 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
8345 nonzero |= (GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x)));
8350 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8351 and num_sign_bit_copies. */
8352 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
8353 == GET_MODE_BITSIZE (GET_MODE (x)))
8359 nonzero &= (nonzero_bits_with_known (XEXP (x, 0), mode)
8360 & GET_MODE_MASK (mode));
8364 nonzero &= nonzero_bits_with_known (XEXP (x, 0), mode);
8365 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
8366 nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
8370 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
8371 Otherwise, show all the bits in the outer mode but not the inner
8373 inner_nz = nonzero_bits_with_known (XEXP (x, 0), mode);
8374 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
8376 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
8378 & (((HOST_WIDE_INT) 1
8379 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
8380 inner_nz |= (GET_MODE_MASK (mode)
8381 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
8384 nonzero &= inner_nz;
8388 nonzero &= (nonzero_bits_with_known (XEXP (x, 0), mode)
8389 & nonzero_bits_with_known (XEXP (x, 1), mode));
8393 case UMIN: case UMAX: case SMIN: case SMAX:
8395 unsigned HOST_WIDE_INT nonzero0 =
8396 nonzero_bits_with_known (XEXP (x, 0), mode);
8398 /* Don't call nonzero_bits for the second time if it cannot change
8400 if ((nonzero & nonzero0) != nonzero)
8401 nonzero &= (nonzero0
8402 | nonzero_bits_with_known (XEXP (x, 1), mode));
8406 case PLUS: case MINUS:
8408 case DIV: case UDIV:
8409 case MOD: case UMOD:
8410 /* We can apply the rules of arithmetic to compute the number of
8411 high- and low-order zero bits of these operations. We start by
8412 computing the width (position of the highest-order nonzero bit)
8413 and the number of low-order zero bits for each value. */
8415 unsigned HOST_WIDE_INT nz0 =
8416 nonzero_bits_with_known (XEXP (x, 0), mode);
8417 unsigned HOST_WIDE_INT nz1 =
8418 nonzero_bits_with_known (XEXP (x, 1), mode);
8419 int sign_index = GET_MODE_BITSIZE (GET_MODE (x)) - 1;
8420 int width0 = floor_log2 (nz0) + 1;
8421 int width1 = floor_log2 (nz1) + 1;
8422 int low0 = floor_log2 (nz0 & -nz0);
8423 int low1 = floor_log2 (nz1 & -nz1);
8424 HOST_WIDE_INT op0_maybe_minusp
8425 = (nz0 & ((HOST_WIDE_INT) 1 << sign_index));
8426 HOST_WIDE_INT op1_maybe_minusp
8427 = (nz1 & ((HOST_WIDE_INT) 1 << sign_index));
8428 unsigned int result_width = mode_width;
8434 result_width = MAX (width0, width1) + 1;
8435 result_low = MIN (low0, low1);
8438 result_low = MIN (low0, low1);
8441 result_width = width0 + width1;
8442 result_low = low0 + low1;
8447 if (! op0_maybe_minusp && ! op1_maybe_minusp)
8448 result_width = width0;
8453 result_width = width0;
8458 if (! op0_maybe_minusp && ! op1_maybe_minusp)
8459 result_width = MIN (width0, width1);
8460 result_low = MIN (low0, low1);
8465 result_width = MIN (width0, width1);
8466 result_low = MIN (low0, low1);
8472 if (result_width < mode_width)
8473 nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1;
8476 nonzero &= ~(((HOST_WIDE_INT) 1 << result_low) - 1);
8478 #ifdef POINTERS_EXTEND_UNSIGNED
8479 /* If pointers extend unsigned and this is an addition or subtraction
8480 to a pointer in Pmode, all the bits above ptr_mode are known to be
8482 if (POINTERS_EXTEND_UNSIGNED > 0 && GET_MODE (x) == Pmode
8483 && (code == PLUS || code == MINUS)
8484 && GET_CODE (XEXP (x, 0)) == REG && REG_POINTER (XEXP (x, 0)))
8485 nonzero &= GET_MODE_MASK (ptr_mode);
8491 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8492 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8493 nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1;
8497 /* If this is a SUBREG formed for a promoted variable that has
8498 been zero-extended, we know that at least the high-order bits
8499 are zero, though others might be too. */
8501 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x) > 0)
8502 nonzero = (GET_MODE_MASK (GET_MODE (x))
8503 & nonzero_bits_with_known (SUBREG_REG (x), GET_MODE (x)));
8505 /* If the inner mode is a single word for both the host and target
8506 machines, we can compute this from which bits of the inner
8507 object might be nonzero. */
8508 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
8509 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8510 <= HOST_BITS_PER_WIDE_INT))
8512 nonzero &= nonzero_bits_with_known (SUBREG_REG (x), mode);
8514 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
8515 /* If this is a typical RISC machine, we only have to worry
8516 about the way loads are extended. */
8517 if ((LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
8519 & (((unsigned HOST_WIDE_INT) 1
8520 << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) - 1))))
8522 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) != ZERO_EXTEND)
8523 || GET_CODE (SUBREG_REG (x)) != MEM)
8526 /* On many CISC machines, accessing an object in a wider mode
8527 causes the high-order bits to become undefined. So they are
8528 not known to be zero. */
8529 if (GET_MODE_SIZE (GET_MODE (x))
8530 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8531 nonzero |= (GET_MODE_MASK (GET_MODE (x))
8532 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
8541 /* The nonzero bits are in two classes: any bits within MODE
8542 that aren't in GET_MODE (x) are always significant. The rest of the
8543 nonzero bits are those that are significant in the operand of
8544 the shift when shifted the appropriate number of bits. This
8545 shows that high-order bits are cleared by the right shift and
8546 low-order bits by left shifts. */
8547 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8548 && INTVAL (XEXP (x, 1)) >= 0
8549 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8551 enum machine_mode inner_mode = GET_MODE (x);
8552 unsigned int width = GET_MODE_BITSIZE (inner_mode);
8553 int count = INTVAL (XEXP (x, 1));
8554 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
8555 unsigned HOST_WIDE_INT op_nonzero =
8556 nonzero_bits_with_known (XEXP (x, 0), mode);
8557 unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask;
8558 unsigned HOST_WIDE_INT outer = 0;
8560 if (mode_width > width)
8561 outer = (op_nonzero & nonzero & ~mode_mask);
8563 if (code == LSHIFTRT)
8565 else if (code == ASHIFTRT)
8569 /* If the sign bit may have been nonzero before the shift, we
8570 need to mark all the places it could have been copied to
8571 by the shift as possibly nonzero. */
8572 if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count)))
8573 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count);
8575 else if (code == ASHIFT)
8578 inner = ((inner << (count % width)
8579 | (inner >> (width - (count % width)))) & mode_mask);
8581 nonzero &= (outer | inner);
8587 /* This is at most the number of bits in the mode. */
8588 nonzero = ((HOST_WIDE_INT) 2 << (floor_log2 (mode_width))) - 1;
8592 /* If CLZ has a known value at zero, then the nonzero bits are
8593 that value, plus the number of bits in the mode minus one. */
8594 if (CLZ_DEFINED_VALUE_AT_ZERO (mode, nonzero))
8595 nonzero |= ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width))) - 1;
8601 /* If CTZ has a known value at zero, then the nonzero bits are
8602 that value, plus the number of bits in the mode minus one. */
8603 if (CTZ_DEFINED_VALUE_AT_ZERO (mode, nonzero))
8604 nonzero |= ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width))) - 1;
8614 nonzero &= (nonzero_bits_with_known (XEXP (x, 1), mode)
8615 | nonzero_bits_with_known (XEXP (x, 2), mode));
8625 /* See the macro definition above. */
8626 #undef cached_num_sign_bit_copies
8628 #define num_sign_bit_copies_with_known(X, M) \
8629 cached_num_sign_bit_copies (X, M, known_x, known_mode, known_ret)
8631 /* The function cached_num_sign_bit_copies is a wrapper around
8632 num_sign_bit_copies1. It avoids exponential behavior in
8633 num_sign_bit_copies1 when X has identical subexpressions on the
8634 first or the second level. */
8637 cached_num_sign_bit_copies (rtx x, enum machine_mode mode, rtx known_x,
8638 enum machine_mode known_mode,
8639 unsigned int known_ret)
8641 if (x == known_x && mode == known_mode)
8644 /* Try to find identical subexpressions. If found call
8645 num_sign_bit_copies1 on X with the subexpressions as KNOWN_X and
8646 the precomputed value for the subexpression as KNOWN_RET. */
8648 if (GET_RTX_CLASS (GET_CODE (x)) == '2'
8649 || GET_RTX_CLASS (GET_CODE (x)) == 'c')
8651 rtx x0 = XEXP (x, 0);
8652 rtx x1 = XEXP (x, 1);
8654 /* Check the first level. */
8657 num_sign_bit_copies1 (x, mode, x0, mode,
8658 num_sign_bit_copies_with_known (x0, mode));
8660 /* Check the second level. */
8661 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
8662 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
8663 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
8665 num_sign_bit_copies1 (x, mode, x1, mode,
8666 num_sign_bit_copies_with_known (x1, mode));
8668 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
8669 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
8670 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
8672 num_sign_bit_copies1 (x, mode, x0, mode,
8673 num_sign_bit_copies_with_known (x0, mode));
8676 return num_sign_bit_copies1 (x, mode, known_x, known_mode, known_ret);
8679 /* Return the number of bits at the high-order end of X that are known to
8680 be equal to the sign bit. X will be used in mode MODE; if MODE is
8681 VOIDmode, X will be used in its own mode. The returned value will always
8682 be between 1 and the number of bits in MODE. */
8685 num_sign_bit_copies1 (rtx x, enum machine_mode mode, rtx known_x,
8686 enum machine_mode known_mode,
8687 unsigned int known_ret)
8689 enum rtx_code code = GET_CODE (x);
8690 unsigned int bitwidth;
8691 int num0, num1, result;
8692 unsigned HOST_WIDE_INT nonzero;
8695 /* If we weren't given a mode, use the mode of X. If the mode is still
8696 VOIDmode, we don't know anything. Likewise if one of the modes is
8699 if (mode == VOIDmode)
8700 mode = GET_MODE (x);
8702 if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x)))
8705 bitwidth = GET_MODE_BITSIZE (mode);
8707 /* For a smaller object, just ignore the high bits. */
8708 if (bitwidth < GET_MODE_BITSIZE (GET_MODE (x)))
8710 num0 = num_sign_bit_copies_with_known (x, GET_MODE (x));
8712 num0 - (int) (GET_MODE_BITSIZE (GET_MODE (x)) - bitwidth));
8715 if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_BITSIZE (GET_MODE (x)))
8717 #ifndef WORD_REGISTER_OPERATIONS
8718 /* If this machine does not do all register operations on the entire
8719 register and MODE is wider than the mode of X, we can say nothing
8720 at all about the high-order bits. */
8723 /* Likewise on machines that do, if the mode of the object is smaller
8724 than a word and loads of that size don't sign extend, we can say
8725 nothing about the high order bits. */
8726 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
8727 #ifdef LOAD_EXTEND_OP
8728 && LOAD_EXTEND_OP (GET_MODE (x)) != SIGN_EXTEND
8739 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8740 /* If pointers extend signed and this is a pointer in Pmode, say that
8741 all the bits above ptr_mode are known to be sign bit copies. */
8742 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode && mode == Pmode
8744 return GET_MODE_BITSIZE (Pmode) - GET_MODE_BITSIZE (ptr_mode) + 1;
8747 if (reg_last_set_value[REGNO (x)] != 0
8748 && reg_last_set_mode[REGNO (x)] == mode
8749 && (reg_last_set_label[REGNO (x)] == label_tick
8750 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8751 && REG_N_SETS (REGNO (x)) == 1
8752 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start,
8754 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
8755 return reg_last_set_sign_bit_copies[REGNO (x)];
8757 tem = get_last_value (x);
8759 return num_sign_bit_copies_with_known (tem, mode);
8761 if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0
8762 && GET_MODE_BITSIZE (GET_MODE (x)) == bitwidth)
8763 return reg_sign_bit_copies[REGNO (x)];
8767 #ifdef LOAD_EXTEND_OP
8768 /* Some RISC machines sign-extend all loads of smaller than a word. */
8769 if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND)
8770 return MAX (1, ((int) bitwidth
8771 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1));
8776 /* If the constant is negative, take its 1's complement and remask.
8777 Then see how many zero bits we have. */
8778 nonzero = INTVAL (x) & GET_MODE_MASK (mode);
8779 if (bitwidth <= HOST_BITS_PER_WIDE_INT
8780 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8781 nonzero = (~nonzero) & GET_MODE_MASK (mode);
8783 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
8786 /* If this is a SUBREG for a promoted object that is sign-extended
8787 and we are looking at it in a wider mode, we know that at least the
8788 high-order bits are known to be sign bit copies. */
8790 if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
8792 num0 = num_sign_bit_copies_with_known (SUBREG_REG (x), mode);
8793 return MAX ((int) bitwidth
8794 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1,
8798 /* For a smaller object, just ignore the high bits. */
8799 if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
8801 num0 = num_sign_bit_copies_with_known (SUBREG_REG (x), VOIDmode);
8802 return MAX (1, (num0
8803 - (int) (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8807 #ifdef WORD_REGISTER_OPERATIONS
8808 #ifdef LOAD_EXTEND_OP
8809 /* For paradoxical SUBREGs on machines where all register operations
8810 affect the entire register, just look inside. Note that we are
8811 passing MODE to the recursive call, so the number of sign bit copies
8812 will remain relative to that mode, not the inner mode. */
8814 /* This works only if loads sign extend. Otherwise, if we get a
8815 reload for the inner part, it may be loaded from the stack, and
8816 then we lose all sign bit copies that existed before the store
8819 if ((GET_MODE_SIZE (GET_MODE (x))
8820 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8821 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
8822 && GET_CODE (SUBREG_REG (x)) == MEM)
8823 return num_sign_bit_copies_with_known (SUBREG_REG (x), mode);
8829 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
8830 return MAX (1, (int) bitwidth - INTVAL (XEXP (x, 1)));
8834 return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8835 + num_sign_bit_copies_with_known (XEXP (x, 0), VOIDmode));
8838 /* For a smaller object, just ignore the high bits. */
8839 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), VOIDmode);
8840 return MAX (1, (num0 - (int) (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8844 return num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8846 case ROTATE: case ROTATERT:
8847 /* If we are rotating left by a number of bits less than the number
8848 of sign bit copies, we can just subtract that amount from the
8850 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8851 && INTVAL (XEXP (x, 1)) >= 0
8852 && INTVAL (XEXP (x, 1)) < (int) bitwidth)
8854 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8855 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
8856 : (int) bitwidth - INTVAL (XEXP (x, 1))));
8861 /* In general, this subtracts one sign bit copy. But if the value
8862 is known to be positive, the number of sign bit copies is the
8863 same as that of the input. Finally, if the input has just one bit
8864 that might be nonzero, all the bits are copies of the sign bit. */
8865 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8866 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8867 return num0 > 1 ? num0 - 1 : 1;
8869 nonzero = nonzero_bits (XEXP (x, 0), mode);
8874 && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero))
8879 case IOR: case AND: case XOR:
8880 case SMIN: case SMAX: case UMIN: case UMAX:
8881 /* Logical operations will preserve the number of sign-bit copies.
8882 MIN and MAX operations always return one of the operands. */
8883 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8884 num1 = num_sign_bit_copies_with_known (XEXP (x, 1), mode);
8885 return MIN (num0, num1);
8887 case PLUS: case MINUS:
8888 /* For addition and subtraction, we can have a 1-bit carry. However,
8889 if we are subtracting 1 from a positive number, there will not
8890 be such a carry. Furthermore, if the positive number is known to
8891 be 0 or 1, we know the result is either -1 or 0. */
8893 if (code == PLUS && XEXP (x, 1) == constm1_rtx
8894 && bitwidth <= HOST_BITS_PER_WIDE_INT)
8896 nonzero = nonzero_bits (XEXP (x, 0), mode);
8897 if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0)
8898 return (nonzero == 1 || nonzero == 0 ? bitwidth
8899 : bitwidth - floor_log2 (nonzero) - 1);
8902 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8903 num1 = num_sign_bit_copies_with_known (XEXP (x, 1), mode);
8904 result = MAX (1, MIN (num0, num1) - 1);
8906 #ifdef POINTERS_EXTEND_UNSIGNED
8907 /* If pointers extend signed and this is an addition or subtraction
8908 to a pointer in Pmode, all the bits above ptr_mode are known to be
8910 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
8911 && (code == PLUS || code == MINUS)
8912 && GET_CODE (XEXP (x, 0)) == REG && REG_POINTER (XEXP (x, 0)))
8913 result = MAX ((int) (GET_MODE_BITSIZE (Pmode)
8914 - GET_MODE_BITSIZE (ptr_mode) + 1),
8920 /* The number of bits of the product is the sum of the number of
8921 bits of both terms. However, unless one of the terms if known
8922 to be positive, we must allow for an additional bit since negating
8923 a negative number can remove one sign bit copy. */
8925 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8926 num1 = num_sign_bit_copies_with_known (XEXP (x, 1), mode);
8928 result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
8930 && (bitwidth > HOST_BITS_PER_WIDE_INT
8931 || (((nonzero_bits (XEXP (x, 0), mode)
8932 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8933 && ((nonzero_bits (XEXP (x, 1), mode)
8934 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))))
8937 return MAX (1, result);
8940 /* The result must be <= the first operand. If the first operand
8941 has the high bit set, we know nothing about the number of sign
8943 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8945 else if ((nonzero_bits (XEXP (x, 0), mode)
8946 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8949 return num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8952 /* The result must be <= the second operand. */
8953 return num_sign_bit_copies_with_known (XEXP (x, 1), mode);
8956 /* Similar to unsigned division, except that we have to worry about
8957 the case where the divisor is negative, in which case we have
8959 result = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8961 && (bitwidth > HOST_BITS_PER_WIDE_INT
8962 || (nonzero_bits (XEXP (x, 1), mode)
8963 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8969 result = num_sign_bit_copies_with_known (XEXP (x, 1), mode);
8971 && (bitwidth > HOST_BITS_PER_WIDE_INT
8972 || (nonzero_bits (XEXP (x, 1), mode)
8973 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8979 /* Shifts by a constant add to the number of bits equal to the
8981 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8982 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8983 && INTVAL (XEXP (x, 1)) > 0)
8984 num0 = MIN ((int) bitwidth, num0 + INTVAL (XEXP (x, 1)));
8989 /* Left shifts destroy copies. */
8990 if (GET_CODE (XEXP (x, 1)) != CONST_INT
8991 || INTVAL (XEXP (x, 1)) < 0
8992 || INTVAL (XEXP (x, 1)) >= (int) bitwidth)
8995 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8996 return MAX (1, num0 - INTVAL (XEXP (x, 1)));
8999 num0 = num_sign_bit_copies_with_known (XEXP (x, 1), mode);
9000 num1 = num_sign_bit_copies_with_known (XEXP (x, 2), mode);
9001 return MIN (num0, num1);
9003 case EQ: case NE: case GE: case GT: case LE: case LT:
9004 case UNEQ: case LTGT: case UNGE: case UNGT: case UNLE: case UNLT:
9005 case GEU: case GTU: case LEU: case LTU:
9006 case UNORDERED: case ORDERED:
9007 /* If the constant is negative, take its 1's complement and remask.
9008 Then see how many zero bits we have. */
9009 nonzero = STORE_FLAG_VALUE;
9010 if (bitwidth <= HOST_BITS_PER_WIDE_INT
9011 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
9012 nonzero = (~nonzero) & GET_MODE_MASK (mode);
9014 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
9021 /* If we haven't been able to figure it out by one of the above rules,
9022 see if some of the high-order bits are known to be zero. If so,
9023 count those bits and return one less than that amount. If we can't
9024 safely compute the mask for this mode, always return BITWIDTH. */
9026 if (bitwidth > HOST_BITS_PER_WIDE_INT)
9029 nonzero = nonzero_bits (x, mode);
9030 return (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))
9031 ? 1 : bitwidth - floor_log2 (nonzero) - 1);
9034 /* Return the number of "extended" bits there are in X, when interpreted
9035 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9036 unsigned quantities, this is the number of high-order zero bits.
9037 For signed quantities, this is the number of copies of the sign bit
9038 minus 1. In both case, this function returns the number of "spare"
9039 bits. For example, if two quantities for which this function returns
9040 at least 1 are added, the addition is known not to overflow.
9042 This function will always return 0 unless called during combine, which
9043 implies that it must be called from a define_split. */
9046 extended_count (rtx x, enum machine_mode mode, int unsignedp)
9048 if (nonzero_sign_valid == 0)
9052 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9053 ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
9054 - floor_log2 (nonzero_bits (x, mode)))
9056 : num_sign_bit_copies (x, mode) - 1);
9059 /* This function is called from `simplify_shift_const' to merge two
9060 outer operations. Specifically, we have already found that we need
9061 to perform operation *POP0 with constant *PCONST0 at the outermost
9062 position. We would now like to also perform OP1 with constant CONST1
9063 (with *POP0 being done last).
9065 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9066 the resulting operation. *PCOMP_P is set to 1 if we would need to
9067 complement the innermost operand, otherwise it is unchanged.
9069 MODE is the mode in which the operation will be done. No bits outside
9070 the width of this mode matter. It is assumed that the width of this mode
9071 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9073 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
9074 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9075 result is simply *PCONST0.
9077 If the resulting operation cannot be expressed as one operation, we
9078 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9081 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
9083 enum rtx_code op0 = *pop0;
9084 HOST_WIDE_INT const0 = *pconst0;
9086 const0 &= GET_MODE_MASK (mode);
9087 const1 &= GET_MODE_MASK (mode);
9089 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9093 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
9096 if (op1 == NIL || op0 == SET)
9099 else if (op0 == NIL)
9100 op0 = op1, const0 = const1;
9102 else if (op0 == op1)
9126 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9127 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
9130 /* If the two constants aren't the same, we can't do anything. The
9131 remaining six cases can all be done. */
9132 else if (const0 != const1)
9140 /* (a & b) | b == b */
9142 else /* op1 == XOR */
9143 /* (a ^ b) | b == a | b */
9149 /* (a & b) ^ b == (~a) & b */
9150 op0 = AND, *pcomp_p = 1;
9151 else /* op1 == IOR */
9152 /* (a | b) ^ b == a & ~b */
9153 op0 = AND, const0 = ~const0;
9158 /* (a | b) & b == b */
9160 else /* op1 == XOR */
9161 /* (a ^ b) & b) == (~a) & b */
9168 /* Check for NO-OP cases. */
9169 const0 &= GET_MODE_MASK (mode);
9171 && (op0 == IOR || op0 == XOR || op0 == PLUS))
9173 else if (const0 == 0 && op0 == AND)
9175 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
9179 /* ??? Slightly redundant with the above mask, but not entirely.
9180 Moving this above means we'd have to sign-extend the mode mask
9181 for the final test. */
9182 const0 = trunc_int_for_mode (const0, mode);
9190 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9191 The result of the shift is RESULT_MODE. X, if nonzero, is an expression
9192 that we started with.
9194 The shift is normally computed in the widest mode we find in VAROP, as
9195 long as it isn't a different number of words than RESULT_MODE. Exceptions
9196 are ASHIFTRT and ROTATE, which are always done in their original mode, */
9199 simplify_shift_const (rtx x, enum rtx_code code,
9200 enum machine_mode result_mode, rtx varop,
9203 enum rtx_code orig_code = code;
9206 enum machine_mode mode = result_mode;
9207 enum machine_mode shift_mode, tmode;
9208 unsigned int mode_words
9209 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
9210 /* We form (outer_op (code varop count) (outer_const)). */
9211 enum rtx_code outer_op = NIL;
9212 HOST_WIDE_INT outer_const = 0;
9214 int complement_p = 0;
9217 /* Make sure and truncate the "natural" shift on the way in. We don't
9218 want to do this inside the loop as it makes it more difficult to
9220 #ifdef SHIFT_COUNT_TRUNCATED
9221 if (SHIFT_COUNT_TRUNCATED)
9222 orig_count &= GET_MODE_BITSIZE (mode) - 1;
9225 /* If we were given an invalid count, don't do anything except exactly
9226 what was requested. */
9228 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
9233 return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (orig_count));
9238 /* Unless one of the branches of the `if' in this loop does a `continue',
9239 we will `break' the loop after the `if'. */
9243 /* If we have an operand of (clobber (const_int 0)), just return that
9245 if (GET_CODE (varop) == CLOBBER)
9248 /* If we discovered we had to complement VAROP, leave. Making a NOT
9249 here would cause an infinite loop. */
9253 /* Convert ROTATERT to ROTATE. */
9254 if (code == ROTATERT)
9256 unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
9258 if (VECTOR_MODE_P (result_mode))
9259 count = bitsize / GET_MODE_NUNITS (result_mode) - count;
9261 count = bitsize - count;
9264 /* We need to determine what mode we will do the shift in. If the
9265 shift is a right shift or a ROTATE, we must always do it in the mode
9266 it was originally done in. Otherwise, we can do it in MODE, the
9267 widest mode encountered. */
9269 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9270 ? result_mode : mode);
9272 /* Handle cases where the count is greater than the size of the mode
9273 minus 1. For ASHIFT, use the size minus one as the count (this can
9274 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9275 take the count modulo the size. For other shifts, the result is
9278 Since these shifts are being produced by the compiler by combining
9279 multiple operations, each of which are defined, we know what the
9280 result is supposed to be. */
9282 if (count > (unsigned int) (GET_MODE_BITSIZE (shift_mode) - 1))
9284 if (code == ASHIFTRT)
9285 count = GET_MODE_BITSIZE (shift_mode) - 1;
9286 else if (code == ROTATE || code == ROTATERT)
9287 count %= GET_MODE_BITSIZE (shift_mode);
9290 /* We can't simply return zero because there may be an
9298 /* An arithmetic right shift of a quantity known to be -1 or 0
9300 if (code == ASHIFTRT
9301 && (num_sign_bit_copies (varop, shift_mode)
9302 == GET_MODE_BITSIZE (shift_mode)))
9308 /* If we are doing an arithmetic right shift and discarding all but
9309 the sign bit copies, this is equivalent to doing a shift by the
9310 bitsize minus one. Convert it into that shift because it will often
9311 allow other simplifications. */
9313 if (code == ASHIFTRT
9314 && (count + num_sign_bit_copies (varop, shift_mode)
9315 >= GET_MODE_BITSIZE (shift_mode)))
9316 count = GET_MODE_BITSIZE (shift_mode) - 1;
9318 /* We simplify the tests below and elsewhere by converting
9319 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9320 `make_compound_operation' will convert it to an ASHIFTRT for
9321 those machines (such as VAX) that don't have an LSHIFTRT. */
9322 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9324 && ((nonzero_bits (varop, shift_mode)
9325 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
9329 if (code == LSHIFTRT
9330 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9331 && !(nonzero_bits (varop, shift_mode) >> count))
9334 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9335 && !((nonzero_bits (varop, shift_mode) << count)
9336 & GET_MODE_MASK (shift_mode)))
9339 switch (GET_CODE (varop))
9345 new = expand_compound_operation (varop);
9354 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9355 minus the width of a smaller mode, we can do this with a
9356 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9357 if ((code == ASHIFTRT || code == LSHIFTRT)
9358 && ! mode_dependent_address_p (XEXP (varop, 0))
9359 && ! MEM_VOLATILE_P (varop)
9360 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9361 MODE_INT, 1)) != BLKmode)
9363 new = adjust_address_nv (varop, tmode,
9364 BYTES_BIG_ENDIAN ? 0
9365 : count / BITS_PER_UNIT);
9367 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9368 : ZERO_EXTEND, mode, new);
9375 /* Similar to the case above, except that we can only do this if
9376 the resulting mode is the same as that of the underlying
9377 MEM and adjust the address depending on the *bits* endianness
9378 because of the way that bit-field extract insns are defined. */
9379 if ((code == ASHIFTRT || code == LSHIFTRT)
9380 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9381 MODE_INT, 1)) != BLKmode
9382 && tmode == GET_MODE (XEXP (varop, 0)))
9384 if (BITS_BIG_ENDIAN)
9385 new = XEXP (varop, 0);
9388 new = copy_rtx (XEXP (varop, 0));
9389 SUBST (XEXP (new, 0),
9390 plus_constant (XEXP (new, 0),
9391 count / BITS_PER_UNIT));
9394 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9395 : ZERO_EXTEND, mode, new);
9402 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9403 the same number of words as what we've seen so far. Then store
9404 the widest mode in MODE. */
9405 if (subreg_lowpart_p (varop)
9406 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9407 > GET_MODE_SIZE (GET_MODE (varop)))
9408 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9409 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9412 varop = SUBREG_REG (varop);
9413 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
9414 mode = GET_MODE (varop);
9420 /* Some machines use MULT instead of ASHIFT because MULT
9421 is cheaper. But it is still better on those machines to
9422 merge two shifts into one. */
9423 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9424 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9427 = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
9428 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
9434 /* Similar, for when divides are cheaper. */
9435 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9436 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9439 = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
9440 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
9446 /* If we are extracting just the sign bit of an arithmetic
9447 right shift, that shift is not needed. However, the sign
9448 bit of a wider mode may be different from what would be
9449 interpreted as the sign bit in a narrower mode, so, if
9450 the result is narrower, don't discard the shift. */
9451 if (code == LSHIFTRT
9452 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9453 && (GET_MODE_BITSIZE (result_mode)
9454 >= GET_MODE_BITSIZE (GET_MODE (varop))))
9456 varop = XEXP (varop, 0);
9460 /* ... fall through ... */
9465 /* Here we have two nested shifts. The result is usually the
9466 AND of a new shift with a mask. We compute the result below. */
9467 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9468 && INTVAL (XEXP (varop, 1)) >= 0
9469 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
9470 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9471 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9473 enum rtx_code first_code = GET_CODE (varop);
9474 unsigned int first_count = INTVAL (XEXP (varop, 1));
9475 unsigned HOST_WIDE_INT mask;
9478 /* We have one common special case. We can't do any merging if
9479 the inner code is an ASHIFTRT of a smaller mode. However, if
9480 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9481 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9482 we can convert it to
9483 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9484 This simplifies certain SIGN_EXTEND operations. */
9485 if (code == ASHIFT && first_code == ASHIFTRT
9486 && count == (unsigned int)
9487 (GET_MODE_BITSIZE (result_mode)
9488 - GET_MODE_BITSIZE (GET_MODE (varop))))
9490 /* C3 has the low-order C1 bits zero. */
9492 mask = (GET_MODE_MASK (mode)
9493 & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
9495 varop = simplify_and_const_int (NULL_RTX, result_mode,
9496 XEXP (varop, 0), mask);
9497 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
9499 count = first_count;
9504 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9505 than C1 high-order bits equal to the sign bit, we can convert
9506 this to either an ASHIFT or an ASHIFTRT depending on the
9509 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9511 if (code == ASHIFTRT && first_code == ASHIFT
9512 && GET_MODE (varop) == shift_mode
9513 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
9516 varop = XEXP (varop, 0);
9518 signed_count = count - first_count;
9519 if (signed_count < 0)
9520 count = -signed_count, code = ASHIFT;
9522 count = signed_count;
9527 /* There are some cases we can't do. If CODE is ASHIFTRT,
9528 we can only do this if FIRST_CODE is also ASHIFTRT.
9530 We can't do the case when CODE is ROTATE and FIRST_CODE is
9533 If the mode of this shift is not the mode of the outer shift,
9534 we can't do this if either shift is a right shift or ROTATE.
9536 Finally, we can't do any of these if the mode is too wide
9537 unless the codes are the same.
9539 Handle the case where the shift codes are the same
9542 if (code == first_code)
9544 if (GET_MODE (varop) != result_mode
9545 && (code == ASHIFTRT || code == LSHIFTRT
9549 count += first_count;
9550 varop = XEXP (varop, 0);
9554 if (code == ASHIFTRT
9555 || (code == ROTATE && first_code == ASHIFTRT)
9556 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
9557 || (GET_MODE (varop) != result_mode
9558 && (first_code == ASHIFTRT || first_code == LSHIFTRT
9559 || first_code == ROTATE
9560 || code == ROTATE)))
9563 /* To compute the mask to apply after the shift, shift the
9564 nonzero bits of the inner shift the same way the
9565 outer shift will. */
9567 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
9570 = simplify_binary_operation (code, result_mode, mask_rtx,
9573 /* Give up if we can't compute an outer operation to use. */
9575 || GET_CODE (mask_rtx) != CONST_INT
9576 || ! merge_outer_ops (&outer_op, &outer_const, AND,
9578 result_mode, &complement_p))
9581 /* If the shifts are in the same direction, we add the
9582 counts. Otherwise, we subtract them. */
9583 signed_count = count;
9584 if ((code == ASHIFTRT || code == LSHIFTRT)
9585 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
9586 signed_count += first_count;
9588 signed_count -= first_count;
9590 /* If COUNT is positive, the new shift is usually CODE,
9591 except for the two exceptions below, in which case it is
9592 FIRST_CODE. If the count is negative, FIRST_CODE should
9594 if (signed_count > 0
9595 && ((first_code == ROTATE && code == ASHIFT)
9596 || (first_code == ASHIFTRT && code == LSHIFTRT)))
9597 code = first_code, count = signed_count;
9598 else if (signed_count < 0)
9599 code = first_code, count = -signed_count;
9601 count = signed_count;
9603 varop = XEXP (varop, 0);
9607 /* If we have (A << B << C) for any shift, we can convert this to
9608 (A << C << B). This wins if A is a constant. Only try this if
9609 B is not a constant. */
9611 else if (GET_CODE (varop) == code
9612 && GET_CODE (XEXP (varop, 1)) != CONST_INT
9614 = simplify_binary_operation (code, mode,
9618 varop = gen_rtx_fmt_ee (code, mode, new, XEXP (varop, 1));
9625 /* Make this fit the case below. */
9626 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
9627 GEN_INT (GET_MODE_MASK (mode)));
9633 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9634 with C the size of VAROP - 1 and the shift is logical if
9635 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9636 we have an (le X 0) operation. If we have an arithmetic shift
9637 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9638 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9640 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
9641 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
9642 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9643 && (code == LSHIFTRT || code == ASHIFTRT)
9644 && count == (unsigned int)
9645 (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9646 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9649 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
9652 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9653 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9658 /* If we have (shift (logical)), move the logical to the outside
9659 to allow it to possibly combine with another logical and the
9660 shift to combine with another shift. This also canonicalizes to
9661 what a ZERO_EXTRACT looks like. Also, some machines have
9662 (and (shift)) insns. */
9664 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9665 && (new = simplify_binary_operation (code, result_mode,
9667 GEN_INT (count))) != 0
9668 && GET_CODE (new) == CONST_INT
9669 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
9670 INTVAL (new), result_mode, &complement_p))
9672 varop = XEXP (varop, 0);
9676 /* If we can't do that, try to simplify the shift in each arm of the
9677 logical expression, make a new logical expression, and apply
9678 the inverse distributive law. */
9680 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9681 XEXP (varop, 0), count);
9682 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9683 XEXP (varop, 1), count);
9685 varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs);
9686 varop = apply_distributive_law (varop);
9693 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9694 says that the sign bit can be tested, FOO has mode MODE, C is
9695 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9696 that may be nonzero. */
9697 if (code == LSHIFTRT
9698 && XEXP (varop, 1) == const0_rtx
9699 && GET_MODE (XEXP (varop, 0)) == result_mode
9700 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9701 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9702 && ((STORE_FLAG_VALUE
9703 & ((HOST_WIDE_INT) 1
9704 < (GET_MODE_BITSIZE (result_mode) - 1))))
9705 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9706 && merge_outer_ops (&outer_op, &outer_const, XOR,
9707 (HOST_WIDE_INT) 1, result_mode,
9710 varop = XEXP (varop, 0);
9717 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9718 than the number of bits in the mode is equivalent to A. */
9719 if (code == LSHIFTRT
9720 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9721 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9723 varop = XEXP (varop, 0);
9728 /* NEG commutes with ASHIFT since it is multiplication. Move the
9729 NEG outside to allow shifts to combine. */
9731 && merge_outer_ops (&outer_op, &outer_const, NEG,
9732 (HOST_WIDE_INT) 0, result_mode,
9735 varop = XEXP (varop, 0);
9741 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9742 is one less than the number of bits in the mode is
9743 equivalent to (xor A 1). */
9744 if (code == LSHIFTRT
9745 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9746 && XEXP (varop, 1) == constm1_rtx
9747 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9748 && merge_outer_ops (&outer_op, &outer_const, XOR,
9749 (HOST_WIDE_INT) 1, result_mode,
9753 varop = XEXP (varop, 0);
9757 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9758 that might be nonzero in BAR are those being shifted out and those
9759 bits are known zero in FOO, we can replace the PLUS with FOO.
9760 Similarly in the other operand order. This code occurs when
9761 we are computing the size of a variable-size array. */
9763 if ((code == ASHIFTRT || code == LSHIFTRT)
9764 && count < HOST_BITS_PER_WIDE_INT
9765 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9766 && (nonzero_bits (XEXP (varop, 1), result_mode)
9767 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9769 varop = XEXP (varop, 0);
9772 else if ((code == ASHIFTRT || code == LSHIFTRT)
9773 && count < HOST_BITS_PER_WIDE_INT
9774 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9775 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9777 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9778 & nonzero_bits (XEXP (varop, 1),
9781 varop = XEXP (varop, 1);
9785 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9787 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9788 && (new = simplify_binary_operation (ASHIFT, result_mode,
9790 GEN_INT (count))) != 0
9791 && GET_CODE (new) == CONST_INT
9792 && merge_outer_ops (&outer_op, &outer_const, PLUS,
9793 INTVAL (new), result_mode, &complement_p))
9795 varop = XEXP (varop, 0);
9801 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9802 with C the size of VAROP - 1 and the shift is logical if
9803 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9804 we have a (gt X 0) operation. If the shift is arithmetic with
9805 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9806 we have a (neg (gt X 0)) operation. */
9808 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9809 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9810 && count == (unsigned int)
9811 (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9812 && (code == LSHIFTRT || code == ASHIFTRT)
9813 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9814 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (varop, 0), 1))
9816 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9819 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9822 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9823 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9830 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9831 if the truncate does not affect the value. */
9832 if (code == LSHIFTRT
9833 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9834 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9835 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9836 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9837 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9839 rtx varop_inner = XEXP (varop, 0);
9842 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9843 XEXP (varop_inner, 0),
9845 (count + INTVAL (XEXP (varop_inner, 1))));
9846 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9859 /* We need to determine what mode to do the shift in. If the shift is
9860 a right shift or ROTATE, we must always do it in the mode it was
9861 originally done in. Otherwise, we can do it in MODE, the widest mode
9862 encountered. The code we care about is that of the shift that will
9863 actually be done, not the shift that was originally requested. */
9865 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9866 ? result_mode : mode);
9868 /* We have now finished analyzing the shift. The result should be
9869 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9870 OUTER_OP is non-NIL, it is an operation that needs to be applied
9871 to the result of the shift. OUTER_CONST is the relevant constant,
9872 but we must turn off all bits turned off in the shift.
9874 If we were passed a value for X, see if we can use any pieces of
9875 it. If not, make new rtx. */
9877 if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
9878 && GET_CODE (XEXP (x, 1)) == CONST_INT
9879 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) == count)
9880 const_rtx = XEXP (x, 1);
9882 const_rtx = GEN_INT (count);
9884 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
9885 && GET_MODE (XEXP (x, 0)) == shift_mode
9886 && SUBREG_REG (XEXP (x, 0)) == varop)
9887 varop = XEXP (x, 0);
9888 else if (GET_MODE (varop) != shift_mode)
9889 varop = gen_lowpart_for_combine (shift_mode, varop);
9891 /* If we can't make the SUBREG, try to return what we were given. */
9892 if (GET_CODE (varop) == CLOBBER)
9893 return x ? x : varop;
9895 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
9899 x = gen_rtx_fmt_ee (code, shift_mode, varop, const_rtx);
9901 /* If we have an outer operation and we just made a shift, it is
9902 possible that we could have simplified the shift were it not
9903 for the outer operation. So try to do the simplification
9906 if (outer_op != NIL && GET_CODE (x) == code
9907 && GET_CODE (XEXP (x, 1)) == CONST_INT)
9908 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
9909 INTVAL (XEXP (x, 1)));
9911 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9912 turn off all the bits that the shift would have turned off. */
9913 if (orig_code == LSHIFTRT && result_mode != shift_mode)
9914 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9915 GET_MODE_MASK (result_mode) >> orig_count);
9917 /* Do the remainder of the processing in RESULT_MODE. */
9918 x = gen_lowpart_for_combine (result_mode, x);
9920 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9923 x = simplify_gen_unary (NOT, result_mode, x, result_mode);
9925 if (outer_op != NIL)
9927 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9928 outer_const = trunc_int_for_mode (outer_const, result_mode);
9930 if (outer_op == AND)
9931 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9932 else if (outer_op == SET)
9933 /* This means that we have determined that the result is
9934 equivalent to a constant. This should be rare. */
9935 x = GEN_INT (outer_const);
9936 else if (GET_RTX_CLASS (outer_op) == '1')
9937 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
9939 x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
9945 /* Like recog, but we receive the address of a pointer to a new pattern.
9946 We try to match the rtx that the pointer points to.
9947 If that fails, we may try to modify or replace the pattern,
9948 storing the replacement into the same pointer object.
9950 Modifications include deletion or addition of CLOBBERs.
9952 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9953 the CLOBBERs are placed.
9955 The value is the final insn code from the pattern ultimately matched,
9959 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
9962 int insn_code_number;
9963 int num_clobbers_to_add = 0;
9968 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9969 we use to indicate that something didn't match. If we find such a
9970 thing, force rejection. */
9971 if (GET_CODE (pat) == PARALLEL)
9972 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9973 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9974 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9977 /* *pnewpat does not have to be actual PATTERN (insn), so make a dummy
9978 instruction for pattern recognition. */
9979 dummy_insn = shallow_copy_rtx (insn);
9980 PATTERN (dummy_insn) = pat;
9981 REG_NOTES (dummy_insn) = 0;
9983 insn_code_number = recog (pat, dummy_insn, &num_clobbers_to_add);
9985 /* If it isn't, there is the possibility that we previously had an insn
9986 that clobbered some register as a side effect, but the combined
9987 insn doesn't need to do that. So try once more without the clobbers
9988 unless this represents an ASM insn. */
9990 if (insn_code_number < 0 && ! check_asm_operands (pat)
9991 && GET_CODE (pat) == PARALLEL)
9995 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9996 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9999 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
10003 SUBST_INT (XVECLEN (pat, 0), pos);
10006 pat = XVECEXP (pat, 0, 0);
10008 PATTERN (dummy_insn) = pat;
10009 insn_code_number = recog (pat, dummy_insn, &num_clobbers_to_add);
10012 /* Recognize all noop sets, these will be killed by followup pass. */
10013 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
10014 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
10016 /* If we had any clobbers to add, make a new pattern than contains
10017 them. Then check to make sure that all of them are dead. */
10018 if (num_clobbers_to_add)
10020 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
10021 rtvec_alloc (GET_CODE (pat) == PARALLEL
10022 ? (XVECLEN (pat, 0)
10023 + num_clobbers_to_add)
10024 : num_clobbers_to_add + 1));
10026 if (GET_CODE (pat) == PARALLEL)
10027 for (i = 0; i < XVECLEN (pat, 0); i++)
10028 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
10030 XVECEXP (newpat, 0, 0) = pat;
10032 add_clobbers (newpat, insn_code_number);
10034 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
10035 i < XVECLEN (newpat, 0); i++)
10037 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
10038 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
10040 notes = gen_rtx_EXPR_LIST (REG_UNUSED,
10041 XEXP (XVECEXP (newpat, 0, i), 0), notes);
10049 return insn_code_number;
10052 /* Like gen_lowpart but for use by combine. In combine it is not possible
10053 to create any new pseudoregs. However, it is safe to create
10054 invalid memory addresses, because combine will try to recognize
10055 them and all they will do is make the combine attempt fail.
10057 If for some reason this cannot do its job, an rtx
10058 (clobber (const_int 0)) is returned.
10059 An insn containing that will not be recognized. */
10064 gen_lowpart_for_combine (enum machine_mode mode, rtx x)
10068 if (GET_MODE (x) == mode)
10071 /* Return identity if this is a CONST or symbolic
10074 && (GET_CODE (x) == CONST
10075 || GET_CODE (x) == SYMBOL_REF
10076 || GET_CODE (x) == LABEL_REF))
10079 /* We can only support MODE being wider than a word if X is a
10080 constant integer or has a mode the same size. */
10082 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
10083 && ! ((GET_MODE (x) == VOIDmode
10084 && (GET_CODE (x) == CONST_INT
10085 || GET_CODE (x) == CONST_DOUBLE))
10086 || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
10087 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
10089 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10090 won't know what to do. So we will strip off the SUBREG here and
10091 process normally. */
10092 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
10094 x = SUBREG_REG (x);
10095 if (GET_MODE (x) == mode)
10099 result = gen_lowpart_common (mode, x);
10100 #ifdef CANNOT_CHANGE_MODE_CLASS
10102 && GET_CODE (result) == SUBREG
10103 && GET_CODE (SUBREG_REG (result)) == REG
10104 && REGNO (SUBREG_REG (result)) >= FIRST_PSEUDO_REGISTER)
10105 bitmap_set_bit (&subregs_of_mode, REGNO (SUBREG_REG (result))
10107 + GET_MODE (result));
10113 if (GET_CODE (x) == MEM)
10117 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10119 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
10120 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
10122 /* If we want to refer to something bigger than the original memref,
10123 generate a perverse subreg instead. That will force a reload
10124 of the original memref X. */
10125 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
10126 return gen_rtx_SUBREG (mode, x, 0);
10128 if (WORDS_BIG_ENDIAN)
10129 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
10130 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
10132 if (BYTES_BIG_ENDIAN)
10134 /* Adjust the address so that the address-after-the-data is
10136 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
10137 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
10140 return adjust_address_nv (x, mode, offset);
10143 /* If X is a comparison operator, rewrite it in a new mode. This
10144 probably won't match, but may allow further simplifications. */
10145 else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
10146 return gen_rtx_fmt_ee (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
10148 /* If we couldn't simplify X any other way, just enclose it in a
10149 SUBREG. Normally, this SUBREG won't match, but some patterns may
10150 include an explicit SUBREG or we may simplify it further in combine. */
10155 enum machine_mode sub_mode = GET_MODE (x);
10157 offset = subreg_lowpart_offset (mode, sub_mode);
10158 if (sub_mode == VOIDmode)
10160 sub_mode = int_mode_for_mode (mode);
10161 x = gen_lowpart_common (sub_mode, x);
10163 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
10165 res = simplify_gen_subreg (mode, x, sub_mode, offset);
10168 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
10172 /* These routines make binary and unary operations by first seeing if they
10173 fold; if not, a new expression is allocated. */
10176 gen_binary (enum rtx_code code, enum machine_mode mode, rtx op0, rtx op1)
10181 if (GET_CODE (op0) == CLOBBER)
10183 else if (GET_CODE (op1) == CLOBBER)
10186 if (GET_RTX_CLASS (code) == 'c'
10187 && swap_commutative_operands_p (op0, op1))
10188 tem = op0, op0 = op1, op1 = tem;
10190 if (GET_RTX_CLASS (code) == '<')
10192 enum machine_mode op_mode = GET_MODE (op0);
10194 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
10195 just (REL_OP X Y). */
10196 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
10198 op1 = XEXP (op0, 1);
10199 op0 = XEXP (op0, 0);
10200 op_mode = GET_MODE (op0);
10203 if (op_mode == VOIDmode)
10204 op_mode = GET_MODE (op1);
10205 result = simplify_relational_operation (code, op_mode, op0, op1);
10208 result = simplify_binary_operation (code, mode, op0, op1);
10213 /* Put complex operands first and constants second. */
10214 if (GET_RTX_CLASS (code) == 'c'
10215 && swap_commutative_operands_p (op0, op1))
10216 return gen_rtx_fmt_ee (code, mode, op1, op0);
10218 /* If we are turning off bits already known off in OP0, we need not do
10220 else if (code == AND && GET_CODE (op1) == CONST_INT
10221 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
10222 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
10225 return gen_rtx_fmt_ee (code, mode, op0, op1);
10228 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10229 comparison code that will be tested.
10231 The result is a possibly different comparison code to use. *POP0 and
10232 *POP1 may be updated.
10234 It is possible that we might detect that a comparison is either always
10235 true or always false. However, we do not perform general constant
10236 folding in combine, so this knowledge isn't useful. Such tautologies
10237 should have been detected earlier. Hence we ignore all such cases. */
10239 static enum rtx_code
10240 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
10246 enum machine_mode mode, tmode;
10248 /* Try a few ways of applying the same transformation to both operands. */
10251 #ifndef WORD_REGISTER_OPERATIONS
10252 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10253 so check specially. */
10254 if (code != GTU && code != GEU && code != LTU && code != LEU
10255 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
10256 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10257 && GET_CODE (XEXP (op1, 0)) == ASHIFT
10258 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
10259 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
10260 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
10261 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
10262 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10263 && XEXP (op0, 1) == XEXP (op1, 1)
10264 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10265 && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
10266 && (INTVAL (XEXP (op0, 1))
10267 == (GET_MODE_BITSIZE (GET_MODE (op0))
10268 - (GET_MODE_BITSIZE
10269 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
10271 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
10272 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
10276 /* If both operands are the same constant shift, see if we can ignore the
10277 shift. We can if the shift is a rotate or if the bits shifted out of
10278 this shift are known to be zero for both inputs and if the type of
10279 comparison is compatible with the shift. */
10280 if (GET_CODE (op0) == GET_CODE (op1)
10281 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10282 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
10283 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
10284 && (code != GT && code != LT && code != GE && code != LE))
10285 || (GET_CODE (op0) == ASHIFTRT
10286 && (code != GTU && code != LTU
10287 && code != GEU && code != LEU)))
10288 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10289 && INTVAL (XEXP (op0, 1)) >= 0
10290 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10291 && XEXP (op0, 1) == XEXP (op1, 1))
10293 enum machine_mode mode = GET_MODE (op0);
10294 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10295 int shift_count = INTVAL (XEXP (op0, 1));
10297 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
10298 mask &= (mask >> shift_count) << shift_count;
10299 else if (GET_CODE (op0) == ASHIFT)
10300 mask = (mask & (mask << shift_count)) >> shift_count;
10302 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
10303 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
10304 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
10309 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10310 SUBREGs are of the same mode, and, in both cases, the AND would
10311 be redundant if the comparison was done in the narrower mode,
10312 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10313 and the operand's possibly nonzero bits are 0xffffff01; in that case
10314 if we only care about QImode, we don't need the AND). This case
10315 occurs if the output mode of an scc insn is not SImode and
10316 STORE_FLAG_VALUE == 1 (e.g., the 386).
10318 Similarly, check for a case where the AND's are ZERO_EXTEND
10319 operations from some narrower mode even though a SUBREG is not
10322 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
10323 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10324 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
10326 rtx inner_op0 = XEXP (op0, 0);
10327 rtx inner_op1 = XEXP (op1, 0);
10328 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
10329 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
10332 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
10333 && (GET_MODE_SIZE (GET_MODE (inner_op0))
10334 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
10335 && (GET_MODE (SUBREG_REG (inner_op0))
10336 == GET_MODE (SUBREG_REG (inner_op1)))
10337 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
10338 <= HOST_BITS_PER_WIDE_INT)
10339 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
10340 GET_MODE (SUBREG_REG (inner_op0)))))
10341 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
10342 GET_MODE (SUBREG_REG (inner_op1))))))
10344 op0 = SUBREG_REG (inner_op0);
10345 op1 = SUBREG_REG (inner_op1);
10347 /* The resulting comparison is always unsigned since we masked
10348 off the original sign bit. */
10349 code = unsigned_condition (code);
10355 for (tmode = GET_CLASS_NARROWEST_MODE
10356 (GET_MODE_CLASS (GET_MODE (op0)));
10357 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
10358 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
10360 op0 = gen_lowpart_for_combine (tmode, inner_op0);
10361 op1 = gen_lowpart_for_combine (tmode, inner_op1);
10362 code = unsigned_condition (code);
10371 /* If both operands are NOT, we can strip off the outer operation
10372 and adjust the comparison code for swapped operands; similarly for
10373 NEG, except that this must be an equality comparison. */
10374 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
10375 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
10376 && (code == EQ || code == NE)))
10377 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
10383 /* If the first operand is a constant, swap the operands and adjust the
10384 comparison code appropriately, but don't do this if the second operand
10385 is already a constant integer. */
10386 if (swap_commutative_operands_p (op0, op1))
10388 tem = op0, op0 = op1, op1 = tem;
10389 code = swap_condition (code);
10392 /* We now enter a loop during which we will try to simplify the comparison.
10393 For the most part, we only are concerned with comparisons with zero,
10394 but some things may really be comparisons with zero but not start
10395 out looking that way. */
10397 while (GET_CODE (op1) == CONST_INT)
10399 enum machine_mode mode = GET_MODE (op0);
10400 unsigned int mode_width = GET_MODE_BITSIZE (mode);
10401 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10402 int equality_comparison_p;
10403 int sign_bit_comparison_p;
10404 int unsigned_comparison_p;
10405 HOST_WIDE_INT const_op;
10407 /* We only want to handle integral modes. This catches VOIDmode,
10408 CCmode, and the floating-point modes. An exception is that we
10409 can handle VOIDmode if OP0 is a COMPARE or a comparison
10412 if (GET_MODE_CLASS (mode) != MODE_INT
10413 && ! (mode == VOIDmode
10414 && (GET_CODE (op0) == COMPARE
10415 || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
10418 /* Get the constant we are comparing against and turn off all bits
10419 not on in our mode. */
10420 const_op = INTVAL (op1);
10421 if (mode != VOIDmode)
10422 const_op = trunc_int_for_mode (const_op, mode);
10423 op1 = GEN_INT (const_op);
10425 /* If we are comparing against a constant power of two and the value
10426 being compared can only have that single bit nonzero (e.g., it was
10427 `and'ed with that bit), we can replace this with a comparison
10430 && (code == EQ || code == NE || code == GE || code == GEU
10431 || code == LT || code == LTU)
10432 && mode_width <= HOST_BITS_PER_WIDE_INT
10433 && exact_log2 (const_op) >= 0
10434 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
10436 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10437 op1 = const0_rtx, const_op = 0;
10440 /* Similarly, if we are comparing a value known to be either -1 or
10441 0 with -1, change it to the opposite comparison against zero. */
10444 && (code == EQ || code == NE || code == GT || code == LE
10445 || code == GEU || code == LTU)
10446 && num_sign_bit_copies (op0, mode) == mode_width)
10448 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10449 op1 = const0_rtx, const_op = 0;
10452 /* Do some canonicalizations based on the comparison code. We prefer
10453 comparisons against zero and then prefer equality comparisons.
10454 If we can reduce the size of a constant, we will do that too. */
10459 /* < C is equivalent to <= (C - 1) */
10463 op1 = GEN_INT (const_op);
10465 /* ... fall through to LE case below. */
10471 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10475 op1 = GEN_INT (const_op);
10479 /* If we are doing a <= 0 comparison on a value known to have
10480 a zero sign bit, we can replace this with == 0. */
10481 else if (const_op == 0
10482 && mode_width <= HOST_BITS_PER_WIDE_INT
10483 && (nonzero_bits (op0, mode)
10484 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10489 /* >= C is equivalent to > (C - 1). */
10493 op1 = GEN_INT (const_op);
10495 /* ... fall through to GT below. */
10501 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10505 op1 = GEN_INT (const_op);
10509 /* If we are doing a > 0 comparison on a value known to have
10510 a zero sign bit, we can replace this with != 0. */
10511 else if (const_op == 0
10512 && mode_width <= HOST_BITS_PER_WIDE_INT
10513 && (nonzero_bits (op0, mode)
10514 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10519 /* < C is equivalent to <= (C - 1). */
10523 op1 = GEN_INT (const_op);
10525 /* ... fall through ... */
10528 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10529 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10530 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10532 const_op = 0, op1 = const0_rtx;
10540 /* unsigned <= 0 is equivalent to == 0 */
10544 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10545 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10546 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10548 const_op = 0, op1 = const0_rtx;
10554 /* >= C is equivalent to < (C - 1). */
10558 op1 = GEN_INT (const_op);
10560 /* ... fall through ... */
10563 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10564 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10565 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10567 const_op = 0, op1 = const0_rtx;
10575 /* unsigned > 0 is equivalent to != 0 */
10579 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10580 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10581 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10583 const_op = 0, op1 = const0_rtx;
10592 /* Compute some predicates to simplify code below. */
10594 equality_comparison_p = (code == EQ || code == NE);
10595 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
10596 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
10599 /* If this is a sign bit comparison and we can do arithmetic in
10600 MODE, say that we will only be needing the sign bit of OP0. */
10601 if (sign_bit_comparison_p
10602 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10603 op0 = force_to_mode (op0, mode,
10605 << (GET_MODE_BITSIZE (mode) - 1)),
10608 /* Now try cases based on the opcode of OP0. If none of the cases
10609 does a "continue", we exit this loop immediately after the
10612 switch (GET_CODE (op0))
10615 /* If we are extracting a single bit from a variable position in
10616 a constant that has only a single bit set and are comparing it
10617 with zero, we can convert this into an equality comparison
10618 between the position and the location of the single bit. */
10620 if (GET_CODE (XEXP (op0, 0)) == CONST_INT
10621 && XEXP (op0, 1) == const1_rtx
10622 && equality_comparison_p && const_op == 0
10623 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
10625 if (BITS_BIG_ENDIAN)
10627 enum machine_mode new_mode
10628 = mode_for_extraction (EP_extzv, 1);
10629 if (new_mode == MAX_MACHINE_MODE)
10630 i = BITS_PER_WORD - 1 - i;
10634 i = (GET_MODE_BITSIZE (mode) - 1 - i);
10638 op0 = XEXP (op0, 2);
10642 /* Result is nonzero iff shift count is equal to I. */
10643 code = reverse_condition (code);
10647 /* ... fall through ... */
10650 tem = expand_compound_operation (op0);
10659 /* If testing for equality, we can take the NOT of the constant. */
10660 if (equality_comparison_p
10661 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
10663 op0 = XEXP (op0, 0);
10668 /* If just looking at the sign bit, reverse the sense of the
10670 if (sign_bit_comparison_p)
10672 op0 = XEXP (op0, 0);
10673 code = (code == GE ? LT : GE);
10679 /* If testing for equality, we can take the NEG of the constant. */
10680 if (equality_comparison_p
10681 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
10683 op0 = XEXP (op0, 0);
10688 /* The remaining cases only apply to comparisons with zero. */
10692 /* When X is ABS or is known positive,
10693 (neg X) is < 0 if and only if X != 0. */
10695 if (sign_bit_comparison_p
10696 && (GET_CODE (XEXP (op0, 0)) == ABS
10697 || (mode_width <= HOST_BITS_PER_WIDE_INT
10698 && (nonzero_bits (XEXP (op0, 0), mode)
10699 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
10701 op0 = XEXP (op0, 0);
10702 code = (code == LT ? NE : EQ);
10706 /* If we have NEG of something whose two high-order bits are the
10707 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10708 if (num_sign_bit_copies (op0, mode) >= 2)
10710 op0 = XEXP (op0, 0);
10711 code = swap_condition (code);
10717 /* If we are testing equality and our count is a constant, we
10718 can perform the inverse operation on our RHS. */
10719 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10720 && (tem = simplify_binary_operation (ROTATERT, mode,
10721 op1, XEXP (op0, 1))) != 0)
10723 op0 = XEXP (op0, 0);
10728 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10729 a particular bit. Convert it to an AND of a constant of that
10730 bit. This will be converted into a ZERO_EXTRACT. */
10731 if (const_op == 0 && sign_bit_comparison_p
10732 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10733 && mode_width <= HOST_BITS_PER_WIDE_INT)
10735 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10738 - INTVAL (XEXP (op0, 1)))));
10739 code = (code == LT ? NE : EQ);
10743 /* Fall through. */
10746 /* ABS is ignorable inside an equality comparison with zero. */
10747 if (const_op == 0 && equality_comparison_p)
10749 op0 = XEXP (op0, 0);
10755 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10756 to (compare FOO CONST) if CONST fits in FOO's mode and we
10757 are either testing inequality or have an unsigned comparison
10758 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10759 if (! unsigned_comparison_p
10760 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10761 <= HOST_BITS_PER_WIDE_INT)
10762 && ((unsigned HOST_WIDE_INT) const_op
10763 < (((unsigned HOST_WIDE_INT) 1
10764 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
10766 op0 = XEXP (op0, 0);
10772 /* Check for the case where we are comparing A - C1 with C2,
10773 both constants are smaller than 1/2 the maximum positive
10774 value in MODE, and the comparison is equality or unsigned.
10775 In that case, if A is either zero-extended to MODE or has
10776 sufficient sign bits so that the high-order bit in MODE
10777 is a copy of the sign in the inner mode, we can prove that it is
10778 safe to do the operation in the wider mode. This simplifies
10779 many range checks. */
10781 if (mode_width <= HOST_BITS_PER_WIDE_INT
10782 && subreg_lowpart_p (op0)
10783 && GET_CODE (SUBREG_REG (op0)) == PLUS
10784 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
10785 && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
10786 && (-INTVAL (XEXP (SUBREG_REG (op0), 1))
10787 < (HOST_WIDE_INT) (GET_MODE_MASK (mode) / 2))
10788 && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2
10789 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0),
10790 GET_MODE (SUBREG_REG (op0)))
10791 & ~GET_MODE_MASK (mode))
10792 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
10793 GET_MODE (SUBREG_REG (op0)))
10795 (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10796 - GET_MODE_BITSIZE (mode)))))
10798 op0 = SUBREG_REG (op0);
10802 /* If the inner mode is narrower and we are extracting the low part,
10803 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10804 if (subreg_lowpart_p (op0)
10805 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10806 /* Fall through */ ;
10810 /* ... fall through ... */
10813 if ((unsigned_comparison_p || equality_comparison_p)
10814 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10815 <= HOST_BITS_PER_WIDE_INT)
10816 && ((unsigned HOST_WIDE_INT) const_op
10817 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
10819 op0 = XEXP (op0, 0);
10825 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10826 this for equality comparisons due to pathological cases involving
10828 if (equality_comparison_p
10829 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10830 op1, XEXP (op0, 1))))
10832 op0 = XEXP (op0, 0);
10837 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10838 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10839 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10841 op0 = XEXP (XEXP (op0, 0), 0);
10842 code = (code == LT ? EQ : NE);
10848 /* We used to optimize signed comparisons against zero, but that
10849 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10850 arrive here as equality comparisons, or (GEU, LTU) are
10851 optimized away. No need to special-case them. */
10853 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10854 (eq B (minus A C)), whichever simplifies. We can only do
10855 this for equality comparisons due to pathological cases involving
10857 if (equality_comparison_p
10858 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10859 XEXP (op0, 1), op1)))
10861 op0 = XEXP (op0, 0);
10866 if (equality_comparison_p
10867 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10868 XEXP (op0, 0), op1)))
10870 op0 = XEXP (op0, 1);
10875 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10876 of bits in X minus 1, is one iff X > 0. */
10877 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10878 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10879 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1))
10881 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10883 op0 = XEXP (op0, 1);
10884 code = (code == GE ? LE : GT);
10890 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10891 if C is zero or B is a constant. */
10892 if (equality_comparison_p
10893 && 0 != (tem = simplify_binary_operation (XOR, mode,
10894 XEXP (op0, 1), op1)))
10896 op0 = XEXP (op0, 0);
10903 case UNEQ: case LTGT:
10904 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
10905 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
10906 case UNORDERED: case ORDERED:
10907 /* We can't do anything if OP0 is a condition code value, rather
10908 than an actual data value. */
10910 || CC0_P (XEXP (op0, 0))
10911 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10914 /* Get the two operands being compared. */
10915 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10916 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10918 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10920 /* Check for the cases where we simply want the result of the
10921 earlier test or the opposite of that result. */
10922 if (code == NE || code == EQ
10923 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10924 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10925 && (STORE_FLAG_VALUE
10926 & (((HOST_WIDE_INT) 1
10927 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10928 && (code == LT || code == GE)))
10930 enum rtx_code new_code;
10931 if (code == LT || code == NE)
10932 new_code = GET_CODE (op0);
10934 new_code = combine_reversed_comparison_code (op0);
10936 if (new_code != UNKNOWN)
10947 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10949 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10950 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10951 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10953 op0 = XEXP (op0, 1);
10954 code = (code == GE ? GT : LE);
10960 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10961 will be converted to a ZERO_EXTRACT later. */
10962 if (const_op == 0 && equality_comparison_p
10963 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10964 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10966 op0 = simplify_and_const_int
10967 (op0, mode, gen_rtx_LSHIFTRT (mode,
10969 XEXP (XEXP (op0, 0), 1)),
10970 (HOST_WIDE_INT) 1);
10974 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10975 zero and X is a comparison and C1 and C2 describe only bits set
10976 in STORE_FLAG_VALUE, we can compare with X. */
10977 if (const_op == 0 && equality_comparison_p
10978 && mode_width <= HOST_BITS_PER_WIDE_INT
10979 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10980 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10981 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10982 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10983 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10985 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10986 << INTVAL (XEXP (XEXP (op0, 0), 1)));
10987 if ((~STORE_FLAG_VALUE & mask) == 0
10988 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
10989 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10990 && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
10992 op0 = XEXP (XEXP (op0, 0), 0);
10997 /* If we are doing an equality comparison of an AND of a bit equal
10998 to the sign bit, replace this with a LT or GE comparison of
10999 the underlying value. */
11000 if (equality_comparison_p
11002 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11003 && mode_width <= HOST_BITS_PER_WIDE_INT
11004 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11005 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11007 op0 = XEXP (op0, 0);
11008 code = (code == EQ ? GE : LT);
11012 /* If this AND operation is really a ZERO_EXTEND from a narrower
11013 mode, the constant fits within that mode, and this is either an
11014 equality or unsigned comparison, try to do this comparison in
11015 the narrower mode. */
11016 if ((equality_comparison_p || unsigned_comparison_p)
11017 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11018 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
11019 & GET_MODE_MASK (mode))
11021 && const_op >> i == 0
11022 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
11024 op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
11028 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11029 fits in both M1 and M2 and the SUBREG is either paradoxical
11030 or represents the low part, permute the SUBREG and the AND
11032 if (GET_CODE (XEXP (op0, 0)) == SUBREG)
11034 unsigned HOST_WIDE_INT c1;
11035 tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
11036 /* Require an integral mode, to avoid creating something like
11038 if (SCALAR_INT_MODE_P (tmode)
11039 /* It is unsafe to commute the AND into the SUBREG if the
11040 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11041 not defined. As originally written the upper bits
11042 have a defined value due to the AND operation.
11043 However, if we commute the AND inside the SUBREG then
11044 they no longer have defined values and the meaning of
11045 the code has been changed. */
11047 #ifdef WORD_REGISTER_OPERATIONS
11048 || (mode_width > GET_MODE_BITSIZE (tmode)
11049 && mode_width <= BITS_PER_WORD)
11051 || (mode_width <= GET_MODE_BITSIZE (tmode)
11052 && subreg_lowpart_p (XEXP (op0, 0))))
11053 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11054 && mode_width <= HOST_BITS_PER_WIDE_INT
11055 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
11056 && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
11057 && (c1 & ~GET_MODE_MASK (tmode)) == 0
11059 && c1 != GET_MODE_MASK (tmode))
11061 op0 = gen_binary (AND, tmode,
11062 SUBREG_REG (XEXP (op0, 0)),
11063 gen_int_mode (c1, tmode));
11064 op0 = gen_lowpart_for_combine (mode, op0);
11069 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
11070 if (const_op == 0 && equality_comparison_p
11071 && XEXP (op0, 1) == const1_rtx
11072 && GET_CODE (XEXP (op0, 0)) == NOT)
11074 op0 = simplify_and_const_int
11075 (NULL_RTX, mode, XEXP (XEXP (op0, 0), 0), (HOST_WIDE_INT) 1);
11076 code = (code == NE ? EQ : NE);
11080 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11081 (eq (and (lshiftrt X) 1) 0). */
11082 if (const_op == 0 && equality_comparison_p
11083 && XEXP (op0, 1) == const1_rtx
11084 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
11085 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == NOT)
11087 op0 = simplify_and_const_int
11089 gen_rtx_LSHIFTRT (mode, XEXP (XEXP (XEXP (op0, 0), 0), 0),
11090 XEXP (XEXP (op0, 0), 1)),
11091 (HOST_WIDE_INT) 1);
11092 code = (code == NE ? EQ : NE);
11098 /* If we have (compare (ashift FOO N) (const_int C)) and
11099 the high order N bits of FOO (N+1 if an inequality comparison)
11100 are known to be zero, we can do this by comparing FOO with C
11101 shifted right N bits so long as the low-order N bits of C are
11103 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
11104 && INTVAL (XEXP (op0, 1)) >= 0
11105 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
11106 < HOST_BITS_PER_WIDE_INT)
11108 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
11109 && mode_width <= HOST_BITS_PER_WIDE_INT
11110 && (nonzero_bits (XEXP (op0, 0), mode)
11111 & ~(mask >> (INTVAL (XEXP (op0, 1))
11112 + ! equality_comparison_p))) == 0)
11114 /* We must perform a logical shift, not an arithmetic one,
11115 as we want the top N bits of C to be zero. */
11116 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
11118 temp >>= INTVAL (XEXP (op0, 1));
11119 op1 = gen_int_mode (temp, mode);
11120 op0 = XEXP (op0, 0);
11124 /* If we are doing a sign bit comparison, it means we are testing
11125 a particular bit. Convert it to the appropriate AND. */
11126 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
11127 && mode_width <= HOST_BITS_PER_WIDE_INT)
11129 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11132 - INTVAL (XEXP (op0, 1)))));
11133 code = (code == LT ? NE : EQ);
11137 /* If this an equality comparison with zero and we are shifting
11138 the low bit to the sign bit, we can convert this to an AND of the
11140 if (const_op == 0 && equality_comparison_p
11141 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11142 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
11145 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11146 (HOST_WIDE_INT) 1);
11152 /* If this is an equality comparison with zero, we can do this
11153 as a logical shift, which might be much simpler. */
11154 if (equality_comparison_p && const_op == 0
11155 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
11157 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
11159 INTVAL (XEXP (op0, 1)));
11163 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11164 do the comparison in a narrower mode. */
11165 if (! unsigned_comparison_p
11166 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11167 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11168 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
11169 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11170 MODE_INT, 1)) != BLKmode
11171 && (((unsigned HOST_WIDE_INT) const_op
11172 + (GET_MODE_MASK (tmode) >> 1) + 1)
11173 <= GET_MODE_MASK (tmode)))
11175 op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
11179 /* Likewise if OP0 is a PLUS of a sign extension with a
11180 constant, which is usually represented with the PLUS
11181 between the shifts. */
11182 if (! unsigned_comparison_p
11183 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11184 && GET_CODE (XEXP (op0, 0)) == PLUS
11185 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
11186 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
11187 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
11188 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11189 MODE_INT, 1)) != BLKmode
11190 && (((unsigned HOST_WIDE_INT) const_op
11191 + (GET_MODE_MASK (tmode) >> 1) + 1)
11192 <= GET_MODE_MASK (tmode)))
11194 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
11195 rtx add_const = XEXP (XEXP (op0, 0), 1);
11196 rtx new_const = gen_binary (ASHIFTRT, GET_MODE (op0), add_const,
11199 op0 = gen_binary (PLUS, tmode,
11200 gen_lowpart_for_combine (tmode, inner),
11205 /* ... fall through ... */
11207 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11208 the low order N bits of FOO are known to be zero, we can do this
11209 by comparing FOO with C shifted left N bits so long as no
11210 overflow occurs. */
11211 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
11212 && INTVAL (XEXP (op0, 1)) >= 0
11213 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11214 && mode_width <= HOST_BITS_PER_WIDE_INT
11215 && (nonzero_bits (XEXP (op0, 0), mode)
11216 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
11217 && (((unsigned HOST_WIDE_INT) const_op
11218 + (GET_CODE (op0) != LSHIFTRT
11219 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
11222 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
11224 /* If the shift was logical, then we must make the condition
11226 if (GET_CODE (op0) == LSHIFTRT)
11227 code = unsigned_condition (code);
11229 const_op <<= INTVAL (XEXP (op0, 1));
11230 op1 = GEN_INT (const_op);
11231 op0 = XEXP (op0, 0);
11235 /* If we are using this shift to extract just the sign bit, we
11236 can replace this with an LT or GE comparison. */
11238 && (equality_comparison_p || sign_bit_comparison_p)
11239 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11240 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
11243 op0 = XEXP (op0, 0);
11244 code = (code == NE || code == GT ? LT : GE);
11256 /* Now make any compound operations involved in this comparison. Then,
11257 check for an outmost SUBREG on OP0 that is not doing anything or is
11258 paradoxical. The latter transformation must only be performed when
11259 it is known that the "extra" bits will be the same in op0 and op1 or
11260 that they don't matter. There are three cases to consider:
11262 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11263 care bits and we can assume they have any convenient value. So
11264 making the transformation is safe.
11266 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11267 In this case the upper bits of op0 are undefined. We should not make
11268 the simplification in that case as we do not know the contents of
11271 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11272 NIL. In that case we know those bits are zeros or ones. We must
11273 also be sure that they are the same as the upper bits of op1.
11275 We can never remove a SUBREG for a non-equality comparison because
11276 the sign bit is in a different place in the underlying object. */
11278 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
11279 op1 = make_compound_operation (op1, SET);
11281 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
11282 /* Case 3 above, to sometimes allow (subreg (mem x)), isn't
11284 && GET_CODE (SUBREG_REG (op0)) == REG
11285 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11286 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
11287 && (code == NE || code == EQ))
11289 if (GET_MODE_SIZE (GET_MODE (op0))
11290 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
11292 op0 = SUBREG_REG (op0);
11293 op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
11295 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
11296 <= HOST_BITS_PER_WIDE_INT)
11297 && (nonzero_bits (SUBREG_REG (op0),
11298 GET_MODE (SUBREG_REG (op0)))
11299 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11301 tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)), op1);
11303 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
11304 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11305 op0 = SUBREG_REG (op0), op1 = tem;
11309 /* We now do the opposite procedure: Some machines don't have compare
11310 insns in all modes. If OP0's mode is an integer mode smaller than a
11311 word and we can't do a compare in that mode, see if there is a larger
11312 mode for which we can do the compare. There are a number of cases in
11313 which we can use the wider mode. */
11315 mode = GET_MODE (op0);
11316 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11317 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
11318 && ! have_insn_for (COMPARE, mode))
11319 for (tmode = GET_MODE_WIDER_MODE (mode);
11321 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
11322 tmode = GET_MODE_WIDER_MODE (tmode))
11323 if (have_insn_for (COMPARE, tmode))
11327 /* If the only nonzero bits in OP0 and OP1 are those in the
11328 narrower mode and this is an equality or unsigned comparison,
11329 we can use the wider mode. Similarly for sign-extended
11330 values, in which case it is true for all comparisons. */
11331 zero_extended = ((code == EQ || code == NE
11332 || code == GEU || code == GTU
11333 || code == LEU || code == LTU)
11334 && (nonzero_bits (op0, tmode)
11335 & ~GET_MODE_MASK (mode)) == 0
11336 && ((GET_CODE (op1) == CONST_INT
11337 || (nonzero_bits (op1, tmode)
11338 & ~GET_MODE_MASK (mode)) == 0)));
11341 || ((num_sign_bit_copies (op0, tmode)
11342 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11343 - GET_MODE_BITSIZE (mode)))
11344 && (num_sign_bit_copies (op1, tmode)
11345 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11346 - GET_MODE_BITSIZE (mode)))))
11348 /* If OP0 is an AND and we don't have an AND in MODE either,
11349 make a new AND in the proper mode. */
11350 if (GET_CODE (op0) == AND
11351 && !have_insn_for (AND, mode))
11352 op0 = gen_binary (AND, tmode,
11353 gen_lowpart_for_combine (tmode,
11355 gen_lowpart_for_combine (tmode,
11358 op0 = gen_lowpart_for_combine (tmode, op0);
11359 if (zero_extended && GET_CODE (op1) == CONST_INT)
11360 op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode));
11361 op1 = gen_lowpart_for_combine (tmode, op1);
11365 /* If this is a test for negative, we can make an explicit
11366 test of the sign bit. */
11368 if (op1 == const0_rtx && (code == LT || code == GE)
11369 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11371 op0 = gen_binary (AND, tmode,
11372 gen_lowpart_for_combine (tmode, op0),
11373 GEN_INT ((HOST_WIDE_INT) 1
11374 << (GET_MODE_BITSIZE (mode) - 1)));
11375 code = (code == LT) ? NE : EQ;
11380 #ifdef CANONICALIZE_COMPARISON
11381 /* If this machine only supports a subset of valid comparisons, see if we
11382 can convert an unsupported one into a supported one. */
11383 CANONICALIZE_COMPARISON (code, op0, op1);
11392 /* Like jump.c' reversed_comparison_code, but use combine infrastructure for
11393 searching backward. */
11394 static enum rtx_code
11395 combine_reversed_comparison_code (rtx exp)
11397 enum rtx_code code1 = reversed_comparison_code (exp, NULL);
11400 if (code1 != UNKNOWN
11401 || GET_MODE_CLASS (GET_MODE (XEXP (exp, 0))) != MODE_CC)
11403 /* Otherwise try and find where the condition codes were last set and
11405 x = get_last_value (XEXP (exp, 0));
11406 if (!x || GET_CODE (x) != COMPARE)
11408 return reversed_comparison_code_parts (GET_CODE (exp),
11409 XEXP (x, 0), XEXP (x, 1), NULL);
11412 /* Return comparison with reversed code of EXP and operands OP0 and OP1.
11413 Return NULL_RTX in case we fail to do the reversal. */
11415 reversed_comparison (rtx exp, enum machine_mode mode, rtx op0, rtx op1)
11417 enum rtx_code reversed_code = combine_reversed_comparison_code (exp);
11418 if (reversed_code == UNKNOWN)
11421 return gen_binary (reversed_code, mode, op0, op1);
11424 /* Utility function for following routine. Called when X is part of a value
11425 being stored into reg_last_set_value. Sets reg_last_set_table_tick
11426 for each register mentioned. Similar to mention_regs in cse.c */
11429 update_table_tick (rtx x)
11431 enum rtx_code code = GET_CODE (x);
11432 const char *fmt = GET_RTX_FORMAT (code);
11437 unsigned int regno = REGNO (x);
11438 unsigned int endregno
11439 = regno + (regno < FIRST_PSEUDO_REGISTER
11440 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11443 for (r = regno; r < endregno; r++)
11444 reg_last_set_table_tick[r] = label_tick;
11449 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11450 /* Note that we can't have an "E" in values stored; see
11451 get_last_value_validate. */
11454 /* Check for identical subexpressions. If x contains
11455 identical subexpression we only have to traverse one of
11458 && (GET_RTX_CLASS (code) == '2'
11459 || GET_RTX_CLASS (code) == 'c'))
11461 /* Note that at this point x1 has already been
11463 rtx x0 = XEXP (x, 0);
11464 rtx x1 = XEXP (x, 1);
11466 /* If x0 and x1 are identical then there is no need to
11471 /* If x0 is identical to a subexpression of x1 then while
11472 processing x1, x0 has already been processed. Thus we
11473 are done with x. */
11474 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
11475 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
11476 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11479 /* If x1 is identical to a subexpression of x0 then we
11480 still have to process the rest of x0. */
11481 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
11482 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
11483 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11485 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
11490 update_table_tick (XEXP (x, i));
11494 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11495 are saying that the register is clobbered and we no longer know its
11496 value. If INSN is zero, don't update reg_last_set; this is only permitted
11497 with VALUE also zero and is used to invalidate the register. */
11500 record_value_for_reg (rtx reg, rtx insn, rtx value)
11502 unsigned int regno = REGNO (reg);
11503 unsigned int endregno
11504 = regno + (regno < FIRST_PSEUDO_REGISTER
11505 ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
11508 /* If VALUE contains REG and we have a previous value for REG, substitute
11509 the previous value. */
11510 if (value && insn && reg_overlap_mentioned_p (reg, value))
11514 /* Set things up so get_last_value is allowed to see anything set up to
11516 subst_low_cuid = INSN_CUID (insn);
11517 tem = get_last_value (reg);
11519 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11520 it isn't going to be useful and will take a lot of time to process,
11521 so just use the CLOBBER. */
11525 if ((GET_RTX_CLASS (GET_CODE (tem)) == '2'
11526 || GET_RTX_CLASS (GET_CODE (tem)) == 'c')
11527 && GET_CODE (XEXP (tem, 0)) == CLOBBER
11528 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
11529 tem = XEXP (tem, 0);
11531 value = replace_rtx (copy_rtx (value), reg, tem);
11535 /* For each register modified, show we don't know its value, that
11536 we don't know about its bitwise content, that its value has been
11537 updated, and that we don't know the location of the death of the
11539 for (i = regno; i < endregno; i++)
11542 reg_last_set[i] = insn;
11544 reg_last_set_value[i] = 0;
11545 reg_last_set_mode[i] = 0;
11546 reg_last_set_nonzero_bits[i] = 0;
11547 reg_last_set_sign_bit_copies[i] = 0;
11548 reg_last_death[i] = 0;
11551 /* Mark registers that are being referenced in this value. */
11553 update_table_tick (value);
11555 /* Now update the status of each register being set.
11556 If someone is using this register in this block, set this register
11557 to invalid since we will get confused between the two lives in this
11558 basic block. This makes using this register always invalid. In cse, we
11559 scan the table to invalidate all entries using this register, but this
11560 is too much work for us. */
11562 for (i = regno; i < endregno; i++)
11564 reg_last_set_label[i] = label_tick;
11565 if (value && reg_last_set_table_tick[i] == label_tick)
11566 reg_last_set_invalid[i] = 1;
11568 reg_last_set_invalid[i] = 0;
11571 /* The value being assigned might refer to X (like in "x++;"). In that
11572 case, we must replace it with (clobber (const_int 0)) to prevent
11574 if (value && ! get_last_value_validate (&value, insn,
11575 reg_last_set_label[regno], 0))
11577 value = copy_rtx (value);
11578 if (! get_last_value_validate (&value, insn,
11579 reg_last_set_label[regno], 1))
11583 /* For the main register being modified, update the value, the mode, the
11584 nonzero bits, and the number of sign bit copies. */
11586 reg_last_set_value[regno] = value;
11590 enum machine_mode mode = GET_MODE (reg);
11591 subst_low_cuid = INSN_CUID (insn);
11592 reg_last_set_mode[regno] = mode;
11593 if (GET_MODE_CLASS (mode) == MODE_INT
11594 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11595 mode = nonzero_bits_mode;
11596 reg_last_set_nonzero_bits[regno] = nonzero_bits (value, mode);
11597 reg_last_set_sign_bit_copies[regno]
11598 = num_sign_bit_copies (value, GET_MODE (reg));
11602 /* Called via note_stores from record_dead_and_set_regs to handle one
11603 SET or CLOBBER in an insn. DATA is the instruction in which the
11604 set is occurring. */
11607 record_dead_and_set_regs_1 (rtx dest, rtx setter, void *data)
11609 rtx record_dead_insn = (rtx) data;
11611 if (GET_CODE (dest) == SUBREG)
11612 dest = SUBREG_REG (dest);
11614 if (GET_CODE (dest) == REG)
11616 /* If we are setting the whole register, we know its value. Otherwise
11617 show that we don't know the value. We can handle SUBREG in
11619 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
11620 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
11621 else if (GET_CODE (setter) == SET
11622 && GET_CODE (SET_DEST (setter)) == SUBREG
11623 && SUBREG_REG (SET_DEST (setter)) == dest
11624 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
11625 && subreg_lowpart_p (SET_DEST (setter)))
11626 record_value_for_reg (dest, record_dead_insn,
11627 gen_lowpart_for_combine (GET_MODE (dest),
11628 SET_SRC (setter)));
11630 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
11632 else if (GET_CODE (dest) == MEM
11633 /* Ignore pushes, they clobber nothing. */
11634 && ! push_operand (dest, GET_MODE (dest)))
11635 mem_last_set = INSN_CUID (record_dead_insn);
11638 /* Update the records of when each REG was most recently set or killed
11639 for the things done by INSN. This is the last thing done in processing
11640 INSN in the combiner loop.
11642 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
11643 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
11644 and also the similar information mem_last_set (which insn most recently
11645 modified memory) and last_call_cuid (which insn was the most recent
11646 subroutine call). */
11649 record_dead_and_set_regs (rtx insn)
11654 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11656 if (REG_NOTE_KIND (link) == REG_DEAD
11657 && GET_CODE (XEXP (link, 0)) == REG)
11659 unsigned int regno = REGNO (XEXP (link, 0));
11660 unsigned int endregno
11661 = regno + (regno < FIRST_PSEUDO_REGISTER
11662 ? HARD_REGNO_NREGS (regno, GET_MODE (XEXP (link, 0)))
11665 for (i = regno; i < endregno; i++)
11666 reg_last_death[i] = insn;
11668 else if (REG_NOTE_KIND (link) == REG_INC)
11669 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11672 if (GET_CODE (insn) == CALL_INSN)
11674 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11675 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
11677 reg_last_set_value[i] = 0;
11678 reg_last_set_mode[i] = 0;
11679 reg_last_set_nonzero_bits[i] = 0;
11680 reg_last_set_sign_bit_copies[i] = 0;
11681 reg_last_death[i] = 0;
11684 last_call_cuid = mem_last_set = INSN_CUID (insn);
11686 /* Don't bother recording what this insn does. It might set the
11687 return value register, but we can't combine into a call
11688 pattern anyway, so there's no point trying (and it may cause
11689 a crash, if e.g. we wind up asking for last_set_value of a
11690 SUBREG of the return value register). */
11694 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11697 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11698 register present in the SUBREG, so for each such SUBREG go back and
11699 adjust nonzero and sign bit information of the registers that are
11700 known to have some zero/sign bits set.
11702 This is needed because when combine blows the SUBREGs away, the
11703 information on zero/sign bits is lost and further combines can be
11704 missed because of that. */
11707 record_promoted_value (rtx insn, rtx subreg)
11710 unsigned int regno = REGNO (SUBREG_REG (subreg));
11711 enum machine_mode mode = GET_MODE (subreg);
11713 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11716 for (links = LOG_LINKS (insn); links;)
11718 insn = XEXP (links, 0);
11719 set = single_set (insn);
11721 if (! set || GET_CODE (SET_DEST (set)) != REG
11722 || REGNO (SET_DEST (set)) != regno
11723 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11725 links = XEXP (links, 1);
11729 if (reg_last_set[regno] == insn)
11731 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
11732 reg_last_set_nonzero_bits[regno] &= GET_MODE_MASK (mode);
11735 if (GET_CODE (SET_SRC (set)) == REG)
11737 regno = REGNO (SET_SRC (set));
11738 links = LOG_LINKS (insn);
11745 /* Scan X for promoted SUBREGs. For each one found,
11746 note what it implies to the registers used in it. */
11749 check_promoted_subreg (rtx insn, rtx x)
11751 if (GET_CODE (x) == SUBREG && SUBREG_PROMOTED_VAR_P (x)
11752 && GET_CODE (SUBREG_REG (x)) == REG)
11753 record_promoted_value (insn, x);
11756 const char *format = GET_RTX_FORMAT (GET_CODE (x));
11759 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11763 check_promoted_subreg (insn, XEXP (x, i));
11767 if (XVEC (x, i) != 0)
11768 for (j = 0; j < XVECLEN (x, i); j++)
11769 check_promoted_subreg (insn, XVECEXP (x, i, j));
11775 /* Utility routine for the following function. Verify that all the registers
11776 mentioned in *LOC are valid when *LOC was part of a value set when
11777 label_tick == TICK. Return 0 if some are not.
11779 If REPLACE is nonzero, replace the invalid reference with
11780 (clobber (const_int 0)) and return 1. This replacement is useful because
11781 we often can get useful information about the form of a value (e.g., if
11782 it was produced by a shift that always produces -1 or 0) even though
11783 we don't know exactly what registers it was produced from. */
11786 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
11789 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11790 int len = GET_RTX_LENGTH (GET_CODE (x));
11793 if (GET_CODE (x) == REG)
11795 unsigned int regno = REGNO (x);
11796 unsigned int endregno
11797 = regno + (regno < FIRST_PSEUDO_REGISTER
11798 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11801 for (j = regno; j < endregno; j++)
11802 if (reg_last_set_invalid[j]
11803 /* If this is a pseudo-register that was only set once and not
11804 live at the beginning of the function, it is always valid. */
11805 || (! (regno >= FIRST_PSEUDO_REGISTER
11806 && REG_N_SETS (regno) == 1
11807 && (! REGNO_REG_SET_P
11808 (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, regno)))
11809 && reg_last_set_label[j] > tick))
11812 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11818 /* If this is a memory reference, make sure that there were
11819 no stores after it that might have clobbered the value. We don't
11820 have alias info, so we assume any store invalidates it. */
11821 else if (GET_CODE (x) == MEM && ! RTX_UNCHANGING_P (x)
11822 && INSN_CUID (insn) <= mem_last_set)
11825 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11829 for (i = 0; i < len; i++)
11833 /* Check for identical subexpressions. If x contains
11834 identical subexpression we only have to traverse one of
11837 && (GET_RTX_CLASS (GET_CODE (x)) == '2'
11838 || GET_RTX_CLASS (GET_CODE (x)) == 'c'))
11840 /* Note that at this point x0 has already been checked
11841 and found valid. */
11842 rtx x0 = XEXP (x, 0);
11843 rtx x1 = XEXP (x, 1);
11845 /* If x0 and x1 are identical then x is also valid. */
11849 /* If x1 is identical to a subexpression of x0 then
11850 while checking x0, x1 has already been checked. Thus
11851 it is valid and so as x. */
11852 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
11853 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
11854 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11857 /* If x0 is identical to a subexpression of x1 then x is
11858 valid iff the rest of x1 is valid. */
11859 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
11860 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
11861 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11863 get_last_value_validate (&XEXP (x1,
11864 x0 == XEXP (x1, 0) ? 1 : 0),
11865 insn, tick, replace);
11868 if (get_last_value_validate (&XEXP (x, i), insn, tick,
11872 /* Don't bother with these. They shouldn't occur anyway. */
11873 else if (fmt[i] == 'E')
11877 /* If we haven't found a reason for it to be invalid, it is valid. */
11881 /* Get the last value assigned to X, if known. Some registers
11882 in the value may be replaced with (clobber (const_int 0)) if their value
11883 is known longer known reliably. */
11886 get_last_value (rtx x)
11888 unsigned int regno;
11891 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11892 then convert it to the desired mode. If this is a paradoxical SUBREG,
11893 we cannot predict what values the "extra" bits might have. */
11894 if (GET_CODE (x) == SUBREG
11895 && subreg_lowpart_p (x)
11896 && (GET_MODE_SIZE (GET_MODE (x))
11897 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11898 && (value = get_last_value (SUBREG_REG (x))) != 0)
11899 return gen_lowpart_for_combine (GET_MODE (x), value);
11901 if (GET_CODE (x) != REG)
11905 value = reg_last_set_value[regno];
11907 /* If we don't have a value, or if it isn't for this basic block and
11908 it's either a hard register, set more than once, or it's a live
11909 at the beginning of the function, return 0.
11911 Because if it's not live at the beginning of the function then the reg
11912 is always set before being used (is never used without being set).
11913 And, if it's set only once, and it's always set before use, then all
11914 uses must have the same last value, even if it's not from this basic
11918 || (reg_last_set_label[regno] != label_tick
11919 && (regno < FIRST_PSEUDO_REGISTER
11920 || REG_N_SETS (regno) != 1
11921 || (REGNO_REG_SET_P
11922 (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, regno)))))
11925 /* If the value was set in a later insn than the ones we are processing,
11926 we can't use it even if the register was only set once. */
11927 if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)
11930 /* If the value has all its registers valid, return it. */
11931 if (get_last_value_validate (&value, reg_last_set[regno],
11932 reg_last_set_label[regno], 0))
11935 /* Otherwise, make a copy and replace any invalid register with
11936 (clobber (const_int 0)). If that fails for some reason, return 0. */
11938 value = copy_rtx (value);
11939 if (get_last_value_validate (&value, reg_last_set[regno],
11940 reg_last_set_label[regno], 1))
11946 /* Return nonzero if expression X refers to a REG or to memory
11947 that is set in an instruction more recent than FROM_CUID. */
11950 use_crosses_set_p (rtx x, int from_cuid)
11954 enum rtx_code code = GET_CODE (x);
11958 unsigned int regno = REGNO (x);
11959 unsigned endreg = regno + (regno < FIRST_PSEUDO_REGISTER
11960 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11962 #ifdef PUSH_ROUNDING
11963 /* Don't allow uses of the stack pointer to be moved,
11964 because we don't know whether the move crosses a push insn. */
11965 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11968 for (; regno < endreg; regno++)
11969 if (reg_last_set[regno]
11970 && INSN_CUID (reg_last_set[regno]) > from_cuid)
11975 if (code == MEM && mem_last_set > from_cuid)
11978 fmt = GET_RTX_FORMAT (code);
11980 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11985 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11986 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
11989 else if (fmt[i] == 'e'
11990 && use_crosses_set_p (XEXP (x, i), from_cuid))
11996 /* Define three variables used for communication between the following
11999 static unsigned int reg_dead_regno, reg_dead_endregno;
12000 static int reg_dead_flag;
12002 /* Function called via note_stores from reg_dead_at_p.
12004 If DEST is within [reg_dead_regno, reg_dead_endregno), set
12005 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
12008 reg_dead_at_p_1 (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
12010 unsigned int regno, endregno;
12012 if (GET_CODE (dest) != REG)
12015 regno = REGNO (dest);
12016 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
12017 ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
12019 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
12020 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
12023 /* Return nonzero if REG is known to be dead at INSN.
12025 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
12026 referencing REG, it is dead. If we hit a SET referencing REG, it is
12027 live. Otherwise, see if it is live or dead at the start of the basic
12028 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
12029 must be assumed to be always live. */
12032 reg_dead_at_p (rtx reg, rtx insn)
12037 /* Set variables for reg_dead_at_p_1. */
12038 reg_dead_regno = REGNO (reg);
12039 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
12040 ? HARD_REGNO_NREGS (reg_dead_regno,
12046 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
12047 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
12049 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12050 if (TEST_HARD_REG_BIT (newpat_used_regs, i))
12054 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
12055 beginning of function. */
12056 for (; insn && GET_CODE (insn) != CODE_LABEL && GET_CODE (insn) != BARRIER;
12057 insn = prev_nonnote_insn (insn))
12059 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
12061 return reg_dead_flag == 1 ? 1 : 0;
12063 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
12067 /* Get the basic block that we were in. */
12069 block = ENTRY_BLOCK_PTR->next_bb;
12072 FOR_EACH_BB (block)
12073 if (insn == block->head)
12076 if (block == EXIT_BLOCK_PTR)
12080 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12081 if (REGNO_REG_SET_P (block->global_live_at_start, i))
12087 /* Note hard registers in X that are used. This code is similar to
12088 that in flow.c, but much simpler since we don't care about pseudos. */
12091 mark_used_regs_combine (rtx x)
12093 RTX_CODE code = GET_CODE (x);
12094 unsigned int regno;
12107 case ADDR_DIFF_VEC:
12110 /* CC0 must die in the insn after it is set, so we don't need to take
12111 special note of it here. */
12117 /* If we are clobbering a MEM, mark any hard registers inside the
12118 address as used. */
12119 if (GET_CODE (XEXP (x, 0)) == MEM)
12120 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
12125 /* A hard reg in a wide mode may really be multiple registers.
12126 If so, mark all of them just like the first. */
12127 if (regno < FIRST_PSEUDO_REGISTER)
12129 unsigned int endregno, r;
12131 /* None of this applies to the stack, frame or arg pointers. */
12132 if (regno == STACK_POINTER_REGNUM
12133 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
12134 || regno == HARD_FRAME_POINTER_REGNUM
12136 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12137 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
12139 || regno == FRAME_POINTER_REGNUM)
12142 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
12143 for (r = regno; r < endregno; r++)
12144 SET_HARD_REG_BIT (newpat_used_regs, r);
12150 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12152 rtx testreg = SET_DEST (x);
12154 while (GET_CODE (testreg) == SUBREG
12155 || GET_CODE (testreg) == ZERO_EXTRACT
12156 || GET_CODE (testreg) == SIGN_EXTRACT
12157 || GET_CODE (testreg) == STRICT_LOW_PART)
12158 testreg = XEXP (testreg, 0);
12160 if (GET_CODE (testreg) == MEM)
12161 mark_used_regs_combine (XEXP (testreg, 0));
12163 mark_used_regs_combine (SET_SRC (x));
12171 /* Recursively scan the operands of this expression. */
12174 const char *fmt = GET_RTX_FORMAT (code);
12176 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12179 mark_used_regs_combine (XEXP (x, i));
12180 else if (fmt[i] == 'E')
12184 for (j = 0; j < XVECLEN (x, i); j++)
12185 mark_used_regs_combine (XVECEXP (x, i, j));
12191 /* Remove register number REGNO from the dead registers list of INSN.
12193 Return the note used to record the death, if there was one. */
12196 remove_death (unsigned int regno, rtx insn)
12198 rtx note = find_regno_note (insn, REG_DEAD, regno);
12202 REG_N_DEATHS (regno)--;
12203 remove_note (insn, note);
12209 /* For each register (hardware or pseudo) used within expression X, if its
12210 death is in an instruction with cuid between FROM_CUID (inclusive) and
12211 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12212 list headed by PNOTES.
12214 That said, don't move registers killed by maybe_kill_insn.
12216 This is done when X is being merged by combination into TO_INSN. These
12217 notes will then be distributed as needed. */
12220 move_deaths (rtx x, rtx maybe_kill_insn, int from_cuid, rtx to_insn,
12225 enum rtx_code code = GET_CODE (x);
12229 unsigned int regno = REGNO (x);
12230 rtx where_dead = reg_last_death[regno];
12231 rtx before_dead, after_dead;
12233 /* Don't move the register if it gets killed in between from and to. */
12234 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
12235 && ! reg_referenced_p (x, maybe_kill_insn))
12238 /* WHERE_DEAD could be a USE insn made by combine, so first we
12239 make sure that we have insns with valid INSN_CUID values. */
12240 before_dead = where_dead;
12241 while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
12242 before_dead = PREV_INSN (before_dead);
12244 after_dead = where_dead;
12245 while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
12246 after_dead = NEXT_INSN (after_dead);
12248 if (before_dead && after_dead
12249 && INSN_CUID (before_dead) >= from_cuid
12250 && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
12251 || (where_dead != after_dead
12252 && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
12254 rtx note = remove_death (regno, where_dead);
12256 /* It is possible for the call above to return 0. This can occur
12257 when reg_last_death points to I2 or I1 that we combined with.
12258 In that case make a new note.
12260 We must also check for the case where X is a hard register
12261 and NOTE is a death note for a range of hard registers
12262 including X. In that case, we must put REG_DEAD notes for
12263 the remaining registers in place of NOTE. */
12265 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
12266 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12267 > GET_MODE_SIZE (GET_MODE (x))))
12269 unsigned int deadregno = REGNO (XEXP (note, 0));
12270 unsigned int deadend
12271 = (deadregno + HARD_REGNO_NREGS (deadregno,
12272 GET_MODE (XEXP (note, 0))));
12273 unsigned int ourend
12274 = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
12277 for (i = deadregno; i < deadend; i++)
12278 if (i < regno || i >= ourend)
12279 REG_NOTES (where_dead)
12280 = gen_rtx_EXPR_LIST (REG_DEAD,
12282 REG_NOTES (where_dead));
12285 /* If we didn't find any note, or if we found a REG_DEAD note that
12286 covers only part of the given reg, and we have a multi-reg hard
12287 register, then to be safe we must check for REG_DEAD notes
12288 for each register other than the first. They could have
12289 their own REG_DEAD notes lying around. */
12290 else if ((note == 0
12292 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12293 < GET_MODE_SIZE (GET_MODE (x)))))
12294 && regno < FIRST_PSEUDO_REGISTER
12295 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
12297 unsigned int ourend
12298 = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
12299 unsigned int i, offset;
12303 offset = HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0)));
12307 for (i = regno + offset; i < ourend; i++)
12308 move_deaths (regno_reg_rtx[i],
12309 maybe_kill_insn, from_cuid, to_insn, &oldnotes);
12312 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
12314 XEXP (note, 1) = *pnotes;
12318 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
12320 REG_N_DEATHS (regno)++;
12326 else if (GET_CODE (x) == SET)
12328 rtx dest = SET_DEST (x);
12330 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
12332 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12333 that accesses one word of a multi-word item, some
12334 piece of everything register in the expression is used by
12335 this insn, so remove any old death. */
12336 /* ??? So why do we test for equality of the sizes? */
12338 if (GET_CODE (dest) == ZERO_EXTRACT
12339 || GET_CODE (dest) == STRICT_LOW_PART
12340 || (GET_CODE (dest) == SUBREG
12341 && (((GET_MODE_SIZE (GET_MODE (dest))
12342 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
12343 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
12344 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
12346 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
12350 /* If this is some other SUBREG, we know it replaces the entire
12351 value, so use that as the destination. */
12352 if (GET_CODE (dest) == SUBREG)
12353 dest = SUBREG_REG (dest);
12355 /* If this is a MEM, adjust deaths of anything used in the address.
12356 For a REG (the only other possibility), the entire value is
12357 being replaced so the old value is not used in this insn. */
12359 if (GET_CODE (dest) == MEM)
12360 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
12365 else if (GET_CODE (x) == CLOBBER)
12368 len = GET_RTX_LENGTH (code);
12369 fmt = GET_RTX_FORMAT (code);
12371 for (i = 0; i < len; i++)
12376 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12377 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
12380 else if (fmt[i] == 'e')
12381 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
12385 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12386 pattern of an insn. X must be a REG. */
12389 reg_bitfield_target_p (rtx x, rtx body)
12393 if (GET_CODE (body) == SET)
12395 rtx dest = SET_DEST (body);
12397 unsigned int regno, tregno, endregno, endtregno;
12399 if (GET_CODE (dest) == ZERO_EXTRACT)
12400 target = XEXP (dest, 0);
12401 else if (GET_CODE (dest) == STRICT_LOW_PART)
12402 target = SUBREG_REG (XEXP (dest, 0));
12406 if (GET_CODE (target) == SUBREG)
12407 target = SUBREG_REG (target);
12409 if (GET_CODE (target) != REG)
12412 tregno = REGNO (target), regno = REGNO (x);
12413 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
12414 return target == x;
12416 endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target));
12417 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
12419 return endregno > tregno && regno < endtregno;
12422 else if (GET_CODE (body) == PARALLEL)
12423 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
12424 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
12430 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12431 as appropriate. I3 and I2 are the insns resulting from the combination
12432 insns including FROM (I2 may be zero).
12434 Each note in the list is either ignored or placed on some insns, depending
12435 on the type of note. */
12438 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2)
12440 rtx note, next_note;
12443 for (note = notes; note; note = next_note)
12445 rtx place = 0, place2 = 0;
12447 /* If this NOTE references a pseudo register, ensure it references
12448 the latest copy of that register. */
12449 if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
12450 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
12451 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
12453 next_note = XEXP (note, 1);
12454 switch (REG_NOTE_KIND (note))
12458 /* Doesn't matter much where we put this, as long as it's somewhere.
12459 It is preferable to keep these notes on branches, which is most
12460 likely to be i3. */
12464 case REG_VTABLE_REF:
12465 /* ??? Should remain with *a particular* memory load. Given the
12466 nature of vtable data, the last insn seems relatively safe. */
12470 case REG_NON_LOCAL_GOTO:
12471 if (GET_CODE (i3) == JUMP_INSN)
12473 else if (i2 && GET_CODE (i2) == JUMP_INSN)
12479 case REG_EH_REGION:
12480 /* These notes must remain with the call or trapping instruction. */
12481 if (GET_CODE (i3) == CALL_INSN)
12483 else if (i2 && GET_CODE (i2) == CALL_INSN)
12485 else if (flag_non_call_exceptions)
12487 if (may_trap_p (i3))
12489 else if (i2 && may_trap_p (i2))
12491 /* ??? Otherwise assume we've combined things such that we
12492 can now prove that the instructions can't trap. Drop the
12493 note in this case. */
12501 /* These notes must remain with the call. It should not be
12502 possible for both I2 and I3 to be a call. */
12503 if (GET_CODE (i3) == CALL_INSN)
12505 else if (i2 && GET_CODE (i2) == CALL_INSN)
12512 /* Any clobbers for i3 may still exist, and so we must process
12513 REG_UNUSED notes from that insn.
12515 Any clobbers from i2 or i1 can only exist if they were added by
12516 recog_for_combine. In that case, recog_for_combine created the
12517 necessary REG_UNUSED notes. Trying to keep any original
12518 REG_UNUSED notes from these insns can cause incorrect output
12519 if it is for the same register as the original i3 dest.
12520 In that case, we will notice that the register is set in i3,
12521 and then add a REG_UNUSED note for the destination of i3, which
12522 is wrong. However, it is possible to have REG_UNUSED notes from
12523 i2 or i1 for register which were both used and clobbered, so
12524 we keep notes from i2 or i1 if they will turn into REG_DEAD
12527 /* If this register is set or clobbered in I3, put the note there
12528 unless there is one already. */
12529 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
12531 if (from_insn != i3)
12534 if (! (GET_CODE (XEXP (note, 0)) == REG
12535 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
12536 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
12539 /* Otherwise, if this register is used by I3, then this register
12540 now dies here, so we must put a REG_DEAD note here unless there
12542 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
12543 && ! (GET_CODE (XEXP (note, 0)) == REG
12544 ? find_regno_note (i3, REG_DEAD,
12545 REGNO (XEXP (note, 0)))
12546 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
12548 PUT_REG_NOTE_KIND (note, REG_DEAD);
12556 /* These notes say something about results of an insn. We can
12557 only support them if they used to be on I3 in which case they
12558 remain on I3. Otherwise they are ignored.
12560 If the note refers to an expression that is not a constant, we
12561 must also ignore the note since we cannot tell whether the
12562 equivalence is still true. It might be possible to do
12563 slightly better than this (we only have a problem if I2DEST
12564 or I1DEST is present in the expression), but it doesn't
12565 seem worth the trouble. */
12567 if (from_insn == i3
12568 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
12573 case REG_NO_CONFLICT:
12574 /* These notes say something about how a register is used. They must
12575 be present on any use of the register in I2 or I3. */
12576 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
12579 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
12589 /* This can show up in several ways -- either directly in the
12590 pattern, or hidden off in the constant pool with (or without?)
12591 a REG_EQUAL note. */
12592 /* ??? Ignore the without-reg_equal-note problem for now. */
12593 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
12594 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
12595 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12596 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
12600 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
12601 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
12602 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12603 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12611 /* Don't attach REG_LABEL note to a JUMP_INSN which has
12612 JUMP_LABEL already. Instead, decrement LABEL_NUSES. */
12613 if (place && GET_CODE (place) == JUMP_INSN && JUMP_LABEL (place))
12615 if (JUMP_LABEL (place) != XEXP (note, 0))
12617 if (GET_CODE (JUMP_LABEL (place)) == CODE_LABEL)
12618 LABEL_NUSES (JUMP_LABEL (place))--;
12621 if (place2 && GET_CODE (place2) == JUMP_INSN && JUMP_LABEL (place2))
12623 if (JUMP_LABEL (place2) != XEXP (note, 0))
12625 if (GET_CODE (JUMP_LABEL (place2)) == CODE_LABEL)
12626 LABEL_NUSES (JUMP_LABEL (place2))--;
12632 /* This note says something about the value of a register prior
12633 to the execution of an insn. It is too much trouble to see
12634 if the note is still correct in all situations. It is better
12635 to simply delete it. */
12639 /* If the insn previously containing this note still exists,
12640 put it back where it was. Otherwise move it to the previous
12641 insn. Adjust the corresponding REG_LIBCALL note. */
12642 if (GET_CODE (from_insn) != NOTE)
12646 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
12647 place = prev_real_insn (from_insn);
12649 XEXP (tem, 0) = place;
12650 /* If we're deleting the last remaining instruction of a
12651 libcall sequence, don't add the notes. */
12652 else if (XEXP (note, 0) == from_insn)
12658 /* This is handled similarly to REG_RETVAL. */
12659 if (GET_CODE (from_insn) != NOTE)
12663 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
12664 place = next_real_insn (from_insn);
12666 XEXP (tem, 0) = place;
12667 /* If we're deleting the last remaining instruction of a
12668 libcall sequence, don't add the notes. */
12669 else if (XEXP (note, 0) == from_insn)
12675 /* If the register is used as an input in I3, it dies there.
12676 Similarly for I2, if it is nonzero and adjacent to I3.
12678 If the register is not used as an input in either I3 or I2
12679 and it is not one of the registers we were supposed to eliminate,
12680 there are two possibilities. We might have a non-adjacent I2
12681 or we might have somehow eliminated an additional register
12682 from a computation. For example, we might have had A & B where
12683 we discover that B will always be zero. In this case we will
12684 eliminate the reference to A.
12686 In both cases, we must search to see if we can find a previous
12687 use of A and put the death note there. */
12690 && GET_CODE (from_insn) == CALL_INSN
12691 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12693 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12695 else if (i2 != 0 && next_nonnote_insn (i2) == i3
12696 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12701 basic_block bb = this_basic_block;
12703 for (tem = PREV_INSN (i3); place == 0; tem = PREV_INSN (tem))
12705 if (! INSN_P (tem))
12707 if (tem == bb->head)
12712 /* If the register is being set at TEM, see if that is all
12713 TEM is doing. If so, delete TEM. Otherwise, make this
12714 into a REG_UNUSED note instead. */
12715 if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
12717 rtx set = single_set (tem);
12718 rtx inner_dest = 0;
12720 rtx cc0_setter = NULL_RTX;
12724 for (inner_dest = SET_DEST (set);
12725 (GET_CODE (inner_dest) == STRICT_LOW_PART
12726 || GET_CODE (inner_dest) == SUBREG
12727 || GET_CODE (inner_dest) == ZERO_EXTRACT);
12728 inner_dest = XEXP (inner_dest, 0))
12731 /* Verify that it was the set, and not a clobber that
12732 modified the register.
12734 CC0 targets must be careful to maintain setter/user
12735 pairs. If we cannot delete the setter due to side
12736 effects, mark the user with an UNUSED note instead
12739 if (set != 0 && ! side_effects_p (SET_SRC (set))
12740 && rtx_equal_p (XEXP (note, 0), inner_dest)
12742 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12743 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12744 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12748 /* Move the notes and links of TEM elsewhere.
12749 This might delete other dead insns recursively.
12750 First set the pattern to something that won't use
12753 PATTERN (tem) = pc_rtx;
12755 distribute_notes (REG_NOTES (tem), tem, tem,
12757 distribute_links (LOG_LINKS (tem));
12759 PUT_CODE (tem, NOTE);
12760 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
12761 NOTE_SOURCE_FILE (tem) = 0;
12764 /* Delete the setter too. */
12767 PATTERN (cc0_setter) = pc_rtx;
12769 distribute_notes (REG_NOTES (cc0_setter),
12770 cc0_setter, cc0_setter,
12772 distribute_links (LOG_LINKS (cc0_setter));
12774 PUT_CODE (cc0_setter, NOTE);
12775 NOTE_LINE_NUMBER (cc0_setter)
12776 = NOTE_INSN_DELETED;
12777 NOTE_SOURCE_FILE (cc0_setter) = 0;
12781 /* If the register is both set and used here, put the
12782 REG_DEAD note here, but place a REG_UNUSED note
12783 here too unless there already is one. */
12784 else if (reg_referenced_p (XEXP (note, 0),
12789 if (! find_regno_note (tem, REG_UNUSED,
12790 REGNO (XEXP (note, 0))))
12792 = gen_rtx_EXPR_LIST (REG_UNUSED, XEXP (note, 0),
12797 PUT_REG_NOTE_KIND (note, REG_UNUSED);
12799 /* If there isn't already a REG_UNUSED note, put one
12801 if (! find_regno_note (tem, REG_UNUSED,
12802 REGNO (XEXP (note, 0))))
12807 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12808 || (GET_CODE (tem) == CALL_INSN
12809 && find_reg_fusage (tem, USE, XEXP (note, 0))))
12813 /* If we are doing a 3->2 combination, and we have a
12814 register which formerly died in i3 and was not used
12815 by i2, which now no longer dies in i3 and is used in
12816 i2 but does not die in i2, and place is between i2
12817 and i3, then we may need to move a link from place to
12819 if (i2 && INSN_UID (place) <= max_uid_cuid
12820 && INSN_CUID (place) > INSN_CUID (i2)
12822 && INSN_CUID (from_insn) > INSN_CUID (i2)
12823 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12825 rtx links = LOG_LINKS (place);
12826 LOG_LINKS (place) = 0;
12827 distribute_links (links);
12832 if (tem == bb->head)
12836 /* We haven't found an insn for the death note and it
12837 is still a REG_DEAD note, but we have hit the beginning
12838 of the block. If the existing life info says the reg
12839 was dead, there's nothing left to do. Otherwise, we'll
12840 need to do a global life update after combine. */
12841 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0
12842 && REGNO_REG_SET_P (bb->global_live_at_start,
12843 REGNO (XEXP (note, 0))))
12844 SET_BIT (refresh_blocks, this_basic_block->index);
12847 /* If the register is set or already dead at PLACE, we needn't do
12848 anything with this note if it is still a REG_DEAD note.
12849 We can here if it is set at all, not if is it totally replace,
12850 which is what `dead_or_set_p' checks, so also check for it being
12853 if (place && REG_NOTE_KIND (note) == REG_DEAD)
12855 unsigned int regno = REGNO (XEXP (note, 0));
12857 /* Similarly, if the instruction on which we want to place
12858 the note is a noop, we'll need do a global live update
12859 after we remove them in delete_noop_moves. */
12860 if (noop_move_p (place))
12861 SET_BIT (refresh_blocks, this_basic_block->index);
12863 if (dead_or_set_p (place, XEXP (note, 0))
12864 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12866 /* Unless the register previously died in PLACE, clear
12867 reg_last_death. [I no longer understand why this is
12869 if (reg_last_death[regno] != place)
12870 reg_last_death[regno] = 0;
12874 reg_last_death[regno] = place;
12876 /* If this is a death note for a hard reg that is occupying
12877 multiple registers, ensure that we are still using all
12878 parts of the object. If we find a piece of the object
12879 that is unused, we must arrange for an appropriate REG_DEAD
12880 note to be added for it. However, we can't just emit a USE
12881 and tag the note to it, since the register might actually
12882 be dead; so we recourse, and the recursive call then finds
12883 the previous insn that used this register. */
12885 if (place && regno < FIRST_PSEUDO_REGISTER
12886 && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
12888 unsigned int endregno
12889 = regno + HARD_REGNO_NREGS (regno,
12890 GET_MODE (XEXP (note, 0)));
12894 for (i = regno; i < endregno; i++)
12895 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12896 && ! find_regno_fusage (place, USE, i))
12897 || dead_or_set_regno_p (place, i))
12902 /* Put only REG_DEAD notes for pieces that are
12903 not already dead or set. */
12905 for (i = regno; i < endregno;
12906 i += HARD_REGNO_NREGS (i, reg_raw_mode[i]))
12908 rtx piece = regno_reg_rtx[i];
12909 basic_block bb = this_basic_block;
12911 if (! dead_or_set_p (place, piece)
12912 && ! reg_bitfield_target_p (piece,
12916 = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX);
12918 distribute_notes (new_note, place, place,
12921 else if (! refers_to_regno_p (i, i + 1,
12922 PATTERN (place), 0)
12923 && ! find_regno_fusage (place, USE, i))
12924 for (tem = PREV_INSN (place); ;
12925 tem = PREV_INSN (tem))
12927 if (! INSN_P (tem))
12929 if (tem == bb->head)
12931 SET_BIT (refresh_blocks,
12932 this_basic_block->index);
12937 if (dead_or_set_p (tem, piece)
12938 || reg_bitfield_target_p (piece,
12942 = gen_rtx_EXPR_LIST (REG_UNUSED, piece,
12957 /* Any other notes should not be present at this point in the
12964 XEXP (note, 1) = REG_NOTES (place);
12965 REG_NOTES (place) = note;
12967 else if ((REG_NOTE_KIND (note) == REG_DEAD
12968 || REG_NOTE_KIND (note) == REG_UNUSED)
12969 && GET_CODE (XEXP (note, 0)) == REG)
12970 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
12974 if ((REG_NOTE_KIND (note) == REG_DEAD
12975 || REG_NOTE_KIND (note) == REG_UNUSED)
12976 && GET_CODE (XEXP (note, 0)) == REG)
12977 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
12979 REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
12980 REG_NOTE_KIND (note),
12982 REG_NOTES (place2));
12987 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12988 I3, I2, and I1 to new locations. This is also called in one case to
12989 add a link pointing at I3 when I3's destination is changed. */
12992 distribute_links (rtx links)
12994 rtx link, next_link;
12996 for (link = links; link; link = next_link)
13002 next_link = XEXP (link, 1);
13004 /* If the insn that this link points to is a NOTE or isn't a single
13005 set, ignore it. In the latter case, it isn't clear what we
13006 can do other than ignore the link, since we can't tell which
13007 register it was for. Such links wouldn't be used by combine
13010 It is not possible for the destination of the target of the link to
13011 have been changed by combine. The only potential of this is if we
13012 replace I3, I2, and I1 by I3 and I2. But in that case the
13013 destination of I2 also remains unchanged. */
13015 if (GET_CODE (XEXP (link, 0)) == NOTE
13016 || (set = single_set (XEXP (link, 0))) == 0)
13019 reg = SET_DEST (set);
13020 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
13021 || GET_CODE (reg) == SIGN_EXTRACT
13022 || GET_CODE (reg) == STRICT_LOW_PART)
13023 reg = XEXP (reg, 0);
13025 /* A LOG_LINK is defined as being placed on the first insn that uses
13026 a register and points to the insn that sets the register. Start
13027 searching at the next insn after the target of the link and stop
13028 when we reach a set of the register or the end of the basic block.
13030 Note that this correctly handles the link that used to point from
13031 I3 to I2. Also note that not much searching is typically done here
13032 since most links don't point very far away. */
13034 for (insn = NEXT_INSN (XEXP (link, 0));
13035 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
13036 || this_basic_block->next_bb->head != insn));
13037 insn = NEXT_INSN (insn))
13038 if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
13040 if (reg_referenced_p (reg, PATTERN (insn)))
13044 else if (GET_CODE (insn) == CALL_INSN
13045 && find_reg_fusage (insn, USE, reg))
13051 /* If we found a place to put the link, place it there unless there
13052 is already a link to the same insn as LINK at that point. */
13058 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
13059 if (XEXP (link2, 0) == XEXP (link, 0))
13064 XEXP (link, 1) = LOG_LINKS (place);
13065 LOG_LINKS (place) = link;
13067 /* Set added_links_insn to the earliest insn we added a
13069 if (added_links_insn == 0
13070 || INSN_CUID (added_links_insn) > INSN_CUID (place))
13071 added_links_insn = place;
13077 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
13080 insn_cuid (rtx insn)
13082 while (insn != 0 && INSN_UID (insn) > max_uid_cuid
13083 && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE)
13084 insn = NEXT_INSN (insn);
13086 if (INSN_UID (insn) > max_uid_cuid)
13089 return INSN_CUID (insn);
13093 dump_combine_stats (FILE *file)
13097 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13098 combine_attempts, combine_merges, combine_extras, combine_successes);
13102 dump_combine_total_stats (FILE *file)
13106 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13107 total_attempts, total_merges, total_extras, total_successes);