1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - reg_n_refs is not adjusted in the rare case when a register is
57 no longer required in a computation
58 - there are extremely rare cases (see distribute_regnotes) when a
60 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
61 removed because there is no way to know which register it was
64 To simplify substitution, we combine only when the earlier insn(s)
65 consist of only a single assignment. To simplify updating afterward,
66 we never combine when a subroutine call appears in the middle.
68 Since we do not represent assignments to CC0 explicitly except when that
69 is all an insn does, there is no LOG_LINKS entry in an insn that uses
70 the condition code for the insn that set the condition code.
71 Fortunately, these two insns must be consecutive.
72 Therefore, every JUMP_INSN is taken to have an implicit logical link
73 to the preceding insn. This is not quite right, since non-jumps can
74 also use the condition code; but in practice such insns would not
83 #include "hard-reg-set.h"
84 #include "basic-block.h"
85 #include "insn-config.h"
87 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
89 #include "insn-attr.h"
94 /* It is not safe to use ordinary gen_lowpart in combine.
95 Use gen_lowpart_for_combine instead. See comments there. */
96 #define gen_lowpart dont_use_gen_lowpart_you_dummy
98 /* Number of attempts to combine instructions in this function. */
100 static int combine_attempts;
102 /* Number of attempts that got as far as substitution in this function. */
104 static int combine_merges;
106 /* Number of instructions combined with added SETs in this function. */
108 static int combine_extras;
110 /* Number of instructions combined in this function. */
112 static int combine_successes;
114 /* Totals over entire compilation. */
116 static int total_attempts, total_merges, total_extras, total_successes;
119 /* Vector mapping INSN_UIDs to cuids.
120 The cuids are like uids but increase monotonically always.
121 Combine always uses cuids so that it can compare them.
122 But actually renumbering the uids, which we used to do,
123 proves to be a bad idea because it makes it hard to compare
124 the dumps produced by earlier passes with those from later passes. */
126 static int *uid_cuid;
127 static int max_uid_cuid;
129 /* Get the cuid of an insn. */
131 #define INSN_CUID(INSN) \
132 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
134 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
135 BITS_PER_WORD would invoke undefined behavior. Work around it. */
137 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
138 (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
140 /* Maximum register number, which is the size of the tables below. */
142 static unsigned int combine_max_regno;
144 /* Record last point of death of (hard or pseudo) register n. */
146 static rtx *reg_last_death;
148 /* Record last point of modification of (hard or pseudo) register n. */
150 static rtx *reg_last_set;
152 /* Record the cuid of the last insn that invalidated memory
153 (anything that writes memory, and subroutine calls, but not pushes). */
155 static int mem_last_set;
157 /* Record the cuid of the last CALL_INSN
158 so we can tell whether a potential combination crosses any calls. */
160 static int last_call_cuid;
162 /* When `subst' is called, this is the insn that is being modified
163 (by combining in a previous insn). The PATTERN of this insn
164 is still the old pattern partially modified and it should not be
165 looked at, but this may be used to examine the successors of the insn
166 to judge whether a simplification is valid. */
168 static rtx subst_insn;
170 /* This is an insn that belongs before subst_insn, but is not currently
171 on the insn chain. */
173 static rtx subst_prev_insn;
175 /* This is the lowest CUID that `subst' is currently dealing with.
176 get_last_value will not return a value if the register was set at or
177 after this CUID. If not for this mechanism, we could get confused if
178 I2 or I1 in try_combine were an insn that used the old value of a register
179 to obtain a new value. In that case, we might erroneously get the
180 new value of the register when we wanted the old one. */
182 static int subst_low_cuid;
184 /* This contains any hard registers that are used in newpat; reg_dead_at_p
185 must consider all these registers to be always live. */
187 static HARD_REG_SET newpat_used_regs;
189 /* This is an insn to which a LOG_LINKS entry has been added. If this
190 insn is the earlier than I2 or I3, combine should rescan starting at
193 static rtx added_links_insn;
195 /* Basic block number of the block in which we are performing combines. */
196 static int this_basic_block;
198 /* A bitmap indicating which blocks had registers go dead at entry.
199 After combine, we'll need to re-do global life analysis with
200 those blocks as starting points. */
201 static sbitmap refresh_blocks;
202 static int need_refresh;
204 /* The next group of arrays allows the recording of the last value assigned
205 to (hard or pseudo) register n. We use this information to see if a
206 operation being processed is redundant given a prior operation performed
207 on the register. For example, an `and' with a constant is redundant if
208 all the zero bits are already known to be turned off.
210 We use an approach similar to that used by cse, but change it in the
213 (1) We do not want to reinitialize at each label.
214 (2) It is useful, but not critical, to know the actual value assigned
215 to a register. Often just its form is helpful.
217 Therefore, we maintain the following arrays:
219 reg_last_set_value the last value assigned
220 reg_last_set_label records the value of label_tick when the
221 register was assigned
222 reg_last_set_table_tick records the value of label_tick when a
223 value using the register is assigned
224 reg_last_set_invalid set to non-zero when it is not valid
225 to use the value of this register in some
228 To understand the usage of these tables, it is important to understand
229 the distinction between the value in reg_last_set_value being valid
230 and the register being validly contained in some other expression in the
233 Entry I in reg_last_set_value is valid if it is non-zero, and either
234 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
236 Register I may validly appear in any expression returned for the value
237 of another register if reg_n_sets[i] is 1. It may also appear in the
238 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
239 reg_last_set_invalid[j] is zero.
241 If an expression is found in the table containing a register which may
242 not validly appear in an expression, the register is replaced by
243 something that won't match, (clobber (const_int 0)).
245 reg_last_set_invalid[i] is set non-zero when register I is being assigned
246 to and reg_last_set_table_tick[i] == label_tick. */
248 /* Record last value assigned to (hard or pseudo) register n. */
250 static rtx *reg_last_set_value;
252 /* Record the value of label_tick when the value for register n is placed in
253 reg_last_set_value[n]. */
255 static int *reg_last_set_label;
257 /* Record the value of label_tick when an expression involving register n
258 is placed in reg_last_set_value. */
260 static int *reg_last_set_table_tick;
262 /* Set non-zero if references to register n in expressions should not be
265 static char *reg_last_set_invalid;
267 /* Incremented for each label. */
269 static int label_tick;
271 /* Some registers that are set more than once and used in more than one
272 basic block are nevertheless always set in similar ways. For example,
273 a QImode register may be loaded from memory in two places on a machine
274 where byte loads zero extend.
276 We record in the following array what we know about the nonzero
277 bits of a register, specifically which bits are known to be zero.
279 If an entry is zero, it means that we don't know anything special. */
281 static unsigned HOST_WIDE_INT *reg_nonzero_bits;
283 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
284 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
286 static enum machine_mode nonzero_bits_mode;
288 /* Nonzero if we know that a register has some leading bits that are always
289 equal to the sign bit. */
291 static unsigned char *reg_sign_bit_copies;
293 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
294 It is zero while computing them and after combine has completed. This
295 former test prevents propagating values based on previously set values,
296 which can be incorrect if a variable is modified in a loop. */
298 static int nonzero_sign_valid;
300 /* These arrays are maintained in parallel with reg_last_set_value
301 and are used to store the mode in which the register was last set,
302 the bits that were known to be zero when it was last set, and the
303 number of sign bits copies it was known to have when it was last set. */
305 static enum machine_mode *reg_last_set_mode;
306 static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits;
307 static char *reg_last_set_sign_bit_copies;
309 /* Record one modification to rtl structure
310 to be undone by storing old_contents into *where.
311 is_int is 1 if the contents are an int. */
317 union {rtx r; unsigned int i;} old_contents;
318 union {rtx *r; unsigned int *i;} where;
321 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
322 num_undo says how many are currently recorded.
324 other_insn is nonzero if we have modified some other insn in the process
325 of working on subst_insn. It must be verified too. */
334 static struct undobuf undobuf;
336 /* Number of times the pseudo being substituted for
337 was found and replaced. */
339 static int n_occurrences;
341 static void do_SUBST PARAMS ((rtx *, rtx));
342 static void do_SUBST_INT PARAMS ((unsigned int *,
344 static void init_reg_last_arrays PARAMS ((void));
345 static void setup_incoming_promotions PARAMS ((void));
346 static void set_nonzero_bits_and_sign_copies PARAMS ((rtx, rtx, void *));
347 static int cant_combine_insn_p PARAMS ((rtx));
348 static int can_combine_p PARAMS ((rtx, rtx, rtx, rtx, rtx *, rtx *));
349 static int sets_function_arg_p PARAMS ((rtx));
350 static int combinable_i3pat PARAMS ((rtx, rtx *, rtx, rtx, int, rtx *));
351 static int contains_muldiv PARAMS ((rtx));
352 static rtx try_combine PARAMS ((rtx, rtx, rtx, int *));
353 static void undo_all PARAMS ((void));
354 static void undo_commit PARAMS ((void));
355 static rtx *find_split_point PARAMS ((rtx *, rtx));
356 static rtx subst PARAMS ((rtx, rtx, rtx, int, int));
357 static rtx combine_simplify_rtx PARAMS ((rtx, enum machine_mode, int, int));
358 static rtx simplify_if_then_else PARAMS ((rtx));
359 static rtx simplify_set PARAMS ((rtx));
360 static rtx simplify_logical PARAMS ((rtx, int));
361 static rtx expand_compound_operation PARAMS ((rtx));
362 static rtx expand_field_assignment PARAMS ((rtx));
363 static rtx make_extraction PARAMS ((enum machine_mode, rtx, HOST_WIDE_INT,
364 rtx, unsigned HOST_WIDE_INT, int,
366 static rtx extract_left_shift PARAMS ((rtx, int));
367 static rtx make_compound_operation PARAMS ((rtx, enum rtx_code));
368 static int get_pos_from_mask PARAMS ((unsigned HOST_WIDE_INT,
369 unsigned HOST_WIDE_INT *));
370 static rtx force_to_mode PARAMS ((rtx, enum machine_mode,
371 unsigned HOST_WIDE_INT, rtx, int));
372 static rtx if_then_else_cond PARAMS ((rtx, rtx *, rtx *));
373 static rtx known_cond PARAMS ((rtx, enum rtx_code, rtx, rtx));
374 static int rtx_equal_for_field_assignment_p PARAMS ((rtx, rtx));
375 static rtx make_field_assignment PARAMS ((rtx));
376 static rtx apply_distributive_law PARAMS ((rtx));
377 static rtx simplify_and_const_int PARAMS ((rtx, enum machine_mode, rtx,
378 unsigned HOST_WIDE_INT));
379 static unsigned HOST_WIDE_INT nonzero_bits PARAMS ((rtx, enum machine_mode));
380 static unsigned int num_sign_bit_copies PARAMS ((rtx, enum machine_mode));
381 static int merge_outer_ops PARAMS ((enum rtx_code *, HOST_WIDE_INT *,
382 enum rtx_code, HOST_WIDE_INT,
383 enum machine_mode, int *));
384 static rtx simplify_shift_const PARAMS ((rtx, enum rtx_code, enum machine_mode,
386 static int recog_for_combine PARAMS ((rtx *, rtx, rtx *));
387 static rtx gen_lowpart_for_combine PARAMS ((enum machine_mode, rtx));
388 static rtx gen_binary PARAMS ((enum rtx_code, enum machine_mode,
390 static enum rtx_code simplify_comparison PARAMS ((enum rtx_code, rtx *, rtx *));
391 static void update_table_tick PARAMS ((rtx));
392 static void record_value_for_reg PARAMS ((rtx, rtx, rtx));
393 static void check_promoted_subreg PARAMS ((rtx, rtx));
394 static void record_dead_and_set_regs_1 PARAMS ((rtx, rtx, void *));
395 static void record_dead_and_set_regs PARAMS ((rtx));
396 static int get_last_value_validate PARAMS ((rtx *, rtx, int, int));
397 static rtx get_last_value PARAMS ((rtx));
398 static int use_crosses_set_p PARAMS ((rtx, int));
399 static void reg_dead_at_p_1 PARAMS ((rtx, rtx, void *));
400 static int reg_dead_at_p PARAMS ((rtx, rtx));
401 static void move_deaths PARAMS ((rtx, rtx, int, rtx, rtx *));
402 static int reg_bitfield_target_p PARAMS ((rtx, rtx));
403 static void distribute_notes PARAMS ((rtx, rtx, rtx, rtx, rtx, rtx));
404 static void distribute_links PARAMS ((rtx));
405 static void mark_used_regs_combine PARAMS ((rtx));
406 static int insn_cuid PARAMS ((rtx));
407 static void record_promoted_value PARAMS ((rtx, rtx));
408 static rtx reversed_comparison PARAMS ((rtx, enum machine_mode, rtx, rtx));
409 static enum rtx_code combine_reversed_comparison_code PARAMS ((rtx));
411 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
412 insn. The substitution can be undone by undo_all. If INTO is already
413 set to NEWVAL, do not record this change. Because computing NEWVAL might
414 also call SUBST, we have to compute it before we put anything into
418 do_SUBST (into, newval)
424 if (oldval == newval)
427 /* We'd like to catch as many invalid transformations here as
428 possible. Unfortunately, there are way too many mode changes
429 that are perfectly valid, so we'd waste too much effort for
430 little gain doing the checks here. Focus on catching invalid
431 transformations involving integer constants. */
432 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
433 && GET_CODE (newval) == CONST_INT)
435 /* Sanity check that we're replacing oldval with a CONST_INT
436 that is a valid sign-extension for the original mode. */
437 if (INTVAL (newval) != trunc_int_for_mode (INTVAL (newval),
441 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
442 CONST_INT is not valid, because after the replacement, the
443 original mode would be gone. Unfortunately, we can't tell
444 when do_SUBST is called to replace the operand thereof, so we
445 perform this test on oldval instead, checking whether an
446 invalid replacement took place before we got here. */
447 if ((GET_CODE (oldval) == SUBREG
448 && GET_CODE (SUBREG_REG (oldval)) == CONST_INT)
449 || (GET_CODE (oldval) == ZERO_EXTEND
450 && GET_CODE (XEXP (oldval, 0)) == CONST_INT))
455 buf = undobuf.frees, undobuf.frees = buf->next;
457 buf = (struct undo *) xmalloc (sizeof (struct undo));
461 buf->old_contents.r = oldval;
464 buf->next = undobuf.undos, undobuf.undos = buf;
467 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
469 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
470 for the value of a HOST_WIDE_INT value (including CONST_INT) is
474 do_SUBST_INT (into, newval)
475 unsigned int *into, newval;
478 unsigned int oldval = *into;
480 if (oldval == newval)
484 buf = undobuf.frees, undobuf.frees = buf->next;
486 buf = (struct undo *) xmalloc (sizeof (struct undo));
490 buf->old_contents.i = oldval;
493 buf->next = undobuf.undos, undobuf.undos = buf;
496 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
498 /* Main entry point for combiner. F is the first insn of the function.
499 NREGS is the first unused pseudo-reg number.
501 Return non-zero if the combiner has turned an indirect jump
502 instruction into a direct jump. */
504 combine_instructions (f, nregs)
513 rtx links, nextlinks;
515 int new_direct_jump_p = 0;
517 combine_attempts = 0;
520 combine_successes = 0;
522 combine_max_regno = nregs;
524 reg_nonzero_bits = ((unsigned HOST_WIDE_INT *)
525 xcalloc (nregs, sizeof (unsigned HOST_WIDE_INT)));
527 = (unsigned char *) xcalloc (nregs, sizeof (unsigned char));
529 reg_last_death = (rtx *) xmalloc (nregs * sizeof (rtx));
530 reg_last_set = (rtx *) xmalloc (nregs * sizeof (rtx));
531 reg_last_set_value = (rtx *) xmalloc (nregs * sizeof (rtx));
532 reg_last_set_table_tick = (int *) xmalloc (nregs * sizeof (int));
533 reg_last_set_label = (int *) xmalloc (nregs * sizeof (int));
534 reg_last_set_invalid = (char *) xmalloc (nregs * sizeof (char));
536 = (enum machine_mode *) xmalloc (nregs * sizeof (enum machine_mode));
537 reg_last_set_nonzero_bits
538 = (unsigned HOST_WIDE_INT *) xmalloc (nregs * sizeof (HOST_WIDE_INT));
539 reg_last_set_sign_bit_copies
540 = (char *) xmalloc (nregs * sizeof (char));
542 init_reg_last_arrays ();
544 init_recog_no_volatile ();
546 /* Compute maximum uid value so uid_cuid can be allocated. */
548 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
549 if (INSN_UID (insn) > i)
552 uid_cuid = (int *) xmalloc ((i + 1) * sizeof (int));
555 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
557 /* Don't use reg_nonzero_bits when computing it. This can cause problems
558 when, for example, we have j <<= 1 in a loop. */
560 nonzero_sign_valid = 0;
562 /* Compute the mapping from uids to cuids.
563 Cuids are numbers assigned to insns, like uids,
564 except that cuids increase monotonically through the code.
566 Scan all SETs and see if we can deduce anything about what
567 bits are known to be zero for some registers and how many copies
568 of the sign bit are known to exist for those registers.
570 Also set any known values so that we can use it while searching
571 for what bits are known to be set. */
575 /* We need to initialize it here, because record_dead_and_set_regs may call
577 subst_prev_insn = NULL_RTX;
579 setup_incoming_promotions ();
581 refresh_blocks = sbitmap_alloc (n_basic_blocks);
582 sbitmap_zero (refresh_blocks);
585 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
587 uid_cuid[INSN_UID (insn)] = ++i;
593 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
595 record_dead_and_set_regs (insn);
598 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
599 if (REG_NOTE_KIND (links) == REG_INC)
600 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
605 if (GET_CODE (insn) == CODE_LABEL)
609 nonzero_sign_valid = 1;
611 /* Now scan all the insns in forward order. */
613 this_basic_block = -1;
617 init_reg_last_arrays ();
618 setup_incoming_promotions ();
620 for (insn = f; insn; insn = next ? next : NEXT_INSN (insn))
624 /* If INSN starts a new basic block, update our basic block number. */
625 if (this_basic_block + 1 < n_basic_blocks
626 && BLOCK_HEAD (this_basic_block + 1) == insn)
629 if (GET_CODE (insn) == CODE_LABEL)
632 else if (INSN_P (insn))
634 /* See if we know about function return values before this
635 insn based upon SUBREG flags. */
636 check_promoted_subreg (insn, PATTERN (insn));
638 /* Try this insn with each insn it links back to. */
640 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
641 if ((next = try_combine (insn, XEXP (links, 0),
642 NULL_RTX, &new_direct_jump_p)) != 0)
645 /* Try each sequence of three linked insns ending with this one. */
647 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
649 rtx link = XEXP (links, 0);
651 /* If the linked insn has been replaced by a note, then there
652 is no point in pursuing this chain any further. */
653 if (GET_CODE (link) == NOTE)
656 for (nextlinks = LOG_LINKS (link);
658 nextlinks = XEXP (nextlinks, 1))
659 if ((next = try_combine (insn, link,
661 &new_direct_jump_p)) != 0)
666 /* Try to combine a jump insn that uses CC0
667 with a preceding insn that sets CC0, and maybe with its
668 logical predecessor as well.
669 This is how we make decrement-and-branch insns.
670 We need this special code because data flow connections
671 via CC0 do not get entered in LOG_LINKS. */
673 if (GET_CODE (insn) == JUMP_INSN
674 && (prev = prev_nonnote_insn (insn)) != 0
675 && GET_CODE (prev) == INSN
676 && sets_cc0_p (PATTERN (prev)))
678 if ((next = try_combine (insn, prev,
679 NULL_RTX, &new_direct_jump_p)) != 0)
682 for (nextlinks = LOG_LINKS (prev); nextlinks;
683 nextlinks = XEXP (nextlinks, 1))
684 if ((next = try_combine (insn, prev,
686 &new_direct_jump_p)) != 0)
690 /* Do the same for an insn that explicitly references CC0. */
691 if (GET_CODE (insn) == INSN
692 && (prev = prev_nonnote_insn (insn)) != 0
693 && GET_CODE (prev) == INSN
694 && sets_cc0_p (PATTERN (prev))
695 && GET_CODE (PATTERN (insn)) == SET
696 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
698 if ((next = try_combine (insn, prev,
699 NULL_RTX, &new_direct_jump_p)) != 0)
702 for (nextlinks = LOG_LINKS (prev); nextlinks;
703 nextlinks = XEXP (nextlinks, 1))
704 if ((next = try_combine (insn, prev,
706 &new_direct_jump_p)) != 0)
710 /* Finally, see if any of the insns that this insn links to
711 explicitly references CC0. If so, try this insn, that insn,
712 and its predecessor if it sets CC0. */
713 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
714 if (GET_CODE (XEXP (links, 0)) == INSN
715 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
716 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
717 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
718 && GET_CODE (prev) == INSN
719 && sets_cc0_p (PATTERN (prev))
720 && (next = try_combine (insn, XEXP (links, 0),
721 prev, &new_direct_jump_p)) != 0)
725 /* Try combining an insn with two different insns whose results it
727 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
728 for (nextlinks = XEXP (links, 1); nextlinks;
729 nextlinks = XEXP (nextlinks, 1))
730 if ((next = try_combine (insn, XEXP (links, 0),
732 &new_direct_jump_p)) != 0)
735 if (GET_CODE (insn) != NOTE)
736 record_dead_and_set_regs (insn);
744 EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks, 0, this_basic_block,
745 BASIC_BLOCK (this_basic_block)->flags |= BB_DIRTY);
746 new_direct_jump_p |= purge_all_dead_edges (0);
747 delete_noop_moves (f);
749 update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES,
750 PROP_DEATH_NOTES | PROP_SCAN_DEAD_CODE
751 | PROP_KILL_DEAD_CODE);
754 sbitmap_free (refresh_blocks);
755 free (reg_nonzero_bits);
756 free (reg_sign_bit_copies);
757 free (reg_last_death);
759 free (reg_last_set_value);
760 free (reg_last_set_table_tick);
761 free (reg_last_set_label);
762 free (reg_last_set_invalid);
763 free (reg_last_set_mode);
764 free (reg_last_set_nonzero_bits);
765 free (reg_last_set_sign_bit_copies);
769 struct undo *undo, *next;
770 for (undo = undobuf.frees; undo; undo = next)
778 total_attempts += combine_attempts;
779 total_merges += combine_merges;
780 total_extras += combine_extras;
781 total_successes += combine_successes;
783 nonzero_sign_valid = 0;
785 /* Make recognizer allow volatile MEMs again. */
788 return new_direct_jump_p;
791 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
794 init_reg_last_arrays ()
796 unsigned int nregs = combine_max_regno;
798 memset ((char *) reg_last_death, 0, nregs * sizeof (rtx));
799 memset ((char *) reg_last_set, 0, nregs * sizeof (rtx));
800 memset ((char *) reg_last_set_value, 0, nregs * sizeof (rtx));
801 memset ((char *) reg_last_set_table_tick, 0, nregs * sizeof (int));
802 memset ((char *) reg_last_set_label, 0, nregs * sizeof (int));
803 memset (reg_last_set_invalid, 0, nregs * sizeof (char));
804 memset ((char *) reg_last_set_mode, 0, nregs * sizeof (enum machine_mode));
805 memset ((char *) reg_last_set_nonzero_bits, 0, nregs * sizeof (HOST_WIDE_INT));
806 memset (reg_last_set_sign_bit_copies, 0, nregs * sizeof (char));
809 /* Set up any promoted values for incoming argument registers. */
812 setup_incoming_promotions ()
814 #ifdef PROMOTE_FUNCTION_ARGS
817 enum machine_mode mode;
819 rtx first = get_insns ();
821 #ifndef OUTGOING_REGNO
822 #define OUTGOING_REGNO(N) N
824 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
825 /* Check whether this register can hold an incoming pointer
826 argument. FUNCTION_ARG_REGNO_P tests outgoing register
827 numbers, so translate if necessary due to register windows. */
828 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno))
829 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
832 (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
835 gen_rtx_CLOBBER (mode, const0_rtx)));
840 /* Called via note_stores. If X is a pseudo that is narrower than
841 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
843 If we are setting only a portion of X and we can't figure out what
844 portion, assume all bits will be used since we don't know what will
847 Similarly, set how many bits of X are known to be copies of the sign bit
848 at all locations in the function. This is the smallest number implied
852 set_nonzero_bits_and_sign_copies (x, set, data)
855 void *data ATTRIBUTE_UNUSED;
859 if (GET_CODE (x) == REG
860 && REGNO (x) >= FIRST_PSEUDO_REGISTER
861 /* If this register is undefined at the start of the file, we can't
862 say what its contents were. */
863 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start, REGNO (x))
864 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
866 if (set == 0 || GET_CODE (set) == CLOBBER)
868 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
869 reg_sign_bit_copies[REGNO (x)] = 1;
873 /* If this is a complex assignment, see if we can convert it into a
874 simple assignment. */
875 set = expand_field_assignment (set);
877 /* If this is a simple assignment, or we have a paradoxical SUBREG,
878 set what we know about X. */
880 if (SET_DEST (set) == x
881 || (GET_CODE (SET_DEST (set)) == SUBREG
882 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
883 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
884 && SUBREG_REG (SET_DEST (set)) == x))
886 rtx src = SET_SRC (set);
888 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
889 /* If X is narrower than a word and SRC is a non-negative
890 constant that would appear negative in the mode of X,
891 sign-extend it for use in reg_nonzero_bits because some
892 machines (maybe most) will actually do the sign-extension
893 and this is the conservative approach.
895 ??? For 2.5, try to tighten up the MD files in this regard
896 instead of this kludge. */
898 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
899 && GET_CODE (src) == CONST_INT
901 && 0 != (INTVAL (src)
903 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
904 src = GEN_INT (INTVAL (src)
905 | ((HOST_WIDE_INT) (-1)
906 << GET_MODE_BITSIZE (GET_MODE (x))));
909 /* Don't call nonzero_bits if it cannot change anything. */
910 if (reg_nonzero_bits[REGNO (x)] != ~(unsigned HOST_WIDE_INT) 0)
911 reg_nonzero_bits[REGNO (x)]
912 |= nonzero_bits (src, nonzero_bits_mode);
913 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
914 if (reg_sign_bit_copies[REGNO (x)] == 0
915 || reg_sign_bit_copies[REGNO (x)] > num)
916 reg_sign_bit_copies[REGNO (x)] = num;
920 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
921 reg_sign_bit_copies[REGNO (x)] = 1;
926 /* See if INSN can be combined into I3. PRED and SUCC are optionally
927 insns that were previously combined into I3 or that will be combined
928 into the merger of INSN and I3.
930 Return 0 if the combination is not allowed for any reason.
932 If the combination is allowed, *PDEST will be set to the single
933 destination of INSN and *PSRC to the single source, and this function
937 can_combine_p (insn, i3, pred, succ, pdest, psrc)
940 rtx pred ATTRIBUTE_UNUSED;
945 rtx set = 0, src, dest;
950 int all_adjacent = (succ ? (next_active_insn (insn) == succ
951 && next_active_insn (succ) == i3)
952 : next_active_insn (insn) == i3);
954 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
955 or a PARALLEL consisting of such a SET and CLOBBERs.
957 If INSN has CLOBBER parallel parts, ignore them for our processing.
958 By definition, these happen during the execution of the insn. When it
959 is merged with another insn, all bets are off. If they are, in fact,
960 needed and aren't also supplied in I3, they may be added by
961 recog_for_combine. Otherwise, it won't match.
963 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
966 Get the source and destination of INSN. If more than one, can't
969 if (GET_CODE (PATTERN (insn)) == SET)
970 set = PATTERN (insn);
971 else if (GET_CODE (PATTERN (insn)) == PARALLEL
972 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
974 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
976 rtx elt = XVECEXP (PATTERN (insn), 0, i);
978 switch (GET_CODE (elt))
980 /* This is important to combine floating point insns
983 /* Combining an isolated USE doesn't make sense.
984 We depend here on combinable_i3pat to reject them. */
985 /* The code below this loop only verifies that the inputs of
986 the SET in INSN do not change. We call reg_set_between_p
987 to verify that the REG in the USE does not change between
989 If the USE in INSN was for a pseudo register, the matching
990 insn pattern will likely match any register; combining this
991 with any other USE would only be safe if we knew that the
992 used registers have identical values, or if there was
993 something to tell them apart, e.g. different modes. For
994 now, we forgo such complicated tests and simply disallow
995 combining of USES of pseudo registers with any other USE. */
996 if (GET_CODE (XEXP (elt, 0)) == REG
997 && GET_CODE (PATTERN (i3)) == PARALLEL)
999 rtx i3pat = PATTERN (i3);
1000 int i = XVECLEN (i3pat, 0) - 1;
1001 unsigned int regno = REGNO (XEXP (elt, 0));
1005 rtx i3elt = XVECEXP (i3pat, 0, i);
1007 if (GET_CODE (i3elt) == USE
1008 && GET_CODE (XEXP (i3elt, 0)) == REG
1009 && (REGNO (XEXP (i3elt, 0)) == regno
1010 ? reg_set_between_p (XEXP (elt, 0),
1011 PREV_INSN (insn), i3)
1012 : regno >= FIRST_PSEUDO_REGISTER))
1019 /* We can ignore CLOBBERs. */
1024 /* Ignore SETs whose result isn't used but not those that
1025 have side-effects. */
1026 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1027 && ! side_effects_p (elt))
1030 /* If we have already found a SET, this is a second one and
1031 so we cannot combine with this insn. */
1039 /* Anything else means we can't combine. */
1045 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1046 so don't do anything with it. */
1047 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1056 set = expand_field_assignment (set);
1057 src = SET_SRC (set), dest = SET_DEST (set);
1059 /* Don't eliminate a store in the stack pointer. */
1060 if (dest == stack_pointer_rtx
1061 /* If we couldn't eliminate a field assignment, we can't combine. */
1062 || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART
1063 /* Don't combine with an insn that sets a register to itself if it has
1064 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1065 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1066 /* Can't merge an ASM_OPERANDS. */
1067 || GET_CODE (src) == ASM_OPERANDS
1068 /* Can't merge a function call. */
1069 || GET_CODE (src) == CALL
1070 /* Don't eliminate a function call argument. */
1071 || (GET_CODE (i3) == CALL_INSN
1072 && (find_reg_fusage (i3, USE, dest)
1073 || (GET_CODE (dest) == REG
1074 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1075 && global_regs[REGNO (dest)])))
1076 /* Don't substitute into an incremented register. */
1077 || FIND_REG_INC_NOTE (i3, dest)
1078 || (succ && FIND_REG_INC_NOTE (succ, dest))
1080 /* Don't combine the end of a libcall into anything. */
1081 /* ??? This gives worse code, and appears to be unnecessary, since no
1082 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1083 use REG_RETVAL notes for noconflict blocks, but other code here
1084 makes sure that those insns don't disappear. */
1085 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
1087 /* Make sure that DEST is not used after SUCC but before I3. */
1088 || (succ && ! all_adjacent
1089 && reg_used_between_p (dest, succ, i3))
1090 /* Make sure that the value that is to be substituted for the register
1091 does not use any registers whose values alter in between. However,
1092 If the insns are adjacent, a use can't cross a set even though we
1093 think it might (this can happen for a sequence of insns each setting
1094 the same destination; reg_last_set of that register might point to
1095 a NOTE). If INSN has a REG_EQUIV note, the register is always
1096 equivalent to the memory so the substitution is valid even if there
1097 are intervening stores. Also, don't move a volatile asm or
1098 UNSPEC_VOLATILE across any other insns. */
1100 && (((GET_CODE (src) != MEM
1101 || ! find_reg_note (insn, REG_EQUIV, src))
1102 && use_crosses_set_p (src, INSN_CUID (insn)))
1103 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1104 || GET_CODE (src) == UNSPEC_VOLATILE))
1105 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1106 better register allocation by not doing the combine. */
1107 || find_reg_note (i3, REG_NO_CONFLICT, dest)
1108 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
1109 /* Don't combine across a CALL_INSN, because that would possibly
1110 change whether the life span of some REGs crosses calls or not,
1111 and it is a pain to update that information.
1112 Exception: if source is a constant, moving it later can't hurt.
1113 Accept that special case, because it helps -fforce-addr a lot. */
1114 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
1117 /* DEST must either be a REG or CC0. */
1118 if (GET_CODE (dest) == REG)
1120 /* If register alignment is being enforced for multi-word items in all
1121 cases except for parameters, it is possible to have a register copy
1122 insn referencing a hard register that is not allowed to contain the
1123 mode being copied and which would not be valid as an operand of most
1124 insns. Eliminate this problem by not combining with such an insn.
1126 Also, on some machines we don't want to extend the life of a hard
1129 if (GET_CODE (src) == REG
1130 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1131 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1132 /* Don't extend the life of a hard register unless it is
1133 user variable (if we have few registers) or it can't
1134 fit into the desired register (meaning something special
1136 Also avoid substituting a return register into I3, because
1137 reload can't handle a conflict with constraints of other
1139 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1140 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1143 else if (GET_CODE (dest) != CC0)
1146 /* Don't substitute for a register intended as a clobberable operand.
1147 Similarly, don't substitute an expression containing a register that
1148 will be clobbered in I3. */
1149 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1150 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1151 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
1152 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0),
1154 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)))
1157 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1158 or not), reject, unless nothing volatile comes between it and I3 */
1160 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1162 /* Make sure succ doesn't contain a volatile reference. */
1163 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1166 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1167 if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1171 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1172 to be an explicit register variable, and was chosen for a reason. */
1174 if (GET_CODE (src) == ASM_OPERANDS
1175 && GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1178 /* If there are any volatile insns between INSN and I3, reject, because
1179 they might affect machine state. */
1181 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1182 if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1185 /* If INSN or I2 contains an autoincrement or autodecrement,
1186 make sure that register is not used between there and I3,
1187 and not already used in I3 either.
1188 Also insist that I3 not be a jump; if it were one
1189 and the incremented register were spilled, we would lose. */
1192 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1193 if (REG_NOTE_KIND (link) == REG_INC
1194 && (GET_CODE (i3) == JUMP_INSN
1195 || reg_used_between_p (XEXP (link, 0), insn, i3)
1196 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1201 /* Don't combine an insn that follows a CC0-setting insn.
1202 An insn that uses CC0 must not be separated from the one that sets it.
1203 We do, however, allow I2 to follow a CC0-setting insn if that insn
1204 is passed as I1; in that case it will be deleted also.
1205 We also allow combining in this case if all the insns are adjacent
1206 because that would leave the two CC0 insns adjacent as well.
1207 It would be more logical to test whether CC0 occurs inside I1 or I2,
1208 but that would be much slower, and this ought to be equivalent. */
1210 p = prev_nonnote_insn (insn);
1211 if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
1216 /* If we get here, we have passed all the tests and the combination is
1225 /* Check if PAT is an insn - or a part of it - used to set up an
1226 argument for a function in a hard register. */
1229 sets_function_arg_p (pat)
1235 switch (GET_CODE (pat))
1238 return sets_function_arg_p (PATTERN (pat));
1241 for (i = XVECLEN (pat, 0); --i >= 0;)
1242 if (sets_function_arg_p (XVECEXP (pat, 0, i)))
1248 inner_dest = SET_DEST (pat);
1249 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1250 || GET_CODE (inner_dest) == SUBREG
1251 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1252 inner_dest = XEXP (inner_dest, 0);
1254 return (GET_CODE (inner_dest) == REG
1255 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1256 && FUNCTION_ARG_REGNO_P (REGNO (inner_dest)));
1265 /* LOC is the location within I3 that contains its pattern or the component
1266 of a PARALLEL of the pattern. We validate that it is valid for combining.
1268 One problem is if I3 modifies its output, as opposed to replacing it
1269 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1270 so would produce an insn that is not equivalent to the original insns.
1274 (set (reg:DI 101) (reg:DI 100))
1275 (set (subreg:SI (reg:DI 101) 0) <foo>)
1277 This is NOT equivalent to:
1279 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1280 (set (reg:DI 101) (reg:DI 100))])
1282 Not only does this modify 100 (in which case it might still be valid
1283 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1285 We can also run into a problem if I2 sets a register that I1
1286 uses and I1 gets directly substituted into I3 (not via I2). In that
1287 case, we would be getting the wrong value of I2DEST into I3, so we
1288 must reject the combination. This case occurs when I2 and I1 both
1289 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1290 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
1291 of a SET must prevent combination from occurring.
1293 Before doing the above check, we first try to expand a field assignment
1294 into a set of logical operations.
1296 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
1297 we place a register that is both set and used within I3. If more than one
1298 such register is detected, we fail.
1300 Return 1 if the combination is valid, zero otherwise. */
1303 combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed)
1309 rtx *pi3dest_killed;
1313 if (GET_CODE (x) == SET)
1315 rtx set = expand_field_assignment (x);
1316 rtx dest = SET_DEST (set);
1317 rtx src = SET_SRC (set);
1318 rtx inner_dest = dest;
1321 rtx inner_src = src;
1326 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1327 || GET_CODE (inner_dest) == SUBREG
1328 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1329 inner_dest = XEXP (inner_dest, 0);
1331 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1334 while (GET_CODE (inner_src) == STRICT_LOW_PART
1335 || GET_CODE (inner_src) == SUBREG
1336 || GET_CODE (inner_src) == ZERO_EXTRACT)
1337 inner_src = XEXP (inner_src, 0);
1339 /* If it is better that two different modes keep two different pseudos,
1340 avoid combining them. This avoids producing the following pattern
1342 (set (subreg:SI (reg/v:QI 21) 0)
1343 (lshiftrt:SI (reg/v:SI 20)
1345 If that were made, reload could not handle the pair of
1346 reg 20/21, since it would try to get any GENERAL_REGS
1347 but some of them don't handle QImode. */
1349 if (rtx_equal_p (inner_src, i2dest)
1350 && GET_CODE (inner_dest) == REG
1351 && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest)))
1355 /* Check for the case where I3 modifies its output, as
1357 if ((inner_dest != dest
1358 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1359 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1361 /* This is the same test done in can_combine_p except we can't test
1362 all_adjacent; we don't have to, since this instruction will stay
1363 in place, thus we are not considering increasing the lifetime of
1366 Also, if this insn sets a function argument, combining it with
1367 something that might need a spill could clobber a previous
1368 function argument; the all_adjacent test in can_combine_p also
1369 checks this; here, we do a more specific test for this case. */
1371 || (GET_CODE (inner_dest) == REG
1372 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1373 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1374 GET_MODE (inner_dest))))
1375 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1378 /* If DEST is used in I3, it is being killed in this insn,
1379 so record that for later.
1380 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1381 STACK_POINTER_REGNUM, since these are always considered to be
1382 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1383 if (pi3dest_killed && GET_CODE (dest) == REG
1384 && reg_referenced_p (dest, PATTERN (i3))
1385 && REGNO (dest) != FRAME_POINTER_REGNUM
1386 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1387 && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
1389 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1390 && (REGNO (dest) != ARG_POINTER_REGNUM
1391 || ! fixed_regs [REGNO (dest)])
1393 && REGNO (dest) != STACK_POINTER_REGNUM)
1395 if (*pi3dest_killed)
1398 *pi3dest_killed = dest;
1402 else if (GET_CODE (x) == PARALLEL)
1406 for (i = 0; i < XVECLEN (x, 0); i++)
1407 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1408 i1_not_in_src, pi3dest_killed))
1415 /* Return 1 if X is an arithmetic expression that contains a multiplication
1416 and division. We don't count multiplications by powers of two here. */
1422 switch (GET_CODE (x))
1424 case MOD: case DIV: case UMOD: case UDIV:
1428 return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1429 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1431 switch (GET_RTX_CLASS (GET_CODE (x)))
1433 case 'c': case '<': case '2':
1434 return contains_muldiv (XEXP (x, 0))
1435 || contains_muldiv (XEXP (x, 1));
1438 return contains_muldiv (XEXP (x, 0));
1446 /* Determine whether INSN can be used in a combination. Return nonzero if
1447 not. This is used in try_combine to detect early some cases where we
1448 can't perform combinations. */
1451 cant_combine_insn_p (insn)
1457 /* If this isn't really an insn, we can't do anything.
1458 This can occur when flow deletes an insn that it has merged into an
1459 auto-increment address. */
1460 if (! INSN_P (insn))
1463 /* Never combine loads and stores involving hard regs. The register
1464 allocator can usually handle such reg-reg moves by tying. If we allow
1465 the combiner to make substitutions of hard regs, we risk aborting in
1466 reload on machines that have SMALL_REGISTER_CLASSES.
1467 As an exception, we allow combinations involving fixed regs; these are
1468 not available to the register allocator so there's no risk involved. */
1470 set = single_set (insn);
1473 src = SET_SRC (set);
1474 dest = SET_DEST (set);
1475 if (GET_CODE (src) == SUBREG)
1476 src = SUBREG_REG (src);
1477 if (GET_CODE (dest) == SUBREG)
1478 dest = SUBREG_REG (dest);
1479 if (REG_P (src) && REG_P (dest)
1480 && ((REGNO (src) < FIRST_PSEUDO_REGISTER
1481 && ! fixed_regs[REGNO (src)])
1482 || (REGNO (dest) < FIRST_PSEUDO_REGISTER
1483 && ! fixed_regs[REGNO (dest)])))
1489 /* Try to combine the insns I1 and I2 into I3.
1490 Here I1 and I2 appear earlier than I3.
1491 I1 can be zero; then we combine just I2 into I3.
1493 If we are combining three insns and the resulting insn is not recognized,
1494 try splitting it into two insns. If that happens, I2 and I3 are retained
1495 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1498 Return 0 if the combination does not work. Then nothing is changed.
1499 If we did the combination, return the insn at which combine should
1502 Set NEW_DIRECT_JUMP_P to a non-zero value if try_combine creates a
1503 new direct jump instruction. */
1506 try_combine (i3, i2, i1, new_direct_jump_p)
1508 int *new_direct_jump_p;
1510 /* New patterns for I3 and I2, respectively. */
1511 rtx newpat, newi2pat = 0;
1512 int substed_i2 = 0, substed_i1 = 0;
1513 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1514 int added_sets_1, added_sets_2;
1515 /* Total number of SETs to put into I3. */
1517 /* Nonzero is I2's body now appears in I3. */
1519 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1520 int insn_code_number, i2_code_number = 0, other_code_number = 0;
1521 /* Contains I3 if the destination of I3 is used in its source, which means
1522 that the old life of I3 is being killed. If that usage is placed into
1523 I2 and not in I3, a REG_DEAD note must be made. */
1524 rtx i3dest_killed = 0;
1525 /* SET_DEST and SET_SRC of I2 and I1. */
1526 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1527 /* PATTERN (I2), or a copy of it in certain cases. */
1529 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1530 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1531 int i1_feeds_i3 = 0;
1532 /* Notes that must be added to REG_NOTES in I3 and I2. */
1533 rtx new_i3_notes, new_i2_notes;
1534 /* Notes that we substituted I3 into I2 instead of the normal case. */
1535 int i3_subst_into_i2 = 0;
1536 /* Notes that I1, I2 or I3 is a MULT operation. */
1544 /* Exit early if one of the insns involved can't be used for
1546 if (cant_combine_insn_p (i3)
1547 || cant_combine_insn_p (i2)
1548 || (i1 && cant_combine_insn_p (i1))
1549 /* We also can't do anything if I3 has a
1550 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1553 /* ??? This gives worse code, and appears to be unnecessary, since no
1554 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1555 || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1561 undobuf.other_insn = 0;
1563 /* Reset the hard register usage information. */
1564 CLEAR_HARD_REG_SET (newpat_used_regs);
1566 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1567 code below, set I1 to be the earlier of the two insns. */
1568 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1569 temp = i1, i1 = i2, i2 = temp;
1571 added_links_insn = 0;
1573 /* First check for one important special-case that the code below will
1574 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1575 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1576 we may be able to replace that destination with the destination of I3.
1577 This occurs in the common code where we compute both a quotient and
1578 remainder into a structure, in which case we want to do the computation
1579 directly into the structure to avoid register-register copies.
1581 Note that this case handles both multiple sets in I2 and also
1582 cases where I2 has a number of CLOBBER or PARALLELs.
1584 We make very conservative checks below and only try to handle the
1585 most common cases of this. For example, we only handle the case
1586 where I2 and I3 are adjacent to avoid making difficult register
1589 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1590 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1591 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1592 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1593 && GET_CODE (PATTERN (i2)) == PARALLEL
1594 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1595 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1596 below would need to check what is inside (and reg_overlap_mentioned_p
1597 doesn't support those codes anyway). Don't allow those destinations;
1598 the resulting insn isn't likely to be recognized anyway. */
1599 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1600 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1601 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1602 SET_DEST (PATTERN (i3)))
1603 && next_real_insn (i2) == i3)
1605 rtx p2 = PATTERN (i2);
1607 /* Make sure that the destination of I3,
1608 which we are going to substitute into one output of I2,
1609 is not used within another output of I2. We must avoid making this:
1610 (parallel [(set (mem (reg 69)) ...)
1611 (set (reg 69) ...)])
1612 which is not well-defined as to order of actions.
1613 (Besides, reload can't handle output reloads for this.)
1615 The problem can also happen if the dest of I3 is a memory ref,
1616 if another dest in I2 is an indirect memory ref. */
1617 for (i = 0; i < XVECLEN (p2, 0); i++)
1618 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1619 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1620 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1621 SET_DEST (XVECEXP (p2, 0, i))))
1624 if (i == XVECLEN (p2, 0))
1625 for (i = 0; i < XVECLEN (p2, 0); i++)
1626 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1627 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1628 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1633 subst_low_cuid = INSN_CUID (i2);
1635 added_sets_2 = added_sets_1 = 0;
1636 i2dest = SET_SRC (PATTERN (i3));
1638 /* Replace the dest in I2 with our dest and make the resulting
1639 insn the new pattern for I3. Then skip to where we
1640 validate the pattern. Everything was set up above. */
1641 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1642 SET_DEST (PATTERN (i3)));
1645 i3_subst_into_i2 = 1;
1646 goto validate_replacement;
1650 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1651 one of those words to another constant, merge them by making a new
1654 && (temp = single_set (i2)) != 0
1655 && (GET_CODE (SET_SRC (temp)) == CONST_INT
1656 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
1657 && GET_CODE (SET_DEST (temp)) == REG
1658 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp))) == MODE_INT
1659 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp))) == 2 * UNITS_PER_WORD
1660 && GET_CODE (PATTERN (i3)) == SET
1661 && GET_CODE (SET_DEST (PATTERN (i3))) == SUBREG
1662 && SUBREG_REG (SET_DEST (PATTERN (i3))) == SET_DEST (temp)
1663 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3)))) == MODE_INT
1664 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3)))) == UNITS_PER_WORD
1665 && GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT)
1667 HOST_WIDE_INT lo, hi;
1669 if (GET_CODE (SET_SRC (temp)) == CONST_INT)
1670 lo = INTVAL (SET_SRC (temp)), hi = lo < 0 ? -1 : 0;
1673 lo = CONST_DOUBLE_LOW (SET_SRC (temp));
1674 hi = CONST_DOUBLE_HIGH (SET_SRC (temp));
1677 if (subreg_lowpart_p (SET_DEST (PATTERN (i3))))
1679 /* We don't handle the case of the target word being wider
1680 than a host wide int. */
1681 if (HOST_BITS_PER_WIDE_INT < BITS_PER_WORD)
1684 lo &= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1685 lo |= (INTVAL (SET_SRC (PATTERN (i3)))
1686 & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1688 else if (HOST_BITS_PER_WIDE_INT == BITS_PER_WORD)
1689 hi = INTVAL (SET_SRC (PATTERN (i3)));
1690 else if (HOST_BITS_PER_WIDE_INT >= 2 * BITS_PER_WORD)
1692 int sign = -(int) ((unsigned HOST_WIDE_INT) lo
1693 >> (HOST_BITS_PER_WIDE_INT - 1));
1695 lo &= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1696 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1697 lo |= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1698 (INTVAL (SET_SRC (PATTERN (i3)))));
1700 hi = lo < 0 ? -1 : 0;
1703 /* We don't handle the case of the higher word not fitting
1704 entirely in either hi or lo. */
1709 subst_low_cuid = INSN_CUID (i2);
1710 added_sets_2 = added_sets_1 = 0;
1711 i2dest = SET_DEST (temp);
1713 SUBST (SET_SRC (temp),
1714 immed_double_const (lo, hi, GET_MODE (SET_DEST (temp))));
1716 newpat = PATTERN (i2);
1717 goto validate_replacement;
1721 /* If we have no I1 and I2 looks like:
1722 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1724 make up a dummy I1 that is
1727 (set (reg:CC X) (compare:CC Y (const_int 0)))
1729 (We can ignore any trailing CLOBBERs.)
1731 This undoes a previous combination and allows us to match a branch-and-
1734 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1735 && XVECLEN (PATTERN (i2), 0) >= 2
1736 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1737 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1739 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1740 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1741 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1742 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1743 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1744 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1746 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1747 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1752 /* We make I1 with the same INSN_UID as I2. This gives it
1753 the same INSN_CUID for value tracking. Our fake I1 will
1754 never appear in the insn stream so giving it the same INSN_UID
1755 as I2 will not cause a problem. */
1757 subst_prev_insn = i1
1758 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
1759 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
1762 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1763 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1764 SET_DEST (PATTERN (i1)));
1769 /* Verify that I2 and I1 are valid for combining. */
1770 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1771 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1777 /* Record whether I2DEST is used in I2SRC and similarly for the other
1778 cases. Knowing this will help in register status updating below. */
1779 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1780 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1781 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1783 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1785 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1787 /* Ensure that I3's pattern can be the destination of combines. */
1788 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1789 i1 && i2dest_in_i1src && i1_feeds_i3,
1796 /* See if any of the insns is a MULT operation. Unless one is, we will
1797 reject a combination that is, since it must be slower. Be conservative
1799 if (GET_CODE (i2src) == MULT
1800 || (i1 != 0 && GET_CODE (i1src) == MULT)
1801 || (GET_CODE (PATTERN (i3)) == SET
1802 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
1805 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1806 We used to do this EXCEPT in one case: I3 has a post-inc in an
1807 output operand. However, that exception can give rise to insns like
1809 which is a famous insn on the PDP-11 where the value of r3 used as the
1810 source was model-dependent. Avoid this sort of thing. */
1813 if (!(GET_CODE (PATTERN (i3)) == SET
1814 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1815 && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1816 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1817 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1818 /* It's not the exception. */
1821 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1822 if (REG_NOTE_KIND (link) == REG_INC
1823 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1825 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1832 /* See if the SETs in I1 or I2 need to be kept around in the merged
1833 instruction: whenever the value set there is still needed past I3.
1834 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1836 For the SET in I1, we have two cases: If I1 and I2 independently
1837 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1838 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1839 in I1 needs to be kept around unless I1DEST dies or is set in either
1840 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1841 I1DEST. If so, we know I1 feeds into I2. */
1843 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1846 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1847 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1849 /* If the set in I2 needs to be kept around, we must make a copy of
1850 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1851 PATTERN (I2), we are only substituting for the original I1DEST, not into
1852 an already-substituted copy. This also prevents making self-referential
1853 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1856 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1857 ? gen_rtx_SET (VOIDmode, i2dest, i2src)
1861 i2pat = copy_rtx (i2pat);
1865 /* Substitute in the latest insn for the regs set by the earlier ones. */
1867 maxreg = max_reg_num ();
1871 /* It is possible that the source of I2 or I1 may be performing an
1872 unneeded operation, such as a ZERO_EXTEND of something that is known
1873 to have the high part zero. Handle that case by letting subst look at
1874 the innermost one of them.
1876 Another way to do this would be to have a function that tries to
1877 simplify a single insn instead of merging two or more insns. We don't
1878 do this because of the potential of infinite loops and because
1879 of the potential extra memory required. However, doing it the way
1880 we are is a bit of a kludge and doesn't catch all cases.
1882 But only do this if -fexpensive-optimizations since it slows things down
1883 and doesn't usually win. */
1885 if (flag_expensive_optimizations)
1887 /* Pass pc_rtx so no substitutions are done, just simplifications.
1888 The cases that we are interested in here do not involve the few
1889 cases were is_replaced is checked. */
1892 subst_low_cuid = INSN_CUID (i1);
1893 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1897 subst_low_cuid = INSN_CUID (i2);
1898 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1903 /* Many machines that don't use CC0 have insns that can both perform an
1904 arithmetic operation and set the condition code. These operations will
1905 be represented as a PARALLEL with the first element of the vector
1906 being a COMPARE of an arithmetic operation with the constant zero.
1907 The second element of the vector will set some pseudo to the result
1908 of the same arithmetic operation. If we simplify the COMPARE, we won't
1909 match such a pattern and so will generate an extra insn. Here we test
1910 for this case, where both the comparison and the operation result are
1911 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1912 I2SRC. Later we will make the PARALLEL that contains I2. */
1914 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1915 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1916 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1917 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1919 #ifdef EXTRA_CC_MODES
1921 enum machine_mode compare_mode;
1924 newpat = PATTERN (i3);
1925 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1929 #ifdef EXTRA_CC_MODES
1930 /* See if a COMPARE with the operand we substituted in should be done
1931 with the mode that is currently being used. If not, do the same
1932 processing we do in `subst' for a SET; namely, if the destination
1933 is used only once, try to replace it with a register of the proper
1934 mode and also replace the COMPARE. */
1935 if (undobuf.other_insn == 0
1936 && (cc_use = find_single_use (SET_DEST (newpat), i3,
1937 &undobuf.other_insn))
1938 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
1940 != GET_MODE (SET_DEST (newpat))))
1942 unsigned int regno = REGNO (SET_DEST (newpat));
1943 rtx new_dest = gen_rtx_REG (compare_mode, regno);
1945 if (regno < FIRST_PSEUDO_REGISTER
1946 || (REG_N_SETS (regno) == 1 && ! added_sets_2
1947 && ! REG_USERVAR_P (SET_DEST (newpat))))
1949 if (regno >= FIRST_PSEUDO_REGISTER)
1950 SUBST (regno_reg_rtx[regno], new_dest);
1952 SUBST (SET_DEST (newpat), new_dest);
1953 SUBST (XEXP (*cc_use, 0), new_dest);
1954 SUBST (SET_SRC (newpat),
1955 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
1958 undobuf.other_insn = 0;
1965 n_occurrences = 0; /* `subst' counts here */
1967 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1968 need to make a unique copy of I2SRC each time we substitute it
1969 to avoid self-referential rtl. */
1971 subst_low_cuid = INSN_CUID (i2);
1972 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1973 ! i1_feeds_i3 && i1dest_in_i1src);
1976 /* Record whether i2's body now appears within i3's body. */
1977 i2_is_used = n_occurrences;
1980 /* If we already got a failure, don't try to do more. Otherwise,
1981 try to substitute in I1 if we have it. */
1983 if (i1 && GET_CODE (newpat) != CLOBBER)
1985 /* Before we can do this substitution, we must redo the test done
1986 above (see detailed comments there) that ensures that I1DEST
1987 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1989 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
1997 subst_low_cuid = INSN_CUID (i1);
1998 newpat = subst (newpat, i1dest, i1src, 0, 0);
2002 /* Fail if an autoincrement side-effect has been duplicated. Be careful
2003 to count all the ways that I2SRC and I1SRC can be used. */
2004 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
2005 && i2_is_used + added_sets_2 > 1)
2006 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2007 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
2009 /* Fail if we tried to make a new register (we used to abort, but there's
2010 really no reason to). */
2011 || max_reg_num () != maxreg
2012 /* Fail if we couldn't do something and have a CLOBBER. */
2013 || GET_CODE (newpat) == CLOBBER
2014 /* Fail if this new pattern is a MULT and we didn't have one before
2015 at the outer level. */
2016 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
2023 /* If the actions of the earlier insns must be kept
2024 in addition to substituting them into the latest one,
2025 we must make a new PARALLEL for the latest insn
2026 to hold additional the SETs. */
2028 if (added_sets_1 || added_sets_2)
2032 if (GET_CODE (newpat) == PARALLEL)
2034 rtvec old = XVEC (newpat, 0);
2035 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
2036 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2037 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
2038 sizeof (old->elem[0]) * old->num_elem);
2043 total_sets = 1 + added_sets_1 + added_sets_2;
2044 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2045 XVECEXP (newpat, 0, 0) = old;
2049 XVECEXP (newpat, 0, --total_sets)
2050 = (GET_CODE (PATTERN (i1)) == PARALLEL
2051 ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
2055 /* If there is no I1, use I2's body as is. We used to also not do
2056 the subst call below if I2 was substituted into I3,
2057 but that could lose a simplification. */
2059 XVECEXP (newpat, 0, --total_sets) = i2pat;
2061 /* See comment where i2pat is assigned. */
2062 XVECEXP (newpat, 0, --total_sets)
2063 = subst (i2pat, i1dest, i1src, 0, 0);
2067 /* We come here when we are replacing a destination in I2 with the
2068 destination of I3. */
2069 validate_replacement:
2071 /* Note which hard regs this insn has as inputs. */
2072 mark_used_regs_combine (newpat);
2074 /* Is the result of combination a valid instruction? */
2075 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2077 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2078 the second SET's destination is a register that is unused. In that case,
2079 we just need the first SET. This can occur when simplifying a divmod
2080 insn. We *must* test for this case here because the code below that
2081 splits two independent SETs doesn't handle this case correctly when it
2082 updates the register status. Also check the case where the first
2083 SET's destination is unused. That would not cause incorrect code, but
2084 does cause an unneeded insn to remain. */
2086 if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
2087 && XVECLEN (newpat, 0) == 2
2088 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2089 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2090 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
2091 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
2092 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
2093 && asm_noperands (newpat) < 0)
2095 newpat = XVECEXP (newpat, 0, 0);
2096 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2099 else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
2100 && XVECLEN (newpat, 0) == 2
2101 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2102 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2103 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
2104 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
2105 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
2106 && asm_noperands (newpat) < 0)
2108 newpat = XVECEXP (newpat, 0, 1);
2109 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2112 /* If we were combining three insns and the result is a simple SET
2113 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2114 insns. There are two ways to do this. It can be split using a
2115 machine-specific method (like when you have an addition of a large
2116 constant) or by combine in the function find_split_point. */
2118 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2119 && asm_noperands (newpat) < 0)
2121 rtx m_split, *split;
2122 rtx ni2dest = i2dest;
2124 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2125 use I2DEST as a scratch register will help. In the latter case,
2126 convert I2DEST to the mode of the source of NEWPAT if we can. */
2128 m_split = split_insns (newpat, i3);
2130 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2131 inputs of NEWPAT. */
2133 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2134 possible to try that as a scratch reg. This would require adding
2135 more code to make it work though. */
2137 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
2139 /* If I2DEST is a hard register or the only use of a pseudo,
2140 we can change its mode. */
2141 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
2142 && GET_MODE (SET_DEST (newpat)) != VOIDmode
2143 && GET_CODE (i2dest) == REG
2144 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2145 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2146 && ! REG_USERVAR_P (i2dest))))
2147 ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)),
2150 m_split = split_insns (gen_rtx_PARALLEL
2152 gen_rtvec (2, newpat,
2153 gen_rtx_CLOBBER (VOIDmode,
2156 /* If the split with the mode-changed register didn't work, try
2157 the original register. */
2158 if (! m_split && ni2dest != i2dest)
2161 m_split = split_insns (gen_rtx_PARALLEL
2163 gen_rtvec (2, newpat,
2164 gen_rtx_CLOBBER (VOIDmode,
2170 /* If we've split a jump pattern, we'll wind up with a sequence even
2171 with one instruction. We can handle that below, so extract it. */
2172 if (m_split && GET_CODE (m_split) == SEQUENCE
2173 && XVECLEN (m_split, 0) == 1)
2174 m_split = PATTERN (XVECEXP (m_split, 0, 0));
2176 if (m_split && GET_CODE (m_split) != SEQUENCE)
2178 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
2179 if (insn_code_number >= 0)
2182 else if (m_split && GET_CODE (m_split) == SEQUENCE
2183 && XVECLEN (m_split, 0) == 2
2184 && (next_real_insn (i2) == i3
2185 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split, 0, 0)),
2189 rtx newi3pat = PATTERN (XVECEXP (m_split, 0, 1));
2190 newi2pat = PATTERN (XVECEXP (m_split, 0, 0));
2192 i3set = single_set (XVECEXP (m_split, 0, 1));
2193 i2set = single_set (XVECEXP (m_split, 0, 0));
2195 /* In case we changed the mode of I2DEST, replace it in the
2196 pseudo-register table here. We can't do it above in case this
2197 code doesn't get executed and we do a split the other way. */
2199 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2200 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
2202 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2204 /* If I2 or I3 has multiple SETs, we won't know how to track
2205 register status, so don't use these insns. If I2's destination
2206 is used between I2 and I3, we also can't use these insns. */
2208 if (i2_code_number >= 0 && i2set && i3set
2209 && (next_real_insn (i2) == i3
2210 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
2211 insn_code_number = recog_for_combine (&newi3pat, i3,
2213 if (insn_code_number >= 0)
2216 /* It is possible that both insns now set the destination of I3.
2217 If so, we must show an extra use of it. */
2219 if (insn_code_number >= 0)
2221 rtx new_i3_dest = SET_DEST (i3set);
2222 rtx new_i2_dest = SET_DEST (i2set);
2224 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
2225 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
2226 || GET_CODE (new_i3_dest) == SUBREG)
2227 new_i3_dest = XEXP (new_i3_dest, 0);
2229 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
2230 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
2231 || GET_CODE (new_i2_dest) == SUBREG)
2232 new_i2_dest = XEXP (new_i2_dest, 0);
2234 if (GET_CODE (new_i3_dest) == REG
2235 && GET_CODE (new_i2_dest) == REG
2236 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
2237 REG_N_SETS (REGNO (new_i2_dest))++;
2241 /* If we can split it and use I2DEST, go ahead and see if that
2242 helps things be recognized. Verify that none of the registers
2243 are set between I2 and I3. */
2244 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
2246 && GET_CODE (i2dest) == REG
2248 /* We need I2DEST in the proper mode. If it is a hard register
2249 or the only use of a pseudo, we can change its mode. */
2250 && (GET_MODE (*split) == GET_MODE (i2dest)
2251 || GET_MODE (*split) == VOIDmode
2252 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2253 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2254 && ! REG_USERVAR_P (i2dest)))
2255 && (next_real_insn (i2) == i3
2256 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
2257 /* We can't overwrite I2DEST if its value is still used by
2259 && ! reg_referenced_p (i2dest, newpat))
2261 rtx newdest = i2dest;
2262 enum rtx_code split_code = GET_CODE (*split);
2263 enum machine_mode split_mode = GET_MODE (*split);
2265 /* Get NEWDEST as a register in the proper mode. We have already
2266 validated that we can do this. */
2267 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2269 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
2271 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2272 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
2275 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2276 an ASHIFT. This can occur if it was inside a PLUS and hence
2277 appeared to be a memory address. This is a kludge. */
2278 if (split_code == MULT
2279 && GET_CODE (XEXP (*split, 1)) == CONST_INT
2280 && INTVAL (XEXP (*split, 1)) > 0
2281 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
2283 SUBST (*split, gen_rtx_ASHIFT (split_mode,
2284 XEXP (*split, 0), GEN_INT (i)));
2285 /* Update split_code because we may not have a multiply
2287 split_code = GET_CODE (*split);
2290 #ifdef INSN_SCHEDULING
2291 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2292 be written as a ZERO_EXTEND. */
2293 if (split_code == SUBREG && GET_CODE (SUBREG_REG (*split)) == MEM)
2294 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
2295 SUBREG_REG (*split)));
2298 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
2299 SUBST (*split, newdest);
2300 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2302 /* If the split point was a MULT and we didn't have one before,
2303 don't use one now. */
2304 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
2305 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2309 /* Check for a case where we loaded from memory in a narrow mode and
2310 then sign extended it, but we need both registers. In that case,
2311 we have a PARALLEL with both loads from the same memory location.
2312 We can split this into a load from memory followed by a register-register
2313 copy. This saves at least one insn, more if register allocation can
2316 We cannot do this if the destination of the second assignment is
2317 a register that we have already assumed is zero-extended. Similarly
2318 for a SUBREG of such a register. */
2320 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2321 && GET_CODE (newpat) == PARALLEL
2322 && XVECLEN (newpat, 0) == 2
2323 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2324 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2325 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2326 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2327 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2328 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2330 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2331 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2332 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2333 (GET_CODE (temp) == REG
2334 && reg_nonzero_bits[REGNO (temp)] != 0
2335 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2336 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2337 && (reg_nonzero_bits[REGNO (temp)]
2338 != GET_MODE_MASK (word_mode))))
2339 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2340 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2341 (GET_CODE (temp) == REG
2342 && reg_nonzero_bits[REGNO (temp)] != 0
2343 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2344 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2345 && (reg_nonzero_bits[REGNO (temp)]
2346 != GET_MODE_MASK (word_mode)))))
2347 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2348 SET_SRC (XVECEXP (newpat, 0, 1)))
2349 && ! find_reg_note (i3, REG_UNUSED,
2350 SET_DEST (XVECEXP (newpat, 0, 0))))
2354 newi2pat = XVECEXP (newpat, 0, 0);
2355 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2356 newpat = XVECEXP (newpat, 0, 1);
2357 SUBST (SET_SRC (newpat),
2358 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest));
2359 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2361 if (i2_code_number >= 0)
2362 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2364 if (insn_code_number >= 0)
2369 /* If we will be able to accept this, we have made a change to the
2370 destination of I3. This can invalidate a LOG_LINKS pointing
2371 to I3. No other part of combine.c makes such a transformation.
2373 The new I3 will have a destination that was previously the
2374 destination of I1 or I2 and which was used in i2 or I3. Call
2375 distribute_links to make a LOG_LINK from the next use of
2376 that destination. */
2378 PATTERN (i3) = newpat;
2379 distribute_links (gen_rtx_INSN_LIST (VOIDmode, i3, NULL_RTX));
2381 /* I3 now uses what used to be its destination and which is
2382 now I2's destination. That means we need a LOG_LINK from
2383 I3 to I2. But we used to have one, so we still will.
2385 However, some later insn might be using I2's dest and have
2386 a LOG_LINK pointing at I3. We must remove this link.
2387 The simplest way to remove the link is to point it at I1,
2388 which we know will be a NOTE. */
2390 for (insn = NEXT_INSN (i3);
2391 insn && (this_basic_block == n_basic_blocks - 1
2392 || insn != BLOCK_HEAD (this_basic_block + 1));
2393 insn = NEXT_INSN (insn))
2395 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
2397 for (link = LOG_LINKS (insn); link;
2398 link = XEXP (link, 1))
2399 if (XEXP (link, 0) == i3)
2400 XEXP (link, 0) = i1;
2408 /* Similarly, check for a case where we have a PARALLEL of two independent
2409 SETs but we started with three insns. In this case, we can do the sets
2410 as two separate insns. This case occurs when some SET allows two
2411 other insns to combine, but the destination of that SET is still live. */
2413 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2414 && GET_CODE (newpat) == PARALLEL
2415 && XVECLEN (newpat, 0) == 2
2416 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2417 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2418 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2419 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2420 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2421 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2422 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2424 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2425 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2426 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2427 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2428 XVECEXP (newpat, 0, 0))
2429 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2430 XVECEXP (newpat, 0, 1))
2431 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
2432 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
2434 /* Normally, it doesn't matter which of the two is done first,
2435 but it does if one references cc0. In that case, it has to
2438 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2440 newi2pat = XVECEXP (newpat, 0, 0);
2441 newpat = XVECEXP (newpat, 0, 1);
2446 newi2pat = XVECEXP (newpat, 0, 1);
2447 newpat = XVECEXP (newpat, 0, 0);
2450 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2452 if (i2_code_number >= 0)
2453 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2456 /* If it still isn't recognized, fail and change things back the way they
2458 if ((insn_code_number < 0
2459 /* Is the result a reasonable ASM_OPERANDS? */
2460 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2466 /* If we had to change another insn, make sure it is valid also. */
2467 if (undobuf.other_insn)
2469 rtx other_pat = PATTERN (undobuf.other_insn);
2470 rtx new_other_notes;
2473 CLEAR_HARD_REG_SET (newpat_used_regs);
2475 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2478 if (other_code_number < 0 && ! check_asm_operands (other_pat))
2484 PATTERN (undobuf.other_insn) = other_pat;
2486 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2487 are still valid. Then add any non-duplicate notes added by
2488 recog_for_combine. */
2489 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2491 next = XEXP (note, 1);
2493 if (REG_NOTE_KIND (note) == REG_UNUSED
2494 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2496 if (GET_CODE (XEXP (note, 0)) == REG)
2497 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2499 remove_note (undobuf.other_insn, note);
2503 for (note = new_other_notes; note; note = XEXP (note, 1))
2504 if (GET_CODE (XEXP (note, 0)) == REG)
2505 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2507 distribute_notes (new_other_notes, undobuf.other_insn,
2508 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
2511 /* If I2 is the setter CC0 and I3 is the user CC0 then check whether
2512 they are adjacent to each other or not. */
2514 rtx p = prev_nonnote_insn (i3);
2515 if (p && p != i2 && GET_CODE (p) == INSN && newi2pat
2516 && sets_cc0_p (newi2pat))
2524 /* We now know that we can do this combination. Merge the insns and
2525 update the status of registers and LOG_LINKS. */
2528 rtx i3notes, i2notes, i1notes = 0;
2529 rtx i3links, i2links, i1links = 0;
2532 /* Compute which registers we expect to eliminate. newi2pat may be setting
2533 either i3dest or i2dest, so we must check it. Also, i1dest may be the
2534 same as i3dest, in which case newi2pat may be setting i1dest. */
2535 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
2536 || i2dest_in_i2src || i2dest_in_i1src
2538 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
2539 || (newi2pat && reg_set_p (i1dest, newi2pat))
2542 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2544 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2545 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2547 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2549 /* Ensure that we do not have something that should not be shared but
2550 occurs multiple times in the new insns. Check this by first
2551 resetting all the `used' flags and then copying anything is shared. */
2553 reset_used_flags (i3notes);
2554 reset_used_flags (i2notes);
2555 reset_used_flags (i1notes);
2556 reset_used_flags (newpat);
2557 reset_used_flags (newi2pat);
2558 if (undobuf.other_insn)
2559 reset_used_flags (PATTERN (undobuf.other_insn));
2561 i3notes = copy_rtx_if_shared (i3notes);
2562 i2notes = copy_rtx_if_shared (i2notes);
2563 i1notes = copy_rtx_if_shared (i1notes);
2564 newpat = copy_rtx_if_shared (newpat);
2565 newi2pat = copy_rtx_if_shared (newi2pat);
2566 if (undobuf.other_insn)
2567 reset_used_flags (PATTERN (undobuf.other_insn));
2569 INSN_CODE (i3) = insn_code_number;
2570 PATTERN (i3) = newpat;
2572 if (GET_CODE (i3) == CALL_INSN && CALL_INSN_FUNCTION_USAGE (i3))
2574 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
2576 reset_used_flags (call_usage);
2577 call_usage = copy_rtx (call_usage);
2580 replace_rtx (call_usage, i2dest, i2src);
2583 replace_rtx (call_usage, i1dest, i1src);
2585 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
2588 if (undobuf.other_insn)
2589 INSN_CODE (undobuf.other_insn) = other_code_number;
2591 /* We had one special case above where I2 had more than one set and
2592 we replaced a destination of one of those sets with the destination
2593 of I3. In that case, we have to update LOG_LINKS of insns later
2594 in this basic block. Note that this (expensive) case is rare.
2596 Also, in this case, we must pretend that all REG_NOTEs for I2
2597 actually came from I3, so that REG_UNUSED notes from I2 will be
2598 properly handled. */
2600 if (i3_subst_into_i2)
2602 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2603 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != USE
2604 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
2605 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2606 && ! find_reg_note (i2, REG_UNUSED,
2607 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2608 for (temp = NEXT_INSN (i2);
2609 temp && (this_basic_block == n_basic_blocks - 1
2610 || BLOCK_HEAD (this_basic_block) != temp);
2611 temp = NEXT_INSN (temp))
2612 if (temp != i3 && INSN_P (temp))
2613 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2614 if (XEXP (link, 0) == i2)
2615 XEXP (link, 0) = i3;
2620 while (XEXP (link, 1))
2621 link = XEXP (link, 1);
2622 XEXP (link, 1) = i2notes;
2636 INSN_CODE (i2) = i2_code_number;
2637 PATTERN (i2) = newi2pat;
2641 PUT_CODE (i2, NOTE);
2642 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
2643 NOTE_SOURCE_FILE (i2) = 0;
2650 PUT_CODE (i1, NOTE);
2651 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
2652 NOTE_SOURCE_FILE (i1) = 0;
2655 /* Get death notes for everything that is now used in either I3 or
2656 I2 and used to die in a previous insn. If we built two new
2657 patterns, move from I1 to I2 then I2 to I3 so that we get the
2658 proper movement on registers that I2 modifies. */
2662 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
2663 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
2666 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
2669 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2671 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
2674 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
2677 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
2680 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2683 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2684 know these are REG_UNUSED and want them to go to the desired insn,
2685 so we always pass it as i3. We have not counted the notes in
2686 reg_n_deaths yet, so we need to do so now. */
2688 if (newi2pat && new_i2_notes)
2690 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2691 if (GET_CODE (XEXP (temp, 0)) == REG)
2692 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2694 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2699 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2700 if (GET_CODE (XEXP (temp, 0)) == REG)
2701 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2703 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
2706 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2707 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2708 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2709 in that case, it might delete I2. Similarly for I2 and I1.
2710 Show an additional death due to the REG_DEAD note we make here. If
2711 we discard it in distribute_notes, we will decrement it again. */
2715 if (GET_CODE (i3dest_killed) == REG)
2716 REG_N_DEATHS (REGNO (i3dest_killed))++;
2718 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
2719 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2721 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
2723 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2725 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2729 if (i2dest_in_i2src)
2731 if (GET_CODE (i2dest) == REG)
2732 REG_N_DEATHS (REGNO (i2dest))++;
2734 if (newi2pat && reg_set_p (i2dest, newi2pat))
2735 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2736 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2738 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2739 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2740 NULL_RTX, NULL_RTX);
2743 if (i1dest_in_i1src)
2745 if (GET_CODE (i1dest) == REG)
2746 REG_N_DEATHS (REGNO (i1dest))++;
2748 if (newi2pat && reg_set_p (i1dest, newi2pat))
2749 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2750 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2752 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2753 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2754 NULL_RTX, NULL_RTX);
2757 distribute_links (i3links);
2758 distribute_links (i2links);
2759 distribute_links (i1links);
2761 if (GET_CODE (i2dest) == REG)
2764 rtx i2_insn = 0, i2_val = 0, set;
2766 /* The insn that used to set this register doesn't exist, and
2767 this life of the register may not exist either. See if one of
2768 I3's links points to an insn that sets I2DEST. If it does,
2769 that is now the last known value for I2DEST. If we don't update
2770 this and I2 set the register to a value that depended on its old
2771 contents, we will get confused. If this insn is used, thing
2772 will be set correctly in combine_instructions. */
2774 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2775 if ((set = single_set (XEXP (link, 0))) != 0
2776 && rtx_equal_p (i2dest, SET_DEST (set)))
2777 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2779 record_value_for_reg (i2dest, i2_insn, i2_val);
2781 /* If the reg formerly set in I2 died only once and that was in I3,
2782 zero its use count so it won't make `reload' do any work. */
2784 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
2785 && ! i2dest_in_i2src)
2787 regno = REGNO (i2dest);
2788 REG_N_SETS (regno)--;
2792 if (i1 && GET_CODE (i1dest) == REG)
2795 rtx i1_insn = 0, i1_val = 0, set;
2797 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2798 if ((set = single_set (XEXP (link, 0))) != 0
2799 && rtx_equal_p (i1dest, SET_DEST (set)))
2800 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2802 record_value_for_reg (i1dest, i1_insn, i1_val);
2804 regno = REGNO (i1dest);
2805 if (! added_sets_1 && ! i1dest_in_i1src)
2806 REG_N_SETS (regno)--;
2809 /* Update reg_nonzero_bits et al for any changes that may have been made
2810 to this insn. The order of set_nonzero_bits_and_sign_copies() is
2811 important. Because newi2pat can affect nonzero_bits of newpat */
2813 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
2814 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
2816 /* Set new_direct_jump_p if a new return or simple jump instruction
2819 If I3 is now an unconditional jump, ensure that it has a
2820 BARRIER following it since it may have initially been a
2821 conditional jump. It may also be the last nonnote insn. */
2823 if (GET_CODE (newpat) == RETURN || any_uncondjump_p (i3))
2825 *new_direct_jump_p = 1;
2827 if ((temp = next_nonnote_insn (i3)) == NULL_RTX
2828 || GET_CODE (temp) != BARRIER)
2829 emit_barrier_after (i3);
2831 /* An NOOP jump does not need barrier, but it does need cleaning up
2833 if (GET_CODE (newpat) == SET
2834 && SET_SRC (newpat) == pc_rtx
2835 && SET_DEST (newpat) == pc_rtx)
2836 *new_direct_jump_p = 1;
2839 combine_successes++;
2842 /* Clear this here, so that subsequent get_last_value calls are not
2844 subst_prev_insn = NULL_RTX;
2846 if (added_links_insn
2847 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
2848 && INSN_CUID (added_links_insn) < INSN_CUID (i3))
2849 return added_links_insn;
2851 return newi2pat ? i2 : i3;
2854 /* Undo all the modifications recorded in undobuf. */
2859 struct undo *undo, *next;
2861 for (undo = undobuf.undos; undo; undo = next)
2865 *undo->where.i = undo->old_contents.i;
2867 *undo->where.r = undo->old_contents.r;
2869 undo->next = undobuf.frees;
2870 undobuf.frees = undo;
2875 /* Clear this here, so that subsequent get_last_value calls are not
2877 subst_prev_insn = NULL_RTX;
2880 /* We've committed to accepting the changes we made. Move all
2881 of the undos to the free list. */
2886 struct undo *undo, *next;
2888 for (undo = undobuf.undos; undo; undo = next)
2891 undo->next = undobuf.frees;
2892 undobuf.frees = undo;
2898 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2899 where we have an arithmetic expression and return that point. LOC will
2902 try_combine will call this function to see if an insn can be split into
2906 find_split_point (loc, insn)
2911 enum rtx_code code = GET_CODE (x);
2913 unsigned HOST_WIDE_INT len = 0;
2914 HOST_WIDE_INT pos = 0;
2916 rtx inner = NULL_RTX;
2918 /* First special-case some codes. */
2922 #ifdef INSN_SCHEDULING
2923 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2925 if (GET_CODE (SUBREG_REG (x)) == MEM)
2928 return find_split_point (&SUBREG_REG (x), insn);
2932 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2933 using LO_SUM and HIGH. */
2934 if (GET_CODE (XEXP (x, 0)) == CONST
2935 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
2938 gen_rtx_LO_SUM (Pmode,
2939 gen_rtx_HIGH (Pmode, XEXP (x, 0)),
2941 return &XEXP (XEXP (x, 0), 0);
2945 /* If we have a PLUS whose second operand is a constant and the
2946 address is not valid, perhaps will can split it up using
2947 the machine-specific way to split large constants. We use
2948 the first pseudo-reg (one of the virtual regs) as a placeholder;
2949 it will not remain in the result. */
2950 if (GET_CODE (XEXP (x, 0)) == PLUS
2951 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2952 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
2954 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
2955 rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
2958 /* This should have produced two insns, each of which sets our
2959 placeholder. If the source of the second is a valid address,
2960 we can make put both sources together and make a split point
2963 if (seq && XVECLEN (seq, 0) == 2
2964 && GET_CODE (XVECEXP (seq, 0, 0)) == INSN
2965 && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) == SET
2966 && SET_DEST (PATTERN (XVECEXP (seq, 0, 0))) == reg
2967 && ! reg_mentioned_p (reg,
2968 SET_SRC (PATTERN (XVECEXP (seq, 0, 0))))
2969 && GET_CODE (XVECEXP (seq, 0, 1)) == INSN
2970 && GET_CODE (PATTERN (XVECEXP (seq, 0, 1))) == SET
2971 && SET_DEST (PATTERN (XVECEXP (seq, 0, 1))) == reg
2972 && memory_address_p (GET_MODE (x),
2973 SET_SRC (PATTERN (XVECEXP (seq, 0, 1)))))
2975 rtx src1 = SET_SRC (PATTERN (XVECEXP (seq, 0, 0)));
2976 rtx src2 = SET_SRC (PATTERN (XVECEXP (seq, 0, 1)));
2978 /* Replace the placeholder in SRC2 with SRC1. If we can
2979 find where in SRC2 it was placed, that can become our
2980 split point and we can replace this address with SRC2.
2981 Just try two obvious places. */
2983 src2 = replace_rtx (src2, reg, src1);
2985 if (XEXP (src2, 0) == src1)
2986 split = &XEXP (src2, 0);
2987 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
2988 && XEXP (XEXP (src2, 0), 0) == src1)
2989 split = &XEXP (XEXP (src2, 0), 0);
2993 SUBST (XEXP (x, 0), src2);
2998 /* If that didn't work, perhaps the first operand is complex and
2999 needs to be computed separately, so make a split point there.
3000 This will occur on machines that just support REG + CONST
3001 and have a constant moved through some previous computation. */
3003 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o'
3004 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
3005 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0))))
3007 return &XEXP (XEXP (x, 0), 0);
3013 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
3014 ZERO_EXTRACT, the most likely reason why this doesn't match is that
3015 we need to put the operand into a register. So split at that
3018 if (SET_DEST (x) == cc0_rtx
3019 && GET_CODE (SET_SRC (x)) != COMPARE
3020 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
3021 && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
3022 && ! (GET_CODE (SET_SRC (x)) == SUBREG
3023 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
3024 return &SET_SRC (x);
3027 /* See if we can split SET_SRC as it stands. */
3028 split = find_split_point (&SET_SRC (x), insn);
3029 if (split && split != &SET_SRC (x))
3032 /* See if we can split SET_DEST as it stands. */
3033 split = find_split_point (&SET_DEST (x), insn);
3034 if (split && split != &SET_DEST (x))
3037 /* See if this is a bitfield assignment with everything constant. If
3038 so, this is an IOR of an AND, so split it into that. */
3039 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
3040 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
3041 <= HOST_BITS_PER_WIDE_INT)
3042 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
3043 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
3044 && GET_CODE (SET_SRC (x)) == CONST_INT
3045 && ((INTVAL (XEXP (SET_DEST (x), 1))
3046 + INTVAL (XEXP (SET_DEST (x), 2)))
3047 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
3048 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
3050 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
3051 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
3052 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
3053 rtx dest = XEXP (SET_DEST (x), 0);
3054 enum machine_mode mode = GET_MODE (dest);
3055 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
3057 if (BITS_BIG_ENDIAN)
3058 pos = GET_MODE_BITSIZE (mode) - len - pos;
3062 gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
3065 gen_binary (IOR, mode,
3066 gen_binary (AND, mode, dest,
3067 GEN_INT (~(mask << pos)
3068 & GET_MODE_MASK (mode))),
3069 GEN_INT (src << pos)));
3071 SUBST (SET_DEST (x), dest);
3073 split = find_split_point (&SET_SRC (x), insn);
3074 if (split && split != &SET_SRC (x))
3078 /* Otherwise, see if this is an operation that we can split into two.
3079 If so, try to split that. */
3080 code = GET_CODE (SET_SRC (x));
3085 /* If we are AND'ing with a large constant that is only a single
3086 bit and the result is only being used in a context where we
3087 need to know if it is zero or non-zero, replace it with a bit
3088 extraction. This will avoid the large constant, which might
3089 have taken more than one insn to make. If the constant were
3090 not a valid argument to the AND but took only one insn to make,
3091 this is no worse, but if it took more than one insn, it will
3094 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3095 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
3096 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
3097 && GET_CODE (SET_DEST (x)) == REG
3098 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
3099 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
3100 && XEXP (*split, 0) == SET_DEST (x)
3101 && XEXP (*split, 1) == const0_rtx)
3103 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
3104 XEXP (SET_SRC (x), 0),
3105 pos, NULL_RTX, 1, 1, 0, 0);
3106 if (extraction != 0)
3108 SUBST (SET_SRC (x), extraction);
3109 return find_split_point (loc, insn);
3115 /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3116 is known to be on, this can be converted into a NEG of a shift. */
3117 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
3118 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
3119 && 1 <= (pos = exact_log2
3120 (nonzero_bits (XEXP (SET_SRC (x), 0),
3121 GET_MODE (XEXP (SET_SRC (x), 0))))))
3123 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
3127 gen_rtx_LSHIFTRT (mode,
3128 XEXP (SET_SRC (x), 0),
3131 split = find_split_point (&SET_SRC (x), insn);
3132 if (split && split != &SET_SRC (x))
3138 inner = XEXP (SET_SRC (x), 0);
3140 /* We can't optimize if either mode is a partial integer
3141 mode as we don't know how many bits are significant
3143 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
3144 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
3148 len = GET_MODE_BITSIZE (GET_MODE (inner));
3154 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3155 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
3157 inner = XEXP (SET_SRC (x), 0);
3158 len = INTVAL (XEXP (SET_SRC (x), 1));
3159 pos = INTVAL (XEXP (SET_SRC (x), 2));
3161 if (BITS_BIG_ENDIAN)
3162 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
3163 unsignedp = (code == ZERO_EXTRACT);
3171 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
3173 enum machine_mode mode = GET_MODE (SET_SRC (x));
3175 /* For unsigned, we have a choice of a shift followed by an
3176 AND or two shifts. Use two shifts for field sizes where the
3177 constant might be too large. We assume here that we can
3178 always at least get 8-bit constants in an AND insn, which is
3179 true for every current RISC. */
3181 if (unsignedp && len <= 8)
3186 (mode, gen_lowpart_for_combine (mode, inner),
3188 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
3190 split = find_split_point (&SET_SRC (x), insn);
3191 if (split && split != &SET_SRC (x))
3198 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
3199 gen_rtx_ASHIFT (mode,
3200 gen_lowpart_for_combine (mode, inner),
3201 GEN_INT (GET_MODE_BITSIZE (mode)
3203 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
3205 split = find_split_point (&SET_SRC (x), insn);
3206 if (split && split != &SET_SRC (x))
3211 /* See if this is a simple operation with a constant as the second
3212 operand. It might be that this constant is out of range and hence
3213 could be used as a split point. */
3214 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3215 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3216 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
3217 && CONSTANT_P (XEXP (SET_SRC (x), 1))
3218 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
3219 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
3220 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
3222 return &XEXP (SET_SRC (x), 1);
3224 /* Finally, see if this is a simple operation with its first operand
3225 not in a register. The operation might require this operand in a
3226 register, so return it as a split point. We can always do this
3227 because if the first operand were another operation, we would have
3228 already found it as a split point. */
3229 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3230 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3231 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
3232 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
3233 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
3234 return &XEXP (SET_SRC (x), 0);
3240 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3241 it is better to write this as (not (ior A B)) so we can split it.
3242 Similarly for IOR. */
3243 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
3246 gen_rtx_NOT (GET_MODE (x),
3247 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
3249 XEXP (XEXP (x, 0), 0),
3250 XEXP (XEXP (x, 1), 0))));
3251 return find_split_point (loc, insn);
3254 /* Many RISC machines have a large set of logical insns. If the
3255 second operand is a NOT, put it first so we will try to split the
3256 other operand first. */
3257 if (GET_CODE (XEXP (x, 1)) == NOT)
3259 rtx tem = XEXP (x, 0);
3260 SUBST (XEXP (x, 0), XEXP (x, 1));
3261 SUBST (XEXP (x, 1), tem);
3269 /* Otherwise, select our actions depending on our rtx class. */
3270 switch (GET_RTX_CLASS (code))
3272 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3274 split = find_split_point (&XEXP (x, 2), insn);
3277 /* ... fall through ... */
3281 split = find_split_point (&XEXP (x, 1), insn);
3284 /* ... fall through ... */
3286 /* Some machines have (and (shift ...) ...) insns. If X is not
3287 an AND, but XEXP (X, 0) is, use it as our split point. */
3288 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
3289 return &XEXP (x, 0);
3291 split = find_split_point (&XEXP (x, 0), insn);
3297 /* Otherwise, we don't have a split point. */
3301 /* Throughout X, replace FROM with TO, and return the result.
3302 The result is TO if X is FROM;
3303 otherwise the result is X, but its contents may have been modified.
3304 If they were modified, a record was made in undobuf so that
3305 undo_all will (among other things) return X to its original state.
3307 If the number of changes necessary is too much to record to undo,
3308 the excess changes are not made, so the result is invalid.
3309 The changes already made can still be undone.
3310 undobuf.num_undo is incremented for such changes, so by testing that
3311 the caller can tell whether the result is valid.
3313 `n_occurrences' is incremented each time FROM is replaced.
3315 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
3317 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
3318 by copying if `n_occurrences' is non-zero. */
3321 subst (x, from, to, in_dest, unique_copy)
3326 enum rtx_code code = GET_CODE (x);
3327 enum machine_mode op0_mode = VOIDmode;
3332 /* Two expressions are equal if they are identical copies of a shared
3333 RTX or if they are both registers with the same register number
3336 #define COMBINE_RTX_EQUAL_P(X,Y) \
3338 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3339 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3341 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3344 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3347 /* If X and FROM are the same register but different modes, they will
3348 not have been seen as equal above. However, flow.c will make a
3349 LOG_LINKS entry for that case. If we do nothing, we will try to
3350 rerecognize our original insn and, when it succeeds, we will
3351 delete the feeding insn, which is incorrect.
3353 So force this insn not to match in this (rare) case. */
3354 if (! in_dest && code == REG && GET_CODE (from) == REG
3355 && REGNO (x) == REGNO (from))
3356 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
3358 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3359 of which may contain things that can be combined. */
3360 if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
3363 /* It is possible to have a subexpression appear twice in the insn.
3364 Suppose that FROM is a register that appears within TO.
3365 Then, after that subexpression has been scanned once by `subst',
3366 the second time it is scanned, TO may be found. If we were
3367 to scan TO here, we would find FROM within it and create a
3368 self-referent rtl structure which is completely wrong. */
3369 if (COMBINE_RTX_EQUAL_P (x, to))
3372 /* Parallel asm_operands need special attention because all of the
3373 inputs are shared across the arms. Furthermore, unsharing the
3374 rtl results in recognition failures. Failure to handle this case
3375 specially can result in circular rtl.
3377 Solve this by doing a normal pass across the first entry of the
3378 parallel, and only processing the SET_DESTs of the subsequent
3381 if (code == PARALLEL
3382 && GET_CODE (XVECEXP (x, 0, 0)) == SET
3383 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
3385 new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3387 /* If this substitution failed, this whole thing fails. */
3388 if (GET_CODE (new) == CLOBBER
3389 && XEXP (new, 0) == const0_rtx)
3392 SUBST (XVECEXP (x, 0, 0), new);
3394 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
3396 rtx dest = SET_DEST (XVECEXP (x, 0, i));
3398 if (GET_CODE (dest) != REG
3399 && GET_CODE (dest) != CC0
3400 && GET_CODE (dest) != PC)
3402 new = subst (dest, from, to, 0, unique_copy);
3404 /* If this substitution failed, this whole thing fails. */
3405 if (GET_CODE (new) == CLOBBER
3406 && XEXP (new, 0) == const0_rtx)
3409 SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
3415 len = GET_RTX_LENGTH (code);
3416 fmt = GET_RTX_FORMAT (code);
3418 /* We don't need to process a SET_DEST that is a register, CC0,
3419 or PC, so set up to skip this common case. All other cases
3420 where we want to suppress replacing something inside a
3421 SET_SRC are handled via the IN_DEST operand. */
3423 && (GET_CODE (SET_DEST (x)) == REG
3424 || GET_CODE (SET_DEST (x)) == CC0
3425 || GET_CODE (SET_DEST (x)) == PC))
3428 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3431 op0_mode = GET_MODE (XEXP (x, 0));
3433 for (i = 0; i < len; i++)
3438 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3440 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3442 new = (unique_copy && n_occurrences
3443 ? copy_rtx (to) : to);
3448 new = subst (XVECEXP (x, i, j), from, to, 0,
3451 /* If this substitution failed, this whole thing
3453 if (GET_CODE (new) == CLOBBER
3454 && XEXP (new, 0) == const0_rtx)
3458 SUBST (XVECEXP (x, i, j), new);
3461 else if (fmt[i] == 'e')
3463 /* If this is a register being set, ignore it. */
3466 && (code == SUBREG || code == STRICT_LOW_PART
3467 || code == ZERO_EXTRACT)
3469 && GET_CODE (new) == REG)
3472 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
3474 /* In general, don't install a subreg involving two
3475 modes not tieable. It can worsen register
3476 allocation, and can even make invalid reload
3477 insns, since the reg inside may need to be copied
3478 from in the outside mode, and that may be invalid
3479 if it is an fp reg copied in integer mode.
3481 We allow two exceptions to this: It is valid if
3482 it is inside another SUBREG and the mode of that
3483 SUBREG and the mode of the inside of TO is
3484 tieable and it is valid if X is a SET that copies
3487 if (GET_CODE (to) == SUBREG
3488 && ! MODES_TIEABLE_P (GET_MODE (to),
3489 GET_MODE (SUBREG_REG (to)))
3490 && ! (code == SUBREG
3491 && MODES_TIEABLE_P (GET_MODE (x),
3492 GET_MODE (SUBREG_REG (to))))
3494 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
3497 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3499 #ifdef CLASS_CANNOT_CHANGE_MODE
3501 && GET_CODE (to) == REG
3502 && REGNO (to) < FIRST_PSEUDO_REGISTER
3503 && (TEST_HARD_REG_BIT
3504 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE],
3506 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (to),
3508 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3511 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3515 /* If we are in a SET_DEST, suppress most cases unless we
3516 have gone inside a MEM, in which case we want to
3517 simplify the address. We assume here that things that
3518 are actually part of the destination have their inner
3519 parts in the first expression. This is true for SUBREG,
3520 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3521 things aside from REG and MEM that should appear in a
3523 new = subst (XEXP (x, i), from, to,
3525 && (code == SUBREG || code == STRICT_LOW_PART
3526 || code == ZERO_EXTRACT))
3528 && i == 0), unique_copy);
3530 /* If we found that we will have to reject this combination,
3531 indicate that by returning the CLOBBER ourselves, rather than
3532 an expression containing it. This will speed things up as
3533 well as prevent accidents where two CLOBBERs are considered
3534 to be equal, thus producing an incorrect simplification. */
3536 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3539 if (GET_CODE (new) == CONST_INT && GET_CODE (x) == SUBREG)
3541 x = simplify_subreg (GET_MODE (x), new,
3542 GET_MODE (SUBREG_REG (x)),
3547 else if (GET_CODE (new) == CONST_INT
3548 && GET_CODE (x) == ZERO_EXTEND)
3550 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
3551 new, GET_MODE (XEXP (x, 0)));
3556 SUBST (XEXP (x, i), new);
3561 /* Try to simplify X. If the simplification changed the code, it is likely
3562 that further simplification will help, so loop, but limit the number
3563 of repetitions that will be performed. */
3565 for (i = 0; i < 4; i++)
3567 /* If X is sufficiently simple, don't bother trying to do anything
3569 if (code != CONST_INT && code != REG && code != CLOBBER)
3570 x = combine_simplify_rtx (x, op0_mode, i == 3, in_dest);
3572 if (GET_CODE (x) == code)
3575 code = GET_CODE (x);
3577 /* We no longer know the original mode of operand 0 since we
3578 have changed the form of X) */
3579 op0_mode = VOIDmode;
3585 /* Simplify X, a piece of RTL. We just operate on the expression at the
3586 outer level; call `subst' to simplify recursively. Return the new
3589 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3590 will be the iteration even if an expression with a code different from
3591 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3594 combine_simplify_rtx (x, op0_mode, last, in_dest)
3596 enum machine_mode op0_mode;
3600 enum rtx_code code = GET_CODE (x);
3601 enum machine_mode mode = GET_MODE (x);
3606 /* If this is a commutative operation, put a constant last and a complex
3607 expression first. We don't need to do this for comparisons here. */
3608 if (GET_RTX_CLASS (code) == 'c'
3609 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
3612 SUBST (XEXP (x, 0), XEXP (x, 1));
3613 SUBST (XEXP (x, 1), temp);
3616 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3617 sign extension of a PLUS with a constant, reverse the order of the sign
3618 extension and the addition. Note that this not the same as the original
3619 code, but overflow is undefined for signed values. Also note that the
3620 PLUS will have been partially moved "inside" the sign-extension, so that
3621 the first operand of X will really look like:
3622 (ashiftrt (plus (ashift A C4) C5) C4).
3624 (plus (ashiftrt (ashift A C4) C2) C4)
3625 and replace the first operand of X with that expression. Later parts
3626 of this function may simplify the expression further.
3628 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3629 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3630 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3632 We do this to simplify address expressions. */
3634 if ((code == PLUS || code == MINUS || code == MULT)
3635 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3636 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
3637 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
3638 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
3639 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3640 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
3641 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3642 && (temp = simplify_binary_operation (ASHIFTRT, mode,
3643 XEXP (XEXP (XEXP (x, 0), 0), 1),
3644 XEXP (XEXP (x, 0), 1))) != 0)
3647 = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3648 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
3649 INTVAL (XEXP (XEXP (x, 0), 1)));
3651 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
3652 INTVAL (XEXP (XEXP (x, 0), 1)));
3654 SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
3657 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3658 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3659 things. Check for cases where both arms are testing the same
3662 Don't do anything if all operands are very simple. */
3664 if (((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c'
3665 || GET_RTX_CLASS (code) == '<')
3666 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3667 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3668 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3670 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o'
3671 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3672 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 1))))
3674 || (GET_RTX_CLASS (code) == '1'
3675 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3676 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3677 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3680 rtx cond, true_rtx, false_rtx;
3682 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
3684 /* If everything is a comparison, what we have is highly unlikely
3685 to be simpler, so don't use it. */
3686 && ! (GET_RTX_CLASS (code) == '<'
3687 && (GET_RTX_CLASS (GET_CODE (true_rtx)) == '<'
3688 || GET_RTX_CLASS (GET_CODE (false_rtx)) == '<')))
3690 rtx cop1 = const0_rtx;
3691 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3693 if (cond_code == NE && GET_RTX_CLASS (GET_CODE (cond)) == '<')
3696 /* Simplify the alternative arms; this may collapse the true and
3697 false arms to store-flag values. */
3698 true_rtx = subst (true_rtx, pc_rtx, pc_rtx, 0, 0);
3699 false_rtx = subst (false_rtx, pc_rtx, pc_rtx, 0, 0);
3701 /* If true_rtx and false_rtx are not general_operands, an if_then_else
3702 is unlikely to be simpler. */
3703 if (general_operand (true_rtx, VOIDmode)
3704 && general_operand (false_rtx, VOIDmode))
3706 /* Restarting if we generate a store-flag expression will cause
3707 us to loop. Just drop through in this case. */
3709 /* If the result values are STORE_FLAG_VALUE and zero, we can
3710 just make the comparison operation. */
3711 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
3712 x = gen_binary (cond_code, mode, cond, cop1);
3713 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
3714 && reverse_condition (cond_code) != UNKNOWN)
3715 x = gen_binary (reverse_condition (cond_code),
3718 /* Likewise, we can make the negate of a comparison operation
3719 if the result values are - STORE_FLAG_VALUE and zero. */
3720 else if (GET_CODE (true_rtx) == CONST_INT
3721 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
3722 && false_rtx == const0_rtx)
3723 x = simplify_gen_unary (NEG, mode,
3724 gen_binary (cond_code, mode, cond,
3727 else if (GET_CODE (false_rtx) == CONST_INT
3728 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
3729 && true_rtx == const0_rtx)
3730 x = simplify_gen_unary (NEG, mode,
3731 gen_binary (reverse_condition
3736 return gen_rtx_IF_THEN_ELSE (mode,
3737 gen_binary (cond_code, VOIDmode,
3739 true_rtx, false_rtx);
3741 code = GET_CODE (x);
3742 op0_mode = VOIDmode;
3747 /* Try to fold this expression in case we have constants that weren't
3750 switch (GET_RTX_CLASS (code))
3753 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
3757 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
3758 if (cmp_mode == VOIDmode)
3760 cmp_mode = GET_MODE (XEXP (x, 1));
3761 if (cmp_mode == VOIDmode)
3762 cmp_mode = op0_mode;
3764 temp = simplify_relational_operation (code, cmp_mode,
3765 XEXP (x, 0), XEXP (x, 1));
3767 #ifdef FLOAT_STORE_FLAG_VALUE
3768 if (temp != 0 && GET_MODE_CLASS (mode) == MODE_FLOAT)
3770 if (temp == const0_rtx)
3771 temp = CONST0_RTX (mode);
3773 temp = immed_real_const_1 (FLOAT_STORE_FLAG_VALUE (mode), mode);
3779 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3783 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
3784 XEXP (x, 1), XEXP (x, 2));
3791 code = GET_CODE (temp);
3792 op0_mode = VOIDmode;
3793 mode = GET_MODE (temp);
3796 /* First see if we can apply the inverse distributive law. */
3797 if (code == PLUS || code == MINUS
3798 || code == AND || code == IOR || code == XOR)
3800 x = apply_distributive_law (x);
3801 code = GET_CODE (x);
3802 op0_mode = VOIDmode;
3805 /* If CODE is an associative operation not otherwise handled, see if we
3806 can associate some operands. This can win if they are constants or
3807 if they are logically related (i.e. (a & b) & a). */
3808 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
3809 || code == AND || code == IOR || code == XOR
3810 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
3811 && ((INTEGRAL_MODE_P (mode) && code != DIV)
3812 || (flag_unsafe_math_optimizations && FLOAT_MODE_P (mode))))
3814 if (GET_CODE (XEXP (x, 0)) == code)
3816 rtx other = XEXP (XEXP (x, 0), 0);
3817 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
3818 rtx inner_op1 = XEXP (x, 1);
3821 /* Make sure we pass the constant operand if any as the second
3822 one if this is a commutative operation. */
3823 if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
3825 rtx tem = inner_op0;
3826 inner_op0 = inner_op1;
3829 inner = simplify_binary_operation (code == MINUS ? PLUS
3830 : code == DIV ? MULT
3832 mode, inner_op0, inner_op1);
3834 /* For commutative operations, try the other pair if that one
3836 if (inner == 0 && GET_RTX_CLASS (code) == 'c')
3838 other = XEXP (XEXP (x, 0), 1);
3839 inner = simplify_binary_operation (code, mode,
3840 XEXP (XEXP (x, 0), 0),
3845 return gen_binary (code, mode, other, inner);
3849 /* A little bit of algebraic simplification here. */
3853 /* Ensure that our address has any ASHIFTs converted to MULT in case
3854 address-recognizing predicates are called later. */
3855 temp = make_compound_operation (XEXP (x, 0), MEM);
3856 SUBST (XEXP (x, 0), temp);
3860 if (op0_mode == VOIDmode)
3861 op0_mode = GET_MODE (SUBREG_REG (x));
3863 /* simplify_subreg can't use gen_lowpart_for_combine. */
3864 if (CONSTANT_P (SUBREG_REG (x))
3865 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x))
3866 return gen_lowpart_for_combine (mode, SUBREG_REG (x));
3868 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
3872 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
3878 /* Don't change the mode of the MEM if that would change the meaning
3880 if (GET_CODE (SUBREG_REG (x)) == MEM
3881 && (MEM_VOLATILE_P (SUBREG_REG (x))
3882 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
3883 return gen_rtx_CLOBBER (mode, const0_rtx);
3885 /* Note that we cannot do any narrowing for non-constants since
3886 we might have been counting on using the fact that some bits were
3887 zero. We now do this in the SET. */
3892 /* (not (plus X -1)) can become (neg X). */
3893 if (GET_CODE (XEXP (x, 0)) == PLUS
3894 && XEXP (XEXP (x, 0), 1) == constm1_rtx)
3895 return gen_rtx_NEG (mode, XEXP (XEXP (x, 0), 0));
3897 /* Similarly, (not (neg X)) is (plus X -1). */
3898 if (GET_CODE (XEXP (x, 0)) == NEG)
3899 return gen_rtx_PLUS (mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3901 /* (not (xor X C)) for C constant is (xor X D) with D = ~C. */
3902 if (GET_CODE (XEXP (x, 0)) == XOR
3903 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3904 && (temp = simplify_unary_operation (NOT, mode,
3905 XEXP (XEXP (x, 0), 1),
3907 return gen_binary (XOR, mode, XEXP (XEXP (x, 0), 0), temp);
3909 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3910 other than 1, but that is not valid. We could do a similar
3911 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3912 but this doesn't seem common enough to bother with. */
3913 if (GET_CODE (XEXP (x, 0)) == ASHIFT
3914 && XEXP (XEXP (x, 0), 0) == const1_rtx)
3915 return gen_rtx_ROTATE (mode, simplify_gen_unary (NOT, mode,
3917 XEXP (XEXP (x, 0), 1));
3919 if (GET_CODE (XEXP (x, 0)) == SUBREG
3920 && subreg_lowpart_p (XEXP (x, 0))
3921 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3922 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
3923 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
3924 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3926 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3928 x = gen_rtx_ROTATE (inner_mode,
3929 simplify_gen_unary (NOT, inner_mode, const1_rtx,
3931 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
3932 return gen_lowpart_for_combine (mode, x);
3935 /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
3936 reversing the comparison code if valid. */
3937 if (STORE_FLAG_VALUE == -1
3938 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3939 && (reversed = reversed_comparison (x, mode, XEXP (XEXP (x, 0), 0),
3940 XEXP (XEXP (x, 0), 1))))
3943 /* (not (ashiftrt foo C)) where C is the number of bits in FOO minus 1
3944 is (ge foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
3945 perform the above simplification. */
3947 if (STORE_FLAG_VALUE == -1
3948 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3949 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3950 && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
3951 return gen_rtx_GE (mode, XEXP (XEXP (x, 0), 0), const0_rtx);
3953 /* Apply De Morgan's laws to reduce number of patterns for machines
3954 with negating logical insns (and-not, nand, etc.). If result has
3955 only one NOT, put it first, since that is how the patterns are
3958 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
3960 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
3961 enum machine_mode op_mode;
3963 op_mode = GET_MODE (in1);
3964 in1 = simplify_gen_unary (NOT, op_mode, in1, op_mode);
3966 op_mode = GET_MODE (in2);
3967 if (op_mode == VOIDmode)
3969 in2 = simplify_gen_unary (NOT, op_mode, in2, op_mode);
3971 if (GET_CODE (in2) == NOT && GET_CODE (in1) != NOT)
3974 in2 = in1; in1 = tem;
3977 return gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
3983 /* (neg (plus X 1)) can become (not X). */
3984 if (GET_CODE (XEXP (x, 0)) == PLUS
3985 && XEXP (XEXP (x, 0), 1) == const1_rtx)
3986 return gen_rtx_NOT (mode, XEXP (XEXP (x, 0), 0));
3988 /* Similarly, (neg (not X)) is (plus X 1). */
3989 if (GET_CODE (XEXP (x, 0)) == NOT)
3990 return plus_constant (XEXP (XEXP (x, 0), 0), 1);
3992 /* (neg (minus X Y)) can become (minus Y X). This transformation
3993 isn't safe for modes with signed zeros, since if X and Y are
3994 both +0, (minus Y X) is the same as (minus X Y). If the rounding
3995 mode is towards +infinity (or -infinity) then the two expressions
3996 will be rounded differently. */
3997 if (GET_CODE (XEXP (x, 0)) == MINUS
3998 && !HONOR_SIGNED_ZEROS (mode)
3999 && !HONOR_SIGN_DEPENDENT_ROUNDING (mode))
4000 return gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
4001 XEXP (XEXP (x, 0), 0));
4003 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
4004 if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx
4005 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
4006 return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
4008 /* NEG commutes with ASHIFT since it is multiplication. Only do this
4009 if we can then eliminate the NEG (e.g.,
4010 if the operand is a constant). */
4012 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
4014 temp = simplify_unary_operation (NEG, mode,
4015 XEXP (XEXP (x, 0), 0), mode);
4017 return gen_binary (ASHIFT, mode, temp, XEXP (XEXP (x, 0), 1));
4020 temp = expand_compound_operation (XEXP (x, 0));
4022 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4023 replaced by (lshiftrt X C). This will convert
4024 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
4026 if (GET_CODE (temp) == ASHIFTRT
4027 && GET_CODE (XEXP (temp, 1)) == CONST_INT
4028 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
4029 return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
4030 INTVAL (XEXP (temp, 1)));
4032 /* If X has only a single bit that might be nonzero, say, bit I, convert
4033 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4034 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4035 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4036 or a SUBREG of one since we'd be making the expression more
4037 complex if it was just a register. */
4039 if (GET_CODE (temp) != REG
4040 && ! (GET_CODE (temp) == SUBREG
4041 && GET_CODE (SUBREG_REG (temp)) == REG)
4042 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
4044 rtx temp1 = simplify_shift_const
4045 (NULL_RTX, ASHIFTRT, mode,
4046 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
4047 GET_MODE_BITSIZE (mode) - 1 - i),
4048 GET_MODE_BITSIZE (mode) - 1 - i);
4050 /* If all we did was surround TEMP with the two shifts, we
4051 haven't improved anything, so don't use it. Otherwise,
4052 we are better off with TEMP1. */
4053 if (GET_CODE (temp1) != ASHIFTRT
4054 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
4055 || XEXP (XEXP (temp1, 0), 0) != temp)
4061 /* We can't handle truncation to a partial integer mode here
4062 because we don't know the real bitsize of the partial
4064 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
4067 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4068 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4069 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4071 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
4072 GET_MODE_MASK (mode), NULL_RTX, 0));
4074 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
4075 if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4076 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4077 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4078 return XEXP (XEXP (x, 0), 0);
4080 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
4081 (OP:SI foo:SI) if OP is NEG or ABS. */
4082 if ((GET_CODE (XEXP (x, 0)) == ABS
4083 || GET_CODE (XEXP (x, 0)) == NEG)
4084 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
4085 || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
4086 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4087 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4088 XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
4090 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
4092 if (GET_CODE (XEXP (x, 0)) == SUBREG
4093 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE
4094 && subreg_lowpart_p (XEXP (x, 0)))
4095 return SUBREG_REG (XEXP (x, 0));
4097 /* If we know that the value is already truncated, we can
4098 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
4099 is nonzero for the corresponding modes. But don't do this
4100 for an (LSHIFTRT (MULT ...)) since this will cause problems
4101 with the umulXi3_highpart patterns. */
4102 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4103 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
4104 && num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4105 >= GET_MODE_BITSIZE (mode) + 1
4106 && ! (GET_CODE (XEXP (x, 0)) == LSHIFTRT
4107 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT))
4108 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4110 /* A truncate of a comparison can be replaced with a subreg if
4111 STORE_FLAG_VALUE permits. This is like the previous test,
4112 but it works even if the comparison is done in a mode larger
4113 than HOST_BITS_PER_WIDE_INT. */
4114 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4115 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4116 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0)
4117 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4119 /* Similarly, a truncate of a register whose value is a
4120 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4122 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4123 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
4124 && (temp = get_last_value (XEXP (x, 0)))
4125 && GET_RTX_CLASS (GET_CODE (temp)) == '<')
4126 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4130 case FLOAT_TRUNCATE:
4131 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4132 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
4133 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4134 return XEXP (XEXP (x, 0), 0);
4136 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4137 (OP:SF foo:SF) if OP is NEG or ABS. */
4138 if ((GET_CODE (XEXP (x, 0)) == ABS
4139 || GET_CODE (XEXP (x, 0)) == NEG)
4140 && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
4141 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4142 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4143 XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
4145 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4146 is (float_truncate:SF x). */
4147 if (GET_CODE (XEXP (x, 0)) == SUBREG
4148 && subreg_lowpart_p (XEXP (x, 0))
4149 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
4150 return SUBREG_REG (XEXP (x, 0));
4155 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4156 using cc0, in which case we want to leave it as a COMPARE
4157 so we can distinguish it from a register-register-copy. */
4158 if (XEXP (x, 1) == const0_rtx)
4161 /* x - 0 is the same as x unless x's mode has signed zeros and
4162 allows rounding towards -infinity. Under those conditions,
4164 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x, 0)))
4165 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x, 0))))
4166 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4172 /* (const (const X)) can become (const X). Do it this way rather than
4173 returning the inner CONST since CONST can be shared with a
4175 if (GET_CODE (XEXP (x, 0)) == CONST)
4176 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4181 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4182 can add in an offset. find_split_point will split this address up
4183 again if it doesn't match. */
4184 if (GET_CODE (XEXP (x, 0)) == HIGH
4185 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4191 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4192 outermost. That's because that's the way indexed addresses are
4193 supposed to appear. This code used to check many more cases, but
4194 they are now checked elsewhere. */
4195 if (GET_CODE (XEXP (x, 0)) == PLUS
4196 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
4197 return gen_binary (PLUS, mode,
4198 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
4200 XEXP (XEXP (x, 0), 1));
4202 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4203 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4204 bit-field and can be replaced by either a sign_extend or a
4205 sign_extract. The `and' may be a zero_extend and the two
4206 <c>, -<c> constants may be reversed. */
4207 if (GET_CODE (XEXP (x, 0)) == XOR
4208 && GET_CODE (XEXP (x, 1)) == CONST_INT
4209 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4210 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
4211 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4212 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4213 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4214 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4215 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4216 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4217 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4218 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4219 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4220 == (unsigned int) i + 1))))
4221 return simplify_shift_const
4222 (NULL_RTX, ASHIFTRT, mode,
4223 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4224 XEXP (XEXP (XEXP (x, 0), 0), 0),
4225 GET_MODE_BITSIZE (mode) - (i + 1)),
4226 GET_MODE_BITSIZE (mode) - (i + 1));
4228 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4229 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4230 is 1. This produces better code than the alternative immediately
4232 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4233 && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
4234 || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx))
4235 && (reversed = reversed_comparison (XEXP (x, 0), mode,
4236 XEXP (XEXP (x, 0), 0),
4237 XEXP (XEXP (x, 0), 1))))
4239 simplify_gen_unary (NEG, mode, reversed, mode);
4241 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4242 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4243 the bitsize of the mode - 1. This allows simplification of
4244 "a = (b & 8) == 0;" */
4245 if (XEXP (x, 1) == constm1_rtx
4246 && GET_CODE (XEXP (x, 0)) != REG
4247 && ! (GET_CODE (XEXP (x,0)) == SUBREG
4248 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
4249 && nonzero_bits (XEXP (x, 0), mode) == 1)
4250 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4251 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4252 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
4253 GET_MODE_BITSIZE (mode) - 1),
4254 GET_MODE_BITSIZE (mode) - 1);
4256 /* If we are adding two things that have no bits in common, convert
4257 the addition into an IOR. This will often be further simplified,
4258 for example in cases like ((a & 1) + (a & 2)), which can
4261 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4262 && (nonzero_bits (XEXP (x, 0), mode)
4263 & nonzero_bits (XEXP (x, 1), mode)) == 0)
4265 /* Try to simplify the expression further. */
4266 rtx tor = gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4267 temp = combine_simplify_rtx (tor, mode, last, in_dest);
4269 /* If we could, great. If not, do not go ahead with the IOR
4270 replacement, since PLUS appears in many special purpose
4271 address arithmetic instructions. */
4272 if (GET_CODE (temp) != CLOBBER && temp != tor)
4278 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4279 by reversing the comparison code if valid. */
4280 if (STORE_FLAG_VALUE == 1
4281 && XEXP (x, 0) == const1_rtx
4282 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<'
4283 && (reversed = reversed_comparison (XEXP (x, 1), mode,
4284 XEXP (XEXP (x, 1), 0),
4285 XEXP (XEXP (x, 1), 1))))
4288 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4289 (and <foo> (const_int pow2-1)) */
4290 if (GET_CODE (XEXP (x, 1)) == AND
4291 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4292 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4293 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4294 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4295 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4297 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4299 if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
4300 return gen_binary (MINUS, mode,
4301 gen_binary (MINUS, mode, XEXP (x, 0),
4302 XEXP (XEXP (x, 1), 0)),
4303 XEXP (XEXP (x, 1), 1));
4307 /* If we have (mult (plus A B) C), apply the distributive law and then
4308 the inverse distributive law to see if things simplify. This
4309 occurs mostly in addresses, often when unrolling loops. */
4311 if (GET_CODE (XEXP (x, 0)) == PLUS)
4313 x = apply_distributive_law
4314 (gen_binary (PLUS, mode,
4315 gen_binary (MULT, mode,
4316 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
4317 gen_binary (MULT, mode,
4318 XEXP (XEXP (x, 0), 1),
4319 copy_rtx (XEXP (x, 1)))));
4321 if (GET_CODE (x) != MULT)
4324 /* Try simplify a*(b/c) as (a*b)/c. */
4325 if (FLOAT_MODE_P (mode) && flag_unsafe_math_optimizations
4326 && GET_CODE (XEXP (x, 0)) == DIV)
4328 rtx tem = simplify_binary_operation (MULT, mode,
4329 XEXP (XEXP (x, 0), 0),
4332 return gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
4337 /* If this is a divide by a power of two, treat it as a shift if
4338 its first operand is a shift. */
4339 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4340 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4341 && (GET_CODE (XEXP (x, 0)) == ASHIFT
4342 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4343 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4344 || GET_CODE (XEXP (x, 0)) == ROTATE
4345 || GET_CODE (XEXP (x, 0)) == ROTATERT))
4346 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
4350 case GT: case GTU: case GE: case GEU:
4351 case LT: case LTU: case LE: case LEU:
4352 case UNEQ: case LTGT:
4353 case UNGT: case UNGE:
4354 case UNLT: case UNLE:
4355 case UNORDERED: case ORDERED:
4356 /* If the first operand is a condition code, we can't do anything
4358 if (GET_CODE (XEXP (x, 0)) == COMPARE
4359 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4361 && XEXP (x, 0) != cc0_rtx
4365 rtx op0 = XEXP (x, 0);
4366 rtx op1 = XEXP (x, 1);
4367 enum rtx_code new_code;
4369 if (GET_CODE (op0) == COMPARE)
4370 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4372 /* Simplify our comparison, if possible. */
4373 new_code = simplify_comparison (code, &op0, &op1);
4375 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4376 if only the low-order bit is possibly nonzero in X (such as when
4377 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4378 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4379 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4382 Remove any ZERO_EXTRACT we made when thinking this was a
4383 comparison. It may now be simpler to use, e.g., an AND. If a
4384 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4385 the call to make_compound_operation in the SET case. */
4387 if (STORE_FLAG_VALUE == 1
4388 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4389 && op1 == const0_rtx
4390 && mode == GET_MODE (op0)
4391 && nonzero_bits (op0, mode) == 1)
4392 return gen_lowpart_for_combine (mode,
4393 expand_compound_operation (op0));
4395 else if (STORE_FLAG_VALUE == 1
4396 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4397 && op1 == const0_rtx
4398 && mode == GET_MODE (op0)
4399 && (num_sign_bit_copies (op0, mode)
4400 == GET_MODE_BITSIZE (mode)))
4402 op0 = expand_compound_operation (op0);
4403 return simplify_gen_unary (NEG, mode,
4404 gen_lowpart_for_combine (mode, op0),
4408 else if (STORE_FLAG_VALUE == 1
4409 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4410 && op1 == const0_rtx
4411 && mode == GET_MODE (op0)
4412 && nonzero_bits (op0, mode) == 1)
4414 op0 = expand_compound_operation (op0);
4415 return gen_binary (XOR, mode,
4416 gen_lowpart_for_combine (mode, op0),
4420 else if (STORE_FLAG_VALUE == 1
4421 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4422 && op1 == const0_rtx
4423 && mode == GET_MODE (op0)
4424 && (num_sign_bit_copies (op0, mode)
4425 == GET_MODE_BITSIZE (mode)))
4427 op0 = expand_compound_operation (op0);
4428 return plus_constant (gen_lowpart_for_combine (mode, op0), 1);
4431 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4433 if (STORE_FLAG_VALUE == -1
4434 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4435 && op1 == const0_rtx
4436 && (num_sign_bit_copies (op0, mode)
4437 == GET_MODE_BITSIZE (mode)))
4438 return gen_lowpart_for_combine (mode,
4439 expand_compound_operation (op0));
4441 else if (STORE_FLAG_VALUE == -1
4442 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4443 && op1 == const0_rtx
4444 && mode == GET_MODE (op0)
4445 && nonzero_bits (op0, mode) == 1)
4447 op0 = expand_compound_operation (op0);
4448 return simplify_gen_unary (NEG, mode,
4449 gen_lowpart_for_combine (mode, op0),
4453 else if (STORE_FLAG_VALUE == -1
4454 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4455 && op1 == const0_rtx
4456 && mode == GET_MODE (op0)
4457 && (num_sign_bit_copies (op0, mode)
4458 == GET_MODE_BITSIZE (mode)))
4460 op0 = expand_compound_operation (op0);
4461 return simplify_gen_unary (NOT, mode,
4462 gen_lowpart_for_combine (mode, op0),
4466 /* If X is 0/1, (eq X 0) is X-1. */
4467 else if (STORE_FLAG_VALUE == -1
4468 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4469 && op1 == const0_rtx
4470 && mode == GET_MODE (op0)
4471 && nonzero_bits (op0, mode) == 1)
4473 op0 = expand_compound_operation (op0);
4474 return plus_constant (gen_lowpart_for_combine (mode, op0), -1);
4477 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4478 one bit that might be nonzero, we can convert (ne x 0) to
4479 (ashift x c) where C puts the bit in the sign bit. Remove any
4480 AND with STORE_FLAG_VALUE when we are done, since we are only
4481 going to test the sign bit. */
4482 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4483 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4484 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4485 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE(mode)-1))
4486 && op1 == const0_rtx
4487 && mode == GET_MODE (op0)
4488 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4490 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4491 expand_compound_operation (op0),
4492 GET_MODE_BITSIZE (mode) - 1 - i);
4493 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4499 /* If the code changed, return a whole new comparison. */
4500 if (new_code != code)
4501 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
4503 /* Otherwise, keep this operation, but maybe change its operands.
4504 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4505 SUBST (XEXP (x, 0), op0);
4506 SUBST (XEXP (x, 1), op1);
4511 return simplify_if_then_else (x);
4517 /* If we are processing SET_DEST, we are done. */
4521 return expand_compound_operation (x);
4524 return simplify_set (x);
4529 return simplify_logical (x, last);
4532 /* (abs (neg <foo>)) -> (abs <foo>) */
4533 if (GET_CODE (XEXP (x, 0)) == NEG)
4534 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4536 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4538 if (GET_MODE (XEXP (x, 0)) == VOIDmode)
4541 /* If operand is something known to be positive, ignore the ABS. */
4542 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4543 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4544 <= HOST_BITS_PER_WIDE_INT)
4545 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4546 & ((HOST_WIDE_INT) 1
4547 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4551 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4552 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4553 return gen_rtx_NEG (mode, XEXP (x, 0));
4558 /* (ffs (*_extend <X>)) = (ffs <X>) */
4559 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4560 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4561 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4565 /* (float (sign_extend <X>)) = (float <X>). */
4566 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4567 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4575 /* If this is a shift by a constant amount, simplify it. */
4576 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4577 return simplify_shift_const (x, code, mode, XEXP (x, 0),
4578 INTVAL (XEXP (x, 1)));
4580 #ifdef SHIFT_COUNT_TRUNCATED
4581 else if (SHIFT_COUNT_TRUNCATED && GET_CODE (XEXP (x, 1)) != REG)
4583 force_to_mode (XEXP (x, 1), GET_MODE (x),
4585 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4594 rtx op0 = XEXP (x, 0);
4595 rtx op1 = XEXP (x, 1);
4598 if (GET_CODE (op1) != PARALLEL)
4600 len = XVECLEN (op1, 0);
4602 && GET_CODE (XVECEXP (op1, 0, 0)) == CONST_INT
4603 && GET_CODE (op0) == VEC_CONCAT)
4605 int offset = INTVAL (XVECEXP (op1, 0, 0)) * GET_MODE_SIZE (GET_MODE (x));
4607 /* Try to find the element in the VEC_CONCAT. */
4610 if (GET_MODE (op0) == GET_MODE (x))
4612 if (GET_CODE (op0) == VEC_CONCAT)
4614 HOST_WIDE_INT op0_size = GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)));
4615 if (op0_size < offset)
4616 op0 = XEXP (op0, 0);
4620 op0 = XEXP (op0, 1);
4638 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4641 simplify_if_then_else (x)
4644 enum machine_mode mode = GET_MODE (x);
4645 rtx cond = XEXP (x, 0);
4646 rtx true_rtx = XEXP (x, 1);
4647 rtx false_rtx = XEXP (x, 2);
4648 enum rtx_code true_code = GET_CODE (cond);
4649 int comparison_p = GET_RTX_CLASS (true_code) == '<';
4652 enum rtx_code false_code;
4655 /* Simplify storing of the truth value. */
4656 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
4657 return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1));
4659 /* Also when the truth value has to be reversed. */
4661 && true_rtx == const0_rtx && false_rtx == const_true_rtx
4662 && (reversed = reversed_comparison (cond, mode, XEXP (cond, 0),
4666 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4667 in it is being compared against certain values. Get the true and false
4668 comparisons and see if that says anything about the value of each arm. */
4671 && ((false_code = combine_reversed_comparison_code (cond))
4673 && GET_CODE (XEXP (cond, 0)) == REG)
4676 rtx from = XEXP (cond, 0);
4677 rtx true_val = XEXP (cond, 1);
4678 rtx false_val = true_val;
4681 /* If FALSE_CODE is EQ, swap the codes and arms. */
4683 if (false_code == EQ)
4685 swapped = 1, true_code = EQ, false_code = NE;
4686 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4689 /* If we are comparing against zero and the expression being tested has
4690 only a single bit that might be nonzero, that is its value when it is
4691 not equal to zero. Similarly if it is known to be -1 or 0. */
4693 if (true_code == EQ && true_val == const0_rtx
4694 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4695 false_code = EQ, false_val = GEN_INT (nzb);
4696 else if (true_code == EQ && true_val == const0_rtx
4697 && (num_sign_bit_copies (from, GET_MODE (from))
4698 == GET_MODE_BITSIZE (GET_MODE (from))))
4699 false_code = EQ, false_val = constm1_rtx;
4701 /* Now simplify an arm if we know the value of the register in the
4702 branch and it is used in the arm. Be careful due to the potential
4703 of locally-shared RTL. */
4705 if (reg_mentioned_p (from, true_rtx))
4706 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
4708 pc_rtx, pc_rtx, 0, 0);
4709 if (reg_mentioned_p (from, false_rtx))
4710 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
4712 pc_rtx, pc_rtx, 0, 0);
4714 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
4715 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
4717 true_rtx = XEXP (x, 1);
4718 false_rtx = XEXP (x, 2);
4719 true_code = GET_CODE (cond);
4722 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4723 reversed, do so to avoid needing two sets of patterns for
4724 subtract-and-branch insns. Similarly if we have a constant in the true
4725 arm, the false arm is the same as the first operand of the comparison, or
4726 the false arm is more complicated than the true arm. */
4729 && combine_reversed_comparison_code (cond) != UNKNOWN
4730 && (true_rtx == pc_rtx
4731 || (CONSTANT_P (true_rtx)
4732 && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx)
4733 || true_rtx == const0_rtx
4734 || (GET_RTX_CLASS (GET_CODE (true_rtx)) == 'o'
4735 && GET_RTX_CLASS (GET_CODE (false_rtx)) != 'o')
4736 || (GET_CODE (true_rtx) == SUBREG
4737 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true_rtx))) == 'o'
4738 && GET_RTX_CLASS (GET_CODE (false_rtx)) != 'o')
4739 || reg_mentioned_p (true_rtx, false_rtx)
4740 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
4742 true_code = reversed_comparison_code (cond, NULL);
4744 reversed_comparison (cond, GET_MODE (cond), XEXP (cond, 0),
4747 SUBST (XEXP (x, 1), false_rtx);
4748 SUBST (XEXP (x, 2), true_rtx);
4750 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4753 /* It is possible that the conditional has been simplified out. */
4754 true_code = GET_CODE (cond);
4755 comparison_p = GET_RTX_CLASS (true_code) == '<';
4758 /* If the two arms are identical, we don't need the comparison. */
4760 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
4763 /* Convert a == b ? b : a to "a". */
4764 if (true_code == EQ && ! side_effects_p (cond)
4765 && (! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4766 && rtx_equal_p (XEXP (cond, 0), false_rtx)
4767 && rtx_equal_p (XEXP (cond, 1), true_rtx))
4769 else if (true_code == NE && ! side_effects_p (cond)
4770 && (! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4771 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4772 && rtx_equal_p (XEXP (cond, 1), false_rtx))
4775 /* Look for cases where we have (abs x) or (neg (abs X)). */
4777 if (GET_MODE_CLASS (mode) == MODE_INT
4778 && GET_CODE (false_rtx) == NEG
4779 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
4781 && rtx_equal_p (true_rtx, XEXP (cond, 0))
4782 && ! side_effects_p (true_rtx))
4787 return simplify_gen_unary (ABS, mode, true_rtx, mode);
4791 simplify_gen_unary (NEG, mode,
4792 simplify_gen_unary (ABS, mode, true_rtx, mode),
4798 /* Look for MIN or MAX. */
4800 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4802 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4803 && rtx_equal_p (XEXP (cond, 1), false_rtx)
4804 && ! side_effects_p (cond))
4809 return gen_binary (SMAX, mode, true_rtx, false_rtx);
4812 return gen_binary (SMIN, mode, true_rtx, false_rtx);
4815 return gen_binary (UMAX, mode, true_rtx, false_rtx);
4818 return gen_binary (UMIN, mode, true_rtx, false_rtx);
4823 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4824 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4825 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4826 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4827 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4828 neither 1 or -1, but it isn't worth checking for. */
4830 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4831 && comparison_p && mode != VOIDmode && ! side_effects_p (x))
4833 rtx t = make_compound_operation (true_rtx, SET);
4834 rtx f = make_compound_operation (false_rtx, SET);
4835 rtx cond_op0 = XEXP (cond, 0);
4836 rtx cond_op1 = XEXP (cond, 1);
4837 enum rtx_code op = NIL, extend_op = NIL;
4838 enum machine_mode m = mode;
4839 rtx z = 0, c1 = NULL_RTX;
4841 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4842 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4843 || GET_CODE (t) == ASHIFT
4844 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4845 && rtx_equal_p (XEXP (t, 0), f))
4846 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4848 /* If an identity-zero op is commutative, check whether there
4849 would be a match if we swapped the operands. */
4850 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4851 || GET_CODE (t) == XOR)
4852 && rtx_equal_p (XEXP (t, 1), f))
4853 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4854 else if (GET_CODE (t) == SIGN_EXTEND
4855 && (GET_CODE (XEXP (t, 0)) == PLUS
4856 || GET_CODE (XEXP (t, 0)) == MINUS
4857 || GET_CODE (XEXP (t, 0)) == IOR
4858 || GET_CODE (XEXP (t, 0)) == XOR
4859 || GET_CODE (XEXP (t, 0)) == ASHIFT
4860 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4861 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4862 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4863 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4864 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4865 && (num_sign_bit_copies (f, GET_MODE (f))
4866 > (GET_MODE_BITSIZE (mode)
4867 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
4869 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4870 extend_op = SIGN_EXTEND;
4871 m = GET_MODE (XEXP (t, 0));
4873 else if (GET_CODE (t) == SIGN_EXTEND
4874 && (GET_CODE (XEXP (t, 0)) == PLUS
4875 || GET_CODE (XEXP (t, 0)) == IOR
4876 || GET_CODE (XEXP (t, 0)) == XOR)
4877 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4878 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4879 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4880 && (num_sign_bit_copies (f, GET_MODE (f))
4881 > (GET_MODE_BITSIZE (mode)
4882 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
4884 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4885 extend_op = SIGN_EXTEND;
4886 m = GET_MODE (XEXP (t, 0));
4888 else if (GET_CODE (t) == ZERO_EXTEND
4889 && (GET_CODE (XEXP (t, 0)) == PLUS
4890 || GET_CODE (XEXP (t, 0)) == MINUS
4891 || GET_CODE (XEXP (t, 0)) == IOR
4892 || GET_CODE (XEXP (t, 0)) == XOR
4893 || GET_CODE (XEXP (t, 0)) == ASHIFT
4894 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4895 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4896 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4897 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4898 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4899 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4900 && ((nonzero_bits (f, GET_MODE (f))
4901 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
4904 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4905 extend_op = ZERO_EXTEND;
4906 m = GET_MODE (XEXP (t, 0));
4908 else if (GET_CODE (t) == ZERO_EXTEND
4909 && (GET_CODE (XEXP (t, 0)) == PLUS
4910 || GET_CODE (XEXP (t, 0)) == IOR
4911 || GET_CODE (XEXP (t, 0)) == XOR)
4912 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4913 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4914 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4915 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4916 && ((nonzero_bits (f, GET_MODE (f))
4917 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
4920 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4921 extend_op = ZERO_EXTEND;
4922 m = GET_MODE (XEXP (t, 0));
4927 temp = subst (gen_binary (true_code, m, cond_op0, cond_op1),
4928 pc_rtx, pc_rtx, 0, 0);
4929 temp = gen_binary (MULT, m, temp,
4930 gen_binary (MULT, m, c1, const_true_rtx));
4931 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
4932 temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp);
4934 if (extend_op != NIL)
4935 temp = simplify_gen_unary (extend_op, mode, temp, m);
4941 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4942 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4943 negation of a single bit, we can convert this operation to a shift. We
4944 can actually do this more generally, but it doesn't seem worth it. */
4946 if (true_code == NE && XEXP (cond, 1) == const0_rtx
4947 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
4948 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
4949 && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
4950 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
4951 == GET_MODE_BITSIZE (mode))
4952 && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
4954 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4955 gen_lowpart_for_combine (mode, XEXP (cond, 0)), i);
4960 /* Simplify X, a SET expression. Return the new expression. */
4966 rtx src = SET_SRC (x);
4967 rtx dest = SET_DEST (x);
4968 enum machine_mode mode
4969 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
4973 /* (set (pc) (return)) gets written as (return). */
4974 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
4977 /* Now that we know for sure which bits of SRC we are using, see if we can
4978 simplify the expression for the object knowing that we only need the
4981 if (GET_MODE_CLASS (mode) == MODE_INT)
4983 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, NULL_RTX, 0);
4984 SUBST (SET_SRC (x), src);
4987 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4988 the comparison result and try to simplify it unless we already have used
4989 undobuf.other_insn. */
4990 if ((GET_CODE (src) == COMPARE
4995 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
4996 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
4997 && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
4998 && rtx_equal_p (XEXP (*cc_use, 0), dest))
5000 enum rtx_code old_code = GET_CODE (*cc_use);
5001 enum rtx_code new_code;
5003 int other_changed = 0;
5004 enum machine_mode compare_mode = GET_MODE (dest);
5006 if (GET_CODE (src) == COMPARE)
5007 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
5009 op0 = src, op1 = const0_rtx;
5011 /* Simplify our comparison, if possible. */
5012 new_code = simplify_comparison (old_code, &op0, &op1);
5014 #ifdef EXTRA_CC_MODES
5015 /* If this machine has CC modes other than CCmode, check to see if we
5016 need to use a different CC mode here. */
5017 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5018 #endif /* EXTRA_CC_MODES */
5020 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
5021 /* If the mode changed, we have to change SET_DEST, the mode in the
5022 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5023 a hard register, just build new versions with the proper mode. If it
5024 is a pseudo, we lose unless it is only time we set the pseudo, in
5025 which case we can safely change its mode. */
5026 if (compare_mode != GET_MODE (dest))
5028 unsigned int regno = REGNO (dest);
5029 rtx new_dest = gen_rtx_REG (compare_mode, regno);
5031 if (regno < FIRST_PSEUDO_REGISTER
5032 || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest)))
5034 if (regno >= FIRST_PSEUDO_REGISTER)
5035 SUBST (regno_reg_rtx[regno], new_dest);
5037 SUBST (SET_DEST (x), new_dest);
5038 SUBST (XEXP (*cc_use, 0), new_dest);
5046 /* If the code changed, we have to build a new comparison in
5047 undobuf.other_insn. */
5048 if (new_code != old_code)
5050 unsigned HOST_WIDE_INT mask;
5052 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5055 /* If the only change we made was to change an EQ into an NE or
5056 vice versa, OP0 has only one bit that might be nonzero, and OP1
5057 is zero, check if changing the user of the condition code will
5058 produce a valid insn. If it won't, we can keep the original code
5059 in that insn by surrounding our operation with an XOR. */
5061 if (((old_code == NE && new_code == EQ)
5062 || (old_code == EQ && new_code == NE))
5063 && ! other_changed && op1 == const0_rtx
5064 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5065 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5067 rtx pat = PATTERN (other_insn), note = 0;
5069 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
5070 && ! check_asm_operands (pat)))
5072 PUT_CODE (*cc_use, old_code);
5075 op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask));
5083 undobuf.other_insn = other_insn;
5086 /* If we are now comparing against zero, change our source if
5087 needed. If we do not use cc0, we always have a COMPARE. */
5088 if (op1 == const0_rtx && dest == cc0_rtx)
5090 SUBST (SET_SRC (x), op0);
5096 /* Otherwise, if we didn't previously have a COMPARE in the
5097 correct mode, we need one. */
5098 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5100 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5105 /* Otherwise, update the COMPARE if needed. */
5106 SUBST (XEXP (src, 0), op0);
5107 SUBST (XEXP (src, 1), op1);
5112 /* Get SET_SRC in a form where we have placed back any
5113 compound expressions. Then do the checks below. */
5114 src = make_compound_operation (src, SET);
5115 SUBST (SET_SRC (x), src);
5118 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5119 and X being a REG or (subreg (reg)), we may be able to convert this to
5120 (set (subreg:m2 x) (op)).
5122 We can always do this if M1 is narrower than M2 because that means that
5123 we only care about the low bits of the result.
5125 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5126 perform a narrower operation than requested since the high-order bits will
5127 be undefined. On machine where it is defined, this transformation is safe
5128 as long as M1 and M2 have the same number of words. */
5130 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5131 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src))) != 'o'
5132 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5134 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5135 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5136 #ifndef WORD_REGISTER_OPERATIONS
5137 && (GET_MODE_SIZE (GET_MODE (src))
5138 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5140 #ifdef CLASS_CANNOT_CHANGE_MODE
5141 && ! (GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER
5142 && (TEST_HARD_REG_BIT
5143 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE],
5145 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (src),
5146 GET_MODE (SUBREG_REG (src))))
5148 && (GET_CODE (dest) == REG
5149 || (GET_CODE (dest) == SUBREG
5150 && GET_CODE (SUBREG_REG (dest)) == REG)))
5152 SUBST (SET_DEST (x),
5153 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src)),
5155 SUBST (SET_SRC (x), SUBREG_REG (src));
5157 src = SET_SRC (x), dest = SET_DEST (x);
5160 #ifdef LOAD_EXTEND_OP
5161 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5162 would require a paradoxical subreg. Replace the subreg with a
5163 zero_extend to avoid the reload that would otherwise be required. */
5165 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5166 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL
5167 && SUBREG_BYTE (src) == 0
5168 && (GET_MODE_SIZE (GET_MODE (src))
5169 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5170 && GET_CODE (SUBREG_REG (src)) == MEM)
5173 gen_rtx (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5174 GET_MODE (src), SUBREG_REG (src)));
5180 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5181 are comparing an item known to be 0 or -1 against 0, use a logical
5182 operation instead. Check for one of the arms being an IOR of the other
5183 arm with some value. We compute three terms to be IOR'ed together. In
5184 practice, at most two will be nonzero. Then we do the IOR's. */
5186 if (GET_CODE (dest) != PC
5187 && GET_CODE (src) == IF_THEN_ELSE
5188 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5189 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5190 && XEXP (XEXP (src, 0), 1) == const0_rtx
5191 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5192 #ifdef HAVE_conditional_move
5193 && ! can_conditionally_move_p (GET_MODE (src))
5195 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5196 GET_MODE (XEXP (XEXP (src, 0), 0)))
5197 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5198 && ! side_effects_p (src))
5200 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
5201 ? XEXP (src, 1) : XEXP (src, 2));
5202 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
5203 ? XEXP (src, 2) : XEXP (src, 1));
5204 rtx term1 = const0_rtx, term2, term3;
5206 if (GET_CODE (true_rtx) == IOR
5207 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
5208 term1 = false_rtx, true_rtx = XEXP(true_rtx, 1), false_rtx = const0_rtx;
5209 else if (GET_CODE (true_rtx) == IOR
5210 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
5211 term1 = false_rtx, true_rtx = XEXP(true_rtx, 0), false_rtx = const0_rtx;
5212 else if (GET_CODE (false_rtx) == IOR
5213 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
5214 term1 = true_rtx, false_rtx = XEXP(false_rtx, 1), true_rtx = const0_rtx;
5215 else if (GET_CODE (false_rtx) == IOR
5216 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
5217 term1 = true_rtx, false_rtx = XEXP(false_rtx, 0), true_rtx = const0_rtx;
5219 term2 = gen_binary (AND, GET_MODE (src),
5220 XEXP (XEXP (src, 0), 0), true_rtx);
5221 term3 = gen_binary (AND, GET_MODE (src),
5222 simplify_gen_unary (NOT, GET_MODE (src),
5223 XEXP (XEXP (src, 0), 0),
5228 gen_binary (IOR, GET_MODE (src),
5229 gen_binary (IOR, GET_MODE (src), term1, term2),
5235 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5236 whole thing fail. */
5237 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5239 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5242 /* Convert this into a field assignment operation, if possible. */
5243 return make_field_assignment (x);
5246 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5247 result. LAST is nonzero if this is the last retry. */
5250 simplify_logical (x, last)
5254 enum machine_mode mode = GET_MODE (x);
5255 rtx op0 = XEXP (x, 0);
5256 rtx op1 = XEXP (x, 1);
5259 switch (GET_CODE (x))
5262 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5263 insn (and may simplify more). */
5264 if (GET_CODE (op0) == XOR
5265 && rtx_equal_p (XEXP (op0, 0), op1)
5266 && ! side_effects_p (op1))
5267 x = gen_binary (AND, mode,
5268 simplify_gen_unary (NOT, mode, XEXP (op0, 1), mode),
5271 if (GET_CODE (op0) == XOR
5272 && rtx_equal_p (XEXP (op0, 1), op1)
5273 && ! side_effects_p (op1))
5274 x = gen_binary (AND, mode,
5275 simplify_gen_unary (NOT, mode, XEXP (op0, 0), mode),
5278 /* Similarly for (~(A ^ B)) & A. */
5279 if (GET_CODE (op0) == NOT
5280 && GET_CODE (XEXP (op0, 0)) == XOR
5281 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
5282 && ! side_effects_p (op1))
5283 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
5285 if (GET_CODE (op0) == NOT
5286 && GET_CODE (XEXP (op0, 0)) == XOR
5287 && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
5288 && ! side_effects_p (op1))
5289 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
5291 /* We can call simplify_and_const_int only if we don't lose
5292 any (sign) bits when converting INTVAL (op1) to
5293 "unsigned HOST_WIDE_INT". */
5294 if (GET_CODE (op1) == CONST_INT
5295 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5296 || INTVAL (op1) > 0))
5298 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5300 /* If we have (ior (and (X C1) C2)) and the next restart would be
5301 the last, simplify this by making C1 as small as possible
5304 && GET_CODE (x) == IOR && GET_CODE (op0) == AND
5305 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5306 && GET_CODE (op1) == CONST_INT)
5307 return gen_binary (IOR, mode,
5308 gen_binary (AND, mode, XEXP (op0, 0),
5309 GEN_INT (INTVAL (XEXP (op0, 1))
5310 & ~INTVAL (op1))), op1);
5312 if (GET_CODE (x) != AND)
5315 if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
5316 || GET_RTX_CLASS (GET_CODE (x)) == '2')
5317 op0 = XEXP (x, 0), op1 = XEXP (x, 1);
5320 /* Convert (A | B) & A to A. */
5321 if (GET_CODE (op0) == IOR
5322 && (rtx_equal_p (XEXP (op0, 0), op1)
5323 || rtx_equal_p (XEXP (op0, 1), op1))
5324 && ! side_effects_p (XEXP (op0, 0))
5325 && ! side_effects_p (XEXP (op0, 1)))
5328 /* In the following group of tests (and those in case IOR below),
5329 we start with some combination of logical operations and apply
5330 the distributive law followed by the inverse distributive law.
5331 Most of the time, this results in no change. However, if some of
5332 the operands are the same or inverses of each other, simplifications
5335 For example, (and (ior A B) (not B)) can occur as the result of
5336 expanding a bit field assignment. When we apply the distributive
5337 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5338 which then simplifies to (and (A (not B))).
5340 If we have (and (ior A B) C), apply the distributive law and then
5341 the inverse distributive law to see if things simplify. */
5343 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5345 x = apply_distributive_law
5346 (gen_binary (GET_CODE (op0), mode,
5347 gen_binary (AND, mode, XEXP (op0, 0), op1),
5348 gen_binary (AND, mode, XEXP (op0, 1),
5350 if (GET_CODE (x) != AND)
5354 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5355 return apply_distributive_law
5356 (gen_binary (GET_CODE (op1), mode,
5357 gen_binary (AND, mode, XEXP (op1, 0), op0),
5358 gen_binary (AND, mode, XEXP (op1, 1),
5361 /* Similarly, taking advantage of the fact that
5362 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5364 if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR)
5365 return apply_distributive_law
5366 (gen_binary (XOR, mode,
5367 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)),
5368 gen_binary (IOR, mode, copy_rtx (XEXP (op0, 0)),
5371 else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR)
5372 return apply_distributive_law
5373 (gen_binary (XOR, mode,
5374 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)),
5375 gen_binary (IOR, mode, copy_rtx (XEXP (op1, 0)), XEXP (op0, 1))));
5379 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5380 if (GET_CODE (op1) == CONST_INT
5381 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5382 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
5385 /* Convert (A & B) | A to A. */
5386 if (GET_CODE (op0) == AND
5387 && (rtx_equal_p (XEXP (op0, 0), op1)
5388 || rtx_equal_p (XEXP (op0, 1), op1))
5389 && ! side_effects_p (XEXP (op0, 0))
5390 && ! side_effects_p (XEXP (op0, 1)))
5393 /* If we have (ior (and A B) C), apply the distributive law and then
5394 the inverse distributive law to see if things simplify. */
5396 if (GET_CODE (op0) == AND)
5398 x = apply_distributive_law
5399 (gen_binary (AND, mode,
5400 gen_binary (IOR, mode, XEXP (op0, 0), op1),
5401 gen_binary (IOR, mode, XEXP (op0, 1),
5404 if (GET_CODE (x) != IOR)
5408 if (GET_CODE (op1) == AND)
5410 x = apply_distributive_law
5411 (gen_binary (AND, mode,
5412 gen_binary (IOR, mode, XEXP (op1, 0), op0),
5413 gen_binary (IOR, mode, XEXP (op1, 1),
5416 if (GET_CODE (x) != IOR)
5420 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5421 mode size to (rotate A CX). */
5423 if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
5424 || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
5425 && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
5426 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5427 && GET_CODE (XEXP (op1, 1)) == CONST_INT
5428 && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
5429 == GET_MODE_BITSIZE (mode)))
5430 return gen_rtx_ROTATE (mode, XEXP (op0, 0),
5431 (GET_CODE (op0) == ASHIFT
5432 ? XEXP (op0, 1) : XEXP (op1, 1)));
5434 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5435 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5436 does not affect any of the bits in OP1, it can really be done
5437 as a PLUS and we can associate. We do this by seeing if OP1
5438 can be safely shifted left C bits. */
5439 if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
5440 && GET_CODE (XEXP (op0, 0)) == PLUS
5441 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
5442 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5443 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
5445 int count = INTVAL (XEXP (op0, 1));
5446 HOST_WIDE_INT mask = INTVAL (op1) << count;
5448 if (mask >> count == INTVAL (op1)
5449 && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
5451 SUBST (XEXP (XEXP (op0, 0), 1),
5452 GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
5459 /* If we are XORing two things that have no bits in common,
5460 convert them into an IOR. This helps to detect rotation encoded
5461 using those methods and possibly other simplifications. */
5463 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5464 && (nonzero_bits (op0, mode)
5465 & nonzero_bits (op1, mode)) == 0)
5466 return (gen_binary (IOR, mode, op0, op1));
5468 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5469 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5472 int num_negated = 0;
5474 if (GET_CODE (op0) == NOT)
5475 num_negated++, op0 = XEXP (op0, 0);
5476 if (GET_CODE (op1) == NOT)
5477 num_negated++, op1 = XEXP (op1, 0);
5479 if (num_negated == 2)
5481 SUBST (XEXP (x, 0), op0);
5482 SUBST (XEXP (x, 1), op1);
5484 else if (num_negated == 1)
5486 simplify_gen_unary (NOT, mode, gen_binary (XOR, mode, op0, op1),
5490 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5491 correspond to a machine insn or result in further simplifications
5492 if B is a constant. */
5494 if (GET_CODE (op0) == AND
5495 && rtx_equal_p (XEXP (op0, 1), op1)
5496 && ! side_effects_p (op1))
5497 return gen_binary (AND, mode,
5498 simplify_gen_unary (NOT, mode, XEXP (op0, 0), mode),
5501 else if (GET_CODE (op0) == AND
5502 && rtx_equal_p (XEXP (op0, 0), op1)
5503 && ! side_effects_p (op1))
5504 return gen_binary (AND, mode,
5505 simplify_gen_unary (NOT, mode, XEXP (op0, 1), mode),
5508 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5509 comparison if STORE_FLAG_VALUE is 1. */
5510 if (STORE_FLAG_VALUE == 1
5511 && op1 == const1_rtx
5512 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5513 && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0),
5517 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5518 is (lt foo (const_int 0)), so we can perform the above
5519 simplification if STORE_FLAG_VALUE is 1. */
5521 if (STORE_FLAG_VALUE == 1
5522 && op1 == const1_rtx
5523 && GET_CODE (op0) == LSHIFTRT
5524 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5525 && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
5526 return gen_rtx_GE (mode, XEXP (op0, 0), const0_rtx);
5528 /* (xor (comparison foo bar) (const_int sign-bit))
5529 when STORE_FLAG_VALUE is the sign bit. */
5530 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5531 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5532 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5533 && op1 == const_true_rtx
5534 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5535 && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0),
5548 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5549 operations" because they can be replaced with two more basic operations.
5550 ZERO_EXTEND is also considered "compound" because it can be replaced with
5551 an AND operation, which is simpler, though only one operation.
5553 The function expand_compound_operation is called with an rtx expression
5554 and will convert it to the appropriate shifts and AND operations,
5555 simplifying at each stage.
5557 The function make_compound_operation is called to convert an expression
5558 consisting of shifts and ANDs into the equivalent compound expression.
5559 It is the inverse of this function, loosely speaking. */
5562 expand_compound_operation (x)
5565 unsigned HOST_WIDE_INT pos = 0, len;
5567 unsigned int modewidth;
5570 switch (GET_CODE (x))
5575 /* We can't necessarily use a const_int for a multiword mode;
5576 it depends on implicitly extending the value.
5577 Since we don't know the right way to extend it,
5578 we can't tell whether the implicit way is right.
5580 Even for a mode that is no wider than a const_int,
5581 we can't win, because we need to sign extend one of its bits through
5582 the rest of it, and we don't know which bit. */
5583 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5586 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5587 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5588 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5589 reloaded. If not for that, MEM's would very rarely be safe.
5591 Reject MODEs bigger than a word, because we might not be able
5592 to reference a two-register group starting with an arbitrary register
5593 (and currently gen_lowpart might crash for a SUBREG). */
5595 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5598 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5599 /* If the inner object has VOIDmode (the only way this can happen
5600 is if it is a ASM_OPERANDS), we can't do anything since we don't
5601 know how much masking to do. */
5610 /* If the operand is a CLOBBER, just return it. */
5611 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5614 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5615 || GET_CODE (XEXP (x, 2)) != CONST_INT
5616 || GET_MODE (XEXP (x, 0)) == VOIDmode)
5619 len = INTVAL (XEXP (x, 1));
5620 pos = INTVAL (XEXP (x, 2));
5622 /* If this goes outside the object being extracted, replace the object
5623 with a (use (mem ...)) construct that only combine understands
5624 and is used only for this purpose. */
5625 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5626 SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0)));
5628 if (BITS_BIG_ENDIAN)
5629 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5636 /* Convert sign extension to zero extension, if we know that the high
5637 bit is not set, as this is easier to optimize. It will be converted
5638 back to cheaper alternative in make_extraction. */
5639 if (GET_CODE (x) == SIGN_EXTEND
5640 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5641 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
5642 & ~(((unsigned HOST_WIDE_INT)
5643 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5647 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
5648 return expand_compound_operation (temp);
5651 /* We can optimize some special cases of ZERO_EXTEND. */
5652 if (GET_CODE (x) == ZERO_EXTEND)
5654 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5655 know that the last value didn't have any inappropriate bits
5657 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5658 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5659 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5660 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5661 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5662 return XEXP (XEXP (x, 0), 0);
5664 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5665 if (GET_CODE (XEXP (x, 0)) == SUBREG
5666 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5667 && subreg_lowpart_p (XEXP (x, 0))
5668 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5669 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5670 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5671 return SUBREG_REG (XEXP (x, 0));
5673 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5674 is a comparison and STORE_FLAG_VALUE permits. This is like
5675 the first case, but it works even when GET_MODE (x) is larger
5676 than HOST_WIDE_INT. */
5677 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5678 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5679 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) == '<'
5680 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5681 <= HOST_BITS_PER_WIDE_INT)
5682 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5683 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5684 return XEXP (XEXP (x, 0), 0);
5686 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5687 if (GET_CODE (XEXP (x, 0)) == SUBREG
5688 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5689 && subreg_lowpart_p (XEXP (x, 0))
5690 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == '<'
5691 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5692 <= HOST_BITS_PER_WIDE_INT)
5693 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5694 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5695 return SUBREG_REG (XEXP (x, 0));
5699 /* If we reach here, we want to return a pair of shifts. The inner
5700 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5701 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5702 logical depending on the value of UNSIGNEDP.
5704 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5705 converted into an AND of a shift.
5707 We must check for the case where the left shift would have a negative
5708 count. This can happen in a case like (x >> 31) & 255 on machines
5709 that can't shift by a constant. On those machines, we would first
5710 combine the shift with the AND to produce a variable-position
5711 extraction. Then the constant of 31 would be substituted in to produce
5712 a such a position. */
5714 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5715 if (modewidth + len >= pos)
5716 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5718 simplify_shift_const (NULL_RTX, ASHIFT,
5721 modewidth - pos - len),
5724 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5725 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5726 simplify_shift_const (NULL_RTX, LSHIFTRT,
5729 ((HOST_WIDE_INT) 1 << len) - 1);
5731 /* Any other cases we can't handle. */
5734 /* If we couldn't do this for some reason, return the original
5736 if (GET_CODE (tem) == CLOBBER)
5742 /* X is a SET which contains an assignment of one object into
5743 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5744 or certain SUBREGS). If possible, convert it into a series of
5747 We half-heartedly support variable positions, but do not at all
5748 support variable lengths. */
5751 expand_field_assignment (x)
5755 rtx pos; /* Always counts from low bit. */
5758 enum machine_mode compute_mode;
5760 /* Loop until we find something we can't simplify. */
5763 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5764 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5766 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5767 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5768 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
5770 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5771 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5773 inner = XEXP (SET_DEST (x), 0);
5774 len = INTVAL (XEXP (SET_DEST (x), 1));
5775 pos = XEXP (SET_DEST (x), 2);
5777 /* If the position is constant and spans the width of INNER,
5778 surround INNER with a USE to indicate this. */
5779 if (GET_CODE (pos) == CONST_INT
5780 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5781 inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner);
5783 if (BITS_BIG_ENDIAN)
5785 if (GET_CODE (pos) == CONST_INT)
5786 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5788 else if (GET_CODE (pos) == MINUS
5789 && GET_CODE (XEXP (pos, 1)) == CONST_INT
5790 && (INTVAL (XEXP (pos, 1))
5791 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5792 /* If position is ADJUST - X, new position is X. */
5793 pos = XEXP (pos, 0);
5795 pos = gen_binary (MINUS, GET_MODE (pos),
5796 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
5802 /* A SUBREG between two modes that occupy the same numbers of words
5803 can be done by moving the SUBREG to the source. */
5804 else if (GET_CODE (SET_DEST (x)) == SUBREG
5805 /* We need SUBREGs to compute nonzero_bits properly. */
5806 && nonzero_sign_valid
5807 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5808 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5809 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5810 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5812 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
5813 gen_lowpart_for_combine
5814 (GET_MODE (SUBREG_REG (SET_DEST (x))),
5821 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5822 inner = SUBREG_REG (inner);
5824 compute_mode = GET_MODE (inner);
5826 /* Don't attempt bitwise arithmetic on non-integral modes. */
5827 if (! INTEGRAL_MODE_P (compute_mode))
5829 enum machine_mode imode;
5831 /* Something is probably seriously wrong if this matches. */
5832 if (! FLOAT_MODE_P (compute_mode))
5835 /* Try to find an integral mode to pun with. */
5836 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
5837 if (imode == BLKmode)
5840 compute_mode = imode;
5841 inner = gen_lowpart_for_combine (imode, inner);
5844 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5845 if (len < HOST_BITS_PER_WIDE_INT)
5846 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
5850 /* Now compute the equivalent expression. Make a copy of INNER
5851 for the SET_DEST in case it is a MEM into which we will substitute;
5852 we don't want shared RTL in that case. */
5854 (VOIDmode, copy_rtx (inner),
5855 gen_binary (IOR, compute_mode,
5856 gen_binary (AND, compute_mode,
5857 simplify_gen_unary (NOT, compute_mode,
5863 gen_binary (ASHIFT, compute_mode,
5864 gen_binary (AND, compute_mode,
5865 gen_lowpart_for_combine
5866 (compute_mode, SET_SRC (x)),
5874 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5875 it is an RTX that represents a variable starting position; otherwise,
5876 POS is the (constant) starting bit position (counted from the LSB).
5878 INNER may be a USE. This will occur when we started with a bitfield
5879 that went outside the boundary of the object in memory, which is
5880 allowed on most machines. To isolate this case, we produce a USE
5881 whose mode is wide enough and surround the MEM with it. The only
5882 code that understands the USE is this routine. If it is not removed,
5883 it will cause the resulting insn not to match.
5885 UNSIGNEDP is non-zero for an unsigned reference and zero for a
5888 IN_DEST is non-zero if this is a reference in the destination of a
5889 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
5890 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5893 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
5894 ZERO_EXTRACT should be built even for bits starting at bit 0.
5896 MODE is the desired mode of the result (if IN_DEST == 0).
5898 The result is an RTX for the extraction or NULL_RTX if the target
5902 make_extraction (mode, inner, pos, pos_rtx, len,
5903 unsignedp, in_dest, in_compare)
5904 enum machine_mode mode;
5908 unsigned HOST_WIDE_INT len;
5910 int in_dest, in_compare;
5912 /* This mode describes the size of the storage area
5913 to fetch the overall value from. Within that, we
5914 ignore the POS lowest bits, etc. */
5915 enum machine_mode is_mode = GET_MODE (inner);
5916 enum machine_mode inner_mode;
5917 enum machine_mode wanted_inner_mode = byte_mode;
5918 enum machine_mode wanted_inner_reg_mode = word_mode;
5919 enum machine_mode pos_mode = word_mode;
5920 enum machine_mode extraction_mode = word_mode;
5921 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
5924 rtx orig_pos_rtx = pos_rtx;
5925 HOST_WIDE_INT orig_pos;
5927 /* Get some information about INNER and get the innermost object. */
5928 if (GET_CODE (inner) == USE)
5929 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
5930 /* We don't need to adjust the position because we set up the USE
5931 to pretend that it was a full-word object. */
5932 spans_byte = 1, inner = XEXP (inner, 0);
5933 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5935 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5936 consider just the QI as the memory to extract from.
5937 The subreg adds or removes high bits; its mode is
5938 irrelevant to the meaning of this extraction,
5939 since POS and LEN count from the lsb. */
5940 if (GET_CODE (SUBREG_REG (inner)) == MEM)
5941 is_mode = GET_MODE (SUBREG_REG (inner));
5942 inner = SUBREG_REG (inner);
5945 inner_mode = GET_MODE (inner);
5947 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
5948 pos = INTVAL (pos_rtx), pos_rtx = 0;
5950 /* See if this can be done without an extraction. We never can if the
5951 width of the field is not the same as that of some integer mode. For
5952 registers, we can only avoid the extraction if the position is at the
5953 low-order bit and this is either not in the destination or we have the
5954 appropriate STRICT_LOW_PART operation available.
5956 For MEM, we can avoid an extract if the field starts on an appropriate
5957 boundary and we can change the mode of the memory reference. However,
5958 we cannot directly access the MEM if we have a USE and the underlying
5959 MEM is not TMODE. This combination means that MEM was being used in a
5960 context where bits outside its mode were being referenced; that is only
5961 valid in bit-field insns. */
5963 if (tmode != BLKmode
5964 && ! (spans_byte && inner_mode != tmode)
5965 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
5966 && GET_CODE (inner) != MEM
5968 || (GET_CODE (inner) == REG
5969 && have_insn_for (STRICT_LOW_PART, tmode))))
5970 || (GET_CODE (inner) == MEM && pos_rtx == 0
5972 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
5973 : BITS_PER_UNIT)) == 0
5974 /* We can't do this if we are widening INNER_MODE (it
5975 may not be aligned, for one thing). */
5976 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
5977 && (inner_mode == tmode
5978 || (! mode_dependent_address_p (XEXP (inner, 0))
5979 && ! MEM_VOLATILE_P (inner))))))
5981 /* If INNER is a MEM, make a new MEM that encompasses just the desired
5982 field. If the original and current mode are the same, we need not
5983 adjust the offset. Otherwise, we do if bytes big endian.
5985 If INNER is not a MEM, get a piece consisting of just the field
5986 of interest (in this case POS % BITS_PER_WORD must be 0). */
5988 if (GET_CODE (inner) == MEM)
5990 HOST_WIDE_INT offset;
5992 /* POS counts from lsb, but make OFFSET count in memory order. */
5993 if (BYTES_BIG_ENDIAN)
5994 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
5996 offset = pos / BITS_PER_UNIT;
5998 new = adjust_address_nv (inner, tmode, offset);
6000 else if (GET_CODE (inner) == REG)
6002 /* We can't call gen_lowpart_for_combine here since we always want
6003 a SUBREG and it would sometimes return a new hard register. */
6004 if (tmode != inner_mode)
6006 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
6008 if (WORDS_BIG_ENDIAN
6009 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
6010 final_word = ((GET_MODE_SIZE (inner_mode)
6011 - GET_MODE_SIZE (tmode))
6012 / UNITS_PER_WORD) - final_word;
6014 final_word *= UNITS_PER_WORD;
6015 if (BYTES_BIG_ENDIAN &&
6016 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
6017 final_word += (GET_MODE_SIZE (inner_mode)
6018 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
6020 new = gen_rtx_SUBREG (tmode, inner, final_word);
6026 new = force_to_mode (inner, tmode,
6027 len >= HOST_BITS_PER_WIDE_INT
6028 ? ~(unsigned HOST_WIDE_INT) 0
6029 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6032 /* If this extraction is going into the destination of a SET,
6033 make a STRICT_LOW_PART unless we made a MEM. */
6036 return (GET_CODE (new) == MEM ? new
6037 : (GET_CODE (new) != SUBREG
6038 ? gen_rtx_CLOBBER (tmode, const0_rtx)
6039 : gen_rtx_STRICT_LOW_PART (VOIDmode, new)));
6044 if (GET_CODE (new) == CONST_INT)
6045 return gen_int_mode (INTVAL (new), mode);
6047 /* If we know that no extraneous bits are set, and that the high
6048 bit is not set, convert the extraction to the cheaper of
6049 sign and zero extension, that are equivalent in these cases. */
6050 if (flag_expensive_optimizations
6051 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6052 && ((nonzero_bits (new, tmode)
6053 & ~(((unsigned HOST_WIDE_INT)
6054 GET_MODE_MASK (tmode))
6058 rtx temp = gen_rtx_ZERO_EXTEND (mode, new);
6059 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new);
6061 /* Prefer ZERO_EXTENSION, since it gives more information to
6063 if (rtx_cost (temp, SET) <= rtx_cost (temp1, SET))
6068 /* Otherwise, sign- or zero-extend unless we already are in the
6071 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6075 /* Unless this is a COMPARE or we have a funny memory reference,
6076 don't do anything with zero-extending field extracts starting at
6077 the low-order bit since they are simple AND operations. */
6078 if (pos_rtx == 0 && pos == 0 && ! in_dest
6079 && ! in_compare && ! spans_byte && unsignedp)
6082 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6083 we would be spanning bytes or if the position is not a constant and the
6084 length is not 1. In all other cases, we would only be going outside
6085 our object in cases when an original shift would have been
6087 if (! spans_byte && GET_CODE (inner) == MEM
6088 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6089 || (pos_rtx != 0 && len != 1)))
6092 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6093 and the mode for the result. */
6094 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6096 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6097 pos_mode = mode_for_extraction (EP_insv, 2);
6098 extraction_mode = mode_for_extraction (EP_insv, 3);
6101 if (! in_dest && unsignedp
6102 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6104 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6105 pos_mode = mode_for_extraction (EP_extzv, 3);
6106 extraction_mode = mode_for_extraction (EP_extzv, 0);
6109 if (! in_dest && ! unsignedp
6110 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6112 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6113 pos_mode = mode_for_extraction (EP_extv, 3);
6114 extraction_mode = mode_for_extraction (EP_extv, 0);
6117 /* Never narrow an object, since that might not be safe. */
6119 if (mode != VOIDmode
6120 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6121 extraction_mode = mode;
6123 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6124 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6125 pos_mode = GET_MODE (pos_rtx);
6127 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6128 if we have to change the mode of memory and cannot, the desired mode is
6130 if (GET_CODE (inner) != MEM)
6131 wanted_inner_mode = wanted_inner_reg_mode;
6132 else if (inner_mode != wanted_inner_mode
6133 && (mode_dependent_address_p (XEXP (inner, 0))
6134 || MEM_VOLATILE_P (inner)))
6135 wanted_inner_mode = extraction_mode;
6139 if (BITS_BIG_ENDIAN)
6141 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6142 BITS_BIG_ENDIAN style. If position is constant, compute new
6143 position. Otherwise, build subtraction.
6144 Note that POS is relative to the mode of the original argument.
6145 If it's a MEM we need to recompute POS relative to that.
6146 However, if we're extracting from (or inserting into) a register,
6147 we want to recompute POS relative to wanted_inner_mode. */
6148 int width = (GET_CODE (inner) == MEM
6149 ? GET_MODE_BITSIZE (is_mode)
6150 : GET_MODE_BITSIZE (wanted_inner_mode));
6153 pos = width - len - pos;
6156 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6157 /* POS may be less than 0 now, but we check for that below.
6158 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
6161 /* If INNER has a wider mode, make it smaller. If this is a constant
6162 extract, try to adjust the byte to point to the byte containing
6164 if (wanted_inner_mode != VOIDmode
6165 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6166 && ((GET_CODE (inner) == MEM
6167 && (inner_mode == wanted_inner_mode
6168 || (! mode_dependent_address_p (XEXP (inner, 0))
6169 && ! MEM_VOLATILE_P (inner))))))
6173 /* The computations below will be correct if the machine is big
6174 endian in both bits and bytes or little endian in bits and bytes.
6175 If it is mixed, we must adjust. */
6177 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6178 adjust OFFSET to compensate. */
6179 if (BYTES_BIG_ENDIAN
6181 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6182 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6184 /* If this is a constant position, we can move to the desired byte. */
6187 offset += pos / BITS_PER_UNIT;
6188 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6191 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6193 && is_mode != wanted_inner_mode)
6194 offset = (GET_MODE_SIZE (is_mode)
6195 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6197 if (offset != 0 || inner_mode != wanted_inner_mode)
6198 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6201 /* If INNER is not memory, we can always get it into the proper mode. If we
6202 are changing its mode, POS must be a constant and smaller than the size
6204 else if (GET_CODE (inner) != MEM)
6206 if (GET_MODE (inner) != wanted_inner_mode
6208 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6211 inner = force_to_mode (inner, wanted_inner_mode,
6213 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6214 ? ~(unsigned HOST_WIDE_INT) 0
6215 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6220 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6221 have to zero extend. Otherwise, we can just use a SUBREG. */
6223 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6225 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6227 /* If we know that no extraneous bits are set, and that the high
6228 bit is not set, convert extraction to cheaper one - either
6229 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6231 if (flag_expensive_optimizations
6232 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6233 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6234 & ~(((unsigned HOST_WIDE_INT)
6235 GET_MODE_MASK (GET_MODE (pos_rtx)))
6239 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6241 /* Prefer ZERO_EXTENSION, since it gives more information to
6243 if (rtx_cost (temp1, SET) < rtx_cost (temp, SET))
6248 else if (pos_rtx != 0
6249 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6250 pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
6252 /* Make POS_RTX unless we already have it and it is correct. If we don't
6253 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6255 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6256 pos_rtx = orig_pos_rtx;
6258 else if (pos_rtx == 0)
6259 pos_rtx = GEN_INT (pos);
6261 /* Make the required operation. See if we can use existing rtx. */
6262 new = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6263 extraction_mode, inner, GEN_INT (len), pos_rtx);
6265 new = gen_lowpart_for_combine (mode, new);
6270 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6271 with any other operations in X. Return X without that shift if so. */
6274 extract_left_shift (x, count)
6278 enum rtx_code code = GET_CODE (x);
6279 enum machine_mode mode = GET_MODE (x);
6285 /* This is the shift itself. If it is wide enough, we will return
6286 either the value being shifted if the shift count is equal to
6287 COUNT or a shift for the difference. */
6288 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6289 && INTVAL (XEXP (x, 1)) >= count)
6290 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6291 INTVAL (XEXP (x, 1)) - count);
6295 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6296 return simplify_gen_unary (code, mode, tem, mode);
6300 case PLUS: case IOR: case XOR: case AND:
6301 /* If we can safely shift this constant and we find the inner shift,
6302 make a new operation. */
6303 if (GET_CODE (XEXP (x,1)) == CONST_INT
6304 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6305 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6306 return gen_binary (code, mode, tem,
6307 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6318 /* Look at the expression rooted at X. Look for expressions
6319 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6320 Form these expressions.
6322 Return the new rtx, usually just X.
6324 Also, for machines like the VAX that don't have logical shift insns,
6325 try to convert logical to arithmetic shift operations in cases where
6326 they are equivalent. This undoes the canonicalizations to logical
6327 shifts done elsewhere.
6329 We try, as much as possible, to re-use rtl expressions to save memory.
6331 IN_CODE says what kind of expression we are processing. Normally, it is
6332 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6333 being kludges), it is MEM. When processing the arguments of a comparison
6334 or a COMPARE against zero, it is COMPARE. */
6337 make_compound_operation (x, in_code)
6339 enum rtx_code in_code;
6341 enum rtx_code code = GET_CODE (x);
6342 enum machine_mode mode = GET_MODE (x);
6343 int mode_width = GET_MODE_BITSIZE (mode);
6345 enum rtx_code next_code;
6351 /* Select the code to be used in recursive calls. Once we are inside an
6352 address, we stay there. If we have a comparison, set to COMPARE,
6353 but once inside, go back to our default of SET. */
6355 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6356 : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
6357 && XEXP (x, 1) == const0_rtx) ? COMPARE
6358 : in_code == COMPARE ? SET : in_code);
6360 /* Process depending on the code of this operation. If NEW is set
6361 non-zero, it will be returned. */
6366 /* Convert shifts by constants into multiplications if inside
6368 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6369 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6370 && INTVAL (XEXP (x, 1)) >= 0)
6372 new = make_compound_operation (XEXP (x, 0), next_code);
6373 new = gen_rtx_MULT (mode, new,
6374 GEN_INT ((HOST_WIDE_INT) 1
6375 << INTVAL (XEXP (x, 1))));
6380 /* If the second operand is not a constant, we can't do anything
6382 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6385 /* If the constant is a power of two minus one and the first operand
6386 is a logical right shift, make an extraction. */
6387 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6388 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6390 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6391 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6392 0, in_code == COMPARE);
6395 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6396 else if (GET_CODE (XEXP (x, 0)) == SUBREG
6397 && subreg_lowpart_p (XEXP (x, 0))
6398 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6399 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6401 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6403 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6404 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6405 0, in_code == COMPARE);
6407 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6408 else if ((GET_CODE (XEXP (x, 0)) == XOR
6409 || GET_CODE (XEXP (x, 0)) == IOR)
6410 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6411 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6412 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6414 /* Apply the distributive law, and then try to make extractions. */
6415 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
6416 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6418 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6420 new = make_compound_operation (new, in_code);
6423 /* If we are have (and (rotate X C) M) and C is larger than the number
6424 of bits in M, this is an extraction. */
6426 else if (GET_CODE (XEXP (x, 0)) == ROTATE
6427 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6428 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6429 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6431 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6432 new = make_extraction (mode, new,
6433 (GET_MODE_BITSIZE (mode)
6434 - INTVAL (XEXP (XEXP (x, 0), 1))),
6435 NULL_RTX, i, 1, 0, in_code == COMPARE);
6438 /* On machines without logical shifts, if the operand of the AND is
6439 a logical shift and our mask turns off all the propagated sign
6440 bits, we can replace the logical shift with an arithmetic shift. */
6441 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6442 && !have_insn_for (LSHIFTRT, mode)
6443 && have_insn_for (ASHIFTRT, mode)
6444 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6445 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6446 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6447 && mode_width <= HOST_BITS_PER_WIDE_INT)
6449 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6451 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6452 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6454 gen_rtx_ASHIFTRT (mode,
6455 make_compound_operation
6456 (XEXP (XEXP (x, 0), 0), next_code),
6457 XEXP (XEXP (x, 0), 1)));
6460 /* If the constant is one less than a power of two, this might be
6461 representable by an extraction even if no shift is present.
6462 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6463 we are in a COMPARE. */
6464 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6465 new = make_extraction (mode,
6466 make_compound_operation (XEXP (x, 0),
6468 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6470 /* If we are in a comparison and this is an AND with a power of two,
6471 convert this into the appropriate bit extract. */
6472 else if (in_code == COMPARE
6473 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6474 new = make_extraction (mode,
6475 make_compound_operation (XEXP (x, 0),
6477 i, NULL_RTX, 1, 1, 0, 1);
6482 /* If the sign bit is known to be zero, replace this with an
6483 arithmetic shift. */
6484 if (have_insn_for (ASHIFTRT, mode)
6485 && ! have_insn_for (LSHIFTRT, mode)
6486 && mode_width <= HOST_BITS_PER_WIDE_INT
6487 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6489 new = gen_rtx_ASHIFTRT (mode,
6490 make_compound_operation (XEXP (x, 0),
6496 /* ... fall through ... */
6502 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6503 this is a SIGN_EXTRACT. */
6504 if (GET_CODE (rhs) == CONST_INT
6505 && GET_CODE (lhs) == ASHIFT
6506 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6507 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6509 new = make_compound_operation (XEXP (lhs, 0), next_code);
6510 new = make_extraction (mode, new,
6511 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6512 NULL_RTX, mode_width - INTVAL (rhs),
6513 code == LSHIFTRT, 0, in_code == COMPARE);
6517 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6518 If so, try to merge the shifts into a SIGN_EXTEND. We could
6519 also do this for some cases of SIGN_EXTRACT, but it doesn't
6520 seem worth the effort; the case checked for occurs on Alpha. */
6522 if (GET_RTX_CLASS (GET_CODE (lhs)) != 'o'
6523 && ! (GET_CODE (lhs) == SUBREG
6524 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs))) == 'o'))
6525 && GET_CODE (rhs) == CONST_INT
6526 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6527 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6528 new = make_extraction (mode, make_compound_operation (new, next_code),
6529 0, NULL_RTX, mode_width - INTVAL (rhs),
6530 code == LSHIFTRT, 0, in_code == COMPARE);
6535 /* Call ourselves recursively on the inner expression. If we are
6536 narrowing the object and it has a different RTL code from
6537 what it originally did, do this SUBREG as a force_to_mode. */
6539 tem = make_compound_operation (SUBREG_REG (x), in_code);
6540 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6541 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6542 && subreg_lowpart_p (x))
6544 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
6547 /* If we have something other than a SUBREG, we might have
6548 done an expansion, so rerun ourselves. */
6549 if (GET_CODE (newer) != SUBREG)
6550 newer = make_compound_operation (newer, in_code);
6555 /* If this is a paradoxical subreg, and the new code is a sign or
6556 zero extension, omit the subreg and widen the extension. If it
6557 is a regular subreg, we can still get rid of the subreg by not
6558 widening so much, or in fact removing the extension entirely. */
6559 if ((GET_CODE (tem) == SIGN_EXTEND
6560 || GET_CODE (tem) == ZERO_EXTEND)
6561 && subreg_lowpart_p (x))
6563 if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (tem))
6564 || (GET_MODE_SIZE (mode) >
6565 GET_MODE_SIZE (GET_MODE (XEXP (tem, 0)))))
6566 tem = gen_rtx_fmt_e (GET_CODE (tem), mode, XEXP (tem, 0));
6568 tem = gen_lowpart_for_combine (mode, XEXP (tem, 0));
6579 x = gen_lowpart_for_combine (mode, new);
6580 code = GET_CODE (x);
6583 /* Now recursively process each operand of this operation. */
6584 fmt = GET_RTX_FORMAT (code);
6585 for (i = 0; i < GET_RTX_LENGTH (code); i++)
6588 new = make_compound_operation (XEXP (x, i), next_code);
6589 SUBST (XEXP (x, i), new);
6595 /* Given M see if it is a value that would select a field of bits
6596 within an item, but not the entire word. Return -1 if not.
6597 Otherwise, return the starting position of the field, where 0 is the
6600 *PLEN is set to the length of the field. */
6603 get_pos_from_mask (m, plen)
6604 unsigned HOST_WIDE_INT m;
6605 unsigned HOST_WIDE_INT *plen;
6607 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6608 int pos = exact_log2 (m & -m);
6614 /* Now shift off the low-order zero bits and see if we have a power of
6616 len = exact_log2 ((m >> pos) + 1);
6625 /* See if X can be simplified knowing that we will only refer to it in
6626 MODE and will only refer to those bits that are nonzero in MASK.
6627 If other bits are being computed or if masking operations are done
6628 that select a superset of the bits in MASK, they can sometimes be
6631 Return a possibly simplified expression, but always convert X to
6632 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6634 Also, if REG is non-zero and X is a register equal in value to REG,
6637 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6638 are all off in X. This is used when X will be complemented, by either
6639 NOT, NEG, or XOR. */
6642 force_to_mode (x, mode, mask, reg, just_select)
6644 enum machine_mode mode;
6645 unsigned HOST_WIDE_INT mask;
6649 enum rtx_code code = GET_CODE (x);
6650 int next_select = just_select || code == XOR || code == NOT || code == NEG;
6651 enum machine_mode op_mode;
6652 unsigned HOST_WIDE_INT fuller_mask, nonzero;
6655 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6656 code below will do the wrong thing since the mode of such an
6657 expression is VOIDmode.
6659 Also do nothing if X is a CLOBBER; this can happen if X was
6660 the return value from a call to gen_lowpart_for_combine. */
6661 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
6664 /* We want to perform the operation is its present mode unless we know
6665 that the operation is valid in MODE, in which case we do the operation
6667 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6668 && have_insn_for (code, mode))
6669 ? mode : GET_MODE (x));
6671 /* It is not valid to do a right-shift in a narrower mode
6672 than the one it came in with. */
6673 if ((code == LSHIFTRT || code == ASHIFTRT)
6674 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6675 op_mode = GET_MODE (x);
6677 /* Truncate MASK to fit OP_MODE. */
6679 mask &= GET_MODE_MASK (op_mode);
6681 /* When we have an arithmetic operation, or a shift whose count we
6682 do not know, we need to assume that all bit the up to the highest-order
6683 bit in MASK will be needed. This is how we form such a mask. */
6685 fuller_mask = (GET_MODE_BITSIZE (op_mode) >= HOST_BITS_PER_WIDE_INT
6686 ? GET_MODE_MASK (op_mode)
6687 : (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
6690 fuller_mask = ~(HOST_WIDE_INT) 0;
6692 /* Determine what bits of X are guaranteed to be (non)zero. */
6693 nonzero = nonzero_bits (x, mode);
6695 /* If none of the bits in X are needed, return a zero. */
6696 if (! just_select && (nonzero & mask) == 0)
6699 /* If X is a CONST_INT, return a new one. Do this here since the
6700 test below will fail. */
6701 if (GET_CODE (x) == CONST_INT)
6703 HOST_WIDE_INT cval = INTVAL (x) & mask;
6704 int width = GET_MODE_BITSIZE (mode);
6706 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6707 number, sign extend it. */
6708 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6709 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6710 cval |= (HOST_WIDE_INT) -1 << width;
6712 return GEN_INT (cval);
6715 /* If X is narrower than MODE and we want all the bits in X's mode, just
6716 get X in the proper mode. */
6717 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6718 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
6719 return gen_lowpart_for_combine (mode, x);
6721 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6722 MASK are already known to be zero in X, we need not do anything. */
6723 if (GET_MODE (x) == mode && code != SUBREG && (~mask & nonzero) == 0)
6729 /* If X is a (clobber (const_int)), return it since we know we are
6730 generating something that won't match. */
6734 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6735 spanned the boundary of the MEM. If we are now masking so it is
6736 within that boundary, we don't need the USE any more. */
6737 if (! BITS_BIG_ENDIAN
6738 && (mask & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6739 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6746 x = expand_compound_operation (x);
6747 if (GET_CODE (x) != code)
6748 return force_to_mode (x, mode, mask, reg, next_select);
6752 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
6753 || rtx_equal_p (reg, get_last_value (x))))
6758 if (subreg_lowpart_p (x)
6759 /* We can ignore the effect of this SUBREG if it narrows the mode or
6760 if the constant masks to zero all the bits the mode doesn't
6762 && ((GET_MODE_SIZE (GET_MODE (x))
6763 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6765 & GET_MODE_MASK (GET_MODE (x))
6766 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6767 return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
6771 /* If this is an AND with a constant, convert it into an AND
6772 whose constant is the AND of that constant with MASK. If it
6773 remains an AND of MASK, delete it since it is redundant. */
6775 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6777 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6778 mask & INTVAL (XEXP (x, 1)));
6780 /* If X is still an AND, see if it is an AND with a mask that
6781 is just some low-order bits. If so, and it is MASK, we don't
6784 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6785 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
6786 == (HOST_WIDE_INT) mask))
6789 /* If it remains an AND, try making another AND with the bits
6790 in the mode mask that aren't in MASK turned on. If the
6791 constant in the AND is wide enough, this might make a
6792 cheaper constant. */
6794 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6795 && GET_MODE_MASK (GET_MODE (x)) != mask
6796 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
6798 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6799 | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
6800 int width = GET_MODE_BITSIZE (GET_MODE (x));
6803 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6804 number, sign extend it. */
6805 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6806 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6807 cval |= (HOST_WIDE_INT) -1 << width;
6809 y = gen_binary (AND, GET_MODE (x), XEXP (x, 0), GEN_INT (cval));
6810 if (rtx_cost (y, SET) < rtx_cost (x, SET))
6820 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6821 low-order bits (as in an alignment operation) and FOO is already
6822 aligned to that boundary, mask C1 to that boundary as well.
6823 This may eliminate that PLUS and, later, the AND. */
6826 unsigned int width = GET_MODE_BITSIZE (mode);
6827 unsigned HOST_WIDE_INT smask = mask;
6829 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6830 number, sign extend it. */
6832 if (width < HOST_BITS_PER_WIDE_INT
6833 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6834 smask |= (HOST_WIDE_INT) -1 << width;
6836 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6837 && exact_log2 (- smask) >= 0
6838 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
6839 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
6840 return force_to_mode (plus_constant (XEXP (x, 0),
6841 (INTVAL (XEXP (x, 1)) & smask)),
6842 mode, smask, reg, next_select);
6845 /* ... fall through ... */
6848 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6849 most significant bit in MASK since carries from those bits will
6850 affect the bits we are interested in. */
6855 /* If X is (minus C Y) where C's least set bit is larger than any bit
6856 in the mask, then we may replace with (neg Y). */
6857 if (GET_CODE (XEXP (x, 0)) == CONST_INT
6858 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
6859 & -INTVAL (XEXP (x, 0))))
6862 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
6864 return force_to_mode (x, mode, mask, reg, next_select);
6867 /* Similarly, if C contains every bit in the mask, then we may
6868 replace with (not Y). */
6869 if (GET_CODE (XEXP (x, 0)) == CONST_INT
6870 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) mask)
6871 == INTVAL (XEXP (x, 0))))
6873 x = simplify_gen_unary (NOT, GET_MODE (x),
6874 XEXP (x, 1), GET_MODE (x));
6875 return force_to_mode (x, mode, mask, reg, next_select);
6883 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6884 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6885 operation which may be a bitfield extraction. Ensure that the
6886 constant we form is not wider than the mode of X. */
6888 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6889 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6890 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6891 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6892 && GET_CODE (XEXP (x, 1)) == CONST_INT
6893 && ((INTVAL (XEXP (XEXP (x, 0), 1))
6894 + floor_log2 (INTVAL (XEXP (x, 1))))
6895 < GET_MODE_BITSIZE (GET_MODE (x)))
6896 && (INTVAL (XEXP (x, 1))
6897 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
6899 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
6900 << INTVAL (XEXP (XEXP (x, 0), 1)));
6901 temp = gen_binary (GET_CODE (x), GET_MODE (x),
6902 XEXP (XEXP (x, 0), 0), temp);
6903 x = gen_binary (LSHIFTRT, GET_MODE (x), temp,
6904 XEXP (XEXP (x, 0), 1));
6905 return force_to_mode (x, mode, mask, reg, next_select);
6909 /* For most binary operations, just propagate into the operation and
6910 change the mode if we have an operation of that mode. */
6912 op0 = gen_lowpart_for_combine (op_mode,
6913 force_to_mode (XEXP (x, 0), mode, mask,
6915 op1 = gen_lowpart_for_combine (op_mode,
6916 force_to_mode (XEXP (x, 1), mode, mask,
6919 /* If OP1 is a CONST_INT and X is an IOR or XOR, clear bits outside
6920 MASK since OP1 might have been sign-extended but we never want
6921 to turn on extra bits, since combine might have previously relied
6922 on them being off. */
6923 if (GET_CODE (op1) == CONST_INT && (code == IOR || code == XOR)
6924 && (INTVAL (op1) & mask) != 0)
6925 op1 = GEN_INT (INTVAL (op1) & mask);
6927 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6928 x = gen_binary (code, op_mode, op0, op1);
6932 /* For left shifts, do the same, but just for the first operand.
6933 However, we cannot do anything with shifts where we cannot
6934 guarantee that the counts are smaller than the size of the mode
6935 because such a count will have a different meaning in a
6938 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
6939 && INTVAL (XEXP (x, 1)) >= 0
6940 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
6941 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
6942 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
6943 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
6946 /* If the shift count is a constant and we can do arithmetic in
6947 the mode of the shift, refine which bits we need. Otherwise, use the
6948 conservative form of the mask. */
6949 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6950 && INTVAL (XEXP (x, 1)) >= 0
6951 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
6952 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6953 mask >>= INTVAL (XEXP (x, 1));
6957 op0 = gen_lowpart_for_combine (op_mode,
6958 force_to_mode (XEXP (x, 0), op_mode,
6959 mask, reg, next_select));
6961 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
6962 x = gen_binary (code, op_mode, op0, XEXP (x, 1));
6966 /* Here we can only do something if the shift count is a constant,
6967 this shift constant is valid for the host, and we can do arithmetic
6970 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6971 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6972 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6974 rtx inner = XEXP (x, 0);
6975 unsigned HOST_WIDE_INT inner_mask;
6977 /* Select the mask of the bits we need for the shift operand. */
6978 inner_mask = mask << INTVAL (XEXP (x, 1));
6980 /* We can only change the mode of the shift if we can do arithmetic
6981 in the mode of the shift and INNER_MASK is no wider than the
6982 width of OP_MODE. */
6983 if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT
6984 || (inner_mask & ~GET_MODE_MASK (op_mode)) != 0)
6985 op_mode = GET_MODE (x);
6987 inner = force_to_mode (inner, op_mode, inner_mask, reg, next_select);
6989 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
6990 x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
6993 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
6994 shift and AND produces only copies of the sign bit (C2 is one less
6995 than a power of two), we can do this with just a shift. */
6997 if (GET_CODE (x) == LSHIFTRT
6998 && GET_CODE (XEXP (x, 1)) == CONST_INT
6999 /* The shift puts one of the sign bit copies in the least significant
7001 && ((INTVAL (XEXP (x, 1))
7002 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7003 >= GET_MODE_BITSIZE (GET_MODE (x)))
7004 && exact_log2 (mask + 1) >= 0
7005 /* Number of bits left after the shift must be more than the mask
7007 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7008 <= GET_MODE_BITSIZE (GET_MODE (x)))
7009 /* Must be more sign bit copies than the mask needs. */
7010 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7011 >= exact_log2 (mask + 1)))
7012 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7013 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7014 - exact_log2 (mask + 1)));
7019 /* If we are just looking for the sign bit, we don't need this shift at
7020 all, even if it has a variable count. */
7021 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7022 && (mask == ((unsigned HOST_WIDE_INT) 1
7023 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7024 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7026 /* If this is a shift by a constant, get a mask that contains those bits
7027 that are not copies of the sign bit. We then have two cases: If
7028 MASK only includes those bits, this can be a logical shift, which may
7029 allow simplifications. If MASK is a single-bit field not within
7030 those bits, we are requesting a copy of the sign bit and hence can
7031 shift the sign bit to the appropriate location. */
7033 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
7034 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7038 /* If the considered data is wider than HOST_WIDE_INT, we can't
7039 represent a mask for all its bits in a single scalar.
7040 But we only care about the lower bits, so calculate these. */
7042 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7044 nonzero = ~(HOST_WIDE_INT) 0;
7046 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7047 is the number of bits a full-width mask would have set.
7048 We need only shift if these are fewer than nonzero can
7049 hold. If not, we must keep all bits set in nonzero. */
7051 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7052 < HOST_BITS_PER_WIDE_INT)
7053 nonzero >>= INTVAL (XEXP (x, 1))
7054 + HOST_BITS_PER_WIDE_INT
7055 - GET_MODE_BITSIZE (GET_MODE (x)) ;
7059 nonzero = GET_MODE_MASK (GET_MODE (x));
7060 nonzero >>= INTVAL (XEXP (x, 1));
7063 if ((mask & ~nonzero) == 0
7064 || (i = exact_log2 (mask)) >= 0)
7066 x = simplify_shift_const
7067 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7068 i < 0 ? INTVAL (XEXP (x, 1))
7069 : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7071 if (GET_CODE (x) != ASHIFTRT)
7072 return force_to_mode (x, mode, mask, reg, next_select);
7076 /* If MASK is 1, convert this to a LSHIFTRT. This can be done
7077 even if the shift count isn't a constant. */
7079 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1));
7083 /* If this is a zero- or sign-extension operation that just affects bits
7084 we don't care about, remove it. Be sure the call above returned
7085 something that is still a shift. */
7087 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7088 && GET_CODE (XEXP (x, 1)) == CONST_INT
7089 && INTVAL (XEXP (x, 1)) >= 0
7090 && (INTVAL (XEXP (x, 1))
7091 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7092 && GET_CODE (XEXP (x, 0)) == ASHIFT
7093 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7094 && INTVAL (XEXP (XEXP (x, 0), 1)) == INTVAL (XEXP (x, 1)))
7095 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7102 /* If the shift count is constant and we can do computations
7103 in the mode of X, compute where the bits we care about are.
7104 Otherwise, we can't do anything. Don't change the mode of
7105 the shift or propagate MODE into the shift, though. */
7106 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7107 && INTVAL (XEXP (x, 1)) >= 0)
7109 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7110 GET_MODE (x), GEN_INT (mask),
7112 if (temp && GET_CODE(temp) == CONST_INT)
7114 force_to_mode (XEXP (x, 0), GET_MODE (x),
7115 INTVAL (temp), reg, next_select));
7120 /* If we just want the low-order bit, the NEG isn't needed since it
7121 won't change the low-order bit. */
7123 return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
7125 /* We need any bits less significant than the most significant bit in
7126 MASK since carries from those bits will affect the bits we are
7132 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7133 same as the XOR case above. Ensure that the constant we form is not
7134 wider than the mode of X. */
7136 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7137 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7138 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7139 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7140 < GET_MODE_BITSIZE (GET_MODE (x)))
7141 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7143 temp = GEN_INT (mask << INTVAL (XEXP (XEXP (x, 0), 1)));
7144 temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp);
7145 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1));
7147 return force_to_mode (x, mode, mask, reg, next_select);
7150 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7151 use the full mask inside the NOT. */
7155 op0 = gen_lowpart_for_combine (op_mode,
7156 force_to_mode (XEXP (x, 0), mode, mask,
7158 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7159 x = simplify_gen_unary (code, op_mode, op0, op_mode);
7163 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7164 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7165 which is equal to STORE_FLAG_VALUE. */
7166 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7167 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7168 && nonzero_bits (XEXP (x, 0), mode) == STORE_FLAG_VALUE)
7169 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7174 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7175 written in a narrower mode. We play it safe and do not do so. */
7178 gen_lowpart_for_combine (GET_MODE (x),
7179 force_to_mode (XEXP (x, 1), mode,
7180 mask, reg, next_select)));
7182 gen_lowpart_for_combine (GET_MODE (x),
7183 force_to_mode (XEXP (x, 2), mode,
7184 mask, reg,next_select)));
7191 /* Ensure we return a value of the proper mode. */
7192 return gen_lowpart_for_combine (mode, x);
7195 /* Return nonzero if X is an expression that has one of two values depending on
7196 whether some other value is zero or nonzero. In that case, we return the
7197 value that is being tested, *PTRUE is set to the value if the rtx being
7198 returned has a nonzero value, and *PFALSE is set to the other alternative.
7200 If we return zero, we set *PTRUE and *PFALSE to X. */
7203 if_then_else_cond (x, ptrue, pfalse)
7205 rtx *ptrue, *pfalse;
7207 enum machine_mode mode = GET_MODE (x);
7208 enum rtx_code code = GET_CODE (x);
7209 rtx cond0, cond1, true0, true1, false0, false1;
7210 unsigned HOST_WIDE_INT nz;
7212 /* If we are comparing a value against zero, we are done. */
7213 if ((code == NE || code == EQ)
7214 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 0)
7216 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7217 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7221 /* If this is a unary operation whose operand has one of two values, apply
7222 our opcode to compute those values. */
7223 else if (GET_RTX_CLASS (code) == '1'
7224 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7226 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
7227 *pfalse = simplify_gen_unary (code, mode, false0,
7228 GET_MODE (XEXP (x, 0)));
7232 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7233 make can't possibly match and would suppress other optimizations. */
7234 else if (code == COMPARE)
7237 /* If this is a binary operation, see if either side has only one of two
7238 values. If either one does or if both do and they are conditional on
7239 the same value, compute the new true and false values. */
7240 else if (GET_RTX_CLASS (code) == 'c' || GET_RTX_CLASS (code) == '2'
7241 || GET_RTX_CLASS (code) == '<')
7243 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7244 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7246 if ((cond0 != 0 || cond1 != 0)
7247 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7249 /* If if_then_else_cond returned zero, then true/false are the
7250 same rtl. We must copy one of them to prevent invalid rtl
7253 true0 = copy_rtx (true0);
7254 else if (cond1 == 0)
7255 true1 = copy_rtx (true1);
7257 *ptrue = gen_binary (code, mode, true0, true1);
7258 *pfalse = gen_binary (code, mode, false0, false1);
7259 return cond0 ? cond0 : cond1;
7262 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7263 operands is zero when the other is non-zero, and vice-versa,
7264 and STORE_FLAG_VALUE is 1 or -1. */
7266 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7267 && (code == PLUS || code == IOR || code == XOR || code == MINUS
7269 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7271 rtx op0 = XEXP (XEXP (x, 0), 1);
7272 rtx op1 = XEXP (XEXP (x, 1), 1);
7274 cond0 = XEXP (XEXP (x, 0), 0);
7275 cond1 = XEXP (XEXP (x, 1), 0);
7277 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7278 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7279 && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1)
7280 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7281 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7282 || ((swap_condition (GET_CODE (cond0))
7283 == combine_reversed_comparison_code (cond1))
7284 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7285 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7286 && ! side_effects_p (x))
7288 *ptrue = gen_binary (MULT, mode, op0, const_true_rtx);
7289 *pfalse = gen_binary (MULT, mode,
7291 ? simplify_gen_unary (NEG, mode, op1,
7299 /* Similarly for MULT, AND and UMIN, except that for these the result
7301 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7302 && (code == MULT || code == AND || code == UMIN)
7303 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7305 cond0 = XEXP (XEXP (x, 0), 0);
7306 cond1 = XEXP (XEXP (x, 1), 0);
7308 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7309 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7310 && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1)
7311 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7312 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7313 || ((swap_condition (GET_CODE (cond0))
7314 == combine_reversed_comparison_code (cond1))
7315 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7316 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7317 && ! side_effects_p (x))
7319 *ptrue = *pfalse = const0_rtx;
7325 else if (code == IF_THEN_ELSE)
7327 /* If we have IF_THEN_ELSE already, extract the condition and
7328 canonicalize it if it is NE or EQ. */
7329 cond0 = XEXP (x, 0);
7330 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7331 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7332 return XEXP (cond0, 0);
7333 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7335 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7336 return XEXP (cond0, 0);
7342 /* If X is a SUBREG, we can narrow both the true and false values
7343 if the inner expression, if there is a condition. */
7344 else if (code == SUBREG
7345 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7348 *ptrue = simplify_gen_subreg (mode, true0,
7349 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7350 *pfalse = simplify_gen_subreg (mode, false0,
7351 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7356 /* If X is a constant, this isn't special and will cause confusions
7357 if we treat it as such. Likewise if it is equivalent to a constant. */
7358 else if (CONSTANT_P (x)
7359 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7362 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7363 will be least confusing to the rest of the compiler. */
7364 else if (mode == BImode)
7366 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
7370 /* If X is known to be either 0 or -1, those are the true and
7371 false values when testing X. */
7372 else if (x == constm1_rtx || x == const0_rtx
7373 || (mode != VOIDmode
7374 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
7376 *ptrue = constm1_rtx, *pfalse = const0_rtx;
7380 /* Likewise for 0 or a single bit. */
7381 else if (mode != VOIDmode
7382 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7383 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7385 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
7389 /* Otherwise fail; show no condition with true and false values the same. */
7390 *ptrue = *pfalse = x;
7394 /* Return the value of expression X given the fact that condition COND
7395 is known to be true when applied to REG as its first operand and VAL
7396 as its second. X is known to not be shared and so can be modified in
7399 We only handle the simplest cases, and specifically those cases that
7400 arise with IF_THEN_ELSE expressions. */
7403 known_cond (x, cond, reg, val)
7408 enum rtx_code code = GET_CODE (x);
7413 if (side_effects_p (x))
7416 /* If either operand of the condition is a floating point value,
7417 then we have to avoid collapsing an EQ comparison. */
7419 && rtx_equal_p (x, reg)
7420 && ! FLOAT_MODE_P (GET_MODE (x))
7421 && ! FLOAT_MODE_P (GET_MODE (val)))
7424 if (cond == UNEQ && rtx_equal_p (x, reg))
7427 /* If X is (abs REG) and we know something about REG's relationship
7428 with zero, we may be able to simplify this. */
7430 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
7433 case GE: case GT: case EQ:
7436 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
7438 GET_MODE (XEXP (x, 0)));
7443 /* The only other cases we handle are MIN, MAX, and comparisons if the
7444 operands are the same as REG and VAL. */
7446 else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
7448 if (rtx_equal_p (XEXP (x, 0), val))
7449 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
7451 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
7453 if (GET_RTX_CLASS (code) == '<')
7455 if (comparison_dominates_p (cond, code))
7456 return const_true_rtx;
7458 code = combine_reversed_comparison_code (x);
7460 && comparison_dominates_p (cond, code))
7465 else if (code == SMAX || code == SMIN
7466 || code == UMIN || code == UMAX)
7468 int unsignedp = (code == UMIN || code == UMAX);
7470 /* Do not reverse the condition when it is NE or EQ.
7471 This is because we cannot conclude anything about
7472 the value of 'SMAX (x, y)' when x is not equal to y,
7473 but we can when x equals y. */
7474 if ((code == SMAX || code == UMAX)
7475 && ! (cond == EQ || cond == NE))
7476 cond = reverse_condition (cond);
7481 return unsignedp ? x : XEXP (x, 1);
7483 return unsignedp ? x : XEXP (x, 0);
7485 return unsignedp ? XEXP (x, 1) : x;
7487 return unsignedp ? XEXP (x, 0) : x;
7494 else if (code == SUBREG)
7496 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
7497 rtx new, r = known_cond (SUBREG_REG (x), cond, reg, val);
7499 if (SUBREG_REG (x) != r)
7501 /* We must simplify subreg here, before we lose track of the
7502 original inner_mode. */
7503 new = simplify_subreg (GET_MODE (x), r,
7504 inner_mode, SUBREG_BYTE (x));
7508 SUBST (SUBREG_REG (x), r);
7513 /* We don't have to handle SIGN_EXTEND here, because even in the
7514 case of replacing something with a modeless CONST_INT, a
7515 CONST_INT is already (supposed to be) a valid sign extension for
7516 its narrower mode, which implies it's already properly
7517 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
7518 story is different. */
7519 else if (code == ZERO_EXTEND)
7521 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
7522 rtx new, r = known_cond (XEXP (x, 0), cond, reg, val);
7524 if (XEXP (x, 0) != r)
7526 /* We must simplify the zero_extend here, before we lose
7527 track of the original inner_mode. */
7528 new = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
7533 SUBST (XEXP (x, 0), r);
7539 fmt = GET_RTX_FORMAT (code);
7540 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7543 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7544 else if (fmt[i] == 'E')
7545 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7546 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7553 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7554 assignment as a field assignment. */
7557 rtx_equal_for_field_assignment_p (x, y)
7561 if (x == y || rtx_equal_p (x, y))
7564 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7567 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7568 Note that all SUBREGs of MEM are paradoxical; otherwise they
7569 would have been rewritten. */
7570 if (GET_CODE (x) == MEM && GET_CODE (y) == SUBREG
7571 && GET_CODE (SUBREG_REG (y)) == MEM
7572 && rtx_equal_p (SUBREG_REG (y),
7573 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y)), x)))
7576 if (GET_CODE (y) == MEM && GET_CODE (x) == SUBREG
7577 && GET_CODE (SUBREG_REG (x)) == MEM
7578 && rtx_equal_p (SUBREG_REG (x),
7579 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x)), y)))
7582 /* We used to see if get_last_value of X and Y were the same but that's
7583 not correct. In one direction, we'll cause the assignment to have
7584 the wrong destination and in the case, we'll import a register into this
7585 insn that might have already have been dead. So fail if none of the
7586 above cases are true. */
7590 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7591 Return that assignment if so.
7593 We only handle the most common cases. */
7596 make_field_assignment (x)
7599 rtx dest = SET_DEST (x);
7600 rtx src = SET_SRC (x);
7605 unsigned HOST_WIDE_INT len;
7607 enum machine_mode mode;
7609 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7610 a clear of a one-bit field. We will have changed it to
7611 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7614 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7615 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7616 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7617 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7619 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7622 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7626 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7627 && subreg_lowpart_p (XEXP (src, 0))
7628 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7629 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7630 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7631 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7632 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7634 assign = make_extraction (VOIDmode, dest, 0,
7635 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7638 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7642 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7644 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7645 && XEXP (XEXP (src, 0), 0) == const1_rtx
7646 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7648 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7651 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
7655 /* The other case we handle is assignments into a constant-position
7656 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7657 a mask that has all one bits except for a group of zero bits and
7658 OTHER is known to have zeros where C1 has ones, this is such an
7659 assignment. Compute the position and length from C1. Shift OTHER
7660 to the appropriate position, force it to the required mode, and
7661 make the extraction. Check for the AND in both operands. */
7663 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
7666 rhs = expand_compound_operation (XEXP (src, 0));
7667 lhs = expand_compound_operation (XEXP (src, 1));
7669 if (GET_CODE (rhs) == AND
7670 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7671 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7672 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7673 else if (GET_CODE (lhs) == AND
7674 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7675 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7676 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
7680 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
7681 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
7682 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7683 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
7686 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
7690 /* The mode to use for the source is the mode of the assignment, or of
7691 what is inside a possible STRICT_LOW_PART. */
7692 mode = (GET_CODE (assign) == STRICT_LOW_PART
7693 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
7695 /* Shift OTHER right POS places and make it the source, restricting it
7696 to the proper length and mode. */
7698 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
7699 GET_MODE (src), other, pos),
7701 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7702 ? ~(unsigned HOST_WIDE_INT) 0
7703 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7706 return gen_rtx_SET (VOIDmode, assign, src);
7709 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7713 apply_distributive_law (x)
7716 enum rtx_code code = GET_CODE (x);
7717 rtx lhs, rhs, other;
7719 enum rtx_code inner_code;
7721 /* Distributivity is not true for floating point.
7722 It can change the value. So don't do it.
7723 -- rms and moshier@world.std.com. */
7724 if (FLOAT_MODE_P (GET_MODE (x)))
7727 /* The outer operation can only be one of the following: */
7728 if (code != IOR && code != AND && code != XOR
7729 && code != PLUS && code != MINUS)
7732 lhs = XEXP (x, 0), rhs = XEXP (x, 1);
7734 /* If either operand is a primitive we can't do anything, so get out
7736 if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
7737 || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
7740 lhs = expand_compound_operation (lhs);
7741 rhs = expand_compound_operation (rhs);
7742 inner_code = GET_CODE (lhs);
7743 if (inner_code != GET_CODE (rhs))
7746 /* See if the inner and outer operations distribute. */
7753 /* These all distribute except over PLUS. */
7754 if (code == PLUS || code == MINUS)
7759 if (code != PLUS && code != MINUS)
7764 /* This is also a multiply, so it distributes over everything. */
7768 /* Non-paradoxical SUBREGs distributes over all operations, provided
7769 the inner modes and byte offsets are the same, this is an extraction
7770 of a low-order part, we don't convert an fp operation to int or
7771 vice versa, and we would not be converting a single-word
7772 operation into a multi-word operation. The latter test is not
7773 required, but it prevents generating unneeded multi-word operations.
7774 Some of the previous tests are redundant given the latter test, but
7775 are retained because they are required for correctness.
7777 We produce the result slightly differently in this case. */
7779 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7780 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
7781 || ! subreg_lowpart_p (lhs)
7782 || (GET_MODE_CLASS (GET_MODE (lhs))
7783 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
7784 || (GET_MODE_SIZE (GET_MODE (lhs))
7785 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
7786 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
7789 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
7790 SUBREG_REG (lhs), SUBREG_REG (rhs));
7791 return gen_lowpart_for_combine (GET_MODE (x), tem);
7797 /* Set LHS and RHS to the inner operands (A and B in the example
7798 above) and set OTHER to the common operand (C in the example).
7799 These is only one way to do this unless the inner operation is
7801 if (GET_RTX_CLASS (inner_code) == 'c'
7802 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
7803 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
7804 else if (GET_RTX_CLASS (inner_code) == 'c'
7805 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
7806 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
7807 else if (GET_RTX_CLASS (inner_code) == 'c'
7808 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
7809 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
7810 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
7811 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
7815 /* Form the new inner operation, seeing if it simplifies first. */
7816 tem = gen_binary (code, GET_MODE (x), lhs, rhs);
7818 /* There is one exception to the general way of distributing:
7819 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
7820 if (code == XOR && inner_code == IOR)
7823 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
7826 /* We may be able to continuing distributing the result, so call
7827 ourselves recursively on the inner operation before forming the
7828 outer operation, which we return. */
7829 return gen_binary (inner_code, GET_MODE (x),
7830 apply_distributive_law (tem), other);
7833 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7836 Return an equivalent form, if different from X. Otherwise, return X. If
7837 X is zero, we are to always construct the equivalent form. */
7840 simplify_and_const_int (x, mode, varop, constop)
7842 enum machine_mode mode;
7844 unsigned HOST_WIDE_INT constop;
7846 unsigned HOST_WIDE_INT nonzero;
7849 /* Simplify VAROP knowing that we will be only looking at some of the
7852 Note by passing in CONSTOP, we guarantee that the bits not set in
7853 CONSTOP are not significant and will never be examined. We must
7854 ensure that is the case by explicitly masking out those bits
7855 before returning. */
7856 varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
7858 /* If VAROP is a CLOBBER, we will fail so return it. */
7859 if (GET_CODE (varop) == CLOBBER)
7862 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
7863 to VAROP and return the new constant. */
7864 if (GET_CODE (varop) == CONST_INT)
7865 return GEN_INT (trunc_int_for_mode (INTVAL (varop) & constop, mode));
7867 /* See what bits may be nonzero in VAROP. Unlike the general case of
7868 a call to nonzero_bits, here we don't care about bits outside
7871 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
7873 /* Turn off all bits in the constant that are known to already be zero.
7874 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7875 which is tested below. */
7879 /* If we don't have any bits left, return zero. */
7883 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7884 a power of two, we can replace this with a ASHIFT. */
7885 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
7886 && (i = exact_log2 (constop)) >= 0)
7887 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
7889 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7890 or XOR, then try to apply the distributive law. This may eliminate
7891 operations if either branch can be simplified because of the AND.
7892 It may also make some cases more complex, but those cases probably
7893 won't match a pattern either with or without this. */
7895 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
7897 gen_lowpart_for_combine
7899 apply_distributive_law
7900 (gen_binary (GET_CODE (varop), GET_MODE (varop),
7901 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7902 XEXP (varop, 0), constop),
7903 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7904 XEXP (varop, 1), constop))));
7906 /* If VAROP is PLUS, and the constant is a mask of low bite, distribute
7907 the AND and see if one of the operands simplifies to zero. If so, we
7908 may eliminate it. */
7910 if (GET_CODE (varop) == PLUS
7911 && exact_log2 (constop + 1) >= 0)
7915 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
7916 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
7917 if (o0 == const0_rtx)
7919 if (o1 == const0_rtx)
7923 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
7924 if we already had one (just check for the simplest cases). */
7925 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
7926 && GET_MODE (XEXP (x, 0)) == mode
7927 && SUBREG_REG (XEXP (x, 0)) == varop)
7928 varop = XEXP (x, 0);
7930 varop = gen_lowpart_for_combine (mode, varop);
7932 /* If we can't make the SUBREG, try to return what we were given. */
7933 if (GET_CODE (varop) == CLOBBER)
7934 return x ? x : varop;
7936 /* If we are only masking insignificant bits, return VAROP. */
7937 if (constop == nonzero)
7941 /* Otherwise, return an AND. */
7942 constop = trunc_int_for_mode (constop, mode);
7943 /* See how much, if any, of X we can use. */
7944 if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
7945 x = gen_binary (AND, mode, varop, GEN_INT (constop));
7949 if (GET_CODE (XEXP (x, 1)) != CONST_INT
7950 || (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) != constop)
7951 SUBST (XEXP (x, 1), GEN_INT (constop));
7953 SUBST (XEXP (x, 0), varop);
7960 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
7961 We don't let nonzero_bits recur into num_sign_bit_copies, because that
7962 is less useful. We can't allow both, because that results in exponential
7963 run time recursion. There is a nullstone testcase that triggered
7964 this. This macro avoids accidental uses of num_sign_bit_copies. */
7965 #define num_sign_bit_copies()
7967 /* Given an expression, X, compute which bits in X can be non-zero.
7968 We don't care about bits outside of those defined in MODE.
7970 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
7971 a shift, AND, or zero_extract, we can do better. */
7973 static unsigned HOST_WIDE_INT
7974 nonzero_bits (x, mode)
7976 enum machine_mode mode;
7978 unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);
7979 unsigned HOST_WIDE_INT inner_nz;
7981 unsigned int mode_width = GET_MODE_BITSIZE (mode);
7984 /* For floating-point values, assume all bits are needed. */
7985 if (FLOAT_MODE_P (GET_MODE (x)) || FLOAT_MODE_P (mode))
7988 /* If X is wider than MODE, use its mode instead. */
7989 if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
7991 mode = GET_MODE (x);
7992 nonzero = GET_MODE_MASK (mode);
7993 mode_width = GET_MODE_BITSIZE (mode);
7996 if (mode_width > HOST_BITS_PER_WIDE_INT)
7997 /* Our only callers in this case look for single bit values. So
7998 just return the mode mask. Those tests will then be false. */
8001 #ifndef WORD_REGISTER_OPERATIONS
8002 /* If MODE is wider than X, but both are a single word for both the host
8003 and target machines, we can compute this from which bits of the
8004 object might be nonzero in its own mode, taking into account the fact
8005 that on many CISC machines, accessing an object in a wider mode
8006 causes the high-order bits to become undefined. So they are
8007 not known to be zero. */
8009 if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode
8010 && GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD
8011 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
8012 && GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (GET_MODE (x)))
8014 nonzero &= nonzero_bits (x, GET_MODE (x));
8015 nonzero |= GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x));
8020 code = GET_CODE (x);
8024 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8025 /* If pointers extend unsigned and this is a pointer in Pmode, say that
8026 all the bits above ptr_mode are known to be zero. */
8027 if (POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
8029 nonzero &= GET_MODE_MASK (ptr_mode);
8032 /* Include declared information about alignment of pointers. */
8033 /* ??? We don't properly preserve REG_POINTER changes across
8034 pointer-to-integer casts, so we can't trust it except for
8035 things that we know must be pointers. See execute/960116-1.c. */
8036 if ((x == stack_pointer_rtx
8037 || x == frame_pointer_rtx
8038 || x == arg_pointer_rtx)
8039 && REGNO_POINTER_ALIGN (REGNO (x)))
8041 unsigned HOST_WIDE_INT alignment
8042 = REGNO_POINTER_ALIGN (REGNO (x)) / BITS_PER_UNIT;
8044 #ifdef PUSH_ROUNDING
8045 /* If PUSH_ROUNDING is defined, it is possible for the
8046 stack to be momentarily aligned only to that amount,
8047 so we pick the least alignment. */
8048 if (x == stack_pointer_rtx && PUSH_ARGS)
8049 alignment = MIN (PUSH_ROUNDING (1), alignment);
8052 nonzero &= ~(alignment - 1);
8055 /* If X is a register whose nonzero bits value is current, use it.
8056 Otherwise, if X is a register whose value we can find, use that
8057 value. Otherwise, use the previously-computed global nonzero bits
8058 for this register. */
8060 if (reg_last_set_value[REGNO (x)] != 0
8061 && (reg_last_set_mode[REGNO (x)] == mode
8062 || (GET_MODE_CLASS (reg_last_set_mode[REGNO (x)]) == MODE_INT
8063 && GET_MODE_CLASS (mode) == MODE_INT))
8064 && (reg_last_set_label[REGNO (x)] == label_tick
8065 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8066 && REG_N_SETS (REGNO (x)) == 1
8067 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start,
8069 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
8070 return reg_last_set_nonzero_bits[REGNO (x)] & nonzero;
8072 tem = get_last_value (x);
8076 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8077 /* If X is narrower than MODE and TEM is a non-negative
8078 constant that would appear negative in the mode of X,
8079 sign-extend it for use in reg_nonzero_bits because some
8080 machines (maybe most) will actually do the sign-extension
8081 and this is the conservative approach.
8083 ??? For 2.5, try to tighten up the MD files in this regard
8084 instead of this kludge. */
8086 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width
8087 && GET_CODE (tem) == CONST_INT
8089 && 0 != (INTVAL (tem)
8090 & ((HOST_WIDE_INT) 1
8091 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8092 tem = GEN_INT (INTVAL (tem)
8093 | ((HOST_WIDE_INT) (-1)
8094 << GET_MODE_BITSIZE (GET_MODE (x))));
8096 return nonzero_bits (tem, mode) & nonzero;
8098 else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)])
8100 unsigned HOST_WIDE_INT mask = reg_nonzero_bits[REGNO (x)];
8102 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width)
8103 /* We don't know anything about the upper bits. */
8104 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
8105 return nonzero & mask;
8111 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8112 /* If X is negative in MODE, sign-extend the value. */
8113 if (INTVAL (x) > 0 && mode_width < BITS_PER_WORD
8114 && 0 != (INTVAL (x) & ((HOST_WIDE_INT) 1 << (mode_width - 1))))
8115 return (INTVAL (x) | ((HOST_WIDE_INT) (-1) << mode_width));
8121 #ifdef LOAD_EXTEND_OP
8122 /* In many, if not most, RISC machines, reading a byte from memory
8123 zeros the rest of the register. Noticing that fact saves a lot
8124 of extra zero-extends. */
8125 if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND)
8126 nonzero &= GET_MODE_MASK (GET_MODE (x));
8131 case UNEQ: case LTGT:
8132 case GT: case GTU: case UNGT:
8133 case LT: case LTU: case UNLT:
8134 case GE: case GEU: case UNGE:
8135 case LE: case LEU: case UNLE:
8136 case UNORDERED: case ORDERED:
8138 /* If this produces an integer result, we know which bits are set.
8139 Code here used to clear bits outside the mode of X, but that is
8142 if (GET_MODE_CLASS (mode) == MODE_INT
8143 && mode_width <= HOST_BITS_PER_WIDE_INT)
8144 nonzero = STORE_FLAG_VALUE;
8149 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8150 and num_sign_bit_copies. */
8151 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
8152 == GET_MODE_BITSIZE (GET_MODE (x)))
8156 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
8157 nonzero |= (GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x)));
8162 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8163 and num_sign_bit_copies. */
8164 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
8165 == GET_MODE_BITSIZE (GET_MODE (x)))
8171 nonzero &= (nonzero_bits (XEXP (x, 0), mode) & GET_MODE_MASK (mode));
8175 nonzero &= nonzero_bits (XEXP (x, 0), mode);
8176 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
8177 nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
8181 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
8182 Otherwise, show all the bits in the outer mode but not the inner
8184 inner_nz = nonzero_bits (XEXP (x, 0), mode);
8185 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
8187 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
8189 & (((HOST_WIDE_INT) 1
8190 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
8191 inner_nz |= (GET_MODE_MASK (mode)
8192 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
8195 nonzero &= inner_nz;
8199 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
8200 & nonzero_bits (XEXP (x, 1), mode));
8204 case UMIN: case UMAX: case SMIN: case SMAX:
8206 unsigned HOST_WIDE_INT nonzero0 = nonzero_bits (XEXP (x, 0), mode);
8208 /* Don't call nonzero_bits for the second time if it cannot change
8210 if ((nonzero & nonzero0) != nonzero)
8211 nonzero &= (nonzero0 | nonzero_bits (XEXP (x, 1), mode));
8215 case PLUS: case MINUS:
8217 case DIV: case UDIV:
8218 case MOD: case UMOD:
8219 /* We can apply the rules of arithmetic to compute the number of
8220 high- and low-order zero bits of these operations. We start by
8221 computing the width (position of the highest-order non-zero bit)
8222 and the number of low-order zero bits for each value. */
8224 unsigned HOST_WIDE_INT nz0 = nonzero_bits (XEXP (x, 0), mode);
8225 unsigned HOST_WIDE_INT nz1 = nonzero_bits (XEXP (x, 1), mode);
8226 int width0 = floor_log2 (nz0) + 1;
8227 int width1 = floor_log2 (nz1) + 1;
8228 int low0 = floor_log2 (nz0 & -nz0);
8229 int low1 = floor_log2 (nz1 & -nz1);
8230 HOST_WIDE_INT op0_maybe_minusp
8231 = (nz0 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
8232 HOST_WIDE_INT op1_maybe_minusp
8233 = (nz1 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
8234 unsigned int result_width = mode_width;
8240 result_width = MAX (width0, width1) + 1;
8241 result_low = MIN (low0, low1);
8244 result_low = MIN (low0, low1);
8247 result_width = width0 + width1;
8248 result_low = low0 + low1;
8253 if (! op0_maybe_minusp && ! op1_maybe_minusp)
8254 result_width = width0;
8259 result_width = width0;
8264 if (! op0_maybe_minusp && ! op1_maybe_minusp)
8265 result_width = MIN (width0, width1);
8266 result_low = MIN (low0, low1);
8271 result_width = MIN (width0, width1);
8272 result_low = MIN (low0, low1);
8278 if (result_width < mode_width)
8279 nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1;
8282 nonzero &= ~(((HOST_WIDE_INT) 1 << result_low) - 1);
8284 #ifdef POINTERS_EXTEND_UNSIGNED
8285 /* If pointers extend unsigned and this is an addition or subtraction
8286 to a pointer in Pmode, all the bits above ptr_mode are known to be
8288 if (POINTERS_EXTEND_UNSIGNED > 0 && GET_MODE (x) == Pmode
8289 && (code == PLUS || code == MINUS)
8290 && GET_CODE (XEXP (x, 0)) == REG && REG_POINTER (XEXP (x, 0)))
8291 nonzero &= GET_MODE_MASK (ptr_mode);
8297 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8298 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8299 nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1;
8303 /* If this is a SUBREG formed for a promoted variable that has
8304 been zero-extended, we know that at least the high-order bits
8305 are zero, though others might be too. */
8307 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x) > 0)
8308 nonzero = (GET_MODE_MASK (GET_MODE (x))
8309 & nonzero_bits (SUBREG_REG (x), GET_MODE (x)));
8311 /* If the inner mode is a single word for both the host and target
8312 machines, we can compute this from which bits of the inner
8313 object might be nonzero. */
8314 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
8315 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8316 <= HOST_BITS_PER_WIDE_INT))
8318 nonzero &= nonzero_bits (SUBREG_REG (x), mode);
8320 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
8321 /* If this is a typical RISC machine, we only have to worry
8322 about the way loads are extended. */
8323 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
8325 & (((unsigned HOST_WIDE_INT) 1
8326 << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) - 1))))
8328 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) != ZERO_EXTEND)
8331 /* On many CISC machines, accessing an object in a wider mode
8332 causes the high-order bits to become undefined. So they are
8333 not known to be zero. */
8334 if (GET_MODE_SIZE (GET_MODE (x))
8335 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8336 nonzero |= (GET_MODE_MASK (GET_MODE (x))
8337 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
8346 /* The nonzero bits are in two classes: any bits within MODE
8347 that aren't in GET_MODE (x) are always significant. The rest of the
8348 nonzero bits are those that are significant in the operand of
8349 the shift when shifted the appropriate number of bits. This
8350 shows that high-order bits are cleared by the right shift and
8351 low-order bits by left shifts. */
8352 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8353 && INTVAL (XEXP (x, 1)) >= 0
8354 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8356 enum machine_mode inner_mode = GET_MODE (x);
8357 unsigned int width = GET_MODE_BITSIZE (inner_mode);
8358 int count = INTVAL (XEXP (x, 1));
8359 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
8360 unsigned HOST_WIDE_INT op_nonzero = nonzero_bits (XEXP (x, 0), mode);
8361 unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask;
8362 unsigned HOST_WIDE_INT outer = 0;
8364 if (mode_width > width)
8365 outer = (op_nonzero & nonzero & ~mode_mask);
8367 if (code == LSHIFTRT)
8369 else if (code == ASHIFTRT)
8373 /* If the sign bit may have been nonzero before the shift, we
8374 need to mark all the places it could have been copied to
8375 by the shift as possibly nonzero. */
8376 if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count)))
8377 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count);
8379 else if (code == ASHIFT)
8382 inner = ((inner << (count % width)
8383 | (inner >> (width - (count % width)))) & mode_mask);
8385 nonzero &= (outer | inner);
8390 /* This is at most the number of bits in the mode. */
8391 nonzero = ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width) + 1)) - 1;
8395 nonzero &= (nonzero_bits (XEXP (x, 1), mode)
8396 | nonzero_bits (XEXP (x, 2), mode));
8406 /* See the macro definition above. */
8407 #undef num_sign_bit_copies
8409 /* Return the number of bits at the high-order end of X that are known to
8410 be equal to the sign bit. X will be used in mode MODE; if MODE is
8411 VOIDmode, X will be used in its own mode. The returned value will always
8412 be between 1 and the number of bits in MODE. */
8415 num_sign_bit_copies (x, mode)
8417 enum machine_mode mode;
8419 enum rtx_code code = GET_CODE (x);
8420 unsigned int bitwidth;
8421 int num0, num1, result;
8422 unsigned HOST_WIDE_INT nonzero;
8425 /* If we weren't given a mode, use the mode of X. If the mode is still
8426 VOIDmode, we don't know anything. Likewise if one of the modes is
8429 if (mode == VOIDmode)
8430 mode = GET_MODE (x);
8432 if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x)))
8435 bitwidth = GET_MODE_BITSIZE (mode);
8437 /* For a smaller object, just ignore the high bits. */
8438 if (bitwidth < GET_MODE_BITSIZE (GET_MODE (x)))
8440 num0 = num_sign_bit_copies (x, GET_MODE (x));
8442 num0 - (int) (GET_MODE_BITSIZE (GET_MODE (x)) - bitwidth));
8445 if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_BITSIZE (GET_MODE (x)))
8447 #ifndef WORD_REGISTER_OPERATIONS
8448 /* If this machine does not do all register operations on the entire
8449 register and MODE is wider than the mode of X, we can say nothing
8450 at all about the high-order bits. */
8453 /* Likewise on machines that do, if the mode of the object is smaller
8454 than a word and loads of that size don't sign extend, we can say
8455 nothing about the high order bits. */
8456 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
8457 #ifdef LOAD_EXTEND_OP
8458 && LOAD_EXTEND_OP (GET_MODE (x)) != SIGN_EXTEND
8469 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8470 /* If pointers extend signed and this is a pointer in Pmode, say that
8471 all the bits above ptr_mode are known to be sign bit copies. */
8472 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode && mode == Pmode
8474 return GET_MODE_BITSIZE (Pmode) - GET_MODE_BITSIZE (ptr_mode) + 1;
8477 if (reg_last_set_value[REGNO (x)] != 0
8478 && reg_last_set_mode[REGNO (x)] == mode
8479 && (reg_last_set_label[REGNO (x)] == label_tick
8480 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8481 && REG_N_SETS (REGNO (x)) == 1
8482 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start,
8484 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
8485 return reg_last_set_sign_bit_copies[REGNO (x)];
8487 tem = get_last_value (x);
8489 return num_sign_bit_copies (tem, mode);
8491 if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0
8492 && GET_MODE_BITSIZE (GET_MODE (x)) == bitwidth)
8493 return reg_sign_bit_copies[REGNO (x)];
8497 #ifdef LOAD_EXTEND_OP
8498 /* Some RISC machines sign-extend all loads of smaller than a word. */
8499 if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND)
8500 return MAX (1, ((int) bitwidth
8501 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1));
8506 /* If the constant is negative, take its 1's complement and remask.
8507 Then see how many zero bits we have. */
8508 nonzero = INTVAL (x) & GET_MODE_MASK (mode);
8509 if (bitwidth <= HOST_BITS_PER_WIDE_INT
8510 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8511 nonzero = (~nonzero) & GET_MODE_MASK (mode);
8513 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
8516 /* If this is a SUBREG for a promoted object that is sign-extended
8517 and we are looking at it in a wider mode, we know that at least the
8518 high-order bits are known to be sign bit copies. */
8520 if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
8522 num0 = num_sign_bit_copies (SUBREG_REG (x), mode);
8523 return MAX ((int) bitwidth
8524 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1,
8528 /* For a smaller object, just ignore the high bits. */
8529 if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
8531 num0 = num_sign_bit_copies (SUBREG_REG (x), VOIDmode);
8532 return MAX (1, (num0
8533 - (int) (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8537 #ifdef WORD_REGISTER_OPERATIONS
8538 #ifdef LOAD_EXTEND_OP
8539 /* For paradoxical SUBREGs on machines where all register operations
8540 affect the entire register, just look inside. Note that we are
8541 passing MODE to the recursive call, so the number of sign bit copies
8542 will remain relative to that mode, not the inner mode. */
8544 /* This works only if loads sign extend. Otherwise, if we get a
8545 reload for the inner part, it may be loaded from the stack, and
8546 then we lose all sign bit copies that existed before the store
8549 if ((GET_MODE_SIZE (GET_MODE (x))
8550 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8551 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND)
8552 return num_sign_bit_copies (SUBREG_REG (x), mode);
8558 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
8559 return MAX (1, (int) bitwidth - INTVAL (XEXP (x, 1)));
8563 return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8564 + num_sign_bit_copies (XEXP (x, 0), VOIDmode));
8567 /* For a smaller object, just ignore the high bits. */
8568 num0 = num_sign_bit_copies (XEXP (x, 0), VOIDmode);
8569 return MAX (1, (num0 - (int) (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8573 return num_sign_bit_copies (XEXP (x, 0), mode);
8575 case ROTATE: case ROTATERT:
8576 /* If we are rotating left by a number of bits less than the number
8577 of sign bit copies, we can just subtract that amount from the
8579 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8580 && INTVAL (XEXP (x, 1)) >= 0
8581 && INTVAL (XEXP (x, 1)) < (int) bitwidth)
8583 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8584 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
8585 : (int) bitwidth - INTVAL (XEXP (x, 1))));
8590 /* In general, this subtracts one sign bit copy. But if the value
8591 is known to be positive, the number of sign bit copies is the
8592 same as that of the input. Finally, if the input has just one bit
8593 that might be nonzero, all the bits are copies of the sign bit. */
8594 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8595 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8596 return num0 > 1 ? num0 - 1 : 1;
8598 nonzero = nonzero_bits (XEXP (x, 0), mode);
8603 && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero))
8608 case IOR: case AND: case XOR:
8609 case SMIN: case SMAX: case UMIN: case UMAX:
8610 /* Logical operations will preserve the number of sign-bit copies.
8611 MIN and MAX operations always return one of the operands. */
8612 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8613 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8614 return MIN (num0, num1);
8616 case PLUS: case MINUS:
8617 /* For addition and subtraction, we can have a 1-bit carry. However,
8618 if we are subtracting 1 from a positive number, there will not
8619 be such a carry. Furthermore, if the positive number is known to
8620 be 0 or 1, we know the result is either -1 or 0. */
8622 if (code == PLUS && XEXP (x, 1) == constm1_rtx
8623 && bitwidth <= HOST_BITS_PER_WIDE_INT)
8625 nonzero = nonzero_bits (XEXP (x, 0), mode);
8626 if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0)
8627 return (nonzero == 1 || nonzero == 0 ? bitwidth
8628 : bitwidth - floor_log2 (nonzero) - 1);
8631 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8632 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8633 result = MAX (1, MIN (num0, num1) - 1);
8635 #ifdef POINTERS_EXTEND_UNSIGNED
8636 /* If pointers extend signed and this is an addition or subtraction
8637 to a pointer in Pmode, all the bits above ptr_mode are known to be
8639 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
8640 && (code == PLUS || code == MINUS)
8641 && GET_CODE (XEXP (x, 0)) == REG && REG_POINTER (XEXP (x, 0)))
8642 result = MAX ((int) (GET_MODE_BITSIZE (Pmode)
8643 - GET_MODE_BITSIZE (ptr_mode) + 1),
8649 /* The number of bits of the product is the sum of the number of
8650 bits of both terms. However, unless one of the terms if known
8651 to be positive, we must allow for an additional bit since negating
8652 a negative number can remove one sign bit copy. */
8654 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8655 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8657 result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
8659 && (bitwidth > HOST_BITS_PER_WIDE_INT
8660 || (((nonzero_bits (XEXP (x, 0), mode)
8661 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8662 && ((nonzero_bits (XEXP (x, 1), mode)
8663 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))))
8666 return MAX (1, result);
8669 /* The result must be <= the first operand. If the first operand
8670 has the high bit set, we know nothing about the number of sign
8672 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8674 else if ((nonzero_bits (XEXP (x, 0), mode)
8675 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8678 return num_sign_bit_copies (XEXP (x, 0), mode);
8681 /* The result must be <= the second operand. */
8682 return num_sign_bit_copies (XEXP (x, 1), mode);
8685 /* Similar to unsigned division, except that we have to worry about
8686 the case where the divisor is negative, in which case we have
8688 result = num_sign_bit_copies (XEXP (x, 0), mode);
8690 && (bitwidth > HOST_BITS_PER_WIDE_INT
8691 || (nonzero_bits (XEXP (x, 1), mode)
8692 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8698 result = num_sign_bit_copies (XEXP (x, 1), mode);
8700 && (bitwidth > HOST_BITS_PER_WIDE_INT
8701 || (nonzero_bits (XEXP (x, 1), mode)
8702 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8708 /* Shifts by a constant add to the number of bits equal to the
8710 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8711 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8712 && INTVAL (XEXP (x, 1)) > 0)
8713 num0 = MIN ((int) bitwidth, num0 + INTVAL (XEXP (x, 1)));
8718 /* Left shifts destroy copies. */
8719 if (GET_CODE (XEXP (x, 1)) != CONST_INT
8720 || INTVAL (XEXP (x, 1)) < 0
8721 || INTVAL (XEXP (x, 1)) >= (int) bitwidth)
8724 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8725 return MAX (1, num0 - INTVAL (XEXP (x, 1)));
8728 num0 = num_sign_bit_copies (XEXP (x, 1), mode);
8729 num1 = num_sign_bit_copies (XEXP (x, 2), mode);
8730 return MIN (num0, num1);
8732 case EQ: case NE: case GE: case GT: case LE: case LT:
8733 case UNEQ: case LTGT: case UNGE: case UNGT: case UNLE: case UNLT:
8734 case GEU: case GTU: case LEU: case LTU:
8735 case UNORDERED: case ORDERED:
8736 /* If the constant is negative, take its 1's complement and remask.
8737 Then see how many zero bits we have. */
8738 nonzero = STORE_FLAG_VALUE;
8739 if (bitwidth <= HOST_BITS_PER_WIDE_INT
8740 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8741 nonzero = (~nonzero) & GET_MODE_MASK (mode);
8743 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
8750 /* If we haven't been able to figure it out by one of the above rules,
8751 see if some of the high-order bits are known to be zero. If so,
8752 count those bits and return one less than that amount. If we can't
8753 safely compute the mask for this mode, always return BITWIDTH. */
8755 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8758 nonzero = nonzero_bits (x, mode);
8759 return (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))
8760 ? 1 : bitwidth - floor_log2 (nonzero) - 1);
8763 /* Return the number of "extended" bits there are in X, when interpreted
8764 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8765 unsigned quantities, this is the number of high-order zero bits.
8766 For signed quantities, this is the number of copies of the sign bit
8767 minus 1. In both case, this function returns the number of "spare"
8768 bits. For example, if two quantities for which this function returns
8769 at least 1 are added, the addition is known not to overflow.
8771 This function will always return 0 unless called during combine, which
8772 implies that it must be called from a define_split. */
8775 extended_count (x, mode, unsignedp)
8777 enum machine_mode mode;
8780 if (nonzero_sign_valid == 0)
8784 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8785 ? (GET_MODE_BITSIZE (mode) - 1
8786 - floor_log2 (nonzero_bits (x, mode)))
8788 : num_sign_bit_copies (x, mode) - 1);
8791 /* This function is called from `simplify_shift_const' to merge two
8792 outer operations. Specifically, we have already found that we need
8793 to perform operation *POP0 with constant *PCONST0 at the outermost
8794 position. We would now like to also perform OP1 with constant CONST1
8795 (with *POP0 being done last).
8797 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8798 the resulting operation. *PCOMP_P is set to 1 if we would need to
8799 complement the innermost operand, otherwise it is unchanged.
8801 MODE is the mode in which the operation will be done. No bits outside
8802 the width of this mode matter. It is assumed that the width of this mode
8803 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8805 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
8806 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8807 result is simply *PCONST0.
8809 If the resulting operation cannot be expressed as one operation, we
8810 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8813 merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p)
8814 enum rtx_code *pop0;
8815 HOST_WIDE_INT *pconst0;
8817 HOST_WIDE_INT const1;
8818 enum machine_mode mode;
8821 enum rtx_code op0 = *pop0;
8822 HOST_WIDE_INT const0 = *pconst0;
8824 const0 &= GET_MODE_MASK (mode);
8825 const1 &= GET_MODE_MASK (mode);
8827 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8831 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
8834 if (op1 == NIL || op0 == SET)
8837 else if (op0 == NIL)
8838 op0 = op1, const0 = const1;
8840 else if (op0 == op1)
8864 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8865 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8868 /* If the two constants aren't the same, we can't do anything. The
8869 remaining six cases can all be done. */
8870 else if (const0 != const1)
8878 /* (a & b) | b == b */
8880 else /* op1 == XOR */
8881 /* (a ^ b) | b == a | b */
8887 /* (a & b) ^ b == (~a) & b */
8888 op0 = AND, *pcomp_p = 1;
8889 else /* op1 == IOR */
8890 /* (a | b) ^ b == a & ~b */
8891 op0 = AND, *pconst0 = ~const0;
8896 /* (a | b) & b == b */
8898 else /* op1 == XOR */
8899 /* (a ^ b) & b) == (~a) & b */
8906 /* Check for NO-OP cases. */
8907 const0 &= GET_MODE_MASK (mode);
8909 && (op0 == IOR || op0 == XOR || op0 == PLUS))
8911 else if (const0 == 0 && op0 == AND)
8913 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8917 /* ??? Slightly redundant with the above mask, but not entirely.
8918 Moving this above means we'd have to sign-extend the mode mask
8919 for the final test. */
8920 const0 = trunc_int_for_mode (const0, mode);
8928 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8929 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
8930 that we started with.
8932 The shift is normally computed in the widest mode we find in VAROP, as
8933 long as it isn't a different number of words than RESULT_MODE. Exceptions
8934 are ASHIFTRT and ROTATE, which are always done in their original mode, */
8937 simplify_shift_const (x, code, result_mode, varop, orig_count)
8940 enum machine_mode result_mode;
8944 enum rtx_code orig_code = code;
8947 enum machine_mode mode = result_mode;
8948 enum machine_mode shift_mode, tmode;
8949 unsigned int mode_words
8950 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8951 /* We form (outer_op (code varop count) (outer_const)). */
8952 enum rtx_code outer_op = NIL;
8953 HOST_WIDE_INT outer_const = 0;
8955 int complement_p = 0;
8958 /* Make sure and truncate the "natural" shift on the way in. We don't
8959 want to do this inside the loop as it makes it more difficult to
8961 #ifdef SHIFT_COUNT_TRUNCATED
8962 if (SHIFT_COUNT_TRUNCATED)
8963 orig_count &= GET_MODE_BITSIZE (mode) - 1;
8966 /* If we were given an invalid count, don't do anything except exactly
8967 what was requested. */
8969 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
8974 return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (orig_count));
8979 /* Unless one of the branches of the `if' in this loop does a `continue',
8980 we will `break' the loop after the `if'. */
8984 /* If we have an operand of (clobber (const_int 0)), just return that
8986 if (GET_CODE (varop) == CLOBBER)
8989 /* If we discovered we had to complement VAROP, leave. Making a NOT
8990 here would cause an infinite loop. */
8994 /* Convert ROTATERT to ROTATE. */
8995 if (code == ROTATERT)
8996 code = ROTATE, count = GET_MODE_BITSIZE (result_mode) - count;
8998 /* We need to determine what mode we will do the shift in. If the
8999 shift is a right shift or a ROTATE, we must always do it in the mode
9000 it was originally done in. Otherwise, we can do it in MODE, the
9001 widest mode encountered. */
9003 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9004 ? result_mode : mode);
9006 /* Handle cases where the count is greater than the size of the mode
9007 minus 1. For ASHIFT, use the size minus one as the count (this can
9008 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9009 take the count modulo the size. For other shifts, the result is
9012 Since these shifts are being produced by the compiler by combining
9013 multiple operations, each of which are defined, we know what the
9014 result is supposed to be. */
9016 if (count > GET_MODE_BITSIZE (shift_mode) - 1)
9018 if (code == ASHIFTRT)
9019 count = GET_MODE_BITSIZE (shift_mode) - 1;
9020 else if (code == ROTATE || code == ROTATERT)
9021 count %= GET_MODE_BITSIZE (shift_mode);
9024 /* We can't simply return zero because there may be an
9032 /* An arithmetic right shift of a quantity known to be -1 or 0
9034 if (code == ASHIFTRT
9035 && (num_sign_bit_copies (varop, shift_mode)
9036 == GET_MODE_BITSIZE (shift_mode)))
9042 /* If we are doing an arithmetic right shift and discarding all but
9043 the sign bit copies, this is equivalent to doing a shift by the
9044 bitsize minus one. Convert it into that shift because it will often
9045 allow other simplifications. */
9047 if (code == ASHIFTRT
9048 && (count + num_sign_bit_copies (varop, shift_mode)
9049 >= GET_MODE_BITSIZE (shift_mode)))
9050 count = GET_MODE_BITSIZE (shift_mode) - 1;
9052 /* We simplify the tests below and elsewhere by converting
9053 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9054 `make_compound_operation' will convert it to a ASHIFTRT for
9055 those machines (such as VAX) that don't have a LSHIFTRT. */
9056 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9058 && ((nonzero_bits (varop, shift_mode)
9059 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
9063 switch (GET_CODE (varop))
9069 new = expand_compound_operation (varop);
9078 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9079 minus the width of a smaller mode, we can do this with a
9080 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9081 if ((code == ASHIFTRT || code == LSHIFTRT)
9082 && ! mode_dependent_address_p (XEXP (varop, 0))
9083 && ! MEM_VOLATILE_P (varop)
9084 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9085 MODE_INT, 1)) != BLKmode)
9087 new = adjust_address_nv (varop, tmode,
9088 BYTES_BIG_ENDIAN ? 0
9089 : count / BITS_PER_UNIT);
9091 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9092 : ZERO_EXTEND, mode, new);
9099 /* Similar to the case above, except that we can only do this if
9100 the resulting mode is the same as that of the underlying
9101 MEM and adjust the address depending on the *bits* endianness
9102 because of the way that bit-field extract insns are defined. */
9103 if ((code == ASHIFTRT || code == LSHIFTRT)
9104 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9105 MODE_INT, 1)) != BLKmode
9106 && tmode == GET_MODE (XEXP (varop, 0)))
9108 if (BITS_BIG_ENDIAN)
9109 new = XEXP (varop, 0);
9112 new = copy_rtx (XEXP (varop, 0));
9113 SUBST (XEXP (new, 0),
9114 plus_constant (XEXP (new, 0),
9115 count / BITS_PER_UNIT));
9118 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9119 : ZERO_EXTEND, mode, new);
9126 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9127 the same number of words as what we've seen so far. Then store
9128 the widest mode in MODE. */
9129 if (subreg_lowpart_p (varop)
9130 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9131 > GET_MODE_SIZE (GET_MODE (varop)))
9132 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9133 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9136 varop = SUBREG_REG (varop);
9137 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
9138 mode = GET_MODE (varop);
9144 /* Some machines use MULT instead of ASHIFT because MULT
9145 is cheaper. But it is still better on those machines to
9146 merge two shifts into one. */
9147 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9148 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9151 = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
9152 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
9158 /* Similar, for when divides are cheaper. */
9159 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9160 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9163 = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
9164 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
9170 /* If we are extracting just the sign bit of an arithmetic
9171 right shift, that shift is not needed. However, the sign
9172 bit of a wider mode may be different from what would be
9173 interpreted as the sign bit in a narrower mode, so, if
9174 the result is narrower, don't discard the shift. */
9175 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
9176 && (GET_MODE_BITSIZE (result_mode)
9177 >= GET_MODE_BITSIZE (GET_MODE (varop))))
9179 varop = XEXP (varop, 0);
9183 /* ... fall through ... */
9188 /* Here we have two nested shifts. The result is usually the
9189 AND of a new shift with a mask. We compute the result below. */
9190 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9191 && INTVAL (XEXP (varop, 1)) >= 0
9192 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
9193 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9194 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9196 enum rtx_code first_code = GET_CODE (varop);
9197 unsigned int first_count = INTVAL (XEXP (varop, 1));
9198 unsigned HOST_WIDE_INT mask;
9201 /* We have one common special case. We can't do any merging if
9202 the inner code is an ASHIFTRT of a smaller mode. However, if
9203 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9204 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9205 we can convert it to
9206 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9207 This simplifies certain SIGN_EXTEND operations. */
9208 if (code == ASHIFT && first_code == ASHIFTRT
9209 && (GET_MODE_BITSIZE (result_mode)
9210 - GET_MODE_BITSIZE (GET_MODE (varop))) == count)
9212 /* C3 has the low-order C1 bits zero. */
9214 mask = (GET_MODE_MASK (mode)
9215 & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
9217 varop = simplify_and_const_int (NULL_RTX, result_mode,
9218 XEXP (varop, 0), mask);
9219 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
9221 count = first_count;
9226 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9227 than C1 high-order bits equal to the sign bit, we can convert
9228 this to either an ASHIFT or a ASHIFTRT depending on the
9231 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9233 if (code == ASHIFTRT && first_code == ASHIFT
9234 && GET_MODE (varop) == shift_mode
9235 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
9238 varop = XEXP (varop, 0);
9240 signed_count = count - first_count;
9241 if (signed_count < 0)
9242 count = -signed_count, code = ASHIFT;
9244 count = signed_count;
9249 /* There are some cases we can't do. If CODE is ASHIFTRT,
9250 we can only do this if FIRST_CODE is also ASHIFTRT.
9252 We can't do the case when CODE is ROTATE and FIRST_CODE is
9255 If the mode of this shift is not the mode of the outer shift,
9256 we can't do this if either shift is a right shift or ROTATE.
9258 Finally, we can't do any of these if the mode is too wide
9259 unless the codes are the same.
9261 Handle the case where the shift codes are the same
9264 if (code == first_code)
9266 if (GET_MODE (varop) != result_mode
9267 && (code == ASHIFTRT || code == LSHIFTRT
9271 count += first_count;
9272 varop = XEXP (varop, 0);
9276 if (code == ASHIFTRT
9277 || (code == ROTATE && first_code == ASHIFTRT)
9278 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
9279 || (GET_MODE (varop) != result_mode
9280 && (first_code == ASHIFTRT || first_code == LSHIFTRT
9281 || first_code == ROTATE
9282 || code == ROTATE)))
9285 /* To compute the mask to apply after the shift, shift the
9286 nonzero bits of the inner shift the same way the
9287 outer shift will. */
9289 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
9292 = simplify_binary_operation (code, result_mode, mask_rtx,
9295 /* Give up if we can't compute an outer operation to use. */
9297 || GET_CODE (mask_rtx) != CONST_INT
9298 || ! merge_outer_ops (&outer_op, &outer_const, AND,
9300 result_mode, &complement_p))
9303 /* If the shifts are in the same direction, we add the
9304 counts. Otherwise, we subtract them. */
9305 signed_count = count;
9306 if ((code == ASHIFTRT || code == LSHIFTRT)
9307 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
9308 signed_count += first_count;
9310 signed_count -= first_count;
9312 /* If COUNT is positive, the new shift is usually CODE,
9313 except for the two exceptions below, in which case it is
9314 FIRST_CODE. If the count is negative, FIRST_CODE should
9316 if (signed_count > 0
9317 && ((first_code == ROTATE && code == ASHIFT)
9318 || (first_code == ASHIFTRT && code == LSHIFTRT)))
9319 code = first_code, count = signed_count;
9320 else if (signed_count < 0)
9321 code = first_code, count = -signed_count;
9323 count = signed_count;
9325 varop = XEXP (varop, 0);
9329 /* If we have (A << B << C) for any shift, we can convert this to
9330 (A << C << B). This wins if A is a constant. Only try this if
9331 B is not a constant. */
9333 else if (GET_CODE (varop) == code
9334 && GET_CODE (XEXP (varop, 1)) != CONST_INT
9336 = simplify_binary_operation (code, mode,
9340 varop = gen_rtx_fmt_ee (code, mode, new, XEXP (varop, 1));
9347 /* Make this fit the case below. */
9348 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
9349 GEN_INT (GET_MODE_MASK (mode)));
9355 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9356 with C the size of VAROP - 1 and the shift is logical if
9357 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9358 we have an (le X 0) operation. If we have an arithmetic shift
9359 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9360 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9362 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
9363 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
9364 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9365 && (code == LSHIFTRT || code == ASHIFTRT)
9366 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
9367 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9370 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
9373 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9374 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9379 /* If we have (shift (logical)), move the logical to the outside
9380 to allow it to possibly combine with another logical and the
9381 shift to combine with another shift. This also canonicalizes to
9382 what a ZERO_EXTRACT looks like. Also, some machines have
9383 (and (shift)) insns. */
9385 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9386 && (new = simplify_binary_operation (code, result_mode,
9388 GEN_INT (count))) != 0
9389 && GET_CODE (new) == CONST_INT
9390 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
9391 INTVAL (new), result_mode, &complement_p))
9393 varop = XEXP (varop, 0);
9397 /* If we can't do that, try to simplify the shift in each arm of the
9398 logical expression, make a new logical expression, and apply
9399 the inverse distributive law. */
9401 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9402 XEXP (varop, 0), count);
9403 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9404 XEXP (varop, 1), count);
9406 varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs);
9407 varop = apply_distributive_law (varop);
9414 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9415 says that the sign bit can be tested, FOO has mode MODE, C is
9416 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9417 that may be nonzero. */
9418 if (code == LSHIFTRT
9419 && XEXP (varop, 1) == const0_rtx
9420 && GET_MODE (XEXP (varop, 0)) == result_mode
9421 && count == GET_MODE_BITSIZE (result_mode) - 1
9422 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9423 && ((STORE_FLAG_VALUE
9424 & ((HOST_WIDE_INT) 1
9425 < (GET_MODE_BITSIZE (result_mode) - 1))))
9426 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9427 && merge_outer_ops (&outer_op, &outer_const, XOR,
9428 (HOST_WIDE_INT) 1, result_mode,
9431 varop = XEXP (varop, 0);
9438 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9439 than the number of bits in the mode is equivalent to A. */
9440 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
9441 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9443 varop = XEXP (varop, 0);
9448 /* NEG commutes with ASHIFT since it is multiplication. Move the
9449 NEG outside to allow shifts to combine. */
9451 && merge_outer_ops (&outer_op, &outer_const, NEG,
9452 (HOST_WIDE_INT) 0, result_mode,
9455 varop = XEXP (varop, 0);
9461 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9462 is one less than the number of bits in the mode is
9463 equivalent to (xor A 1). */
9464 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
9465 && XEXP (varop, 1) == constm1_rtx
9466 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9467 && merge_outer_ops (&outer_op, &outer_const, XOR,
9468 (HOST_WIDE_INT) 1, result_mode,
9472 varop = XEXP (varop, 0);
9476 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9477 that might be nonzero in BAR are those being shifted out and those
9478 bits are known zero in FOO, we can replace the PLUS with FOO.
9479 Similarly in the other operand order. This code occurs when
9480 we are computing the size of a variable-size array. */
9482 if ((code == ASHIFTRT || code == LSHIFTRT)
9483 && count < HOST_BITS_PER_WIDE_INT
9484 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9485 && (nonzero_bits (XEXP (varop, 1), result_mode)
9486 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9488 varop = XEXP (varop, 0);
9491 else if ((code == ASHIFTRT || code == LSHIFTRT)
9492 && count < HOST_BITS_PER_WIDE_INT
9493 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9494 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9496 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9497 & nonzero_bits (XEXP (varop, 1),
9500 varop = XEXP (varop, 1);
9504 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9506 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9507 && (new = simplify_binary_operation (ASHIFT, result_mode,
9509 GEN_INT (count))) != 0
9510 && GET_CODE (new) == CONST_INT
9511 && merge_outer_ops (&outer_op, &outer_const, PLUS,
9512 INTVAL (new), result_mode, &complement_p))
9514 varop = XEXP (varop, 0);
9520 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9521 with C the size of VAROP - 1 and the shift is logical if
9522 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9523 we have a (gt X 0) operation. If the shift is arithmetic with
9524 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9525 we have a (neg (gt X 0)) operation. */
9527 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9528 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9529 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
9530 && (code == LSHIFTRT || code == ASHIFTRT)
9531 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9532 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
9533 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9536 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9539 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9540 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9547 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9548 if the truncate does not affect the value. */
9549 if (code == LSHIFTRT
9550 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9551 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9552 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9553 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9554 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9556 rtx varop_inner = XEXP (varop, 0);
9559 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9560 XEXP (varop_inner, 0),
9562 (count + INTVAL (XEXP (varop_inner, 1))));
9563 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9576 /* We need to determine what mode to do the shift in. If the shift is
9577 a right shift or ROTATE, we must always do it in the mode it was
9578 originally done in. Otherwise, we can do it in MODE, the widest mode
9579 encountered. The code we care about is that of the shift that will
9580 actually be done, not the shift that was originally requested. */
9582 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9583 ? result_mode : mode);
9585 /* We have now finished analyzing the shift. The result should be
9586 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9587 OUTER_OP is non-NIL, it is an operation that needs to be applied
9588 to the result of the shift. OUTER_CONST is the relevant constant,
9589 but we must turn off all bits turned off in the shift.
9591 If we were passed a value for X, see if we can use any pieces of
9592 it. If not, make new rtx. */
9594 if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
9595 && GET_CODE (XEXP (x, 1)) == CONST_INT
9596 && INTVAL (XEXP (x, 1)) == count)
9597 const_rtx = XEXP (x, 1);
9599 const_rtx = GEN_INT (count);
9601 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
9602 && GET_MODE (XEXP (x, 0)) == shift_mode
9603 && SUBREG_REG (XEXP (x, 0)) == varop)
9604 varop = XEXP (x, 0);
9605 else if (GET_MODE (varop) != shift_mode)
9606 varop = gen_lowpart_for_combine (shift_mode, varop);
9608 /* If we can't make the SUBREG, try to return what we were given. */
9609 if (GET_CODE (varop) == CLOBBER)
9610 return x ? x : varop;
9612 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
9616 x = gen_rtx_fmt_ee (code, shift_mode, varop, const_rtx);
9618 /* If we have an outer operation and we just made a shift, it is
9619 possible that we could have simplified the shift were it not
9620 for the outer operation. So try to do the simplification
9623 if (outer_op != NIL && GET_CODE (x) == code
9624 && GET_CODE (XEXP (x, 1)) == CONST_INT)
9625 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
9626 INTVAL (XEXP (x, 1)));
9628 /* If we were doing a LSHIFTRT in a wider mode than it was originally,
9629 turn off all the bits that the shift would have turned off. */
9630 if (orig_code == LSHIFTRT && result_mode != shift_mode)
9631 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9632 GET_MODE_MASK (result_mode) >> orig_count);
9634 /* Do the remainder of the processing in RESULT_MODE. */
9635 x = gen_lowpart_for_combine (result_mode, x);
9637 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9640 x =simplify_gen_unary (NOT, result_mode, x, result_mode);
9642 if (outer_op != NIL)
9644 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9645 outer_const = trunc_int_for_mode (outer_const, result_mode);
9647 if (outer_op == AND)
9648 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9649 else if (outer_op == SET)
9650 /* This means that we have determined that the result is
9651 equivalent to a constant. This should be rare. */
9652 x = GEN_INT (outer_const);
9653 else if (GET_RTX_CLASS (outer_op) == '1')
9654 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
9656 x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
9662 /* Like recog, but we receive the address of a pointer to a new pattern.
9663 We try to match the rtx that the pointer points to.
9664 If that fails, we may try to modify or replace the pattern,
9665 storing the replacement into the same pointer object.
9667 Modifications include deletion or addition of CLOBBERs.
9669 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9670 the CLOBBERs are placed.
9672 The value is the final insn code from the pattern ultimately matched,
9676 recog_for_combine (pnewpat, insn, pnotes)
9682 int insn_code_number;
9683 int num_clobbers_to_add = 0;
9688 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9689 we use to indicate that something didn't match. If we find such a
9690 thing, force rejection. */
9691 if (GET_CODE (pat) == PARALLEL)
9692 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9693 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9694 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9697 /* *pnewpat does not have to be actual PATTERN (insn), so make a dummy
9698 instruction for pattern recognition. */
9699 dummy_insn = shallow_copy_rtx (insn);
9700 PATTERN (dummy_insn) = pat;
9701 REG_NOTES (dummy_insn) = 0;
9703 insn_code_number = recog (pat, dummy_insn, &num_clobbers_to_add);
9705 /* If it isn't, there is the possibility that we previously had an insn
9706 that clobbered some register as a side effect, but the combined
9707 insn doesn't need to do that. So try once more without the clobbers
9708 unless this represents an ASM insn. */
9710 if (insn_code_number < 0 && ! check_asm_operands (pat)
9711 && GET_CODE (pat) == PARALLEL)
9715 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9716 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9719 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9723 SUBST_INT (XVECLEN (pat, 0), pos);
9726 pat = XVECEXP (pat, 0, 0);
9728 PATTERN (dummy_insn) = pat;
9729 insn_code_number = recog (pat, dummy_insn, &num_clobbers_to_add);
9732 /* Recognize all noop sets, these will be killed by followup pass. */
9733 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
9734 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
9736 /* If we had any clobbers to add, make a new pattern than contains
9737 them. Then check to make sure that all of them are dead. */
9738 if (num_clobbers_to_add)
9740 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9741 rtvec_alloc (GET_CODE (pat) == PARALLEL
9743 + num_clobbers_to_add)
9744 : num_clobbers_to_add + 1));
9746 if (GET_CODE (pat) == PARALLEL)
9747 for (i = 0; i < XVECLEN (pat, 0); i++)
9748 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9750 XVECEXP (newpat, 0, 0) = pat;
9752 add_clobbers (newpat, insn_code_number);
9754 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9755 i < XVECLEN (newpat, 0); i++)
9757 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
9758 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9760 notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9761 XEXP (XVECEXP (newpat, 0, i), 0), notes);
9769 return insn_code_number;
9772 /* Like gen_lowpart but for use by combine. In combine it is not possible
9773 to create any new pseudoregs. However, it is safe to create
9774 invalid memory addresses, because combine will try to recognize
9775 them and all they will do is make the combine attempt fail.
9777 If for some reason this cannot do its job, an rtx
9778 (clobber (const_int 0)) is returned.
9779 An insn containing that will not be recognized. */
9784 gen_lowpart_for_combine (mode, x)
9785 enum machine_mode mode;
9790 if (GET_MODE (x) == mode)
9793 /* We can only support MODE being wider than a word if X is a
9794 constant integer or has a mode the same size. */
9796 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
9797 && ! ((GET_MODE (x) == VOIDmode
9798 && (GET_CODE (x) == CONST_INT
9799 || GET_CODE (x) == CONST_DOUBLE))
9800 || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
9801 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9803 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9804 won't know what to do. So we will strip off the SUBREG here and
9805 process normally. */
9806 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
9809 if (GET_MODE (x) == mode)
9813 result = gen_lowpart_common (mode, x);
9814 #ifdef CLASS_CANNOT_CHANGE_MODE
9816 && GET_CODE (result) == SUBREG
9817 && GET_CODE (SUBREG_REG (result)) == REG
9818 && REGNO (SUBREG_REG (result)) >= FIRST_PSEUDO_REGISTER
9819 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (result),
9820 GET_MODE (SUBREG_REG (result))))
9821 REG_CHANGES_MODE (REGNO (SUBREG_REG (result))) = 1;
9827 if (GET_CODE (x) == MEM)
9831 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9833 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9834 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9836 /* If we want to refer to something bigger than the original memref,
9837 generate a perverse subreg instead. That will force a reload
9838 of the original memref X. */
9839 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
9840 return gen_rtx_SUBREG (mode, x, 0);
9842 if (WORDS_BIG_ENDIAN)
9843 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
9844 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
9846 if (BYTES_BIG_ENDIAN)
9848 /* Adjust the address so that the address-after-the-data is
9850 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
9851 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
9854 return adjust_address_nv (x, mode, offset);
9857 /* If X is a comparison operator, rewrite it in a new mode. This
9858 probably won't match, but may allow further simplifications. */
9859 else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
9860 return gen_rtx_fmt_ee (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
9862 /* If we couldn't simplify X any other way, just enclose it in a
9863 SUBREG. Normally, this SUBREG won't match, but some patterns may
9864 include an explicit SUBREG or we may simplify it further in combine. */
9870 offset = subreg_lowpart_offset (mode, GET_MODE (x));
9871 res = simplify_gen_subreg (mode, x, GET_MODE (x), offset);
9874 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9878 /* These routines make binary and unary operations by first seeing if they
9879 fold; if not, a new expression is allocated. */
9882 gen_binary (code, mode, op0, op1)
9884 enum machine_mode mode;
9890 if (GET_RTX_CLASS (code) == 'c'
9891 && swap_commutative_operands_p (op0, op1))
9892 tem = op0, op0 = op1, op1 = tem;
9894 if (GET_RTX_CLASS (code) == '<')
9896 enum machine_mode op_mode = GET_MODE (op0);
9898 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
9899 just (REL_OP X Y). */
9900 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
9902 op1 = XEXP (op0, 1);
9903 op0 = XEXP (op0, 0);
9904 op_mode = GET_MODE (op0);
9907 if (op_mode == VOIDmode)
9908 op_mode = GET_MODE (op1);
9909 result = simplify_relational_operation (code, op_mode, op0, op1);
9912 result = simplify_binary_operation (code, mode, op0, op1);
9917 /* Put complex operands first and constants second. */
9918 if (GET_RTX_CLASS (code) == 'c'
9919 && swap_commutative_operands_p (op0, op1))
9920 return gen_rtx_fmt_ee (code, mode, op1, op0);
9922 /* If we are turning off bits already known off in OP0, we need not do
9924 else if (code == AND && GET_CODE (op1) == CONST_INT
9925 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9926 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
9929 return gen_rtx_fmt_ee (code, mode, op0, op1);
9932 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9933 comparison code that will be tested.
9935 The result is a possibly different comparison code to use. *POP0 and
9936 *POP1 may be updated.
9938 It is possible that we might detect that a comparison is either always
9939 true or always false. However, we do not perform general constant
9940 folding in combine, so this knowledge isn't useful. Such tautologies
9941 should have been detected earlier. Hence we ignore all such cases. */
9943 static enum rtx_code
9944 simplify_comparison (code, pop0, pop1)
9953 enum machine_mode mode, tmode;
9955 /* Try a few ways of applying the same transformation to both operands. */
9958 #ifndef WORD_REGISTER_OPERATIONS
9959 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9960 so check specially. */
9961 if (code != GTU && code != GEU && code != LTU && code != LEU
9962 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9963 && GET_CODE (XEXP (op0, 0)) == ASHIFT
9964 && GET_CODE (XEXP (op1, 0)) == ASHIFT
9965 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9966 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9967 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
9968 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
9969 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9970 && GET_CODE (XEXP (op1, 1)) == CONST_INT
9971 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
9972 && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT
9973 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (op1, 1))
9974 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op0, 0), 1))
9975 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op1, 0), 1))
9976 && (INTVAL (XEXP (op0, 1))
9977 == (GET_MODE_BITSIZE (GET_MODE (op0))
9979 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
9981 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
9982 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
9986 /* If both operands are the same constant shift, see if we can ignore the
9987 shift. We can if the shift is a rotate or if the bits shifted out of
9988 this shift are known to be zero for both inputs and if the type of
9989 comparison is compatible with the shift. */
9990 if (GET_CODE (op0) == GET_CODE (op1)
9991 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9992 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
9993 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
9994 && (code != GT && code != LT && code != GE && code != LE))
9995 || (GET_CODE (op0) == ASHIFTRT
9996 && (code != GTU && code != LTU
9997 && code != GEU && code != LEU)))
9998 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9999 && INTVAL (XEXP (op0, 1)) >= 0
10000 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10001 && XEXP (op0, 1) == XEXP (op1, 1))
10003 enum machine_mode mode = GET_MODE (op0);
10004 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10005 int shift_count = INTVAL (XEXP (op0, 1));
10007 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
10008 mask &= (mask >> shift_count) << shift_count;
10009 else if (GET_CODE (op0) == ASHIFT)
10010 mask = (mask & (mask << shift_count)) >> shift_count;
10012 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
10013 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
10014 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
10019 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10020 SUBREGs are of the same mode, and, in both cases, the AND would
10021 be redundant if the comparison was done in the narrower mode,
10022 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10023 and the operand's possibly nonzero bits are 0xffffff01; in that case
10024 if we only care about QImode, we don't need the AND). This case
10025 occurs if the output mode of an scc insn is not SImode and
10026 STORE_FLAG_VALUE == 1 (e.g., the 386).
10028 Similarly, check for a case where the AND's are ZERO_EXTEND
10029 operations from some narrower mode even though a SUBREG is not
10032 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
10033 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10034 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
10036 rtx inner_op0 = XEXP (op0, 0);
10037 rtx inner_op1 = XEXP (op1, 0);
10038 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
10039 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
10042 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
10043 && (GET_MODE_SIZE (GET_MODE (inner_op0))
10044 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
10045 && (GET_MODE (SUBREG_REG (inner_op0))
10046 == GET_MODE (SUBREG_REG (inner_op1)))
10047 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
10048 <= HOST_BITS_PER_WIDE_INT)
10049 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
10050 GET_MODE (SUBREG_REG (inner_op0)))))
10051 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
10052 GET_MODE (SUBREG_REG (inner_op1))))))
10054 op0 = SUBREG_REG (inner_op0);
10055 op1 = SUBREG_REG (inner_op1);
10057 /* The resulting comparison is always unsigned since we masked
10058 off the original sign bit. */
10059 code = unsigned_condition (code);
10065 for (tmode = GET_CLASS_NARROWEST_MODE
10066 (GET_MODE_CLASS (GET_MODE (op0)));
10067 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
10068 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
10070 op0 = gen_lowpart_for_combine (tmode, inner_op0);
10071 op1 = gen_lowpart_for_combine (tmode, inner_op1);
10072 code = unsigned_condition (code);
10081 /* If both operands are NOT, we can strip off the outer operation
10082 and adjust the comparison code for swapped operands; similarly for
10083 NEG, except that this must be an equality comparison. */
10084 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
10085 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
10086 && (code == EQ || code == NE)))
10087 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
10093 /* If the first operand is a constant, swap the operands and adjust the
10094 comparison code appropriately, but don't do this if the second operand
10095 is already a constant integer. */
10096 if (swap_commutative_operands_p (op0, op1))
10098 tem = op0, op0 = op1, op1 = tem;
10099 code = swap_condition (code);
10102 /* We now enter a loop during which we will try to simplify the comparison.
10103 For the most part, we only are concerned with comparisons with zero,
10104 but some things may really be comparisons with zero but not start
10105 out looking that way. */
10107 while (GET_CODE (op1) == CONST_INT)
10109 enum machine_mode mode = GET_MODE (op0);
10110 unsigned int mode_width = GET_MODE_BITSIZE (mode);
10111 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10112 int equality_comparison_p;
10113 int sign_bit_comparison_p;
10114 int unsigned_comparison_p;
10115 HOST_WIDE_INT const_op;
10117 /* We only want to handle integral modes. This catches VOIDmode,
10118 CCmode, and the floating-point modes. An exception is that we
10119 can handle VOIDmode if OP0 is a COMPARE or a comparison
10122 if (GET_MODE_CLASS (mode) != MODE_INT
10123 && ! (mode == VOIDmode
10124 && (GET_CODE (op0) == COMPARE
10125 || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
10128 /* Get the constant we are comparing against and turn off all bits
10129 not on in our mode. */
10130 const_op = trunc_int_for_mode (INTVAL (op1), mode);
10131 op1 = GEN_INT (const_op);
10133 /* If we are comparing against a constant power of two and the value
10134 being compared can only have that single bit nonzero (e.g., it was
10135 `and'ed with that bit), we can replace this with a comparison
10138 && (code == EQ || code == NE || code == GE || code == GEU
10139 || code == LT || code == LTU)
10140 && mode_width <= HOST_BITS_PER_WIDE_INT
10141 && exact_log2 (const_op) >= 0
10142 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
10144 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10145 op1 = const0_rtx, const_op = 0;
10148 /* Similarly, if we are comparing a value known to be either -1 or
10149 0 with -1, change it to the opposite comparison against zero. */
10152 && (code == EQ || code == NE || code == GT || code == LE
10153 || code == GEU || code == LTU)
10154 && num_sign_bit_copies (op0, mode) == mode_width)
10156 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10157 op1 = const0_rtx, const_op = 0;
10160 /* Do some canonicalizations based on the comparison code. We prefer
10161 comparisons against zero and then prefer equality comparisons.
10162 If we can reduce the size of a constant, we will do that too. */
10167 /* < C is equivalent to <= (C - 1) */
10171 op1 = GEN_INT (const_op);
10173 /* ... fall through to LE case below. */
10179 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10183 op1 = GEN_INT (const_op);
10187 /* If we are doing a <= 0 comparison on a value known to have
10188 a zero sign bit, we can replace this with == 0. */
10189 else if (const_op == 0
10190 && mode_width <= HOST_BITS_PER_WIDE_INT
10191 && (nonzero_bits (op0, mode)
10192 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10197 /* >= C is equivalent to > (C - 1). */
10201 op1 = GEN_INT (const_op);
10203 /* ... fall through to GT below. */
10209 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10213 op1 = GEN_INT (const_op);
10217 /* If we are doing a > 0 comparison on a value known to have
10218 a zero sign bit, we can replace this with != 0. */
10219 else if (const_op == 0
10220 && mode_width <= HOST_BITS_PER_WIDE_INT
10221 && (nonzero_bits (op0, mode)
10222 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10227 /* < C is equivalent to <= (C - 1). */
10231 op1 = GEN_INT (const_op);
10233 /* ... fall through ... */
10236 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10237 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10238 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10240 const_op = 0, op1 = const0_rtx;
10248 /* unsigned <= 0 is equivalent to == 0 */
10252 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10253 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10254 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10256 const_op = 0, op1 = const0_rtx;
10262 /* >= C is equivalent to < (C - 1). */
10266 op1 = GEN_INT (const_op);
10268 /* ... fall through ... */
10271 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10272 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10273 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10275 const_op = 0, op1 = const0_rtx;
10283 /* unsigned > 0 is equivalent to != 0 */
10287 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10288 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10289 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10291 const_op = 0, op1 = const0_rtx;
10300 /* Compute some predicates to simplify code below. */
10302 equality_comparison_p = (code == EQ || code == NE);
10303 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
10304 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
10307 /* If this is a sign bit comparison and we can do arithmetic in
10308 MODE, say that we will only be needing the sign bit of OP0. */
10309 if (sign_bit_comparison_p
10310 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10311 op0 = force_to_mode (op0, mode,
10313 << (GET_MODE_BITSIZE (mode) - 1)),
10316 /* Now try cases based on the opcode of OP0. If none of the cases
10317 does a "continue", we exit this loop immediately after the
10320 switch (GET_CODE (op0))
10323 /* If we are extracting a single bit from a variable position in
10324 a constant that has only a single bit set and are comparing it
10325 with zero, we can convert this into an equality comparison
10326 between the position and the location of the single bit. */
10328 if (GET_CODE (XEXP (op0, 0)) == CONST_INT
10329 && XEXP (op0, 1) == const1_rtx
10330 && equality_comparison_p && const_op == 0
10331 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
10333 if (BITS_BIG_ENDIAN)
10335 enum machine_mode new_mode
10336 = mode_for_extraction (EP_extzv, 1);
10337 if (new_mode == MAX_MACHINE_MODE)
10338 i = BITS_PER_WORD - 1 - i;
10342 i = (GET_MODE_BITSIZE (mode) - 1 - i);
10346 op0 = XEXP (op0, 2);
10350 /* Result is nonzero iff shift count is equal to I. */
10351 code = reverse_condition (code);
10355 /* ... fall through ... */
10358 tem = expand_compound_operation (op0);
10367 /* If testing for equality, we can take the NOT of the constant. */
10368 if (equality_comparison_p
10369 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
10371 op0 = XEXP (op0, 0);
10376 /* If just looking at the sign bit, reverse the sense of the
10378 if (sign_bit_comparison_p)
10380 op0 = XEXP (op0, 0);
10381 code = (code == GE ? LT : GE);
10387 /* If testing for equality, we can take the NEG of the constant. */
10388 if (equality_comparison_p
10389 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
10391 op0 = XEXP (op0, 0);
10396 /* The remaining cases only apply to comparisons with zero. */
10400 /* When X is ABS or is known positive,
10401 (neg X) is < 0 if and only if X != 0. */
10403 if (sign_bit_comparison_p
10404 && (GET_CODE (XEXP (op0, 0)) == ABS
10405 || (mode_width <= HOST_BITS_PER_WIDE_INT
10406 && (nonzero_bits (XEXP (op0, 0), mode)
10407 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
10409 op0 = XEXP (op0, 0);
10410 code = (code == LT ? NE : EQ);
10414 /* If we have NEG of something whose two high-order bits are the
10415 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10416 if (num_sign_bit_copies (op0, mode) >= 2)
10418 op0 = XEXP (op0, 0);
10419 code = swap_condition (code);
10425 /* If we are testing equality and our count is a constant, we
10426 can perform the inverse operation on our RHS. */
10427 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10428 && (tem = simplify_binary_operation (ROTATERT, mode,
10429 op1, XEXP (op0, 1))) != 0)
10431 op0 = XEXP (op0, 0);
10436 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10437 a particular bit. Convert it to an AND of a constant of that
10438 bit. This will be converted into a ZERO_EXTRACT. */
10439 if (const_op == 0 && sign_bit_comparison_p
10440 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10441 && mode_width <= HOST_BITS_PER_WIDE_INT)
10443 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10446 - INTVAL (XEXP (op0, 1)))));
10447 code = (code == LT ? NE : EQ);
10451 /* Fall through. */
10454 /* ABS is ignorable inside an equality comparison with zero. */
10455 if (const_op == 0 && equality_comparison_p)
10457 op0 = XEXP (op0, 0);
10463 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10464 to (compare FOO CONST) if CONST fits in FOO's mode and we
10465 are either testing inequality or have an unsigned comparison
10466 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10467 if (! unsigned_comparison_p
10468 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10469 <= HOST_BITS_PER_WIDE_INT)
10470 && ((unsigned HOST_WIDE_INT) const_op
10471 < (((unsigned HOST_WIDE_INT) 1
10472 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
10474 op0 = XEXP (op0, 0);
10480 /* Check for the case where we are comparing A - C1 with C2,
10481 both constants are smaller than 1/2 the maximum positive
10482 value in MODE, and the comparison is equality or unsigned.
10483 In that case, if A is either zero-extended to MODE or has
10484 sufficient sign bits so that the high-order bit in MODE
10485 is a copy of the sign in the inner mode, we can prove that it is
10486 safe to do the operation in the wider mode. This simplifies
10487 many range checks. */
10489 if (mode_width <= HOST_BITS_PER_WIDE_INT
10490 && subreg_lowpart_p (op0)
10491 && GET_CODE (SUBREG_REG (op0)) == PLUS
10492 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
10493 && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
10494 && (-INTVAL (XEXP (SUBREG_REG (op0), 1))
10495 < (HOST_WIDE_INT) (GET_MODE_MASK (mode) / 2))
10496 && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2
10497 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0),
10498 GET_MODE (SUBREG_REG (op0)))
10499 & ~GET_MODE_MASK (mode))
10500 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
10501 GET_MODE (SUBREG_REG (op0)))
10502 > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10503 - GET_MODE_BITSIZE (mode)))))
10505 op0 = SUBREG_REG (op0);
10509 /* If the inner mode is narrower and we are extracting the low part,
10510 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10511 if (subreg_lowpart_p (op0)
10512 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10513 /* Fall through */ ;
10517 /* ... fall through ... */
10520 if ((unsigned_comparison_p || equality_comparison_p)
10521 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10522 <= HOST_BITS_PER_WIDE_INT)
10523 && ((unsigned HOST_WIDE_INT) const_op
10524 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
10526 op0 = XEXP (op0, 0);
10532 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10533 this for equality comparisons due to pathological cases involving
10535 if (equality_comparison_p
10536 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10537 op1, XEXP (op0, 1))))
10539 op0 = XEXP (op0, 0);
10544 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10545 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10546 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10548 op0 = XEXP (XEXP (op0, 0), 0);
10549 code = (code == LT ? EQ : NE);
10555 /* We used to optimize signed comparisons against zero, but that
10556 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10557 arrive here as equality comparisons, or (GEU, LTU) are
10558 optimized away. No need to special-case them. */
10560 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10561 (eq B (minus A C)), whichever simplifies. We can only do
10562 this for equality comparisons due to pathological cases involving
10564 if (equality_comparison_p
10565 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10566 XEXP (op0, 1), op1)))
10568 op0 = XEXP (op0, 0);
10573 if (equality_comparison_p
10574 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10575 XEXP (op0, 0), op1)))
10577 op0 = XEXP (op0, 1);
10582 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10583 of bits in X minus 1, is one iff X > 0. */
10584 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10585 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10586 && INTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
10587 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10589 op0 = XEXP (op0, 1);
10590 code = (code == GE ? LE : GT);
10596 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10597 if C is zero or B is a constant. */
10598 if (equality_comparison_p
10599 && 0 != (tem = simplify_binary_operation (XOR, mode,
10600 XEXP (op0, 1), op1)))
10602 op0 = XEXP (op0, 0);
10609 case UNEQ: case LTGT:
10610 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
10611 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
10612 case UNORDERED: case ORDERED:
10613 /* We can't do anything if OP0 is a condition code value, rather
10614 than an actual data value. */
10617 || XEXP (op0, 0) == cc0_rtx
10619 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10622 /* Get the two operands being compared. */
10623 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10624 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10626 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10628 /* Check for the cases where we simply want the result of the
10629 earlier test or the opposite of that result. */
10630 if (code == NE || code == EQ
10631 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10632 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10633 && (STORE_FLAG_VALUE
10634 & (((HOST_WIDE_INT) 1
10635 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10636 && (code == LT || code == GE)))
10638 enum rtx_code new_code;
10639 if (code == LT || code == NE)
10640 new_code = GET_CODE (op0);
10642 new_code = combine_reversed_comparison_code (op0);
10644 if (new_code != UNKNOWN)
10655 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
10657 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10658 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10659 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10661 op0 = XEXP (op0, 1);
10662 code = (code == GE ? GT : LE);
10668 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10669 will be converted to a ZERO_EXTRACT later. */
10670 if (const_op == 0 && equality_comparison_p
10671 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10672 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10674 op0 = simplify_and_const_int
10675 (op0, mode, gen_rtx_LSHIFTRT (mode,
10677 XEXP (XEXP (op0, 0), 1)),
10678 (HOST_WIDE_INT) 1);
10682 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10683 zero and X is a comparison and C1 and C2 describe only bits set
10684 in STORE_FLAG_VALUE, we can compare with X. */
10685 if (const_op == 0 && equality_comparison_p
10686 && mode_width <= HOST_BITS_PER_WIDE_INT
10687 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10688 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10689 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10690 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10691 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10693 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10694 << INTVAL (XEXP (XEXP (op0, 0), 1)));
10695 if ((~STORE_FLAG_VALUE & mask) == 0
10696 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
10697 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10698 && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
10700 op0 = XEXP (XEXP (op0, 0), 0);
10705 /* If we are doing an equality comparison of an AND of a bit equal
10706 to the sign bit, replace this with a LT or GE comparison of
10707 the underlying value. */
10708 if (equality_comparison_p
10710 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10711 && mode_width <= HOST_BITS_PER_WIDE_INT
10712 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10713 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10715 op0 = XEXP (op0, 0);
10716 code = (code == EQ ? GE : LT);
10720 /* If this AND operation is really a ZERO_EXTEND from a narrower
10721 mode, the constant fits within that mode, and this is either an
10722 equality or unsigned comparison, try to do this comparison in
10723 the narrower mode. */
10724 if ((equality_comparison_p || unsigned_comparison_p)
10725 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10726 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10727 & GET_MODE_MASK (mode))
10729 && const_op >> i == 0
10730 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
10732 op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
10736 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1 fits
10737 in both M1 and M2 and the SUBREG is either paradoxical or
10738 represents the low part, permute the SUBREG and the AND and
10740 if (GET_CODE (XEXP (op0, 0)) == SUBREG
10742 #ifdef WORD_REGISTER_OPERATIONS
10744 > (GET_MODE_BITSIZE
10745 (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10746 && mode_width <= BITS_PER_WORD)
10749 <= (GET_MODE_BITSIZE
10750 (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10751 && subreg_lowpart_p (XEXP (op0, 0))))
10752 #ifndef WORD_REGISTER_OPERATIONS
10753 /* It is unsafe to commute the AND into the SUBREG if the SUBREG
10754 is paradoxical and WORD_REGISTER_OPERATIONS is not defined.
10755 As originally written the upper bits have a defined value
10756 due to the AND operation. However, if we commute the AND
10757 inside the SUBREG then they no longer have defined values
10758 and the meaning of the code has been changed. */
10759 && (GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)))
10760 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0)))))
10762 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10763 && mode_width <= HOST_BITS_PER_WIDE_INT
10764 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
10765 <= HOST_BITS_PER_WIDE_INT)
10766 && (INTVAL (XEXP (op0, 1)) & ~mask) == 0
10767 && 0 == (~GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
10768 & INTVAL (XEXP (op0, 1)))
10769 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1)) != mask
10770 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10771 != GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10775 = gen_lowpart_for_combine
10777 gen_binary (AND, GET_MODE (SUBREG_REG (XEXP (op0, 0))),
10778 SUBREG_REG (XEXP (op0, 0)), XEXP (op0, 1)));
10782 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10783 (eq (and (lshiftrt X) 1) 0). */
10784 if (const_op == 0 && equality_comparison_p
10785 && XEXP (op0, 1) == const1_rtx
10786 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10787 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == NOT)
10789 op0 = simplify_and_const_int
10791 gen_rtx_LSHIFTRT (mode, XEXP (XEXP (XEXP (op0, 0), 0), 0),
10792 XEXP (XEXP (op0, 0), 1)),
10793 (HOST_WIDE_INT) 1);
10794 code = (code == NE ? EQ : NE);
10800 /* If we have (compare (ashift FOO N) (const_int C)) and
10801 the high order N bits of FOO (N+1 if an inequality comparison)
10802 are known to be zero, we can do this by comparing FOO with C
10803 shifted right N bits so long as the low-order N bits of C are
10805 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10806 && INTVAL (XEXP (op0, 1)) >= 0
10807 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10808 < HOST_BITS_PER_WIDE_INT)
10810 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10811 && mode_width <= HOST_BITS_PER_WIDE_INT
10812 && (nonzero_bits (XEXP (op0, 0), mode)
10813 & ~(mask >> (INTVAL (XEXP (op0, 1))
10814 + ! equality_comparison_p))) == 0)
10816 /* We must perform a logical shift, not an arithmetic one,
10817 as we want the top N bits of C to be zero. */
10818 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
10820 temp >>= INTVAL (XEXP (op0, 1));
10821 op1 = gen_int_mode (temp, mode);
10822 op0 = XEXP (op0, 0);
10826 /* If we are doing a sign bit comparison, it means we are testing
10827 a particular bit. Convert it to the appropriate AND. */
10828 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10829 && mode_width <= HOST_BITS_PER_WIDE_INT)
10831 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10834 - INTVAL (XEXP (op0, 1)))));
10835 code = (code == LT ? NE : EQ);
10839 /* If this an equality comparison with zero and we are shifting
10840 the low bit to the sign bit, we can convert this to an AND of the
10842 if (const_op == 0 && equality_comparison_p
10843 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10844 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
10846 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10847 (HOST_WIDE_INT) 1);
10853 /* If this is an equality comparison with zero, we can do this
10854 as a logical shift, which might be much simpler. */
10855 if (equality_comparison_p && const_op == 0
10856 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10858 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10860 INTVAL (XEXP (op0, 1)));
10864 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10865 do the comparison in a narrower mode. */
10866 if (! unsigned_comparison_p
10867 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10868 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10869 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10870 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10871 MODE_INT, 1)) != BLKmode
10872 && (((unsigned HOST_WIDE_INT) const_op
10873 + (GET_MODE_MASK (tmode) >> 1) + 1)
10874 <= GET_MODE_MASK (tmode)))
10876 op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
10880 /* Likewise if OP0 is a PLUS of a sign extension with a
10881 constant, which is usually represented with the PLUS
10882 between the shifts. */
10883 if (! unsigned_comparison_p
10884 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10885 && GET_CODE (XEXP (op0, 0)) == PLUS
10886 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10887 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
10888 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
10889 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10890 MODE_INT, 1)) != BLKmode
10891 && (((unsigned HOST_WIDE_INT) const_op
10892 + (GET_MODE_MASK (tmode) >> 1) + 1)
10893 <= GET_MODE_MASK (tmode)))
10895 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
10896 rtx add_const = XEXP (XEXP (op0, 0), 1);
10897 rtx new_const = gen_binary (ASHIFTRT, GET_MODE (op0), add_const,
10900 op0 = gen_binary (PLUS, tmode,
10901 gen_lowpart_for_combine (tmode, inner),
10906 /* ... fall through ... */
10908 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10909 the low order N bits of FOO are known to be zero, we can do this
10910 by comparing FOO with C shifted left N bits so long as no
10911 overflow occurs. */
10912 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10913 && INTVAL (XEXP (op0, 1)) >= 0
10914 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10915 && mode_width <= HOST_BITS_PER_WIDE_INT
10916 && (nonzero_bits (XEXP (op0, 0), mode)
10917 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
10918 && (((unsigned HOST_WIDE_INT) const_op
10919 + (GET_CODE (op0) != LSHIFTRT
10920 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
10923 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
10925 /* If the shift was logical, then we must make the condition
10927 if (GET_CODE (op0) == LSHIFTRT)
10928 code = unsigned_condition (code);
10930 const_op <<= INTVAL (XEXP (op0, 1));
10931 op1 = GEN_INT (const_op);
10932 op0 = XEXP (op0, 0);
10936 /* If we are using this shift to extract just the sign bit, we
10937 can replace this with an LT or GE comparison. */
10939 && (equality_comparison_p || sign_bit_comparison_p)
10940 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10941 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
10943 op0 = XEXP (op0, 0);
10944 code = (code == NE || code == GT ? LT : GE);
10956 /* Now make any compound operations involved in this comparison. Then,
10957 check for an outmost SUBREG on OP0 that is not doing anything or is
10958 paradoxical. The latter transformation must only be performed when
10959 it is known that the "extra" bits will be the same in op0 and op1 or
10960 that they don't matter. There are three cases to consider:
10962 1. SUBREG_REG (op0) is a register. In this case the bits are don't
10963 care bits and we can assume they have any convenient value. So
10964 making the transformation is safe.
10966 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
10967 In this case the upper bits of op0 are undefined. We should not make
10968 the simplification in that case as we do not know the contents of
10971 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
10972 NIL. In that case we know those bits are zeros or ones. We must
10973 also be sure that they are the same as the upper bits of op1.
10975 We can never remove a SUBREG for a non-equality comparison because
10976 the sign bit is in a different place in the underlying object. */
10978 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
10979 op1 = make_compound_operation (op1, SET);
10981 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10982 /* Case 3 above, to sometimes allow (subreg (mem x)), isn't
10984 && GET_CODE (SUBREG_REG (op0)) == REG
10985 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10986 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
10987 && (code == NE || code == EQ))
10989 if (GET_MODE_SIZE (GET_MODE (op0))
10990 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
10992 op0 = SUBREG_REG (op0);
10993 op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
10995 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10996 <= HOST_BITS_PER_WIDE_INT)
10997 && (nonzero_bits (SUBREG_REG (op0),
10998 GET_MODE (SUBREG_REG (op0)))
10999 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11001 tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)), op1);
11003 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
11004 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11005 op0 = SUBREG_REG (op0), op1 = tem;
11009 /* We now do the opposite procedure: Some machines don't have compare
11010 insns in all modes. If OP0's mode is an integer mode smaller than a
11011 word and we can't do a compare in that mode, see if there is a larger
11012 mode for which we can do the compare. There are a number of cases in
11013 which we can use the wider mode. */
11015 mode = GET_MODE (op0);
11016 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11017 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
11018 && ! have_insn_for (COMPARE, mode))
11019 for (tmode = GET_MODE_WIDER_MODE (mode);
11021 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
11022 tmode = GET_MODE_WIDER_MODE (tmode))
11023 if (have_insn_for (COMPARE, tmode))
11027 /* If the only nonzero bits in OP0 and OP1 are those in the
11028 narrower mode and this is an equality or unsigned comparison,
11029 we can use the wider mode. Similarly for sign-extended
11030 values, in which case it is true for all comparisons. */
11031 zero_extended = ((code == EQ || code == NE
11032 || code == GEU || code == GTU
11033 || code == LEU || code == LTU)
11034 && (nonzero_bits (op0, tmode)
11035 & ~GET_MODE_MASK (mode)) == 0
11036 && ((GET_CODE (op1) == CONST_INT
11037 || (nonzero_bits (op1, tmode)
11038 & ~GET_MODE_MASK (mode)) == 0)));
11041 || ((num_sign_bit_copies (op0, tmode)
11042 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))
11043 && (num_sign_bit_copies (op1, tmode)
11044 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))))
11046 /* If OP0 is an AND and we don't have an AND in MODE either,
11047 make a new AND in the proper mode. */
11048 if (GET_CODE (op0) == AND
11049 && !have_insn_for (AND, mode))
11050 op0 = gen_binary (AND, tmode,
11051 gen_lowpart_for_combine (tmode,
11053 gen_lowpart_for_combine (tmode,
11056 op0 = gen_lowpart_for_combine (tmode, op0);
11057 if (zero_extended && GET_CODE (op1) == CONST_INT)
11058 op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode));
11059 op1 = gen_lowpart_for_combine (tmode, op1);
11063 /* If this is a test for negative, we can make an explicit
11064 test of the sign bit. */
11066 if (op1 == const0_rtx && (code == LT || code == GE)
11067 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11069 op0 = gen_binary (AND, tmode,
11070 gen_lowpart_for_combine (tmode, op0),
11071 GEN_INT ((HOST_WIDE_INT) 1
11072 << (GET_MODE_BITSIZE (mode) - 1)));
11073 code = (code == LT) ? NE : EQ;
11078 #ifdef CANONICALIZE_COMPARISON
11079 /* If this machine only supports a subset of valid comparisons, see if we
11080 can convert an unsupported one into a supported one. */
11081 CANONICALIZE_COMPARISON (code, op0, op1);
11090 /* Like jump.c' reversed_comparison_code, but use combine infrastructure for
11091 searching backward. */
11092 static enum rtx_code
11093 combine_reversed_comparison_code (exp)
11096 enum rtx_code code1 = reversed_comparison_code (exp, NULL);
11099 if (code1 != UNKNOWN
11100 || GET_MODE_CLASS (GET_MODE (XEXP (exp, 0))) != MODE_CC)
11102 /* Otherwise try and find where the condition codes were last set and
11104 x = get_last_value (XEXP (exp, 0));
11105 if (!x || GET_CODE (x) != COMPARE)
11107 return reversed_comparison_code_parts (GET_CODE (exp),
11108 XEXP (x, 0), XEXP (x, 1), NULL);
11110 /* Return comparison with reversed code of EXP and operands OP0 and OP1.
11111 Return NULL_RTX in case we fail to do the reversal. */
11113 reversed_comparison (exp, mode, op0, op1)
11115 enum machine_mode mode;
11117 enum rtx_code reversed_code = combine_reversed_comparison_code (exp);
11118 if (reversed_code == UNKNOWN)
11121 return gen_binary (reversed_code, mode, op0, op1);
11124 /* Utility function for following routine. Called when X is part of a value
11125 being stored into reg_last_set_value. Sets reg_last_set_table_tick
11126 for each register mentioned. Similar to mention_regs in cse.c */
11129 update_table_tick (x)
11132 enum rtx_code code = GET_CODE (x);
11133 const char *fmt = GET_RTX_FORMAT (code);
11138 unsigned int regno = REGNO (x);
11139 unsigned int endregno
11140 = regno + (regno < FIRST_PSEUDO_REGISTER
11141 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11144 for (r = regno; r < endregno; r++)
11145 reg_last_set_table_tick[r] = label_tick;
11150 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11151 /* Note that we can't have an "E" in values stored; see
11152 get_last_value_validate. */
11154 update_table_tick (XEXP (x, i));
11157 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11158 are saying that the register is clobbered and we no longer know its
11159 value. If INSN is zero, don't update reg_last_set; this is only permitted
11160 with VALUE also zero and is used to invalidate the register. */
11163 record_value_for_reg (reg, insn, value)
11168 unsigned int regno = REGNO (reg);
11169 unsigned int endregno
11170 = regno + (regno < FIRST_PSEUDO_REGISTER
11171 ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
11174 /* If VALUE contains REG and we have a previous value for REG, substitute
11175 the previous value. */
11176 if (value && insn && reg_overlap_mentioned_p (reg, value))
11180 /* Set things up so get_last_value is allowed to see anything set up to
11182 subst_low_cuid = INSN_CUID (insn);
11183 tem = get_last_value (reg);
11185 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11186 it isn't going to be useful and will take a lot of time to process,
11187 so just use the CLOBBER. */
11191 if ((GET_RTX_CLASS (GET_CODE (tem)) == '2'
11192 || GET_RTX_CLASS (GET_CODE (tem)) == 'c')
11193 && GET_CODE (XEXP (tem, 0)) == CLOBBER
11194 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
11195 tem = XEXP (tem, 0);
11197 value = replace_rtx (copy_rtx (value), reg, tem);
11201 /* For each register modified, show we don't know its value, that
11202 we don't know about its bitwise content, that its value has been
11203 updated, and that we don't know the location of the death of the
11205 for (i = regno; i < endregno; i++)
11208 reg_last_set[i] = insn;
11210 reg_last_set_value[i] = 0;
11211 reg_last_set_mode[i] = 0;
11212 reg_last_set_nonzero_bits[i] = 0;
11213 reg_last_set_sign_bit_copies[i] = 0;
11214 reg_last_death[i] = 0;
11217 /* Mark registers that are being referenced in this value. */
11219 update_table_tick (value);
11221 /* Now update the status of each register being set.
11222 If someone is using this register in this block, set this register
11223 to invalid since we will get confused between the two lives in this
11224 basic block. This makes using this register always invalid. In cse, we
11225 scan the table to invalidate all entries using this register, but this
11226 is too much work for us. */
11228 for (i = regno; i < endregno; i++)
11230 reg_last_set_label[i] = label_tick;
11231 if (value && reg_last_set_table_tick[i] == label_tick)
11232 reg_last_set_invalid[i] = 1;
11234 reg_last_set_invalid[i] = 0;
11237 /* The value being assigned might refer to X (like in "x++;"). In that
11238 case, we must replace it with (clobber (const_int 0)) to prevent
11240 if (value && ! get_last_value_validate (&value, insn,
11241 reg_last_set_label[regno], 0))
11243 value = copy_rtx (value);
11244 if (! get_last_value_validate (&value, insn,
11245 reg_last_set_label[regno], 1))
11249 /* For the main register being modified, update the value, the mode, the
11250 nonzero bits, and the number of sign bit copies. */
11252 reg_last_set_value[regno] = value;
11256 enum machine_mode mode = GET_MODE (reg);
11257 subst_low_cuid = INSN_CUID (insn);
11258 reg_last_set_mode[regno] = mode;
11259 if (GET_MODE_CLASS (mode) == MODE_INT
11260 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11261 mode = nonzero_bits_mode;
11262 reg_last_set_nonzero_bits[regno] = nonzero_bits (value, mode);
11263 reg_last_set_sign_bit_copies[regno]
11264 = num_sign_bit_copies (value, GET_MODE (reg));
11268 /* Called via note_stores from record_dead_and_set_regs to handle one
11269 SET or CLOBBER in an insn. DATA is the instruction in which the
11270 set is occurring. */
11273 record_dead_and_set_regs_1 (dest, setter, data)
11277 rtx record_dead_insn = (rtx) data;
11279 if (GET_CODE (dest) == SUBREG)
11280 dest = SUBREG_REG (dest);
11282 if (GET_CODE (dest) == REG)
11284 /* If we are setting the whole register, we know its value. Otherwise
11285 show that we don't know the value. We can handle SUBREG in
11287 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
11288 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
11289 else if (GET_CODE (setter) == SET
11290 && GET_CODE (SET_DEST (setter)) == SUBREG
11291 && SUBREG_REG (SET_DEST (setter)) == dest
11292 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
11293 && subreg_lowpart_p (SET_DEST (setter)))
11294 record_value_for_reg (dest, record_dead_insn,
11295 gen_lowpart_for_combine (GET_MODE (dest),
11296 SET_SRC (setter)));
11298 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
11300 else if (GET_CODE (dest) == MEM
11301 /* Ignore pushes, they clobber nothing. */
11302 && ! push_operand (dest, GET_MODE (dest)))
11303 mem_last_set = INSN_CUID (record_dead_insn);
11306 /* Update the records of when each REG was most recently set or killed
11307 for the things done by INSN. This is the last thing done in processing
11308 INSN in the combiner loop.
11310 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
11311 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
11312 and also the similar information mem_last_set (which insn most recently
11313 modified memory) and last_call_cuid (which insn was the most recent
11314 subroutine call). */
11317 record_dead_and_set_regs (insn)
11323 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11325 if (REG_NOTE_KIND (link) == REG_DEAD
11326 && GET_CODE (XEXP (link, 0)) == REG)
11328 unsigned int regno = REGNO (XEXP (link, 0));
11329 unsigned int endregno
11330 = regno + (regno < FIRST_PSEUDO_REGISTER
11331 ? HARD_REGNO_NREGS (regno, GET_MODE (XEXP (link, 0)))
11334 for (i = regno; i < endregno; i++)
11335 reg_last_death[i] = insn;
11337 else if (REG_NOTE_KIND (link) == REG_INC)
11338 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11341 if (GET_CODE (insn) == CALL_INSN)
11343 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11344 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
11346 reg_last_set_value[i] = 0;
11347 reg_last_set_mode[i] = 0;
11348 reg_last_set_nonzero_bits[i] = 0;
11349 reg_last_set_sign_bit_copies[i] = 0;
11350 reg_last_death[i] = 0;
11353 last_call_cuid = mem_last_set = INSN_CUID (insn);
11355 /* Don't bother recording what this insn does. It might set the
11356 return value register, but we can't combine into a call
11357 pattern anyway, so there's no point trying (and it may cause
11358 a crash, if e.g. we wind up asking for last_set_value of a
11359 SUBREG of the return value register). */
11363 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11366 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11367 register present in the SUBREG, so for each such SUBREG go back and
11368 adjust nonzero and sign bit information of the registers that are
11369 known to have some zero/sign bits set.
11371 This is needed because when combine blows the SUBREGs away, the
11372 information on zero/sign bits is lost and further combines can be
11373 missed because of that. */
11376 record_promoted_value (insn, subreg)
11381 unsigned int regno = REGNO (SUBREG_REG (subreg));
11382 enum machine_mode mode = GET_MODE (subreg);
11384 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11387 for (links = LOG_LINKS (insn); links;)
11389 insn = XEXP (links, 0);
11390 set = single_set (insn);
11392 if (! set || GET_CODE (SET_DEST (set)) != REG
11393 || REGNO (SET_DEST (set)) != regno
11394 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11396 links = XEXP (links, 1);
11400 if (reg_last_set[regno] == insn)
11402 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
11403 reg_last_set_nonzero_bits[regno] &= GET_MODE_MASK (mode);
11406 if (GET_CODE (SET_SRC (set)) == REG)
11408 regno = REGNO (SET_SRC (set));
11409 links = LOG_LINKS (insn);
11416 /* Scan X for promoted SUBREGs. For each one found,
11417 note what it implies to the registers used in it. */
11420 check_promoted_subreg (insn, x)
11424 if (GET_CODE (x) == SUBREG && SUBREG_PROMOTED_VAR_P (x)
11425 && GET_CODE (SUBREG_REG (x)) == REG)
11426 record_promoted_value (insn, x);
11429 const char *format = GET_RTX_FORMAT (GET_CODE (x));
11432 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11436 check_promoted_subreg (insn, XEXP (x, i));
11440 if (XVEC (x, i) != 0)
11441 for (j = 0; j < XVECLEN (x, i); j++)
11442 check_promoted_subreg (insn, XVECEXP (x, i, j));
11448 /* Utility routine for the following function. Verify that all the registers
11449 mentioned in *LOC are valid when *LOC was part of a value set when
11450 label_tick == TICK. Return 0 if some are not.
11452 If REPLACE is non-zero, replace the invalid reference with
11453 (clobber (const_int 0)) and return 1. This replacement is useful because
11454 we often can get useful information about the form of a value (e.g., if
11455 it was produced by a shift that always produces -1 or 0) even though
11456 we don't know exactly what registers it was produced from. */
11459 get_last_value_validate (loc, insn, tick, replace)
11466 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11467 int len = GET_RTX_LENGTH (GET_CODE (x));
11470 if (GET_CODE (x) == REG)
11472 unsigned int regno = REGNO (x);
11473 unsigned int endregno
11474 = regno + (regno < FIRST_PSEUDO_REGISTER
11475 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11478 for (j = regno; j < endregno; j++)
11479 if (reg_last_set_invalid[j]
11480 /* If this is a pseudo-register that was only set once and not
11481 live at the beginning of the function, it is always valid. */
11482 || (! (regno >= FIRST_PSEUDO_REGISTER
11483 && REG_N_SETS (regno) == 1
11484 && (! REGNO_REG_SET_P
11485 (BASIC_BLOCK (0)->global_live_at_start, regno)))
11486 && reg_last_set_label[j] > tick))
11489 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11495 /* If this is a memory reference, make sure that there were
11496 no stores after it that might have clobbered the value. We don't
11497 have alias info, so we assume any store invalidates it. */
11498 else if (GET_CODE (x) == MEM && ! RTX_UNCHANGING_P (x)
11499 && INSN_CUID (insn) <= mem_last_set)
11502 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11506 for (i = 0; i < len; i++)
11508 && get_last_value_validate (&XEXP (x, i), insn, tick, replace) == 0)
11509 /* Don't bother with these. They shouldn't occur anyway. */
11513 /* If we haven't found a reason for it to be invalid, it is valid. */
11517 /* Get the last value assigned to X, if known. Some registers
11518 in the value may be replaced with (clobber (const_int 0)) if their value
11519 is known longer known reliably. */
11525 unsigned int regno;
11528 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11529 then convert it to the desired mode. If this is a paradoxical SUBREG,
11530 we cannot predict what values the "extra" bits might have. */
11531 if (GET_CODE (x) == SUBREG
11532 && subreg_lowpart_p (x)
11533 && (GET_MODE_SIZE (GET_MODE (x))
11534 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11535 && (value = get_last_value (SUBREG_REG (x))) != 0)
11536 return gen_lowpart_for_combine (GET_MODE (x), value);
11538 if (GET_CODE (x) != REG)
11542 value = reg_last_set_value[regno];
11544 /* If we don't have a value, or if it isn't for this basic block and
11545 it's either a hard register, set more than once, or it's a live
11546 at the beginning of the function, return 0.
11548 Because if it's not live at the beginning of the function then the reg
11549 is always set before being used (is never used without being set).
11550 And, if it's set only once, and it's always set before use, then all
11551 uses must have the same last value, even if it's not from this basic
11555 || (reg_last_set_label[regno] != label_tick
11556 && (regno < FIRST_PSEUDO_REGISTER
11557 || REG_N_SETS (regno) != 1
11558 || (REGNO_REG_SET_P
11559 (BASIC_BLOCK (0)->global_live_at_start, regno)))))
11562 /* If the value was set in a later insn than the ones we are processing,
11563 we can't use it even if the register was only set once. */
11564 if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)
11567 /* If the value has all its registers valid, return it. */
11568 if (get_last_value_validate (&value, reg_last_set[regno],
11569 reg_last_set_label[regno], 0))
11572 /* Otherwise, make a copy and replace any invalid register with
11573 (clobber (const_int 0)). If that fails for some reason, return 0. */
11575 value = copy_rtx (value);
11576 if (get_last_value_validate (&value, reg_last_set[regno],
11577 reg_last_set_label[regno], 1))
11583 /* Return nonzero if expression X refers to a REG or to memory
11584 that is set in an instruction more recent than FROM_CUID. */
11587 use_crosses_set_p (x, from_cuid)
11593 enum rtx_code code = GET_CODE (x);
11597 unsigned int regno = REGNO (x);
11598 unsigned endreg = regno + (regno < FIRST_PSEUDO_REGISTER
11599 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11601 #ifdef PUSH_ROUNDING
11602 /* Don't allow uses of the stack pointer to be moved,
11603 because we don't know whether the move crosses a push insn. */
11604 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11607 for (; regno < endreg; regno++)
11608 if (reg_last_set[regno]
11609 && INSN_CUID (reg_last_set[regno]) > from_cuid)
11614 if (code == MEM && mem_last_set > from_cuid)
11617 fmt = GET_RTX_FORMAT (code);
11619 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11624 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11625 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
11628 else if (fmt[i] == 'e'
11629 && use_crosses_set_p (XEXP (x, i), from_cuid))
11635 /* Define three variables used for communication between the following
11638 static unsigned int reg_dead_regno, reg_dead_endregno;
11639 static int reg_dead_flag;
11641 /* Function called via note_stores from reg_dead_at_p.
11643 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11644 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11647 reg_dead_at_p_1 (dest, x, data)
11650 void *data ATTRIBUTE_UNUSED;
11652 unsigned int regno, endregno;
11654 if (GET_CODE (dest) != REG)
11657 regno = REGNO (dest);
11658 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
11659 ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
11661 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11662 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11665 /* Return non-zero if REG is known to be dead at INSN.
11667 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11668 referencing REG, it is dead. If we hit a SET referencing REG, it is
11669 live. Otherwise, see if it is live or dead at the start of the basic
11670 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11671 must be assumed to be always live. */
11674 reg_dead_at_p (reg, insn)
11681 /* Set variables for reg_dead_at_p_1. */
11682 reg_dead_regno = REGNO (reg);
11683 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
11684 ? HARD_REGNO_NREGS (reg_dead_regno,
11690 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
11691 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11693 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11694 if (TEST_HARD_REG_BIT (newpat_used_regs, i))
11698 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11699 beginning of function. */
11700 for (; insn && GET_CODE (insn) != CODE_LABEL && GET_CODE (insn) != BARRIER;
11701 insn = prev_nonnote_insn (insn))
11703 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
11705 return reg_dead_flag == 1 ? 1 : 0;
11707 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11711 /* Get the basic block number that we were in. */
11716 for (block = 0; block < n_basic_blocks; block++)
11717 if (insn == BLOCK_HEAD (block))
11720 if (block == n_basic_blocks)
11724 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11725 if (REGNO_REG_SET_P (BASIC_BLOCK (block)->global_live_at_start, i))
11731 /* Note hard registers in X that are used. This code is similar to
11732 that in flow.c, but much simpler since we don't care about pseudos. */
11735 mark_used_regs_combine (x)
11738 RTX_CODE code = GET_CODE (x);
11739 unsigned int regno;
11752 case ADDR_DIFF_VEC:
11755 /* CC0 must die in the insn after it is set, so we don't need to take
11756 special note of it here. */
11762 /* If we are clobbering a MEM, mark any hard registers inside the
11763 address as used. */
11764 if (GET_CODE (XEXP (x, 0)) == MEM)
11765 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
11770 /* A hard reg in a wide mode may really be multiple registers.
11771 If so, mark all of them just like the first. */
11772 if (regno < FIRST_PSEUDO_REGISTER)
11774 unsigned int endregno, r;
11776 /* None of this applies to the stack, frame or arg pointers */
11777 if (regno == STACK_POINTER_REGNUM
11778 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11779 || regno == HARD_FRAME_POINTER_REGNUM
11781 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11782 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
11784 || regno == FRAME_POINTER_REGNUM)
11787 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11788 for (r = regno; r < endregno; r++)
11789 SET_HARD_REG_BIT (newpat_used_regs, r);
11795 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11797 rtx testreg = SET_DEST (x);
11799 while (GET_CODE (testreg) == SUBREG
11800 || GET_CODE (testreg) == ZERO_EXTRACT
11801 || GET_CODE (testreg) == SIGN_EXTRACT
11802 || GET_CODE (testreg) == STRICT_LOW_PART)
11803 testreg = XEXP (testreg, 0);
11805 if (GET_CODE (testreg) == MEM)
11806 mark_used_regs_combine (XEXP (testreg, 0));
11808 mark_used_regs_combine (SET_SRC (x));
11816 /* Recursively scan the operands of this expression. */
11819 const char *fmt = GET_RTX_FORMAT (code);
11821 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11824 mark_used_regs_combine (XEXP (x, i));
11825 else if (fmt[i] == 'E')
11829 for (j = 0; j < XVECLEN (x, i); j++)
11830 mark_used_regs_combine (XVECEXP (x, i, j));
11836 /* Remove register number REGNO from the dead registers list of INSN.
11838 Return the note used to record the death, if there was one. */
11841 remove_death (regno, insn)
11842 unsigned int regno;
11845 rtx note = find_regno_note (insn, REG_DEAD, regno);
11849 REG_N_DEATHS (regno)--;
11850 remove_note (insn, note);
11856 /* For each register (hardware or pseudo) used within expression X, if its
11857 death is in an instruction with cuid between FROM_CUID (inclusive) and
11858 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11859 list headed by PNOTES.
11861 That said, don't move registers killed by maybe_kill_insn.
11863 This is done when X is being merged by combination into TO_INSN. These
11864 notes will then be distributed as needed. */
11867 move_deaths (x, maybe_kill_insn, from_cuid, to_insn, pnotes)
11869 rtx maybe_kill_insn;
11876 enum rtx_code code = GET_CODE (x);
11880 unsigned int regno = REGNO (x);
11881 rtx where_dead = reg_last_death[regno];
11882 rtx before_dead, after_dead;
11884 /* Don't move the register if it gets killed in between from and to */
11885 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
11886 && ! reg_referenced_p (x, maybe_kill_insn))
11889 /* WHERE_DEAD could be a USE insn made by combine, so first we
11890 make sure that we have insns with valid INSN_CUID values. */
11891 before_dead = where_dead;
11892 while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
11893 before_dead = PREV_INSN (before_dead);
11895 after_dead = where_dead;
11896 while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
11897 after_dead = NEXT_INSN (after_dead);
11899 if (before_dead && after_dead
11900 && INSN_CUID (before_dead) >= from_cuid
11901 && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
11902 || (where_dead != after_dead
11903 && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
11905 rtx note = remove_death (regno, where_dead);
11907 /* It is possible for the call above to return 0. This can occur
11908 when reg_last_death points to I2 or I1 that we combined with.
11909 In that case make a new note.
11911 We must also check for the case where X is a hard register
11912 and NOTE is a death note for a range of hard registers
11913 including X. In that case, we must put REG_DEAD notes for
11914 the remaining registers in place of NOTE. */
11916 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
11917 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11918 > GET_MODE_SIZE (GET_MODE (x))))
11920 unsigned int deadregno = REGNO (XEXP (note, 0));
11921 unsigned int deadend
11922 = (deadregno + HARD_REGNO_NREGS (deadregno,
11923 GET_MODE (XEXP (note, 0))));
11924 unsigned int ourend
11925 = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11928 for (i = deadregno; i < deadend; i++)
11929 if (i < regno || i >= ourend)
11930 REG_NOTES (where_dead)
11931 = gen_rtx_EXPR_LIST (REG_DEAD,
11932 gen_rtx_REG (reg_raw_mode[i], i),
11933 REG_NOTES (where_dead));
11936 /* If we didn't find any note, or if we found a REG_DEAD note that
11937 covers only part of the given reg, and we have a multi-reg hard
11938 register, then to be safe we must check for REG_DEAD notes
11939 for each register other than the first. They could have
11940 their own REG_DEAD notes lying around. */
11941 else if ((note == 0
11943 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11944 < GET_MODE_SIZE (GET_MODE (x)))))
11945 && regno < FIRST_PSEUDO_REGISTER
11946 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
11948 unsigned int ourend
11949 = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11950 unsigned int i, offset;
11954 offset = HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0)));
11958 for (i = regno + offset; i < ourend; i++)
11959 move_deaths (gen_rtx_REG (reg_raw_mode[i], i),
11960 maybe_kill_insn, from_cuid, to_insn, &oldnotes);
11963 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
11965 XEXP (note, 1) = *pnotes;
11969 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
11971 REG_N_DEATHS (regno)++;
11977 else if (GET_CODE (x) == SET)
11979 rtx dest = SET_DEST (x);
11981 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
11983 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11984 that accesses one word of a multi-word item, some
11985 piece of everything register in the expression is used by
11986 this insn, so remove any old death. */
11987 /* ??? So why do we test for equality of the sizes? */
11989 if (GET_CODE (dest) == ZERO_EXTRACT
11990 || GET_CODE (dest) == STRICT_LOW_PART
11991 || (GET_CODE (dest) == SUBREG
11992 && (((GET_MODE_SIZE (GET_MODE (dest))
11993 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
11994 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
11995 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
11997 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
12001 /* If this is some other SUBREG, we know it replaces the entire
12002 value, so use that as the destination. */
12003 if (GET_CODE (dest) == SUBREG)
12004 dest = SUBREG_REG (dest);
12006 /* If this is a MEM, adjust deaths of anything used in the address.
12007 For a REG (the only other possibility), the entire value is
12008 being replaced so the old value is not used in this insn. */
12010 if (GET_CODE (dest) == MEM)
12011 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
12016 else if (GET_CODE (x) == CLOBBER)
12019 len = GET_RTX_LENGTH (code);
12020 fmt = GET_RTX_FORMAT (code);
12022 for (i = 0; i < len; i++)
12027 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12028 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
12031 else if (fmt[i] == 'e')
12032 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
12036 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12037 pattern of an insn. X must be a REG. */
12040 reg_bitfield_target_p (x, body)
12046 if (GET_CODE (body) == SET)
12048 rtx dest = SET_DEST (body);
12050 unsigned int regno, tregno, endregno, endtregno;
12052 if (GET_CODE (dest) == ZERO_EXTRACT)
12053 target = XEXP (dest, 0);
12054 else if (GET_CODE (dest) == STRICT_LOW_PART)
12055 target = SUBREG_REG (XEXP (dest, 0));
12059 if (GET_CODE (target) == SUBREG)
12060 target = SUBREG_REG (target);
12062 if (GET_CODE (target) != REG)
12065 tregno = REGNO (target), regno = REGNO (x);
12066 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
12067 return target == x;
12069 endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target));
12070 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
12072 return endregno > tregno && regno < endtregno;
12075 else if (GET_CODE (body) == PARALLEL)
12076 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
12077 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
12083 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12084 as appropriate. I3 and I2 are the insns resulting from the combination
12085 insns including FROM (I2 may be zero).
12087 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
12088 not need REG_DEAD notes because they are being substituted for. This
12089 saves searching in the most common cases.
12091 Each note in the list is either ignored or placed on some insns, depending
12092 on the type of note. */
12095 distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1)
12099 rtx elim_i2, elim_i1;
12101 rtx note, next_note;
12104 for (note = notes; note; note = next_note)
12106 rtx place = 0, place2 = 0;
12108 /* If this NOTE references a pseudo register, ensure it references
12109 the latest copy of that register. */
12110 if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
12111 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
12112 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
12114 next_note = XEXP (note, 1);
12115 switch (REG_NOTE_KIND (note))
12119 case REG_EXEC_COUNT:
12120 /* Doesn't matter much where we put this, as long as it's somewhere.
12121 It is preferable to keep these notes on branches, which is most
12122 likely to be i3. */
12126 case REG_VTABLE_REF:
12127 /* ??? Should remain with *a particular* memory load. Given the
12128 nature of vtable data, the last insn seems relatively safe. */
12132 case REG_NON_LOCAL_GOTO:
12133 if (GET_CODE (i3) == JUMP_INSN)
12135 else if (i2 && GET_CODE (i2) == JUMP_INSN)
12141 case REG_EH_REGION:
12142 /* These notes must remain with the call or trapping instruction. */
12143 if (GET_CODE (i3) == CALL_INSN)
12145 else if (i2 && GET_CODE (i2) == CALL_INSN)
12147 else if (flag_non_call_exceptions)
12149 if (may_trap_p (i3))
12151 else if (i2 && may_trap_p (i2))
12153 /* ??? Otherwise assume we've combined things such that we
12154 can now prove that the instructions can't trap. Drop the
12155 note in this case. */
12163 /* These notes must remain with the call. It should not be
12164 possible for both I2 and I3 to be a call. */
12165 if (GET_CODE (i3) == CALL_INSN)
12167 else if (i2 && GET_CODE (i2) == CALL_INSN)
12174 /* Any clobbers for i3 may still exist, and so we must process
12175 REG_UNUSED notes from that insn.
12177 Any clobbers from i2 or i1 can only exist if they were added by
12178 recog_for_combine. In that case, recog_for_combine created the
12179 necessary REG_UNUSED notes. Trying to keep any original
12180 REG_UNUSED notes from these insns can cause incorrect output
12181 if it is for the same register as the original i3 dest.
12182 In that case, we will notice that the register is set in i3,
12183 and then add a REG_UNUSED note for the destination of i3, which
12184 is wrong. However, it is possible to have REG_UNUSED notes from
12185 i2 or i1 for register which were both used and clobbered, so
12186 we keep notes from i2 or i1 if they will turn into REG_DEAD
12189 /* If this register is set or clobbered in I3, put the note there
12190 unless there is one already. */
12191 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
12193 if (from_insn != i3)
12196 if (! (GET_CODE (XEXP (note, 0)) == REG
12197 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
12198 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
12201 /* Otherwise, if this register is used by I3, then this register
12202 now dies here, so we must put a REG_DEAD note here unless there
12204 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
12205 && ! (GET_CODE (XEXP (note, 0)) == REG
12206 ? find_regno_note (i3, REG_DEAD,
12207 REGNO (XEXP (note, 0)))
12208 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
12210 PUT_REG_NOTE_KIND (note, REG_DEAD);
12218 /* These notes say something about results of an insn. We can
12219 only support them if they used to be on I3 in which case they
12220 remain on I3. Otherwise they are ignored.
12222 If the note refers to an expression that is not a constant, we
12223 must also ignore the note since we cannot tell whether the
12224 equivalence is still true. It might be possible to do
12225 slightly better than this (we only have a problem if I2DEST
12226 or I1DEST is present in the expression), but it doesn't
12227 seem worth the trouble. */
12229 if (from_insn == i3
12230 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
12235 case REG_NO_CONFLICT:
12236 /* These notes say something about how a register is used. They must
12237 be present on any use of the register in I2 or I3. */
12238 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
12241 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
12251 /* This can show up in several ways -- either directly in the
12252 pattern, or hidden off in the constant pool with (or without?)
12253 a REG_EQUAL note. */
12254 /* ??? Ignore the without-reg_equal-note problem for now. */
12255 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
12256 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
12257 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12258 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
12262 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
12263 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
12264 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12265 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12273 /* Don't attach REG_LABEL note to a JUMP_INSN which has
12274 JUMP_LABEL already. Instead, decrement LABEL_NUSES. */
12275 if (place && GET_CODE (place) == JUMP_INSN && JUMP_LABEL (place))
12277 if (JUMP_LABEL (place) != XEXP (note, 0))
12279 if (GET_CODE (JUMP_LABEL (place)) == CODE_LABEL)
12280 LABEL_NUSES (JUMP_LABEL (place))--;
12283 if (place2 && GET_CODE (place2) == JUMP_INSN && JUMP_LABEL (place2))
12285 if (JUMP_LABEL (place2) != XEXP (note, 0))
12287 if (GET_CODE (JUMP_LABEL (place2)) == CODE_LABEL)
12288 LABEL_NUSES (JUMP_LABEL (place2))--;
12295 /* These notes say something about the value of a register prior
12296 to the execution of an insn. It is too much trouble to see
12297 if the note is still correct in all situations. It is better
12298 to simply delete it. */
12302 /* If the insn previously containing this note still exists,
12303 put it back where it was. Otherwise move it to the previous
12304 insn. Adjust the corresponding REG_LIBCALL note. */
12305 if (GET_CODE (from_insn) != NOTE)
12309 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
12310 place = prev_real_insn (from_insn);
12312 XEXP (tem, 0) = place;
12313 /* If we're deleting the last remaining instruction of a
12314 libcall sequence, don't add the notes. */
12315 else if (XEXP (note, 0) == from_insn)
12321 /* This is handled similarly to REG_RETVAL. */
12322 if (GET_CODE (from_insn) != NOTE)
12326 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
12327 place = next_real_insn (from_insn);
12329 XEXP (tem, 0) = place;
12330 /* If we're deleting the last remaining instruction of a
12331 libcall sequence, don't add the notes. */
12332 else if (XEXP (note, 0) == from_insn)
12338 /* If the register is used as an input in I3, it dies there.
12339 Similarly for I2, if it is non-zero and adjacent to I3.
12341 If the register is not used as an input in either I3 or I2
12342 and it is not one of the registers we were supposed to eliminate,
12343 there are two possibilities. We might have a non-adjacent I2
12344 or we might have somehow eliminated an additional register
12345 from a computation. For example, we might have had A & B where
12346 we discover that B will always be zero. In this case we will
12347 eliminate the reference to A.
12349 In both cases, we must search to see if we can find a previous
12350 use of A and put the death note there. */
12353 && GET_CODE (from_insn) == CALL_INSN
12354 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12356 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12358 else if (i2 != 0 && next_nonnote_insn (i2) == i3
12359 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12362 if (rtx_equal_p (XEXP (note, 0), elim_i2)
12363 || rtx_equal_p (XEXP (note, 0), elim_i1))
12368 basic_block bb = BASIC_BLOCK (this_basic_block);
12370 for (tem = PREV_INSN (i3); place == 0; tem = PREV_INSN (tem))
12372 if (! INSN_P (tem))
12374 if (tem == bb->head)
12379 /* If the register is being set at TEM, see if that is all
12380 TEM is doing. If so, delete TEM. Otherwise, make this
12381 into a REG_UNUSED note instead. */
12382 if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
12384 rtx set = single_set (tem);
12385 rtx inner_dest = 0;
12387 rtx cc0_setter = NULL_RTX;
12391 for (inner_dest = SET_DEST (set);
12392 (GET_CODE (inner_dest) == STRICT_LOW_PART
12393 || GET_CODE (inner_dest) == SUBREG
12394 || GET_CODE (inner_dest) == ZERO_EXTRACT);
12395 inner_dest = XEXP (inner_dest, 0))
12398 /* Verify that it was the set, and not a clobber that
12399 modified the register.
12401 CC0 targets must be careful to maintain setter/user
12402 pairs. If we cannot delete the setter due to side
12403 effects, mark the user with an UNUSED note instead
12406 if (set != 0 && ! side_effects_p (SET_SRC (set))
12407 && rtx_equal_p (XEXP (note, 0), inner_dest)
12409 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12410 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12411 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12415 /* Move the notes and links of TEM elsewhere.
12416 This might delete other dead insns recursively.
12417 First set the pattern to something that won't use
12420 PATTERN (tem) = pc_rtx;
12422 distribute_notes (REG_NOTES (tem), tem, tem,
12423 NULL_RTX, NULL_RTX, NULL_RTX);
12424 distribute_links (LOG_LINKS (tem));
12426 PUT_CODE (tem, NOTE);
12427 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
12428 NOTE_SOURCE_FILE (tem) = 0;
12431 /* Delete the setter too. */
12434 PATTERN (cc0_setter) = pc_rtx;
12436 distribute_notes (REG_NOTES (cc0_setter),
12437 cc0_setter, cc0_setter,
12438 NULL_RTX, NULL_RTX, NULL_RTX);
12439 distribute_links (LOG_LINKS (cc0_setter));
12441 PUT_CODE (cc0_setter, NOTE);
12442 NOTE_LINE_NUMBER (cc0_setter)
12443 = NOTE_INSN_DELETED;
12444 NOTE_SOURCE_FILE (cc0_setter) = 0;
12448 /* If the register is both set and used here, put the
12449 REG_DEAD note here, but place a REG_UNUSED note
12450 here too unless there already is one. */
12451 else if (reg_referenced_p (XEXP (note, 0),
12456 if (! find_regno_note (tem, REG_UNUSED,
12457 REGNO (XEXP (note, 0))))
12459 = gen_rtx_EXPR_LIST (REG_UNUSED, XEXP (note, 0),
12464 PUT_REG_NOTE_KIND (note, REG_UNUSED);
12466 /* If there isn't already a REG_UNUSED note, put one
12468 if (! find_regno_note (tem, REG_UNUSED,
12469 REGNO (XEXP (note, 0))))
12474 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12475 || (GET_CODE (tem) == CALL_INSN
12476 && find_reg_fusage (tem, USE, XEXP (note, 0))))
12480 /* If we are doing a 3->2 combination, and we have a
12481 register which formerly died in i3 and was not used
12482 by i2, which now no longer dies in i3 and is used in
12483 i2 but does not die in i2, and place is between i2
12484 and i3, then we may need to move a link from place to
12486 if (i2 && INSN_UID (place) <= max_uid_cuid
12487 && INSN_CUID (place) > INSN_CUID (i2)
12489 && INSN_CUID (from_insn) > INSN_CUID (i2)
12490 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12492 rtx links = LOG_LINKS (place);
12493 LOG_LINKS (place) = 0;
12494 distribute_links (links);
12499 if (tem == bb->head)
12503 /* We haven't found an insn for the death note and it
12504 is still a REG_DEAD note, but we have hit the beginning
12505 of the block. If the existing life info says the reg
12506 was dead, there's nothing left to do. Otherwise, we'll
12507 need to do a global life update after combine. */
12508 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0
12509 && REGNO_REG_SET_P (bb->global_live_at_start,
12510 REGNO (XEXP (note, 0))))
12512 SET_BIT (refresh_blocks, this_basic_block);
12517 /* If the register is set or already dead at PLACE, we needn't do
12518 anything with this note if it is still a REG_DEAD note.
12519 We can here if it is set at all, not if is it totally replace,
12520 which is what `dead_or_set_p' checks, so also check for it being
12523 if (place && REG_NOTE_KIND (note) == REG_DEAD)
12525 unsigned int regno = REGNO (XEXP (note, 0));
12527 /* Similarly, if the instruction on which we want to place
12528 the note is a noop, we'll need do a global live update
12529 after we remove them in delete_noop_moves. */
12530 if (noop_move_p (place))
12532 SET_BIT (refresh_blocks, this_basic_block);
12536 if (dead_or_set_p (place, XEXP (note, 0))
12537 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12539 /* Unless the register previously died in PLACE, clear
12540 reg_last_death. [I no longer understand why this is
12542 if (reg_last_death[regno] != place)
12543 reg_last_death[regno] = 0;
12547 reg_last_death[regno] = place;
12549 /* If this is a death note for a hard reg that is occupying
12550 multiple registers, ensure that we are still using all
12551 parts of the object. If we find a piece of the object
12552 that is unused, we must arrange for an appropriate REG_DEAD
12553 note to be added for it. However, we can't just emit a USE
12554 and tag the note to it, since the register might actually
12555 be dead; so we recourse, and the recursive call then finds
12556 the previous insn that used this register. */
12558 if (place && regno < FIRST_PSEUDO_REGISTER
12559 && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
12561 unsigned int endregno
12562 = regno + HARD_REGNO_NREGS (regno,
12563 GET_MODE (XEXP (note, 0)));
12567 for (i = regno; i < endregno; i++)
12568 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12569 && ! find_regno_fusage (place, USE, i))
12570 || dead_or_set_regno_p (place, i))
12575 /* Put only REG_DEAD notes for pieces that are
12576 not already dead or set. */
12578 for (i = regno; i < endregno;
12579 i += HARD_REGNO_NREGS (i, reg_raw_mode[i]))
12581 rtx piece = gen_rtx_REG (reg_raw_mode[i], i);
12582 basic_block bb = BASIC_BLOCK (this_basic_block);
12584 if (! dead_or_set_p (place, piece)
12585 && ! reg_bitfield_target_p (piece,
12589 = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX);
12591 distribute_notes (new_note, place, place,
12592 NULL_RTX, NULL_RTX, NULL_RTX);
12594 else if (! refers_to_regno_p (i, i + 1,
12595 PATTERN (place), 0)
12596 && ! find_regno_fusage (place, USE, i))
12597 for (tem = PREV_INSN (place); ;
12598 tem = PREV_INSN (tem))
12600 if (! INSN_P (tem))
12602 if (tem == bb->head)
12604 SET_BIT (refresh_blocks,
12611 if (dead_or_set_p (tem, piece)
12612 || reg_bitfield_target_p (piece,
12616 = gen_rtx_EXPR_LIST (REG_UNUSED, piece,
12631 /* Any other notes should not be present at this point in the
12638 XEXP (note, 1) = REG_NOTES (place);
12639 REG_NOTES (place) = note;
12641 else if ((REG_NOTE_KIND (note) == REG_DEAD
12642 || REG_NOTE_KIND (note) == REG_UNUSED)
12643 && GET_CODE (XEXP (note, 0)) == REG)
12644 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
12648 if ((REG_NOTE_KIND (note) == REG_DEAD
12649 || REG_NOTE_KIND (note) == REG_UNUSED)
12650 && GET_CODE (XEXP (note, 0)) == REG)
12651 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
12653 REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
12654 REG_NOTE_KIND (note),
12656 REG_NOTES (place2));
12661 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12662 I3, I2, and I1 to new locations. This is also called in one case to
12663 add a link pointing at I3 when I3's destination is changed. */
12666 distribute_links (links)
12669 rtx link, next_link;
12671 for (link = links; link; link = next_link)
12677 next_link = XEXP (link, 1);
12679 /* If the insn that this link points to is a NOTE or isn't a single
12680 set, ignore it. In the latter case, it isn't clear what we
12681 can do other than ignore the link, since we can't tell which
12682 register it was for. Such links wouldn't be used by combine
12685 It is not possible for the destination of the target of the link to
12686 have been changed by combine. The only potential of this is if we
12687 replace I3, I2, and I1 by I3 and I2. But in that case the
12688 destination of I2 also remains unchanged. */
12690 if (GET_CODE (XEXP (link, 0)) == NOTE
12691 || (set = single_set (XEXP (link, 0))) == 0)
12694 reg = SET_DEST (set);
12695 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12696 || GET_CODE (reg) == SIGN_EXTRACT
12697 || GET_CODE (reg) == STRICT_LOW_PART)
12698 reg = XEXP (reg, 0);
12700 /* A LOG_LINK is defined as being placed on the first insn that uses
12701 a register and points to the insn that sets the register. Start
12702 searching at the next insn after the target of the link and stop
12703 when we reach a set of the register or the end of the basic block.
12705 Note that this correctly handles the link that used to point from
12706 I3 to I2. Also note that not much searching is typically done here
12707 since most links don't point very far away. */
12709 for (insn = NEXT_INSN (XEXP (link, 0));
12710 (insn && (this_basic_block == n_basic_blocks - 1
12711 || BLOCK_HEAD (this_basic_block + 1) != insn));
12712 insn = NEXT_INSN (insn))
12713 if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12715 if (reg_referenced_p (reg, PATTERN (insn)))
12719 else if (GET_CODE (insn) == CALL_INSN
12720 && find_reg_fusage (insn, USE, reg))
12726 /* If we found a place to put the link, place it there unless there
12727 is already a link to the same insn as LINK at that point. */
12733 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12734 if (XEXP (link2, 0) == XEXP (link, 0))
12739 XEXP (link, 1) = LOG_LINKS (place);
12740 LOG_LINKS (place) = link;
12742 /* Set added_links_insn to the earliest insn we added a
12744 if (added_links_insn == 0
12745 || INSN_CUID (added_links_insn) > INSN_CUID (place))
12746 added_links_insn = place;
12752 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12758 while (insn != 0 && INSN_UID (insn) > max_uid_cuid
12759 && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE)
12760 insn = NEXT_INSN (insn);
12762 if (INSN_UID (insn) > max_uid_cuid)
12765 return INSN_CUID (insn);
12769 dump_combine_stats (file)
12774 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12775 combine_attempts, combine_merges, combine_extras, combine_successes);
12779 dump_combine_total_stats (file)
12784 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12785 total_attempts, total_merges, total_extras, total_successes);