1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
87 #include "hard-reg-set.h"
88 #include "basic-block.h"
89 #include "insn-config.h"
91 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
93 #include "insn-attr.h"
99 #include "insn-codes.h"
100 #include "rtlhooks-def.h"
101 /* Include output.h for dump_file. */
105 #include "tree-pass.h"
109 /* Number of attempts to combine instructions in this function. */
111 static int combine_attempts;
113 /* Number of attempts that got as far as substitution in this function. */
115 static int combine_merges;
117 /* Number of instructions combined with added SETs in this function. */
119 static int combine_extras;
121 /* Number of instructions combined in this function. */
123 static int combine_successes;
125 /* Totals over entire compilation. */
127 static int total_attempts, total_merges, total_extras, total_successes;
129 /* combine_instructions may try to replace the right hand side of the
130 second instruction with the value of an associated REG_EQUAL note
131 before throwing it at try_combine. That is problematic when there
132 is a REG_DEAD note for a register used in the old right hand side
133 and can cause distribute_notes to do wrong things. This is the
134 second instruction if it has been so modified, null otherwise. */
138 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
140 static rtx i2mod_old_rhs;
142 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
144 static rtx i2mod_new_rhs;
146 typedef struct reg_stat_struct {
147 /* Record last point of death of (hard or pseudo) register n. */
150 /* Record last point of modification of (hard or pseudo) register n. */
153 /* The next group of fields allows the recording of the last value assigned
154 to (hard or pseudo) register n. We use this information to see if an
155 operation being processed is redundant given a prior operation performed
156 on the register. For example, an `and' with a constant is redundant if
157 all the zero bits are already known to be turned off.
159 We use an approach similar to that used by cse, but change it in the
162 (1) We do not want to reinitialize at each label.
163 (2) It is useful, but not critical, to know the actual value assigned
164 to a register. Often just its form is helpful.
166 Therefore, we maintain the following fields:
168 last_set_value the last value assigned
169 last_set_label records the value of label_tick when the
170 register was assigned
171 last_set_table_tick records the value of label_tick when a
172 value using the register is assigned
173 last_set_invalid set to nonzero when it is not valid
174 to use the value of this register in some
177 To understand the usage of these tables, it is important to understand
178 the distinction between the value in last_set_value being valid and
179 the register being validly contained in some other expression in the
182 (The next two parameters are out of date).
184 reg_stat[i].last_set_value is valid if it is nonzero, and either
185 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
187 Register I may validly appear in any expression returned for the value
188 of another register if reg_n_sets[i] is 1. It may also appear in the
189 value for register J if reg_stat[j].last_set_invalid is zero, or
190 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
192 If an expression is found in the table containing a register which may
193 not validly appear in an expression, the register is replaced by
194 something that won't match, (clobber (const_int 0)). */
196 /* Record last value assigned to (hard or pseudo) register n. */
200 /* Record the value of label_tick when an expression involving register n
201 is placed in last_set_value. */
203 int last_set_table_tick;
205 /* Record the value of label_tick when the value for register n is placed in
210 /* These fields are maintained in parallel with last_set_value and are
211 used to store the mode in which the register was last set, the bits
212 that were known to be zero when it was last set, and the number of
213 sign bits copies it was known to have when it was last set. */
215 unsigned HOST_WIDE_INT last_set_nonzero_bits;
216 char last_set_sign_bit_copies;
217 ENUM_BITFIELD(machine_mode) last_set_mode : 8;
219 /* Set nonzero if references to register n in expressions should not be
220 used. last_set_invalid is set nonzero when this register is being
221 assigned to and last_set_table_tick == label_tick. */
223 char last_set_invalid;
225 /* Some registers that are set more than once and used in more than one
226 basic block are nevertheless always set in similar ways. For example,
227 a QImode register may be loaded from memory in two places on a machine
228 where byte loads zero extend.
230 We record in the following fields if a register has some leading bits
231 that are always equal to the sign bit, and what we know about the
232 nonzero bits of a register, specifically which bits are known to be
235 If an entry is zero, it means that we don't know anything special. */
237 unsigned char sign_bit_copies;
239 unsigned HOST_WIDE_INT nonzero_bits;
241 /* Record the value of the label_tick when the last truncation
242 happened. The field truncated_to_mode is only valid if
243 truncation_label == label_tick. */
245 int truncation_label;
247 /* Record the last truncation seen for this register. If truncation
248 is not a nop to this mode we might be able to save an explicit
249 truncation if we know that value already contains a truncated
252 ENUM_BITFIELD(machine_mode) truncated_to_mode : 8;
255 DEF_VEC_O(reg_stat_type);
256 DEF_VEC_ALLOC_O(reg_stat_type,heap);
258 static VEC(reg_stat_type,heap) *reg_stat;
260 /* Record the luid of the last insn that invalidated memory
261 (anything that writes memory, and subroutine calls, but not pushes). */
263 static int mem_last_set;
265 /* Record the luid of the last CALL_INSN
266 so we can tell whether a potential combination crosses any calls. */
268 static int last_call_luid;
270 /* When `subst' is called, this is the insn that is being modified
271 (by combining in a previous insn). The PATTERN of this insn
272 is still the old pattern partially modified and it should not be
273 looked at, but this may be used to examine the successors of the insn
274 to judge whether a simplification is valid. */
276 static rtx subst_insn;
278 /* This is the lowest LUID that `subst' is currently dealing with.
279 get_last_value will not return a value if the register was set at or
280 after this LUID. If not for this mechanism, we could get confused if
281 I2 or I1 in try_combine were an insn that used the old value of a register
282 to obtain a new value. In that case, we might erroneously get the
283 new value of the register when we wanted the old one. */
285 static int subst_low_luid;
287 /* This contains any hard registers that are used in newpat; reg_dead_at_p
288 must consider all these registers to be always live. */
290 static HARD_REG_SET newpat_used_regs;
292 /* This is an insn to which a LOG_LINKS entry has been added. If this
293 insn is the earlier than I2 or I3, combine should rescan starting at
296 static rtx added_links_insn;
298 /* Basic block in which we are performing combines. */
299 static basic_block this_basic_block;
300 static bool optimize_this_for_speed_p;
303 /* Length of the currently allocated uid_insn_cost array. */
305 static int max_uid_known;
307 /* The following array records the insn_rtx_cost for every insn
308 in the instruction stream. */
310 static int *uid_insn_cost;
312 /* The following array records the LOG_LINKS for every insn in the
313 instruction stream as an INSN_LIST rtx. */
315 static rtx *uid_log_links;
317 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
318 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
320 /* Incremented for each basic block. */
322 static int label_tick;
324 /* Reset to label_tick for each label. */
326 static int label_tick_ebb_start;
328 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
329 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
331 static enum machine_mode nonzero_bits_mode;
333 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
334 be safely used. It is zero while computing them and after combine has
335 completed. This former test prevents propagating values based on
336 previously set values, which can be incorrect if a variable is modified
339 static int nonzero_sign_valid;
342 /* Record one modification to rtl structure
343 to be undone by storing old_contents into *where. */
348 enum { UNDO_RTX, UNDO_INT, UNDO_MODE } kind;
349 union { rtx r; int i; enum machine_mode m; } old_contents;
350 union { rtx *r; int *i; } where;
353 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
354 num_undo says how many are currently recorded.
356 other_insn is nonzero if we have modified some other insn in the process
357 of working on subst_insn. It must be verified too. */
366 static struct undobuf undobuf;
368 /* Number of times the pseudo being substituted for
369 was found and replaced. */
371 static int n_occurrences;
373 static rtx reg_nonzero_bits_for_combine (const_rtx, enum machine_mode, const_rtx,
375 unsigned HOST_WIDE_INT,
376 unsigned HOST_WIDE_INT *);
377 static rtx reg_num_sign_bit_copies_for_combine (const_rtx, enum machine_mode, const_rtx,
379 unsigned int, unsigned int *);
380 static void do_SUBST (rtx *, rtx);
381 static void do_SUBST_INT (int *, int);
382 static void init_reg_last (void);
383 static void setup_incoming_promotions (rtx);
384 static void set_nonzero_bits_and_sign_copies (rtx, const_rtx, void *);
385 static int cant_combine_insn_p (rtx);
386 static int can_combine_p (rtx, rtx, rtx, rtx, rtx *, rtx *);
387 static int combinable_i3pat (rtx, rtx *, rtx, rtx, int, rtx *);
388 static int contains_muldiv (rtx);
389 static rtx try_combine (rtx, rtx, rtx, int *);
390 static void undo_all (void);
391 static void undo_commit (void);
392 static rtx *find_split_point (rtx *, rtx);
393 static rtx subst (rtx, rtx, rtx, int, int);
394 static rtx combine_simplify_rtx (rtx, enum machine_mode, int);
395 static rtx simplify_if_then_else (rtx);
396 static rtx simplify_set (rtx);
397 static rtx simplify_logical (rtx);
398 static rtx expand_compound_operation (rtx);
399 static const_rtx expand_field_assignment (const_rtx);
400 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
401 rtx, unsigned HOST_WIDE_INT, int, int, int);
402 static rtx extract_left_shift (rtx, int);
403 static rtx make_compound_operation (rtx, enum rtx_code);
404 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
405 unsigned HOST_WIDE_INT *);
406 static rtx canon_reg_for_combine (rtx, rtx);
407 static rtx force_to_mode (rtx, enum machine_mode,
408 unsigned HOST_WIDE_INT, int);
409 static rtx if_then_else_cond (rtx, rtx *, rtx *);
410 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
411 static int rtx_equal_for_field_assignment_p (rtx, rtx);
412 static rtx make_field_assignment (rtx);
413 static rtx apply_distributive_law (rtx);
414 static rtx distribute_and_simplify_rtx (rtx, int);
415 static rtx simplify_and_const_int_1 (enum machine_mode, rtx,
416 unsigned HOST_WIDE_INT);
417 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
418 unsigned HOST_WIDE_INT);
419 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
420 HOST_WIDE_INT, enum machine_mode, int *);
421 static rtx simplify_shift_const_1 (enum rtx_code, enum machine_mode, rtx, int);
422 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
424 static int recog_for_combine (rtx *, rtx, rtx *);
425 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
426 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
427 static void update_table_tick (rtx);
428 static void record_value_for_reg (rtx, rtx, rtx);
429 static void check_promoted_subreg (rtx, rtx);
430 static void record_dead_and_set_regs_1 (rtx, const_rtx, void *);
431 static void record_dead_and_set_regs (rtx);
432 static int get_last_value_validate (rtx *, rtx, int, int);
433 static rtx get_last_value (const_rtx);
434 static int use_crosses_set_p (const_rtx, int);
435 static void reg_dead_at_p_1 (rtx, const_rtx, void *);
436 static int reg_dead_at_p (rtx, rtx);
437 static void move_deaths (rtx, rtx, int, rtx, rtx *);
438 static int reg_bitfield_target_p (rtx, rtx);
439 static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx);
440 static void distribute_links (rtx);
441 static void mark_used_regs_combine (rtx);
442 static void record_promoted_value (rtx, rtx);
443 static int unmentioned_reg_p_1 (rtx *, void *);
444 static bool unmentioned_reg_p (rtx, rtx);
445 static int record_truncated_value (rtx *, void *);
446 static void record_truncated_values (rtx *, void *);
447 static bool reg_truncated_to_mode (enum machine_mode, const_rtx);
448 static rtx gen_lowpart_or_truncate (enum machine_mode, rtx);
451 /* It is not safe to use ordinary gen_lowpart in combine.
452 See comments in gen_lowpart_for_combine. */
453 #undef RTL_HOOKS_GEN_LOWPART
454 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
456 /* Our implementation of gen_lowpart never emits a new pseudo. */
457 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
458 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
460 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
461 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
463 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
464 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
466 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
467 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
469 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
472 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
473 PATTERN can not be split. Otherwise, it returns an insn sequence.
474 This is a wrapper around split_insns which ensures that the
475 reg_stat vector is made larger if the splitter creates a new
479 combine_split_insns (rtx pattern, rtx insn)
484 ret = split_insns (pattern, insn);
485 nregs = max_reg_num ();
486 if (nregs > VEC_length (reg_stat_type, reg_stat))
487 VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
491 /* This is used by find_single_use to locate an rtx in LOC that
492 contains exactly one use of DEST, which is typically either a REG
493 or CC0. It returns a pointer to the innermost rtx expression
494 containing DEST. Appearances of DEST that are being used to
495 totally replace it are not counted. */
498 find_single_use_1 (rtx dest, rtx *loc)
501 enum rtx_code code = GET_CODE (x);
519 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
520 of a REG that occupies all of the REG, the insn uses DEST if
521 it is mentioned in the destination or the source. Otherwise, we
522 need just check the source. */
523 if (GET_CODE (SET_DEST (x)) != CC0
524 && GET_CODE (SET_DEST (x)) != PC
525 && !REG_P (SET_DEST (x))
526 && ! (GET_CODE (SET_DEST (x)) == SUBREG
527 && REG_P (SUBREG_REG (SET_DEST (x)))
528 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
529 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
530 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
531 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))))
534 return find_single_use_1 (dest, &SET_SRC (x));
538 return find_single_use_1 (dest, &XEXP (x, 0));
544 /* If it wasn't one of the common cases above, check each expression and
545 vector of this code. Look for a unique usage of DEST. */
547 fmt = GET_RTX_FORMAT (code);
548 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
552 if (dest == XEXP (x, i)
553 || (REG_P (dest) && REG_P (XEXP (x, i))
554 && REGNO (dest) == REGNO (XEXP (x, i))))
557 this_result = find_single_use_1 (dest, &XEXP (x, i));
560 result = this_result;
561 else if (this_result)
562 /* Duplicate usage. */
565 else if (fmt[i] == 'E')
569 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
571 if (XVECEXP (x, i, j) == dest
573 && REG_P (XVECEXP (x, i, j))
574 && REGNO (XVECEXP (x, i, j)) == REGNO (dest)))
577 this_result = find_single_use_1 (dest, &XVECEXP (x, i, j));
580 result = this_result;
581 else if (this_result)
591 /* See if DEST, produced in INSN, is used only a single time in the
592 sequel. If so, return a pointer to the innermost rtx expression in which
595 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
597 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
598 care about REG_DEAD notes or LOG_LINKS.
600 Otherwise, we find the single use by finding an insn that has a
601 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
602 only referenced once in that insn, we know that it must be the first
603 and last insn referencing DEST. */
606 find_single_use (rtx dest, rtx insn, rtx *ploc)
616 next = NEXT_INSN (insn);
618 || (!NONJUMP_INSN_P (next) && !JUMP_P (next)))
621 result = find_single_use_1 (dest, &PATTERN (next));
631 bb = BLOCK_FOR_INSN (insn);
632 for (next = NEXT_INSN (insn);
633 next && BLOCK_FOR_INSN (next) == bb;
634 next = NEXT_INSN (next))
635 if (INSN_P (next) && dead_or_set_p (next, dest))
637 for (link = LOG_LINKS (next); link; link = XEXP (link, 1))
638 if (XEXP (link, 0) == insn)
643 result = find_single_use_1 (dest, &PATTERN (next));
653 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
654 insn. The substitution can be undone by undo_all. If INTO is already
655 set to NEWVAL, do not record this change. Because computing NEWVAL might
656 also call SUBST, we have to compute it before we put anything into
660 do_SUBST (rtx *into, rtx newval)
665 if (oldval == newval)
668 /* We'd like to catch as many invalid transformations here as
669 possible. Unfortunately, there are way too many mode changes
670 that are perfectly valid, so we'd waste too much effort for
671 little gain doing the checks here. Focus on catching invalid
672 transformations involving integer constants. */
673 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
674 && GET_CODE (newval) == CONST_INT)
676 /* Sanity check that we're replacing oldval with a CONST_INT
677 that is a valid sign-extension for the original mode. */
678 gcc_assert (INTVAL (newval)
679 == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
681 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
682 CONST_INT is not valid, because after the replacement, the
683 original mode would be gone. Unfortunately, we can't tell
684 when do_SUBST is called to replace the operand thereof, so we
685 perform this test on oldval instead, checking whether an
686 invalid replacement took place before we got here. */
687 gcc_assert (!(GET_CODE (oldval) == SUBREG
688 && GET_CODE (SUBREG_REG (oldval)) == CONST_INT));
689 gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
690 && GET_CODE (XEXP (oldval, 0)) == CONST_INT));
694 buf = undobuf.frees, undobuf.frees = buf->next;
696 buf = XNEW (struct undo);
698 buf->kind = UNDO_RTX;
700 buf->old_contents.r = oldval;
703 buf->next = undobuf.undos, undobuf.undos = buf;
706 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
708 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
709 for the value of a HOST_WIDE_INT value (including CONST_INT) is
713 do_SUBST_INT (int *into, int newval)
718 if (oldval == newval)
722 buf = undobuf.frees, undobuf.frees = buf->next;
724 buf = XNEW (struct undo);
726 buf->kind = UNDO_INT;
728 buf->old_contents.i = oldval;
731 buf->next = undobuf.undos, undobuf.undos = buf;
734 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
736 /* Similar to SUBST, but just substitute the mode. This is used when
737 changing the mode of a pseudo-register, so that any other
738 references to the entry in the regno_reg_rtx array will change as
742 do_SUBST_MODE (rtx *into, enum machine_mode newval)
745 enum machine_mode oldval = GET_MODE (*into);
747 if (oldval == newval)
751 buf = undobuf.frees, undobuf.frees = buf->next;
753 buf = XNEW (struct undo);
755 buf->kind = UNDO_MODE;
757 buf->old_contents.m = oldval;
758 adjust_reg_mode (*into, newval);
760 buf->next = undobuf.undos, undobuf.undos = buf;
763 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE(&(INTO), (NEWVAL))
765 /* Subroutine of try_combine. Determine whether the combine replacement
766 patterns NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to
767 insn_rtx_cost that the original instruction sequence I1, I2, I3 and
768 undobuf.other_insn. Note that I1 and/or NEWI2PAT may be NULL_RTX.
769 NEWOTHERPAT and undobuf.other_insn may also both be NULL_RTX. This
770 function returns false, if the costs of all instructions can be
771 estimated, and the replacements are more expensive than the original
775 combine_validate_cost (rtx i1, rtx i2, rtx i3, rtx newpat, rtx newi2pat,
778 int i1_cost, i2_cost, i3_cost;
779 int new_i2_cost, new_i3_cost;
780 int old_cost, new_cost;
782 /* Lookup the original insn_rtx_costs. */
783 i2_cost = INSN_COST (i2);
784 i3_cost = INSN_COST (i3);
788 i1_cost = INSN_COST (i1);
789 old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0)
790 ? i1_cost + i2_cost + i3_cost : 0;
794 old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
798 /* Calculate the replacement insn_rtx_costs. */
799 new_i3_cost = insn_rtx_cost (newpat, optimize_this_for_speed_p);
802 new_i2_cost = insn_rtx_cost (newi2pat, optimize_this_for_speed_p);
803 new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
804 ? new_i2_cost + new_i3_cost : 0;
808 new_cost = new_i3_cost;
812 if (undobuf.other_insn)
814 int old_other_cost, new_other_cost;
816 old_other_cost = INSN_COST (undobuf.other_insn);
817 new_other_cost = insn_rtx_cost (newotherpat, optimize_this_for_speed_p);
818 if (old_other_cost > 0 && new_other_cost > 0)
820 old_cost += old_other_cost;
821 new_cost += new_other_cost;
827 /* Disallow this recombination if both new_cost and old_cost are
828 greater than zero, and new_cost is greater than old cost. */
830 && new_cost > old_cost)
837 "rejecting combination of insns %d, %d and %d\n",
838 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
839 fprintf (dump_file, "original costs %d + %d + %d = %d\n",
840 i1_cost, i2_cost, i3_cost, old_cost);
845 "rejecting combination of insns %d and %d\n",
846 INSN_UID (i2), INSN_UID (i3));
847 fprintf (dump_file, "original costs %d + %d = %d\n",
848 i2_cost, i3_cost, old_cost);
853 fprintf (dump_file, "replacement costs %d + %d = %d\n",
854 new_i2_cost, new_i3_cost, new_cost);
857 fprintf (dump_file, "replacement cost %d\n", new_cost);
863 /* Update the uid_insn_cost array with the replacement costs. */
864 INSN_COST (i2) = new_i2_cost;
865 INSN_COST (i3) = new_i3_cost;
873 /* Delete any insns that copy a register to itself. */
876 delete_noop_moves (void)
883 for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); insn = next)
885 next = NEXT_INSN (insn);
886 if (INSN_P (insn) && noop_move_p (insn))
889 fprintf (dump_file, "deleting noop move %d\n", INSN_UID (insn));
891 delete_insn_and_edges (insn);
898 /* Fill in log links field for all insns. */
901 create_log_links (void)
905 df_ref *def_vec, *use_vec;
907 next_use = XCNEWVEC (rtx, max_reg_num ());
909 /* Pass through each block from the end, recording the uses of each
910 register and establishing log links when def is encountered.
911 Note that we do not clear next_use array in order to save time,
912 so we have to test whether the use is in the same basic block as def.
914 There are a few cases below when we do not consider the definition or
915 usage -- these are taken from original flow.c did. Don't ask me why it is
916 done this way; I don't know and if it works, I don't want to know. */
920 FOR_BB_INSNS_REVERSE (bb, insn)
925 /* Log links are created only once. */
926 gcc_assert (!LOG_LINKS (insn));
928 for (def_vec = DF_INSN_DEFS (insn); *def_vec; def_vec++)
930 df_ref def = *def_vec;
931 int regno = DF_REF_REGNO (def);
934 if (!next_use[regno])
937 /* Do not consider if it is pre/post modification in MEM. */
938 if (DF_REF_FLAGS (def) & DF_REF_PRE_POST_MODIFY)
941 /* Do not make the log link for frame pointer. */
942 if ((regno == FRAME_POINTER_REGNUM
943 && (! reload_completed || frame_pointer_needed))
944 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
945 || (regno == HARD_FRAME_POINTER_REGNUM
946 && (! reload_completed || frame_pointer_needed))
948 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
949 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
954 use_insn = next_use[regno];
955 if (BLOCK_FOR_INSN (use_insn) == bb)
959 We don't build a LOG_LINK for hard registers contained
960 in ASM_OPERANDs. If these registers get replaced,
961 we might wind up changing the semantics of the insn,
962 even if reload can make what appear to be valid
963 assignments later. */
964 if (regno >= FIRST_PSEUDO_REGISTER
965 || asm_noperands (PATTERN (use_insn)) < 0)
967 /* Don't add duplicate links between instructions. */
969 for (links = LOG_LINKS (use_insn); links;
970 links = XEXP (links, 1))
971 if (insn == XEXP (links, 0))
975 LOG_LINKS (use_insn) =
976 alloc_INSN_LIST (insn, LOG_LINKS (use_insn));
979 next_use[regno] = NULL_RTX;
982 for (use_vec = DF_INSN_USES (insn); *use_vec; use_vec++)
984 df_ref use = *use_vec;
985 int regno = DF_REF_REGNO (use);
987 /* Do not consider the usage of the stack pointer
989 if (DF_REF_FLAGS (use) & DF_REF_CALL_STACK_USAGE)
992 next_use[regno] = insn;
1000 /* Clear LOG_LINKS fields of insns. */
1003 clear_log_links (void)
1007 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
1009 free_INSN_LIST_list (&LOG_LINKS (insn));
1015 /* Main entry point for combiner. F is the first insn of the function.
1016 NREGS is the first unused pseudo-reg number.
1018 Return nonzero if the combiner has turned an indirect jump
1019 instruction into a direct jump. */
1021 combine_instructions (rtx f, unsigned int nregs)
1027 rtx links, nextlinks;
1030 int new_direct_jump_p = 0;
1032 for (first = f; first && !INSN_P (first); )
1033 first = NEXT_INSN (first);
1037 combine_attempts = 0;
1040 combine_successes = 0;
1042 rtl_hooks = combine_rtl_hooks;
1044 VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
1046 init_recog_no_volatile ();
1048 /* Allocate array for insn info. */
1049 max_uid_known = get_max_uid ();
1050 uid_log_links = XCNEWVEC (rtx, max_uid_known + 1);
1051 uid_insn_cost = XCNEWVEC (int, max_uid_known + 1);
1053 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
1055 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1056 problems when, for example, we have j <<= 1 in a loop. */
1058 nonzero_sign_valid = 0;
1060 /* Scan all SETs and see if we can deduce anything about what
1061 bits are known to be zero for some registers and how many copies
1062 of the sign bit are known to exist for those registers.
1064 Also set any known values so that we can use it while searching
1065 for what bits are known to be set. */
1067 setup_incoming_promotions (first);
1069 create_log_links ();
1070 label_tick_ebb_start = ENTRY_BLOCK_PTR->index;
1071 FOR_EACH_BB (this_basic_block)
1073 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1076 label_tick = this_basic_block->index;
1077 if (!single_pred_p (this_basic_block)
1078 || single_pred (this_basic_block)->index != label_tick - 1)
1079 label_tick_ebb_start = label_tick;
1080 FOR_BB_INSNS (this_basic_block, insn)
1081 if (INSN_P (insn) && BLOCK_FOR_INSN (insn))
1083 subst_low_luid = DF_INSN_LUID (insn);
1086 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
1088 record_dead_and_set_regs (insn);
1091 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
1092 if (REG_NOTE_KIND (links) == REG_INC)
1093 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
1097 /* Record the current insn_rtx_cost of this instruction. */
1098 if (NONJUMP_INSN_P (insn))
1099 INSN_COST (insn) = insn_rtx_cost (PATTERN (insn),
1100 optimize_this_for_speed_p);
1102 fprintf(dump_file, "insn_cost %d: %d\n",
1103 INSN_UID (insn), INSN_COST (insn));
1107 nonzero_sign_valid = 1;
1109 /* Now scan all the insns in forward order. */
1111 label_tick_ebb_start = ENTRY_BLOCK_PTR->index;
1113 setup_incoming_promotions (first);
1115 FOR_EACH_BB (this_basic_block)
1117 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1120 label_tick = this_basic_block->index;
1121 if (!single_pred_p (this_basic_block)
1122 || single_pred (this_basic_block)->index != label_tick - 1)
1123 label_tick_ebb_start = label_tick;
1124 rtl_profile_for_bb (this_basic_block);
1125 for (insn = BB_HEAD (this_basic_block);
1126 insn != NEXT_INSN (BB_END (this_basic_block));
1127 insn = next ? next : NEXT_INSN (insn))
1132 /* See if we know about function return values before this
1133 insn based upon SUBREG flags. */
1134 check_promoted_subreg (insn, PATTERN (insn));
1136 /* See if we can find hardregs and subreg of pseudos in
1137 narrower modes. This could help turning TRUNCATEs
1139 note_uses (&PATTERN (insn), record_truncated_values, NULL);
1141 /* Try this insn with each insn it links back to. */
1143 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1144 if ((next = try_combine (insn, XEXP (links, 0),
1145 NULL_RTX, &new_direct_jump_p)) != 0)
1148 /* Try each sequence of three linked insns ending with this one. */
1150 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1152 rtx link = XEXP (links, 0);
1154 /* If the linked insn has been replaced by a note, then there
1155 is no point in pursuing this chain any further. */
1159 for (nextlinks = LOG_LINKS (link);
1161 nextlinks = XEXP (nextlinks, 1))
1162 if ((next = try_combine (insn, link,
1163 XEXP (nextlinks, 0),
1164 &new_direct_jump_p)) != 0)
1169 /* Try to combine a jump insn that uses CC0
1170 with a preceding insn that sets CC0, and maybe with its
1171 logical predecessor as well.
1172 This is how we make decrement-and-branch insns.
1173 We need this special code because data flow connections
1174 via CC0 do not get entered in LOG_LINKS. */
1177 && (prev = prev_nonnote_insn (insn)) != 0
1178 && NONJUMP_INSN_P (prev)
1179 && sets_cc0_p (PATTERN (prev)))
1181 if ((next = try_combine (insn, prev,
1182 NULL_RTX, &new_direct_jump_p)) != 0)
1185 for (nextlinks = LOG_LINKS (prev); nextlinks;
1186 nextlinks = XEXP (nextlinks, 1))
1187 if ((next = try_combine (insn, prev,
1188 XEXP (nextlinks, 0),
1189 &new_direct_jump_p)) != 0)
1193 /* Do the same for an insn that explicitly references CC0. */
1194 if (NONJUMP_INSN_P (insn)
1195 && (prev = prev_nonnote_insn (insn)) != 0
1196 && NONJUMP_INSN_P (prev)
1197 && sets_cc0_p (PATTERN (prev))
1198 && GET_CODE (PATTERN (insn)) == SET
1199 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
1201 if ((next = try_combine (insn, prev,
1202 NULL_RTX, &new_direct_jump_p)) != 0)
1205 for (nextlinks = LOG_LINKS (prev); nextlinks;
1206 nextlinks = XEXP (nextlinks, 1))
1207 if ((next = try_combine (insn, prev,
1208 XEXP (nextlinks, 0),
1209 &new_direct_jump_p)) != 0)
1213 /* Finally, see if any of the insns that this insn links to
1214 explicitly references CC0. If so, try this insn, that insn,
1215 and its predecessor if it sets CC0. */
1216 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1217 if (NONJUMP_INSN_P (XEXP (links, 0))
1218 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
1219 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
1220 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
1221 && NONJUMP_INSN_P (prev)
1222 && sets_cc0_p (PATTERN (prev))
1223 && (next = try_combine (insn, XEXP (links, 0),
1224 prev, &new_direct_jump_p)) != 0)
1228 /* Try combining an insn with two different insns whose results it
1230 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1231 for (nextlinks = XEXP (links, 1); nextlinks;
1232 nextlinks = XEXP (nextlinks, 1))
1233 if ((next = try_combine (insn, XEXP (links, 0),
1234 XEXP (nextlinks, 0),
1235 &new_direct_jump_p)) != 0)
1238 /* Try this insn with each REG_EQUAL note it links back to. */
1239 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1242 rtx temp = XEXP (links, 0);
1243 if ((set = single_set (temp)) != 0
1244 && (note = find_reg_equal_equiv_note (temp)) != 0
1245 && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
1246 /* Avoid using a register that may already been marked
1247 dead by an earlier instruction. */
1248 && ! unmentioned_reg_p (note, SET_SRC (set))
1249 && (GET_MODE (note) == VOIDmode
1250 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
1251 : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
1253 /* Temporarily replace the set's source with the
1254 contents of the REG_EQUAL note. The insn will
1255 be deleted or recognized by try_combine. */
1256 rtx orig = SET_SRC (set);
1257 SET_SRC (set) = note;
1259 i2mod_old_rhs = copy_rtx (orig);
1260 i2mod_new_rhs = copy_rtx (note);
1261 next = try_combine (insn, i2mod, NULL_RTX,
1262 &new_direct_jump_p);
1266 SET_SRC (set) = orig;
1271 record_dead_and_set_regs (insn);
1279 default_rtl_profile ();
1282 new_direct_jump_p |= purge_all_dead_edges ();
1283 delete_noop_moves ();
1286 free (uid_log_links);
1287 free (uid_insn_cost);
1288 VEC_free (reg_stat_type, heap, reg_stat);
1291 struct undo *undo, *next;
1292 for (undo = undobuf.frees; undo; undo = next)
1300 total_attempts += combine_attempts;
1301 total_merges += combine_merges;
1302 total_extras += combine_extras;
1303 total_successes += combine_successes;
1305 nonzero_sign_valid = 0;
1306 rtl_hooks = general_rtl_hooks;
1308 /* Make recognizer allow volatile MEMs again. */
1311 return new_direct_jump_p;
1314 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1317 init_reg_last (void)
1322 for (i = 0; VEC_iterate (reg_stat_type, reg_stat, i, p); ++i)
1323 memset (p, 0, offsetof (reg_stat_type, sign_bit_copies));
1326 /* Set up any promoted values for incoming argument registers. */
1329 setup_incoming_promotions (rtx first)
1332 bool strictly_local = false;
1334 if (!targetm.calls.promote_function_args (TREE_TYPE (cfun->decl)))
1337 for (arg = DECL_ARGUMENTS (current_function_decl); arg;
1338 arg = TREE_CHAIN (arg))
1340 rtx reg = DECL_INCOMING_RTL (arg);
1342 enum machine_mode mode1, mode2, mode3, mode4;
1344 /* Only continue if the incoming argument is in a register. */
1348 /* Determine, if possible, whether all call sites of the current
1349 function lie within the current compilation unit. (This does
1350 take into account the exporting of a function via taking its
1351 address, and so forth.) */
1352 strictly_local = cgraph_local_info (current_function_decl)->local;
1354 /* The mode and signedness of the argument before any promotions happen
1355 (equal to the mode of the pseudo holding it at that stage). */
1356 mode1 = TYPE_MODE (TREE_TYPE (arg));
1357 uns1 = TYPE_UNSIGNED (TREE_TYPE (arg));
1359 /* The mode and signedness of the argument after any source language and
1360 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1361 mode2 = TYPE_MODE (DECL_ARG_TYPE (arg));
1362 uns3 = TYPE_UNSIGNED (DECL_ARG_TYPE (arg));
1364 /* The mode and signedness of the argument as it is actually passed,
1365 after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions. */
1366 mode3 = promote_mode (DECL_ARG_TYPE (arg), mode2, &uns3, 1);
1368 /* The mode of the register in which the argument is being passed. */
1369 mode4 = GET_MODE (reg);
1371 /* Eliminate sign extensions in the callee when possible. Only
1373 (a) a mode promotion has occurred;
1374 (b) the mode of the register is the same as the mode of
1375 the argument as it is passed; and
1376 (c) the signedness does not change across any of the promotions; and
1377 (d) when no language-level promotions (which we cannot guarantee
1378 will have been done by an external caller) are necessary,
1379 unless we know that this function is only ever called from
1380 the current compilation unit -- all of whose call sites will
1381 do the mode1 --> mode2 promotion. */
1385 && (mode1 == mode2 || strictly_local))
1387 /* Record that the value was promoted from mode1 to mode3,
1388 so that any sign extension at the head of the current
1389 function may be eliminated. */
1391 x = gen_rtx_CLOBBER (mode1, const0_rtx);
1392 x = gen_rtx_fmt_e ((uns3 ? ZERO_EXTEND : SIGN_EXTEND), mode3, x);
1393 record_value_for_reg (reg, first, x);
1398 /* Called via note_stores. If X is a pseudo that is narrower than
1399 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1401 If we are setting only a portion of X and we can't figure out what
1402 portion, assume all bits will be used since we don't know what will
1405 Similarly, set how many bits of X are known to be copies of the sign bit
1406 at all locations in the function. This is the smallest number implied
1410 set_nonzero_bits_and_sign_copies (rtx x, const_rtx set, void *data)
1412 rtx insn = (rtx) data;
1416 && REGNO (x) >= FIRST_PSEUDO_REGISTER
1417 /* If this register is undefined at the start of the file, we can't
1418 say what its contents were. */
1419 && ! REGNO_REG_SET_P
1420 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x))
1421 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
1423 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
1425 if (set == 0 || GET_CODE (set) == CLOBBER)
1427 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1428 rsp->sign_bit_copies = 1;
1432 /* If this register is being initialized using itself, and the
1433 register is uninitialized in this basic block, and there are
1434 no LOG_LINKS which set the register, then part of the
1435 register is uninitialized. In that case we can't assume
1436 anything about the number of nonzero bits.
1438 ??? We could do better if we checked this in
1439 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1440 could avoid making assumptions about the insn which initially
1441 sets the register, while still using the information in other
1442 insns. We would have to be careful to check every insn
1443 involved in the combination. */
1446 && reg_referenced_p (x, PATTERN (insn))
1447 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn)),
1452 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
1454 if (dead_or_set_p (XEXP (link, 0), x))
1459 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1460 rsp->sign_bit_copies = 1;
1465 /* If this is a complex assignment, see if we can convert it into a
1466 simple assignment. */
1467 set = expand_field_assignment (set);
1469 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1470 set what we know about X. */
1472 if (SET_DEST (set) == x
1473 || (GET_CODE (SET_DEST (set)) == SUBREG
1474 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
1475 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
1476 && SUBREG_REG (SET_DEST (set)) == x))
1478 rtx src = SET_SRC (set);
1480 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1481 /* If X is narrower than a word and SRC is a non-negative
1482 constant that would appear negative in the mode of X,
1483 sign-extend it for use in reg_stat[].nonzero_bits because some
1484 machines (maybe most) will actually do the sign-extension
1485 and this is the conservative approach.
1487 ??? For 2.5, try to tighten up the MD files in this regard
1488 instead of this kludge. */
1490 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
1491 && GET_CODE (src) == CONST_INT
1493 && 0 != (INTVAL (src)
1494 & ((HOST_WIDE_INT) 1
1495 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
1496 src = GEN_INT (INTVAL (src)
1497 | ((HOST_WIDE_INT) (-1)
1498 << GET_MODE_BITSIZE (GET_MODE (x))));
1501 /* Don't call nonzero_bits if it cannot change anything. */
1502 if (rsp->nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1503 rsp->nonzero_bits |= nonzero_bits (src, nonzero_bits_mode);
1504 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1505 if (rsp->sign_bit_copies == 0
1506 || rsp->sign_bit_copies > num)
1507 rsp->sign_bit_copies = num;
1511 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1512 rsp->sign_bit_copies = 1;
1517 /* See if INSN can be combined into I3. PRED and SUCC are optionally
1518 insns that were previously combined into I3 or that will be combined
1519 into the merger of INSN and I3.
1521 Return 0 if the combination is not allowed for any reason.
1523 If the combination is allowed, *PDEST will be set to the single
1524 destination of INSN and *PSRC to the single source, and this function
1528 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED, rtx succ,
1529 rtx *pdest, rtx *psrc)
1538 int all_adjacent = (succ ? (next_active_insn (insn) == succ
1539 && next_active_insn (succ) == i3)
1540 : next_active_insn (insn) == i3);
1542 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1543 or a PARALLEL consisting of such a SET and CLOBBERs.
1545 If INSN has CLOBBER parallel parts, ignore them for our processing.
1546 By definition, these happen during the execution of the insn. When it
1547 is merged with another insn, all bets are off. If they are, in fact,
1548 needed and aren't also supplied in I3, they may be added by
1549 recog_for_combine. Otherwise, it won't match.
1551 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1554 Get the source and destination of INSN. If more than one, can't
1557 if (GET_CODE (PATTERN (insn)) == SET)
1558 set = PATTERN (insn);
1559 else if (GET_CODE (PATTERN (insn)) == PARALLEL
1560 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1562 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1564 rtx elt = XVECEXP (PATTERN (insn), 0, i);
1567 switch (GET_CODE (elt))
1569 /* This is important to combine floating point insns
1570 for the SH4 port. */
1572 /* Combining an isolated USE doesn't make sense.
1573 We depend here on combinable_i3pat to reject them. */
1574 /* The code below this loop only verifies that the inputs of
1575 the SET in INSN do not change. We call reg_set_between_p
1576 to verify that the REG in the USE does not change between
1578 If the USE in INSN was for a pseudo register, the matching
1579 insn pattern will likely match any register; combining this
1580 with any other USE would only be safe if we knew that the
1581 used registers have identical values, or if there was
1582 something to tell them apart, e.g. different modes. For
1583 now, we forgo such complicated tests and simply disallow
1584 combining of USES of pseudo registers with any other USE. */
1585 if (REG_P (XEXP (elt, 0))
1586 && GET_CODE (PATTERN (i3)) == PARALLEL)
1588 rtx i3pat = PATTERN (i3);
1589 int i = XVECLEN (i3pat, 0) - 1;
1590 unsigned int regno = REGNO (XEXP (elt, 0));
1594 rtx i3elt = XVECEXP (i3pat, 0, i);
1596 if (GET_CODE (i3elt) == USE
1597 && REG_P (XEXP (i3elt, 0))
1598 && (REGNO (XEXP (i3elt, 0)) == regno
1599 ? reg_set_between_p (XEXP (elt, 0),
1600 PREV_INSN (insn), i3)
1601 : regno >= FIRST_PSEUDO_REGISTER))
1608 /* We can ignore CLOBBERs. */
1613 /* Ignore SETs whose result isn't used but not those that
1614 have side-effects. */
1615 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1616 && (!(note = find_reg_note (insn, REG_EH_REGION, NULL_RTX))
1617 || INTVAL (XEXP (note, 0)) <= 0)
1618 && ! side_effects_p (elt))
1621 /* If we have already found a SET, this is a second one and
1622 so we cannot combine with this insn. */
1630 /* Anything else means we can't combine. */
1636 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1637 so don't do anything with it. */
1638 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1647 set = expand_field_assignment (set);
1648 src = SET_SRC (set), dest = SET_DEST (set);
1650 /* Don't eliminate a store in the stack pointer. */
1651 if (dest == stack_pointer_rtx
1652 /* Don't combine with an insn that sets a register to itself if it has
1653 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1654 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1655 /* Can't merge an ASM_OPERANDS. */
1656 || GET_CODE (src) == ASM_OPERANDS
1657 /* Can't merge a function call. */
1658 || GET_CODE (src) == CALL
1659 /* Don't eliminate a function call argument. */
1661 && (find_reg_fusage (i3, USE, dest)
1663 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1664 && global_regs[REGNO (dest)])))
1665 /* Don't substitute into an incremented register. */
1666 || FIND_REG_INC_NOTE (i3, dest)
1667 || (succ && FIND_REG_INC_NOTE (succ, dest))
1668 /* Don't substitute into a non-local goto, this confuses CFG. */
1669 || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1670 /* Make sure that DEST is not used after SUCC but before I3. */
1671 || (succ && ! all_adjacent
1672 && reg_used_between_p (dest, succ, i3))
1673 /* Make sure that the value that is to be substituted for the register
1674 does not use any registers whose values alter in between. However,
1675 If the insns are adjacent, a use can't cross a set even though we
1676 think it might (this can happen for a sequence of insns each setting
1677 the same destination; last_set of that register might point to
1678 a NOTE). If INSN has a REG_EQUIV note, the register is always
1679 equivalent to the memory so the substitution is valid even if there
1680 are intervening stores. Also, don't move a volatile asm or
1681 UNSPEC_VOLATILE across any other insns. */
1684 || ! find_reg_note (insn, REG_EQUIV, src))
1685 && use_crosses_set_p (src, DF_INSN_LUID (insn)))
1686 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1687 || GET_CODE (src) == UNSPEC_VOLATILE))
1688 /* Don't combine across a CALL_INSN, because that would possibly
1689 change whether the life span of some REGs crosses calls or not,
1690 and it is a pain to update that information.
1691 Exception: if source is a constant, moving it later can't hurt.
1692 Accept that as a special case. */
1693 || (DF_INSN_LUID (insn) < last_call_luid && ! CONSTANT_P (src)))
1696 /* DEST must either be a REG or CC0. */
1699 /* If register alignment is being enforced for multi-word items in all
1700 cases except for parameters, it is possible to have a register copy
1701 insn referencing a hard register that is not allowed to contain the
1702 mode being copied and which would not be valid as an operand of most
1703 insns. Eliminate this problem by not combining with such an insn.
1705 Also, on some machines we don't want to extend the life of a hard
1709 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1710 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1711 /* Don't extend the life of a hard register unless it is
1712 user variable (if we have few registers) or it can't
1713 fit into the desired register (meaning something special
1715 Also avoid substituting a return register into I3, because
1716 reload can't handle a conflict with constraints of other
1718 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1719 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1722 else if (GET_CODE (dest) != CC0)
1726 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1727 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1728 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1730 /* Don't substitute for a register intended as a clobberable
1732 rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1733 if (rtx_equal_p (reg, dest))
1736 /* If the clobber represents an earlyclobber operand, we must not
1737 substitute an expression containing the clobbered register.
1738 As we do not analyze the constraint strings here, we have to
1739 make the conservative assumption. However, if the register is
1740 a fixed hard reg, the clobber cannot represent any operand;
1741 we leave it up to the machine description to either accept or
1742 reject use-and-clobber patterns. */
1744 || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1745 || !fixed_regs[REGNO (reg)])
1746 if (reg_overlap_mentioned_p (reg, src))
1750 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1751 or not), reject, unless nothing volatile comes between it and I3 */
1753 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1755 /* Make sure succ doesn't contain a volatile reference. */
1756 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1759 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1760 if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1764 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1765 to be an explicit register variable, and was chosen for a reason. */
1767 if (GET_CODE (src) == ASM_OPERANDS
1768 && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1771 /* If there are any volatile insns between INSN and I3, reject, because
1772 they might affect machine state. */
1774 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1775 if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1778 /* If INSN contains an autoincrement or autodecrement, make sure that
1779 register is not used between there and I3, and not already used in
1780 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1781 Also insist that I3 not be a jump; if it were one
1782 and the incremented register were spilled, we would lose. */
1785 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1786 if (REG_NOTE_KIND (link) == REG_INC
1788 || reg_used_between_p (XEXP (link, 0), insn, i3)
1789 || (pred != NULL_RTX
1790 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
1791 || (succ != NULL_RTX
1792 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
1793 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1798 /* Don't combine an insn that follows a CC0-setting insn.
1799 An insn that uses CC0 must not be separated from the one that sets it.
1800 We do, however, allow I2 to follow a CC0-setting insn if that insn
1801 is passed as I1; in that case it will be deleted also.
1802 We also allow combining in this case if all the insns are adjacent
1803 because that would leave the two CC0 insns adjacent as well.
1804 It would be more logical to test whether CC0 occurs inside I1 or I2,
1805 but that would be much slower, and this ought to be equivalent. */
1807 p = prev_nonnote_insn (insn);
1808 if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
1813 /* If we get here, we have passed all the tests and the combination is
1822 /* LOC is the location within I3 that contains its pattern or the component
1823 of a PARALLEL of the pattern. We validate that it is valid for combining.
1825 One problem is if I3 modifies its output, as opposed to replacing it
1826 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1827 so would produce an insn that is not equivalent to the original insns.
1831 (set (reg:DI 101) (reg:DI 100))
1832 (set (subreg:SI (reg:DI 101) 0) <foo>)
1834 This is NOT equivalent to:
1836 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1837 (set (reg:DI 101) (reg:DI 100))])
1839 Not only does this modify 100 (in which case it might still be valid
1840 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1842 We can also run into a problem if I2 sets a register that I1
1843 uses and I1 gets directly substituted into I3 (not via I2). In that
1844 case, we would be getting the wrong value of I2DEST into I3, so we
1845 must reject the combination. This case occurs when I2 and I1 both
1846 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1847 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1848 of a SET must prevent combination from occurring.
1850 Before doing the above check, we first try to expand a field assignment
1851 into a set of logical operations.
1853 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1854 we place a register that is both set and used within I3. If more than one
1855 such register is detected, we fail.
1857 Return 1 if the combination is valid, zero otherwise. */
1860 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest,
1861 int i1_not_in_src, rtx *pi3dest_killed)
1865 if (GET_CODE (x) == SET)
1868 rtx dest = SET_DEST (set);
1869 rtx src = SET_SRC (set);
1870 rtx inner_dest = dest;
1873 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1874 || GET_CODE (inner_dest) == SUBREG
1875 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1876 inner_dest = XEXP (inner_dest, 0);
1878 /* Check for the case where I3 modifies its output, as discussed
1879 above. We don't want to prevent pseudos from being combined
1880 into the address of a MEM, so only prevent the combination if
1881 i1 or i2 set the same MEM. */
1882 if ((inner_dest != dest &&
1883 (!MEM_P (inner_dest)
1884 || rtx_equal_p (i2dest, inner_dest)
1885 || (i1dest && rtx_equal_p (i1dest, inner_dest)))
1886 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1887 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1889 /* This is the same test done in can_combine_p except we can't test
1890 all_adjacent; we don't have to, since this instruction will stay
1891 in place, thus we are not considering increasing the lifetime of
1894 Also, if this insn sets a function argument, combining it with
1895 something that might need a spill could clobber a previous
1896 function argument; the all_adjacent test in can_combine_p also
1897 checks this; here, we do a more specific test for this case. */
1899 || (REG_P (inner_dest)
1900 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1901 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1902 GET_MODE (inner_dest))))
1903 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1906 /* If DEST is used in I3, it is being killed in this insn, so
1907 record that for later. We have to consider paradoxical
1908 subregs here, since they kill the whole register, but we
1909 ignore partial subregs, STRICT_LOW_PART, etc.
1910 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1911 STACK_POINTER_REGNUM, since these are always considered to be
1912 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1914 if (GET_CODE (subdest) == SUBREG
1915 && (GET_MODE_SIZE (GET_MODE (subdest))
1916 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
1917 subdest = SUBREG_REG (subdest);
1920 && reg_referenced_p (subdest, PATTERN (i3))
1921 && REGNO (subdest) != FRAME_POINTER_REGNUM
1922 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1923 && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
1925 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1926 && (REGNO (subdest) != ARG_POINTER_REGNUM
1927 || ! fixed_regs [REGNO (subdest)])
1929 && REGNO (subdest) != STACK_POINTER_REGNUM)
1931 if (*pi3dest_killed)
1934 *pi3dest_killed = subdest;
1938 else if (GET_CODE (x) == PARALLEL)
1942 for (i = 0; i < XVECLEN (x, 0); i++)
1943 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1944 i1_not_in_src, pi3dest_killed))
1951 /* Return 1 if X is an arithmetic expression that contains a multiplication
1952 and division. We don't count multiplications by powers of two here. */
1955 contains_muldiv (rtx x)
1957 switch (GET_CODE (x))
1959 case MOD: case DIV: case UMOD: case UDIV:
1963 return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1964 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1967 return contains_muldiv (XEXP (x, 0))
1968 || contains_muldiv (XEXP (x, 1));
1971 return contains_muldiv (XEXP (x, 0));
1977 /* Determine whether INSN can be used in a combination. Return nonzero if
1978 not. This is used in try_combine to detect early some cases where we
1979 can't perform combinations. */
1982 cant_combine_insn_p (rtx insn)
1987 /* If this isn't really an insn, we can't do anything.
1988 This can occur when flow deletes an insn that it has merged into an
1989 auto-increment address. */
1990 if (! INSN_P (insn))
1993 /* Never combine loads and stores involving hard regs that are likely
1994 to be spilled. The register allocator can usually handle such
1995 reg-reg moves by tying. If we allow the combiner to make
1996 substitutions of likely-spilled regs, reload might die.
1997 As an exception, we allow combinations involving fixed regs; these are
1998 not available to the register allocator so there's no risk involved. */
2000 set = single_set (insn);
2003 src = SET_SRC (set);
2004 dest = SET_DEST (set);
2005 if (GET_CODE (src) == SUBREG)
2006 src = SUBREG_REG (src);
2007 if (GET_CODE (dest) == SUBREG)
2008 dest = SUBREG_REG (dest);
2009 if (REG_P (src) && REG_P (dest)
2010 && ((REGNO (src) < FIRST_PSEUDO_REGISTER
2011 && ! fixed_regs[REGNO (src)]
2012 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src))))
2013 || (REGNO (dest) < FIRST_PSEUDO_REGISTER
2014 && ! fixed_regs[REGNO (dest)]
2015 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest))))))
2021 struct likely_spilled_retval_info
2023 unsigned regno, nregs;
2027 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2028 hard registers that are known to be written to / clobbered in full. */
2030 likely_spilled_retval_1 (rtx x, const_rtx set, void *data)
2032 struct likely_spilled_retval_info *const info =
2033 (struct likely_spilled_retval_info *) data;
2034 unsigned regno, nregs;
2037 if (!REG_P (XEXP (set, 0)))
2040 if (regno >= info->regno + info->nregs)
2042 nregs = hard_regno_nregs[regno][GET_MODE (x)];
2043 if (regno + nregs <= info->regno)
2045 new_mask = (2U << (nregs - 1)) - 1;
2046 if (regno < info->regno)
2047 new_mask >>= info->regno - regno;
2049 new_mask <<= regno - info->regno;
2050 info->mask &= ~new_mask;
2053 /* Return nonzero iff part of the return value is live during INSN, and
2054 it is likely spilled. This can happen when more than one insn is needed
2055 to copy the return value, e.g. when we consider to combine into the
2056 second copy insn for a complex value. */
2059 likely_spilled_retval_p (rtx insn)
2061 rtx use = BB_END (this_basic_block);
2063 unsigned regno, nregs;
2064 /* We assume here that no machine mode needs more than
2065 32 hard registers when the value overlaps with a register
2066 for which FUNCTION_VALUE_REGNO_P is true. */
2068 struct likely_spilled_retval_info info;
2070 if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
2072 reg = XEXP (PATTERN (use), 0);
2073 if (!REG_P (reg) || !FUNCTION_VALUE_REGNO_P (REGNO (reg)))
2075 regno = REGNO (reg);
2076 nregs = hard_regno_nregs[regno][GET_MODE (reg)];
2079 mask = (2U << (nregs - 1)) - 1;
2081 /* Disregard parts of the return value that are set later. */
2085 for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
2087 note_stores (PATTERN (p), likely_spilled_retval_1, &info);
2090 /* Check if any of the (probably) live return value registers is
2095 if ((mask & 1 << nregs)
2096 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (regno + nregs)))
2102 /* Adjust INSN after we made a change to its destination.
2104 Changing the destination can invalidate notes that say something about
2105 the results of the insn and a LOG_LINK pointing to the insn. */
2108 adjust_for_new_dest (rtx insn)
2110 /* For notes, be conservative and simply remove them. */
2111 remove_reg_equal_equiv_notes (insn);
2113 /* The new insn will have a destination that was previously the destination
2114 of an insn just above it. Call distribute_links to make a LOG_LINK from
2115 the next use of that destination. */
2116 distribute_links (gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX));
2118 df_insn_rescan (insn);
2121 /* Return TRUE if combine can reuse reg X in mode MODE.
2122 ADDED_SETS is nonzero if the original set is still required. */
2124 can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode)
2132 /* Allow hard registers if the new mode is legal, and occupies no more
2133 registers than the old mode. */
2134 if (regno < FIRST_PSEUDO_REGISTER)
2135 return (HARD_REGNO_MODE_OK (regno, mode)
2136 && (hard_regno_nregs[regno][GET_MODE (x)]
2137 >= hard_regno_nregs[regno][mode]));
2139 /* Or a pseudo that is only used once. */
2140 return (REG_N_SETS (regno) == 1 && !added_sets
2141 && !REG_USERVAR_P (x));
2145 /* Check whether X, the destination of a set, refers to part of
2146 the register specified by REG. */
2149 reg_subword_p (rtx x, rtx reg)
2151 /* Check that reg is an integer mode register. */
2152 if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
2155 if (GET_CODE (x) == STRICT_LOW_PART
2156 || GET_CODE (x) == ZERO_EXTRACT)
2159 return GET_CODE (x) == SUBREG
2160 && SUBREG_REG (x) == reg
2161 && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
2165 /* Delete the conditional jump INSN and adjust the CFG correspondingly.
2166 Note that the INSN should be deleted *after* removing dead edges, so
2167 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2168 but not for a (set (pc) (label_ref FOO)). */
2171 update_cfg_for_uncondjump (rtx insn)
2173 basic_block bb = BLOCK_FOR_INSN (insn);
2175 if (BB_END (bb) == insn)
2176 purge_dead_edges (bb);
2179 if (EDGE_COUNT (bb->succs) == 1)
2180 single_succ_edge (bb)->flags |= EDGE_FALLTHRU;
2184 /* Try to combine the insns I1 and I2 into I3.
2185 Here I1 and I2 appear earlier than I3.
2186 I1 can be zero; then we combine just I2 into I3.
2188 If we are combining three insns and the resulting insn is not recognized,
2189 try splitting it into two insns. If that happens, I2 and I3 are retained
2190 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
2193 Return 0 if the combination does not work. Then nothing is changed.
2194 If we did the combination, return the insn at which combine should
2197 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2198 new direct jump instruction. */
2201 try_combine (rtx i3, rtx i2, rtx i1, int *new_direct_jump_p)
2203 /* New patterns for I3 and I2, respectively. */
2204 rtx newpat, newi2pat = 0;
2205 rtvec newpat_vec_with_clobbers = 0;
2206 int substed_i2 = 0, substed_i1 = 0;
2207 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
2208 int added_sets_1, added_sets_2;
2209 /* Total number of SETs to put into I3. */
2211 /* Nonzero if I2's body now appears in I3. */
2213 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2214 int insn_code_number, i2_code_number = 0, other_code_number = 0;
2215 /* Contains I3 if the destination of I3 is used in its source, which means
2216 that the old life of I3 is being killed. If that usage is placed into
2217 I2 and not in I3, a REG_DEAD note must be made. */
2218 rtx i3dest_killed = 0;
2219 /* SET_DEST and SET_SRC of I2 and I1. */
2220 rtx i2dest, i2src, i1dest = 0, i1src = 0;
2221 /* PATTERN (I1) and PATTERN (I2), or a copy of it in certain cases. */
2222 rtx i1pat = 0, i2pat = 0;
2223 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2224 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
2225 int i2dest_killed = 0, i1dest_killed = 0;
2226 int i1_feeds_i3 = 0;
2227 /* Notes that must be added to REG_NOTES in I3 and I2. */
2228 rtx new_i3_notes, new_i2_notes;
2229 /* Notes that we substituted I3 into I2 instead of the normal case. */
2230 int i3_subst_into_i2 = 0;
2231 /* Notes that I1, I2 or I3 is a MULT operation. */
2234 int changed_i3_dest = 0;
2240 rtx new_other_notes;
2243 /* Exit early if one of the insns involved can't be used for
2245 if (cant_combine_insn_p (i3)
2246 || cant_combine_insn_p (i2)
2247 || (i1 && cant_combine_insn_p (i1))
2248 || likely_spilled_retval_p (i3))
2252 undobuf.other_insn = 0;
2254 /* Reset the hard register usage information. */
2255 CLEAR_HARD_REG_SET (newpat_used_regs);
2257 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
2258 code below, set I1 to be the earlier of the two insns. */
2259 if (i1 && DF_INSN_LUID (i1) > DF_INSN_LUID (i2))
2260 temp = i1, i1 = i2, i2 = temp;
2262 added_links_insn = 0;
2264 /* First check for one important special-case that the code below will
2265 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2266 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2267 we may be able to replace that destination with the destination of I3.
2268 This occurs in the common code where we compute both a quotient and
2269 remainder into a structure, in which case we want to do the computation
2270 directly into the structure to avoid register-register copies.
2272 Note that this case handles both multiple sets in I2 and also
2273 cases where I2 has a number of CLOBBER or PARALLELs.
2275 We make very conservative checks below and only try to handle the
2276 most common cases of this. For example, we only handle the case
2277 where I2 and I3 are adjacent to avoid making difficult register
2280 if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
2281 && REG_P (SET_SRC (PATTERN (i3)))
2282 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
2283 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
2284 && GET_CODE (PATTERN (i2)) == PARALLEL
2285 && ! side_effects_p (SET_DEST (PATTERN (i3)))
2286 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2287 below would need to check what is inside (and reg_overlap_mentioned_p
2288 doesn't support those codes anyway). Don't allow those destinations;
2289 the resulting insn isn't likely to be recognized anyway. */
2290 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
2291 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
2292 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
2293 SET_DEST (PATTERN (i3)))
2294 && next_real_insn (i2) == i3)
2296 rtx p2 = PATTERN (i2);
2298 /* Make sure that the destination of I3,
2299 which we are going to substitute into one output of I2,
2300 is not used within another output of I2. We must avoid making this:
2301 (parallel [(set (mem (reg 69)) ...)
2302 (set (reg 69) ...)])
2303 which is not well-defined as to order of actions.
2304 (Besides, reload can't handle output reloads for this.)
2306 The problem can also happen if the dest of I3 is a memory ref,
2307 if another dest in I2 is an indirect memory ref. */
2308 for (i = 0; i < XVECLEN (p2, 0); i++)
2309 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2310 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2311 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
2312 SET_DEST (XVECEXP (p2, 0, i))))
2315 if (i == XVECLEN (p2, 0))
2316 for (i = 0; i < XVECLEN (p2, 0); i++)
2317 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2318 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2319 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
2324 subst_low_luid = DF_INSN_LUID (i2);
2326 added_sets_2 = added_sets_1 = 0;
2327 i2dest = SET_SRC (PATTERN (i3));
2328 i2dest_killed = dead_or_set_p (i2, i2dest);
2330 /* Replace the dest in I2 with our dest and make the resulting
2331 insn the new pattern for I3. Then skip to where we
2332 validate the pattern. Everything was set up above. */
2333 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
2334 SET_DEST (PATTERN (i3)));
2337 i3_subst_into_i2 = 1;
2338 goto validate_replacement;
2342 /* If I2 is setting a pseudo to a constant and I3 is setting some
2343 sub-part of it to another constant, merge them by making a new
2346 && (temp = single_set (i2)) != 0
2347 && (GET_CODE (SET_SRC (temp)) == CONST_INT
2348 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
2349 && GET_CODE (PATTERN (i3)) == SET
2350 && (GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT
2351 || GET_CODE (SET_SRC (PATTERN (i3))) == CONST_DOUBLE)
2352 && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp)))
2354 rtx dest = SET_DEST (PATTERN (i3));
2358 if (GET_CODE (dest) == ZERO_EXTRACT)
2360 if (GET_CODE (XEXP (dest, 1)) == CONST_INT
2361 && GET_CODE (XEXP (dest, 2)) == CONST_INT)
2363 width = INTVAL (XEXP (dest, 1));
2364 offset = INTVAL (XEXP (dest, 2));
2365 dest = XEXP (dest, 0);
2366 if (BITS_BIG_ENDIAN)
2367 offset = GET_MODE_BITSIZE (GET_MODE (dest)) - width - offset;
2372 if (GET_CODE (dest) == STRICT_LOW_PART)
2373 dest = XEXP (dest, 0);
2374 width = GET_MODE_BITSIZE (GET_MODE (dest));
2380 /* If this is the low part, we're done. */
2381 if (subreg_lowpart_p (dest))
2383 /* Handle the case where inner is twice the size of outer. */
2384 else if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
2385 == 2 * GET_MODE_BITSIZE (GET_MODE (dest)))
2386 offset += GET_MODE_BITSIZE (GET_MODE (dest));
2387 /* Otherwise give up for now. */
2393 && (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
2394 <= HOST_BITS_PER_WIDE_INT * 2))
2396 HOST_WIDE_INT mhi, ohi, ihi;
2397 HOST_WIDE_INT mlo, olo, ilo;
2398 rtx inner = SET_SRC (PATTERN (i3));
2399 rtx outer = SET_SRC (temp);
2401 if (GET_CODE (outer) == CONST_INT)
2403 olo = INTVAL (outer);
2404 ohi = olo < 0 ? -1 : 0;
2408 olo = CONST_DOUBLE_LOW (outer);
2409 ohi = CONST_DOUBLE_HIGH (outer);
2412 if (GET_CODE (inner) == CONST_INT)
2414 ilo = INTVAL (inner);
2415 ihi = ilo < 0 ? -1 : 0;
2419 ilo = CONST_DOUBLE_LOW (inner);
2420 ihi = CONST_DOUBLE_HIGH (inner);
2423 if (width < HOST_BITS_PER_WIDE_INT)
2425 mlo = ((unsigned HOST_WIDE_INT) 1 << width) - 1;
2428 else if (width < HOST_BITS_PER_WIDE_INT * 2)
2430 mhi = ((unsigned HOST_WIDE_INT) 1
2431 << (width - HOST_BITS_PER_WIDE_INT)) - 1;
2443 if (offset >= HOST_BITS_PER_WIDE_INT)
2445 mhi = mlo << (offset - HOST_BITS_PER_WIDE_INT);
2447 ihi = ilo << (offset - HOST_BITS_PER_WIDE_INT);
2450 else if (offset > 0)
2452 mhi = (mhi << offset) | ((unsigned HOST_WIDE_INT) mlo
2453 >> (HOST_BITS_PER_WIDE_INT - offset));
2454 mlo = mlo << offset;
2455 ihi = (ihi << offset) | ((unsigned HOST_WIDE_INT) ilo
2456 >> (HOST_BITS_PER_WIDE_INT - offset));
2457 ilo = ilo << offset;
2460 olo = (olo & ~mlo) | ilo;
2461 ohi = (ohi & ~mhi) | ihi;
2465 subst_low_luid = DF_INSN_LUID (i2);
2466 added_sets_2 = added_sets_1 = 0;
2467 i2dest = SET_DEST (temp);
2468 i2dest_killed = dead_or_set_p (i2, i2dest);
2470 SUBST (SET_SRC (temp),
2471 immed_double_const (olo, ohi, GET_MODE (SET_DEST (temp))));
2473 newpat = PATTERN (i2);
2474 goto validate_replacement;
2479 /* If we have no I1 and I2 looks like:
2480 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2482 make up a dummy I1 that is
2485 (set (reg:CC X) (compare:CC Y (const_int 0)))
2487 (We can ignore any trailing CLOBBERs.)
2489 This undoes a previous combination and allows us to match a branch-and-
2492 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
2493 && XVECLEN (PATTERN (i2), 0) >= 2
2494 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
2495 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2497 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2498 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2499 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
2500 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
2501 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2502 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
2504 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
2505 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
2510 /* We make I1 with the same INSN_UID as I2. This gives it
2511 the same DF_INSN_LUID for value tracking. Our fake I1 will
2512 never appear in the insn stream so giving it the same INSN_UID
2513 as I2 will not cause a problem. */
2515 i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
2516 BLOCK_FOR_INSN (i2), INSN_LOCATOR (i2),
2517 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX);
2519 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2520 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2521 SET_DEST (PATTERN (i1)));
2526 /* Verify that I2 and I1 are valid for combining. */
2527 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
2528 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
2534 /* Record whether I2DEST is used in I2SRC and similarly for the other
2535 cases. Knowing this will help in register status updating below. */
2536 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2537 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2538 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2539 i2dest_killed = dead_or_set_p (i2, i2dest);
2540 i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2542 /* See if I1 directly feeds into I3. It does if I1DEST is not used
2544 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
2546 /* Ensure that I3's pattern can be the destination of combines. */
2547 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
2548 i1 && i2dest_in_i1src && i1_feeds_i3,
2555 /* See if any of the insns is a MULT operation. Unless one is, we will
2556 reject a combination that is, since it must be slower. Be conservative
2558 if (GET_CODE (i2src) == MULT
2559 || (i1 != 0 && GET_CODE (i1src) == MULT)
2560 || (GET_CODE (PATTERN (i3)) == SET
2561 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
2564 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2565 We used to do this EXCEPT in one case: I3 has a post-inc in an
2566 output operand. However, that exception can give rise to insns like
2568 which is a famous insn on the PDP-11 where the value of r3 used as the
2569 source was model-dependent. Avoid this sort of thing. */
2572 if (!(GET_CODE (PATTERN (i3)) == SET
2573 && REG_P (SET_SRC (PATTERN (i3)))
2574 && MEM_P (SET_DEST (PATTERN (i3)))
2575 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
2576 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
2577 /* It's not the exception. */
2580 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
2581 if (REG_NOTE_KIND (link) == REG_INC
2582 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
2584 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
2591 /* See if the SETs in I1 or I2 need to be kept around in the merged
2592 instruction: whenever the value set there is still needed past I3.
2593 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2595 For the SET in I1, we have two cases: If I1 and I2 independently
2596 feed into I3, the set in I1 needs to be kept around if I1DEST dies
2597 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2598 in I1 needs to be kept around unless I1DEST dies or is set in either
2599 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
2600 I1DEST. If so, we know I1 feeds into I2. */
2602 added_sets_2 = ! dead_or_set_p (i3, i2dest);
2605 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
2606 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
2608 /* If the set in I2 needs to be kept around, we must make a copy of
2609 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2610 PATTERN (I2), we are only substituting for the original I1DEST, not into
2611 an already-substituted copy. This also prevents making self-referential
2612 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2617 if (GET_CODE (PATTERN (i2)) == PARALLEL)
2618 i2pat = gen_rtx_SET (VOIDmode, i2dest, copy_rtx (i2src));
2620 i2pat = copy_rtx (PATTERN (i2));
2625 if (GET_CODE (PATTERN (i1)) == PARALLEL)
2626 i1pat = gen_rtx_SET (VOIDmode, i1dest, copy_rtx (i1src));
2628 i1pat = copy_rtx (PATTERN (i1));
2633 /* Substitute in the latest insn for the regs set by the earlier ones. */
2635 maxreg = max_reg_num ();
2640 /* Many machines that don't use CC0 have insns that can both perform an
2641 arithmetic operation and set the condition code. These operations will
2642 be represented as a PARALLEL with the first element of the vector
2643 being a COMPARE of an arithmetic operation with the constant zero.
2644 The second element of the vector will set some pseudo to the result
2645 of the same arithmetic operation. If we simplify the COMPARE, we won't
2646 match such a pattern and so will generate an extra insn. Here we test
2647 for this case, where both the comparison and the operation result are
2648 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2649 I2SRC. Later we will make the PARALLEL that contains I2. */
2651 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
2652 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
2653 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
2654 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
2656 #ifdef SELECT_CC_MODE
2658 enum machine_mode compare_mode;
2661 newpat = PATTERN (i3);
2662 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
2666 #ifdef SELECT_CC_MODE
2667 /* See if a COMPARE with the operand we substituted in should be done
2668 with the mode that is currently being used. If not, do the same
2669 processing we do in `subst' for a SET; namely, if the destination
2670 is used only once, try to replace it with a register of the proper
2671 mode and also replace the COMPARE. */
2672 if (undobuf.other_insn == 0
2673 && (cc_use = find_single_use (SET_DEST (newpat), i3,
2674 &undobuf.other_insn))
2675 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
2677 != GET_MODE (SET_DEST (newpat))))
2679 if (can_change_dest_mode(SET_DEST (newpat), added_sets_2,
2682 unsigned int regno = REGNO (SET_DEST (newpat));
2685 if (regno < FIRST_PSEUDO_REGISTER)
2686 new_dest = gen_rtx_REG (compare_mode, regno);
2689 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
2690 new_dest = regno_reg_rtx[regno];
2693 SUBST (SET_DEST (newpat), new_dest);
2694 SUBST (XEXP (*cc_use, 0), new_dest);
2695 SUBST (SET_SRC (newpat),
2696 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
2699 undobuf.other_insn = 0;
2706 /* It is possible that the source of I2 or I1 may be performing
2707 an unneeded operation, such as a ZERO_EXTEND of something
2708 that is known to have the high part zero. Handle that case
2709 by letting subst look at the innermost one of them.
2711 Another way to do this would be to have a function that tries
2712 to simplify a single insn instead of merging two or more
2713 insns. We don't do this because of the potential of infinite
2714 loops and because of the potential extra memory required.
2715 However, doing it the way we are is a bit of a kludge and
2716 doesn't catch all cases.
2718 But only do this if -fexpensive-optimizations since it slows
2719 things down and doesn't usually win.
2721 This is not done in the COMPARE case above because the
2722 unmodified I2PAT is used in the PARALLEL and so a pattern
2723 with a modified I2SRC would not match. */
2725 if (flag_expensive_optimizations)
2727 /* Pass pc_rtx so no substitutions are done, just
2731 subst_low_luid = DF_INSN_LUID (i1);
2732 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
2736 subst_low_luid = DF_INSN_LUID (i2);
2737 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
2741 n_occurrences = 0; /* `subst' counts here */
2743 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
2744 need to make a unique copy of I2SRC each time we substitute it
2745 to avoid self-referential rtl. */
2747 subst_low_luid = DF_INSN_LUID (i2);
2748 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
2749 ! i1_feeds_i3 && i1dest_in_i1src);
2752 /* Record whether i2's body now appears within i3's body. */
2753 i2_is_used = n_occurrences;
2756 /* If we already got a failure, don't try to do more. Otherwise,
2757 try to substitute in I1 if we have it. */
2759 if (i1 && GET_CODE (newpat) != CLOBBER)
2761 /* Check that an autoincrement side-effect on I1 has not been lost.
2762 This happens if I1DEST is mentioned in I2 and dies there, and
2763 has disappeared from the new pattern. */
2764 if ((FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2766 && dead_or_set_p (i2, i1dest)
2767 && !reg_overlap_mentioned_p (i1dest, newpat))
2768 /* Before we can do this substitution, we must redo the test done
2769 above (see detailed comments there) that ensures that I1DEST
2770 isn't mentioned in any SETs in NEWPAT that are field assignments. */
2771 || !combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX, 0, 0))
2778 subst_low_luid = DF_INSN_LUID (i1);
2779 newpat = subst (newpat, i1dest, i1src, 0, 0);
2783 /* Fail if an autoincrement side-effect has been duplicated. Be careful
2784 to count all the ways that I2SRC and I1SRC can be used. */
2785 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
2786 && i2_is_used + added_sets_2 > 1)
2787 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2788 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
2790 /* Fail if we tried to make a new register. */
2791 || max_reg_num () != maxreg
2792 /* Fail if we couldn't do something and have a CLOBBER. */
2793 || GET_CODE (newpat) == CLOBBER
2794 /* Fail if this new pattern is a MULT and we didn't have one before
2795 at the outer level. */
2796 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
2803 /* If the actions of the earlier insns must be kept
2804 in addition to substituting them into the latest one,
2805 we must make a new PARALLEL for the latest insn
2806 to hold additional the SETs. */
2808 if (added_sets_1 || added_sets_2)
2812 if (GET_CODE (newpat) == PARALLEL)
2814 rtvec old = XVEC (newpat, 0);
2815 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
2816 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2817 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
2818 sizeof (old->elem[0]) * old->num_elem);
2823 total_sets = 1 + added_sets_1 + added_sets_2;
2824 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2825 XVECEXP (newpat, 0, 0) = old;
2829 XVECEXP (newpat, 0, --total_sets) = i1pat;
2833 /* If there is no I1, use I2's body as is. We used to also not do
2834 the subst call below if I2 was substituted into I3,
2835 but that could lose a simplification. */
2837 XVECEXP (newpat, 0, --total_sets) = i2pat;
2839 /* See comment where i2pat is assigned. */
2840 XVECEXP (newpat, 0, --total_sets)
2841 = subst (i2pat, i1dest, i1src, 0, 0);
2845 /* We come here when we are replacing a destination in I2 with the
2846 destination of I3. */
2847 validate_replacement:
2849 /* Note which hard regs this insn has as inputs. */
2850 mark_used_regs_combine (newpat);
2852 /* If recog_for_combine fails, it strips existing clobbers. If we'll
2853 consider splitting this pattern, we might need these clobbers. */
2854 if (i1 && GET_CODE (newpat) == PARALLEL
2855 && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
2857 int len = XVECLEN (newpat, 0);
2859 newpat_vec_with_clobbers = rtvec_alloc (len);
2860 for (i = 0; i < len; i++)
2861 RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
2864 /* Is the result of combination a valid instruction? */
2865 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2867 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2868 the second SET's destination is a register that is unused and isn't
2869 marked as an instruction that might trap in an EH region. In that case,
2870 we just need the first SET. This can occur when simplifying a divmod
2871 insn. We *must* test for this case here because the code below that
2872 splits two independent SETs doesn't handle this case correctly when it
2873 updates the register status.
2875 It's pointless doing this if we originally had two sets, one from
2876 i3, and one from i2. Combining then splitting the parallel results
2877 in the original i2 again plus an invalid insn (which we delete).
2878 The net effect is only to move instructions around, which makes
2879 debug info less accurate.
2881 Also check the case where the first SET's destination is unused.
2882 That would not cause incorrect code, but does cause an unneeded
2885 if (insn_code_number < 0
2886 && !(added_sets_2 && i1 == 0)
2887 && GET_CODE (newpat) == PARALLEL
2888 && XVECLEN (newpat, 0) == 2
2889 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2890 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2891 && asm_noperands (newpat) < 0)
2893 rtx set0 = XVECEXP (newpat, 0, 0);
2894 rtx set1 = XVECEXP (newpat, 0, 1);
2897 if (((REG_P (SET_DEST (set1))
2898 && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
2899 || (GET_CODE (SET_DEST (set1)) == SUBREG
2900 && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
2901 && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2902 || INTVAL (XEXP (note, 0)) <= 0)
2903 && ! side_effects_p (SET_SRC (set1)))
2906 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2909 else if (((REG_P (SET_DEST (set0))
2910 && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
2911 || (GET_CODE (SET_DEST (set0)) == SUBREG
2912 && find_reg_note (i3, REG_UNUSED,
2913 SUBREG_REG (SET_DEST (set0)))))
2914 && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2915 || INTVAL (XEXP (note, 0)) <= 0)
2916 && ! side_effects_p (SET_SRC (set0)))
2919 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2921 if (insn_code_number >= 0)
2922 changed_i3_dest = 1;
2926 /* If we were combining three insns and the result is a simple SET
2927 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2928 insns. There are two ways to do this. It can be split using a
2929 machine-specific method (like when you have an addition of a large
2930 constant) or by combine in the function find_split_point. */
2932 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2933 && asm_noperands (newpat) < 0)
2935 rtx parallel, m_split, *split;
2937 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2938 use I2DEST as a scratch register will help. In the latter case,
2939 convert I2DEST to the mode of the source of NEWPAT if we can. */
2941 m_split = combine_split_insns (newpat, i3);
2943 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2944 inputs of NEWPAT. */
2946 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2947 possible to try that as a scratch reg. This would require adding
2948 more code to make it work though. */
2950 if (m_split == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
2952 enum machine_mode new_mode = GET_MODE (SET_DEST (newpat));
2954 /* First try to split using the original register as a
2955 scratch register. */
2956 parallel = gen_rtx_PARALLEL (VOIDmode,
2957 gen_rtvec (2, newpat,
2958 gen_rtx_CLOBBER (VOIDmode,
2960 m_split = combine_split_insns (parallel, i3);
2962 /* If that didn't work, try changing the mode of I2DEST if
2965 && new_mode != GET_MODE (i2dest)
2966 && new_mode != VOIDmode
2967 && can_change_dest_mode (i2dest, added_sets_2, new_mode))
2969 enum machine_mode old_mode = GET_MODE (i2dest);
2972 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
2973 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
2976 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode);
2977 ni2dest = regno_reg_rtx[REGNO (i2dest)];
2980 parallel = (gen_rtx_PARALLEL
2982 gen_rtvec (2, newpat,
2983 gen_rtx_CLOBBER (VOIDmode,
2985 m_split = combine_split_insns (parallel, i3);
2988 && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2992 adjust_reg_mode (regno_reg_rtx[REGNO (i2dest)], old_mode);
2993 buf = undobuf.undos;
2994 undobuf.undos = buf->next;
2995 buf->next = undobuf.frees;
2996 undobuf.frees = buf;
3001 /* If recog_for_combine has discarded clobbers, try to use them
3002 again for the split. */
3003 if (m_split == 0 && newpat_vec_with_clobbers)
3005 parallel = gen_rtx_PARALLEL (VOIDmode, newpat_vec_with_clobbers);
3006 m_split = combine_split_insns (parallel, i3);
3009 if (m_split && NEXT_INSN (m_split) == NULL_RTX)
3011 m_split = PATTERN (m_split);
3012 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
3013 if (insn_code_number >= 0)
3016 else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
3017 && (next_real_insn (i2) == i3
3018 || ! use_crosses_set_p (PATTERN (m_split), DF_INSN_LUID (i2))))
3021 rtx newi3pat = PATTERN (NEXT_INSN (m_split));
3022 newi2pat = PATTERN (m_split);
3024 i3set = single_set (NEXT_INSN (m_split));
3025 i2set = single_set (m_split);
3027 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3029 /* If I2 or I3 has multiple SETs, we won't know how to track
3030 register status, so don't use these insns. If I2's destination
3031 is used between I2 and I3, we also can't use these insns. */
3033 if (i2_code_number >= 0 && i2set && i3set
3034 && (next_real_insn (i2) == i3
3035 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
3036 insn_code_number = recog_for_combine (&newi3pat, i3,
3038 if (insn_code_number >= 0)
3041 /* It is possible that both insns now set the destination of I3.
3042 If so, we must show an extra use of it. */
3044 if (insn_code_number >= 0)
3046 rtx new_i3_dest = SET_DEST (i3set);
3047 rtx new_i2_dest = SET_DEST (i2set);
3049 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
3050 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
3051 || GET_CODE (new_i3_dest) == SUBREG)
3052 new_i3_dest = XEXP (new_i3_dest, 0);
3054 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
3055 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
3056 || GET_CODE (new_i2_dest) == SUBREG)
3057 new_i2_dest = XEXP (new_i2_dest, 0);
3059 if (REG_P (new_i3_dest)
3060 && REG_P (new_i2_dest)
3061 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
3062 INC_REG_N_SETS (REGNO (new_i2_dest), 1);
3066 /* If we can split it and use I2DEST, go ahead and see if that
3067 helps things be recognized. Verify that none of the registers
3068 are set between I2 and I3. */
3069 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
3073 /* We need I2DEST in the proper mode. If it is a hard register
3074 or the only use of a pseudo, we can change its mode.
3075 Make sure we don't change a hard register to have a mode that
3076 isn't valid for it, or change the number of registers. */
3077 && (GET_MODE (*split) == GET_MODE (i2dest)
3078 || GET_MODE (*split) == VOIDmode
3079 || can_change_dest_mode (i2dest, added_sets_2,
3081 && (next_real_insn (i2) == i3
3082 || ! use_crosses_set_p (*split, DF_INSN_LUID (i2)))
3083 /* We can't overwrite I2DEST if its value is still used by
3085 && ! reg_referenced_p (i2dest, newpat))
3087 rtx newdest = i2dest;
3088 enum rtx_code split_code = GET_CODE (*split);
3089 enum machine_mode split_mode = GET_MODE (*split);
3090 bool subst_done = false;
3091 newi2pat = NULL_RTX;
3093 /* Get NEWDEST as a register in the proper mode. We have already
3094 validated that we can do this. */
3095 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
3097 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3098 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
3101 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode);
3102 newdest = regno_reg_rtx[REGNO (i2dest)];
3106 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3107 an ASHIFT. This can occur if it was inside a PLUS and hence
3108 appeared to be a memory address. This is a kludge. */
3109 if (split_code == MULT
3110 && GET_CODE (XEXP (*split, 1)) == CONST_INT
3111 && INTVAL (XEXP (*split, 1)) > 0
3112 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
3114 SUBST (*split, gen_rtx_ASHIFT (split_mode,
3115 XEXP (*split, 0), GEN_INT (i)));
3116 /* Update split_code because we may not have a multiply
3118 split_code = GET_CODE (*split);
3121 #ifdef INSN_SCHEDULING
3122 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3123 be written as a ZERO_EXTEND. */
3124 if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
3126 #ifdef LOAD_EXTEND_OP
3127 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3128 what it really is. */
3129 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
3131 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
3132 SUBREG_REG (*split)));
3135 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
3136 SUBREG_REG (*split)));
3140 /* Attempt to split binary operators using arithmetic identities. */
3141 if (BINARY_P (SET_SRC (newpat))
3142 && split_mode == GET_MODE (SET_SRC (newpat))
3143 && ! side_effects_p (SET_SRC (newpat)))
3145 rtx setsrc = SET_SRC (newpat);
3146 enum machine_mode mode = GET_MODE (setsrc);
3147 enum rtx_code code = GET_CODE (setsrc);
3148 rtx src_op0 = XEXP (setsrc, 0);
3149 rtx src_op1 = XEXP (setsrc, 1);
3151 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3152 if (rtx_equal_p (src_op0, src_op1))
3154 newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0);
3155 SUBST (XEXP (setsrc, 0), newdest);
3156 SUBST (XEXP (setsrc, 1), newdest);
3159 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3160 else if ((code == PLUS || code == MULT)
3161 && GET_CODE (src_op0) == code
3162 && GET_CODE (XEXP (src_op0, 0)) == code
3163 && (INTEGRAL_MODE_P (mode)
3164 || (FLOAT_MODE_P (mode)
3165 && flag_unsafe_math_optimizations)))
3167 rtx p = XEXP (XEXP (src_op0, 0), 0);
3168 rtx q = XEXP (XEXP (src_op0, 0), 1);
3169 rtx r = XEXP (src_op0, 1);
3172 /* Split both "((X op Y) op X) op Y" and
3173 "((X op Y) op Y) op X" as "T op T" where T is
3175 if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
3176 || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
3178 newi2pat = gen_rtx_SET (VOIDmode, newdest,
3180 SUBST (XEXP (setsrc, 0), newdest);
3181 SUBST (XEXP (setsrc, 1), newdest);
3184 /* Split "((X op X) op Y) op Y)" as "T op T" where
3186 else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
3188 rtx tmp = simplify_gen_binary (code, mode, p, r);
3189 newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp);
3190 SUBST (XEXP (setsrc, 0), newdest);
3191 SUBST (XEXP (setsrc, 1), newdest);
3199 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
3200 SUBST (*split, newdest);
3203 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3205 /* recog_for_combine might have added CLOBBERs to newi2pat.
3206 Make sure NEWPAT does not depend on the clobbered regs. */
3207 if (GET_CODE (newi2pat) == PARALLEL)
3208 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3209 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3211 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3212 if (reg_overlap_mentioned_p (reg, newpat))
3219 /* If the split point was a MULT and we didn't have one before,
3220 don't use one now. */
3221 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
3222 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3226 /* Check for a case where we loaded from memory in a narrow mode and
3227 then sign extended it, but we need both registers. In that case,
3228 we have a PARALLEL with both loads from the same memory location.
3229 We can split this into a load from memory followed by a register-register
3230 copy. This saves at least one insn, more if register allocation can
3233 We cannot do this if the destination of the first assignment is a
3234 condition code register or cc0. We eliminate this case by making sure
3235 the SET_DEST and SET_SRC have the same mode.
3237 We cannot do this if the destination of the second assignment is
3238 a register that we have already assumed is zero-extended. Similarly
3239 for a SUBREG of such a register. */
3241 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3242 && GET_CODE (newpat) == PARALLEL
3243 && XVECLEN (newpat, 0) == 2
3244 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3245 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
3246 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
3247 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
3248 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3249 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3250 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
3251 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3253 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3254 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3255 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
3257 && VEC_index (reg_stat_type, reg_stat,
3258 REGNO (temp))->nonzero_bits != 0
3259 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
3260 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
3261 && (VEC_index (reg_stat_type, reg_stat,
3262 REGNO (temp))->nonzero_bits
3263 != GET_MODE_MASK (word_mode))))
3264 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
3265 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
3267 && VEC_index (reg_stat_type, reg_stat,
3268 REGNO (temp))->nonzero_bits != 0
3269 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
3270 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
3271 && (VEC_index (reg_stat_type, reg_stat,
3272 REGNO (temp))->nonzero_bits
3273 != GET_MODE_MASK (word_mode)))))
3274 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3275 SET_SRC (XVECEXP (newpat, 0, 1)))
3276 && ! find_reg_note (i3, REG_UNUSED,
3277 SET_DEST (XVECEXP (newpat, 0, 0))))
3281 newi2pat = XVECEXP (newpat, 0, 0);
3282 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
3283 newpat = XVECEXP (newpat, 0, 1);
3284 SUBST (SET_SRC (newpat),
3285 gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
3286 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3288 if (i2_code_number >= 0)
3289 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3291 if (insn_code_number >= 0)
3295 /* Similarly, check for a case where we have a PARALLEL of two independent
3296 SETs but we started with three insns. In this case, we can do the sets
3297 as two separate insns. This case occurs when some SET allows two
3298 other insns to combine, but the destination of that SET is still live. */
3300 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3301 && GET_CODE (newpat) == PARALLEL
3302 && XVECLEN (newpat, 0) == 2
3303 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3304 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
3305 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
3306 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3307 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3308 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3309 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3311 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3312 XVECEXP (newpat, 0, 0))
3313 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
3314 XVECEXP (newpat, 0, 1))
3315 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
3316 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1))))
3318 /* We cannot split the parallel into two sets if both sets
3320 && ! (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0))
3321 && reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 1)))
3325 /* Normally, it doesn't matter which of the two is done first,
3326 but it does if one references cc0. In that case, it has to
3329 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
3331 newi2pat = XVECEXP (newpat, 0, 0);
3332 newpat = XVECEXP (newpat, 0, 1);
3337 newi2pat = XVECEXP (newpat, 0, 1);
3338 newpat = XVECEXP (newpat, 0, 0);
3341 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3343 if (i2_code_number >= 0)
3344 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3347 /* If it still isn't recognized, fail and change things back the way they
3349 if ((insn_code_number < 0
3350 /* Is the result a reasonable ASM_OPERANDS? */
3351 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
3357 /* If we had to change another insn, make sure it is valid also. */
3358 if (undobuf.other_insn)
3360 CLEAR_HARD_REG_SET (newpat_used_regs);
3362 other_pat = PATTERN (undobuf.other_insn);
3363 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
3366 if (other_code_number < 0 && ! check_asm_operands (other_pat))
3374 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3375 they are adjacent to each other or not. */
3377 rtx p = prev_nonnote_insn (i3);
3378 if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
3379 && sets_cc0_p (newi2pat))
3387 /* Only allow this combination if insn_rtx_costs reports that the
3388 replacement instructions are cheaper than the originals. */
3389 if (!combine_validate_cost (i1, i2, i3, newpat, newi2pat, other_pat))
3395 /* If we will be able to accept this, we have made a
3396 change to the destination of I3. This requires us to
3397 do a few adjustments. */
3399 if (changed_i3_dest)
3401 PATTERN (i3) = newpat;
3402 adjust_for_new_dest (i3);
3405 /* We now know that we can do this combination. Merge the insns and
3406 update the status of registers and LOG_LINKS. */
3408 if (undobuf.other_insn)
3412 PATTERN (undobuf.other_insn) = other_pat;
3414 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
3415 are still valid. Then add any non-duplicate notes added by
3416 recog_for_combine. */
3417 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
3419 next = XEXP (note, 1);
3421 if (REG_NOTE_KIND (note) == REG_UNUSED
3422 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
3423 remove_note (undobuf.other_insn, note);
3426 distribute_notes (new_other_notes, undobuf.other_insn,
3427 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
3436 /* I3 now uses what used to be its destination and which is now
3437 I2's destination. This requires us to do a few adjustments. */
3438 PATTERN (i3) = newpat;
3439 adjust_for_new_dest (i3);
3441 /* We need a LOG_LINK from I3 to I2. But we used to have one,
3444 However, some later insn might be using I2's dest and have
3445 a LOG_LINK pointing at I3. We must remove this link.
3446 The simplest way to remove the link is to point it at I1,
3447 which we know will be a NOTE. */
3449 /* newi2pat is usually a SET here; however, recog_for_combine might
3450 have added some clobbers. */
3451 if (GET_CODE (newi2pat) == PARALLEL)
3452 ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
3454 ni2dest = SET_DEST (newi2pat);
3456 for (insn = NEXT_INSN (i3);
3457 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3458 || insn != BB_HEAD (this_basic_block->next_bb));
3459 insn = NEXT_INSN (insn))
3461 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
3463 for (link = LOG_LINKS (insn); link;
3464 link = XEXP (link, 1))
3465 if (XEXP (link, 0) == i3)
3466 XEXP (link, 0) = i1;
3474 rtx i3notes, i2notes, i1notes = 0;
3475 rtx i3links, i2links, i1links = 0;
3478 /* Compute which registers we expect to eliminate. newi2pat may be setting
3479 either i3dest or i2dest, so we must check it. Also, i1dest may be the
3480 same as i3dest, in which case newi2pat may be setting i1dest. */
3481 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
3482 || i2dest_in_i2src || i2dest_in_i1src
3485 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
3486 || (newi2pat && reg_set_p (i1dest, newi2pat))
3490 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
3492 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
3493 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
3495 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
3497 /* Ensure that we do not have something that should not be shared but
3498 occurs multiple times in the new insns. Check this by first
3499 resetting all the `used' flags and then copying anything is shared. */
3501 reset_used_flags (i3notes);
3502 reset_used_flags (i2notes);
3503 reset_used_flags (i1notes);
3504 reset_used_flags (newpat);
3505 reset_used_flags (newi2pat);
3506 if (undobuf.other_insn)
3507 reset_used_flags (PATTERN (undobuf.other_insn));
3509 i3notes = copy_rtx_if_shared (i3notes);
3510 i2notes = copy_rtx_if_shared (i2notes);
3511 i1notes = copy_rtx_if_shared (i1notes);
3512 newpat = copy_rtx_if_shared (newpat);
3513 newi2pat = copy_rtx_if_shared (newi2pat);
3514 if (undobuf.other_insn)
3515 reset_used_flags (PATTERN (undobuf.other_insn));
3517 INSN_CODE (i3) = insn_code_number;
3518 PATTERN (i3) = newpat;
3520 if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
3522 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
3524 reset_used_flags (call_usage);
3525 call_usage = copy_rtx (call_usage);
3528 replace_rtx (call_usage, i2dest, i2src);
3531 replace_rtx (call_usage, i1dest, i1src);
3533 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
3536 if (undobuf.other_insn)
3537 INSN_CODE (undobuf.other_insn) = other_code_number;
3539 /* We had one special case above where I2 had more than one set and
3540 we replaced a destination of one of those sets with the destination
3541 of I3. In that case, we have to update LOG_LINKS of insns later
3542 in this basic block. Note that this (expensive) case is rare.
3544 Also, in this case, we must pretend that all REG_NOTEs for I2
3545 actually came from I3, so that REG_UNUSED notes from I2 will be
3546 properly handled. */
3548 if (i3_subst_into_i2)
3550 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
3551 if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET
3552 || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER)
3553 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
3554 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
3555 && ! find_reg_note (i2, REG_UNUSED,
3556 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
3557 for (temp = NEXT_INSN (i2);
3558 temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3559 || BB_HEAD (this_basic_block) != temp);
3560 temp = NEXT_INSN (temp))
3561 if (temp != i3 && INSN_P (temp))
3562 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
3563 if (XEXP (link, 0) == i2)
3564 XEXP (link, 0) = i3;
3569 while (XEXP (link, 1))
3570 link = XEXP (link, 1);
3571 XEXP (link, 1) = i2notes;
3585 INSN_CODE (i2) = i2_code_number;
3586 PATTERN (i2) = newi2pat;
3589 SET_INSN_DELETED (i2);
3595 SET_INSN_DELETED (i1);
3598 /* Get death notes for everything that is now used in either I3 or
3599 I2 and used to die in a previous insn. If we built two new
3600 patterns, move from I1 to I2 then I2 to I3 so that we get the
3601 proper movement on registers that I2 modifies. */
3605 move_deaths (newi2pat, NULL_RTX, DF_INSN_LUID (i1), i2, &midnotes);
3606 move_deaths (newpat, newi2pat, DF_INSN_LUID (i1), i3, &midnotes);
3609 move_deaths (newpat, NULL_RTX, i1 ? DF_INSN_LUID (i1) : DF_INSN_LUID (i2),
3612 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
3614 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
3617 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
3620 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
3623 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3626 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
3627 know these are REG_UNUSED and want them to go to the desired insn,
3628 so we always pass it as i3. */
3630 if (newi2pat && new_i2_notes)
3631 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3634 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
3636 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
3637 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
3638 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
3639 in that case, it might delete I2. Similarly for I2 and I1.
3640 Show an additional death due to the REG_DEAD note we make here. If
3641 we discard it in distribute_notes, we will decrement it again. */
3645 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
3646 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
3648 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
3650 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
3652 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3656 if (i2dest_in_i2src)
3658 if (newi2pat && reg_set_p (i2dest, newi2pat))
3659 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
3660 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3662 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
3663 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3664 NULL_RTX, NULL_RTX);
3667 if (i1dest_in_i1src)
3669 if (newi2pat && reg_set_p (i1dest, newi2pat))
3670 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
3671 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3673 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
3674 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3675 NULL_RTX, NULL_RTX);
3678 distribute_links (i3links);
3679 distribute_links (i2links);
3680 distribute_links (i1links);
3685 rtx i2_insn = 0, i2_val = 0, set;
3687 /* The insn that used to set this register doesn't exist, and
3688 this life of the register may not exist either. See if one of
3689 I3's links points to an insn that sets I2DEST. If it does,
3690 that is now the last known value for I2DEST. If we don't update
3691 this and I2 set the register to a value that depended on its old
3692 contents, we will get confused. If this insn is used, thing
3693 will be set correctly in combine_instructions. */
3695 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3696 if ((set = single_set (XEXP (link, 0))) != 0
3697 && rtx_equal_p (i2dest, SET_DEST (set)))
3698 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
3700 record_value_for_reg (i2dest, i2_insn, i2_val);
3702 /* If the reg formerly set in I2 died only once and that was in I3,
3703 zero its use count so it won't make `reload' do any work. */
3705 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
3706 && ! i2dest_in_i2src)
3708 regno = REGNO (i2dest);
3709 INC_REG_N_SETS (regno, -1);
3713 if (i1 && REG_P (i1dest))
3716 rtx i1_insn = 0, i1_val = 0, set;
3718 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3719 if ((set = single_set (XEXP (link, 0))) != 0
3720 && rtx_equal_p (i1dest, SET_DEST (set)))
3721 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
3723 record_value_for_reg (i1dest, i1_insn, i1_val);
3725 regno = REGNO (i1dest);
3726 if (! added_sets_1 && ! i1dest_in_i1src)
3727 INC_REG_N_SETS (regno, -1);
3730 /* Update reg_stat[].nonzero_bits et al for any changes that may have
3731 been made to this insn. The order of
3732 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
3733 can affect nonzero_bits of newpat */
3735 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
3736 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
3739 if (undobuf.other_insn != NULL_RTX)
3743 fprintf (dump_file, "modifying other_insn ");
3744 dump_insn_slim (dump_file, undobuf.other_insn);
3746 df_insn_rescan (undobuf.other_insn);
3749 if (i1 && !(NOTE_P(i1) && (NOTE_KIND (i1) == NOTE_INSN_DELETED)))
3753 fprintf (dump_file, "modifying insn i1 ");
3754 dump_insn_slim (dump_file, i1);
3756 df_insn_rescan (i1);
3759 if (i2 && !(NOTE_P(i2) && (NOTE_KIND (i2) == NOTE_INSN_DELETED)))
3763 fprintf (dump_file, "modifying insn i2 ");
3764 dump_insn_slim (dump_file, i2);
3766 df_insn_rescan (i2);
3769 if (i3 && !(NOTE_P(i3) && (NOTE_KIND (i3) == NOTE_INSN_DELETED)))
3773 fprintf (dump_file, "modifying insn i3 ");
3774 dump_insn_slim (dump_file, i3);
3776 df_insn_rescan (i3);
3779 /* Set new_direct_jump_p if a new return or simple jump instruction
3780 has been created. Adjust the CFG accordingly. */
3782 if (returnjump_p (i3) || any_uncondjump_p (i3))
3784 *new_direct_jump_p = 1;
3785 mark_jump_label (PATTERN (i3), i3, 0);
3786 update_cfg_for_uncondjump (i3);
3789 if (undobuf.other_insn != NULL_RTX
3790 && (returnjump_p (undobuf.other_insn)
3791 || any_uncondjump_p (undobuf.other_insn)))
3793 *new_direct_jump_p = 1;
3794 update_cfg_for_uncondjump (undobuf.other_insn);
3797 /* A noop might also need cleaning up of CFG, if it comes from the
3798 simplification of a jump. */
3799 if (GET_CODE (newpat) == SET
3800 && SET_SRC (newpat) == pc_rtx
3801 && SET_DEST (newpat) == pc_rtx)
3803 *new_direct_jump_p = 1;
3804 update_cfg_for_uncondjump (i3);
3807 combine_successes++;
3810 if (added_links_insn
3811 && (newi2pat == 0 || DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i2))
3812 && DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i3))
3813 return added_links_insn;
3815 return newi2pat ? i2 : i3;
3818 /* Undo all the modifications recorded in undobuf. */
3823 struct undo *undo, *next;
3825 for (undo = undobuf.undos; undo; undo = next)
3831 *undo->where.r = undo->old_contents.r;
3834 *undo->where.i = undo->old_contents.i;
3837 adjust_reg_mode (*undo->where.r, undo->old_contents.m);
3843 undo->next = undobuf.frees;
3844 undobuf.frees = undo;
3850 /* We've committed to accepting the changes we made. Move all
3851 of the undos to the free list. */
3856 struct undo *undo, *next;
3858 for (undo = undobuf.undos; undo; undo = next)
3861 undo->next = undobuf.frees;
3862 undobuf.frees = undo;
3867 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
3868 where we have an arithmetic expression and return that point. LOC will
3871 try_combine will call this function to see if an insn can be split into
3875 find_split_point (rtx *loc, rtx insn)
3878 enum rtx_code code = GET_CODE (x);
3880 unsigned HOST_WIDE_INT len = 0;
3881 HOST_WIDE_INT pos = 0;
3883 rtx inner = NULL_RTX;
3885 /* First special-case some codes. */
3889 #ifdef INSN_SCHEDULING
3890 /* If we are making a paradoxical SUBREG invalid, it becomes a split
3892 if (MEM_P (SUBREG_REG (x)))
3895 return find_split_point (&SUBREG_REG (x), insn);
3899 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
3900 using LO_SUM and HIGH. */
3901 if (GET_CODE (XEXP (x, 0)) == CONST
3902 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
3905 gen_rtx_LO_SUM (Pmode,
3906 gen_rtx_HIGH (Pmode, XEXP (x, 0)),
3908 return &XEXP (XEXP (x, 0), 0);
3912 /* If we have a PLUS whose second operand is a constant and the
3913 address is not valid, perhaps will can split it up using
3914 the machine-specific way to split large constants. We use
3915 the first pseudo-reg (one of the virtual regs) as a placeholder;
3916 it will not remain in the result. */
3917 if (GET_CODE (XEXP (x, 0)) == PLUS
3918 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3919 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
3921 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
3922 rtx seq = combine_split_insns (gen_rtx_SET (VOIDmode, reg,
3926 /* This should have produced two insns, each of which sets our
3927 placeholder. If the source of the second is a valid address,
3928 we can make put both sources together and make a split point
3932 && NEXT_INSN (seq) != NULL_RTX
3933 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
3934 && NONJUMP_INSN_P (seq)
3935 && GET_CODE (PATTERN (seq)) == SET
3936 && SET_DEST (PATTERN (seq)) == reg
3937 && ! reg_mentioned_p (reg,
3938 SET_SRC (PATTERN (seq)))
3939 && NONJUMP_INSN_P (NEXT_INSN (seq))
3940 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
3941 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
3942 && memory_address_p (GET_MODE (x),
3943 SET_SRC (PATTERN (NEXT_INSN (seq)))))
3945 rtx src1 = SET_SRC (PATTERN (seq));
3946 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
3948 /* Replace the placeholder in SRC2 with SRC1. If we can
3949 find where in SRC2 it was placed, that can become our
3950 split point and we can replace this address with SRC2.
3951 Just try two obvious places. */
3953 src2 = replace_rtx (src2, reg, src1);
3955 if (XEXP (src2, 0) == src1)
3956 split = &XEXP (src2, 0);
3957 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
3958 && XEXP (XEXP (src2, 0), 0) == src1)
3959 split = &XEXP (XEXP (src2, 0), 0);
3963 SUBST (XEXP (x, 0), src2);
3968 /* If that didn't work, perhaps the first operand is complex and
3969 needs to be computed separately, so make a split point there.
3970 This will occur on machines that just support REG + CONST
3971 and have a constant moved through some previous computation. */
3973 else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
3974 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
3975 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
3976 return &XEXP (XEXP (x, 0), 0);
3979 /* If we have a PLUS whose first operand is complex, try computing it
3980 separately by making a split there. */
3981 if (GET_CODE (XEXP (x, 0)) == PLUS
3982 && ! memory_address_p (GET_MODE (x), XEXP (x, 0))
3983 && ! OBJECT_P (XEXP (XEXP (x, 0), 0))
3984 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
3985 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
3986 return &XEXP (XEXP (x, 0), 0);
3991 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
3992 ZERO_EXTRACT, the most likely reason why this doesn't match is that
3993 we need to put the operand into a register. So split at that
3996 if (SET_DEST (x) == cc0_rtx
3997 && GET_CODE (SET_SRC (x)) != COMPARE
3998 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
3999 && !OBJECT_P (SET_SRC (x))
4000 && ! (GET_CODE (SET_SRC (x)) == SUBREG
4001 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
4002 return &SET_SRC (x);
4005 /* See if we can split SET_SRC as it stands. */
4006 split = find_split_point (&SET_SRC (x), insn);
4007 if (split && split != &SET_SRC (x))
4010 /* See if we can split SET_DEST as it stands. */
4011 split = find_split_point (&SET_DEST (x), insn);
4012 if (split && split != &SET_DEST (x))
4015 /* See if this is a bitfield assignment with everything constant. If
4016 so, this is an IOR of an AND, so split it into that. */
4017 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
4018 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
4019 <= HOST_BITS_PER_WIDE_INT)
4020 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
4021 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
4022 && GET_CODE (SET_SRC (x)) == CONST_INT
4023 && ((INTVAL (XEXP (SET_DEST (x), 1))
4024 + INTVAL (XEXP (SET_DEST (x), 2)))
4025 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
4026 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
4028 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
4029 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
4030 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
4031 rtx dest = XEXP (SET_DEST (x), 0);
4032 enum machine_mode mode = GET_MODE (dest);
4033 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
4036 if (BITS_BIG_ENDIAN)
4037 pos = GET_MODE_BITSIZE (mode) - len - pos;
4039 or_mask = gen_int_mode (src << pos, mode);
4042 simplify_gen_binary (IOR, mode, dest, or_mask));
4045 rtx negmask = gen_int_mode (~(mask << pos), mode);
4047 simplify_gen_binary (IOR, mode,
4048 simplify_gen_binary (AND, mode,
4053 SUBST (SET_DEST (x), dest);
4055 split = find_split_point (&SET_SRC (x), insn);
4056 if (split && split != &SET_SRC (x))
4060 /* Otherwise, see if this is an operation that we can split into two.
4061 If so, try to split that. */
4062 code = GET_CODE (SET_SRC (x));
4067 /* If we are AND'ing with a large constant that is only a single
4068 bit and the result is only being used in a context where we
4069 need to know if it is zero or nonzero, replace it with a bit
4070 extraction. This will avoid the large constant, which might
4071 have taken more than one insn to make. If the constant were
4072 not a valid argument to the AND but took only one insn to make,
4073 this is no worse, but if it took more than one insn, it will
4076 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
4077 && REG_P (XEXP (SET_SRC (x), 0))
4078 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
4079 && REG_P (SET_DEST (x))
4080 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
4081 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
4082 && XEXP (*split, 0) == SET_DEST (x)
4083 && XEXP (*split, 1) == const0_rtx)
4085 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
4086 XEXP (SET_SRC (x), 0),
4087 pos, NULL_RTX, 1, 1, 0, 0);
4088 if (extraction != 0)
4090 SUBST (SET_SRC (x), extraction);
4091 return find_split_point (loc, insn);
4097 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4098 is known to be on, this can be converted into a NEG of a shift. */
4099 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
4100 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
4101 && 1 <= (pos = exact_log2
4102 (nonzero_bits (XEXP (SET_SRC (x), 0),
4103 GET_MODE (XEXP (SET_SRC (x), 0))))))
4105 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
4109 gen_rtx_LSHIFTRT (mode,
4110 XEXP (SET_SRC (x), 0),
4113 split = find_split_point (&SET_SRC (x), insn);
4114 if (split && split != &SET_SRC (x))
4120 inner = XEXP (SET_SRC (x), 0);
4122 /* We can't optimize if either mode is a partial integer
4123 mode as we don't know how many bits are significant
4125 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
4126 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
4130 len = GET_MODE_BITSIZE (GET_MODE (inner));
4136 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
4137 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
4139 inner = XEXP (SET_SRC (x), 0);
4140 len = INTVAL (XEXP (SET_SRC (x), 1));
4141 pos = INTVAL (XEXP (SET_SRC (x), 2));
4143 if (BITS_BIG_ENDIAN)
4144 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
4145 unsignedp = (code == ZERO_EXTRACT);
4153 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
4155 enum machine_mode mode = GET_MODE (SET_SRC (x));
4157 /* For unsigned, we have a choice of a shift followed by an
4158 AND or two shifts. Use two shifts for field sizes where the
4159 constant might be too large. We assume here that we can
4160 always at least get 8-bit constants in an AND insn, which is
4161 true for every current RISC. */
4163 if (unsignedp && len <= 8)
4168 (mode, gen_lowpart (mode, inner),
4170 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
4172 split = find_split_point (&SET_SRC (x), insn);
4173 if (split && split != &SET_SRC (x))
4180 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
4181 gen_rtx_ASHIFT (mode,
4182 gen_lowpart (mode, inner),
4183 GEN_INT (GET_MODE_BITSIZE (mode)
4185 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
4187 split = find_split_point (&SET_SRC (x), insn);
4188 if (split && split != &SET_SRC (x))
4193 /* See if this is a simple operation with a constant as the second
4194 operand. It might be that this constant is out of range and hence
4195 could be used as a split point. */
4196 if (BINARY_P (SET_SRC (x))
4197 && CONSTANT_P (XEXP (SET_SRC (x), 1))
4198 && (OBJECT_P (XEXP (SET_SRC (x), 0))
4199 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
4200 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
4201 return &XEXP (SET_SRC (x), 1);
4203 /* Finally, see if this is a simple operation with its first operand
4204 not in a register. The operation might require this operand in a
4205 register, so return it as a split point. We can always do this
4206 because if the first operand were another operation, we would have
4207 already found it as a split point. */
4208 if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
4209 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
4210 return &XEXP (SET_SRC (x), 0);
4216 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4217 it is better to write this as (not (ior A B)) so we can split it.
4218 Similarly for IOR. */
4219 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
4222 gen_rtx_NOT (GET_MODE (x),
4223 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
4225 XEXP (XEXP (x, 0), 0),
4226 XEXP (XEXP (x, 1), 0))));
4227 return find_split_point (loc, insn);
4230 /* Many RISC machines have a large set of logical insns. If the
4231 second operand is a NOT, put it first so we will try to split the
4232 other operand first. */
4233 if (GET_CODE (XEXP (x, 1)) == NOT)
4235 rtx tem = XEXP (x, 0);
4236 SUBST (XEXP (x, 0), XEXP (x, 1));
4237 SUBST (XEXP (x, 1), tem);
4245 /* Otherwise, select our actions depending on our rtx class. */
4246 switch (GET_RTX_CLASS (code))
4248 case RTX_BITFIELD_OPS: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
4250 split = find_split_point (&XEXP (x, 2), insn);
4253 /* ... fall through ... */
4255 case RTX_COMM_ARITH:
4257 case RTX_COMM_COMPARE:
4258 split = find_split_point (&XEXP (x, 1), insn);
4261 /* ... fall through ... */
4263 /* Some machines have (and (shift ...) ...) insns. If X is not
4264 an AND, but XEXP (X, 0) is, use it as our split point. */
4265 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
4266 return &XEXP (x, 0);
4268 split = find_split_point (&XEXP (x, 0), insn);
4274 /* Otherwise, we don't have a split point. */
4279 /* Throughout X, replace FROM with TO, and return the result.
4280 The result is TO if X is FROM;
4281 otherwise the result is X, but its contents may have been modified.
4282 If they were modified, a record was made in undobuf so that
4283 undo_all will (among other things) return X to its original state.
4285 If the number of changes necessary is too much to record to undo,
4286 the excess changes are not made, so the result is invalid.
4287 The changes already made can still be undone.
4288 undobuf.num_undo is incremented for such changes, so by testing that
4289 the caller can tell whether the result is valid.
4291 `n_occurrences' is incremented each time FROM is replaced.
4293 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
4295 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
4296 by copying if `n_occurrences' is nonzero. */
4299 subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy)
4301 enum rtx_code code = GET_CODE (x);
4302 enum machine_mode op0_mode = VOIDmode;
4307 /* Two expressions are equal if they are identical copies of a shared
4308 RTX or if they are both registers with the same register number
4311 #define COMBINE_RTX_EQUAL_P(X,Y) \
4313 || (REG_P (X) && REG_P (Y) \
4314 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
4316 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
4319 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
4322 /* If X and FROM are the same register but different modes, they
4323 will not have been seen as equal above. However, the log links code
4324 will make a LOG_LINKS entry for that case. If we do nothing, we
4325 will try to rerecognize our original insn and, when it succeeds,
4326 we will delete the feeding insn, which is incorrect.
4328 So force this insn not to match in this (rare) case. */
4329 if (! in_dest && code == REG && REG_P (from)
4330 && reg_overlap_mentioned_p (x, from))
4331 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
4333 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
4334 of which may contain things that can be combined. */
4335 if (code != MEM && code != LO_SUM && OBJECT_P (x))
4338 /* It is possible to have a subexpression appear twice in the insn.
4339 Suppose that FROM is a register that appears within TO.
4340 Then, after that subexpression has been scanned once by `subst',
4341 the second time it is scanned, TO may be found. If we were
4342 to scan TO here, we would find FROM within it and create a
4343 self-referent rtl structure which is completely wrong. */
4344 if (COMBINE_RTX_EQUAL_P (x, to))
4347 /* Parallel asm_operands need special attention because all of the
4348 inputs are shared across the arms. Furthermore, unsharing the
4349 rtl results in recognition failures. Failure to handle this case
4350 specially can result in circular rtl.
4352 Solve this by doing a normal pass across the first entry of the
4353 parallel, and only processing the SET_DESTs of the subsequent
4356 if (code == PARALLEL
4357 && GET_CODE (XVECEXP (x, 0, 0)) == SET
4358 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
4360 new_rtx = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
4362 /* If this substitution failed, this whole thing fails. */
4363 if (GET_CODE (new_rtx) == CLOBBER
4364 && XEXP (new_rtx, 0) == const0_rtx)
4367 SUBST (XVECEXP (x, 0, 0), new_rtx);
4369 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
4371 rtx dest = SET_DEST (XVECEXP (x, 0, i));
4374 && GET_CODE (dest) != CC0
4375 && GET_CODE (dest) != PC)
4377 new_rtx = subst (dest, from, to, 0, unique_copy);
4379 /* If this substitution failed, this whole thing fails. */
4380 if (GET_CODE (new_rtx) == CLOBBER
4381 && XEXP (new_rtx, 0) == const0_rtx)
4384 SUBST (SET_DEST (XVECEXP (x, 0, i)), new_rtx);
4390 len = GET_RTX_LENGTH (code);
4391 fmt = GET_RTX_FORMAT (code);
4393 /* We don't need to process a SET_DEST that is a register, CC0,
4394 or PC, so set up to skip this common case. All other cases
4395 where we want to suppress replacing something inside a
4396 SET_SRC are handled via the IN_DEST operand. */
4398 && (REG_P (SET_DEST (x))
4399 || GET_CODE (SET_DEST (x)) == CC0
4400 || GET_CODE (SET_DEST (x)) == PC))
4403 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
4406 op0_mode = GET_MODE (XEXP (x, 0));
4408 for (i = 0; i < len; i++)
4413 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4415 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
4417 new_rtx = (unique_copy && n_occurrences
4418 ? copy_rtx (to) : to);
4423 new_rtx = subst (XVECEXP (x, i, j), from, to, 0,
4426 /* If this substitution failed, this whole thing
4428 if (GET_CODE (new_rtx) == CLOBBER
4429 && XEXP (new_rtx, 0) == const0_rtx)
4433 SUBST (XVECEXP (x, i, j), new_rtx);
4436 else if (fmt[i] == 'e')
4438 /* If this is a register being set, ignore it. */
4439 new_rtx = XEXP (x, i);
4442 && (((code == SUBREG || code == ZERO_EXTRACT)
4444 || code == STRICT_LOW_PART))
4447 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
4449 /* In general, don't install a subreg involving two
4450 modes not tieable. It can worsen register
4451 allocation, and can even make invalid reload
4452 insns, since the reg inside may need to be copied
4453 from in the outside mode, and that may be invalid
4454 if it is an fp reg copied in integer mode.
4456 We allow two exceptions to this: It is valid if
4457 it is inside another SUBREG and the mode of that
4458 SUBREG and the mode of the inside of TO is
4459 tieable and it is valid if X is a SET that copies
4462 if (GET_CODE (to) == SUBREG
4463 && ! MODES_TIEABLE_P (GET_MODE (to),
4464 GET_MODE (SUBREG_REG (to)))
4465 && ! (code == SUBREG
4466 && MODES_TIEABLE_P (GET_MODE (x),
4467 GET_MODE (SUBREG_REG (to))))
4469 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
4472 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4474 #ifdef CANNOT_CHANGE_MODE_CLASS
4477 && REGNO (to) < FIRST_PSEUDO_REGISTER
4478 && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
4481 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4484 new_rtx = (unique_copy && n_occurrences ? copy_rtx (to) : to);
4488 /* If we are in a SET_DEST, suppress most cases unless we
4489 have gone inside a MEM, in which case we want to
4490 simplify the address. We assume here that things that
4491 are actually part of the destination have their inner
4492 parts in the first expression. This is true for SUBREG,
4493 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
4494 things aside from REG and MEM that should appear in a
4496 new_rtx = subst (XEXP (x, i), from, to,
4498 && (code == SUBREG || code == STRICT_LOW_PART
4499 || code == ZERO_EXTRACT))
4501 && i == 0), unique_copy);
4503 /* If we found that we will have to reject this combination,
4504 indicate that by returning the CLOBBER ourselves, rather than
4505 an expression containing it. This will speed things up as
4506 well as prevent accidents where two CLOBBERs are considered
4507 to be equal, thus producing an incorrect simplification. */
4509 if (GET_CODE (new_rtx) == CLOBBER && XEXP (new_rtx, 0) == const0_rtx)
4512 if (GET_CODE (x) == SUBREG
4513 && (GET_CODE (new_rtx) == CONST_INT
4514 || GET_CODE (new_rtx) == CONST_DOUBLE))
4516 enum machine_mode mode = GET_MODE (x);
4518 x = simplify_subreg (GET_MODE (x), new_rtx,
4519 GET_MODE (SUBREG_REG (x)),
4522 x = gen_rtx_CLOBBER (mode, const0_rtx);
4524 else if (GET_CODE (new_rtx) == CONST_INT
4525 && GET_CODE (x) == ZERO_EXTEND)
4527 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
4528 new_rtx, GET_MODE (XEXP (x, 0)));
4532 SUBST (XEXP (x, i), new_rtx);
4537 /* Check if we are loading something from the constant pool via float
4538 extension; in this case we would undo compress_float_constant
4539 optimization and degenerate constant load to an immediate value. */
4540 if (GET_CODE (x) == FLOAT_EXTEND
4541 && MEM_P (XEXP (x, 0))
4542 && MEM_READONLY_P (XEXP (x, 0)))
4544 rtx tmp = avoid_constant_pool_reference (x);
4549 /* Try to simplify X. If the simplification changed the code, it is likely
4550 that further simplification will help, so loop, but limit the number
4551 of repetitions that will be performed. */
4553 for (i = 0; i < 4; i++)
4555 /* If X is sufficiently simple, don't bother trying to do anything
4557 if (code != CONST_INT && code != REG && code != CLOBBER)
4558 x = combine_simplify_rtx (x, op0_mode, in_dest);
4560 if (GET_CODE (x) == code)
4563 code = GET_CODE (x);
4565 /* We no longer know the original mode of operand 0 since we
4566 have changed the form of X) */
4567 op0_mode = VOIDmode;
4573 /* Simplify X, a piece of RTL. We just operate on the expression at the
4574 outer level; call `subst' to simplify recursively. Return the new
4577 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
4578 if we are inside a SET_DEST. */
4581 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest)
4583 enum rtx_code code = GET_CODE (x);
4584 enum machine_mode mode = GET_MODE (x);
4588 /* If this is a commutative operation, put a constant last and a complex
4589 expression first. We don't need to do this for comparisons here. */
4590 if (COMMUTATIVE_ARITH_P (x)
4591 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
4594 SUBST (XEXP (x, 0), XEXP (x, 1));
4595 SUBST (XEXP (x, 1), temp);
4598 /* If this is a simple operation applied to an IF_THEN_ELSE, try
4599 applying it to the arms of the IF_THEN_ELSE. This often simplifies
4600 things. Check for cases where both arms are testing the same
4603 Don't do anything if all operands are very simple. */
4606 && ((!OBJECT_P (XEXP (x, 0))
4607 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4608 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
4609 || (!OBJECT_P (XEXP (x, 1))
4610 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
4611 && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
4613 && (!OBJECT_P (XEXP (x, 0))
4614 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4615 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
4617 rtx cond, true_rtx, false_rtx;
4619 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
4621 /* If everything is a comparison, what we have is highly unlikely
4622 to be simpler, so don't use it. */
4623 && ! (COMPARISON_P (x)
4624 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
4626 rtx cop1 = const0_rtx;
4627 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
4629 if (cond_code == NE && COMPARISON_P (cond))
4632 /* Simplify the alternative arms; this may collapse the true and
4633 false arms to store-flag values. Be careful to use copy_rtx
4634 here since true_rtx or false_rtx might share RTL with x as a
4635 result of the if_then_else_cond call above. */
4636 true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0);
4637 false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0);
4639 /* If true_rtx and false_rtx are not general_operands, an if_then_else
4640 is unlikely to be simpler. */
4641 if (general_operand (true_rtx, VOIDmode)
4642 && general_operand (false_rtx, VOIDmode))
4644 enum rtx_code reversed;
4646 /* Restarting if we generate a store-flag expression will cause
4647 us to loop. Just drop through in this case. */
4649 /* If the result values are STORE_FLAG_VALUE and zero, we can
4650 just make the comparison operation. */
4651 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
4652 x = simplify_gen_relational (cond_code, mode, VOIDmode,
4654 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
4655 && ((reversed = reversed_comparison_code_parts
4656 (cond_code, cond, cop1, NULL))
4658 x = simplify_gen_relational (reversed, mode, VOIDmode,
4661 /* Likewise, we can make the negate of a comparison operation
4662 if the result values are - STORE_FLAG_VALUE and zero. */
4663 else if (GET_CODE (true_rtx) == CONST_INT
4664 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
4665 && false_rtx == const0_rtx)
4666 x = simplify_gen_unary (NEG, mode,
4667 simplify_gen_relational (cond_code,
4671 else if (GET_CODE (false_rtx) == CONST_INT
4672 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
4673 && true_rtx == const0_rtx
4674 && ((reversed = reversed_comparison_code_parts
4675 (cond_code, cond, cop1, NULL))
4677 x = simplify_gen_unary (NEG, mode,
4678 simplify_gen_relational (reversed,
4683 return gen_rtx_IF_THEN_ELSE (mode,
4684 simplify_gen_relational (cond_code,
4689 true_rtx, false_rtx);
4691 code = GET_CODE (x);
4692 op0_mode = VOIDmode;
4697 /* Try to fold this expression in case we have constants that weren't
4700 switch (GET_RTX_CLASS (code))
4703 if (op0_mode == VOIDmode)
4704 op0_mode = GET_MODE (XEXP (x, 0));
4705 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
4708 case RTX_COMM_COMPARE:
4710 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
4711 if (cmp_mode == VOIDmode)
4713 cmp_mode = GET_MODE (XEXP (x, 1));
4714 if (cmp_mode == VOIDmode)
4715 cmp_mode = op0_mode;
4717 temp = simplify_relational_operation (code, mode, cmp_mode,
4718 XEXP (x, 0), XEXP (x, 1));
4721 case RTX_COMM_ARITH:
4723 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
4725 case RTX_BITFIELD_OPS:
4727 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
4728 XEXP (x, 1), XEXP (x, 2));
4737 code = GET_CODE (temp);
4738 op0_mode = VOIDmode;
4739 mode = GET_MODE (temp);
4742 /* First see if we can apply the inverse distributive law. */
4743 if (code == PLUS || code == MINUS
4744 || code == AND || code == IOR || code == XOR)
4746 x = apply_distributive_law (x);
4747 code = GET_CODE (x);
4748 op0_mode = VOIDmode;
4751 /* If CODE is an associative operation not otherwise handled, see if we
4752 can associate some operands. This can win if they are constants or
4753 if they are logically related (i.e. (a & b) & a). */
4754 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
4755 || code == AND || code == IOR || code == XOR
4756 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
4757 && ((INTEGRAL_MODE_P (mode) && code != DIV)
4758 || (flag_associative_math && FLOAT_MODE_P (mode))))
4760 if (GET_CODE (XEXP (x, 0)) == code)
4762 rtx other = XEXP (XEXP (x, 0), 0);
4763 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
4764 rtx inner_op1 = XEXP (x, 1);
4767 /* Make sure we pass the constant operand if any as the second
4768 one if this is a commutative operation. */
4769 if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
4771 rtx tem = inner_op0;
4772 inner_op0 = inner_op1;
4775 inner = simplify_binary_operation (code == MINUS ? PLUS
4776 : code == DIV ? MULT
4778 mode, inner_op0, inner_op1);
4780 /* For commutative operations, try the other pair if that one
4782 if (inner == 0 && COMMUTATIVE_ARITH_P (x))
4784 other = XEXP (XEXP (x, 0), 1);
4785 inner = simplify_binary_operation (code, mode,
4786 XEXP (XEXP (x, 0), 0),
4791 return simplify_gen_binary (code, mode, other, inner);
4795 /* A little bit of algebraic simplification here. */
4799 /* Ensure that our address has any ASHIFTs converted to MULT in case
4800 address-recognizing predicates are called later. */
4801 temp = make_compound_operation (XEXP (x, 0), MEM);
4802 SUBST (XEXP (x, 0), temp);
4806 if (op0_mode == VOIDmode)
4807 op0_mode = GET_MODE (SUBREG_REG (x));
4809 /* See if this can be moved to simplify_subreg. */
4810 if (CONSTANT_P (SUBREG_REG (x))
4811 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
4812 /* Don't call gen_lowpart if the inner mode
4813 is VOIDmode and we cannot simplify it, as SUBREG without
4814 inner mode is invalid. */
4815 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
4816 || gen_lowpart_common (mode, SUBREG_REG (x))))
4817 return gen_lowpart (mode, SUBREG_REG (x));
4819 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
4823 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
4829 /* Don't change the mode of the MEM if that would change the meaning
4831 if (MEM_P (SUBREG_REG (x))
4832 && (MEM_VOLATILE_P (SUBREG_REG (x))
4833 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
4834 return gen_rtx_CLOBBER (mode, const0_rtx);
4836 /* Note that we cannot do any narrowing for non-constants since
4837 we might have been counting on using the fact that some bits were
4838 zero. We now do this in the SET. */
4843 temp = expand_compound_operation (XEXP (x, 0));
4845 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4846 replaced by (lshiftrt X C). This will convert
4847 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
4849 if (GET_CODE (temp) == ASHIFTRT
4850 && GET_CODE (XEXP (temp, 1)) == CONST_INT
4851 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
4852 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
4853 INTVAL (XEXP (temp, 1)));
4855 /* If X has only a single bit that might be nonzero, say, bit I, convert
4856 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4857 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4858 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4859 or a SUBREG of one since we'd be making the expression more
4860 complex if it was just a register. */
4863 && ! (GET_CODE (temp) == SUBREG
4864 && REG_P (SUBREG_REG (temp)))
4865 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
4867 rtx temp1 = simplify_shift_const
4868 (NULL_RTX, ASHIFTRT, mode,
4869 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
4870 GET_MODE_BITSIZE (mode) - 1 - i),
4871 GET_MODE_BITSIZE (mode) - 1 - i);
4873 /* If all we did was surround TEMP with the two shifts, we
4874 haven't improved anything, so don't use it. Otherwise,
4875 we are better off with TEMP1. */
4876 if (GET_CODE (temp1) != ASHIFTRT
4877 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
4878 || XEXP (XEXP (temp1, 0), 0) != temp)
4884 /* We can't handle truncation to a partial integer mode here
4885 because we don't know the real bitsize of the partial
4887 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
4890 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4891 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4892 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4894 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
4895 GET_MODE_MASK (mode), 0));
4897 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
4898 whose value is a comparison can be replaced with a subreg if
4899 STORE_FLAG_VALUE permits. */
4900 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4901 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
4902 && (temp = get_last_value (XEXP (x, 0)))
4903 && COMPARISON_P (temp))
4904 return gen_lowpart (mode, XEXP (x, 0));
4909 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4910 using cc0, in which case we want to leave it as a COMPARE
4911 so we can distinguish it from a register-register-copy. */
4912 if (XEXP (x, 1) == const0_rtx)
4915 /* x - 0 is the same as x unless x's mode has signed zeros and
4916 allows rounding towards -infinity. Under those conditions,
4918 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x, 0)))
4919 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x, 0))))
4920 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4926 /* (const (const X)) can become (const X). Do it this way rather than
4927 returning the inner CONST since CONST can be shared with a
4929 if (GET_CODE (XEXP (x, 0)) == CONST)
4930 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4935 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4936 can add in an offset. find_split_point will split this address up
4937 again if it doesn't match. */
4938 if (GET_CODE (XEXP (x, 0)) == HIGH
4939 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4945 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4946 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4947 bit-field and can be replaced by either a sign_extend or a
4948 sign_extract. The `and' may be a zero_extend and the two
4949 <c>, -<c> constants may be reversed. */
4950 if (GET_CODE (XEXP (x, 0)) == XOR
4951 && GET_CODE (XEXP (x, 1)) == CONST_INT
4952 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4953 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
4954 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4955 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4956 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4957 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4958 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4959 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4960 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4961 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4962 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4963 == (unsigned int) i + 1))))
4964 return simplify_shift_const
4965 (NULL_RTX, ASHIFTRT, mode,
4966 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4967 XEXP (XEXP (XEXP (x, 0), 0), 0),
4968 GET_MODE_BITSIZE (mode) - (i + 1)),
4969 GET_MODE_BITSIZE (mode) - (i + 1));
4971 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4972 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4973 the bitsize of the mode - 1. This allows simplification of
4974 "a = (b & 8) == 0;" */
4975 if (XEXP (x, 1) == constm1_rtx
4976 && !REG_P (XEXP (x, 0))
4977 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4978 && REG_P (SUBREG_REG (XEXP (x, 0))))
4979 && nonzero_bits (XEXP (x, 0), mode) == 1)
4980 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4981 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4982 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
4983 GET_MODE_BITSIZE (mode) - 1),
4984 GET_MODE_BITSIZE (mode) - 1);
4986 /* If we are adding two things that have no bits in common, convert
4987 the addition into an IOR. This will often be further simplified,
4988 for example in cases like ((a & 1) + (a & 2)), which can
4991 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4992 && (nonzero_bits (XEXP (x, 0), mode)
4993 & nonzero_bits (XEXP (x, 1), mode)) == 0)
4995 /* Try to simplify the expression further. */
4996 rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4997 temp = combine_simplify_rtx (tor, mode, in_dest);
4999 /* If we could, great. If not, do not go ahead with the IOR
5000 replacement, since PLUS appears in many special purpose
5001 address arithmetic instructions. */
5002 if (GET_CODE (temp) != CLOBBER && temp != tor)
5008 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5009 (and <foo> (const_int pow2-1)) */
5010 if (GET_CODE (XEXP (x, 1)) == AND
5011 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
5012 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
5013 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
5014 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
5015 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
5019 /* If we have (mult (plus A B) C), apply the distributive law and then
5020 the inverse distributive law to see if things simplify. This
5021 occurs mostly in addresses, often when unrolling loops. */
5023 if (GET_CODE (XEXP (x, 0)) == PLUS)
5025 rtx result = distribute_and_simplify_rtx (x, 0);
5030 /* Try simplify a*(b/c) as (a*b)/c. */
5031 if (FLOAT_MODE_P (mode) && flag_associative_math
5032 && GET_CODE (XEXP (x, 0)) == DIV)
5034 rtx tem = simplify_binary_operation (MULT, mode,
5035 XEXP (XEXP (x, 0), 0),
5038 return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
5043 /* If this is a divide by a power of two, treat it as a shift if
5044 its first operand is a shift. */
5045 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5046 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
5047 && (GET_CODE (XEXP (x, 0)) == ASHIFT
5048 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
5049 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
5050 || GET_CODE (XEXP (x, 0)) == ROTATE
5051 || GET_CODE (XEXP (x, 0)) == ROTATERT))
5052 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
5056 case GT: case GTU: case GE: case GEU:
5057 case LT: case LTU: case LE: case LEU:
5058 case UNEQ: case LTGT:
5059 case UNGT: case UNGE:
5060 case UNLT: case UNLE:
5061 case UNORDERED: case ORDERED:
5062 /* If the first operand is a condition code, we can't do anything
5064 if (GET_CODE (XEXP (x, 0)) == COMPARE
5065 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
5066 && ! CC0_P (XEXP (x, 0))))
5068 rtx op0 = XEXP (x, 0);
5069 rtx op1 = XEXP (x, 1);
5070 enum rtx_code new_code;
5072 if (GET_CODE (op0) == COMPARE)
5073 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
5075 /* Simplify our comparison, if possible. */
5076 new_code = simplify_comparison (code, &op0, &op1);
5078 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5079 if only the low-order bit is possibly nonzero in X (such as when
5080 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5081 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5082 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5085 Remove any ZERO_EXTRACT we made when thinking this was a
5086 comparison. It may now be simpler to use, e.g., an AND. If a
5087 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5088 the call to make_compound_operation in the SET case. */
5090 if (STORE_FLAG_VALUE == 1
5091 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5092 && op1 == const0_rtx
5093 && mode == GET_MODE (op0)
5094 && nonzero_bits (op0, mode) == 1)
5095 return gen_lowpart (mode,
5096 expand_compound_operation (op0));
5098 else if (STORE_FLAG_VALUE == 1
5099 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5100 && op1 == const0_rtx
5101 && mode == GET_MODE (op0)
5102 && (num_sign_bit_copies (op0, mode)
5103 == GET_MODE_BITSIZE (mode)))
5105 op0 = expand_compound_operation (op0);
5106 return simplify_gen_unary (NEG, mode,
5107 gen_lowpart (mode, op0),
5111 else if (STORE_FLAG_VALUE == 1
5112 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5113 && op1 == const0_rtx
5114 && mode == GET_MODE (op0)
5115 && nonzero_bits (op0, mode) == 1)
5117 op0 = expand_compound_operation (op0);
5118 return simplify_gen_binary (XOR, mode,
5119 gen_lowpart (mode, op0),
5123 else if (STORE_FLAG_VALUE == 1
5124 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5125 && op1 == const0_rtx
5126 && mode == GET_MODE (op0)
5127 && (num_sign_bit_copies (op0, mode)
5128 == GET_MODE_BITSIZE (mode)))
5130 op0 = expand_compound_operation (op0);
5131 return plus_constant (gen_lowpart (mode, op0), 1);
5134 /* If STORE_FLAG_VALUE is -1, we have cases similar to
5136 if (STORE_FLAG_VALUE == -1
5137 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5138 && op1 == const0_rtx
5139 && (num_sign_bit_copies (op0, mode)
5140 == GET_MODE_BITSIZE (mode)))
5141 return gen_lowpart (mode,
5142 expand_compound_operation (op0));
5144 else if (STORE_FLAG_VALUE == -1
5145 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5146 && op1 == const0_rtx
5147 && mode == GET_MODE (op0)
5148 && nonzero_bits (op0, mode) == 1)
5150 op0 = expand_compound_operation (op0);
5151 return simplify_gen_unary (NEG, mode,
5152 gen_lowpart (mode, op0),
5156 else if (STORE_FLAG_VALUE == -1
5157 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5158 && op1 == const0_rtx
5159 && mode == GET_MODE (op0)
5160 && (num_sign_bit_copies (op0, mode)
5161 == GET_MODE_BITSIZE (mode)))
5163 op0 = expand_compound_operation (op0);
5164 return simplify_gen_unary (NOT, mode,
5165 gen_lowpart (mode, op0),
5169 /* If X is 0/1, (eq X 0) is X-1. */
5170 else if (STORE_FLAG_VALUE == -1
5171 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5172 && op1 == const0_rtx
5173 && mode == GET_MODE (op0)
5174 && nonzero_bits (op0, mode) == 1)
5176 op0 = expand_compound_operation (op0);
5177 return plus_constant (gen_lowpart (mode, op0), -1);
5180 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5181 one bit that might be nonzero, we can convert (ne x 0) to
5182 (ashift x c) where C puts the bit in the sign bit. Remove any
5183 AND with STORE_FLAG_VALUE when we are done, since we are only
5184 going to test the sign bit. */
5185 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5186 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5187 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5188 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5189 && op1 == const0_rtx
5190 && mode == GET_MODE (op0)
5191 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
5193 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
5194 expand_compound_operation (op0),
5195 GET_MODE_BITSIZE (mode) - 1 - i);
5196 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
5202 /* If the code changed, return a whole new comparison. */
5203 if (new_code != code)
5204 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
5206 /* Otherwise, keep this operation, but maybe change its operands.
5207 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
5208 SUBST (XEXP (x, 0), op0);
5209 SUBST (XEXP (x, 1), op1);
5214 return simplify_if_then_else (x);
5220 /* If we are processing SET_DEST, we are done. */
5224 return expand_compound_operation (x);
5227 return simplify_set (x);
5231 return simplify_logical (x);
5238 /* If this is a shift by a constant amount, simplify it. */
5239 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
5240 return simplify_shift_const (x, code, mode, XEXP (x, 0),
5241 INTVAL (XEXP (x, 1)));
5243 else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
5245 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
5247 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
5259 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
5262 simplify_if_then_else (rtx x)
5264 enum machine_mode mode = GET_MODE (x);
5265 rtx cond = XEXP (x, 0);
5266 rtx true_rtx = XEXP (x, 1);
5267 rtx false_rtx = XEXP (x, 2);
5268 enum rtx_code true_code = GET_CODE (cond);
5269 int comparison_p = COMPARISON_P (cond);
5272 enum rtx_code false_code;
5275 /* Simplify storing of the truth value. */
5276 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
5277 return simplify_gen_relational (true_code, mode, VOIDmode,
5278 XEXP (cond, 0), XEXP (cond, 1));
5280 /* Also when the truth value has to be reversed. */
5282 && true_rtx == const0_rtx && false_rtx == const_true_rtx
5283 && (reversed = reversed_comparison (cond, mode)))
5286 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
5287 in it is being compared against certain values. Get the true and false
5288 comparisons and see if that says anything about the value of each arm. */
5291 && ((false_code = reversed_comparison_code (cond, NULL))
5293 && REG_P (XEXP (cond, 0)))
5296 rtx from = XEXP (cond, 0);
5297 rtx true_val = XEXP (cond, 1);
5298 rtx false_val = true_val;
5301 /* If FALSE_CODE is EQ, swap the codes and arms. */
5303 if (false_code == EQ)
5305 swapped = 1, true_code = EQ, false_code = NE;
5306 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5309 /* If we are comparing against zero and the expression being tested has
5310 only a single bit that might be nonzero, that is its value when it is
5311 not equal to zero. Similarly if it is known to be -1 or 0. */
5313 if (true_code == EQ && true_val == const0_rtx
5314 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
5317 false_val = GEN_INT (trunc_int_for_mode (nzb, GET_MODE (from)));
5319 else if (true_code == EQ && true_val == const0_rtx
5320 && (num_sign_bit_copies (from, GET_MODE (from))
5321 == GET_MODE_BITSIZE (GET_MODE (from))))
5324 false_val = constm1_rtx;
5327 /* Now simplify an arm if we know the value of the register in the
5328 branch and it is used in the arm. Be careful due to the potential
5329 of locally-shared RTL. */
5331 if (reg_mentioned_p (from, true_rtx))
5332 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
5334 pc_rtx, pc_rtx, 0, 0);
5335 if (reg_mentioned_p (from, false_rtx))
5336 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
5338 pc_rtx, pc_rtx, 0, 0);
5340 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
5341 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
5343 true_rtx = XEXP (x, 1);
5344 false_rtx = XEXP (x, 2);
5345 true_code = GET_CODE (cond);
5348 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
5349 reversed, do so to avoid needing two sets of patterns for
5350 subtract-and-branch insns. Similarly if we have a constant in the true
5351 arm, the false arm is the same as the first operand of the comparison, or
5352 the false arm is more complicated than the true arm. */
5355 && reversed_comparison_code (cond, NULL) != UNKNOWN
5356 && (true_rtx == pc_rtx
5357 || (CONSTANT_P (true_rtx)
5358 && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx)
5359 || true_rtx == const0_rtx
5360 || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
5361 || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
5362 && !OBJECT_P (false_rtx))
5363 || reg_mentioned_p (true_rtx, false_rtx)
5364 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
5366 true_code = reversed_comparison_code (cond, NULL);
5367 SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
5368 SUBST (XEXP (x, 1), false_rtx);
5369 SUBST (XEXP (x, 2), true_rtx);
5371 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5374 /* It is possible that the conditional has been simplified out. */
5375 true_code = GET_CODE (cond);
5376 comparison_p = COMPARISON_P (cond);
5379 /* If the two arms are identical, we don't need the comparison. */
5381 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
5384 /* Convert a == b ? b : a to "a". */
5385 if (true_code == EQ && ! side_effects_p (cond)
5386 && !HONOR_NANS (mode)
5387 && rtx_equal_p (XEXP (cond, 0), false_rtx)
5388 && rtx_equal_p (XEXP (cond, 1), true_rtx))
5390 else if (true_code == NE && ! side_effects_p (cond)
5391 && !HONOR_NANS (mode)
5392 && rtx_equal_p (XEXP (cond, 0), true_rtx)
5393 && rtx_equal_p (XEXP (cond, 1), false_rtx))
5396 /* Look for cases where we have (abs x) or (neg (abs X)). */
5398 if (GET_MODE_CLASS (mode) == MODE_INT
5400 && XEXP (cond, 1) == const0_rtx
5401 && GET_CODE (false_rtx) == NEG
5402 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
5403 && rtx_equal_p (true_rtx, XEXP (cond, 0))
5404 && ! side_effects_p (true_rtx))
5409 return simplify_gen_unary (ABS, mode, true_rtx, mode);
5413 simplify_gen_unary (NEG, mode,
5414 simplify_gen_unary (ABS, mode, true_rtx, mode),
5420 /* Look for MIN or MAX. */
5422 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
5424 && rtx_equal_p (XEXP (cond, 0), true_rtx)
5425 && rtx_equal_p (XEXP (cond, 1), false_rtx)
5426 && ! side_effects_p (cond))
5431 return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
5434 return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
5437 return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
5440 return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
5445 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
5446 second operand is zero, this can be done as (OP Z (mult COND C2)) where
5447 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
5448 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
5449 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
5450 neither 1 or -1, but it isn't worth checking for. */
5452 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
5454 && GET_MODE_CLASS (mode) == MODE_INT
5455 && ! side_effects_p (x))
5457 rtx t = make_compound_operation (true_rtx, SET);
5458 rtx f = make_compound_operation (false_rtx, SET);
5459 rtx cond_op0 = XEXP (cond, 0);
5460 rtx cond_op1 = XEXP (cond, 1);
5461 enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
5462 enum machine_mode m = mode;
5463 rtx z = 0, c1 = NULL_RTX;
5465 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
5466 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
5467 || GET_CODE (t) == ASHIFT
5468 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
5469 && rtx_equal_p (XEXP (t, 0), f))
5470 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
5472 /* If an identity-zero op is commutative, check whether there
5473 would be a match if we swapped the operands. */
5474 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
5475 || GET_CODE (t) == XOR)
5476 && rtx_equal_p (XEXP (t, 1), f))
5477 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
5478 else if (GET_CODE (t) == SIGN_EXTEND
5479 && (GET_CODE (XEXP (t, 0)) == PLUS
5480 || GET_CODE (XEXP (t, 0)) == MINUS
5481 || GET_CODE (XEXP (t, 0)) == IOR
5482 || GET_CODE (XEXP (t, 0)) == XOR
5483 || GET_CODE (XEXP (t, 0)) == ASHIFT
5484 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5485 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5486 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5487 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5488 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5489 && (num_sign_bit_copies (f, GET_MODE (f))
5491 (GET_MODE_BITSIZE (mode)
5492 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
5494 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5495 extend_op = SIGN_EXTEND;
5496 m = GET_MODE (XEXP (t, 0));
5498 else if (GET_CODE (t) == SIGN_EXTEND
5499 && (GET_CODE (XEXP (t, 0)) == PLUS
5500 || GET_CODE (XEXP (t, 0)) == IOR
5501 || GET_CODE (XEXP (t, 0)) == XOR)
5502 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5503 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5504 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5505 && (num_sign_bit_copies (f, GET_MODE (f))
5507 (GET_MODE_BITSIZE (mode)
5508 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
5510 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5511 extend_op = SIGN_EXTEND;
5512 m = GET_MODE (XEXP (t, 0));
5514 else if (GET_CODE (t) == ZERO_EXTEND
5515 && (GET_CODE (XEXP (t, 0)) == PLUS
5516 || GET_CODE (XEXP (t, 0)) == MINUS
5517 || GET_CODE (XEXP (t, 0)) == IOR
5518 || GET_CODE (XEXP (t, 0)) == XOR
5519 || GET_CODE (XEXP (t, 0)) == ASHIFT
5520 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5521 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5522 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5523 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5524 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5525 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5526 && ((nonzero_bits (f, GET_MODE (f))
5527 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
5530 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5531 extend_op = ZERO_EXTEND;
5532 m = GET_MODE (XEXP (t, 0));
5534 else if (GET_CODE (t) == ZERO_EXTEND
5535 && (GET_CODE (XEXP (t, 0)) == PLUS
5536 || GET_CODE (XEXP (t, 0)) == IOR
5537 || GET_CODE (XEXP (t, 0)) == XOR)
5538 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5539 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5540 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5541 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5542 && ((nonzero_bits (f, GET_MODE (f))
5543 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
5546 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5547 extend_op = ZERO_EXTEND;
5548 m = GET_MODE (XEXP (t, 0));
5553 temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
5554 cond_op0, cond_op1),
5555 pc_rtx, pc_rtx, 0, 0);
5556 temp = simplify_gen_binary (MULT, m, temp,
5557 simplify_gen_binary (MULT, m, c1,
5559 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
5560 temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
5562 if (extend_op != UNKNOWN)
5563 temp = simplify_gen_unary (extend_op, mode, temp, m);
5569 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5570 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5571 negation of a single bit, we can convert this operation to a shift. We
5572 can actually do this more generally, but it doesn't seem worth it. */
5574 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5575 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5576 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
5577 && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
5578 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
5579 == GET_MODE_BITSIZE (mode))
5580 && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
5582 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5583 gen_lowpart (mode, XEXP (cond, 0)), i);
5585 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
5586 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5587 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5588 && GET_MODE (XEXP (cond, 0)) == mode
5589 && (INTVAL (true_rtx) & GET_MODE_MASK (mode))
5590 == nonzero_bits (XEXP (cond, 0), mode)
5591 && (i = exact_log2 (INTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
5592 return XEXP (cond, 0);
5597 /* Simplify X, a SET expression. Return the new expression. */
5600 simplify_set (rtx x)
5602 rtx src = SET_SRC (x);
5603 rtx dest = SET_DEST (x);
5604 enum machine_mode mode
5605 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
5609 /* (set (pc) (return)) gets written as (return). */
5610 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
5613 /* Now that we know for sure which bits of SRC we are using, see if we can
5614 simplify the expression for the object knowing that we only need the
5617 if (GET_MODE_CLASS (mode) == MODE_INT
5618 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5620 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, 0);
5621 SUBST (SET_SRC (x), src);
5624 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5625 the comparison result and try to simplify it unless we already have used
5626 undobuf.other_insn. */
5627 if ((GET_MODE_CLASS (mode) == MODE_CC
5628 || GET_CODE (src) == COMPARE
5630 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
5631 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
5632 && COMPARISON_P (*cc_use)
5633 && rtx_equal_p (XEXP (*cc_use, 0), dest))
5635 enum rtx_code old_code = GET_CODE (*cc_use);
5636 enum rtx_code new_code;
5638 int other_changed = 0;
5639 enum machine_mode compare_mode = GET_MODE (dest);
5641 if (GET_CODE (src) == COMPARE)
5642 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
5644 op0 = src, op1 = CONST0_RTX (GET_MODE (src));
5646 tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
5649 new_code = old_code;
5650 else if (!CONSTANT_P (tmp))
5652 new_code = GET_CODE (tmp);
5653 op0 = XEXP (tmp, 0);
5654 op1 = XEXP (tmp, 1);
5658 rtx pat = PATTERN (other_insn);
5659 undobuf.other_insn = other_insn;
5660 SUBST (*cc_use, tmp);
5662 /* Attempt to simplify CC user. */
5663 if (GET_CODE (pat) == SET)
5665 rtx new_rtx = simplify_rtx (SET_SRC (pat));
5666 if (new_rtx != NULL_RTX)
5667 SUBST (SET_SRC (pat), new_rtx);
5670 /* Convert X into a no-op move. */
5671 SUBST (SET_DEST (x), pc_rtx);
5672 SUBST (SET_SRC (x), pc_rtx);
5676 /* Simplify our comparison, if possible. */
5677 new_code = simplify_comparison (new_code, &op0, &op1);
5679 #ifdef SELECT_CC_MODE
5680 /* If this machine has CC modes other than CCmode, check to see if we
5681 need to use a different CC mode here. */
5682 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
5683 compare_mode = GET_MODE (op0);
5685 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5688 /* If the mode changed, we have to change SET_DEST, the mode in the
5689 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5690 a hard register, just build new versions with the proper mode. If it
5691 is a pseudo, we lose unless it is only time we set the pseudo, in
5692 which case we can safely change its mode. */
5693 if (compare_mode != GET_MODE (dest))
5695 if (can_change_dest_mode (dest, 0, compare_mode))
5697 unsigned int regno = REGNO (dest);
5700 if (regno < FIRST_PSEUDO_REGISTER)
5701 new_dest = gen_rtx_REG (compare_mode, regno);
5704 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
5705 new_dest = regno_reg_rtx[regno];
5708 SUBST (SET_DEST (x), new_dest);
5709 SUBST (XEXP (*cc_use, 0), new_dest);
5716 #endif /* SELECT_CC_MODE */
5718 /* If the code changed, we have to build a new comparison in
5719 undobuf.other_insn. */
5720 if (new_code != old_code)
5722 int other_changed_previously = other_changed;
5723 unsigned HOST_WIDE_INT mask;
5724 rtx old_cc_use = *cc_use;
5726 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5730 /* If the only change we made was to change an EQ into an NE or
5731 vice versa, OP0 has only one bit that might be nonzero, and OP1
5732 is zero, check if changing the user of the condition code will
5733 produce a valid insn. If it won't, we can keep the original code
5734 in that insn by surrounding our operation with an XOR. */
5736 if (((old_code == NE && new_code == EQ)
5737 || (old_code == EQ && new_code == NE))
5738 && ! other_changed_previously && op1 == const0_rtx
5739 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5740 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5742 rtx pat = PATTERN (other_insn), note = 0;
5744 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
5745 && ! check_asm_operands (pat)))
5747 *cc_use = old_cc_use;
5750 op0 = simplify_gen_binary (XOR, GET_MODE (op0),
5751 op0, GEN_INT (mask));
5757 undobuf.other_insn = other_insn;
5760 /* If we are now comparing against zero, change our source if
5761 needed. If we do not use cc0, we always have a COMPARE. */
5762 if (op1 == const0_rtx && dest == cc0_rtx)
5764 SUBST (SET_SRC (x), op0);
5770 /* Otherwise, if we didn't previously have a COMPARE in the
5771 correct mode, we need one. */
5772 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5774 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5777 else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
5779 SUBST (SET_SRC (x), op0);
5782 /* Otherwise, update the COMPARE if needed. */
5783 else if (XEXP (src, 0) != op0 || XEXP (src, 1) != op1)
5785 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5791 /* Get SET_SRC in a form where we have placed back any
5792 compound expressions. Then do the checks below. */
5793 src = make_compound_operation (src, SET);
5794 SUBST (SET_SRC (x), src);
5797 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5798 and X being a REG or (subreg (reg)), we may be able to convert this to
5799 (set (subreg:m2 x) (op)).
5801 We can always do this if M1 is narrower than M2 because that means that
5802 we only care about the low bits of the result.
5804 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5805 perform a narrower operation than requested since the high-order bits will
5806 be undefined. On machine where it is defined, this transformation is safe
5807 as long as M1 and M2 have the same number of words. */
5809 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5810 && !OBJECT_P (SUBREG_REG (src))
5811 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5813 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5814 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5815 #ifndef WORD_REGISTER_OPERATIONS
5816 && (GET_MODE_SIZE (GET_MODE (src))
5817 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5819 #ifdef CANNOT_CHANGE_MODE_CLASS
5820 && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
5821 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
5822 GET_MODE (SUBREG_REG (src)),
5826 || (GET_CODE (dest) == SUBREG
5827 && REG_P (SUBREG_REG (dest)))))
5829 SUBST (SET_DEST (x),
5830 gen_lowpart (GET_MODE (SUBREG_REG (src)),
5832 SUBST (SET_SRC (x), SUBREG_REG (src));
5834 src = SET_SRC (x), dest = SET_DEST (x);
5838 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5841 && GET_CODE (src) == SUBREG
5842 && subreg_lowpart_p (src)
5843 && (GET_MODE_BITSIZE (GET_MODE (src))
5844 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
5846 rtx inner = SUBREG_REG (src);
5847 enum machine_mode inner_mode = GET_MODE (inner);
5849 /* Here we make sure that we don't have a sign bit on. */
5850 if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
5851 && (nonzero_bits (inner, inner_mode)
5852 < ((unsigned HOST_WIDE_INT) 1
5853 << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
5855 SUBST (SET_SRC (x), inner);
5861 #ifdef LOAD_EXTEND_OP
5862 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5863 would require a paradoxical subreg. Replace the subreg with a
5864 zero_extend to avoid the reload that would otherwise be required. */
5866 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5867 && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src)))
5868 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
5869 && SUBREG_BYTE (src) == 0
5870 && (GET_MODE_SIZE (GET_MODE (src))
5871 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5872 && MEM_P (SUBREG_REG (src)))
5875 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5876 GET_MODE (src), SUBREG_REG (src)));
5882 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5883 are comparing an item known to be 0 or -1 against 0, use a logical
5884 operation instead. Check for one of the arms being an IOR of the other
5885 arm with some value. We compute three terms to be IOR'ed together. In
5886 practice, at most two will be nonzero. Then we do the IOR's. */
5888 if (GET_CODE (dest) != PC
5889 && GET_CODE (src) == IF_THEN_ELSE
5890 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5891 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5892 && XEXP (XEXP (src, 0), 1) == const0_rtx
5893 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5894 #ifdef HAVE_conditional_move
5895 && ! can_conditionally_move_p (GET_MODE (src))
5897 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5898 GET_MODE (XEXP (XEXP (src, 0), 0)))
5899 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5900 && ! side_effects_p (src))
5902 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
5903 ? XEXP (src, 1) : XEXP (src, 2));
5904 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
5905 ? XEXP (src, 2) : XEXP (src, 1));
5906 rtx term1 = const0_rtx, term2, term3;
5908 if (GET_CODE (true_rtx) == IOR
5909 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
5910 term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
5911 else if (GET_CODE (true_rtx) == IOR
5912 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
5913 term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
5914 else if (GET_CODE (false_rtx) == IOR
5915 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
5916 term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
5917 else if (GET_CODE (false_rtx) == IOR
5918 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
5919 term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
5921 term2 = simplify_gen_binary (AND, GET_MODE (src),
5922 XEXP (XEXP (src, 0), 0), true_rtx);
5923 term3 = simplify_gen_binary (AND, GET_MODE (src),
5924 simplify_gen_unary (NOT, GET_MODE (src),
5925 XEXP (XEXP (src, 0), 0),
5930 simplify_gen_binary (IOR, GET_MODE (src),
5931 simplify_gen_binary (IOR, GET_MODE (src),
5938 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5939 whole thing fail. */
5940 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5942 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5945 /* Convert this into a field assignment operation, if possible. */
5946 return make_field_assignment (x);
5949 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5953 simplify_logical (rtx x)
5955 enum machine_mode mode = GET_MODE (x);
5956 rtx op0 = XEXP (x, 0);
5957 rtx op1 = XEXP (x, 1);
5959 switch (GET_CODE (x))
5962 /* We can call simplify_and_const_int only if we don't lose
5963 any (sign) bits when converting INTVAL (op1) to
5964 "unsigned HOST_WIDE_INT". */
5965 if (GET_CODE (op1) == CONST_INT
5966 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5967 || INTVAL (op1) > 0))
5969 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5970 if (GET_CODE (x) != AND)
5977 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
5978 apply the distributive law and then the inverse distributive
5979 law to see if things simplify. */
5980 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5982 rtx result = distribute_and_simplify_rtx (x, 0);
5986 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5988 rtx result = distribute_and_simplify_rtx (x, 1);
5995 /* If we have (ior (and A B) C), apply the distributive law and then
5996 the inverse distributive law to see if things simplify. */
5998 if (GET_CODE (op0) == AND)
6000 rtx result = distribute_and_simplify_rtx (x, 0);
6005 if (GET_CODE (op1) == AND)
6007 rtx result = distribute_and_simplify_rtx (x, 1);
6020 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6021 operations" because they can be replaced with two more basic operations.
6022 ZERO_EXTEND is also considered "compound" because it can be replaced with
6023 an AND operation, which is simpler, though only one operation.
6025 The function expand_compound_operation is called with an rtx expression
6026 and will convert it to the appropriate shifts and AND operations,
6027 simplifying at each stage.
6029 The function make_compound_operation is called to convert an expression
6030 consisting of shifts and ANDs into the equivalent compound expression.
6031 It is the inverse of this function, loosely speaking. */
6034 expand_compound_operation (rtx x)
6036 unsigned HOST_WIDE_INT pos = 0, len;
6038 unsigned int modewidth;
6041 switch (GET_CODE (x))
6046 /* We can't necessarily use a const_int for a multiword mode;
6047 it depends on implicitly extending the value.
6048 Since we don't know the right way to extend it,
6049 we can't tell whether the implicit way is right.
6051 Even for a mode that is no wider than a const_int,
6052 we can't win, because we need to sign extend one of its bits through
6053 the rest of it, and we don't know which bit. */
6054 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
6057 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6058 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6059 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6060 reloaded. If not for that, MEM's would very rarely be safe.
6062 Reject MODEs bigger than a word, because we might not be able
6063 to reference a two-register group starting with an arbitrary register
6064 (and currently gen_lowpart might crash for a SUBREG). */
6066 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
6069 /* Reject MODEs that aren't scalar integers because turning vector
6070 or complex modes into shifts causes problems. */
6072 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6075 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
6076 /* If the inner object has VOIDmode (the only way this can happen
6077 is if it is an ASM_OPERANDS), we can't do anything since we don't
6078 know how much masking to do. */
6087 /* ... fall through ... */
6090 /* If the operand is a CLOBBER, just return it. */
6091 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
6094 if (GET_CODE (XEXP (x, 1)) != CONST_INT
6095 || GET_CODE (XEXP (x, 2)) != CONST_INT
6096 || GET_MODE (XEXP (x, 0)) == VOIDmode)
6099 /* Reject MODEs that aren't scalar integers because turning vector
6100 or complex modes into shifts causes problems. */
6102 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6105 len = INTVAL (XEXP (x, 1));
6106 pos = INTVAL (XEXP (x, 2));
6108 /* This should stay within the object being extracted, fail otherwise. */
6109 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
6112 if (BITS_BIG_ENDIAN)
6113 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
6120 /* Convert sign extension to zero extension, if we know that the high
6121 bit is not set, as this is easier to optimize. It will be converted
6122 back to cheaper alternative in make_extraction. */
6123 if (GET_CODE (x) == SIGN_EXTEND
6124 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6125 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6126 & ~(((unsigned HOST_WIDE_INT)
6127 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
6131 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
6132 rtx temp2 = expand_compound_operation (temp);
6134 /* Make sure this is a profitable operation. */
6135 if (rtx_cost (x, SET, optimize_this_for_speed_p)
6136 > rtx_cost (temp2, SET, optimize_this_for_speed_p))
6138 else if (rtx_cost (x, SET, optimize_this_for_speed_p)
6139 > rtx_cost (temp, SET, optimize_this_for_speed_p))
6145 /* We can optimize some special cases of ZERO_EXTEND. */
6146 if (GET_CODE (x) == ZERO_EXTEND)
6148 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6149 know that the last value didn't have any inappropriate bits
6151 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6152 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6153 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6154 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
6155 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6156 return XEXP (XEXP (x, 0), 0);
6158 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6159 if (GET_CODE (XEXP (x, 0)) == SUBREG
6160 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6161 && subreg_lowpart_p (XEXP (x, 0))
6162 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6163 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
6164 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6165 return SUBREG_REG (XEXP (x, 0));
6167 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6168 is a comparison and STORE_FLAG_VALUE permits. This is like
6169 the first case, but it works even when GET_MODE (x) is larger
6170 than HOST_WIDE_INT. */
6171 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6172 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6173 && COMPARISON_P (XEXP (XEXP (x, 0), 0))
6174 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6175 <= HOST_BITS_PER_WIDE_INT)
6176 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
6177 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6178 return XEXP (XEXP (x, 0), 0);
6180 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6181 if (GET_CODE (XEXP (x, 0)) == SUBREG
6182 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6183 && subreg_lowpart_p (XEXP (x, 0))
6184 && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
6185 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6186 <= HOST_BITS_PER_WIDE_INT)
6187 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
6188 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6189 return SUBREG_REG (XEXP (x, 0));
6193 /* If we reach here, we want to return a pair of shifts. The inner
6194 shift is a left shift of BITSIZE - POS - LEN bits. The outer
6195 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
6196 logical depending on the value of UNSIGNEDP.
6198 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6199 converted into an AND of a shift.
6201 We must check for the case where the left shift would have a negative
6202 count. This can happen in a case like (x >> 31) & 255 on machines
6203 that can't shift by a constant. On those machines, we would first
6204 combine the shift with the AND to produce a variable-position
6205 extraction. Then the constant of 31 would be substituted in to produce
6206 a such a position. */
6208 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
6209 if (modewidth + len >= pos)
6211 enum machine_mode mode = GET_MODE (x);
6212 tem = gen_lowpart (mode, XEXP (x, 0));
6213 if (!tem || GET_CODE (tem) == CLOBBER)
6215 tem = simplify_shift_const (NULL_RTX, ASHIFT, mode,
6216 tem, modewidth - pos - len);
6217 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
6218 mode, tem, modewidth - len);
6220 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
6221 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
6222 simplify_shift_const (NULL_RTX, LSHIFTRT,
6225 ((HOST_WIDE_INT) 1 << len) - 1);
6227 /* Any other cases we can't handle. */
6230 /* If we couldn't do this for some reason, return the original
6232 if (GET_CODE (tem) == CLOBBER)
6238 /* X is a SET which contains an assignment of one object into
6239 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6240 or certain SUBREGS). If possible, convert it into a series of
6243 We half-heartedly support variable positions, but do not at all
6244 support variable lengths. */
6247 expand_field_assignment (const_rtx x)
6250 rtx pos; /* Always counts from low bit. */
6252 rtx mask, cleared, masked;
6253 enum machine_mode compute_mode;
6255 /* Loop until we find something we can't simplify. */
6258 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
6259 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
6261 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
6262 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
6263 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
6265 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
6266 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
6268 inner = XEXP (SET_DEST (x), 0);
6269 len = INTVAL (XEXP (SET_DEST (x), 1));
6270 pos = XEXP (SET_DEST (x), 2);
6272 /* A constant position should stay within the width of INNER. */
6273 if (GET_CODE (pos) == CONST_INT
6274 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
6277 if (BITS_BIG_ENDIAN)
6279 if (GET_CODE (pos) == CONST_INT)
6280 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
6282 else if (GET_CODE (pos) == MINUS
6283 && GET_CODE (XEXP (pos, 1)) == CONST_INT
6284 && (INTVAL (XEXP (pos, 1))
6285 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
6286 /* If position is ADJUST - X, new position is X. */
6287 pos = XEXP (pos, 0);
6289 pos = simplify_gen_binary (MINUS, GET_MODE (pos),
6290 GEN_INT (GET_MODE_BITSIZE (
6297 /* A SUBREG between two modes that occupy the same numbers of words
6298 can be done by moving the SUBREG to the source. */
6299 else if (GET_CODE (SET_DEST (x)) == SUBREG
6300 /* We need SUBREGs to compute nonzero_bits properly. */
6301 && nonzero_sign_valid
6302 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
6303 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
6304 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
6305 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
6307 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
6309 (GET_MODE (SUBREG_REG (SET_DEST (x))),
6316 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6317 inner = SUBREG_REG (inner);
6319 compute_mode = GET_MODE (inner);
6321 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6322 if (! SCALAR_INT_MODE_P (compute_mode))
6324 enum machine_mode imode;
6326 /* Don't do anything for vector or complex integral types. */
6327 if (! FLOAT_MODE_P (compute_mode))
6330 /* Try to find an integral mode to pun with. */
6331 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
6332 if (imode == BLKmode)
6335 compute_mode = imode;
6336 inner = gen_lowpart (imode, inner);
6339 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6340 if (len >= HOST_BITS_PER_WIDE_INT)
6343 /* Now compute the equivalent expression. Make a copy of INNER
6344 for the SET_DEST in case it is a MEM into which we will substitute;
6345 we don't want shared RTL in that case. */
6346 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
6347 cleared = simplify_gen_binary (AND, compute_mode,
6348 simplify_gen_unary (NOT, compute_mode,
6349 simplify_gen_binary (ASHIFT,
6354 masked = simplify_gen_binary (ASHIFT, compute_mode,
6355 simplify_gen_binary (
6357 gen_lowpart (compute_mode, SET_SRC (x)),
6361 x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
6362 simplify_gen_binary (IOR, compute_mode,
6369 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6370 it is an RTX that represents a variable starting position; otherwise,
6371 POS is the (constant) starting bit position (counted from the LSB).
6373 UNSIGNEDP is nonzero for an unsigned reference and zero for a
6376 IN_DEST is nonzero if this is a reference in the destination of a
6377 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6378 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6381 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
6382 ZERO_EXTRACT should be built even for bits starting at bit 0.
6384 MODE is the desired mode of the result (if IN_DEST == 0).
6386 The result is an RTX for the extraction or NULL_RTX if the target
6390 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
6391 rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
6392 int in_dest, int in_compare)
6394 /* This mode describes the size of the storage area
6395 to fetch the overall value from. Within that, we
6396 ignore the POS lowest bits, etc. */
6397 enum machine_mode is_mode = GET_MODE (inner);
6398 enum machine_mode inner_mode;
6399 enum machine_mode wanted_inner_mode;
6400 enum machine_mode wanted_inner_reg_mode = word_mode;
6401 enum machine_mode pos_mode = word_mode;
6402 enum machine_mode extraction_mode = word_mode;
6403 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
6405 rtx orig_pos_rtx = pos_rtx;
6406 HOST_WIDE_INT orig_pos;
6408 if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6410 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
6411 consider just the QI as the memory to extract from.
6412 The subreg adds or removes high bits; its mode is
6413 irrelevant to the meaning of this extraction,
6414 since POS and LEN count from the lsb. */
6415 if (MEM_P (SUBREG_REG (inner)))
6416 is_mode = GET_MODE (SUBREG_REG (inner));
6417 inner = SUBREG_REG (inner);
6419 else if (GET_CODE (inner) == ASHIFT
6420 && GET_CODE (XEXP (inner, 1)) == CONST_INT
6421 && pos_rtx == 0 && pos == 0
6422 && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1)))
6424 /* We're extracting the least significant bits of an rtx
6425 (ashift X (const_int C)), where LEN > C. Extract the
6426 least significant (LEN - C) bits of X, giving an rtx
6427 whose mode is MODE, then shift it left C times. */
6428 new_rtx = make_extraction (mode, XEXP (inner, 0),
6429 0, 0, len - INTVAL (XEXP (inner, 1)),
6430 unsignedp, in_dest, in_compare);
6432 return gen_rtx_ASHIFT (mode, new_rtx, XEXP (inner, 1));
6435 inner_mode = GET_MODE (inner);
6437 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
6438 pos = INTVAL (pos_rtx), pos_rtx = 0;
6440 /* See if this can be done without an extraction. We never can if the
6441 width of the field is not the same as that of some integer mode. For
6442 registers, we can only avoid the extraction if the position is at the
6443 low-order bit and this is either not in the destination or we have the
6444 appropriate STRICT_LOW_PART operation available.
6446 For MEM, we can avoid an extract if the field starts on an appropriate
6447 boundary and we can change the mode of the memory reference. */
6449 if (tmode != BLKmode
6450 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
6452 && (inner_mode == tmode
6454 || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
6455 GET_MODE_BITSIZE (inner_mode))
6456 || reg_truncated_to_mode (tmode, inner))
6459 && have_insn_for (STRICT_LOW_PART, tmode))))
6460 || (MEM_P (inner) && pos_rtx == 0
6462 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
6463 : BITS_PER_UNIT)) == 0
6464 /* We can't do this if we are widening INNER_MODE (it
6465 may not be aligned, for one thing). */
6466 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
6467 && (inner_mode == tmode
6468 || (! mode_dependent_address_p (XEXP (inner, 0))
6469 && ! MEM_VOLATILE_P (inner))))))
6471 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6472 field. If the original and current mode are the same, we need not
6473 adjust the offset. Otherwise, we do if bytes big endian.
6475 If INNER is not a MEM, get a piece consisting of just the field
6476 of interest (in this case POS % BITS_PER_WORD must be 0). */
6480 HOST_WIDE_INT offset;
6482 /* POS counts from lsb, but make OFFSET count in memory order. */
6483 if (BYTES_BIG_ENDIAN)
6484 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
6486 offset = pos / BITS_PER_UNIT;
6488 new_rtx = adjust_address_nv (inner, tmode, offset);
6490 else if (REG_P (inner))
6492 if (tmode != inner_mode)
6494 /* We can't call gen_lowpart in a DEST since we
6495 always want a SUBREG (see below) and it would sometimes
6496 return a new hard register. */
6499 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
6501 if (WORDS_BIG_ENDIAN
6502 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
6503 final_word = ((GET_MODE_SIZE (inner_mode)
6504 - GET_MODE_SIZE (tmode))
6505 / UNITS_PER_WORD) - final_word;
6507 final_word *= UNITS_PER_WORD;
6508 if (BYTES_BIG_ENDIAN &&
6509 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
6510 final_word += (GET_MODE_SIZE (inner_mode)
6511 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
6513 /* Avoid creating invalid subregs, for example when
6514 simplifying (x>>32)&255. */
6515 if (!validate_subreg (tmode, inner_mode, inner, final_word))
6518 new_rtx = gen_rtx_SUBREG (tmode, inner, final_word);
6521 new_rtx = gen_lowpart (tmode, inner);
6527 new_rtx = force_to_mode (inner, tmode,
6528 len >= HOST_BITS_PER_WIDE_INT
6529 ? ~(unsigned HOST_WIDE_INT) 0
6530 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6533 /* If this extraction is going into the destination of a SET,
6534 make a STRICT_LOW_PART unless we made a MEM. */
6537 return (MEM_P (new_rtx) ? new_rtx
6538 : (GET_CODE (new_rtx) != SUBREG
6539 ? gen_rtx_CLOBBER (tmode, const0_rtx)
6540 : gen_rtx_STRICT_LOW_PART (VOIDmode, new_rtx)));
6545 if (GET_CODE (new_rtx) == CONST_INT)
6546 return gen_int_mode (INTVAL (new_rtx), mode);
6548 /* If we know that no extraneous bits are set, and that the high
6549 bit is not set, convert the extraction to the cheaper of
6550 sign and zero extension, that are equivalent in these cases. */
6551 if (flag_expensive_optimizations
6552 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6553 && ((nonzero_bits (new_rtx, tmode)
6554 & ~(((unsigned HOST_WIDE_INT)
6555 GET_MODE_MASK (tmode))
6559 rtx temp = gen_rtx_ZERO_EXTEND (mode, new_rtx);
6560 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new_rtx);
6562 /* Prefer ZERO_EXTENSION, since it gives more information to
6564 if (rtx_cost (temp, SET, optimize_this_for_speed_p)
6565 <= rtx_cost (temp1, SET, optimize_this_for_speed_p))
6570 /* Otherwise, sign- or zero-extend unless we already are in the
6573 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6577 /* Unless this is a COMPARE or we have a funny memory reference,
6578 don't do anything with zero-extending field extracts starting at
6579 the low-order bit since they are simple AND operations. */
6580 if (pos_rtx == 0 && pos == 0 && ! in_dest
6581 && ! in_compare && unsignedp)
6584 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
6585 if the position is not a constant and the length is not 1. In all
6586 other cases, we would only be going outside our object in cases when
6587 an original shift would have been undefined. */
6589 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6590 || (pos_rtx != 0 && len != 1)))
6593 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6594 and the mode for the result. */
6595 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6597 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6598 pos_mode = mode_for_extraction (EP_insv, 2);
6599 extraction_mode = mode_for_extraction (EP_insv, 3);
6602 if (! in_dest && unsignedp
6603 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6605 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6606 pos_mode = mode_for_extraction (EP_extzv, 3);
6607 extraction_mode = mode_for_extraction (EP_extzv, 0);
6610 if (! in_dest && ! unsignedp
6611 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6613 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6614 pos_mode = mode_for_extraction (EP_extv, 3);
6615 extraction_mode = mode_for_extraction (EP_extv, 0);
6618 /* Never narrow an object, since that might not be safe. */
6620 if (mode != VOIDmode
6621 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6622 extraction_mode = mode;
6624 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6625 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6626 pos_mode = GET_MODE (pos_rtx);
6628 /* If this is not from memory, the desired mode is the preferred mode
6629 for an extraction pattern's first input operand, or word_mode if there
6632 wanted_inner_mode = wanted_inner_reg_mode;
6635 /* Be careful not to go beyond the extracted object and maintain the
6636 natural alignment of the memory. */
6637 wanted_inner_mode = smallest_mode_for_size (len, MODE_INT);
6638 while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len
6639 > GET_MODE_BITSIZE (wanted_inner_mode))
6641 wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode);
6642 gcc_assert (wanted_inner_mode != VOIDmode);
6645 /* If we have to change the mode of memory and cannot, the desired mode
6646 is EXTRACTION_MODE. */
6647 if (inner_mode != wanted_inner_mode
6648 && (mode_dependent_address_p (XEXP (inner, 0))
6649 || MEM_VOLATILE_P (inner)
6651 wanted_inner_mode = extraction_mode;
6656 if (BITS_BIG_ENDIAN)
6658 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6659 BITS_BIG_ENDIAN style. If position is constant, compute new
6660 position. Otherwise, build subtraction.
6661 Note that POS is relative to the mode of the original argument.
6662 If it's a MEM we need to recompute POS relative to that.
6663 However, if we're extracting from (or inserting into) a register,
6664 we want to recompute POS relative to wanted_inner_mode. */
6665 int width = (MEM_P (inner)
6666 ? GET_MODE_BITSIZE (is_mode)
6667 : GET_MODE_BITSIZE (wanted_inner_mode));
6670 pos = width - len - pos;
6673 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6674 /* POS may be less than 0 now, but we check for that below.
6675 Note that it can only be less than 0 if !MEM_P (inner). */
6678 /* If INNER has a wider mode, and this is a constant extraction, try to
6679 make it smaller and adjust the byte to point to the byte containing
6681 if (wanted_inner_mode != VOIDmode
6682 && inner_mode != wanted_inner_mode
6684 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6686 && ! mode_dependent_address_p (XEXP (inner, 0))
6687 && ! MEM_VOLATILE_P (inner))
6691 /* The computations below will be correct if the machine is big
6692 endian in both bits and bytes or little endian in bits and bytes.
6693 If it is mixed, we must adjust. */
6695 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6696 adjust OFFSET to compensate. */
6697 if (BYTES_BIG_ENDIAN
6698 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6699 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6701 /* We can now move to the desired byte. */
6702 offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode))
6703 * GET_MODE_SIZE (wanted_inner_mode);
6704 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6706 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6707 && is_mode != wanted_inner_mode)
6708 offset = (GET_MODE_SIZE (is_mode)
6709 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6711 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6714 /* If INNER is not memory, we can always get it into the proper mode. If we
6715 are changing its mode, POS must be a constant and smaller than the size
6717 else if (!MEM_P (inner))
6719 if (GET_MODE (inner) != wanted_inner_mode
6721 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6727 inner = force_to_mode (inner, wanted_inner_mode,
6729 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6730 ? ~(unsigned HOST_WIDE_INT) 0
6731 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6736 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6737 have to zero extend. Otherwise, we can just use a SUBREG. */
6739 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6741 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6743 /* If we know that no extraneous bits are set, and that the high
6744 bit is not set, convert extraction to cheaper one - either
6745 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6747 if (flag_expensive_optimizations
6748 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6749 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6750 & ~(((unsigned HOST_WIDE_INT)
6751 GET_MODE_MASK (GET_MODE (pos_rtx)))
6755 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6757 /* Prefer ZERO_EXTENSION, since it gives more information to
6759 if (rtx_cost (temp1, SET, optimize_this_for_speed_p)
6760 < rtx_cost (temp, SET, optimize_this_for_speed_p))
6765 else if (pos_rtx != 0
6766 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6767 pos_rtx = gen_lowpart (pos_mode, pos_rtx);
6769 /* Make POS_RTX unless we already have it and it is correct. If we don't
6770 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6772 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6773 pos_rtx = orig_pos_rtx;
6775 else if (pos_rtx == 0)
6776 pos_rtx = GEN_INT (pos);
6778 /* Make the required operation. See if we can use existing rtx. */
6779 new_rtx = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6780 extraction_mode, inner, GEN_INT (len), pos_rtx);
6782 new_rtx = gen_lowpart (mode, new_rtx);
6787 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6788 with any other operations in X. Return X without that shift if so. */
6791 extract_left_shift (rtx x, int count)
6793 enum rtx_code code = GET_CODE (x);
6794 enum machine_mode mode = GET_MODE (x);
6800 /* This is the shift itself. If it is wide enough, we will return
6801 either the value being shifted if the shift count is equal to
6802 COUNT or a shift for the difference. */
6803 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6804 && INTVAL (XEXP (x, 1)) >= count)
6805 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6806 INTVAL (XEXP (x, 1)) - count);
6810 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6811 return simplify_gen_unary (code, mode, tem, mode);
6815 case PLUS: case IOR: case XOR: case AND:
6816 /* If we can safely shift this constant and we find the inner shift,
6817 make a new operation. */
6818 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6819 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6820 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6821 return simplify_gen_binary (code, mode, tem,
6822 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6833 /* Look at the expression rooted at X. Look for expressions
6834 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6835 Form these expressions.
6837 Return the new rtx, usually just X.
6839 Also, for machines like the VAX that don't have logical shift insns,
6840 try to convert logical to arithmetic shift operations in cases where
6841 they are equivalent. This undoes the canonicalizations to logical
6842 shifts done elsewhere.
6844 We try, as much as possible, to re-use rtl expressions to save memory.
6846 IN_CODE says what kind of expression we are processing. Normally, it is
6847 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6848 being kludges), it is MEM. When processing the arguments of a comparison
6849 or a COMPARE against zero, it is COMPARE. */
6852 make_compound_operation (rtx x, enum rtx_code in_code)
6854 enum rtx_code code = GET_CODE (x);
6855 enum machine_mode mode = GET_MODE (x);
6856 int mode_width = GET_MODE_BITSIZE (mode);
6858 enum rtx_code next_code;
6864 /* Select the code to be used in recursive calls. Once we are inside an
6865 address, we stay there. If we have a comparison, set to COMPARE,
6866 but once inside, go back to our default of SET. */
6868 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6869 : ((code == COMPARE || COMPARISON_P (x))
6870 && XEXP (x, 1) == const0_rtx) ? COMPARE
6871 : in_code == COMPARE ? SET : in_code);
6873 /* Process depending on the code of this operation. If NEW is set
6874 nonzero, it will be returned. */
6879 /* Convert shifts by constants into multiplications if inside
6881 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6882 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6883 && INTVAL (XEXP (x, 1)) >= 0)
6885 new_rtx = make_compound_operation (XEXP (x, 0), next_code);
6886 new_rtx = gen_rtx_MULT (mode, new_rtx,
6887 GEN_INT ((HOST_WIDE_INT) 1
6888 << INTVAL (XEXP (x, 1))));
6893 /* If the second operand is not a constant, we can't do anything
6895 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6898 /* If the constant is a power of two minus one and the first operand
6899 is a logical right shift, make an extraction. */
6900 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6901 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6903 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6904 new_rtx = make_extraction (mode, new_rtx, 0, XEXP (XEXP (x, 0), 1), i, 1,
6905 0, in_code == COMPARE);
6908 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6909 else if (GET_CODE (XEXP (x, 0)) == SUBREG
6910 && subreg_lowpart_p (XEXP (x, 0))
6911 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6912 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6914 new_rtx = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6916 new_rtx = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new_rtx, 0,
6917 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6918 0, in_code == COMPARE);
6920 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6921 else if ((GET_CODE (XEXP (x, 0)) == XOR
6922 || GET_CODE (XEXP (x, 0)) == IOR)
6923 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6924 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6925 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6927 /* Apply the distributive law, and then try to make extractions. */
6928 new_rtx = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
6929 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6931 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6933 new_rtx = make_compound_operation (new_rtx, in_code);
6936 /* If we are have (and (rotate X C) M) and C is larger than the number
6937 of bits in M, this is an extraction. */
6939 else if (GET_CODE (XEXP (x, 0)) == ROTATE
6940 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6941 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6942 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6944 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6945 new_rtx = make_extraction (mode, new_rtx,
6946 (GET_MODE_BITSIZE (mode)
6947 - INTVAL (XEXP (XEXP (x, 0), 1))),
6948 NULL_RTX, i, 1, 0, in_code == COMPARE);
6951 /* On machines without logical shifts, if the operand of the AND is
6952 a logical shift and our mask turns off all the propagated sign
6953 bits, we can replace the logical shift with an arithmetic shift. */
6954 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6955 && !have_insn_for (LSHIFTRT, mode)
6956 && have_insn_for (ASHIFTRT, mode)
6957 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6958 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6959 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6960 && mode_width <= HOST_BITS_PER_WIDE_INT)
6962 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6964 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6965 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6967 gen_rtx_ASHIFTRT (mode,
6968 make_compound_operation
6969 (XEXP (XEXP (x, 0), 0), next_code),
6970 XEXP (XEXP (x, 0), 1)));
6973 /* If the constant is one less than a power of two, this might be
6974 representable by an extraction even if no shift is present.
6975 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6976 we are in a COMPARE. */
6977 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6978 new_rtx = make_extraction (mode,
6979 make_compound_operation (XEXP (x, 0),
6981 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6983 /* If we are in a comparison and this is an AND with a power of two,
6984 convert this into the appropriate bit extract. */
6985 else if (in_code == COMPARE
6986 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6987 new_rtx = make_extraction (mode,
6988 make_compound_operation (XEXP (x, 0),
6990 i, NULL_RTX, 1, 1, 0, 1);
6995 /* If the sign bit is known to be zero, replace this with an
6996 arithmetic shift. */
6997 if (have_insn_for (ASHIFTRT, mode)
6998 && ! have_insn_for (LSHIFTRT, mode)
6999 && mode_width <= HOST_BITS_PER_WIDE_INT
7000 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
7002 new_rtx = gen_rtx_ASHIFTRT (mode,
7003 make_compound_operation (XEXP (x, 0),
7009 /* ... fall through ... */
7015 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7016 this is a SIGN_EXTRACT. */
7017 if (GET_CODE (rhs) == CONST_INT
7018 && GET_CODE (lhs) == ASHIFT
7019 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7020 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1))
7021 && INTVAL (rhs) < mode_width)
7023 new_rtx = make_compound_operation (XEXP (lhs, 0), next_code);
7024 new_rtx = make_extraction (mode, new_rtx,
7025 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
7026 NULL_RTX, mode_width - INTVAL (rhs),
7027 code == LSHIFTRT, 0, in_code == COMPARE);
7031 /* See if we have operations between an ASHIFTRT and an ASHIFT.
7032 If so, try to merge the shifts into a SIGN_EXTEND. We could
7033 also do this for some cases of SIGN_EXTRACT, but it doesn't
7034 seem worth the effort; the case checked for occurs on Alpha. */
7037 && ! (GET_CODE (lhs) == SUBREG
7038 && (OBJECT_P (SUBREG_REG (lhs))))
7039 && GET_CODE (rhs) == CONST_INT
7040 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
7041 && INTVAL (rhs) < mode_width
7042 && (new_rtx = extract_left_shift (lhs, INTVAL (rhs))) != 0)
7043 new_rtx = make_extraction (mode, make_compound_operation (new_rtx, next_code),
7044 0, NULL_RTX, mode_width - INTVAL (rhs),
7045 code == LSHIFTRT, 0, in_code == COMPARE);
7050 /* Call ourselves recursively on the inner expression. If we are
7051 narrowing the object and it has a different RTL code from
7052 what it originally did, do this SUBREG as a force_to_mode. */
7054 tem = make_compound_operation (SUBREG_REG (x), in_code);
7058 simplified = simplify_subreg (GET_MODE (x), tem, GET_MODE (tem),
7064 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
7065 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
7066 && subreg_lowpart_p (x))
7068 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
7071 /* If we have something other than a SUBREG, we might have
7072 done an expansion, so rerun ourselves. */
7073 if (GET_CODE (newer) != SUBREG)
7074 newer = make_compound_operation (newer, in_code);
7090 x = gen_lowpart (mode, new_rtx);
7091 code = GET_CODE (x);
7094 /* Now recursively process each operand of this operation. */
7095 fmt = GET_RTX_FORMAT (code);
7096 for (i = 0; i < GET_RTX_LENGTH (code); i++)
7099 new_rtx = make_compound_operation (XEXP (x, i), next_code);
7100 SUBST (XEXP (x, i), new_rtx);
7102 else if (fmt[i] == 'E')
7103 for (j = 0; j < XVECLEN (x, i); j++)
7105 new_rtx = make_compound_operation (XVECEXP (x, i, j), next_code);
7106 SUBST (XVECEXP (x, i, j), new_rtx);
7109 /* If this is a commutative operation, the changes to the operands
7110 may have made it noncanonical. */
7111 if (COMMUTATIVE_ARITH_P (x)
7112 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
7115 SUBST (XEXP (x, 0), XEXP (x, 1));
7116 SUBST (XEXP (x, 1), tem);
7122 /* Given M see if it is a value that would select a field of bits
7123 within an item, but not the entire word. Return -1 if not.
7124 Otherwise, return the starting position of the field, where 0 is the
7127 *PLEN is set to the length of the field. */
7130 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
7132 /* Get the bit number of the first 1 bit from the right, -1 if none. */
7133 int pos = exact_log2 (m & -m);
7137 /* Now shift off the low-order zero bits and see if we have a
7138 power of two minus 1. */
7139 len = exact_log2 ((m >> pos) + 1);
7148 /* If X refers to a register that equals REG in value, replace these
7149 references with REG. */
7151 canon_reg_for_combine (rtx x, rtx reg)
7158 enum rtx_code code = GET_CODE (x);
7159 switch (GET_RTX_CLASS (code))
7162 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7163 if (op0 != XEXP (x, 0))
7164 return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
7169 case RTX_COMM_ARITH:
7170 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7171 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7172 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7173 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
7177 case RTX_COMM_COMPARE:
7178 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7179 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7180 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7181 return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
7182 GET_MODE (op0), op0, op1);
7186 case RTX_BITFIELD_OPS:
7187 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7188 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7189 op2 = canon_reg_for_combine (XEXP (x, 2), reg);
7190 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
7191 return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
7192 GET_MODE (op0), op0, op1, op2);
7197 if (rtx_equal_p (get_last_value (reg), x)
7198 || rtx_equal_p (reg, get_last_value (x)))
7207 fmt = GET_RTX_FORMAT (code);
7209 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7212 rtx op = canon_reg_for_combine (XEXP (x, i), reg);
7213 if (op != XEXP (x, i))
7223 else if (fmt[i] == 'E')
7226 for (j = 0; j < XVECLEN (x, i); j++)
7228 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
7229 if (op != XVECEXP (x, i, j))
7236 XVECEXP (x, i, j) = op;
7247 /* Return X converted to MODE. If the value is already truncated to
7248 MODE we can just return a subreg even though in the general case we
7249 would need an explicit truncation. */
7252 gen_lowpart_or_truncate (enum machine_mode mode, rtx x)
7254 if (GET_MODE_SIZE (GET_MODE (x)) <= GET_MODE_SIZE (mode)
7255 || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
7256 GET_MODE_BITSIZE (GET_MODE (x)))
7257 || (REG_P (x) && reg_truncated_to_mode (mode, x)))
7258 return gen_lowpart (mode, x);
7260 return simplify_gen_unary (TRUNCATE, mode, x, GET_MODE (x));
7263 /* See if X can be simplified knowing that we will only refer to it in
7264 MODE and will only refer to those bits that are nonzero in MASK.
7265 If other bits are being computed or if masking operations are done
7266 that select a superset of the bits in MASK, they can sometimes be
7269 Return a possibly simplified expression, but always convert X to
7270 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
7272 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
7273 are all off in X. This is used when X will be complemented, by either
7274 NOT, NEG, or XOR. */
7277 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
7280 enum rtx_code code = GET_CODE (x);
7281 int next_select = just_select || code == XOR || code == NOT || code == NEG;
7282 enum machine_mode op_mode;
7283 unsigned HOST_WIDE_INT fuller_mask, nonzero;
7286 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
7287 code below will do the wrong thing since the mode of such an
7288 expression is VOIDmode.
7290 Also do nothing if X is a CLOBBER; this can happen if X was
7291 the return value from a call to gen_lowpart. */
7292 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
7295 /* We want to perform the operation is its present mode unless we know
7296 that the operation is valid in MODE, in which case we do the operation
7298 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
7299 && have_insn_for (code, mode))
7300 ? mode : GET_MODE (x));
7302 /* It is not valid to do a right-shift in a narrower mode
7303 than the one it came in with. */
7304 if ((code == LSHIFTRT || code == ASHIFTRT)
7305 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
7306 op_mode = GET_MODE (x);
7308 /* Truncate MASK to fit OP_MODE. */
7310 mask &= GET_MODE_MASK (op_mode);
7312 /* When we have an arithmetic operation, or a shift whose count we
7313 do not know, we need to assume that all bits up to the highest-order
7314 bit in MASK will be needed. This is how we form such a mask. */
7315 if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
7316 fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
7318 fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
7321 /* Determine what bits of X are guaranteed to be (non)zero. */
7322 nonzero = nonzero_bits (x, mode);
7324 /* If none of the bits in X are needed, return a zero. */
7325 if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x))
7328 /* If X is a CONST_INT, return a new one. Do this here since the
7329 test below will fail. */
7330 if (GET_CODE (x) == CONST_INT)
7332 if (SCALAR_INT_MODE_P (mode))
7333 return gen_int_mode (INTVAL (x) & mask, mode);
7336 x = GEN_INT (INTVAL (x) & mask);
7337 return gen_lowpart_common (mode, x);
7341 /* If X is narrower than MODE and we want all the bits in X's mode, just
7342 get X in the proper mode. */
7343 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
7344 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
7345 return gen_lowpart (mode, x);
7347 /* The arithmetic simplifications here do the wrong thing on vector modes. */
7348 if (VECTOR_MODE_P (mode) || VECTOR_MODE_P (GET_MODE (x)))
7349 return gen_lowpart (mode, x);
7354 /* If X is a (clobber (const_int)), return it since we know we are
7355 generating something that won't match. */
7362 x = expand_compound_operation (x);
7363 if (GET_CODE (x) != code)
7364 return force_to_mode (x, mode, mask, next_select);
7368 if (subreg_lowpart_p (x)
7369 /* We can ignore the effect of this SUBREG if it narrows the mode or
7370 if the constant masks to zero all the bits the mode doesn't
7372 && ((GET_MODE_SIZE (GET_MODE (x))
7373 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7375 & GET_MODE_MASK (GET_MODE (x))
7376 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
7377 return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
7381 /* If this is an AND with a constant, convert it into an AND
7382 whose constant is the AND of that constant with MASK. If it
7383 remains an AND of MASK, delete it since it is redundant. */
7385 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
7387 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
7388 mask & INTVAL (XEXP (x, 1)));
7390 /* If X is still an AND, see if it is an AND with a mask that
7391 is just some low-order bits. If so, and it is MASK, we don't
7394 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
7395 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
7399 /* If it remains an AND, try making another AND with the bits
7400 in the mode mask that aren't in MASK turned on. If the
7401 constant in the AND is wide enough, this might make a
7402 cheaper constant. */
7404 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
7405 && GET_MODE_MASK (GET_MODE (x)) != mask
7406 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
7408 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
7409 | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
7410 int width = GET_MODE_BITSIZE (GET_MODE (x));
7413 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
7414 number, sign extend it. */
7415 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
7416 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7417 cval |= (HOST_WIDE_INT) -1 << width;
7419 y = simplify_gen_binary (AND, GET_MODE (x),
7420 XEXP (x, 0), GEN_INT (cval));
7421 if (rtx_cost (y, SET, optimize_this_for_speed_p)
7422 < rtx_cost (x, SET, optimize_this_for_speed_p))
7432 /* In (and (plus FOO C1) M), if M is a mask that just turns off
7433 low-order bits (as in an alignment operation) and FOO is already
7434 aligned to that boundary, mask C1 to that boundary as well.
7435 This may eliminate that PLUS and, later, the AND. */
7438 unsigned int width = GET_MODE_BITSIZE (mode);
7439 unsigned HOST_WIDE_INT smask = mask;
7441 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
7442 number, sign extend it. */
7444 if (width < HOST_BITS_PER_WIDE_INT
7445 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7446 smask |= (HOST_WIDE_INT) -1 << width;
7448 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7449 && exact_log2 (- smask) >= 0
7450 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
7451 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
7452 return force_to_mode (plus_constant (XEXP (x, 0),
7453 (INTVAL (XEXP (x, 1)) & smask)),
7454 mode, smask, next_select);
7457 /* ... fall through ... */
7460 /* For PLUS, MINUS and MULT, we need any bits less significant than the
7461 most significant bit in MASK since carries from those bits will
7462 affect the bits we are interested in. */
7467 /* If X is (minus C Y) where C's least set bit is larger than any bit
7468 in the mask, then we may replace with (neg Y). */
7469 if (GET_CODE (XEXP (x, 0)) == CONST_INT
7470 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
7471 & -INTVAL (XEXP (x, 0))))
7474 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
7476 return force_to_mode (x, mode, mask, next_select);
7479 /* Similarly, if C contains every bit in the fuller_mask, then we may
7480 replace with (not Y). */
7481 if (GET_CODE (XEXP (x, 0)) == CONST_INT
7482 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask)
7483 == INTVAL (XEXP (x, 0))))
7485 x = simplify_gen_unary (NOT, GET_MODE (x),
7486 XEXP (x, 1), GET_MODE (x));
7487 return force_to_mode (x, mode, mask, next_select);
7495 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7496 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7497 operation which may be a bitfield extraction. Ensure that the
7498 constant we form is not wider than the mode of X. */
7500 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7501 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7502 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7503 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7504 && GET_CODE (XEXP (x, 1)) == CONST_INT
7505 && ((INTVAL (XEXP (XEXP (x, 0), 1))
7506 + floor_log2 (INTVAL (XEXP (x, 1))))
7507 < GET_MODE_BITSIZE (GET_MODE (x)))
7508 && (INTVAL (XEXP (x, 1))
7509 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
7511 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
7512 << INTVAL (XEXP (XEXP (x, 0), 1)));
7513 temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
7514 XEXP (XEXP (x, 0), 0), temp);
7515 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
7516 XEXP (XEXP (x, 0), 1));
7517 return force_to_mode (x, mode, mask, next_select);
7521 /* For most binary operations, just propagate into the operation and
7522 change the mode if we have an operation of that mode. */
7524 op0 = gen_lowpart_or_truncate (op_mode,
7525 force_to_mode (XEXP (x, 0), mode, mask,
7527 op1 = gen_lowpart_or_truncate (op_mode,
7528 force_to_mode (XEXP (x, 1), mode, mask,
7531 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7532 x = simplify_gen_binary (code, op_mode, op0, op1);
7536 /* For left shifts, do the same, but just for the first operand.
7537 However, we cannot do anything with shifts where we cannot
7538 guarantee that the counts are smaller than the size of the mode
7539 because such a count will have a different meaning in a
7542 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
7543 && INTVAL (XEXP (x, 1)) >= 0
7544 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
7545 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
7546 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
7547 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
7550 /* If the shift count is a constant and we can do arithmetic in
7551 the mode of the shift, refine which bits we need. Otherwise, use the
7552 conservative form of the mask. */
7553 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7554 && INTVAL (XEXP (x, 1)) >= 0
7555 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
7556 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7557 mask >>= INTVAL (XEXP (x, 1));
7561 op0 = gen_lowpart_or_truncate (op_mode,
7562 force_to_mode (XEXP (x, 0), op_mode,
7563 mask, next_select));
7565 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7566 x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
7570 /* Here we can only do something if the shift count is a constant,
7571 this shift constant is valid for the host, and we can do arithmetic
7574 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7575 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7576 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7578 rtx inner = XEXP (x, 0);
7579 unsigned HOST_WIDE_INT inner_mask;
7581 /* Select the mask of the bits we need for the shift operand. */
7582 inner_mask = mask << INTVAL (XEXP (x, 1));
7584 /* We can only change the mode of the shift if we can do arithmetic
7585 in the mode of the shift and INNER_MASK is no wider than the
7586 width of X's mode. */
7587 if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
7588 op_mode = GET_MODE (x);
7590 inner = force_to_mode (inner, op_mode, inner_mask, next_select);
7592 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
7593 x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
7596 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7597 shift and AND produces only copies of the sign bit (C2 is one less
7598 than a power of two), we can do this with just a shift. */
7600 if (GET_CODE (x) == LSHIFTRT
7601 && GET_CODE (XEXP (x, 1)) == CONST_INT
7602 /* The shift puts one of the sign bit copies in the least significant
7604 && ((INTVAL (XEXP (x, 1))
7605 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7606 >= GET_MODE_BITSIZE (GET_MODE (x)))
7607 && exact_log2 (mask + 1) >= 0
7608 /* Number of bits left after the shift must be more than the mask
7610 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7611 <= GET_MODE_BITSIZE (GET_MODE (x)))
7612 /* Must be more sign bit copies than the mask needs. */
7613 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7614 >= exact_log2 (mask + 1)))
7615 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7616 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7617 - exact_log2 (mask + 1)));
7622 /* If we are just looking for the sign bit, we don't need this shift at
7623 all, even if it has a variable count. */
7624 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7625 && (mask == ((unsigned HOST_WIDE_INT) 1
7626 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7627 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7629 /* If this is a shift by a constant, get a mask that contains those bits
7630 that are not copies of the sign bit. We then have two cases: If
7631 MASK only includes those bits, this can be a logical shift, which may
7632 allow simplifications. If MASK is a single-bit field not within
7633 those bits, we are requesting a copy of the sign bit and hence can
7634 shift the sign bit to the appropriate location. */
7636 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
7637 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7641 /* If the considered data is wider than HOST_WIDE_INT, we can't
7642 represent a mask for all its bits in a single scalar.
7643 But we only care about the lower bits, so calculate these. */
7645 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7647 nonzero = ~(HOST_WIDE_INT) 0;
7649 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7650 is the number of bits a full-width mask would have set.
7651 We need only shift if these are fewer than nonzero can
7652 hold. If not, we must keep all bits set in nonzero. */
7654 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7655 < HOST_BITS_PER_WIDE_INT)
7656 nonzero >>= INTVAL (XEXP (x, 1))
7657 + HOST_BITS_PER_WIDE_INT
7658 - GET_MODE_BITSIZE (GET_MODE (x)) ;
7662 nonzero = GET_MODE_MASK (GET_MODE (x));
7663 nonzero >>= INTVAL (XEXP (x, 1));
7666 if ((mask & ~nonzero) == 0)
7668 x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x),
7669 XEXP (x, 0), INTVAL (XEXP (x, 1)));
7670 if (GET_CODE (x) != ASHIFTRT)
7671 return force_to_mode (x, mode, mask, next_select);
7674 else if ((i = exact_log2 (mask)) >= 0)
7676 x = simplify_shift_const
7677 (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7678 GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7680 if (GET_CODE (x) != ASHIFTRT)
7681 return force_to_mode (x, mode, mask, next_select);
7685 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7686 even if the shift count isn't a constant. */
7688 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7689 XEXP (x, 0), XEXP (x, 1));
7693 /* If this is a zero- or sign-extension operation that just affects bits
7694 we don't care about, remove it. Be sure the call above returned
7695 something that is still a shift. */
7697 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7698 && GET_CODE (XEXP (x, 1)) == CONST_INT
7699 && INTVAL (XEXP (x, 1)) >= 0
7700 && (INTVAL (XEXP (x, 1))
7701 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7702 && GET_CODE (XEXP (x, 0)) == ASHIFT
7703 && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
7704 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7711 /* If the shift count is constant and we can do computations
7712 in the mode of X, compute where the bits we care about are.
7713 Otherwise, we can't do anything. Don't change the mode of
7714 the shift or propagate MODE into the shift, though. */
7715 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7716 && INTVAL (XEXP (x, 1)) >= 0)
7718 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7719 GET_MODE (x), GEN_INT (mask),
7721 if (temp && GET_CODE (temp) == CONST_INT)
7723 force_to_mode (XEXP (x, 0), GET_MODE (x),
7724 INTVAL (temp), next_select));
7729 /* If we just want the low-order bit, the NEG isn't needed since it
7730 won't change the low-order bit. */
7732 return force_to_mode (XEXP (x, 0), mode, mask, just_select);
7734 /* We need any bits less significant than the most significant bit in
7735 MASK since carries from those bits will affect the bits we are
7741 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7742 same as the XOR case above. Ensure that the constant we form is not
7743 wider than the mode of X. */
7745 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7746 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7747 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7748 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7749 < GET_MODE_BITSIZE (GET_MODE (x)))
7750 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7752 temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
7754 temp = simplify_gen_binary (XOR, GET_MODE (x),
7755 XEXP (XEXP (x, 0), 0), temp);
7756 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7757 temp, XEXP (XEXP (x, 0), 1));
7759 return force_to_mode (x, mode, mask, next_select);
7762 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7763 use the full mask inside the NOT. */
7767 op0 = gen_lowpart_or_truncate (op_mode,
7768 force_to_mode (XEXP (x, 0), mode, mask,
7770 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7771 x = simplify_gen_unary (code, op_mode, op0, op_mode);
7775 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7776 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7777 which is equal to STORE_FLAG_VALUE. */
7778 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7779 && GET_MODE (XEXP (x, 0)) == mode
7780 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7781 && (nonzero_bits (XEXP (x, 0), mode)
7782 == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
7783 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7788 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7789 written in a narrower mode. We play it safe and do not do so. */
7792 gen_lowpart_or_truncate (GET_MODE (x),
7793 force_to_mode (XEXP (x, 1), mode,
7794 mask, next_select)));
7796 gen_lowpart_or_truncate (GET_MODE (x),
7797 force_to_mode (XEXP (x, 2), mode,
7798 mask, next_select)));
7805 /* Ensure we return a value of the proper mode. */
7806 return gen_lowpart_or_truncate (mode, x);
7809 /* Return nonzero if X is an expression that has one of two values depending on
7810 whether some other value is zero or nonzero. In that case, we return the
7811 value that is being tested, *PTRUE is set to the value if the rtx being
7812 returned has a nonzero value, and *PFALSE is set to the other alternative.
7814 If we return zero, we set *PTRUE and *PFALSE to X. */
7817 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
7819 enum machine_mode mode = GET_MODE (x);
7820 enum rtx_code code = GET_CODE (x);
7821 rtx cond0, cond1, true0, true1, false0, false1;
7822 unsigned HOST_WIDE_INT nz;
7824 /* If we are comparing a value against zero, we are done. */
7825 if ((code == NE || code == EQ)
7826 && XEXP (x, 1) == const0_rtx)
7828 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7829 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7833 /* If this is a unary operation whose operand has one of two values, apply
7834 our opcode to compute those values. */
7835 else if (UNARY_P (x)
7836 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7838 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
7839 *pfalse = simplify_gen_unary (code, mode, false0,
7840 GET_MODE (XEXP (x, 0)));
7844 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7845 make can't possibly match and would suppress other optimizations. */
7846 else if (code == COMPARE)
7849 /* If this is a binary operation, see if either side has only one of two
7850 values. If either one does or if both do and they are conditional on
7851 the same value, compute the new true and false values. */
7852 else if (BINARY_P (x))
7854 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7855 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7857 if ((cond0 != 0 || cond1 != 0)
7858 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7860 /* If if_then_else_cond returned zero, then true/false are the
7861 same rtl. We must copy one of them to prevent invalid rtl
7864 true0 = copy_rtx (true0);
7865 else if (cond1 == 0)
7866 true1 = copy_rtx (true1);
7868 if (COMPARISON_P (x))
7870 *ptrue = simplify_gen_relational (code, mode, VOIDmode,
7872 *pfalse = simplify_gen_relational (code, mode, VOIDmode,
7877 *ptrue = simplify_gen_binary (code, mode, true0, true1);
7878 *pfalse = simplify_gen_binary (code, mode, false0, false1);
7881 return cond0 ? cond0 : cond1;
7884 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7885 operands is zero when the other is nonzero, and vice-versa,
7886 and STORE_FLAG_VALUE is 1 or -1. */
7888 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7889 && (code == PLUS || code == IOR || code == XOR || code == MINUS
7891 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7893 rtx op0 = XEXP (XEXP (x, 0), 1);
7894 rtx op1 = XEXP (XEXP (x, 1), 1);
7896 cond0 = XEXP (XEXP (x, 0), 0);
7897 cond1 = XEXP (XEXP (x, 1), 0);
7899 if (COMPARISON_P (cond0)
7900 && COMPARISON_P (cond1)
7901 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
7902 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7903 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7904 || ((swap_condition (GET_CODE (cond0))
7905 == reversed_comparison_code (cond1, NULL))
7906 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7907 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7908 && ! side_effects_p (x))
7910 *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
7911 *pfalse = simplify_gen_binary (MULT, mode,
7913 ? simplify_gen_unary (NEG, mode,
7921 /* Similarly for MULT, AND and UMIN, except that for these the result
7923 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7924 && (code == MULT || code == AND || code == UMIN)
7925 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7927 cond0 = XEXP (XEXP (x, 0), 0);
7928 cond1 = XEXP (XEXP (x, 1), 0);
7930 if (COMPARISON_P (cond0)
7931 && COMPARISON_P (cond1)
7932 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
7933 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7934 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7935 || ((swap_condition (GET_CODE (cond0))
7936 == reversed_comparison_code (cond1, NULL))
7937 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7938 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7939 && ! side_effects_p (x))
7941 *ptrue = *pfalse = const0_rtx;
7947 else if (code == IF_THEN_ELSE)
7949 /* If we have IF_THEN_ELSE already, extract the condition and
7950 canonicalize it if it is NE or EQ. */
7951 cond0 = XEXP (x, 0);
7952 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7953 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7954 return XEXP (cond0, 0);
7955 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7957 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7958 return XEXP (cond0, 0);
7964 /* If X is a SUBREG, we can narrow both the true and false values
7965 if the inner expression, if there is a condition. */
7966 else if (code == SUBREG
7967 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7970 true0 = simplify_gen_subreg (mode, true0,
7971 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7972 false0 = simplify_gen_subreg (mode, false0,
7973 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7974 if (true0 && false0)
7982 /* If X is a constant, this isn't special and will cause confusions
7983 if we treat it as such. Likewise if it is equivalent to a constant. */
7984 else if (CONSTANT_P (x)
7985 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7988 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7989 will be least confusing to the rest of the compiler. */
7990 else if (mode == BImode)
7992 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
7996 /* If X is known to be either 0 or -1, those are the true and
7997 false values when testing X. */
7998 else if (x == constm1_rtx || x == const0_rtx
7999 || (mode != VOIDmode
8000 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
8002 *ptrue = constm1_rtx, *pfalse = const0_rtx;
8006 /* Likewise for 0 or a single bit. */
8007 else if (SCALAR_INT_MODE_P (mode)
8008 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8009 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
8011 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
8015 /* Otherwise fail; show no condition with true and false values the same. */
8016 *ptrue = *pfalse = x;
8020 /* Return the value of expression X given the fact that condition COND
8021 is known to be true when applied to REG as its first operand and VAL
8022 as its second. X is known to not be shared and so can be modified in
8025 We only handle the simplest cases, and specifically those cases that
8026 arise with IF_THEN_ELSE expressions. */
8029 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
8031 enum rtx_code code = GET_CODE (x);
8036 if (side_effects_p (x))
8039 /* If either operand of the condition is a floating point value,
8040 then we have to avoid collapsing an EQ comparison. */
8042 && rtx_equal_p (x, reg)
8043 && ! FLOAT_MODE_P (GET_MODE (x))
8044 && ! FLOAT_MODE_P (GET_MODE (val)))
8047 if (cond == UNEQ && rtx_equal_p (x, reg))
8050 /* If X is (abs REG) and we know something about REG's relationship
8051 with zero, we may be able to simplify this. */
8053 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
8056 case GE: case GT: case EQ:
8059 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
8061 GET_MODE (XEXP (x, 0)));
8066 /* The only other cases we handle are MIN, MAX, and comparisons if the
8067 operands are the same as REG and VAL. */
8069 else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
8071 if (rtx_equal_p (XEXP (x, 0), val))
8072 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
8074 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
8076 if (COMPARISON_P (x))
8078 if (comparison_dominates_p (cond, code))
8079 return const_true_rtx;
8081 code = reversed_comparison_code (x, NULL);
8083 && comparison_dominates_p (cond, code))
8088 else if (code == SMAX || code == SMIN
8089 || code == UMIN || code == UMAX)
8091 int unsignedp = (code == UMIN || code == UMAX);
8093 /* Do not reverse the condition when it is NE or EQ.
8094 This is because we cannot conclude anything about
8095 the value of 'SMAX (x, y)' when x is not equal to y,
8096 but we can when x equals y. */
8097 if ((code == SMAX || code == UMAX)
8098 && ! (cond == EQ || cond == NE))
8099 cond = reverse_condition (cond);
8104 return unsignedp ? x : XEXP (x, 1);
8106 return unsignedp ? x : XEXP (x, 0);
8108 return unsignedp ? XEXP (x, 1) : x;
8110 return unsignedp ? XEXP (x, 0) : x;
8117 else if (code == SUBREG)
8119 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
8120 rtx new_rtx, r = known_cond (SUBREG_REG (x), cond, reg, val);
8122 if (SUBREG_REG (x) != r)
8124 /* We must simplify subreg here, before we lose track of the
8125 original inner_mode. */
8126 new_rtx = simplify_subreg (GET_MODE (x), r,
8127 inner_mode, SUBREG_BYTE (x));
8131 SUBST (SUBREG_REG (x), r);
8136 /* We don't have to handle SIGN_EXTEND here, because even in the
8137 case of replacing something with a modeless CONST_INT, a
8138 CONST_INT is already (supposed to be) a valid sign extension for
8139 its narrower mode, which implies it's already properly
8140 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
8141 story is different. */
8142 else if (code == ZERO_EXTEND)
8144 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
8145 rtx new_rtx, r = known_cond (XEXP (x, 0), cond, reg, val);
8147 if (XEXP (x, 0) != r)
8149 /* We must simplify the zero_extend here, before we lose
8150 track of the original inner_mode. */
8151 new_rtx = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
8156 SUBST (XEXP (x, 0), r);
8162 fmt = GET_RTX_FORMAT (code);
8163 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8166 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
8167 else if (fmt[i] == 'E')
8168 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8169 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
8176 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
8177 assignment as a field assignment. */
8180 rtx_equal_for_field_assignment_p (rtx x, rtx y)
8182 if (x == y || rtx_equal_p (x, y))
8185 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
8188 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
8189 Note that all SUBREGs of MEM are paradoxical; otherwise they
8190 would have been rewritten. */
8191 if (MEM_P (x) && GET_CODE (y) == SUBREG
8192 && MEM_P (SUBREG_REG (y))
8193 && rtx_equal_p (SUBREG_REG (y),
8194 gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
8197 if (MEM_P (y) && GET_CODE (x) == SUBREG
8198 && MEM_P (SUBREG_REG (x))
8199 && rtx_equal_p (SUBREG_REG (x),
8200 gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
8203 /* We used to see if get_last_value of X and Y were the same but that's
8204 not correct. In one direction, we'll cause the assignment to have
8205 the wrong destination and in the case, we'll import a register into this
8206 insn that might have already have been dead. So fail if none of the
8207 above cases are true. */
8211 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
8212 Return that assignment if so.
8214 We only handle the most common cases. */
8217 make_field_assignment (rtx x)
8219 rtx dest = SET_DEST (x);
8220 rtx src = SET_SRC (x);
8225 unsigned HOST_WIDE_INT len;
8227 enum machine_mode mode;
8229 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
8230 a clear of a one-bit field. We will have changed it to
8231 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
8234 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
8235 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
8236 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
8237 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8239 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8242 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8246 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
8247 && subreg_lowpart_p (XEXP (src, 0))
8248 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
8249 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
8250 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
8251 && GET_CODE (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == CONST_INT
8252 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
8253 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8255 assign = make_extraction (VOIDmode, dest, 0,
8256 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
8259 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8263 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
8265 if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
8266 && XEXP (XEXP (src, 0), 0) == const1_rtx
8267 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8269 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8272 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
8276 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
8277 SRC is an AND with all bits of that field set, then we can discard
8279 if (GET_CODE (dest) == ZERO_EXTRACT
8280 && GET_CODE (XEXP (dest, 1)) == CONST_INT
8281 && GET_CODE (src) == AND
8282 && GET_CODE (XEXP (src, 1)) == CONST_INT)
8284 HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
8285 unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
8286 unsigned HOST_WIDE_INT ze_mask;
8288 if (width >= HOST_BITS_PER_WIDE_INT)
8291 ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
8293 /* Complete overlap. We can remove the source AND. */
8294 if ((and_mask & ze_mask) == ze_mask)
8295 return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
8297 /* Partial overlap. We can reduce the source AND. */
8298 if ((and_mask & ze_mask) != and_mask)
8300 mode = GET_MODE (src);
8301 src = gen_rtx_AND (mode, XEXP (src, 0),
8302 gen_int_mode (and_mask & ze_mask, mode));
8303 return gen_rtx_SET (VOIDmode, dest, src);
8307 /* The other case we handle is assignments into a constant-position
8308 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
8309 a mask that has all one bits except for a group of zero bits and
8310 OTHER is known to have zeros where C1 has ones, this is such an
8311 assignment. Compute the position and length from C1. Shift OTHER
8312 to the appropriate position, force it to the required mode, and
8313 make the extraction. Check for the AND in both operands. */
8315 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
8318 rhs = expand_compound_operation (XEXP (src, 0));
8319 lhs = expand_compound_operation (XEXP (src, 1));
8321 if (GET_CODE (rhs) == AND
8322 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
8323 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
8324 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
8325 else if (GET_CODE (lhs) == AND
8326 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
8327 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
8328 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
8332 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
8333 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
8334 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
8335 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
8338 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
8342 /* The mode to use for the source is the mode of the assignment, or of
8343 what is inside a possible STRICT_LOW_PART. */
8344 mode = (GET_CODE (assign) == STRICT_LOW_PART
8345 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
8347 /* Shift OTHER right POS places and make it the source, restricting it
8348 to the proper length and mode. */
8350 src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
8354 src = force_to_mode (src, mode,
8355 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
8356 ? ~(unsigned HOST_WIDE_INT) 0
8357 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
8360 /* If SRC is masked by an AND that does not make a difference in
8361 the value being stored, strip it. */
8362 if (GET_CODE (assign) == ZERO_EXTRACT
8363 && GET_CODE (XEXP (assign, 1)) == CONST_INT
8364 && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
8365 && GET_CODE (src) == AND
8366 && GET_CODE (XEXP (src, 1)) == CONST_INT
8367 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (src, 1))
8368 == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1))
8369 src = XEXP (src, 0);
8371 return gen_rtx_SET (VOIDmode, assign, src);
8374 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
8378 apply_distributive_law (rtx x)
8380 enum rtx_code code = GET_CODE (x);
8381 enum rtx_code inner_code;
8382 rtx lhs, rhs, other;
8385 /* Distributivity is not true for floating point as it can change the
8386 value. So we don't do it unless -funsafe-math-optimizations. */
8387 if (FLOAT_MODE_P (GET_MODE (x))
8388 && ! flag_unsafe_math_optimizations)
8391 /* The outer operation can only be one of the following: */
8392 if (code != IOR && code != AND && code != XOR
8393 && code != PLUS && code != MINUS)
8399 /* If either operand is a primitive we can't do anything, so get out
8401 if (OBJECT_P (lhs) || OBJECT_P (rhs))
8404 lhs = expand_compound_operation (lhs);
8405 rhs = expand_compound_operation (rhs);
8406 inner_code = GET_CODE (lhs);
8407 if (inner_code != GET_CODE (rhs))
8410 /* See if the inner and outer operations distribute. */
8417 /* These all distribute except over PLUS. */
8418 if (code == PLUS || code == MINUS)
8423 if (code != PLUS && code != MINUS)
8428 /* This is also a multiply, so it distributes over everything. */
8432 /* Non-paradoxical SUBREGs distributes over all operations,
8433 provided the inner modes and byte offsets are the same, this
8434 is an extraction of a low-order part, we don't convert an fp
8435 operation to int or vice versa, this is not a vector mode,
8436 and we would not be converting a single-word operation into a
8437 multi-word operation. The latter test is not required, but
8438 it prevents generating unneeded multi-word operations. Some
8439 of the previous tests are redundant given the latter test,
8440 but are retained because they are required for correctness.
8442 We produce the result slightly differently in this case. */
8444 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
8445 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
8446 || ! subreg_lowpart_p (lhs)
8447 || (GET_MODE_CLASS (GET_MODE (lhs))
8448 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
8449 || (GET_MODE_SIZE (GET_MODE (lhs))
8450 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
8451 || VECTOR_MODE_P (GET_MODE (lhs))
8452 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD
8453 /* Result might need to be truncated. Don't change mode if
8454 explicit truncation is needed. */
8455 || !TRULY_NOOP_TRUNCATION
8456 (GET_MODE_BITSIZE (GET_MODE (x)),
8457 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (lhs)))))
8460 tem = simplify_gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
8461 SUBREG_REG (lhs), SUBREG_REG (rhs));
8462 return gen_lowpart (GET_MODE (x), tem);
8468 /* Set LHS and RHS to the inner operands (A and B in the example
8469 above) and set OTHER to the common operand (C in the example).
8470 There is only one way to do this unless the inner operation is
8472 if (COMMUTATIVE_ARITH_P (lhs)
8473 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
8474 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
8475 else if (COMMUTATIVE_ARITH_P (lhs)
8476 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
8477 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
8478 else if (COMMUTATIVE_ARITH_P (lhs)
8479 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
8480 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
8481 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
8482 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
8486 /* Form the new inner operation, seeing if it simplifies first. */
8487 tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
8489 /* There is one exception to the general way of distributing:
8490 (a | c) ^ (b | c) -> (a ^ b) & ~c */
8491 if (code == XOR && inner_code == IOR)
8494 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
8497 /* We may be able to continuing distributing the result, so call
8498 ourselves recursively on the inner operation before forming the
8499 outer operation, which we return. */
8500 return simplify_gen_binary (inner_code, GET_MODE (x),
8501 apply_distributive_law (tem), other);
8504 /* See if X is of the form (* (+ A B) C), and if so convert to
8505 (+ (* A C) (* B C)) and try to simplify.
8507 Most of the time, this results in no change. However, if some of
8508 the operands are the same or inverses of each other, simplifications
8511 For example, (and (ior A B) (not B)) can occur as the result of
8512 expanding a bit field assignment. When we apply the distributive
8513 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
8514 which then simplifies to (and (A (not B))).
8516 Note that no checks happen on the validity of applying the inverse
8517 distributive law. This is pointless since we can do it in the
8518 few places where this routine is called.
8520 N is the index of the term that is decomposed (the arithmetic operation,
8521 i.e. (+ A B) in the first example above). !N is the index of the term that
8522 is distributed, i.e. of C in the first example above. */
8524 distribute_and_simplify_rtx (rtx x, int n)
8526 enum machine_mode mode;
8527 enum rtx_code outer_code, inner_code;
8528 rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
8530 decomposed = XEXP (x, n);
8531 if (!ARITHMETIC_P (decomposed))
8534 mode = GET_MODE (x);
8535 outer_code = GET_CODE (x);
8536 distributed = XEXP (x, !n);
8538 inner_code = GET_CODE (decomposed);
8539 inner_op0 = XEXP (decomposed, 0);
8540 inner_op1 = XEXP (decomposed, 1);
8542 /* Special case (and (xor B C) (not A)), which is equivalent to
8543 (xor (ior A B) (ior A C)) */
8544 if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
8546 distributed = XEXP (distributed, 0);
8552 /* Distribute the second term. */
8553 new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
8554 new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
8558 /* Distribute the first term. */
8559 new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
8560 new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
8563 tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
8565 if (GET_CODE (tmp) != outer_code
8566 && rtx_cost (tmp, SET, optimize_this_for_speed_p)
8567 < rtx_cost (x, SET, optimize_this_for_speed_p))
8573 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
8574 in MODE. Return an equivalent form, if different from (and VAROP
8575 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
8578 simplify_and_const_int_1 (enum machine_mode mode, rtx varop,
8579 unsigned HOST_WIDE_INT constop)
8581 unsigned HOST_WIDE_INT nonzero;
8582 unsigned HOST_WIDE_INT orig_constop;
8587 orig_constop = constop;
8588 if (GET_CODE (varop) == CLOBBER)
8591 /* Simplify VAROP knowing that we will be only looking at some of the
8594 Note by passing in CONSTOP, we guarantee that the bits not set in
8595 CONSTOP are not significant and will never be examined. We must
8596 ensure that is the case by explicitly masking out those bits
8597 before returning. */
8598 varop = force_to_mode (varop, mode, constop, 0);
8600 /* If VAROP is a CLOBBER, we will fail so return it. */
8601 if (GET_CODE (varop) == CLOBBER)
8604 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
8605 to VAROP and return the new constant. */
8606 if (GET_CODE (varop) == CONST_INT)
8607 return gen_int_mode (INTVAL (varop) & constop, mode);
8609 /* See what bits may be nonzero in VAROP. Unlike the general case of
8610 a call to nonzero_bits, here we don't care about bits outside
8613 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
8615 /* Turn off all bits in the constant that are known to already be zero.
8616 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8617 which is tested below. */
8621 /* If we don't have any bits left, return zero. */
8625 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8626 a power of two, we can replace this with an ASHIFT. */
8627 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
8628 && (i = exact_log2 (constop)) >= 0)
8629 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
8631 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8632 or XOR, then try to apply the distributive law. This may eliminate
8633 operations if either branch can be simplified because of the AND.
8634 It may also make some cases more complex, but those cases probably
8635 won't match a pattern either with or without this. */
8637 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
8641 apply_distributive_law
8642 (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
8643 simplify_and_const_int (NULL_RTX,
8647 simplify_and_const_int (NULL_RTX,
8652 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
8653 the AND and see if one of the operands simplifies to zero. If so, we
8654 may eliminate it. */
8656 if (GET_CODE (varop) == PLUS
8657 && exact_log2 (constop + 1) >= 0)
8661 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
8662 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
8663 if (o0 == const0_rtx)
8665 if (o1 == const0_rtx)
8669 /* Make a SUBREG if necessary. If we can't make it, fail. */
8670 varop = gen_lowpart (mode, varop);
8671 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
8674 /* If we are only masking insignificant bits, return VAROP. */
8675 if (constop == nonzero)
8678 if (varop == orig_varop && constop == orig_constop)
8681 /* Otherwise, return an AND. */
8682 return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode));
8686 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
8689 Return an equivalent form, if different from X. Otherwise, return X. If
8690 X is zero, we are to always construct the equivalent form. */
8693 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
8694 unsigned HOST_WIDE_INT constop)
8696 rtx tem = simplify_and_const_int_1 (mode, varop, constop);
8701 x = simplify_gen_binary (AND, GET_MODE (varop), varop,
8702 gen_int_mode (constop, mode));
8703 if (GET_MODE (x) != mode)
8704 x = gen_lowpart (mode, x);
8708 /* Given a REG, X, compute which bits in X can be nonzero.
8709 We don't care about bits outside of those defined in MODE.
8711 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8712 a shift, AND, or zero_extract, we can do better. */
8715 reg_nonzero_bits_for_combine (const_rtx x, enum machine_mode mode,
8716 const_rtx known_x ATTRIBUTE_UNUSED,
8717 enum machine_mode known_mode ATTRIBUTE_UNUSED,
8718 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
8719 unsigned HOST_WIDE_INT *nonzero)
8724 /* If X is a register whose nonzero bits value is current, use it.
8725 Otherwise, if X is a register whose value we can find, use that
8726 value. Otherwise, use the previously-computed global nonzero bits
8727 for this register. */
8729 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
8730 if (rsp->last_set_value != 0
8731 && (rsp->last_set_mode == mode
8732 || (GET_MODE_CLASS (rsp->last_set_mode) == MODE_INT
8733 && GET_MODE_CLASS (mode) == MODE_INT))
8734 && ((rsp->last_set_label >= label_tick_ebb_start
8735 && rsp->last_set_label < label_tick)
8736 || (rsp->last_set_label == label_tick
8737 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
8738 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8739 && REG_N_SETS (REGNO (x)) == 1
8741 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
8743 *nonzero &= rsp->last_set_nonzero_bits;
8747 tem = get_last_value (x);
8751 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8752 /* If X is narrower than MODE and TEM is a non-negative
8753 constant that would appear negative in the mode of X,
8754 sign-extend it for use in reg_nonzero_bits because some
8755 machines (maybe most) will actually do the sign-extension
8756 and this is the conservative approach.
8758 ??? For 2.5, try to tighten up the MD files in this regard
8759 instead of this kludge. */
8761 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode)
8762 && GET_CODE (tem) == CONST_INT
8764 && 0 != (INTVAL (tem)
8765 & ((HOST_WIDE_INT) 1
8766 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8767 tem = GEN_INT (INTVAL (tem)
8768 | ((HOST_WIDE_INT) (-1)
8769 << GET_MODE_BITSIZE (GET_MODE (x))));
8773 else if (nonzero_sign_valid && rsp->nonzero_bits)
8775 unsigned HOST_WIDE_INT mask = rsp->nonzero_bits;
8777 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode))
8778 /* We don't know anything about the upper bits. */
8779 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
8786 /* Return the number of bits at the high-order end of X that are known to
8787 be equal to the sign bit. X will be used in mode MODE; if MODE is
8788 VOIDmode, X will be used in its own mode. The returned value will always
8789 be between 1 and the number of bits in MODE. */
8792 reg_num_sign_bit_copies_for_combine (const_rtx x, enum machine_mode mode,
8793 const_rtx known_x ATTRIBUTE_UNUSED,
8794 enum machine_mode known_mode
8796 unsigned int known_ret ATTRIBUTE_UNUSED,
8797 unsigned int *result)
8802 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
8803 if (rsp->last_set_value != 0
8804 && rsp->last_set_mode == mode
8805 && ((rsp->last_set_label >= label_tick_ebb_start
8806 && rsp->last_set_label < label_tick)
8807 || (rsp->last_set_label == label_tick
8808 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
8809 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8810 && REG_N_SETS (REGNO (x)) == 1
8812 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
8814 *result = rsp->last_set_sign_bit_copies;
8818 tem = get_last_value (x);
8822 if (nonzero_sign_valid && rsp->sign_bit_copies != 0
8823 && GET_MODE_BITSIZE (GET_MODE (x)) == GET_MODE_BITSIZE (mode))
8824 *result = rsp->sign_bit_copies;
8829 /* Return the number of "extended" bits there are in X, when interpreted
8830 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8831 unsigned quantities, this is the number of high-order zero bits.
8832 For signed quantities, this is the number of copies of the sign bit
8833 minus 1. In both case, this function returns the number of "spare"
8834 bits. For example, if two quantities for which this function returns
8835 at least 1 are added, the addition is known not to overflow.
8837 This function will always return 0 unless called during combine, which
8838 implies that it must be called from a define_split. */
8841 extended_count (const_rtx x, enum machine_mode mode, int unsignedp)
8843 if (nonzero_sign_valid == 0)
8847 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8848 ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
8849 - floor_log2 (nonzero_bits (x, mode)))
8851 : num_sign_bit_copies (x, mode) - 1);
8854 /* This function is called from `simplify_shift_const' to merge two
8855 outer operations. Specifically, we have already found that we need
8856 to perform operation *POP0 with constant *PCONST0 at the outermost
8857 position. We would now like to also perform OP1 with constant CONST1
8858 (with *POP0 being done last).
8860 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8861 the resulting operation. *PCOMP_P is set to 1 if we would need to
8862 complement the innermost operand, otherwise it is unchanged.
8864 MODE is the mode in which the operation will be done. No bits outside
8865 the width of this mode matter. It is assumed that the width of this mode
8866 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8868 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
8869 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8870 result is simply *PCONST0.
8872 If the resulting operation cannot be expressed as one operation, we
8873 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8876 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
8878 enum rtx_code op0 = *pop0;
8879 HOST_WIDE_INT const0 = *pconst0;
8881 const0 &= GET_MODE_MASK (mode);
8882 const1 &= GET_MODE_MASK (mode);
8884 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8888 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
8891 if (op1 == UNKNOWN || op0 == SET)
8894 else if (op0 == UNKNOWN)
8895 op0 = op1, const0 = const1;
8897 else if (op0 == op1)
8921 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8922 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8925 /* If the two constants aren't the same, we can't do anything. The
8926 remaining six cases can all be done. */
8927 else if (const0 != const1)
8935 /* (a & b) | b == b */
8937 else /* op1 == XOR */
8938 /* (a ^ b) | b == a | b */
8944 /* (a & b) ^ b == (~a) & b */
8945 op0 = AND, *pcomp_p = 1;
8946 else /* op1 == IOR */
8947 /* (a | b) ^ b == a & ~b */
8948 op0 = AND, const0 = ~const0;
8953 /* (a | b) & b == b */
8955 else /* op1 == XOR */
8956 /* (a ^ b) & b) == (~a) & b */
8963 /* Check for NO-OP cases. */
8964 const0 &= GET_MODE_MASK (mode);
8966 && (op0 == IOR || op0 == XOR || op0 == PLUS))
8968 else if (const0 == 0 && op0 == AND)
8970 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8976 /* ??? Slightly redundant with the above mask, but not entirely.
8977 Moving this above means we'd have to sign-extend the mode mask
8978 for the final test. */
8979 if (op0 != UNKNOWN && op0 != NEG)
8980 *pconst0 = trunc_int_for_mode (const0, mode);
8985 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8986 The result of the shift is RESULT_MODE. Return NULL_RTX if we cannot
8987 simplify it. Otherwise, return a simplified value.
8989 The shift is normally computed in the widest mode we find in VAROP, as
8990 long as it isn't a different number of words than RESULT_MODE. Exceptions
8991 are ASHIFTRT and ROTATE, which are always done in their original mode. */
8994 simplify_shift_const_1 (enum rtx_code code, enum machine_mode result_mode,
8995 rtx varop, int orig_count)
8997 enum rtx_code orig_code = code;
8998 rtx orig_varop = varop;
9000 enum machine_mode mode = result_mode;
9001 enum machine_mode shift_mode, tmode;
9002 unsigned int mode_words
9003 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
9004 /* We form (outer_op (code varop count) (outer_const)). */
9005 enum rtx_code outer_op = UNKNOWN;
9006 HOST_WIDE_INT outer_const = 0;
9007 int complement_p = 0;
9010 /* Make sure and truncate the "natural" shift on the way in. We don't
9011 want to do this inside the loop as it makes it more difficult to
9013 if (SHIFT_COUNT_TRUNCATED)
9014 orig_count &= GET_MODE_BITSIZE (mode) - 1;
9016 /* If we were given an invalid count, don't do anything except exactly
9017 what was requested. */
9019 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
9024 /* Unless one of the branches of the `if' in this loop does a `continue',
9025 we will `break' the loop after the `if'. */
9029 /* If we have an operand of (clobber (const_int 0)), fail. */
9030 if (GET_CODE (varop) == CLOBBER)
9033 /* Convert ROTATERT to ROTATE. */
9034 if (code == ROTATERT)
9036 unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
9038 if (VECTOR_MODE_P (result_mode))
9039 count = bitsize / GET_MODE_NUNITS (result_mode) - count;
9041 count = bitsize - count;
9044 /* We need to determine what mode we will do the shift in. If the
9045 shift is a right shift or a ROTATE, we must always do it in the mode
9046 it was originally done in. Otherwise, we can do it in MODE, the
9047 widest mode encountered. */
9049 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9050 ? result_mode : mode);
9052 /* Handle cases where the count is greater than the size of the mode
9053 minus 1. For ASHIFT, use the size minus one as the count (this can
9054 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9055 take the count modulo the size. For other shifts, the result is
9058 Since these shifts are being produced by the compiler by combining
9059 multiple operations, each of which are defined, we know what the
9060 result is supposed to be. */
9062 if (count > (GET_MODE_BITSIZE (shift_mode) - 1))
9064 if (code == ASHIFTRT)
9065 count = GET_MODE_BITSIZE (shift_mode) - 1;
9066 else if (code == ROTATE || code == ROTATERT)
9067 count %= GET_MODE_BITSIZE (shift_mode);
9070 /* We can't simply return zero because there may be an
9078 /* If we discovered we had to complement VAROP, leave. Making a NOT
9079 here would cause an infinite loop. */
9083 /* An arithmetic right shift of a quantity known to be -1 or 0
9085 if (code == ASHIFTRT
9086 && (num_sign_bit_copies (varop, shift_mode)
9087 == GET_MODE_BITSIZE (shift_mode)))
9093 /* If we are doing an arithmetic right shift and discarding all but
9094 the sign bit copies, this is equivalent to doing a shift by the
9095 bitsize minus one. Convert it into that shift because it will often
9096 allow other simplifications. */
9098 if (code == ASHIFTRT
9099 && (count + num_sign_bit_copies (varop, shift_mode)
9100 >= GET_MODE_BITSIZE (shift_mode)))
9101 count = GET_MODE_BITSIZE (shift_mode) - 1;
9103 /* We simplify the tests below and elsewhere by converting
9104 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9105 `make_compound_operation' will convert it to an ASHIFTRT for
9106 those machines (such as VAX) that don't have an LSHIFTRT. */
9107 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9109 && ((nonzero_bits (varop, shift_mode)
9110 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
9114 if (((code == LSHIFTRT
9115 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9116 && !(nonzero_bits (varop, shift_mode) >> count))
9118 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9119 && !((nonzero_bits (varop, shift_mode) << count)
9120 & GET_MODE_MASK (shift_mode))))
9121 && !side_effects_p (varop))
9124 switch (GET_CODE (varop))
9130 new_rtx = expand_compound_operation (varop);
9131 if (new_rtx != varop)
9139 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9140 minus the width of a smaller mode, we can do this with a
9141 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9142 if ((code == ASHIFTRT || code == LSHIFTRT)
9143 && ! mode_dependent_address_p (XEXP (varop, 0))
9144 && ! MEM_VOLATILE_P (varop)
9145 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9146 MODE_INT, 1)) != BLKmode)
9148 new_rtx = adjust_address_nv (varop, tmode,
9149 BYTES_BIG_ENDIAN ? 0
9150 : count / BITS_PER_UNIT);
9152 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9153 : ZERO_EXTEND, mode, new_rtx);
9160 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9161 the same number of words as what we've seen so far. Then store
9162 the widest mode in MODE. */
9163 if (subreg_lowpart_p (varop)
9164 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9165 > GET_MODE_SIZE (GET_MODE (varop)))
9166 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9167 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9170 varop = SUBREG_REG (varop);
9171 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
9172 mode = GET_MODE (varop);
9178 /* Some machines use MULT instead of ASHIFT because MULT
9179 is cheaper. But it is still better on those machines to
9180 merge two shifts into one. */
9181 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9182 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9185 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
9187 GEN_INT (exact_log2 (
9188 INTVAL (XEXP (varop, 1)))));
9194 /* Similar, for when divides are cheaper. */
9195 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9196 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9199 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
9201 GEN_INT (exact_log2 (
9202 INTVAL (XEXP (varop, 1)))));
9208 /* If we are extracting just the sign bit of an arithmetic
9209 right shift, that shift is not needed. However, the sign
9210 bit of a wider mode may be different from what would be
9211 interpreted as the sign bit in a narrower mode, so, if
9212 the result is narrower, don't discard the shift. */
9213 if (code == LSHIFTRT
9214 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9215 && (GET_MODE_BITSIZE (result_mode)
9216 >= GET_MODE_BITSIZE (GET_MODE (varop))))
9218 varop = XEXP (varop, 0);
9222 /* ... fall through ... */
9227 /* Here we have two nested shifts. The result is usually the
9228 AND of a new shift with a mask. We compute the result below. */
9229 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9230 && INTVAL (XEXP (varop, 1)) >= 0
9231 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
9232 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9233 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9234 && !VECTOR_MODE_P (result_mode))
9236 enum rtx_code first_code = GET_CODE (varop);
9237 unsigned int first_count = INTVAL (XEXP (varop, 1));
9238 unsigned HOST_WIDE_INT mask;
9241 /* We have one common special case. We can't do any merging if
9242 the inner code is an ASHIFTRT of a smaller mode. However, if
9243 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9244 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9245 we can convert it to
9246 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9247 This simplifies certain SIGN_EXTEND operations. */
9248 if (code == ASHIFT && first_code == ASHIFTRT
9249 && count == (GET_MODE_BITSIZE (result_mode)
9250 - GET_MODE_BITSIZE (GET_MODE (varop))))
9252 /* C3 has the low-order C1 bits zero. */
9254 mask = (GET_MODE_MASK (mode)
9255 & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
9257 varop = simplify_and_const_int (NULL_RTX, result_mode,
9258 XEXP (varop, 0), mask);
9259 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
9261 count = first_count;
9266 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9267 than C1 high-order bits equal to the sign bit, we can convert
9268 this to either an ASHIFT or an ASHIFTRT depending on the
9271 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9273 if (code == ASHIFTRT && first_code == ASHIFT
9274 && GET_MODE (varop) == shift_mode
9275 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
9278 varop = XEXP (varop, 0);
9279 count -= first_count;
9289 /* There are some cases we can't do. If CODE is ASHIFTRT,
9290 we can only do this if FIRST_CODE is also ASHIFTRT.
9292 We can't do the case when CODE is ROTATE and FIRST_CODE is
9295 If the mode of this shift is not the mode of the outer shift,
9296 we can't do this if either shift is a right shift or ROTATE.
9298 Finally, we can't do any of these if the mode is too wide
9299 unless the codes are the same.
9301 Handle the case where the shift codes are the same
9304 if (code == first_code)
9306 if (GET_MODE (varop) != result_mode
9307 && (code == ASHIFTRT || code == LSHIFTRT
9311 count += first_count;
9312 varop = XEXP (varop, 0);
9316 if (code == ASHIFTRT
9317 || (code == ROTATE && first_code == ASHIFTRT)
9318 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
9319 || (GET_MODE (varop) != result_mode
9320 && (first_code == ASHIFTRT || first_code == LSHIFTRT
9321 || first_code == ROTATE
9322 || code == ROTATE)))
9325 /* To compute the mask to apply after the shift, shift the
9326 nonzero bits of the inner shift the same way the
9327 outer shift will. */
9329 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
9332 = simplify_const_binary_operation (code, result_mode, mask_rtx,
9335 /* Give up if we can't compute an outer operation to use. */
9337 || GET_CODE (mask_rtx) != CONST_INT
9338 || ! merge_outer_ops (&outer_op, &outer_const, AND,
9340 result_mode, &complement_p))
9343 /* If the shifts are in the same direction, we add the
9344 counts. Otherwise, we subtract them. */
9345 if ((code == ASHIFTRT || code == LSHIFTRT)
9346 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
9347 count += first_count;
9349 count -= first_count;
9351 /* If COUNT is positive, the new shift is usually CODE,
9352 except for the two exceptions below, in which case it is
9353 FIRST_CODE. If the count is negative, FIRST_CODE should
9356 && ((first_code == ROTATE && code == ASHIFT)
9357 || (first_code == ASHIFTRT && code == LSHIFTRT)))
9360 code = first_code, count = -count;
9362 varop = XEXP (varop, 0);
9366 /* If we have (A << B << C) for any shift, we can convert this to
9367 (A << C << B). This wins if A is a constant. Only try this if
9368 B is not a constant. */
9370 else if (GET_CODE (varop) == code
9371 && GET_CODE (XEXP (varop, 0)) == CONST_INT
9372 && GET_CODE (XEXP (varop, 1)) != CONST_INT)
9374 rtx new_rtx = simplify_const_binary_operation (code, mode,
9377 varop = gen_rtx_fmt_ee (code, mode, new_rtx, XEXP (varop, 1));
9384 if (VECTOR_MODE_P (mode))
9387 /* Make this fit the case below. */
9388 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
9389 GEN_INT (GET_MODE_MASK (mode)));
9395 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9396 with C the size of VAROP - 1 and the shift is logical if
9397 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9398 we have an (le X 0) operation. If we have an arithmetic shift
9399 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9400 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9402 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
9403 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
9404 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9405 && (code == LSHIFTRT || code == ASHIFTRT)
9406 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9407 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9410 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
9413 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9414 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9419 /* If we have (shift (logical)), move the logical to the outside
9420 to allow it to possibly combine with another logical and the
9421 shift to combine with another shift. This also canonicalizes to
9422 what a ZERO_EXTRACT looks like. Also, some machines have
9423 (and (shift)) insns. */
9425 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9426 /* We can't do this if we have (ashiftrt (xor)) and the
9427 constant has its sign bit set in shift_mode. */
9428 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
9429 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
9431 && (new_rtx = simplify_const_binary_operation (code, result_mode,
9433 GEN_INT (count))) != 0
9434 && GET_CODE (new_rtx) == CONST_INT
9435 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
9436 INTVAL (new_rtx), result_mode, &complement_p))
9438 varop = XEXP (varop, 0);
9442 /* If we can't do that, try to simplify the shift in each arm of the
9443 logical expression, make a new logical expression, and apply
9444 the inverse distributive law. This also can't be done
9445 for some (ashiftrt (xor)). */
9446 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9447 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
9448 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
9451 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9452 XEXP (varop, 0), count);
9453 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9454 XEXP (varop, 1), count);
9456 varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
9458 varop = apply_distributive_law (varop);
9466 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9467 says that the sign bit can be tested, FOO has mode MODE, C is
9468 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9469 that may be nonzero. */
9470 if (code == LSHIFTRT
9471 && XEXP (varop, 1) == const0_rtx
9472 && GET_MODE (XEXP (varop, 0)) == result_mode
9473 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9474 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9475 && STORE_FLAG_VALUE == -1
9476 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9477 && merge_outer_ops (&outer_op, &outer_const, XOR,
9478 (HOST_WIDE_INT) 1, result_mode,
9481 varop = XEXP (varop, 0);
9488 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9489 than the number of bits in the mode is equivalent to A. */
9490 if (code == LSHIFTRT
9491 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9492 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9494 varop = XEXP (varop, 0);
9499 /* NEG commutes with ASHIFT since it is multiplication. Move the
9500 NEG outside to allow shifts to combine. */
9502 && merge_outer_ops (&outer_op, &outer_const, NEG,
9503 (HOST_WIDE_INT) 0, result_mode,
9506 varop = XEXP (varop, 0);
9512 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9513 is one less than the number of bits in the mode is
9514 equivalent to (xor A 1). */
9515 if (code == LSHIFTRT
9516 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9517 && XEXP (varop, 1) == constm1_rtx
9518 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9519 && merge_outer_ops (&outer_op, &outer_const, XOR,
9520 (HOST_WIDE_INT) 1, result_mode,
9524 varop = XEXP (varop, 0);
9528 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9529 that might be nonzero in BAR are those being shifted out and those
9530 bits are known zero in FOO, we can replace the PLUS with FOO.
9531 Similarly in the other operand order. This code occurs when
9532 we are computing the size of a variable-size array. */
9534 if ((code == ASHIFTRT || code == LSHIFTRT)
9535 && count < HOST_BITS_PER_WIDE_INT
9536 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9537 && (nonzero_bits (XEXP (varop, 1), result_mode)
9538 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9540 varop = XEXP (varop, 0);
9543 else if ((code == ASHIFTRT || code == LSHIFTRT)
9544 && count < HOST_BITS_PER_WIDE_INT
9545 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9546 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9548 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9549 & nonzero_bits (XEXP (varop, 1),
9552 varop = XEXP (varop, 1);
9556 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9558 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9559 && (new_rtx = simplify_const_binary_operation (ASHIFT, result_mode,
9561 GEN_INT (count))) != 0
9562 && GET_CODE (new_rtx) == CONST_INT
9563 && merge_outer_ops (&outer_op, &outer_const, PLUS,
9564 INTVAL (new_rtx), result_mode, &complement_p))
9566 varop = XEXP (varop, 0);
9570 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
9571 signbit', and attempt to change the PLUS to an XOR and move it to
9572 the outer operation as is done above in the AND/IOR/XOR case
9573 leg for shift(logical). See details in logical handling above
9574 for reasoning in doing so. */
9575 if (code == LSHIFTRT
9576 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9577 && mode_signbit_p (result_mode, XEXP (varop, 1))
9578 && (new_rtx = simplify_const_binary_operation (code, result_mode,
9580 GEN_INT (count))) != 0
9581 && GET_CODE (new_rtx) == CONST_INT
9582 && merge_outer_ops (&outer_op, &outer_const, XOR,
9583 INTVAL (new_rtx), result_mode, &complement_p))
9585 varop = XEXP (varop, 0);
9592 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9593 with C the size of VAROP - 1 and the shift is logical if
9594 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9595 we have a (gt X 0) operation. If the shift is arithmetic with
9596 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9597 we have a (neg (gt X 0)) operation. */
9599 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9600 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9601 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9602 && (code == LSHIFTRT || code == ASHIFTRT)
9603 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9604 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
9605 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9608 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9611 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9612 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9619 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9620 if the truncate does not affect the value. */
9621 if (code == LSHIFTRT
9622 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9623 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9624 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9625 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9626 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9628 rtx varop_inner = XEXP (varop, 0);
9631 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9632 XEXP (varop_inner, 0),
9634 (count + INTVAL (XEXP (varop_inner, 1))));
9635 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9648 /* We need to determine what mode to do the shift in. If the shift is
9649 a right shift or ROTATE, we must always do it in the mode it was
9650 originally done in. Otherwise, we can do it in MODE, the widest mode
9651 encountered. The code we care about is that of the shift that will
9652 actually be done, not the shift that was originally requested. */
9654 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9655 ? result_mode : mode);
9657 /* We have now finished analyzing the shift. The result should be
9658 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9659 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
9660 to the result of the shift. OUTER_CONST is the relevant constant,
9661 but we must turn off all bits turned off in the shift. */
9663 if (outer_op == UNKNOWN
9664 && orig_code == code && orig_count == count
9665 && varop == orig_varop
9666 && shift_mode == GET_MODE (varop))
9669 /* Make a SUBREG if necessary. If we can't make it, fail. */
9670 varop = gen_lowpart (shift_mode, varop);
9671 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
9674 /* If we have an outer operation and we just made a shift, it is
9675 possible that we could have simplified the shift were it not
9676 for the outer operation. So try to do the simplification
9679 if (outer_op != UNKNOWN)
9680 x = simplify_shift_const_1 (code, shift_mode, varop, count);
9685 x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count));
9687 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9688 turn off all the bits that the shift would have turned off. */
9689 if (orig_code == LSHIFTRT && result_mode != shift_mode)
9690 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9691 GET_MODE_MASK (result_mode) >> orig_count);
9693 /* Do the remainder of the processing in RESULT_MODE. */
9694 x = gen_lowpart_or_truncate (result_mode, x);
9696 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9699 x = simplify_gen_unary (NOT, result_mode, x, result_mode);
9701 if (outer_op != UNKNOWN)
9703 if (GET_RTX_CLASS (outer_op) != RTX_UNARY
9704 && GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9705 outer_const = trunc_int_for_mode (outer_const, result_mode);
9707 if (outer_op == AND)
9708 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9709 else if (outer_op == SET)
9711 /* This means that we have determined that the result is
9712 equivalent to a constant. This should be rare. */
9713 if (!side_effects_p (x))
9714 x = GEN_INT (outer_const);
9716 else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
9717 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
9719 x = simplify_gen_binary (outer_op, result_mode, x,
9720 GEN_INT (outer_const));
9726 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9727 The result of the shift is RESULT_MODE. If we cannot simplify it,
9728 return X or, if it is NULL, synthesize the expression with
9729 simplify_gen_binary. Otherwise, return a simplified value.
9731 The shift is normally computed in the widest mode we find in VAROP, as
9732 long as it isn't a different number of words than RESULT_MODE. Exceptions
9733 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9736 simplify_shift_const (rtx x, enum rtx_code code, enum machine_mode result_mode,
9737 rtx varop, int count)
9739 rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
9744 x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count));
9745 if (GET_MODE (x) != result_mode)
9746 x = gen_lowpart (result_mode, x);
9751 /* Like recog, but we receive the address of a pointer to a new pattern.
9752 We try to match the rtx that the pointer points to.
9753 If that fails, we may try to modify or replace the pattern,
9754 storing the replacement into the same pointer object.
9756 Modifications include deletion or addition of CLOBBERs.
9758 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9759 the CLOBBERs are placed.
9761 The value is the final insn code from the pattern ultimately matched,
9765 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
9768 int insn_code_number;
9769 int num_clobbers_to_add = 0;
9772 rtx old_notes, old_pat;
9774 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9775 we use to indicate that something didn't match. If we find such a
9776 thing, force rejection. */
9777 if (GET_CODE (pat) == PARALLEL)
9778 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9779 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9780 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9783 old_pat = PATTERN (insn);
9784 old_notes = REG_NOTES (insn);
9785 PATTERN (insn) = pat;
9786 REG_NOTES (insn) = 0;
9788 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9789 if (dump_file && (dump_flags & TDF_DETAILS))
9791 if (insn_code_number < 0)
9792 fputs ("Failed to match this instruction:\n", dump_file);
9794 fputs ("Successfully matched this instruction:\n", dump_file);
9795 print_rtl_single (dump_file, pat);
9798 /* If it isn't, there is the possibility that we previously had an insn
9799 that clobbered some register as a side effect, but the combined
9800 insn doesn't need to do that. So try once more without the clobbers
9801 unless this represents an ASM insn. */
9803 if (insn_code_number < 0 && ! check_asm_operands (pat)
9804 && GET_CODE (pat) == PARALLEL)
9808 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9809 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9812 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9816 SUBST_INT (XVECLEN (pat, 0), pos);
9819 pat = XVECEXP (pat, 0, 0);
9821 PATTERN (insn) = pat;
9822 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9823 if (dump_file && (dump_flags & TDF_DETAILS))
9825 if (insn_code_number < 0)
9826 fputs ("Failed to match this instruction:\n", dump_file);
9828 fputs ("Successfully matched this instruction:\n", dump_file);
9829 print_rtl_single (dump_file, pat);
9832 PATTERN (insn) = old_pat;
9833 REG_NOTES (insn) = old_notes;
9835 /* Recognize all noop sets, these will be killed by followup pass. */
9836 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
9837 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
9839 /* If we had any clobbers to add, make a new pattern than contains
9840 them. Then check to make sure that all of them are dead. */
9841 if (num_clobbers_to_add)
9843 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9844 rtvec_alloc (GET_CODE (pat) == PARALLEL
9846 + num_clobbers_to_add)
9847 : num_clobbers_to_add + 1));
9849 if (GET_CODE (pat) == PARALLEL)
9850 for (i = 0; i < XVECLEN (pat, 0); i++)
9851 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9853 XVECEXP (newpat, 0, 0) = pat;
9855 add_clobbers (newpat, insn_code_number);
9857 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9858 i < XVECLEN (newpat, 0); i++)
9860 if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
9861 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9863 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) != SCRATCH)
9865 gcc_assert (REG_P (XEXP (XVECEXP (newpat, 0, i), 0)));
9866 notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9867 XEXP (XVECEXP (newpat, 0, i), 0), notes);
9876 return insn_code_number;
9879 /* Like gen_lowpart_general but for use by combine. In combine it
9880 is not possible to create any new pseudoregs. However, it is
9881 safe to create invalid memory addresses, because combine will
9882 try to recognize them and all they will do is make the combine
9885 If for some reason this cannot do its job, an rtx
9886 (clobber (const_int 0)) is returned.
9887 An insn containing that will not be recognized. */
9890 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
9892 enum machine_mode imode = GET_MODE (x);
9893 unsigned int osize = GET_MODE_SIZE (omode);
9894 unsigned int isize = GET_MODE_SIZE (imode);
9900 /* Return identity if this is a CONST or symbolic reference. */
9902 && (GET_CODE (x) == CONST
9903 || GET_CODE (x) == SYMBOL_REF
9904 || GET_CODE (x) == LABEL_REF))
9907 /* We can only support MODE being wider than a word if X is a
9908 constant integer or has a mode the same size. */
9909 if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
9910 && ! ((imode == VOIDmode
9911 && (GET_CODE (x) == CONST_INT
9912 || GET_CODE (x) == CONST_DOUBLE))
9916 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9917 won't know what to do. So we will strip off the SUBREG here and
9918 process normally. */
9919 if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
9923 /* For use in case we fall down into the address adjustments
9924 further below, we need to adjust the known mode and size of
9925 x; imode and isize, since we just adjusted x. */
9926 imode = GET_MODE (x);
9931 isize = GET_MODE_SIZE (imode);
9934 result = gen_lowpart_common (omode, x);
9943 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9945 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9948 /* If we want to refer to something bigger than the original memref,
9949 generate a paradoxical subreg instead. That will force a reload
9950 of the original memref X. */
9952 return gen_rtx_SUBREG (omode, x, 0);
9954 if (WORDS_BIG_ENDIAN)
9955 offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
9957 /* Adjust the address so that the address-after-the-data is
9959 if (BYTES_BIG_ENDIAN)
9960 offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
9962 return adjust_address_nv (x, omode, offset);
9965 /* If X is a comparison operator, rewrite it in a new mode. This
9966 probably won't match, but may allow further simplifications. */
9967 else if (COMPARISON_P (x))
9968 return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
9970 /* If we couldn't simplify X any other way, just enclose it in a
9971 SUBREG. Normally, this SUBREG won't match, but some patterns may
9972 include an explicit SUBREG or we may simplify it further in combine. */
9978 offset = subreg_lowpart_offset (omode, imode);
9979 if (imode == VOIDmode)
9981 imode = int_mode_for_mode (omode);
9982 x = gen_lowpart_common (imode, x);
9986 res = simplify_gen_subreg (omode, x, imode, offset);
9992 return gen_rtx_CLOBBER (omode, const0_rtx);
9995 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9996 comparison code that will be tested.
9998 The result is a possibly different comparison code to use. *POP0 and
9999 *POP1 may be updated.
10001 It is possible that we might detect that a comparison is either always
10002 true or always false. However, we do not perform general constant
10003 folding in combine, so this knowledge isn't useful. Such tautologies
10004 should have been detected earlier. Hence we ignore all such cases. */
10006 static enum rtx_code
10007 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
10013 enum machine_mode mode, tmode;
10015 /* Try a few ways of applying the same transformation to both operands. */
10018 #ifndef WORD_REGISTER_OPERATIONS
10019 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10020 so check specially. */
10021 if (code != GTU && code != GEU && code != LTU && code != LEU
10022 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
10023 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10024 && GET_CODE (XEXP (op1, 0)) == ASHIFT
10025 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
10026 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
10027 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
10028 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
10029 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10030 && XEXP (op0, 1) == XEXP (op1, 1)
10031 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10032 && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
10033 && (INTVAL (XEXP (op0, 1))
10034 == (GET_MODE_BITSIZE (GET_MODE (op0))
10035 - (GET_MODE_BITSIZE
10036 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
10038 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
10039 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
10043 /* If both operands are the same constant shift, see if we can ignore the
10044 shift. We can if the shift is a rotate or if the bits shifted out of
10045 this shift are known to be zero for both inputs and if the type of
10046 comparison is compatible with the shift. */
10047 if (GET_CODE (op0) == GET_CODE (op1)
10048 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10049 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
10050 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
10051 && (code != GT && code != LT && code != GE && code != LE))
10052 || (GET_CODE (op0) == ASHIFTRT
10053 && (code != GTU && code != LTU
10054 && code != GEU && code != LEU)))
10055 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10056 && INTVAL (XEXP (op0, 1)) >= 0
10057 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10058 && XEXP (op0, 1) == XEXP (op1, 1))
10060 enum machine_mode mode = GET_MODE (op0);
10061 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10062 int shift_count = INTVAL (XEXP (op0, 1));
10064 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
10065 mask &= (mask >> shift_count) << shift_count;
10066 else if (GET_CODE (op0) == ASHIFT)
10067 mask = (mask & (mask << shift_count)) >> shift_count;
10069 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
10070 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
10071 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
10076 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10077 SUBREGs are of the same mode, and, in both cases, the AND would
10078 be redundant if the comparison was done in the narrower mode,
10079 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10080 and the operand's possibly nonzero bits are 0xffffff01; in that case
10081 if we only care about QImode, we don't need the AND). This case
10082 occurs if the output mode of an scc insn is not SImode and
10083 STORE_FLAG_VALUE == 1 (e.g., the 386).
10085 Similarly, check for a case where the AND's are ZERO_EXTEND
10086 operations from some narrower mode even though a SUBREG is not
10089 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
10090 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10091 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
10093 rtx inner_op0 = XEXP (op0, 0);
10094 rtx inner_op1 = XEXP (op1, 0);
10095 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
10096 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
10099 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
10100 && (GET_MODE_SIZE (GET_MODE (inner_op0))
10101 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
10102 && (GET_MODE (SUBREG_REG (inner_op0))
10103 == GET_MODE (SUBREG_REG (inner_op1)))
10104 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
10105 <= HOST_BITS_PER_WIDE_INT)
10106 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
10107 GET_MODE (SUBREG_REG (inner_op0)))))
10108 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
10109 GET_MODE (SUBREG_REG (inner_op1))))))
10111 op0 = SUBREG_REG (inner_op0);
10112 op1 = SUBREG_REG (inner_op1);
10114 /* The resulting comparison is always unsigned since we masked
10115 off the original sign bit. */
10116 code = unsigned_condition (code);
10122 for (tmode = GET_CLASS_NARROWEST_MODE
10123 (GET_MODE_CLASS (GET_MODE (op0)));
10124 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
10125 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
10127 op0 = gen_lowpart (tmode, inner_op0);
10128 op1 = gen_lowpart (tmode, inner_op1);
10129 code = unsigned_condition (code);
10138 /* If both operands are NOT, we can strip off the outer operation
10139 and adjust the comparison code for swapped operands; similarly for
10140 NEG, except that this must be an equality comparison. */
10141 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
10142 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
10143 && (code == EQ || code == NE)))
10144 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
10150 /* If the first operand is a constant, swap the operands and adjust the
10151 comparison code appropriately, but don't do this if the second operand
10152 is already a constant integer. */
10153 if (swap_commutative_operands_p (op0, op1))
10155 tem = op0, op0 = op1, op1 = tem;
10156 code = swap_condition (code);
10159 /* We now enter a loop during which we will try to simplify the comparison.
10160 For the most part, we only are concerned with comparisons with zero,
10161 but some things may really be comparisons with zero but not start
10162 out looking that way. */
10164 while (GET_CODE (op1) == CONST_INT)
10166 enum machine_mode mode = GET_MODE (op0);
10167 unsigned int mode_width = GET_MODE_BITSIZE (mode);
10168 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10169 int equality_comparison_p;
10170 int sign_bit_comparison_p;
10171 int unsigned_comparison_p;
10172 HOST_WIDE_INT const_op;
10174 /* We only want to handle integral modes. This catches VOIDmode,
10175 CCmode, and the floating-point modes. An exception is that we
10176 can handle VOIDmode if OP0 is a COMPARE or a comparison
10179 if (GET_MODE_CLASS (mode) != MODE_INT
10180 && ! (mode == VOIDmode
10181 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
10184 /* Get the constant we are comparing against and turn off all bits
10185 not on in our mode. */
10186 const_op = INTVAL (op1);
10187 if (mode != VOIDmode)
10188 const_op = trunc_int_for_mode (const_op, mode);
10189 op1 = GEN_INT (const_op);
10191 /* If we are comparing against a constant power of two and the value
10192 being compared can only have that single bit nonzero (e.g., it was
10193 `and'ed with that bit), we can replace this with a comparison
10196 && (code == EQ || code == NE || code == GE || code == GEU
10197 || code == LT || code == LTU)
10198 && mode_width <= HOST_BITS_PER_WIDE_INT
10199 && exact_log2 (const_op) >= 0
10200 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
10202 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10203 op1 = const0_rtx, const_op = 0;
10206 /* Similarly, if we are comparing a value known to be either -1 or
10207 0 with -1, change it to the opposite comparison against zero. */
10210 && (code == EQ || code == NE || code == GT || code == LE
10211 || code == GEU || code == LTU)
10212 && num_sign_bit_copies (op0, mode) == mode_width)
10214 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10215 op1 = const0_rtx, const_op = 0;
10218 /* Do some canonicalizations based on the comparison code. We prefer
10219 comparisons against zero and then prefer equality comparisons.
10220 If we can reduce the size of a constant, we will do that too. */
10225 /* < C is equivalent to <= (C - 1) */
10229 op1 = GEN_INT (const_op);
10231 /* ... fall through to LE case below. */
10237 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10241 op1 = GEN_INT (const_op);
10245 /* If we are doing a <= 0 comparison on a value known to have
10246 a zero sign bit, we can replace this with == 0. */
10247 else if (const_op == 0
10248 && mode_width <= HOST_BITS_PER_WIDE_INT
10249 && (nonzero_bits (op0, mode)
10250 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10255 /* >= C is equivalent to > (C - 1). */
10259 op1 = GEN_INT (const_op);
10261 /* ... fall through to GT below. */
10267 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10271 op1 = GEN_INT (const_op);
10275 /* If we are doing a > 0 comparison on a value known to have
10276 a zero sign bit, we can replace this with != 0. */
10277 else if (const_op == 0
10278 && mode_width <= HOST_BITS_PER_WIDE_INT
10279 && (nonzero_bits (op0, mode)
10280 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10285 /* < C is equivalent to <= (C - 1). */
10289 op1 = GEN_INT (const_op);
10291 /* ... fall through ... */
10294 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10295 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10296 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10298 const_op = 0, op1 = const0_rtx;
10306 /* unsigned <= 0 is equivalent to == 0 */
10310 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10311 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10312 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10314 const_op = 0, op1 = const0_rtx;
10320 /* >= C is equivalent to > (C - 1). */
10324 op1 = GEN_INT (const_op);
10326 /* ... fall through ... */
10329 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10330 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10331 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10333 const_op = 0, op1 = const0_rtx;
10341 /* unsigned > 0 is equivalent to != 0 */
10345 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10346 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10347 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10349 const_op = 0, op1 = const0_rtx;
10358 /* Compute some predicates to simplify code below. */
10360 equality_comparison_p = (code == EQ || code == NE);
10361 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
10362 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
10365 /* If this is a sign bit comparison and we can do arithmetic in
10366 MODE, say that we will only be needing the sign bit of OP0. */
10367 if (sign_bit_comparison_p
10368 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10369 op0 = force_to_mode (op0, mode,
10371 << (GET_MODE_BITSIZE (mode) - 1)),
10374 /* Now try cases based on the opcode of OP0. If none of the cases
10375 does a "continue", we exit this loop immediately after the
10378 switch (GET_CODE (op0))
10381 /* If we are extracting a single bit from a variable position in
10382 a constant that has only a single bit set and are comparing it
10383 with zero, we can convert this into an equality comparison
10384 between the position and the location of the single bit. */
10385 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
10386 have already reduced the shift count modulo the word size. */
10387 if (!SHIFT_COUNT_TRUNCATED
10388 && GET_CODE (XEXP (op0, 0)) == CONST_INT
10389 && XEXP (op0, 1) == const1_rtx
10390 && equality_comparison_p && const_op == 0
10391 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
10393 if (BITS_BIG_ENDIAN)
10395 enum machine_mode new_mode
10396 = mode_for_extraction (EP_extzv, 1);
10397 if (new_mode == MAX_MACHINE_MODE)
10398 i = BITS_PER_WORD - 1 - i;
10402 i = (GET_MODE_BITSIZE (mode) - 1 - i);
10406 op0 = XEXP (op0, 2);
10410 /* Result is nonzero iff shift count is equal to I. */
10411 code = reverse_condition (code);
10415 /* ... fall through ... */
10418 tem = expand_compound_operation (op0);
10427 /* If testing for equality, we can take the NOT of the constant. */
10428 if (equality_comparison_p
10429 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
10431 op0 = XEXP (op0, 0);
10436 /* If just looking at the sign bit, reverse the sense of the
10438 if (sign_bit_comparison_p)
10440 op0 = XEXP (op0, 0);
10441 code = (code == GE ? LT : GE);
10447 /* If testing for equality, we can take the NEG of the constant. */
10448 if (equality_comparison_p
10449 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
10451 op0 = XEXP (op0, 0);
10456 /* The remaining cases only apply to comparisons with zero. */
10460 /* When X is ABS or is known positive,
10461 (neg X) is < 0 if and only if X != 0. */
10463 if (sign_bit_comparison_p
10464 && (GET_CODE (XEXP (op0, 0)) == ABS
10465 || (mode_width <= HOST_BITS_PER_WIDE_INT
10466 && (nonzero_bits (XEXP (op0, 0), mode)
10467 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
10469 op0 = XEXP (op0, 0);
10470 code = (code == LT ? NE : EQ);
10474 /* If we have NEG of something whose two high-order bits are the
10475 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10476 if (num_sign_bit_copies (op0, mode) >= 2)
10478 op0 = XEXP (op0, 0);
10479 code = swap_condition (code);
10485 /* If we are testing equality and our count is a constant, we
10486 can perform the inverse operation on our RHS. */
10487 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10488 && (tem = simplify_binary_operation (ROTATERT, mode,
10489 op1, XEXP (op0, 1))) != 0)
10491 op0 = XEXP (op0, 0);
10496 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10497 a particular bit. Convert it to an AND of a constant of that
10498 bit. This will be converted into a ZERO_EXTRACT. */
10499 if (const_op == 0 && sign_bit_comparison_p
10500 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10501 && mode_width <= HOST_BITS_PER_WIDE_INT)
10503 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10506 - INTVAL (XEXP (op0, 1)))));
10507 code = (code == LT ? NE : EQ);
10511 /* Fall through. */
10514 /* ABS is ignorable inside an equality comparison with zero. */
10515 if (const_op == 0 && equality_comparison_p)
10517 op0 = XEXP (op0, 0);
10523 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
10524 (compare FOO CONST) if CONST fits in FOO's mode and we
10525 are either testing inequality or have an unsigned
10526 comparison with ZERO_EXTEND or a signed comparison with
10527 SIGN_EXTEND. But don't do it if we don't have a compare
10528 insn of the given mode, since we'd have to revert it
10529 later on, and then we wouldn't know whether to sign- or
10531 mode = GET_MODE (XEXP (op0, 0));
10532 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10533 && ! unsigned_comparison_p
10534 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10535 && ((unsigned HOST_WIDE_INT) const_op
10536 < (((unsigned HOST_WIDE_INT) 1
10537 << (GET_MODE_BITSIZE (mode) - 1))))
10538 && have_insn_for (COMPARE, mode))
10540 op0 = XEXP (op0, 0);
10546 /* Check for the case where we are comparing A - C1 with C2, that is
10548 (subreg:MODE (plus (A) (-C1))) op (C2)
10550 with C1 a constant, and try to lift the SUBREG, i.e. to do the
10551 comparison in the wider mode. One of the following two conditions
10552 must be true in order for this to be valid:
10554 1. The mode extension results in the same bit pattern being added
10555 on both sides and the comparison is equality or unsigned. As
10556 C2 has been truncated to fit in MODE, the pattern can only be
10559 2. The mode extension results in the sign bit being copied on
10562 The difficulty here is that we have predicates for A but not for
10563 (A - C1) so we need to check that C1 is within proper bounds so
10564 as to perturbate A as little as possible. */
10566 if (mode_width <= HOST_BITS_PER_WIDE_INT
10567 && subreg_lowpart_p (op0)
10568 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) > mode_width
10569 && GET_CODE (SUBREG_REG (op0)) == PLUS
10570 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT)
10572 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
10573 rtx a = XEXP (SUBREG_REG (op0), 0);
10574 HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
10577 && (unsigned HOST_WIDE_INT) c1
10578 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
10579 && (equality_comparison_p || unsigned_comparison_p)
10580 /* (A - C1) zero-extends if it is positive and sign-extends
10581 if it is negative, C2 both zero- and sign-extends. */
10582 && ((0 == (nonzero_bits (a, inner_mode)
10583 & ~GET_MODE_MASK (mode))
10585 /* (A - C1) sign-extends if it is positive and 1-extends
10586 if it is negative, C2 both sign- and 1-extends. */
10587 || (num_sign_bit_copies (a, inner_mode)
10588 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10591 || ((unsigned HOST_WIDE_INT) c1
10592 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
10593 /* (A - C1) always sign-extends, like C2. */
10594 && num_sign_bit_copies (a, inner_mode)
10595 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10596 - (mode_width - 1))))
10598 op0 = SUBREG_REG (op0);
10603 /* If the inner mode is narrower and we are extracting the low part,
10604 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10605 if (subreg_lowpart_p (op0)
10606 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10607 /* Fall through */ ;
10611 /* ... fall through ... */
10614 mode = GET_MODE (XEXP (op0, 0));
10615 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10616 && (unsigned_comparison_p || equality_comparison_p)
10617 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10618 && ((unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode))
10619 && have_insn_for (COMPARE, mode))
10621 op0 = XEXP (op0, 0);
10627 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10628 this for equality comparisons due to pathological cases involving
10630 if (equality_comparison_p
10631 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10632 op1, XEXP (op0, 1))))
10634 op0 = XEXP (op0, 0);
10639 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10640 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10641 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10643 op0 = XEXP (XEXP (op0, 0), 0);
10644 code = (code == LT ? EQ : NE);
10650 /* We used to optimize signed comparisons against zero, but that
10651 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10652 arrive here as equality comparisons, or (GEU, LTU) are
10653 optimized away. No need to special-case them. */
10655 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10656 (eq B (minus A C)), whichever simplifies. We can only do
10657 this for equality comparisons due to pathological cases involving
10659 if (equality_comparison_p
10660 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10661 XEXP (op0, 1), op1)))
10663 op0 = XEXP (op0, 0);
10668 if (equality_comparison_p
10669 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10670 XEXP (op0, 0), op1)))
10672 op0 = XEXP (op0, 1);
10677 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10678 of bits in X minus 1, is one iff X > 0. */
10679 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10680 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10681 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1))
10683 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10685 op0 = XEXP (op0, 1);
10686 code = (code == GE ? LE : GT);
10692 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10693 if C is zero or B is a constant. */
10694 if (equality_comparison_p
10695 && 0 != (tem = simplify_binary_operation (XOR, mode,
10696 XEXP (op0, 1), op1)))
10698 op0 = XEXP (op0, 0);
10705 case UNEQ: case LTGT:
10706 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
10707 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
10708 case UNORDERED: case ORDERED:
10709 /* We can't do anything if OP0 is a condition code value, rather
10710 than an actual data value. */
10712 || CC0_P (XEXP (op0, 0))
10713 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10716 /* Get the two operands being compared. */
10717 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10718 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10720 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10722 /* Check for the cases where we simply want the result of the
10723 earlier test or the opposite of that result. */
10724 if (code == NE || code == EQ
10725 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10726 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10727 && (STORE_FLAG_VALUE
10728 & (((HOST_WIDE_INT) 1
10729 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10730 && (code == LT || code == GE)))
10732 enum rtx_code new_code;
10733 if (code == LT || code == NE)
10734 new_code = GET_CODE (op0);
10736 new_code = reversed_comparison_code (op0, NULL);
10738 if (new_code != UNKNOWN)
10749 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10751 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10752 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10753 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10755 op0 = XEXP (op0, 1);
10756 code = (code == GE ? GT : LE);
10762 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10763 will be converted to a ZERO_EXTRACT later. */
10764 if (const_op == 0 && equality_comparison_p
10765 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10766 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10768 op0 = simplify_and_const_int
10769 (NULL_RTX, mode, gen_rtx_LSHIFTRT (mode,
10771 XEXP (XEXP (op0, 0), 1)),
10772 (HOST_WIDE_INT) 1);
10776 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10777 zero and X is a comparison and C1 and C2 describe only bits set
10778 in STORE_FLAG_VALUE, we can compare with X. */
10779 if (const_op == 0 && equality_comparison_p
10780 && mode_width <= HOST_BITS_PER_WIDE_INT
10781 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10782 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10783 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10784 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10785 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10787 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10788 << INTVAL (XEXP (XEXP (op0, 0), 1)));
10789 if ((~STORE_FLAG_VALUE & mask) == 0
10790 && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
10791 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10792 && COMPARISON_P (tem))))
10794 op0 = XEXP (XEXP (op0, 0), 0);
10799 /* If we are doing an equality comparison of an AND of a bit equal
10800 to the sign bit, replace this with a LT or GE comparison of
10801 the underlying value. */
10802 if (equality_comparison_p
10804 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10805 && mode_width <= HOST_BITS_PER_WIDE_INT
10806 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10807 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10809 op0 = XEXP (op0, 0);
10810 code = (code == EQ ? GE : LT);
10814 /* If this AND operation is really a ZERO_EXTEND from a narrower
10815 mode, the constant fits within that mode, and this is either an
10816 equality or unsigned comparison, try to do this comparison in
10821 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
10822 -> (ne:DI (reg:SI 4) (const_int 0))
10824 unless TRULY_NOOP_TRUNCATION allows it or the register is
10825 known to hold a value of the required mode the
10826 transformation is invalid. */
10827 if ((equality_comparison_p || unsigned_comparison_p)
10828 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10829 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10830 & GET_MODE_MASK (mode))
10832 && const_op >> i == 0
10833 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode
10834 && (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
10835 GET_MODE_BITSIZE (GET_MODE (op0)))
10836 || (REG_P (XEXP (op0, 0))
10837 && reg_truncated_to_mode (tmode, XEXP (op0, 0)))))
10839 op0 = gen_lowpart (tmode, XEXP (op0, 0));
10843 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
10844 fits in both M1 and M2 and the SUBREG is either paradoxical
10845 or represents the low part, permute the SUBREG and the AND
10847 if (GET_CODE (XEXP (op0, 0)) == SUBREG)
10849 unsigned HOST_WIDE_INT c1;
10850 tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
10851 /* Require an integral mode, to avoid creating something like
10853 if (SCALAR_INT_MODE_P (tmode)
10854 /* It is unsafe to commute the AND into the SUBREG if the
10855 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
10856 not defined. As originally written the upper bits
10857 have a defined value due to the AND operation.
10858 However, if we commute the AND inside the SUBREG then
10859 they no longer have defined values and the meaning of
10860 the code has been changed. */
10862 #ifdef WORD_REGISTER_OPERATIONS
10863 || (mode_width > GET_MODE_BITSIZE (tmode)
10864 && mode_width <= BITS_PER_WORD)
10866 || (mode_width <= GET_MODE_BITSIZE (tmode)
10867 && subreg_lowpart_p (XEXP (op0, 0))))
10868 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10869 && mode_width <= HOST_BITS_PER_WIDE_INT
10870 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
10871 && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
10872 && (c1 & ~GET_MODE_MASK (tmode)) == 0
10874 && c1 != GET_MODE_MASK (tmode))
10876 op0 = simplify_gen_binary (AND, tmode,
10877 SUBREG_REG (XEXP (op0, 0)),
10878 gen_int_mode (c1, tmode));
10879 op0 = gen_lowpart (mode, op0);
10884 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
10885 if (const_op == 0 && equality_comparison_p
10886 && XEXP (op0, 1) == const1_rtx
10887 && GET_CODE (XEXP (op0, 0)) == NOT)
10889 op0 = simplify_and_const_int
10890 (NULL_RTX, mode, XEXP (XEXP (op0, 0), 0), (HOST_WIDE_INT) 1);
10891 code = (code == NE ? EQ : NE);
10895 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10896 (eq (and (lshiftrt X) 1) 0).
10897 Also handle the case where (not X) is expressed using xor. */
10898 if (const_op == 0 && equality_comparison_p
10899 && XEXP (op0, 1) == const1_rtx
10900 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
10902 rtx shift_op = XEXP (XEXP (op0, 0), 0);
10903 rtx shift_count = XEXP (XEXP (op0, 0), 1);
10905 if (GET_CODE (shift_op) == NOT
10906 || (GET_CODE (shift_op) == XOR
10907 && GET_CODE (XEXP (shift_op, 1)) == CONST_INT
10908 && GET_CODE (shift_count) == CONST_INT
10909 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
10910 && (INTVAL (XEXP (shift_op, 1))
10911 == (HOST_WIDE_INT) 1 << INTVAL (shift_count))))
10913 op0 = simplify_and_const_int
10915 gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count),
10916 (HOST_WIDE_INT) 1);
10917 code = (code == NE ? EQ : NE);
10924 /* If we have (compare (ashift FOO N) (const_int C)) and
10925 the high order N bits of FOO (N+1 if an inequality comparison)
10926 are known to be zero, we can do this by comparing FOO with C
10927 shifted right N bits so long as the low-order N bits of C are
10929 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10930 && INTVAL (XEXP (op0, 1)) >= 0
10931 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10932 < HOST_BITS_PER_WIDE_INT)
10934 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10935 && mode_width <= HOST_BITS_PER_WIDE_INT
10936 && (nonzero_bits (XEXP (op0, 0), mode)
10937 & ~(mask >> (INTVAL (XEXP (op0, 1))
10938 + ! equality_comparison_p))) == 0)
10940 /* We must perform a logical shift, not an arithmetic one,
10941 as we want the top N bits of C to be zero. */
10942 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
10944 temp >>= INTVAL (XEXP (op0, 1));
10945 op1 = gen_int_mode (temp, mode);
10946 op0 = XEXP (op0, 0);
10950 /* If we are doing a sign bit comparison, it means we are testing
10951 a particular bit. Convert it to the appropriate AND. */
10952 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10953 && mode_width <= HOST_BITS_PER_WIDE_INT)
10955 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10958 - INTVAL (XEXP (op0, 1)))));
10959 code = (code == LT ? NE : EQ);
10963 /* If this an equality comparison with zero and we are shifting
10964 the low bit to the sign bit, we can convert this to an AND of the
10966 if (const_op == 0 && equality_comparison_p
10967 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10968 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10971 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10972 (HOST_WIDE_INT) 1);
10978 /* If this is an equality comparison with zero, we can do this
10979 as a logical shift, which might be much simpler. */
10980 if (equality_comparison_p && const_op == 0
10981 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10983 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10985 INTVAL (XEXP (op0, 1)));
10989 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10990 do the comparison in a narrower mode. */
10991 if (! unsigned_comparison_p
10992 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10993 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10994 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10995 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10996 MODE_INT, 1)) != BLKmode
10997 && (((unsigned HOST_WIDE_INT) const_op
10998 + (GET_MODE_MASK (tmode) >> 1) + 1)
10999 <= GET_MODE_MASK (tmode)))
11001 op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
11005 /* Likewise if OP0 is a PLUS of a sign extension with a
11006 constant, which is usually represented with the PLUS
11007 between the shifts. */
11008 if (! unsigned_comparison_p
11009 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11010 && GET_CODE (XEXP (op0, 0)) == PLUS
11011 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
11012 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
11013 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
11014 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11015 MODE_INT, 1)) != BLKmode
11016 && (((unsigned HOST_WIDE_INT) const_op
11017 + (GET_MODE_MASK (tmode) >> 1) + 1)
11018 <= GET_MODE_MASK (tmode)))
11020 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
11021 rtx add_const = XEXP (XEXP (op0, 0), 1);
11022 rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
11023 add_const, XEXP (op0, 1));
11025 op0 = simplify_gen_binary (PLUS, tmode,
11026 gen_lowpart (tmode, inner),
11031 /* ... fall through ... */
11033 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11034 the low order N bits of FOO are known to be zero, we can do this
11035 by comparing FOO with C shifted left N bits so long as no
11036 overflow occurs. */
11037 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
11038 && INTVAL (XEXP (op0, 1)) >= 0
11039 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11040 && mode_width <= HOST_BITS_PER_WIDE_INT
11041 && (nonzero_bits (XEXP (op0, 0), mode)
11042 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
11043 && (((unsigned HOST_WIDE_INT) const_op
11044 + (GET_CODE (op0) != LSHIFTRT
11045 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
11048 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
11050 /* If the shift was logical, then we must make the condition
11052 if (GET_CODE (op0) == LSHIFTRT)
11053 code = unsigned_condition (code);
11055 const_op <<= INTVAL (XEXP (op0, 1));
11056 op1 = GEN_INT (const_op);
11057 op0 = XEXP (op0, 0);
11061 /* If we are using this shift to extract just the sign bit, we
11062 can replace this with an LT or GE comparison. */
11064 && (equality_comparison_p || sign_bit_comparison_p)
11065 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11066 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
11069 op0 = XEXP (op0, 0);
11070 code = (code == NE || code == GT ? LT : GE);
11082 /* Now make any compound operations involved in this comparison. Then,
11083 check for an outmost SUBREG on OP0 that is not doing anything or is
11084 paradoxical. The latter transformation must only be performed when
11085 it is known that the "extra" bits will be the same in op0 and op1 or
11086 that they don't matter. There are three cases to consider:
11088 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11089 care bits and we can assume they have any convenient value. So
11090 making the transformation is safe.
11092 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11093 In this case the upper bits of op0 are undefined. We should not make
11094 the simplification in that case as we do not know the contents of
11097 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11098 UNKNOWN. In that case we know those bits are zeros or ones. We must
11099 also be sure that they are the same as the upper bits of op1.
11101 We can never remove a SUBREG for a non-equality comparison because
11102 the sign bit is in a different place in the underlying object. */
11104 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
11105 op1 = make_compound_operation (op1, SET);
11107 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
11108 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11109 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
11110 && (code == NE || code == EQ))
11112 if (GET_MODE_SIZE (GET_MODE (op0))
11113 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
11115 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
11117 if (REG_P (SUBREG_REG (op0)))
11119 op0 = SUBREG_REG (op0);
11120 op1 = gen_lowpart (GET_MODE (op0), op1);
11123 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
11124 <= HOST_BITS_PER_WIDE_INT)
11125 && (nonzero_bits (SUBREG_REG (op0),
11126 GET_MODE (SUBREG_REG (op0)))
11127 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11129 tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
11131 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
11132 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11133 op0 = SUBREG_REG (op0), op1 = tem;
11137 /* We now do the opposite procedure: Some machines don't have compare
11138 insns in all modes. If OP0's mode is an integer mode smaller than a
11139 word and we can't do a compare in that mode, see if there is a larger
11140 mode for which we can do the compare. There are a number of cases in
11141 which we can use the wider mode. */
11143 mode = GET_MODE (op0);
11144 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11145 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
11146 && ! have_insn_for (COMPARE, mode))
11147 for (tmode = GET_MODE_WIDER_MODE (mode);
11149 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
11150 tmode = GET_MODE_WIDER_MODE (tmode))
11151 if (have_insn_for (COMPARE, tmode))
11155 /* If the only nonzero bits in OP0 and OP1 are those in the
11156 narrower mode and this is an equality or unsigned comparison,
11157 we can use the wider mode. Similarly for sign-extended
11158 values, in which case it is true for all comparisons. */
11159 zero_extended = ((code == EQ || code == NE
11160 || code == GEU || code == GTU
11161 || code == LEU || code == LTU)
11162 && (nonzero_bits (op0, tmode)
11163 & ~GET_MODE_MASK (mode)) == 0
11164 && ((GET_CODE (op1) == CONST_INT
11165 || (nonzero_bits (op1, tmode)
11166 & ~GET_MODE_MASK (mode)) == 0)));
11169 || ((num_sign_bit_copies (op0, tmode)
11170 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11171 - GET_MODE_BITSIZE (mode)))
11172 && (num_sign_bit_copies (op1, tmode)
11173 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11174 - GET_MODE_BITSIZE (mode)))))
11176 /* If OP0 is an AND and we don't have an AND in MODE either,
11177 make a new AND in the proper mode. */
11178 if (GET_CODE (op0) == AND
11179 && !have_insn_for (AND, mode))
11180 op0 = simplify_gen_binary (AND, tmode,
11181 gen_lowpart (tmode,
11183 gen_lowpart (tmode,
11186 op0 = gen_lowpart (tmode, op0);
11187 if (zero_extended && GET_CODE (op1) == CONST_INT)
11188 op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode));
11189 op1 = gen_lowpart (tmode, op1);
11193 /* If this is a test for negative, we can make an explicit
11194 test of the sign bit. */
11196 if (op1 == const0_rtx && (code == LT || code == GE)
11197 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11199 op0 = simplify_gen_binary (AND, tmode,
11200 gen_lowpart (tmode, op0),
11201 GEN_INT ((HOST_WIDE_INT) 1
11202 << (GET_MODE_BITSIZE (mode)
11204 code = (code == LT) ? NE : EQ;
11209 #ifdef CANONICALIZE_COMPARISON
11210 /* If this machine only supports a subset of valid comparisons, see if we
11211 can convert an unsupported one into a supported one. */
11212 CANONICALIZE_COMPARISON (code, op0, op1);
11221 /* Utility function for record_value_for_reg. Count number of
11226 enum rtx_code code = GET_CODE (x);
11230 if (GET_RTX_CLASS (code) == '2'
11231 || GET_RTX_CLASS (code) == 'c')
11233 rtx x0 = XEXP (x, 0);
11234 rtx x1 = XEXP (x, 1);
11237 return 1 + 2 * count_rtxs (x0);
11239 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
11240 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
11241 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11242 return 2 + 2 * count_rtxs (x0)
11243 + count_rtxs (x == XEXP (x1, 0)
11244 ? XEXP (x1, 1) : XEXP (x1, 0));
11246 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
11247 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
11248 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11249 return 2 + 2 * count_rtxs (x1)
11250 + count_rtxs (x == XEXP (x0, 0)
11251 ? XEXP (x0, 1) : XEXP (x0, 0));
11254 fmt = GET_RTX_FORMAT (code);
11255 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11257 ret += count_rtxs (XEXP (x, i));
11258 else if (fmt[i] == 'E')
11259 for (j = 0; j < XVECLEN (x, i); j++)
11260 ret += count_rtxs (XVECEXP (x, i, j));
11265 /* Utility function for following routine. Called when X is part of a value
11266 being stored into last_set_value. Sets last_set_table_tick
11267 for each register mentioned. Similar to mention_regs in cse.c */
11270 update_table_tick (rtx x)
11272 enum rtx_code code = GET_CODE (x);
11273 const char *fmt = GET_RTX_FORMAT (code);
11278 unsigned int regno = REGNO (x);
11279 unsigned int endregno = END_REGNO (x);
11282 for (r = regno; r < endregno; r++)
11284 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, r);
11285 rsp->last_set_table_tick = label_tick;
11291 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11294 /* Check for identical subexpressions. If x contains
11295 identical subexpression we only have to traverse one of
11297 if (i == 0 && ARITHMETIC_P (x))
11299 /* Note that at this point x1 has already been
11301 rtx x0 = XEXP (x, 0);
11302 rtx x1 = XEXP (x, 1);
11304 /* If x0 and x1 are identical then there is no need to
11309 /* If x0 is identical to a subexpression of x1 then while
11310 processing x1, x0 has already been processed. Thus we
11311 are done with x. */
11312 if (ARITHMETIC_P (x1)
11313 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11316 /* If x1 is identical to a subexpression of x0 then we
11317 still have to process the rest of x0. */
11318 if (ARITHMETIC_P (x0)
11319 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11321 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
11326 update_table_tick (XEXP (x, i));
11328 else if (fmt[i] == 'E')
11329 for (j = 0; j < XVECLEN (x, i); j++)
11330 update_table_tick (XVECEXP (x, i, j));
11333 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11334 are saying that the register is clobbered and we no longer know its
11335 value. If INSN is zero, don't update reg_stat[].last_set; this is
11336 only permitted with VALUE also zero and is used to invalidate the
11340 record_value_for_reg (rtx reg, rtx insn, rtx value)
11342 unsigned int regno = REGNO (reg);
11343 unsigned int endregno = END_REGNO (reg);
11345 reg_stat_type *rsp;
11347 /* If VALUE contains REG and we have a previous value for REG, substitute
11348 the previous value. */
11349 if (value && insn && reg_overlap_mentioned_p (reg, value))
11353 /* Set things up so get_last_value is allowed to see anything set up to
11355 subst_low_luid = DF_INSN_LUID (insn);
11356 tem = get_last_value (reg);
11358 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11359 it isn't going to be useful and will take a lot of time to process,
11360 so just use the CLOBBER. */
11364 if (ARITHMETIC_P (tem)
11365 && GET_CODE (XEXP (tem, 0)) == CLOBBER
11366 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
11367 tem = XEXP (tem, 0);
11368 else if (count_occurrences (value, reg, 1) >= 2)
11370 /* If there are two or more occurrences of REG in VALUE,
11371 prevent the value from growing too much. */
11372 if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
11373 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
11376 value = replace_rtx (copy_rtx (value), reg, tem);
11380 /* For each register modified, show we don't know its value, that
11381 we don't know about its bitwise content, that its value has been
11382 updated, and that we don't know the location of the death of the
11384 for (i = regno; i < endregno; i++)
11386 rsp = VEC_index (reg_stat_type, reg_stat, i);
11389 rsp->last_set = insn;
11391 rsp->last_set_value = 0;
11392 rsp->last_set_mode = 0;
11393 rsp->last_set_nonzero_bits = 0;
11394 rsp->last_set_sign_bit_copies = 0;
11395 rsp->last_death = 0;
11396 rsp->truncated_to_mode = 0;
11399 /* Mark registers that are being referenced in this value. */
11401 update_table_tick (value);
11403 /* Now update the status of each register being set.
11404 If someone is using this register in this block, set this register
11405 to invalid since we will get confused between the two lives in this
11406 basic block. This makes using this register always invalid. In cse, we
11407 scan the table to invalidate all entries using this register, but this
11408 is too much work for us. */
11410 for (i = regno; i < endregno; i++)
11412 rsp = VEC_index (reg_stat_type, reg_stat, i);
11413 rsp->last_set_label = label_tick;
11415 || (value && rsp->last_set_table_tick >= label_tick_ebb_start))
11416 rsp->last_set_invalid = 1;
11418 rsp->last_set_invalid = 0;
11421 /* The value being assigned might refer to X (like in "x++;"). In that
11422 case, we must replace it with (clobber (const_int 0)) to prevent
11424 rsp = VEC_index (reg_stat_type, reg_stat, regno);
11425 if (value && ! get_last_value_validate (&value, insn,
11426 rsp->last_set_label, 0))
11428 value = copy_rtx (value);
11429 if (! get_last_value_validate (&value, insn,
11430 rsp->last_set_label, 1))
11434 /* For the main register being modified, update the value, the mode, the
11435 nonzero bits, and the number of sign bit copies. */
11437 rsp->last_set_value = value;
11441 enum machine_mode mode = GET_MODE (reg);
11442 subst_low_luid = DF_INSN_LUID (insn);
11443 rsp->last_set_mode = mode;
11444 if (GET_MODE_CLASS (mode) == MODE_INT
11445 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11446 mode = nonzero_bits_mode;
11447 rsp->last_set_nonzero_bits = nonzero_bits (value, mode);
11448 rsp->last_set_sign_bit_copies
11449 = num_sign_bit_copies (value, GET_MODE (reg));
11453 /* Called via note_stores from record_dead_and_set_regs to handle one
11454 SET or CLOBBER in an insn. DATA is the instruction in which the
11455 set is occurring. */
11458 record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data)
11460 rtx record_dead_insn = (rtx) data;
11462 if (GET_CODE (dest) == SUBREG)
11463 dest = SUBREG_REG (dest);
11465 if (!record_dead_insn)
11468 record_value_for_reg (dest, NULL_RTX, NULL_RTX);
11474 /* If we are setting the whole register, we know its value. Otherwise
11475 show that we don't know the value. We can handle SUBREG in
11477 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
11478 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
11479 else if (GET_CODE (setter) == SET
11480 && GET_CODE (SET_DEST (setter)) == SUBREG
11481 && SUBREG_REG (SET_DEST (setter)) == dest
11482 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
11483 && subreg_lowpart_p (SET_DEST (setter)))
11484 record_value_for_reg (dest, record_dead_insn,
11485 gen_lowpart (GET_MODE (dest),
11486 SET_SRC (setter)));
11488 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
11490 else if (MEM_P (dest)
11491 /* Ignore pushes, they clobber nothing. */
11492 && ! push_operand (dest, GET_MODE (dest)))
11493 mem_last_set = DF_INSN_LUID (record_dead_insn);
11496 /* Update the records of when each REG was most recently set or killed
11497 for the things done by INSN. This is the last thing done in processing
11498 INSN in the combiner loop.
11500 We update reg_stat[], in particular fields last_set, last_set_value,
11501 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
11502 last_death, and also the similar information mem_last_set (which insn
11503 most recently modified memory) and last_call_luid (which insn was the
11504 most recent subroutine call). */
11507 record_dead_and_set_regs (rtx insn)
11512 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11514 if (REG_NOTE_KIND (link) == REG_DEAD
11515 && REG_P (XEXP (link, 0)))
11517 unsigned int regno = REGNO (XEXP (link, 0));
11518 unsigned int endregno = END_REGNO (XEXP (link, 0));
11520 for (i = regno; i < endregno; i++)
11522 reg_stat_type *rsp;
11524 rsp = VEC_index (reg_stat_type, reg_stat, i);
11525 rsp->last_death = insn;
11528 else if (REG_NOTE_KIND (link) == REG_INC)
11529 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11534 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11535 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
11537 reg_stat_type *rsp;
11539 rsp = VEC_index (reg_stat_type, reg_stat, i);
11540 rsp->last_set_invalid = 1;
11541 rsp->last_set = insn;
11542 rsp->last_set_value = 0;
11543 rsp->last_set_mode = 0;
11544 rsp->last_set_nonzero_bits = 0;
11545 rsp->last_set_sign_bit_copies = 0;
11546 rsp->last_death = 0;
11547 rsp->truncated_to_mode = 0;
11550 last_call_luid = mem_last_set = DF_INSN_LUID (insn);
11552 /* We can't combine into a call pattern. Remember, though, that
11553 the return value register is set at this LUID. We could
11554 still replace a register with the return value from the
11555 wrong subroutine call! */
11556 note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX);
11559 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11562 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11563 register present in the SUBREG, so for each such SUBREG go back and
11564 adjust nonzero and sign bit information of the registers that are
11565 known to have some zero/sign bits set.
11567 This is needed because when combine blows the SUBREGs away, the
11568 information on zero/sign bits is lost and further combines can be
11569 missed because of that. */
11572 record_promoted_value (rtx insn, rtx subreg)
11575 unsigned int regno = REGNO (SUBREG_REG (subreg));
11576 enum machine_mode mode = GET_MODE (subreg);
11578 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11581 for (links = LOG_LINKS (insn); links;)
11583 reg_stat_type *rsp;
11585 insn = XEXP (links, 0);
11586 set = single_set (insn);
11588 if (! set || !REG_P (SET_DEST (set))
11589 || REGNO (SET_DEST (set)) != regno
11590 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11592 links = XEXP (links, 1);
11596 rsp = VEC_index (reg_stat_type, reg_stat, regno);
11597 if (rsp->last_set == insn)
11599 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
11600 rsp->last_set_nonzero_bits &= GET_MODE_MASK (mode);
11603 if (REG_P (SET_SRC (set)))
11605 regno = REGNO (SET_SRC (set));
11606 links = LOG_LINKS (insn);
11613 /* Check if X, a register, is known to contain a value already
11614 truncated to MODE. In this case we can use a subreg to refer to
11615 the truncated value even though in the generic case we would need
11616 an explicit truncation. */
11619 reg_truncated_to_mode (enum machine_mode mode, const_rtx x)
11621 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
11622 enum machine_mode truncated = rsp->truncated_to_mode;
11625 || rsp->truncation_label < label_tick_ebb_start)
11627 if (GET_MODE_SIZE (truncated) <= GET_MODE_SIZE (mode))
11629 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
11630 GET_MODE_BITSIZE (truncated)))
11635 /* Callback for for_each_rtx. If *P is a hard reg or a subreg record the mode
11636 that the register is accessed in. For non-TRULY_NOOP_TRUNCATION targets we
11637 might be able to turn a truncate into a subreg using this information.
11638 Return -1 if traversing *P is complete or 0 otherwise. */
11641 record_truncated_value (rtx *p, void *data ATTRIBUTE_UNUSED)
11644 enum machine_mode truncated_mode;
11645 reg_stat_type *rsp;
11647 if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
11649 enum machine_mode original_mode = GET_MODE (SUBREG_REG (x));
11650 truncated_mode = GET_MODE (x);
11652 if (GET_MODE_SIZE (original_mode) <= GET_MODE_SIZE (truncated_mode))
11655 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (truncated_mode),
11656 GET_MODE_BITSIZE (original_mode)))
11659 x = SUBREG_REG (x);
11661 /* ??? For hard-regs we now record everything. We might be able to
11662 optimize this using last_set_mode. */
11663 else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
11664 truncated_mode = GET_MODE (x);
11668 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
11669 if (rsp->truncated_to_mode == 0
11670 || rsp->truncation_label < label_tick_ebb_start
11671 || (GET_MODE_SIZE (truncated_mode)
11672 < GET_MODE_SIZE (rsp->truncated_to_mode)))
11674 rsp->truncated_to_mode = truncated_mode;
11675 rsp->truncation_label = label_tick;
11681 /* Callback for note_uses. Find hardregs and subregs of pseudos and
11682 the modes they are used in. This can help truning TRUNCATEs into
11686 record_truncated_values (rtx *x, void *data ATTRIBUTE_UNUSED)
11688 for_each_rtx (x, record_truncated_value, NULL);
11691 /* Scan X for promoted SUBREGs. For each one found,
11692 note what it implies to the registers used in it. */
11695 check_promoted_subreg (rtx insn, rtx x)
11697 if (GET_CODE (x) == SUBREG
11698 && SUBREG_PROMOTED_VAR_P (x)
11699 && REG_P (SUBREG_REG (x)))
11700 record_promoted_value (insn, x);
11703 const char *format = GET_RTX_FORMAT (GET_CODE (x));
11706 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11710 check_promoted_subreg (insn, XEXP (x, i));
11714 if (XVEC (x, i) != 0)
11715 for (j = 0; j < XVECLEN (x, i); j++)
11716 check_promoted_subreg (insn, XVECEXP (x, i, j));
11722 /* Utility routine for the following function. Verify that all the registers
11723 mentioned in *LOC are valid when *LOC was part of a value set when
11724 label_tick == TICK. Return 0 if some are not.
11726 If REPLACE is nonzero, replace the invalid reference with
11727 (clobber (const_int 0)) and return 1. This replacement is useful because
11728 we often can get useful information about the form of a value (e.g., if
11729 it was produced by a shift that always produces -1 or 0) even though
11730 we don't know exactly what registers it was produced from. */
11733 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
11736 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11737 int len = GET_RTX_LENGTH (GET_CODE (x));
11742 unsigned int regno = REGNO (x);
11743 unsigned int endregno = END_REGNO (x);
11746 for (j = regno; j < endregno; j++)
11748 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, j);
11749 if (rsp->last_set_invalid
11750 /* If this is a pseudo-register that was only set once and not
11751 live at the beginning of the function, it is always valid. */
11752 || (! (regno >= FIRST_PSEUDO_REGISTER
11753 && REG_N_SETS (regno) == 1
11754 && (!REGNO_REG_SET_P
11755 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno)))
11756 && rsp->last_set_label > tick))
11759 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11766 /* If this is a memory reference, make sure that there were
11767 no stores after it that might have clobbered the value. We don't
11768 have alias info, so we assume any store invalidates it. */
11769 else if (MEM_P (x) && !MEM_READONLY_P (x)
11770 && DF_INSN_LUID (insn) <= mem_last_set)
11773 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11777 for (i = 0; i < len; i++)
11781 /* Check for identical subexpressions. If x contains
11782 identical subexpression we only have to traverse one of
11784 if (i == 1 && ARITHMETIC_P (x))
11786 /* Note that at this point x0 has already been checked
11787 and found valid. */
11788 rtx x0 = XEXP (x, 0);
11789 rtx x1 = XEXP (x, 1);
11791 /* If x0 and x1 are identical then x is also valid. */
11795 /* If x1 is identical to a subexpression of x0 then
11796 while checking x0, x1 has already been checked. Thus
11797 it is valid and so as x. */
11798 if (ARITHMETIC_P (x0)
11799 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11802 /* If x0 is identical to a subexpression of x1 then x is
11803 valid iff the rest of x1 is valid. */
11804 if (ARITHMETIC_P (x1)
11805 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11807 get_last_value_validate (&XEXP (x1,
11808 x0 == XEXP (x1, 0) ? 1 : 0),
11809 insn, tick, replace);
11812 if (get_last_value_validate (&XEXP (x, i), insn, tick,
11816 else if (fmt[i] == 'E')
11817 for (j = 0; j < XVECLEN (x, i); j++)
11818 if (get_last_value_validate (&XVECEXP (x, i, j),
11819 insn, tick, replace) == 0)
11823 /* If we haven't found a reason for it to be invalid, it is valid. */
11827 /* Get the last value assigned to X, if known. Some registers
11828 in the value may be replaced with (clobber (const_int 0)) if their value
11829 is known longer known reliably. */
11832 get_last_value (const_rtx x)
11834 unsigned int regno;
11836 reg_stat_type *rsp;
11838 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11839 then convert it to the desired mode. If this is a paradoxical SUBREG,
11840 we cannot predict what values the "extra" bits might have. */
11841 if (GET_CODE (x) == SUBREG
11842 && subreg_lowpart_p (x)
11843 && (GET_MODE_SIZE (GET_MODE (x))
11844 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11845 && (value = get_last_value (SUBREG_REG (x))) != 0)
11846 return gen_lowpart (GET_MODE (x), value);
11852 rsp = VEC_index (reg_stat_type, reg_stat, regno);
11853 value = rsp->last_set_value;
11855 /* If we don't have a value, or if it isn't for this basic block and
11856 it's either a hard register, set more than once, or it's a live
11857 at the beginning of the function, return 0.
11859 Because if it's not live at the beginning of the function then the reg
11860 is always set before being used (is never used without being set).
11861 And, if it's set only once, and it's always set before use, then all
11862 uses must have the same last value, even if it's not from this basic
11866 || (rsp->last_set_label < label_tick_ebb_start
11867 && (regno < FIRST_PSEUDO_REGISTER
11868 || REG_N_SETS (regno) != 1
11870 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno))))
11873 /* If the value was set in a later insn than the ones we are processing,
11874 we can't use it even if the register was only set once. */
11875 if (rsp->last_set_label == label_tick
11876 && DF_INSN_LUID (rsp->last_set) >= subst_low_luid)
11879 /* If the value has all its registers valid, return it. */
11880 if (get_last_value_validate (&value, rsp->last_set,
11881 rsp->last_set_label, 0))
11884 /* Otherwise, make a copy and replace any invalid register with
11885 (clobber (const_int 0)). If that fails for some reason, return 0. */
11887 value = copy_rtx (value);
11888 if (get_last_value_validate (&value, rsp->last_set,
11889 rsp->last_set_label, 1))
11895 /* Return nonzero if expression X refers to a REG or to memory
11896 that is set in an instruction more recent than FROM_LUID. */
11899 use_crosses_set_p (const_rtx x, int from_luid)
11903 enum rtx_code code = GET_CODE (x);
11907 unsigned int regno = REGNO (x);
11908 unsigned endreg = END_REGNO (x);
11910 #ifdef PUSH_ROUNDING
11911 /* Don't allow uses of the stack pointer to be moved,
11912 because we don't know whether the move crosses a push insn. */
11913 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11916 for (; regno < endreg; regno++)
11918 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
11920 && rsp->last_set_label == label_tick
11921 && DF_INSN_LUID (rsp->last_set) > from_luid)
11927 if (code == MEM && mem_last_set > from_luid)
11930 fmt = GET_RTX_FORMAT (code);
11932 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11937 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11938 if (use_crosses_set_p (XVECEXP (x, i, j), from_luid))
11941 else if (fmt[i] == 'e'
11942 && use_crosses_set_p (XEXP (x, i), from_luid))
11948 /* Define three variables used for communication between the following
11951 static unsigned int reg_dead_regno, reg_dead_endregno;
11952 static int reg_dead_flag;
11954 /* Function called via note_stores from reg_dead_at_p.
11956 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11957 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11960 reg_dead_at_p_1 (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
11962 unsigned int regno, endregno;
11967 regno = REGNO (dest);
11968 endregno = END_REGNO (dest);
11969 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11970 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11973 /* Return nonzero if REG is known to be dead at INSN.
11975 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11976 referencing REG, it is dead. If we hit a SET referencing REG, it is
11977 live. Otherwise, see if it is live or dead at the start of the basic
11978 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11979 must be assumed to be always live. */
11982 reg_dead_at_p (rtx reg, rtx insn)
11987 /* Set variables for reg_dead_at_p_1. */
11988 reg_dead_regno = REGNO (reg);
11989 reg_dead_endregno = END_REGNO (reg);
11993 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
11994 we allow the machine description to decide whether use-and-clobber
11995 patterns are OK. */
11996 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11998 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11999 if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
12003 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
12004 beginning of basic block. */
12005 block = BLOCK_FOR_INSN (insn);
12010 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
12012 return reg_dead_flag == 1 ? 1 : 0;
12014 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
12018 if (insn == BB_HEAD (block))
12021 insn = PREV_INSN (insn);
12024 /* Look at live-in sets for the basic block that we were in. */
12025 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12026 if (REGNO_REG_SET_P (df_get_live_in (block), i))
12032 /* Note hard registers in X that are used. */
12035 mark_used_regs_combine (rtx x)
12037 RTX_CODE code = GET_CODE (x);
12038 unsigned int regno;
12051 case ADDR_DIFF_VEC:
12054 /* CC0 must die in the insn after it is set, so we don't need to take
12055 special note of it here. */
12061 /* If we are clobbering a MEM, mark any hard registers inside the
12062 address as used. */
12063 if (MEM_P (XEXP (x, 0)))
12064 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
12069 /* A hard reg in a wide mode may really be multiple registers.
12070 If so, mark all of them just like the first. */
12071 if (regno < FIRST_PSEUDO_REGISTER)
12073 /* None of this applies to the stack, frame or arg pointers. */
12074 if (regno == STACK_POINTER_REGNUM
12075 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
12076 || regno == HARD_FRAME_POINTER_REGNUM
12078 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12079 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
12081 || regno == FRAME_POINTER_REGNUM)
12084 add_to_hard_reg_set (&newpat_used_regs, GET_MODE (x), regno);
12090 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12092 rtx testreg = SET_DEST (x);
12094 while (GET_CODE (testreg) == SUBREG
12095 || GET_CODE (testreg) == ZERO_EXTRACT
12096 || GET_CODE (testreg) == STRICT_LOW_PART)
12097 testreg = XEXP (testreg, 0);
12099 if (MEM_P (testreg))
12100 mark_used_regs_combine (XEXP (testreg, 0));
12102 mark_used_regs_combine (SET_SRC (x));
12110 /* Recursively scan the operands of this expression. */
12113 const char *fmt = GET_RTX_FORMAT (code);
12115 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12118 mark_used_regs_combine (XEXP (x, i));
12119 else if (fmt[i] == 'E')
12123 for (j = 0; j < XVECLEN (x, i); j++)
12124 mark_used_regs_combine (XVECEXP (x, i, j));
12130 /* Remove register number REGNO from the dead registers list of INSN.
12132 Return the note used to record the death, if there was one. */
12135 remove_death (unsigned int regno, rtx insn)
12137 rtx note = find_regno_note (insn, REG_DEAD, regno);
12140 remove_note (insn, note);
12145 /* For each register (hardware or pseudo) used within expression X, if its
12146 death is in an instruction with luid between FROM_LUID (inclusive) and
12147 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12148 list headed by PNOTES.
12150 That said, don't move registers killed by maybe_kill_insn.
12152 This is done when X is being merged by combination into TO_INSN. These
12153 notes will then be distributed as needed. */
12156 move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx to_insn,
12161 enum rtx_code code = GET_CODE (x);
12165 unsigned int regno = REGNO (x);
12166 rtx where_dead = VEC_index (reg_stat_type, reg_stat, regno)->last_death;
12168 /* Don't move the register if it gets killed in between from and to. */
12169 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
12170 && ! reg_referenced_p (x, maybe_kill_insn))
12174 && DF_INSN_LUID (where_dead) >= from_luid
12175 && DF_INSN_LUID (where_dead) < DF_INSN_LUID (to_insn))
12177 rtx note = remove_death (regno, where_dead);
12179 /* It is possible for the call above to return 0. This can occur
12180 when last_death points to I2 or I1 that we combined with.
12181 In that case make a new note.
12183 We must also check for the case where X is a hard register
12184 and NOTE is a death note for a range of hard registers
12185 including X. In that case, we must put REG_DEAD notes for
12186 the remaining registers in place of NOTE. */
12188 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
12189 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12190 > GET_MODE_SIZE (GET_MODE (x))))
12192 unsigned int deadregno = REGNO (XEXP (note, 0));
12193 unsigned int deadend = END_HARD_REGNO (XEXP (note, 0));
12194 unsigned int ourend = END_HARD_REGNO (x);
12197 for (i = deadregno; i < deadend; i++)
12198 if (i < regno || i >= ourend)
12199 add_reg_note (where_dead, REG_DEAD, regno_reg_rtx[i]);
12202 /* If we didn't find any note, or if we found a REG_DEAD note that
12203 covers only part of the given reg, and we have a multi-reg hard
12204 register, then to be safe we must check for REG_DEAD notes
12205 for each register other than the first. They could have
12206 their own REG_DEAD notes lying around. */
12207 else if ((note == 0
12209 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12210 < GET_MODE_SIZE (GET_MODE (x)))))
12211 && regno < FIRST_PSEUDO_REGISTER
12212 && hard_regno_nregs[regno][GET_MODE (x)] > 1)
12214 unsigned int ourend = END_HARD_REGNO (x);
12215 unsigned int i, offset;
12219 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
12223 for (i = regno + offset; i < ourend; i++)
12224 move_deaths (regno_reg_rtx[i],
12225 maybe_kill_insn, from_luid, to_insn, &oldnotes);
12228 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
12230 XEXP (note, 1) = *pnotes;
12234 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
12240 else if (GET_CODE (x) == SET)
12242 rtx dest = SET_DEST (x);
12244 move_deaths (SET_SRC (x), maybe_kill_insn, from_luid, to_insn, pnotes);
12246 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12247 that accesses one word of a multi-word item, some
12248 piece of everything register in the expression is used by
12249 this insn, so remove any old death. */
12250 /* ??? So why do we test for equality of the sizes? */
12252 if (GET_CODE (dest) == ZERO_EXTRACT
12253 || GET_CODE (dest) == STRICT_LOW_PART
12254 || (GET_CODE (dest) == SUBREG
12255 && (((GET_MODE_SIZE (GET_MODE (dest))
12256 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
12257 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
12258 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
12260 move_deaths (dest, maybe_kill_insn, from_luid, to_insn, pnotes);
12264 /* If this is some other SUBREG, we know it replaces the entire
12265 value, so use that as the destination. */
12266 if (GET_CODE (dest) == SUBREG)
12267 dest = SUBREG_REG (dest);
12269 /* If this is a MEM, adjust deaths of anything used in the address.
12270 For a REG (the only other possibility), the entire value is
12271 being replaced so the old value is not used in this insn. */
12274 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_luid,
12279 else if (GET_CODE (x) == CLOBBER)
12282 len = GET_RTX_LENGTH (code);
12283 fmt = GET_RTX_FORMAT (code);
12285 for (i = 0; i < len; i++)
12290 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12291 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_luid,
12294 else if (fmt[i] == 'e')
12295 move_deaths (XEXP (x, i), maybe_kill_insn, from_luid, to_insn, pnotes);
12299 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12300 pattern of an insn. X must be a REG. */
12303 reg_bitfield_target_p (rtx x, rtx body)
12307 if (GET_CODE (body) == SET)
12309 rtx dest = SET_DEST (body);
12311 unsigned int regno, tregno, endregno, endtregno;
12313 if (GET_CODE (dest) == ZERO_EXTRACT)
12314 target = XEXP (dest, 0);
12315 else if (GET_CODE (dest) == STRICT_LOW_PART)
12316 target = SUBREG_REG (XEXP (dest, 0));
12320 if (GET_CODE (target) == SUBREG)
12321 target = SUBREG_REG (target);
12323 if (!REG_P (target))
12326 tregno = REGNO (target), regno = REGNO (x);
12327 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
12328 return target == x;
12330 endtregno = end_hard_regno (GET_MODE (target), tregno);
12331 endregno = end_hard_regno (GET_MODE (x), regno);
12333 return endregno > tregno && regno < endtregno;
12336 else if (GET_CODE (body) == PARALLEL)
12337 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
12338 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
12344 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12345 as appropriate. I3 and I2 are the insns resulting from the combination
12346 insns including FROM (I2 may be zero).
12348 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
12349 not need REG_DEAD notes because they are being substituted for. This
12350 saves searching in the most common cases.
12352 Each note in the list is either ignored or placed on some insns, depending
12353 on the type of note. */
12356 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2,
12359 rtx note, next_note;
12362 for (note = notes; note; note = next_note)
12364 rtx place = 0, place2 = 0;
12366 next_note = XEXP (note, 1);
12367 switch (REG_NOTE_KIND (note))
12371 /* Doesn't matter much where we put this, as long as it's somewhere.
12372 It is preferable to keep these notes on branches, which is most
12373 likely to be i3. */
12377 case REG_VALUE_PROFILE:
12378 /* Just get rid of this note, as it is unused later anyway. */
12381 case REG_NON_LOCAL_GOTO:
12386 gcc_assert (i2 && JUMP_P (i2));
12391 case REG_EH_REGION:
12392 /* These notes must remain with the call or trapping instruction. */
12395 else if (i2 && CALL_P (i2))
12399 gcc_assert (flag_non_call_exceptions);
12400 if (may_trap_p (i3))
12402 else if (i2 && may_trap_p (i2))
12404 /* ??? Otherwise assume we've combined things such that we
12405 can now prove that the instructions can't trap. Drop the
12406 note in this case. */
12412 /* These notes must remain with the call. It should not be
12413 possible for both I2 and I3 to be a call. */
12418 gcc_assert (i2 && CALL_P (i2));
12424 /* Any clobbers for i3 may still exist, and so we must process
12425 REG_UNUSED notes from that insn.
12427 Any clobbers from i2 or i1 can only exist if they were added by
12428 recog_for_combine. In that case, recog_for_combine created the
12429 necessary REG_UNUSED notes. Trying to keep any original
12430 REG_UNUSED notes from these insns can cause incorrect output
12431 if it is for the same register as the original i3 dest.
12432 In that case, we will notice that the register is set in i3,
12433 and then add a REG_UNUSED note for the destination of i3, which
12434 is wrong. However, it is possible to have REG_UNUSED notes from
12435 i2 or i1 for register which were both used and clobbered, so
12436 we keep notes from i2 or i1 if they will turn into REG_DEAD
12439 /* If this register is set or clobbered in I3, put the note there
12440 unless there is one already. */
12441 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
12443 if (from_insn != i3)
12446 if (! (REG_P (XEXP (note, 0))
12447 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
12448 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
12451 /* Otherwise, if this register is used by I3, then this register
12452 now dies here, so we must put a REG_DEAD note here unless there
12454 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
12455 && ! (REG_P (XEXP (note, 0))
12456 ? find_regno_note (i3, REG_DEAD,
12457 REGNO (XEXP (note, 0)))
12458 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
12460 PUT_REG_NOTE_KIND (note, REG_DEAD);
12468 /* These notes say something about results of an insn. We can
12469 only support them if they used to be on I3 in which case they
12470 remain on I3. Otherwise they are ignored.
12472 If the note refers to an expression that is not a constant, we
12473 must also ignore the note since we cannot tell whether the
12474 equivalence is still true. It might be possible to do
12475 slightly better than this (we only have a problem if I2DEST
12476 or I1DEST is present in the expression), but it doesn't
12477 seem worth the trouble. */
12479 if (from_insn == i3
12480 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
12485 /* These notes say something about how a register is used. They must
12486 be present on any use of the register in I2 or I3. */
12487 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
12490 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
12499 case REG_LABEL_TARGET:
12500 case REG_LABEL_OPERAND:
12501 /* This can show up in several ways -- either directly in the
12502 pattern, or hidden off in the constant pool with (or without?)
12503 a REG_EQUAL note. */
12504 /* ??? Ignore the without-reg_equal-note problem for now. */
12505 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
12506 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
12507 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12508 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
12512 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
12513 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
12514 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12515 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12523 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
12524 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
12526 if (place && JUMP_P (place)
12527 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
12528 && (JUMP_LABEL (place) == NULL
12529 || JUMP_LABEL (place) == XEXP (note, 0)))
12531 rtx label = JUMP_LABEL (place);
12534 JUMP_LABEL (place) = XEXP (note, 0);
12535 else if (LABEL_P (label))
12536 LABEL_NUSES (label)--;
12539 if (place2 && JUMP_P (place2)
12540 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
12541 && (JUMP_LABEL (place2) == NULL
12542 || JUMP_LABEL (place2) == XEXP (note, 0)))
12544 rtx label = JUMP_LABEL (place2);
12547 JUMP_LABEL (place2) = XEXP (note, 0);
12548 else if (LABEL_P (label))
12549 LABEL_NUSES (label)--;
12555 /* This note says something about the value of a register prior
12556 to the execution of an insn. It is too much trouble to see
12557 if the note is still correct in all situations. It is better
12558 to simply delete it. */
12562 /* If we replaced the right hand side of FROM_INSN with a
12563 REG_EQUAL note, the original use of the dying register
12564 will not have been combined into I3 and I2. In such cases,
12565 FROM_INSN is guaranteed to be the first of the combined
12566 instructions, so we simply need to search back before
12567 FROM_INSN for the previous use or set of this register,
12568 then alter the notes there appropriately.
12570 If the register is used as an input in I3, it dies there.
12571 Similarly for I2, if it is nonzero and adjacent to I3.
12573 If the register is not used as an input in either I3 or I2
12574 and it is not one of the registers we were supposed to eliminate,
12575 there are two possibilities. We might have a non-adjacent I2
12576 or we might have somehow eliminated an additional register
12577 from a computation. For example, we might have had A & B where
12578 we discover that B will always be zero. In this case we will
12579 eliminate the reference to A.
12581 In both cases, we must search to see if we can find a previous
12582 use of A and put the death note there. */
12585 && from_insn == i2mod
12586 && !reg_overlap_mentioned_p (XEXP (note, 0), i2mod_new_rhs))
12591 && CALL_P (from_insn)
12592 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12594 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12596 else if (i2 != 0 && next_nonnote_insn (i2) == i3
12597 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12599 else if ((rtx_equal_p (XEXP (note, 0), elim_i2)
12601 && reg_overlap_mentioned_p (XEXP (note, 0),
12603 || rtx_equal_p (XEXP (note, 0), elim_i1))
12610 basic_block bb = this_basic_block;
12612 for (tem = PREV_INSN (tem); place == 0; tem = PREV_INSN (tem))
12614 if (! INSN_P (tem))
12616 if (tem == BB_HEAD (bb))
12621 /* If the register is being set at TEM, see if that is all
12622 TEM is doing. If so, delete TEM. Otherwise, make this
12623 into a REG_UNUSED note instead. Don't delete sets to
12624 global register vars. */
12625 if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
12626 || !global_regs[REGNO (XEXP (note, 0))])
12627 && reg_set_p (XEXP (note, 0), PATTERN (tem)))
12629 rtx set = single_set (tem);
12630 rtx inner_dest = 0;
12632 rtx cc0_setter = NULL_RTX;
12636 for (inner_dest = SET_DEST (set);
12637 (GET_CODE (inner_dest) == STRICT_LOW_PART
12638 || GET_CODE (inner_dest) == SUBREG
12639 || GET_CODE (inner_dest) == ZERO_EXTRACT);
12640 inner_dest = XEXP (inner_dest, 0))
12643 /* Verify that it was the set, and not a clobber that
12644 modified the register.
12646 CC0 targets must be careful to maintain setter/user
12647 pairs. If we cannot delete the setter due to side
12648 effects, mark the user with an UNUSED note instead
12651 if (set != 0 && ! side_effects_p (SET_SRC (set))
12652 && rtx_equal_p (XEXP (note, 0), inner_dest)
12654 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12655 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12656 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12660 /* Move the notes and links of TEM elsewhere.
12661 This might delete other dead insns recursively.
12662 First set the pattern to something that won't use
12664 rtx old_notes = REG_NOTES (tem);
12666 PATTERN (tem) = pc_rtx;
12667 REG_NOTES (tem) = NULL;
12669 distribute_notes (old_notes, tem, tem, NULL_RTX,
12670 NULL_RTX, NULL_RTX);
12671 distribute_links (LOG_LINKS (tem));
12673 SET_INSN_DELETED (tem);
12678 /* Delete the setter too. */
12681 PATTERN (cc0_setter) = pc_rtx;
12682 old_notes = REG_NOTES (cc0_setter);
12683 REG_NOTES (cc0_setter) = NULL;
12685 distribute_notes (old_notes, cc0_setter,
12686 cc0_setter, NULL_RTX,
12687 NULL_RTX, NULL_RTX);
12688 distribute_links (LOG_LINKS (cc0_setter));
12690 SET_INSN_DELETED (cc0_setter);
12691 if (cc0_setter == i2)
12698 PUT_REG_NOTE_KIND (note, REG_UNUSED);
12700 /* If there isn't already a REG_UNUSED note, put one
12701 here. Do not place a REG_DEAD note, even if
12702 the register is also used here; that would not
12703 match the algorithm used in lifetime analysis
12704 and can cause the consistency check in the
12705 scheduler to fail. */
12706 if (! find_regno_note (tem, REG_UNUSED,
12707 REGNO (XEXP (note, 0))))
12712 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12714 && find_reg_fusage (tem, USE, XEXP (note, 0))))
12718 /* If we are doing a 3->2 combination, and we have a
12719 register which formerly died in i3 and was not used
12720 by i2, which now no longer dies in i3 and is used in
12721 i2 but does not die in i2, and place is between i2
12722 and i3, then we may need to move a link from place to
12724 if (i2 && DF_INSN_LUID (place) > DF_INSN_LUID (i2)
12726 && DF_INSN_LUID (from_insn) > DF_INSN_LUID (i2)
12727 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12729 rtx links = LOG_LINKS (place);
12730 LOG_LINKS (place) = 0;
12731 distribute_links (links);
12736 if (tem == BB_HEAD (bb))
12742 /* If the register is set or already dead at PLACE, we needn't do
12743 anything with this note if it is still a REG_DEAD note.
12744 We check here if it is set at all, not if is it totally replaced,
12745 which is what `dead_or_set_p' checks, so also check for it being
12748 if (place && REG_NOTE_KIND (note) == REG_DEAD)
12750 unsigned int regno = REGNO (XEXP (note, 0));
12751 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
12753 if (dead_or_set_p (place, XEXP (note, 0))
12754 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12756 /* Unless the register previously died in PLACE, clear
12757 last_death. [I no longer understand why this is
12759 if (rsp->last_death != place)
12760 rsp->last_death = 0;
12764 rsp->last_death = place;
12766 /* If this is a death note for a hard reg that is occupying
12767 multiple registers, ensure that we are still using all
12768 parts of the object. If we find a piece of the object
12769 that is unused, we must arrange for an appropriate REG_DEAD
12770 note to be added for it. However, we can't just emit a USE
12771 and tag the note to it, since the register might actually
12772 be dead; so we recourse, and the recursive call then finds
12773 the previous insn that used this register. */
12775 if (place && regno < FIRST_PSEUDO_REGISTER
12776 && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
12778 unsigned int endregno = END_HARD_REGNO (XEXP (note, 0));
12782 for (i = regno; i < endregno; i++)
12783 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12784 && ! find_regno_fusage (place, USE, i))
12785 || dead_or_set_regno_p (place, i))
12790 /* Put only REG_DEAD notes for pieces that are
12791 not already dead or set. */
12793 for (i = regno; i < endregno;
12794 i += hard_regno_nregs[i][reg_raw_mode[i]])
12796 rtx piece = regno_reg_rtx[i];
12797 basic_block bb = this_basic_block;
12799 if (! dead_or_set_p (place, piece)
12800 && ! reg_bitfield_target_p (piece,
12804 = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX);
12806 distribute_notes (new_note, place, place,
12807 NULL_RTX, NULL_RTX, NULL_RTX);
12809 else if (! refers_to_regno_p (i, i + 1,
12810 PATTERN (place), 0)
12811 && ! find_regno_fusage (place, USE, i))
12812 for (tem = PREV_INSN (place); ;
12813 tem = PREV_INSN (tem))
12815 if (! INSN_P (tem))
12817 if (tem == BB_HEAD (bb))
12821 if (dead_or_set_p (tem, piece)
12822 || reg_bitfield_target_p (piece,
12825 add_reg_note (tem, REG_UNUSED, piece);
12839 /* Any other notes should not be present at this point in the
12841 gcc_unreachable ();
12846 XEXP (note, 1) = REG_NOTES (place);
12847 REG_NOTES (place) = note;
12852 = gen_rtx_fmt_ee (GET_CODE (note), REG_NOTE_KIND (note),
12853 XEXP (note, 0), REG_NOTES (place2));
12857 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12858 I3, I2, and I1 to new locations. This is also called to add a link
12859 pointing at I3 when I3's destination is changed. */
12862 distribute_links (rtx links)
12864 rtx link, next_link;
12866 for (link = links; link; link = next_link)
12872 next_link = XEXP (link, 1);
12874 /* If the insn that this link points to is a NOTE or isn't a single
12875 set, ignore it. In the latter case, it isn't clear what we
12876 can do other than ignore the link, since we can't tell which
12877 register it was for. Such links wouldn't be used by combine
12880 It is not possible for the destination of the target of the link to
12881 have been changed by combine. The only potential of this is if we
12882 replace I3, I2, and I1 by I3 and I2. But in that case the
12883 destination of I2 also remains unchanged. */
12885 if (NOTE_P (XEXP (link, 0))
12886 || (set = single_set (XEXP (link, 0))) == 0)
12889 reg = SET_DEST (set);
12890 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12891 || GET_CODE (reg) == STRICT_LOW_PART)
12892 reg = XEXP (reg, 0);
12894 /* A LOG_LINK is defined as being placed on the first insn that uses
12895 a register and points to the insn that sets the register. Start
12896 searching at the next insn after the target of the link and stop
12897 when we reach a set of the register or the end of the basic block.
12899 Note that this correctly handles the link that used to point from
12900 I3 to I2. Also note that not much searching is typically done here
12901 since most links don't point very far away. */
12903 for (insn = NEXT_INSN (XEXP (link, 0));
12904 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
12905 || BB_HEAD (this_basic_block->next_bb) != insn));
12906 insn = NEXT_INSN (insn))
12907 if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12909 if (reg_referenced_p (reg, PATTERN (insn)))
12913 else if (CALL_P (insn)
12914 && find_reg_fusage (insn, USE, reg))
12919 else if (INSN_P (insn) && reg_set_p (reg, insn))
12922 /* If we found a place to put the link, place it there unless there
12923 is already a link to the same insn as LINK at that point. */
12929 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12930 if (XEXP (link2, 0) == XEXP (link, 0))
12935 XEXP (link, 1) = LOG_LINKS (place);
12936 LOG_LINKS (place) = link;
12938 /* Set added_links_insn to the earliest insn we added a
12940 if (added_links_insn == 0
12941 || DF_INSN_LUID (added_links_insn) > DF_INSN_LUID (place))
12942 added_links_insn = place;
12948 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
12949 Check whether the expression pointer to by LOC is a register or
12950 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
12951 Otherwise return zero. */
12954 unmentioned_reg_p_1 (rtx *loc, void *expr)
12959 && (REG_P (x) || MEM_P (x))
12960 && ! reg_mentioned_p (x, (rtx) expr))
12965 /* Check for any register or memory mentioned in EQUIV that is not
12966 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
12967 of EXPR where some registers may have been replaced by constants. */
12970 unmentioned_reg_p (rtx equiv, rtx expr)
12972 return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
12976 dump_combine_stats (FILE *file)
12980 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12981 combine_attempts, combine_merges, combine_extras, combine_successes);
12985 dump_combine_total_stats (FILE *file)
12989 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12990 total_attempts, total_merges, total_extras, total_successes);
12994 gate_handle_combine (void)
12996 return (optimize > 0);
12999 /* Try combining insns through substitution. */
13000 static unsigned int
13001 rest_of_handle_combine (void)
13003 int rebuild_jump_labels_after_combine;
13005 df_set_flags (DF_LR_RUN_DCE + DF_DEFER_INSN_RESCAN);
13006 df_note_add_problem ();
13009 regstat_init_n_sets_and_refs ();
13011 rebuild_jump_labels_after_combine
13012 = combine_instructions (get_insns (), max_reg_num ());
13014 /* Combining insns may have turned an indirect jump into a
13015 direct jump. Rebuild the JUMP_LABEL fields of jumping
13017 if (rebuild_jump_labels_after_combine)
13019 timevar_push (TV_JUMP);
13020 rebuild_jump_labels (get_insns ());
13022 timevar_pop (TV_JUMP);
13025 regstat_free_n_sets_and_refs ();
13029 struct rtl_opt_pass pass_combine =
13033 "combine", /* name */
13034 gate_handle_combine, /* gate */
13035 rest_of_handle_combine, /* execute */
13038 0, /* static_pass_number */
13039 TV_COMBINE, /* tv_id */
13040 PROP_cfglayout, /* properties_required */
13041 0, /* properties_provided */
13042 0, /* properties_destroyed */
13043 0, /* todo_flags_start */
13045 TODO_df_finish | TODO_verify_rtl_sharing |
13046 TODO_ggc_collect, /* todo_flags_finish */
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