1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - reg_n_refs is not adjusted in the rare case when a register is
57 no longer required in a computation
58 - there are extremely rare cases (see distribute_regnotes) when a
60 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
61 removed because there is no way to know which register it was
64 To simplify substitution, we combine only when the earlier insn(s)
65 consist of only a single assignment. To simplify updating afterward,
66 we never combine when a subroutine call appears in the middle.
68 Since we do not represent assignments to CC0 explicitly except when that
69 is all an insn does, there is no LOG_LINKS entry in an insn that uses
70 the condition code for the insn that set the condition code.
71 Fortunately, these two insns must be consecutive.
72 Therefore, every JUMP_INSN is taken to have an implicit logical link
73 to the preceding insn. This is not quite right, since non-jumps can
74 also use the condition code; but in practice such insns would not
83 #include "hard-reg-set.h"
84 #include "basic-block.h"
85 #include "insn-config.h"
87 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
89 #include "insn-flags.h"
90 #include "insn-codes.h"
91 #include "insn-attr.h"
97 #ifndef ACCUMULATE_OUTGOING_ARGS
98 #define ACCUMULATE_OUTGOING_ARGS 0
101 /* Supply a default definition for PUSH_ARGS. */
104 #define PUSH_ARGS !ACCUMULATE_OUTGOING_ARGS
110 /* It is not safe to use ordinary gen_lowpart in combine.
111 Use gen_lowpart_for_combine instead. See comments there. */
112 #define gen_lowpart dont_use_gen_lowpart_you_dummy
114 /* Number of attempts to combine instructions in this function. */
116 static int combine_attempts;
118 /* Number of attempts that got as far as substitution in this function. */
120 static int combine_merges;
122 /* Number of instructions combined with added SETs in this function. */
124 static int combine_extras;
126 /* Number of instructions combined in this function. */
128 static int combine_successes;
130 /* Totals over entire compilation. */
132 static int total_attempts, total_merges, total_extras, total_successes;
134 /* Define a default value for REVERSIBLE_CC_MODE.
135 We can never assume that a condition code mode is safe to reverse unless
136 the md tells us so. */
137 #ifndef REVERSIBLE_CC_MODE
138 #define REVERSIBLE_CC_MODE(MODE) 0
141 /* Vector mapping INSN_UIDs to cuids.
142 The cuids are like uids but increase monotonically always.
143 Combine always uses cuids so that it can compare them.
144 But actually renumbering the uids, which we used to do,
145 proves to be a bad idea because it makes it hard to compare
146 the dumps produced by earlier passes with those from later passes. */
148 static int *uid_cuid;
149 static int max_uid_cuid;
151 /* Get the cuid of an insn. */
153 #define INSN_CUID(INSN) \
154 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
156 /* Maximum register number, which is the size of the tables below. */
158 static unsigned int combine_max_regno;
160 /* Record last point of death of (hard or pseudo) register n. */
162 static rtx *reg_last_death;
164 /* Record last point of modification of (hard or pseudo) register n. */
166 static rtx *reg_last_set;
168 /* Record the cuid of the last insn that invalidated memory
169 (anything that writes memory, and subroutine calls, but not pushes). */
171 static int mem_last_set;
173 /* Record the cuid of the last CALL_INSN
174 so we can tell whether a potential combination crosses any calls. */
176 static int last_call_cuid;
178 /* When `subst' is called, this is the insn that is being modified
179 (by combining in a previous insn). The PATTERN of this insn
180 is still the old pattern partially modified and it should not be
181 looked at, but this may be used to examine the successors of the insn
182 to judge whether a simplification is valid. */
184 static rtx subst_insn;
186 /* This is an insn that belongs before subst_insn, but is not currently
187 on the insn chain. */
189 static rtx subst_prev_insn;
191 /* This is the lowest CUID that `subst' is currently dealing with.
192 get_last_value will not return a value if the register was set at or
193 after this CUID. If not for this mechanism, we could get confused if
194 I2 or I1 in try_combine were an insn that used the old value of a register
195 to obtain a new value. In that case, we might erroneously get the
196 new value of the register when we wanted the old one. */
198 static int subst_low_cuid;
200 /* This contains any hard registers that are used in newpat; reg_dead_at_p
201 must consider all these registers to be always live. */
203 static HARD_REG_SET newpat_used_regs;
205 /* This is an insn to which a LOG_LINKS entry has been added. If this
206 insn is the earlier than I2 or I3, combine should rescan starting at
209 static rtx added_links_insn;
211 /* Basic block number of the block in which we are performing combines. */
212 static int this_basic_block;
214 /* A bitmap indicating which blocks had registers go dead at entry.
215 After combine, we'll need to re-do global life analysis with
216 those blocks as starting points. */
217 static sbitmap refresh_blocks;
218 static int need_refresh;
220 /* The next group of arrays allows the recording of the last value assigned
221 to (hard or pseudo) register n. We use this information to see if a
222 operation being processed is redundant given a prior operation performed
223 on the register. For example, an `and' with a constant is redundant if
224 all the zero bits are already known to be turned off.
226 We use an approach similar to that used by cse, but change it in the
229 (1) We do not want to reinitialize at each label.
230 (2) It is useful, but not critical, to know the actual value assigned
231 to a register. Often just its form is helpful.
233 Therefore, we maintain the following arrays:
235 reg_last_set_value the last value assigned
236 reg_last_set_label records the value of label_tick when the
237 register was assigned
238 reg_last_set_table_tick records the value of label_tick when a
239 value using the register is assigned
240 reg_last_set_invalid set to non-zero when it is not valid
241 to use the value of this register in some
244 To understand the usage of these tables, it is important to understand
245 the distinction between the value in reg_last_set_value being valid
246 and the register being validly contained in some other expression in the
249 Entry I in reg_last_set_value is valid if it is non-zero, and either
250 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
252 Register I may validly appear in any expression returned for the value
253 of another register if reg_n_sets[i] is 1. It may also appear in the
254 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
255 reg_last_set_invalid[j] is zero.
257 If an expression is found in the table containing a register which may
258 not validly appear in an expression, the register is replaced by
259 something that won't match, (clobber (const_int 0)).
261 reg_last_set_invalid[i] is set non-zero when register I is being assigned
262 to and reg_last_set_table_tick[i] == label_tick. */
264 /* Record last value assigned to (hard or pseudo) register n. */
266 static rtx *reg_last_set_value;
268 /* Record the value of label_tick when the value for register n is placed in
269 reg_last_set_value[n]. */
271 static int *reg_last_set_label;
273 /* Record the value of label_tick when an expression involving register n
274 is placed in reg_last_set_value. */
276 static int *reg_last_set_table_tick;
278 /* Set non-zero if references to register n in expressions should not be
281 static char *reg_last_set_invalid;
283 /* Incremented for each label. */
285 static int label_tick;
287 /* Some registers that are set more than once and used in more than one
288 basic block are nevertheless always set in similar ways. For example,
289 a QImode register may be loaded from memory in two places on a machine
290 where byte loads zero extend.
292 We record in the following array what we know about the nonzero
293 bits of a register, specifically which bits are known to be zero.
295 If an entry is zero, it means that we don't know anything special. */
297 static unsigned HOST_WIDE_INT *reg_nonzero_bits;
299 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
300 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
302 static enum machine_mode nonzero_bits_mode;
304 /* Nonzero if we know that a register has some leading bits that are always
305 equal to the sign bit. */
307 static unsigned char *reg_sign_bit_copies;
309 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
310 It is zero while computing them and after combine has completed. This
311 former test prevents propagating values based on previously set values,
312 which can be incorrect if a variable is modified in a loop. */
314 static int nonzero_sign_valid;
316 /* These arrays are maintained in parallel with reg_last_set_value
317 and are used to store the mode in which the register was last set,
318 the bits that were known to be zero when it was last set, and the
319 number of sign bits copies it was known to have when it was last set. */
321 static enum machine_mode *reg_last_set_mode;
322 static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits;
323 static char *reg_last_set_sign_bit_copies;
325 /* Record one modification to rtl structure
326 to be undone by storing old_contents into *where.
327 is_int is 1 if the contents are an int. */
333 union {rtx r; unsigned int i;} old_contents;
334 union {rtx *r; unsigned int *i;} where;
337 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
338 num_undo says how many are currently recorded.
340 other_insn is nonzero if we have modified some other insn in the process
341 of working on subst_insn. It must be verified too.
343 previous_undos is the value of undobuf.undos when we started processing
344 this substitution. This will prevent gen_rtx_combine from re-used a piece
345 from the previous expression. Doing so can produce circular rtl
352 struct undo *previous_undos;
356 static struct undobuf undobuf;
358 /* Number of times the pseudo being substituted for
359 was found and replaced. */
361 static int n_occurrences;
363 static void do_SUBST PARAMS ((rtx *, rtx));
364 static void do_SUBST_INT PARAMS ((unsigned int *,
366 static void init_reg_last_arrays PARAMS ((void));
367 static void setup_incoming_promotions PARAMS ((void));
368 static void set_nonzero_bits_and_sign_copies PARAMS ((rtx, rtx, void *));
369 static int cant_combine_insn_p PARAMS ((rtx));
370 static int can_combine_p PARAMS ((rtx, rtx, rtx, rtx, rtx *, rtx *));
371 static int sets_function_arg_p PARAMS ((rtx));
372 static int combinable_i3pat PARAMS ((rtx, rtx *, rtx, rtx, int, rtx *));
373 static int contains_muldiv PARAMS ((rtx));
374 static rtx try_combine PARAMS ((rtx, rtx, rtx, int *));
375 static void undo_all PARAMS ((void));
376 static void undo_commit PARAMS ((void));
377 static rtx *find_split_point PARAMS ((rtx *, rtx));
378 static rtx subst PARAMS ((rtx, rtx, rtx, int, int));
379 static rtx combine_simplify_rtx PARAMS ((rtx, enum machine_mode, int, int));
380 static rtx simplify_if_then_else PARAMS ((rtx));
381 static rtx simplify_set PARAMS ((rtx));
382 static rtx simplify_logical PARAMS ((rtx, int));
383 static rtx expand_compound_operation PARAMS ((rtx));
384 static rtx expand_field_assignment PARAMS ((rtx));
385 static rtx make_extraction PARAMS ((enum machine_mode, rtx, HOST_WIDE_INT,
386 rtx, unsigned HOST_WIDE_INT, int,
388 static rtx extract_left_shift PARAMS ((rtx, int));
389 static rtx make_compound_operation PARAMS ((rtx, enum rtx_code));
390 static int get_pos_from_mask PARAMS ((unsigned HOST_WIDE_INT,
391 unsigned HOST_WIDE_INT *));
392 static rtx force_to_mode PARAMS ((rtx, enum machine_mode,
393 unsigned HOST_WIDE_INT, rtx, int));
394 static rtx if_then_else_cond PARAMS ((rtx, rtx *, rtx *));
395 static rtx known_cond PARAMS ((rtx, enum rtx_code, rtx, rtx));
396 static int rtx_equal_for_field_assignment_p PARAMS ((rtx, rtx));
397 static rtx make_field_assignment PARAMS ((rtx));
398 static rtx apply_distributive_law PARAMS ((rtx));
399 static rtx simplify_and_const_int PARAMS ((rtx, enum machine_mode, rtx,
400 unsigned HOST_WIDE_INT));
401 static unsigned HOST_WIDE_INT nonzero_bits PARAMS ((rtx, enum machine_mode));
402 static unsigned int num_sign_bit_copies PARAMS ((rtx, enum machine_mode));
403 static int merge_outer_ops PARAMS ((enum rtx_code *, HOST_WIDE_INT *,
404 enum rtx_code, HOST_WIDE_INT,
405 enum machine_mode, int *));
406 static rtx simplify_shift_const PARAMS ((rtx, enum rtx_code, enum machine_mode,
408 static int recog_for_combine PARAMS ((rtx *, rtx, rtx *));
409 static rtx gen_lowpart_for_combine PARAMS ((enum machine_mode, rtx));
410 static rtx gen_rtx_combine PARAMS ((enum rtx_code code, enum machine_mode mode,
412 static rtx gen_binary PARAMS ((enum rtx_code, enum machine_mode,
414 static rtx gen_unary PARAMS ((enum rtx_code, enum machine_mode,
415 enum machine_mode, rtx));
416 static enum rtx_code simplify_comparison PARAMS ((enum rtx_code, rtx *, rtx *));
417 static int reversible_comparison_p PARAMS ((rtx));
418 static void update_table_tick PARAMS ((rtx));
419 static void record_value_for_reg PARAMS ((rtx, rtx, rtx));
420 static void check_promoted_subreg PARAMS ((rtx, rtx));
421 static void record_dead_and_set_regs_1 PARAMS ((rtx, rtx, void *));
422 static void record_dead_and_set_regs PARAMS ((rtx));
423 static int get_last_value_validate PARAMS ((rtx *, rtx, int, int));
424 static rtx get_last_value PARAMS ((rtx));
425 static int use_crosses_set_p PARAMS ((rtx, int));
426 static void reg_dead_at_p_1 PARAMS ((rtx, rtx, void *));
427 static int reg_dead_at_p PARAMS ((rtx, rtx));
428 static void move_deaths PARAMS ((rtx, rtx, int, rtx, rtx *));
429 static int reg_bitfield_target_p PARAMS ((rtx, rtx));
430 static void distribute_notes PARAMS ((rtx, rtx, rtx, rtx, rtx, rtx));
431 static void distribute_links PARAMS ((rtx));
432 static void mark_used_regs_combine PARAMS ((rtx));
433 static int insn_cuid PARAMS ((rtx));
434 static void record_promoted_value PARAMS ((rtx, rtx));
436 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
437 insn. The substitution can be undone by undo_all. If INTO is already
438 set to NEWVAL, do not record this change. Because computing NEWVAL might
439 also call SUBST, we have to compute it before we put anything into
443 do_SUBST (into, newval)
449 if (oldval == newval)
453 buf = undobuf.frees, undobuf.frees = buf->next;
455 buf = (struct undo *) xmalloc (sizeof (struct undo));
459 buf->old_contents.r = oldval;
462 buf->next = undobuf.undos, undobuf.undos = buf;
465 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
467 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
468 for the value of a HOST_WIDE_INT value (including CONST_INT) is
472 do_SUBST_INT (into, newval)
473 unsigned int *into, newval;
476 unsigned int oldval = *into;
478 if (oldval == newval)
482 buf = undobuf.frees, undobuf.frees = buf->next;
484 buf = (struct undo *) xmalloc (sizeof (struct undo));
488 buf->old_contents.i = oldval;
491 buf->next = undobuf.undos, undobuf.undos = buf;
494 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
496 /* Main entry point for combiner. F is the first insn of the function.
497 NREGS is the first unused pseudo-reg number.
499 Return non-zero if the combiner has turned an indirect jump
500 instruction into a direct jump. */
502 combine_instructions (f, nregs)
506 register rtx insn, next;
511 register rtx links, nextlinks;
513 int new_direct_jump_p = 0;
515 combine_attempts = 0;
518 combine_successes = 0;
520 combine_max_regno = nregs;
522 reg_nonzero_bits = ((unsigned HOST_WIDE_INT *)
523 xcalloc (nregs, sizeof (unsigned HOST_WIDE_INT)));
525 = (unsigned char *) xcalloc (nregs, sizeof (unsigned char));
527 reg_last_death = (rtx *) xmalloc (nregs * sizeof (rtx));
528 reg_last_set = (rtx *) xmalloc (nregs * sizeof (rtx));
529 reg_last_set_value = (rtx *) xmalloc (nregs * sizeof (rtx));
530 reg_last_set_table_tick = (int *) xmalloc (nregs * sizeof (int));
531 reg_last_set_label = (int *) xmalloc (nregs * sizeof (int));
532 reg_last_set_invalid = (char *) xmalloc (nregs * sizeof (char));
534 = (enum machine_mode *) xmalloc (nregs * sizeof (enum machine_mode));
535 reg_last_set_nonzero_bits
536 = (unsigned HOST_WIDE_INT *) xmalloc (nregs * sizeof (HOST_WIDE_INT));
537 reg_last_set_sign_bit_copies
538 = (char *) xmalloc (nregs * sizeof (char));
540 init_reg_last_arrays ();
542 init_recog_no_volatile ();
544 /* Compute maximum uid value so uid_cuid can be allocated. */
546 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
547 if (INSN_UID (insn) > i)
550 uid_cuid = (int *) xmalloc ((i + 1) * sizeof (int));
553 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
555 /* Don't use reg_nonzero_bits when computing it. This can cause problems
556 when, for example, we have j <<= 1 in a loop. */
558 nonzero_sign_valid = 0;
560 /* Compute the mapping from uids to cuids.
561 Cuids are numbers assigned to insns, like uids,
562 except that cuids increase monotonically through the code.
564 Scan all SETs and see if we can deduce anything about what
565 bits are known to be zero for some registers and how many copies
566 of the sign bit are known to exist for those registers.
568 Also set any known values so that we can use it while searching
569 for what bits are known to be set. */
573 /* We need to initialize it here, because record_dead_and_set_regs may call
575 subst_prev_insn = NULL_RTX;
577 setup_incoming_promotions ();
579 refresh_blocks = sbitmap_alloc (n_basic_blocks);
580 sbitmap_zero (refresh_blocks);
583 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
585 uid_cuid[INSN_UID (insn)] = ++i;
591 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
593 record_dead_and_set_regs (insn);
596 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
597 if (REG_NOTE_KIND (links) == REG_INC)
598 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
603 if (GET_CODE (insn) == CODE_LABEL)
607 nonzero_sign_valid = 1;
609 /* Now scan all the insns in forward order. */
611 this_basic_block = -1;
615 init_reg_last_arrays ();
616 setup_incoming_promotions ();
618 for (insn = f; insn; insn = next ? next : NEXT_INSN (insn))
622 /* If INSN starts a new basic block, update our basic block number. */
623 if (this_basic_block + 1 < n_basic_blocks
624 && BLOCK_HEAD (this_basic_block + 1) == insn)
627 if (GET_CODE (insn) == CODE_LABEL)
630 else if (INSN_P (insn))
632 /* See if we know about function return values before this
633 insn based upon SUBREG flags. */
634 check_promoted_subreg (insn, PATTERN (insn));
636 /* Try this insn with each insn it links back to. */
638 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
639 if ((next = try_combine (insn, XEXP (links, 0),
640 NULL_RTX, &new_direct_jump_p)) != 0)
643 /* Try each sequence of three linked insns ending with this one. */
645 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
647 rtx link = XEXP (links, 0);
649 /* If the linked insn has been replaced by a note, then there
650 is no point in persuing this chain any further. */
651 if (GET_CODE (link) == NOTE)
654 for (nextlinks = LOG_LINKS (link);
656 nextlinks = XEXP (nextlinks, 1))
657 if ((next = try_combine (insn, XEXP (links, 0),
659 &new_direct_jump_p)) != 0)
664 /* Try to combine a jump insn that uses CC0
665 with a preceding insn that sets CC0, and maybe with its
666 logical predecessor as well.
667 This is how we make decrement-and-branch insns.
668 We need this special code because data flow connections
669 via CC0 do not get entered in LOG_LINKS. */
671 if (GET_CODE (insn) == JUMP_INSN
672 && (prev = prev_nonnote_insn (insn)) != 0
673 && GET_CODE (prev) == INSN
674 && sets_cc0_p (PATTERN (prev)))
676 if ((next = try_combine (insn, prev,
677 NULL_RTX, &new_direct_jump_p)) != 0)
680 for (nextlinks = LOG_LINKS (prev); nextlinks;
681 nextlinks = XEXP (nextlinks, 1))
682 if ((next = try_combine (insn, prev,
684 &new_direct_jump_p)) != 0)
688 /* Do the same for an insn that explicitly references CC0. */
689 if (GET_CODE (insn) == INSN
690 && (prev = prev_nonnote_insn (insn)) != 0
691 && GET_CODE (prev) == INSN
692 && sets_cc0_p (PATTERN (prev))
693 && GET_CODE (PATTERN (insn)) == SET
694 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
696 if ((next = try_combine (insn, prev,
697 NULL_RTX, &new_direct_jump_p)) != 0)
700 for (nextlinks = LOG_LINKS (prev); nextlinks;
701 nextlinks = XEXP (nextlinks, 1))
702 if ((next = try_combine (insn, prev,
704 &new_direct_jump_p)) != 0)
708 /* Finally, see if any of the insns that this insn links to
709 explicitly references CC0. If so, try this insn, that insn,
710 and its predecessor if it sets CC0. */
711 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
712 if (GET_CODE (XEXP (links, 0)) == INSN
713 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
714 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
715 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
716 && GET_CODE (prev) == INSN
717 && sets_cc0_p (PATTERN (prev))
718 && (next = try_combine (insn, XEXP (links, 0),
719 prev, &new_direct_jump_p)) != 0)
723 /* Try combining an insn with two different insns whose results it
725 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
726 for (nextlinks = XEXP (links, 1); nextlinks;
727 nextlinks = XEXP (nextlinks, 1))
728 if ((next = try_combine (insn, XEXP (links, 0),
730 &new_direct_jump_p)) != 0)
733 if (GET_CODE (insn) != NOTE)
734 record_dead_and_set_regs (insn);
743 compute_bb_for_insn (get_max_uid ());
744 update_life_info (refresh_blocks, UPDATE_LIFE_GLOBAL_RM_NOTES,
749 sbitmap_free (refresh_blocks);
750 free (reg_nonzero_bits);
751 free (reg_sign_bit_copies);
752 free (reg_last_death);
754 free (reg_last_set_value);
755 free (reg_last_set_table_tick);
756 free (reg_last_set_label);
757 free (reg_last_set_invalid);
758 free (reg_last_set_mode);
759 free (reg_last_set_nonzero_bits);
760 free (reg_last_set_sign_bit_copies);
764 struct undo *undo, *next;
765 for (undo = undobuf.frees; undo; undo = next)
773 total_attempts += combine_attempts;
774 total_merges += combine_merges;
775 total_extras += combine_extras;
776 total_successes += combine_successes;
778 nonzero_sign_valid = 0;
780 /* Make recognizer allow volatile MEMs again. */
783 return new_direct_jump_p;
786 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
789 init_reg_last_arrays ()
791 unsigned int nregs = combine_max_regno;
793 memset ((char *) reg_last_death, 0, nregs * sizeof (rtx));
794 memset ((char *) reg_last_set, 0, nregs * sizeof (rtx));
795 memset ((char *) reg_last_set_value, 0, nregs * sizeof (rtx));
796 memset ((char *) reg_last_set_table_tick, 0, nregs * sizeof (int));
797 memset ((char *) reg_last_set_label, 0, nregs * sizeof (int));
798 memset (reg_last_set_invalid, 0, nregs * sizeof (char));
799 memset ((char *) reg_last_set_mode, 0, nregs * sizeof (enum machine_mode));
800 memset ((char *) reg_last_set_nonzero_bits, 0, nregs * sizeof (HOST_WIDE_INT));
801 memset (reg_last_set_sign_bit_copies, 0, nregs * sizeof (char));
804 /* Set up any promoted values for incoming argument registers. */
807 setup_incoming_promotions ()
809 #ifdef PROMOTE_FUNCTION_ARGS
812 enum machine_mode mode;
814 rtx first = get_insns ();
816 #ifndef OUTGOING_REGNO
817 #define OUTGOING_REGNO(N) N
819 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
820 /* Check whether this register can hold an incoming pointer
821 argument. FUNCTION_ARG_REGNO_P tests outgoing register
822 numbers, so translate if necessary due to register windows. */
823 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno))
824 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
827 (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
830 gen_rtx_CLOBBER (mode, const0_rtx)));
835 /* Called via note_stores. If X is a pseudo that is narrower than
836 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
838 If we are setting only a portion of X and we can't figure out what
839 portion, assume all bits will be used since we don't know what will
842 Similarly, set how many bits of X are known to be copies of the sign bit
843 at all locations in the function. This is the smallest number implied
847 set_nonzero_bits_and_sign_copies (x, set, data)
850 void *data ATTRIBUTE_UNUSED;
854 if (GET_CODE (x) == REG
855 && REGNO (x) >= FIRST_PSEUDO_REGISTER
856 /* If this register is undefined at the start of the file, we can't
857 say what its contents were. */
858 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start, REGNO (x))
859 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
861 if (set == 0 || GET_CODE (set) == CLOBBER)
863 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
864 reg_sign_bit_copies[REGNO (x)] = 1;
868 /* If this is a complex assignment, see if we can convert it into a
869 simple assignment. */
870 set = expand_field_assignment (set);
872 /* If this is a simple assignment, or we have a paradoxical SUBREG,
873 set what we know about X. */
875 if (SET_DEST (set) == x
876 || (GET_CODE (SET_DEST (set)) == SUBREG
877 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
878 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
879 && SUBREG_REG (SET_DEST (set)) == x))
881 rtx src = SET_SRC (set);
883 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
884 /* If X is narrower than a word and SRC is a non-negative
885 constant that would appear negative in the mode of X,
886 sign-extend it for use in reg_nonzero_bits because some
887 machines (maybe most) will actually do the sign-extension
888 and this is the conservative approach.
890 ??? For 2.5, try to tighten up the MD files in this regard
891 instead of this kludge. */
893 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
894 && GET_CODE (src) == CONST_INT
896 && 0 != (INTVAL (src)
898 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
899 src = GEN_INT (INTVAL (src)
900 | ((HOST_WIDE_INT) (-1)
901 << GET_MODE_BITSIZE (GET_MODE (x))));
904 reg_nonzero_bits[REGNO (x)]
905 |= nonzero_bits (src, nonzero_bits_mode);
906 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
907 if (reg_sign_bit_copies[REGNO (x)] == 0
908 || reg_sign_bit_copies[REGNO (x)] > num)
909 reg_sign_bit_copies[REGNO (x)] = num;
913 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
914 reg_sign_bit_copies[REGNO (x)] = 1;
919 /* See if INSN can be combined into I3. PRED and SUCC are optionally
920 insns that were previously combined into I3 or that will be combined
921 into the merger of INSN and I3.
923 Return 0 if the combination is not allowed for any reason.
925 If the combination is allowed, *PDEST will be set to the single
926 destination of INSN and *PSRC to the single source, and this function
930 can_combine_p (insn, i3, pred, succ, pdest, psrc)
933 rtx pred ATTRIBUTE_UNUSED;
938 rtx set = 0, src, dest;
943 int all_adjacent = (succ ? (next_active_insn (insn) == succ
944 && next_active_insn (succ) == i3)
945 : next_active_insn (insn) == i3);
947 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
948 or a PARALLEL consisting of such a SET and CLOBBERs.
950 If INSN has CLOBBER parallel parts, ignore them for our processing.
951 By definition, these happen during the execution of the insn. When it
952 is merged with another insn, all bets are off. If they are, in fact,
953 needed and aren't also supplied in I3, they may be added by
954 recog_for_combine. Otherwise, it won't match.
956 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
959 Get the source and destination of INSN. If more than one, can't
962 if (GET_CODE (PATTERN (insn)) == SET)
963 set = PATTERN (insn);
964 else if (GET_CODE (PATTERN (insn)) == PARALLEL
965 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
967 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
969 rtx elt = XVECEXP (PATTERN (insn), 0, i);
971 switch (GET_CODE (elt))
973 /* This is important to combine floating point insns
976 /* Combining an isolated USE doesn't make sense.
977 We depend here on combinable_i3_pat to reject them. */
978 /* The code below this loop only verifies that the inputs of
979 the SET in INSN do not change. We call reg_set_between_p
980 to verify that the REG in the USE does not change betweeen
982 If the USE in INSN was for a pseudo register, the matching
983 insn pattern will likely match any register; combining this
984 with any other USE would only be safe if we knew that the
985 used registers have identical values, or if there was
986 something to tell them apart, e.g. different modes. For
987 now, we forgo such compilcated tests and simply disallow
988 combining of USES of pseudo registers with any other USE. */
989 if (GET_CODE (XEXP (elt, 0)) == REG
990 && GET_CODE (PATTERN (i3)) == PARALLEL)
992 rtx i3pat = PATTERN (i3);
993 int i = XVECLEN (i3pat, 0) - 1;
994 unsigned int regno = REGNO (XEXP (elt, 0));
998 rtx i3elt = XVECEXP (i3pat, 0, i);
1000 if (GET_CODE (i3elt) == USE
1001 && GET_CODE (XEXP (i3elt, 0)) == REG
1002 && (REGNO (XEXP (i3elt, 0)) == regno
1003 ? reg_set_between_p (XEXP (elt, 0),
1004 PREV_INSN (insn), i3)
1005 : regno >= FIRST_PSEUDO_REGISTER))
1012 /* We can ignore CLOBBERs. */
1017 /* Ignore SETs whose result isn't used but not those that
1018 have side-effects. */
1019 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1020 && ! side_effects_p (elt))
1023 /* If we have already found a SET, this is a second one and
1024 so we cannot combine with this insn. */
1032 /* Anything else means we can't combine. */
1038 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1039 so don't do anything with it. */
1040 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1049 set = expand_field_assignment (set);
1050 src = SET_SRC (set), dest = SET_DEST (set);
1052 /* Don't eliminate a store in the stack pointer. */
1053 if (dest == stack_pointer_rtx
1054 /* If we couldn't eliminate a field assignment, we can't combine. */
1055 || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART
1056 /* Don't combine with an insn that sets a register to itself if it has
1057 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1058 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1059 /* Can't merge an ASM_OPERANDS. */
1060 || GET_CODE (src) == ASM_OPERANDS
1061 /* Can't merge a function call. */
1062 || GET_CODE (src) == CALL
1063 /* Don't eliminate a function call argument. */
1064 || (GET_CODE (i3) == CALL_INSN
1065 && (find_reg_fusage (i3, USE, dest)
1066 || (GET_CODE (dest) == REG
1067 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1068 && global_regs[REGNO (dest)])))
1069 /* Don't substitute into an incremented register. */
1070 || FIND_REG_INC_NOTE (i3, dest)
1071 || (succ && FIND_REG_INC_NOTE (succ, dest))
1073 /* Don't combine the end of a libcall into anything. */
1074 /* ??? This gives worse code, and appears to be unnecessary, since no
1075 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1076 use REG_RETVAL notes for noconflict blocks, but other code here
1077 makes sure that those insns don't disappear. */
1078 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
1080 /* Make sure that DEST is not used after SUCC but before I3. */
1081 || (succ && ! all_adjacent
1082 && reg_used_between_p (dest, succ, i3))
1083 /* Make sure that the value that is to be substituted for the register
1084 does not use any registers whose values alter in between. However,
1085 If the insns are adjacent, a use can't cross a set even though we
1086 think it might (this can happen for a sequence of insns each setting
1087 the same destination; reg_last_set of that register might point to
1088 a NOTE). If INSN has a REG_EQUIV note, the register is always
1089 equivalent to the memory so the substitution is valid even if there
1090 are intervening stores. Also, don't move a volatile asm or
1091 UNSPEC_VOLATILE across any other insns. */
1093 && (((GET_CODE (src) != MEM
1094 || ! find_reg_note (insn, REG_EQUIV, src))
1095 && use_crosses_set_p (src, INSN_CUID (insn)))
1096 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1097 || GET_CODE (src) == UNSPEC_VOLATILE))
1098 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1099 better register allocation by not doing the combine. */
1100 || find_reg_note (i3, REG_NO_CONFLICT, dest)
1101 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
1102 /* Don't combine across a CALL_INSN, because that would possibly
1103 change whether the life span of some REGs crosses calls or not,
1104 and it is a pain to update that information.
1105 Exception: if source is a constant, moving it later can't hurt.
1106 Accept that special case, because it helps -fforce-addr a lot. */
1107 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
1110 /* DEST must either be a REG or CC0. */
1111 if (GET_CODE (dest) == REG)
1113 /* If register alignment is being enforced for multi-word items in all
1114 cases except for parameters, it is possible to have a register copy
1115 insn referencing a hard register that is not allowed to contain the
1116 mode being copied and which would not be valid as an operand of most
1117 insns. Eliminate this problem by not combining with such an insn.
1119 Also, on some machines we don't want to extend the life of a hard
1122 if (GET_CODE (src) == REG
1123 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1124 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1125 /* Don't extend the life of a hard register unless it is
1126 user variable (if we have few registers) or it can't
1127 fit into the desired register (meaning something special
1129 Also avoid substituting a return register into I3, because
1130 reload can't handle a conflict with constraints of other
1132 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1133 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1136 else if (GET_CODE (dest) != CC0)
1139 /* Don't substitute for a register intended as a clobberable operand.
1140 Similarly, don't substitute an expression containing a register that
1141 will be clobbered in I3. */
1142 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1143 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1144 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
1145 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0),
1147 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)))
1150 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1151 or not), reject, unless nothing volatile comes between it and I3 */
1153 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1155 /* Make sure succ doesn't contain a volatile reference. */
1156 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1159 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1160 if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1164 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1165 to be an explicit register variable, and was chosen for a reason. */
1167 if (GET_CODE (src) == ASM_OPERANDS
1168 && GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1171 /* If there are any volatile insns between INSN and I3, reject, because
1172 they might affect machine state. */
1174 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1175 if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1178 /* If INSN or I2 contains an autoincrement or autodecrement,
1179 make sure that register is not used between there and I3,
1180 and not already used in I3 either.
1181 Also insist that I3 not be a jump; if it were one
1182 and the incremented register were spilled, we would lose. */
1185 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1186 if (REG_NOTE_KIND (link) == REG_INC
1187 && (GET_CODE (i3) == JUMP_INSN
1188 || reg_used_between_p (XEXP (link, 0), insn, i3)
1189 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1194 /* Don't combine an insn that follows a CC0-setting insn.
1195 An insn that uses CC0 must not be separated from the one that sets it.
1196 We do, however, allow I2 to follow a CC0-setting insn if that insn
1197 is passed as I1; in that case it will be deleted also.
1198 We also allow combining in this case if all the insns are adjacent
1199 because that would leave the two CC0 insns adjacent as well.
1200 It would be more logical to test whether CC0 occurs inside I1 or I2,
1201 but that would be much slower, and this ought to be equivalent. */
1203 p = prev_nonnote_insn (insn);
1204 if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
1209 /* If we get here, we have passed all the tests and the combination is
1218 /* Check if PAT is an insn - or a part of it - used to set up an
1219 argument for a function in a hard register. */
1222 sets_function_arg_p (pat)
1228 switch (GET_CODE (pat))
1231 return sets_function_arg_p (PATTERN (pat));
1234 for (i = XVECLEN (pat, 0); --i >= 0;)
1235 if (sets_function_arg_p (XVECEXP (pat, 0, i)))
1241 inner_dest = SET_DEST (pat);
1242 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1243 || GET_CODE (inner_dest) == SUBREG
1244 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1245 inner_dest = XEXP (inner_dest, 0);
1247 return (GET_CODE (inner_dest) == REG
1248 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1249 && FUNCTION_ARG_REGNO_P (REGNO (inner_dest)));
1258 /* LOC is the location within I3 that contains its pattern or the component
1259 of a PARALLEL of the pattern. We validate that it is valid for combining.
1261 One problem is if I3 modifies its output, as opposed to replacing it
1262 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1263 so would produce an insn that is not equivalent to the original insns.
1267 (set (reg:DI 101) (reg:DI 100))
1268 (set (subreg:SI (reg:DI 101) 0) <foo>)
1270 This is NOT equivalent to:
1272 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1273 (set (reg:DI 101) (reg:DI 100))])
1275 Not only does this modify 100 (in which case it might still be valid
1276 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1278 We can also run into a problem if I2 sets a register that I1
1279 uses and I1 gets directly substituted into I3 (not via I2). In that
1280 case, we would be getting the wrong value of I2DEST into I3, so we
1281 must reject the combination. This case occurs when I2 and I1 both
1282 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1283 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
1284 of a SET must prevent combination from occurring.
1286 Before doing the above check, we first try to expand a field assignment
1287 into a set of logical operations.
1289 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
1290 we place a register that is both set and used within I3. If more than one
1291 such register is detected, we fail.
1293 Return 1 if the combination is valid, zero otherwise. */
1296 combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed)
1302 rtx *pi3dest_killed;
1306 if (GET_CODE (x) == SET)
1308 rtx set = expand_field_assignment (x);
1309 rtx dest = SET_DEST (set);
1310 rtx src = SET_SRC (set);
1311 rtx inner_dest = dest;
1314 rtx inner_src = src;
1319 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1320 || GET_CODE (inner_dest) == SUBREG
1321 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1322 inner_dest = XEXP (inner_dest, 0);
1324 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1327 while (GET_CODE (inner_src) == STRICT_LOW_PART
1328 || GET_CODE (inner_src) == SUBREG
1329 || GET_CODE (inner_src) == ZERO_EXTRACT)
1330 inner_src = XEXP (inner_src, 0);
1332 /* If it is better that two different modes keep two different pseudos,
1333 avoid combining them. This avoids producing the following pattern
1335 (set (subreg:SI (reg/v:QI 21) 0)
1336 (lshiftrt:SI (reg/v:SI 20)
1338 If that were made, reload could not handle the pair of
1339 reg 20/21, since it would try to get any GENERAL_REGS
1340 but some of them don't handle QImode. */
1342 if (rtx_equal_p (inner_src, i2dest)
1343 && GET_CODE (inner_dest) == REG
1344 && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest)))
1348 /* Check for the case where I3 modifies its output, as
1350 if ((inner_dest != dest
1351 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1352 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1354 /* This is the same test done in can_combine_p except we can't test
1355 all_adjacent; we don't have to, since this instruction will stay
1356 in place, thus we are not considering increasing the lifetime of
1359 Also, if this insn sets a function argument, combining it with
1360 something that might need a spill could clobber a previous
1361 function argument; the all_adjacent test in can_combine_p also
1362 checks this; here, we do a more specific test for this case. */
1364 || (GET_CODE (inner_dest) == REG
1365 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1366 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1367 GET_MODE (inner_dest))))
1368 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1371 /* If DEST is used in I3, it is being killed in this insn,
1372 so record that for later.
1373 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1374 STACK_POINTER_REGNUM, since these are always considered to be
1375 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1376 if (pi3dest_killed && GET_CODE (dest) == REG
1377 && reg_referenced_p (dest, PATTERN (i3))
1378 && REGNO (dest) != FRAME_POINTER_REGNUM
1379 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1380 && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
1382 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1383 && (REGNO (dest) != ARG_POINTER_REGNUM
1384 || ! fixed_regs [REGNO (dest)])
1386 && REGNO (dest) != STACK_POINTER_REGNUM)
1388 if (*pi3dest_killed)
1391 *pi3dest_killed = dest;
1395 else if (GET_CODE (x) == PARALLEL)
1399 for (i = 0; i < XVECLEN (x, 0); i++)
1400 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1401 i1_not_in_src, pi3dest_killed))
1408 /* Return 1 if X is an arithmetic expression that contains a multiplication
1409 and division. We don't count multiplications by powers of two here. */
1415 switch (GET_CODE (x))
1417 case MOD: case DIV: case UMOD: case UDIV:
1421 return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1422 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1424 switch (GET_RTX_CLASS (GET_CODE (x)))
1426 case 'c': case '<': case '2':
1427 return contains_muldiv (XEXP (x, 0))
1428 || contains_muldiv (XEXP (x, 1));
1431 return contains_muldiv (XEXP (x, 0));
1439 /* Determine whether INSN can be used in a combination. Return nonzero if
1440 not. This is used in try_combine to detect early some cases where we
1441 can't perform combinations. */
1444 cant_combine_insn_p (insn)
1450 /* If this isn't really an insn, we can't do anything.
1451 This can occur when flow deletes an insn that it has merged into an
1452 auto-increment address. */
1453 if (! INSN_P (insn))
1456 /* Never combine loads and stores involving hard regs. The register
1457 allocator can usually handle such reg-reg moves by tying. If we allow
1458 the combiner to make substitutions of hard regs, we risk aborting in
1459 reload on machines that have SMALL_REGISTER_CLASSES.
1460 As an exception, we allow combinations involving fixed regs; these are
1461 not available to the register allocator so there's no risk involved. */
1463 set = single_set (insn);
1466 src = SET_SRC (set);
1467 dest = SET_DEST (set);
1468 if (REG_P (src) && REG_P (dest)
1469 && ((REGNO (src) < FIRST_PSEUDO_REGISTER
1470 && ! fixed_regs[REGNO (src)])
1471 || (REGNO (dest) < FIRST_PSEUDO_REGISTER
1472 && ! fixed_regs[REGNO (dest)])))
1478 /* Try to combine the insns I1 and I2 into I3.
1479 Here I1 and I2 appear earlier than I3.
1480 I1 can be zero; then we combine just I2 into I3.
1482 It we are combining three insns and the resulting insn is not recognized,
1483 try splitting it into two insns. If that happens, I2 and I3 are retained
1484 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1487 Return 0 if the combination does not work. Then nothing is changed.
1488 If we did the combination, return the insn at which combine should
1491 Set NEW_DIRECT_JUMP_P to a non-zero value if try_combine creates a
1492 new direct jump instruction. */
1495 try_combine (i3, i2, i1, new_direct_jump_p)
1496 register rtx i3, i2, i1;
1497 register int *new_direct_jump_p;
1499 /* New patterns for I3 and I2, respectively. */
1500 rtx newpat, newi2pat = 0;
1501 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1502 int added_sets_1, added_sets_2;
1503 /* Total number of SETs to put into I3. */
1505 /* Nonzero is I2's body now appears in I3. */
1507 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1508 int insn_code_number, i2_code_number = 0, other_code_number = 0;
1509 /* Contains I3 if the destination of I3 is used in its source, which means
1510 that the old life of I3 is being killed. If that usage is placed into
1511 I2 and not in I3, a REG_DEAD note must be made. */
1512 rtx i3dest_killed = 0;
1513 /* SET_DEST and SET_SRC of I2 and I1. */
1514 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1515 /* PATTERN (I2), or a copy of it in certain cases. */
1517 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1518 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1519 int i1_feeds_i3 = 0;
1520 /* Notes that must be added to REG_NOTES in I3 and I2. */
1521 rtx new_i3_notes, new_i2_notes;
1522 /* Notes that we substituted I3 into I2 instead of the normal case. */
1523 int i3_subst_into_i2 = 0;
1524 /* Notes that I1, I2 or I3 is a MULT operation. */
1532 /* Exit early if one of the insns involved can't be used for
1534 if (cant_combine_insn_p (i3)
1535 || cant_combine_insn_p (i2)
1536 || (i1 && cant_combine_insn_p (i1))
1537 /* We also can't do anything if I3 has a
1538 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1541 /* ??? This gives worse code, and appears to be unnecessary, since no
1542 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1543 || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1549 undobuf.other_insn = 0;
1551 /* Reset the hard register usage information. */
1552 CLEAR_HARD_REG_SET (newpat_used_regs);
1554 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1555 code below, set I1 to be the earlier of the two insns. */
1556 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1557 temp = i1, i1 = i2, i2 = temp;
1559 added_links_insn = 0;
1561 /* First check for one important special-case that the code below will
1562 not handle. Namely, the case where I1 is zero, I2 has multiple sets,
1563 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1564 we may be able to replace that destination with the destination of I3.
1565 This occurs in the common code where we compute both a quotient and
1566 remainder into a structure, in which case we want to do the computation
1567 directly into the structure to avoid register-register copies.
1569 We make very conservative checks below and only try to handle the
1570 most common cases of this. For example, we only handle the case
1571 where I2 and I3 are adjacent to avoid making difficult register
1574 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1575 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1576 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1577 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1578 && GET_CODE (PATTERN (i2)) == PARALLEL
1579 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1580 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1581 below would need to check what is inside (and reg_overlap_mentioned_p
1582 doesn't support those codes anyway). Don't allow those destinations;
1583 the resulting insn isn't likely to be recognized anyway. */
1584 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1585 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1586 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1587 SET_DEST (PATTERN (i3)))
1588 && next_real_insn (i2) == i3)
1590 rtx p2 = PATTERN (i2);
1592 /* Make sure that the destination of I3,
1593 which we are going to substitute into one output of I2,
1594 is not used within another output of I2. We must avoid making this:
1595 (parallel [(set (mem (reg 69)) ...)
1596 (set (reg 69) ...)])
1597 which is not well-defined as to order of actions.
1598 (Besides, reload can't handle output reloads for this.)
1600 The problem can also happen if the dest of I3 is a memory ref,
1601 if another dest in I2 is an indirect memory ref. */
1602 for (i = 0; i < XVECLEN (p2, 0); i++)
1603 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1604 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1605 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1606 SET_DEST (XVECEXP (p2, 0, i))))
1609 if (i == XVECLEN (p2, 0))
1610 for (i = 0; i < XVECLEN (p2, 0); i++)
1611 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1612 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1613 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1618 subst_low_cuid = INSN_CUID (i2);
1620 added_sets_2 = added_sets_1 = 0;
1621 i2dest = SET_SRC (PATTERN (i3));
1623 /* Replace the dest in I2 with our dest and make the resulting
1624 insn the new pattern for I3. Then skip to where we
1625 validate the pattern. Everything was set up above. */
1626 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1627 SET_DEST (PATTERN (i3)));
1630 i3_subst_into_i2 = 1;
1631 goto validate_replacement;
1635 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1636 one of those words to another constant, merge them by making a new
1639 && (temp = single_set (i2)) != 0
1640 && (GET_CODE (SET_SRC (temp)) == CONST_INT
1641 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
1642 && GET_CODE (SET_DEST (temp)) == REG
1643 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp))) == MODE_INT
1644 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp))) == 2 * UNITS_PER_WORD
1645 && GET_CODE (PATTERN (i3)) == SET
1646 && GET_CODE (SET_DEST (PATTERN (i3))) == SUBREG
1647 && SUBREG_REG (SET_DEST (PATTERN (i3))) == SET_DEST (temp)
1648 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3)))) == MODE_INT
1649 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3)))) == UNITS_PER_WORD
1650 && GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT)
1652 HOST_WIDE_INT lo, hi;
1654 if (GET_CODE (SET_SRC (temp)) == CONST_INT)
1655 lo = INTVAL (SET_SRC (temp)), hi = lo < 0 ? -1 : 0;
1658 lo = CONST_DOUBLE_LOW (SET_SRC (temp));
1659 hi = CONST_DOUBLE_HIGH (SET_SRC (temp));
1662 if (subreg_lowpart_p (SET_DEST (PATTERN (i3))))
1663 lo = INTVAL (SET_SRC (PATTERN (i3)));
1665 hi = INTVAL (SET_SRC (PATTERN (i3)));
1669 subst_low_cuid = INSN_CUID (i2);
1670 added_sets_2 = added_sets_1 = 0;
1671 i2dest = SET_DEST (temp);
1673 SUBST (SET_SRC (temp),
1674 immed_double_const (lo, hi, GET_MODE (SET_DEST (temp))));
1676 newpat = PATTERN (i2);
1677 i3_subst_into_i2 = 1;
1678 goto validate_replacement;
1682 /* If we have no I1 and I2 looks like:
1683 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1685 make up a dummy I1 that is
1688 (set (reg:CC X) (compare:CC Y (const_int 0)))
1690 (We can ignore any trailing CLOBBERs.)
1692 This undoes a previous combination and allows us to match a branch-and-
1695 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1696 && XVECLEN (PATTERN (i2), 0) >= 2
1697 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1698 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1700 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1701 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1702 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1703 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1704 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1705 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1707 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1708 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1713 /* We make I1 with the same INSN_UID as I2. This gives it
1714 the same INSN_CUID for value tracking. Our fake I1 will
1715 never appear in the insn stream so giving it the same INSN_UID
1716 as I2 will not cause a problem. */
1718 subst_prev_insn = i1
1719 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
1720 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
1723 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1724 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1725 SET_DEST (PATTERN (i1)));
1730 /* Verify that I2 and I1 are valid for combining. */
1731 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1732 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1738 /* Record whether I2DEST is used in I2SRC and similarly for the other
1739 cases. Knowing this will help in register status updating below. */
1740 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1741 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1742 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1744 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1746 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1748 /* Ensure that I3's pattern can be the destination of combines. */
1749 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1750 i1 && i2dest_in_i1src && i1_feeds_i3,
1757 /* See if any of the insns is a MULT operation. Unless one is, we will
1758 reject a combination that is, since it must be slower. Be conservative
1760 if (GET_CODE (i2src) == MULT
1761 || (i1 != 0 && GET_CODE (i1src) == MULT)
1762 || (GET_CODE (PATTERN (i3)) == SET
1763 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
1766 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1767 We used to do this EXCEPT in one case: I3 has a post-inc in an
1768 output operand. However, that exception can give rise to insns like
1770 which is a famous insn on the PDP-11 where the value of r3 used as the
1771 source was model-dependent. Avoid this sort of thing. */
1774 if (!(GET_CODE (PATTERN (i3)) == SET
1775 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1776 && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1777 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1778 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1779 /* It's not the exception. */
1782 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1783 if (REG_NOTE_KIND (link) == REG_INC
1784 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1786 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1793 /* See if the SETs in I1 or I2 need to be kept around in the merged
1794 instruction: whenever the value set there is still needed past I3.
1795 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1797 For the SET in I1, we have two cases: If I1 and I2 independently
1798 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1799 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1800 in I1 needs to be kept around unless I1DEST dies or is set in either
1801 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1802 I1DEST. If so, we know I1 feeds into I2. */
1804 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1807 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1808 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1810 /* If the set in I2 needs to be kept around, we must make a copy of
1811 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1812 PATTERN (I2), we are only substituting for the original I1DEST, not into
1813 an already-substituted copy. This also prevents making self-referential
1814 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1817 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1818 ? gen_rtx_SET (VOIDmode, i2dest, i2src)
1822 i2pat = copy_rtx (i2pat);
1826 /* Substitute in the latest insn for the regs set by the earlier ones. */
1828 maxreg = max_reg_num ();
1832 /* It is possible that the source of I2 or I1 may be performing an
1833 unneeded operation, such as a ZERO_EXTEND of something that is known
1834 to have the high part zero. Handle that case by letting subst look at
1835 the innermost one of them.
1837 Another way to do this would be to have a function that tries to
1838 simplify a single insn instead of merging two or more insns. We don't
1839 do this because of the potential of infinite loops and because
1840 of the potential extra memory required. However, doing it the way
1841 we are is a bit of a kludge and doesn't catch all cases.
1843 But only do this if -fexpensive-optimizations since it slows things down
1844 and doesn't usually win. */
1846 if (flag_expensive_optimizations)
1848 /* Pass pc_rtx so no substitutions are done, just simplifications.
1849 The cases that we are interested in here do not involve the few
1850 cases were is_replaced is checked. */
1853 subst_low_cuid = INSN_CUID (i1);
1854 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1858 subst_low_cuid = INSN_CUID (i2);
1859 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1862 undobuf.previous_undos = undobuf.undos;
1866 /* Many machines that don't use CC0 have insns that can both perform an
1867 arithmetic operation and set the condition code. These operations will
1868 be represented as a PARALLEL with the first element of the vector
1869 being a COMPARE of an arithmetic operation with the constant zero.
1870 The second element of the vector will set some pseudo to the result
1871 of the same arithmetic operation. If we simplify the COMPARE, we won't
1872 match such a pattern and so will generate an extra insn. Here we test
1873 for this case, where both the comparison and the operation result are
1874 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1875 I2SRC. Later we will make the PARALLEL that contains I2. */
1877 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1878 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1879 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1880 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1882 #ifdef EXTRA_CC_MODES
1884 enum machine_mode compare_mode;
1887 newpat = PATTERN (i3);
1888 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1892 #ifdef EXTRA_CC_MODES
1893 /* See if a COMPARE with the operand we substituted in should be done
1894 with the mode that is currently being used. If not, do the same
1895 processing we do in `subst' for a SET; namely, if the destination
1896 is used only once, try to replace it with a register of the proper
1897 mode and also replace the COMPARE. */
1898 if (undobuf.other_insn == 0
1899 && (cc_use = find_single_use (SET_DEST (newpat), i3,
1900 &undobuf.other_insn))
1901 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
1903 != GET_MODE (SET_DEST (newpat))))
1905 unsigned int regno = REGNO (SET_DEST (newpat));
1906 rtx new_dest = gen_rtx_REG (compare_mode, regno);
1908 if (regno < FIRST_PSEUDO_REGISTER
1909 || (REG_N_SETS (regno) == 1 && ! added_sets_2
1910 && ! REG_USERVAR_P (SET_DEST (newpat))))
1912 if (regno >= FIRST_PSEUDO_REGISTER)
1913 SUBST (regno_reg_rtx[regno], new_dest);
1915 SUBST (SET_DEST (newpat), new_dest);
1916 SUBST (XEXP (*cc_use, 0), new_dest);
1917 SUBST (SET_SRC (newpat),
1918 gen_rtx_combine (COMPARE, compare_mode,
1919 i2src, const0_rtx));
1922 undobuf.other_insn = 0;
1929 n_occurrences = 0; /* `subst' counts here */
1931 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1932 need to make a unique copy of I2SRC each time we substitute it
1933 to avoid self-referential rtl. */
1935 subst_low_cuid = INSN_CUID (i2);
1936 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1937 ! i1_feeds_i3 && i1dest_in_i1src);
1938 undobuf.previous_undos = undobuf.undos;
1940 /* Record whether i2's body now appears within i3's body. */
1941 i2_is_used = n_occurrences;
1944 /* If we already got a failure, don't try to do more. Otherwise,
1945 try to substitute in I1 if we have it. */
1947 if (i1 && GET_CODE (newpat) != CLOBBER)
1949 /* Before we can do this substitution, we must redo the test done
1950 above (see detailed comments there) that ensures that I1DEST
1951 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1953 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
1961 subst_low_cuid = INSN_CUID (i1);
1962 newpat = subst (newpat, i1dest, i1src, 0, 0);
1963 undobuf.previous_undos = undobuf.undos;
1966 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1967 to count all the ways that I2SRC and I1SRC can be used. */
1968 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
1969 && i2_is_used + added_sets_2 > 1)
1970 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
1971 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
1973 /* Fail if we tried to make a new register (we used to abort, but there's
1974 really no reason to). */
1975 || max_reg_num () != maxreg
1976 /* Fail if we couldn't do something and have a CLOBBER. */
1977 || GET_CODE (newpat) == CLOBBER
1978 /* Fail if this new pattern is a MULT and we didn't have one before
1979 at the outer level. */
1980 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
1987 /* If the actions of the earlier insns must be kept
1988 in addition to substituting them into the latest one,
1989 we must make a new PARALLEL for the latest insn
1990 to hold additional the SETs. */
1992 if (added_sets_1 || added_sets_2)
1996 if (GET_CODE (newpat) == PARALLEL)
1998 rtvec old = XVEC (newpat, 0);
1999 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
2000 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2001 bcopy ((char *) &old->elem[0], (char *) XVEC (newpat, 0)->elem,
2002 sizeof (old->elem[0]) * old->num_elem);
2007 total_sets = 1 + added_sets_1 + added_sets_2;
2008 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2009 XVECEXP (newpat, 0, 0) = old;
2013 XVECEXP (newpat, 0, --total_sets)
2014 = (GET_CODE (PATTERN (i1)) == PARALLEL
2015 ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
2019 /* If there is no I1, use I2's body as is. We used to also not do
2020 the subst call below if I2 was substituted into I3,
2021 but that could lose a simplification. */
2023 XVECEXP (newpat, 0, --total_sets) = i2pat;
2025 /* See comment where i2pat is assigned. */
2026 XVECEXP (newpat, 0, --total_sets)
2027 = subst (i2pat, i1dest, i1src, 0, 0);
2031 /* We come here when we are replacing a destination in I2 with the
2032 destination of I3. */
2033 validate_replacement:
2035 /* Note which hard regs this insn has as inputs. */
2036 mark_used_regs_combine (newpat);
2038 /* Is the result of combination a valid instruction? */
2039 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2041 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2042 the second SET's destination is a register that is unused. In that case,
2043 we just need the first SET. This can occur when simplifying a divmod
2044 insn. We *must* test for this case here because the code below that
2045 splits two independent SETs doesn't handle this case correctly when it
2046 updates the register status. Also check the case where the first
2047 SET's destination is unused. That would not cause incorrect code, but
2048 does cause an unneeded insn to remain. */
2050 if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
2051 && XVECLEN (newpat, 0) == 2
2052 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2053 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2054 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
2055 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
2056 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
2057 && asm_noperands (newpat) < 0)
2059 newpat = XVECEXP (newpat, 0, 0);
2060 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2063 else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
2064 && XVECLEN (newpat, 0) == 2
2065 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2066 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2067 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
2068 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
2069 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
2070 && asm_noperands (newpat) < 0)
2072 newpat = XVECEXP (newpat, 0, 1);
2073 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2076 /* If we were combining three insns and the result is a simple SET
2077 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2078 insns. There are two ways to do this. It can be split using a
2079 machine-specific method (like when you have an addition of a large
2080 constant) or by combine in the function find_split_point. */
2082 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2083 && asm_noperands (newpat) < 0)
2085 rtx m_split, *split;
2086 rtx ni2dest = i2dest;
2088 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2089 use I2DEST as a scratch register will help. In the latter case,
2090 convert I2DEST to the mode of the source of NEWPAT if we can. */
2092 m_split = split_insns (newpat, i3);
2094 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2095 inputs of NEWPAT. */
2097 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2098 possible to try that as a scratch reg. This would require adding
2099 more code to make it work though. */
2101 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
2103 /* If I2DEST is a hard register or the only use of a pseudo,
2104 we can change its mode. */
2105 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
2106 && GET_MODE (SET_DEST (newpat)) != VOIDmode
2107 && GET_CODE (i2dest) == REG
2108 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2109 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2110 && ! REG_USERVAR_P (i2dest))))
2111 ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)),
2114 m_split = split_insns (gen_rtx_PARALLEL
2116 gen_rtvec (2, newpat,
2117 gen_rtx_CLOBBER (VOIDmode,
2122 if (m_split && GET_CODE (m_split) != SEQUENCE)
2124 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
2125 if (insn_code_number >= 0)
2128 else if (m_split && GET_CODE (m_split) == SEQUENCE
2129 && XVECLEN (m_split, 0) == 2
2130 && (next_real_insn (i2) == i3
2131 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split, 0, 0)),
2135 rtx newi3pat = PATTERN (XVECEXP (m_split, 0, 1));
2136 newi2pat = PATTERN (XVECEXP (m_split, 0, 0));
2138 i3set = single_set (XVECEXP (m_split, 0, 1));
2139 i2set = single_set (XVECEXP (m_split, 0, 0));
2141 /* In case we changed the mode of I2DEST, replace it in the
2142 pseudo-register table here. We can't do it above in case this
2143 code doesn't get executed and we do a split the other way. */
2145 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2146 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
2148 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2150 /* If I2 or I3 has multiple SETs, we won't know how to track
2151 register status, so don't use these insns. If I2's destination
2152 is used between I2 and I3, we also can't use these insns. */
2154 if (i2_code_number >= 0 && i2set && i3set
2155 && (next_real_insn (i2) == i3
2156 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
2157 insn_code_number = recog_for_combine (&newi3pat, i3,
2159 if (insn_code_number >= 0)
2162 /* It is possible that both insns now set the destination of I3.
2163 If so, we must show an extra use of it. */
2165 if (insn_code_number >= 0)
2167 rtx new_i3_dest = SET_DEST (i3set);
2168 rtx new_i2_dest = SET_DEST (i2set);
2170 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
2171 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
2172 || GET_CODE (new_i3_dest) == SUBREG)
2173 new_i3_dest = XEXP (new_i3_dest, 0);
2175 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
2176 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
2177 || GET_CODE (new_i2_dest) == SUBREG)
2178 new_i2_dest = XEXP (new_i2_dest, 0);
2180 if (GET_CODE (new_i3_dest) == REG
2181 && GET_CODE (new_i2_dest) == REG
2182 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
2183 REG_N_SETS (REGNO (new_i2_dest))++;
2187 /* If we can split it and use I2DEST, go ahead and see if that
2188 helps things be recognized. Verify that none of the registers
2189 are set between I2 and I3. */
2190 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
2192 && GET_CODE (i2dest) == REG
2194 /* We need I2DEST in the proper mode. If it is a hard register
2195 or the only use of a pseudo, we can change its mode. */
2196 && (GET_MODE (*split) == GET_MODE (i2dest)
2197 || GET_MODE (*split) == VOIDmode
2198 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2199 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2200 && ! REG_USERVAR_P (i2dest)))
2201 && (next_real_insn (i2) == i3
2202 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
2203 /* We can't overwrite I2DEST if its value is still used by
2205 && ! reg_referenced_p (i2dest, newpat))
2207 rtx newdest = i2dest;
2208 enum rtx_code split_code = GET_CODE (*split);
2209 enum machine_mode split_mode = GET_MODE (*split);
2211 /* Get NEWDEST as a register in the proper mode. We have already
2212 validated that we can do this. */
2213 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2215 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
2217 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2218 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
2221 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2222 an ASHIFT. This can occur if it was inside a PLUS and hence
2223 appeared to be a memory address. This is a kludge. */
2224 if (split_code == MULT
2225 && GET_CODE (XEXP (*split, 1)) == CONST_INT
2226 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
2228 SUBST (*split, gen_rtx_combine (ASHIFT, split_mode,
2229 XEXP (*split, 0), GEN_INT (i)));
2230 /* Update split_code because we may not have a multiply
2232 split_code = GET_CODE (*split);
2235 #ifdef INSN_SCHEDULING
2236 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2237 be written as a ZERO_EXTEND. */
2238 if (split_code == SUBREG && GET_CODE (SUBREG_REG (*split)) == MEM)
2239 SUBST (*split, gen_rtx_combine (ZERO_EXTEND, split_mode,
2243 newi2pat = gen_rtx_combine (SET, VOIDmode, newdest, *split);
2244 SUBST (*split, newdest);
2245 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2247 /* If the split point was a MULT and we didn't have one before,
2248 don't use one now. */
2249 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
2250 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2254 /* Check for a case where we loaded from memory in a narrow mode and
2255 then sign extended it, but we need both registers. In that case,
2256 we have a PARALLEL with both loads from the same memory location.
2257 We can split this into a load from memory followed by a register-register
2258 copy. This saves at least one insn, more if register allocation can
2261 We cannot do this if the destination of the second assignment is
2262 a register that we have already assumed is zero-extended. Similarly
2263 for a SUBREG of such a register. */
2265 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2266 && GET_CODE (newpat) == PARALLEL
2267 && XVECLEN (newpat, 0) == 2
2268 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2269 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2270 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2271 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2272 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2273 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2275 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2276 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2277 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2278 (GET_CODE (temp) == REG
2279 && reg_nonzero_bits[REGNO (temp)] != 0
2280 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2281 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2282 && (reg_nonzero_bits[REGNO (temp)]
2283 != GET_MODE_MASK (word_mode))))
2284 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2285 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2286 (GET_CODE (temp) == REG
2287 && reg_nonzero_bits[REGNO (temp)] != 0
2288 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2289 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2290 && (reg_nonzero_bits[REGNO (temp)]
2291 != GET_MODE_MASK (word_mode)))))
2292 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2293 SET_SRC (XVECEXP (newpat, 0, 1)))
2294 && ! find_reg_note (i3, REG_UNUSED,
2295 SET_DEST (XVECEXP (newpat, 0, 0))))
2299 newi2pat = XVECEXP (newpat, 0, 0);
2300 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2301 newpat = XVECEXP (newpat, 0, 1);
2302 SUBST (SET_SRC (newpat),
2303 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest));
2304 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2306 if (i2_code_number >= 0)
2307 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2309 if (insn_code_number >= 0)
2314 /* If we will be able to accept this, we have made a change to the
2315 destination of I3. This can invalidate a LOG_LINKS pointing
2316 to I3. No other part of combine.c makes such a transformation.
2318 The new I3 will have a destination that was previously the
2319 destination of I1 or I2 and which was used in i2 or I3. Call
2320 distribute_links to make a LOG_LINK from the next use of
2321 that destination. */
2323 PATTERN (i3) = newpat;
2324 distribute_links (gen_rtx_INSN_LIST (VOIDmode, i3, NULL_RTX));
2326 /* I3 now uses what used to be its destination and which is
2327 now I2's destination. That means we need a LOG_LINK from
2328 I3 to I2. But we used to have one, so we still will.
2330 However, some later insn might be using I2's dest and have
2331 a LOG_LINK pointing at I3. We must remove this link.
2332 The simplest way to remove the link is to point it at I1,
2333 which we know will be a NOTE. */
2335 for (insn = NEXT_INSN (i3);
2336 insn && (this_basic_block == n_basic_blocks - 1
2337 || insn != BLOCK_HEAD (this_basic_block + 1));
2338 insn = NEXT_INSN (insn))
2340 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
2342 for (link = LOG_LINKS (insn); link;
2343 link = XEXP (link, 1))
2344 if (XEXP (link, 0) == i3)
2345 XEXP (link, 0) = i1;
2353 /* Similarly, check for a case where we have a PARALLEL of two independent
2354 SETs but we started with three insns. In this case, we can do the sets
2355 as two separate insns. This case occurs when some SET allows two
2356 other insns to combine, but the destination of that SET is still live. */
2358 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2359 && GET_CODE (newpat) == PARALLEL
2360 && XVECLEN (newpat, 0) == 2
2361 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2362 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2363 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2364 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2365 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2366 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2367 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2369 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2370 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2371 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2372 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2373 XVECEXP (newpat, 0, 0))
2374 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2375 XVECEXP (newpat, 0, 1))
2376 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
2377 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
2379 /* Normally, it doesn't matter which of the two is done first,
2380 but it does if one references cc0. In that case, it has to
2383 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2385 newi2pat = XVECEXP (newpat, 0, 0);
2386 newpat = XVECEXP (newpat, 0, 1);
2391 newi2pat = XVECEXP (newpat, 0, 1);
2392 newpat = XVECEXP (newpat, 0, 0);
2395 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2397 if (i2_code_number >= 0)
2398 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2401 /* If it still isn't recognized, fail and change things back the way they
2403 if ((insn_code_number < 0
2404 /* Is the result a reasonable ASM_OPERANDS? */
2405 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2411 /* If we had to change another insn, make sure it is valid also. */
2412 if (undobuf.other_insn)
2414 rtx other_pat = PATTERN (undobuf.other_insn);
2415 rtx new_other_notes;
2418 CLEAR_HARD_REG_SET (newpat_used_regs);
2420 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2423 if (other_code_number < 0 && ! check_asm_operands (other_pat))
2429 PATTERN (undobuf.other_insn) = other_pat;
2431 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2432 are still valid. Then add any non-duplicate notes added by
2433 recog_for_combine. */
2434 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2436 next = XEXP (note, 1);
2438 if (REG_NOTE_KIND (note) == REG_UNUSED
2439 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2441 if (GET_CODE (XEXP (note, 0)) == REG)
2442 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2444 remove_note (undobuf.other_insn, note);
2448 for (note = new_other_notes; note; note = XEXP (note, 1))
2449 if (GET_CODE (XEXP (note, 0)) == REG)
2450 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2452 distribute_notes (new_other_notes, undobuf.other_insn,
2453 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
2456 /* If I2 is the setter CC0 and I3 is the user CC0 then check whether
2457 they are adjacent to each other or not. */
2459 rtx p = prev_nonnote_insn (i3);
2460 if (p && p != i2 && GET_CODE (p) == INSN && newi2pat
2461 && sets_cc0_p (newi2pat))
2469 /* We now know that we can do this combination. Merge the insns and
2470 update the status of registers and LOG_LINKS. */
2473 rtx i3notes, i2notes, i1notes = 0;
2474 rtx i3links, i2links, i1links = 0;
2477 /* Compute which registers we expect to eliminate. newi2pat may be setting
2478 either i3dest or i2dest, so we must check it. Also, i1dest may be the
2479 same as i3dest, in which case newi2pat may be setting i1dest. */
2480 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
2481 || i2dest_in_i2src || i2dest_in_i1src
2483 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
2484 || (newi2pat && reg_set_p (i1dest, newi2pat))
2487 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2489 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2490 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2492 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2494 /* Ensure that we do not have something that should not be shared but
2495 occurs multiple times in the new insns. Check this by first
2496 resetting all the `used' flags and then copying anything is shared. */
2498 reset_used_flags (i3notes);
2499 reset_used_flags (i2notes);
2500 reset_used_flags (i1notes);
2501 reset_used_flags (newpat);
2502 reset_used_flags (newi2pat);
2503 if (undobuf.other_insn)
2504 reset_used_flags (PATTERN (undobuf.other_insn));
2506 i3notes = copy_rtx_if_shared (i3notes);
2507 i2notes = copy_rtx_if_shared (i2notes);
2508 i1notes = copy_rtx_if_shared (i1notes);
2509 newpat = copy_rtx_if_shared (newpat);
2510 newi2pat = copy_rtx_if_shared (newi2pat);
2511 if (undobuf.other_insn)
2512 reset_used_flags (PATTERN (undobuf.other_insn));
2514 INSN_CODE (i3) = insn_code_number;
2515 PATTERN (i3) = newpat;
2516 if (undobuf.other_insn)
2517 INSN_CODE (undobuf.other_insn) = other_code_number;
2519 /* We had one special case above where I2 had more than one set and
2520 we replaced a destination of one of those sets with the destination
2521 of I3. In that case, we have to update LOG_LINKS of insns later
2522 in this basic block. Note that this (expensive) case is rare.
2524 Also, in this case, we must pretend that all REG_NOTEs for I2
2525 actually came from I3, so that REG_UNUSED notes from I2 will be
2526 properly handled. */
2528 if (i3_subst_into_i2 && GET_CODE (PATTERN (i2)) == PARALLEL)
2530 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2531 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != USE
2532 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
2533 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2534 && ! find_reg_note (i2, REG_UNUSED,
2535 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2536 for (temp = NEXT_INSN (i2);
2537 temp && (this_basic_block == n_basic_blocks - 1
2538 || BLOCK_HEAD (this_basic_block) != temp);
2539 temp = NEXT_INSN (temp))
2540 if (temp != i3 && INSN_P (temp))
2541 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2542 if (XEXP (link, 0) == i2)
2543 XEXP (link, 0) = i3;
2548 while (XEXP (link, 1))
2549 link = XEXP (link, 1);
2550 XEXP (link, 1) = i2notes;
2564 INSN_CODE (i2) = i2_code_number;
2565 PATTERN (i2) = newi2pat;
2569 PUT_CODE (i2, NOTE);
2570 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
2571 NOTE_SOURCE_FILE (i2) = 0;
2578 PUT_CODE (i1, NOTE);
2579 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
2580 NOTE_SOURCE_FILE (i1) = 0;
2583 /* Get death notes for everything that is now used in either I3 or
2584 I2 and used to die in a previous insn. If we built two new
2585 patterns, move from I1 to I2 then I2 to I3 so that we get the
2586 proper movement on registers that I2 modifies. */
2590 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
2591 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
2594 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
2597 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2599 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
2602 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
2605 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
2608 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2611 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2612 know these are REG_UNUSED and want them to go to the desired insn,
2613 so we always pass it as i3. We have not counted the notes in
2614 reg_n_deaths yet, so we need to do so now. */
2616 if (newi2pat && new_i2_notes)
2618 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2619 if (GET_CODE (XEXP (temp, 0)) == REG)
2620 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2622 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2627 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2628 if (GET_CODE (XEXP (temp, 0)) == REG)
2629 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2631 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
2634 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2635 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2636 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2637 in that case, it might delete I2. Similarly for I2 and I1.
2638 Show an additional death due to the REG_DEAD note we make here. If
2639 we discard it in distribute_notes, we will decrement it again. */
2643 if (GET_CODE (i3dest_killed) == REG)
2644 REG_N_DEATHS (REGNO (i3dest_killed))++;
2646 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
2647 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2649 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
2651 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2653 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2657 if (i2dest_in_i2src)
2659 if (GET_CODE (i2dest) == REG)
2660 REG_N_DEATHS (REGNO (i2dest))++;
2662 if (newi2pat && reg_set_p (i2dest, newi2pat))
2663 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2664 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2666 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2667 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2668 NULL_RTX, NULL_RTX);
2671 if (i1dest_in_i1src)
2673 if (GET_CODE (i1dest) == REG)
2674 REG_N_DEATHS (REGNO (i1dest))++;
2676 if (newi2pat && reg_set_p (i1dest, newi2pat))
2677 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2678 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2680 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2681 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2682 NULL_RTX, NULL_RTX);
2685 distribute_links (i3links);
2686 distribute_links (i2links);
2687 distribute_links (i1links);
2689 if (GET_CODE (i2dest) == REG)
2692 rtx i2_insn = 0, i2_val = 0, set;
2694 /* The insn that used to set this register doesn't exist, and
2695 this life of the register may not exist either. See if one of
2696 I3's links points to an insn that sets I2DEST. If it does,
2697 that is now the last known value for I2DEST. If we don't update
2698 this and I2 set the register to a value that depended on its old
2699 contents, we will get confused. If this insn is used, thing
2700 will be set correctly in combine_instructions. */
2702 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2703 if ((set = single_set (XEXP (link, 0))) != 0
2704 && rtx_equal_p (i2dest, SET_DEST (set)))
2705 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2707 record_value_for_reg (i2dest, i2_insn, i2_val);
2709 /* If the reg formerly set in I2 died only once and that was in I3,
2710 zero its use count so it won't make `reload' do any work. */
2712 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
2713 && ! i2dest_in_i2src)
2715 regno = REGNO (i2dest);
2716 REG_N_SETS (regno)--;
2720 if (i1 && GET_CODE (i1dest) == REG)
2723 rtx i1_insn = 0, i1_val = 0, set;
2725 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2726 if ((set = single_set (XEXP (link, 0))) != 0
2727 && rtx_equal_p (i1dest, SET_DEST (set)))
2728 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2730 record_value_for_reg (i1dest, i1_insn, i1_val);
2732 regno = REGNO (i1dest);
2733 if (! added_sets_1 && ! i1dest_in_i1src)
2734 REG_N_SETS (regno)--;
2737 /* Update reg_nonzero_bits et al for any changes that may have been made
2738 to this insn. The order of set_nonzero_bits_and_sign_copies() is
2739 important. Because newi2pat can affect nonzero_bits of newpat */
2741 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
2742 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
2744 /* Set new_direct_jump_p if a new return or simple jump instruction
2747 If I3 is now an unconditional jump, ensure that it has a
2748 BARRIER following it since it may have initially been a
2749 conditional jump. It may also be the last nonnote insn. */
2751 if (GET_CODE (newpat) == RETURN || any_uncondjump_p (i3))
2753 *new_direct_jump_p = 1;
2755 if ((temp = next_nonnote_insn (i3)) == NULL_RTX
2756 || GET_CODE (temp) != BARRIER)
2757 emit_barrier_after (i3);
2761 combine_successes++;
2764 /* Clear this here, so that subsequent get_last_value calls are not
2766 subst_prev_insn = NULL_RTX;
2768 if (added_links_insn
2769 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
2770 && INSN_CUID (added_links_insn) < INSN_CUID (i3))
2771 return added_links_insn;
2773 return newi2pat ? i2 : i3;
2776 /* Undo all the modifications recorded in undobuf. */
2781 struct undo *undo, *next;
2783 for (undo = undobuf.undos; undo; undo = next)
2787 *undo->where.i = undo->old_contents.i;
2789 *undo->where.r = undo->old_contents.r;
2791 undo->next = undobuf.frees;
2792 undobuf.frees = undo;
2795 undobuf.undos = undobuf.previous_undos = 0;
2797 /* Clear this here, so that subsequent get_last_value calls are not
2799 subst_prev_insn = NULL_RTX;
2802 /* We've committed to accepting the changes we made. Move all
2803 of the undos to the free list. */
2808 struct undo *undo, *next;
2810 for (undo = undobuf.undos; undo; undo = next)
2813 undo->next = undobuf.frees;
2814 undobuf.frees = undo;
2816 undobuf.undos = undobuf.previous_undos = 0;
2820 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2821 where we have an arithmetic expression and return that point. LOC will
2824 try_combine will call this function to see if an insn can be split into
2828 find_split_point (loc, insn)
2833 enum rtx_code code = GET_CODE (x);
2835 unsigned HOST_WIDE_INT len = 0;
2836 HOST_WIDE_INT pos = 0;
2838 rtx inner = NULL_RTX;
2840 /* First special-case some codes. */
2844 #ifdef INSN_SCHEDULING
2845 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2847 if (GET_CODE (SUBREG_REG (x)) == MEM)
2850 return find_split_point (&SUBREG_REG (x), insn);
2854 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2855 using LO_SUM and HIGH. */
2856 if (GET_CODE (XEXP (x, 0)) == CONST
2857 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
2860 gen_rtx_combine (LO_SUM, Pmode,
2861 gen_rtx_combine (HIGH, Pmode, XEXP (x, 0)),
2863 return &XEXP (XEXP (x, 0), 0);
2867 /* If we have a PLUS whose second operand is a constant and the
2868 address is not valid, perhaps will can split it up using
2869 the machine-specific way to split large constants. We use
2870 the first pseudo-reg (one of the virtual regs) as a placeholder;
2871 it will not remain in the result. */
2872 if (GET_CODE (XEXP (x, 0)) == PLUS
2873 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2874 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
2876 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
2877 rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
2880 /* This should have produced two insns, each of which sets our
2881 placeholder. If the source of the second is a valid address,
2882 we can make put both sources together and make a split point
2885 if (seq && XVECLEN (seq, 0) == 2
2886 && GET_CODE (XVECEXP (seq, 0, 0)) == INSN
2887 && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) == SET
2888 && SET_DEST (PATTERN (XVECEXP (seq, 0, 0))) == reg
2889 && ! reg_mentioned_p (reg,
2890 SET_SRC (PATTERN (XVECEXP (seq, 0, 0))))
2891 && GET_CODE (XVECEXP (seq, 0, 1)) == INSN
2892 && GET_CODE (PATTERN (XVECEXP (seq, 0, 1))) == SET
2893 && SET_DEST (PATTERN (XVECEXP (seq, 0, 1))) == reg
2894 && memory_address_p (GET_MODE (x),
2895 SET_SRC (PATTERN (XVECEXP (seq, 0, 1)))))
2897 rtx src1 = SET_SRC (PATTERN (XVECEXP (seq, 0, 0)));
2898 rtx src2 = SET_SRC (PATTERN (XVECEXP (seq, 0, 1)));
2900 /* Replace the placeholder in SRC2 with SRC1. If we can
2901 find where in SRC2 it was placed, that can become our
2902 split point and we can replace this address with SRC2.
2903 Just try two obvious places. */
2905 src2 = replace_rtx (src2, reg, src1);
2907 if (XEXP (src2, 0) == src1)
2908 split = &XEXP (src2, 0);
2909 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
2910 && XEXP (XEXP (src2, 0), 0) == src1)
2911 split = &XEXP (XEXP (src2, 0), 0);
2915 SUBST (XEXP (x, 0), src2);
2920 /* If that didn't work, perhaps the first operand is complex and
2921 needs to be computed separately, so make a split point there.
2922 This will occur on machines that just support REG + CONST
2923 and have a constant moved through some previous computation. */
2925 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o'
2926 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
2927 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0))))
2929 return &XEXP (XEXP (x, 0), 0);
2935 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2936 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2937 we need to put the operand into a register. So split at that
2940 if (SET_DEST (x) == cc0_rtx
2941 && GET_CODE (SET_SRC (x)) != COMPARE
2942 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
2943 && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
2944 && ! (GET_CODE (SET_SRC (x)) == SUBREG
2945 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
2946 return &SET_SRC (x);
2949 /* See if we can split SET_SRC as it stands. */
2950 split = find_split_point (&SET_SRC (x), insn);
2951 if (split && split != &SET_SRC (x))
2954 /* See if we can split SET_DEST as it stands. */
2955 split = find_split_point (&SET_DEST (x), insn);
2956 if (split && split != &SET_DEST (x))
2959 /* See if this is a bitfield assignment with everything constant. If
2960 so, this is an IOR of an AND, so split it into that. */
2961 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
2962 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
2963 <= HOST_BITS_PER_WIDE_INT)
2964 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
2965 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
2966 && GET_CODE (SET_SRC (x)) == CONST_INT
2967 && ((INTVAL (XEXP (SET_DEST (x), 1))
2968 + INTVAL (XEXP (SET_DEST (x), 2)))
2969 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
2970 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
2972 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
2973 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
2974 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
2975 rtx dest = XEXP (SET_DEST (x), 0);
2976 enum machine_mode mode = GET_MODE (dest);
2977 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
2979 if (BITS_BIG_ENDIAN)
2980 pos = GET_MODE_BITSIZE (mode) - len - pos;
2984 gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
2987 gen_binary (IOR, mode,
2988 gen_binary (AND, mode, dest,
2989 GEN_INT (~(mask << pos)
2990 & GET_MODE_MASK (mode))),
2991 GEN_INT (src << pos)));
2993 SUBST (SET_DEST (x), dest);
2995 split = find_split_point (&SET_SRC (x), insn);
2996 if (split && split != &SET_SRC (x))
3000 /* Otherwise, see if this is an operation that we can split into two.
3001 If so, try to split that. */
3002 code = GET_CODE (SET_SRC (x));
3007 /* If we are AND'ing with a large constant that is only a single
3008 bit and the result is only being used in a context where we
3009 need to know if it is zero or non-zero, replace it with a bit
3010 extraction. This will avoid the large constant, which might
3011 have taken more than one insn to make. If the constant were
3012 not a valid argument to the AND but took only one insn to make,
3013 this is no worse, but if it took more than one insn, it will
3016 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3017 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
3018 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
3019 && GET_CODE (SET_DEST (x)) == REG
3020 && (split = find_single_use (SET_DEST (x), insn, NULL_PTR)) != 0
3021 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
3022 && XEXP (*split, 0) == SET_DEST (x)
3023 && XEXP (*split, 1) == const0_rtx)
3025 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
3026 XEXP (SET_SRC (x), 0),
3027 pos, NULL_RTX, 1, 1, 0, 0);
3028 if (extraction != 0)
3030 SUBST (SET_SRC (x), extraction);
3031 return find_split_point (loc, insn);
3037 /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3038 is known to be on, this can be converted into a NEG of a shift. */
3039 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
3040 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
3041 && 1 <= (pos = exact_log2
3042 (nonzero_bits (XEXP (SET_SRC (x), 0),
3043 GET_MODE (XEXP (SET_SRC (x), 0))))))
3045 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
3048 gen_rtx_combine (NEG, mode,
3049 gen_rtx_combine (LSHIFTRT, mode,
3050 XEXP (SET_SRC (x), 0),
3053 split = find_split_point (&SET_SRC (x), insn);
3054 if (split && split != &SET_SRC (x))
3060 inner = XEXP (SET_SRC (x), 0);
3062 /* We can't optimize if either mode is a partial integer
3063 mode as we don't know how many bits are significant
3065 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
3066 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
3070 len = GET_MODE_BITSIZE (GET_MODE (inner));
3076 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3077 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
3079 inner = XEXP (SET_SRC (x), 0);
3080 len = INTVAL (XEXP (SET_SRC (x), 1));
3081 pos = INTVAL (XEXP (SET_SRC (x), 2));
3083 if (BITS_BIG_ENDIAN)
3084 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
3085 unsignedp = (code == ZERO_EXTRACT);
3093 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
3095 enum machine_mode mode = GET_MODE (SET_SRC (x));
3097 /* For unsigned, we have a choice of a shift followed by an
3098 AND or two shifts. Use two shifts for field sizes where the
3099 constant might be too large. We assume here that we can
3100 always at least get 8-bit constants in an AND insn, which is
3101 true for every current RISC. */
3103 if (unsignedp && len <= 8)
3108 gen_rtx_combine (LSHIFTRT, mode,
3109 gen_lowpart_for_combine (mode, inner),
3111 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
3113 split = find_split_point (&SET_SRC (x), insn);
3114 if (split && split != &SET_SRC (x))
3121 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
3122 gen_rtx_combine (ASHIFT, mode,
3123 gen_lowpart_for_combine (mode, inner),
3124 GEN_INT (GET_MODE_BITSIZE (mode)
3126 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
3128 split = find_split_point (&SET_SRC (x), insn);
3129 if (split && split != &SET_SRC (x))
3134 /* See if this is a simple operation with a constant as the second
3135 operand. It might be that this constant is out of range and hence
3136 could be used as a split point. */
3137 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3138 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3139 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
3140 && CONSTANT_P (XEXP (SET_SRC (x), 1))
3141 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
3142 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
3143 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
3145 return &XEXP (SET_SRC (x), 1);
3147 /* Finally, see if this is a simple operation with its first operand
3148 not in a register. The operation might require this operand in a
3149 register, so return it as a split point. We can always do this
3150 because if the first operand were another operation, we would have
3151 already found it as a split point. */
3152 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3153 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3154 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
3155 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
3156 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
3157 return &XEXP (SET_SRC (x), 0);
3163 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3164 it is better to write this as (not (ior A B)) so we can split it.
3165 Similarly for IOR. */
3166 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
3169 gen_rtx_combine (NOT, GET_MODE (x),
3170 gen_rtx_combine (code == IOR ? AND : IOR,
3172 XEXP (XEXP (x, 0), 0),
3173 XEXP (XEXP (x, 1), 0))));
3174 return find_split_point (loc, insn);
3177 /* Many RISC machines have a large set of logical insns. If the
3178 second operand is a NOT, put it first so we will try to split the
3179 other operand first. */
3180 if (GET_CODE (XEXP (x, 1)) == NOT)
3182 rtx tem = XEXP (x, 0);
3183 SUBST (XEXP (x, 0), XEXP (x, 1));
3184 SUBST (XEXP (x, 1), tem);
3192 /* Otherwise, select our actions depending on our rtx class. */
3193 switch (GET_RTX_CLASS (code))
3195 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3197 split = find_split_point (&XEXP (x, 2), insn);
3200 /* ... fall through ... */
3204 split = find_split_point (&XEXP (x, 1), insn);
3207 /* ... fall through ... */
3209 /* Some machines have (and (shift ...) ...) insns. If X is not
3210 an AND, but XEXP (X, 0) is, use it as our split point. */
3211 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
3212 return &XEXP (x, 0);
3214 split = find_split_point (&XEXP (x, 0), insn);
3220 /* Otherwise, we don't have a split point. */
3224 /* Throughout X, replace FROM with TO, and return the result.
3225 The result is TO if X is FROM;
3226 otherwise the result is X, but its contents may have been modified.
3227 If they were modified, a record was made in undobuf so that
3228 undo_all will (among other things) return X to its original state.
3230 If the number of changes necessary is too much to record to undo,
3231 the excess changes are not made, so the result is invalid.
3232 The changes already made can still be undone.
3233 undobuf.num_undo is incremented for such changes, so by testing that
3234 the caller can tell whether the result is valid.
3236 `n_occurrences' is incremented each time FROM is replaced.
3238 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
3240 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
3241 by copying if `n_occurrences' is non-zero. */
3244 subst (x, from, to, in_dest, unique_copy)
3245 register rtx x, from, to;
3249 register enum rtx_code code = GET_CODE (x);
3250 enum machine_mode op0_mode = VOIDmode;
3251 register const char *fmt;
3252 register int len, i;
3255 /* Two expressions are equal if they are identical copies of a shared
3256 RTX or if they are both registers with the same register number
3259 #define COMBINE_RTX_EQUAL_P(X,Y) \
3261 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3262 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3264 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3267 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3270 /* If X and FROM are the same register but different modes, they will
3271 not have been seen as equal above. However, flow.c will make a
3272 LOG_LINKS entry for that case. If we do nothing, we will try to
3273 rerecognize our original insn and, when it succeeds, we will
3274 delete the feeding insn, which is incorrect.
3276 So force this insn not to match in this (rare) case. */
3277 if (! in_dest && code == REG && GET_CODE (from) == REG
3278 && REGNO (x) == REGNO (from))
3279 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
3281 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3282 of which may contain things that can be combined. */
3283 if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
3286 /* It is possible to have a subexpression appear twice in the insn.
3287 Suppose that FROM is a register that appears within TO.
3288 Then, after that subexpression has been scanned once by `subst',
3289 the second time it is scanned, TO may be found. If we were
3290 to scan TO here, we would find FROM within it and create a
3291 self-referent rtl structure which is completely wrong. */
3292 if (COMBINE_RTX_EQUAL_P (x, to))
3295 /* Parallel asm_operands need special attention because all of the
3296 inputs are shared across the arms. Furthermore, unsharing the
3297 rtl results in recognition failures. Failure to handle this case
3298 specially can result in circular rtl.
3300 Solve this by doing a normal pass across the first entry of the
3301 parallel, and only processing the SET_DESTs of the subsequent
3304 if (code == PARALLEL
3305 && GET_CODE (XVECEXP (x, 0, 0)) == SET
3306 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
3308 new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3310 /* If this substitution failed, this whole thing fails. */
3311 if (GET_CODE (new) == CLOBBER
3312 && XEXP (new, 0) == const0_rtx)
3315 SUBST (XVECEXP (x, 0, 0), new);
3317 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
3319 rtx dest = SET_DEST (XVECEXP (x, 0, i));
3321 if (GET_CODE (dest) != REG
3322 && GET_CODE (dest) != CC0
3323 && GET_CODE (dest) != PC)
3325 new = subst (dest, from, to, 0, unique_copy);
3327 /* If this substitution failed, this whole thing fails. */
3328 if (GET_CODE (new) == CLOBBER
3329 && XEXP (new, 0) == const0_rtx)
3332 SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
3338 len = GET_RTX_LENGTH (code);
3339 fmt = GET_RTX_FORMAT (code);
3341 /* We don't need to process a SET_DEST that is a register, CC0,
3342 or PC, so set up to skip this common case. All other cases
3343 where we want to suppress replacing something inside a
3344 SET_SRC are handled via the IN_DEST operand. */
3346 && (GET_CODE (SET_DEST (x)) == REG
3347 || GET_CODE (SET_DEST (x)) == CC0
3348 || GET_CODE (SET_DEST (x)) == PC))
3351 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3354 op0_mode = GET_MODE (XEXP (x, 0));
3356 for (i = 0; i < len; i++)
3361 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3363 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3365 new = (unique_copy && n_occurrences
3366 ? copy_rtx (to) : to);
3371 new = subst (XVECEXP (x, i, j), from, to, 0,
3374 /* If this substitution failed, this whole thing
3376 if (GET_CODE (new) == CLOBBER
3377 && XEXP (new, 0) == const0_rtx)
3381 SUBST (XVECEXP (x, i, j), new);
3384 else if (fmt[i] == 'e')
3386 if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
3388 /* In general, don't install a subreg involving two
3389 modes not tieable. It can worsen register
3390 allocation, and can even make invalid reload
3391 insns, since the reg inside may need to be copied
3392 from in the outside mode, and that may be invalid
3393 if it is an fp reg copied in integer mode.
3395 We allow two exceptions to this: It is valid if
3396 it is inside another SUBREG and the mode of that
3397 SUBREG and the mode of the inside of TO is
3398 tieable and it is valid if X is a SET that copies
3401 if (GET_CODE (to) == SUBREG
3402 && ! MODES_TIEABLE_P (GET_MODE (to),
3403 GET_MODE (SUBREG_REG (to)))
3404 && ! (code == SUBREG
3405 && MODES_TIEABLE_P (GET_MODE (x),
3406 GET_MODE (SUBREG_REG (to))))
3408 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
3411 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3413 #ifdef CLASS_CANNOT_CHANGE_MODE
3415 && GET_CODE (to) == REG
3416 && REGNO (to) < FIRST_PSEUDO_REGISTER
3417 && (TEST_HARD_REG_BIT
3418 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE],
3420 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (to),
3422 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3425 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3429 /* If we are in a SET_DEST, suppress most cases unless we
3430 have gone inside a MEM, in which case we want to
3431 simplify the address. We assume here that things that
3432 are actually part of the destination have their inner
3433 parts in the first expression. This is true for SUBREG,
3434 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3435 things aside from REG and MEM that should appear in a
3437 new = subst (XEXP (x, i), from, to,
3439 && (code == SUBREG || code == STRICT_LOW_PART
3440 || code == ZERO_EXTRACT))
3442 && i == 0), unique_copy);
3444 /* If we found that we will have to reject this combination,
3445 indicate that by returning the CLOBBER ourselves, rather than
3446 an expression containing it. This will speed things up as
3447 well as prevent accidents where two CLOBBERs are considered
3448 to be equal, thus producing an incorrect simplification. */
3450 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3453 SUBST (XEXP (x, i), new);
3458 /* Try to simplify X. If the simplification changed the code, it is likely
3459 that further simplification will help, so loop, but limit the number
3460 of repetitions that will be performed. */
3462 for (i = 0; i < 4; i++)
3464 /* If X is sufficiently simple, don't bother trying to do anything
3466 if (code != CONST_INT && code != REG && code != CLOBBER)
3467 x = combine_simplify_rtx (x, op0_mode, i == 3, in_dest);
3469 if (GET_CODE (x) == code)
3472 code = GET_CODE (x);
3474 /* We no longer know the original mode of operand 0 since we
3475 have changed the form of X) */
3476 op0_mode = VOIDmode;
3482 /* Simplify X, a piece of RTL. We just operate on the expression at the
3483 outer level; call `subst' to simplify recursively. Return the new
3486 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3487 will be the iteration even if an expression with a code different from
3488 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3491 combine_simplify_rtx (x, op0_mode, last, in_dest)
3493 enum machine_mode op0_mode;
3497 enum rtx_code code = GET_CODE (x);
3498 enum machine_mode mode = GET_MODE (x);
3502 /* If this is a commutative operation, put a constant last and a complex
3503 expression first. We don't need to do this for comparisons here. */
3504 if (GET_RTX_CLASS (code) == 'c'
3505 && ((CONSTANT_P (XEXP (x, 0)) && GET_CODE (XEXP (x, 1)) != CONST_INT)
3506 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == 'o'
3507 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')
3508 || (GET_CODE (XEXP (x, 0)) == SUBREG
3509 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == 'o'
3510 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')))
3513 SUBST (XEXP (x, 0), XEXP (x, 1));
3514 SUBST (XEXP (x, 1), temp);
3517 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3518 sign extension of a PLUS with a constant, reverse the order of the sign
3519 extension and the addition. Note that this not the same as the original
3520 code, but overflow is undefined for signed values. Also note that the
3521 PLUS will have been partially moved "inside" the sign-extension, so that
3522 the first operand of X will really look like:
3523 (ashiftrt (plus (ashift A C4) C5) C4).
3525 (plus (ashiftrt (ashift A C4) C2) C4)
3526 and replace the first operand of X with that expression. Later parts
3527 of this function may simplify the expression further.
3529 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3530 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3531 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3533 We do this to simplify address expressions. */
3535 if ((code == PLUS || code == MINUS || code == MULT)
3536 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3537 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
3538 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
3539 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
3540 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3541 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
3542 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3543 && (temp = simplify_binary_operation (ASHIFTRT, mode,
3544 XEXP (XEXP (XEXP (x, 0), 0), 1),
3545 XEXP (XEXP (x, 0), 1))) != 0)
3548 = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3549 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
3550 INTVAL (XEXP (XEXP (x, 0), 1)));
3552 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
3553 INTVAL (XEXP (XEXP (x, 0), 1)));
3555 SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
3558 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3559 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3560 things. Check for cases where both arms are testing the same
3563 Don't do anything if all operands are very simple. */
3565 if (((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c'
3566 || GET_RTX_CLASS (code) == '<')
3567 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3568 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3569 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3571 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o'
3572 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3573 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 1))))
3575 || (GET_RTX_CLASS (code) == '1'
3576 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3577 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3578 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3581 rtx cond, true, false;
3583 cond = if_then_else_cond (x, &true, &false);
3585 /* If everything is a comparison, what we have is highly unlikely
3586 to be simpler, so don't use it. */
3587 && ! (GET_RTX_CLASS (code) == '<'
3588 && (GET_RTX_CLASS (GET_CODE (true)) == '<'
3589 || GET_RTX_CLASS (GET_CODE (false)) == '<')))
3591 rtx cop1 = const0_rtx;
3592 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3594 if (cond_code == NE && GET_RTX_CLASS (GET_CODE (cond)) == '<')
3597 /* Simplify the alternative arms; this may collapse the true and
3598 false arms to store-flag values. */
3599 true = subst (true, pc_rtx, pc_rtx, 0, 0);
3600 false = subst (false, pc_rtx, pc_rtx, 0, 0);
3602 /* If true and false are not general_operands, an if_then_else
3603 is unlikely to be simpler. */
3604 if (general_operand (true, VOIDmode)
3605 && general_operand (false, VOIDmode))
3607 /* Restarting if we generate a store-flag expression will cause
3608 us to loop. Just drop through in this case. */
3610 /* If the result values are STORE_FLAG_VALUE and zero, we can
3611 just make the comparison operation. */
3612 if (true == const_true_rtx && false == const0_rtx)
3613 x = gen_binary (cond_code, mode, cond, cop1);
3614 else if (true == const0_rtx && false == const_true_rtx)
3615 x = gen_binary (reverse_condition (cond_code),
3618 /* Likewise, we can make the negate of a comparison operation
3619 if the result values are - STORE_FLAG_VALUE and zero. */
3620 else if (GET_CODE (true) == CONST_INT
3621 && INTVAL (true) == - STORE_FLAG_VALUE
3622 && false == const0_rtx)
3623 x = gen_unary (NEG, mode, mode,
3624 gen_binary (cond_code, mode, cond, cop1));
3625 else if (GET_CODE (false) == CONST_INT
3626 && INTVAL (false) == - STORE_FLAG_VALUE
3627 && true == const0_rtx)
3628 x = gen_unary (NEG, mode, mode,
3629 gen_binary (reverse_condition (cond_code),
3632 return gen_rtx_IF_THEN_ELSE (mode,
3633 gen_binary (cond_code, VOIDmode,
3637 code = GET_CODE (x);
3638 op0_mode = VOIDmode;
3643 /* Try to fold this expression in case we have constants that weren't
3646 switch (GET_RTX_CLASS (code))
3649 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
3653 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
3654 if (cmp_mode == VOIDmode)
3655 cmp_mode = GET_MODE (XEXP (x, 1));
3656 temp = simplify_relational_operation (code, cmp_mode,
3657 XEXP (x, 0), XEXP (x, 1));
3659 #ifdef FLOAT_STORE_FLAG_VALUE
3660 if (temp != 0 && GET_MODE_CLASS (mode) == MODE_FLOAT)
3662 if (temp == const0_rtx)
3663 temp = CONST0_RTX (mode);
3665 temp = immed_real_const_1 (FLOAT_STORE_FLAG_VALUE (mode), mode);
3671 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3675 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
3676 XEXP (x, 1), XEXP (x, 2));
3681 x = temp, code = GET_CODE (temp);
3683 /* First see if we can apply the inverse distributive law. */
3684 if (code == PLUS || code == MINUS
3685 || code == AND || code == IOR || code == XOR)
3687 x = apply_distributive_law (x);
3688 code = GET_CODE (x);
3691 /* If CODE is an associative operation not otherwise handled, see if we
3692 can associate some operands. This can win if they are constants or
3693 if they are logically related (i.e. (a & b) & a. */
3694 if ((code == PLUS || code == MINUS
3695 || code == MULT || code == AND || code == IOR || code == XOR
3696 || code == DIV || code == UDIV
3697 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
3698 && INTEGRAL_MODE_P (mode))
3700 if (GET_CODE (XEXP (x, 0)) == code)
3702 rtx other = XEXP (XEXP (x, 0), 0);
3703 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
3704 rtx inner_op1 = XEXP (x, 1);
3707 /* Make sure we pass the constant operand if any as the second
3708 one if this is a commutative operation. */
3709 if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
3711 rtx tem = inner_op0;
3712 inner_op0 = inner_op1;
3715 inner = simplify_binary_operation (code == MINUS ? PLUS
3716 : code == DIV ? MULT
3717 : code == UDIV ? MULT
3719 mode, inner_op0, inner_op1);
3721 /* For commutative operations, try the other pair if that one
3723 if (inner == 0 && GET_RTX_CLASS (code) == 'c')
3725 other = XEXP (XEXP (x, 0), 1);
3726 inner = simplify_binary_operation (code, mode,
3727 XEXP (XEXP (x, 0), 0),
3732 return gen_binary (code, mode, other, inner);
3736 /* A little bit of algebraic simplification here. */
3740 /* Ensure that our address has any ASHIFTs converted to MULT in case
3741 address-recognizing predicates are called later. */
3742 temp = make_compound_operation (XEXP (x, 0), MEM);
3743 SUBST (XEXP (x, 0), temp);
3747 /* (subreg:A (mem:B X) N) becomes a modified MEM unless the SUBREG
3748 is paradoxical. If we can't do that safely, then it becomes
3749 something nonsensical so that this combination won't take place. */
3751 if (GET_CODE (SUBREG_REG (x)) == MEM
3752 && (GET_MODE_SIZE (mode)
3753 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
3755 rtx inner = SUBREG_REG (x);
3756 int endian_offset = 0;
3757 /* Don't change the mode of the MEM
3758 if that would change the meaning of the address. */
3759 if (MEM_VOLATILE_P (SUBREG_REG (x))
3760 || mode_dependent_address_p (XEXP (inner, 0)))
3761 return gen_rtx_CLOBBER (mode, const0_rtx);
3763 if (BYTES_BIG_ENDIAN)
3765 if (GET_MODE_SIZE (mode) < UNITS_PER_WORD)
3766 endian_offset += UNITS_PER_WORD - GET_MODE_SIZE (mode);
3767 if (GET_MODE_SIZE (GET_MODE (inner)) < UNITS_PER_WORD)
3768 endian_offset -= (UNITS_PER_WORD
3769 - GET_MODE_SIZE (GET_MODE (inner)));
3771 /* Note if the plus_constant doesn't make a valid address
3772 then this combination won't be accepted. */
3773 x = gen_rtx_MEM (mode,
3774 plus_constant (XEXP (inner, 0),
3775 (SUBREG_WORD (x) * UNITS_PER_WORD
3777 MEM_COPY_ATTRIBUTES (x, inner);
3781 /* If we are in a SET_DEST, these other cases can't apply. */
3785 /* Changing mode twice with SUBREG => just change it once,
3786 or not at all if changing back to starting mode. */
3787 if (GET_CODE (SUBREG_REG (x)) == SUBREG)
3789 if (mode == GET_MODE (SUBREG_REG (SUBREG_REG (x)))
3790 && SUBREG_WORD (x) == 0 && SUBREG_WORD (SUBREG_REG (x)) == 0)
3791 return SUBREG_REG (SUBREG_REG (x));
3793 SUBST_INT (SUBREG_WORD (x),
3794 SUBREG_WORD (x) + SUBREG_WORD (SUBREG_REG (x)));
3795 SUBST (SUBREG_REG (x), SUBREG_REG (SUBREG_REG (x)));
3798 /* SUBREG of a hard register => just change the register number
3799 and/or mode. If the hard register is not valid in that mode,
3800 suppress this combination. If the hard register is the stack,
3801 frame, or argument pointer, leave this as a SUBREG. */
3803 if (GET_CODE (SUBREG_REG (x)) == REG
3804 && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER
3805 && REGNO (SUBREG_REG (x)) != FRAME_POINTER_REGNUM
3806 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3807 && REGNO (SUBREG_REG (x)) != HARD_FRAME_POINTER_REGNUM
3809 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3810 && REGNO (SUBREG_REG (x)) != ARG_POINTER_REGNUM
3812 && REGNO (SUBREG_REG (x)) != STACK_POINTER_REGNUM)
3814 if (HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (x)) + SUBREG_WORD (x),
3816 return gen_rtx_REG (mode,
3817 REGNO (SUBREG_REG (x)) + SUBREG_WORD (x));
3819 return gen_rtx_CLOBBER (mode, const0_rtx);
3822 /* For a constant, try to pick up the part we want. Handle a full
3823 word and low-order part. Only do this if we are narrowing
3824 the constant; if it is being widened, we have no idea what
3825 the extra bits will have been set to. */
3827 if (CONSTANT_P (SUBREG_REG (x)) && op0_mode != VOIDmode
3828 && GET_MODE_SIZE (mode) == UNITS_PER_WORD
3829 && GET_MODE_SIZE (op0_mode) > UNITS_PER_WORD
3830 && GET_MODE_CLASS (mode) == MODE_INT)
3832 temp = operand_subword (SUBREG_REG (x), SUBREG_WORD (x),
3838 /* If we want a subreg of a constant, at offset 0,
3839 take the low bits. On a little-endian machine, that's
3840 always valid. On a big-endian machine, it's valid
3841 only if the constant's mode fits in one word. Note that we
3842 cannot use subreg_lowpart_p since SUBREG_REG may be VOIDmode. */
3843 if (CONSTANT_P (SUBREG_REG (x))
3844 && ((GET_MODE_SIZE (op0_mode) <= UNITS_PER_WORD
3845 || ! WORDS_BIG_ENDIAN)
3846 ? SUBREG_WORD (x) == 0
3848 == ((GET_MODE_SIZE (op0_mode)
3849 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
3851 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (op0_mode)
3852 && (! WORDS_BIG_ENDIAN
3853 || GET_MODE_BITSIZE (op0_mode) <= BITS_PER_WORD))
3854 return gen_lowpart_for_combine (mode, SUBREG_REG (x));
3856 /* A paradoxical SUBREG of a VOIDmode constant is the same constant,
3857 since we are saying that the high bits don't matter. */
3858 if (CONSTANT_P (SUBREG_REG (x)) && GET_MODE (SUBREG_REG (x)) == VOIDmode
3859 && GET_MODE_SIZE (mode) > GET_MODE_SIZE (op0_mode))
3861 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))) > UNITS_PER_WORD
3862 && (WORDS_BIG_ENDIAN || SUBREG_WORD (x) != 0))
3863 return operand_subword (SUBREG_REG (x), SUBREG_WORD (x), 0, mode);
3864 return SUBREG_REG (x);
3867 /* Note that we cannot do any narrowing for non-constants since
3868 we might have been counting on using the fact that some bits were
3869 zero. We now do this in the SET. */
3874 /* (not (plus X -1)) can become (neg X). */
3875 if (GET_CODE (XEXP (x, 0)) == PLUS
3876 && XEXP (XEXP (x, 0), 1) == constm1_rtx)
3877 return gen_rtx_combine (NEG, mode, XEXP (XEXP (x, 0), 0));
3879 /* Similarly, (not (neg X)) is (plus X -1). */
3880 if (GET_CODE (XEXP (x, 0)) == NEG)
3881 return gen_rtx_combine (PLUS, mode, XEXP (XEXP (x, 0), 0),
3884 /* (not (xor X C)) for C constant is (xor X D) with D = ~C. */
3885 if (GET_CODE (XEXP (x, 0)) == XOR
3886 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3887 && (temp = simplify_unary_operation (NOT, mode,
3888 XEXP (XEXP (x, 0), 1),
3890 return gen_binary (XOR, mode, XEXP (XEXP (x, 0), 0), temp);
3892 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3893 other than 1, but that is not valid. We could do a similar
3894 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3895 but this doesn't seem common enough to bother with. */
3896 if (GET_CODE (XEXP (x, 0)) == ASHIFT
3897 && XEXP (XEXP (x, 0), 0) == const1_rtx)
3898 return gen_rtx_ROTATE (mode, gen_unary (NOT, mode, mode, const1_rtx),
3899 XEXP (XEXP (x, 0), 1));
3901 if (GET_CODE (XEXP (x, 0)) == SUBREG
3902 && subreg_lowpart_p (XEXP (x, 0))
3903 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3904 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
3905 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
3906 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3908 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3910 x = gen_rtx_ROTATE (inner_mode,
3911 gen_unary (NOT, inner_mode, inner_mode,
3913 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
3914 return gen_lowpart_for_combine (mode, x);
3917 /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
3918 reversing the comparison code if valid. */
3919 if (STORE_FLAG_VALUE == -1
3920 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3921 && reversible_comparison_p (XEXP (x, 0)))
3922 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
3923 mode, XEXP (XEXP (x, 0), 0),
3924 XEXP (XEXP (x, 0), 1));
3926 /* (ashiftrt foo C) where C is the number of bits in FOO minus 1
3927 is (lt foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
3928 perform the above simplification. */
3930 if (STORE_FLAG_VALUE == -1
3931 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3932 && XEXP (x, 1) == const1_rtx
3933 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3934 && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
3935 return gen_rtx_combine (GE, mode, XEXP (XEXP (x, 0), 0), const0_rtx);
3937 /* Apply De Morgan's laws to reduce number of patterns for machines
3938 with negating logical insns (and-not, nand, etc.). If result has
3939 only one NOT, put it first, since that is how the patterns are
3942 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
3944 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
3945 enum machine_mode op_mode;
3947 op_mode = GET_MODE (in1);
3948 in1 = gen_unary (NOT, op_mode, op_mode, in1);
3950 op_mode = GET_MODE (in2);
3951 if (op_mode == VOIDmode)
3953 in2 = gen_unary (NOT, op_mode, op_mode, in2);
3955 if (GET_CODE (in2) == NOT && GET_CODE (in1) != NOT)
3958 in2 = in1; in1 = tem;
3961 return gen_rtx_combine (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
3967 /* (neg (plus X 1)) can become (not X). */
3968 if (GET_CODE (XEXP (x, 0)) == PLUS
3969 && XEXP (XEXP (x, 0), 1) == const1_rtx)
3970 return gen_rtx_combine (NOT, mode, XEXP (XEXP (x, 0), 0));
3972 /* Similarly, (neg (not X)) is (plus X 1). */
3973 if (GET_CODE (XEXP (x, 0)) == NOT)
3974 return plus_constant (XEXP (XEXP (x, 0), 0), 1);
3976 /* (neg (minus X Y)) can become (minus Y X). */
3977 if (GET_CODE (XEXP (x, 0)) == MINUS
3978 && (! FLOAT_MODE_P (mode)
3979 /* x-y != -(y-x) with IEEE floating point. */
3980 || TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
3982 return gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
3983 XEXP (XEXP (x, 0), 0));
3985 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
3986 if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx
3987 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
3988 return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3990 /* NEG commutes with ASHIFT since it is multiplication. Only do this
3991 if we can then eliminate the NEG (e.g.,
3992 if the operand is a constant). */
3994 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
3996 temp = simplify_unary_operation (NEG, mode,
3997 XEXP (XEXP (x, 0), 0), mode);
4000 SUBST (XEXP (XEXP (x, 0), 0), temp);
4005 temp = expand_compound_operation (XEXP (x, 0));
4007 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4008 replaced by (lshiftrt X C). This will convert
4009 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
4011 if (GET_CODE (temp) == ASHIFTRT
4012 && GET_CODE (XEXP (temp, 1)) == CONST_INT
4013 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
4014 return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
4015 INTVAL (XEXP (temp, 1)));
4017 /* If X has only a single bit that might be nonzero, say, bit I, convert
4018 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4019 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4020 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4021 or a SUBREG of one since we'd be making the expression more
4022 complex if it was just a register. */
4024 if (GET_CODE (temp) != REG
4025 && ! (GET_CODE (temp) == SUBREG
4026 && GET_CODE (SUBREG_REG (temp)) == REG)
4027 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
4029 rtx temp1 = simplify_shift_const
4030 (NULL_RTX, ASHIFTRT, mode,
4031 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
4032 GET_MODE_BITSIZE (mode) - 1 - i),
4033 GET_MODE_BITSIZE (mode) - 1 - i);
4035 /* If all we did was surround TEMP with the two shifts, we
4036 haven't improved anything, so don't use it. Otherwise,
4037 we are better off with TEMP1. */
4038 if (GET_CODE (temp1) != ASHIFTRT
4039 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
4040 || XEXP (XEXP (temp1, 0), 0) != temp)
4046 /* We can't handle truncation to a partial integer mode here
4047 because we don't know the real bitsize of the partial
4049 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
4052 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4053 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4054 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4056 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
4057 GET_MODE_MASK (mode), NULL_RTX, 0));
4059 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
4060 if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4061 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4062 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4063 return XEXP (XEXP (x, 0), 0);
4065 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
4066 (OP:SI foo:SI) if OP is NEG or ABS. */
4067 if ((GET_CODE (XEXP (x, 0)) == ABS
4068 || GET_CODE (XEXP (x, 0)) == NEG)
4069 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
4070 || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
4071 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4072 return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode,
4073 XEXP (XEXP (XEXP (x, 0), 0), 0));
4075 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
4077 if (GET_CODE (XEXP (x, 0)) == SUBREG
4078 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE
4079 && subreg_lowpart_p (XEXP (x, 0)))
4080 return SUBREG_REG (XEXP (x, 0));
4082 /* If we know that the value is already truncated, we can
4083 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
4084 is nonzero for the corresponding modes. But don't do this
4085 for an (LSHIFTRT (MULT ...)) since this will cause problems
4086 with the umulXi3_highpart patterns. */
4087 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4088 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
4089 && num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4090 >= GET_MODE_BITSIZE (mode) + 1
4091 && ! (GET_CODE (XEXP (x, 0)) == LSHIFTRT
4092 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT))
4093 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4095 /* A truncate of a comparison can be replaced with a subreg if
4096 STORE_FLAG_VALUE permits. This is like the previous test,
4097 but it works even if the comparison is done in a mode larger
4098 than HOST_BITS_PER_WIDE_INT. */
4099 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4100 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4101 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0)
4102 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4104 /* Similarly, a truncate of a register whose value is a
4105 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4107 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4108 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
4109 && (temp = get_last_value (XEXP (x, 0)))
4110 && GET_RTX_CLASS (GET_CODE (temp)) == '<')
4111 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4115 case FLOAT_TRUNCATE:
4116 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4117 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
4118 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4119 return XEXP (XEXP (x, 0), 0);
4121 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4122 (OP:SF foo:SF) if OP is NEG or ABS. */
4123 if ((GET_CODE (XEXP (x, 0)) == ABS
4124 || GET_CODE (XEXP (x, 0)) == NEG)
4125 && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
4126 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4127 return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode,
4128 XEXP (XEXP (XEXP (x, 0), 0), 0));
4130 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4131 is (float_truncate:SF x). */
4132 if (GET_CODE (XEXP (x, 0)) == SUBREG
4133 && subreg_lowpart_p (XEXP (x, 0))
4134 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
4135 return SUBREG_REG (XEXP (x, 0));
4140 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4141 using cc0, in which case we want to leave it as a COMPARE
4142 so we can distinguish it from a register-register-copy. */
4143 if (XEXP (x, 1) == const0_rtx)
4146 /* In IEEE floating point, x-0 is not the same as x. */
4147 if ((TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
4148 || ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0)))
4150 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4156 /* (const (const X)) can become (const X). Do it this way rather than
4157 returning the inner CONST since CONST can be shared with a
4159 if (GET_CODE (XEXP (x, 0)) == CONST)
4160 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4165 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4166 can add in an offset. find_split_point will split this address up
4167 again if it doesn't match. */
4168 if (GET_CODE (XEXP (x, 0)) == HIGH
4169 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4175 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4176 outermost. That's because that's the way indexed addresses are
4177 supposed to appear. This code used to check many more cases, but
4178 they are now checked elsewhere. */
4179 if (GET_CODE (XEXP (x, 0)) == PLUS
4180 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
4181 return gen_binary (PLUS, mode,
4182 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
4184 XEXP (XEXP (x, 0), 1));
4186 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4187 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4188 bit-field and can be replaced by either a sign_extend or a
4189 sign_extract. The `and' may be a zero_extend and the two
4190 <c>, -<c> constants may be reversed. */
4191 if (GET_CODE (XEXP (x, 0)) == XOR
4192 && GET_CODE (XEXP (x, 1)) == CONST_INT
4193 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4194 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
4195 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4196 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4197 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4198 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4199 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4200 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4201 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4202 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4203 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4204 == (unsigned int) i + 1))))
4205 return simplify_shift_const
4206 (NULL_RTX, ASHIFTRT, mode,
4207 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4208 XEXP (XEXP (XEXP (x, 0), 0), 0),
4209 GET_MODE_BITSIZE (mode) - (i + 1)),
4210 GET_MODE_BITSIZE (mode) - (i + 1));
4212 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4213 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4214 is 1. This produces better code than the alternative immediately
4216 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4217 && reversible_comparison_p (XEXP (x, 0))
4218 && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
4219 || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx)))
4221 gen_unary (NEG, mode, mode,
4222 gen_binary (reverse_condition (GET_CODE (XEXP (x, 0))),
4223 mode, XEXP (XEXP (x, 0), 0),
4224 XEXP (XEXP (x, 0), 1)));
4226 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4227 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4228 the bitsize of the mode - 1. This allows simplification of
4229 "a = (b & 8) == 0;" */
4230 if (XEXP (x, 1) == constm1_rtx
4231 && GET_CODE (XEXP (x, 0)) != REG
4232 && ! (GET_CODE (XEXP (x,0)) == SUBREG
4233 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
4234 && nonzero_bits (XEXP (x, 0), mode) == 1)
4235 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4236 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4237 gen_rtx_combine (XOR, mode,
4238 XEXP (x, 0), const1_rtx),
4239 GET_MODE_BITSIZE (mode) - 1),
4240 GET_MODE_BITSIZE (mode) - 1);
4242 /* If we are adding two things that have no bits in common, convert
4243 the addition into an IOR. This will often be further simplified,
4244 for example in cases like ((a & 1) + (a & 2)), which can
4247 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4248 && (nonzero_bits (XEXP (x, 0), mode)
4249 & nonzero_bits (XEXP (x, 1), mode)) == 0)
4251 /* Try to simplify the expression further. */
4252 rtx tor = gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4253 temp = combine_simplify_rtx (tor, mode, last, in_dest);
4255 /* If we could, great. If not, do not go ahead with the IOR
4256 replacement, since PLUS appears in many special purpose
4257 address arithmetic instructions. */
4258 if (GET_CODE (temp) != CLOBBER && temp != tor)
4264 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4265 by reversing the comparison code if valid. */
4266 if (STORE_FLAG_VALUE == 1
4267 && XEXP (x, 0) == const1_rtx
4268 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<'
4269 && reversible_comparison_p (XEXP (x, 1)))
4270 return gen_binary (reverse_condition (GET_CODE (XEXP (x, 1))), mode,
4271 XEXP (XEXP (x, 1), 0),
4272 XEXP (XEXP (x, 1), 1));
4274 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4275 (and <foo> (const_int pow2-1)) */
4276 if (GET_CODE (XEXP (x, 1)) == AND
4277 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4278 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4279 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4280 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4281 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4283 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4285 if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
4286 return gen_binary (MINUS, mode,
4287 gen_binary (MINUS, mode, XEXP (x, 0),
4288 XEXP (XEXP (x, 1), 0)),
4289 XEXP (XEXP (x, 1), 1));
4293 /* If we have (mult (plus A B) C), apply the distributive law and then
4294 the inverse distributive law to see if things simplify. This
4295 occurs mostly in addresses, often when unrolling loops. */
4297 if (GET_CODE (XEXP (x, 0)) == PLUS)
4299 x = apply_distributive_law
4300 (gen_binary (PLUS, mode,
4301 gen_binary (MULT, mode,
4302 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
4303 gen_binary (MULT, mode,
4304 XEXP (XEXP (x, 0), 1),
4305 copy_rtx (XEXP (x, 1)))));
4307 if (GET_CODE (x) != MULT)
4313 /* If this is a divide by a power of two, treat it as a shift if
4314 its first operand is a shift. */
4315 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4316 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4317 && (GET_CODE (XEXP (x, 0)) == ASHIFT
4318 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4319 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4320 || GET_CODE (XEXP (x, 0)) == ROTATE
4321 || GET_CODE (XEXP (x, 0)) == ROTATERT))
4322 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
4326 case GT: case GTU: case GE: case GEU:
4327 case LT: case LTU: case LE: case LEU:
4328 /* If the first operand is a condition code, we can't do anything
4330 if (GET_CODE (XEXP (x, 0)) == COMPARE
4331 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4333 && XEXP (x, 0) != cc0_rtx
4337 rtx op0 = XEXP (x, 0);
4338 rtx op1 = XEXP (x, 1);
4339 enum rtx_code new_code;
4341 if (GET_CODE (op0) == COMPARE)
4342 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4344 /* Simplify our comparison, if possible. */
4345 new_code = simplify_comparison (code, &op0, &op1);
4347 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4348 if only the low-order bit is possibly nonzero in X (such as when
4349 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4350 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4351 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4354 Remove any ZERO_EXTRACT we made when thinking this was a
4355 comparison. It may now be simpler to use, e.g., an AND. If a
4356 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4357 the call to make_compound_operation in the SET case. */
4359 if (STORE_FLAG_VALUE == 1
4360 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4361 && op1 == const0_rtx
4362 && mode == GET_MODE (op0)
4363 && nonzero_bits (op0, mode) == 1)
4364 return gen_lowpart_for_combine (mode,
4365 expand_compound_operation (op0));
4367 else if (STORE_FLAG_VALUE == 1
4368 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4369 && op1 == const0_rtx
4370 && mode == GET_MODE (op0)
4371 && (num_sign_bit_copies (op0, mode)
4372 == GET_MODE_BITSIZE (mode)))
4374 op0 = expand_compound_operation (op0);
4375 return gen_unary (NEG, mode, mode,
4376 gen_lowpart_for_combine (mode, op0));
4379 else if (STORE_FLAG_VALUE == 1
4380 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4381 && op1 == const0_rtx
4382 && mode == GET_MODE (op0)
4383 && nonzero_bits (op0, mode) == 1)
4385 op0 = expand_compound_operation (op0);
4386 return gen_binary (XOR, mode,
4387 gen_lowpart_for_combine (mode, op0),
4391 else if (STORE_FLAG_VALUE == 1
4392 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4393 && op1 == const0_rtx
4394 && mode == GET_MODE (op0)
4395 && (num_sign_bit_copies (op0, mode)
4396 == GET_MODE_BITSIZE (mode)))
4398 op0 = expand_compound_operation (op0);
4399 return plus_constant (gen_lowpart_for_combine (mode, op0), 1);
4402 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4404 if (STORE_FLAG_VALUE == -1
4405 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4406 && op1 == const0_rtx
4407 && (num_sign_bit_copies (op0, mode)
4408 == GET_MODE_BITSIZE (mode)))
4409 return gen_lowpart_for_combine (mode,
4410 expand_compound_operation (op0));
4412 else if (STORE_FLAG_VALUE == -1
4413 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4414 && op1 == const0_rtx
4415 && mode == GET_MODE (op0)
4416 && nonzero_bits (op0, mode) == 1)
4418 op0 = expand_compound_operation (op0);
4419 return gen_unary (NEG, mode, mode,
4420 gen_lowpart_for_combine (mode, op0));
4423 else if (STORE_FLAG_VALUE == -1
4424 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4425 && op1 == const0_rtx
4426 && mode == GET_MODE (op0)
4427 && (num_sign_bit_copies (op0, mode)
4428 == GET_MODE_BITSIZE (mode)))
4430 op0 = expand_compound_operation (op0);
4431 return gen_unary (NOT, mode, mode,
4432 gen_lowpart_for_combine (mode, op0));
4435 /* If X is 0/1, (eq X 0) is X-1. */
4436 else if (STORE_FLAG_VALUE == -1
4437 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4438 && op1 == const0_rtx
4439 && mode == GET_MODE (op0)
4440 && nonzero_bits (op0, mode) == 1)
4442 op0 = expand_compound_operation (op0);
4443 return plus_constant (gen_lowpart_for_combine (mode, op0), -1);
4446 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4447 one bit that might be nonzero, we can convert (ne x 0) to
4448 (ashift x c) where C puts the bit in the sign bit. Remove any
4449 AND with STORE_FLAG_VALUE when we are done, since we are only
4450 going to test the sign bit. */
4451 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4452 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4453 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4454 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE(mode)-1))
4455 && op1 == const0_rtx
4456 && mode == GET_MODE (op0)
4457 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4459 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4460 expand_compound_operation (op0),
4461 GET_MODE_BITSIZE (mode) - 1 - i);
4462 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4468 /* If the code changed, return a whole new comparison. */
4469 if (new_code != code)
4470 return gen_rtx_combine (new_code, mode, op0, op1);
4472 /* Otherwise, keep this operation, but maybe change its operands.
4473 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4474 SUBST (XEXP (x, 0), op0);
4475 SUBST (XEXP (x, 1), op1);
4480 return simplify_if_then_else (x);
4486 /* If we are processing SET_DEST, we are done. */
4490 return expand_compound_operation (x);
4493 return simplify_set (x);
4498 return simplify_logical (x, last);
4501 /* (abs (neg <foo>)) -> (abs <foo>) */
4502 if (GET_CODE (XEXP (x, 0)) == NEG)
4503 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4505 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4507 if (GET_MODE (XEXP (x, 0)) == VOIDmode)
4510 /* If operand is something known to be positive, ignore the ABS. */
4511 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4512 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4513 <= HOST_BITS_PER_WIDE_INT)
4514 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4515 & ((HOST_WIDE_INT) 1
4516 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4520 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4521 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4522 return gen_rtx_combine (NEG, mode, XEXP (x, 0));
4527 /* (ffs (*_extend <X>)) = (ffs <X>) */
4528 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4529 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4530 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4534 /* (float (sign_extend <X>)) = (float <X>). */
4535 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4536 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4544 /* If this is a shift by a constant amount, simplify it. */
4545 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4546 return simplify_shift_const (x, code, mode, XEXP (x, 0),
4547 INTVAL (XEXP (x, 1)));
4549 #ifdef SHIFT_COUNT_TRUNCATED
4550 else if (SHIFT_COUNT_TRUNCATED && GET_CODE (XEXP (x, 1)) != REG)
4552 force_to_mode (XEXP (x, 1), GET_MODE (x),
4554 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4563 rtx op0 = XEXP (x, 0);
4564 rtx op1 = XEXP (x, 1);
4567 if (GET_CODE (op1) != PARALLEL)
4569 len = XVECLEN (op1, 0);
4571 && GET_CODE (XVECEXP (op1, 0, 0)) == CONST_INT
4572 && GET_CODE (op0) == VEC_CONCAT)
4574 int offset = INTVAL (XVECEXP (op1, 0, 0)) * GET_MODE_SIZE (GET_MODE (x));
4576 /* Try to find the element in the VEC_CONCAT. */
4579 if (GET_MODE (op0) == GET_MODE (x))
4581 if (GET_CODE (op0) == VEC_CONCAT)
4583 HOST_WIDE_INT op0_size = GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)));
4584 if (op0_size < offset)
4585 op0 = XEXP (op0, 0);
4589 op0 = XEXP (op0, 1);
4607 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4610 simplify_if_then_else (x)
4613 enum machine_mode mode = GET_MODE (x);
4614 rtx cond = XEXP (x, 0);
4615 rtx true = XEXP (x, 1);
4616 rtx false = XEXP (x, 2);
4617 enum rtx_code true_code = GET_CODE (cond);
4618 int comparison_p = GET_RTX_CLASS (true_code) == '<';
4622 /* Simplify storing of the truth value. */
4623 if (comparison_p && true == const_true_rtx && false == const0_rtx)
4624 return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1));
4626 /* Also when the truth value has to be reversed. */
4627 if (comparison_p && reversible_comparison_p (cond)
4628 && true == const0_rtx && false == const_true_rtx)
4629 return gen_binary (reverse_condition (true_code),
4630 mode, XEXP (cond, 0), XEXP (cond, 1));
4632 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4633 in it is being compared against certain values. Get the true and false
4634 comparisons and see if that says anything about the value of each arm. */
4636 if (comparison_p && reversible_comparison_p (cond)
4637 && GET_CODE (XEXP (cond, 0)) == REG)
4640 rtx from = XEXP (cond, 0);
4641 enum rtx_code false_code = reverse_condition (true_code);
4642 rtx true_val = XEXP (cond, 1);
4643 rtx false_val = true_val;
4646 /* If FALSE_CODE is EQ, swap the codes and arms. */
4648 if (false_code == EQ)
4650 swapped = 1, true_code = EQ, false_code = NE;
4651 temp = true, true = false, false = temp;
4654 /* If we are comparing against zero and the expression being tested has
4655 only a single bit that might be nonzero, that is its value when it is
4656 not equal to zero. Similarly if it is known to be -1 or 0. */
4658 if (true_code == EQ && true_val == const0_rtx
4659 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4660 false_code = EQ, false_val = GEN_INT (nzb);
4661 else if (true_code == EQ && true_val == const0_rtx
4662 && (num_sign_bit_copies (from, GET_MODE (from))
4663 == GET_MODE_BITSIZE (GET_MODE (from))))
4664 false_code = EQ, false_val = constm1_rtx;
4666 /* Now simplify an arm if we know the value of the register in the
4667 branch and it is used in the arm. Be careful due to the potential
4668 of locally-shared RTL. */
4670 if (reg_mentioned_p (from, true))
4671 true = subst (known_cond (copy_rtx (true), true_code, from, true_val),
4672 pc_rtx, pc_rtx, 0, 0);
4673 if (reg_mentioned_p (from, false))
4674 false = subst (known_cond (copy_rtx (false), false_code,
4676 pc_rtx, pc_rtx, 0, 0);
4678 SUBST (XEXP (x, 1), swapped ? false : true);
4679 SUBST (XEXP (x, 2), swapped ? true : false);
4681 true = XEXP (x, 1), false = XEXP (x, 2), true_code = GET_CODE (cond);
4684 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4685 reversed, do so to avoid needing two sets of patterns for
4686 subtract-and-branch insns. Similarly if we have a constant in the true
4687 arm, the false arm is the same as the first operand of the comparison, or
4688 the false arm is more complicated than the true arm. */
4690 if (comparison_p && reversible_comparison_p (cond)
4692 || (CONSTANT_P (true)
4693 && GET_CODE (false) != CONST_INT && false != pc_rtx)
4694 || true == const0_rtx
4695 || (GET_RTX_CLASS (GET_CODE (true)) == 'o'
4696 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4697 || (GET_CODE (true) == SUBREG
4698 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true))) == 'o'
4699 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4700 || reg_mentioned_p (true, false)
4701 || rtx_equal_p (false, XEXP (cond, 0))))
4703 true_code = reverse_condition (true_code);
4705 gen_binary (true_code, GET_MODE (cond), XEXP (cond, 0),
4708 SUBST (XEXP (x, 1), false);
4709 SUBST (XEXP (x, 2), true);
4711 temp = true, true = false, false = temp, cond = XEXP (x, 0);
4713 /* It is possible that the conditional has been simplified out. */
4714 true_code = GET_CODE (cond);
4715 comparison_p = GET_RTX_CLASS (true_code) == '<';
4718 /* If the two arms are identical, we don't need the comparison. */
4720 if (rtx_equal_p (true, false) && ! side_effects_p (cond))
4723 /* Convert a == b ? b : a to "a". */
4724 if (true_code == EQ && ! side_effects_p (cond)
4725 && (! FLOAT_MODE_P (mode) || flag_fast_math)
4726 && rtx_equal_p (XEXP (cond, 0), false)
4727 && rtx_equal_p (XEXP (cond, 1), true))
4729 else if (true_code == NE && ! side_effects_p (cond)
4730 && (! FLOAT_MODE_P (mode) || flag_fast_math)
4731 && rtx_equal_p (XEXP (cond, 0), true)
4732 && rtx_equal_p (XEXP (cond, 1), false))
4735 /* Look for cases where we have (abs x) or (neg (abs X)). */
4737 if (GET_MODE_CLASS (mode) == MODE_INT
4738 && GET_CODE (false) == NEG
4739 && rtx_equal_p (true, XEXP (false, 0))
4741 && rtx_equal_p (true, XEXP (cond, 0))
4742 && ! side_effects_p (true))
4747 return gen_unary (ABS, mode, mode, true);
4750 return gen_unary (NEG, mode, mode, gen_unary (ABS, mode, mode, true));
4755 /* Look for MIN or MAX. */
4757 if ((! FLOAT_MODE_P (mode) || flag_fast_math)
4759 && rtx_equal_p (XEXP (cond, 0), true)
4760 && rtx_equal_p (XEXP (cond, 1), false)
4761 && ! side_effects_p (cond))
4766 return gen_binary (SMAX, mode, true, false);
4769 return gen_binary (SMIN, mode, true, false);
4772 return gen_binary (UMAX, mode, true, false);
4775 return gen_binary (UMIN, mode, true, false);
4780 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4781 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4782 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4783 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4784 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4785 neither 1 or -1, but it isn't worth checking for. */
4787 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4788 && comparison_p && mode != VOIDmode && ! side_effects_p (x))
4790 rtx t = make_compound_operation (true, SET);
4791 rtx f = make_compound_operation (false, SET);
4792 rtx cond_op0 = XEXP (cond, 0);
4793 rtx cond_op1 = XEXP (cond, 1);
4794 enum rtx_code op = NIL, extend_op = NIL;
4795 enum machine_mode m = mode;
4796 rtx z = 0, c1 = NULL_RTX;
4798 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4799 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4800 || GET_CODE (t) == ASHIFT
4801 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4802 && rtx_equal_p (XEXP (t, 0), f))
4803 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4805 /* If an identity-zero op is commutative, check whether there
4806 would be a match if we swapped the operands. */
4807 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4808 || GET_CODE (t) == XOR)
4809 && rtx_equal_p (XEXP (t, 1), f))
4810 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4811 else if (GET_CODE (t) == SIGN_EXTEND
4812 && (GET_CODE (XEXP (t, 0)) == PLUS
4813 || GET_CODE (XEXP (t, 0)) == MINUS
4814 || GET_CODE (XEXP (t, 0)) == IOR
4815 || GET_CODE (XEXP (t, 0)) == XOR
4816 || GET_CODE (XEXP (t, 0)) == ASHIFT
4817 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4818 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4819 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4820 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4821 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4822 && (num_sign_bit_copies (f, GET_MODE (f))
4823 > (GET_MODE_BITSIZE (mode)
4824 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
4826 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4827 extend_op = SIGN_EXTEND;
4828 m = GET_MODE (XEXP (t, 0));
4830 else if (GET_CODE (t) == SIGN_EXTEND
4831 && (GET_CODE (XEXP (t, 0)) == PLUS
4832 || GET_CODE (XEXP (t, 0)) == IOR
4833 || GET_CODE (XEXP (t, 0)) == XOR)
4834 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4835 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4836 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4837 && (num_sign_bit_copies (f, GET_MODE (f))
4838 > (GET_MODE_BITSIZE (mode)
4839 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
4841 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4842 extend_op = SIGN_EXTEND;
4843 m = GET_MODE (XEXP (t, 0));
4845 else if (GET_CODE (t) == ZERO_EXTEND
4846 && (GET_CODE (XEXP (t, 0)) == PLUS
4847 || GET_CODE (XEXP (t, 0)) == MINUS
4848 || GET_CODE (XEXP (t, 0)) == IOR
4849 || GET_CODE (XEXP (t, 0)) == XOR
4850 || GET_CODE (XEXP (t, 0)) == ASHIFT
4851 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4852 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4853 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4854 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4855 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4856 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4857 && ((nonzero_bits (f, GET_MODE (f))
4858 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
4861 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4862 extend_op = ZERO_EXTEND;
4863 m = GET_MODE (XEXP (t, 0));
4865 else if (GET_CODE (t) == ZERO_EXTEND
4866 && (GET_CODE (XEXP (t, 0)) == PLUS
4867 || GET_CODE (XEXP (t, 0)) == IOR
4868 || GET_CODE (XEXP (t, 0)) == XOR)
4869 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4870 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4871 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4872 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4873 && ((nonzero_bits (f, GET_MODE (f))
4874 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
4877 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4878 extend_op = ZERO_EXTEND;
4879 m = GET_MODE (XEXP (t, 0));
4884 temp = subst (gen_binary (true_code, m, cond_op0, cond_op1),
4885 pc_rtx, pc_rtx, 0, 0);
4886 temp = gen_binary (MULT, m, temp,
4887 gen_binary (MULT, m, c1, const_true_rtx));
4888 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
4889 temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp);
4891 if (extend_op != NIL)
4892 temp = gen_unary (extend_op, mode, m, temp);
4898 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4899 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4900 negation of a single bit, we can convert this operation to a shift. We
4901 can actually do this more generally, but it doesn't seem worth it. */
4903 if (true_code == NE && XEXP (cond, 1) == const0_rtx
4904 && false == const0_rtx && GET_CODE (true) == CONST_INT
4905 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
4906 && (i = exact_log2 (INTVAL (true))) >= 0)
4907 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
4908 == GET_MODE_BITSIZE (mode))
4909 && (i = exact_log2 (-INTVAL (true))) >= 0)))
4911 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4912 gen_lowpart_for_combine (mode, XEXP (cond, 0)), i);
4917 /* Simplify X, a SET expression. Return the new expression. */
4923 rtx src = SET_SRC (x);
4924 rtx dest = SET_DEST (x);
4925 enum machine_mode mode
4926 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
4930 /* (set (pc) (return)) gets written as (return). */
4931 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
4934 /* Now that we know for sure which bits of SRC we are using, see if we can
4935 simplify the expression for the object knowing that we only need the
4938 if (GET_MODE_CLASS (mode) == MODE_INT)
4940 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, NULL_RTX, 0);
4941 SUBST (SET_SRC (x), src);
4944 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4945 the comparison result and try to simplify it unless we already have used
4946 undobuf.other_insn. */
4947 if ((GET_CODE (src) == COMPARE
4952 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
4953 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
4954 && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
4955 && rtx_equal_p (XEXP (*cc_use, 0), dest))
4957 enum rtx_code old_code = GET_CODE (*cc_use);
4958 enum rtx_code new_code;
4960 int other_changed = 0;
4961 enum machine_mode compare_mode = GET_MODE (dest);
4963 if (GET_CODE (src) == COMPARE)
4964 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
4966 op0 = src, op1 = const0_rtx;
4968 /* Simplify our comparison, if possible. */
4969 new_code = simplify_comparison (old_code, &op0, &op1);
4971 #ifdef EXTRA_CC_MODES
4972 /* If this machine has CC modes other than CCmode, check to see if we
4973 need to use a different CC mode here. */
4974 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
4975 #endif /* EXTRA_CC_MODES */
4977 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
4978 /* If the mode changed, we have to change SET_DEST, the mode in the
4979 compare, and the mode in the place SET_DEST is used. If SET_DEST is
4980 a hard register, just build new versions with the proper mode. If it
4981 is a pseudo, we lose unless it is only time we set the pseudo, in
4982 which case we can safely change its mode. */
4983 if (compare_mode != GET_MODE (dest))
4985 unsigned int regno = REGNO (dest);
4986 rtx new_dest = gen_rtx_REG (compare_mode, regno);
4988 if (regno < FIRST_PSEUDO_REGISTER
4989 || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest)))
4991 if (regno >= FIRST_PSEUDO_REGISTER)
4992 SUBST (regno_reg_rtx[regno], new_dest);
4994 SUBST (SET_DEST (x), new_dest);
4995 SUBST (XEXP (*cc_use, 0), new_dest);
5003 /* If the code changed, we have to build a new comparison in
5004 undobuf.other_insn. */
5005 if (new_code != old_code)
5007 unsigned HOST_WIDE_INT mask;
5009 SUBST (*cc_use, gen_rtx_combine (new_code, GET_MODE (*cc_use),
5012 /* If the only change we made was to change an EQ into an NE or
5013 vice versa, OP0 has only one bit that might be nonzero, and OP1
5014 is zero, check if changing the user of the condition code will
5015 produce a valid insn. If it won't, we can keep the original code
5016 in that insn by surrounding our operation with an XOR. */
5018 if (((old_code == NE && new_code == EQ)
5019 || (old_code == EQ && new_code == NE))
5020 && ! other_changed && op1 == const0_rtx
5021 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5022 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5024 rtx pat = PATTERN (other_insn), note = 0;
5026 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
5027 && ! check_asm_operands (pat)))
5029 PUT_CODE (*cc_use, old_code);
5032 op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask));
5040 undobuf.other_insn = other_insn;
5043 /* If we are now comparing against zero, change our source if
5044 needed. If we do not use cc0, we always have a COMPARE. */
5045 if (op1 == const0_rtx && dest == cc0_rtx)
5047 SUBST (SET_SRC (x), op0);
5053 /* Otherwise, if we didn't previously have a COMPARE in the
5054 correct mode, we need one. */
5055 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5058 gen_rtx_combine (COMPARE, compare_mode, op0, op1));
5063 /* Otherwise, update the COMPARE if needed. */
5064 SUBST (XEXP (src, 0), op0);
5065 SUBST (XEXP (src, 1), op1);
5070 /* Get SET_SRC in a form where we have placed back any
5071 compound expressions. Then do the checks below. */
5072 src = make_compound_operation (src, SET);
5073 SUBST (SET_SRC (x), src);
5076 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5077 and X being a REG or (subreg (reg)), we may be able to convert this to
5078 (set (subreg:m2 x) (op)).
5080 We can always do this if M1 is narrower than M2 because that means that
5081 we only care about the low bits of the result.
5083 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5084 perform a narrower operation than requested since the high-order bits will
5085 be undefined. On machine where it is defined, this transformation is safe
5086 as long as M1 and M2 have the same number of words. */
5088 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5089 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src))) != 'o'
5090 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5092 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5093 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5094 #ifndef WORD_REGISTER_OPERATIONS
5095 && (GET_MODE_SIZE (GET_MODE (src))
5096 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5098 #ifdef CLASS_CANNOT_CHANGE_MODE
5099 && ! (GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER
5100 && (TEST_HARD_REG_BIT
5101 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE],
5103 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (src),
5104 GET_MODE (SUBREG_REG (src))))
5106 && (GET_CODE (dest) == REG
5107 || (GET_CODE (dest) == SUBREG
5108 && GET_CODE (SUBREG_REG (dest)) == REG)))
5110 SUBST (SET_DEST (x),
5111 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src)),
5113 SUBST (SET_SRC (x), SUBREG_REG (src));
5115 src = SET_SRC (x), dest = SET_DEST (x);
5118 #ifdef LOAD_EXTEND_OP
5119 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5120 would require a paradoxical subreg. Replace the subreg with a
5121 zero_extend to avoid the reload that would otherwise be required. */
5123 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5124 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL
5125 && SUBREG_WORD (src) == 0
5126 && (GET_MODE_SIZE (GET_MODE (src))
5127 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5128 && GET_CODE (SUBREG_REG (src)) == MEM)
5131 gen_rtx_combine (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5132 GET_MODE (src), XEXP (src, 0)));
5138 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5139 are comparing an item known to be 0 or -1 against 0, use a logical
5140 operation instead. Check for one of the arms being an IOR of the other
5141 arm with some value. We compute three terms to be IOR'ed together. In
5142 practice, at most two will be nonzero. Then we do the IOR's. */
5144 if (GET_CODE (dest) != PC
5145 && GET_CODE (src) == IF_THEN_ELSE
5146 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5147 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5148 && XEXP (XEXP (src, 0), 1) == const0_rtx
5149 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5150 #ifdef HAVE_conditional_move
5151 && ! can_conditionally_move_p (GET_MODE (src))
5153 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5154 GET_MODE (XEXP (XEXP (src, 0), 0)))
5155 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5156 && ! side_effects_p (src))
5158 rtx true = (GET_CODE (XEXP (src, 0)) == NE
5159 ? XEXP (src, 1) : XEXP (src, 2));
5160 rtx false = (GET_CODE (XEXP (src, 0)) == NE
5161 ? XEXP (src, 2) : XEXP (src, 1));
5162 rtx term1 = const0_rtx, term2, term3;
5164 if (GET_CODE (true) == IOR && rtx_equal_p (XEXP (true, 0), false))
5165 term1 = false, true = XEXP (true, 1), false = const0_rtx;
5166 else if (GET_CODE (true) == IOR
5167 && rtx_equal_p (XEXP (true, 1), false))
5168 term1 = false, true = XEXP (true, 0), false = const0_rtx;
5169 else if (GET_CODE (false) == IOR
5170 && rtx_equal_p (XEXP (false, 0), true))
5171 term1 = true, false = XEXP (false, 1), true = const0_rtx;
5172 else if (GET_CODE (false) == IOR
5173 && rtx_equal_p (XEXP (false, 1), true))
5174 term1 = true, false = XEXP (false, 0), true = const0_rtx;
5176 term2 = gen_binary (AND, GET_MODE (src), XEXP (XEXP (src, 0), 0), true);
5177 term3 = gen_binary (AND, GET_MODE (src),
5178 gen_unary (NOT, GET_MODE (src), GET_MODE (src),
5179 XEXP (XEXP (src, 0), 0)),
5183 gen_binary (IOR, GET_MODE (src),
5184 gen_binary (IOR, GET_MODE (src), term1, term2),
5190 #ifdef HAVE_conditional_arithmetic
5191 /* If we have conditional arithmetic and the operand of a SET is
5192 a conditional expression, replace this with an IF_THEN_ELSE.
5193 We can either have a conditional expression or a MULT of that expression
5195 if ((GET_RTX_CLASS (GET_CODE (src)) == '1'
5196 || GET_RTX_CLASS (GET_CODE (src)) == '2'
5197 || GET_RTX_CLASS (GET_CODE (src)) == 'c')
5198 && (GET_RTX_CLASS (GET_CODE (XEXP (src, 0))) == '<'
5199 || (GET_CODE (XEXP (src, 0)) == MULT
5200 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (src, 0), 0))) == '<'
5201 && GET_CODE (XEXP (XEXP (src, 0), 1)) == CONST_INT)))
5203 rtx cond = XEXP (src, 0);
5204 rtx true_val = const1_rtx;
5205 rtx false_arm, true_arm;
5207 if (GET_CODE (cond) == MULT)
5209 true_val = XEXP (cond, 1);
5210 cond = XEXP (cond, 0);
5213 if (GET_RTX_CLASS (GET_CODE (src)) == '1')
5215 true_arm = gen_unary (GET_CODE (src), GET_MODE (src),
5216 GET_MODE (XEXP (src, 0)), true_val);
5217 false_arm = gen_unary (GET_CODE (src), GET_MODE (src),
5218 GET_MODE (XEXP (src, 0)), const0_rtx);
5222 true_arm = gen_binary (GET_CODE (src), GET_MODE (src),
5223 true_val, XEXP (src, 1));
5224 false_arm = gen_binary (GET_CODE (src), GET_MODE (src),
5225 const0_rtx, XEXP (src, 1));
5228 /* Canonicalize if true_arm is the simpler one. */
5229 if (GET_RTX_CLASS (GET_CODE (true_arm)) == 'o'
5230 && GET_RTX_CLASS (GET_CODE (false_arm)) != 'o'
5231 && reversible_comparison_p (cond))
5233 rtx temp = true_arm;
5235 true_arm = false_arm;
5238 cond = gen_rtx_combine (reverse_condition (GET_CODE (cond)),
5239 GET_MODE (cond), XEXP (cond, 0),
5243 src = gen_rtx_combine (IF_THEN_ELSE, GET_MODE (src),
5244 gen_rtx_combine (GET_CODE (cond), VOIDmode,
5247 true_arm, false_arm);
5248 SUBST (SET_SRC (x), src);
5252 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5253 whole thing fail. */
5254 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5256 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5259 /* Convert this into a field assignment operation, if possible. */
5260 return make_field_assignment (x);
5263 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5264 result. LAST is nonzero if this is the last retry. */
5267 simplify_logical (x, last)
5271 enum machine_mode mode = GET_MODE (x);
5272 rtx op0 = XEXP (x, 0);
5273 rtx op1 = XEXP (x, 1);
5275 switch (GET_CODE (x))
5278 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5279 insn (and may simplify more). */
5280 if (GET_CODE (op0) == XOR
5281 && rtx_equal_p (XEXP (op0, 0), op1)
5282 && ! side_effects_p (op1))
5283 x = gen_binary (AND, mode,
5284 gen_unary (NOT, mode, mode, XEXP (op0, 1)), op1);
5286 if (GET_CODE (op0) == XOR
5287 && rtx_equal_p (XEXP (op0, 1), op1)
5288 && ! side_effects_p (op1))
5289 x = gen_binary (AND, mode,
5290 gen_unary (NOT, mode, mode, XEXP (op0, 0)), op1);
5292 /* Similarly for (~(A ^ B)) & A. */
5293 if (GET_CODE (op0) == NOT
5294 && GET_CODE (XEXP (op0, 0)) == XOR
5295 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
5296 && ! side_effects_p (op1))
5297 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
5299 if (GET_CODE (op0) == NOT
5300 && GET_CODE (XEXP (op0, 0)) == XOR
5301 && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
5302 && ! side_effects_p (op1))
5303 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
5305 /* We can call simplify_and_const_int only if we don't lose
5306 any (sign) bits when converting INTVAL (op1) to
5307 "unsigned HOST_WIDE_INT". */
5308 if (GET_CODE (op1) == CONST_INT
5309 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5310 || INTVAL (op1) > 0))
5312 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5314 /* If we have (ior (and (X C1) C2)) and the next restart would be
5315 the last, simplify this by making C1 as small as possible
5318 && GET_CODE (x) == IOR && GET_CODE (op0) == AND
5319 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5320 && GET_CODE (op1) == CONST_INT)
5321 return gen_binary (IOR, mode,
5322 gen_binary (AND, mode, XEXP (op0, 0),
5323 GEN_INT (INTVAL (XEXP (op0, 1))
5324 & ~INTVAL (op1))), op1);
5326 if (GET_CODE (x) != AND)
5329 if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
5330 || GET_RTX_CLASS (GET_CODE (x)) == '2')
5331 op0 = XEXP (x, 0), op1 = XEXP (x, 1);
5334 /* Convert (A | B) & A to A. */
5335 if (GET_CODE (op0) == IOR
5336 && (rtx_equal_p (XEXP (op0, 0), op1)
5337 || rtx_equal_p (XEXP (op0, 1), op1))
5338 && ! side_effects_p (XEXP (op0, 0))
5339 && ! side_effects_p (XEXP (op0, 1)))
5342 /* In the following group of tests (and those in case IOR below),
5343 we start with some combination of logical operations and apply
5344 the distributive law followed by the inverse distributive law.
5345 Most of the time, this results in no change. However, if some of
5346 the operands are the same or inverses of each other, simplifications
5349 For example, (and (ior A B) (not B)) can occur as the result of
5350 expanding a bit field assignment. When we apply the distributive
5351 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5352 which then simplifies to (and (A (not B))).
5354 If we have (and (ior A B) C), apply the distributive law and then
5355 the inverse distributive law to see if things simplify. */
5357 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5359 x = apply_distributive_law
5360 (gen_binary (GET_CODE (op0), mode,
5361 gen_binary (AND, mode, XEXP (op0, 0), op1),
5362 gen_binary (AND, mode, XEXP (op0, 1),
5364 if (GET_CODE (x) != AND)
5368 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5369 return apply_distributive_law
5370 (gen_binary (GET_CODE (op1), mode,
5371 gen_binary (AND, mode, XEXP (op1, 0), op0),
5372 gen_binary (AND, mode, XEXP (op1, 1),
5375 /* Similarly, taking advantage of the fact that
5376 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5378 if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR)
5379 return apply_distributive_law
5380 (gen_binary (XOR, mode,
5381 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)),
5382 gen_binary (IOR, mode, copy_rtx (XEXP (op0, 0)),
5385 else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR)
5386 return apply_distributive_law
5387 (gen_binary (XOR, mode,
5388 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)),
5389 gen_binary (IOR, mode, copy_rtx (XEXP (op1, 0)), XEXP (op0, 1))));
5393 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5394 if (GET_CODE (op1) == CONST_INT
5395 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5396 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
5399 /* Convert (A & B) | A to A. */
5400 if (GET_CODE (op0) == AND
5401 && (rtx_equal_p (XEXP (op0, 0), op1)
5402 || rtx_equal_p (XEXP (op0, 1), op1))
5403 && ! side_effects_p (XEXP (op0, 0))
5404 && ! side_effects_p (XEXP (op0, 1)))
5407 /* If we have (ior (and A B) C), apply the distributive law and then
5408 the inverse distributive law to see if things simplify. */
5410 if (GET_CODE (op0) == AND)
5412 x = apply_distributive_law
5413 (gen_binary (AND, mode,
5414 gen_binary (IOR, mode, XEXP (op0, 0), op1),
5415 gen_binary (IOR, mode, XEXP (op0, 1),
5418 if (GET_CODE (x) != IOR)
5422 if (GET_CODE (op1) == AND)
5424 x = apply_distributive_law
5425 (gen_binary (AND, mode,
5426 gen_binary (IOR, mode, XEXP (op1, 0), op0),
5427 gen_binary (IOR, mode, XEXP (op1, 1),
5430 if (GET_CODE (x) != IOR)
5434 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5435 mode size to (rotate A CX). */
5437 if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
5438 || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
5439 && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
5440 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5441 && GET_CODE (XEXP (op1, 1)) == CONST_INT
5442 && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
5443 == GET_MODE_BITSIZE (mode)))
5444 return gen_rtx_ROTATE (mode, XEXP (op0, 0),
5445 (GET_CODE (op0) == ASHIFT
5446 ? XEXP (op0, 1) : XEXP (op1, 1)));
5448 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5449 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5450 does not affect any of the bits in OP1, it can really be done
5451 as a PLUS and we can associate. We do this by seeing if OP1
5452 can be safely shifted left C bits. */
5453 if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
5454 && GET_CODE (XEXP (op0, 0)) == PLUS
5455 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
5456 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5457 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
5459 int count = INTVAL (XEXP (op0, 1));
5460 HOST_WIDE_INT mask = INTVAL (op1) << count;
5462 if (mask >> count == INTVAL (op1)
5463 && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
5465 SUBST (XEXP (XEXP (op0, 0), 1),
5466 GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
5473 /* If we are XORing two things that have no bits in common,
5474 convert them into an IOR. This helps to detect rotation encoded
5475 using those methods and possibly other simplifications. */
5477 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5478 && (nonzero_bits (op0, mode)
5479 & nonzero_bits (op1, mode)) == 0)
5480 return (gen_binary (IOR, mode, op0, op1));
5482 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5483 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5486 int num_negated = 0;
5488 if (GET_CODE (op0) == NOT)
5489 num_negated++, op0 = XEXP (op0, 0);
5490 if (GET_CODE (op1) == NOT)
5491 num_negated++, op1 = XEXP (op1, 0);
5493 if (num_negated == 2)
5495 SUBST (XEXP (x, 0), op0);
5496 SUBST (XEXP (x, 1), op1);
5498 else if (num_negated == 1)
5499 return gen_unary (NOT, mode, mode, gen_binary (XOR, mode, op0, op1));
5502 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5503 correspond to a machine insn or result in further simplifications
5504 if B is a constant. */
5506 if (GET_CODE (op0) == AND
5507 && rtx_equal_p (XEXP (op0, 1), op1)
5508 && ! side_effects_p (op1))
5509 return gen_binary (AND, mode,
5510 gen_unary (NOT, mode, mode, XEXP (op0, 0)),
5513 else if (GET_CODE (op0) == AND
5514 && rtx_equal_p (XEXP (op0, 0), op1)
5515 && ! side_effects_p (op1))
5516 return gen_binary (AND, mode,
5517 gen_unary (NOT, mode, mode, XEXP (op0, 1)),
5520 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5521 comparison if STORE_FLAG_VALUE is 1. */
5522 if (STORE_FLAG_VALUE == 1
5523 && op1 == const1_rtx
5524 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5525 && reversible_comparison_p (op0))
5526 return gen_rtx_combine (reverse_condition (GET_CODE (op0)),
5527 mode, XEXP (op0, 0), XEXP (op0, 1));
5529 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5530 is (lt foo (const_int 0)), so we can perform the above
5531 simplification if STORE_FLAG_VALUE is 1. */
5533 if (STORE_FLAG_VALUE == 1
5534 && op1 == const1_rtx
5535 && GET_CODE (op0) == LSHIFTRT
5536 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5537 && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
5538 return gen_rtx_combine (GE, mode, XEXP (op0, 0), const0_rtx);
5540 /* (xor (comparison foo bar) (const_int sign-bit))
5541 when STORE_FLAG_VALUE is the sign bit. */
5542 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5543 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5544 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5545 && op1 == const_true_rtx
5546 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5547 && reversible_comparison_p (op0))
5548 return gen_rtx_combine (reverse_condition (GET_CODE (op0)),
5549 mode, XEXP (op0, 0), XEXP (op0, 1));
5560 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5561 operations" because they can be replaced with two more basic operations.
5562 ZERO_EXTEND is also considered "compound" because it can be replaced with
5563 an AND operation, which is simpler, though only one operation.
5565 The function expand_compound_operation is called with an rtx expression
5566 and will convert it to the appropriate shifts and AND operations,
5567 simplifying at each stage.
5569 The function make_compound_operation is called to convert an expression
5570 consisting of shifts and ANDs into the equivalent compound expression.
5571 It is the inverse of this function, loosely speaking. */
5574 expand_compound_operation (x)
5577 unsigned HOST_WIDE_INT pos = 0, len;
5579 unsigned int modewidth;
5582 switch (GET_CODE (x))
5587 /* We can't necessarily use a const_int for a multiword mode;
5588 it depends on implicitly extending the value.
5589 Since we don't know the right way to extend it,
5590 we can't tell whether the implicit way is right.
5592 Even for a mode that is no wider than a const_int,
5593 we can't win, because we need to sign extend one of its bits through
5594 the rest of it, and we don't know which bit. */
5595 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5598 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5599 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5600 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5601 reloaded. If not for that, MEM's would very rarely be safe.
5603 Reject MODEs bigger than a word, because we might not be able
5604 to reference a two-register group starting with an arbitrary register
5605 (and currently gen_lowpart might crash for a SUBREG). */
5607 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5610 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5611 /* If the inner object has VOIDmode (the only way this can happen
5612 is if it is a ASM_OPERANDS), we can't do anything since we don't
5613 know how much masking to do. */
5622 /* If the operand is a CLOBBER, just return it. */
5623 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5626 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5627 || GET_CODE (XEXP (x, 2)) != CONST_INT
5628 || GET_MODE (XEXP (x, 0)) == VOIDmode)
5631 len = INTVAL (XEXP (x, 1));
5632 pos = INTVAL (XEXP (x, 2));
5634 /* If this goes outside the object being extracted, replace the object
5635 with a (use (mem ...)) construct that only combine understands
5636 and is used only for this purpose. */
5637 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5638 SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0)));
5640 if (BITS_BIG_ENDIAN)
5641 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5648 /* Convert sign extension to zero extension, if we know that the high
5649 bit is not set, as this is easier to optimize. It will be converted
5650 back to cheaper alternative in make_extraction. */
5651 if (GET_CODE (x) == SIGN_EXTEND
5652 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5653 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
5654 & ~(((unsigned HOST_WIDE_INT)
5655 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5659 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
5660 return expand_compound_operation (temp);
5663 /* We can optimize some special cases of ZERO_EXTEND. */
5664 if (GET_CODE (x) == ZERO_EXTEND)
5666 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5667 know that the last value didn't have any inappropriate bits
5669 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5670 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5671 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5672 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5673 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5674 return XEXP (XEXP (x, 0), 0);
5676 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5677 if (GET_CODE (XEXP (x, 0)) == SUBREG
5678 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5679 && subreg_lowpart_p (XEXP (x, 0))
5680 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5681 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5682 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5683 return SUBREG_REG (XEXP (x, 0));
5685 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5686 is a comparison and STORE_FLAG_VALUE permits. This is like
5687 the first case, but it works even when GET_MODE (x) is larger
5688 than HOST_WIDE_INT. */
5689 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5690 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5691 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) == '<'
5692 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5693 <= HOST_BITS_PER_WIDE_INT)
5694 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5695 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5696 return XEXP (XEXP (x, 0), 0);
5698 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5699 if (GET_CODE (XEXP (x, 0)) == SUBREG
5700 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5701 && subreg_lowpart_p (XEXP (x, 0))
5702 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == '<'
5703 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5704 <= HOST_BITS_PER_WIDE_INT)
5705 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5706 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5707 return SUBREG_REG (XEXP (x, 0));
5711 /* If we reach here, we want to return a pair of shifts. The inner
5712 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5713 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5714 logical depending on the value of UNSIGNEDP.
5716 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5717 converted into an AND of a shift.
5719 We must check for the case where the left shift would have a negative
5720 count. This can happen in a case like (x >> 31) & 255 on machines
5721 that can't shift by a constant. On those machines, we would first
5722 combine the shift with the AND to produce a variable-position
5723 extraction. Then the constant of 31 would be substituted in to produce
5724 a such a position. */
5726 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5727 if (modewidth + len >= pos)
5728 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5730 simplify_shift_const (NULL_RTX, ASHIFT,
5733 modewidth - pos - len),
5736 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5737 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5738 simplify_shift_const (NULL_RTX, LSHIFTRT,
5741 ((HOST_WIDE_INT) 1 << len) - 1);
5743 /* Any other cases we can't handle. */
5746 /* If we couldn't do this for some reason, return the original
5748 if (GET_CODE (tem) == CLOBBER)
5754 /* X is a SET which contains an assignment of one object into
5755 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5756 or certain SUBREGS). If possible, convert it into a series of
5759 We half-heartedly support variable positions, but do not at all
5760 support variable lengths. */
5763 expand_field_assignment (x)
5767 rtx pos; /* Always counts from low bit. */
5770 enum machine_mode compute_mode;
5772 /* Loop until we find something we can't simplify. */
5775 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5776 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5778 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5779 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5780 pos = GEN_INT (BITS_PER_WORD * SUBREG_WORD (XEXP (SET_DEST (x), 0)));
5782 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5783 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5785 inner = XEXP (SET_DEST (x), 0);
5786 len = INTVAL (XEXP (SET_DEST (x), 1));
5787 pos = XEXP (SET_DEST (x), 2);
5789 /* If the position is constant and spans the width of INNER,
5790 surround INNER with a USE to indicate this. */
5791 if (GET_CODE (pos) == CONST_INT
5792 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5793 inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner);
5795 if (BITS_BIG_ENDIAN)
5797 if (GET_CODE (pos) == CONST_INT)
5798 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5800 else if (GET_CODE (pos) == MINUS
5801 && GET_CODE (XEXP (pos, 1)) == CONST_INT
5802 && (INTVAL (XEXP (pos, 1))
5803 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5804 /* If position is ADJUST - X, new position is X. */
5805 pos = XEXP (pos, 0);
5807 pos = gen_binary (MINUS, GET_MODE (pos),
5808 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
5814 /* A SUBREG between two modes that occupy the same numbers of words
5815 can be done by moving the SUBREG to the source. */
5816 else if (GET_CODE (SET_DEST (x)) == SUBREG
5817 /* We need SUBREGs to compute nonzero_bits properly. */
5818 && nonzero_sign_valid
5819 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5820 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5821 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5822 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5824 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
5825 gen_lowpart_for_combine
5826 (GET_MODE (SUBREG_REG (SET_DEST (x))),
5833 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5834 inner = SUBREG_REG (inner);
5836 compute_mode = GET_MODE (inner);
5838 /* Don't attempt bitwise arithmetic on non-integral modes. */
5839 if (! INTEGRAL_MODE_P (compute_mode))
5841 enum machine_mode imode;
5843 /* Something is probably seriously wrong if this matches. */
5844 if (! FLOAT_MODE_P (compute_mode))
5847 /* Try to find an integral mode to pun with. */
5848 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
5849 if (imode == BLKmode)
5852 compute_mode = imode;
5853 inner = gen_lowpart_for_combine (imode, inner);
5856 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5857 if (len < HOST_BITS_PER_WIDE_INT)
5858 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
5862 /* Now compute the equivalent expression. Make a copy of INNER
5863 for the SET_DEST in case it is a MEM into which we will substitute;
5864 we don't want shared RTL in that case. */
5866 (VOIDmode, copy_rtx (inner),
5867 gen_binary (IOR, compute_mode,
5868 gen_binary (AND, compute_mode,
5869 gen_unary (NOT, compute_mode,
5875 gen_binary (ASHIFT, compute_mode,
5876 gen_binary (AND, compute_mode,
5877 gen_lowpart_for_combine
5878 (compute_mode, SET_SRC (x)),
5886 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5887 it is an RTX that represents a variable starting position; otherwise,
5888 POS is the (constant) starting bit position (counted from the LSB).
5890 INNER may be a USE. This will occur when we started with a bitfield
5891 that went outside the boundary of the object in memory, which is
5892 allowed on most machines. To isolate this case, we produce a USE
5893 whose mode is wide enough and surround the MEM with it. The only
5894 code that understands the USE is this routine. If it is not removed,
5895 it will cause the resulting insn not to match.
5897 UNSIGNEDP is non-zero for an unsigned reference and zero for a
5900 IN_DEST is non-zero if this is a reference in the destination of a
5901 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
5902 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5905 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
5906 ZERO_EXTRACT should be built even for bits starting at bit 0.
5908 MODE is the desired mode of the result (if IN_DEST == 0).
5910 The result is an RTX for the extraction or NULL_RTX if the target
5914 make_extraction (mode, inner, pos, pos_rtx, len,
5915 unsignedp, in_dest, in_compare)
5916 enum machine_mode mode;
5920 unsigned HOST_WIDE_INT len;
5922 int in_dest, in_compare;
5924 /* This mode describes the size of the storage area
5925 to fetch the overall value from. Within that, we
5926 ignore the POS lowest bits, etc. */
5927 enum machine_mode is_mode = GET_MODE (inner);
5928 enum machine_mode inner_mode;
5929 enum machine_mode wanted_inner_mode = byte_mode;
5930 enum machine_mode wanted_inner_reg_mode = word_mode;
5931 enum machine_mode pos_mode = word_mode;
5932 enum machine_mode extraction_mode = word_mode;
5933 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
5936 rtx orig_pos_rtx = pos_rtx;
5937 HOST_WIDE_INT orig_pos;
5939 /* Get some information about INNER and get the innermost object. */
5940 if (GET_CODE (inner) == USE)
5941 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
5942 /* We don't need to adjust the position because we set up the USE
5943 to pretend that it was a full-word object. */
5944 spans_byte = 1, inner = XEXP (inner, 0);
5945 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5947 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5948 consider just the QI as the memory to extract from.
5949 The subreg adds or removes high bits; its mode is
5950 irrelevant to the meaning of this extraction,
5951 since POS and LEN count from the lsb. */
5952 if (GET_CODE (SUBREG_REG (inner)) == MEM)
5953 is_mode = GET_MODE (SUBREG_REG (inner));
5954 inner = SUBREG_REG (inner);
5957 inner_mode = GET_MODE (inner);
5959 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
5960 pos = INTVAL (pos_rtx), pos_rtx = 0;
5962 /* See if this can be done without an extraction. We never can if the
5963 width of the field is not the same as that of some integer mode. For
5964 registers, we can only avoid the extraction if the position is at the
5965 low-order bit and this is either not in the destination or we have the
5966 appropriate STRICT_LOW_PART operation available.
5968 For MEM, we can avoid an extract if the field starts on an appropriate
5969 boundary and we can change the mode of the memory reference. However,
5970 we cannot directly access the MEM if we have a USE and the underlying
5971 MEM is not TMODE. This combination means that MEM was being used in a
5972 context where bits outside its mode were being referenced; that is only
5973 valid in bit-field insns. */
5975 if (tmode != BLKmode
5976 && ! (spans_byte && inner_mode != tmode)
5977 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
5978 && GET_CODE (inner) != MEM
5980 || (GET_CODE (inner) == REG
5981 && (movstrict_optab->handlers[(int) tmode].insn_code
5982 != CODE_FOR_nothing))))
5983 || (GET_CODE (inner) == MEM && pos_rtx == 0
5985 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
5986 : BITS_PER_UNIT)) == 0
5987 /* We can't do this if we are widening INNER_MODE (it
5988 may not be aligned, for one thing). */
5989 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
5990 && (inner_mode == tmode
5991 || (! mode_dependent_address_p (XEXP (inner, 0))
5992 && ! MEM_VOLATILE_P (inner))))))
5994 /* If INNER is a MEM, make a new MEM that encompasses just the desired
5995 field. If the original and current mode are the same, we need not
5996 adjust the offset. Otherwise, we do if bytes big endian.
5998 If INNER is not a MEM, get a piece consisting of just the field
5999 of interest (in this case POS % BITS_PER_WORD must be 0). */
6001 if (GET_CODE (inner) == MEM)
6004 /* POS counts from lsb, but make OFFSET count in memory order. */
6005 if (BYTES_BIG_ENDIAN)
6006 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
6008 offset = pos / BITS_PER_UNIT;
6010 new = gen_rtx_MEM (tmode, plus_constant (XEXP (inner, 0), offset));
6011 MEM_COPY_ATTRIBUTES (new, inner);
6013 else if (GET_CODE (inner) == REG)
6015 /* We can't call gen_lowpart_for_combine here since we always want
6016 a SUBREG and it would sometimes return a new hard register. */
6017 if (tmode != inner_mode)
6018 new = gen_rtx_SUBREG (tmode, inner,
6020 && (GET_MODE_SIZE (inner_mode)
6022 ? (((GET_MODE_SIZE (inner_mode)
6023 - GET_MODE_SIZE (tmode))
6025 - pos / BITS_PER_WORD)
6026 : pos / BITS_PER_WORD));
6031 new = force_to_mode (inner, tmode,
6032 len >= HOST_BITS_PER_WIDE_INT
6033 ? ~(unsigned HOST_WIDE_INT) 0
6034 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6037 /* If this extraction is going into the destination of a SET,
6038 make a STRICT_LOW_PART unless we made a MEM. */
6041 return (GET_CODE (new) == MEM ? new
6042 : (GET_CODE (new) != SUBREG
6043 ? gen_rtx_CLOBBER (tmode, const0_rtx)
6044 : gen_rtx_combine (STRICT_LOW_PART, VOIDmode, new)));
6049 /* If we know that no extraneous bits are set, and that the high
6050 bit is not set, convert the extraction to the cheaper of
6051 sign and zero extension, that are equivalent in these cases. */
6052 if (flag_expensive_optimizations
6053 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6054 && ((nonzero_bits (new, tmode)
6055 & ~(((unsigned HOST_WIDE_INT)
6056 GET_MODE_MASK (tmode))
6060 rtx temp = gen_rtx_ZERO_EXTEND (mode, new);
6061 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new);
6063 /* Prefer ZERO_EXTENSION, since it gives more information to
6065 if (rtx_cost (temp, SET) <= rtx_cost (temp1, SET))
6070 /* Otherwise, sign- or zero-extend unless we already are in the
6073 return (gen_rtx_combine (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6077 /* Unless this is a COMPARE or we have a funny memory reference,
6078 don't do anything with zero-extending field extracts starting at
6079 the low-order bit since they are simple AND operations. */
6080 if (pos_rtx == 0 && pos == 0 && ! in_dest
6081 && ! in_compare && ! spans_byte && unsignedp)
6084 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6085 we would be spanning bytes or if the position is not a constant and the
6086 length is not 1. In all other cases, we would only be going outside
6087 our object in cases when an original shift would have been
6089 if (! spans_byte && GET_CODE (inner) == MEM
6090 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6091 || (pos_rtx != 0 && len != 1)))
6094 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6095 and the mode for the result. */
6099 wanted_inner_reg_mode
6100 = insn_data[(int) CODE_FOR_insv].operand[0].mode;
6101 if (wanted_inner_reg_mode == VOIDmode)
6102 wanted_inner_reg_mode = word_mode;
6104 pos_mode = insn_data[(int) CODE_FOR_insv].operand[2].mode;
6105 if (pos_mode == VOIDmode)
6106 pos_mode = word_mode;
6108 extraction_mode = insn_data[(int) CODE_FOR_insv].operand[3].mode;
6109 if (extraction_mode == VOIDmode)
6110 extraction_mode = word_mode;
6115 if (! in_dest && unsignedp)
6117 wanted_inner_reg_mode
6118 = insn_data[(int) CODE_FOR_extzv].operand[1].mode;
6119 if (wanted_inner_reg_mode == VOIDmode)
6120 wanted_inner_reg_mode = word_mode;
6122 pos_mode = insn_data[(int) CODE_FOR_extzv].operand[3].mode;
6123 if (pos_mode == VOIDmode)
6124 pos_mode = word_mode;
6126 extraction_mode = insn_data[(int) CODE_FOR_extzv].operand[0].mode;
6127 if (extraction_mode == VOIDmode)
6128 extraction_mode = word_mode;
6133 if (! in_dest && ! unsignedp)
6135 wanted_inner_reg_mode
6136 = insn_data[(int) CODE_FOR_extv].operand[1].mode;
6137 if (wanted_inner_reg_mode == VOIDmode)
6138 wanted_inner_reg_mode = word_mode;
6140 pos_mode = insn_data[(int) CODE_FOR_extv].operand[3].mode;
6141 if (pos_mode == VOIDmode)
6142 pos_mode = word_mode;
6144 extraction_mode = insn_data[(int) CODE_FOR_extv].operand[0].mode;
6145 if (extraction_mode == VOIDmode)
6146 extraction_mode = word_mode;
6150 /* Never narrow an object, since that might not be safe. */
6152 if (mode != VOIDmode
6153 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6154 extraction_mode = mode;
6156 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6157 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6158 pos_mode = GET_MODE (pos_rtx);
6160 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6161 if we have to change the mode of memory and cannot, the desired mode is
6163 if (GET_CODE (inner) != MEM)
6164 wanted_inner_mode = wanted_inner_reg_mode;
6165 else if (inner_mode != wanted_inner_mode
6166 && (mode_dependent_address_p (XEXP (inner, 0))
6167 || MEM_VOLATILE_P (inner)))
6168 wanted_inner_mode = extraction_mode;
6172 if (BITS_BIG_ENDIAN)
6174 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6175 BITS_BIG_ENDIAN style. If position is constant, compute new
6176 position. Otherwise, build subtraction.
6177 Note that POS is relative to the mode of the original argument.
6178 If it's a MEM we need to recompute POS relative to that.
6179 However, if we're extracting from (or inserting into) a register,
6180 we want to recompute POS relative to wanted_inner_mode. */
6181 int width = (GET_CODE (inner) == MEM
6182 ? GET_MODE_BITSIZE (is_mode)
6183 : GET_MODE_BITSIZE (wanted_inner_mode));
6186 pos = width - len - pos;
6189 = gen_rtx_combine (MINUS, GET_MODE (pos_rtx),
6190 GEN_INT (width - len), pos_rtx);
6191 /* POS may be less than 0 now, but we check for that below.
6192 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
6195 /* If INNER has a wider mode, make it smaller. If this is a constant
6196 extract, try to adjust the byte to point to the byte containing
6198 if (wanted_inner_mode != VOIDmode
6199 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6200 && ((GET_CODE (inner) == MEM
6201 && (inner_mode == wanted_inner_mode
6202 || (! mode_dependent_address_p (XEXP (inner, 0))
6203 && ! MEM_VOLATILE_P (inner))))))
6207 /* The computations below will be correct if the machine is big
6208 endian in both bits and bytes or little endian in bits and bytes.
6209 If it is mixed, we must adjust. */
6211 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6212 adjust OFFSET to compensate. */
6213 if (BYTES_BIG_ENDIAN
6215 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6216 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6218 /* If this is a constant position, we can move to the desired byte. */
6221 offset += pos / BITS_PER_UNIT;
6222 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6225 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6227 && is_mode != wanted_inner_mode)
6228 offset = (GET_MODE_SIZE (is_mode)
6229 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6231 if (offset != 0 || inner_mode != wanted_inner_mode)
6233 rtx newmem = gen_rtx_MEM (wanted_inner_mode,
6234 plus_constant (XEXP (inner, 0), offset));
6236 MEM_COPY_ATTRIBUTES (newmem, inner);
6241 /* If INNER is not memory, we can always get it into the proper mode. If we
6242 are changing its mode, POS must be a constant and smaller than the size
6244 else if (GET_CODE (inner) != MEM)
6246 if (GET_MODE (inner) != wanted_inner_mode
6248 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6251 inner = force_to_mode (inner, wanted_inner_mode,
6253 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6254 ? ~(unsigned HOST_WIDE_INT) 0
6255 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6260 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6261 have to zero extend. Otherwise, we can just use a SUBREG. */
6263 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6265 rtx temp = gen_rtx_combine (ZERO_EXTEND, pos_mode, pos_rtx);
6267 /* If we know that no extraneous bits are set, and that the high
6268 bit is not set, convert extraction to cheaper one - eighter
6269 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6271 if (flag_expensive_optimizations
6272 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6273 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6274 & ~(((unsigned HOST_WIDE_INT)
6275 GET_MODE_MASK (GET_MODE (pos_rtx)))
6279 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6281 /* Prefer ZERO_EXTENSION, since it gives more information to
6283 if (rtx_cost (temp1, SET) < rtx_cost (temp, SET))
6288 else if (pos_rtx != 0
6289 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6290 pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
6292 /* Make POS_RTX unless we already have it and it is correct. If we don't
6293 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6295 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6296 pos_rtx = orig_pos_rtx;
6298 else if (pos_rtx == 0)
6299 pos_rtx = GEN_INT (pos);
6301 /* Make the required operation. See if we can use existing rtx. */
6302 new = gen_rtx_combine (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6303 extraction_mode, inner, GEN_INT (len), pos_rtx);
6305 new = gen_lowpart_for_combine (mode, new);
6310 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6311 with any other operations in X. Return X without that shift if so. */
6314 extract_left_shift (x, count)
6318 enum rtx_code code = GET_CODE (x);
6319 enum machine_mode mode = GET_MODE (x);
6325 /* This is the shift itself. If it is wide enough, we will return
6326 either the value being shifted if the shift count is equal to
6327 COUNT or a shift for the difference. */
6328 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6329 && INTVAL (XEXP (x, 1)) >= count)
6330 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6331 INTVAL (XEXP (x, 1)) - count);
6335 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6336 return gen_unary (code, mode, mode, tem);
6340 case PLUS: case IOR: case XOR: case AND:
6341 /* If we can safely shift this constant and we find the inner shift,
6342 make a new operation. */
6343 if (GET_CODE (XEXP (x,1)) == CONST_INT
6344 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6345 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6346 return gen_binary (code, mode, tem,
6347 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6358 /* Look at the expression rooted at X. Look for expressions
6359 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6360 Form these expressions.
6362 Return the new rtx, usually just X.
6364 Also, for machines like the Vax that don't have logical shift insns,
6365 try to convert logical to arithmetic shift operations in cases where
6366 they are equivalent. This undoes the canonicalizations to logical
6367 shifts done elsewhere.
6369 We try, as much as possible, to re-use rtl expressions to save memory.
6371 IN_CODE says what kind of expression we are processing. Normally, it is
6372 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6373 being kludges), it is MEM. When processing the arguments of a comparison
6374 or a COMPARE against zero, it is COMPARE. */
6377 make_compound_operation (x, in_code)
6379 enum rtx_code in_code;
6381 enum rtx_code code = GET_CODE (x);
6382 enum machine_mode mode = GET_MODE (x);
6383 int mode_width = GET_MODE_BITSIZE (mode);
6385 enum rtx_code next_code;
6391 /* Select the code to be used in recursive calls. Once we are inside an
6392 address, we stay there. If we have a comparison, set to COMPARE,
6393 but once inside, go back to our default of SET. */
6395 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6396 : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
6397 && XEXP (x, 1) == const0_rtx) ? COMPARE
6398 : in_code == COMPARE ? SET : in_code);
6400 /* Process depending on the code of this operation. If NEW is set
6401 non-zero, it will be returned. */
6406 /* Convert shifts by constants into multiplications if inside
6408 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6409 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6410 && INTVAL (XEXP (x, 1)) >= 0)
6412 new = make_compound_operation (XEXP (x, 0), next_code);
6413 new = gen_rtx_combine (MULT, mode, new,
6414 GEN_INT ((HOST_WIDE_INT) 1
6415 << INTVAL (XEXP (x, 1))));
6420 /* If the second operand is not a constant, we can't do anything
6422 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6425 /* If the constant is a power of two minus one and the first operand
6426 is a logical right shift, make an extraction. */
6427 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6428 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6430 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6431 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6432 0, in_code == COMPARE);
6435 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6436 else if (GET_CODE (XEXP (x, 0)) == SUBREG
6437 && subreg_lowpart_p (XEXP (x, 0))
6438 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6439 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6441 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6443 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6444 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6445 0, in_code == COMPARE);
6447 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6448 else if ((GET_CODE (XEXP (x, 0)) == XOR
6449 || GET_CODE (XEXP (x, 0)) == IOR)
6450 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6451 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6452 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6454 /* Apply the distributive law, and then try to make extractions. */
6455 new = gen_rtx_combine (GET_CODE (XEXP (x, 0)), mode,
6456 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6458 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6460 new = make_compound_operation (new, in_code);
6463 /* If we are have (and (rotate X C) M) and C is larger than the number
6464 of bits in M, this is an extraction. */
6466 else if (GET_CODE (XEXP (x, 0)) == ROTATE
6467 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6468 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6469 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6471 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6472 new = make_extraction (mode, new,
6473 (GET_MODE_BITSIZE (mode)
6474 - INTVAL (XEXP (XEXP (x, 0), 1))),
6475 NULL_RTX, i, 1, 0, in_code == COMPARE);
6478 /* On machines without logical shifts, if the operand of the AND is
6479 a logical shift and our mask turns off all the propagated sign
6480 bits, we can replace the logical shift with an arithmetic shift. */
6481 else if (ashr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
6482 && (lshr_optab->handlers[(int) mode].insn_code
6483 == CODE_FOR_nothing)
6484 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
6485 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6486 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6487 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6488 && mode_width <= HOST_BITS_PER_WIDE_INT)
6490 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6492 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6493 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6495 gen_rtx_combine (ASHIFTRT, mode,
6496 make_compound_operation (XEXP (XEXP (x, 0), 0),
6498 XEXP (XEXP (x, 0), 1)));
6501 /* If the constant is one less than a power of two, this might be
6502 representable by an extraction even if no shift is present.
6503 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6504 we are in a COMPARE. */
6505 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6506 new = make_extraction (mode,
6507 make_compound_operation (XEXP (x, 0),
6509 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6511 /* If we are in a comparison and this is an AND with a power of two,
6512 convert this into the appropriate bit extract. */
6513 else if (in_code == COMPARE
6514 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6515 new = make_extraction (mode,
6516 make_compound_operation (XEXP (x, 0),
6518 i, NULL_RTX, 1, 1, 0, 1);
6523 /* If the sign bit is known to be zero, replace this with an
6524 arithmetic shift. */
6525 if (ashr_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing
6526 && lshr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
6527 && mode_width <= HOST_BITS_PER_WIDE_INT
6528 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6530 new = gen_rtx_combine (ASHIFTRT, mode,
6531 make_compound_operation (XEXP (x, 0),
6537 /* ... fall through ... */
6543 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6544 this is a SIGN_EXTRACT. */
6545 if (GET_CODE (rhs) == CONST_INT
6546 && GET_CODE (lhs) == ASHIFT
6547 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6548 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6550 new = make_compound_operation (XEXP (lhs, 0), next_code);
6551 new = make_extraction (mode, new,
6552 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6553 NULL_RTX, mode_width - INTVAL (rhs),
6554 code == LSHIFTRT, 0, in_code == COMPARE);
6558 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6559 If so, try to merge the shifts into a SIGN_EXTEND. We could
6560 also do this for some cases of SIGN_EXTRACT, but it doesn't
6561 seem worth the effort; the case checked for occurs on Alpha. */
6563 if (GET_RTX_CLASS (GET_CODE (lhs)) != 'o'
6564 && ! (GET_CODE (lhs) == SUBREG
6565 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs))) == 'o'))
6566 && GET_CODE (rhs) == CONST_INT
6567 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6568 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6569 new = make_extraction (mode, make_compound_operation (new, next_code),
6570 0, NULL_RTX, mode_width - INTVAL (rhs),
6571 code == LSHIFTRT, 0, in_code == COMPARE);
6576 /* Call ourselves recursively on the inner expression. If we are
6577 narrowing the object and it has a different RTL code from
6578 what it originally did, do this SUBREG as a force_to_mode. */
6580 tem = make_compound_operation (SUBREG_REG (x), in_code);
6581 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6582 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6583 && subreg_lowpart_p (x))
6585 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
6588 /* If we have something other than a SUBREG, we might have
6589 done an expansion, so rerun outselves. */
6590 if (GET_CODE (newer) != SUBREG)
6591 newer = make_compound_operation (newer, in_code);
6596 /* If this is a paradoxical subreg, and the new code is a sign or
6597 zero extension, omit the subreg and widen the extension. If it
6598 is a regular subreg, we can still get rid of the subreg by not
6599 widening so much, or in fact removing the extension entirely. */
6600 if ((GET_CODE (tem) == SIGN_EXTEND
6601 || GET_CODE (tem) == ZERO_EXTEND)
6602 && subreg_lowpart_p (x))
6604 if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (tem))
6605 || (GET_MODE_SIZE (mode) >
6606 GET_MODE_SIZE (GET_MODE (XEXP (tem, 0)))))
6607 tem = gen_rtx_combine (GET_CODE (tem), mode, XEXP (tem, 0));
6609 tem = gen_lowpart_for_combine (mode, XEXP (tem, 0));
6620 x = gen_lowpart_for_combine (mode, new);
6621 code = GET_CODE (x);
6624 /* Now recursively process each operand of this operation. */
6625 fmt = GET_RTX_FORMAT (code);
6626 for (i = 0; i < GET_RTX_LENGTH (code); i++)
6629 new = make_compound_operation (XEXP (x, i), next_code);
6630 SUBST (XEXP (x, i), new);
6636 /* Given M see if it is a value that would select a field of bits
6637 within an item, but not the entire word. Return -1 if not.
6638 Otherwise, return the starting position of the field, where 0 is the
6641 *PLEN is set to the length of the field. */
6644 get_pos_from_mask (m, plen)
6645 unsigned HOST_WIDE_INT m;
6646 unsigned HOST_WIDE_INT *plen;
6648 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6649 int pos = exact_log2 (m & -m);
6655 /* Now shift off the low-order zero bits and see if we have a power of
6657 len = exact_log2 ((m >> pos) + 1);
6666 /* See if X can be simplified knowing that we will only refer to it in
6667 MODE and will only refer to those bits that are nonzero in MASK.
6668 If other bits are being computed or if masking operations are done
6669 that select a superset of the bits in MASK, they can sometimes be
6672 Return a possibly simplified expression, but always convert X to
6673 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6675 Also, if REG is non-zero and X is a register equal in value to REG,
6678 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6679 are all off in X. This is used when X will be complemented, by either
6680 NOT, NEG, or XOR. */
6683 force_to_mode (x, mode, mask, reg, just_select)
6685 enum machine_mode mode;
6686 unsigned HOST_WIDE_INT mask;
6690 enum rtx_code code = GET_CODE (x);
6691 int next_select = just_select || code == XOR || code == NOT || code == NEG;
6692 enum machine_mode op_mode;
6693 unsigned HOST_WIDE_INT fuller_mask, nonzero;
6696 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6697 code below will do the wrong thing since the mode of such an
6698 expression is VOIDmode.
6700 Also do nothing if X is a CLOBBER; this can happen if X was
6701 the return value from a call to gen_lowpart_for_combine. */
6702 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
6705 /* We want to perform the operation is its present mode unless we know
6706 that the operation is valid in MODE, in which case we do the operation
6708 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6709 && code_to_optab[(int) code] != 0
6710 && (code_to_optab[(int) code]->handlers[(int) mode].insn_code
6711 != CODE_FOR_nothing))
6712 ? mode : GET_MODE (x));
6714 /* It is not valid to do a right-shift in a narrower mode
6715 than the one it came in with. */
6716 if ((code == LSHIFTRT || code == ASHIFTRT)
6717 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6718 op_mode = GET_MODE (x);
6720 /* Truncate MASK to fit OP_MODE. */
6722 mask &= GET_MODE_MASK (op_mode);
6724 /* When we have an arithmetic operation, or a shift whose count we
6725 do not know, we need to assume that all bit the up to the highest-order
6726 bit in MASK will be needed. This is how we form such a mask. */
6728 fuller_mask = (GET_MODE_BITSIZE (op_mode) >= HOST_BITS_PER_WIDE_INT
6729 ? GET_MODE_MASK (op_mode)
6730 : (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
6733 fuller_mask = ~(HOST_WIDE_INT) 0;
6735 /* Determine what bits of X are guaranteed to be (non)zero. */
6736 nonzero = nonzero_bits (x, mode);
6738 /* If none of the bits in X are needed, return a zero. */
6739 if (! just_select && (nonzero & mask) == 0)
6742 /* If X is a CONST_INT, return a new one. Do this here since the
6743 test below will fail. */
6744 if (GET_CODE (x) == CONST_INT)
6746 HOST_WIDE_INT cval = INTVAL (x) & mask;
6747 int width = GET_MODE_BITSIZE (mode);
6749 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6750 number, sign extend it. */
6751 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6752 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6753 cval |= (HOST_WIDE_INT) -1 << width;
6755 return GEN_INT (cval);
6758 /* If X is narrower than MODE and we want all the bits in X's mode, just
6759 get X in the proper mode. */
6760 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6761 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
6762 return gen_lowpart_for_combine (mode, x);
6764 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6765 MASK are already known to be zero in X, we need not do anything. */
6766 if (GET_MODE (x) == mode && code != SUBREG && (~mask & nonzero) == 0)
6772 /* If X is a (clobber (const_int)), return it since we know we are
6773 generating something that won't match. */
6777 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6778 spanned the boundary of the MEM. If we are now masking so it is
6779 within that boundary, we don't need the USE any more. */
6780 if (! BITS_BIG_ENDIAN
6781 && (mask & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6782 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6789 x = expand_compound_operation (x);
6790 if (GET_CODE (x) != code)
6791 return force_to_mode (x, mode, mask, reg, next_select);
6795 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
6796 || rtx_equal_p (reg, get_last_value (x))))
6801 if (subreg_lowpart_p (x)
6802 /* We can ignore the effect of this SUBREG if it narrows the mode or
6803 if the constant masks to zero all the bits the mode doesn't
6805 && ((GET_MODE_SIZE (GET_MODE (x))
6806 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6808 & GET_MODE_MASK (GET_MODE (x))
6809 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6810 return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
6814 /* If this is an AND with a constant, convert it into an AND
6815 whose constant is the AND of that constant with MASK. If it
6816 remains an AND of MASK, delete it since it is redundant. */
6818 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6820 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6821 mask & INTVAL (XEXP (x, 1)));
6823 /* If X is still an AND, see if it is an AND with a mask that
6824 is just some low-order bits. If so, and it is MASK, we don't
6827 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6828 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) == mask)
6831 /* If it remains an AND, try making another AND with the bits
6832 in the mode mask that aren't in MASK turned on. If the
6833 constant in the AND is wide enough, this might make a
6834 cheaper constant. */
6836 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6837 && GET_MODE_MASK (GET_MODE (x)) != mask
6838 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
6840 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6841 | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
6842 int width = GET_MODE_BITSIZE (GET_MODE (x));
6845 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6846 number, sign extend it. */
6847 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6848 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6849 cval |= (HOST_WIDE_INT) -1 << width;
6851 y = gen_binary (AND, GET_MODE (x), XEXP (x, 0), GEN_INT (cval));
6852 if (rtx_cost (y, SET) < rtx_cost (x, SET))
6862 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6863 low-order bits (as in an alignment operation) and FOO is already
6864 aligned to that boundary, mask C1 to that boundary as well.
6865 This may eliminate that PLUS and, later, the AND. */
6868 unsigned int width = GET_MODE_BITSIZE (mode);
6869 unsigned HOST_WIDE_INT smask = mask;
6871 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6872 number, sign extend it. */
6874 if (width < HOST_BITS_PER_WIDE_INT
6875 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6876 smask |= (HOST_WIDE_INT) -1 << width;
6878 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6879 && exact_log2 (- smask) >= 0)
6883 && (XEXP (x, 0) == stack_pointer_rtx
6884 || XEXP (x, 0) == frame_pointer_rtx))
6886 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
6887 unsigned HOST_WIDE_INT sp_mask = GET_MODE_MASK (mode);
6889 sp_mask &= ~(sp_alignment - 1);
6890 if ((sp_mask & ~smask) == 0
6891 && ((INTVAL (XEXP (x, 1)) - STACK_BIAS) & ~smask) != 0)
6892 return force_to_mode (plus_constant (XEXP (x, 0),
6893 ((INTVAL (XEXP (x, 1)) -
6894 STACK_BIAS) & smask)
6896 mode, smask, reg, next_select);
6899 if ((nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
6900 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
6901 return force_to_mode (plus_constant (XEXP (x, 0),
6902 (INTVAL (XEXP (x, 1))
6904 mode, smask, reg, next_select);
6908 /* ... fall through ... */
6911 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6912 most significant bit in MASK since carries from those bits will
6913 affect the bits we are interested in. */
6918 /* If X is (minus C Y) where C's least set bit is larger than any bit
6919 in the mask, then we may replace with (neg Y). */
6920 if (GET_CODE (XEXP (x, 0)) == CONST_INT
6921 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
6922 & -INTVAL (XEXP (x, 0))))
6925 x = gen_unary (NEG, GET_MODE (x), GET_MODE (x), XEXP (x, 1));
6926 return force_to_mode (x, mode, mask, reg, next_select);
6929 /* Similarly, if C contains every bit in the mask, then we may
6930 replace with (not Y). */
6931 if (GET_CODE (XEXP (x, 0)) == CONST_INT
6932 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) mask)
6933 == INTVAL (XEXP (x, 0))))
6935 x = gen_unary (NOT, GET_MODE (x), GET_MODE (x), XEXP (x, 1));
6936 return force_to_mode (x, mode, mask, reg, next_select);
6944 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6945 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6946 operation which may be a bitfield extraction. Ensure that the
6947 constant we form is not wider than the mode of X. */
6949 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6950 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6951 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6952 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6953 && GET_CODE (XEXP (x, 1)) == CONST_INT
6954 && ((INTVAL (XEXP (XEXP (x, 0), 1))
6955 + floor_log2 (INTVAL (XEXP (x, 1))))
6956 < GET_MODE_BITSIZE (GET_MODE (x)))
6957 && (INTVAL (XEXP (x, 1))
6958 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
6960 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
6961 << INTVAL (XEXP (XEXP (x, 0), 1)));
6962 temp = gen_binary (GET_CODE (x), GET_MODE (x),
6963 XEXP (XEXP (x, 0), 0), temp);
6964 x = gen_binary (LSHIFTRT, GET_MODE (x), temp,
6965 XEXP (XEXP (x, 0), 1));
6966 return force_to_mode (x, mode, mask, reg, next_select);
6970 /* For most binary operations, just propagate into the operation and
6971 change the mode if we have an operation of that mode. */
6973 op0 = gen_lowpart_for_combine (op_mode,
6974 force_to_mode (XEXP (x, 0), mode, mask,
6976 op1 = gen_lowpart_for_combine (op_mode,
6977 force_to_mode (XEXP (x, 1), mode, mask,
6980 /* If OP1 is a CONST_INT and X is an IOR or XOR, clear bits outside
6981 MASK since OP1 might have been sign-extended but we never want
6982 to turn on extra bits, since combine might have previously relied
6983 on them being off. */
6984 if (GET_CODE (op1) == CONST_INT && (code == IOR || code == XOR)
6985 && (INTVAL (op1) & mask) != 0)
6986 op1 = GEN_INT (INTVAL (op1) & mask);
6988 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6989 x = gen_binary (code, op_mode, op0, op1);
6993 /* For left shifts, do the same, but just for the first operand.
6994 However, we cannot do anything with shifts where we cannot
6995 guarantee that the counts are smaller than the size of the mode
6996 because such a count will have a different meaning in a
6999 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
7000 && INTVAL (XEXP (x, 1)) >= 0
7001 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
7002 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
7003 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
7004 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
7007 /* If the shift count is a constant and we can do arithmetic in
7008 the mode of the shift, refine which bits we need. Otherwise, use the
7009 conservative form of the mask. */
7010 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7011 && INTVAL (XEXP (x, 1)) >= 0
7012 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
7013 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7014 mask >>= INTVAL (XEXP (x, 1));
7018 op0 = gen_lowpart_for_combine (op_mode,
7019 force_to_mode (XEXP (x, 0), op_mode,
7020 mask, reg, next_select));
7022 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7023 x = gen_binary (code, op_mode, op0, XEXP (x, 1));
7027 /* Here we can only do something if the shift count is a constant,
7028 this shift constant is valid for the host, and we can do arithmetic
7031 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7032 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7033 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7035 rtx inner = XEXP (x, 0);
7036 unsigned HOST_WIDE_INT inner_mask;
7038 /* Select the mask of the bits we need for the shift operand. */
7039 inner_mask = mask << INTVAL (XEXP (x, 1));
7041 /* We can only change the mode of the shift if we can do arithmetic
7042 in the mode of the shift and INNER_MASK is no wider than the
7043 width of OP_MODE. */
7044 if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT
7045 || (inner_mask & ~GET_MODE_MASK (op_mode)) != 0)
7046 op_mode = GET_MODE (x);
7048 inner = force_to_mode (inner, op_mode, inner_mask, reg, next_select);
7050 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
7051 x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
7054 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7055 shift and AND produces only copies of the sign bit (C2 is one less
7056 than a power of two), we can do this with just a shift. */
7058 if (GET_CODE (x) == LSHIFTRT
7059 && GET_CODE (XEXP (x, 1)) == CONST_INT
7060 /* The shift puts one of the sign bit copies in the least significant
7062 && ((INTVAL (XEXP (x, 1))
7063 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7064 >= GET_MODE_BITSIZE (GET_MODE (x)))
7065 && exact_log2 (mask + 1) >= 0
7066 /* Number of bits left after the shift must be more than the mask
7068 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7069 <= GET_MODE_BITSIZE (GET_MODE (x)))
7070 /* Must be more sign bit copies than the mask needs. */
7071 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7072 >= exact_log2 (mask + 1)))
7073 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7074 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7075 - exact_log2 (mask + 1)));
7080 /* If we are just looking for the sign bit, we don't need this shift at
7081 all, even if it has a variable count. */
7082 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7083 && (mask == ((unsigned HOST_WIDE_INT) 1
7084 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7085 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7087 /* If this is a shift by a constant, get a mask that contains those bits
7088 that are not copies of the sign bit. We then have two cases: If
7089 MASK only includes those bits, this can be a logical shift, which may
7090 allow simplifications. If MASK is a single-bit field not within
7091 those bits, we are requesting a copy of the sign bit and hence can
7092 shift the sign bit to the appropriate location. */
7094 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
7095 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7099 /* If the considered data is wider then HOST_WIDE_INT, we can't
7100 represent a mask for all its bits in a single scalar.
7101 But we only care about the lower bits, so calculate these. */
7103 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7105 nonzero = ~(HOST_WIDE_INT) 0;
7107 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7108 is the number of bits a full-width mask would have set.
7109 We need only shift if these are fewer than nonzero can
7110 hold. If not, we must keep all bits set in nonzero. */
7112 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7113 < HOST_BITS_PER_WIDE_INT)
7114 nonzero >>= INTVAL (XEXP (x, 1))
7115 + HOST_BITS_PER_WIDE_INT
7116 - GET_MODE_BITSIZE (GET_MODE (x)) ;
7120 nonzero = GET_MODE_MASK (GET_MODE (x));
7121 nonzero >>= INTVAL (XEXP (x, 1));
7124 if ((mask & ~nonzero) == 0
7125 || (i = exact_log2 (mask)) >= 0)
7127 x = simplify_shift_const
7128 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7129 i < 0 ? INTVAL (XEXP (x, 1))
7130 : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7132 if (GET_CODE (x) != ASHIFTRT)
7133 return force_to_mode (x, mode, mask, reg, next_select);
7137 /* If MASK is 1, convert this to a LSHIFTRT. This can be done
7138 even if the shift count isn't a constant. */
7140 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1));
7144 /* If this is a zero- or sign-extension operation that just affects bits
7145 we don't care about, remove it. Be sure the call above returned
7146 something that is still a shift. */
7148 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7149 && GET_CODE (XEXP (x, 1)) == CONST_INT
7150 && INTVAL (XEXP (x, 1)) >= 0
7151 && (INTVAL (XEXP (x, 1))
7152 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7153 && GET_CODE (XEXP (x, 0)) == ASHIFT
7154 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7155 && INTVAL (XEXP (XEXP (x, 0), 1)) == INTVAL (XEXP (x, 1)))
7156 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7163 /* If the shift count is constant and we can do computations
7164 in the mode of X, compute where the bits we care about are.
7165 Otherwise, we can't do anything. Don't change the mode of
7166 the shift or propagate MODE into the shift, though. */
7167 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7168 && INTVAL (XEXP (x, 1)) >= 0)
7170 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7171 GET_MODE (x), GEN_INT (mask),
7173 if (temp && GET_CODE(temp) == CONST_INT)
7175 force_to_mode (XEXP (x, 0), GET_MODE (x),
7176 INTVAL (temp), reg, next_select));
7181 /* If we just want the low-order bit, the NEG isn't needed since it
7182 won't change the low-order bit. */
7184 return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
7186 /* We need any bits less significant than the most significant bit in
7187 MASK since carries from those bits will affect the bits we are
7193 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7194 same as the XOR case above. Ensure that the constant we form is not
7195 wider than the mode of X. */
7197 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7198 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7199 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7200 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7201 < GET_MODE_BITSIZE (GET_MODE (x)))
7202 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7204 temp = GEN_INT (mask << INTVAL (XEXP (XEXP (x, 0), 1)));
7205 temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp);
7206 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1));
7208 return force_to_mode (x, mode, mask, reg, next_select);
7211 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7212 use the full mask inside the NOT. */
7216 op0 = gen_lowpart_for_combine (op_mode,
7217 force_to_mode (XEXP (x, 0), mode, mask,
7219 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7220 x = gen_unary (code, op_mode, op_mode, op0);
7224 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7225 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7226 which is equal to STORE_FLAG_VALUE. */
7227 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7228 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7229 && nonzero_bits (XEXP (x, 0), mode) == STORE_FLAG_VALUE)
7230 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7235 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7236 written in a narrower mode. We play it safe and do not do so. */
7239 gen_lowpart_for_combine (GET_MODE (x),
7240 force_to_mode (XEXP (x, 1), mode,
7241 mask, reg, next_select)));
7243 gen_lowpart_for_combine (GET_MODE (x),
7244 force_to_mode (XEXP (x, 2), mode,
7245 mask, reg,next_select)));
7252 /* Ensure we return a value of the proper mode. */
7253 return gen_lowpart_for_combine (mode, x);
7256 /* Return nonzero if X is an expression that has one of two values depending on
7257 whether some other value is zero or nonzero. In that case, we return the
7258 value that is being tested, *PTRUE is set to the value if the rtx being
7259 returned has a nonzero value, and *PFALSE is set to the other alternative.
7261 If we return zero, we set *PTRUE and *PFALSE to X. */
7264 if_then_else_cond (x, ptrue, pfalse)
7266 rtx *ptrue, *pfalse;
7268 enum machine_mode mode = GET_MODE (x);
7269 enum rtx_code code = GET_CODE (x);
7270 rtx cond0, cond1, true0, true1, false0, false1;
7271 unsigned HOST_WIDE_INT nz;
7273 /* If we are comparing a value against zero, we are done. */
7274 if ((code == NE || code == EQ)
7275 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 0)
7277 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7278 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7282 /* If this is a unary operation whose operand has one of two values, apply
7283 our opcode to compute those values. */
7284 else if (GET_RTX_CLASS (code) == '1'
7285 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7287 *ptrue = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), true0);
7288 *pfalse = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), false0);
7292 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7293 make can't possibly match and would suppress other optimizations. */
7294 else if (code == COMPARE)
7297 /* If this is a binary operation, see if either side has only one of two
7298 values. If either one does or if both do and they are conditional on
7299 the same value, compute the new true and false values. */
7300 else if (GET_RTX_CLASS (code) == 'c' || GET_RTX_CLASS (code) == '2'
7301 || GET_RTX_CLASS (code) == '<')
7303 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7304 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7306 if ((cond0 != 0 || cond1 != 0)
7307 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7309 /* If if_then_else_cond returned zero, then true/false are the
7310 same rtl. We must copy one of them to prevent invalid rtl
7313 true0 = copy_rtx (true0);
7314 else if (cond1 == 0)
7315 true1 = copy_rtx (true1);
7317 *ptrue = gen_binary (code, mode, true0, true1);
7318 *pfalse = gen_binary (code, mode, false0, false1);
7319 return cond0 ? cond0 : cond1;
7322 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7323 operands is zero when the other is non-zero, and vice-versa,
7324 and STORE_FLAG_VALUE is 1 or -1. */
7326 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7327 && (code == PLUS || code == IOR || code == XOR || code == MINUS
7329 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7331 rtx op0 = XEXP (XEXP (x, 0), 1);
7332 rtx op1 = XEXP (XEXP (x, 1), 1);
7334 cond0 = XEXP (XEXP (x, 0), 0);
7335 cond1 = XEXP (XEXP (x, 1), 0);
7337 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7338 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7339 && reversible_comparison_p (cond1)
7340 && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1))
7341 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7342 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7343 || ((swap_condition (GET_CODE (cond0))
7344 == reverse_condition (GET_CODE (cond1)))
7345 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7346 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7347 && ! side_effects_p (x))
7349 *ptrue = gen_binary (MULT, mode, op0, const_true_rtx);
7350 *pfalse = gen_binary (MULT, mode,
7352 ? gen_unary (NEG, mode, mode, op1) : op1),
7358 /* Similarly for MULT, AND and UMIN, execpt that for these the result
7360 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7361 && (code == MULT || code == AND || code == UMIN)
7362 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7364 cond0 = XEXP (XEXP (x, 0), 0);
7365 cond1 = XEXP (XEXP (x, 1), 0);
7367 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7368 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7369 && reversible_comparison_p (cond1)
7370 && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1))
7371 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7372 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7373 || ((swap_condition (GET_CODE (cond0))
7374 == reverse_condition (GET_CODE (cond1)))
7375 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7376 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7377 && ! side_effects_p (x))
7379 *ptrue = *pfalse = const0_rtx;
7385 else if (code == IF_THEN_ELSE)
7387 /* If we have IF_THEN_ELSE already, extract the condition and
7388 canonicalize it if it is NE or EQ. */
7389 cond0 = XEXP (x, 0);
7390 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7391 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7392 return XEXP (cond0, 0);
7393 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7395 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7396 return XEXP (cond0, 0);
7402 /* If X is a normal SUBREG with both inner and outer modes integral,
7403 we can narrow both the true and false values of the inner expression,
7404 if there is a condition. */
7405 else if (code == SUBREG && GET_MODE_CLASS (mode) == MODE_INT
7406 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_INT
7407 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))
7408 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7411 if ((GET_CODE (SUBREG_REG (x)) == REG
7412 || GET_CODE (SUBREG_REG (x)) == MEM
7413 || CONSTANT_P (SUBREG_REG (x)))
7414 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))) > UNITS_PER_WORD
7415 && (WORDS_BIG_ENDIAN || SUBREG_WORD (x) != 0))
7417 true0 = operand_subword (true0, SUBREG_WORD (x), 0, mode);
7418 false0 = operand_subword (false0, SUBREG_WORD (x), 0, mode);
7420 *ptrue = force_to_mode (true0, mode, ~(HOST_WIDE_INT) 0, NULL_RTX, 0);
7422 = force_to_mode (false0, mode, ~(HOST_WIDE_INT) 0, NULL_RTX, 0);
7427 /* If X is a constant, this isn't special and will cause confusions
7428 if we treat it as such. Likewise if it is equivalent to a constant. */
7429 else if (CONSTANT_P (x)
7430 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7433 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7434 will be least confusing to the rest of the compiler. */
7435 else if (mode == BImode)
7437 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
7441 /* If X is known to be either 0 or -1, those are the true and
7442 false values when testing X. */
7443 else if (x == constm1_rtx || x == const0_rtx
7444 || (mode != VOIDmode
7445 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
7447 *ptrue = constm1_rtx, *pfalse = const0_rtx;
7451 /* Likewise for 0 or a single bit. */
7452 else if (mode != VOIDmode
7453 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7454 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7456 *ptrue = GEN_INT (nz), *pfalse = const0_rtx;
7460 /* Otherwise fail; show no condition with true and false values the same. */
7461 *ptrue = *pfalse = x;
7465 /* Return the value of expression X given the fact that condition COND
7466 is known to be true when applied to REG as its first operand and VAL
7467 as its second. X is known to not be shared and so can be modified in
7470 We only handle the simplest cases, and specifically those cases that
7471 arise with IF_THEN_ELSE expressions. */
7474 known_cond (x, cond, reg, val)
7479 enum rtx_code code = GET_CODE (x);
7484 if (side_effects_p (x))
7487 if (cond == EQ && rtx_equal_p (x, reg))
7490 /* If X is (abs REG) and we know something about REG's relationship
7491 with zero, we may be able to simplify this. */
7493 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
7496 case GE: case GT: case EQ:
7499 return gen_unary (NEG, GET_MODE (XEXP (x, 0)), GET_MODE (XEXP (x, 0)),
7505 /* The only other cases we handle are MIN, MAX, and comparisons if the
7506 operands are the same as REG and VAL. */
7508 else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
7510 if (rtx_equal_p (XEXP (x, 0), val))
7511 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
7513 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
7515 if (GET_RTX_CLASS (code) == '<')
7517 if (comparison_dominates_p (cond, code))
7518 return const_true_rtx;
7520 code = reverse_condition (code);
7522 && comparison_dominates_p (cond, code))
7527 else if (code == SMAX || code == SMIN
7528 || code == UMIN || code == UMAX)
7530 int unsignedp = (code == UMIN || code == UMAX);
7532 if (code == SMAX || code == UMAX)
7533 cond = reverse_condition (cond);
7538 return unsignedp ? x : XEXP (x, 1);
7540 return unsignedp ? x : XEXP (x, 0);
7542 return unsignedp ? XEXP (x, 1) : x;
7544 return unsignedp ? XEXP (x, 0) : x;
7552 fmt = GET_RTX_FORMAT (code);
7553 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7556 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7557 else if (fmt[i] == 'E')
7558 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7559 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7566 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7567 assignment as a field assignment. */
7570 rtx_equal_for_field_assignment_p (x, y)
7574 if (x == y || rtx_equal_p (x, y))
7577 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7580 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7581 Note that all SUBREGs of MEM are paradoxical; otherwise they
7582 would have been rewritten. */
7583 if (GET_CODE (x) == MEM && GET_CODE (y) == SUBREG
7584 && GET_CODE (SUBREG_REG (y)) == MEM
7585 && rtx_equal_p (SUBREG_REG (y),
7586 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y)), x)))
7589 if (GET_CODE (y) == MEM && GET_CODE (x) == SUBREG
7590 && GET_CODE (SUBREG_REG (x)) == MEM
7591 && rtx_equal_p (SUBREG_REG (x),
7592 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x)), y)))
7595 /* We used to see if get_last_value of X and Y were the same but that's
7596 not correct. In one direction, we'll cause the assignment to have
7597 the wrong destination and in the case, we'll import a register into this
7598 insn that might have already have been dead. So fail if none of the
7599 above cases are true. */
7603 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7604 Return that assignment if so.
7606 We only handle the most common cases. */
7609 make_field_assignment (x)
7612 rtx dest = SET_DEST (x);
7613 rtx src = SET_SRC (x);
7618 unsigned HOST_WIDE_INT len;
7620 enum machine_mode mode;
7622 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7623 a clear of a one-bit field. We will have changed it to
7624 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7627 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7628 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7629 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7630 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7632 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7635 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7639 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7640 && subreg_lowpart_p (XEXP (src, 0))
7641 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7642 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7643 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7644 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7645 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7647 assign = make_extraction (VOIDmode, dest, 0,
7648 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7651 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7655 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7657 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7658 && XEXP (XEXP (src, 0), 0) == const1_rtx
7659 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7661 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7664 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
7668 /* The other case we handle is assignments into a constant-position
7669 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7670 a mask that has all one bits except for a group of zero bits and
7671 OTHER is known to have zeros where C1 has ones, this is such an
7672 assignment. Compute the position and length from C1. Shift OTHER
7673 to the appropriate position, force it to the required mode, and
7674 make the extraction. Check for the AND in both operands. */
7676 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
7679 rhs = expand_compound_operation (XEXP (src, 0));
7680 lhs = expand_compound_operation (XEXP (src, 1));
7682 if (GET_CODE (rhs) == AND
7683 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7684 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7685 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7686 else if (GET_CODE (lhs) == AND
7687 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7688 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7689 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
7693 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
7694 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
7695 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7696 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
7699 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
7703 /* The mode to use for the source is the mode of the assignment, or of
7704 what is inside a possible STRICT_LOW_PART. */
7705 mode = (GET_CODE (assign) == STRICT_LOW_PART
7706 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
7708 /* Shift OTHER right POS places and make it the source, restricting it
7709 to the proper length and mode. */
7711 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
7712 GET_MODE (src), other, pos),
7714 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7715 ? ~(unsigned HOST_WIDE_INT) 0
7716 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7719 return gen_rtx_combine (SET, VOIDmode, assign, src);
7722 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7726 apply_distributive_law (x)
7729 enum rtx_code code = GET_CODE (x);
7730 rtx lhs, rhs, other;
7732 enum rtx_code inner_code;
7734 /* Distributivity is not true for floating point.
7735 It can change the value. So don't do it.
7736 -- rms and moshier@world.std.com. */
7737 if (FLOAT_MODE_P (GET_MODE (x)))
7740 /* The outer operation can only be one of the following: */
7741 if (code != IOR && code != AND && code != XOR
7742 && code != PLUS && code != MINUS)
7745 lhs = XEXP (x, 0), rhs = XEXP (x, 1);
7747 /* If either operand is a primitive we can't do anything, so get out
7749 if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
7750 || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
7753 lhs = expand_compound_operation (lhs);
7754 rhs = expand_compound_operation (rhs);
7755 inner_code = GET_CODE (lhs);
7756 if (inner_code != GET_CODE (rhs))
7759 /* See if the inner and outer operations distribute. */
7766 /* These all distribute except over PLUS. */
7767 if (code == PLUS || code == MINUS)
7772 if (code != PLUS && code != MINUS)
7777 /* This is also a multiply, so it distributes over everything. */
7781 /* Non-paradoxical SUBREGs distributes over all operations, provided
7782 the inner modes and word numbers are the same, this is an extraction
7783 of a low-order part, we don't convert an fp operation to int or
7784 vice versa, and we would not be converting a single-word
7785 operation into a multi-word operation. The latter test is not
7786 required, but it prevents generating unneeded multi-word operations.
7787 Some of the previous tests are redundant given the latter test, but
7788 are retained because they are required for correctness.
7790 We produce the result slightly differently in this case. */
7792 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7793 || SUBREG_WORD (lhs) != SUBREG_WORD (rhs)
7794 || ! subreg_lowpart_p (lhs)
7795 || (GET_MODE_CLASS (GET_MODE (lhs))
7796 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
7797 || (GET_MODE_SIZE (GET_MODE (lhs))
7798 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
7799 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
7802 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
7803 SUBREG_REG (lhs), SUBREG_REG (rhs));
7804 return gen_lowpart_for_combine (GET_MODE (x), tem);
7810 /* Set LHS and RHS to the inner operands (A and B in the example
7811 above) and set OTHER to the common operand (C in the example).
7812 These is only one way to do this unless the inner operation is
7814 if (GET_RTX_CLASS (inner_code) == 'c'
7815 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
7816 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
7817 else if (GET_RTX_CLASS (inner_code) == 'c'
7818 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
7819 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
7820 else if (GET_RTX_CLASS (inner_code) == 'c'
7821 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
7822 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
7823 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
7824 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
7828 /* Form the new inner operation, seeing if it simplifies first. */
7829 tem = gen_binary (code, GET_MODE (x), lhs, rhs);
7831 /* There is one exception to the general way of distributing:
7832 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
7833 if (code == XOR && inner_code == IOR)
7836 other = gen_unary (NOT, GET_MODE (x), GET_MODE (x), other);
7839 /* We may be able to continuing distributing the result, so call
7840 ourselves recursively on the inner operation before forming the
7841 outer operation, which we return. */
7842 return gen_binary (inner_code, GET_MODE (x),
7843 apply_distributive_law (tem), other);
7846 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7849 Return an equivalent form, if different from X. Otherwise, return X. If
7850 X is zero, we are to always construct the equivalent form. */
7853 simplify_and_const_int (x, mode, varop, constop)
7855 enum machine_mode mode;
7857 unsigned HOST_WIDE_INT constop;
7859 unsigned HOST_WIDE_INT nonzero;
7862 /* Simplify VAROP knowing that we will be only looking at some of the
7864 varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
7866 /* If VAROP is a CLOBBER, we will fail so return it; if it is a
7867 CONST_INT, we are done. */
7868 if (GET_CODE (varop) == CLOBBER || GET_CODE (varop) == CONST_INT)
7871 /* See what bits may be nonzero in VAROP. Unlike the general case of
7872 a call to nonzero_bits, here we don't care about bits outside
7875 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
7876 nonzero = trunc_int_for_mode (nonzero, mode);
7878 /* Turn off all bits in the constant that are known to already be zero.
7879 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7880 which is tested below. */
7884 /* If we don't have any bits left, return zero. */
7888 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7889 a power of two, we can replace this with a ASHIFT. */
7890 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
7891 && (i = exact_log2 (constop)) >= 0)
7892 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
7894 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7895 or XOR, then try to apply the distributive law. This may eliminate
7896 operations if either branch can be simplified because of the AND.
7897 It may also make some cases more complex, but those cases probably
7898 won't match a pattern either with or without this. */
7900 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
7902 gen_lowpart_for_combine
7904 apply_distributive_law
7905 (gen_binary (GET_CODE (varop), GET_MODE (varop),
7906 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7907 XEXP (varop, 0), constop),
7908 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7909 XEXP (varop, 1), constop))));
7911 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
7912 if we already had one (just check for the simplest cases). */
7913 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
7914 && GET_MODE (XEXP (x, 0)) == mode
7915 && SUBREG_REG (XEXP (x, 0)) == varop)
7916 varop = XEXP (x, 0);
7918 varop = gen_lowpart_for_combine (mode, varop);
7920 /* If we can't make the SUBREG, try to return what we were given. */
7921 if (GET_CODE (varop) == CLOBBER)
7922 return x ? x : varop;
7924 /* If we are only masking insignificant bits, return VAROP. */
7925 if (constop == nonzero)
7928 /* Otherwise, return an AND. See how much, if any, of X we can use. */
7929 else if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
7930 x = gen_binary (AND, mode, varop, GEN_INT (constop));
7934 if (GET_CODE (XEXP (x, 1)) != CONST_INT
7935 || (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) != constop)
7936 SUBST (XEXP (x, 1), GEN_INT (constop));
7938 SUBST (XEXP (x, 0), varop);
7944 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
7945 We don't let nonzero_bits recur into num_sign_bit_copies, because that
7946 is less useful. We can't allow both, because that results in exponential
7947 run time recursion. There is a nullstone testcase that triggered
7948 this. This macro avoids accidental uses of num_sign_bit_copies. */
7949 #define num_sign_bit_copies()
7951 /* Given an expression, X, compute which bits in X can be non-zero.
7952 We don't care about bits outside of those defined in MODE.
7954 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
7955 a shift, AND, or zero_extract, we can do better. */
7957 static unsigned HOST_WIDE_INT
7958 nonzero_bits (x, mode)
7960 enum machine_mode mode;
7962 unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);
7963 unsigned HOST_WIDE_INT inner_nz;
7965 unsigned int mode_width = GET_MODE_BITSIZE (mode);
7968 /* For floating-point values, assume all bits are needed. */
7969 if (FLOAT_MODE_P (GET_MODE (x)) || FLOAT_MODE_P (mode))
7972 /* If X is wider than MODE, use its mode instead. */
7973 if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
7975 mode = GET_MODE (x);
7976 nonzero = GET_MODE_MASK (mode);
7977 mode_width = GET_MODE_BITSIZE (mode);
7980 if (mode_width > HOST_BITS_PER_WIDE_INT)
7981 /* Our only callers in this case look for single bit values. So
7982 just return the mode mask. Those tests will then be false. */
7985 #ifndef WORD_REGISTER_OPERATIONS
7986 /* If MODE is wider than X, but both are a single word for both the host
7987 and target machines, we can compute this from which bits of the
7988 object might be nonzero in its own mode, taking into account the fact
7989 that on many CISC machines, accessing an object in a wider mode
7990 causes the high-order bits to become undefined. So they are
7991 not known to be zero. */
7993 if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode
7994 && GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD
7995 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7996 && GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (GET_MODE (x)))
7998 nonzero &= nonzero_bits (x, GET_MODE (x));
7999 nonzero |= GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x));
8004 code = GET_CODE (x);
8008 #ifdef POINTERS_EXTEND_UNSIGNED
8009 /* If pointers extend unsigned and this is a pointer in Pmode, say that
8010 all the bits above ptr_mode are known to be zero. */
8011 if (POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
8013 nonzero &= GET_MODE_MASK (ptr_mode);
8016 #ifdef STACK_BOUNDARY
8017 /* If this is the stack pointer, we may know something about its
8018 alignment. If PUSH_ROUNDING is defined, it is possible for the
8019 stack to be momentarily aligned only to that amount, so we pick
8020 the least alignment. */
8022 /* We can't check for arg_pointer_rtx here, because it is not
8023 guaranteed to have as much alignment as the stack pointer.
8024 In particular, in the Irix6 n64 ABI, the stack has 128 bit
8025 alignment but the argument pointer has only 64 bit alignment. */
8027 if ((x == frame_pointer_rtx
8028 || x == stack_pointer_rtx
8029 || x == hard_frame_pointer_rtx
8030 || (REGNO (x) >= FIRST_VIRTUAL_REGISTER
8031 && REGNO (x) <= LAST_VIRTUAL_REGISTER))
8037 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
8039 #ifdef PUSH_ROUNDING
8040 if (REGNO (x) == STACK_POINTER_REGNUM && PUSH_ARGS)
8041 sp_alignment = MIN (PUSH_ROUNDING (1), sp_alignment);
8044 /* We must return here, otherwise we may get a worse result from
8045 one of the choices below. There is nothing useful below as
8046 far as the stack pointer is concerned. */
8047 return nonzero &= ~(sp_alignment - 1);
8051 /* If X is a register whose nonzero bits value is current, use it.
8052 Otherwise, if X is a register whose value we can find, use that
8053 value. Otherwise, use the previously-computed global nonzero bits
8054 for this register. */
8056 if (reg_last_set_value[REGNO (x)] != 0
8057 && reg_last_set_mode[REGNO (x)] == mode
8058 && (reg_last_set_label[REGNO (x)] == label_tick
8059 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8060 && REG_N_SETS (REGNO (x)) == 1
8061 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start,
8063 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
8064 return reg_last_set_nonzero_bits[REGNO (x)];
8066 tem = get_last_value (x);
8070 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8071 /* If X is narrower than MODE and TEM is a non-negative
8072 constant that would appear negative in the mode of X,
8073 sign-extend it for use in reg_nonzero_bits because some
8074 machines (maybe most) will actually do the sign-extension
8075 and this is the conservative approach.
8077 ??? For 2.5, try to tighten up the MD files in this regard
8078 instead of this kludge. */
8080 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width
8081 && GET_CODE (tem) == CONST_INT
8083 && 0 != (INTVAL (tem)
8084 & ((HOST_WIDE_INT) 1
8085 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8086 tem = GEN_INT (INTVAL (tem)
8087 | ((HOST_WIDE_INT) (-1)
8088 << GET_MODE_BITSIZE (GET_MODE (x))));
8090 return nonzero_bits (tem, mode);
8092 else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)])
8093 return reg_nonzero_bits[REGNO (x)] & nonzero;
8098 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8099 /* If X is negative in MODE, sign-extend the value. */
8100 if (INTVAL (x) > 0 && mode_width < BITS_PER_WORD
8101 && 0 != (INTVAL (x) & ((HOST_WIDE_INT) 1 << (mode_width - 1))))
8102 return (INTVAL (x) | ((HOST_WIDE_INT) (-1) << mode_width));
8108 #ifdef LOAD_EXTEND_OP
8109 /* In many, if not most, RISC machines, reading a byte from memory
8110 zeros the rest of the register. Noticing that fact saves a lot
8111 of extra zero-extends. */
8112 if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND)
8113 nonzero &= GET_MODE_MASK (GET_MODE (x));
8123 /* If this produces an integer result, we know which bits are set.
8124 Code here used to clear bits outside the mode of X, but that is
8127 if (GET_MODE_CLASS (mode) == MODE_INT
8128 && mode_width <= HOST_BITS_PER_WIDE_INT)
8129 nonzero = STORE_FLAG_VALUE;
8134 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8135 and num_sign_bit_copies. */
8136 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
8137 == GET_MODE_BITSIZE (GET_MODE (x)))
8141 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
8142 nonzero |= (GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x)));
8147 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8148 and num_sign_bit_copies. */
8149 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
8150 == GET_MODE_BITSIZE (GET_MODE (x)))
8156 nonzero &= (nonzero_bits (XEXP (x, 0), mode) & GET_MODE_MASK (mode));
8160 nonzero &= nonzero_bits (XEXP (x, 0), mode);
8161 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
8162 nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
8166 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
8167 Otherwise, show all the bits in the outer mode but not the inner
8169 inner_nz = nonzero_bits (XEXP (x, 0), mode);
8170 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
8172 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
8174 & (((HOST_WIDE_INT) 1
8175 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
8176 inner_nz |= (GET_MODE_MASK (mode)
8177 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
8180 nonzero &= inner_nz;
8184 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
8185 & nonzero_bits (XEXP (x, 1), mode));
8189 case UMIN: case UMAX: case SMIN: case SMAX:
8190 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
8191 | nonzero_bits (XEXP (x, 1), mode));
8194 case PLUS: case MINUS:
8196 case DIV: case UDIV:
8197 case MOD: case UMOD:
8198 /* We can apply the rules of arithmetic to compute the number of
8199 high- and low-order zero bits of these operations. We start by
8200 computing the width (position of the highest-order non-zero bit)
8201 and the number of low-order zero bits for each value. */
8203 unsigned HOST_WIDE_INT nz0 = nonzero_bits (XEXP (x, 0), mode);
8204 unsigned HOST_WIDE_INT nz1 = nonzero_bits (XEXP (x, 1), mode);
8205 int width0 = floor_log2 (nz0) + 1;
8206 int width1 = floor_log2 (nz1) + 1;
8207 int low0 = floor_log2 (nz0 & -nz0);
8208 int low1 = floor_log2 (nz1 & -nz1);
8209 HOST_WIDE_INT op0_maybe_minusp
8210 = (nz0 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
8211 HOST_WIDE_INT op1_maybe_minusp
8212 = (nz1 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
8213 unsigned int result_width = mode_width;
8221 && (XEXP (x, 0) == stack_pointer_rtx
8222 || XEXP (x, 0) == frame_pointer_rtx)
8223 && GET_CODE (XEXP (x, 1)) == CONST_INT)
8225 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
8227 nz0 = (GET_MODE_MASK (mode) & ~(sp_alignment - 1));
8228 nz1 = INTVAL (XEXP (x, 1)) - STACK_BIAS;
8229 width0 = floor_log2 (nz0) + 1;
8230 width1 = floor_log2 (nz1) + 1;
8231 low0 = floor_log2 (nz0 & -nz0);
8232 low1 = floor_log2 (nz1 & -nz1);
8235 result_width = MAX (width0, width1) + 1;
8236 result_low = MIN (low0, low1);
8239 result_low = MIN (low0, low1);
8242 result_width = width0 + width1;
8243 result_low = low0 + low1;
8246 if (! op0_maybe_minusp && ! op1_maybe_minusp)
8247 result_width = width0;
8250 result_width = width0;
8253 if (! op0_maybe_minusp && ! op1_maybe_minusp)
8254 result_width = MIN (width0, width1);
8255 result_low = MIN (low0, low1);
8258 result_width = MIN (width0, width1);
8259 result_low = MIN (low0, low1);
8265 if (result_width < mode_width)
8266 nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1;
8269 nonzero &= ~(((HOST_WIDE_INT) 1 << result_low) - 1);
8274 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8275 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8276 nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1;
8280 /* If this is a SUBREG formed for a promoted variable that has
8281 been zero-extended, we know that at least the high-order bits
8282 are zero, though others might be too. */
8284 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x))
8285 nonzero = (GET_MODE_MASK (GET_MODE (x))
8286 & nonzero_bits (SUBREG_REG (x), GET_MODE (x)));
8288 /* If the inner mode is a single word for both the host and target
8289 machines, we can compute this from which bits of the inner
8290 object might be nonzero. */
8291 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
8292 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8293 <= HOST_BITS_PER_WIDE_INT))
8295 nonzero &= nonzero_bits (SUBREG_REG (x), mode);
8297 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
8298 /* If this is a typical RISC machine, we only have to worry
8299 about the way loads are extended. */
8300 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
8302 & (((unsigned HOST_WIDE_INT) 1
8303 << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) - 1))))
8305 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) != ZERO_EXTEND)
8308 /* On many CISC machines, accessing an object in a wider mode
8309 causes the high-order bits to become undefined. So they are
8310 not known to be zero. */
8311 if (GET_MODE_SIZE (GET_MODE (x))
8312 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8313 nonzero |= (GET_MODE_MASK (GET_MODE (x))
8314 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
8323 /* The nonzero bits are in two classes: any bits within MODE
8324 that aren't in GET_MODE (x) are always significant. The rest of the
8325 nonzero bits are those that are significant in the operand of
8326 the shift when shifted the appropriate number of bits. This
8327 shows that high-order bits are cleared by the right shift and
8328 low-order bits by left shifts. */
8329 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8330 && INTVAL (XEXP (x, 1)) >= 0
8331 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8333 enum machine_mode inner_mode = GET_MODE (x);
8334 unsigned int width = GET_MODE_BITSIZE (inner_mode);
8335 int count = INTVAL (XEXP (x, 1));
8336 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
8337 unsigned HOST_WIDE_INT op_nonzero = nonzero_bits (XEXP (x, 0), mode);
8338 unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask;
8339 unsigned HOST_WIDE_INT outer = 0;
8341 if (mode_width > width)
8342 outer = (op_nonzero & nonzero & ~mode_mask);
8344 if (code == LSHIFTRT)
8346 else if (code == ASHIFTRT)
8350 /* If the sign bit may have been nonzero before the shift, we
8351 need to mark all the places it could have been copied to
8352 by the shift as possibly nonzero. */
8353 if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count)))
8354 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count);
8356 else if (code == ASHIFT)
8359 inner = ((inner << (count % width)
8360 | (inner >> (width - (count % width)))) & mode_mask);
8362 nonzero &= (outer | inner);
8367 /* This is at most the number of bits in the mode. */
8368 nonzero = ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width) + 1)) - 1;
8372 nonzero &= (nonzero_bits (XEXP (x, 1), mode)
8373 | nonzero_bits (XEXP (x, 2), mode));
8383 /* See the macro definition above. */
8384 #undef num_sign_bit_copies
8386 /* Return the number of bits at the high-order end of X that are known to
8387 be equal to the sign bit. X will be used in mode MODE; if MODE is
8388 VOIDmode, X will be used in its own mode. The returned value will always
8389 be between 1 and the number of bits in MODE. */
8392 num_sign_bit_copies (x, mode)
8394 enum machine_mode mode;
8396 enum rtx_code code = GET_CODE (x);
8397 unsigned int bitwidth;
8398 int num0, num1, result;
8399 unsigned HOST_WIDE_INT nonzero;
8402 /* If we weren't given a mode, use the mode of X. If the mode is still
8403 VOIDmode, we don't know anything. Likewise if one of the modes is
8406 if (mode == VOIDmode)
8407 mode = GET_MODE (x);
8409 if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x)))
8412 bitwidth = GET_MODE_BITSIZE (mode);
8414 /* For a smaller object, just ignore the high bits. */
8415 if (bitwidth < GET_MODE_BITSIZE (GET_MODE (x)))
8417 num0 = num_sign_bit_copies (x, GET_MODE (x));
8419 num0 - (int) (GET_MODE_BITSIZE (GET_MODE (x)) - bitwidth));
8422 if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_BITSIZE (GET_MODE (x)))
8424 #ifndef WORD_REGISTER_OPERATIONS
8425 /* If this machine does not do all register operations on the entire
8426 register and MODE is wider than the mode of X, we can say nothing
8427 at all about the high-order bits. */
8430 /* Likewise on machines that do, if the mode of the object is smaller
8431 than a word and loads of that size don't sign extend, we can say
8432 nothing about the high order bits. */
8433 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
8434 #ifdef LOAD_EXTEND_OP
8435 && LOAD_EXTEND_OP (GET_MODE (x)) != SIGN_EXTEND
8446 #ifdef POINTERS_EXTEND_UNSIGNED
8447 /* If pointers extend signed and this is a pointer in Pmode, say that
8448 all the bits above ptr_mode are known to be sign bit copies. */
8449 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode && mode == Pmode
8451 return GET_MODE_BITSIZE (Pmode) - GET_MODE_BITSIZE (ptr_mode) + 1;
8454 if (reg_last_set_value[REGNO (x)] != 0
8455 && reg_last_set_mode[REGNO (x)] == mode
8456 && (reg_last_set_label[REGNO (x)] == label_tick
8457 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8458 && REG_N_SETS (REGNO (x)) == 1
8459 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start,
8461 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
8462 return reg_last_set_sign_bit_copies[REGNO (x)];
8464 tem = get_last_value (x);
8466 return num_sign_bit_copies (tem, mode);
8468 if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0)
8469 return reg_sign_bit_copies[REGNO (x)];
8473 #ifdef LOAD_EXTEND_OP
8474 /* Some RISC machines sign-extend all loads of smaller than a word. */
8475 if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND)
8476 return MAX (1, ((int) bitwidth
8477 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1));
8482 /* If the constant is negative, take its 1's complement and remask.
8483 Then see how many zero bits we have. */
8484 nonzero = INTVAL (x) & GET_MODE_MASK (mode);
8485 if (bitwidth <= HOST_BITS_PER_WIDE_INT
8486 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8487 nonzero = (~nonzero) & GET_MODE_MASK (mode);
8489 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
8492 /* If this is a SUBREG for a promoted object that is sign-extended
8493 and we are looking at it in a wider mode, we know that at least the
8494 high-order bits are known to be sign bit copies. */
8496 if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
8498 num0 = num_sign_bit_copies (SUBREG_REG (x), mode);
8499 return MAX ((int) bitwidth
8500 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1,
8504 /* For a smaller object, just ignore the high bits. */
8505 if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
8507 num0 = num_sign_bit_copies (SUBREG_REG (x), VOIDmode);
8508 return MAX (1, (num0
8509 - (int) (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8513 #ifdef WORD_REGISTER_OPERATIONS
8514 #ifdef LOAD_EXTEND_OP
8515 /* For paradoxical SUBREGs on machines where all register operations
8516 affect the entire register, just look inside. Note that we are
8517 passing MODE to the recursive call, so the number of sign bit copies
8518 will remain relative to that mode, not the inner mode. */
8520 /* This works only if loads sign extend. Otherwise, if we get a
8521 reload for the inner part, it may be loaded from the stack, and
8522 then we lose all sign bit copies that existed before the store
8525 if ((GET_MODE_SIZE (GET_MODE (x))
8526 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8527 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND)
8528 return num_sign_bit_copies (SUBREG_REG (x), mode);
8534 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
8535 return MAX (1, (int) bitwidth - INTVAL (XEXP (x, 1)));
8539 return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8540 + num_sign_bit_copies (XEXP (x, 0), VOIDmode));
8543 /* For a smaller object, just ignore the high bits. */
8544 num0 = num_sign_bit_copies (XEXP (x, 0), VOIDmode);
8545 return MAX (1, (num0 - (int) (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8549 return num_sign_bit_copies (XEXP (x, 0), mode);
8551 case ROTATE: case ROTATERT:
8552 /* If we are rotating left by a number of bits less than the number
8553 of sign bit copies, we can just subtract that amount from the
8555 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8556 && INTVAL (XEXP (x, 1)) >= 0 && INTVAL (XEXP (x, 1)) < bitwidth)
8558 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8559 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
8560 : (int) bitwidth - INTVAL (XEXP (x, 1))));
8565 /* In general, this subtracts one sign bit copy. But if the value
8566 is known to be positive, the number of sign bit copies is the
8567 same as that of the input. Finally, if the input has just one bit
8568 that might be nonzero, all the bits are copies of the sign bit. */
8569 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8570 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8571 return num0 > 1 ? num0 - 1 : 1;
8573 nonzero = nonzero_bits (XEXP (x, 0), mode);
8578 && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero))
8583 case IOR: case AND: case XOR:
8584 case SMIN: case SMAX: case UMIN: case UMAX:
8585 /* Logical operations will preserve the number of sign-bit copies.
8586 MIN and MAX operations always return one of the operands. */
8587 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8588 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8589 return MIN (num0, num1);
8591 case PLUS: case MINUS:
8592 /* For addition and subtraction, we can have a 1-bit carry. However,
8593 if we are subtracting 1 from a positive number, there will not
8594 be such a carry. Furthermore, if the positive number is known to
8595 be 0 or 1, we know the result is either -1 or 0. */
8597 if (code == PLUS && XEXP (x, 1) == constm1_rtx
8598 && bitwidth <= HOST_BITS_PER_WIDE_INT)
8600 nonzero = nonzero_bits (XEXP (x, 0), mode);
8601 if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0)
8602 return (nonzero == 1 || nonzero == 0 ? bitwidth
8603 : bitwidth - floor_log2 (nonzero) - 1);
8606 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8607 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8608 return MAX (1, MIN (num0, num1) - 1);
8611 /* The number of bits of the product is the sum of the number of
8612 bits of both terms. However, unless one of the terms if known
8613 to be positive, we must allow for an additional bit since negating
8614 a negative number can remove one sign bit copy. */
8616 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8617 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8619 result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
8621 && (bitwidth > HOST_BITS_PER_WIDE_INT
8622 || (((nonzero_bits (XEXP (x, 0), mode)
8623 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8624 && ((nonzero_bits (XEXP (x, 1), mode)
8625 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))))
8628 return MAX (1, result);
8631 /* The result must be <= the first operand. If the first operand
8632 has the high bit set, we know nothing about the number of sign
8634 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8636 else if ((nonzero_bits (XEXP (x, 0), mode)
8637 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8640 return num_sign_bit_copies (XEXP (x, 0), mode);
8643 /* The result must be <= the scond operand. */
8644 return num_sign_bit_copies (XEXP (x, 1), mode);
8647 /* Similar to unsigned division, except that we have to worry about
8648 the case where the divisor is negative, in which case we have
8650 result = num_sign_bit_copies (XEXP (x, 0), mode);
8652 && (bitwidth > HOST_BITS_PER_WIDE_INT
8653 || (nonzero_bits (XEXP (x, 1), mode)
8654 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8660 result = num_sign_bit_copies (XEXP (x, 1), mode);
8662 && (bitwidth > HOST_BITS_PER_WIDE_INT
8663 || (nonzero_bits (XEXP (x, 1), mode)
8664 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8670 /* Shifts by a constant add to the number of bits equal to the
8672 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8673 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8674 && INTVAL (XEXP (x, 1)) > 0)
8675 num0 = MIN (bitwidth, num0 + INTVAL (XEXP (x, 1)));
8680 /* Left shifts destroy copies. */
8681 if (GET_CODE (XEXP (x, 1)) != CONST_INT
8682 || INTVAL (XEXP (x, 1)) < 0
8683 || INTVAL (XEXP (x, 1)) >= bitwidth)
8686 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8687 return MAX (1, num0 - INTVAL (XEXP (x, 1)));
8690 num0 = num_sign_bit_copies (XEXP (x, 1), mode);
8691 num1 = num_sign_bit_copies (XEXP (x, 2), mode);
8692 return MIN (num0, num1);
8694 case EQ: case NE: case GE: case GT: case LE: case LT:
8695 case GEU: case GTU: case LEU: case LTU:
8696 if (STORE_FLAG_VALUE == -1)
8704 /* If we haven't been able to figure it out by one of the above rules,
8705 see if some of the high-order bits are known to be zero. If so,
8706 count those bits and return one less than that amount. If we can't
8707 safely compute the mask for this mode, always return BITWIDTH. */
8709 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8712 nonzero = nonzero_bits (x, mode);
8713 return (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))
8714 ? 1 : bitwidth - floor_log2 (nonzero) - 1);
8717 /* Return the number of "extended" bits there are in X, when interpreted
8718 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8719 unsigned quantities, this is the number of high-order zero bits.
8720 For signed quantities, this is the number of copies of the sign bit
8721 minus 1. In both case, this function returns the number of "spare"
8722 bits. For example, if two quantities for which this function returns
8723 at least 1 are added, the addition is known not to overflow.
8725 This function will always return 0 unless called during combine, which
8726 implies that it must be called from a define_split. */
8729 extended_count (x, mode, unsignedp)
8731 enum machine_mode mode;
8734 if (nonzero_sign_valid == 0)
8738 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8739 ? (GET_MODE_BITSIZE (mode) - 1
8740 - floor_log2 (nonzero_bits (x, mode)))
8742 : num_sign_bit_copies (x, mode) - 1);
8745 /* This function is called from `simplify_shift_const' to merge two
8746 outer operations. Specifically, we have already found that we need
8747 to perform operation *POP0 with constant *PCONST0 at the outermost
8748 position. We would now like to also perform OP1 with constant CONST1
8749 (with *POP0 being done last).
8751 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8752 the resulting operation. *PCOMP_P is set to 1 if we would need to
8753 complement the innermost operand, otherwise it is unchanged.
8755 MODE is the mode in which the operation will be done. No bits outside
8756 the width of this mode matter. It is assumed that the width of this mode
8757 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8759 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
8760 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8761 result is simply *PCONST0.
8763 If the resulting operation cannot be expressed as one operation, we
8764 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8767 merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p)
8768 enum rtx_code *pop0;
8769 HOST_WIDE_INT *pconst0;
8771 HOST_WIDE_INT const1;
8772 enum machine_mode mode;
8775 enum rtx_code op0 = *pop0;
8776 HOST_WIDE_INT const0 = *pconst0;
8778 const0 &= GET_MODE_MASK (mode);
8779 const1 &= GET_MODE_MASK (mode);
8781 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8785 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
8788 if (op1 == NIL || op0 == SET)
8791 else if (op0 == NIL)
8792 op0 = op1, const0 = const1;
8794 else if (op0 == op1)
8818 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8819 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8822 /* If the two constants aren't the same, we can't do anything. The
8823 remaining six cases can all be done. */
8824 else if (const0 != const1)
8832 /* (a & b) | b == b */
8834 else /* op1 == XOR */
8835 /* (a ^ b) | b == a | b */
8841 /* (a & b) ^ b == (~a) & b */
8842 op0 = AND, *pcomp_p = 1;
8843 else /* op1 == IOR */
8844 /* (a | b) ^ b == a & ~b */
8845 op0 = AND, *pconst0 = ~const0;
8850 /* (a | b) & b == b */
8852 else /* op1 == XOR */
8853 /* (a ^ b) & b) == (~a) & b */
8860 /* Check for NO-OP cases. */
8861 const0 &= GET_MODE_MASK (mode);
8863 && (op0 == IOR || op0 == XOR || op0 == PLUS))
8865 else if (const0 == 0 && op0 == AND)
8867 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8871 /* ??? Slightly redundant with the above mask, but not entirely.
8872 Moving this above means we'd have to sign-extend the mode mask
8873 for the final test. */
8874 const0 = trunc_int_for_mode (const0, mode);
8882 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8883 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
8884 that we started with.
8886 The shift is normally computed in the widest mode we find in VAROP, as
8887 long as it isn't a different number of words than RESULT_MODE. Exceptions
8888 are ASHIFTRT and ROTATE, which are always done in their original mode, */
8891 simplify_shift_const (x, code, result_mode, varop, input_count)
8894 enum machine_mode result_mode;
8898 enum rtx_code orig_code = code;
8899 int orig_count = input_count;
8902 enum machine_mode mode = result_mode;
8903 enum machine_mode shift_mode, tmode;
8904 unsigned int mode_words
8905 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8906 /* We form (outer_op (code varop count) (outer_const)). */
8907 enum rtx_code outer_op = NIL;
8908 HOST_WIDE_INT outer_const = 0;
8910 int complement_p = 0;
8913 /* If we were given an invalid count, don't do anything except exactly
8914 what was requested. */
8916 if (input_count < 0 || input_count > (int) GET_MODE_BITSIZE (mode))
8921 return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (input_count));
8924 count = input_count;
8926 /* Make sure and truncate the "natural" shift on the way in. We don't
8927 want to do this inside the loop as it makes it more difficult to
8929 #ifdef SHIFT_COUNT_TRUNCATED
8930 if (SHIFT_COUNT_TRUNCATED)
8931 count %= GET_MODE_BITSIZE (mode);
8934 /* Unless one of the branches of the `if' in this loop does a `continue',
8935 we will `break' the loop after the `if'. */
8939 /* If we have an operand of (clobber (const_int 0)), just return that
8941 if (GET_CODE (varop) == CLOBBER)
8944 /* If we discovered we had to complement VAROP, leave. Making a NOT
8945 here would cause an infinite loop. */
8949 /* Convert ROTATERT to ROTATE. */
8950 if (code == ROTATERT)
8951 code = ROTATE, count = GET_MODE_BITSIZE (result_mode) - count;
8953 /* We need to determine what mode we will do the shift in. If the
8954 shift is a right shift or a ROTATE, we must always do it in the mode
8955 it was originally done in. Otherwise, we can do it in MODE, the
8956 widest mode encountered. */
8958 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8959 ? result_mode : mode);
8961 /* Handle cases where the count is greater than the size of the mode
8962 minus 1. For ASHIFT, use the size minus one as the count (this can
8963 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
8964 take the count modulo the size. For other shifts, the result is
8967 Since these shifts are being produced by the compiler by combining
8968 multiple operations, each of which are defined, we know what the
8969 result is supposed to be. */
8971 if (count > GET_MODE_BITSIZE (shift_mode) - 1)
8973 if (code == ASHIFTRT)
8974 count = GET_MODE_BITSIZE (shift_mode) - 1;
8975 else if (code == ROTATE || code == ROTATERT)
8976 count %= GET_MODE_BITSIZE (shift_mode);
8979 /* We can't simply return zero because there may be an
8987 /* An arithmetic right shift of a quantity known to be -1 or 0
8989 if (code == ASHIFTRT
8990 && (num_sign_bit_copies (varop, shift_mode)
8991 == GET_MODE_BITSIZE (shift_mode)))
8997 /* If we are doing an arithmetic right shift and discarding all but
8998 the sign bit copies, this is equivalent to doing a shift by the
8999 bitsize minus one. Convert it into that shift because it will often
9000 allow other simplifications. */
9002 if (code == ASHIFTRT
9003 && (count + num_sign_bit_copies (varop, shift_mode)
9004 >= GET_MODE_BITSIZE (shift_mode)))
9005 count = GET_MODE_BITSIZE (shift_mode) - 1;
9007 /* We simplify the tests below and elsewhere by converting
9008 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9009 `make_compound_operation' will convert it to a ASHIFTRT for
9010 those machines (such as Vax) that don't have a LSHIFTRT. */
9011 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9013 && ((nonzero_bits (varop, shift_mode)
9014 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
9018 switch (GET_CODE (varop))
9024 new = expand_compound_operation (varop);
9033 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9034 minus the width of a smaller mode, we can do this with a
9035 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9036 if ((code == ASHIFTRT || code == LSHIFTRT)
9037 && ! mode_dependent_address_p (XEXP (varop, 0))
9038 && ! MEM_VOLATILE_P (varop)
9039 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9040 MODE_INT, 1)) != BLKmode)
9042 if (BYTES_BIG_ENDIAN)
9043 new = gen_rtx_MEM (tmode, XEXP (varop, 0));
9045 new = gen_rtx_MEM (tmode,
9046 plus_constant (XEXP (varop, 0),
9047 count / BITS_PER_UNIT));
9049 MEM_COPY_ATTRIBUTES (new, varop);
9050 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
9051 : ZERO_EXTEND, mode, new);
9058 /* Similar to the case above, except that we can only do this if
9059 the resulting mode is the same as that of the underlying
9060 MEM and adjust the address depending on the *bits* endianness
9061 because of the way that bit-field extract insns are defined. */
9062 if ((code == ASHIFTRT || code == LSHIFTRT)
9063 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9064 MODE_INT, 1)) != BLKmode
9065 && tmode == GET_MODE (XEXP (varop, 0)))
9067 if (BITS_BIG_ENDIAN)
9068 new = XEXP (varop, 0);
9071 new = copy_rtx (XEXP (varop, 0));
9072 SUBST (XEXP (new, 0),
9073 plus_constant (XEXP (new, 0),
9074 count / BITS_PER_UNIT));
9077 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
9078 : ZERO_EXTEND, mode, new);
9085 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9086 the same number of words as what we've seen so far. Then store
9087 the widest mode in MODE. */
9088 if (subreg_lowpart_p (varop)
9089 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9090 > GET_MODE_SIZE (GET_MODE (varop)))
9091 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9092 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9095 varop = SUBREG_REG (varop);
9096 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
9097 mode = GET_MODE (varop);
9103 /* Some machines use MULT instead of ASHIFT because MULT
9104 is cheaper. But it is still better on those machines to
9105 merge two shifts into one. */
9106 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9107 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9110 = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
9111 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
9117 /* Similar, for when divides are cheaper. */
9118 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9119 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9122 = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
9123 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
9129 /* If we are extracting just the sign bit of an arithmetic right
9130 shift, that shift is not needed. */
9131 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1)
9133 varop = XEXP (varop, 0);
9137 /* ... fall through ... */
9142 /* Here we have two nested shifts. The result is usually the
9143 AND of a new shift with a mask. We compute the result below. */
9144 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9145 && INTVAL (XEXP (varop, 1)) >= 0
9146 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
9147 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9148 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9150 enum rtx_code first_code = GET_CODE (varop);
9151 unsigned int first_count = INTVAL (XEXP (varop, 1));
9152 unsigned HOST_WIDE_INT mask;
9155 /* We have one common special case. We can't do any merging if
9156 the inner code is an ASHIFTRT of a smaller mode. However, if
9157 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9158 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9159 we can convert it to
9160 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9161 This simplifies certain SIGN_EXTEND operations. */
9162 if (code == ASHIFT && first_code == ASHIFTRT
9163 && (GET_MODE_BITSIZE (result_mode)
9164 - GET_MODE_BITSIZE (GET_MODE (varop))) == count)
9166 /* C3 has the low-order C1 bits zero. */
9168 mask = (GET_MODE_MASK (mode)
9169 & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
9171 varop = simplify_and_const_int (NULL_RTX, result_mode,
9172 XEXP (varop, 0), mask);
9173 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
9175 count = first_count;
9180 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9181 than C1 high-order bits equal to the sign bit, we can convert
9182 this to either an ASHIFT or a ASHIFTRT depending on the
9185 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9187 if (code == ASHIFTRT && first_code == ASHIFT
9188 && GET_MODE (varop) == shift_mode
9189 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
9192 varop = XEXP (varop, 0);
9194 signed_count = count - first_count;
9195 if (signed_count < 0)
9196 count = -signed_count, code = ASHIFT;
9198 count = signed_count;
9203 /* There are some cases we can't do. If CODE is ASHIFTRT,
9204 we can only do this if FIRST_CODE is also ASHIFTRT.
9206 We can't do the case when CODE is ROTATE and FIRST_CODE is
9209 If the mode of this shift is not the mode of the outer shift,
9210 we can't do this if either shift is a right shift or ROTATE.
9212 Finally, we can't do any of these if the mode is too wide
9213 unless the codes are the same.
9215 Handle the case where the shift codes are the same
9218 if (code == first_code)
9220 if (GET_MODE (varop) != result_mode
9221 && (code == ASHIFTRT || code == LSHIFTRT
9225 count += first_count;
9226 varop = XEXP (varop, 0);
9230 if (code == ASHIFTRT
9231 || (code == ROTATE && first_code == ASHIFTRT)
9232 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
9233 || (GET_MODE (varop) != result_mode
9234 && (first_code == ASHIFTRT || first_code == LSHIFTRT
9235 || first_code == ROTATE
9236 || code == ROTATE)))
9239 /* To compute the mask to apply after the shift, shift the
9240 nonzero bits of the inner shift the same way the
9241 outer shift will. */
9243 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
9246 = simplify_binary_operation (code, result_mode, mask_rtx,
9249 /* Give up if we can't compute an outer operation to use. */
9251 || GET_CODE (mask_rtx) != CONST_INT
9252 || ! merge_outer_ops (&outer_op, &outer_const, AND,
9254 result_mode, &complement_p))
9257 /* If the shifts are in the same direction, we add the
9258 counts. Otherwise, we subtract them. */
9259 signed_count = count;
9260 if ((code == ASHIFTRT || code == LSHIFTRT)
9261 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
9262 signed_count += first_count;
9264 signed_count -= first_count;
9266 /* If COUNT is positive, the new shift is usually CODE,
9267 except for the two exceptions below, in which case it is
9268 FIRST_CODE. If the count is negative, FIRST_CODE should
9270 if (signed_count > 0
9271 && ((first_code == ROTATE && code == ASHIFT)
9272 || (first_code == ASHIFTRT && code == LSHIFTRT)))
9273 code = first_code, count = signed_count;
9274 else if (signed_count < 0)
9275 code = first_code, count = -signed_count;
9277 count = signed_count;
9279 varop = XEXP (varop, 0);
9283 /* If we have (A << B << C) for any shift, we can convert this to
9284 (A << C << B). This wins if A is a constant. Only try this if
9285 B is not a constant. */
9287 else if (GET_CODE (varop) == code
9288 && GET_CODE (XEXP (varop, 1)) != CONST_INT
9290 = simplify_binary_operation (code, mode,
9294 varop = gen_rtx_combine (code, mode, new, XEXP (varop, 1));
9301 /* Make this fit the case below. */
9302 varop = gen_rtx_combine (XOR, mode, XEXP (varop, 0),
9303 GEN_INT (GET_MODE_MASK (mode)));
9309 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9310 with C the size of VAROP - 1 and the shift is logical if
9311 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9312 we have an (le X 0) operation. If we have an arithmetic shift
9313 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9314 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9316 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
9317 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
9318 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9319 && (code == LSHIFTRT || code == ASHIFTRT)
9320 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
9321 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9324 varop = gen_rtx_combine (LE, GET_MODE (varop), XEXP (varop, 1),
9327 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9328 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
9333 /* If we have (shift (logical)), move the logical to the outside
9334 to allow it to possibly combine with another logical and the
9335 shift to combine with another shift. This also canonicalizes to
9336 what a ZERO_EXTRACT looks like. Also, some machines have
9337 (and (shift)) insns. */
9339 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9340 && (new = simplify_binary_operation (code, result_mode,
9342 GEN_INT (count))) != 0
9343 && GET_CODE (new) == CONST_INT
9344 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
9345 INTVAL (new), result_mode, &complement_p))
9347 varop = XEXP (varop, 0);
9351 /* If we can't do that, try to simplify the shift in each arm of the
9352 logical expression, make a new logical expression, and apply
9353 the inverse distributive law. */
9355 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9356 XEXP (varop, 0), count);
9357 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9358 XEXP (varop, 1), count);
9360 varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs);
9361 varop = apply_distributive_law (varop);
9368 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9369 says that the sign bit can be tested, FOO has mode MODE, C is
9370 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9371 that may be nonzero. */
9372 if (code == LSHIFTRT
9373 && XEXP (varop, 1) == const0_rtx
9374 && GET_MODE (XEXP (varop, 0)) == result_mode
9375 && count == GET_MODE_BITSIZE (result_mode) - 1
9376 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9377 && ((STORE_FLAG_VALUE
9378 & ((HOST_WIDE_INT) 1
9379 < (GET_MODE_BITSIZE (result_mode) - 1))))
9380 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9381 && merge_outer_ops (&outer_op, &outer_const, XOR,
9382 (HOST_WIDE_INT) 1, result_mode,
9385 varop = XEXP (varop, 0);
9392 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9393 than the number of bits in the mode is equivalent to A. */
9394 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
9395 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9397 varop = XEXP (varop, 0);
9402 /* NEG commutes with ASHIFT since it is multiplication. Move the
9403 NEG outside to allow shifts to combine. */
9405 && merge_outer_ops (&outer_op, &outer_const, NEG,
9406 (HOST_WIDE_INT) 0, result_mode,
9409 varop = XEXP (varop, 0);
9415 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9416 is one less than the number of bits in the mode is
9417 equivalent to (xor A 1). */
9418 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
9419 && XEXP (varop, 1) == constm1_rtx
9420 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9421 && merge_outer_ops (&outer_op, &outer_const, XOR,
9422 (HOST_WIDE_INT) 1, result_mode,
9426 varop = XEXP (varop, 0);
9430 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9431 that might be nonzero in BAR are those being shifted out and those
9432 bits are known zero in FOO, we can replace the PLUS with FOO.
9433 Similarly in the other operand order. This code occurs when
9434 we are computing the size of a variable-size array. */
9436 if ((code == ASHIFTRT || code == LSHIFTRT)
9437 && count < HOST_BITS_PER_WIDE_INT
9438 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9439 && (nonzero_bits (XEXP (varop, 1), result_mode)
9440 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9442 varop = XEXP (varop, 0);
9445 else if ((code == ASHIFTRT || code == LSHIFTRT)
9446 && count < HOST_BITS_PER_WIDE_INT
9447 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9448 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9450 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9451 & nonzero_bits (XEXP (varop, 1),
9454 varop = XEXP (varop, 1);
9458 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9460 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9461 && (new = simplify_binary_operation (ASHIFT, result_mode,
9463 GEN_INT (count))) != 0
9464 && GET_CODE (new) == CONST_INT
9465 && merge_outer_ops (&outer_op, &outer_const, PLUS,
9466 INTVAL (new), result_mode, &complement_p))
9468 varop = XEXP (varop, 0);
9474 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9475 with C the size of VAROP - 1 and the shift is logical if
9476 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9477 we have a (gt X 0) operation. If the shift is arithmetic with
9478 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9479 we have a (neg (gt X 0)) operation. */
9481 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9482 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9483 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
9484 && (code == LSHIFTRT || code == ASHIFTRT)
9485 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9486 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
9487 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9490 varop = gen_rtx_combine (GT, GET_MODE (varop), XEXP (varop, 1),
9493 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9494 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
9501 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9502 if the truncate does not affect the value. */
9503 if (code == LSHIFTRT
9504 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9505 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9506 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9507 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9508 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9510 rtx varop_inner = XEXP (varop, 0);
9513 = gen_rtx_combine (LSHIFTRT, GET_MODE (varop_inner),
9514 XEXP (varop_inner, 0),
9516 + INTVAL (XEXP (varop_inner, 1))));
9517 varop = gen_rtx_combine (TRUNCATE, GET_MODE (varop),
9531 /* We need to determine what mode to do the shift in. If the shift is
9532 a right shift or ROTATE, we must always do it in the mode it was
9533 originally done in. Otherwise, we can do it in MODE, the widest mode
9534 encountered. The code we care about is that of the shift that will
9535 actually be done, not the shift that was originally requested. */
9537 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9538 ? result_mode : mode);
9540 /* We have now finished analyzing the shift. The result should be
9541 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9542 OUTER_OP is non-NIL, it is an operation that needs to be applied
9543 to the result of the shift. OUTER_CONST is the relevant constant,
9544 but we must turn off all bits turned off in the shift.
9546 If we were passed a value for X, see if we can use any pieces of
9547 it. If not, make new rtx. */
9549 if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
9550 && GET_CODE (XEXP (x, 1)) == CONST_INT
9551 && INTVAL (XEXP (x, 1)) == count)
9552 const_rtx = XEXP (x, 1);
9554 const_rtx = GEN_INT (count);
9556 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
9557 && GET_MODE (XEXP (x, 0)) == shift_mode
9558 && SUBREG_REG (XEXP (x, 0)) == varop)
9559 varop = XEXP (x, 0);
9560 else if (GET_MODE (varop) != shift_mode)
9561 varop = gen_lowpart_for_combine (shift_mode, varop);
9563 /* If we can't make the SUBREG, try to return what we were given. */
9564 if (GET_CODE (varop) == CLOBBER)
9565 return x ? x : varop;
9567 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
9572 if (x == 0 || GET_CODE (x) != code || GET_MODE (x) != shift_mode)
9573 x = gen_rtx_combine (code, shift_mode, varop, const_rtx);
9575 SUBST (XEXP (x, 0), varop);
9576 SUBST (XEXP (x, 1), const_rtx);
9579 /* If we have an outer operation and we just made a shift, it is
9580 possible that we could have simplified the shift were it not
9581 for the outer operation. So try to do the simplification
9584 if (outer_op != NIL && GET_CODE (x) == code
9585 && GET_CODE (XEXP (x, 1)) == CONST_INT)
9586 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
9587 INTVAL (XEXP (x, 1)));
9589 /* If we were doing a LSHIFTRT in a wider mode than it was originally,
9590 turn off all the bits that the shift would have turned off. */
9591 if (orig_code == LSHIFTRT && result_mode != shift_mode)
9592 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9593 GET_MODE_MASK (result_mode) >> orig_count);
9595 /* Do the remainder of the processing in RESULT_MODE. */
9596 x = gen_lowpart_for_combine (result_mode, x);
9598 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9601 x = gen_unary (NOT, result_mode, result_mode, x);
9603 if (outer_op != NIL)
9605 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9606 outer_const = trunc_int_for_mode (outer_const, result_mode);
9608 if (outer_op == AND)
9609 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9610 else if (outer_op == SET)
9611 /* This means that we have determined that the result is
9612 equivalent to a constant. This should be rare. */
9613 x = GEN_INT (outer_const);
9614 else if (GET_RTX_CLASS (outer_op) == '1')
9615 x = gen_unary (outer_op, result_mode, result_mode, x);
9617 x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
9623 /* Like recog, but we receive the address of a pointer to a new pattern.
9624 We try to match the rtx that the pointer points to.
9625 If that fails, we may try to modify or replace the pattern,
9626 storing the replacement into the same pointer object.
9628 Modifications include deletion or addition of CLOBBERs.
9630 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9631 the CLOBBERs are placed.
9633 The value is the final insn code from the pattern ultimately matched,
9637 recog_for_combine (pnewpat, insn, pnotes)
9642 register rtx pat = *pnewpat;
9643 int insn_code_number;
9644 int num_clobbers_to_add = 0;
9649 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9650 we use to indicate that something didn't match. If we find such a
9651 thing, force rejection. */
9652 if (GET_CODE (pat) == PARALLEL)
9653 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9654 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9655 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9658 /* Remove the old notes prior to trying to recognize the new pattern. */
9659 old_notes = REG_NOTES (insn);
9660 REG_NOTES (insn) = 0;
9662 /* Is the result of combination a valid instruction? */
9663 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9665 /* If it isn't, there is the possibility that we previously had an insn
9666 that clobbered some register as a side effect, but the combined
9667 insn doesn't need to do that. So try once more without the clobbers
9668 unless this represents an ASM insn. */
9670 if (insn_code_number < 0 && ! check_asm_operands (pat)
9671 && GET_CODE (pat) == PARALLEL)
9675 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9676 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9679 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9683 SUBST_INT (XVECLEN (pat, 0), pos);
9686 pat = XVECEXP (pat, 0, 0);
9688 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9691 REG_NOTES (insn) = old_notes;
9693 /* If we had any clobbers to add, make a new pattern than contains
9694 them. Then check to make sure that all of them are dead. */
9695 if (num_clobbers_to_add)
9697 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9698 rtvec_alloc (GET_CODE (pat) == PARALLEL
9700 + num_clobbers_to_add)
9701 : num_clobbers_to_add + 1));
9703 if (GET_CODE (pat) == PARALLEL)
9704 for (i = 0; i < XVECLEN (pat, 0); i++)
9705 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9707 XVECEXP (newpat, 0, 0) = pat;
9709 add_clobbers (newpat, insn_code_number);
9711 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9712 i < XVECLEN (newpat, 0); i++)
9714 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
9715 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9717 notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9718 XEXP (XVECEXP (newpat, 0, i), 0), notes);
9726 return insn_code_number;
9729 /* Like gen_lowpart but for use by combine. In combine it is not possible
9730 to create any new pseudoregs. However, it is safe to create
9731 invalid memory addresses, because combine will try to recognize
9732 them and all they will do is make the combine attempt fail.
9734 If for some reason this cannot do its job, an rtx
9735 (clobber (const_int 0)) is returned.
9736 An insn containing that will not be recognized. */
9741 gen_lowpart_for_combine (mode, x)
9742 enum machine_mode mode;
9747 if (GET_MODE (x) == mode)
9750 /* We can only support MODE being wider than a word if X is a
9751 constant integer or has a mode the same size. */
9753 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
9754 && ! ((GET_MODE (x) == VOIDmode
9755 && (GET_CODE (x) == CONST_INT
9756 || GET_CODE (x) == CONST_DOUBLE))
9757 || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
9758 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9760 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9761 won't know what to do. So we will strip off the SUBREG here and
9762 process normally. */
9763 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
9766 if (GET_MODE (x) == mode)
9770 result = gen_lowpart_common (mode, x);
9771 #ifdef CLASS_CANNOT_CHANGE_MODE
9773 && GET_CODE (result) == SUBREG
9774 && GET_CODE (SUBREG_REG (result)) == REG
9775 && REGNO (SUBREG_REG (result)) >= FIRST_PSEUDO_REGISTER
9776 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (result),
9777 GET_MODE (SUBREG_REG (result))))
9778 REG_CHANGES_MODE (REGNO (SUBREG_REG (result))) = 1;
9784 if (GET_CODE (x) == MEM)
9786 register int offset = 0;
9789 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9791 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9792 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9794 /* If we want to refer to something bigger than the original memref,
9795 generate a perverse subreg instead. That will force a reload
9796 of the original memref X. */
9797 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
9798 return gen_rtx_SUBREG (mode, x, 0);
9800 if (WORDS_BIG_ENDIAN)
9801 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
9802 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
9804 if (BYTES_BIG_ENDIAN)
9806 /* Adjust the address so that the address-after-the-data is
9808 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
9809 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
9811 new = gen_rtx_MEM (mode, plus_constant (XEXP (x, 0), offset));
9812 MEM_COPY_ATTRIBUTES (new, x);
9816 /* If X is a comparison operator, rewrite it in a new mode. This
9817 probably won't match, but may allow further simplifications. */
9818 else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
9819 return gen_rtx_combine (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
9821 /* If we couldn't simplify X any other way, just enclose it in a
9822 SUBREG. Normally, this SUBREG won't match, but some patterns may
9823 include an explicit SUBREG or we may simplify it further in combine. */
9828 if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
9829 word = ((GET_MODE_SIZE (GET_MODE (x))
9830 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
9832 return gen_rtx_SUBREG (mode, x, word);
9836 /* Make an rtx expression. This is a subset of gen_rtx and only supports
9837 expressions of 1, 2, or 3 operands, each of which are rtx expressions.
9839 If the identical expression was previously in the insn (in the undobuf),
9840 it will be returned. Only if it is not found will a new expression
9845 gen_rtx_combine VPARAMS ((enum rtx_code code, enum machine_mode mode, ...))
9847 #ifndef ANSI_PROTOTYPES
9849 enum machine_mode mode;
9861 #ifndef ANSI_PROTOTYPES
9862 code = va_arg (p, enum rtx_code);
9863 mode = va_arg (p, enum machine_mode);
9866 n_args = GET_RTX_LENGTH (code);
9867 fmt = GET_RTX_FORMAT (code);
9869 if (n_args == 0 || n_args > 3)
9872 /* Get each arg and verify that it is supposed to be an expression. */
9873 for (j = 0; j < n_args; j++)
9878 args[j] = va_arg (p, rtx);
9883 /* See if this is in undobuf. Be sure we don't use objects that came
9884 from another insn; this could produce circular rtl structures. */
9886 for (undo = undobuf.undos; undo != undobuf.previous_undos; undo = undo->next)
9888 && GET_CODE (undo->old_contents.r) == code
9889 && GET_MODE (undo->old_contents.r) == mode)
9891 for (j = 0; j < n_args; j++)
9892 if (XEXP (undo->old_contents.r, j) != args[j])
9896 return undo->old_contents.r;
9899 /* Otherwise make a new rtx. We know we have 1, 2, or 3 args.
9900 Use rtx_alloc instead of gen_rtx because it's faster on RISC. */
9901 rt = rtx_alloc (code);
9902 PUT_MODE (rt, mode);
9903 XEXP (rt, 0) = args[0];
9906 XEXP (rt, 1) = args[1];
9908 XEXP (rt, 2) = args[2];
9913 /* These routines make binary and unary operations by first seeing if they
9914 fold; if not, a new expression is allocated. */
9917 gen_binary (code, mode, op0, op1)
9919 enum machine_mode mode;
9925 if (GET_RTX_CLASS (code) == 'c'
9926 && (GET_CODE (op0) == CONST_INT
9927 || (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)))
9928 tem = op0, op0 = op1, op1 = tem;
9930 if (GET_RTX_CLASS (code) == '<')
9932 enum machine_mode op_mode = GET_MODE (op0);
9934 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
9935 just (REL_OP X Y). */
9936 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
9938 op1 = XEXP (op0, 1);
9939 op0 = XEXP (op0, 0);
9940 op_mode = GET_MODE (op0);
9943 if (op_mode == VOIDmode)
9944 op_mode = GET_MODE (op1);
9945 result = simplify_relational_operation (code, op_mode, op0, op1);
9948 result = simplify_binary_operation (code, mode, op0, op1);
9953 /* Put complex operands first and constants second. */
9954 if (GET_RTX_CLASS (code) == 'c'
9955 && ((CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
9956 || (GET_RTX_CLASS (GET_CODE (op0)) == 'o'
9957 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')
9958 || (GET_CODE (op0) == SUBREG
9959 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (op0))) == 'o'
9960 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')))
9961 return gen_rtx_combine (code, mode, op1, op0);
9963 /* If we are turning off bits already known off in OP0, we need not do
9965 else if (code == AND && GET_CODE (op1) == CONST_INT
9966 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9967 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
9970 return gen_rtx_combine (code, mode, op0, op1);
9974 gen_unary (code, mode, op0_mode, op0)
9976 enum machine_mode mode, op0_mode;
9979 rtx result = simplify_unary_operation (code, mode, op0, op0_mode);
9984 return gen_rtx_combine (code, mode, op0);
9987 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9988 comparison code that will be tested.
9990 The result is a possibly different comparison code to use. *POP0 and
9991 *POP1 may be updated.
9993 It is possible that we might detect that a comparison is either always
9994 true or always false. However, we do not perform general constant
9995 folding in combine, so this knowledge isn't useful. Such tautologies
9996 should have been detected earlier. Hence we ignore all such cases. */
9998 static enum rtx_code
9999 simplify_comparison (code, pop0, pop1)
10000 enum rtx_code code;
10008 enum machine_mode mode, tmode;
10010 /* Try a few ways of applying the same transformation to both operands. */
10013 #ifndef WORD_REGISTER_OPERATIONS
10014 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10015 so check specially. */
10016 if (code != GTU && code != GEU && code != LTU && code != LEU
10017 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
10018 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10019 && GET_CODE (XEXP (op1, 0)) == ASHIFT
10020 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
10021 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
10022 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
10023 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
10024 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10025 && GET_CODE (XEXP (op1, 1)) == CONST_INT
10026 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10027 && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT
10028 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (op1, 1))
10029 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op0, 0), 1))
10030 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op1, 0), 1))
10031 && (INTVAL (XEXP (op0, 1))
10032 == (GET_MODE_BITSIZE (GET_MODE (op0))
10033 - (GET_MODE_BITSIZE
10034 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
10036 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
10037 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
10041 /* If both operands are the same constant shift, see if we can ignore the
10042 shift. We can if the shift is a rotate or if the bits shifted out of
10043 this shift are known to be zero for both inputs and if the type of
10044 comparison is compatible with the shift. */
10045 if (GET_CODE (op0) == GET_CODE (op1)
10046 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10047 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
10048 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
10049 && (code != GT && code != LT && code != GE && code != LE))
10050 || (GET_CODE (op0) == ASHIFTRT
10051 && (code != GTU && code != LTU
10052 && code != GEU && code != GEU)))
10053 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10054 && INTVAL (XEXP (op0, 1)) >= 0
10055 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10056 && XEXP (op0, 1) == XEXP (op1, 1))
10058 enum machine_mode mode = GET_MODE (op0);
10059 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10060 int shift_count = INTVAL (XEXP (op0, 1));
10062 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
10063 mask &= (mask >> shift_count) << shift_count;
10064 else if (GET_CODE (op0) == ASHIFT)
10065 mask = (mask & (mask << shift_count)) >> shift_count;
10067 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
10068 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
10069 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
10074 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10075 SUBREGs are of the same mode, and, in both cases, the AND would
10076 be redundant if the comparison was done in the narrower mode,
10077 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10078 and the operand's possibly nonzero bits are 0xffffff01; in that case
10079 if we only care about QImode, we don't need the AND). This case
10080 occurs if the output mode of an scc insn is not SImode and
10081 STORE_FLAG_VALUE == 1 (e.g., the 386).
10083 Similarly, check for a case where the AND's are ZERO_EXTEND
10084 operations from some narrower mode even though a SUBREG is not
10087 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
10088 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10089 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
10091 rtx inner_op0 = XEXP (op0, 0);
10092 rtx inner_op1 = XEXP (op1, 0);
10093 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
10094 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
10097 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
10098 && (GET_MODE_SIZE (GET_MODE (inner_op0))
10099 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
10100 && (GET_MODE (SUBREG_REG (inner_op0))
10101 == GET_MODE (SUBREG_REG (inner_op1)))
10102 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
10103 <= HOST_BITS_PER_WIDE_INT)
10104 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
10105 GET_MODE (SUBREG_REG (inner_op0)))))
10106 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
10107 GET_MODE (SUBREG_REG (inner_op1))))))
10109 op0 = SUBREG_REG (inner_op0);
10110 op1 = SUBREG_REG (inner_op1);
10112 /* The resulting comparison is always unsigned since we masked
10113 off the original sign bit. */
10114 code = unsigned_condition (code);
10120 for (tmode = GET_CLASS_NARROWEST_MODE
10121 (GET_MODE_CLASS (GET_MODE (op0)));
10122 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
10123 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
10125 op0 = gen_lowpart_for_combine (tmode, inner_op0);
10126 op1 = gen_lowpart_for_combine (tmode, inner_op1);
10127 code = unsigned_condition (code);
10136 /* If both operands are NOT, we can strip off the outer operation
10137 and adjust the comparison code for swapped operands; similarly for
10138 NEG, except that this must be an equality comparison. */
10139 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
10140 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
10141 && (code == EQ || code == NE)))
10142 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
10148 /* If the first operand is a constant, swap the operands and adjust the
10149 comparison code appropriately, but don't do this if the second operand
10150 is already a constant integer. */
10151 if (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
10153 tem = op0, op0 = op1, op1 = tem;
10154 code = swap_condition (code);
10157 /* We now enter a loop during which we will try to simplify the comparison.
10158 For the most part, we only are concerned with comparisons with zero,
10159 but some things may really be comparisons with zero but not start
10160 out looking that way. */
10162 while (GET_CODE (op1) == CONST_INT)
10164 enum machine_mode mode = GET_MODE (op0);
10165 unsigned int mode_width = GET_MODE_BITSIZE (mode);
10166 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10167 int equality_comparison_p;
10168 int sign_bit_comparison_p;
10169 int unsigned_comparison_p;
10170 HOST_WIDE_INT const_op;
10172 /* We only want to handle integral modes. This catches VOIDmode,
10173 CCmode, and the floating-point modes. An exception is that we
10174 can handle VOIDmode if OP0 is a COMPARE or a comparison
10177 if (GET_MODE_CLASS (mode) != MODE_INT
10178 && ! (mode == VOIDmode
10179 && (GET_CODE (op0) == COMPARE
10180 || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
10183 /* Get the constant we are comparing against and turn off all bits
10184 not on in our mode. */
10185 const_op = trunc_int_for_mode (INTVAL (op1), mode);
10187 /* If we are comparing against a constant power of two and the value
10188 being compared can only have that single bit nonzero (e.g., it was
10189 `and'ed with that bit), we can replace this with a comparison
10192 && (code == EQ || code == NE || code == GE || code == GEU
10193 || code == LT || code == LTU)
10194 && mode_width <= HOST_BITS_PER_WIDE_INT
10195 && exact_log2 (const_op) >= 0
10196 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
10198 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10199 op1 = const0_rtx, const_op = 0;
10202 /* Similarly, if we are comparing a value known to be either -1 or
10203 0 with -1, change it to the opposite comparison against zero. */
10206 && (code == EQ || code == NE || code == GT || code == LE
10207 || code == GEU || code == LTU)
10208 && num_sign_bit_copies (op0, mode) == mode_width)
10210 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10211 op1 = const0_rtx, const_op = 0;
10214 /* Do some canonicalizations based on the comparison code. We prefer
10215 comparisons against zero and then prefer equality comparisons.
10216 If we can reduce the size of a constant, we will do that too. */
10221 /* < C is equivalent to <= (C - 1) */
10225 op1 = GEN_INT (const_op);
10227 /* ... fall through to LE case below. */
10233 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10237 op1 = GEN_INT (const_op);
10241 /* If we are doing a <= 0 comparison on a value known to have
10242 a zero sign bit, we can replace this with == 0. */
10243 else if (const_op == 0
10244 && mode_width <= HOST_BITS_PER_WIDE_INT
10245 && (nonzero_bits (op0, mode)
10246 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10251 /* >= C is equivalent to > (C - 1). */
10255 op1 = GEN_INT (const_op);
10257 /* ... fall through to GT below. */
10263 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10267 op1 = GEN_INT (const_op);
10271 /* If we are doing a > 0 comparison on a value known to have
10272 a zero sign bit, we can replace this with != 0. */
10273 else if (const_op == 0
10274 && mode_width <= HOST_BITS_PER_WIDE_INT
10275 && (nonzero_bits (op0, mode)
10276 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10281 /* < C is equivalent to <= (C - 1). */
10285 op1 = GEN_INT (const_op);
10287 /* ... fall through ... */
10290 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10291 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10292 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10294 const_op = 0, op1 = const0_rtx;
10302 /* unsigned <= 0 is equivalent to == 0 */
10306 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10307 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10308 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10310 const_op = 0, op1 = const0_rtx;
10316 /* >= C is equivalent to < (C - 1). */
10320 op1 = GEN_INT (const_op);
10322 /* ... fall through ... */
10325 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10326 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10327 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10329 const_op = 0, op1 = const0_rtx;
10337 /* unsigned > 0 is equivalent to != 0 */
10341 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10342 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10343 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10345 const_op = 0, op1 = const0_rtx;
10354 /* Compute some predicates to simplify code below. */
10356 equality_comparison_p = (code == EQ || code == NE);
10357 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
10358 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
10361 /* If this is a sign bit comparison and we can do arithmetic in
10362 MODE, say that we will only be needing the sign bit of OP0. */
10363 if (sign_bit_comparison_p
10364 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10365 op0 = force_to_mode (op0, mode,
10367 << (GET_MODE_BITSIZE (mode) - 1)),
10370 /* Now try cases based on the opcode of OP0. If none of the cases
10371 does a "continue", we exit this loop immediately after the
10374 switch (GET_CODE (op0))
10377 /* If we are extracting a single bit from a variable position in
10378 a constant that has only a single bit set and are comparing it
10379 with zero, we can convert this into an equality comparison
10380 between the position and the location of the single bit. */
10382 if (GET_CODE (XEXP (op0, 0)) == CONST_INT
10383 && XEXP (op0, 1) == const1_rtx
10384 && equality_comparison_p && const_op == 0
10385 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
10387 if (BITS_BIG_ENDIAN)
10390 mode = insn_data[(int) CODE_FOR_extzv].operand[1].mode;
10391 if (mode == VOIDmode)
10393 i = (GET_MODE_BITSIZE (mode) - 1 - i);
10395 i = BITS_PER_WORD - 1 - i;
10399 op0 = XEXP (op0, 2);
10403 /* Result is nonzero iff shift count is equal to I. */
10404 code = reverse_condition (code);
10408 /* ... fall through ... */
10411 tem = expand_compound_operation (op0);
10420 /* If testing for equality, we can take the NOT of the constant. */
10421 if (equality_comparison_p
10422 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
10424 op0 = XEXP (op0, 0);
10429 /* If just looking at the sign bit, reverse the sense of the
10431 if (sign_bit_comparison_p)
10433 op0 = XEXP (op0, 0);
10434 code = (code == GE ? LT : GE);
10440 /* If testing for equality, we can take the NEG of the constant. */
10441 if (equality_comparison_p
10442 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
10444 op0 = XEXP (op0, 0);
10449 /* The remaining cases only apply to comparisons with zero. */
10453 /* When X is ABS or is known positive,
10454 (neg X) is < 0 if and only if X != 0. */
10456 if (sign_bit_comparison_p
10457 && (GET_CODE (XEXP (op0, 0)) == ABS
10458 || (mode_width <= HOST_BITS_PER_WIDE_INT
10459 && (nonzero_bits (XEXP (op0, 0), mode)
10460 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
10462 op0 = XEXP (op0, 0);
10463 code = (code == LT ? NE : EQ);
10467 /* If we have NEG of something whose two high-order bits are the
10468 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10469 if (num_sign_bit_copies (op0, mode) >= 2)
10471 op0 = XEXP (op0, 0);
10472 code = swap_condition (code);
10478 /* If we are testing equality and our count is a constant, we
10479 can perform the inverse operation on our RHS. */
10480 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10481 && (tem = simplify_binary_operation (ROTATERT, mode,
10482 op1, XEXP (op0, 1))) != 0)
10484 op0 = XEXP (op0, 0);
10489 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10490 a particular bit. Convert it to an AND of a constant of that
10491 bit. This will be converted into a ZERO_EXTRACT. */
10492 if (const_op == 0 && sign_bit_comparison_p
10493 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10494 && mode_width <= HOST_BITS_PER_WIDE_INT)
10496 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10499 - INTVAL (XEXP (op0, 1)))));
10500 code = (code == LT ? NE : EQ);
10504 /* Fall through. */
10507 /* ABS is ignorable inside an equality comparison with zero. */
10508 if (const_op == 0 && equality_comparison_p)
10510 op0 = XEXP (op0, 0);
10516 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10517 to (compare FOO CONST) if CONST fits in FOO's mode and we
10518 are either testing inequality or have an unsigned comparison
10519 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10520 if (! unsigned_comparison_p
10521 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10522 <= HOST_BITS_PER_WIDE_INT)
10523 && ((unsigned HOST_WIDE_INT) const_op
10524 < (((unsigned HOST_WIDE_INT) 1
10525 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
10527 op0 = XEXP (op0, 0);
10533 /* Check for the case where we are comparing A - C1 with C2,
10534 both constants are smaller than 1/2 the maximum positive
10535 value in MODE, and the comparison is equality or unsigned.
10536 In that case, if A is either zero-extended to MODE or has
10537 sufficient sign bits so that the high-order bit in MODE
10538 is a copy of the sign in the inner mode, we can prove that it is
10539 safe to do the operation in the wider mode. This simplifies
10540 many range checks. */
10542 if (mode_width <= HOST_BITS_PER_WIDE_INT
10543 && subreg_lowpart_p (op0)
10544 && GET_CODE (SUBREG_REG (op0)) == PLUS
10545 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
10546 && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
10547 && (-INTVAL (XEXP (SUBREG_REG (op0), 1))
10548 < (HOST_WIDE_INT) (GET_MODE_MASK (mode) / 2))
10549 && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2
10550 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0),
10551 GET_MODE (SUBREG_REG (op0)))
10552 & ~GET_MODE_MASK (mode))
10553 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
10554 GET_MODE (SUBREG_REG (op0)))
10555 > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10556 - GET_MODE_BITSIZE (mode)))))
10558 op0 = SUBREG_REG (op0);
10562 /* If the inner mode is narrower and we are extracting the low part,
10563 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10564 if (subreg_lowpart_p (op0)
10565 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10566 /* Fall through */ ;
10570 /* ... fall through ... */
10573 if ((unsigned_comparison_p || equality_comparison_p)
10574 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10575 <= HOST_BITS_PER_WIDE_INT)
10576 && ((unsigned HOST_WIDE_INT) const_op
10577 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
10579 op0 = XEXP (op0, 0);
10585 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10586 this for equality comparisons due to pathological cases involving
10588 if (equality_comparison_p
10589 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10590 op1, XEXP (op0, 1))))
10592 op0 = XEXP (op0, 0);
10597 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10598 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10599 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10601 op0 = XEXP (XEXP (op0, 0), 0);
10602 code = (code == LT ? EQ : NE);
10608 /* We used to optimize signed comparisons against zero, but that
10609 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10610 arrive here as equality comparisons, or (GEU, LTU) are
10611 optimized away. No need to special-case them. */
10613 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10614 (eq B (minus A C)), whichever simplifies. We can only do
10615 this for equality comparisons due to pathological cases involving
10617 if (equality_comparison_p
10618 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10619 XEXP (op0, 1), op1)))
10621 op0 = XEXP (op0, 0);
10626 if (equality_comparison_p
10627 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10628 XEXP (op0, 0), op1)))
10630 op0 = XEXP (op0, 1);
10635 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10636 of bits in X minus 1, is one iff X > 0. */
10637 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10638 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10639 && INTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
10640 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10642 op0 = XEXP (op0, 1);
10643 code = (code == GE ? LE : GT);
10649 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10650 if C is zero or B is a constant. */
10651 if (equality_comparison_p
10652 && 0 != (tem = simplify_binary_operation (XOR, mode,
10653 XEXP (op0, 1), op1)))
10655 op0 = XEXP (op0, 0);
10662 case LT: case LTU: case LE: case LEU:
10663 case GT: case GTU: case GE: case GEU:
10664 /* We can't do anything if OP0 is a condition code value, rather
10665 than an actual data value. */
10668 || XEXP (op0, 0) == cc0_rtx
10670 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10673 /* Get the two operands being compared. */
10674 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10675 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10677 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10679 /* Check for the cases where we simply want the result of the
10680 earlier test or the opposite of that result. */
10682 || (code == EQ && reversible_comparison_p (op0))
10683 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10684 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10685 && (STORE_FLAG_VALUE
10686 & (((HOST_WIDE_INT) 1
10687 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10689 || (code == GE && reversible_comparison_p (op0)))))
10691 code = (code == LT || code == NE
10692 ? GET_CODE (op0) : reverse_condition (GET_CODE (op0)));
10693 op0 = tem, op1 = tem1;
10699 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
10701 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10702 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10703 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10705 op0 = XEXP (op0, 1);
10706 code = (code == GE ? GT : LE);
10712 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10713 will be converted to a ZERO_EXTRACT later. */
10714 if (const_op == 0 && equality_comparison_p
10715 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10716 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10718 op0 = simplify_and_const_int
10719 (op0, mode, gen_rtx_combine (LSHIFTRT, mode,
10721 XEXP (XEXP (op0, 0), 1)),
10722 (HOST_WIDE_INT) 1);
10726 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10727 zero and X is a comparison and C1 and C2 describe only bits set
10728 in STORE_FLAG_VALUE, we can compare with X. */
10729 if (const_op == 0 && equality_comparison_p
10730 && mode_width <= HOST_BITS_PER_WIDE_INT
10731 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10732 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10733 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10734 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10735 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10737 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10738 << INTVAL (XEXP (XEXP (op0, 0), 1)));
10739 if ((~STORE_FLAG_VALUE & mask) == 0
10740 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
10741 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10742 && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
10744 op0 = XEXP (XEXP (op0, 0), 0);
10749 /* If we are doing an equality comparison of an AND of a bit equal
10750 to the sign bit, replace this with a LT or GE comparison of
10751 the underlying value. */
10752 if (equality_comparison_p
10754 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10755 && mode_width <= HOST_BITS_PER_WIDE_INT
10756 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10757 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10759 op0 = XEXP (op0, 0);
10760 code = (code == EQ ? GE : LT);
10764 /* If this AND operation is really a ZERO_EXTEND from a narrower
10765 mode, the constant fits within that mode, and this is either an
10766 equality or unsigned comparison, try to do this comparison in
10767 the narrower mode. */
10768 if ((equality_comparison_p || unsigned_comparison_p)
10769 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10770 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10771 & GET_MODE_MASK (mode))
10773 && const_op >> i == 0
10774 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
10776 op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
10780 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1 fits
10781 in both M1 and M2 and the SUBREG is either paradoxical or
10782 represents the low part, permute the SUBREG and the AND and
10784 if (GET_CODE (XEXP (op0, 0)) == SUBREG
10786 #ifdef WORD_REGISTER_OPERATIONS
10788 > (GET_MODE_BITSIZE
10789 (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10790 && mode_width <= BITS_PER_WORD)
10793 <= (GET_MODE_BITSIZE
10794 (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10795 && subreg_lowpart_p (XEXP (op0, 0))))
10796 #ifndef WORD_REGISTER_OPERATIONS
10797 /* It is unsafe to commute the AND into the SUBREG if the SUBREG
10798 is paradoxical and WORD_REGISTER_OPERATIONS is not defined.
10799 As originally written the upper bits have a defined value
10800 due to the AND operation. However, if we commute the AND
10801 inside the SUBREG then they no longer have defined values
10802 and the meaning of the code has been changed. */
10803 && (GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)))
10804 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0)))))
10806 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10807 && mode_width <= HOST_BITS_PER_WIDE_INT
10808 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
10809 <= HOST_BITS_PER_WIDE_INT)
10810 && (INTVAL (XEXP (op0, 1)) & ~mask) == 0
10811 && 0 == (~GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
10812 & INTVAL (XEXP (op0, 1)))
10813 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1)) != mask
10814 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10815 != GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10819 = gen_lowpart_for_combine
10821 gen_binary (AND, GET_MODE (SUBREG_REG (XEXP (op0, 0))),
10822 SUBREG_REG (XEXP (op0, 0)), XEXP (op0, 1)));
10826 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10827 (eq (and (lshiftrt X) 1) 0). */
10828 if (const_op == 0 && equality_comparison_p
10829 && XEXP (op0, 1) == const1_rtx
10830 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10831 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == NOT)
10833 op0 = simplify_and_const_int
10834 (op0, mode, gen_rtx_combine (LSHIFTRT, mode,
10835 XEXP (XEXP (XEXP (op0, 0), 0), 0),
10836 XEXP (XEXP (op0, 0), 1)),
10837 (HOST_WIDE_INT) 1);
10838 code = (code == NE ? EQ : NE);
10844 /* If we have (compare (ashift FOO N) (const_int C)) and
10845 the high order N bits of FOO (N+1 if an inequality comparison)
10846 are known to be zero, we can do this by comparing FOO with C
10847 shifted right N bits so long as the low-order N bits of C are
10849 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10850 && INTVAL (XEXP (op0, 1)) >= 0
10851 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10852 < HOST_BITS_PER_WIDE_INT)
10854 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10855 && mode_width <= HOST_BITS_PER_WIDE_INT
10856 && (nonzero_bits (XEXP (op0, 0), mode)
10857 & ~(mask >> (INTVAL (XEXP (op0, 1))
10858 + ! equality_comparison_p))) == 0)
10860 /* We must perform a logical shift, not an arithmetic one,
10861 as we want the top N bits of C to be zero. */
10862 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
10864 temp >>= INTVAL (XEXP (op0, 1));
10865 op1 = GEN_INT (trunc_int_for_mode (temp, mode));
10866 op0 = XEXP (op0, 0);
10870 /* If we are doing a sign bit comparison, it means we are testing
10871 a particular bit. Convert it to the appropriate AND. */
10872 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10873 && mode_width <= HOST_BITS_PER_WIDE_INT)
10875 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10878 - INTVAL (XEXP (op0, 1)))));
10879 code = (code == LT ? NE : EQ);
10883 /* If this an equality comparison with zero and we are shifting
10884 the low bit to the sign bit, we can convert this to an AND of the
10886 if (const_op == 0 && equality_comparison_p
10887 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10888 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
10890 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10891 (HOST_WIDE_INT) 1);
10897 /* If this is an equality comparison with zero, we can do this
10898 as a logical shift, which might be much simpler. */
10899 if (equality_comparison_p && const_op == 0
10900 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10902 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10904 INTVAL (XEXP (op0, 1)));
10908 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10909 do the comparison in a narrower mode. */
10910 if (! unsigned_comparison_p
10911 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10912 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10913 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10914 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10915 MODE_INT, 1)) != BLKmode
10916 && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode)
10917 || ((unsigned HOST_WIDE_INT) -const_op
10918 <= GET_MODE_MASK (tmode))))
10920 op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
10924 /* Likewise if OP0 is a PLUS of a sign extension with a
10925 constant, which is usually represented with the PLUS
10926 between the shifts. */
10927 if (! unsigned_comparison_p
10928 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10929 && GET_CODE (XEXP (op0, 0)) == PLUS
10930 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10931 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
10932 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
10933 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10934 MODE_INT, 1)) != BLKmode
10935 && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode)
10936 || ((unsigned HOST_WIDE_INT) -const_op
10937 <= GET_MODE_MASK (tmode))))
10939 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
10940 rtx add_const = XEXP (XEXP (op0, 0), 1);
10941 rtx new_const = gen_binary (ASHIFTRT, GET_MODE (op0), add_const,
10944 op0 = gen_binary (PLUS, tmode,
10945 gen_lowpart_for_combine (tmode, inner),
10950 /* ... fall through ... */
10952 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10953 the low order N bits of FOO are known to be zero, we can do this
10954 by comparing FOO with C shifted left N bits so long as no
10955 overflow occurs. */
10956 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10957 && INTVAL (XEXP (op0, 1)) >= 0
10958 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10959 && mode_width <= HOST_BITS_PER_WIDE_INT
10960 && (nonzero_bits (XEXP (op0, 0), mode)
10961 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
10963 || (floor_log2 (const_op) + INTVAL (XEXP (op0, 1))
10966 const_op <<= INTVAL (XEXP (op0, 1));
10967 op1 = GEN_INT (const_op);
10968 op0 = XEXP (op0, 0);
10972 /* If we are using this shift to extract just the sign bit, we
10973 can replace this with an LT or GE comparison. */
10975 && (equality_comparison_p || sign_bit_comparison_p)
10976 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10977 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
10979 op0 = XEXP (op0, 0);
10980 code = (code == NE || code == GT ? LT : GE);
10992 /* Now make any compound operations involved in this comparison. Then,
10993 check for an outmost SUBREG on OP0 that is not doing anything or is
10994 paradoxical. The latter case can only occur when it is known that the
10995 "extra" bits will be zero. Therefore, it is safe to remove the SUBREG.
10996 We can never remove a SUBREG for a non-equality comparison because the
10997 sign bit is in a different place in the underlying object. */
10999 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
11000 op1 = make_compound_operation (op1, SET);
11002 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
11003 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11004 && (code == NE || code == EQ)
11005 && ((GET_MODE_SIZE (GET_MODE (op0))
11006 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))))
11008 op0 = SUBREG_REG (op0);
11009 op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
11012 else if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
11013 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11014 && (code == NE || code == EQ)
11015 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
11016 <= HOST_BITS_PER_WIDE_INT)
11017 && (nonzero_bits (SUBREG_REG (op0), GET_MODE (SUBREG_REG (op0)))
11018 & ~GET_MODE_MASK (GET_MODE (op0))) == 0
11019 && (tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)),
11021 (nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
11022 & ~GET_MODE_MASK (GET_MODE (op0))) == 0))
11023 op0 = SUBREG_REG (op0), op1 = tem;
11025 /* We now do the opposite procedure: Some machines don't have compare
11026 insns in all modes. If OP0's mode is an integer mode smaller than a
11027 word and we can't do a compare in that mode, see if there is a larger
11028 mode for which we can do the compare. There are a number of cases in
11029 which we can use the wider mode. */
11031 mode = GET_MODE (op0);
11032 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11033 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
11034 && cmp_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
11035 for (tmode = GET_MODE_WIDER_MODE (mode);
11037 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
11038 tmode = GET_MODE_WIDER_MODE (tmode))
11039 if (cmp_optab->handlers[(int) tmode].insn_code != CODE_FOR_nothing)
11041 /* If the only nonzero bits in OP0 and OP1 are those in the
11042 narrower mode and this is an equality or unsigned comparison,
11043 we can use the wider mode. Similarly for sign-extended
11044 values, in which case it is true for all comparisons. */
11045 if (((code == EQ || code == NE
11046 || code == GEU || code == GTU || code == LEU || code == LTU)
11047 && (nonzero_bits (op0, tmode) & ~GET_MODE_MASK (mode)) == 0
11048 && (nonzero_bits (op1, tmode) & ~GET_MODE_MASK (mode)) == 0)
11049 || ((num_sign_bit_copies (op0, tmode)
11050 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))
11051 && (num_sign_bit_copies (op1, tmode)
11052 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))))
11054 /* If OP0 is an AND and we don't have an AND in MODE either,
11055 make a new AND in the proper mode. */
11056 if (GET_CODE (op0) == AND
11057 && (add_optab->handlers[(int) mode].insn_code
11058 == CODE_FOR_nothing))
11059 op0 = gen_binary (AND, tmode,
11060 gen_lowpart_for_combine (tmode,
11062 gen_lowpart_for_combine (tmode,
11065 op0 = gen_lowpart_for_combine (tmode, op0);
11066 op1 = gen_lowpart_for_combine (tmode, op1);
11070 /* If this is a test for negative, we can make an explicit
11071 test of the sign bit. */
11073 if (op1 == const0_rtx && (code == LT || code == GE)
11074 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11076 op0 = gen_binary (AND, tmode,
11077 gen_lowpart_for_combine (tmode, op0),
11078 GEN_INT ((HOST_WIDE_INT) 1
11079 << (GET_MODE_BITSIZE (mode) - 1)));
11080 code = (code == LT) ? NE : EQ;
11085 #ifdef CANONICALIZE_COMPARISON
11086 /* If this machine only supports a subset of valid comparisons, see if we
11087 can convert an unsupported one into a supported one. */
11088 CANONICALIZE_COMPARISON (code, op0, op1);
11097 /* Return 1 if we know that X, a comparison operation, is not operating
11098 on a floating-point value or is EQ or NE, meaning that we can safely
11102 reversible_comparison_p (x)
11105 if (TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
11107 || GET_CODE (x) == NE || GET_CODE (x) == EQ
11108 || GET_CODE (x) == UNORDERED || GET_CODE (x) == ORDERED)
11111 switch (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))))
11114 case MODE_PARTIAL_INT:
11115 case MODE_COMPLEX_INT:
11119 /* If the mode of the condition codes tells us that this is safe,
11120 we need look no further. */
11121 if (REVERSIBLE_CC_MODE (GET_MODE (XEXP (x, 0))))
11124 /* Otherwise try and find where the condition codes were last set and
11126 x = get_last_value (XEXP (x, 0));
11127 return (x && GET_CODE (x) == COMPARE
11128 && ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0))));
11135 /* Utility function for following routine. Called when X is part of a value
11136 being stored into reg_last_set_value. Sets reg_last_set_table_tick
11137 for each register mentioned. Similar to mention_regs in cse.c */
11140 update_table_tick (x)
11143 register enum rtx_code code = GET_CODE (x);
11144 register const char *fmt = GET_RTX_FORMAT (code);
11149 unsigned int regno = REGNO (x);
11150 unsigned int endregno
11151 = regno + (regno < FIRST_PSEUDO_REGISTER
11152 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11155 for (r = regno; r < endregno; r++)
11156 reg_last_set_table_tick[r] = label_tick;
11161 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11162 /* Note that we can't have an "E" in values stored; see
11163 get_last_value_validate. */
11165 update_table_tick (XEXP (x, i));
11168 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11169 are saying that the register is clobbered and we no longer know its
11170 value. If INSN is zero, don't update reg_last_set; this is only permitted
11171 with VALUE also zero and is used to invalidate the register. */
11174 record_value_for_reg (reg, insn, value)
11179 unsigned int regno = REGNO (reg);
11180 unsigned int endregno
11181 = regno + (regno < FIRST_PSEUDO_REGISTER
11182 ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
11185 /* If VALUE contains REG and we have a previous value for REG, substitute
11186 the previous value. */
11187 if (value && insn && reg_overlap_mentioned_p (reg, value))
11191 /* Set things up so get_last_value is allowed to see anything set up to
11193 subst_low_cuid = INSN_CUID (insn);
11194 tem = get_last_value (reg);
11196 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11197 it isn't going to be useful and will take a lot of time to process,
11198 so just use the CLOBBER. */
11202 if ((GET_RTX_CLASS (GET_CODE (tem)) == '2'
11203 || GET_RTX_CLASS (GET_CODE (tem)) == 'c')
11204 && GET_CODE (XEXP (tem, 0)) == CLOBBER
11205 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
11206 tem = XEXP (tem, 0);
11208 value = replace_rtx (copy_rtx (value), reg, tem);
11212 /* For each register modified, show we don't know its value, that
11213 we don't know about its bitwise content, that its value has been
11214 updated, and that we don't know the location of the death of the
11216 for (i = regno; i < endregno; i++)
11219 reg_last_set[i] = insn;
11221 reg_last_set_value[i] = 0;
11222 reg_last_set_mode[i] = 0;
11223 reg_last_set_nonzero_bits[i] = 0;
11224 reg_last_set_sign_bit_copies[i] = 0;
11225 reg_last_death[i] = 0;
11228 /* Mark registers that are being referenced in this value. */
11230 update_table_tick (value);
11232 /* Now update the status of each register being set.
11233 If someone is using this register in this block, set this register
11234 to invalid since we will get confused between the two lives in this
11235 basic block. This makes using this register always invalid. In cse, we
11236 scan the table to invalidate all entries using this register, but this
11237 is too much work for us. */
11239 for (i = regno; i < endregno; i++)
11241 reg_last_set_label[i] = label_tick;
11242 if (value && reg_last_set_table_tick[i] == label_tick)
11243 reg_last_set_invalid[i] = 1;
11245 reg_last_set_invalid[i] = 0;
11248 /* The value being assigned might refer to X (like in "x++;"). In that
11249 case, we must replace it with (clobber (const_int 0)) to prevent
11251 if (value && ! get_last_value_validate (&value, insn,
11252 reg_last_set_label[regno], 0))
11254 value = copy_rtx (value);
11255 if (! get_last_value_validate (&value, insn,
11256 reg_last_set_label[regno], 1))
11260 /* For the main register being modified, update the value, the mode, the
11261 nonzero bits, and the number of sign bit copies. */
11263 reg_last_set_value[regno] = value;
11267 subst_low_cuid = INSN_CUID (insn);
11268 reg_last_set_mode[regno] = GET_MODE (reg);
11269 reg_last_set_nonzero_bits[regno] = nonzero_bits (value, GET_MODE (reg));
11270 reg_last_set_sign_bit_copies[regno]
11271 = num_sign_bit_copies (value, GET_MODE (reg));
11275 /* Called via note_stores from record_dead_and_set_regs to handle one
11276 SET or CLOBBER in an insn. DATA is the instruction in which the
11277 set is occurring. */
11280 record_dead_and_set_regs_1 (dest, setter, data)
11284 rtx record_dead_insn = (rtx) data;
11286 if (GET_CODE (dest) == SUBREG)
11287 dest = SUBREG_REG (dest);
11289 if (GET_CODE (dest) == REG)
11291 /* If we are setting the whole register, we know its value. Otherwise
11292 show that we don't know the value. We can handle SUBREG in
11294 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
11295 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
11296 else if (GET_CODE (setter) == SET
11297 && GET_CODE (SET_DEST (setter)) == SUBREG
11298 && SUBREG_REG (SET_DEST (setter)) == dest
11299 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
11300 && subreg_lowpart_p (SET_DEST (setter)))
11301 record_value_for_reg (dest, record_dead_insn,
11302 gen_lowpart_for_combine (GET_MODE (dest),
11303 SET_SRC (setter)));
11305 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
11307 else if (GET_CODE (dest) == MEM
11308 /* Ignore pushes, they clobber nothing. */
11309 && ! push_operand (dest, GET_MODE (dest)))
11310 mem_last_set = INSN_CUID (record_dead_insn);
11313 /* Update the records of when each REG was most recently set or killed
11314 for the things done by INSN. This is the last thing done in processing
11315 INSN in the combiner loop.
11317 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
11318 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
11319 and also the similar information mem_last_set (which insn most recently
11320 modified memory) and last_call_cuid (which insn was the most recent
11321 subroutine call). */
11324 record_dead_and_set_regs (insn)
11330 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11332 if (REG_NOTE_KIND (link) == REG_DEAD
11333 && GET_CODE (XEXP (link, 0)) == REG)
11335 unsigned int regno = REGNO (XEXP (link, 0));
11336 unsigned int endregno
11337 = regno + (regno < FIRST_PSEUDO_REGISTER
11338 ? HARD_REGNO_NREGS (regno, GET_MODE (XEXP (link, 0)))
11341 for (i = regno; i < endregno; i++)
11342 reg_last_death[i] = insn;
11344 else if (REG_NOTE_KIND (link) == REG_INC)
11345 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11348 if (GET_CODE (insn) == CALL_INSN)
11350 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11351 if (call_used_regs[i])
11353 reg_last_set_value[i] = 0;
11354 reg_last_set_mode[i] = 0;
11355 reg_last_set_nonzero_bits[i] = 0;
11356 reg_last_set_sign_bit_copies[i] = 0;
11357 reg_last_death[i] = 0;
11360 last_call_cuid = mem_last_set = INSN_CUID (insn);
11363 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11366 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11367 register present in the SUBREG, so for each such SUBREG go back and
11368 adjust nonzero and sign bit information of the registers that are
11369 known to have some zero/sign bits set.
11371 This is needed because when combine blows the SUBREGs away, the
11372 information on zero/sign bits is lost and further combines can be
11373 missed because of that. */
11376 record_promoted_value (insn, subreg)
11381 unsigned int regno = REGNO (SUBREG_REG (subreg));
11382 enum machine_mode mode = GET_MODE (subreg);
11384 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11387 for (links = LOG_LINKS (insn); links;)
11389 insn = XEXP (links, 0);
11390 set = single_set (insn);
11392 if (! set || GET_CODE (SET_DEST (set)) != REG
11393 || REGNO (SET_DEST (set)) != regno
11394 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11396 links = XEXP (links, 1);
11400 if (reg_last_set[regno] == insn)
11402 if (SUBREG_PROMOTED_UNSIGNED_P (subreg))
11403 reg_last_set_nonzero_bits[regno] &= GET_MODE_MASK (mode);
11406 if (GET_CODE (SET_SRC (set)) == REG)
11408 regno = REGNO (SET_SRC (set));
11409 links = LOG_LINKS (insn);
11416 /* Scan X for promoted SUBREGs. For each one found,
11417 note what it implies to the registers used in it. */
11420 check_promoted_subreg (insn, x)
11424 if (GET_CODE (x) == SUBREG && SUBREG_PROMOTED_VAR_P (x)
11425 && GET_CODE (SUBREG_REG (x)) == REG)
11426 record_promoted_value (insn, x);
11429 const char *format = GET_RTX_FORMAT (GET_CODE (x));
11432 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11436 check_promoted_subreg (insn, XEXP (x, i));
11440 if (XVEC (x, i) != 0)
11441 for (j = 0; j < XVECLEN (x, i); j++)
11442 check_promoted_subreg (insn, XVECEXP (x, i, j));
11448 /* Utility routine for the following function. Verify that all the registers
11449 mentioned in *LOC are valid when *LOC was part of a value set when
11450 label_tick == TICK. Return 0 if some are not.
11452 If REPLACE is non-zero, replace the invalid reference with
11453 (clobber (const_int 0)) and return 1. This replacement is useful because
11454 we often can get useful information about the form of a value (e.g., if
11455 it was produced by a shift that always produces -1 or 0) even though
11456 we don't know exactly what registers it was produced from. */
11459 get_last_value_validate (loc, insn, tick, replace)
11466 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11467 int len = GET_RTX_LENGTH (GET_CODE (x));
11470 if (GET_CODE (x) == REG)
11472 unsigned int regno = REGNO (x);
11473 unsigned int endregno
11474 = regno + (regno < FIRST_PSEUDO_REGISTER
11475 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11478 for (j = regno; j < endregno; j++)
11479 if (reg_last_set_invalid[j]
11480 /* If this is a pseudo-register that was only set once and not
11481 live at the beginning of the function, it is always valid. */
11482 || (! (regno >= FIRST_PSEUDO_REGISTER
11483 && REG_N_SETS (regno) == 1
11484 && (! REGNO_REG_SET_P
11485 (BASIC_BLOCK (0)->global_live_at_start, regno)))
11486 && reg_last_set_label[j] > tick))
11489 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11495 /* If this is a memory reference, make sure that there were
11496 no stores after it that might have clobbered the value. We don't
11497 have alias info, so we assume any store invalidates it. */
11498 else if (GET_CODE (x) == MEM && ! RTX_UNCHANGING_P (x)
11499 && INSN_CUID (insn) <= mem_last_set)
11502 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11506 for (i = 0; i < len; i++)
11508 && get_last_value_validate (&XEXP (x, i), insn, tick, replace) == 0)
11509 /* Don't bother with these. They shouldn't occur anyway. */
11513 /* If we haven't found a reason for it to be invalid, it is valid. */
11517 /* Get the last value assigned to X, if known. Some registers
11518 in the value may be replaced with (clobber (const_int 0)) if their value
11519 is known longer known reliably. */
11525 unsigned int regno;
11528 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11529 then convert it to the desired mode. If this is a paradoxical SUBREG,
11530 we cannot predict what values the "extra" bits might have. */
11531 if (GET_CODE (x) == SUBREG
11532 && subreg_lowpart_p (x)
11533 && (GET_MODE_SIZE (GET_MODE (x))
11534 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11535 && (value = get_last_value (SUBREG_REG (x))) != 0)
11536 return gen_lowpart_for_combine (GET_MODE (x), value);
11538 if (GET_CODE (x) != REG)
11542 value = reg_last_set_value[regno];
11544 /* If we don't have a value, or if it isn't for this basic block and
11545 it's either a hard register, set more than once, or it's a live
11546 at the beginning of the function, return 0.
11548 Because if it's not live at the beginnning of the function then the reg
11549 is always set before being used (is never used without being set).
11550 And, if it's set only once, and it's always set before use, then all
11551 uses must have the same last value, even if it's not from this basic
11555 || (reg_last_set_label[regno] != label_tick
11556 && (regno < FIRST_PSEUDO_REGISTER
11557 || REG_N_SETS (regno) != 1
11558 || (REGNO_REG_SET_P
11559 (BASIC_BLOCK (0)->global_live_at_start, regno)))))
11562 /* If the value was set in a later insn than the ones we are processing,
11563 we can't use it even if the register was only set once. */
11564 if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)
11567 /* If the value has all its registers valid, return it. */
11568 if (get_last_value_validate (&value, reg_last_set[regno],
11569 reg_last_set_label[regno], 0))
11572 /* Otherwise, make a copy and replace any invalid register with
11573 (clobber (const_int 0)). If that fails for some reason, return 0. */
11575 value = copy_rtx (value);
11576 if (get_last_value_validate (&value, reg_last_set[regno],
11577 reg_last_set_label[regno], 1))
11583 /* Return nonzero if expression X refers to a REG or to memory
11584 that is set in an instruction more recent than FROM_CUID. */
11587 use_crosses_set_p (x, from_cuid)
11591 register const char *fmt;
11593 register enum rtx_code code = GET_CODE (x);
11597 unsigned int regno = REGNO (x);
11598 unsigned endreg = regno + (regno < FIRST_PSEUDO_REGISTER
11599 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11601 #ifdef PUSH_ROUNDING
11602 /* Don't allow uses of the stack pointer to be moved,
11603 because we don't know whether the move crosses a push insn. */
11604 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11607 for (; regno < endreg; regno++)
11608 if (reg_last_set[regno]
11609 && INSN_CUID (reg_last_set[regno]) > from_cuid)
11614 if (code == MEM && mem_last_set > from_cuid)
11617 fmt = GET_RTX_FORMAT (code);
11619 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11624 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11625 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
11628 else if (fmt[i] == 'e'
11629 && use_crosses_set_p (XEXP (x, i), from_cuid))
11635 /* Define three variables used for communication between the following
11638 static unsigned int reg_dead_regno, reg_dead_endregno;
11639 static int reg_dead_flag;
11641 /* Function called via note_stores from reg_dead_at_p.
11643 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11644 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11647 reg_dead_at_p_1 (dest, x, data)
11650 void *data ATTRIBUTE_UNUSED;
11652 unsigned int regno, endregno;
11654 if (GET_CODE (dest) != REG)
11657 regno = REGNO (dest);
11658 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
11659 ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
11661 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11662 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11665 /* Return non-zero if REG is known to be dead at INSN.
11667 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11668 referencing REG, it is dead. If we hit a SET referencing REG, it is
11669 live. Otherwise, see if it is live or dead at the start of the basic
11670 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11671 must be assumed to be always live. */
11674 reg_dead_at_p (reg, insn)
11681 /* Set variables for reg_dead_at_p_1. */
11682 reg_dead_regno = REGNO (reg);
11683 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
11684 ? HARD_REGNO_NREGS (reg_dead_regno,
11690 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
11691 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11693 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11694 if (TEST_HARD_REG_BIT (newpat_used_regs, i))
11698 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11699 beginning of function. */
11700 for (; insn && GET_CODE (insn) != CODE_LABEL && GET_CODE (insn) != BARRIER;
11701 insn = prev_nonnote_insn (insn))
11703 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
11705 return reg_dead_flag == 1 ? 1 : 0;
11707 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11711 /* Get the basic block number that we were in. */
11716 for (block = 0; block < n_basic_blocks; block++)
11717 if (insn == BLOCK_HEAD (block))
11720 if (block == n_basic_blocks)
11724 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11725 if (REGNO_REG_SET_P (BASIC_BLOCK (block)->global_live_at_start, i))
11731 /* Note hard registers in X that are used. This code is similar to
11732 that in flow.c, but much simpler since we don't care about pseudos. */
11735 mark_used_regs_combine (x)
11738 RTX_CODE code = GET_CODE (x);
11739 unsigned int regno;
11751 case ADDR_DIFF_VEC:
11754 /* CC0 must die in the insn after it is set, so we don't need to take
11755 special note of it here. */
11761 /* If we are clobbering a MEM, mark any hard registers inside the
11762 address as used. */
11763 if (GET_CODE (XEXP (x, 0)) == MEM)
11764 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
11769 /* A hard reg in a wide mode may really be multiple registers.
11770 If so, mark all of them just like the first. */
11771 if (regno < FIRST_PSEUDO_REGISTER)
11773 unsigned int endregno, r;
11775 /* None of this applies to the stack, frame or arg pointers */
11776 if (regno == STACK_POINTER_REGNUM
11777 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11778 || regno == HARD_FRAME_POINTER_REGNUM
11780 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11781 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
11783 || regno == FRAME_POINTER_REGNUM)
11786 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11787 for (r = regno; r < endregno; r++)
11788 SET_HARD_REG_BIT (newpat_used_regs, r);
11794 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11796 register rtx testreg = SET_DEST (x);
11798 while (GET_CODE (testreg) == SUBREG
11799 || GET_CODE (testreg) == ZERO_EXTRACT
11800 || GET_CODE (testreg) == SIGN_EXTRACT
11801 || GET_CODE (testreg) == STRICT_LOW_PART)
11802 testreg = XEXP (testreg, 0);
11804 if (GET_CODE (testreg) == MEM)
11805 mark_used_regs_combine (XEXP (testreg, 0));
11807 mark_used_regs_combine (SET_SRC (x));
11815 /* Recursively scan the operands of this expression. */
11818 register const char *fmt = GET_RTX_FORMAT (code);
11820 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11823 mark_used_regs_combine (XEXP (x, i));
11824 else if (fmt[i] == 'E')
11828 for (j = 0; j < XVECLEN (x, i); j++)
11829 mark_used_regs_combine (XVECEXP (x, i, j));
11835 /* Remove register number REGNO from the dead registers list of INSN.
11837 Return the note used to record the death, if there was one. */
11840 remove_death (regno, insn)
11841 unsigned int regno;
11844 register rtx note = find_regno_note (insn, REG_DEAD, regno);
11848 REG_N_DEATHS (regno)--;
11849 remove_note (insn, note);
11855 /* For each register (hardware or pseudo) used within expression X, if its
11856 death is in an instruction with cuid between FROM_CUID (inclusive) and
11857 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11858 list headed by PNOTES.
11860 That said, don't move registers killed by maybe_kill_insn.
11862 This is done when X is being merged by combination into TO_INSN. These
11863 notes will then be distributed as needed. */
11866 move_deaths (x, maybe_kill_insn, from_cuid, to_insn, pnotes)
11868 rtx maybe_kill_insn;
11873 register const char *fmt;
11874 register int len, i;
11875 register enum rtx_code code = GET_CODE (x);
11879 unsigned int regno = REGNO (x);
11880 register rtx where_dead = reg_last_death[regno];
11881 register rtx before_dead, after_dead;
11883 /* Don't move the register if it gets killed in between from and to */
11884 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
11885 && ! reg_referenced_p (x, maybe_kill_insn))
11888 /* WHERE_DEAD could be a USE insn made by combine, so first we
11889 make sure that we have insns with valid INSN_CUID values. */
11890 before_dead = where_dead;
11891 while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
11892 before_dead = PREV_INSN (before_dead);
11894 after_dead = where_dead;
11895 while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
11896 after_dead = NEXT_INSN (after_dead);
11898 if (before_dead && after_dead
11899 && INSN_CUID (before_dead) >= from_cuid
11900 && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
11901 || (where_dead != after_dead
11902 && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
11904 rtx note = remove_death (regno, where_dead);
11906 /* It is possible for the call above to return 0. This can occur
11907 when reg_last_death points to I2 or I1 that we combined with.
11908 In that case make a new note.
11910 We must also check for the case where X is a hard register
11911 and NOTE is a death note for a range of hard registers
11912 including X. In that case, we must put REG_DEAD notes for
11913 the remaining registers in place of NOTE. */
11915 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
11916 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11917 > GET_MODE_SIZE (GET_MODE (x))))
11919 unsigned int deadregno = REGNO (XEXP (note, 0));
11920 unsigned int deadend
11921 = (deadregno + HARD_REGNO_NREGS (deadregno,
11922 GET_MODE (XEXP (note, 0))));
11923 unsigned int ourend
11924 = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11927 for (i = deadregno; i < deadend; i++)
11928 if (i < regno || i >= ourend)
11929 REG_NOTES (where_dead)
11930 = gen_rtx_EXPR_LIST (REG_DEAD,
11931 gen_rtx_REG (reg_raw_mode[i], i),
11932 REG_NOTES (where_dead));
11935 /* If we didn't find any note, or if we found a REG_DEAD note that
11936 covers only part of the given reg, and we have a multi-reg hard
11937 register, then to be safe we must check for REG_DEAD notes
11938 for each register other than the first. They could have
11939 their own REG_DEAD notes lying around. */
11940 else if ((note == 0
11942 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11943 < GET_MODE_SIZE (GET_MODE (x)))))
11944 && regno < FIRST_PSEUDO_REGISTER
11945 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
11947 unsigned int ourend
11948 = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11949 unsigned int i, offset;
11953 offset = HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0)));
11957 for (i = regno + offset; i < ourend; i++)
11958 move_deaths (gen_rtx_REG (reg_raw_mode[i], i),
11959 maybe_kill_insn, from_cuid, to_insn, &oldnotes);
11962 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
11964 XEXP (note, 1) = *pnotes;
11968 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
11970 REG_N_DEATHS (regno)++;
11976 else if (GET_CODE (x) == SET)
11978 rtx dest = SET_DEST (x);
11980 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
11982 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11983 that accesses one word of a multi-word item, some
11984 piece of everything register in the expression is used by
11985 this insn, so remove any old death. */
11987 if (GET_CODE (dest) == ZERO_EXTRACT
11988 || GET_CODE (dest) == STRICT_LOW_PART
11989 || (GET_CODE (dest) == SUBREG
11990 && (((GET_MODE_SIZE (GET_MODE (dest))
11991 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
11992 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
11993 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
11995 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
11999 /* If this is some other SUBREG, we know it replaces the entire
12000 value, so use that as the destination. */
12001 if (GET_CODE (dest) == SUBREG)
12002 dest = SUBREG_REG (dest);
12004 /* If this is a MEM, adjust deaths of anything used in the address.
12005 For a REG (the only other possibility), the entire value is
12006 being replaced so the old value is not used in this insn. */
12008 if (GET_CODE (dest) == MEM)
12009 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
12014 else if (GET_CODE (x) == CLOBBER)
12017 len = GET_RTX_LENGTH (code);
12018 fmt = GET_RTX_FORMAT (code);
12020 for (i = 0; i < len; i++)
12025 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12026 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
12029 else if (fmt[i] == 'e')
12030 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
12034 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12035 pattern of an insn. X must be a REG. */
12038 reg_bitfield_target_p (x, body)
12044 if (GET_CODE (body) == SET)
12046 rtx dest = SET_DEST (body);
12048 unsigned int regno, tregno, endregno, endtregno;
12050 if (GET_CODE (dest) == ZERO_EXTRACT)
12051 target = XEXP (dest, 0);
12052 else if (GET_CODE (dest) == STRICT_LOW_PART)
12053 target = SUBREG_REG (XEXP (dest, 0));
12057 if (GET_CODE (target) == SUBREG)
12058 target = SUBREG_REG (target);
12060 if (GET_CODE (target) != REG)
12063 tregno = REGNO (target), regno = REGNO (x);
12064 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
12065 return target == x;
12067 endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target));
12068 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
12070 return endregno > tregno && regno < endtregno;
12073 else if (GET_CODE (body) == PARALLEL)
12074 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
12075 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
12081 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12082 as appropriate. I3 and I2 are the insns resulting from the combination
12083 insns including FROM (I2 may be zero).
12085 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
12086 not need REG_DEAD notes because they are being substituted for. This
12087 saves searching in the most common cases.
12089 Each note in the list is either ignored or placed on some insns, depending
12090 on the type of note. */
12093 distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1)
12097 rtx elim_i2, elim_i1;
12099 rtx note, next_note;
12102 for (note = notes; note; note = next_note)
12104 rtx place = 0, place2 = 0;
12106 /* If this NOTE references a pseudo register, ensure it references
12107 the latest copy of that register. */
12108 if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
12109 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
12110 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
12112 next_note = XEXP (note, 1);
12113 switch (REG_NOTE_KIND (note))
12116 case REG_EXEC_COUNT:
12117 /* Doesn't matter much where we put this, as long as it's somewhere.
12118 It is preferable to keep these notes on branches, which is most
12119 likely to be i3. */
12123 case REG_EH_REGION:
12124 case REG_EH_RETHROW:
12126 /* These notes must remain with the call. It should not be
12127 possible for both I2 and I3 to be a call. */
12128 if (GET_CODE (i3) == CALL_INSN)
12130 else if (i2 && GET_CODE (i2) == CALL_INSN)
12137 /* Any clobbers for i3 may still exist, and so we must process
12138 REG_UNUSED notes from that insn.
12140 Any clobbers from i2 or i1 can only exist if they were added by
12141 recog_for_combine. In that case, recog_for_combine created the
12142 necessary REG_UNUSED notes. Trying to keep any original
12143 REG_UNUSED notes from these insns can cause incorrect output
12144 if it is for the same register as the original i3 dest.
12145 In that case, we will notice that the register is set in i3,
12146 and then add a REG_UNUSED note for the destination of i3, which
12147 is wrong. However, it is possible to have REG_UNUSED notes from
12148 i2 or i1 for register which were both used and clobbered, so
12149 we keep notes from i2 or i1 if they will turn into REG_DEAD
12152 /* If this register is set or clobbered in I3, put the note there
12153 unless there is one already. */
12154 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
12156 if (from_insn != i3)
12159 if (! (GET_CODE (XEXP (note, 0)) == REG
12160 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
12161 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
12164 /* Otherwise, if this register is used by I3, then this register
12165 now dies here, so we must put a REG_DEAD note here unless there
12167 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
12168 && ! (GET_CODE (XEXP (note, 0)) == REG
12169 ? find_regno_note (i3, REG_DEAD,
12170 REGNO (XEXP (note, 0)))
12171 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
12173 PUT_REG_NOTE_KIND (note, REG_DEAD);
12181 /* These notes say something about results of an insn. We can
12182 only support them if they used to be on I3 in which case they
12183 remain on I3. Otherwise they are ignored.
12185 If the note refers to an expression that is not a constant, we
12186 must also ignore the note since we cannot tell whether the
12187 equivalence is still true. It might be possible to do
12188 slightly better than this (we only have a problem if I2DEST
12189 or I1DEST is present in the expression), but it doesn't
12190 seem worth the trouble. */
12192 if (from_insn == i3
12193 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
12198 case REG_NO_CONFLICT:
12199 /* These notes say something about how a register is used. They must
12200 be present on any use of the register in I2 or I3. */
12201 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
12204 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
12214 /* This can show up in several ways -- either directly in the
12215 pattern, or hidden off in the constant pool with (or without?)
12216 a REG_EQUAL note. */
12217 /* ??? Ignore the without-reg_equal-note problem for now. */
12218 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
12219 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
12220 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12221 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
12225 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
12226 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
12227 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12228 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12239 /* These notes say something about the value of a register prior
12240 to the execution of an insn. It is too much trouble to see
12241 if the note is still correct in all situations. It is better
12242 to simply delete it. */
12246 /* If the insn previously containing this note still exists,
12247 put it back where it was. Otherwise move it to the previous
12248 insn. Adjust the corresponding REG_LIBCALL note. */
12249 if (GET_CODE (from_insn) != NOTE)
12253 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
12254 place = prev_real_insn (from_insn);
12256 XEXP (tem, 0) = place;
12257 /* If we're deleting the last remaining instruction of a
12258 libcall sequence, don't add the notes. */
12259 else if (XEXP (note, 0) == from_insn)
12265 /* This is handled similarly to REG_RETVAL. */
12266 if (GET_CODE (from_insn) != NOTE)
12270 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
12271 place = next_real_insn (from_insn);
12273 XEXP (tem, 0) = place;
12274 /* If we're deleting the last remaining instruction of a
12275 libcall sequence, don't add the notes. */
12276 else if (XEXP (note, 0) == from_insn)
12282 /* If the register is used as an input in I3, it dies there.
12283 Similarly for I2, if it is non-zero and adjacent to I3.
12285 If the register is not used as an input in either I3 or I2
12286 and it is not one of the registers we were supposed to eliminate,
12287 there are two possibilities. We might have a non-adjacent I2
12288 or we might have somehow eliminated an additional register
12289 from a computation. For example, we might have had A & B where
12290 we discover that B will always be zero. In this case we will
12291 eliminate the reference to A.
12293 In both cases, we must search to see if we can find a previous
12294 use of A and put the death note there. */
12297 && GET_CODE (from_insn) == CALL_INSN
12298 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12300 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12302 else if (i2 != 0 && next_nonnote_insn (i2) == i3
12303 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12306 if (rtx_equal_p (XEXP (note, 0), elim_i2)
12307 || rtx_equal_p (XEXP (note, 0), elim_i1))
12312 basic_block bb = BASIC_BLOCK (this_basic_block);
12314 for (tem = PREV_INSN (i3); place == 0; tem = PREV_INSN (tem))
12316 if (! INSN_P (tem))
12318 if (tem == bb->head)
12323 /* If the register is being set at TEM, see if that is all
12324 TEM is doing. If so, delete TEM. Otherwise, make this
12325 into a REG_UNUSED note instead. */
12326 if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
12328 rtx set = single_set (tem);
12329 rtx inner_dest = 0;
12331 rtx cc0_setter = NULL_RTX;
12335 for (inner_dest = SET_DEST (set);
12336 (GET_CODE (inner_dest) == STRICT_LOW_PART
12337 || GET_CODE (inner_dest) == SUBREG
12338 || GET_CODE (inner_dest) == ZERO_EXTRACT);
12339 inner_dest = XEXP (inner_dest, 0))
12342 /* Verify that it was the set, and not a clobber that
12343 modified the register.
12345 CC0 targets must be careful to maintain setter/user
12346 pairs. If we cannot delete the setter due to side
12347 effects, mark the user with an UNUSED note instead
12350 if (set != 0 && ! side_effects_p (SET_SRC (set))
12351 && rtx_equal_p (XEXP (note, 0), inner_dest)
12353 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12354 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12355 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12359 /* Move the notes and links of TEM elsewhere.
12360 This might delete other dead insns recursively.
12361 First set the pattern to something that won't use
12364 PATTERN (tem) = pc_rtx;
12366 distribute_notes (REG_NOTES (tem), tem, tem,
12367 NULL_RTX, NULL_RTX, NULL_RTX);
12368 distribute_links (LOG_LINKS (tem));
12370 PUT_CODE (tem, NOTE);
12371 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
12372 NOTE_SOURCE_FILE (tem) = 0;
12375 /* Delete the setter too. */
12378 PATTERN (cc0_setter) = pc_rtx;
12380 distribute_notes (REG_NOTES (cc0_setter),
12381 cc0_setter, cc0_setter,
12382 NULL_RTX, NULL_RTX, NULL_RTX);
12383 distribute_links (LOG_LINKS (cc0_setter));
12385 PUT_CODE (cc0_setter, NOTE);
12386 NOTE_LINE_NUMBER (cc0_setter)
12387 = NOTE_INSN_DELETED;
12388 NOTE_SOURCE_FILE (cc0_setter) = 0;
12392 /* If the register is both set and used here, put the
12393 REG_DEAD note here, but place a REG_UNUSED note
12394 here too unless there already is one. */
12395 else if (reg_referenced_p (XEXP (note, 0),
12400 if (! find_regno_note (tem, REG_UNUSED,
12401 REGNO (XEXP (note, 0))))
12403 = gen_rtx_EXPR_LIST (REG_UNUSED, XEXP (note, 0),
12408 PUT_REG_NOTE_KIND (note, REG_UNUSED);
12410 /* If there isn't already a REG_UNUSED note, put one
12412 if (! find_regno_note (tem, REG_UNUSED,
12413 REGNO (XEXP (note, 0))))
12418 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12419 || (GET_CODE (tem) == CALL_INSN
12420 && find_reg_fusage (tem, USE, XEXP (note, 0))))
12424 /* If we are doing a 3->2 combination, and we have a
12425 register which formerly died in i3 and was not used
12426 by i2, which now no longer dies in i3 and is used in
12427 i2 but does not die in i2, and place is between i2
12428 and i3, then we may need to move a link from place to
12430 if (i2 && INSN_UID (place) <= max_uid_cuid
12431 && INSN_CUID (place) > INSN_CUID (i2)
12433 && INSN_CUID (from_insn) > INSN_CUID (i2)
12434 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12436 rtx links = LOG_LINKS (place);
12437 LOG_LINKS (place) = 0;
12438 distribute_links (links);
12443 if (tem == bb->head)
12447 /* We haven't found an insn for the death note and it
12448 is still a REG_DEAD note, but we have hit the beginning
12449 of the block. If the existing life info says the reg
12450 was dead, there's nothing left to do. Otherwise, we'll
12451 need to do a global life update after combine. */
12452 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0
12453 && REGNO_REG_SET_P (bb->global_live_at_start,
12454 REGNO (XEXP (note, 0))))
12456 SET_BIT (refresh_blocks, this_basic_block);
12461 /* If the register is set or already dead at PLACE, we needn't do
12462 anything with this note if it is still a REG_DEAD note.
12463 We can here if it is set at all, not if is it totally replace,
12464 which is what `dead_or_set_p' checks, so also check for it being
12467 if (place && REG_NOTE_KIND (note) == REG_DEAD)
12469 unsigned int regno = REGNO (XEXP (note, 0));
12471 if (dead_or_set_p (place, XEXP (note, 0))
12472 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12474 /* Unless the register previously died in PLACE, clear
12475 reg_last_death. [I no longer understand why this is
12477 if (reg_last_death[regno] != place)
12478 reg_last_death[regno] = 0;
12482 reg_last_death[regno] = place;
12484 /* If this is a death note for a hard reg that is occupying
12485 multiple registers, ensure that we are still using all
12486 parts of the object. If we find a piece of the object
12487 that is unused, we must arrange for an appropriate REG_DEAD
12488 note to be added for it. However, we can't just emit a USE
12489 and tag the note to it, since the register might actually
12490 be dead; so we recourse, and the recursive call then finds
12491 the previous insn that used this register. */
12493 if (place && regno < FIRST_PSEUDO_REGISTER
12494 && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
12496 unsigned int endregno
12497 = regno + HARD_REGNO_NREGS (regno,
12498 GET_MODE (XEXP (note, 0)));
12502 for (i = regno; i < endregno; i++)
12503 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12504 && ! find_regno_fusage (place, USE, i))
12505 || dead_or_set_regno_p (place, i))
12510 /* Put only REG_DEAD notes for pieces that are
12511 not already dead or set. */
12513 for (i = regno; i < endregno;
12514 i += HARD_REGNO_NREGS (i, reg_raw_mode[i]))
12516 rtx piece = gen_rtx_REG (reg_raw_mode[i], i);
12517 basic_block bb = BASIC_BLOCK (this_basic_block);
12519 if (! dead_or_set_p (place, piece)
12520 && ! reg_bitfield_target_p (piece,
12524 = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX);
12526 distribute_notes (new_note, place, place,
12527 NULL_RTX, NULL_RTX, NULL_RTX);
12529 else if (! refers_to_regno_p (i, i + 1,
12530 PATTERN (place), 0)
12531 && ! find_regno_fusage (place, USE, i))
12532 for (tem = PREV_INSN (place); ;
12533 tem = PREV_INSN (tem))
12535 if (! INSN_P (tem))
12537 if (tem == bb->head)
12539 SET_BIT (refresh_blocks,
12546 if (dead_or_set_p (tem, piece)
12547 || reg_bitfield_target_p (piece,
12551 = gen_rtx_EXPR_LIST (REG_UNUSED, piece,
12566 /* Any other notes should not be present at this point in the
12573 XEXP (note, 1) = REG_NOTES (place);
12574 REG_NOTES (place) = note;
12576 else if ((REG_NOTE_KIND (note) == REG_DEAD
12577 || REG_NOTE_KIND (note) == REG_UNUSED)
12578 && GET_CODE (XEXP (note, 0)) == REG)
12579 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
12583 if ((REG_NOTE_KIND (note) == REG_DEAD
12584 || REG_NOTE_KIND (note) == REG_UNUSED)
12585 && GET_CODE (XEXP (note, 0)) == REG)
12586 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
12588 REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
12589 REG_NOTE_KIND (note),
12591 REG_NOTES (place2));
12596 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12597 I3, I2, and I1 to new locations. This is also called in one case to
12598 add a link pointing at I3 when I3's destination is changed. */
12601 distribute_links (links)
12604 rtx link, next_link;
12606 for (link = links; link; link = next_link)
12612 next_link = XEXP (link, 1);
12614 /* If the insn that this link points to is a NOTE or isn't a single
12615 set, ignore it. In the latter case, it isn't clear what we
12616 can do other than ignore the link, since we can't tell which
12617 register it was for. Such links wouldn't be used by combine
12620 It is not possible for the destination of the target of the link to
12621 have been changed by combine. The only potential of this is if we
12622 replace I3, I2, and I1 by I3 and I2. But in that case the
12623 destination of I2 also remains unchanged. */
12625 if (GET_CODE (XEXP (link, 0)) == NOTE
12626 || (set = single_set (XEXP (link, 0))) == 0)
12629 reg = SET_DEST (set);
12630 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12631 || GET_CODE (reg) == SIGN_EXTRACT
12632 || GET_CODE (reg) == STRICT_LOW_PART)
12633 reg = XEXP (reg, 0);
12635 /* A LOG_LINK is defined as being placed on the first insn that uses
12636 a register and points to the insn that sets the register. Start
12637 searching at the next insn after the target of the link and stop
12638 when we reach a set of the register or the end of the basic block.
12640 Note that this correctly handles the link that used to point from
12641 I3 to I2. Also note that not much searching is typically done here
12642 since most links don't point very far away. */
12644 for (insn = NEXT_INSN (XEXP (link, 0));
12645 (insn && (this_basic_block == n_basic_blocks - 1
12646 || BLOCK_HEAD (this_basic_block + 1) != insn));
12647 insn = NEXT_INSN (insn))
12648 if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12650 if (reg_referenced_p (reg, PATTERN (insn)))
12654 else if (GET_CODE (insn) == CALL_INSN
12655 && find_reg_fusage (insn, USE, reg))
12661 /* If we found a place to put the link, place it there unless there
12662 is already a link to the same insn as LINK at that point. */
12668 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12669 if (XEXP (link2, 0) == XEXP (link, 0))
12674 XEXP (link, 1) = LOG_LINKS (place);
12675 LOG_LINKS (place) = link;
12677 /* Set added_links_insn to the earliest insn we added a
12679 if (added_links_insn == 0
12680 || INSN_CUID (added_links_insn) > INSN_CUID (place))
12681 added_links_insn = place;
12687 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12693 while (insn != 0 && INSN_UID (insn) > max_uid_cuid
12694 && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE)
12695 insn = NEXT_INSN (insn);
12697 if (INSN_UID (insn) > max_uid_cuid)
12700 return INSN_CUID (insn);
12704 dump_combine_stats (file)
12709 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12710 combine_attempts, combine_merges, combine_extras, combine_successes);
12714 dump_combine_total_stats (file)
12719 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12720 total_attempts, total_merges, total_extras, total_successes);