1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
87 #include "hard-reg-set.h"
88 #include "basic-block.h"
89 #include "insn-config.h"
91 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
93 #include "insn-attr.h"
99 #include "insn-codes.h"
100 #include "rtlhooks-def.h"
101 /* Include output.h for dump_file. */
105 #include "tree-pass.h"
109 /* Number of attempts to combine instructions in this function. */
111 static int combine_attempts;
113 /* Number of attempts that got as far as substitution in this function. */
115 static int combine_merges;
117 /* Number of instructions combined with added SETs in this function. */
119 static int combine_extras;
121 /* Number of instructions combined in this function. */
123 static int combine_successes;
125 /* Totals over entire compilation. */
127 static int total_attempts, total_merges, total_extras, total_successes;
129 /* combine_instructions may try to replace the right hand side of the
130 second instruction with the value of an associated REG_EQUAL note
131 before throwing it at try_combine. That is problematic when there
132 is a REG_DEAD note for a register used in the old right hand side
133 and can cause distribute_notes to do wrong things. This is the
134 second instruction if it has been so modified, null otherwise. */
138 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
140 static rtx i2mod_old_rhs;
142 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
144 static rtx i2mod_new_rhs;
146 typedef struct reg_stat_struct {
147 /* Record last point of death of (hard or pseudo) register n. */
150 /* Record last point of modification of (hard or pseudo) register n. */
153 /* The next group of fields allows the recording of the last value assigned
154 to (hard or pseudo) register n. We use this information to see if an
155 operation being processed is redundant given a prior operation performed
156 on the register. For example, an `and' with a constant is redundant if
157 all the zero bits are already known to be turned off.
159 We use an approach similar to that used by cse, but change it in the
162 (1) We do not want to reinitialize at each label.
163 (2) It is useful, but not critical, to know the actual value assigned
164 to a register. Often just its form is helpful.
166 Therefore, we maintain the following fields:
168 last_set_value the last value assigned
169 last_set_label records the value of label_tick when the
170 register was assigned
171 last_set_table_tick records the value of label_tick when a
172 value using the register is assigned
173 last_set_invalid set to nonzero when it is not valid
174 to use the value of this register in some
177 To understand the usage of these tables, it is important to understand
178 the distinction between the value in last_set_value being valid and
179 the register being validly contained in some other expression in the
182 (The next two parameters are out of date).
184 reg_stat[i].last_set_value is valid if it is nonzero, and either
185 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
187 Register I may validly appear in any expression returned for the value
188 of another register if reg_n_sets[i] is 1. It may also appear in the
189 value for register J if reg_stat[j].last_set_invalid is zero, or
190 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
192 If an expression is found in the table containing a register which may
193 not validly appear in an expression, the register is replaced by
194 something that won't match, (clobber (const_int 0)). */
196 /* Record last value assigned to (hard or pseudo) register n. */
200 /* Record the value of label_tick when an expression involving register n
201 is placed in last_set_value. */
203 int last_set_table_tick;
205 /* Record the value of label_tick when the value for register n is placed in
210 /* These fields are maintained in parallel with last_set_value and are
211 used to store the mode in which the register was last set, the bits
212 that were known to be zero when it was last set, and the number of
213 sign bits copies it was known to have when it was last set. */
215 unsigned HOST_WIDE_INT last_set_nonzero_bits;
216 char last_set_sign_bit_copies;
217 ENUM_BITFIELD(machine_mode) last_set_mode : 8;
219 /* Set nonzero if references to register n in expressions should not be
220 used. last_set_invalid is set nonzero when this register is being
221 assigned to and last_set_table_tick == label_tick. */
223 char last_set_invalid;
225 /* Some registers that are set more than once and used in more than one
226 basic block are nevertheless always set in similar ways. For example,
227 a QImode register may be loaded from memory in two places on a machine
228 where byte loads zero extend.
230 We record in the following fields if a register has some leading bits
231 that are always equal to the sign bit, and what we know about the
232 nonzero bits of a register, specifically which bits are known to be
235 If an entry is zero, it means that we don't know anything special. */
237 unsigned char sign_bit_copies;
239 unsigned HOST_WIDE_INT nonzero_bits;
241 /* Record the value of the label_tick when the last truncation
242 happened. The field truncated_to_mode is only valid if
243 truncation_label == label_tick. */
245 int truncation_label;
247 /* Record the last truncation seen for this register. If truncation
248 is not a nop to this mode we might be able to save an explicit
249 truncation if we know that value already contains a truncated
252 ENUM_BITFIELD(machine_mode) truncated_to_mode : 8;
255 DEF_VEC_O(reg_stat_type);
256 DEF_VEC_ALLOC_O(reg_stat_type,heap);
258 static VEC(reg_stat_type,heap) *reg_stat;
260 /* Record the luid of the last insn that invalidated memory
261 (anything that writes memory, and subroutine calls, but not pushes). */
263 static int mem_last_set;
265 /* Record the luid of the last CALL_INSN
266 so we can tell whether a potential combination crosses any calls. */
268 static int last_call_luid;
270 /* When `subst' is called, this is the insn that is being modified
271 (by combining in a previous insn). The PATTERN of this insn
272 is still the old pattern partially modified and it should not be
273 looked at, but this may be used to examine the successors of the insn
274 to judge whether a simplification is valid. */
276 static rtx subst_insn;
278 /* This is the lowest LUID that `subst' is currently dealing with.
279 get_last_value will not return a value if the register was set at or
280 after this LUID. If not for this mechanism, we could get confused if
281 I2 or I1 in try_combine were an insn that used the old value of a register
282 to obtain a new value. In that case, we might erroneously get the
283 new value of the register when we wanted the old one. */
285 static int subst_low_luid;
287 /* This contains any hard registers that are used in newpat; reg_dead_at_p
288 must consider all these registers to be always live. */
290 static HARD_REG_SET newpat_used_regs;
292 /* This is an insn to which a LOG_LINKS entry has been added. If this
293 insn is the earlier than I2 or I3, combine should rescan starting at
296 static rtx added_links_insn;
298 /* Basic block in which we are performing combines. */
299 static basic_block this_basic_block;
300 static bool optimize_this_for_speed_p;
303 /* Length of the currently allocated uid_insn_cost array. */
305 static int max_uid_known;
307 /* The following array records the insn_rtx_cost for every insn
308 in the instruction stream. */
310 static int *uid_insn_cost;
312 /* The following array records the LOG_LINKS for every insn in the
313 instruction stream as an INSN_LIST rtx. */
315 static rtx *uid_log_links;
317 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
318 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
320 /* Incremented for each basic block. */
322 static int label_tick;
324 /* Reset to label_tick for each label. */
326 static int label_tick_ebb_start;
328 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
329 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
331 static enum machine_mode nonzero_bits_mode;
333 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
334 be safely used. It is zero while computing them and after combine has
335 completed. This former test prevents propagating values based on
336 previously set values, which can be incorrect if a variable is modified
339 static int nonzero_sign_valid;
342 /* Record one modification to rtl structure
343 to be undone by storing old_contents into *where. */
345 enum undo_kind { UNDO_RTX, UNDO_INT, UNDO_MODE };
351 union { rtx r; int i; enum machine_mode m; } old_contents;
352 union { rtx *r; int *i; } where;
355 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
356 num_undo says how many are currently recorded.
358 other_insn is nonzero if we have modified some other insn in the process
359 of working on subst_insn. It must be verified too. */
368 static struct undobuf undobuf;
370 /* Number of times the pseudo being substituted for
371 was found and replaced. */
373 static int n_occurrences;
375 static rtx reg_nonzero_bits_for_combine (const_rtx, enum machine_mode, const_rtx,
377 unsigned HOST_WIDE_INT,
378 unsigned HOST_WIDE_INT *);
379 static rtx reg_num_sign_bit_copies_for_combine (const_rtx, enum machine_mode, const_rtx,
381 unsigned int, unsigned int *);
382 static void do_SUBST (rtx *, rtx);
383 static void do_SUBST_INT (int *, int);
384 static void init_reg_last (void);
385 static void setup_incoming_promotions (rtx);
386 static void set_nonzero_bits_and_sign_copies (rtx, const_rtx, void *);
387 static int cant_combine_insn_p (rtx);
388 static int can_combine_p (rtx, rtx, rtx, rtx, rtx *, rtx *);
389 static int combinable_i3pat (rtx, rtx *, rtx, rtx, int, rtx *);
390 static int contains_muldiv (rtx);
391 static rtx try_combine (rtx, rtx, rtx, int *);
392 static void undo_all (void);
393 static void undo_commit (void);
394 static rtx *find_split_point (rtx *, rtx);
395 static rtx subst (rtx, rtx, rtx, int, int);
396 static rtx combine_simplify_rtx (rtx, enum machine_mode, int);
397 static rtx simplify_if_then_else (rtx);
398 static rtx simplify_set (rtx);
399 static rtx simplify_logical (rtx);
400 static rtx expand_compound_operation (rtx);
401 static const_rtx expand_field_assignment (const_rtx);
402 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
403 rtx, unsigned HOST_WIDE_INT, int, int, int);
404 static rtx extract_left_shift (rtx, int);
405 static rtx make_compound_operation (rtx, enum rtx_code);
406 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
407 unsigned HOST_WIDE_INT *);
408 static rtx canon_reg_for_combine (rtx, rtx);
409 static rtx force_to_mode (rtx, enum machine_mode,
410 unsigned HOST_WIDE_INT, int);
411 static rtx if_then_else_cond (rtx, rtx *, rtx *);
412 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
413 static int rtx_equal_for_field_assignment_p (rtx, rtx);
414 static rtx make_field_assignment (rtx);
415 static rtx apply_distributive_law (rtx);
416 static rtx distribute_and_simplify_rtx (rtx, int);
417 static rtx simplify_and_const_int_1 (enum machine_mode, rtx,
418 unsigned HOST_WIDE_INT);
419 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
420 unsigned HOST_WIDE_INT);
421 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
422 HOST_WIDE_INT, enum machine_mode, int *);
423 static rtx simplify_shift_const_1 (enum rtx_code, enum machine_mode, rtx, int);
424 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
426 static int recog_for_combine (rtx *, rtx, rtx *);
427 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
428 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
429 static void update_table_tick (rtx);
430 static void record_value_for_reg (rtx, rtx, rtx);
431 static void check_promoted_subreg (rtx, rtx);
432 static void record_dead_and_set_regs_1 (rtx, const_rtx, void *);
433 static void record_dead_and_set_regs (rtx);
434 static int get_last_value_validate (rtx *, rtx, int, int);
435 static rtx get_last_value (const_rtx);
436 static int use_crosses_set_p (const_rtx, int);
437 static void reg_dead_at_p_1 (rtx, const_rtx, void *);
438 static int reg_dead_at_p (rtx, rtx);
439 static void move_deaths (rtx, rtx, int, rtx, rtx *);
440 static int reg_bitfield_target_p (rtx, rtx);
441 static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx);
442 static void distribute_links (rtx);
443 static void mark_used_regs_combine (rtx);
444 static void record_promoted_value (rtx, rtx);
445 static int unmentioned_reg_p_1 (rtx *, void *);
446 static bool unmentioned_reg_p (rtx, rtx);
447 static int record_truncated_value (rtx *, void *);
448 static void record_truncated_values (rtx *, void *);
449 static bool reg_truncated_to_mode (enum machine_mode, const_rtx);
450 static rtx gen_lowpart_or_truncate (enum machine_mode, rtx);
453 /* It is not safe to use ordinary gen_lowpart in combine.
454 See comments in gen_lowpart_for_combine. */
455 #undef RTL_HOOKS_GEN_LOWPART
456 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
458 /* Our implementation of gen_lowpart never emits a new pseudo. */
459 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
460 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
462 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
463 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
465 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
466 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
468 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
469 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
471 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
474 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
475 PATTERN can not be split. Otherwise, it returns an insn sequence.
476 This is a wrapper around split_insns which ensures that the
477 reg_stat vector is made larger if the splitter creates a new
481 combine_split_insns (rtx pattern, rtx insn)
486 ret = split_insns (pattern, insn);
487 nregs = max_reg_num ();
488 if (nregs > VEC_length (reg_stat_type, reg_stat))
489 VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
493 /* This is used by find_single_use to locate an rtx in LOC that
494 contains exactly one use of DEST, which is typically either a REG
495 or CC0. It returns a pointer to the innermost rtx expression
496 containing DEST. Appearances of DEST that are being used to
497 totally replace it are not counted. */
500 find_single_use_1 (rtx dest, rtx *loc)
503 enum rtx_code code = GET_CODE (x);
521 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
522 of a REG that occupies all of the REG, the insn uses DEST if
523 it is mentioned in the destination or the source. Otherwise, we
524 need just check the source. */
525 if (GET_CODE (SET_DEST (x)) != CC0
526 && GET_CODE (SET_DEST (x)) != PC
527 && !REG_P (SET_DEST (x))
528 && ! (GET_CODE (SET_DEST (x)) == SUBREG
529 && REG_P (SUBREG_REG (SET_DEST (x)))
530 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
531 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
532 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
533 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))))
536 return find_single_use_1 (dest, &SET_SRC (x));
540 return find_single_use_1 (dest, &XEXP (x, 0));
546 /* If it wasn't one of the common cases above, check each expression and
547 vector of this code. Look for a unique usage of DEST. */
549 fmt = GET_RTX_FORMAT (code);
550 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
554 if (dest == XEXP (x, i)
555 || (REG_P (dest) && REG_P (XEXP (x, i))
556 && REGNO (dest) == REGNO (XEXP (x, i))))
559 this_result = find_single_use_1 (dest, &XEXP (x, i));
562 result = this_result;
563 else if (this_result)
564 /* Duplicate usage. */
567 else if (fmt[i] == 'E')
571 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
573 if (XVECEXP (x, i, j) == dest
575 && REG_P (XVECEXP (x, i, j))
576 && REGNO (XVECEXP (x, i, j)) == REGNO (dest)))
579 this_result = find_single_use_1 (dest, &XVECEXP (x, i, j));
582 result = this_result;
583 else if (this_result)
593 /* See if DEST, produced in INSN, is used only a single time in the
594 sequel. If so, return a pointer to the innermost rtx expression in which
597 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
599 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
600 care about REG_DEAD notes or LOG_LINKS.
602 Otherwise, we find the single use by finding an insn that has a
603 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
604 only referenced once in that insn, we know that it must be the first
605 and last insn referencing DEST. */
608 find_single_use (rtx dest, rtx insn, rtx *ploc)
618 next = NEXT_INSN (insn);
620 || (!NONJUMP_INSN_P (next) && !JUMP_P (next)))
623 result = find_single_use_1 (dest, &PATTERN (next));
633 bb = BLOCK_FOR_INSN (insn);
634 for (next = NEXT_INSN (insn);
635 next && BLOCK_FOR_INSN (next) == bb;
636 next = NEXT_INSN (next))
637 if (INSN_P (next) && dead_or_set_p (next, dest))
639 for (link = LOG_LINKS (next); link; link = XEXP (link, 1))
640 if (XEXP (link, 0) == insn)
645 result = find_single_use_1 (dest, &PATTERN (next));
655 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
656 insn. The substitution can be undone by undo_all. If INTO is already
657 set to NEWVAL, do not record this change. Because computing NEWVAL might
658 also call SUBST, we have to compute it before we put anything into
662 do_SUBST (rtx *into, rtx newval)
667 if (oldval == newval)
670 /* We'd like to catch as many invalid transformations here as
671 possible. Unfortunately, there are way too many mode changes
672 that are perfectly valid, so we'd waste too much effort for
673 little gain doing the checks here. Focus on catching invalid
674 transformations involving integer constants. */
675 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
676 && GET_CODE (newval) == CONST_INT)
678 /* Sanity check that we're replacing oldval with a CONST_INT
679 that is a valid sign-extension for the original mode. */
680 gcc_assert (INTVAL (newval)
681 == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
683 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
684 CONST_INT is not valid, because after the replacement, the
685 original mode would be gone. Unfortunately, we can't tell
686 when do_SUBST is called to replace the operand thereof, so we
687 perform this test on oldval instead, checking whether an
688 invalid replacement took place before we got here. */
689 gcc_assert (!(GET_CODE (oldval) == SUBREG
690 && GET_CODE (SUBREG_REG (oldval)) == CONST_INT));
691 gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
692 && GET_CODE (XEXP (oldval, 0)) == CONST_INT));
696 buf = undobuf.frees, undobuf.frees = buf->next;
698 buf = XNEW (struct undo);
700 buf->kind = UNDO_RTX;
702 buf->old_contents.r = oldval;
705 buf->next = undobuf.undos, undobuf.undos = buf;
708 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
710 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
711 for the value of a HOST_WIDE_INT value (including CONST_INT) is
715 do_SUBST_INT (int *into, int newval)
720 if (oldval == newval)
724 buf = undobuf.frees, undobuf.frees = buf->next;
726 buf = XNEW (struct undo);
728 buf->kind = UNDO_INT;
730 buf->old_contents.i = oldval;
733 buf->next = undobuf.undos, undobuf.undos = buf;
736 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
738 /* Similar to SUBST, but just substitute the mode. This is used when
739 changing the mode of a pseudo-register, so that any other
740 references to the entry in the regno_reg_rtx array will change as
744 do_SUBST_MODE (rtx *into, enum machine_mode newval)
747 enum machine_mode oldval = GET_MODE (*into);
749 if (oldval == newval)
753 buf = undobuf.frees, undobuf.frees = buf->next;
755 buf = XNEW (struct undo);
757 buf->kind = UNDO_MODE;
759 buf->old_contents.m = oldval;
760 adjust_reg_mode (*into, newval);
762 buf->next = undobuf.undos, undobuf.undos = buf;
765 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE(&(INTO), (NEWVAL))
767 /* Subroutine of try_combine. Determine whether the combine replacement
768 patterns NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to
769 insn_rtx_cost that the original instruction sequence I1, I2, I3 and
770 undobuf.other_insn. Note that I1 and/or NEWI2PAT may be NULL_RTX.
771 NEWOTHERPAT and undobuf.other_insn may also both be NULL_RTX. This
772 function returns false, if the costs of all instructions can be
773 estimated, and the replacements are more expensive than the original
777 combine_validate_cost (rtx i1, rtx i2, rtx i3, rtx newpat, rtx newi2pat,
780 int i1_cost, i2_cost, i3_cost;
781 int new_i2_cost, new_i3_cost;
782 int old_cost, new_cost;
784 /* Lookup the original insn_rtx_costs. */
785 i2_cost = INSN_COST (i2);
786 i3_cost = INSN_COST (i3);
790 i1_cost = INSN_COST (i1);
791 old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0)
792 ? i1_cost + i2_cost + i3_cost : 0;
796 old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
800 /* Calculate the replacement insn_rtx_costs. */
801 new_i3_cost = insn_rtx_cost (newpat, optimize_this_for_speed_p);
804 new_i2_cost = insn_rtx_cost (newi2pat, optimize_this_for_speed_p);
805 new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
806 ? new_i2_cost + new_i3_cost : 0;
810 new_cost = new_i3_cost;
814 if (undobuf.other_insn)
816 int old_other_cost, new_other_cost;
818 old_other_cost = INSN_COST (undobuf.other_insn);
819 new_other_cost = insn_rtx_cost (newotherpat, optimize_this_for_speed_p);
820 if (old_other_cost > 0 && new_other_cost > 0)
822 old_cost += old_other_cost;
823 new_cost += new_other_cost;
829 /* Disallow this recombination if both new_cost and old_cost are
830 greater than zero, and new_cost is greater than old cost. */
832 && new_cost > old_cost)
839 "rejecting combination of insns %d, %d and %d\n",
840 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
841 fprintf (dump_file, "original costs %d + %d + %d = %d\n",
842 i1_cost, i2_cost, i3_cost, old_cost);
847 "rejecting combination of insns %d and %d\n",
848 INSN_UID (i2), INSN_UID (i3));
849 fprintf (dump_file, "original costs %d + %d = %d\n",
850 i2_cost, i3_cost, old_cost);
855 fprintf (dump_file, "replacement costs %d + %d = %d\n",
856 new_i2_cost, new_i3_cost, new_cost);
859 fprintf (dump_file, "replacement cost %d\n", new_cost);
865 /* Update the uid_insn_cost array with the replacement costs. */
866 INSN_COST (i2) = new_i2_cost;
867 INSN_COST (i3) = new_i3_cost;
875 /* Delete any insns that copy a register to itself. */
878 delete_noop_moves (void)
885 for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); insn = next)
887 next = NEXT_INSN (insn);
888 if (INSN_P (insn) && noop_move_p (insn))
891 fprintf (dump_file, "deleting noop move %d\n", INSN_UID (insn));
893 delete_insn_and_edges (insn);
900 /* Fill in log links field for all insns. */
903 create_log_links (void)
907 df_ref *def_vec, *use_vec;
909 next_use = XCNEWVEC (rtx, max_reg_num ());
911 /* Pass through each block from the end, recording the uses of each
912 register and establishing log links when def is encountered.
913 Note that we do not clear next_use array in order to save time,
914 so we have to test whether the use is in the same basic block as def.
916 There are a few cases below when we do not consider the definition or
917 usage -- these are taken from original flow.c did. Don't ask me why it is
918 done this way; I don't know and if it works, I don't want to know. */
922 FOR_BB_INSNS_REVERSE (bb, insn)
927 /* Log links are created only once. */
928 gcc_assert (!LOG_LINKS (insn));
930 for (def_vec = DF_INSN_DEFS (insn); *def_vec; def_vec++)
932 df_ref def = *def_vec;
933 int regno = DF_REF_REGNO (def);
936 if (!next_use[regno])
939 /* Do not consider if it is pre/post modification in MEM. */
940 if (DF_REF_FLAGS (def) & DF_REF_PRE_POST_MODIFY)
943 /* Do not make the log link for frame pointer. */
944 if ((regno == FRAME_POINTER_REGNUM
945 && (! reload_completed || frame_pointer_needed))
946 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
947 || (regno == HARD_FRAME_POINTER_REGNUM
948 && (! reload_completed || frame_pointer_needed))
950 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
951 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
956 use_insn = next_use[regno];
957 if (BLOCK_FOR_INSN (use_insn) == bb)
961 We don't build a LOG_LINK for hard registers contained
962 in ASM_OPERANDs. If these registers get replaced,
963 we might wind up changing the semantics of the insn,
964 even if reload can make what appear to be valid
965 assignments later. */
966 if (regno >= FIRST_PSEUDO_REGISTER
967 || asm_noperands (PATTERN (use_insn)) < 0)
969 /* Don't add duplicate links between instructions. */
971 for (links = LOG_LINKS (use_insn); links;
972 links = XEXP (links, 1))
973 if (insn == XEXP (links, 0))
977 LOG_LINKS (use_insn) =
978 alloc_INSN_LIST (insn, LOG_LINKS (use_insn));
981 next_use[regno] = NULL_RTX;
984 for (use_vec = DF_INSN_USES (insn); *use_vec; use_vec++)
986 df_ref use = *use_vec;
987 int regno = DF_REF_REGNO (use);
989 /* Do not consider the usage of the stack pointer
991 if (DF_REF_FLAGS (use) & DF_REF_CALL_STACK_USAGE)
994 next_use[regno] = insn;
1002 /* Clear LOG_LINKS fields of insns. */
1005 clear_log_links (void)
1009 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
1011 free_INSN_LIST_list (&LOG_LINKS (insn));
1017 /* Main entry point for combiner. F is the first insn of the function.
1018 NREGS is the first unused pseudo-reg number.
1020 Return nonzero if the combiner has turned an indirect jump
1021 instruction into a direct jump. */
1023 combine_instructions (rtx f, unsigned int nregs)
1029 rtx links, nextlinks;
1032 int new_direct_jump_p = 0;
1034 for (first = f; first && !INSN_P (first); )
1035 first = NEXT_INSN (first);
1039 combine_attempts = 0;
1042 combine_successes = 0;
1044 rtl_hooks = combine_rtl_hooks;
1046 VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
1048 init_recog_no_volatile ();
1050 /* Allocate array for insn info. */
1051 max_uid_known = get_max_uid ();
1052 uid_log_links = XCNEWVEC (rtx, max_uid_known + 1);
1053 uid_insn_cost = XCNEWVEC (int, max_uid_known + 1);
1055 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
1057 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1058 problems when, for example, we have j <<= 1 in a loop. */
1060 nonzero_sign_valid = 0;
1062 /* Scan all SETs and see if we can deduce anything about what
1063 bits are known to be zero for some registers and how many copies
1064 of the sign bit are known to exist for those registers.
1066 Also set any known values so that we can use it while searching
1067 for what bits are known to be set. */
1069 setup_incoming_promotions (first);
1071 create_log_links ();
1072 label_tick_ebb_start = ENTRY_BLOCK_PTR->index;
1073 FOR_EACH_BB (this_basic_block)
1075 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1078 label_tick = this_basic_block->index;
1079 if (!single_pred_p (this_basic_block)
1080 || single_pred (this_basic_block)->index != label_tick - 1)
1081 label_tick_ebb_start = label_tick;
1082 FOR_BB_INSNS (this_basic_block, insn)
1083 if (INSN_P (insn) && BLOCK_FOR_INSN (insn))
1085 subst_low_luid = DF_INSN_LUID (insn);
1088 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
1090 record_dead_and_set_regs (insn);
1093 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
1094 if (REG_NOTE_KIND (links) == REG_INC)
1095 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
1099 /* Record the current insn_rtx_cost of this instruction. */
1100 if (NONJUMP_INSN_P (insn))
1101 INSN_COST (insn) = insn_rtx_cost (PATTERN (insn),
1102 optimize_this_for_speed_p);
1104 fprintf(dump_file, "insn_cost %d: %d\n",
1105 INSN_UID (insn), INSN_COST (insn));
1109 nonzero_sign_valid = 1;
1111 /* Now scan all the insns in forward order. */
1113 label_tick_ebb_start = ENTRY_BLOCK_PTR->index;
1115 setup_incoming_promotions (first);
1117 FOR_EACH_BB (this_basic_block)
1119 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1122 label_tick = this_basic_block->index;
1123 if (!single_pred_p (this_basic_block)
1124 || single_pred (this_basic_block)->index != label_tick - 1)
1125 label_tick_ebb_start = label_tick;
1126 rtl_profile_for_bb (this_basic_block);
1127 for (insn = BB_HEAD (this_basic_block);
1128 insn != NEXT_INSN (BB_END (this_basic_block));
1129 insn = next ? next : NEXT_INSN (insn))
1134 /* See if we know about function return values before this
1135 insn based upon SUBREG flags. */
1136 check_promoted_subreg (insn, PATTERN (insn));
1138 /* See if we can find hardregs and subreg of pseudos in
1139 narrower modes. This could help turning TRUNCATEs
1141 note_uses (&PATTERN (insn), record_truncated_values, NULL);
1143 /* Try this insn with each insn it links back to. */
1145 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1146 if ((next = try_combine (insn, XEXP (links, 0),
1147 NULL_RTX, &new_direct_jump_p)) != 0)
1150 /* Try each sequence of three linked insns ending with this one. */
1152 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1154 rtx link = XEXP (links, 0);
1156 /* If the linked insn has been replaced by a note, then there
1157 is no point in pursuing this chain any further. */
1161 for (nextlinks = LOG_LINKS (link);
1163 nextlinks = XEXP (nextlinks, 1))
1164 if ((next = try_combine (insn, link,
1165 XEXP (nextlinks, 0),
1166 &new_direct_jump_p)) != 0)
1171 /* Try to combine a jump insn that uses CC0
1172 with a preceding insn that sets CC0, and maybe with its
1173 logical predecessor as well.
1174 This is how we make decrement-and-branch insns.
1175 We need this special code because data flow connections
1176 via CC0 do not get entered in LOG_LINKS. */
1179 && (prev = prev_nonnote_insn (insn)) != 0
1180 && NONJUMP_INSN_P (prev)
1181 && sets_cc0_p (PATTERN (prev)))
1183 if ((next = try_combine (insn, prev,
1184 NULL_RTX, &new_direct_jump_p)) != 0)
1187 for (nextlinks = LOG_LINKS (prev); nextlinks;
1188 nextlinks = XEXP (nextlinks, 1))
1189 if ((next = try_combine (insn, prev,
1190 XEXP (nextlinks, 0),
1191 &new_direct_jump_p)) != 0)
1195 /* Do the same for an insn that explicitly references CC0. */
1196 if (NONJUMP_INSN_P (insn)
1197 && (prev = prev_nonnote_insn (insn)) != 0
1198 && NONJUMP_INSN_P (prev)
1199 && sets_cc0_p (PATTERN (prev))
1200 && GET_CODE (PATTERN (insn)) == SET
1201 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
1203 if ((next = try_combine (insn, prev,
1204 NULL_RTX, &new_direct_jump_p)) != 0)
1207 for (nextlinks = LOG_LINKS (prev); nextlinks;
1208 nextlinks = XEXP (nextlinks, 1))
1209 if ((next = try_combine (insn, prev,
1210 XEXP (nextlinks, 0),
1211 &new_direct_jump_p)) != 0)
1215 /* Finally, see if any of the insns that this insn links to
1216 explicitly references CC0. If so, try this insn, that insn,
1217 and its predecessor if it sets CC0. */
1218 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1219 if (NONJUMP_INSN_P (XEXP (links, 0))
1220 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
1221 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
1222 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
1223 && NONJUMP_INSN_P (prev)
1224 && sets_cc0_p (PATTERN (prev))
1225 && (next = try_combine (insn, XEXP (links, 0),
1226 prev, &new_direct_jump_p)) != 0)
1230 /* Try combining an insn with two different insns whose results it
1232 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1233 for (nextlinks = XEXP (links, 1); nextlinks;
1234 nextlinks = XEXP (nextlinks, 1))
1235 if ((next = try_combine (insn, XEXP (links, 0),
1236 XEXP (nextlinks, 0),
1237 &new_direct_jump_p)) != 0)
1240 /* Try this insn with each REG_EQUAL note it links back to. */
1241 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1244 rtx temp = XEXP (links, 0);
1245 if ((set = single_set (temp)) != 0
1246 && (note = find_reg_equal_equiv_note (temp)) != 0
1247 && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
1248 /* Avoid using a register that may already been marked
1249 dead by an earlier instruction. */
1250 && ! unmentioned_reg_p (note, SET_SRC (set))
1251 && (GET_MODE (note) == VOIDmode
1252 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
1253 : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
1255 /* Temporarily replace the set's source with the
1256 contents of the REG_EQUAL note. The insn will
1257 be deleted or recognized by try_combine. */
1258 rtx orig = SET_SRC (set);
1259 SET_SRC (set) = note;
1261 i2mod_old_rhs = copy_rtx (orig);
1262 i2mod_new_rhs = copy_rtx (note);
1263 next = try_combine (insn, i2mod, NULL_RTX,
1264 &new_direct_jump_p);
1268 SET_SRC (set) = orig;
1273 record_dead_and_set_regs (insn);
1281 default_rtl_profile ();
1284 new_direct_jump_p |= purge_all_dead_edges ();
1285 delete_noop_moves ();
1288 free (uid_log_links);
1289 free (uid_insn_cost);
1290 VEC_free (reg_stat_type, heap, reg_stat);
1293 struct undo *undo, *next;
1294 for (undo = undobuf.frees; undo; undo = next)
1302 total_attempts += combine_attempts;
1303 total_merges += combine_merges;
1304 total_extras += combine_extras;
1305 total_successes += combine_successes;
1307 nonzero_sign_valid = 0;
1308 rtl_hooks = general_rtl_hooks;
1310 /* Make recognizer allow volatile MEMs again. */
1313 return new_direct_jump_p;
1316 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1319 init_reg_last (void)
1324 for (i = 0; VEC_iterate (reg_stat_type, reg_stat, i, p); ++i)
1325 memset (p, 0, offsetof (reg_stat_type, sign_bit_copies));
1328 /* Set up any promoted values for incoming argument registers. */
1331 setup_incoming_promotions (rtx first)
1334 bool strictly_local = false;
1336 if (!targetm.calls.promote_function_args (TREE_TYPE (cfun->decl)))
1339 for (arg = DECL_ARGUMENTS (current_function_decl); arg;
1340 arg = TREE_CHAIN (arg))
1342 rtx reg = DECL_INCOMING_RTL (arg);
1344 enum machine_mode mode1, mode2, mode3, mode4;
1346 /* Only continue if the incoming argument is in a register. */
1350 /* Determine, if possible, whether all call sites of the current
1351 function lie within the current compilation unit. (This does
1352 take into account the exporting of a function via taking its
1353 address, and so forth.) */
1354 strictly_local = cgraph_local_info (current_function_decl)->local;
1356 /* The mode and signedness of the argument before any promotions happen
1357 (equal to the mode of the pseudo holding it at that stage). */
1358 mode1 = TYPE_MODE (TREE_TYPE (arg));
1359 uns1 = TYPE_UNSIGNED (TREE_TYPE (arg));
1361 /* The mode and signedness of the argument after any source language and
1362 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1363 mode2 = TYPE_MODE (DECL_ARG_TYPE (arg));
1364 uns3 = TYPE_UNSIGNED (DECL_ARG_TYPE (arg));
1366 /* The mode and signedness of the argument as it is actually passed,
1367 after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions. */
1368 mode3 = promote_mode (DECL_ARG_TYPE (arg), mode2, &uns3, 1);
1370 /* The mode of the register in which the argument is being passed. */
1371 mode4 = GET_MODE (reg);
1373 /* Eliminate sign extensions in the callee when possible. Only
1375 (a) a mode promotion has occurred;
1376 (b) the mode of the register is the same as the mode of
1377 the argument as it is passed; and
1378 (c) the signedness does not change across any of the promotions; and
1379 (d) when no language-level promotions (which we cannot guarantee
1380 will have been done by an external caller) are necessary,
1381 unless we know that this function is only ever called from
1382 the current compilation unit -- all of whose call sites will
1383 do the mode1 --> mode2 promotion. */
1387 && (mode1 == mode2 || strictly_local))
1389 /* Record that the value was promoted from mode1 to mode3,
1390 so that any sign extension at the head of the current
1391 function may be eliminated. */
1393 x = gen_rtx_CLOBBER (mode1, const0_rtx);
1394 x = gen_rtx_fmt_e ((uns3 ? ZERO_EXTEND : SIGN_EXTEND), mode3, x);
1395 record_value_for_reg (reg, first, x);
1400 /* Called via note_stores. If X is a pseudo that is narrower than
1401 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1403 If we are setting only a portion of X and we can't figure out what
1404 portion, assume all bits will be used since we don't know what will
1407 Similarly, set how many bits of X are known to be copies of the sign bit
1408 at all locations in the function. This is the smallest number implied
1412 set_nonzero_bits_and_sign_copies (rtx x, const_rtx set, void *data)
1414 rtx insn = (rtx) data;
1418 && REGNO (x) >= FIRST_PSEUDO_REGISTER
1419 /* If this register is undefined at the start of the file, we can't
1420 say what its contents were. */
1421 && ! REGNO_REG_SET_P
1422 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x))
1423 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
1425 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
1427 if (set == 0 || GET_CODE (set) == CLOBBER)
1429 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1430 rsp->sign_bit_copies = 1;
1434 /* If this register is being initialized using itself, and the
1435 register is uninitialized in this basic block, and there are
1436 no LOG_LINKS which set the register, then part of the
1437 register is uninitialized. In that case we can't assume
1438 anything about the number of nonzero bits.
1440 ??? We could do better if we checked this in
1441 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1442 could avoid making assumptions about the insn which initially
1443 sets the register, while still using the information in other
1444 insns. We would have to be careful to check every insn
1445 involved in the combination. */
1448 && reg_referenced_p (x, PATTERN (insn))
1449 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn)),
1454 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
1456 if (dead_or_set_p (XEXP (link, 0), x))
1461 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1462 rsp->sign_bit_copies = 1;
1467 /* If this is a complex assignment, see if we can convert it into a
1468 simple assignment. */
1469 set = expand_field_assignment (set);
1471 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1472 set what we know about X. */
1474 if (SET_DEST (set) == x
1475 || (GET_CODE (SET_DEST (set)) == SUBREG
1476 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
1477 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
1478 && SUBREG_REG (SET_DEST (set)) == x))
1480 rtx src = SET_SRC (set);
1482 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1483 /* If X is narrower than a word and SRC is a non-negative
1484 constant that would appear negative in the mode of X,
1485 sign-extend it for use in reg_stat[].nonzero_bits because some
1486 machines (maybe most) will actually do the sign-extension
1487 and this is the conservative approach.
1489 ??? For 2.5, try to tighten up the MD files in this regard
1490 instead of this kludge. */
1492 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
1493 && GET_CODE (src) == CONST_INT
1495 && 0 != (INTVAL (src)
1496 & ((HOST_WIDE_INT) 1
1497 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
1498 src = GEN_INT (INTVAL (src)
1499 | ((HOST_WIDE_INT) (-1)
1500 << GET_MODE_BITSIZE (GET_MODE (x))));
1503 /* Don't call nonzero_bits if it cannot change anything. */
1504 if (rsp->nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1505 rsp->nonzero_bits |= nonzero_bits (src, nonzero_bits_mode);
1506 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1507 if (rsp->sign_bit_copies == 0
1508 || rsp->sign_bit_copies > num)
1509 rsp->sign_bit_copies = num;
1513 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1514 rsp->sign_bit_copies = 1;
1519 /* See if INSN can be combined into I3. PRED and SUCC are optionally
1520 insns that were previously combined into I3 or that will be combined
1521 into the merger of INSN and I3.
1523 Return 0 if the combination is not allowed for any reason.
1525 If the combination is allowed, *PDEST will be set to the single
1526 destination of INSN and *PSRC to the single source, and this function
1530 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED, rtx succ,
1531 rtx *pdest, rtx *psrc)
1540 int all_adjacent = (succ ? (next_active_insn (insn) == succ
1541 && next_active_insn (succ) == i3)
1542 : next_active_insn (insn) == i3);
1544 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1545 or a PARALLEL consisting of such a SET and CLOBBERs.
1547 If INSN has CLOBBER parallel parts, ignore them for our processing.
1548 By definition, these happen during the execution of the insn. When it
1549 is merged with another insn, all bets are off. If they are, in fact,
1550 needed and aren't also supplied in I3, they may be added by
1551 recog_for_combine. Otherwise, it won't match.
1553 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1556 Get the source and destination of INSN. If more than one, can't
1559 if (GET_CODE (PATTERN (insn)) == SET)
1560 set = PATTERN (insn);
1561 else if (GET_CODE (PATTERN (insn)) == PARALLEL
1562 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1564 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1566 rtx elt = XVECEXP (PATTERN (insn), 0, i);
1569 switch (GET_CODE (elt))
1571 /* This is important to combine floating point insns
1572 for the SH4 port. */
1574 /* Combining an isolated USE doesn't make sense.
1575 We depend here on combinable_i3pat to reject them. */
1576 /* The code below this loop only verifies that the inputs of
1577 the SET in INSN do not change. We call reg_set_between_p
1578 to verify that the REG in the USE does not change between
1580 If the USE in INSN was for a pseudo register, the matching
1581 insn pattern will likely match any register; combining this
1582 with any other USE would only be safe if we knew that the
1583 used registers have identical values, or if there was
1584 something to tell them apart, e.g. different modes. For
1585 now, we forgo such complicated tests and simply disallow
1586 combining of USES of pseudo registers with any other USE. */
1587 if (REG_P (XEXP (elt, 0))
1588 && GET_CODE (PATTERN (i3)) == PARALLEL)
1590 rtx i3pat = PATTERN (i3);
1591 int i = XVECLEN (i3pat, 0) - 1;
1592 unsigned int regno = REGNO (XEXP (elt, 0));
1596 rtx i3elt = XVECEXP (i3pat, 0, i);
1598 if (GET_CODE (i3elt) == USE
1599 && REG_P (XEXP (i3elt, 0))
1600 && (REGNO (XEXP (i3elt, 0)) == regno
1601 ? reg_set_between_p (XEXP (elt, 0),
1602 PREV_INSN (insn), i3)
1603 : regno >= FIRST_PSEUDO_REGISTER))
1610 /* We can ignore CLOBBERs. */
1615 /* Ignore SETs whose result isn't used but not those that
1616 have side-effects. */
1617 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1618 && (!(note = find_reg_note (insn, REG_EH_REGION, NULL_RTX))
1619 || INTVAL (XEXP (note, 0)) <= 0)
1620 && ! side_effects_p (elt))
1623 /* If we have already found a SET, this is a second one and
1624 so we cannot combine with this insn. */
1632 /* Anything else means we can't combine. */
1638 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1639 so don't do anything with it. */
1640 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1649 set = expand_field_assignment (set);
1650 src = SET_SRC (set), dest = SET_DEST (set);
1652 /* Don't eliminate a store in the stack pointer. */
1653 if (dest == stack_pointer_rtx
1654 /* Don't combine with an insn that sets a register to itself if it has
1655 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1656 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1657 /* Can't merge an ASM_OPERANDS. */
1658 || GET_CODE (src) == ASM_OPERANDS
1659 /* Can't merge a function call. */
1660 || GET_CODE (src) == CALL
1661 /* Don't eliminate a function call argument. */
1663 && (find_reg_fusage (i3, USE, dest)
1665 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1666 && global_regs[REGNO (dest)])))
1667 /* Don't substitute into an incremented register. */
1668 || FIND_REG_INC_NOTE (i3, dest)
1669 || (succ && FIND_REG_INC_NOTE (succ, dest))
1670 /* Don't substitute into a non-local goto, this confuses CFG. */
1671 || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1672 /* Make sure that DEST is not used after SUCC but before I3. */
1673 || (succ && ! all_adjacent
1674 && reg_used_between_p (dest, succ, i3))
1675 /* Make sure that the value that is to be substituted for the register
1676 does not use any registers whose values alter in between. However,
1677 If the insns are adjacent, a use can't cross a set even though we
1678 think it might (this can happen for a sequence of insns each setting
1679 the same destination; last_set of that register might point to
1680 a NOTE). If INSN has a REG_EQUIV note, the register is always
1681 equivalent to the memory so the substitution is valid even if there
1682 are intervening stores. Also, don't move a volatile asm or
1683 UNSPEC_VOLATILE across any other insns. */
1686 || ! find_reg_note (insn, REG_EQUIV, src))
1687 && use_crosses_set_p (src, DF_INSN_LUID (insn)))
1688 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1689 || GET_CODE (src) == UNSPEC_VOLATILE))
1690 /* Don't combine across a CALL_INSN, because that would possibly
1691 change whether the life span of some REGs crosses calls or not,
1692 and it is a pain to update that information.
1693 Exception: if source is a constant, moving it later can't hurt.
1694 Accept that as a special case. */
1695 || (DF_INSN_LUID (insn) < last_call_luid && ! CONSTANT_P (src)))
1698 /* DEST must either be a REG or CC0. */
1701 /* If register alignment is being enforced for multi-word items in all
1702 cases except for parameters, it is possible to have a register copy
1703 insn referencing a hard register that is not allowed to contain the
1704 mode being copied and which would not be valid as an operand of most
1705 insns. Eliminate this problem by not combining with such an insn.
1707 Also, on some machines we don't want to extend the life of a hard
1711 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1712 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1713 /* Don't extend the life of a hard register unless it is
1714 user variable (if we have few registers) or it can't
1715 fit into the desired register (meaning something special
1717 Also avoid substituting a return register into I3, because
1718 reload can't handle a conflict with constraints of other
1720 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1721 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1724 else if (GET_CODE (dest) != CC0)
1728 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1729 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1730 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1732 /* Don't substitute for a register intended as a clobberable
1734 rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1735 if (rtx_equal_p (reg, dest))
1738 /* If the clobber represents an earlyclobber operand, we must not
1739 substitute an expression containing the clobbered register.
1740 As we do not analyze the constraint strings here, we have to
1741 make the conservative assumption. However, if the register is
1742 a fixed hard reg, the clobber cannot represent any operand;
1743 we leave it up to the machine description to either accept or
1744 reject use-and-clobber patterns. */
1746 || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1747 || !fixed_regs[REGNO (reg)])
1748 if (reg_overlap_mentioned_p (reg, src))
1752 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1753 or not), reject, unless nothing volatile comes between it and I3 */
1755 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1757 /* Make sure succ doesn't contain a volatile reference. */
1758 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1761 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1762 if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1766 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1767 to be an explicit register variable, and was chosen for a reason. */
1769 if (GET_CODE (src) == ASM_OPERANDS
1770 && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1773 /* If there are any volatile insns between INSN and I3, reject, because
1774 they might affect machine state. */
1776 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1777 if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1780 /* If INSN contains an autoincrement or autodecrement, make sure that
1781 register is not used between there and I3, and not already used in
1782 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1783 Also insist that I3 not be a jump; if it were one
1784 and the incremented register were spilled, we would lose. */
1787 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1788 if (REG_NOTE_KIND (link) == REG_INC
1790 || reg_used_between_p (XEXP (link, 0), insn, i3)
1791 || (pred != NULL_RTX
1792 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
1793 || (succ != NULL_RTX
1794 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
1795 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1800 /* Don't combine an insn that follows a CC0-setting insn.
1801 An insn that uses CC0 must not be separated from the one that sets it.
1802 We do, however, allow I2 to follow a CC0-setting insn if that insn
1803 is passed as I1; in that case it will be deleted also.
1804 We also allow combining in this case if all the insns are adjacent
1805 because that would leave the two CC0 insns adjacent as well.
1806 It would be more logical to test whether CC0 occurs inside I1 or I2,
1807 but that would be much slower, and this ought to be equivalent. */
1809 p = prev_nonnote_insn (insn);
1810 if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
1815 /* If we get here, we have passed all the tests and the combination is
1824 /* LOC is the location within I3 that contains its pattern or the component
1825 of a PARALLEL of the pattern. We validate that it is valid for combining.
1827 One problem is if I3 modifies its output, as opposed to replacing it
1828 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1829 so would produce an insn that is not equivalent to the original insns.
1833 (set (reg:DI 101) (reg:DI 100))
1834 (set (subreg:SI (reg:DI 101) 0) <foo>)
1836 This is NOT equivalent to:
1838 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1839 (set (reg:DI 101) (reg:DI 100))])
1841 Not only does this modify 100 (in which case it might still be valid
1842 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1844 We can also run into a problem if I2 sets a register that I1
1845 uses and I1 gets directly substituted into I3 (not via I2). In that
1846 case, we would be getting the wrong value of I2DEST into I3, so we
1847 must reject the combination. This case occurs when I2 and I1 both
1848 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1849 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1850 of a SET must prevent combination from occurring.
1852 Before doing the above check, we first try to expand a field assignment
1853 into a set of logical operations.
1855 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1856 we place a register that is both set and used within I3. If more than one
1857 such register is detected, we fail.
1859 Return 1 if the combination is valid, zero otherwise. */
1862 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest,
1863 int i1_not_in_src, rtx *pi3dest_killed)
1867 if (GET_CODE (x) == SET)
1870 rtx dest = SET_DEST (set);
1871 rtx src = SET_SRC (set);
1872 rtx inner_dest = dest;
1875 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1876 || GET_CODE (inner_dest) == SUBREG
1877 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1878 inner_dest = XEXP (inner_dest, 0);
1880 /* Check for the case where I3 modifies its output, as discussed
1881 above. We don't want to prevent pseudos from being combined
1882 into the address of a MEM, so only prevent the combination if
1883 i1 or i2 set the same MEM. */
1884 if ((inner_dest != dest &&
1885 (!MEM_P (inner_dest)
1886 || rtx_equal_p (i2dest, inner_dest)
1887 || (i1dest && rtx_equal_p (i1dest, inner_dest)))
1888 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1889 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1891 /* This is the same test done in can_combine_p except we can't test
1892 all_adjacent; we don't have to, since this instruction will stay
1893 in place, thus we are not considering increasing the lifetime of
1896 Also, if this insn sets a function argument, combining it with
1897 something that might need a spill could clobber a previous
1898 function argument; the all_adjacent test in can_combine_p also
1899 checks this; here, we do a more specific test for this case. */
1901 || (REG_P (inner_dest)
1902 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1903 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1904 GET_MODE (inner_dest))))
1905 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1908 /* If DEST is used in I3, it is being killed in this insn, so
1909 record that for later. We have to consider paradoxical
1910 subregs here, since they kill the whole register, but we
1911 ignore partial subregs, STRICT_LOW_PART, etc.
1912 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1913 STACK_POINTER_REGNUM, since these are always considered to be
1914 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1916 if (GET_CODE (subdest) == SUBREG
1917 && (GET_MODE_SIZE (GET_MODE (subdest))
1918 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
1919 subdest = SUBREG_REG (subdest);
1922 && reg_referenced_p (subdest, PATTERN (i3))
1923 && REGNO (subdest) != FRAME_POINTER_REGNUM
1924 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1925 && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
1927 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1928 && (REGNO (subdest) != ARG_POINTER_REGNUM
1929 || ! fixed_regs [REGNO (subdest)])
1931 && REGNO (subdest) != STACK_POINTER_REGNUM)
1933 if (*pi3dest_killed)
1936 *pi3dest_killed = subdest;
1940 else if (GET_CODE (x) == PARALLEL)
1944 for (i = 0; i < XVECLEN (x, 0); i++)
1945 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1946 i1_not_in_src, pi3dest_killed))
1953 /* Return 1 if X is an arithmetic expression that contains a multiplication
1954 and division. We don't count multiplications by powers of two here. */
1957 contains_muldiv (rtx x)
1959 switch (GET_CODE (x))
1961 case MOD: case DIV: case UMOD: case UDIV:
1965 return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1966 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1969 return contains_muldiv (XEXP (x, 0))
1970 || contains_muldiv (XEXP (x, 1));
1973 return contains_muldiv (XEXP (x, 0));
1979 /* Determine whether INSN can be used in a combination. Return nonzero if
1980 not. This is used in try_combine to detect early some cases where we
1981 can't perform combinations. */
1984 cant_combine_insn_p (rtx insn)
1989 /* If this isn't really an insn, we can't do anything.
1990 This can occur when flow deletes an insn that it has merged into an
1991 auto-increment address. */
1992 if (! INSN_P (insn))
1995 /* Never combine loads and stores involving hard regs that are likely
1996 to be spilled. The register allocator can usually handle such
1997 reg-reg moves by tying. If we allow the combiner to make
1998 substitutions of likely-spilled regs, reload might die.
1999 As an exception, we allow combinations involving fixed regs; these are
2000 not available to the register allocator so there's no risk involved. */
2002 set = single_set (insn);
2005 src = SET_SRC (set);
2006 dest = SET_DEST (set);
2007 if (GET_CODE (src) == SUBREG)
2008 src = SUBREG_REG (src);
2009 if (GET_CODE (dest) == SUBREG)
2010 dest = SUBREG_REG (dest);
2011 if (REG_P (src) && REG_P (dest)
2012 && ((REGNO (src) < FIRST_PSEUDO_REGISTER
2013 && ! fixed_regs[REGNO (src)]
2014 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src))))
2015 || (REGNO (dest) < FIRST_PSEUDO_REGISTER
2016 && ! fixed_regs[REGNO (dest)]
2017 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest))))))
2023 struct likely_spilled_retval_info
2025 unsigned regno, nregs;
2029 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2030 hard registers that are known to be written to / clobbered in full. */
2032 likely_spilled_retval_1 (rtx x, const_rtx set, void *data)
2034 struct likely_spilled_retval_info *const info =
2035 (struct likely_spilled_retval_info *) data;
2036 unsigned regno, nregs;
2039 if (!REG_P (XEXP (set, 0)))
2042 if (regno >= info->regno + info->nregs)
2044 nregs = hard_regno_nregs[regno][GET_MODE (x)];
2045 if (regno + nregs <= info->regno)
2047 new_mask = (2U << (nregs - 1)) - 1;
2048 if (regno < info->regno)
2049 new_mask >>= info->regno - regno;
2051 new_mask <<= regno - info->regno;
2052 info->mask &= ~new_mask;
2055 /* Return nonzero iff part of the return value is live during INSN, and
2056 it is likely spilled. This can happen when more than one insn is needed
2057 to copy the return value, e.g. when we consider to combine into the
2058 second copy insn for a complex value. */
2061 likely_spilled_retval_p (rtx insn)
2063 rtx use = BB_END (this_basic_block);
2065 unsigned regno, nregs;
2066 /* We assume here that no machine mode needs more than
2067 32 hard registers when the value overlaps with a register
2068 for which FUNCTION_VALUE_REGNO_P is true. */
2070 struct likely_spilled_retval_info info;
2072 if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
2074 reg = XEXP (PATTERN (use), 0);
2075 if (!REG_P (reg) || !FUNCTION_VALUE_REGNO_P (REGNO (reg)))
2077 regno = REGNO (reg);
2078 nregs = hard_regno_nregs[regno][GET_MODE (reg)];
2081 mask = (2U << (nregs - 1)) - 1;
2083 /* Disregard parts of the return value that are set later. */
2087 for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
2089 note_stores (PATTERN (p), likely_spilled_retval_1, &info);
2092 /* Check if any of the (probably) live return value registers is
2097 if ((mask & 1 << nregs)
2098 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (regno + nregs)))
2104 /* Adjust INSN after we made a change to its destination.
2106 Changing the destination can invalidate notes that say something about
2107 the results of the insn and a LOG_LINK pointing to the insn. */
2110 adjust_for_new_dest (rtx insn)
2112 /* For notes, be conservative and simply remove them. */
2113 remove_reg_equal_equiv_notes (insn);
2115 /* The new insn will have a destination that was previously the destination
2116 of an insn just above it. Call distribute_links to make a LOG_LINK from
2117 the next use of that destination. */
2118 distribute_links (gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX));
2120 df_insn_rescan (insn);
2123 /* Return TRUE if combine can reuse reg X in mode MODE.
2124 ADDED_SETS is nonzero if the original set is still required. */
2126 can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode)
2134 /* Allow hard registers if the new mode is legal, and occupies no more
2135 registers than the old mode. */
2136 if (regno < FIRST_PSEUDO_REGISTER)
2137 return (HARD_REGNO_MODE_OK (regno, mode)
2138 && (hard_regno_nregs[regno][GET_MODE (x)]
2139 >= hard_regno_nregs[regno][mode]));
2141 /* Or a pseudo that is only used once. */
2142 return (REG_N_SETS (regno) == 1 && !added_sets
2143 && !REG_USERVAR_P (x));
2147 /* Check whether X, the destination of a set, refers to part of
2148 the register specified by REG. */
2151 reg_subword_p (rtx x, rtx reg)
2153 /* Check that reg is an integer mode register. */
2154 if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
2157 if (GET_CODE (x) == STRICT_LOW_PART
2158 || GET_CODE (x) == ZERO_EXTRACT)
2161 return GET_CODE (x) == SUBREG
2162 && SUBREG_REG (x) == reg
2163 && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
2167 /* Delete the conditional jump INSN and adjust the CFG correspondingly.
2168 Note that the INSN should be deleted *after* removing dead edges, so
2169 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2170 but not for a (set (pc) (label_ref FOO)). */
2173 update_cfg_for_uncondjump (rtx insn)
2175 basic_block bb = BLOCK_FOR_INSN (insn);
2177 if (BB_END (bb) == insn)
2178 purge_dead_edges (bb);
2181 if (EDGE_COUNT (bb->succs) == 1)
2182 single_succ_edge (bb)->flags |= EDGE_FALLTHRU;
2186 /* Try to combine the insns I1 and I2 into I3.
2187 Here I1 and I2 appear earlier than I3.
2188 I1 can be zero; then we combine just I2 into I3.
2190 If we are combining three insns and the resulting insn is not recognized,
2191 try splitting it into two insns. If that happens, I2 and I3 are retained
2192 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
2195 Return 0 if the combination does not work. Then nothing is changed.
2196 If we did the combination, return the insn at which combine should
2199 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2200 new direct jump instruction. */
2203 try_combine (rtx i3, rtx i2, rtx i1, int *new_direct_jump_p)
2205 /* New patterns for I3 and I2, respectively. */
2206 rtx newpat, newi2pat = 0;
2207 rtvec newpat_vec_with_clobbers = 0;
2208 int substed_i2 = 0, substed_i1 = 0;
2209 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
2210 int added_sets_1, added_sets_2;
2211 /* Total number of SETs to put into I3. */
2213 /* Nonzero if I2's body now appears in I3. */
2215 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2216 int insn_code_number, i2_code_number = 0, other_code_number = 0;
2217 /* Contains I3 if the destination of I3 is used in its source, which means
2218 that the old life of I3 is being killed. If that usage is placed into
2219 I2 and not in I3, a REG_DEAD note must be made. */
2220 rtx i3dest_killed = 0;
2221 /* SET_DEST and SET_SRC of I2 and I1. */
2222 rtx i2dest, i2src, i1dest = 0, i1src = 0;
2223 /* PATTERN (I1) and PATTERN (I2), or a copy of it in certain cases. */
2224 rtx i1pat = 0, i2pat = 0;
2225 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2226 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
2227 int i2dest_killed = 0, i1dest_killed = 0;
2228 int i1_feeds_i3 = 0;
2229 /* Notes that must be added to REG_NOTES in I3 and I2. */
2230 rtx new_i3_notes, new_i2_notes;
2231 /* Notes that we substituted I3 into I2 instead of the normal case. */
2232 int i3_subst_into_i2 = 0;
2233 /* Notes that I1, I2 or I3 is a MULT operation. */
2236 int changed_i3_dest = 0;
2242 rtx new_other_notes;
2245 /* Exit early if one of the insns involved can't be used for
2247 if (cant_combine_insn_p (i3)
2248 || cant_combine_insn_p (i2)
2249 || (i1 && cant_combine_insn_p (i1))
2250 || likely_spilled_retval_p (i3))
2254 undobuf.other_insn = 0;
2256 /* Reset the hard register usage information. */
2257 CLEAR_HARD_REG_SET (newpat_used_regs);
2259 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
2260 code below, set I1 to be the earlier of the two insns. */
2261 if (i1 && DF_INSN_LUID (i1) > DF_INSN_LUID (i2))
2262 temp = i1, i1 = i2, i2 = temp;
2264 added_links_insn = 0;
2266 /* First check for one important special-case that the code below will
2267 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2268 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2269 we may be able to replace that destination with the destination of I3.
2270 This occurs in the common code where we compute both a quotient and
2271 remainder into a structure, in which case we want to do the computation
2272 directly into the structure to avoid register-register copies.
2274 Note that this case handles both multiple sets in I2 and also
2275 cases where I2 has a number of CLOBBER or PARALLELs.
2277 We make very conservative checks below and only try to handle the
2278 most common cases of this. For example, we only handle the case
2279 where I2 and I3 are adjacent to avoid making difficult register
2282 if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
2283 && REG_P (SET_SRC (PATTERN (i3)))
2284 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
2285 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
2286 && GET_CODE (PATTERN (i2)) == PARALLEL
2287 && ! side_effects_p (SET_DEST (PATTERN (i3)))
2288 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2289 below would need to check what is inside (and reg_overlap_mentioned_p
2290 doesn't support those codes anyway). Don't allow those destinations;
2291 the resulting insn isn't likely to be recognized anyway. */
2292 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
2293 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
2294 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
2295 SET_DEST (PATTERN (i3)))
2296 && next_real_insn (i2) == i3)
2298 rtx p2 = PATTERN (i2);
2300 /* Make sure that the destination of I3,
2301 which we are going to substitute into one output of I2,
2302 is not used within another output of I2. We must avoid making this:
2303 (parallel [(set (mem (reg 69)) ...)
2304 (set (reg 69) ...)])
2305 which is not well-defined as to order of actions.
2306 (Besides, reload can't handle output reloads for this.)
2308 The problem can also happen if the dest of I3 is a memory ref,
2309 if another dest in I2 is an indirect memory ref. */
2310 for (i = 0; i < XVECLEN (p2, 0); i++)
2311 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2312 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2313 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
2314 SET_DEST (XVECEXP (p2, 0, i))))
2317 if (i == XVECLEN (p2, 0))
2318 for (i = 0; i < XVECLEN (p2, 0); i++)
2319 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2320 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2321 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
2326 subst_low_luid = DF_INSN_LUID (i2);
2328 added_sets_2 = added_sets_1 = 0;
2329 i2dest = SET_SRC (PATTERN (i3));
2330 i2dest_killed = dead_or_set_p (i2, i2dest);
2332 /* Replace the dest in I2 with our dest and make the resulting
2333 insn the new pattern for I3. Then skip to where we
2334 validate the pattern. Everything was set up above. */
2335 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
2336 SET_DEST (PATTERN (i3)));
2339 i3_subst_into_i2 = 1;
2340 goto validate_replacement;
2344 /* If I2 is setting a pseudo to a constant and I3 is setting some
2345 sub-part of it to another constant, merge them by making a new
2348 && (temp = single_set (i2)) != 0
2349 && (GET_CODE (SET_SRC (temp)) == CONST_INT
2350 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
2351 && GET_CODE (PATTERN (i3)) == SET
2352 && (GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT
2353 || GET_CODE (SET_SRC (PATTERN (i3))) == CONST_DOUBLE)
2354 && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp)))
2356 rtx dest = SET_DEST (PATTERN (i3));
2360 if (GET_CODE (dest) == ZERO_EXTRACT)
2362 if (GET_CODE (XEXP (dest, 1)) == CONST_INT
2363 && GET_CODE (XEXP (dest, 2)) == CONST_INT)
2365 width = INTVAL (XEXP (dest, 1));
2366 offset = INTVAL (XEXP (dest, 2));
2367 dest = XEXP (dest, 0);
2368 if (BITS_BIG_ENDIAN)
2369 offset = GET_MODE_BITSIZE (GET_MODE (dest)) - width - offset;
2374 if (GET_CODE (dest) == STRICT_LOW_PART)
2375 dest = XEXP (dest, 0);
2376 width = GET_MODE_BITSIZE (GET_MODE (dest));
2382 /* If this is the low part, we're done. */
2383 if (subreg_lowpart_p (dest))
2385 /* Handle the case where inner is twice the size of outer. */
2386 else if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
2387 == 2 * GET_MODE_BITSIZE (GET_MODE (dest)))
2388 offset += GET_MODE_BITSIZE (GET_MODE (dest));
2389 /* Otherwise give up for now. */
2395 && (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
2396 <= HOST_BITS_PER_WIDE_INT * 2))
2398 HOST_WIDE_INT mhi, ohi, ihi;
2399 HOST_WIDE_INT mlo, olo, ilo;
2400 rtx inner = SET_SRC (PATTERN (i3));
2401 rtx outer = SET_SRC (temp);
2403 if (GET_CODE (outer) == CONST_INT)
2405 olo = INTVAL (outer);
2406 ohi = olo < 0 ? -1 : 0;
2410 olo = CONST_DOUBLE_LOW (outer);
2411 ohi = CONST_DOUBLE_HIGH (outer);
2414 if (GET_CODE (inner) == CONST_INT)
2416 ilo = INTVAL (inner);
2417 ihi = ilo < 0 ? -1 : 0;
2421 ilo = CONST_DOUBLE_LOW (inner);
2422 ihi = CONST_DOUBLE_HIGH (inner);
2425 if (width < HOST_BITS_PER_WIDE_INT)
2427 mlo = ((unsigned HOST_WIDE_INT) 1 << width) - 1;
2430 else if (width < HOST_BITS_PER_WIDE_INT * 2)
2432 mhi = ((unsigned HOST_WIDE_INT) 1
2433 << (width - HOST_BITS_PER_WIDE_INT)) - 1;
2445 if (offset >= HOST_BITS_PER_WIDE_INT)
2447 mhi = mlo << (offset - HOST_BITS_PER_WIDE_INT);
2449 ihi = ilo << (offset - HOST_BITS_PER_WIDE_INT);
2452 else if (offset > 0)
2454 mhi = (mhi << offset) | ((unsigned HOST_WIDE_INT) mlo
2455 >> (HOST_BITS_PER_WIDE_INT - offset));
2456 mlo = mlo << offset;
2457 ihi = (ihi << offset) | ((unsigned HOST_WIDE_INT) ilo
2458 >> (HOST_BITS_PER_WIDE_INT - offset));
2459 ilo = ilo << offset;
2462 olo = (olo & ~mlo) | ilo;
2463 ohi = (ohi & ~mhi) | ihi;
2467 subst_low_luid = DF_INSN_LUID (i2);
2468 added_sets_2 = added_sets_1 = 0;
2469 i2dest = SET_DEST (temp);
2470 i2dest_killed = dead_or_set_p (i2, i2dest);
2472 SUBST (SET_SRC (temp),
2473 immed_double_const (olo, ohi, GET_MODE (SET_DEST (temp))));
2475 newpat = PATTERN (i2);
2476 goto validate_replacement;
2481 /* If we have no I1 and I2 looks like:
2482 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2484 make up a dummy I1 that is
2487 (set (reg:CC X) (compare:CC Y (const_int 0)))
2489 (We can ignore any trailing CLOBBERs.)
2491 This undoes a previous combination and allows us to match a branch-and-
2494 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
2495 && XVECLEN (PATTERN (i2), 0) >= 2
2496 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
2497 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2499 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2500 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2501 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
2502 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
2503 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2504 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
2506 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
2507 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
2512 /* We make I1 with the same INSN_UID as I2. This gives it
2513 the same DF_INSN_LUID for value tracking. Our fake I1 will
2514 never appear in the insn stream so giving it the same INSN_UID
2515 as I2 will not cause a problem. */
2517 i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
2518 BLOCK_FOR_INSN (i2), INSN_LOCATOR (i2),
2519 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX);
2521 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2522 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2523 SET_DEST (PATTERN (i1)));
2528 /* Verify that I2 and I1 are valid for combining. */
2529 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
2530 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
2536 /* Record whether I2DEST is used in I2SRC and similarly for the other
2537 cases. Knowing this will help in register status updating below. */
2538 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2539 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2540 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2541 i2dest_killed = dead_or_set_p (i2, i2dest);
2542 i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2544 /* See if I1 directly feeds into I3. It does if I1DEST is not used
2546 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
2548 /* Ensure that I3's pattern can be the destination of combines. */
2549 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
2550 i1 && i2dest_in_i1src && i1_feeds_i3,
2557 /* See if any of the insns is a MULT operation. Unless one is, we will
2558 reject a combination that is, since it must be slower. Be conservative
2560 if (GET_CODE (i2src) == MULT
2561 || (i1 != 0 && GET_CODE (i1src) == MULT)
2562 || (GET_CODE (PATTERN (i3)) == SET
2563 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
2566 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2567 We used to do this EXCEPT in one case: I3 has a post-inc in an
2568 output operand. However, that exception can give rise to insns like
2570 which is a famous insn on the PDP-11 where the value of r3 used as the
2571 source was model-dependent. Avoid this sort of thing. */
2574 if (!(GET_CODE (PATTERN (i3)) == SET
2575 && REG_P (SET_SRC (PATTERN (i3)))
2576 && MEM_P (SET_DEST (PATTERN (i3)))
2577 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
2578 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
2579 /* It's not the exception. */
2582 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
2583 if (REG_NOTE_KIND (link) == REG_INC
2584 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
2586 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
2593 /* See if the SETs in I1 or I2 need to be kept around in the merged
2594 instruction: whenever the value set there is still needed past I3.
2595 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2597 For the SET in I1, we have two cases: If I1 and I2 independently
2598 feed into I3, the set in I1 needs to be kept around if I1DEST dies
2599 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2600 in I1 needs to be kept around unless I1DEST dies or is set in either
2601 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
2602 I1DEST. If so, we know I1 feeds into I2. */
2604 added_sets_2 = ! dead_or_set_p (i3, i2dest);
2607 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
2608 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
2610 /* If the set in I2 needs to be kept around, we must make a copy of
2611 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2612 PATTERN (I2), we are only substituting for the original I1DEST, not into
2613 an already-substituted copy. This also prevents making self-referential
2614 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2619 if (GET_CODE (PATTERN (i2)) == PARALLEL)
2620 i2pat = gen_rtx_SET (VOIDmode, i2dest, copy_rtx (i2src));
2622 i2pat = copy_rtx (PATTERN (i2));
2627 if (GET_CODE (PATTERN (i1)) == PARALLEL)
2628 i1pat = gen_rtx_SET (VOIDmode, i1dest, copy_rtx (i1src));
2630 i1pat = copy_rtx (PATTERN (i1));
2635 /* Substitute in the latest insn for the regs set by the earlier ones. */
2637 maxreg = max_reg_num ();
2642 /* Many machines that don't use CC0 have insns that can both perform an
2643 arithmetic operation and set the condition code. These operations will
2644 be represented as a PARALLEL with the first element of the vector
2645 being a COMPARE of an arithmetic operation with the constant zero.
2646 The second element of the vector will set some pseudo to the result
2647 of the same arithmetic operation. If we simplify the COMPARE, we won't
2648 match such a pattern and so will generate an extra insn. Here we test
2649 for this case, where both the comparison and the operation result are
2650 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2651 I2SRC. Later we will make the PARALLEL that contains I2. */
2653 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
2654 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
2655 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
2656 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
2658 #ifdef SELECT_CC_MODE
2660 enum machine_mode compare_mode;
2663 newpat = PATTERN (i3);
2664 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
2668 #ifdef SELECT_CC_MODE
2669 /* See if a COMPARE with the operand we substituted in should be done
2670 with the mode that is currently being used. If not, do the same
2671 processing we do in `subst' for a SET; namely, if the destination
2672 is used only once, try to replace it with a register of the proper
2673 mode and also replace the COMPARE. */
2674 if (undobuf.other_insn == 0
2675 && (cc_use = find_single_use (SET_DEST (newpat), i3,
2676 &undobuf.other_insn))
2677 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
2679 != GET_MODE (SET_DEST (newpat))))
2681 if (can_change_dest_mode(SET_DEST (newpat), added_sets_2,
2684 unsigned int regno = REGNO (SET_DEST (newpat));
2687 if (regno < FIRST_PSEUDO_REGISTER)
2688 new_dest = gen_rtx_REG (compare_mode, regno);
2691 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
2692 new_dest = regno_reg_rtx[regno];
2695 SUBST (SET_DEST (newpat), new_dest);
2696 SUBST (XEXP (*cc_use, 0), new_dest);
2697 SUBST (SET_SRC (newpat),
2698 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
2701 undobuf.other_insn = 0;
2708 /* It is possible that the source of I2 or I1 may be performing
2709 an unneeded operation, such as a ZERO_EXTEND of something
2710 that is known to have the high part zero. Handle that case
2711 by letting subst look at the innermost one of them.
2713 Another way to do this would be to have a function that tries
2714 to simplify a single insn instead of merging two or more
2715 insns. We don't do this because of the potential of infinite
2716 loops and because of the potential extra memory required.
2717 However, doing it the way we are is a bit of a kludge and
2718 doesn't catch all cases.
2720 But only do this if -fexpensive-optimizations since it slows
2721 things down and doesn't usually win.
2723 This is not done in the COMPARE case above because the
2724 unmodified I2PAT is used in the PARALLEL and so a pattern
2725 with a modified I2SRC would not match. */
2727 if (flag_expensive_optimizations)
2729 /* Pass pc_rtx so no substitutions are done, just
2733 subst_low_luid = DF_INSN_LUID (i1);
2734 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
2738 subst_low_luid = DF_INSN_LUID (i2);
2739 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
2743 n_occurrences = 0; /* `subst' counts here */
2745 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
2746 need to make a unique copy of I2SRC each time we substitute it
2747 to avoid self-referential rtl. */
2749 subst_low_luid = DF_INSN_LUID (i2);
2750 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
2751 ! i1_feeds_i3 && i1dest_in_i1src);
2754 /* Record whether i2's body now appears within i3's body. */
2755 i2_is_used = n_occurrences;
2758 /* If we already got a failure, don't try to do more. Otherwise,
2759 try to substitute in I1 if we have it. */
2761 if (i1 && GET_CODE (newpat) != CLOBBER)
2763 /* Check that an autoincrement side-effect on I1 has not been lost.
2764 This happens if I1DEST is mentioned in I2 and dies there, and
2765 has disappeared from the new pattern. */
2766 if ((FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2768 && dead_or_set_p (i2, i1dest)
2769 && !reg_overlap_mentioned_p (i1dest, newpat))
2770 /* Before we can do this substitution, we must redo the test done
2771 above (see detailed comments there) that ensures that I1DEST
2772 isn't mentioned in any SETs in NEWPAT that are field assignments. */
2773 || !combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX, 0, 0))
2780 subst_low_luid = DF_INSN_LUID (i1);
2781 newpat = subst (newpat, i1dest, i1src, 0, 0);
2785 /* Fail if an autoincrement side-effect has been duplicated. Be careful
2786 to count all the ways that I2SRC and I1SRC can be used. */
2787 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
2788 && i2_is_used + added_sets_2 > 1)
2789 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2790 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
2792 /* Fail if we tried to make a new register. */
2793 || max_reg_num () != maxreg
2794 /* Fail if we couldn't do something and have a CLOBBER. */
2795 || GET_CODE (newpat) == CLOBBER
2796 /* Fail if this new pattern is a MULT and we didn't have one before
2797 at the outer level. */
2798 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
2805 /* If the actions of the earlier insns must be kept
2806 in addition to substituting them into the latest one,
2807 we must make a new PARALLEL for the latest insn
2808 to hold additional the SETs. */
2810 if (added_sets_1 || added_sets_2)
2814 if (GET_CODE (newpat) == PARALLEL)
2816 rtvec old = XVEC (newpat, 0);
2817 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
2818 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2819 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
2820 sizeof (old->elem[0]) * old->num_elem);
2825 total_sets = 1 + added_sets_1 + added_sets_2;
2826 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2827 XVECEXP (newpat, 0, 0) = old;
2831 XVECEXP (newpat, 0, --total_sets) = i1pat;
2835 /* If there is no I1, use I2's body as is. We used to also not do
2836 the subst call below if I2 was substituted into I3,
2837 but that could lose a simplification. */
2839 XVECEXP (newpat, 0, --total_sets) = i2pat;
2841 /* See comment where i2pat is assigned. */
2842 XVECEXP (newpat, 0, --total_sets)
2843 = subst (i2pat, i1dest, i1src, 0, 0);
2847 /* We come here when we are replacing a destination in I2 with the
2848 destination of I3. */
2849 validate_replacement:
2851 /* Note which hard regs this insn has as inputs. */
2852 mark_used_regs_combine (newpat);
2854 /* If recog_for_combine fails, it strips existing clobbers. If we'll
2855 consider splitting this pattern, we might need these clobbers. */
2856 if (i1 && GET_CODE (newpat) == PARALLEL
2857 && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
2859 int len = XVECLEN (newpat, 0);
2861 newpat_vec_with_clobbers = rtvec_alloc (len);
2862 for (i = 0; i < len; i++)
2863 RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
2866 /* Is the result of combination a valid instruction? */
2867 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2869 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2870 the second SET's destination is a register that is unused and isn't
2871 marked as an instruction that might trap in an EH region. In that case,
2872 we just need the first SET. This can occur when simplifying a divmod
2873 insn. We *must* test for this case here because the code below that
2874 splits two independent SETs doesn't handle this case correctly when it
2875 updates the register status.
2877 It's pointless doing this if we originally had two sets, one from
2878 i3, and one from i2. Combining then splitting the parallel results
2879 in the original i2 again plus an invalid insn (which we delete).
2880 The net effect is only to move instructions around, which makes
2881 debug info less accurate.
2883 Also check the case where the first SET's destination is unused.
2884 That would not cause incorrect code, but does cause an unneeded
2887 if (insn_code_number < 0
2888 && !(added_sets_2 && i1 == 0)
2889 && GET_CODE (newpat) == PARALLEL
2890 && XVECLEN (newpat, 0) == 2
2891 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2892 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2893 && asm_noperands (newpat) < 0)
2895 rtx set0 = XVECEXP (newpat, 0, 0);
2896 rtx set1 = XVECEXP (newpat, 0, 1);
2899 if (((REG_P (SET_DEST (set1))
2900 && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
2901 || (GET_CODE (SET_DEST (set1)) == SUBREG
2902 && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
2903 && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2904 || INTVAL (XEXP (note, 0)) <= 0)
2905 && ! side_effects_p (SET_SRC (set1)))
2908 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2911 else if (((REG_P (SET_DEST (set0))
2912 && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
2913 || (GET_CODE (SET_DEST (set0)) == SUBREG
2914 && find_reg_note (i3, REG_UNUSED,
2915 SUBREG_REG (SET_DEST (set0)))))
2916 && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2917 || INTVAL (XEXP (note, 0)) <= 0)
2918 && ! side_effects_p (SET_SRC (set0)))
2921 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2923 if (insn_code_number >= 0)
2924 changed_i3_dest = 1;
2928 /* If we were combining three insns and the result is a simple SET
2929 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2930 insns. There are two ways to do this. It can be split using a
2931 machine-specific method (like when you have an addition of a large
2932 constant) or by combine in the function find_split_point. */
2934 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2935 && asm_noperands (newpat) < 0)
2937 rtx parallel, m_split, *split;
2939 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2940 use I2DEST as a scratch register will help. In the latter case,
2941 convert I2DEST to the mode of the source of NEWPAT if we can. */
2943 m_split = combine_split_insns (newpat, i3);
2945 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2946 inputs of NEWPAT. */
2948 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2949 possible to try that as a scratch reg. This would require adding
2950 more code to make it work though. */
2952 if (m_split == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
2954 enum machine_mode new_mode = GET_MODE (SET_DEST (newpat));
2956 /* First try to split using the original register as a
2957 scratch register. */
2958 parallel = gen_rtx_PARALLEL (VOIDmode,
2959 gen_rtvec (2, newpat,
2960 gen_rtx_CLOBBER (VOIDmode,
2962 m_split = combine_split_insns (parallel, i3);
2964 /* If that didn't work, try changing the mode of I2DEST if
2967 && new_mode != GET_MODE (i2dest)
2968 && new_mode != VOIDmode
2969 && can_change_dest_mode (i2dest, added_sets_2, new_mode))
2971 enum machine_mode old_mode = GET_MODE (i2dest);
2974 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
2975 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
2978 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode);
2979 ni2dest = regno_reg_rtx[REGNO (i2dest)];
2982 parallel = (gen_rtx_PARALLEL
2984 gen_rtvec (2, newpat,
2985 gen_rtx_CLOBBER (VOIDmode,
2987 m_split = combine_split_insns (parallel, i3);
2990 && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2994 adjust_reg_mode (regno_reg_rtx[REGNO (i2dest)], old_mode);
2995 buf = undobuf.undos;
2996 undobuf.undos = buf->next;
2997 buf->next = undobuf.frees;
2998 undobuf.frees = buf;
3003 /* If recog_for_combine has discarded clobbers, try to use them
3004 again for the split. */
3005 if (m_split == 0 && newpat_vec_with_clobbers)
3007 parallel = gen_rtx_PARALLEL (VOIDmode, newpat_vec_with_clobbers);
3008 m_split = combine_split_insns (parallel, i3);
3011 if (m_split && NEXT_INSN (m_split) == NULL_RTX)
3013 m_split = PATTERN (m_split);
3014 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
3015 if (insn_code_number >= 0)
3018 else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
3019 && (next_real_insn (i2) == i3
3020 || ! use_crosses_set_p (PATTERN (m_split), DF_INSN_LUID (i2))))
3023 rtx newi3pat = PATTERN (NEXT_INSN (m_split));
3024 newi2pat = PATTERN (m_split);
3026 i3set = single_set (NEXT_INSN (m_split));
3027 i2set = single_set (m_split);
3029 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3031 /* If I2 or I3 has multiple SETs, we won't know how to track
3032 register status, so don't use these insns. If I2's destination
3033 is used between I2 and I3, we also can't use these insns. */
3035 if (i2_code_number >= 0 && i2set && i3set
3036 && (next_real_insn (i2) == i3
3037 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
3038 insn_code_number = recog_for_combine (&newi3pat, i3,
3040 if (insn_code_number >= 0)
3043 /* It is possible that both insns now set the destination of I3.
3044 If so, we must show an extra use of it. */
3046 if (insn_code_number >= 0)
3048 rtx new_i3_dest = SET_DEST (i3set);
3049 rtx new_i2_dest = SET_DEST (i2set);
3051 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
3052 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
3053 || GET_CODE (new_i3_dest) == SUBREG)
3054 new_i3_dest = XEXP (new_i3_dest, 0);
3056 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
3057 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
3058 || GET_CODE (new_i2_dest) == SUBREG)
3059 new_i2_dest = XEXP (new_i2_dest, 0);
3061 if (REG_P (new_i3_dest)
3062 && REG_P (new_i2_dest)
3063 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
3064 INC_REG_N_SETS (REGNO (new_i2_dest), 1);
3068 /* If we can split it and use I2DEST, go ahead and see if that
3069 helps things be recognized. Verify that none of the registers
3070 are set between I2 and I3. */
3071 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
3075 /* We need I2DEST in the proper mode. If it is a hard register
3076 or the only use of a pseudo, we can change its mode.
3077 Make sure we don't change a hard register to have a mode that
3078 isn't valid for it, or change the number of registers. */
3079 && (GET_MODE (*split) == GET_MODE (i2dest)
3080 || GET_MODE (*split) == VOIDmode
3081 || can_change_dest_mode (i2dest, added_sets_2,
3083 && (next_real_insn (i2) == i3
3084 || ! use_crosses_set_p (*split, DF_INSN_LUID (i2)))
3085 /* We can't overwrite I2DEST if its value is still used by
3087 && ! reg_referenced_p (i2dest, newpat))
3089 rtx newdest = i2dest;
3090 enum rtx_code split_code = GET_CODE (*split);
3091 enum machine_mode split_mode = GET_MODE (*split);
3092 bool subst_done = false;
3093 newi2pat = NULL_RTX;
3095 /* Get NEWDEST as a register in the proper mode. We have already
3096 validated that we can do this. */
3097 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
3099 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3100 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
3103 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode);
3104 newdest = regno_reg_rtx[REGNO (i2dest)];
3108 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3109 an ASHIFT. This can occur if it was inside a PLUS and hence
3110 appeared to be a memory address. This is a kludge. */
3111 if (split_code == MULT
3112 && GET_CODE (XEXP (*split, 1)) == CONST_INT
3113 && INTVAL (XEXP (*split, 1)) > 0
3114 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
3116 SUBST (*split, gen_rtx_ASHIFT (split_mode,
3117 XEXP (*split, 0), GEN_INT (i)));
3118 /* Update split_code because we may not have a multiply
3120 split_code = GET_CODE (*split);
3123 #ifdef INSN_SCHEDULING
3124 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3125 be written as a ZERO_EXTEND. */
3126 if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
3128 #ifdef LOAD_EXTEND_OP
3129 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3130 what it really is. */
3131 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
3133 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
3134 SUBREG_REG (*split)));
3137 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
3138 SUBREG_REG (*split)));
3142 /* Attempt to split binary operators using arithmetic identities. */
3143 if (BINARY_P (SET_SRC (newpat))
3144 && split_mode == GET_MODE (SET_SRC (newpat))
3145 && ! side_effects_p (SET_SRC (newpat)))
3147 rtx setsrc = SET_SRC (newpat);
3148 enum machine_mode mode = GET_MODE (setsrc);
3149 enum rtx_code code = GET_CODE (setsrc);
3150 rtx src_op0 = XEXP (setsrc, 0);
3151 rtx src_op1 = XEXP (setsrc, 1);
3153 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3154 if (rtx_equal_p (src_op0, src_op1))
3156 newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0);
3157 SUBST (XEXP (setsrc, 0), newdest);
3158 SUBST (XEXP (setsrc, 1), newdest);
3161 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3162 else if ((code == PLUS || code == MULT)
3163 && GET_CODE (src_op0) == code
3164 && GET_CODE (XEXP (src_op0, 0)) == code
3165 && (INTEGRAL_MODE_P (mode)
3166 || (FLOAT_MODE_P (mode)
3167 && flag_unsafe_math_optimizations)))
3169 rtx p = XEXP (XEXP (src_op0, 0), 0);
3170 rtx q = XEXP (XEXP (src_op0, 0), 1);
3171 rtx r = XEXP (src_op0, 1);
3174 /* Split both "((X op Y) op X) op Y" and
3175 "((X op Y) op Y) op X" as "T op T" where T is
3177 if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
3178 || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
3180 newi2pat = gen_rtx_SET (VOIDmode, newdest,
3182 SUBST (XEXP (setsrc, 0), newdest);
3183 SUBST (XEXP (setsrc, 1), newdest);
3186 /* Split "((X op X) op Y) op Y)" as "T op T" where
3188 else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
3190 rtx tmp = simplify_gen_binary (code, mode, p, r);
3191 newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp);
3192 SUBST (XEXP (setsrc, 0), newdest);
3193 SUBST (XEXP (setsrc, 1), newdest);
3201 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
3202 SUBST (*split, newdest);
3205 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3207 /* recog_for_combine might have added CLOBBERs to newi2pat.
3208 Make sure NEWPAT does not depend on the clobbered regs. */
3209 if (GET_CODE (newi2pat) == PARALLEL)
3210 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3211 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3213 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3214 if (reg_overlap_mentioned_p (reg, newpat))
3221 /* If the split point was a MULT and we didn't have one before,
3222 don't use one now. */
3223 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
3224 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3228 /* Check for a case where we loaded from memory in a narrow mode and
3229 then sign extended it, but we need both registers. In that case,
3230 we have a PARALLEL with both loads from the same memory location.
3231 We can split this into a load from memory followed by a register-register
3232 copy. This saves at least one insn, more if register allocation can
3235 We cannot do this if the destination of the first assignment is a
3236 condition code register or cc0. We eliminate this case by making sure
3237 the SET_DEST and SET_SRC have the same mode.
3239 We cannot do this if the destination of the second assignment is
3240 a register that we have already assumed is zero-extended. Similarly
3241 for a SUBREG of such a register. */
3243 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3244 && GET_CODE (newpat) == PARALLEL
3245 && XVECLEN (newpat, 0) == 2
3246 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3247 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
3248 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
3249 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
3250 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3251 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3252 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
3253 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3255 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3256 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3257 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
3259 && VEC_index (reg_stat_type, reg_stat,
3260 REGNO (temp))->nonzero_bits != 0
3261 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
3262 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
3263 && (VEC_index (reg_stat_type, reg_stat,
3264 REGNO (temp))->nonzero_bits
3265 != GET_MODE_MASK (word_mode))))
3266 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
3267 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
3269 && VEC_index (reg_stat_type, reg_stat,
3270 REGNO (temp))->nonzero_bits != 0
3271 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
3272 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
3273 && (VEC_index (reg_stat_type, reg_stat,
3274 REGNO (temp))->nonzero_bits
3275 != GET_MODE_MASK (word_mode)))))
3276 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3277 SET_SRC (XVECEXP (newpat, 0, 1)))
3278 && ! find_reg_note (i3, REG_UNUSED,
3279 SET_DEST (XVECEXP (newpat, 0, 0))))
3283 newi2pat = XVECEXP (newpat, 0, 0);
3284 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
3285 newpat = XVECEXP (newpat, 0, 1);
3286 SUBST (SET_SRC (newpat),
3287 gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
3288 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3290 if (i2_code_number >= 0)
3291 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3293 if (insn_code_number >= 0)
3297 /* Similarly, check for a case where we have a PARALLEL of two independent
3298 SETs but we started with three insns. In this case, we can do the sets
3299 as two separate insns. This case occurs when some SET allows two
3300 other insns to combine, but the destination of that SET is still live. */
3302 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3303 && GET_CODE (newpat) == PARALLEL
3304 && XVECLEN (newpat, 0) == 2
3305 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3306 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
3307 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
3308 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3309 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3310 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3311 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3313 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3314 XVECEXP (newpat, 0, 0))
3315 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
3316 XVECEXP (newpat, 0, 1))
3317 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
3318 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1))))
3320 /* We cannot split the parallel into two sets if both sets
3322 && ! (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0))
3323 && reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 1)))
3327 /* Normally, it doesn't matter which of the two is done first,
3328 but it does if one references cc0. In that case, it has to
3331 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
3333 newi2pat = XVECEXP (newpat, 0, 0);
3334 newpat = XVECEXP (newpat, 0, 1);
3339 newi2pat = XVECEXP (newpat, 0, 1);
3340 newpat = XVECEXP (newpat, 0, 0);
3343 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3345 if (i2_code_number >= 0)
3346 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3349 /* If it still isn't recognized, fail and change things back the way they
3351 if ((insn_code_number < 0
3352 /* Is the result a reasonable ASM_OPERANDS? */
3353 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
3359 /* If we had to change another insn, make sure it is valid also. */
3360 if (undobuf.other_insn)
3362 CLEAR_HARD_REG_SET (newpat_used_regs);
3364 other_pat = PATTERN (undobuf.other_insn);
3365 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
3368 if (other_code_number < 0 && ! check_asm_operands (other_pat))
3376 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3377 they are adjacent to each other or not. */
3379 rtx p = prev_nonnote_insn (i3);
3380 if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
3381 && sets_cc0_p (newi2pat))
3389 /* Only allow this combination if insn_rtx_costs reports that the
3390 replacement instructions are cheaper than the originals. */
3391 if (!combine_validate_cost (i1, i2, i3, newpat, newi2pat, other_pat))
3397 /* If we will be able to accept this, we have made a
3398 change to the destination of I3. This requires us to
3399 do a few adjustments. */
3401 if (changed_i3_dest)
3403 PATTERN (i3) = newpat;
3404 adjust_for_new_dest (i3);
3407 /* We now know that we can do this combination. Merge the insns and
3408 update the status of registers and LOG_LINKS. */
3410 if (undobuf.other_insn)
3414 PATTERN (undobuf.other_insn) = other_pat;
3416 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
3417 are still valid. Then add any non-duplicate notes added by
3418 recog_for_combine. */
3419 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
3421 next = XEXP (note, 1);
3423 if (REG_NOTE_KIND (note) == REG_UNUSED
3424 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
3425 remove_note (undobuf.other_insn, note);
3428 distribute_notes (new_other_notes, undobuf.other_insn,
3429 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
3438 /* I3 now uses what used to be its destination and which is now
3439 I2's destination. This requires us to do a few adjustments. */
3440 PATTERN (i3) = newpat;
3441 adjust_for_new_dest (i3);
3443 /* We need a LOG_LINK from I3 to I2. But we used to have one,
3446 However, some later insn might be using I2's dest and have
3447 a LOG_LINK pointing at I3. We must remove this link.
3448 The simplest way to remove the link is to point it at I1,
3449 which we know will be a NOTE. */
3451 /* newi2pat is usually a SET here; however, recog_for_combine might
3452 have added some clobbers. */
3453 if (GET_CODE (newi2pat) == PARALLEL)
3454 ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
3456 ni2dest = SET_DEST (newi2pat);
3458 for (insn = NEXT_INSN (i3);
3459 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3460 || insn != BB_HEAD (this_basic_block->next_bb));
3461 insn = NEXT_INSN (insn))
3463 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
3465 for (link = LOG_LINKS (insn); link;
3466 link = XEXP (link, 1))
3467 if (XEXP (link, 0) == i3)
3468 XEXP (link, 0) = i1;
3476 rtx i3notes, i2notes, i1notes = 0;
3477 rtx i3links, i2links, i1links = 0;
3480 /* Compute which registers we expect to eliminate. newi2pat may be setting
3481 either i3dest or i2dest, so we must check it. Also, i1dest may be the
3482 same as i3dest, in which case newi2pat may be setting i1dest. */
3483 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
3484 || i2dest_in_i2src || i2dest_in_i1src
3487 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
3488 || (newi2pat && reg_set_p (i1dest, newi2pat))
3492 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
3494 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
3495 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
3497 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
3499 /* Ensure that we do not have something that should not be shared but
3500 occurs multiple times in the new insns. Check this by first
3501 resetting all the `used' flags and then copying anything is shared. */
3503 reset_used_flags (i3notes);
3504 reset_used_flags (i2notes);
3505 reset_used_flags (i1notes);
3506 reset_used_flags (newpat);
3507 reset_used_flags (newi2pat);
3508 if (undobuf.other_insn)
3509 reset_used_flags (PATTERN (undobuf.other_insn));
3511 i3notes = copy_rtx_if_shared (i3notes);
3512 i2notes = copy_rtx_if_shared (i2notes);
3513 i1notes = copy_rtx_if_shared (i1notes);
3514 newpat = copy_rtx_if_shared (newpat);
3515 newi2pat = copy_rtx_if_shared (newi2pat);
3516 if (undobuf.other_insn)
3517 reset_used_flags (PATTERN (undobuf.other_insn));
3519 INSN_CODE (i3) = insn_code_number;
3520 PATTERN (i3) = newpat;
3522 if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
3524 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
3526 reset_used_flags (call_usage);
3527 call_usage = copy_rtx (call_usage);
3530 replace_rtx (call_usage, i2dest, i2src);
3533 replace_rtx (call_usage, i1dest, i1src);
3535 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
3538 if (undobuf.other_insn)
3539 INSN_CODE (undobuf.other_insn) = other_code_number;
3541 /* We had one special case above where I2 had more than one set and
3542 we replaced a destination of one of those sets with the destination
3543 of I3. In that case, we have to update LOG_LINKS of insns later
3544 in this basic block. Note that this (expensive) case is rare.
3546 Also, in this case, we must pretend that all REG_NOTEs for I2
3547 actually came from I3, so that REG_UNUSED notes from I2 will be
3548 properly handled. */
3550 if (i3_subst_into_i2)
3552 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
3553 if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET
3554 || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER)
3555 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
3556 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
3557 && ! find_reg_note (i2, REG_UNUSED,
3558 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
3559 for (temp = NEXT_INSN (i2);
3560 temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3561 || BB_HEAD (this_basic_block) != temp);
3562 temp = NEXT_INSN (temp))
3563 if (temp != i3 && INSN_P (temp))
3564 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
3565 if (XEXP (link, 0) == i2)
3566 XEXP (link, 0) = i3;
3571 while (XEXP (link, 1))
3572 link = XEXP (link, 1);
3573 XEXP (link, 1) = i2notes;
3587 INSN_CODE (i2) = i2_code_number;
3588 PATTERN (i2) = newi2pat;
3591 SET_INSN_DELETED (i2);
3597 SET_INSN_DELETED (i1);
3600 /* Get death notes for everything that is now used in either I3 or
3601 I2 and used to die in a previous insn. If we built two new
3602 patterns, move from I1 to I2 then I2 to I3 so that we get the
3603 proper movement on registers that I2 modifies. */
3607 move_deaths (newi2pat, NULL_RTX, DF_INSN_LUID (i1), i2, &midnotes);
3608 move_deaths (newpat, newi2pat, DF_INSN_LUID (i1), i3, &midnotes);
3611 move_deaths (newpat, NULL_RTX, i1 ? DF_INSN_LUID (i1) : DF_INSN_LUID (i2),
3614 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
3616 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
3619 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
3622 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
3625 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3628 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
3629 know these are REG_UNUSED and want them to go to the desired insn,
3630 so we always pass it as i3. */
3632 if (newi2pat && new_i2_notes)
3633 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3636 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
3638 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
3639 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
3640 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
3641 in that case, it might delete I2. Similarly for I2 and I1.
3642 Show an additional death due to the REG_DEAD note we make here. If
3643 we discard it in distribute_notes, we will decrement it again. */
3647 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
3648 distribute_notes (alloc_reg_note (REG_DEAD, i3dest_killed,
3650 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
3652 distribute_notes (alloc_reg_note (REG_DEAD, i3dest_killed,
3654 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3658 if (i2dest_in_i2src)
3660 if (newi2pat && reg_set_p (i2dest, newi2pat))
3661 distribute_notes (alloc_reg_note (REG_DEAD, i2dest, NULL_RTX),
3662 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3664 distribute_notes (alloc_reg_note (REG_DEAD, i2dest, NULL_RTX),
3665 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3666 NULL_RTX, NULL_RTX);
3669 if (i1dest_in_i1src)
3671 if (newi2pat && reg_set_p (i1dest, newi2pat))
3672 distribute_notes (alloc_reg_note (REG_DEAD, i1dest, NULL_RTX),
3673 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3675 distribute_notes (alloc_reg_note (REG_DEAD, i1dest, NULL_RTX),
3676 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3677 NULL_RTX, NULL_RTX);
3680 distribute_links (i3links);
3681 distribute_links (i2links);
3682 distribute_links (i1links);
3687 rtx i2_insn = 0, i2_val = 0, set;
3689 /* The insn that used to set this register doesn't exist, and
3690 this life of the register may not exist either. See if one of
3691 I3's links points to an insn that sets I2DEST. If it does,
3692 that is now the last known value for I2DEST. If we don't update
3693 this and I2 set the register to a value that depended on its old
3694 contents, we will get confused. If this insn is used, thing
3695 will be set correctly in combine_instructions. */
3697 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3698 if ((set = single_set (XEXP (link, 0))) != 0
3699 && rtx_equal_p (i2dest, SET_DEST (set)))
3700 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
3702 record_value_for_reg (i2dest, i2_insn, i2_val);
3704 /* If the reg formerly set in I2 died only once and that was in I3,
3705 zero its use count so it won't make `reload' do any work. */
3707 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
3708 && ! i2dest_in_i2src)
3710 regno = REGNO (i2dest);
3711 INC_REG_N_SETS (regno, -1);
3715 if (i1 && REG_P (i1dest))
3718 rtx i1_insn = 0, i1_val = 0, set;
3720 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3721 if ((set = single_set (XEXP (link, 0))) != 0
3722 && rtx_equal_p (i1dest, SET_DEST (set)))
3723 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
3725 record_value_for_reg (i1dest, i1_insn, i1_val);
3727 regno = REGNO (i1dest);
3728 if (! added_sets_1 && ! i1dest_in_i1src)
3729 INC_REG_N_SETS (regno, -1);
3732 /* Update reg_stat[].nonzero_bits et al for any changes that may have
3733 been made to this insn. The order of
3734 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
3735 can affect nonzero_bits of newpat */
3737 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
3738 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
3741 if (undobuf.other_insn != NULL_RTX)
3745 fprintf (dump_file, "modifying other_insn ");
3746 dump_insn_slim (dump_file, undobuf.other_insn);
3748 df_insn_rescan (undobuf.other_insn);
3751 if (i1 && !(NOTE_P(i1) && (NOTE_KIND (i1) == NOTE_INSN_DELETED)))
3755 fprintf (dump_file, "modifying insn i1 ");
3756 dump_insn_slim (dump_file, i1);
3758 df_insn_rescan (i1);
3761 if (i2 && !(NOTE_P(i2) && (NOTE_KIND (i2) == NOTE_INSN_DELETED)))
3765 fprintf (dump_file, "modifying insn i2 ");
3766 dump_insn_slim (dump_file, i2);
3768 df_insn_rescan (i2);
3771 if (i3 && !(NOTE_P(i3) && (NOTE_KIND (i3) == NOTE_INSN_DELETED)))
3775 fprintf (dump_file, "modifying insn i3 ");
3776 dump_insn_slim (dump_file, i3);
3778 df_insn_rescan (i3);
3781 /* Set new_direct_jump_p if a new return or simple jump instruction
3782 has been created. Adjust the CFG accordingly. */
3784 if (returnjump_p (i3) || any_uncondjump_p (i3))
3786 *new_direct_jump_p = 1;
3787 mark_jump_label (PATTERN (i3), i3, 0);
3788 update_cfg_for_uncondjump (i3);
3791 if (undobuf.other_insn != NULL_RTX
3792 && (returnjump_p (undobuf.other_insn)
3793 || any_uncondjump_p (undobuf.other_insn)))
3795 *new_direct_jump_p = 1;
3796 update_cfg_for_uncondjump (undobuf.other_insn);
3799 /* A noop might also need cleaning up of CFG, if it comes from the
3800 simplification of a jump. */
3801 if (GET_CODE (newpat) == SET
3802 && SET_SRC (newpat) == pc_rtx
3803 && SET_DEST (newpat) == pc_rtx)
3805 *new_direct_jump_p = 1;
3806 update_cfg_for_uncondjump (i3);
3809 combine_successes++;
3812 if (added_links_insn
3813 && (newi2pat == 0 || DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i2))
3814 && DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i3))
3815 return added_links_insn;
3817 return newi2pat ? i2 : i3;
3820 /* Undo all the modifications recorded in undobuf. */
3825 struct undo *undo, *next;
3827 for (undo = undobuf.undos; undo; undo = next)
3833 *undo->where.r = undo->old_contents.r;
3836 *undo->where.i = undo->old_contents.i;
3839 adjust_reg_mode (*undo->where.r, undo->old_contents.m);
3845 undo->next = undobuf.frees;
3846 undobuf.frees = undo;
3852 /* We've committed to accepting the changes we made. Move all
3853 of the undos to the free list. */
3858 struct undo *undo, *next;
3860 for (undo = undobuf.undos; undo; undo = next)
3863 undo->next = undobuf.frees;
3864 undobuf.frees = undo;
3869 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
3870 where we have an arithmetic expression and return that point. LOC will
3873 try_combine will call this function to see if an insn can be split into
3877 find_split_point (rtx *loc, rtx insn)
3880 enum rtx_code code = GET_CODE (x);
3882 unsigned HOST_WIDE_INT len = 0;
3883 HOST_WIDE_INT pos = 0;
3885 rtx inner = NULL_RTX;
3887 /* First special-case some codes. */
3891 #ifdef INSN_SCHEDULING
3892 /* If we are making a paradoxical SUBREG invalid, it becomes a split
3894 if (MEM_P (SUBREG_REG (x)))
3897 return find_split_point (&SUBREG_REG (x), insn);
3901 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
3902 using LO_SUM and HIGH. */
3903 if (GET_CODE (XEXP (x, 0)) == CONST
3904 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
3907 gen_rtx_LO_SUM (Pmode,
3908 gen_rtx_HIGH (Pmode, XEXP (x, 0)),
3910 return &XEXP (XEXP (x, 0), 0);
3914 /* If we have a PLUS whose second operand is a constant and the
3915 address is not valid, perhaps will can split it up using
3916 the machine-specific way to split large constants. We use
3917 the first pseudo-reg (one of the virtual regs) as a placeholder;
3918 it will not remain in the result. */
3919 if (GET_CODE (XEXP (x, 0)) == PLUS
3920 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3921 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
3923 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
3924 rtx seq = combine_split_insns (gen_rtx_SET (VOIDmode, reg,
3928 /* This should have produced two insns, each of which sets our
3929 placeholder. If the source of the second is a valid address,
3930 we can make put both sources together and make a split point
3934 && NEXT_INSN (seq) != NULL_RTX
3935 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
3936 && NONJUMP_INSN_P (seq)
3937 && GET_CODE (PATTERN (seq)) == SET
3938 && SET_DEST (PATTERN (seq)) == reg
3939 && ! reg_mentioned_p (reg,
3940 SET_SRC (PATTERN (seq)))
3941 && NONJUMP_INSN_P (NEXT_INSN (seq))
3942 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
3943 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
3944 && memory_address_p (GET_MODE (x),
3945 SET_SRC (PATTERN (NEXT_INSN (seq)))))
3947 rtx src1 = SET_SRC (PATTERN (seq));
3948 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
3950 /* Replace the placeholder in SRC2 with SRC1. If we can
3951 find where in SRC2 it was placed, that can become our
3952 split point and we can replace this address with SRC2.
3953 Just try two obvious places. */
3955 src2 = replace_rtx (src2, reg, src1);
3957 if (XEXP (src2, 0) == src1)
3958 split = &XEXP (src2, 0);
3959 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
3960 && XEXP (XEXP (src2, 0), 0) == src1)
3961 split = &XEXP (XEXP (src2, 0), 0);
3965 SUBST (XEXP (x, 0), src2);
3970 /* If that didn't work, perhaps the first operand is complex and
3971 needs to be computed separately, so make a split point there.
3972 This will occur on machines that just support REG + CONST
3973 and have a constant moved through some previous computation. */
3975 else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
3976 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
3977 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
3978 return &XEXP (XEXP (x, 0), 0);
3981 /* If we have a PLUS whose first operand is complex, try computing it
3982 separately by making a split there. */
3983 if (GET_CODE (XEXP (x, 0)) == PLUS
3984 && ! memory_address_p (GET_MODE (x), XEXP (x, 0))
3985 && ! OBJECT_P (XEXP (XEXP (x, 0), 0))
3986 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
3987 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
3988 return &XEXP (XEXP (x, 0), 0);
3993 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
3994 ZERO_EXTRACT, the most likely reason why this doesn't match is that
3995 we need to put the operand into a register. So split at that
3998 if (SET_DEST (x) == cc0_rtx
3999 && GET_CODE (SET_SRC (x)) != COMPARE
4000 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
4001 && !OBJECT_P (SET_SRC (x))
4002 && ! (GET_CODE (SET_SRC (x)) == SUBREG
4003 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
4004 return &SET_SRC (x);
4007 /* See if we can split SET_SRC as it stands. */
4008 split = find_split_point (&SET_SRC (x), insn);
4009 if (split && split != &SET_SRC (x))
4012 /* See if we can split SET_DEST as it stands. */
4013 split = find_split_point (&SET_DEST (x), insn);
4014 if (split && split != &SET_DEST (x))
4017 /* See if this is a bitfield assignment with everything constant. If
4018 so, this is an IOR of an AND, so split it into that. */
4019 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
4020 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
4021 <= HOST_BITS_PER_WIDE_INT)
4022 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
4023 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
4024 && GET_CODE (SET_SRC (x)) == CONST_INT
4025 && ((INTVAL (XEXP (SET_DEST (x), 1))
4026 + INTVAL (XEXP (SET_DEST (x), 2)))
4027 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
4028 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
4030 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
4031 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
4032 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
4033 rtx dest = XEXP (SET_DEST (x), 0);
4034 enum machine_mode mode = GET_MODE (dest);
4035 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
4038 if (BITS_BIG_ENDIAN)
4039 pos = GET_MODE_BITSIZE (mode) - len - pos;
4041 or_mask = gen_int_mode (src << pos, mode);
4044 simplify_gen_binary (IOR, mode, dest, or_mask));
4047 rtx negmask = gen_int_mode (~(mask << pos), mode);
4049 simplify_gen_binary (IOR, mode,
4050 simplify_gen_binary (AND, mode,
4055 SUBST (SET_DEST (x), dest);
4057 split = find_split_point (&SET_SRC (x), insn);
4058 if (split && split != &SET_SRC (x))
4062 /* Otherwise, see if this is an operation that we can split into two.
4063 If so, try to split that. */
4064 code = GET_CODE (SET_SRC (x));
4069 /* If we are AND'ing with a large constant that is only a single
4070 bit and the result is only being used in a context where we
4071 need to know if it is zero or nonzero, replace it with a bit
4072 extraction. This will avoid the large constant, which might
4073 have taken more than one insn to make. If the constant were
4074 not a valid argument to the AND but took only one insn to make,
4075 this is no worse, but if it took more than one insn, it will
4078 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
4079 && REG_P (XEXP (SET_SRC (x), 0))
4080 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
4081 && REG_P (SET_DEST (x))
4082 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
4083 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
4084 && XEXP (*split, 0) == SET_DEST (x)
4085 && XEXP (*split, 1) == const0_rtx)
4087 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
4088 XEXP (SET_SRC (x), 0),
4089 pos, NULL_RTX, 1, 1, 0, 0);
4090 if (extraction != 0)
4092 SUBST (SET_SRC (x), extraction);
4093 return find_split_point (loc, insn);
4099 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4100 is known to be on, this can be converted into a NEG of a shift. */
4101 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
4102 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
4103 && 1 <= (pos = exact_log2
4104 (nonzero_bits (XEXP (SET_SRC (x), 0),
4105 GET_MODE (XEXP (SET_SRC (x), 0))))))
4107 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
4111 gen_rtx_LSHIFTRT (mode,
4112 XEXP (SET_SRC (x), 0),
4115 split = find_split_point (&SET_SRC (x), insn);
4116 if (split && split != &SET_SRC (x))
4122 inner = XEXP (SET_SRC (x), 0);
4124 /* We can't optimize if either mode is a partial integer
4125 mode as we don't know how many bits are significant
4127 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
4128 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
4132 len = GET_MODE_BITSIZE (GET_MODE (inner));
4138 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
4139 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
4141 inner = XEXP (SET_SRC (x), 0);
4142 len = INTVAL (XEXP (SET_SRC (x), 1));
4143 pos = INTVAL (XEXP (SET_SRC (x), 2));
4145 if (BITS_BIG_ENDIAN)
4146 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
4147 unsignedp = (code == ZERO_EXTRACT);
4155 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
4157 enum machine_mode mode = GET_MODE (SET_SRC (x));
4159 /* For unsigned, we have a choice of a shift followed by an
4160 AND or two shifts. Use two shifts for field sizes where the
4161 constant might be too large. We assume here that we can
4162 always at least get 8-bit constants in an AND insn, which is
4163 true for every current RISC. */
4165 if (unsignedp && len <= 8)
4170 (mode, gen_lowpart (mode, inner),
4172 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
4174 split = find_split_point (&SET_SRC (x), insn);
4175 if (split && split != &SET_SRC (x))
4182 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
4183 gen_rtx_ASHIFT (mode,
4184 gen_lowpart (mode, inner),
4185 GEN_INT (GET_MODE_BITSIZE (mode)
4187 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
4189 split = find_split_point (&SET_SRC (x), insn);
4190 if (split && split != &SET_SRC (x))
4195 /* See if this is a simple operation with a constant as the second
4196 operand. It might be that this constant is out of range and hence
4197 could be used as a split point. */
4198 if (BINARY_P (SET_SRC (x))
4199 && CONSTANT_P (XEXP (SET_SRC (x), 1))
4200 && (OBJECT_P (XEXP (SET_SRC (x), 0))
4201 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
4202 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
4203 return &XEXP (SET_SRC (x), 1);
4205 /* Finally, see if this is a simple operation with its first operand
4206 not in a register. The operation might require this operand in a
4207 register, so return it as a split point. We can always do this
4208 because if the first operand were another operation, we would have
4209 already found it as a split point. */
4210 if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
4211 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
4212 return &XEXP (SET_SRC (x), 0);
4218 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4219 it is better to write this as (not (ior A B)) so we can split it.
4220 Similarly for IOR. */
4221 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
4224 gen_rtx_NOT (GET_MODE (x),
4225 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
4227 XEXP (XEXP (x, 0), 0),
4228 XEXP (XEXP (x, 1), 0))));
4229 return find_split_point (loc, insn);
4232 /* Many RISC machines have a large set of logical insns. If the
4233 second operand is a NOT, put it first so we will try to split the
4234 other operand first. */
4235 if (GET_CODE (XEXP (x, 1)) == NOT)
4237 rtx tem = XEXP (x, 0);
4238 SUBST (XEXP (x, 0), XEXP (x, 1));
4239 SUBST (XEXP (x, 1), tem);
4247 /* Otherwise, select our actions depending on our rtx class. */
4248 switch (GET_RTX_CLASS (code))
4250 case RTX_BITFIELD_OPS: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
4252 split = find_split_point (&XEXP (x, 2), insn);
4255 /* ... fall through ... */
4257 case RTX_COMM_ARITH:
4259 case RTX_COMM_COMPARE:
4260 split = find_split_point (&XEXP (x, 1), insn);
4263 /* ... fall through ... */
4265 /* Some machines have (and (shift ...) ...) insns. If X is not
4266 an AND, but XEXP (X, 0) is, use it as our split point. */
4267 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
4268 return &XEXP (x, 0);
4270 split = find_split_point (&XEXP (x, 0), insn);
4276 /* Otherwise, we don't have a split point. */
4281 /* Throughout X, replace FROM with TO, and return the result.
4282 The result is TO if X is FROM;
4283 otherwise the result is X, but its contents may have been modified.
4284 If they were modified, a record was made in undobuf so that
4285 undo_all will (among other things) return X to its original state.
4287 If the number of changes necessary is too much to record to undo,
4288 the excess changes are not made, so the result is invalid.
4289 The changes already made can still be undone.
4290 undobuf.num_undo is incremented for such changes, so by testing that
4291 the caller can tell whether the result is valid.
4293 `n_occurrences' is incremented each time FROM is replaced.
4295 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
4297 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
4298 by copying if `n_occurrences' is nonzero. */
4301 subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy)
4303 enum rtx_code code = GET_CODE (x);
4304 enum machine_mode op0_mode = VOIDmode;
4309 /* Two expressions are equal if they are identical copies of a shared
4310 RTX or if they are both registers with the same register number
4313 #define COMBINE_RTX_EQUAL_P(X,Y) \
4315 || (REG_P (X) && REG_P (Y) \
4316 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
4318 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
4321 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
4324 /* If X and FROM are the same register but different modes, they
4325 will not have been seen as equal above. However, the log links code
4326 will make a LOG_LINKS entry for that case. If we do nothing, we
4327 will try to rerecognize our original insn and, when it succeeds,
4328 we will delete the feeding insn, which is incorrect.
4330 So force this insn not to match in this (rare) case. */
4331 if (! in_dest && code == REG && REG_P (from)
4332 && reg_overlap_mentioned_p (x, from))
4333 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
4335 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
4336 of which may contain things that can be combined. */
4337 if (code != MEM && code != LO_SUM && OBJECT_P (x))
4340 /* It is possible to have a subexpression appear twice in the insn.
4341 Suppose that FROM is a register that appears within TO.
4342 Then, after that subexpression has been scanned once by `subst',
4343 the second time it is scanned, TO may be found. If we were
4344 to scan TO here, we would find FROM within it and create a
4345 self-referent rtl structure which is completely wrong. */
4346 if (COMBINE_RTX_EQUAL_P (x, to))
4349 /* Parallel asm_operands need special attention because all of the
4350 inputs are shared across the arms. Furthermore, unsharing the
4351 rtl results in recognition failures. Failure to handle this case
4352 specially can result in circular rtl.
4354 Solve this by doing a normal pass across the first entry of the
4355 parallel, and only processing the SET_DESTs of the subsequent
4358 if (code == PARALLEL
4359 && GET_CODE (XVECEXP (x, 0, 0)) == SET
4360 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
4362 new_rtx = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
4364 /* If this substitution failed, this whole thing fails. */
4365 if (GET_CODE (new_rtx) == CLOBBER
4366 && XEXP (new_rtx, 0) == const0_rtx)
4369 SUBST (XVECEXP (x, 0, 0), new_rtx);
4371 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
4373 rtx dest = SET_DEST (XVECEXP (x, 0, i));
4376 && GET_CODE (dest) != CC0
4377 && GET_CODE (dest) != PC)
4379 new_rtx = subst (dest, from, to, 0, unique_copy);
4381 /* If this substitution failed, this whole thing fails. */
4382 if (GET_CODE (new_rtx) == CLOBBER
4383 && XEXP (new_rtx, 0) == const0_rtx)
4386 SUBST (SET_DEST (XVECEXP (x, 0, i)), new_rtx);
4392 len = GET_RTX_LENGTH (code);
4393 fmt = GET_RTX_FORMAT (code);
4395 /* We don't need to process a SET_DEST that is a register, CC0,
4396 or PC, so set up to skip this common case. All other cases
4397 where we want to suppress replacing something inside a
4398 SET_SRC are handled via the IN_DEST operand. */
4400 && (REG_P (SET_DEST (x))
4401 || GET_CODE (SET_DEST (x)) == CC0
4402 || GET_CODE (SET_DEST (x)) == PC))
4405 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
4408 op0_mode = GET_MODE (XEXP (x, 0));
4410 for (i = 0; i < len; i++)
4415 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4417 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
4419 new_rtx = (unique_copy && n_occurrences
4420 ? copy_rtx (to) : to);
4425 new_rtx = subst (XVECEXP (x, i, j), from, to, 0,
4428 /* If this substitution failed, this whole thing
4430 if (GET_CODE (new_rtx) == CLOBBER
4431 && XEXP (new_rtx, 0) == const0_rtx)
4435 SUBST (XVECEXP (x, i, j), new_rtx);
4438 else if (fmt[i] == 'e')
4440 /* If this is a register being set, ignore it. */
4441 new_rtx = XEXP (x, i);
4444 && (((code == SUBREG || code == ZERO_EXTRACT)
4446 || code == STRICT_LOW_PART))
4449 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
4451 /* In general, don't install a subreg involving two
4452 modes not tieable. It can worsen register
4453 allocation, and can even make invalid reload
4454 insns, since the reg inside may need to be copied
4455 from in the outside mode, and that may be invalid
4456 if it is an fp reg copied in integer mode.
4458 We allow two exceptions to this: It is valid if
4459 it is inside another SUBREG and the mode of that
4460 SUBREG and the mode of the inside of TO is
4461 tieable and it is valid if X is a SET that copies
4464 if (GET_CODE (to) == SUBREG
4465 && ! MODES_TIEABLE_P (GET_MODE (to),
4466 GET_MODE (SUBREG_REG (to)))
4467 && ! (code == SUBREG
4468 && MODES_TIEABLE_P (GET_MODE (x),
4469 GET_MODE (SUBREG_REG (to))))
4471 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
4474 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4476 #ifdef CANNOT_CHANGE_MODE_CLASS
4479 && REGNO (to) < FIRST_PSEUDO_REGISTER
4480 && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
4483 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4486 new_rtx = (unique_copy && n_occurrences ? copy_rtx (to) : to);
4490 /* If we are in a SET_DEST, suppress most cases unless we
4491 have gone inside a MEM, in which case we want to
4492 simplify the address. We assume here that things that
4493 are actually part of the destination have their inner
4494 parts in the first expression. This is true for SUBREG,
4495 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
4496 things aside from REG and MEM that should appear in a
4498 new_rtx = subst (XEXP (x, i), from, to,
4500 && (code == SUBREG || code == STRICT_LOW_PART
4501 || code == ZERO_EXTRACT))
4503 && i == 0), unique_copy);
4505 /* If we found that we will have to reject this combination,
4506 indicate that by returning the CLOBBER ourselves, rather than
4507 an expression containing it. This will speed things up as
4508 well as prevent accidents where two CLOBBERs are considered
4509 to be equal, thus producing an incorrect simplification. */
4511 if (GET_CODE (new_rtx) == CLOBBER && XEXP (new_rtx, 0) == const0_rtx)
4514 if (GET_CODE (x) == SUBREG
4515 && (GET_CODE (new_rtx) == CONST_INT
4516 || GET_CODE (new_rtx) == CONST_DOUBLE))
4518 enum machine_mode mode = GET_MODE (x);
4520 x = simplify_subreg (GET_MODE (x), new_rtx,
4521 GET_MODE (SUBREG_REG (x)),
4524 x = gen_rtx_CLOBBER (mode, const0_rtx);
4526 else if (GET_CODE (new_rtx) == CONST_INT
4527 && GET_CODE (x) == ZERO_EXTEND)
4529 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
4530 new_rtx, GET_MODE (XEXP (x, 0)));
4534 SUBST (XEXP (x, i), new_rtx);
4539 /* Check if we are loading something from the constant pool via float
4540 extension; in this case we would undo compress_float_constant
4541 optimization and degenerate constant load to an immediate value. */
4542 if (GET_CODE (x) == FLOAT_EXTEND
4543 && MEM_P (XEXP (x, 0))
4544 && MEM_READONLY_P (XEXP (x, 0)))
4546 rtx tmp = avoid_constant_pool_reference (x);
4551 /* Try to simplify X. If the simplification changed the code, it is likely
4552 that further simplification will help, so loop, but limit the number
4553 of repetitions that will be performed. */
4555 for (i = 0; i < 4; i++)
4557 /* If X is sufficiently simple, don't bother trying to do anything
4559 if (code != CONST_INT && code != REG && code != CLOBBER)
4560 x = combine_simplify_rtx (x, op0_mode, in_dest);
4562 if (GET_CODE (x) == code)
4565 code = GET_CODE (x);
4567 /* We no longer know the original mode of operand 0 since we
4568 have changed the form of X) */
4569 op0_mode = VOIDmode;
4575 /* Simplify X, a piece of RTL. We just operate on the expression at the
4576 outer level; call `subst' to simplify recursively. Return the new
4579 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
4580 if we are inside a SET_DEST. */
4583 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest)
4585 enum rtx_code code = GET_CODE (x);
4586 enum machine_mode mode = GET_MODE (x);
4590 /* If this is a commutative operation, put a constant last and a complex
4591 expression first. We don't need to do this for comparisons here. */
4592 if (COMMUTATIVE_ARITH_P (x)
4593 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
4596 SUBST (XEXP (x, 0), XEXP (x, 1));
4597 SUBST (XEXP (x, 1), temp);
4600 /* If this is a simple operation applied to an IF_THEN_ELSE, try
4601 applying it to the arms of the IF_THEN_ELSE. This often simplifies
4602 things. Check for cases where both arms are testing the same
4605 Don't do anything if all operands are very simple. */
4608 && ((!OBJECT_P (XEXP (x, 0))
4609 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4610 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
4611 || (!OBJECT_P (XEXP (x, 1))
4612 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
4613 && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
4615 && (!OBJECT_P (XEXP (x, 0))
4616 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4617 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
4619 rtx cond, true_rtx, false_rtx;
4621 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
4623 /* If everything is a comparison, what we have is highly unlikely
4624 to be simpler, so don't use it. */
4625 && ! (COMPARISON_P (x)
4626 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
4628 rtx cop1 = const0_rtx;
4629 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
4631 if (cond_code == NE && COMPARISON_P (cond))
4634 /* Simplify the alternative arms; this may collapse the true and
4635 false arms to store-flag values. Be careful to use copy_rtx
4636 here since true_rtx or false_rtx might share RTL with x as a
4637 result of the if_then_else_cond call above. */
4638 true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0);
4639 false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0);
4641 /* If true_rtx and false_rtx are not general_operands, an if_then_else
4642 is unlikely to be simpler. */
4643 if (general_operand (true_rtx, VOIDmode)
4644 && general_operand (false_rtx, VOIDmode))
4646 enum rtx_code reversed;
4648 /* Restarting if we generate a store-flag expression will cause
4649 us to loop. Just drop through in this case. */
4651 /* If the result values are STORE_FLAG_VALUE and zero, we can
4652 just make the comparison operation. */
4653 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
4654 x = simplify_gen_relational (cond_code, mode, VOIDmode,
4656 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
4657 && ((reversed = reversed_comparison_code_parts
4658 (cond_code, cond, cop1, NULL))
4660 x = simplify_gen_relational (reversed, mode, VOIDmode,
4663 /* Likewise, we can make the negate of a comparison operation
4664 if the result values are - STORE_FLAG_VALUE and zero. */
4665 else if (GET_CODE (true_rtx) == CONST_INT
4666 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
4667 && false_rtx == const0_rtx)
4668 x = simplify_gen_unary (NEG, mode,
4669 simplify_gen_relational (cond_code,
4673 else if (GET_CODE (false_rtx) == CONST_INT
4674 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
4675 && true_rtx == const0_rtx
4676 && ((reversed = reversed_comparison_code_parts
4677 (cond_code, cond, cop1, NULL))
4679 x = simplify_gen_unary (NEG, mode,
4680 simplify_gen_relational (reversed,
4685 return gen_rtx_IF_THEN_ELSE (mode,
4686 simplify_gen_relational (cond_code,
4691 true_rtx, false_rtx);
4693 code = GET_CODE (x);
4694 op0_mode = VOIDmode;
4699 /* Try to fold this expression in case we have constants that weren't
4702 switch (GET_RTX_CLASS (code))
4705 if (op0_mode == VOIDmode)
4706 op0_mode = GET_MODE (XEXP (x, 0));
4707 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
4710 case RTX_COMM_COMPARE:
4712 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
4713 if (cmp_mode == VOIDmode)
4715 cmp_mode = GET_MODE (XEXP (x, 1));
4716 if (cmp_mode == VOIDmode)
4717 cmp_mode = op0_mode;
4719 temp = simplify_relational_operation (code, mode, cmp_mode,
4720 XEXP (x, 0), XEXP (x, 1));
4723 case RTX_COMM_ARITH:
4725 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
4727 case RTX_BITFIELD_OPS:
4729 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
4730 XEXP (x, 1), XEXP (x, 2));
4739 code = GET_CODE (temp);
4740 op0_mode = VOIDmode;
4741 mode = GET_MODE (temp);
4744 /* First see if we can apply the inverse distributive law. */
4745 if (code == PLUS || code == MINUS
4746 || code == AND || code == IOR || code == XOR)
4748 x = apply_distributive_law (x);
4749 code = GET_CODE (x);
4750 op0_mode = VOIDmode;
4753 /* If CODE is an associative operation not otherwise handled, see if we
4754 can associate some operands. This can win if they are constants or
4755 if they are logically related (i.e. (a & b) & a). */
4756 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
4757 || code == AND || code == IOR || code == XOR
4758 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
4759 && ((INTEGRAL_MODE_P (mode) && code != DIV)
4760 || (flag_associative_math && FLOAT_MODE_P (mode))))
4762 if (GET_CODE (XEXP (x, 0)) == code)
4764 rtx other = XEXP (XEXP (x, 0), 0);
4765 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
4766 rtx inner_op1 = XEXP (x, 1);
4769 /* Make sure we pass the constant operand if any as the second
4770 one if this is a commutative operation. */
4771 if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
4773 rtx tem = inner_op0;
4774 inner_op0 = inner_op1;
4777 inner = simplify_binary_operation (code == MINUS ? PLUS
4778 : code == DIV ? MULT
4780 mode, inner_op0, inner_op1);
4782 /* For commutative operations, try the other pair if that one
4784 if (inner == 0 && COMMUTATIVE_ARITH_P (x))
4786 other = XEXP (XEXP (x, 0), 1);
4787 inner = simplify_binary_operation (code, mode,
4788 XEXP (XEXP (x, 0), 0),
4793 return simplify_gen_binary (code, mode, other, inner);
4797 /* A little bit of algebraic simplification here. */
4801 /* Ensure that our address has any ASHIFTs converted to MULT in case
4802 address-recognizing predicates are called later. */
4803 temp = make_compound_operation (XEXP (x, 0), MEM);
4804 SUBST (XEXP (x, 0), temp);
4808 if (op0_mode == VOIDmode)
4809 op0_mode = GET_MODE (SUBREG_REG (x));
4811 /* See if this can be moved to simplify_subreg. */
4812 if (CONSTANT_P (SUBREG_REG (x))
4813 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
4814 /* Don't call gen_lowpart if the inner mode
4815 is VOIDmode and we cannot simplify it, as SUBREG without
4816 inner mode is invalid. */
4817 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
4818 || gen_lowpart_common (mode, SUBREG_REG (x))))
4819 return gen_lowpart (mode, SUBREG_REG (x));
4821 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
4825 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
4831 /* Don't change the mode of the MEM if that would change the meaning
4833 if (MEM_P (SUBREG_REG (x))
4834 && (MEM_VOLATILE_P (SUBREG_REG (x))
4835 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
4836 return gen_rtx_CLOBBER (mode, const0_rtx);
4838 /* Note that we cannot do any narrowing for non-constants since
4839 we might have been counting on using the fact that some bits were
4840 zero. We now do this in the SET. */
4845 temp = expand_compound_operation (XEXP (x, 0));
4847 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4848 replaced by (lshiftrt X C). This will convert
4849 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
4851 if (GET_CODE (temp) == ASHIFTRT
4852 && GET_CODE (XEXP (temp, 1)) == CONST_INT
4853 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
4854 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
4855 INTVAL (XEXP (temp, 1)));
4857 /* If X has only a single bit that might be nonzero, say, bit I, convert
4858 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4859 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4860 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4861 or a SUBREG of one since we'd be making the expression more
4862 complex if it was just a register. */
4865 && ! (GET_CODE (temp) == SUBREG
4866 && REG_P (SUBREG_REG (temp)))
4867 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
4869 rtx temp1 = simplify_shift_const
4870 (NULL_RTX, ASHIFTRT, mode,
4871 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
4872 GET_MODE_BITSIZE (mode) - 1 - i),
4873 GET_MODE_BITSIZE (mode) - 1 - i);
4875 /* If all we did was surround TEMP with the two shifts, we
4876 haven't improved anything, so don't use it. Otherwise,
4877 we are better off with TEMP1. */
4878 if (GET_CODE (temp1) != ASHIFTRT
4879 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
4880 || XEXP (XEXP (temp1, 0), 0) != temp)
4886 /* We can't handle truncation to a partial integer mode here
4887 because we don't know the real bitsize of the partial
4889 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
4892 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4893 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4894 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4896 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
4897 GET_MODE_MASK (mode), 0));
4899 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
4900 whose value is a comparison can be replaced with a subreg if
4901 STORE_FLAG_VALUE permits. */
4902 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4903 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
4904 && (temp = get_last_value (XEXP (x, 0)))
4905 && COMPARISON_P (temp))
4906 return gen_lowpart (mode, XEXP (x, 0));
4910 /* (const (const X)) can become (const X). Do it this way rather than
4911 returning the inner CONST since CONST can be shared with a
4913 if (GET_CODE (XEXP (x, 0)) == CONST)
4914 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4919 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4920 can add in an offset. find_split_point will split this address up
4921 again if it doesn't match. */
4922 if (GET_CODE (XEXP (x, 0)) == HIGH
4923 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4929 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4930 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4931 bit-field and can be replaced by either a sign_extend or a
4932 sign_extract. The `and' may be a zero_extend and the two
4933 <c>, -<c> constants may be reversed. */
4934 if (GET_CODE (XEXP (x, 0)) == XOR
4935 && GET_CODE (XEXP (x, 1)) == CONST_INT
4936 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4937 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
4938 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4939 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4940 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4941 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4942 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4943 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4944 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4945 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4946 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4947 == (unsigned int) i + 1))))
4948 return simplify_shift_const
4949 (NULL_RTX, ASHIFTRT, mode,
4950 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4951 XEXP (XEXP (XEXP (x, 0), 0), 0),
4952 GET_MODE_BITSIZE (mode) - (i + 1)),
4953 GET_MODE_BITSIZE (mode) - (i + 1));
4955 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4956 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4957 the bitsize of the mode - 1. This allows simplification of
4958 "a = (b & 8) == 0;" */
4959 if (XEXP (x, 1) == constm1_rtx
4960 && !REG_P (XEXP (x, 0))
4961 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4962 && REG_P (SUBREG_REG (XEXP (x, 0))))
4963 && nonzero_bits (XEXP (x, 0), mode) == 1)
4964 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4965 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4966 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
4967 GET_MODE_BITSIZE (mode) - 1),
4968 GET_MODE_BITSIZE (mode) - 1);
4970 /* If we are adding two things that have no bits in common, convert
4971 the addition into an IOR. This will often be further simplified,
4972 for example in cases like ((a & 1) + (a & 2)), which can
4975 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4976 && (nonzero_bits (XEXP (x, 0), mode)
4977 & nonzero_bits (XEXP (x, 1), mode)) == 0)
4979 /* Try to simplify the expression further. */
4980 rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4981 temp = combine_simplify_rtx (tor, mode, in_dest);
4983 /* If we could, great. If not, do not go ahead with the IOR
4984 replacement, since PLUS appears in many special purpose
4985 address arithmetic instructions. */
4986 if (GET_CODE (temp) != CLOBBER && temp != tor)
4992 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4993 (and <foo> (const_int pow2-1)) */
4994 if (GET_CODE (XEXP (x, 1)) == AND
4995 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4996 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4997 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4998 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4999 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
5003 /* If we have (mult (plus A B) C), apply the distributive law and then
5004 the inverse distributive law to see if things simplify. This
5005 occurs mostly in addresses, often when unrolling loops. */
5007 if (GET_CODE (XEXP (x, 0)) == PLUS)
5009 rtx result = distribute_and_simplify_rtx (x, 0);
5014 /* Try simplify a*(b/c) as (a*b)/c. */
5015 if (FLOAT_MODE_P (mode) && flag_associative_math
5016 && GET_CODE (XEXP (x, 0)) == DIV)
5018 rtx tem = simplify_binary_operation (MULT, mode,
5019 XEXP (XEXP (x, 0), 0),
5022 return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
5027 /* If this is a divide by a power of two, treat it as a shift if
5028 its first operand is a shift. */
5029 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5030 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
5031 && (GET_CODE (XEXP (x, 0)) == ASHIFT
5032 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
5033 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
5034 || GET_CODE (XEXP (x, 0)) == ROTATE
5035 || GET_CODE (XEXP (x, 0)) == ROTATERT))
5036 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
5040 case GT: case GTU: case GE: case GEU:
5041 case LT: case LTU: case LE: case LEU:
5042 case UNEQ: case LTGT:
5043 case UNGT: case UNGE:
5044 case UNLT: case UNLE:
5045 case UNORDERED: case ORDERED:
5046 /* If the first operand is a condition code, we can't do anything
5048 if (GET_CODE (XEXP (x, 0)) == COMPARE
5049 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
5050 && ! CC0_P (XEXP (x, 0))))
5052 rtx op0 = XEXP (x, 0);
5053 rtx op1 = XEXP (x, 1);
5054 enum rtx_code new_code;
5056 if (GET_CODE (op0) == COMPARE)
5057 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
5059 /* Simplify our comparison, if possible. */
5060 new_code = simplify_comparison (code, &op0, &op1);
5062 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5063 if only the low-order bit is possibly nonzero in X (such as when
5064 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5065 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5066 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5069 Remove any ZERO_EXTRACT we made when thinking this was a
5070 comparison. It may now be simpler to use, e.g., an AND. If a
5071 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5072 the call to make_compound_operation in the SET case. */
5074 if (STORE_FLAG_VALUE == 1
5075 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5076 && op1 == const0_rtx
5077 && mode == GET_MODE (op0)
5078 && nonzero_bits (op0, mode) == 1)
5079 return gen_lowpart (mode,
5080 expand_compound_operation (op0));
5082 else if (STORE_FLAG_VALUE == 1
5083 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5084 && op1 == const0_rtx
5085 && mode == GET_MODE (op0)
5086 && (num_sign_bit_copies (op0, mode)
5087 == GET_MODE_BITSIZE (mode)))
5089 op0 = expand_compound_operation (op0);
5090 return simplify_gen_unary (NEG, mode,
5091 gen_lowpart (mode, op0),
5095 else if (STORE_FLAG_VALUE == 1
5096 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5097 && op1 == const0_rtx
5098 && mode == GET_MODE (op0)
5099 && nonzero_bits (op0, mode) == 1)
5101 op0 = expand_compound_operation (op0);
5102 return simplify_gen_binary (XOR, mode,
5103 gen_lowpart (mode, op0),
5107 else if (STORE_FLAG_VALUE == 1
5108 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5109 && op1 == const0_rtx
5110 && mode == GET_MODE (op0)
5111 && (num_sign_bit_copies (op0, mode)
5112 == GET_MODE_BITSIZE (mode)))
5114 op0 = expand_compound_operation (op0);
5115 return plus_constant (gen_lowpart (mode, op0), 1);
5118 /* If STORE_FLAG_VALUE is -1, we have cases similar to
5120 if (STORE_FLAG_VALUE == -1
5121 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5122 && op1 == const0_rtx
5123 && (num_sign_bit_copies (op0, mode)
5124 == GET_MODE_BITSIZE (mode)))
5125 return gen_lowpart (mode,
5126 expand_compound_operation (op0));
5128 else if (STORE_FLAG_VALUE == -1
5129 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5130 && op1 == const0_rtx
5131 && mode == GET_MODE (op0)
5132 && nonzero_bits (op0, mode) == 1)
5134 op0 = expand_compound_operation (op0);
5135 return simplify_gen_unary (NEG, mode,
5136 gen_lowpart (mode, op0),
5140 else if (STORE_FLAG_VALUE == -1
5141 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5142 && op1 == const0_rtx
5143 && mode == GET_MODE (op0)
5144 && (num_sign_bit_copies (op0, mode)
5145 == GET_MODE_BITSIZE (mode)))
5147 op0 = expand_compound_operation (op0);
5148 return simplify_gen_unary (NOT, mode,
5149 gen_lowpart (mode, op0),
5153 /* If X is 0/1, (eq X 0) is X-1. */
5154 else if (STORE_FLAG_VALUE == -1
5155 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5156 && op1 == const0_rtx
5157 && mode == GET_MODE (op0)
5158 && nonzero_bits (op0, mode) == 1)
5160 op0 = expand_compound_operation (op0);
5161 return plus_constant (gen_lowpart (mode, op0), -1);
5164 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5165 one bit that might be nonzero, we can convert (ne x 0) to
5166 (ashift x c) where C puts the bit in the sign bit. Remove any
5167 AND with STORE_FLAG_VALUE when we are done, since we are only
5168 going to test the sign bit. */
5169 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5170 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5171 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5172 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5173 && op1 == const0_rtx
5174 && mode == GET_MODE (op0)
5175 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
5177 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
5178 expand_compound_operation (op0),
5179 GET_MODE_BITSIZE (mode) - 1 - i);
5180 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
5186 /* If the code changed, return a whole new comparison. */
5187 if (new_code != code)
5188 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
5190 /* Otherwise, keep this operation, but maybe change its operands.
5191 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
5192 SUBST (XEXP (x, 0), op0);
5193 SUBST (XEXP (x, 1), op1);
5198 return simplify_if_then_else (x);
5204 /* If we are processing SET_DEST, we are done. */
5208 return expand_compound_operation (x);
5211 return simplify_set (x);
5215 return simplify_logical (x);
5222 /* If this is a shift by a constant amount, simplify it. */
5223 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
5224 return simplify_shift_const (x, code, mode, XEXP (x, 0),
5225 INTVAL (XEXP (x, 1)));
5227 else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
5229 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
5231 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
5243 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
5246 simplify_if_then_else (rtx x)
5248 enum machine_mode mode = GET_MODE (x);
5249 rtx cond = XEXP (x, 0);
5250 rtx true_rtx = XEXP (x, 1);
5251 rtx false_rtx = XEXP (x, 2);
5252 enum rtx_code true_code = GET_CODE (cond);
5253 int comparison_p = COMPARISON_P (cond);
5256 enum rtx_code false_code;
5259 /* Simplify storing of the truth value. */
5260 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
5261 return simplify_gen_relational (true_code, mode, VOIDmode,
5262 XEXP (cond, 0), XEXP (cond, 1));
5264 /* Also when the truth value has to be reversed. */
5266 && true_rtx == const0_rtx && false_rtx == const_true_rtx
5267 && (reversed = reversed_comparison (cond, mode)))
5270 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
5271 in it is being compared against certain values. Get the true and false
5272 comparisons and see if that says anything about the value of each arm. */
5275 && ((false_code = reversed_comparison_code (cond, NULL))
5277 && REG_P (XEXP (cond, 0)))
5280 rtx from = XEXP (cond, 0);
5281 rtx true_val = XEXP (cond, 1);
5282 rtx false_val = true_val;
5285 /* If FALSE_CODE is EQ, swap the codes and arms. */
5287 if (false_code == EQ)
5289 swapped = 1, true_code = EQ, false_code = NE;
5290 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5293 /* If we are comparing against zero and the expression being tested has
5294 only a single bit that might be nonzero, that is its value when it is
5295 not equal to zero. Similarly if it is known to be -1 or 0. */
5297 if (true_code == EQ && true_val == const0_rtx
5298 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
5301 false_val = GEN_INT (trunc_int_for_mode (nzb, GET_MODE (from)));
5303 else if (true_code == EQ && true_val == const0_rtx
5304 && (num_sign_bit_copies (from, GET_MODE (from))
5305 == GET_MODE_BITSIZE (GET_MODE (from))))
5308 false_val = constm1_rtx;
5311 /* Now simplify an arm if we know the value of the register in the
5312 branch and it is used in the arm. Be careful due to the potential
5313 of locally-shared RTL. */
5315 if (reg_mentioned_p (from, true_rtx))
5316 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
5318 pc_rtx, pc_rtx, 0, 0);
5319 if (reg_mentioned_p (from, false_rtx))
5320 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
5322 pc_rtx, pc_rtx, 0, 0);
5324 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
5325 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
5327 true_rtx = XEXP (x, 1);
5328 false_rtx = XEXP (x, 2);
5329 true_code = GET_CODE (cond);
5332 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
5333 reversed, do so to avoid needing two sets of patterns for
5334 subtract-and-branch insns. Similarly if we have a constant in the true
5335 arm, the false arm is the same as the first operand of the comparison, or
5336 the false arm is more complicated than the true arm. */
5339 && reversed_comparison_code (cond, NULL) != UNKNOWN
5340 && (true_rtx == pc_rtx
5341 || (CONSTANT_P (true_rtx)
5342 && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx)
5343 || true_rtx == const0_rtx
5344 || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
5345 || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
5346 && !OBJECT_P (false_rtx))
5347 || reg_mentioned_p (true_rtx, false_rtx)
5348 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
5350 true_code = reversed_comparison_code (cond, NULL);
5351 SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
5352 SUBST (XEXP (x, 1), false_rtx);
5353 SUBST (XEXP (x, 2), true_rtx);
5355 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5358 /* It is possible that the conditional has been simplified out. */
5359 true_code = GET_CODE (cond);
5360 comparison_p = COMPARISON_P (cond);
5363 /* If the two arms are identical, we don't need the comparison. */
5365 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
5368 /* Convert a == b ? b : a to "a". */
5369 if (true_code == EQ && ! side_effects_p (cond)
5370 && !HONOR_NANS (mode)
5371 && rtx_equal_p (XEXP (cond, 0), false_rtx)
5372 && rtx_equal_p (XEXP (cond, 1), true_rtx))
5374 else if (true_code == NE && ! side_effects_p (cond)
5375 && !HONOR_NANS (mode)
5376 && rtx_equal_p (XEXP (cond, 0), true_rtx)
5377 && rtx_equal_p (XEXP (cond, 1), false_rtx))
5380 /* Look for cases where we have (abs x) or (neg (abs X)). */
5382 if (GET_MODE_CLASS (mode) == MODE_INT
5384 && XEXP (cond, 1) == const0_rtx
5385 && GET_CODE (false_rtx) == NEG
5386 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
5387 && rtx_equal_p (true_rtx, XEXP (cond, 0))
5388 && ! side_effects_p (true_rtx))
5393 return simplify_gen_unary (ABS, mode, true_rtx, mode);
5397 simplify_gen_unary (NEG, mode,
5398 simplify_gen_unary (ABS, mode, true_rtx, mode),
5404 /* Look for MIN or MAX. */
5406 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
5408 && rtx_equal_p (XEXP (cond, 0), true_rtx)
5409 && rtx_equal_p (XEXP (cond, 1), false_rtx)
5410 && ! side_effects_p (cond))
5415 return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
5418 return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
5421 return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
5424 return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
5429 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
5430 second operand is zero, this can be done as (OP Z (mult COND C2)) where
5431 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
5432 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
5433 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
5434 neither 1 or -1, but it isn't worth checking for. */
5436 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
5438 && GET_MODE_CLASS (mode) == MODE_INT
5439 && ! side_effects_p (x))
5441 rtx t = make_compound_operation (true_rtx, SET);
5442 rtx f = make_compound_operation (false_rtx, SET);
5443 rtx cond_op0 = XEXP (cond, 0);
5444 rtx cond_op1 = XEXP (cond, 1);
5445 enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
5446 enum machine_mode m = mode;
5447 rtx z = 0, c1 = NULL_RTX;
5449 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
5450 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
5451 || GET_CODE (t) == ASHIFT
5452 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
5453 && rtx_equal_p (XEXP (t, 0), f))
5454 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
5456 /* If an identity-zero op is commutative, check whether there
5457 would be a match if we swapped the operands. */
5458 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
5459 || GET_CODE (t) == XOR)
5460 && rtx_equal_p (XEXP (t, 1), f))
5461 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
5462 else if (GET_CODE (t) == SIGN_EXTEND
5463 && (GET_CODE (XEXP (t, 0)) == PLUS
5464 || GET_CODE (XEXP (t, 0)) == MINUS
5465 || GET_CODE (XEXP (t, 0)) == IOR
5466 || GET_CODE (XEXP (t, 0)) == XOR
5467 || GET_CODE (XEXP (t, 0)) == ASHIFT
5468 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5469 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5470 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5471 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5472 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5473 && (num_sign_bit_copies (f, GET_MODE (f))
5475 (GET_MODE_BITSIZE (mode)
5476 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
5478 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5479 extend_op = SIGN_EXTEND;
5480 m = GET_MODE (XEXP (t, 0));
5482 else if (GET_CODE (t) == SIGN_EXTEND
5483 && (GET_CODE (XEXP (t, 0)) == PLUS
5484 || GET_CODE (XEXP (t, 0)) == IOR
5485 || GET_CODE (XEXP (t, 0)) == XOR)
5486 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5487 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5488 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5489 && (num_sign_bit_copies (f, GET_MODE (f))
5491 (GET_MODE_BITSIZE (mode)
5492 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
5494 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5495 extend_op = SIGN_EXTEND;
5496 m = GET_MODE (XEXP (t, 0));
5498 else if (GET_CODE (t) == ZERO_EXTEND
5499 && (GET_CODE (XEXP (t, 0)) == PLUS
5500 || GET_CODE (XEXP (t, 0)) == MINUS
5501 || GET_CODE (XEXP (t, 0)) == IOR
5502 || GET_CODE (XEXP (t, 0)) == XOR
5503 || GET_CODE (XEXP (t, 0)) == ASHIFT
5504 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5505 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5506 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5507 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5508 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5509 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5510 && ((nonzero_bits (f, GET_MODE (f))
5511 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
5514 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5515 extend_op = ZERO_EXTEND;
5516 m = GET_MODE (XEXP (t, 0));
5518 else if (GET_CODE (t) == ZERO_EXTEND
5519 && (GET_CODE (XEXP (t, 0)) == PLUS
5520 || GET_CODE (XEXP (t, 0)) == IOR
5521 || GET_CODE (XEXP (t, 0)) == XOR)
5522 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5523 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5524 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5525 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5526 && ((nonzero_bits (f, GET_MODE (f))
5527 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
5530 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5531 extend_op = ZERO_EXTEND;
5532 m = GET_MODE (XEXP (t, 0));
5537 temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
5538 cond_op0, cond_op1),
5539 pc_rtx, pc_rtx, 0, 0);
5540 temp = simplify_gen_binary (MULT, m, temp,
5541 simplify_gen_binary (MULT, m, c1,
5543 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
5544 temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
5546 if (extend_op != UNKNOWN)
5547 temp = simplify_gen_unary (extend_op, mode, temp, m);
5553 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5554 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5555 negation of a single bit, we can convert this operation to a shift. We
5556 can actually do this more generally, but it doesn't seem worth it. */
5558 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5559 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5560 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
5561 && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
5562 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
5563 == GET_MODE_BITSIZE (mode))
5564 && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
5566 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5567 gen_lowpart (mode, XEXP (cond, 0)), i);
5569 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
5570 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5571 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5572 && GET_MODE (XEXP (cond, 0)) == mode
5573 && (INTVAL (true_rtx) & GET_MODE_MASK (mode))
5574 == nonzero_bits (XEXP (cond, 0), mode)
5575 && (i = exact_log2 (INTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
5576 return XEXP (cond, 0);
5581 /* Simplify X, a SET expression. Return the new expression. */
5584 simplify_set (rtx x)
5586 rtx src = SET_SRC (x);
5587 rtx dest = SET_DEST (x);
5588 enum machine_mode mode
5589 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
5593 /* (set (pc) (return)) gets written as (return). */
5594 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
5597 /* Now that we know for sure which bits of SRC we are using, see if we can
5598 simplify the expression for the object knowing that we only need the
5601 if (GET_MODE_CLASS (mode) == MODE_INT
5602 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5604 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, 0);
5605 SUBST (SET_SRC (x), src);
5608 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5609 the comparison result and try to simplify it unless we already have used
5610 undobuf.other_insn. */
5611 if ((GET_MODE_CLASS (mode) == MODE_CC
5612 || GET_CODE (src) == COMPARE
5614 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
5615 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
5616 && COMPARISON_P (*cc_use)
5617 && rtx_equal_p (XEXP (*cc_use, 0), dest))
5619 enum rtx_code old_code = GET_CODE (*cc_use);
5620 enum rtx_code new_code;
5622 int other_changed = 0;
5623 enum machine_mode compare_mode = GET_MODE (dest);
5625 if (GET_CODE (src) == COMPARE)
5626 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
5628 op0 = src, op1 = CONST0_RTX (GET_MODE (src));
5630 tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
5633 new_code = old_code;
5634 else if (!CONSTANT_P (tmp))
5636 new_code = GET_CODE (tmp);
5637 op0 = XEXP (tmp, 0);
5638 op1 = XEXP (tmp, 1);
5642 rtx pat = PATTERN (other_insn);
5643 undobuf.other_insn = other_insn;
5644 SUBST (*cc_use, tmp);
5646 /* Attempt to simplify CC user. */
5647 if (GET_CODE (pat) == SET)
5649 rtx new_rtx = simplify_rtx (SET_SRC (pat));
5650 if (new_rtx != NULL_RTX)
5651 SUBST (SET_SRC (pat), new_rtx);
5654 /* Convert X into a no-op move. */
5655 SUBST (SET_DEST (x), pc_rtx);
5656 SUBST (SET_SRC (x), pc_rtx);
5660 /* Simplify our comparison, if possible. */
5661 new_code = simplify_comparison (new_code, &op0, &op1);
5663 #ifdef SELECT_CC_MODE
5664 /* If this machine has CC modes other than CCmode, check to see if we
5665 need to use a different CC mode here. */
5666 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
5667 compare_mode = GET_MODE (op0);
5669 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5672 /* If the mode changed, we have to change SET_DEST, the mode in the
5673 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5674 a hard register, just build new versions with the proper mode. If it
5675 is a pseudo, we lose unless it is only time we set the pseudo, in
5676 which case we can safely change its mode. */
5677 if (compare_mode != GET_MODE (dest))
5679 if (can_change_dest_mode (dest, 0, compare_mode))
5681 unsigned int regno = REGNO (dest);
5684 if (regno < FIRST_PSEUDO_REGISTER)
5685 new_dest = gen_rtx_REG (compare_mode, regno);
5688 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
5689 new_dest = regno_reg_rtx[regno];
5692 SUBST (SET_DEST (x), new_dest);
5693 SUBST (XEXP (*cc_use, 0), new_dest);
5700 #endif /* SELECT_CC_MODE */
5702 /* If the code changed, we have to build a new comparison in
5703 undobuf.other_insn. */
5704 if (new_code != old_code)
5706 int other_changed_previously = other_changed;
5707 unsigned HOST_WIDE_INT mask;
5708 rtx old_cc_use = *cc_use;
5710 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5714 /* If the only change we made was to change an EQ into an NE or
5715 vice versa, OP0 has only one bit that might be nonzero, and OP1
5716 is zero, check if changing the user of the condition code will
5717 produce a valid insn. If it won't, we can keep the original code
5718 in that insn by surrounding our operation with an XOR. */
5720 if (((old_code == NE && new_code == EQ)
5721 || (old_code == EQ && new_code == NE))
5722 && ! other_changed_previously && op1 == const0_rtx
5723 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5724 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5726 rtx pat = PATTERN (other_insn), note = 0;
5728 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
5729 && ! check_asm_operands (pat)))
5731 *cc_use = old_cc_use;
5734 op0 = simplify_gen_binary (XOR, GET_MODE (op0),
5735 op0, GEN_INT (mask));
5741 undobuf.other_insn = other_insn;
5743 /* Otherwise, if we didn't previously have a COMPARE in the
5744 correct mode, we need one. */
5745 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5747 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5750 else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
5752 SUBST (SET_SRC (x), op0);
5755 /* Otherwise, update the COMPARE if needed. */
5756 else if (XEXP (src, 0) != op0 || XEXP (src, 1) != op1)
5758 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5764 /* Get SET_SRC in a form where we have placed back any
5765 compound expressions. Then do the checks below. */
5766 src = make_compound_operation (src, SET);
5767 SUBST (SET_SRC (x), src);
5770 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5771 and X being a REG or (subreg (reg)), we may be able to convert this to
5772 (set (subreg:m2 x) (op)).
5774 We can always do this if M1 is narrower than M2 because that means that
5775 we only care about the low bits of the result.
5777 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5778 perform a narrower operation than requested since the high-order bits will
5779 be undefined. On machine where it is defined, this transformation is safe
5780 as long as M1 and M2 have the same number of words. */
5782 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5783 && !OBJECT_P (SUBREG_REG (src))
5784 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5786 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5787 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5788 #ifndef WORD_REGISTER_OPERATIONS
5789 && (GET_MODE_SIZE (GET_MODE (src))
5790 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5792 #ifdef CANNOT_CHANGE_MODE_CLASS
5793 && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
5794 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
5795 GET_MODE (SUBREG_REG (src)),
5799 || (GET_CODE (dest) == SUBREG
5800 && REG_P (SUBREG_REG (dest)))))
5802 SUBST (SET_DEST (x),
5803 gen_lowpart (GET_MODE (SUBREG_REG (src)),
5805 SUBST (SET_SRC (x), SUBREG_REG (src));
5807 src = SET_SRC (x), dest = SET_DEST (x);
5811 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5814 && GET_CODE (src) == SUBREG
5815 && subreg_lowpart_p (src)
5816 && (GET_MODE_BITSIZE (GET_MODE (src))
5817 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
5819 rtx inner = SUBREG_REG (src);
5820 enum machine_mode inner_mode = GET_MODE (inner);
5822 /* Here we make sure that we don't have a sign bit on. */
5823 if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
5824 && (nonzero_bits (inner, inner_mode)
5825 < ((unsigned HOST_WIDE_INT) 1
5826 << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
5828 SUBST (SET_SRC (x), inner);
5834 #ifdef LOAD_EXTEND_OP
5835 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5836 would require a paradoxical subreg. Replace the subreg with a
5837 zero_extend to avoid the reload that would otherwise be required. */
5839 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5840 && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src)))
5841 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
5842 && SUBREG_BYTE (src) == 0
5843 && (GET_MODE_SIZE (GET_MODE (src))
5844 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5845 && MEM_P (SUBREG_REG (src)))
5848 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5849 GET_MODE (src), SUBREG_REG (src)));
5855 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5856 are comparing an item known to be 0 or -1 against 0, use a logical
5857 operation instead. Check for one of the arms being an IOR of the other
5858 arm with some value. We compute three terms to be IOR'ed together. In
5859 practice, at most two will be nonzero. Then we do the IOR's. */
5861 if (GET_CODE (dest) != PC
5862 && GET_CODE (src) == IF_THEN_ELSE
5863 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5864 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5865 && XEXP (XEXP (src, 0), 1) == const0_rtx
5866 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5867 #ifdef HAVE_conditional_move
5868 && ! can_conditionally_move_p (GET_MODE (src))
5870 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5871 GET_MODE (XEXP (XEXP (src, 0), 0)))
5872 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5873 && ! side_effects_p (src))
5875 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
5876 ? XEXP (src, 1) : XEXP (src, 2));
5877 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
5878 ? XEXP (src, 2) : XEXP (src, 1));
5879 rtx term1 = const0_rtx, term2, term3;
5881 if (GET_CODE (true_rtx) == IOR
5882 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
5883 term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
5884 else if (GET_CODE (true_rtx) == IOR
5885 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
5886 term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
5887 else if (GET_CODE (false_rtx) == IOR
5888 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
5889 term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
5890 else if (GET_CODE (false_rtx) == IOR
5891 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
5892 term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
5894 term2 = simplify_gen_binary (AND, GET_MODE (src),
5895 XEXP (XEXP (src, 0), 0), true_rtx);
5896 term3 = simplify_gen_binary (AND, GET_MODE (src),
5897 simplify_gen_unary (NOT, GET_MODE (src),
5898 XEXP (XEXP (src, 0), 0),
5903 simplify_gen_binary (IOR, GET_MODE (src),
5904 simplify_gen_binary (IOR, GET_MODE (src),
5911 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5912 whole thing fail. */
5913 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5915 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5918 /* Convert this into a field assignment operation, if possible. */
5919 return make_field_assignment (x);
5922 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5926 simplify_logical (rtx x)
5928 enum machine_mode mode = GET_MODE (x);
5929 rtx op0 = XEXP (x, 0);
5930 rtx op1 = XEXP (x, 1);
5932 switch (GET_CODE (x))
5935 /* We can call simplify_and_const_int only if we don't lose
5936 any (sign) bits when converting INTVAL (op1) to
5937 "unsigned HOST_WIDE_INT". */
5938 if (GET_CODE (op1) == CONST_INT
5939 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5940 || INTVAL (op1) > 0))
5942 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5943 if (GET_CODE (x) != AND)
5950 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
5951 apply the distributive law and then the inverse distributive
5952 law to see if things simplify. */
5953 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5955 rtx result = distribute_and_simplify_rtx (x, 0);
5959 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5961 rtx result = distribute_and_simplify_rtx (x, 1);
5968 /* If we have (ior (and A B) C), apply the distributive law and then
5969 the inverse distributive law to see if things simplify. */
5971 if (GET_CODE (op0) == AND)
5973 rtx result = distribute_and_simplify_rtx (x, 0);
5978 if (GET_CODE (op1) == AND)
5980 rtx result = distribute_and_simplify_rtx (x, 1);
5993 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5994 operations" because they can be replaced with two more basic operations.
5995 ZERO_EXTEND is also considered "compound" because it can be replaced with
5996 an AND operation, which is simpler, though only one operation.
5998 The function expand_compound_operation is called with an rtx expression
5999 and will convert it to the appropriate shifts and AND operations,
6000 simplifying at each stage.
6002 The function make_compound_operation is called to convert an expression
6003 consisting of shifts and ANDs into the equivalent compound expression.
6004 It is the inverse of this function, loosely speaking. */
6007 expand_compound_operation (rtx x)
6009 unsigned HOST_WIDE_INT pos = 0, len;
6011 unsigned int modewidth;
6014 switch (GET_CODE (x))
6019 /* We can't necessarily use a const_int for a multiword mode;
6020 it depends on implicitly extending the value.
6021 Since we don't know the right way to extend it,
6022 we can't tell whether the implicit way is right.
6024 Even for a mode that is no wider than a const_int,
6025 we can't win, because we need to sign extend one of its bits through
6026 the rest of it, and we don't know which bit. */
6027 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
6030 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6031 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6032 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6033 reloaded. If not for that, MEM's would very rarely be safe.
6035 Reject MODEs bigger than a word, because we might not be able
6036 to reference a two-register group starting with an arbitrary register
6037 (and currently gen_lowpart might crash for a SUBREG). */
6039 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
6042 /* Reject MODEs that aren't scalar integers because turning vector
6043 or complex modes into shifts causes problems. */
6045 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6048 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
6049 /* If the inner object has VOIDmode (the only way this can happen
6050 is if it is an ASM_OPERANDS), we can't do anything since we don't
6051 know how much masking to do. */
6060 /* ... fall through ... */
6063 /* If the operand is a CLOBBER, just return it. */
6064 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
6067 if (GET_CODE (XEXP (x, 1)) != CONST_INT
6068 || GET_CODE (XEXP (x, 2)) != CONST_INT
6069 || GET_MODE (XEXP (x, 0)) == VOIDmode)
6072 /* Reject MODEs that aren't scalar integers because turning vector
6073 or complex modes into shifts causes problems. */
6075 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6078 len = INTVAL (XEXP (x, 1));
6079 pos = INTVAL (XEXP (x, 2));
6081 /* This should stay within the object being extracted, fail otherwise. */
6082 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
6085 if (BITS_BIG_ENDIAN)
6086 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
6093 /* Convert sign extension to zero extension, if we know that the high
6094 bit is not set, as this is easier to optimize. It will be converted
6095 back to cheaper alternative in make_extraction. */
6096 if (GET_CODE (x) == SIGN_EXTEND
6097 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6098 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6099 & ~(((unsigned HOST_WIDE_INT)
6100 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
6104 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
6105 rtx temp2 = expand_compound_operation (temp);
6107 /* Make sure this is a profitable operation. */
6108 if (rtx_cost (x, SET, optimize_this_for_speed_p)
6109 > rtx_cost (temp2, SET, optimize_this_for_speed_p))
6111 else if (rtx_cost (x, SET, optimize_this_for_speed_p)
6112 > rtx_cost (temp, SET, optimize_this_for_speed_p))
6118 /* We can optimize some special cases of ZERO_EXTEND. */
6119 if (GET_CODE (x) == ZERO_EXTEND)
6121 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6122 know that the last value didn't have any inappropriate bits
6124 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6125 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6126 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6127 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
6128 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6129 return XEXP (XEXP (x, 0), 0);
6131 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6132 if (GET_CODE (XEXP (x, 0)) == SUBREG
6133 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6134 && subreg_lowpart_p (XEXP (x, 0))
6135 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6136 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
6137 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6138 return SUBREG_REG (XEXP (x, 0));
6140 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6141 is a comparison and STORE_FLAG_VALUE permits. This is like
6142 the first case, but it works even when GET_MODE (x) is larger
6143 than HOST_WIDE_INT. */
6144 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6145 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6146 && COMPARISON_P (XEXP (XEXP (x, 0), 0))
6147 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6148 <= HOST_BITS_PER_WIDE_INT)
6149 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
6150 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6151 return XEXP (XEXP (x, 0), 0);
6153 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6154 if (GET_CODE (XEXP (x, 0)) == SUBREG
6155 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6156 && subreg_lowpart_p (XEXP (x, 0))
6157 && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
6158 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6159 <= HOST_BITS_PER_WIDE_INT)
6160 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
6161 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6162 return SUBREG_REG (XEXP (x, 0));
6166 /* If we reach here, we want to return a pair of shifts. The inner
6167 shift is a left shift of BITSIZE - POS - LEN bits. The outer
6168 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
6169 logical depending on the value of UNSIGNEDP.
6171 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6172 converted into an AND of a shift.
6174 We must check for the case where the left shift would have a negative
6175 count. This can happen in a case like (x >> 31) & 255 on machines
6176 that can't shift by a constant. On those machines, we would first
6177 combine the shift with the AND to produce a variable-position
6178 extraction. Then the constant of 31 would be substituted in to produce
6179 a such a position. */
6181 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
6182 if (modewidth + len >= pos)
6184 enum machine_mode mode = GET_MODE (x);
6185 tem = gen_lowpart (mode, XEXP (x, 0));
6186 if (!tem || GET_CODE (tem) == CLOBBER)
6188 tem = simplify_shift_const (NULL_RTX, ASHIFT, mode,
6189 tem, modewidth - pos - len);
6190 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
6191 mode, tem, modewidth - len);
6193 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
6194 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
6195 simplify_shift_const (NULL_RTX, LSHIFTRT,
6198 ((HOST_WIDE_INT) 1 << len) - 1);
6200 /* Any other cases we can't handle. */
6203 /* If we couldn't do this for some reason, return the original
6205 if (GET_CODE (tem) == CLOBBER)
6211 /* X is a SET which contains an assignment of one object into
6212 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6213 or certain SUBREGS). If possible, convert it into a series of
6216 We half-heartedly support variable positions, but do not at all
6217 support variable lengths. */
6220 expand_field_assignment (const_rtx x)
6223 rtx pos; /* Always counts from low bit. */
6225 rtx mask, cleared, masked;
6226 enum machine_mode compute_mode;
6228 /* Loop until we find something we can't simplify. */
6231 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
6232 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
6234 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
6235 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
6236 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
6238 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
6239 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
6241 inner = XEXP (SET_DEST (x), 0);
6242 len = INTVAL (XEXP (SET_DEST (x), 1));
6243 pos = XEXP (SET_DEST (x), 2);
6245 /* A constant position should stay within the width of INNER. */
6246 if (GET_CODE (pos) == CONST_INT
6247 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
6250 if (BITS_BIG_ENDIAN)
6252 if (GET_CODE (pos) == CONST_INT)
6253 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
6255 else if (GET_CODE (pos) == MINUS
6256 && GET_CODE (XEXP (pos, 1)) == CONST_INT
6257 && (INTVAL (XEXP (pos, 1))
6258 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
6259 /* If position is ADJUST - X, new position is X. */
6260 pos = XEXP (pos, 0);
6262 pos = simplify_gen_binary (MINUS, GET_MODE (pos),
6263 GEN_INT (GET_MODE_BITSIZE (
6270 /* A SUBREG between two modes that occupy the same numbers of words
6271 can be done by moving the SUBREG to the source. */
6272 else if (GET_CODE (SET_DEST (x)) == SUBREG
6273 /* We need SUBREGs to compute nonzero_bits properly. */
6274 && nonzero_sign_valid
6275 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
6276 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
6277 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
6278 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
6280 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
6282 (GET_MODE (SUBREG_REG (SET_DEST (x))),
6289 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6290 inner = SUBREG_REG (inner);
6292 compute_mode = GET_MODE (inner);
6294 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6295 if (! SCALAR_INT_MODE_P (compute_mode))
6297 enum machine_mode imode;
6299 /* Don't do anything for vector or complex integral types. */
6300 if (! FLOAT_MODE_P (compute_mode))
6303 /* Try to find an integral mode to pun with. */
6304 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
6305 if (imode == BLKmode)
6308 compute_mode = imode;
6309 inner = gen_lowpart (imode, inner);
6312 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6313 if (len >= HOST_BITS_PER_WIDE_INT)
6316 /* Now compute the equivalent expression. Make a copy of INNER
6317 for the SET_DEST in case it is a MEM into which we will substitute;
6318 we don't want shared RTL in that case. */
6319 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
6320 cleared = simplify_gen_binary (AND, compute_mode,
6321 simplify_gen_unary (NOT, compute_mode,
6322 simplify_gen_binary (ASHIFT,
6327 masked = simplify_gen_binary (ASHIFT, compute_mode,
6328 simplify_gen_binary (
6330 gen_lowpart (compute_mode, SET_SRC (x)),
6334 x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
6335 simplify_gen_binary (IOR, compute_mode,
6342 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6343 it is an RTX that represents a variable starting position; otherwise,
6344 POS is the (constant) starting bit position (counted from the LSB).
6346 UNSIGNEDP is nonzero for an unsigned reference and zero for a
6349 IN_DEST is nonzero if this is a reference in the destination of a
6350 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6351 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6354 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
6355 ZERO_EXTRACT should be built even for bits starting at bit 0.
6357 MODE is the desired mode of the result (if IN_DEST == 0).
6359 The result is an RTX for the extraction or NULL_RTX if the target
6363 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
6364 rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
6365 int in_dest, int in_compare)
6367 /* This mode describes the size of the storage area
6368 to fetch the overall value from. Within that, we
6369 ignore the POS lowest bits, etc. */
6370 enum machine_mode is_mode = GET_MODE (inner);
6371 enum machine_mode inner_mode;
6372 enum machine_mode wanted_inner_mode;
6373 enum machine_mode wanted_inner_reg_mode = word_mode;
6374 enum machine_mode pos_mode = word_mode;
6375 enum machine_mode extraction_mode = word_mode;
6376 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
6378 rtx orig_pos_rtx = pos_rtx;
6379 HOST_WIDE_INT orig_pos;
6381 if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6383 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
6384 consider just the QI as the memory to extract from.
6385 The subreg adds or removes high bits; its mode is
6386 irrelevant to the meaning of this extraction,
6387 since POS and LEN count from the lsb. */
6388 if (MEM_P (SUBREG_REG (inner)))
6389 is_mode = GET_MODE (SUBREG_REG (inner));
6390 inner = SUBREG_REG (inner);
6392 else if (GET_CODE (inner) == ASHIFT
6393 && GET_CODE (XEXP (inner, 1)) == CONST_INT
6394 && pos_rtx == 0 && pos == 0
6395 && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1)))
6397 /* We're extracting the least significant bits of an rtx
6398 (ashift X (const_int C)), where LEN > C. Extract the
6399 least significant (LEN - C) bits of X, giving an rtx
6400 whose mode is MODE, then shift it left C times. */
6401 new_rtx = make_extraction (mode, XEXP (inner, 0),
6402 0, 0, len - INTVAL (XEXP (inner, 1)),
6403 unsignedp, in_dest, in_compare);
6405 return gen_rtx_ASHIFT (mode, new_rtx, XEXP (inner, 1));
6408 inner_mode = GET_MODE (inner);
6410 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
6411 pos = INTVAL (pos_rtx), pos_rtx = 0;
6413 /* See if this can be done without an extraction. We never can if the
6414 width of the field is not the same as that of some integer mode. For
6415 registers, we can only avoid the extraction if the position is at the
6416 low-order bit and this is either not in the destination or we have the
6417 appropriate STRICT_LOW_PART operation available.
6419 For MEM, we can avoid an extract if the field starts on an appropriate
6420 boundary and we can change the mode of the memory reference. */
6422 if (tmode != BLKmode
6423 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
6425 && (inner_mode == tmode
6427 || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
6428 GET_MODE_BITSIZE (inner_mode))
6429 || reg_truncated_to_mode (tmode, inner))
6432 && have_insn_for (STRICT_LOW_PART, tmode))))
6433 || (MEM_P (inner) && pos_rtx == 0
6435 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
6436 : BITS_PER_UNIT)) == 0
6437 /* We can't do this if we are widening INNER_MODE (it
6438 may not be aligned, for one thing). */
6439 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
6440 && (inner_mode == tmode
6441 || (! mode_dependent_address_p (XEXP (inner, 0))
6442 && ! MEM_VOLATILE_P (inner))))))
6444 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6445 field. If the original and current mode are the same, we need not
6446 adjust the offset. Otherwise, we do if bytes big endian.
6448 If INNER is not a MEM, get a piece consisting of just the field
6449 of interest (in this case POS % BITS_PER_WORD must be 0). */
6453 HOST_WIDE_INT offset;
6455 /* POS counts from lsb, but make OFFSET count in memory order. */
6456 if (BYTES_BIG_ENDIAN)
6457 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
6459 offset = pos / BITS_PER_UNIT;
6461 new_rtx = adjust_address_nv (inner, tmode, offset);
6463 else if (REG_P (inner))
6465 if (tmode != inner_mode)
6467 /* We can't call gen_lowpart in a DEST since we
6468 always want a SUBREG (see below) and it would sometimes
6469 return a new hard register. */
6472 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
6474 if (WORDS_BIG_ENDIAN
6475 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
6476 final_word = ((GET_MODE_SIZE (inner_mode)
6477 - GET_MODE_SIZE (tmode))
6478 / UNITS_PER_WORD) - final_word;
6480 final_word *= UNITS_PER_WORD;
6481 if (BYTES_BIG_ENDIAN &&
6482 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
6483 final_word += (GET_MODE_SIZE (inner_mode)
6484 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
6486 /* Avoid creating invalid subregs, for example when
6487 simplifying (x>>32)&255. */
6488 if (!validate_subreg (tmode, inner_mode, inner, final_word))
6491 new_rtx = gen_rtx_SUBREG (tmode, inner, final_word);
6494 new_rtx = gen_lowpart (tmode, inner);
6500 new_rtx = force_to_mode (inner, tmode,
6501 len >= HOST_BITS_PER_WIDE_INT
6502 ? ~(unsigned HOST_WIDE_INT) 0
6503 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6506 /* If this extraction is going into the destination of a SET,
6507 make a STRICT_LOW_PART unless we made a MEM. */
6510 return (MEM_P (new_rtx) ? new_rtx
6511 : (GET_CODE (new_rtx) != SUBREG
6512 ? gen_rtx_CLOBBER (tmode, const0_rtx)
6513 : gen_rtx_STRICT_LOW_PART (VOIDmode, new_rtx)));
6518 if (GET_CODE (new_rtx) == CONST_INT)
6519 return gen_int_mode (INTVAL (new_rtx), mode);
6521 /* If we know that no extraneous bits are set, and that the high
6522 bit is not set, convert the extraction to the cheaper of
6523 sign and zero extension, that are equivalent in these cases. */
6524 if (flag_expensive_optimizations
6525 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6526 && ((nonzero_bits (new_rtx, tmode)
6527 & ~(((unsigned HOST_WIDE_INT)
6528 GET_MODE_MASK (tmode))
6532 rtx temp = gen_rtx_ZERO_EXTEND (mode, new_rtx);
6533 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new_rtx);
6535 /* Prefer ZERO_EXTENSION, since it gives more information to
6537 if (rtx_cost (temp, SET, optimize_this_for_speed_p)
6538 <= rtx_cost (temp1, SET, optimize_this_for_speed_p))
6543 /* Otherwise, sign- or zero-extend unless we already are in the
6546 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6550 /* Unless this is a COMPARE or we have a funny memory reference,
6551 don't do anything with zero-extending field extracts starting at
6552 the low-order bit since they are simple AND operations. */
6553 if (pos_rtx == 0 && pos == 0 && ! in_dest
6554 && ! in_compare && unsignedp)
6557 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
6558 if the position is not a constant and the length is not 1. In all
6559 other cases, we would only be going outside our object in cases when
6560 an original shift would have been undefined. */
6562 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6563 || (pos_rtx != 0 && len != 1)))
6566 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6567 and the mode for the result. */
6568 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6570 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6571 pos_mode = mode_for_extraction (EP_insv, 2);
6572 extraction_mode = mode_for_extraction (EP_insv, 3);
6575 if (! in_dest && unsignedp
6576 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6578 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6579 pos_mode = mode_for_extraction (EP_extzv, 3);
6580 extraction_mode = mode_for_extraction (EP_extzv, 0);
6583 if (! in_dest && ! unsignedp
6584 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6586 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6587 pos_mode = mode_for_extraction (EP_extv, 3);
6588 extraction_mode = mode_for_extraction (EP_extv, 0);
6591 /* Never narrow an object, since that might not be safe. */
6593 if (mode != VOIDmode
6594 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6595 extraction_mode = mode;
6597 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6598 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6599 pos_mode = GET_MODE (pos_rtx);
6601 /* If this is not from memory, the desired mode is the preferred mode
6602 for an extraction pattern's first input operand, or word_mode if there
6605 wanted_inner_mode = wanted_inner_reg_mode;
6608 /* Be careful not to go beyond the extracted object and maintain the
6609 natural alignment of the memory. */
6610 wanted_inner_mode = smallest_mode_for_size (len, MODE_INT);
6611 while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len
6612 > GET_MODE_BITSIZE (wanted_inner_mode))
6614 wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode);
6615 gcc_assert (wanted_inner_mode != VOIDmode);
6618 /* If we have to change the mode of memory and cannot, the desired mode
6619 is EXTRACTION_MODE. */
6620 if (inner_mode != wanted_inner_mode
6621 && (mode_dependent_address_p (XEXP (inner, 0))
6622 || MEM_VOLATILE_P (inner)
6624 wanted_inner_mode = extraction_mode;
6629 if (BITS_BIG_ENDIAN)
6631 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6632 BITS_BIG_ENDIAN style. If position is constant, compute new
6633 position. Otherwise, build subtraction.
6634 Note that POS is relative to the mode of the original argument.
6635 If it's a MEM we need to recompute POS relative to that.
6636 However, if we're extracting from (or inserting into) a register,
6637 we want to recompute POS relative to wanted_inner_mode. */
6638 int width = (MEM_P (inner)
6639 ? GET_MODE_BITSIZE (is_mode)
6640 : GET_MODE_BITSIZE (wanted_inner_mode));
6643 pos = width - len - pos;
6646 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6647 /* POS may be less than 0 now, but we check for that below.
6648 Note that it can only be less than 0 if !MEM_P (inner). */
6651 /* If INNER has a wider mode, and this is a constant extraction, try to
6652 make it smaller and adjust the byte to point to the byte containing
6654 if (wanted_inner_mode != VOIDmode
6655 && inner_mode != wanted_inner_mode
6657 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6659 && ! mode_dependent_address_p (XEXP (inner, 0))
6660 && ! MEM_VOLATILE_P (inner))
6664 /* The computations below will be correct if the machine is big
6665 endian in both bits and bytes or little endian in bits and bytes.
6666 If it is mixed, we must adjust. */
6668 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6669 adjust OFFSET to compensate. */
6670 if (BYTES_BIG_ENDIAN
6671 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6672 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6674 /* We can now move to the desired byte. */
6675 offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode))
6676 * GET_MODE_SIZE (wanted_inner_mode);
6677 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6679 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6680 && is_mode != wanted_inner_mode)
6681 offset = (GET_MODE_SIZE (is_mode)
6682 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6684 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6687 /* If INNER is not memory, we can always get it into the proper mode. If we
6688 are changing its mode, POS must be a constant and smaller than the size
6690 else if (!MEM_P (inner))
6692 if (GET_MODE (inner) != wanted_inner_mode
6694 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6700 inner = force_to_mode (inner, wanted_inner_mode,
6702 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6703 ? ~(unsigned HOST_WIDE_INT) 0
6704 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6709 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6710 have to zero extend. Otherwise, we can just use a SUBREG. */
6712 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6714 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6716 /* If we know that no extraneous bits are set, and that the high
6717 bit is not set, convert extraction to cheaper one - either
6718 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6720 if (flag_expensive_optimizations
6721 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6722 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6723 & ~(((unsigned HOST_WIDE_INT)
6724 GET_MODE_MASK (GET_MODE (pos_rtx)))
6728 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6730 /* Prefer ZERO_EXTENSION, since it gives more information to
6732 if (rtx_cost (temp1, SET, optimize_this_for_speed_p)
6733 < rtx_cost (temp, SET, optimize_this_for_speed_p))
6738 else if (pos_rtx != 0
6739 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6740 pos_rtx = gen_lowpart (pos_mode, pos_rtx);
6742 /* Make POS_RTX unless we already have it and it is correct. If we don't
6743 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6745 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6746 pos_rtx = orig_pos_rtx;
6748 else if (pos_rtx == 0)
6749 pos_rtx = GEN_INT (pos);
6751 /* Make the required operation. See if we can use existing rtx. */
6752 new_rtx = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6753 extraction_mode, inner, GEN_INT (len), pos_rtx);
6755 new_rtx = gen_lowpart (mode, new_rtx);
6760 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6761 with any other operations in X. Return X without that shift if so. */
6764 extract_left_shift (rtx x, int count)
6766 enum rtx_code code = GET_CODE (x);
6767 enum machine_mode mode = GET_MODE (x);
6773 /* This is the shift itself. If it is wide enough, we will return
6774 either the value being shifted if the shift count is equal to
6775 COUNT or a shift for the difference. */
6776 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6777 && INTVAL (XEXP (x, 1)) >= count)
6778 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6779 INTVAL (XEXP (x, 1)) - count);
6783 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6784 return simplify_gen_unary (code, mode, tem, mode);
6788 case PLUS: case IOR: case XOR: case AND:
6789 /* If we can safely shift this constant and we find the inner shift,
6790 make a new operation. */
6791 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6792 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6793 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6794 return simplify_gen_binary (code, mode, tem,
6795 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6806 /* Look at the expression rooted at X. Look for expressions
6807 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6808 Form these expressions.
6810 Return the new rtx, usually just X.
6812 Also, for machines like the VAX that don't have logical shift insns,
6813 try to convert logical to arithmetic shift operations in cases where
6814 they are equivalent. This undoes the canonicalizations to logical
6815 shifts done elsewhere.
6817 We try, as much as possible, to re-use rtl expressions to save memory.
6819 IN_CODE says what kind of expression we are processing. Normally, it is
6820 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6821 being kludges), it is MEM. When processing the arguments of a comparison
6822 or a COMPARE against zero, it is COMPARE. */
6825 make_compound_operation (rtx x, enum rtx_code in_code)
6827 enum rtx_code code = GET_CODE (x);
6828 enum machine_mode mode = GET_MODE (x);
6829 int mode_width = GET_MODE_BITSIZE (mode);
6831 enum rtx_code next_code;
6837 /* Select the code to be used in recursive calls. Once we are inside an
6838 address, we stay there. If we have a comparison, set to COMPARE,
6839 but once inside, go back to our default of SET. */
6841 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6842 : ((code == COMPARE || COMPARISON_P (x))
6843 && XEXP (x, 1) == const0_rtx) ? COMPARE
6844 : in_code == COMPARE ? SET : in_code);
6846 /* Process depending on the code of this operation. If NEW is set
6847 nonzero, it will be returned. */
6852 /* Convert shifts by constants into multiplications if inside
6854 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6855 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6856 && INTVAL (XEXP (x, 1)) >= 0)
6858 new_rtx = make_compound_operation (XEXP (x, 0), next_code);
6859 new_rtx = gen_rtx_MULT (mode, new_rtx,
6860 GEN_INT ((HOST_WIDE_INT) 1
6861 << INTVAL (XEXP (x, 1))));
6866 /* If the second operand is not a constant, we can't do anything
6868 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6871 /* If the constant is a power of two minus one and the first operand
6872 is a logical right shift, make an extraction. */
6873 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6874 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6876 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6877 new_rtx = make_extraction (mode, new_rtx, 0, XEXP (XEXP (x, 0), 1), i, 1,
6878 0, in_code == COMPARE);
6881 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6882 else if (GET_CODE (XEXP (x, 0)) == SUBREG
6883 && subreg_lowpart_p (XEXP (x, 0))
6884 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6885 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6887 new_rtx = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6889 new_rtx = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new_rtx, 0,
6890 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6891 0, in_code == COMPARE);
6893 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6894 else if ((GET_CODE (XEXP (x, 0)) == XOR
6895 || GET_CODE (XEXP (x, 0)) == IOR)
6896 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6897 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6898 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6900 /* Apply the distributive law, and then try to make extractions. */
6901 new_rtx = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
6902 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6904 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6906 new_rtx = make_compound_operation (new_rtx, in_code);
6909 /* If we are have (and (rotate X C) M) and C is larger than the number
6910 of bits in M, this is an extraction. */
6912 else if (GET_CODE (XEXP (x, 0)) == ROTATE
6913 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6914 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6915 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6917 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6918 new_rtx = make_extraction (mode, new_rtx,
6919 (GET_MODE_BITSIZE (mode)
6920 - INTVAL (XEXP (XEXP (x, 0), 1))),
6921 NULL_RTX, i, 1, 0, in_code == COMPARE);
6924 /* On machines without logical shifts, if the operand of the AND is
6925 a logical shift and our mask turns off all the propagated sign
6926 bits, we can replace the logical shift with an arithmetic shift. */
6927 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6928 && !have_insn_for (LSHIFTRT, mode)
6929 && have_insn_for (ASHIFTRT, mode)
6930 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6931 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6932 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6933 && mode_width <= HOST_BITS_PER_WIDE_INT)
6935 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6937 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6938 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6940 gen_rtx_ASHIFTRT (mode,
6941 make_compound_operation
6942 (XEXP (XEXP (x, 0), 0), next_code),
6943 XEXP (XEXP (x, 0), 1)));
6946 /* If the constant is one less than a power of two, this might be
6947 representable by an extraction even if no shift is present.
6948 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6949 we are in a COMPARE. */
6950 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6951 new_rtx = make_extraction (mode,
6952 make_compound_operation (XEXP (x, 0),
6954 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6956 /* If we are in a comparison and this is an AND with a power of two,
6957 convert this into the appropriate bit extract. */
6958 else if (in_code == COMPARE
6959 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6960 new_rtx = make_extraction (mode,
6961 make_compound_operation (XEXP (x, 0),
6963 i, NULL_RTX, 1, 1, 0, 1);
6968 /* If the sign bit is known to be zero, replace this with an
6969 arithmetic shift. */
6970 if (have_insn_for (ASHIFTRT, mode)
6971 && ! have_insn_for (LSHIFTRT, mode)
6972 && mode_width <= HOST_BITS_PER_WIDE_INT
6973 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6975 new_rtx = gen_rtx_ASHIFTRT (mode,
6976 make_compound_operation (XEXP (x, 0),
6982 /* ... fall through ... */
6988 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6989 this is a SIGN_EXTRACT. */
6990 if (GET_CODE (rhs) == CONST_INT
6991 && GET_CODE (lhs) == ASHIFT
6992 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6993 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1))
6994 && INTVAL (rhs) < mode_width)
6996 new_rtx = make_compound_operation (XEXP (lhs, 0), next_code);
6997 new_rtx = make_extraction (mode, new_rtx,
6998 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6999 NULL_RTX, mode_width - INTVAL (rhs),
7000 code == LSHIFTRT, 0, in_code == COMPARE);
7004 /* See if we have operations between an ASHIFTRT and an ASHIFT.
7005 If so, try to merge the shifts into a SIGN_EXTEND. We could
7006 also do this for some cases of SIGN_EXTRACT, but it doesn't
7007 seem worth the effort; the case checked for occurs on Alpha. */
7010 && ! (GET_CODE (lhs) == SUBREG
7011 && (OBJECT_P (SUBREG_REG (lhs))))
7012 && GET_CODE (rhs) == CONST_INT
7013 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
7014 && INTVAL (rhs) < mode_width
7015 && (new_rtx = extract_left_shift (lhs, INTVAL (rhs))) != 0)
7016 new_rtx = make_extraction (mode, make_compound_operation (new_rtx, next_code),
7017 0, NULL_RTX, mode_width - INTVAL (rhs),
7018 code == LSHIFTRT, 0, in_code == COMPARE);
7023 /* Call ourselves recursively on the inner expression. If we are
7024 narrowing the object and it has a different RTL code from
7025 what it originally did, do this SUBREG as a force_to_mode. */
7027 tem = make_compound_operation (SUBREG_REG (x), in_code);
7031 simplified = simplify_subreg (GET_MODE (x), tem, GET_MODE (tem),
7037 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
7038 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
7039 && subreg_lowpart_p (x))
7041 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
7044 /* If we have something other than a SUBREG, we might have
7045 done an expansion, so rerun ourselves. */
7046 if (GET_CODE (newer) != SUBREG)
7047 newer = make_compound_operation (newer, in_code);
7063 x = gen_lowpart (mode, new_rtx);
7064 code = GET_CODE (x);
7067 /* Now recursively process each operand of this operation. */
7068 fmt = GET_RTX_FORMAT (code);
7069 for (i = 0; i < GET_RTX_LENGTH (code); i++)
7072 new_rtx = make_compound_operation (XEXP (x, i), next_code);
7073 SUBST (XEXP (x, i), new_rtx);
7075 else if (fmt[i] == 'E')
7076 for (j = 0; j < XVECLEN (x, i); j++)
7078 new_rtx = make_compound_operation (XVECEXP (x, i, j), next_code);
7079 SUBST (XVECEXP (x, i, j), new_rtx);
7082 /* If this is a commutative operation, the changes to the operands
7083 may have made it noncanonical. */
7084 if (COMMUTATIVE_ARITH_P (x)
7085 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
7088 SUBST (XEXP (x, 0), XEXP (x, 1));
7089 SUBST (XEXP (x, 1), tem);
7095 /* Given M see if it is a value that would select a field of bits
7096 within an item, but not the entire word. Return -1 if not.
7097 Otherwise, return the starting position of the field, where 0 is the
7100 *PLEN is set to the length of the field. */
7103 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
7105 /* Get the bit number of the first 1 bit from the right, -1 if none. */
7106 int pos = exact_log2 (m & -m);
7110 /* Now shift off the low-order zero bits and see if we have a
7111 power of two minus 1. */
7112 len = exact_log2 ((m >> pos) + 1);
7121 /* If X refers to a register that equals REG in value, replace these
7122 references with REG. */
7124 canon_reg_for_combine (rtx x, rtx reg)
7131 enum rtx_code code = GET_CODE (x);
7132 switch (GET_RTX_CLASS (code))
7135 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7136 if (op0 != XEXP (x, 0))
7137 return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
7142 case RTX_COMM_ARITH:
7143 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7144 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7145 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7146 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
7150 case RTX_COMM_COMPARE:
7151 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7152 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7153 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7154 return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
7155 GET_MODE (op0), op0, op1);
7159 case RTX_BITFIELD_OPS:
7160 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7161 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7162 op2 = canon_reg_for_combine (XEXP (x, 2), reg);
7163 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
7164 return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
7165 GET_MODE (op0), op0, op1, op2);
7170 if (rtx_equal_p (get_last_value (reg), x)
7171 || rtx_equal_p (reg, get_last_value (x)))
7180 fmt = GET_RTX_FORMAT (code);
7182 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7185 rtx op = canon_reg_for_combine (XEXP (x, i), reg);
7186 if (op != XEXP (x, i))
7196 else if (fmt[i] == 'E')
7199 for (j = 0; j < XVECLEN (x, i); j++)
7201 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
7202 if (op != XVECEXP (x, i, j))
7209 XVECEXP (x, i, j) = op;
7220 /* Return X converted to MODE. If the value is already truncated to
7221 MODE we can just return a subreg even though in the general case we
7222 would need an explicit truncation. */
7225 gen_lowpart_or_truncate (enum machine_mode mode, rtx x)
7227 if (GET_MODE_SIZE (GET_MODE (x)) <= GET_MODE_SIZE (mode)
7228 || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
7229 GET_MODE_BITSIZE (GET_MODE (x)))
7230 || (REG_P (x) && reg_truncated_to_mode (mode, x)))
7231 return gen_lowpart (mode, x);
7233 return simplify_gen_unary (TRUNCATE, mode, x, GET_MODE (x));
7236 /* See if X can be simplified knowing that we will only refer to it in
7237 MODE and will only refer to those bits that are nonzero in MASK.
7238 If other bits are being computed or if masking operations are done
7239 that select a superset of the bits in MASK, they can sometimes be
7242 Return a possibly simplified expression, but always convert X to
7243 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
7245 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
7246 are all off in X. This is used when X will be complemented, by either
7247 NOT, NEG, or XOR. */
7250 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
7253 enum rtx_code code = GET_CODE (x);
7254 int next_select = just_select || code == XOR || code == NOT || code == NEG;
7255 enum machine_mode op_mode;
7256 unsigned HOST_WIDE_INT fuller_mask, nonzero;
7259 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
7260 code below will do the wrong thing since the mode of such an
7261 expression is VOIDmode.
7263 Also do nothing if X is a CLOBBER; this can happen if X was
7264 the return value from a call to gen_lowpart. */
7265 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
7268 /* We want to perform the operation is its present mode unless we know
7269 that the operation is valid in MODE, in which case we do the operation
7271 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
7272 && have_insn_for (code, mode))
7273 ? mode : GET_MODE (x));
7275 /* It is not valid to do a right-shift in a narrower mode
7276 than the one it came in with. */
7277 if ((code == LSHIFTRT || code == ASHIFTRT)
7278 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
7279 op_mode = GET_MODE (x);
7281 /* Truncate MASK to fit OP_MODE. */
7283 mask &= GET_MODE_MASK (op_mode);
7285 /* When we have an arithmetic operation, or a shift whose count we
7286 do not know, we need to assume that all bits up to the highest-order
7287 bit in MASK will be needed. This is how we form such a mask. */
7288 if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
7289 fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
7291 fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
7294 /* Determine what bits of X are guaranteed to be (non)zero. */
7295 nonzero = nonzero_bits (x, mode);
7297 /* If none of the bits in X are needed, return a zero. */
7298 if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x))
7301 /* If X is a CONST_INT, return a new one. Do this here since the
7302 test below will fail. */
7303 if (GET_CODE (x) == CONST_INT)
7305 if (SCALAR_INT_MODE_P (mode))
7306 return gen_int_mode (INTVAL (x) & mask, mode);
7309 x = GEN_INT (INTVAL (x) & mask);
7310 return gen_lowpart_common (mode, x);
7314 /* If X is narrower than MODE and we want all the bits in X's mode, just
7315 get X in the proper mode. */
7316 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
7317 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
7318 return gen_lowpart (mode, x);
7320 /* The arithmetic simplifications here do the wrong thing on vector modes. */
7321 if (VECTOR_MODE_P (mode) || VECTOR_MODE_P (GET_MODE (x)))
7322 return gen_lowpart (mode, x);
7327 /* If X is a (clobber (const_int)), return it since we know we are
7328 generating something that won't match. */
7335 x = expand_compound_operation (x);
7336 if (GET_CODE (x) != code)
7337 return force_to_mode (x, mode, mask, next_select);
7341 if (subreg_lowpart_p (x)
7342 /* We can ignore the effect of this SUBREG if it narrows the mode or
7343 if the constant masks to zero all the bits the mode doesn't
7345 && ((GET_MODE_SIZE (GET_MODE (x))
7346 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7348 & GET_MODE_MASK (GET_MODE (x))
7349 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
7350 return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
7354 /* If this is an AND with a constant, convert it into an AND
7355 whose constant is the AND of that constant with MASK. If it
7356 remains an AND of MASK, delete it since it is redundant. */
7358 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
7360 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
7361 mask & INTVAL (XEXP (x, 1)));
7363 /* If X is still an AND, see if it is an AND with a mask that
7364 is just some low-order bits. If so, and it is MASK, we don't
7367 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
7368 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
7372 /* If it remains an AND, try making another AND with the bits
7373 in the mode mask that aren't in MASK turned on. If the
7374 constant in the AND is wide enough, this might make a
7375 cheaper constant. */
7377 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
7378 && GET_MODE_MASK (GET_MODE (x)) != mask
7379 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
7381 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
7382 | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
7383 int width = GET_MODE_BITSIZE (GET_MODE (x));
7386 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
7387 number, sign extend it. */
7388 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
7389 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7390 cval |= (HOST_WIDE_INT) -1 << width;
7392 y = simplify_gen_binary (AND, GET_MODE (x),
7393 XEXP (x, 0), GEN_INT (cval));
7394 if (rtx_cost (y, SET, optimize_this_for_speed_p)
7395 < rtx_cost (x, SET, optimize_this_for_speed_p))
7405 /* In (and (plus FOO C1) M), if M is a mask that just turns off
7406 low-order bits (as in an alignment operation) and FOO is already
7407 aligned to that boundary, mask C1 to that boundary as well.
7408 This may eliminate that PLUS and, later, the AND. */
7411 unsigned int width = GET_MODE_BITSIZE (mode);
7412 unsigned HOST_WIDE_INT smask = mask;
7414 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
7415 number, sign extend it. */
7417 if (width < HOST_BITS_PER_WIDE_INT
7418 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7419 smask |= (HOST_WIDE_INT) -1 << width;
7421 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7422 && exact_log2 (- smask) >= 0
7423 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
7424 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
7425 return force_to_mode (plus_constant (XEXP (x, 0),
7426 (INTVAL (XEXP (x, 1)) & smask)),
7427 mode, smask, next_select);
7430 /* ... fall through ... */
7433 /* For PLUS, MINUS and MULT, we need any bits less significant than the
7434 most significant bit in MASK since carries from those bits will
7435 affect the bits we are interested in. */
7440 /* If X is (minus C Y) where C's least set bit is larger than any bit
7441 in the mask, then we may replace with (neg Y). */
7442 if (GET_CODE (XEXP (x, 0)) == CONST_INT
7443 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
7444 & -INTVAL (XEXP (x, 0))))
7447 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
7449 return force_to_mode (x, mode, mask, next_select);
7452 /* Similarly, if C contains every bit in the fuller_mask, then we may
7453 replace with (not Y). */
7454 if (GET_CODE (XEXP (x, 0)) == CONST_INT
7455 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask)
7456 == INTVAL (XEXP (x, 0))))
7458 x = simplify_gen_unary (NOT, GET_MODE (x),
7459 XEXP (x, 1), GET_MODE (x));
7460 return force_to_mode (x, mode, mask, next_select);
7468 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7469 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7470 operation which may be a bitfield extraction. Ensure that the
7471 constant we form is not wider than the mode of X. */
7473 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7474 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7475 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7476 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7477 && GET_CODE (XEXP (x, 1)) == CONST_INT
7478 && ((INTVAL (XEXP (XEXP (x, 0), 1))
7479 + floor_log2 (INTVAL (XEXP (x, 1))))
7480 < GET_MODE_BITSIZE (GET_MODE (x)))
7481 && (INTVAL (XEXP (x, 1))
7482 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
7484 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
7485 << INTVAL (XEXP (XEXP (x, 0), 1)));
7486 temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
7487 XEXP (XEXP (x, 0), 0), temp);
7488 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
7489 XEXP (XEXP (x, 0), 1));
7490 return force_to_mode (x, mode, mask, next_select);
7494 /* For most binary operations, just propagate into the operation and
7495 change the mode if we have an operation of that mode. */
7497 op0 = gen_lowpart_or_truncate (op_mode,
7498 force_to_mode (XEXP (x, 0), mode, mask,
7500 op1 = gen_lowpart_or_truncate (op_mode,
7501 force_to_mode (XEXP (x, 1), mode, mask,
7504 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7505 x = simplify_gen_binary (code, op_mode, op0, op1);
7509 /* For left shifts, do the same, but just for the first operand.
7510 However, we cannot do anything with shifts where we cannot
7511 guarantee that the counts are smaller than the size of the mode
7512 because such a count will have a different meaning in a
7515 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
7516 && INTVAL (XEXP (x, 1)) >= 0
7517 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
7518 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
7519 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
7520 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
7523 /* If the shift count is a constant and we can do arithmetic in
7524 the mode of the shift, refine which bits we need. Otherwise, use the
7525 conservative form of the mask. */
7526 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7527 && INTVAL (XEXP (x, 1)) >= 0
7528 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
7529 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7530 mask >>= INTVAL (XEXP (x, 1));
7534 op0 = gen_lowpart_or_truncate (op_mode,
7535 force_to_mode (XEXP (x, 0), op_mode,
7536 mask, next_select));
7538 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7539 x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
7543 /* Here we can only do something if the shift count is a constant,
7544 this shift constant is valid for the host, and we can do arithmetic
7547 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7548 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7549 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7551 rtx inner = XEXP (x, 0);
7552 unsigned HOST_WIDE_INT inner_mask;
7554 /* Select the mask of the bits we need for the shift operand. */
7555 inner_mask = mask << INTVAL (XEXP (x, 1));
7557 /* We can only change the mode of the shift if we can do arithmetic
7558 in the mode of the shift and INNER_MASK is no wider than the
7559 width of X's mode. */
7560 if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
7561 op_mode = GET_MODE (x);
7563 inner = force_to_mode (inner, op_mode, inner_mask, next_select);
7565 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
7566 x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
7569 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7570 shift and AND produces only copies of the sign bit (C2 is one less
7571 than a power of two), we can do this with just a shift. */
7573 if (GET_CODE (x) == LSHIFTRT
7574 && GET_CODE (XEXP (x, 1)) == CONST_INT
7575 /* The shift puts one of the sign bit copies in the least significant
7577 && ((INTVAL (XEXP (x, 1))
7578 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7579 >= GET_MODE_BITSIZE (GET_MODE (x)))
7580 && exact_log2 (mask + 1) >= 0
7581 /* Number of bits left after the shift must be more than the mask
7583 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7584 <= GET_MODE_BITSIZE (GET_MODE (x)))
7585 /* Must be more sign bit copies than the mask needs. */
7586 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7587 >= exact_log2 (mask + 1)))
7588 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7589 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7590 - exact_log2 (mask + 1)));
7595 /* If we are just looking for the sign bit, we don't need this shift at
7596 all, even if it has a variable count. */
7597 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7598 && (mask == ((unsigned HOST_WIDE_INT) 1
7599 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7600 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7602 /* If this is a shift by a constant, get a mask that contains those bits
7603 that are not copies of the sign bit. We then have two cases: If
7604 MASK only includes those bits, this can be a logical shift, which may
7605 allow simplifications. If MASK is a single-bit field not within
7606 those bits, we are requesting a copy of the sign bit and hence can
7607 shift the sign bit to the appropriate location. */
7609 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
7610 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7614 /* If the considered data is wider than HOST_WIDE_INT, we can't
7615 represent a mask for all its bits in a single scalar.
7616 But we only care about the lower bits, so calculate these. */
7618 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7620 nonzero = ~(HOST_WIDE_INT) 0;
7622 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7623 is the number of bits a full-width mask would have set.
7624 We need only shift if these are fewer than nonzero can
7625 hold. If not, we must keep all bits set in nonzero. */
7627 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7628 < HOST_BITS_PER_WIDE_INT)
7629 nonzero >>= INTVAL (XEXP (x, 1))
7630 + HOST_BITS_PER_WIDE_INT
7631 - GET_MODE_BITSIZE (GET_MODE (x)) ;
7635 nonzero = GET_MODE_MASK (GET_MODE (x));
7636 nonzero >>= INTVAL (XEXP (x, 1));
7639 if ((mask & ~nonzero) == 0)
7641 x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x),
7642 XEXP (x, 0), INTVAL (XEXP (x, 1)));
7643 if (GET_CODE (x) != ASHIFTRT)
7644 return force_to_mode (x, mode, mask, next_select);
7647 else if ((i = exact_log2 (mask)) >= 0)
7649 x = simplify_shift_const
7650 (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7651 GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7653 if (GET_CODE (x) != ASHIFTRT)
7654 return force_to_mode (x, mode, mask, next_select);
7658 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7659 even if the shift count isn't a constant. */
7661 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7662 XEXP (x, 0), XEXP (x, 1));
7666 /* If this is a zero- or sign-extension operation that just affects bits
7667 we don't care about, remove it. Be sure the call above returned
7668 something that is still a shift. */
7670 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7671 && GET_CODE (XEXP (x, 1)) == CONST_INT
7672 && INTVAL (XEXP (x, 1)) >= 0
7673 && (INTVAL (XEXP (x, 1))
7674 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7675 && GET_CODE (XEXP (x, 0)) == ASHIFT
7676 && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
7677 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7684 /* If the shift count is constant and we can do computations
7685 in the mode of X, compute where the bits we care about are.
7686 Otherwise, we can't do anything. Don't change the mode of
7687 the shift or propagate MODE into the shift, though. */
7688 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7689 && INTVAL (XEXP (x, 1)) >= 0)
7691 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7692 GET_MODE (x), GEN_INT (mask),
7694 if (temp && GET_CODE (temp) == CONST_INT)
7696 force_to_mode (XEXP (x, 0), GET_MODE (x),
7697 INTVAL (temp), next_select));
7702 /* If we just want the low-order bit, the NEG isn't needed since it
7703 won't change the low-order bit. */
7705 return force_to_mode (XEXP (x, 0), mode, mask, just_select);
7707 /* We need any bits less significant than the most significant bit in
7708 MASK since carries from those bits will affect the bits we are
7714 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7715 same as the XOR case above. Ensure that the constant we form is not
7716 wider than the mode of X. */
7718 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7719 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7720 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7721 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7722 < GET_MODE_BITSIZE (GET_MODE (x)))
7723 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7725 temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
7727 temp = simplify_gen_binary (XOR, GET_MODE (x),
7728 XEXP (XEXP (x, 0), 0), temp);
7729 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7730 temp, XEXP (XEXP (x, 0), 1));
7732 return force_to_mode (x, mode, mask, next_select);
7735 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7736 use the full mask inside the NOT. */
7740 op0 = gen_lowpart_or_truncate (op_mode,
7741 force_to_mode (XEXP (x, 0), mode, mask,
7743 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7744 x = simplify_gen_unary (code, op_mode, op0, op_mode);
7748 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7749 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7750 which is equal to STORE_FLAG_VALUE. */
7751 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7752 && GET_MODE (XEXP (x, 0)) == mode
7753 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7754 && (nonzero_bits (XEXP (x, 0), mode)
7755 == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
7756 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7761 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7762 written in a narrower mode. We play it safe and do not do so. */
7765 gen_lowpart_or_truncate (GET_MODE (x),
7766 force_to_mode (XEXP (x, 1), mode,
7767 mask, next_select)));
7769 gen_lowpart_or_truncate (GET_MODE (x),
7770 force_to_mode (XEXP (x, 2), mode,
7771 mask, next_select)));
7778 /* Ensure we return a value of the proper mode. */
7779 return gen_lowpart_or_truncate (mode, x);
7782 /* Return nonzero if X is an expression that has one of two values depending on
7783 whether some other value is zero or nonzero. In that case, we return the
7784 value that is being tested, *PTRUE is set to the value if the rtx being
7785 returned has a nonzero value, and *PFALSE is set to the other alternative.
7787 If we return zero, we set *PTRUE and *PFALSE to X. */
7790 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
7792 enum machine_mode mode = GET_MODE (x);
7793 enum rtx_code code = GET_CODE (x);
7794 rtx cond0, cond1, true0, true1, false0, false1;
7795 unsigned HOST_WIDE_INT nz;
7797 /* If we are comparing a value against zero, we are done. */
7798 if ((code == NE || code == EQ)
7799 && XEXP (x, 1) == const0_rtx)
7801 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7802 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7806 /* If this is a unary operation whose operand has one of two values, apply
7807 our opcode to compute those values. */
7808 else if (UNARY_P (x)
7809 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7811 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
7812 *pfalse = simplify_gen_unary (code, mode, false0,
7813 GET_MODE (XEXP (x, 0)));
7817 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7818 make can't possibly match and would suppress other optimizations. */
7819 else if (code == COMPARE)
7822 /* If this is a binary operation, see if either side has only one of two
7823 values. If either one does or if both do and they are conditional on
7824 the same value, compute the new true and false values. */
7825 else if (BINARY_P (x))
7827 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7828 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7830 if ((cond0 != 0 || cond1 != 0)
7831 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7833 /* If if_then_else_cond returned zero, then true/false are the
7834 same rtl. We must copy one of them to prevent invalid rtl
7837 true0 = copy_rtx (true0);
7838 else if (cond1 == 0)
7839 true1 = copy_rtx (true1);
7841 if (COMPARISON_P (x))
7843 *ptrue = simplify_gen_relational (code, mode, VOIDmode,
7845 *pfalse = simplify_gen_relational (code, mode, VOIDmode,
7850 *ptrue = simplify_gen_binary (code, mode, true0, true1);
7851 *pfalse = simplify_gen_binary (code, mode, false0, false1);
7854 return cond0 ? cond0 : cond1;
7857 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7858 operands is zero when the other is nonzero, and vice-versa,
7859 and STORE_FLAG_VALUE is 1 or -1. */
7861 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7862 && (code == PLUS || code == IOR || code == XOR || code == MINUS
7864 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7866 rtx op0 = XEXP (XEXP (x, 0), 1);
7867 rtx op1 = XEXP (XEXP (x, 1), 1);
7869 cond0 = XEXP (XEXP (x, 0), 0);
7870 cond1 = XEXP (XEXP (x, 1), 0);
7872 if (COMPARISON_P (cond0)
7873 && COMPARISON_P (cond1)
7874 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
7875 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7876 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7877 || ((swap_condition (GET_CODE (cond0))
7878 == reversed_comparison_code (cond1, NULL))
7879 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7880 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7881 && ! side_effects_p (x))
7883 *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
7884 *pfalse = simplify_gen_binary (MULT, mode,
7886 ? simplify_gen_unary (NEG, mode,
7894 /* Similarly for MULT, AND and UMIN, except that for these the result
7896 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7897 && (code == MULT || code == AND || code == UMIN)
7898 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7900 cond0 = XEXP (XEXP (x, 0), 0);
7901 cond1 = XEXP (XEXP (x, 1), 0);
7903 if (COMPARISON_P (cond0)
7904 && COMPARISON_P (cond1)
7905 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
7906 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7907 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7908 || ((swap_condition (GET_CODE (cond0))
7909 == reversed_comparison_code (cond1, NULL))
7910 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7911 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7912 && ! side_effects_p (x))
7914 *ptrue = *pfalse = const0_rtx;
7920 else if (code == IF_THEN_ELSE)
7922 /* If we have IF_THEN_ELSE already, extract the condition and
7923 canonicalize it if it is NE or EQ. */
7924 cond0 = XEXP (x, 0);
7925 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7926 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7927 return XEXP (cond0, 0);
7928 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7930 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7931 return XEXP (cond0, 0);
7937 /* If X is a SUBREG, we can narrow both the true and false values
7938 if the inner expression, if there is a condition. */
7939 else if (code == SUBREG
7940 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7943 true0 = simplify_gen_subreg (mode, true0,
7944 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7945 false0 = simplify_gen_subreg (mode, false0,
7946 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7947 if (true0 && false0)
7955 /* If X is a constant, this isn't special and will cause confusions
7956 if we treat it as such. Likewise if it is equivalent to a constant. */
7957 else if (CONSTANT_P (x)
7958 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7961 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7962 will be least confusing to the rest of the compiler. */
7963 else if (mode == BImode)
7965 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
7969 /* If X is known to be either 0 or -1, those are the true and
7970 false values when testing X. */
7971 else if (x == constm1_rtx || x == const0_rtx
7972 || (mode != VOIDmode
7973 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
7975 *ptrue = constm1_rtx, *pfalse = const0_rtx;
7979 /* Likewise for 0 or a single bit. */
7980 else if (SCALAR_INT_MODE_P (mode)
7981 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7982 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7984 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
7988 /* Otherwise fail; show no condition with true and false values the same. */
7989 *ptrue = *pfalse = x;
7993 /* Return the value of expression X given the fact that condition COND
7994 is known to be true when applied to REG as its first operand and VAL
7995 as its second. X is known to not be shared and so can be modified in
7998 We only handle the simplest cases, and specifically those cases that
7999 arise with IF_THEN_ELSE expressions. */
8002 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
8004 enum rtx_code code = GET_CODE (x);
8009 if (side_effects_p (x))
8012 /* If either operand of the condition is a floating point value,
8013 then we have to avoid collapsing an EQ comparison. */
8015 && rtx_equal_p (x, reg)
8016 && ! FLOAT_MODE_P (GET_MODE (x))
8017 && ! FLOAT_MODE_P (GET_MODE (val)))
8020 if (cond == UNEQ && rtx_equal_p (x, reg))
8023 /* If X is (abs REG) and we know something about REG's relationship
8024 with zero, we may be able to simplify this. */
8026 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
8029 case GE: case GT: case EQ:
8032 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
8034 GET_MODE (XEXP (x, 0)));
8039 /* The only other cases we handle are MIN, MAX, and comparisons if the
8040 operands are the same as REG and VAL. */
8042 else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
8044 if (rtx_equal_p (XEXP (x, 0), val))
8045 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
8047 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
8049 if (COMPARISON_P (x))
8051 if (comparison_dominates_p (cond, code))
8052 return const_true_rtx;
8054 code = reversed_comparison_code (x, NULL);
8056 && comparison_dominates_p (cond, code))
8061 else if (code == SMAX || code == SMIN
8062 || code == UMIN || code == UMAX)
8064 int unsignedp = (code == UMIN || code == UMAX);
8066 /* Do not reverse the condition when it is NE or EQ.
8067 This is because we cannot conclude anything about
8068 the value of 'SMAX (x, y)' when x is not equal to y,
8069 but we can when x equals y. */
8070 if ((code == SMAX || code == UMAX)
8071 && ! (cond == EQ || cond == NE))
8072 cond = reverse_condition (cond);
8077 return unsignedp ? x : XEXP (x, 1);
8079 return unsignedp ? x : XEXP (x, 0);
8081 return unsignedp ? XEXP (x, 1) : x;
8083 return unsignedp ? XEXP (x, 0) : x;
8090 else if (code == SUBREG)
8092 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
8093 rtx new_rtx, r = known_cond (SUBREG_REG (x), cond, reg, val);
8095 if (SUBREG_REG (x) != r)
8097 /* We must simplify subreg here, before we lose track of the
8098 original inner_mode. */
8099 new_rtx = simplify_subreg (GET_MODE (x), r,
8100 inner_mode, SUBREG_BYTE (x));
8104 SUBST (SUBREG_REG (x), r);
8109 /* We don't have to handle SIGN_EXTEND here, because even in the
8110 case of replacing something with a modeless CONST_INT, a
8111 CONST_INT is already (supposed to be) a valid sign extension for
8112 its narrower mode, which implies it's already properly
8113 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
8114 story is different. */
8115 else if (code == ZERO_EXTEND)
8117 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
8118 rtx new_rtx, r = known_cond (XEXP (x, 0), cond, reg, val);
8120 if (XEXP (x, 0) != r)
8122 /* We must simplify the zero_extend here, before we lose
8123 track of the original inner_mode. */
8124 new_rtx = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
8129 SUBST (XEXP (x, 0), r);
8135 fmt = GET_RTX_FORMAT (code);
8136 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8139 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
8140 else if (fmt[i] == 'E')
8141 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8142 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
8149 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
8150 assignment as a field assignment. */
8153 rtx_equal_for_field_assignment_p (rtx x, rtx y)
8155 if (x == y || rtx_equal_p (x, y))
8158 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
8161 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
8162 Note that all SUBREGs of MEM are paradoxical; otherwise they
8163 would have been rewritten. */
8164 if (MEM_P (x) && GET_CODE (y) == SUBREG
8165 && MEM_P (SUBREG_REG (y))
8166 && rtx_equal_p (SUBREG_REG (y),
8167 gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
8170 if (MEM_P (y) && GET_CODE (x) == SUBREG
8171 && MEM_P (SUBREG_REG (x))
8172 && rtx_equal_p (SUBREG_REG (x),
8173 gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
8176 /* We used to see if get_last_value of X and Y were the same but that's
8177 not correct. In one direction, we'll cause the assignment to have
8178 the wrong destination and in the case, we'll import a register into this
8179 insn that might have already have been dead. So fail if none of the
8180 above cases are true. */
8184 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
8185 Return that assignment if so.
8187 We only handle the most common cases. */
8190 make_field_assignment (rtx x)
8192 rtx dest = SET_DEST (x);
8193 rtx src = SET_SRC (x);
8198 unsigned HOST_WIDE_INT len;
8200 enum machine_mode mode;
8202 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
8203 a clear of a one-bit field. We will have changed it to
8204 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
8207 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
8208 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
8209 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
8210 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8212 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8215 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8219 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
8220 && subreg_lowpart_p (XEXP (src, 0))
8221 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
8222 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
8223 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
8224 && GET_CODE (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == CONST_INT
8225 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
8226 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8228 assign = make_extraction (VOIDmode, dest, 0,
8229 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
8232 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8236 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
8238 if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
8239 && XEXP (XEXP (src, 0), 0) == const1_rtx
8240 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8242 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8245 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
8249 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
8250 SRC is an AND with all bits of that field set, then we can discard
8252 if (GET_CODE (dest) == ZERO_EXTRACT
8253 && GET_CODE (XEXP (dest, 1)) == CONST_INT
8254 && GET_CODE (src) == AND
8255 && GET_CODE (XEXP (src, 1)) == CONST_INT)
8257 HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
8258 unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
8259 unsigned HOST_WIDE_INT ze_mask;
8261 if (width >= HOST_BITS_PER_WIDE_INT)
8264 ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
8266 /* Complete overlap. We can remove the source AND. */
8267 if ((and_mask & ze_mask) == ze_mask)
8268 return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
8270 /* Partial overlap. We can reduce the source AND. */
8271 if ((and_mask & ze_mask) != and_mask)
8273 mode = GET_MODE (src);
8274 src = gen_rtx_AND (mode, XEXP (src, 0),
8275 gen_int_mode (and_mask & ze_mask, mode));
8276 return gen_rtx_SET (VOIDmode, dest, src);
8280 /* The other case we handle is assignments into a constant-position
8281 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
8282 a mask that has all one bits except for a group of zero bits and
8283 OTHER is known to have zeros where C1 has ones, this is such an
8284 assignment. Compute the position and length from C1. Shift OTHER
8285 to the appropriate position, force it to the required mode, and
8286 make the extraction. Check for the AND in both operands. */
8288 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
8291 rhs = expand_compound_operation (XEXP (src, 0));
8292 lhs = expand_compound_operation (XEXP (src, 1));
8294 if (GET_CODE (rhs) == AND
8295 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
8296 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
8297 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
8298 else if (GET_CODE (lhs) == AND
8299 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
8300 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
8301 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
8305 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
8306 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
8307 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
8308 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
8311 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
8315 /* The mode to use for the source is the mode of the assignment, or of
8316 what is inside a possible STRICT_LOW_PART. */
8317 mode = (GET_CODE (assign) == STRICT_LOW_PART
8318 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
8320 /* Shift OTHER right POS places and make it the source, restricting it
8321 to the proper length and mode. */
8323 src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
8327 src = force_to_mode (src, mode,
8328 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
8329 ? ~(unsigned HOST_WIDE_INT) 0
8330 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
8333 /* If SRC is masked by an AND that does not make a difference in
8334 the value being stored, strip it. */
8335 if (GET_CODE (assign) == ZERO_EXTRACT
8336 && GET_CODE (XEXP (assign, 1)) == CONST_INT
8337 && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
8338 && GET_CODE (src) == AND
8339 && GET_CODE (XEXP (src, 1)) == CONST_INT
8340 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (src, 1))
8341 == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1))
8342 src = XEXP (src, 0);
8344 return gen_rtx_SET (VOIDmode, assign, src);
8347 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
8351 apply_distributive_law (rtx x)
8353 enum rtx_code code = GET_CODE (x);
8354 enum rtx_code inner_code;
8355 rtx lhs, rhs, other;
8358 /* Distributivity is not true for floating point as it can change the
8359 value. So we don't do it unless -funsafe-math-optimizations. */
8360 if (FLOAT_MODE_P (GET_MODE (x))
8361 && ! flag_unsafe_math_optimizations)
8364 /* The outer operation can only be one of the following: */
8365 if (code != IOR && code != AND && code != XOR
8366 && code != PLUS && code != MINUS)
8372 /* If either operand is a primitive we can't do anything, so get out
8374 if (OBJECT_P (lhs) || OBJECT_P (rhs))
8377 lhs = expand_compound_operation (lhs);
8378 rhs = expand_compound_operation (rhs);
8379 inner_code = GET_CODE (lhs);
8380 if (inner_code != GET_CODE (rhs))
8383 /* See if the inner and outer operations distribute. */
8390 /* These all distribute except over PLUS. */
8391 if (code == PLUS || code == MINUS)
8396 if (code != PLUS && code != MINUS)
8401 /* This is also a multiply, so it distributes over everything. */
8405 /* Non-paradoxical SUBREGs distributes over all operations,
8406 provided the inner modes and byte offsets are the same, this
8407 is an extraction of a low-order part, we don't convert an fp
8408 operation to int or vice versa, this is not a vector mode,
8409 and we would not be converting a single-word operation into a
8410 multi-word operation. The latter test is not required, but
8411 it prevents generating unneeded multi-word operations. Some
8412 of the previous tests are redundant given the latter test,
8413 but are retained because they are required for correctness.
8415 We produce the result slightly differently in this case. */
8417 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
8418 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
8419 || ! subreg_lowpart_p (lhs)
8420 || (GET_MODE_CLASS (GET_MODE (lhs))
8421 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
8422 || (GET_MODE_SIZE (GET_MODE (lhs))
8423 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
8424 || VECTOR_MODE_P (GET_MODE (lhs))
8425 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD
8426 /* Result might need to be truncated. Don't change mode if
8427 explicit truncation is needed. */
8428 || !TRULY_NOOP_TRUNCATION
8429 (GET_MODE_BITSIZE (GET_MODE (x)),
8430 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (lhs)))))
8433 tem = simplify_gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
8434 SUBREG_REG (lhs), SUBREG_REG (rhs));
8435 return gen_lowpart (GET_MODE (x), tem);
8441 /* Set LHS and RHS to the inner operands (A and B in the example
8442 above) and set OTHER to the common operand (C in the example).
8443 There is only one way to do this unless the inner operation is
8445 if (COMMUTATIVE_ARITH_P (lhs)
8446 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
8447 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
8448 else if (COMMUTATIVE_ARITH_P (lhs)
8449 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
8450 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
8451 else if (COMMUTATIVE_ARITH_P (lhs)
8452 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
8453 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
8454 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
8455 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
8459 /* Form the new inner operation, seeing if it simplifies first. */
8460 tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
8462 /* There is one exception to the general way of distributing:
8463 (a | c) ^ (b | c) -> (a ^ b) & ~c */
8464 if (code == XOR && inner_code == IOR)
8467 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
8470 /* We may be able to continuing distributing the result, so call
8471 ourselves recursively on the inner operation before forming the
8472 outer operation, which we return. */
8473 return simplify_gen_binary (inner_code, GET_MODE (x),
8474 apply_distributive_law (tem), other);
8477 /* See if X is of the form (* (+ A B) C), and if so convert to
8478 (+ (* A C) (* B C)) and try to simplify.
8480 Most of the time, this results in no change. However, if some of
8481 the operands are the same or inverses of each other, simplifications
8484 For example, (and (ior A B) (not B)) can occur as the result of
8485 expanding a bit field assignment. When we apply the distributive
8486 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
8487 which then simplifies to (and (A (not B))).
8489 Note that no checks happen on the validity of applying the inverse
8490 distributive law. This is pointless since we can do it in the
8491 few places where this routine is called.
8493 N is the index of the term that is decomposed (the arithmetic operation,
8494 i.e. (+ A B) in the first example above). !N is the index of the term that
8495 is distributed, i.e. of C in the first example above. */
8497 distribute_and_simplify_rtx (rtx x, int n)
8499 enum machine_mode mode;
8500 enum rtx_code outer_code, inner_code;
8501 rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
8503 decomposed = XEXP (x, n);
8504 if (!ARITHMETIC_P (decomposed))
8507 mode = GET_MODE (x);
8508 outer_code = GET_CODE (x);
8509 distributed = XEXP (x, !n);
8511 inner_code = GET_CODE (decomposed);
8512 inner_op0 = XEXP (decomposed, 0);
8513 inner_op1 = XEXP (decomposed, 1);
8515 /* Special case (and (xor B C) (not A)), which is equivalent to
8516 (xor (ior A B) (ior A C)) */
8517 if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
8519 distributed = XEXP (distributed, 0);
8525 /* Distribute the second term. */
8526 new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
8527 new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
8531 /* Distribute the first term. */
8532 new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
8533 new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
8536 tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
8538 if (GET_CODE (tmp) != outer_code
8539 && rtx_cost (tmp, SET, optimize_this_for_speed_p)
8540 < rtx_cost (x, SET, optimize_this_for_speed_p))
8546 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
8547 in MODE. Return an equivalent form, if different from (and VAROP
8548 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
8551 simplify_and_const_int_1 (enum machine_mode mode, rtx varop,
8552 unsigned HOST_WIDE_INT constop)
8554 unsigned HOST_WIDE_INT nonzero;
8555 unsigned HOST_WIDE_INT orig_constop;
8560 orig_constop = constop;
8561 if (GET_CODE (varop) == CLOBBER)
8564 /* Simplify VAROP knowing that we will be only looking at some of the
8567 Note by passing in CONSTOP, we guarantee that the bits not set in
8568 CONSTOP are not significant and will never be examined. We must
8569 ensure that is the case by explicitly masking out those bits
8570 before returning. */
8571 varop = force_to_mode (varop, mode, constop, 0);
8573 /* If VAROP is a CLOBBER, we will fail so return it. */
8574 if (GET_CODE (varop) == CLOBBER)
8577 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
8578 to VAROP and return the new constant. */
8579 if (GET_CODE (varop) == CONST_INT)
8580 return gen_int_mode (INTVAL (varop) & constop, mode);
8582 /* See what bits may be nonzero in VAROP. Unlike the general case of
8583 a call to nonzero_bits, here we don't care about bits outside
8586 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
8588 /* Turn off all bits in the constant that are known to already be zero.
8589 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8590 which is tested below. */
8594 /* If we don't have any bits left, return zero. */
8598 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8599 a power of two, we can replace this with an ASHIFT. */
8600 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
8601 && (i = exact_log2 (constop)) >= 0)
8602 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
8604 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8605 or XOR, then try to apply the distributive law. This may eliminate
8606 operations if either branch can be simplified because of the AND.
8607 It may also make some cases more complex, but those cases probably
8608 won't match a pattern either with or without this. */
8610 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
8614 apply_distributive_law
8615 (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
8616 simplify_and_const_int (NULL_RTX,
8620 simplify_and_const_int (NULL_RTX,
8625 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
8626 the AND and see if one of the operands simplifies to zero. If so, we
8627 may eliminate it. */
8629 if (GET_CODE (varop) == PLUS
8630 && exact_log2 (constop + 1) >= 0)
8634 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
8635 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
8636 if (o0 == const0_rtx)
8638 if (o1 == const0_rtx)
8642 /* Make a SUBREG if necessary. If we can't make it, fail. */
8643 varop = gen_lowpart (mode, varop);
8644 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
8647 /* If we are only masking insignificant bits, return VAROP. */
8648 if (constop == nonzero)
8651 if (varop == orig_varop && constop == orig_constop)
8654 /* Otherwise, return an AND. */
8655 return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode));
8659 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
8662 Return an equivalent form, if different from X. Otherwise, return X. If
8663 X is zero, we are to always construct the equivalent form. */
8666 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
8667 unsigned HOST_WIDE_INT constop)
8669 rtx tem = simplify_and_const_int_1 (mode, varop, constop);
8674 x = simplify_gen_binary (AND, GET_MODE (varop), varop,
8675 gen_int_mode (constop, mode));
8676 if (GET_MODE (x) != mode)
8677 x = gen_lowpart (mode, x);
8681 /* Given a REG, X, compute which bits in X can be nonzero.
8682 We don't care about bits outside of those defined in MODE.
8684 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8685 a shift, AND, or zero_extract, we can do better. */
8688 reg_nonzero_bits_for_combine (const_rtx x, enum machine_mode mode,
8689 const_rtx known_x ATTRIBUTE_UNUSED,
8690 enum machine_mode known_mode ATTRIBUTE_UNUSED,
8691 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
8692 unsigned HOST_WIDE_INT *nonzero)
8697 /* If X is a register whose nonzero bits value is current, use it.
8698 Otherwise, if X is a register whose value we can find, use that
8699 value. Otherwise, use the previously-computed global nonzero bits
8700 for this register. */
8702 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
8703 if (rsp->last_set_value != 0
8704 && (rsp->last_set_mode == mode
8705 || (GET_MODE_CLASS (rsp->last_set_mode) == MODE_INT
8706 && GET_MODE_CLASS (mode) == MODE_INT))
8707 && ((rsp->last_set_label >= label_tick_ebb_start
8708 && rsp->last_set_label < label_tick)
8709 || (rsp->last_set_label == label_tick
8710 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
8711 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8712 && REG_N_SETS (REGNO (x)) == 1
8714 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
8716 *nonzero &= rsp->last_set_nonzero_bits;
8720 tem = get_last_value (x);
8724 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8725 /* If X is narrower than MODE and TEM is a non-negative
8726 constant that would appear negative in the mode of X,
8727 sign-extend it for use in reg_nonzero_bits because some
8728 machines (maybe most) will actually do the sign-extension
8729 and this is the conservative approach.
8731 ??? For 2.5, try to tighten up the MD files in this regard
8732 instead of this kludge. */
8734 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode)
8735 && GET_CODE (tem) == CONST_INT
8737 && 0 != (INTVAL (tem)
8738 & ((HOST_WIDE_INT) 1
8739 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8740 tem = GEN_INT (INTVAL (tem)
8741 | ((HOST_WIDE_INT) (-1)
8742 << GET_MODE_BITSIZE (GET_MODE (x))));
8746 else if (nonzero_sign_valid && rsp->nonzero_bits)
8748 unsigned HOST_WIDE_INT mask = rsp->nonzero_bits;
8750 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode))
8751 /* We don't know anything about the upper bits. */
8752 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
8759 /* Return the number of bits at the high-order end of X that are known to
8760 be equal to the sign bit. X will be used in mode MODE; if MODE is
8761 VOIDmode, X will be used in its own mode. The returned value will always
8762 be between 1 and the number of bits in MODE. */
8765 reg_num_sign_bit_copies_for_combine (const_rtx x, enum machine_mode mode,
8766 const_rtx known_x ATTRIBUTE_UNUSED,
8767 enum machine_mode known_mode
8769 unsigned int known_ret ATTRIBUTE_UNUSED,
8770 unsigned int *result)
8775 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
8776 if (rsp->last_set_value != 0
8777 && rsp->last_set_mode == mode
8778 && ((rsp->last_set_label >= label_tick_ebb_start
8779 && rsp->last_set_label < label_tick)
8780 || (rsp->last_set_label == label_tick
8781 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
8782 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8783 && REG_N_SETS (REGNO (x)) == 1
8785 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
8787 *result = rsp->last_set_sign_bit_copies;
8791 tem = get_last_value (x);
8795 if (nonzero_sign_valid && rsp->sign_bit_copies != 0
8796 && GET_MODE_BITSIZE (GET_MODE (x)) == GET_MODE_BITSIZE (mode))
8797 *result = rsp->sign_bit_copies;
8802 /* Return the number of "extended" bits there are in X, when interpreted
8803 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8804 unsigned quantities, this is the number of high-order zero bits.
8805 For signed quantities, this is the number of copies of the sign bit
8806 minus 1. In both case, this function returns the number of "spare"
8807 bits. For example, if two quantities for which this function returns
8808 at least 1 are added, the addition is known not to overflow.
8810 This function will always return 0 unless called during combine, which
8811 implies that it must be called from a define_split. */
8814 extended_count (const_rtx x, enum machine_mode mode, int unsignedp)
8816 if (nonzero_sign_valid == 0)
8820 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8821 ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
8822 - floor_log2 (nonzero_bits (x, mode)))
8824 : num_sign_bit_copies (x, mode) - 1);
8827 /* This function is called from `simplify_shift_const' to merge two
8828 outer operations. Specifically, we have already found that we need
8829 to perform operation *POP0 with constant *PCONST0 at the outermost
8830 position. We would now like to also perform OP1 with constant CONST1
8831 (with *POP0 being done last).
8833 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8834 the resulting operation. *PCOMP_P is set to 1 if we would need to
8835 complement the innermost operand, otherwise it is unchanged.
8837 MODE is the mode in which the operation will be done. No bits outside
8838 the width of this mode matter. It is assumed that the width of this mode
8839 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8841 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
8842 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8843 result is simply *PCONST0.
8845 If the resulting operation cannot be expressed as one operation, we
8846 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8849 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
8851 enum rtx_code op0 = *pop0;
8852 HOST_WIDE_INT const0 = *pconst0;
8854 const0 &= GET_MODE_MASK (mode);
8855 const1 &= GET_MODE_MASK (mode);
8857 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8861 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
8864 if (op1 == UNKNOWN || op0 == SET)
8867 else if (op0 == UNKNOWN)
8868 op0 = op1, const0 = const1;
8870 else if (op0 == op1)
8894 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8895 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8898 /* If the two constants aren't the same, we can't do anything. The
8899 remaining six cases can all be done. */
8900 else if (const0 != const1)
8908 /* (a & b) | b == b */
8910 else /* op1 == XOR */
8911 /* (a ^ b) | b == a | b */
8917 /* (a & b) ^ b == (~a) & b */
8918 op0 = AND, *pcomp_p = 1;
8919 else /* op1 == IOR */
8920 /* (a | b) ^ b == a & ~b */
8921 op0 = AND, const0 = ~const0;
8926 /* (a | b) & b == b */
8928 else /* op1 == XOR */
8929 /* (a ^ b) & b) == (~a) & b */
8936 /* Check for NO-OP cases. */
8937 const0 &= GET_MODE_MASK (mode);
8939 && (op0 == IOR || op0 == XOR || op0 == PLUS))
8941 else if (const0 == 0 && op0 == AND)
8943 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8949 /* ??? Slightly redundant with the above mask, but not entirely.
8950 Moving this above means we'd have to sign-extend the mode mask
8951 for the final test. */
8952 if (op0 != UNKNOWN && op0 != NEG)
8953 *pconst0 = trunc_int_for_mode (const0, mode);
8958 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8959 The result of the shift is RESULT_MODE. Return NULL_RTX if we cannot
8960 simplify it. Otherwise, return a simplified value.
8962 The shift is normally computed in the widest mode we find in VAROP, as
8963 long as it isn't a different number of words than RESULT_MODE. Exceptions
8964 are ASHIFTRT and ROTATE, which are always done in their original mode. */
8967 simplify_shift_const_1 (enum rtx_code code, enum machine_mode result_mode,
8968 rtx varop, int orig_count)
8970 enum rtx_code orig_code = code;
8971 rtx orig_varop = varop;
8973 enum machine_mode mode = result_mode;
8974 enum machine_mode shift_mode, tmode;
8975 unsigned int mode_words
8976 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8977 /* We form (outer_op (code varop count) (outer_const)). */
8978 enum rtx_code outer_op = UNKNOWN;
8979 HOST_WIDE_INT outer_const = 0;
8980 int complement_p = 0;
8983 /* Make sure and truncate the "natural" shift on the way in. We don't
8984 want to do this inside the loop as it makes it more difficult to
8986 if (SHIFT_COUNT_TRUNCATED)
8987 orig_count &= GET_MODE_BITSIZE (mode) - 1;
8989 /* If we were given an invalid count, don't do anything except exactly
8990 what was requested. */
8992 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
8997 /* Unless one of the branches of the `if' in this loop does a `continue',
8998 we will `break' the loop after the `if'. */
9002 /* If we have an operand of (clobber (const_int 0)), fail. */
9003 if (GET_CODE (varop) == CLOBBER)
9006 /* Convert ROTATERT to ROTATE. */
9007 if (code == ROTATERT)
9009 unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
9011 if (VECTOR_MODE_P (result_mode))
9012 count = bitsize / GET_MODE_NUNITS (result_mode) - count;
9014 count = bitsize - count;
9017 /* We need to determine what mode we will do the shift in. If the
9018 shift is a right shift or a ROTATE, we must always do it in the mode
9019 it was originally done in. Otherwise, we can do it in MODE, the
9020 widest mode encountered. */
9022 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9023 ? result_mode : mode);
9025 /* Handle cases where the count is greater than the size of the mode
9026 minus 1. For ASHIFT, use the size minus one as the count (this can
9027 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9028 take the count modulo the size. For other shifts, the result is
9031 Since these shifts are being produced by the compiler by combining
9032 multiple operations, each of which are defined, we know what the
9033 result is supposed to be. */
9035 if (count > (GET_MODE_BITSIZE (shift_mode) - 1))
9037 if (code == ASHIFTRT)
9038 count = GET_MODE_BITSIZE (shift_mode) - 1;
9039 else if (code == ROTATE || code == ROTATERT)
9040 count %= GET_MODE_BITSIZE (shift_mode);
9043 /* We can't simply return zero because there may be an
9051 /* If we discovered we had to complement VAROP, leave. Making a NOT
9052 here would cause an infinite loop. */
9056 /* An arithmetic right shift of a quantity known to be -1 or 0
9058 if (code == ASHIFTRT
9059 && (num_sign_bit_copies (varop, shift_mode)
9060 == GET_MODE_BITSIZE (shift_mode)))
9066 /* If we are doing an arithmetic right shift and discarding all but
9067 the sign bit copies, this is equivalent to doing a shift by the
9068 bitsize minus one. Convert it into that shift because it will often
9069 allow other simplifications. */
9071 if (code == ASHIFTRT
9072 && (count + num_sign_bit_copies (varop, shift_mode)
9073 >= GET_MODE_BITSIZE (shift_mode)))
9074 count = GET_MODE_BITSIZE (shift_mode) - 1;
9076 /* We simplify the tests below and elsewhere by converting
9077 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9078 `make_compound_operation' will convert it to an ASHIFTRT for
9079 those machines (such as VAX) that don't have an LSHIFTRT. */
9080 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9082 && ((nonzero_bits (varop, shift_mode)
9083 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
9087 if (((code == LSHIFTRT
9088 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9089 && !(nonzero_bits (varop, shift_mode) >> count))
9091 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9092 && !((nonzero_bits (varop, shift_mode) << count)
9093 & GET_MODE_MASK (shift_mode))))
9094 && !side_effects_p (varop))
9097 switch (GET_CODE (varop))
9103 new_rtx = expand_compound_operation (varop);
9104 if (new_rtx != varop)
9112 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9113 minus the width of a smaller mode, we can do this with a
9114 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9115 if ((code == ASHIFTRT || code == LSHIFTRT)
9116 && ! mode_dependent_address_p (XEXP (varop, 0))
9117 && ! MEM_VOLATILE_P (varop)
9118 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9119 MODE_INT, 1)) != BLKmode)
9121 new_rtx = adjust_address_nv (varop, tmode,
9122 BYTES_BIG_ENDIAN ? 0
9123 : count / BITS_PER_UNIT);
9125 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9126 : ZERO_EXTEND, mode, new_rtx);
9133 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9134 the same number of words as what we've seen so far. Then store
9135 the widest mode in MODE. */
9136 if (subreg_lowpart_p (varop)
9137 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9138 > GET_MODE_SIZE (GET_MODE (varop)))
9139 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9140 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9143 varop = SUBREG_REG (varop);
9144 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
9145 mode = GET_MODE (varop);
9151 /* Some machines use MULT instead of ASHIFT because MULT
9152 is cheaper. But it is still better on those machines to
9153 merge two shifts into one. */
9154 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9155 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9158 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
9160 GEN_INT (exact_log2 (
9161 INTVAL (XEXP (varop, 1)))));
9167 /* Similar, for when divides are cheaper. */
9168 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9169 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9172 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
9174 GEN_INT (exact_log2 (
9175 INTVAL (XEXP (varop, 1)))));
9181 /* If we are extracting just the sign bit of an arithmetic
9182 right shift, that shift is not needed. However, the sign
9183 bit of a wider mode may be different from what would be
9184 interpreted as the sign bit in a narrower mode, so, if
9185 the result is narrower, don't discard the shift. */
9186 if (code == LSHIFTRT
9187 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9188 && (GET_MODE_BITSIZE (result_mode)
9189 >= GET_MODE_BITSIZE (GET_MODE (varop))))
9191 varop = XEXP (varop, 0);
9195 /* ... fall through ... */
9200 /* Here we have two nested shifts. The result is usually the
9201 AND of a new shift with a mask. We compute the result below. */
9202 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9203 && INTVAL (XEXP (varop, 1)) >= 0
9204 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
9205 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9206 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9207 && !VECTOR_MODE_P (result_mode))
9209 enum rtx_code first_code = GET_CODE (varop);
9210 unsigned int first_count = INTVAL (XEXP (varop, 1));
9211 unsigned HOST_WIDE_INT mask;
9214 /* We have one common special case. We can't do any merging if
9215 the inner code is an ASHIFTRT of a smaller mode. However, if
9216 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9217 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9218 we can convert it to
9219 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9220 This simplifies certain SIGN_EXTEND operations. */
9221 if (code == ASHIFT && first_code == ASHIFTRT
9222 && count == (GET_MODE_BITSIZE (result_mode)
9223 - GET_MODE_BITSIZE (GET_MODE (varop))))
9225 /* C3 has the low-order C1 bits zero. */
9227 mask = (GET_MODE_MASK (mode)
9228 & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
9230 varop = simplify_and_const_int (NULL_RTX, result_mode,
9231 XEXP (varop, 0), mask);
9232 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
9234 count = first_count;
9239 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9240 than C1 high-order bits equal to the sign bit, we can convert
9241 this to either an ASHIFT or an ASHIFTRT depending on the
9244 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9246 if (code == ASHIFTRT && first_code == ASHIFT
9247 && GET_MODE (varop) == shift_mode
9248 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
9251 varop = XEXP (varop, 0);
9252 count -= first_count;
9262 /* There are some cases we can't do. If CODE is ASHIFTRT,
9263 we can only do this if FIRST_CODE is also ASHIFTRT.
9265 We can't do the case when CODE is ROTATE and FIRST_CODE is
9268 If the mode of this shift is not the mode of the outer shift,
9269 we can't do this if either shift is a right shift or ROTATE.
9271 Finally, we can't do any of these if the mode is too wide
9272 unless the codes are the same.
9274 Handle the case where the shift codes are the same
9277 if (code == first_code)
9279 if (GET_MODE (varop) != result_mode
9280 && (code == ASHIFTRT || code == LSHIFTRT
9284 count += first_count;
9285 varop = XEXP (varop, 0);
9289 if (code == ASHIFTRT
9290 || (code == ROTATE && first_code == ASHIFTRT)
9291 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
9292 || (GET_MODE (varop) != result_mode
9293 && (first_code == ASHIFTRT || first_code == LSHIFTRT
9294 || first_code == ROTATE
9295 || code == ROTATE)))
9298 /* To compute the mask to apply after the shift, shift the
9299 nonzero bits of the inner shift the same way the
9300 outer shift will. */
9302 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
9305 = simplify_const_binary_operation (code, result_mode, mask_rtx,
9308 /* Give up if we can't compute an outer operation to use. */
9310 || GET_CODE (mask_rtx) != CONST_INT
9311 || ! merge_outer_ops (&outer_op, &outer_const, AND,
9313 result_mode, &complement_p))
9316 /* If the shifts are in the same direction, we add the
9317 counts. Otherwise, we subtract them. */
9318 if ((code == ASHIFTRT || code == LSHIFTRT)
9319 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
9320 count += first_count;
9322 count -= first_count;
9324 /* If COUNT is positive, the new shift is usually CODE,
9325 except for the two exceptions below, in which case it is
9326 FIRST_CODE. If the count is negative, FIRST_CODE should
9329 && ((first_code == ROTATE && code == ASHIFT)
9330 || (first_code == ASHIFTRT && code == LSHIFTRT)))
9333 code = first_code, count = -count;
9335 varop = XEXP (varop, 0);
9339 /* If we have (A << B << C) for any shift, we can convert this to
9340 (A << C << B). This wins if A is a constant. Only try this if
9341 B is not a constant. */
9343 else if (GET_CODE (varop) == code
9344 && GET_CODE (XEXP (varop, 0)) == CONST_INT
9345 && GET_CODE (XEXP (varop, 1)) != CONST_INT)
9347 rtx new_rtx = simplify_const_binary_operation (code, mode,
9350 varop = gen_rtx_fmt_ee (code, mode, new_rtx, XEXP (varop, 1));
9357 if (VECTOR_MODE_P (mode))
9360 /* Make this fit the case below. */
9361 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
9362 GEN_INT (GET_MODE_MASK (mode)));
9368 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9369 with C the size of VAROP - 1 and the shift is logical if
9370 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9371 we have an (le X 0) operation. If we have an arithmetic shift
9372 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9373 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9375 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
9376 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
9377 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9378 && (code == LSHIFTRT || code == ASHIFTRT)
9379 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9380 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9383 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
9386 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9387 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9392 /* If we have (shift (logical)), move the logical to the outside
9393 to allow it to possibly combine with another logical and the
9394 shift to combine with another shift. This also canonicalizes to
9395 what a ZERO_EXTRACT looks like. Also, some machines have
9396 (and (shift)) insns. */
9398 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9399 /* We can't do this if we have (ashiftrt (xor)) and the
9400 constant has its sign bit set in shift_mode. */
9401 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
9402 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
9404 && (new_rtx = simplify_const_binary_operation (code, result_mode,
9406 GEN_INT (count))) != 0
9407 && GET_CODE (new_rtx) == CONST_INT
9408 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
9409 INTVAL (new_rtx), result_mode, &complement_p))
9411 varop = XEXP (varop, 0);
9415 /* If we can't do that, try to simplify the shift in each arm of the
9416 logical expression, make a new logical expression, and apply
9417 the inverse distributive law. This also can't be done
9418 for some (ashiftrt (xor)). */
9419 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9420 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
9421 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
9424 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9425 XEXP (varop, 0), count);
9426 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9427 XEXP (varop, 1), count);
9429 varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
9431 varop = apply_distributive_law (varop);
9439 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9440 says that the sign bit can be tested, FOO has mode MODE, C is
9441 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9442 that may be nonzero. */
9443 if (code == LSHIFTRT
9444 && XEXP (varop, 1) == const0_rtx
9445 && GET_MODE (XEXP (varop, 0)) == result_mode
9446 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9447 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9448 && STORE_FLAG_VALUE == -1
9449 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9450 && merge_outer_ops (&outer_op, &outer_const, XOR,
9451 (HOST_WIDE_INT) 1, result_mode,
9454 varop = XEXP (varop, 0);
9461 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9462 than the number of bits in the mode is equivalent to A. */
9463 if (code == LSHIFTRT
9464 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9465 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9467 varop = XEXP (varop, 0);
9472 /* NEG commutes with ASHIFT since it is multiplication. Move the
9473 NEG outside to allow shifts to combine. */
9475 && merge_outer_ops (&outer_op, &outer_const, NEG,
9476 (HOST_WIDE_INT) 0, result_mode,
9479 varop = XEXP (varop, 0);
9485 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9486 is one less than the number of bits in the mode is
9487 equivalent to (xor A 1). */
9488 if (code == LSHIFTRT
9489 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9490 && XEXP (varop, 1) == constm1_rtx
9491 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9492 && merge_outer_ops (&outer_op, &outer_const, XOR,
9493 (HOST_WIDE_INT) 1, result_mode,
9497 varop = XEXP (varop, 0);
9501 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9502 that might be nonzero in BAR are those being shifted out and those
9503 bits are known zero in FOO, we can replace the PLUS with FOO.
9504 Similarly in the other operand order. This code occurs when
9505 we are computing the size of a variable-size array. */
9507 if ((code == ASHIFTRT || code == LSHIFTRT)
9508 && count < HOST_BITS_PER_WIDE_INT
9509 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9510 && (nonzero_bits (XEXP (varop, 1), result_mode)
9511 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9513 varop = XEXP (varop, 0);
9516 else if ((code == ASHIFTRT || code == LSHIFTRT)
9517 && count < HOST_BITS_PER_WIDE_INT
9518 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9519 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9521 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9522 & nonzero_bits (XEXP (varop, 1),
9525 varop = XEXP (varop, 1);
9529 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9531 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9532 && (new_rtx = simplify_const_binary_operation (ASHIFT, result_mode,
9534 GEN_INT (count))) != 0
9535 && GET_CODE (new_rtx) == CONST_INT
9536 && merge_outer_ops (&outer_op, &outer_const, PLUS,
9537 INTVAL (new_rtx), result_mode, &complement_p))
9539 varop = XEXP (varop, 0);
9543 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
9544 signbit', and attempt to change the PLUS to an XOR and move it to
9545 the outer operation as is done above in the AND/IOR/XOR case
9546 leg for shift(logical). See details in logical handling above
9547 for reasoning in doing so. */
9548 if (code == LSHIFTRT
9549 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9550 && mode_signbit_p (result_mode, XEXP (varop, 1))
9551 && (new_rtx = simplify_const_binary_operation (code, result_mode,
9553 GEN_INT (count))) != 0
9554 && GET_CODE (new_rtx) == CONST_INT
9555 && merge_outer_ops (&outer_op, &outer_const, XOR,
9556 INTVAL (new_rtx), result_mode, &complement_p))
9558 varop = XEXP (varop, 0);
9565 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9566 with C the size of VAROP - 1 and the shift is logical if
9567 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9568 we have a (gt X 0) operation. If the shift is arithmetic with
9569 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9570 we have a (neg (gt X 0)) operation. */
9572 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9573 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9574 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9575 && (code == LSHIFTRT || code == ASHIFTRT)
9576 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9577 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
9578 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9581 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9584 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9585 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9592 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9593 if the truncate does not affect the value. */
9594 if (code == LSHIFTRT
9595 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9596 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9597 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9598 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9599 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9601 rtx varop_inner = XEXP (varop, 0);
9604 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9605 XEXP (varop_inner, 0),
9607 (count + INTVAL (XEXP (varop_inner, 1))));
9608 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9621 /* We need to determine what mode to do the shift in. If the shift is
9622 a right shift or ROTATE, we must always do it in the mode it was
9623 originally done in. Otherwise, we can do it in MODE, the widest mode
9624 encountered. The code we care about is that of the shift that will
9625 actually be done, not the shift that was originally requested. */
9627 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9628 ? result_mode : mode);
9630 /* We have now finished analyzing the shift. The result should be
9631 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9632 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
9633 to the result of the shift. OUTER_CONST is the relevant constant,
9634 but we must turn off all bits turned off in the shift. */
9636 if (outer_op == UNKNOWN
9637 && orig_code == code && orig_count == count
9638 && varop == orig_varop
9639 && shift_mode == GET_MODE (varop))
9642 /* Make a SUBREG if necessary. If we can't make it, fail. */
9643 varop = gen_lowpart (shift_mode, varop);
9644 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
9647 /* If we have an outer operation and we just made a shift, it is
9648 possible that we could have simplified the shift were it not
9649 for the outer operation. So try to do the simplification
9652 if (outer_op != UNKNOWN)
9653 x = simplify_shift_const_1 (code, shift_mode, varop, count);
9658 x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count));
9660 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9661 turn off all the bits that the shift would have turned off. */
9662 if (orig_code == LSHIFTRT && result_mode != shift_mode)
9663 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9664 GET_MODE_MASK (result_mode) >> orig_count);
9666 /* Do the remainder of the processing in RESULT_MODE. */
9667 x = gen_lowpart_or_truncate (result_mode, x);
9669 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9672 x = simplify_gen_unary (NOT, result_mode, x, result_mode);
9674 if (outer_op != UNKNOWN)
9676 if (GET_RTX_CLASS (outer_op) != RTX_UNARY
9677 && GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9678 outer_const = trunc_int_for_mode (outer_const, result_mode);
9680 if (outer_op == AND)
9681 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9682 else if (outer_op == SET)
9684 /* This means that we have determined that the result is
9685 equivalent to a constant. This should be rare. */
9686 if (!side_effects_p (x))
9687 x = GEN_INT (outer_const);
9689 else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
9690 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
9692 x = simplify_gen_binary (outer_op, result_mode, x,
9693 GEN_INT (outer_const));
9699 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9700 The result of the shift is RESULT_MODE. If we cannot simplify it,
9701 return X or, if it is NULL, synthesize the expression with
9702 simplify_gen_binary. Otherwise, return a simplified value.
9704 The shift is normally computed in the widest mode we find in VAROP, as
9705 long as it isn't a different number of words than RESULT_MODE. Exceptions
9706 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9709 simplify_shift_const (rtx x, enum rtx_code code, enum machine_mode result_mode,
9710 rtx varop, int count)
9712 rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
9717 x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count));
9718 if (GET_MODE (x) != result_mode)
9719 x = gen_lowpart (result_mode, x);
9724 /* Like recog, but we receive the address of a pointer to a new pattern.
9725 We try to match the rtx that the pointer points to.
9726 If that fails, we may try to modify or replace the pattern,
9727 storing the replacement into the same pointer object.
9729 Modifications include deletion or addition of CLOBBERs.
9731 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9732 the CLOBBERs are placed.
9734 The value is the final insn code from the pattern ultimately matched,
9738 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
9741 int insn_code_number;
9742 int num_clobbers_to_add = 0;
9745 rtx old_notes, old_pat;
9747 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9748 we use to indicate that something didn't match. If we find such a
9749 thing, force rejection. */
9750 if (GET_CODE (pat) == PARALLEL)
9751 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9752 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9753 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9756 old_pat = PATTERN (insn);
9757 old_notes = REG_NOTES (insn);
9758 PATTERN (insn) = pat;
9759 REG_NOTES (insn) = 0;
9761 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9762 if (dump_file && (dump_flags & TDF_DETAILS))
9764 if (insn_code_number < 0)
9765 fputs ("Failed to match this instruction:\n", dump_file);
9767 fputs ("Successfully matched this instruction:\n", dump_file);
9768 print_rtl_single (dump_file, pat);
9771 /* If it isn't, there is the possibility that we previously had an insn
9772 that clobbered some register as a side effect, but the combined
9773 insn doesn't need to do that. So try once more without the clobbers
9774 unless this represents an ASM insn. */
9776 if (insn_code_number < 0 && ! check_asm_operands (pat)
9777 && GET_CODE (pat) == PARALLEL)
9781 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9782 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9785 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9789 SUBST_INT (XVECLEN (pat, 0), pos);
9792 pat = XVECEXP (pat, 0, 0);
9794 PATTERN (insn) = pat;
9795 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9796 if (dump_file && (dump_flags & TDF_DETAILS))
9798 if (insn_code_number < 0)
9799 fputs ("Failed to match this instruction:\n", dump_file);
9801 fputs ("Successfully matched this instruction:\n", dump_file);
9802 print_rtl_single (dump_file, pat);
9805 PATTERN (insn) = old_pat;
9806 REG_NOTES (insn) = old_notes;
9808 /* Recognize all noop sets, these will be killed by followup pass. */
9809 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
9810 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
9812 /* If we had any clobbers to add, make a new pattern than contains
9813 them. Then check to make sure that all of them are dead. */
9814 if (num_clobbers_to_add)
9816 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9817 rtvec_alloc (GET_CODE (pat) == PARALLEL
9819 + num_clobbers_to_add)
9820 : num_clobbers_to_add + 1));
9822 if (GET_CODE (pat) == PARALLEL)
9823 for (i = 0; i < XVECLEN (pat, 0); i++)
9824 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9826 XVECEXP (newpat, 0, 0) = pat;
9828 add_clobbers (newpat, insn_code_number);
9830 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9831 i < XVECLEN (newpat, 0); i++)
9833 if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
9834 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9836 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) != SCRATCH)
9838 gcc_assert (REG_P (XEXP (XVECEXP (newpat, 0, i), 0)));
9839 notes = alloc_reg_note (REG_UNUSED,
9840 XEXP (XVECEXP (newpat, 0, i), 0), notes);
9849 return insn_code_number;
9852 /* Like gen_lowpart_general but for use by combine. In combine it
9853 is not possible to create any new pseudoregs. However, it is
9854 safe to create invalid memory addresses, because combine will
9855 try to recognize them and all they will do is make the combine
9858 If for some reason this cannot do its job, an rtx
9859 (clobber (const_int 0)) is returned.
9860 An insn containing that will not be recognized. */
9863 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
9865 enum machine_mode imode = GET_MODE (x);
9866 unsigned int osize = GET_MODE_SIZE (omode);
9867 unsigned int isize = GET_MODE_SIZE (imode);
9873 /* Return identity if this is a CONST or symbolic reference. */
9875 && (GET_CODE (x) == CONST
9876 || GET_CODE (x) == SYMBOL_REF
9877 || GET_CODE (x) == LABEL_REF))
9880 /* We can only support MODE being wider than a word if X is a
9881 constant integer or has a mode the same size. */
9882 if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
9883 && ! ((imode == VOIDmode
9884 && (GET_CODE (x) == CONST_INT
9885 || GET_CODE (x) == CONST_DOUBLE))
9889 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9890 won't know what to do. So we will strip off the SUBREG here and
9891 process normally. */
9892 if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
9896 /* For use in case we fall down into the address adjustments
9897 further below, we need to adjust the known mode and size of
9898 x; imode and isize, since we just adjusted x. */
9899 imode = GET_MODE (x);
9904 isize = GET_MODE_SIZE (imode);
9907 result = gen_lowpart_common (omode, x);
9916 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9918 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9921 /* If we want to refer to something bigger than the original memref,
9922 generate a paradoxical subreg instead. That will force a reload
9923 of the original memref X. */
9925 return gen_rtx_SUBREG (omode, x, 0);
9927 if (WORDS_BIG_ENDIAN)
9928 offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
9930 /* Adjust the address so that the address-after-the-data is
9932 if (BYTES_BIG_ENDIAN)
9933 offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
9935 return adjust_address_nv (x, omode, offset);
9938 /* If X is a comparison operator, rewrite it in a new mode. This
9939 probably won't match, but may allow further simplifications. */
9940 else if (COMPARISON_P (x))
9941 return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
9943 /* If we couldn't simplify X any other way, just enclose it in a
9944 SUBREG. Normally, this SUBREG won't match, but some patterns may
9945 include an explicit SUBREG or we may simplify it further in combine. */
9951 offset = subreg_lowpart_offset (omode, imode);
9952 if (imode == VOIDmode)
9954 imode = int_mode_for_mode (omode);
9955 x = gen_lowpart_common (imode, x);
9959 res = simplify_gen_subreg (omode, x, imode, offset);
9965 return gen_rtx_CLOBBER (omode, const0_rtx);
9968 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9969 comparison code that will be tested.
9971 The result is a possibly different comparison code to use. *POP0 and
9972 *POP1 may be updated.
9974 It is possible that we might detect that a comparison is either always
9975 true or always false. However, we do not perform general constant
9976 folding in combine, so this knowledge isn't useful. Such tautologies
9977 should have been detected earlier. Hence we ignore all such cases. */
9979 static enum rtx_code
9980 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
9986 enum machine_mode mode, tmode;
9988 /* Try a few ways of applying the same transformation to both operands. */
9991 #ifndef WORD_REGISTER_OPERATIONS
9992 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9993 so check specially. */
9994 if (code != GTU && code != GEU && code != LTU && code != LEU
9995 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9996 && GET_CODE (XEXP (op0, 0)) == ASHIFT
9997 && GET_CODE (XEXP (op1, 0)) == ASHIFT
9998 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9999 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
10000 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
10001 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
10002 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10003 && XEXP (op0, 1) == XEXP (op1, 1)
10004 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10005 && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
10006 && (INTVAL (XEXP (op0, 1))
10007 == (GET_MODE_BITSIZE (GET_MODE (op0))
10008 - (GET_MODE_BITSIZE
10009 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
10011 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
10012 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
10016 /* If both operands are the same constant shift, see if we can ignore the
10017 shift. We can if the shift is a rotate or if the bits shifted out of
10018 this shift are known to be zero for both inputs and if the type of
10019 comparison is compatible with the shift. */
10020 if (GET_CODE (op0) == GET_CODE (op1)
10021 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10022 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
10023 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
10024 && (code != GT && code != LT && code != GE && code != LE))
10025 || (GET_CODE (op0) == ASHIFTRT
10026 && (code != GTU && code != LTU
10027 && code != GEU && code != LEU)))
10028 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10029 && INTVAL (XEXP (op0, 1)) >= 0
10030 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10031 && XEXP (op0, 1) == XEXP (op1, 1))
10033 enum machine_mode mode = GET_MODE (op0);
10034 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10035 int shift_count = INTVAL (XEXP (op0, 1));
10037 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
10038 mask &= (mask >> shift_count) << shift_count;
10039 else if (GET_CODE (op0) == ASHIFT)
10040 mask = (mask & (mask << shift_count)) >> shift_count;
10042 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
10043 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
10044 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
10049 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10050 SUBREGs are of the same mode, and, in both cases, the AND would
10051 be redundant if the comparison was done in the narrower mode,
10052 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10053 and the operand's possibly nonzero bits are 0xffffff01; in that case
10054 if we only care about QImode, we don't need the AND). This case
10055 occurs if the output mode of an scc insn is not SImode and
10056 STORE_FLAG_VALUE == 1 (e.g., the 386).
10058 Similarly, check for a case where the AND's are ZERO_EXTEND
10059 operations from some narrower mode even though a SUBREG is not
10062 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
10063 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10064 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
10066 rtx inner_op0 = XEXP (op0, 0);
10067 rtx inner_op1 = XEXP (op1, 0);
10068 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
10069 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
10072 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
10073 && (GET_MODE_SIZE (GET_MODE (inner_op0))
10074 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
10075 && (GET_MODE (SUBREG_REG (inner_op0))
10076 == GET_MODE (SUBREG_REG (inner_op1)))
10077 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
10078 <= HOST_BITS_PER_WIDE_INT)
10079 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
10080 GET_MODE (SUBREG_REG (inner_op0)))))
10081 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
10082 GET_MODE (SUBREG_REG (inner_op1))))))
10084 op0 = SUBREG_REG (inner_op0);
10085 op1 = SUBREG_REG (inner_op1);
10087 /* The resulting comparison is always unsigned since we masked
10088 off the original sign bit. */
10089 code = unsigned_condition (code);
10095 for (tmode = GET_CLASS_NARROWEST_MODE
10096 (GET_MODE_CLASS (GET_MODE (op0)));
10097 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
10098 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
10100 op0 = gen_lowpart (tmode, inner_op0);
10101 op1 = gen_lowpart (tmode, inner_op1);
10102 code = unsigned_condition (code);
10111 /* If both operands are NOT, we can strip off the outer operation
10112 and adjust the comparison code for swapped operands; similarly for
10113 NEG, except that this must be an equality comparison. */
10114 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
10115 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
10116 && (code == EQ || code == NE)))
10117 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
10123 /* If the first operand is a constant, swap the operands and adjust the
10124 comparison code appropriately, but don't do this if the second operand
10125 is already a constant integer. */
10126 if (swap_commutative_operands_p (op0, op1))
10128 tem = op0, op0 = op1, op1 = tem;
10129 code = swap_condition (code);
10132 /* We now enter a loop during which we will try to simplify the comparison.
10133 For the most part, we only are concerned with comparisons with zero,
10134 but some things may really be comparisons with zero but not start
10135 out looking that way. */
10137 while (GET_CODE (op1) == CONST_INT)
10139 enum machine_mode mode = GET_MODE (op0);
10140 unsigned int mode_width = GET_MODE_BITSIZE (mode);
10141 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10142 int equality_comparison_p;
10143 int sign_bit_comparison_p;
10144 int unsigned_comparison_p;
10145 HOST_WIDE_INT const_op;
10147 /* We only want to handle integral modes. This catches VOIDmode,
10148 CCmode, and the floating-point modes. An exception is that we
10149 can handle VOIDmode if OP0 is a COMPARE or a comparison
10152 if (GET_MODE_CLASS (mode) != MODE_INT
10153 && ! (mode == VOIDmode
10154 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
10157 /* Get the constant we are comparing against and turn off all bits
10158 not on in our mode. */
10159 const_op = INTVAL (op1);
10160 if (mode != VOIDmode)
10161 const_op = trunc_int_for_mode (const_op, mode);
10162 op1 = GEN_INT (const_op);
10164 /* If we are comparing against a constant power of two and the value
10165 being compared can only have that single bit nonzero (e.g., it was
10166 `and'ed with that bit), we can replace this with a comparison
10169 && (code == EQ || code == NE || code == GE || code == GEU
10170 || code == LT || code == LTU)
10171 && mode_width <= HOST_BITS_PER_WIDE_INT
10172 && exact_log2 (const_op) >= 0
10173 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
10175 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10176 op1 = const0_rtx, const_op = 0;
10179 /* Similarly, if we are comparing a value known to be either -1 or
10180 0 with -1, change it to the opposite comparison against zero. */
10183 && (code == EQ || code == NE || code == GT || code == LE
10184 || code == GEU || code == LTU)
10185 && num_sign_bit_copies (op0, mode) == mode_width)
10187 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10188 op1 = const0_rtx, const_op = 0;
10191 /* Do some canonicalizations based on the comparison code. We prefer
10192 comparisons against zero and then prefer equality comparisons.
10193 If we can reduce the size of a constant, we will do that too. */
10198 /* < C is equivalent to <= (C - 1) */
10202 op1 = GEN_INT (const_op);
10204 /* ... fall through to LE case below. */
10210 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10214 op1 = GEN_INT (const_op);
10218 /* If we are doing a <= 0 comparison on a value known to have
10219 a zero sign bit, we can replace this with == 0. */
10220 else if (const_op == 0
10221 && mode_width <= HOST_BITS_PER_WIDE_INT
10222 && (nonzero_bits (op0, mode)
10223 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10228 /* >= C is equivalent to > (C - 1). */
10232 op1 = GEN_INT (const_op);
10234 /* ... fall through to GT below. */
10240 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10244 op1 = GEN_INT (const_op);
10248 /* If we are doing a > 0 comparison on a value known to have
10249 a zero sign bit, we can replace this with != 0. */
10250 else if (const_op == 0
10251 && mode_width <= HOST_BITS_PER_WIDE_INT
10252 && (nonzero_bits (op0, mode)
10253 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10258 /* < C is equivalent to <= (C - 1). */
10262 op1 = GEN_INT (const_op);
10264 /* ... fall through ... */
10267 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10268 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10269 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10271 const_op = 0, op1 = const0_rtx;
10279 /* unsigned <= 0 is equivalent to == 0 */
10283 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10284 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10285 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10287 const_op = 0, op1 = const0_rtx;
10293 /* >= C is equivalent to > (C - 1). */
10297 op1 = GEN_INT (const_op);
10299 /* ... fall through ... */
10302 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10303 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10304 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10306 const_op = 0, op1 = const0_rtx;
10314 /* unsigned > 0 is equivalent to != 0 */
10318 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10319 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10320 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10322 const_op = 0, op1 = const0_rtx;
10331 /* Compute some predicates to simplify code below. */
10333 equality_comparison_p = (code == EQ || code == NE);
10334 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
10335 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
10338 /* If this is a sign bit comparison and we can do arithmetic in
10339 MODE, say that we will only be needing the sign bit of OP0. */
10340 if (sign_bit_comparison_p
10341 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10342 op0 = force_to_mode (op0, mode,
10344 << (GET_MODE_BITSIZE (mode) - 1)),
10347 /* Now try cases based on the opcode of OP0. If none of the cases
10348 does a "continue", we exit this loop immediately after the
10351 switch (GET_CODE (op0))
10354 /* If we are extracting a single bit from a variable position in
10355 a constant that has only a single bit set and are comparing it
10356 with zero, we can convert this into an equality comparison
10357 between the position and the location of the single bit. */
10358 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
10359 have already reduced the shift count modulo the word size. */
10360 if (!SHIFT_COUNT_TRUNCATED
10361 && GET_CODE (XEXP (op0, 0)) == CONST_INT
10362 && XEXP (op0, 1) == const1_rtx
10363 && equality_comparison_p && const_op == 0
10364 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
10366 if (BITS_BIG_ENDIAN)
10368 enum machine_mode new_mode
10369 = mode_for_extraction (EP_extzv, 1);
10370 if (new_mode == MAX_MACHINE_MODE)
10371 i = BITS_PER_WORD - 1 - i;
10375 i = (GET_MODE_BITSIZE (mode) - 1 - i);
10379 op0 = XEXP (op0, 2);
10383 /* Result is nonzero iff shift count is equal to I. */
10384 code = reverse_condition (code);
10388 /* ... fall through ... */
10391 tem = expand_compound_operation (op0);
10400 /* If testing for equality, we can take the NOT of the constant. */
10401 if (equality_comparison_p
10402 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
10404 op0 = XEXP (op0, 0);
10409 /* If just looking at the sign bit, reverse the sense of the
10411 if (sign_bit_comparison_p)
10413 op0 = XEXP (op0, 0);
10414 code = (code == GE ? LT : GE);
10420 /* If testing for equality, we can take the NEG of the constant. */
10421 if (equality_comparison_p
10422 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
10424 op0 = XEXP (op0, 0);
10429 /* The remaining cases only apply to comparisons with zero. */
10433 /* When X is ABS or is known positive,
10434 (neg X) is < 0 if and only if X != 0. */
10436 if (sign_bit_comparison_p
10437 && (GET_CODE (XEXP (op0, 0)) == ABS
10438 || (mode_width <= HOST_BITS_PER_WIDE_INT
10439 && (nonzero_bits (XEXP (op0, 0), mode)
10440 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
10442 op0 = XEXP (op0, 0);
10443 code = (code == LT ? NE : EQ);
10447 /* If we have NEG of something whose two high-order bits are the
10448 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10449 if (num_sign_bit_copies (op0, mode) >= 2)
10451 op0 = XEXP (op0, 0);
10452 code = swap_condition (code);
10458 /* If we are testing equality and our count is a constant, we
10459 can perform the inverse operation on our RHS. */
10460 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10461 && (tem = simplify_binary_operation (ROTATERT, mode,
10462 op1, XEXP (op0, 1))) != 0)
10464 op0 = XEXP (op0, 0);
10469 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10470 a particular bit. Convert it to an AND of a constant of that
10471 bit. This will be converted into a ZERO_EXTRACT. */
10472 if (const_op == 0 && sign_bit_comparison_p
10473 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10474 && mode_width <= HOST_BITS_PER_WIDE_INT)
10476 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10479 - INTVAL (XEXP (op0, 1)))));
10480 code = (code == LT ? NE : EQ);
10484 /* Fall through. */
10487 /* ABS is ignorable inside an equality comparison with zero. */
10488 if (const_op == 0 && equality_comparison_p)
10490 op0 = XEXP (op0, 0);
10496 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
10497 (compare FOO CONST) if CONST fits in FOO's mode and we
10498 are either testing inequality or have an unsigned
10499 comparison with ZERO_EXTEND or a signed comparison with
10500 SIGN_EXTEND. But don't do it if we don't have a compare
10501 insn of the given mode, since we'd have to revert it
10502 later on, and then we wouldn't know whether to sign- or
10504 mode = GET_MODE (XEXP (op0, 0));
10505 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10506 && ! unsigned_comparison_p
10507 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10508 && ((unsigned HOST_WIDE_INT) const_op
10509 < (((unsigned HOST_WIDE_INT) 1
10510 << (GET_MODE_BITSIZE (mode) - 1))))
10511 && have_insn_for (COMPARE, mode))
10513 op0 = XEXP (op0, 0);
10519 /* Check for the case where we are comparing A - C1 with C2, that is
10521 (subreg:MODE (plus (A) (-C1))) op (C2)
10523 with C1 a constant, and try to lift the SUBREG, i.e. to do the
10524 comparison in the wider mode. One of the following two conditions
10525 must be true in order for this to be valid:
10527 1. The mode extension results in the same bit pattern being added
10528 on both sides and the comparison is equality or unsigned. As
10529 C2 has been truncated to fit in MODE, the pattern can only be
10532 2. The mode extension results in the sign bit being copied on
10535 The difficulty here is that we have predicates for A but not for
10536 (A - C1) so we need to check that C1 is within proper bounds so
10537 as to perturbate A as little as possible. */
10539 if (mode_width <= HOST_BITS_PER_WIDE_INT
10540 && subreg_lowpart_p (op0)
10541 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) > mode_width
10542 && GET_CODE (SUBREG_REG (op0)) == PLUS
10543 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT)
10545 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
10546 rtx a = XEXP (SUBREG_REG (op0), 0);
10547 HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
10550 && (unsigned HOST_WIDE_INT) c1
10551 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
10552 && (equality_comparison_p || unsigned_comparison_p)
10553 /* (A - C1) zero-extends if it is positive and sign-extends
10554 if it is negative, C2 both zero- and sign-extends. */
10555 && ((0 == (nonzero_bits (a, inner_mode)
10556 & ~GET_MODE_MASK (mode))
10558 /* (A - C1) sign-extends if it is positive and 1-extends
10559 if it is negative, C2 both sign- and 1-extends. */
10560 || (num_sign_bit_copies (a, inner_mode)
10561 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10564 || ((unsigned HOST_WIDE_INT) c1
10565 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
10566 /* (A - C1) always sign-extends, like C2. */
10567 && num_sign_bit_copies (a, inner_mode)
10568 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10569 - (mode_width - 1))))
10571 op0 = SUBREG_REG (op0);
10576 /* If the inner mode is narrower and we are extracting the low part,
10577 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10578 if (subreg_lowpart_p (op0)
10579 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10580 /* Fall through */ ;
10584 /* ... fall through ... */
10587 mode = GET_MODE (XEXP (op0, 0));
10588 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10589 && (unsigned_comparison_p || equality_comparison_p)
10590 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10591 && ((unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode))
10592 && have_insn_for (COMPARE, mode))
10594 op0 = XEXP (op0, 0);
10600 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10601 this for equality comparisons due to pathological cases involving
10603 if (equality_comparison_p
10604 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10605 op1, XEXP (op0, 1))))
10607 op0 = XEXP (op0, 0);
10612 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10613 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10614 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10616 op0 = XEXP (XEXP (op0, 0), 0);
10617 code = (code == LT ? EQ : NE);
10623 /* We used to optimize signed comparisons against zero, but that
10624 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10625 arrive here as equality comparisons, or (GEU, LTU) are
10626 optimized away. No need to special-case them. */
10628 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10629 (eq B (minus A C)), whichever simplifies. We can only do
10630 this for equality comparisons due to pathological cases involving
10632 if (equality_comparison_p
10633 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10634 XEXP (op0, 1), op1)))
10636 op0 = XEXP (op0, 0);
10641 if (equality_comparison_p
10642 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10643 XEXP (op0, 0), op1)))
10645 op0 = XEXP (op0, 1);
10650 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10651 of bits in X minus 1, is one iff X > 0. */
10652 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10653 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10654 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1))
10656 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10658 op0 = XEXP (op0, 1);
10659 code = (code == GE ? LE : GT);
10665 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10666 if C is zero or B is a constant. */
10667 if (equality_comparison_p
10668 && 0 != (tem = simplify_binary_operation (XOR, mode,
10669 XEXP (op0, 1), op1)))
10671 op0 = XEXP (op0, 0);
10678 case UNEQ: case LTGT:
10679 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
10680 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
10681 case UNORDERED: case ORDERED:
10682 /* We can't do anything if OP0 is a condition code value, rather
10683 than an actual data value. */
10685 || CC0_P (XEXP (op0, 0))
10686 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10689 /* Get the two operands being compared. */
10690 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10691 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10693 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10695 /* Check for the cases where we simply want the result of the
10696 earlier test or the opposite of that result. */
10697 if (code == NE || code == EQ
10698 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10699 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10700 && (STORE_FLAG_VALUE
10701 & (((HOST_WIDE_INT) 1
10702 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10703 && (code == LT || code == GE)))
10705 enum rtx_code new_code;
10706 if (code == LT || code == NE)
10707 new_code = GET_CODE (op0);
10709 new_code = reversed_comparison_code (op0, NULL);
10711 if (new_code != UNKNOWN)
10722 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10724 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10725 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10726 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10728 op0 = XEXP (op0, 1);
10729 code = (code == GE ? GT : LE);
10735 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10736 will be converted to a ZERO_EXTRACT later. */
10737 if (const_op == 0 && equality_comparison_p
10738 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10739 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10741 op0 = simplify_and_const_int
10742 (NULL_RTX, mode, gen_rtx_LSHIFTRT (mode,
10744 XEXP (XEXP (op0, 0), 1)),
10745 (HOST_WIDE_INT) 1);
10749 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10750 zero and X is a comparison and C1 and C2 describe only bits set
10751 in STORE_FLAG_VALUE, we can compare with X. */
10752 if (const_op == 0 && equality_comparison_p
10753 && mode_width <= HOST_BITS_PER_WIDE_INT
10754 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10755 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10756 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10757 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10758 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10760 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10761 << INTVAL (XEXP (XEXP (op0, 0), 1)));
10762 if ((~STORE_FLAG_VALUE & mask) == 0
10763 && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
10764 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10765 && COMPARISON_P (tem))))
10767 op0 = XEXP (XEXP (op0, 0), 0);
10772 /* If we are doing an equality comparison of an AND of a bit equal
10773 to the sign bit, replace this with a LT or GE comparison of
10774 the underlying value. */
10775 if (equality_comparison_p
10777 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10778 && mode_width <= HOST_BITS_PER_WIDE_INT
10779 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10780 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10782 op0 = XEXP (op0, 0);
10783 code = (code == EQ ? GE : LT);
10787 /* If this AND operation is really a ZERO_EXTEND from a narrower
10788 mode, the constant fits within that mode, and this is either an
10789 equality or unsigned comparison, try to do this comparison in
10794 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
10795 -> (ne:DI (reg:SI 4) (const_int 0))
10797 unless TRULY_NOOP_TRUNCATION allows it or the register is
10798 known to hold a value of the required mode the
10799 transformation is invalid. */
10800 if ((equality_comparison_p || unsigned_comparison_p)
10801 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10802 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10803 & GET_MODE_MASK (mode))
10805 && const_op >> i == 0
10806 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode
10807 && (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
10808 GET_MODE_BITSIZE (GET_MODE (op0)))
10809 || (REG_P (XEXP (op0, 0))
10810 && reg_truncated_to_mode (tmode, XEXP (op0, 0)))))
10812 op0 = gen_lowpart (tmode, XEXP (op0, 0));
10816 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
10817 fits in both M1 and M2 and the SUBREG is either paradoxical
10818 or represents the low part, permute the SUBREG and the AND
10820 if (GET_CODE (XEXP (op0, 0)) == SUBREG)
10822 unsigned HOST_WIDE_INT c1;
10823 tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
10824 /* Require an integral mode, to avoid creating something like
10826 if (SCALAR_INT_MODE_P (tmode)
10827 /* It is unsafe to commute the AND into the SUBREG if the
10828 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
10829 not defined. As originally written the upper bits
10830 have a defined value due to the AND operation.
10831 However, if we commute the AND inside the SUBREG then
10832 they no longer have defined values and the meaning of
10833 the code has been changed. */
10835 #ifdef WORD_REGISTER_OPERATIONS
10836 || (mode_width > GET_MODE_BITSIZE (tmode)
10837 && mode_width <= BITS_PER_WORD)
10839 || (mode_width <= GET_MODE_BITSIZE (tmode)
10840 && subreg_lowpart_p (XEXP (op0, 0))))
10841 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10842 && mode_width <= HOST_BITS_PER_WIDE_INT
10843 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
10844 && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
10845 && (c1 & ~GET_MODE_MASK (tmode)) == 0
10847 && c1 != GET_MODE_MASK (tmode))
10849 op0 = simplify_gen_binary (AND, tmode,
10850 SUBREG_REG (XEXP (op0, 0)),
10851 gen_int_mode (c1, tmode));
10852 op0 = gen_lowpart (mode, op0);
10857 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
10858 if (const_op == 0 && equality_comparison_p
10859 && XEXP (op0, 1) == const1_rtx
10860 && GET_CODE (XEXP (op0, 0)) == NOT)
10862 op0 = simplify_and_const_int
10863 (NULL_RTX, mode, XEXP (XEXP (op0, 0), 0), (HOST_WIDE_INT) 1);
10864 code = (code == NE ? EQ : NE);
10868 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10869 (eq (and (lshiftrt X) 1) 0).
10870 Also handle the case where (not X) is expressed using xor. */
10871 if (const_op == 0 && equality_comparison_p
10872 && XEXP (op0, 1) == const1_rtx
10873 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
10875 rtx shift_op = XEXP (XEXP (op0, 0), 0);
10876 rtx shift_count = XEXP (XEXP (op0, 0), 1);
10878 if (GET_CODE (shift_op) == NOT
10879 || (GET_CODE (shift_op) == XOR
10880 && GET_CODE (XEXP (shift_op, 1)) == CONST_INT
10881 && GET_CODE (shift_count) == CONST_INT
10882 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
10883 && (INTVAL (XEXP (shift_op, 1))
10884 == (HOST_WIDE_INT) 1 << INTVAL (shift_count))))
10886 op0 = simplify_and_const_int
10888 gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count),
10889 (HOST_WIDE_INT) 1);
10890 code = (code == NE ? EQ : NE);
10897 /* If we have (compare (ashift FOO N) (const_int C)) and
10898 the high order N bits of FOO (N+1 if an inequality comparison)
10899 are known to be zero, we can do this by comparing FOO with C
10900 shifted right N bits so long as the low-order N bits of C are
10902 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10903 && INTVAL (XEXP (op0, 1)) >= 0
10904 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10905 < HOST_BITS_PER_WIDE_INT)
10907 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10908 && mode_width <= HOST_BITS_PER_WIDE_INT
10909 && (nonzero_bits (XEXP (op0, 0), mode)
10910 & ~(mask >> (INTVAL (XEXP (op0, 1))
10911 + ! equality_comparison_p))) == 0)
10913 /* We must perform a logical shift, not an arithmetic one,
10914 as we want the top N bits of C to be zero. */
10915 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
10917 temp >>= INTVAL (XEXP (op0, 1));
10918 op1 = gen_int_mode (temp, mode);
10919 op0 = XEXP (op0, 0);
10923 /* If we are doing a sign bit comparison, it means we are testing
10924 a particular bit. Convert it to the appropriate AND. */
10925 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10926 && mode_width <= HOST_BITS_PER_WIDE_INT)
10928 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10931 - INTVAL (XEXP (op0, 1)))));
10932 code = (code == LT ? NE : EQ);
10936 /* If this an equality comparison with zero and we are shifting
10937 the low bit to the sign bit, we can convert this to an AND of the
10939 if (const_op == 0 && equality_comparison_p
10940 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10941 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10944 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10945 (HOST_WIDE_INT) 1);
10951 /* If this is an equality comparison with zero, we can do this
10952 as a logical shift, which might be much simpler. */
10953 if (equality_comparison_p && const_op == 0
10954 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10956 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10958 INTVAL (XEXP (op0, 1)));
10962 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10963 do the comparison in a narrower mode. */
10964 if (! unsigned_comparison_p
10965 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10966 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10967 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10968 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10969 MODE_INT, 1)) != BLKmode
10970 && (((unsigned HOST_WIDE_INT) const_op
10971 + (GET_MODE_MASK (tmode) >> 1) + 1)
10972 <= GET_MODE_MASK (tmode)))
10974 op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
10978 /* Likewise if OP0 is a PLUS of a sign extension with a
10979 constant, which is usually represented with the PLUS
10980 between the shifts. */
10981 if (! unsigned_comparison_p
10982 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10983 && GET_CODE (XEXP (op0, 0)) == PLUS
10984 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10985 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
10986 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
10987 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10988 MODE_INT, 1)) != BLKmode
10989 && (((unsigned HOST_WIDE_INT) const_op
10990 + (GET_MODE_MASK (tmode) >> 1) + 1)
10991 <= GET_MODE_MASK (tmode)))
10993 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
10994 rtx add_const = XEXP (XEXP (op0, 0), 1);
10995 rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
10996 add_const, XEXP (op0, 1));
10998 op0 = simplify_gen_binary (PLUS, tmode,
10999 gen_lowpart (tmode, inner),
11004 /* ... fall through ... */
11006 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11007 the low order N bits of FOO are known to be zero, we can do this
11008 by comparing FOO with C shifted left N bits so long as no
11009 overflow occurs. */
11010 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
11011 && INTVAL (XEXP (op0, 1)) >= 0
11012 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11013 && mode_width <= HOST_BITS_PER_WIDE_INT
11014 && (nonzero_bits (XEXP (op0, 0), mode)
11015 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
11016 && (((unsigned HOST_WIDE_INT) const_op
11017 + (GET_CODE (op0) != LSHIFTRT
11018 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
11021 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
11023 /* If the shift was logical, then we must make the condition
11025 if (GET_CODE (op0) == LSHIFTRT)
11026 code = unsigned_condition (code);
11028 const_op <<= INTVAL (XEXP (op0, 1));
11029 op1 = GEN_INT (const_op);
11030 op0 = XEXP (op0, 0);
11034 /* If we are using this shift to extract just the sign bit, we
11035 can replace this with an LT or GE comparison. */
11037 && (equality_comparison_p || sign_bit_comparison_p)
11038 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11039 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
11042 op0 = XEXP (op0, 0);
11043 code = (code == NE || code == GT ? LT : GE);
11055 /* Now make any compound operations involved in this comparison. Then,
11056 check for an outmost SUBREG on OP0 that is not doing anything or is
11057 paradoxical. The latter transformation must only be performed when
11058 it is known that the "extra" bits will be the same in op0 and op1 or
11059 that they don't matter. There are three cases to consider:
11061 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11062 care bits and we can assume they have any convenient value. So
11063 making the transformation is safe.
11065 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11066 In this case the upper bits of op0 are undefined. We should not make
11067 the simplification in that case as we do not know the contents of
11070 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11071 UNKNOWN. In that case we know those bits are zeros or ones. We must
11072 also be sure that they are the same as the upper bits of op1.
11074 We can never remove a SUBREG for a non-equality comparison because
11075 the sign bit is in a different place in the underlying object. */
11077 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
11078 op1 = make_compound_operation (op1, SET);
11080 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
11081 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11082 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
11083 && (code == NE || code == EQ))
11085 if (GET_MODE_SIZE (GET_MODE (op0))
11086 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
11088 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
11090 if (REG_P (SUBREG_REG (op0)))
11092 op0 = SUBREG_REG (op0);
11093 op1 = gen_lowpart (GET_MODE (op0), op1);
11096 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
11097 <= HOST_BITS_PER_WIDE_INT)
11098 && (nonzero_bits (SUBREG_REG (op0),
11099 GET_MODE (SUBREG_REG (op0)))
11100 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11102 tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
11104 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
11105 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11106 op0 = SUBREG_REG (op0), op1 = tem;
11110 /* We now do the opposite procedure: Some machines don't have compare
11111 insns in all modes. If OP0's mode is an integer mode smaller than a
11112 word and we can't do a compare in that mode, see if there is a larger
11113 mode for which we can do the compare. There are a number of cases in
11114 which we can use the wider mode. */
11116 mode = GET_MODE (op0);
11117 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11118 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
11119 && ! have_insn_for (COMPARE, mode))
11120 for (tmode = GET_MODE_WIDER_MODE (mode);
11122 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
11123 tmode = GET_MODE_WIDER_MODE (tmode))
11124 if (have_insn_for (COMPARE, tmode))
11128 /* If the only nonzero bits in OP0 and OP1 are those in the
11129 narrower mode and this is an equality or unsigned comparison,
11130 we can use the wider mode. Similarly for sign-extended
11131 values, in which case it is true for all comparisons. */
11132 zero_extended = ((code == EQ || code == NE
11133 || code == GEU || code == GTU
11134 || code == LEU || code == LTU)
11135 && (nonzero_bits (op0, tmode)
11136 & ~GET_MODE_MASK (mode)) == 0
11137 && ((GET_CODE (op1) == CONST_INT
11138 || (nonzero_bits (op1, tmode)
11139 & ~GET_MODE_MASK (mode)) == 0)));
11142 || ((num_sign_bit_copies (op0, tmode)
11143 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11144 - GET_MODE_BITSIZE (mode)))
11145 && (num_sign_bit_copies (op1, tmode)
11146 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11147 - GET_MODE_BITSIZE (mode)))))
11149 /* If OP0 is an AND and we don't have an AND in MODE either,
11150 make a new AND in the proper mode. */
11151 if (GET_CODE (op0) == AND
11152 && !have_insn_for (AND, mode))
11153 op0 = simplify_gen_binary (AND, tmode,
11154 gen_lowpart (tmode,
11156 gen_lowpart (tmode,
11159 op0 = gen_lowpart (tmode, op0);
11160 if (zero_extended && GET_CODE (op1) == CONST_INT)
11161 op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode));
11162 op1 = gen_lowpart (tmode, op1);
11166 /* If this is a test for negative, we can make an explicit
11167 test of the sign bit. */
11169 if (op1 == const0_rtx && (code == LT || code == GE)
11170 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11172 op0 = simplify_gen_binary (AND, tmode,
11173 gen_lowpart (tmode, op0),
11174 GEN_INT ((HOST_WIDE_INT) 1
11175 << (GET_MODE_BITSIZE (mode)
11177 code = (code == LT) ? NE : EQ;
11182 #ifdef CANONICALIZE_COMPARISON
11183 /* If this machine only supports a subset of valid comparisons, see if we
11184 can convert an unsupported one into a supported one. */
11185 CANONICALIZE_COMPARISON (code, op0, op1);
11194 /* Utility function for record_value_for_reg. Count number of
11199 enum rtx_code code = GET_CODE (x);
11203 if (GET_RTX_CLASS (code) == '2'
11204 || GET_RTX_CLASS (code) == 'c')
11206 rtx x0 = XEXP (x, 0);
11207 rtx x1 = XEXP (x, 1);
11210 return 1 + 2 * count_rtxs (x0);
11212 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
11213 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
11214 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11215 return 2 + 2 * count_rtxs (x0)
11216 + count_rtxs (x == XEXP (x1, 0)
11217 ? XEXP (x1, 1) : XEXP (x1, 0));
11219 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
11220 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
11221 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11222 return 2 + 2 * count_rtxs (x1)
11223 + count_rtxs (x == XEXP (x0, 0)
11224 ? XEXP (x0, 1) : XEXP (x0, 0));
11227 fmt = GET_RTX_FORMAT (code);
11228 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11230 ret += count_rtxs (XEXP (x, i));
11231 else if (fmt[i] == 'E')
11232 for (j = 0; j < XVECLEN (x, i); j++)
11233 ret += count_rtxs (XVECEXP (x, i, j));
11238 /* Utility function for following routine. Called when X is part of a value
11239 being stored into last_set_value. Sets last_set_table_tick
11240 for each register mentioned. Similar to mention_regs in cse.c */
11243 update_table_tick (rtx x)
11245 enum rtx_code code = GET_CODE (x);
11246 const char *fmt = GET_RTX_FORMAT (code);
11251 unsigned int regno = REGNO (x);
11252 unsigned int endregno = END_REGNO (x);
11255 for (r = regno; r < endregno; r++)
11257 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, r);
11258 rsp->last_set_table_tick = label_tick;
11264 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11267 /* Check for identical subexpressions. If x contains
11268 identical subexpression we only have to traverse one of
11270 if (i == 0 && ARITHMETIC_P (x))
11272 /* Note that at this point x1 has already been
11274 rtx x0 = XEXP (x, 0);
11275 rtx x1 = XEXP (x, 1);
11277 /* If x0 and x1 are identical then there is no need to
11282 /* If x0 is identical to a subexpression of x1 then while
11283 processing x1, x0 has already been processed. Thus we
11284 are done with x. */
11285 if (ARITHMETIC_P (x1)
11286 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11289 /* If x1 is identical to a subexpression of x0 then we
11290 still have to process the rest of x0. */
11291 if (ARITHMETIC_P (x0)
11292 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11294 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
11299 update_table_tick (XEXP (x, i));
11301 else if (fmt[i] == 'E')
11302 for (j = 0; j < XVECLEN (x, i); j++)
11303 update_table_tick (XVECEXP (x, i, j));
11306 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11307 are saying that the register is clobbered and we no longer know its
11308 value. If INSN is zero, don't update reg_stat[].last_set; this is
11309 only permitted with VALUE also zero and is used to invalidate the
11313 record_value_for_reg (rtx reg, rtx insn, rtx value)
11315 unsigned int regno = REGNO (reg);
11316 unsigned int endregno = END_REGNO (reg);
11318 reg_stat_type *rsp;
11320 /* If VALUE contains REG and we have a previous value for REG, substitute
11321 the previous value. */
11322 if (value && insn && reg_overlap_mentioned_p (reg, value))
11326 /* Set things up so get_last_value is allowed to see anything set up to
11328 subst_low_luid = DF_INSN_LUID (insn);
11329 tem = get_last_value (reg);
11331 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11332 it isn't going to be useful and will take a lot of time to process,
11333 so just use the CLOBBER. */
11337 if (ARITHMETIC_P (tem)
11338 && GET_CODE (XEXP (tem, 0)) == CLOBBER
11339 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
11340 tem = XEXP (tem, 0);
11341 else if (count_occurrences (value, reg, 1) >= 2)
11343 /* If there are two or more occurrences of REG in VALUE,
11344 prevent the value from growing too much. */
11345 if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
11346 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
11349 value = replace_rtx (copy_rtx (value), reg, tem);
11353 /* For each register modified, show we don't know its value, that
11354 we don't know about its bitwise content, that its value has been
11355 updated, and that we don't know the location of the death of the
11357 for (i = regno; i < endregno; i++)
11359 rsp = VEC_index (reg_stat_type, reg_stat, i);
11362 rsp->last_set = insn;
11364 rsp->last_set_value = 0;
11365 rsp->last_set_mode = VOIDmode;
11366 rsp->last_set_nonzero_bits = 0;
11367 rsp->last_set_sign_bit_copies = 0;
11368 rsp->last_death = 0;
11369 rsp->truncated_to_mode = VOIDmode;
11372 /* Mark registers that are being referenced in this value. */
11374 update_table_tick (value);
11376 /* Now update the status of each register being set.
11377 If someone is using this register in this block, set this register
11378 to invalid since we will get confused between the two lives in this
11379 basic block. This makes using this register always invalid. In cse, we
11380 scan the table to invalidate all entries using this register, but this
11381 is too much work for us. */
11383 for (i = regno; i < endregno; i++)
11385 rsp = VEC_index (reg_stat_type, reg_stat, i);
11386 rsp->last_set_label = label_tick;
11388 || (value && rsp->last_set_table_tick >= label_tick_ebb_start))
11389 rsp->last_set_invalid = 1;
11391 rsp->last_set_invalid = 0;
11394 /* The value being assigned might refer to X (like in "x++;"). In that
11395 case, we must replace it with (clobber (const_int 0)) to prevent
11397 rsp = VEC_index (reg_stat_type, reg_stat, regno);
11398 if (value && ! get_last_value_validate (&value, insn,
11399 rsp->last_set_label, 0))
11401 value = copy_rtx (value);
11402 if (! get_last_value_validate (&value, insn,
11403 rsp->last_set_label, 1))
11407 /* For the main register being modified, update the value, the mode, the
11408 nonzero bits, and the number of sign bit copies. */
11410 rsp->last_set_value = value;
11414 enum machine_mode mode = GET_MODE (reg);
11415 subst_low_luid = DF_INSN_LUID (insn);
11416 rsp->last_set_mode = mode;
11417 if (GET_MODE_CLASS (mode) == MODE_INT
11418 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11419 mode = nonzero_bits_mode;
11420 rsp->last_set_nonzero_bits = nonzero_bits (value, mode);
11421 rsp->last_set_sign_bit_copies
11422 = num_sign_bit_copies (value, GET_MODE (reg));
11426 /* Called via note_stores from record_dead_and_set_regs to handle one
11427 SET or CLOBBER in an insn. DATA is the instruction in which the
11428 set is occurring. */
11431 record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data)
11433 rtx record_dead_insn = (rtx) data;
11435 if (GET_CODE (dest) == SUBREG)
11436 dest = SUBREG_REG (dest);
11438 if (!record_dead_insn)
11441 record_value_for_reg (dest, NULL_RTX, NULL_RTX);
11447 /* If we are setting the whole register, we know its value. Otherwise
11448 show that we don't know the value. We can handle SUBREG in
11450 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
11451 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
11452 else if (GET_CODE (setter) == SET
11453 && GET_CODE (SET_DEST (setter)) == SUBREG
11454 && SUBREG_REG (SET_DEST (setter)) == dest
11455 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
11456 && subreg_lowpart_p (SET_DEST (setter)))
11457 record_value_for_reg (dest, record_dead_insn,
11458 gen_lowpart (GET_MODE (dest),
11459 SET_SRC (setter)));
11461 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
11463 else if (MEM_P (dest)
11464 /* Ignore pushes, they clobber nothing. */
11465 && ! push_operand (dest, GET_MODE (dest)))
11466 mem_last_set = DF_INSN_LUID (record_dead_insn);
11469 /* Update the records of when each REG was most recently set or killed
11470 for the things done by INSN. This is the last thing done in processing
11471 INSN in the combiner loop.
11473 We update reg_stat[], in particular fields last_set, last_set_value,
11474 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
11475 last_death, and also the similar information mem_last_set (which insn
11476 most recently modified memory) and last_call_luid (which insn was the
11477 most recent subroutine call). */
11480 record_dead_and_set_regs (rtx insn)
11485 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11487 if (REG_NOTE_KIND (link) == REG_DEAD
11488 && REG_P (XEXP (link, 0)))
11490 unsigned int regno = REGNO (XEXP (link, 0));
11491 unsigned int endregno = END_REGNO (XEXP (link, 0));
11493 for (i = regno; i < endregno; i++)
11495 reg_stat_type *rsp;
11497 rsp = VEC_index (reg_stat_type, reg_stat, i);
11498 rsp->last_death = insn;
11501 else if (REG_NOTE_KIND (link) == REG_INC)
11502 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11507 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11508 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
11510 reg_stat_type *rsp;
11512 rsp = VEC_index (reg_stat_type, reg_stat, i);
11513 rsp->last_set_invalid = 1;
11514 rsp->last_set = insn;
11515 rsp->last_set_value = 0;
11516 rsp->last_set_mode = VOIDmode;
11517 rsp->last_set_nonzero_bits = 0;
11518 rsp->last_set_sign_bit_copies = 0;
11519 rsp->last_death = 0;
11520 rsp->truncated_to_mode = VOIDmode;
11523 last_call_luid = mem_last_set = DF_INSN_LUID (insn);
11525 /* We can't combine into a call pattern. Remember, though, that
11526 the return value register is set at this LUID. We could
11527 still replace a register with the return value from the
11528 wrong subroutine call! */
11529 note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX);
11532 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11535 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11536 register present in the SUBREG, so for each such SUBREG go back and
11537 adjust nonzero and sign bit information of the registers that are
11538 known to have some zero/sign bits set.
11540 This is needed because when combine blows the SUBREGs away, the
11541 information on zero/sign bits is lost and further combines can be
11542 missed because of that. */
11545 record_promoted_value (rtx insn, rtx subreg)
11548 unsigned int regno = REGNO (SUBREG_REG (subreg));
11549 enum machine_mode mode = GET_MODE (subreg);
11551 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11554 for (links = LOG_LINKS (insn); links;)
11556 reg_stat_type *rsp;
11558 insn = XEXP (links, 0);
11559 set = single_set (insn);
11561 if (! set || !REG_P (SET_DEST (set))
11562 || REGNO (SET_DEST (set)) != regno
11563 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11565 links = XEXP (links, 1);
11569 rsp = VEC_index (reg_stat_type, reg_stat, regno);
11570 if (rsp->last_set == insn)
11572 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
11573 rsp->last_set_nonzero_bits &= GET_MODE_MASK (mode);
11576 if (REG_P (SET_SRC (set)))
11578 regno = REGNO (SET_SRC (set));
11579 links = LOG_LINKS (insn);
11586 /* Check if X, a register, is known to contain a value already
11587 truncated to MODE. In this case we can use a subreg to refer to
11588 the truncated value even though in the generic case we would need
11589 an explicit truncation. */
11592 reg_truncated_to_mode (enum machine_mode mode, const_rtx x)
11594 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
11595 enum machine_mode truncated = rsp->truncated_to_mode;
11598 || rsp->truncation_label < label_tick_ebb_start)
11600 if (GET_MODE_SIZE (truncated) <= GET_MODE_SIZE (mode))
11602 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
11603 GET_MODE_BITSIZE (truncated)))
11608 /* Callback for for_each_rtx. If *P is a hard reg or a subreg record the mode
11609 that the register is accessed in. For non-TRULY_NOOP_TRUNCATION targets we
11610 might be able to turn a truncate into a subreg using this information.
11611 Return -1 if traversing *P is complete or 0 otherwise. */
11614 record_truncated_value (rtx *p, void *data ATTRIBUTE_UNUSED)
11617 enum machine_mode truncated_mode;
11618 reg_stat_type *rsp;
11620 if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
11622 enum machine_mode original_mode = GET_MODE (SUBREG_REG (x));
11623 truncated_mode = GET_MODE (x);
11625 if (GET_MODE_SIZE (original_mode) <= GET_MODE_SIZE (truncated_mode))
11628 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (truncated_mode),
11629 GET_MODE_BITSIZE (original_mode)))
11632 x = SUBREG_REG (x);
11634 /* ??? For hard-regs we now record everything. We might be able to
11635 optimize this using last_set_mode. */
11636 else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
11637 truncated_mode = GET_MODE (x);
11641 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
11642 if (rsp->truncated_to_mode == 0
11643 || rsp->truncation_label < label_tick_ebb_start
11644 || (GET_MODE_SIZE (truncated_mode)
11645 < GET_MODE_SIZE (rsp->truncated_to_mode)))
11647 rsp->truncated_to_mode = truncated_mode;
11648 rsp->truncation_label = label_tick;
11654 /* Callback for note_uses. Find hardregs and subregs of pseudos and
11655 the modes they are used in. This can help truning TRUNCATEs into
11659 record_truncated_values (rtx *x, void *data ATTRIBUTE_UNUSED)
11661 for_each_rtx (x, record_truncated_value, NULL);
11664 /* Scan X for promoted SUBREGs. For each one found,
11665 note what it implies to the registers used in it. */
11668 check_promoted_subreg (rtx insn, rtx x)
11670 if (GET_CODE (x) == SUBREG
11671 && SUBREG_PROMOTED_VAR_P (x)
11672 && REG_P (SUBREG_REG (x)))
11673 record_promoted_value (insn, x);
11676 const char *format = GET_RTX_FORMAT (GET_CODE (x));
11679 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11683 check_promoted_subreg (insn, XEXP (x, i));
11687 if (XVEC (x, i) != 0)
11688 for (j = 0; j < XVECLEN (x, i); j++)
11689 check_promoted_subreg (insn, XVECEXP (x, i, j));
11695 /* Utility routine for the following function. Verify that all the registers
11696 mentioned in *LOC are valid when *LOC was part of a value set when
11697 label_tick == TICK. Return 0 if some are not.
11699 If REPLACE is nonzero, replace the invalid reference with
11700 (clobber (const_int 0)) and return 1. This replacement is useful because
11701 we often can get useful information about the form of a value (e.g., if
11702 it was produced by a shift that always produces -1 or 0) even though
11703 we don't know exactly what registers it was produced from. */
11706 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
11709 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11710 int len = GET_RTX_LENGTH (GET_CODE (x));
11715 unsigned int regno = REGNO (x);
11716 unsigned int endregno = END_REGNO (x);
11719 for (j = regno; j < endregno; j++)
11721 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, j);
11722 if (rsp->last_set_invalid
11723 /* If this is a pseudo-register that was only set once and not
11724 live at the beginning of the function, it is always valid. */
11725 || (! (regno >= FIRST_PSEUDO_REGISTER
11726 && REG_N_SETS (regno) == 1
11727 && (!REGNO_REG_SET_P
11728 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno)))
11729 && rsp->last_set_label > tick))
11732 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11739 /* If this is a memory reference, make sure that there were
11740 no stores after it that might have clobbered the value. We don't
11741 have alias info, so we assume any store invalidates it. */
11742 else if (MEM_P (x) && !MEM_READONLY_P (x)
11743 && DF_INSN_LUID (insn) <= mem_last_set)
11746 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11750 for (i = 0; i < len; i++)
11754 /* Check for identical subexpressions. If x contains
11755 identical subexpression we only have to traverse one of
11757 if (i == 1 && ARITHMETIC_P (x))
11759 /* Note that at this point x0 has already been checked
11760 and found valid. */
11761 rtx x0 = XEXP (x, 0);
11762 rtx x1 = XEXP (x, 1);
11764 /* If x0 and x1 are identical then x is also valid. */
11768 /* If x1 is identical to a subexpression of x0 then
11769 while checking x0, x1 has already been checked. Thus
11770 it is valid and so as x. */
11771 if (ARITHMETIC_P (x0)
11772 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11775 /* If x0 is identical to a subexpression of x1 then x is
11776 valid iff the rest of x1 is valid. */
11777 if (ARITHMETIC_P (x1)
11778 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11780 get_last_value_validate (&XEXP (x1,
11781 x0 == XEXP (x1, 0) ? 1 : 0),
11782 insn, tick, replace);
11785 if (get_last_value_validate (&XEXP (x, i), insn, tick,
11789 else if (fmt[i] == 'E')
11790 for (j = 0; j < XVECLEN (x, i); j++)
11791 if (get_last_value_validate (&XVECEXP (x, i, j),
11792 insn, tick, replace) == 0)
11796 /* If we haven't found a reason for it to be invalid, it is valid. */
11800 /* Get the last value assigned to X, if known. Some registers
11801 in the value may be replaced with (clobber (const_int 0)) if their value
11802 is known longer known reliably. */
11805 get_last_value (const_rtx x)
11807 unsigned int regno;
11809 reg_stat_type *rsp;
11811 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11812 then convert it to the desired mode. If this is a paradoxical SUBREG,
11813 we cannot predict what values the "extra" bits might have. */
11814 if (GET_CODE (x) == SUBREG
11815 && subreg_lowpart_p (x)
11816 && (GET_MODE_SIZE (GET_MODE (x))
11817 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11818 && (value = get_last_value (SUBREG_REG (x))) != 0)
11819 return gen_lowpart (GET_MODE (x), value);
11825 rsp = VEC_index (reg_stat_type, reg_stat, regno);
11826 value = rsp->last_set_value;
11828 /* If we don't have a value, or if it isn't for this basic block and
11829 it's either a hard register, set more than once, or it's a live
11830 at the beginning of the function, return 0.
11832 Because if it's not live at the beginning of the function then the reg
11833 is always set before being used (is never used without being set).
11834 And, if it's set only once, and it's always set before use, then all
11835 uses must have the same last value, even if it's not from this basic
11839 || (rsp->last_set_label < label_tick_ebb_start
11840 && (regno < FIRST_PSEUDO_REGISTER
11841 || REG_N_SETS (regno) != 1
11843 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno))))
11846 /* If the value was set in a later insn than the ones we are processing,
11847 we can't use it even if the register was only set once. */
11848 if (rsp->last_set_label == label_tick
11849 && DF_INSN_LUID (rsp->last_set) >= subst_low_luid)
11852 /* If the value has all its registers valid, return it. */
11853 if (get_last_value_validate (&value, rsp->last_set,
11854 rsp->last_set_label, 0))
11857 /* Otherwise, make a copy and replace any invalid register with
11858 (clobber (const_int 0)). If that fails for some reason, return 0. */
11860 value = copy_rtx (value);
11861 if (get_last_value_validate (&value, rsp->last_set,
11862 rsp->last_set_label, 1))
11868 /* Return nonzero if expression X refers to a REG or to memory
11869 that is set in an instruction more recent than FROM_LUID. */
11872 use_crosses_set_p (const_rtx x, int from_luid)
11876 enum rtx_code code = GET_CODE (x);
11880 unsigned int regno = REGNO (x);
11881 unsigned endreg = END_REGNO (x);
11883 #ifdef PUSH_ROUNDING
11884 /* Don't allow uses of the stack pointer to be moved,
11885 because we don't know whether the move crosses a push insn. */
11886 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11889 for (; regno < endreg; regno++)
11891 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
11893 && rsp->last_set_label == label_tick
11894 && DF_INSN_LUID (rsp->last_set) > from_luid)
11900 if (code == MEM && mem_last_set > from_luid)
11903 fmt = GET_RTX_FORMAT (code);
11905 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11910 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11911 if (use_crosses_set_p (XVECEXP (x, i, j), from_luid))
11914 else if (fmt[i] == 'e'
11915 && use_crosses_set_p (XEXP (x, i), from_luid))
11921 /* Define three variables used for communication between the following
11924 static unsigned int reg_dead_regno, reg_dead_endregno;
11925 static int reg_dead_flag;
11927 /* Function called via note_stores from reg_dead_at_p.
11929 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11930 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11933 reg_dead_at_p_1 (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
11935 unsigned int regno, endregno;
11940 regno = REGNO (dest);
11941 endregno = END_REGNO (dest);
11942 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11943 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11946 /* Return nonzero if REG is known to be dead at INSN.
11948 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11949 referencing REG, it is dead. If we hit a SET referencing REG, it is
11950 live. Otherwise, see if it is live or dead at the start of the basic
11951 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11952 must be assumed to be always live. */
11955 reg_dead_at_p (rtx reg, rtx insn)
11960 /* Set variables for reg_dead_at_p_1. */
11961 reg_dead_regno = REGNO (reg);
11962 reg_dead_endregno = END_REGNO (reg);
11966 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
11967 we allow the machine description to decide whether use-and-clobber
11968 patterns are OK. */
11969 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11971 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11972 if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
11976 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
11977 beginning of basic block. */
11978 block = BLOCK_FOR_INSN (insn);
11983 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
11985 return reg_dead_flag == 1 ? 1 : 0;
11987 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11991 if (insn == BB_HEAD (block))
11994 insn = PREV_INSN (insn);
11997 /* Look at live-in sets for the basic block that we were in. */
11998 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11999 if (REGNO_REG_SET_P (df_get_live_in (block), i))
12005 /* Note hard registers in X that are used. */
12008 mark_used_regs_combine (rtx x)
12010 RTX_CODE code = GET_CODE (x);
12011 unsigned int regno;
12024 case ADDR_DIFF_VEC:
12027 /* CC0 must die in the insn after it is set, so we don't need to take
12028 special note of it here. */
12034 /* If we are clobbering a MEM, mark any hard registers inside the
12035 address as used. */
12036 if (MEM_P (XEXP (x, 0)))
12037 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
12042 /* A hard reg in a wide mode may really be multiple registers.
12043 If so, mark all of them just like the first. */
12044 if (regno < FIRST_PSEUDO_REGISTER)
12046 /* None of this applies to the stack, frame or arg pointers. */
12047 if (regno == STACK_POINTER_REGNUM
12048 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
12049 || regno == HARD_FRAME_POINTER_REGNUM
12051 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12052 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
12054 || regno == FRAME_POINTER_REGNUM)
12057 add_to_hard_reg_set (&newpat_used_regs, GET_MODE (x), regno);
12063 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12065 rtx testreg = SET_DEST (x);
12067 while (GET_CODE (testreg) == SUBREG
12068 || GET_CODE (testreg) == ZERO_EXTRACT
12069 || GET_CODE (testreg) == STRICT_LOW_PART)
12070 testreg = XEXP (testreg, 0);
12072 if (MEM_P (testreg))
12073 mark_used_regs_combine (XEXP (testreg, 0));
12075 mark_used_regs_combine (SET_SRC (x));
12083 /* Recursively scan the operands of this expression. */
12086 const char *fmt = GET_RTX_FORMAT (code);
12088 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12091 mark_used_regs_combine (XEXP (x, i));
12092 else if (fmt[i] == 'E')
12096 for (j = 0; j < XVECLEN (x, i); j++)
12097 mark_used_regs_combine (XVECEXP (x, i, j));
12103 /* Remove register number REGNO from the dead registers list of INSN.
12105 Return the note used to record the death, if there was one. */
12108 remove_death (unsigned int regno, rtx insn)
12110 rtx note = find_regno_note (insn, REG_DEAD, regno);
12113 remove_note (insn, note);
12118 /* For each register (hardware or pseudo) used within expression X, if its
12119 death is in an instruction with luid between FROM_LUID (inclusive) and
12120 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12121 list headed by PNOTES.
12123 That said, don't move registers killed by maybe_kill_insn.
12125 This is done when X is being merged by combination into TO_INSN. These
12126 notes will then be distributed as needed. */
12129 move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx to_insn,
12134 enum rtx_code code = GET_CODE (x);
12138 unsigned int regno = REGNO (x);
12139 rtx where_dead = VEC_index (reg_stat_type, reg_stat, regno)->last_death;
12141 /* Don't move the register if it gets killed in between from and to. */
12142 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
12143 && ! reg_referenced_p (x, maybe_kill_insn))
12147 && DF_INSN_LUID (where_dead) >= from_luid
12148 && DF_INSN_LUID (where_dead) < DF_INSN_LUID (to_insn))
12150 rtx note = remove_death (regno, where_dead);
12152 /* It is possible for the call above to return 0. This can occur
12153 when last_death points to I2 or I1 that we combined with.
12154 In that case make a new note.
12156 We must also check for the case where X is a hard register
12157 and NOTE is a death note for a range of hard registers
12158 including X. In that case, we must put REG_DEAD notes for
12159 the remaining registers in place of NOTE. */
12161 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
12162 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12163 > GET_MODE_SIZE (GET_MODE (x))))
12165 unsigned int deadregno = REGNO (XEXP (note, 0));
12166 unsigned int deadend = END_HARD_REGNO (XEXP (note, 0));
12167 unsigned int ourend = END_HARD_REGNO (x);
12170 for (i = deadregno; i < deadend; i++)
12171 if (i < regno || i >= ourend)
12172 add_reg_note (where_dead, REG_DEAD, regno_reg_rtx[i]);
12175 /* If we didn't find any note, or if we found a REG_DEAD note that
12176 covers only part of the given reg, and we have a multi-reg hard
12177 register, then to be safe we must check for REG_DEAD notes
12178 for each register other than the first. They could have
12179 their own REG_DEAD notes lying around. */
12180 else if ((note == 0
12182 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12183 < GET_MODE_SIZE (GET_MODE (x)))))
12184 && regno < FIRST_PSEUDO_REGISTER
12185 && hard_regno_nregs[regno][GET_MODE (x)] > 1)
12187 unsigned int ourend = END_HARD_REGNO (x);
12188 unsigned int i, offset;
12192 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
12196 for (i = regno + offset; i < ourend; i++)
12197 move_deaths (regno_reg_rtx[i],
12198 maybe_kill_insn, from_luid, to_insn, &oldnotes);
12201 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
12203 XEXP (note, 1) = *pnotes;
12207 *pnotes = alloc_reg_note (REG_DEAD, x, *pnotes);
12213 else if (GET_CODE (x) == SET)
12215 rtx dest = SET_DEST (x);
12217 move_deaths (SET_SRC (x), maybe_kill_insn, from_luid, to_insn, pnotes);
12219 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12220 that accesses one word of a multi-word item, some
12221 piece of everything register in the expression is used by
12222 this insn, so remove any old death. */
12223 /* ??? So why do we test for equality of the sizes? */
12225 if (GET_CODE (dest) == ZERO_EXTRACT
12226 || GET_CODE (dest) == STRICT_LOW_PART
12227 || (GET_CODE (dest) == SUBREG
12228 && (((GET_MODE_SIZE (GET_MODE (dest))
12229 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
12230 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
12231 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
12233 move_deaths (dest, maybe_kill_insn, from_luid, to_insn, pnotes);
12237 /* If this is some other SUBREG, we know it replaces the entire
12238 value, so use that as the destination. */
12239 if (GET_CODE (dest) == SUBREG)
12240 dest = SUBREG_REG (dest);
12242 /* If this is a MEM, adjust deaths of anything used in the address.
12243 For a REG (the only other possibility), the entire value is
12244 being replaced so the old value is not used in this insn. */
12247 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_luid,
12252 else if (GET_CODE (x) == CLOBBER)
12255 len = GET_RTX_LENGTH (code);
12256 fmt = GET_RTX_FORMAT (code);
12258 for (i = 0; i < len; i++)
12263 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12264 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_luid,
12267 else if (fmt[i] == 'e')
12268 move_deaths (XEXP (x, i), maybe_kill_insn, from_luid, to_insn, pnotes);
12272 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12273 pattern of an insn. X must be a REG. */
12276 reg_bitfield_target_p (rtx x, rtx body)
12280 if (GET_CODE (body) == SET)
12282 rtx dest = SET_DEST (body);
12284 unsigned int regno, tregno, endregno, endtregno;
12286 if (GET_CODE (dest) == ZERO_EXTRACT)
12287 target = XEXP (dest, 0);
12288 else if (GET_CODE (dest) == STRICT_LOW_PART)
12289 target = SUBREG_REG (XEXP (dest, 0));
12293 if (GET_CODE (target) == SUBREG)
12294 target = SUBREG_REG (target);
12296 if (!REG_P (target))
12299 tregno = REGNO (target), regno = REGNO (x);
12300 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
12301 return target == x;
12303 endtregno = end_hard_regno (GET_MODE (target), tregno);
12304 endregno = end_hard_regno (GET_MODE (x), regno);
12306 return endregno > tregno && regno < endtregno;
12309 else if (GET_CODE (body) == PARALLEL)
12310 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
12311 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
12317 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12318 as appropriate. I3 and I2 are the insns resulting from the combination
12319 insns including FROM (I2 may be zero).
12321 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
12322 not need REG_DEAD notes because they are being substituted for. This
12323 saves searching in the most common cases.
12325 Each note in the list is either ignored or placed on some insns, depending
12326 on the type of note. */
12329 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2,
12332 rtx note, next_note;
12335 for (note = notes; note; note = next_note)
12337 rtx place = 0, place2 = 0;
12339 next_note = XEXP (note, 1);
12340 switch (REG_NOTE_KIND (note))
12344 /* Doesn't matter much where we put this, as long as it's somewhere.
12345 It is preferable to keep these notes on branches, which is most
12346 likely to be i3. */
12350 case REG_VALUE_PROFILE:
12351 /* Just get rid of this note, as it is unused later anyway. */
12354 case REG_NON_LOCAL_GOTO:
12359 gcc_assert (i2 && JUMP_P (i2));
12364 case REG_EH_REGION:
12365 /* These notes must remain with the call or trapping instruction. */
12368 else if (i2 && CALL_P (i2))
12372 gcc_assert (flag_non_call_exceptions);
12373 if (may_trap_p (i3))
12375 else if (i2 && may_trap_p (i2))
12377 /* ??? Otherwise assume we've combined things such that we
12378 can now prove that the instructions can't trap. Drop the
12379 note in this case. */
12385 /* These notes must remain with the call. It should not be
12386 possible for both I2 and I3 to be a call. */
12391 gcc_assert (i2 && CALL_P (i2));
12397 /* Any clobbers for i3 may still exist, and so we must process
12398 REG_UNUSED notes from that insn.
12400 Any clobbers from i2 or i1 can only exist if they were added by
12401 recog_for_combine. In that case, recog_for_combine created the
12402 necessary REG_UNUSED notes. Trying to keep any original
12403 REG_UNUSED notes from these insns can cause incorrect output
12404 if it is for the same register as the original i3 dest.
12405 In that case, we will notice that the register is set in i3,
12406 and then add a REG_UNUSED note for the destination of i3, which
12407 is wrong. However, it is possible to have REG_UNUSED notes from
12408 i2 or i1 for register which were both used and clobbered, so
12409 we keep notes from i2 or i1 if they will turn into REG_DEAD
12412 /* If this register is set or clobbered in I3, put the note there
12413 unless there is one already. */
12414 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
12416 if (from_insn != i3)
12419 if (! (REG_P (XEXP (note, 0))
12420 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
12421 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
12424 /* Otherwise, if this register is used by I3, then this register
12425 now dies here, so we must put a REG_DEAD note here unless there
12427 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
12428 && ! (REG_P (XEXP (note, 0))
12429 ? find_regno_note (i3, REG_DEAD,
12430 REGNO (XEXP (note, 0)))
12431 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
12433 PUT_REG_NOTE_KIND (note, REG_DEAD);
12441 /* These notes say something about results of an insn. We can
12442 only support them if they used to be on I3 in which case they
12443 remain on I3. Otherwise they are ignored.
12445 If the note refers to an expression that is not a constant, we
12446 must also ignore the note since we cannot tell whether the
12447 equivalence is still true. It might be possible to do
12448 slightly better than this (we only have a problem if I2DEST
12449 or I1DEST is present in the expression), but it doesn't
12450 seem worth the trouble. */
12452 if (from_insn == i3
12453 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
12458 /* These notes say something about how a register is used. They must
12459 be present on any use of the register in I2 or I3. */
12460 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
12463 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
12472 case REG_LABEL_TARGET:
12473 case REG_LABEL_OPERAND:
12474 /* This can show up in several ways -- either directly in the
12475 pattern, or hidden off in the constant pool with (or without?)
12476 a REG_EQUAL note. */
12477 /* ??? Ignore the without-reg_equal-note problem for now. */
12478 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
12479 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
12480 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12481 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
12485 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
12486 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
12487 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12488 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12496 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
12497 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
12499 if (place && JUMP_P (place)
12500 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
12501 && (JUMP_LABEL (place) == NULL
12502 || JUMP_LABEL (place) == XEXP (note, 0)))
12504 rtx label = JUMP_LABEL (place);
12507 JUMP_LABEL (place) = XEXP (note, 0);
12508 else if (LABEL_P (label))
12509 LABEL_NUSES (label)--;
12512 if (place2 && JUMP_P (place2)
12513 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
12514 && (JUMP_LABEL (place2) == NULL
12515 || JUMP_LABEL (place2) == XEXP (note, 0)))
12517 rtx label = JUMP_LABEL (place2);
12520 JUMP_LABEL (place2) = XEXP (note, 0);
12521 else if (LABEL_P (label))
12522 LABEL_NUSES (label)--;
12528 /* This note says something about the value of a register prior
12529 to the execution of an insn. It is too much trouble to see
12530 if the note is still correct in all situations. It is better
12531 to simply delete it. */
12535 /* If we replaced the right hand side of FROM_INSN with a
12536 REG_EQUAL note, the original use of the dying register
12537 will not have been combined into I3 and I2. In such cases,
12538 FROM_INSN is guaranteed to be the first of the combined
12539 instructions, so we simply need to search back before
12540 FROM_INSN for the previous use or set of this register,
12541 then alter the notes there appropriately.
12543 If the register is used as an input in I3, it dies there.
12544 Similarly for I2, if it is nonzero and adjacent to I3.
12546 If the register is not used as an input in either I3 or I2
12547 and it is not one of the registers we were supposed to eliminate,
12548 there are two possibilities. We might have a non-adjacent I2
12549 or we might have somehow eliminated an additional register
12550 from a computation. For example, we might have had A & B where
12551 we discover that B will always be zero. In this case we will
12552 eliminate the reference to A.
12554 In both cases, we must search to see if we can find a previous
12555 use of A and put the death note there. */
12558 && from_insn == i2mod
12559 && !reg_overlap_mentioned_p (XEXP (note, 0), i2mod_new_rhs))
12564 && CALL_P (from_insn)
12565 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12567 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12569 else if (i2 != 0 && next_nonnote_insn (i2) == i3
12570 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12572 else if ((rtx_equal_p (XEXP (note, 0), elim_i2)
12574 && reg_overlap_mentioned_p (XEXP (note, 0),
12576 || rtx_equal_p (XEXP (note, 0), elim_i1))
12583 basic_block bb = this_basic_block;
12585 for (tem = PREV_INSN (tem); place == 0; tem = PREV_INSN (tem))
12587 if (! INSN_P (tem))
12589 if (tem == BB_HEAD (bb))
12594 /* If the register is being set at TEM, see if that is all
12595 TEM is doing. If so, delete TEM. Otherwise, make this
12596 into a REG_UNUSED note instead. Don't delete sets to
12597 global register vars. */
12598 if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
12599 || !global_regs[REGNO (XEXP (note, 0))])
12600 && reg_set_p (XEXP (note, 0), PATTERN (tem)))
12602 rtx set = single_set (tem);
12603 rtx inner_dest = 0;
12605 rtx cc0_setter = NULL_RTX;
12609 for (inner_dest = SET_DEST (set);
12610 (GET_CODE (inner_dest) == STRICT_LOW_PART
12611 || GET_CODE (inner_dest) == SUBREG
12612 || GET_CODE (inner_dest) == ZERO_EXTRACT);
12613 inner_dest = XEXP (inner_dest, 0))
12616 /* Verify that it was the set, and not a clobber that
12617 modified the register.
12619 CC0 targets must be careful to maintain setter/user
12620 pairs. If we cannot delete the setter due to side
12621 effects, mark the user with an UNUSED note instead
12624 if (set != 0 && ! side_effects_p (SET_SRC (set))
12625 && rtx_equal_p (XEXP (note, 0), inner_dest)
12627 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12628 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12629 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12633 /* Move the notes and links of TEM elsewhere.
12634 This might delete other dead insns recursively.
12635 First set the pattern to something that won't use
12637 rtx old_notes = REG_NOTES (tem);
12639 PATTERN (tem) = pc_rtx;
12640 REG_NOTES (tem) = NULL;
12642 distribute_notes (old_notes, tem, tem, NULL_RTX,
12643 NULL_RTX, NULL_RTX);
12644 distribute_links (LOG_LINKS (tem));
12646 SET_INSN_DELETED (tem);
12651 /* Delete the setter too. */
12654 PATTERN (cc0_setter) = pc_rtx;
12655 old_notes = REG_NOTES (cc0_setter);
12656 REG_NOTES (cc0_setter) = NULL;
12658 distribute_notes (old_notes, cc0_setter,
12659 cc0_setter, NULL_RTX,
12660 NULL_RTX, NULL_RTX);
12661 distribute_links (LOG_LINKS (cc0_setter));
12663 SET_INSN_DELETED (cc0_setter);
12664 if (cc0_setter == i2)
12671 PUT_REG_NOTE_KIND (note, REG_UNUSED);
12673 /* If there isn't already a REG_UNUSED note, put one
12674 here. Do not place a REG_DEAD note, even if
12675 the register is also used here; that would not
12676 match the algorithm used in lifetime analysis
12677 and can cause the consistency check in the
12678 scheduler to fail. */
12679 if (! find_regno_note (tem, REG_UNUSED,
12680 REGNO (XEXP (note, 0))))
12685 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12687 && find_reg_fusage (tem, USE, XEXP (note, 0))))
12691 /* If we are doing a 3->2 combination, and we have a
12692 register which formerly died in i3 and was not used
12693 by i2, which now no longer dies in i3 and is used in
12694 i2 but does not die in i2, and place is between i2
12695 and i3, then we may need to move a link from place to
12697 if (i2 && DF_INSN_LUID (place) > DF_INSN_LUID (i2)
12699 && DF_INSN_LUID (from_insn) > DF_INSN_LUID (i2)
12700 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12702 rtx links = LOG_LINKS (place);
12703 LOG_LINKS (place) = 0;
12704 distribute_links (links);
12709 if (tem == BB_HEAD (bb))
12715 /* If the register is set or already dead at PLACE, we needn't do
12716 anything with this note if it is still a REG_DEAD note.
12717 We check here if it is set at all, not if is it totally replaced,
12718 which is what `dead_or_set_p' checks, so also check for it being
12721 if (place && REG_NOTE_KIND (note) == REG_DEAD)
12723 unsigned int regno = REGNO (XEXP (note, 0));
12724 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
12726 if (dead_or_set_p (place, XEXP (note, 0))
12727 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12729 /* Unless the register previously died in PLACE, clear
12730 last_death. [I no longer understand why this is
12732 if (rsp->last_death != place)
12733 rsp->last_death = 0;
12737 rsp->last_death = place;
12739 /* If this is a death note for a hard reg that is occupying
12740 multiple registers, ensure that we are still using all
12741 parts of the object. If we find a piece of the object
12742 that is unused, we must arrange for an appropriate REG_DEAD
12743 note to be added for it. However, we can't just emit a USE
12744 and tag the note to it, since the register might actually
12745 be dead; so we recourse, and the recursive call then finds
12746 the previous insn that used this register. */
12748 if (place && regno < FIRST_PSEUDO_REGISTER
12749 && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
12751 unsigned int endregno = END_HARD_REGNO (XEXP (note, 0));
12755 for (i = regno; i < endregno; i++)
12756 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12757 && ! find_regno_fusage (place, USE, i))
12758 || dead_or_set_regno_p (place, i))
12763 /* Put only REG_DEAD notes for pieces that are
12764 not already dead or set. */
12766 for (i = regno; i < endregno;
12767 i += hard_regno_nregs[i][reg_raw_mode[i]])
12769 rtx piece = regno_reg_rtx[i];
12770 basic_block bb = this_basic_block;
12772 if (! dead_or_set_p (place, piece)
12773 && ! reg_bitfield_target_p (piece,
12776 rtx new_note = alloc_reg_note (REG_DEAD, piece,
12779 distribute_notes (new_note, place, place,
12780 NULL_RTX, NULL_RTX, NULL_RTX);
12782 else if (! refers_to_regno_p (i, i + 1,
12783 PATTERN (place), 0)
12784 && ! find_regno_fusage (place, USE, i))
12785 for (tem = PREV_INSN (place); ;
12786 tem = PREV_INSN (tem))
12788 if (! INSN_P (tem))
12790 if (tem == BB_HEAD (bb))
12794 if (dead_or_set_p (tem, piece)
12795 || reg_bitfield_target_p (piece,
12798 add_reg_note (tem, REG_UNUSED, piece);
12812 /* Any other notes should not be present at this point in the
12814 gcc_unreachable ();
12819 XEXP (note, 1) = REG_NOTES (place);
12820 REG_NOTES (place) = note;
12824 add_reg_note (place2, REG_NOTE_KIND (note), XEXP (note, 0));
12828 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12829 I3, I2, and I1 to new locations. This is also called to add a link
12830 pointing at I3 when I3's destination is changed. */
12833 distribute_links (rtx links)
12835 rtx link, next_link;
12837 for (link = links; link; link = next_link)
12843 next_link = XEXP (link, 1);
12845 /* If the insn that this link points to is a NOTE or isn't a single
12846 set, ignore it. In the latter case, it isn't clear what we
12847 can do other than ignore the link, since we can't tell which
12848 register it was for. Such links wouldn't be used by combine
12851 It is not possible for the destination of the target of the link to
12852 have been changed by combine. The only potential of this is if we
12853 replace I3, I2, and I1 by I3 and I2. But in that case the
12854 destination of I2 also remains unchanged. */
12856 if (NOTE_P (XEXP (link, 0))
12857 || (set = single_set (XEXP (link, 0))) == 0)
12860 reg = SET_DEST (set);
12861 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12862 || GET_CODE (reg) == STRICT_LOW_PART)
12863 reg = XEXP (reg, 0);
12865 /* A LOG_LINK is defined as being placed on the first insn that uses
12866 a register and points to the insn that sets the register. Start
12867 searching at the next insn after the target of the link and stop
12868 when we reach a set of the register or the end of the basic block.
12870 Note that this correctly handles the link that used to point from
12871 I3 to I2. Also note that not much searching is typically done here
12872 since most links don't point very far away. */
12874 for (insn = NEXT_INSN (XEXP (link, 0));
12875 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
12876 || BB_HEAD (this_basic_block->next_bb) != insn));
12877 insn = NEXT_INSN (insn))
12878 if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12880 if (reg_referenced_p (reg, PATTERN (insn)))
12884 else if (CALL_P (insn)
12885 && find_reg_fusage (insn, USE, reg))
12890 else if (INSN_P (insn) && reg_set_p (reg, insn))
12893 /* If we found a place to put the link, place it there unless there
12894 is already a link to the same insn as LINK at that point. */
12900 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12901 if (XEXP (link2, 0) == XEXP (link, 0))
12906 XEXP (link, 1) = LOG_LINKS (place);
12907 LOG_LINKS (place) = link;
12909 /* Set added_links_insn to the earliest insn we added a
12911 if (added_links_insn == 0
12912 || DF_INSN_LUID (added_links_insn) > DF_INSN_LUID (place))
12913 added_links_insn = place;
12919 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
12920 Check whether the expression pointer to by LOC is a register or
12921 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
12922 Otherwise return zero. */
12925 unmentioned_reg_p_1 (rtx *loc, void *expr)
12930 && (REG_P (x) || MEM_P (x))
12931 && ! reg_mentioned_p (x, (rtx) expr))
12936 /* Check for any register or memory mentioned in EQUIV that is not
12937 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
12938 of EXPR where some registers may have been replaced by constants. */
12941 unmentioned_reg_p (rtx equiv, rtx expr)
12943 return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
12947 dump_combine_stats (FILE *file)
12951 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12952 combine_attempts, combine_merges, combine_extras, combine_successes);
12956 dump_combine_total_stats (FILE *file)
12960 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12961 total_attempts, total_merges, total_extras, total_successes);
12965 gate_handle_combine (void)
12967 return (optimize > 0);
12970 /* Try combining insns through substitution. */
12971 static unsigned int
12972 rest_of_handle_combine (void)
12974 int rebuild_jump_labels_after_combine;
12976 df_set_flags (DF_LR_RUN_DCE + DF_DEFER_INSN_RESCAN);
12977 df_note_add_problem ();
12980 regstat_init_n_sets_and_refs ();
12982 rebuild_jump_labels_after_combine
12983 = combine_instructions (get_insns (), max_reg_num ());
12985 /* Combining insns may have turned an indirect jump into a
12986 direct jump. Rebuild the JUMP_LABEL fields of jumping
12988 if (rebuild_jump_labels_after_combine)
12990 timevar_push (TV_JUMP);
12991 rebuild_jump_labels (get_insns ());
12993 timevar_pop (TV_JUMP);
12996 regstat_free_n_sets_and_refs ();
13000 struct rtl_opt_pass pass_combine =
13004 "combine", /* name */
13005 gate_handle_combine, /* gate */
13006 rest_of_handle_combine, /* execute */
13009 0, /* static_pass_number */
13010 TV_COMBINE, /* tv_id */
13011 PROP_cfglayout, /* properties_required */
13012 0, /* properties_provided */
13013 0, /* properties_destroyed */
13014 0, /* todo_flags_start */
13016 TODO_df_finish | TODO_verify_rtl_sharing |
13017 TODO_ggc_collect, /* todo_flags_finish */
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