1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - reg_n_refs is not adjusted in the rare case when a register is
57 no longer required in a computation
58 - there are extremely rare cases (see distribute_notes) when a
60 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
61 removed because there is no way to know which register it was
64 To simplify substitution, we combine only when the earlier insn(s)
65 consist of only a single assignment. To simplify updating afterward,
66 we never combine when a subroutine call appears in the middle.
68 Since we do not represent assignments to CC0 explicitly except when that
69 is all an insn does, there is no LOG_LINKS entry in an insn that uses
70 the condition code for the insn that set the condition code.
71 Fortunately, these two insns must be consecutive.
72 Therefore, every JUMP_INSN is taken to have an implicit logical link
73 to the preceding insn. This is not quite right, since non-jumps can
74 also use the condition code; but in practice such insns would not
79 #include "coretypes.h"
86 #include "hard-reg-set.h"
87 #include "basic-block.h"
88 #include "insn-config.h"
90 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
92 #include "insn-attr.h"
98 #include "insn-codes.h"
99 #include "rtlhooks-def.h"
100 /* Include output.h for dump_file. */
104 #include "tree-pass.h"
106 /* Number of attempts to combine instructions in this function. */
108 static int combine_attempts;
110 /* Number of attempts that got as far as substitution in this function. */
112 static int combine_merges;
114 /* Number of instructions combined with added SETs in this function. */
116 static int combine_extras;
118 /* Number of instructions combined in this function. */
120 static int combine_successes;
122 /* Totals over entire compilation. */
124 static int total_attempts, total_merges, total_extras, total_successes;
127 /* Vector mapping INSN_UIDs to cuids.
128 The cuids are like uids but increase monotonically always.
129 Combine always uses cuids so that it can compare them.
130 But actually renumbering the uids, which we used to do,
131 proves to be a bad idea because it makes it hard to compare
132 the dumps produced by earlier passes with those from later passes. */
134 static int *uid_cuid;
135 static int max_uid_cuid;
137 /* Get the cuid of an insn. */
139 #define INSN_CUID(INSN) \
140 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
142 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
143 BITS_PER_WORD would invoke undefined behavior. Work around it. */
145 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
146 (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
148 /* Maximum register number, which is the size of the tables below. */
150 static unsigned int combine_max_regno;
153 /* Record last point of death of (hard or pseudo) register n. */
156 /* Record last point of modification of (hard or pseudo) register n. */
159 /* The next group of fields allows the recording of the last value assigned
160 to (hard or pseudo) register n. We use this information to see if an
161 operation being processed is redundant given a prior operation performed
162 on the register. For example, an `and' with a constant is redundant if
163 all the zero bits are already known to be turned off.
165 We use an approach similar to that used by cse, but change it in the
168 (1) We do not want to reinitialize at each label.
169 (2) It is useful, but not critical, to know the actual value assigned
170 to a register. Often just its form is helpful.
172 Therefore, we maintain the following fields:
174 last_set_value the last value assigned
175 last_set_label records the value of label_tick when the
176 register was assigned
177 last_set_table_tick records the value of label_tick when a
178 value using the register is assigned
179 last_set_invalid set to nonzero when it is not valid
180 to use the value of this register in some
183 To understand the usage of these tables, it is important to understand
184 the distinction between the value in last_set_value being valid and
185 the register being validly contained in some other expression in the
188 (The next two parameters are out of date).
190 reg_stat[i].last_set_value is valid if it is nonzero, and either
191 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
193 Register I may validly appear in any expression returned for the value
194 of another register if reg_n_sets[i] is 1. It may also appear in the
195 value for register J if reg_stat[j].last_set_invalid is zero, or
196 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
198 If an expression is found in the table containing a register which may
199 not validly appear in an expression, the register is replaced by
200 something that won't match, (clobber (const_int 0)). */
202 /* Record last value assigned to (hard or pseudo) register n. */
206 /* Record the value of label_tick when an expression involving register n
207 is placed in last_set_value. */
209 int last_set_table_tick;
211 /* Record the value of label_tick when the value for register n is placed in
216 /* These fields are maintained in parallel with last_set_value and are
217 used to store the mode in which the register was last set, the bits
218 that were known to be zero when it was last set, and the number of
219 sign bits copies it was known to have when it was last set. */
221 unsigned HOST_WIDE_INT last_set_nonzero_bits;
222 char last_set_sign_bit_copies;
223 ENUM_BITFIELD(machine_mode) last_set_mode : 8;
225 /* Set nonzero if references to register n in expressions should not be
226 used. last_set_invalid is set nonzero when this register is being
227 assigned to and last_set_table_tick == label_tick. */
229 char last_set_invalid;
231 /* Some registers that are set more than once and used in more than one
232 basic block are nevertheless always set in similar ways. For example,
233 a QImode register may be loaded from memory in two places on a machine
234 where byte loads zero extend.
236 We record in the following fields if a register has some leading bits
237 that are always equal to the sign bit, and what we know about the
238 nonzero bits of a register, specifically which bits are known to be
241 If an entry is zero, it means that we don't know anything special. */
243 unsigned char sign_bit_copies;
245 unsigned HOST_WIDE_INT nonzero_bits;
247 /* Record the value of the label_tick when the last truncation
248 happened. The field truncated_to_mode is only valid if
249 truncation_label == label_tick. */
251 int truncation_label;
253 /* Record the last truncation seen for this register. If truncation
254 is not a nop to this mode we might be able to save an explicit
255 truncation if we know that value already contains a truncated
258 ENUM_BITFIELD(machine_mode) truncated_to_mode : 8;
261 static struct reg_stat *reg_stat;
263 /* Record the cuid of the last insn that invalidated memory
264 (anything that writes memory, and subroutine calls, but not pushes). */
266 static int mem_last_set;
268 /* Record the cuid of the last CALL_INSN
269 so we can tell whether a potential combination crosses any calls. */
271 static int last_call_cuid;
273 /* When `subst' is called, this is the insn that is being modified
274 (by combining in a previous insn). The PATTERN of this insn
275 is still the old pattern partially modified and it should not be
276 looked at, but this may be used to examine the successors of the insn
277 to judge whether a simplification is valid. */
279 static rtx subst_insn;
281 /* This is the lowest CUID that `subst' is currently dealing with.
282 get_last_value will not return a value if the register was set at or
283 after this CUID. If not for this mechanism, we could get confused if
284 I2 or I1 in try_combine were an insn that used the old value of a register
285 to obtain a new value. In that case, we might erroneously get the
286 new value of the register when we wanted the old one. */
288 static int subst_low_cuid;
290 /* This contains any hard registers that are used in newpat; reg_dead_at_p
291 must consider all these registers to be always live. */
293 static HARD_REG_SET newpat_used_regs;
295 /* This is an insn to which a LOG_LINKS entry has been added. If this
296 insn is the earlier than I2 or I3, combine should rescan starting at
299 static rtx added_links_insn;
301 /* Basic block in which we are performing combines. */
302 static basic_block this_basic_block;
304 /* A bitmap indicating which blocks had registers go dead at entry.
305 After combine, we'll need to re-do global life analysis with
306 those blocks as starting points. */
307 static sbitmap refresh_blocks;
309 /* The following array records the insn_rtx_cost for every insn
310 in the instruction stream. */
312 static int *uid_insn_cost;
314 /* Length of the currently allocated uid_insn_cost array. */
316 static int last_insn_cost;
318 /* Incremented for each label. */
320 static int label_tick;
322 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
323 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
325 static enum machine_mode nonzero_bits_mode;
327 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
328 be safely used. It is zero while computing them and after combine has
329 completed. This former test prevents propagating values based on
330 previously set values, which can be incorrect if a variable is modified
333 static int nonzero_sign_valid;
336 /* Record one modification to rtl structure
337 to be undone by storing old_contents into *where. */
342 enum { UNDO_RTX, UNDO_INT, UNDO_MODE } kind;
343 union { rtx r; int i; enum machine_mode m; } old_contents;
344 union { rtx *r; int *i; } where;
347 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
348 num_undo says how many are currently recorded.
350 other_insn is nonzero if we have modified some other insn in the process
351 of working on subst_insn. It must be verified too. */
360 static struct undobuf undobuf;
362 /* Number of times the pseudo being substituted for
363 was found and replaced. */
365 static int n_occurrences;
367 static rtx reg_nonzero_bits_for_combine (rtx, enum machine_mode, rtx,
369 unsigned HOST_WIDE_INT,
370 unsigned HOST_WIDE_INT *);
371 static rtx reg_num_sign_bit_copies_for_combine (rtx, enum machine_mode, rtx,
373 unsigned int, unsigned int *);
374 static void do_SUBST (rtx *, rtx);
375 static void do_SUBST_INT (int *, int);
376 static void init_reg_last (void);
377 static void setup_incoming_promotions (void);
378 static void set_nonzero_bits_and_sign_copies (rtx, rtx, void *);
379 static int cant_combine_insn_p (rtx);
380 static int can_combine_p (rtx, rtx, rtx, rtx, rtx *, rtx *);
381 static int combinable_i3pat (rtx, rtx *, rtx, rtx, int, rtx *);
382 static int contains_muldiv (rtx);
383 static rtx try_combine (rtx, rtx, rtx, int *);
384 static void undo_all (void);
385 static void undo_commit (void);
386 static rtx *find_split_point (rtx *, rtx);
387 static rtx subst (rtx, rtx, rtx, int, int);
388 static rtx combine_simplify_rtx (rtx, enum machine_mode, int);
389 static rtx simplify_if_then_else (rtx);
390 static rtx simplify_set (rtx);
391 static rtx simplify_logical (rtx);
392 static rtx expand_compound_operation (rtx);
393 static rtx expand_field_assignment (rtx);
394 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
395 rtx, unsigned HOST_WIDE_INT, int, int, int);
396 static rtx extract_left_shift (rtx, int);
397 static rtx make_compound_operation (rtx, enum rtx_code);
398 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
399 unsigned HOST_WIDE_INT *);
400 static rtx canon_reg_for_combine (rtx, rtx);
401 static rtx force_to_mode (rtx, enum machine_mode,
402 unsigned HOST_WIDE_INT, int);
403 static rtx if_then_else_cond (rtx, rtx *, rtx *);
404 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
405 static int rtx_equal_for_field_assignment_p (rtx, rtx);
406 static rtx make_field_assignment (rtx);
407 static rtx apply_distributive_law (rtx);
408 static rtx distribute_and_simplify_rtx (rtx, int);
409 static rtx simplify_and_const_int_1 (enum machine_mode, rtx,
410 unsigned HOST_WIDE_INT);
411 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
412 unsigned HOST_WIDE_INT);
413 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
414 HOST_WIDE_INT, enum machine_mode, int *);
415 static rtx simplify_shift_const_1 (enum rtx_code, enum machine_mode, rtx, int);
416 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
418 static int recog_for_combine (rtx *, rtx, rtx *);
419 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
420 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
421 static void update_table_tick (rtx);
422 static void record_value_for_reg (rtx, rtx, rtx);
423 static void check_conversions (rtx, rtx);
424 static void record_dead_and_set_regs_1 (rtx, rtx, void *);
425 static void record_dead_and_set_regs (rtx);
426 static int get_last_value_validate (rtx *, rtx, int, int);
427 static rtx get_last_value (rtx);
428 static int use_crosses_set_p (rtx, int);
429 static void reg_dead_at_p_1 (rtx, rtx, void *);
430 static int reg_dead_at_p (rtx, rtx);
431 static void move_deaths (rtx, rtx, int, rtx, rtx *);
432 static int reg_bitfield_target_p (rtx, rtx);
433 static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx);
434 static void distribute_links (rtx);
435 static void mark_used_regs_combine (rtx);
436 static int insn_cuid (rtx);
437 static void record_promoted_value (rtx, rtx);
438 static int unmentioned_reg_p_1 (rtx *, void *);
439 static bool unmentioned_reg_p (rtx, rtx);
440 static void record_truncated_value (rtx);
441 static bool reg_truncated_to_mode (enum machine_mode, rtx);
442 static rtx gen_lowpart_or_truncate (enum machine_mode, rtx);
445 /* It is not safe to use ordinary gen_lowpart in combine.
446 See comments in gen_lowpart_for_combine. */
447 #undef RTL_HOOKS_GEN_LOWPART
448 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
450 /* Our implementation of gen_lowpart never emits a new pseudo. */
451 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
452 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
454 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
455 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
457 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
458 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
460 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
463 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
464 insn. The substitution can be undone by undo_all. If INTO is already
465 set to NEWVAL, do not record this change. Because computing NEWVAL might
466 also call SUBST, we have to compute it before we put anything into
470 do_SUBST (rtx *into, rtx newval)
475 if (oldval == newval)
478 /* We'd like to catch as many invalid transformations here as
479 possible. Unfortunately, there are way too many mode changes
480 that are perfectly valid, so we'd waste too much effort for
481 little gain doing the checks here. Focus on catching invalid
482 transformations involving integer constants. */
483 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
484 && GET_CODE (newval) == CONST_INT)
486 /* Sanity check that we're replacing oldval with a CONST_INT
487 that is a valid sign-extension for the original mode. */
488 gcc_assert (INTVAL (newval)
489 == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
491 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
492 CONST_INT is not valid, because after the replacement, the
493 original mode would be gone. Unfortunately, we can't tell
494 when do_SUBST is called to replace the operand thereof, so we
495 perform this test on oldval instead, checking whether an
496 invalid replacement took place before we got here. */
497 gcc_assert (!(GET_CODE (oldval) == SUBREG
498 && GET_CODE (SUBREG_REG (oldval)) == CONST_INT));
499 gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
500 && GET_CODE (XEXP (oldval, 0)) == CONST_INT));
504 buf = undobuf.frees, undobuf.frees = buf->next;
506 buf = xmalloc (sizeof (struct undo));
508 buf->kind = UNDO_RTX;
510 buf->old_contents.r = oldval;
513 buf->next = undobuf.undos, undobuf.undos = buf;
516 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
518 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
519 for the value of a HOST_WIDE_INT value (including CONST_INT) is
523 do_SUBST_INT (int *into, int newval)
528 if (oldval == newval)
532 buf = undobuf.frees, undobuf.frees = buf->next;
534 buf = xmalloc (sizeof (struct undo));
536 buf->kind = UNDO_INT;
538 buf->old_contents.i = oldval;
541 buf->next = undobuf.undos, undobuf.undos = buf;
544 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
546 /* Similar to SUBST, but just substitute the mode. This is used when
547 changing the mode of a pseudo-register, so that any other
548 references to the entry in the regno_reg_rtx array will change as
552 do_SUBST_MODE (rtx *into, enum machine_mode newval)
555 enum machine_mode oldval = GET_MODE (*into);
557 if (oldval == newval)
561 buf = undobuf.frees, undobuf.frees = buf->next;
563 buf = xmalloc (sizeof (struct undo));
565 buf->kind = UNDO_MODE;
567 buf->old_contents.m = oldval;
568 PUT_MODE (*into, newval);
570 buf->next = undobuf.undos, undobuf.undos = buf;
573 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE(&(INTO), (NEWVAL))
575 /* Subroutine of try_combine. Determine whether the combine replacement
576 patterns NEWPAT and NEWI2PAT are cheaper according to insn_rtx_cost
577 that the original instruction sequence I1, I2 and I3. Note that I1
578 and/or NEWI2PAT may be NULL_RTX. This function returns false, if the
579 costs of all instructions can be estimated, and the replacements are
580 more expensive than the original sequence. */
583 combine_validate_cost (rtx i1, rtx i2, rtx i3, rtx newpat, rtx newi2pat)
585 int i1_cost, i2_cost, i3_cost;
586 int new_i2_cost, new_i3_cost;
587 int old_cost, new_cost;
589 /* Lookup the original insn_rtx_costs. */
590 i2_cost = INSN_UID (i2) <= last_insn_cost
591 ? uid_insn_cost[INSN_UID (i2)] : 0;
592 i3_cost = INSN_UID (i3) <= last_insn_cost
593 ? uid_insn_cost[INSN_UID (i3)] : 0;
597 i1_cost = INSN_UID (i1) <= last_insn_cost
598 ? uid_insn_cost[INSN_UID (i1)] : 0;
599 old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0)
600 ? i1_cost + i2_cost + i3_cost : 0;
604 old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
608 /* Calculate the replacement insn_rtx_costs. */
609 new_i3_cost = insn_rtx_cost (newpat);
612 new_i2_cost = insn_rtx_cost (newi2pat);
613 new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
614 ? new_i2_cost + new_i3_cost : 0;
618 new_cost = new_i3_cost;
622 if (undobuf.other_insn)
624 int old_other_cost, new_other_cost;
626 old_other_cost = (INSN_UID (undobuf.other_insn) <= last_insn_cost
627 ? uid_insn_cost[INSN_UID (undobuf.other_insn)] : 0);
628 new_other_cost = insn_rtx_cost (PATTERN (undobuf.other_insn));
629 if (old_other_cost > 0 && new_other_cost > 0)
631 old_cost += old_other_cost;
632 new_cost += new_other_cost;
638 /* Disallow this recombination if both new_cost and old_cost are
639 greater than zero, and new_cost is greater than old cost. */
641 && new_cost > old_cost)
648 "rejecting combination of insns %d, %d and %d\n",
649 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
650 fprintf (dump_file, "original costs %d + %d + %d = %d\n",
651 i1_cost, i2_cost, i3_cost, old_cost);
656 "rejecting combination of insns %d and %d\n",
657 INSN_UID (i2), INSN_UID (i3));
658 fprintf (dump_file, "original costs %d + %d = %d\n",
659 i2_cost, i3_cost, old_cost);
664 fprintf (dump_file, "replacement costs %d + %d = %d\n",
665 new_i2_cost, new_i3_cost, new_cost);
668 fprintf (dump_file, "replacement cost %d\n", new_cost);
674 /* Update the uid_insn_cost array with the replacement costs. */
675 uid_insn_cost[INSN_UID (i2)] = new_i2_cost;
676 uid_insn_cost[INSN_UID (i3)] = new_i3_cost;
678 uid_insn_cost[INSN_UID (i1)] = 0;
683 /* Main entry point for combiner. F is the first insn of the function.
684 NREGS is the first unused pseudo-reg number.
686 Return nonzero if the combiner has turned an indirect jump
687 instruction into a direct jump. */
689 combine_instructions (rtx f, unsigned int nregs)
697 rtx links, nextlinks;
698 sbitmap_iterator sbi;
700 int new_direct_jump_p = 0;
702 combine_attempts = 0;
705 combine_successes = 0;
707 combine_max_regno = nregs;
709 rtl_hooks = combine_rtl_hooks;
711 reg_stat = xcalloc (nregs, sizeof (struct reg_stat));
713 init_recog_no_volatile ();
715 /* Compute maximum uid value so uid_cuid can be allocated. */
717 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
718 if (INSN_UID (insn) > i)
721 uid_cuid = xmalloc ((i + 1) * sizeof (int));
724 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
726 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
727 problems when, for example, we have j <<= 1 in a loop. */
729 nonzero_sign_valid = 0;
731 /* Compute the mapping from uids to cuids.
732 Cuids are numbers assigned to insns, like uids,
733 except that cuids increase monotonically through the code.
735 Scan all SETs and see if we can deduce anything about what
736 bits are known to be zero for some registers and how many copies
737 of the sign bit are known to exist for those registers.
739 Also set any known values so that we can use it while searching
740 for what bits are known to be set. */
744 setup_incoming_promotions ();
746 refresh_blocks = sbitmap_alloc (last_basic_block);
747 sbitmap_zero (refresh_blocks);
749 /* Allocate array of current insn_rtx_costs. */
750 uid_insn_cost = xcalloc (max_uid_cuid + 1, sizeof (int));
751 last_insn_cost = max_uid_cuid;
753 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
755 uid_cuid[INSN_UID (insn)] = ++i;
761 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
763 record_dead_and_set_regs (insn);
766 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
767 if (REG_NOTE_KIND (links) == REG_INC)
768 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
772 /* Record the current insn_rtx_cost of this instruction. */
773 if (NONJUMP_INSN_P (insn))
774 uid_insn_cost[INSN_UID (insn)] = insn_rtx_cost (PATTERN (insn));
776 fprintf(dump_file, "insn_cost %d: %d\n",
777 INSN_UID (insn), uid_insn_cost[INSN_UID (insn)]);
784 nonzero_sign_valid = 1;
786 /* Now scan all the insns in forward order. */
792 setup_incoming_promotions ();
794 FOR_EACH_BB (this_basic_block)
796 for (insn = BB_HEAD (this_basic_block);
797 insn != NEXT_INSN (BB_END (this_basic_block));
798 insn = next ? next : NEXT_INSN (insn))
805 else if (INSN_P (insn))
807 /* See if we know about function return values before this
808 insn based upon SUBREG flags. */
809 check_conversions (insn, PATTERN (insn));
811 /* Try this insn with each insn it links back to. */
813 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
814 if ((next = try_combine (insn, XEXP (links, 0),
815 NULL_RTX, &new_direct_jump_p)) != 0)
818 /* Try each sequence of three linked insns ending with this one. */
820 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
822 rtx link = XEXP (links, 0);
824 /* If the linked insn has been replaced by a note, then there
825 is no point in pursuing this chain any further. */
829 for (nextlinks = LOG_LINKS (link);
831 nextlinks = XEXP (nextlinks, 1))
832 if ((next = try_combine (insn, link,
834 &new_direct_jump_p)) != 0)
839 /* Try to combine a jump insn that uses CC0
840 with a preceding insn that sets CC0, and maybe with its
841 logical predecessor as well.
842 This is how we make decrement-and-branch insns.
843 We need this special code because data flow connections
844 via CC0 do not get entered in LOG_LINKS. */
847 && (prev = prev_nonnote_insn (insn)) != 0
848 && NONJUMP_INSN_P (prev)
849 && sets_cc0_p (PATTERN (prev)))
851 if ((next = try_combine (insn, prev,
852 NULL_RTX, &new_direct_jump_p)) != 0)
855 for (nextlinks = LOG_LINKS (prev); nextlinks;
856 nextlinks = XEXP (nextlinks, 1))
857 if ((next = try_combine (insn, prev,
859 &new_direct_jump_p)) != 0)
863 /* Do the same for an insn that explicitly references CC0. */
864 if (NONJUMP_INSN_P (insn)
865 && (prev = prev_nonnote_insn (insn)) != 0
866 && NONJUMP_INSN_P (prev)
867 && sets_cc0_p (PATTERN (prev))
868 && GET_CODE (PATTERN (insn)) == SET
869 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
871 if ((next = try_combine (insn, prev,
872 NULL_RTX, &new_direct_jump_p)) != 0)
875 for (nextlinks = LOG_LINKS (prev); nextlinks;
876 nextlinks = XEXP (nextlinks, 1))
877 if ((next = try_combine (insn, prev,
879 &new_direct_jump_p)) != 0)
883 /* Finally, see if any of the insns that this insn links to
884 explicitly references CC0. If so, try this insn, that insn,
885 and its predecessor if it sets CC0. */
886 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
887 if (NONJUMP_INSN_P (XEXP (links, 0))
888 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
889 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
890 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
891 && NONJUMP_INSN_P (prev)
892 && sets_cc0_p (PATTERN (prev))
893 && (next = try_combine (insn, XEXP (links, 0),
894 prev, &new_direct_jump_p)) != 0)
898 /* Try combining an insn with two different insns whose results it
900 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
901 for (nextlinks = XEXP (links, 1); nextlinks;
902 nextlinks = XEXP (nextlinks, 1))
903 if ((next = try_combine (insn, XEXP (links, 0),
905 &new_direct_jump_p)) != 0)
908 /* Try this insn with each REG_EQUAL note it links back to. */
909 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
912 rtx temp = XEXP (links, 0);
913 if ((set = single_set (temp)) != 0
914 && (note = find_reg_equal_equiv_note (temp)) != 0
915 && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
916 /* Avoid using a register that may already been marked
917 dead by an earlier instruction. */
918 && ! unmentioned_reg_p (note, SET_SRC (set))
919 && (GET_MODE (note) == VOIDmode
920 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
921 : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
923 /* Temporarily replace the set's source with the
924 contents of the REG_EQUAL note. The insn will
925 be deleted or recognized by try_combine. */
926 rtx orig = SET_SRC (set);
927 SET_SRC (set) = note;
928 next = try_combine (insn, temp, NULL_RTX,
932 SET_SRC (set) = orig;
937 record_dead_and_set_regs (insn);
946 EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks, 0, j, sbi)
947 BASIC_BLOCK (j)->flags |= BB_DIRTY;
948 new_direct_jump_p |= purge_all_dead_edges ();
949 delete_noop_moves ();
951 update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES,
952 PROP_DEATH_NOTES | PROP_SCAN_DEAD_CODE
953 | PROP_KILL_DEAD_CODE);
956 sbitmap_free (refresh_blocks);
957 free (uid_insn_cost);
962 struct undo *undo, *next;
963 for (undo = undobuf.frees; undo; undo = next)
971 total_attempts += combine_attempts;
972 total_merges += combine_merges;
973 total_extras += combine_extras;
974 total_successes += combine_successes;
976 nonzero_sign_valid = 0;
977 rtl_hooks = general_rtl_hooks;
979 /* Make recognizer allow volatile MEMs again. */
982 return new_direct_jump_p;
985 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
991 for (i = 0; i < combine_max_regno; i++)
992 memset (reg_stat + i, 0, offsetof (struct reg_stat, sign_bit_copies));
995 /* Set up any promoted values for incoming argument registers. */
998 setup_incoming_promotions (void)
1002 enum machine_mode mode;
1004 rtx first = get_insns ();
1006 if (targetm.calls.promote_function_args (TREE_TYPE (cfun->decl)))
1008 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
1009 /* Check whether this register can hold an incoming pointer
1010 argument. FUNCTION_ARG_REGNO_P tests outgoing register
1011 numbers, so translate if necessary due to register windows. */
1012 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno))
1013 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
1015 record_value_for_reg
1016 (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
1019 gen_rtx_CLOBBER (mode, const0_rtx)));
1024 /* Called via note_stores. If X is a pseudo that is narrower than
1025 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1027 If we are setting only a portion of X and we can't figure out what
1028 portion, assume all bits will be used since we don't know what will
1031 Similarly, set how many bits of X are known to be copies of the sign bit
1032 at all locations in the function. This is the smallest number implied
1036 set_nonzero_bits_and_sign_copies (rtx x, rtx set,
1037 void *data ATTRIBUTE_UNUSED)
1042 && REGNO (x) >= FIRST_PSEUDO_REGISTER
1043 /* If this register is undefined at the start of the file, we can't
1044 say what its contents were. */
1045 && ! REGNO_REG_SET_P
1046 (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start, REGNO (x))
1047 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
1049 if (set == 0 || GET_CODE (set) == CLOBBER)
1051 reg_stat[REGNO (x)].nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1052 reg_stat[REGNO (x)].sign_bit_copies = 1;
1056 /* If this is a complex assignment, see if we can convert it into a
1057 simple assignment. */
1058 set = expand_field_assignment (set);
1060 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1061 set what we know about X. */
1063 if (SET_DEST (set) == x
1064 || (GET_CODE (SET_DEST (set)) == SUBREG
1065 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
1066 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
1067 && SUBREG_REG (SET_DEST (set)) == x))
1069 rtx src = SET_SRC (set);
1071 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1072 /* If X is narrower than a word and SRC is a non-negative
1073 constant that would appear negative in the mode of X,
1074 sign-extend it for use in reg_stat[].nonzero_bits because some
1075 machines (maybe most) will actually do the sign-extension
1076 and this is the conservative approach.
1078 ??? For 2.5, try to tighten up the MD files in this regard
1079 instead of this kludge. */
1081 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
1082 && GET_CODE (src) == CONST_INT
1084 && 0 != (INTVAL (src)
1085 & ((HOST_WIDE_INT) 1
1086 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
1087 src = GEN_INT (INTVAL (src)
1088 | ((HOST_WIDE_INT) (-1)
1089 << GET_MODE_BITSIZE (GET_MODE (x))));
1092 /* Don't call nonzero_bits if it cannot change anything. */
1093 if (reg_stat[REGNO (x)].nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1094 reg_stat[REGNO (x)].nonzero_bits
1095 |= nonzero_bits (src, nonzero_bits_mode);
1096 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1097 if (reg_stat[REGNO (x)].sign_bit_copies == 0
1098 || reg_stat[REGNO (x)].sign_bit_copies > num)
1099 reg_stat[REGNO (x)].sign_bit_copies = num;
1103 reg_stat[REGNO (x)].nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1104 reg_stat[REGNO (x)].sign_bit_copies = 1;
1109 /* See if INSN can be combined into I3. PRED and SUCC are optionally
1110 insns that were previously combined into I3 or that will be combined
1111 into the merger of INSN and I3.
1113 Return 0 if the combination is not allowed for any reason.
1115 If the combination is allowed, *PDEST will be set to the single
1116 destination of INSN and *PSRC to the single source, and this function
1120 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED, rtx succ,
1121 rtx *pdest, rtx *psrc)
1124 rtx set = 0, src, dest;
1129 int all_adjacent = (succ ? (next_active_insn (insn) == succ
1130 && next_active_insn (succ) == i3)
1131 : next_active_insn (insn) == i3);
1133 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1134 or a PARALLEL consisting of such a SET and CLOBBERs.
1136 If INSN has CLOBBER parallel parts, ignore them for our processing.
1137 By definition, these happen during the execution of the insn. When it
1138 is merged with another insn, all bets are off. If they are, in fact,
1139 needed and aren't also supplied in I3, they may be added by
1140 recog_for_combine. Otherwise, it won't match.
1142 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1145 Get the source and destination of INSN. If more than one, can't
1148 if (GET_CODE (PATTERN (insn)) == SET)
1149 set = PATTERN (insn);
1150 else if (GET_CODE (PATTERN (insn)) == PARALLEL
1151 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1153 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1155 rtx elt = XVECEXP (PATTERN (insn), 0, i);
1158 switch (GET_CODE (elt))
1160 /* This is important to combine floating point insns
1161 for the SH4 port. */
1163 /* Combining an isolated USE doesn't make sense.
1164 We depend here on combinable_i3pat to reject them. */
1165 /* The code below this loop only verifies that the inputs of
1166 the SET in INSN do not change. We call reg_set_between_p
1167 to verify that the REG in the USE does not change between
1169 If the USE in INSN was for a pseudo register, the matching
1170 insn pattern will likely match any register; combining this
1171 with any other USE would only be safe if we knew that the
1172 used registers have identical values, or if there was
1173 something to tell them apart, e.g. different modes. For
1174 now, we forgo such complicated tests and simply disallow
1175 combining of USES of pseudo registers with any other USE. */
1176 if (REG_P (XEXP (elt, 0))
1177 && GET_CODE (PATTERN (i3)) == PARALLEL)
1179 rtx i3pat = PATTERN (i3);
1180 int i = XVECLEN (i3pat, 0) - 1;
1181 unsigned int regno = REGNO (XEXP (elt, 0));
1185 rtx i3elt = XVECEXP (i3pat, 0, i);
1187 if (GET_CODE (i3elt) == USE
1188 && REG_P (XEXP (i3elt, 0))
1189 && (REGNO (XEXP (i3elt, 0)) == regno
1190 ? reg_set_between_p (XEXP (elt, 0),
1191 PREV_INSN (insn), i3)
1192 : regno >= FIRST_PSEUDO_REGISTER))
1199 /* We can ignore CLOBBERs. */
1204 /* Ignore SETs whose result isn't used but not those that
1205 have side-effects. */
1206 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1207 && (!(note = find_reg_note (insn, REG_EH_REGION, NULL_RTX))
1208 || INTVAL (XEXP (note, 0)) <= 0)
1209 && ! side_effects_p (elt))
1212 /* If we have already found a SET, this is a second one and
1213 so we cannot combine with this insn. */
1221 /* Anything else means we can't combine. */
1227 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1228 so don't do anything with it. */
1229 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1238 set = expand_field_assignment (set);
1239 src = SET_SRC (set), dest = SET_DEST (set);
1241 /* Don't eliminate a store in the stack pointer. */
1242 if (dest == stack_pointer_rtx
1243 /* Don't combine with an insn that sets a register to itself if it has
1244 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1245 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1246 /* Can't merge an ASM_OPERANDS. */
1247 || GET_CODE (src) == ASM_OPERANDS
1248 /* Can't merge a function call. */
1249 || GET_CODE (src) == CALL
1250 /* Don't eliminate a function call argument. */
1252 && (find_reg_fusage (i3, USE, dest)
1254 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1255 && global_regs[REGNO (dest)])))
1256 /* Don't substitute into an incremented register. */
1257 || FIND_REG_INC_NOTE (i3, dest)
1258 || (succ && FIND_REG_INC_NOTE (succ, dest))
1259 /* Don't substitute into a non-local goto, this confuses CFG. */
1260 || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1262 /* Don't combine the end of a libcall into anything. */
1263 /* ??? This gives worse code, and appears to be unnecessary, since no
1264 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1265 use REG_RETVAL notes for noconflict blocks, but other code here
1266 makes sure that those insns don't disappear. */
1267 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
1269 /* Make sure that DEST is not used after SUCC but before I3. */
1270 || (succ && ! all_adjacent
1271 && reg_used_between_p (dest, succ, i3))
1272 /* Make sure that the value that is to be substituted for the register
1273 does not use any registers whose values alter in between. However,
1274 If the insns are adjacent, a use can't cross a set even though we
1275 think it might (this can happen for a sequence of insns each setting
1276 the same destination; last_set of that register might point to
1277 a NOTE). If INSN has a REG_EQUIV note, the register is always
1278 equivalent to the memory so the substitution is valid even if there
1279 are intervening stores. Also, don't move a volatile asm or
1280 UNSPEC_VOLATILE across any other insns. */
1283 || ! find_reg_note (insn, REG_EQUIV, src))
1284 && use_crosses_set_p (src, INSN_CUID (insn)))
1285 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1286 || GET_CODE (src) == UNSPEC_VOLATILE))
1287 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1288 better register allocation by not doing the combine. */
1289 || find_reg_note (i3, REG_NO_CONFLICT, dest)
1290 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
1291 /* Don't combine across a CALL_INSN, because that would possibly
1292 change whether the life span of some REGs crosses calls or not,
1293 and it is a pain to update that information.
1294 Exception: if source is a constant, moving it later can't hurt.
1295 Accept that special case, because it helps -fforce-addr a lot. */
1296 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
1299 /* DEST must either be a REG or CC0. */
1302 /* If register alignment is being enforced for multi-word items in all
1303 cases except for parameters, it is possible to have a register copy
1304 insn referencing a hard register that is not allowed to contain the
1305 mode being copied and which would not be valid as an operand of most
1306 insns. Eliminate this problem by not combining with such an insn.
1308 Also, on some machines we don't want to extend the life of a hard
1312 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1313 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1314 /* Don't extend the life of a hard register unless it is
1315 user variable (if we have few registers) or it can't
1316 fit into the desired register (meaning something special
1318 Also avoid substituting a return register into I3, because
1319 reload can't handle a conflict with constraints of other
1321 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1322 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1325 else if (GET_CODE (dest) != CC0)
1329 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1330 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1331 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1333 /* Don't substitute for a register intended as a clobberable
1335 rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1336 if (rtx_equal_p (reg, dest))
1339 /* If the clobber represents an earlyclobber operand, we must not
1340 substitute an expression containing the clobbered register.
1341 As we do not analyze the constraint strings here, we have to
1342 make the conservative assumption. However, if the register is
1343 a fixed hard reg, the clobber cannot represent any operand;
1344 we leave it up to the machine description to either accept or
1345 reject use-and-clobber patterns. */
1347 || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1348 || !fixed_regs[REGNO (reg)])
1349 if (reg_overlap_mentioned_p (reg, src))
1353 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1354 or not), reject, unless nothing volatile comes between it and I3 */
1356 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1358 /* Make sure succ doesn't contain a volatile reference. */
1359 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1362 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1363 if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1367 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1368 to be an explicit register variable, and was chosen for a reason. */
1370 if (GET_CODE (src) == ASM_OPERANDS
1371 && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1374 /* If there are any volatile insns between INSN and I3, reject, because
1375 they might affect machine state. */
1377 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1378 if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1381 /* If INSN contains an autoincrement or autodecrement, make sure that
1382 register is not used between there and I3, and not already used in
1383 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1384 Also insist that I3 not be a jump; if it were one
1385 and the incremented register were spilled, we would lose. */
1388 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1389 if (REG_NOTE_KIND (link) == REG_INC
1391 || reg_used_between_p (XEXP (link, 0), insn, i3)
1392 || (pred != NULL_RTX
1393 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
1394 || (succ != NULL_RTX
1395 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
1396 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1401 /* Don't combine an insn that follows a CC0-setting insn.
1402 An insn that uses CC0 must not be separated from the one that sets it.
1403 We do, however, allow I2 to follow a CC0-setting insn if that insn
1404 is passed as I1; in that case it will be deleted also.
1405 We also allow combining in this case if all the insns are adjacent
1406 because that would leave the two CC0 insns adjacent as well.
1407 It would be more logical to test whether CC0 occurs inside I1 or I2,
1408 but that would be much slower, and this ought to be equivalent. */
1410 p = prev_nonnote_insn (insn);
1411 if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
1416 /* If we get here, we have passed all the tests and the combination is
1425 /* LOC is the location within I3 that contains its pattern or the component
1426 of a PARALLEL of the pattern. We validate that it is valid for combining.
1428 One problem is if I3 modifies its output, as opposed to replacing it
1429 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1430 so would produce an insn that is not equivalent to the original insns.
1434 (set (reg:DI 101) (reg:DI 100))
1435 (set (subreg:SI (reg:DI 101) 0) <foo>)
1437 This is NOT equivalent to:
1439 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1440 (set (reg:DI 101) (reg:DI 100))])
1442 Not only does this modify 100 (in which case it might still be valid
1443 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1445 We can also run into a problem if I2 sets a register that I1
1446 uses and I1 gets directly substituted into I3 (not via I2). In that
1447 case, we would be getting the wrong value of I2DEST into I3, so we
1448 must reject the combination. This case occurs when I2 and I1 both
1449 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1450 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1451 of a SET must prevent combination from occurring.
1453 Before doing the above check, we first try to expand a field assignment
1454 into a set of logical operations.
1456 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1457 we place a register that is both set and used within I3. If more than one
1458 such register is detected, we fail.
1460 Return 1 if the combination is valid, zero otherwise. */
1463 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest,
1464 int i1_not_in_src, rtx *pi3dest_killed)
1468 if (GET_CODE (x) == SET)
1471 rtx dest = SET_DEST (set);
1472 rtx src = SET_SRC (set);
1473 rtx inner_dest = dest;
1476 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1477 || GET_CODE (inner_dest) == SUBREG
1478 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1479 inner_dest = XEXP (inner_dest, 0);
1481 /* Check for the case where I3 modifies its output, as discussed
1482 above. We don't want to prevent pseudos from being combined
1483 into the address of a MEM, so only prevent the combination if
1484 i1 or i2 set the same MEM. */
1485 if ((inner_dest != dest &&
1486 (!MEM_P (inner_dest)
1487 || rtx_equal_p (i2dest, inner_dest)
1488 || (i1dest && rtx_equal_p (i1dest, inner_dest)))
1489 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1490 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1492 /* This is the same test done in can_combine_p except we can't test
1493 all_adjacent; we don't have to, since this instruction will stay
1494 in place, thus we are not considering increasing the lifetime of
1497 Also, if this insn sets a function argument, combining it with
1498 something that might need a spill could clobber a previous
1499 function argument; the all_adjacent test in can_combine_p also
1500 checks this; here, we do a more specific test for this case. */
1502 || (REG_P (inner_dest)
1503 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1504 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1505 GET_MODE (inner_dest))))
1506 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1509 /* If DEST is used in I3, it is being killed in this insn, so
1510 record that for later. We have to consider paradoxical
1511 subregs here, since they kill the whole register, but we
1512 ignore partial subregs, STRICT_LOW_PART, etc.
1513 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1514 STACK_POINTER_REGNUM, since these are always considered to be
1515 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1517 if (GET_CODE (subdest) == SUBREG
1518 && (GET_MODE_SIZE (GET_MODE (subdest))
1519 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
1520 subdest = SUBREG_REG (subdest);
1523 && reg_referenced_p (subdest, PATTERN (i3))
1524 && REGNO (subdest) != FRAME_POINTER_REGNUM
1525 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1526 && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
1528 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1529 && (REGNO (subdest) != ARG_POINTER_REGNUM
1530 || ! fixed_regs [REGNO (subdest)])
1532 && REGNO (subdest) != STACK_POINTER_REGNUM)
1534 if (*pi3dest_killed)
1537 *pi3dest_killed = subdest;
1541 else if (GET_CODE (x) == PARALLEL)
1545 for (i = 0; i < XVECLEN (x, 0); i++)
1546 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1547 i1_not_in_src, pi3dest_killed))
1554 /* Return 1 if X is an arithmetic expression that contains a multiplication
1555 and division. We don't count multiplications by powers of two here. */
1558 contains_muldiv (rtx x)
1560 switch (GET_CODE (x))
1562 case MOD: case DIV: case UMOD: case UDIV:
1566 return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1567 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1570 return contains_muldiv (XEXP (x, 0))
1571 || contains_muldiv (XEXP (x, 1));
1574 return contains_muldiv (XEXP (x, 0));
1580 /* Determine whether INSN can be used in a combination. Return nonzero if
1581 not. This is used in try_combine to detect early some cases where we
1582 can't perform combinations. */
1585 cant_combine_insn_p (rtx insn)
1590 /* If this isn't really an insn, we can't do anything.
1591 This can occur when flow deletes an insn that it has merged into an
1592 auto-increment address. */
1593 if (! INSN_P (insn))
1596 /* Never combine loads and stores involving hard regs that are likely
1597 to be spilled. The register allocator can usually handle such
1598 reg-reg moves by tying. If we allow the combiner to make
1599 substitutions of likely-spilled regs, reload might die.
1600 As an exception, we allow combinations involving fixed regs; these are
1601 not available to the register allocator so there's no risk involved. */
1603 set = single_set (insn);
1606 src = SET_SRC (set);
1607 dest = SET_DEST (set);
1608 if (GET_CODE (src) == SUBREG)
1609 src = SUBREG_REG (src);
1610 if (GET_CODE (dest) == SUBREG)
1611 dest = SUBREG_REG (dest);
1612 if (REG_P (src) && REG_P (dest)
1613 && ((REGNO (src) < FIRST_PSEUDO_REGISTER
1614 && ! fixed_regs[REGNO (src)]
1615 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src))))
1616 || (REGNO (dest) < FIRST_PSEUDO_REGISTER
1617 && ! fixed_regs[REGNO (dest)]
1618 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest))))))
1624 struct likely_spilled_retval_info
1626 unsigned regno, nregs;
1630 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
1631 hard registers that are known to be written to / clobbered in full. */
1633 likely_spilled_retval_1 (rtx x, rtx set, void *data)
1635 struct likely_spilled_retval_info *info = data;
1636 unsigned regno, nregs;
1639 if (!REG_P (XEXP (set, 0)))
1642 if (regno >= info->regno + info->nregs)
1644 nregs = hard_regno_nregs[regno][GET_MODE (x)];
1645 if (regno + nregs <= info->regno)
1647 new_mask = (2U << (nregs - 1)) - 1;
1648 if (regno < info->regno)
1649 new_mask >>= info->regno - regno;
1651 new_mask <<= regno - info->regno;
1652 info->mask &= new_mask;
1655 /* Return nonzero iff part of the return value is live during INSN, and
1656 it is likely spilled. This can happen when more than one insn is needed
1657 to copy the return value, e.g. when we consider to combine into the
1658 second copy insn for a complex value. */
1661 likely_spilled_retval_p (rtx insn)
1663 rtx use = BB_END (this_basic_block);
1665 unsigned regno, nregs;
1666 /* We assume here that no machine mode needs more than
1667 32 hard registers when the value overlaps with a register
1668 for which FUNCTION_VALUE_REGNO_P is true. */
1670 struct likely_spilled_retval_info info;
1672 if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
1674 reg = XEXP (PATTERN (use), 0);
1675 if (!REG_P (reg) || !FUNCTION_VALUE_REGNO_P (REGNO (reg)))
1677 regno = REGNO (reg);
1678 nregs = hard_regno_nregs[regno][GET_MODE (reg)];
1681 mask = (2U << (nregs - 1)) - 1;
1683 /* Disregard parts of the return value that are set later. */
1687 for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
1688 note_stores (PATTERN (insn), likely_spilled_retval_1, &info);
1691 /* Check if any of the (probably) live return value registers is
1696 if ((mask & 1 << nregs)
1697 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (regno + nregs)))
1703 /* Adjust INSN after we made a change to its destination.
1705 Changing the destination can invalidate notes that say something about
1706 the results of the insn and a LOG_LINK pointing to the insn. */
1709 adjust_for_new_dest (rtx insn)
1713 /* For notes, be conservative and simply remove them. */
1714 loc = ®_NOTES (insn);
1717 enum reg_note kind = REG_NOTE_KIND (*loc);
1718 if (kind == REG_EQUAL || kind == REG_EQUIV)
1719 *loc = XEXP (*loc, 1);
1721 loc = &XEXP (*loc, 1);
1724 /* The new insn will have a destination that was previously the destination
1725 of an insn just above it. Call distribute_links to make a LOG_LINK from
1726 the next use of that destination. */
1727 distribute_links (gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX));
1730 /* Return TRUE if combine can reuse reg X in mode MODE.
1731 ADDED_SETS is nonzero if the original set is still required. */
1733 can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode)
1741 /* Allow hard registers if the new mode is legal, and occupies no more
1742 registers than the old mode. */
1743 if (regno < FIRST_PSEUDO_REGISTER)
1744 return (HARD_REGNO_MODE_OK (regno, mode)
1745 && (hard_regno_nregs[regno][GET_MODE (x)]
1746 >= hard_regno_nregs[regno][mode]));
1748 /* Or a pseudo that is only used once. */
1749 return (REG_N_SETS (regno) == 1 && !added_sets
1750 && !REG_USERVAR_P (x));
1754 /* Check whether X, the destination of a set, refers to part of
1755 the register specified by REG. */
1758 reg_subword_p (rtx x, rtx reg)
1760 /* Check that reg is an integer mode register. */
1761 if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
1764 if (GET_CODE (x) == STRICT_LOW_PART
1765 || GET_CODE (x) == ZERO_EXTRACT)
1768 return GET_CODE (x) == SUBREG
1769 && SUBREG_REG (x) == reg
1770 && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
1774 /* Try to combine the insns I1 and I2 into I3.
1775 Here I1 and I2 appear earlier than I3.
1776 I1 can be zero; then we combine just I2 into I3.
1778 If we are combining three insns and the resulting insn is not recognized,
1779 try splitting it into two insns. If that happens, I2 and I3 are retained
1780 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1783 Return 0 if the combination does not work. Then nothing is changed.
1784 If we did the combination, return the insn at which combine should
1787 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
1788 new direct jump instruction. */
1791 try_combine (rtx i3, rtx i2, rtx i1, int *new_direct_jump_p)
1793 /* New patterns for I3 and I2, respectively. */
1794 rtx newpat, newi2pat = 0;
1795 rtvec newpat_vec_with_clobbers = 0;
1796 int substed_i2 = 0, substed_i1 = 0;
1797 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1798 int added_sets_1, added_sets_2;
1799 /* Total number of SETs to put into I3. */
1801 /* Nonzero if I2's body now appears in I3. */
1803 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1804 int insn_code_number, i2_code_number = 0, other_code_number = 0;
1805 /* Contains I3 if the destination of I3 is used in its source, which means
1806 that the old life of I3 is being killed. If that usage is placed into
1807 I2 and not in I3, a REG_DEAD note must be made. */
1808 rtx i3dest_killed = 0;
1809 /* SET_DEST and SET_SRC of I2 and I1. */
1810 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1811 /* PATTERN (I2), or a copy of it in certain cases. */
1813 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1814 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1815 int i2dest_killed = 0, i1dest_killed = 0;
1816 int i1_feeds_i3 = 0;
1817 /* Notes that must be added to REG_NOTES in I3 and I2. */
1818 rtx new_i3_notes, new_i2_notes;
1819 /* Notes that we substituted I3 into I2 instead of the normal case. */
1820 int i3_subst_into_i2 = 0;
1821 /* Notes that I1, I2 or I3 is a MULT operation. */
1830 /* Exit early if one of the insns involved can't be used for
1832 if (cant_combine_insn_p (i3)
1833 || cant_combine_insn_p (i2)
1834 || (i1 && cant_combine_insn_p (i1))
1835 || likely_spilled_retval_p (i3)
1836 /* We also can't do anything if I3 has a
1837 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1840 /* ??? This gives worse code, and appears to be unnecessary, since no
1841 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1842 || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1848 undobuf.other_insn = 0;
1850 /* Reset the hard register usage information. */
1851 CLEAR_HARD_REG_SET (newpat_used_regs);
1853 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1854 code below, set I1 to be the earlier of the two insns. */
1855 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1856 temp = i1, i1 = i2, i2 = temp;
1858 added_links_insn = 0;
1860 /* First check for one important special-case that the code below will
1861 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1862 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1863 we may be able to replace that destination with the destination of I3.
1864 This occurs in the common code where we compute both a quotient and
1865 remainder into a structure, in which case we want to do the computation
1866 directly into the structure to avoid register-register copies.
1868 Note that this case handles both multiple sets in I2 and also
1869 cases where I2 has a number of CLOBBER or PARALLELs.
1871 We make very conservative checks below and only try to handle the
1872 most common cases of this. For example, we only handle the case
1873 where I2 and I3 are adjacent to avoid making difficult register
1876 if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
1877 && REG_P (SET_SRC (PATTERN (i3)))
1878 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1879 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1880 && GET_CODE (PATTERN (i2)) == PARALLEL
1881 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1882 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1883 below would need to check what is inside (and reg_overlap_mentioned_p
1884 doesn't support those codes anyway). Don't allow those destinations;
1885 the resulting insn isn't likely to be recognized anyway. */
1886 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1887 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1888 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1889 SET_DEST (PATTERN (i3)))
1890 && next_real_insn (i2) == i3)
1892 rtx p2 = PATTERN (i2);
1894 /* Make sure that the destination of I3,
1895 which we are going to substitute into one output of I2,
1896 is not used within another output of I2. We must avoid making this:
1897 (parallel [(set (mem (reg 69)) ...)
1898 (set (reg 69) ...)])
1899 which is not well-defined as to order of actions.
1900 (Besides, reload can't handle output reloads for this.)
1902 The problem can also happen if the dest of I3 is a memory ref,
1903 if another dest in I2 is an indirect memory ref. */
1904 for (i = 0; i < XVECLEN (p2, 0); i++)
1905 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1906 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1907 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1908 SET_DEST (XVECEXP (p2, 0, i))))
1911 if (i == XVECLEN (p2, 0))
1912 for (i = 0; i < XVECLEN (p2, 0); i++)
1913 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1914 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1915 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1920 subst_low_cuid = INSN_CUID (i2);
1922 added_sets_2 = added_sets_1 = 0;
1923 i2dest = SET_SRC (PATTERN (i3));
1924 i2dest_killed = dead_or_set_p (i2, i2dest);
1926 /* Replace the dest in I2 with our dest and make the resulting
1927 insn the new pattern for I3. Then skip to where we
1928 validate the pattern. Everything was set up above. */
1929 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1930 SET_DEST (PATTERN (i3)));
1933 i3_subst_into_i2 = 1;
1934 goto validate_replacement;
1938 /* If I2 is setting a pseudo to a constant and I3 is setting some
1939 sub-part of it to another constant, merge them by making a new
1942 && (temp = single_set (i2)) != 0
1943 && (GET_CODE (SET_SRC (temp)) == CONST_INT
1944 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
1945 && GET_CODE (PATTERN (i3)) == SET
1946 && (GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT
1947 || GET_CODE (SET_SRC (PATTERN (i3))) == CONST_DOUBLE)
1948 && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp)))
1950 rtx dest = SET_DEST (PATTERN (i3));
1954 if (GET_CODE (dest) == STRICT_LOW_PART)
1956 width = GET_MODE_BITSIZE (GET_MODE (XEXP (dest, 0)));
1959 else if (GET_CODE (dest) == ZERO_EXTRACT)
1961 if (GET_CODE (XEXP (dest, 1)) == CONST_INT
1962 && GET_CODE (XEXP (dest, 2)) == CONST_INT)
1964 width = INTVAL (XEXP (dest, 1));
1965 offset = INTVAL (XEXP (dest, 2));
1967 if (BITS_BIG_ENDIAN)
1968 offset = GET_MODE_BITSIZE (GET_MODE (XEXP (dest, 0)))
1972 else if (subreg_lowpart_p (dest))
1974 width = GET_MODE_BITSIZE (GET_MODE (dest));
1977 /* ??? Preserve the original logic to handle setting the high word
1978 of double-word pseudos, where inner is half the size of outer
1979 but not the lowpart. This could be generalized by handling
1980 SUBREG_BYTE, WORDS_BIG_ENDIAN and BYTES_BIG_ENDIAN ourselves.
1981 Unfortunately this logic is tricky to get right and probably
1982 not worth the effort. */
1983 else if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
1984 == 2 * GET_MODE_BITSIZE (GET_MODE (dest)))
1986 width = GET_MODE_BITSIZE (GET_MODE (dest));
1992 HOST_WIDE_INT mhi, ohi, ihi;
1993 HOST_WIDE_INT mlo, olo, ilo;
1994 rtx inner = SET_SRC (PATTERN (i3));
1995 rtx outer = SET_SRC (temp);
1997 if (GET_CODE (outer) == CONST_INT)
1999 olo = INTVAL (outer);
2000 ohi = olo < 0 ? -1 : 0;
2004 olo = CONST_DOUBLE_LOW (outer);
2005 ohi = CONST_DOUBLE_HIGH (outer);
2008 if (GET_CODE (inner) == CONST_INT)
2010 ilo = INTVAL (inner);
2011 ihi = ilo < 0 ? -1 : 0;
2015 ilo = CONST_DOUBLE_LOW (inner);
2016 ihi = CONST_DOUBLE_HIGH (inner);
2019 if (width < HOST_BITS_PER_WIDE_INT)
2021 mlo = ((unsigned HOST_WIDE_INT) 1 << width) - 1;
2024 else if (width < HOST_BITS_PER_WIDE_INT * 2)
2026 mhi = ((unsigned HOST_WIDE_INT) 1
2027 << (width - HOST_BITS_PER_WIDE_INT)) - 1;
2039 if (offset >= HOST_BITS_PER_WIDE_INT)
2041 mhi = mlo << (offset - HOST_BITS_PER_WIDE_INT);
2043 ihi = ilo << (offset - HOST_BITS_PER_WIDE_INT);
2046 else if (offset > 0)
2048 mhi = (mhi << offset) | ((unsigned HOST_WIDE_INT) mlo
2049 >> (HOST_BITS_PER_WIDE_INT - offset));
2050 mlo = mlo << offset;
2051 ihi = (ihi << offset) | ((unsigned HOST_WIDE_INT) ilo
2052 >> (HOST_BITS_PER_WIDE_INT - offset));
2053 ilo = ilo << offset;
2056 olo = (olo & ~mlo) | ilo;
2057 ohi = (ohi & ~mhi) | ihi;
2061 subst_low_cuid = INSN_CUID (i2);
2062 added_sets_2 = added_sets_1 = 0;
2063 i2dest = SET_DEST (temp);
2064 i2dest_killed = dead_or_set_p (i2, i2dest);
2066 SUBST (SET_SRC (temp),
2067 immed_double_const (olo, ohi, GET_MODE (SET_DEST (temp))));
2069 newpat = PATTERN (i2);
2070 goto validate_replacement;
2075 /* If we have no I1 and I2 looks like:
2076 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2078 make up a dummy I1 that is
2081 (set (reg:CC X) (compare:CC Y (const_int 0)))
2083 (We can ignore any trailing CLOBBERs.)
2085 This undoes a previous combination and allows us to match a branch-and-
2088 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
2089 && XVECLEN (PATTERN (i2), 0) >= 2
2090 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
2091 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2093 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2094 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2095 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
2096 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
2097 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2098 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
2100 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
2101 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
2106 /* We make I1 with the same INSN_UID as I2. This gives it
2107 the same INSN_CUID for value tracking. Our fake I1 will
2108 never appear in the insn stream so giving it the same INSN_UID
2109 as I2 will not cause a problem. */
2111 i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
2112 BLOCK_FOR_INSN (i2), INSN_LOCATOR (i2),
2113 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
2116 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2117 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2118 SET_DEST (PATTERN (i1)));
2123 /* Verify that I2 and I1 are valid for combining. */
2124 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
2125 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
2131 /* Record whether I2DEST is used in I2SRC and similarly for the other
2132 cases. Knowing this will help in register status updating below. */
2133 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2134 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2135 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2136 i2dest_killed = dead_or_set_p (i2, i2dest);
2137 i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2139 /* See if I1 directly feeds into I3. It does if I1DEST is not used
2141 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
2143 /* Ensure that I3's pattern can be the destination of combines. */
2144 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
2145 i1 && i2dest_in_i1src && i1_feeds_i3,
2152 /* See if any of the insns is a MULT operation. Unless one is, we will
2153 reject a combination that is, since it must be slower. Be conservative
2155 if (GET_CODE (i2src) == MULT
2156 || (i1 != 0 && GET_CODE (i1src) == MULT)
2157 || (GET_CODE (PATTERN (i3)) == SET
2158 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
2161 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2162 We used to do this EXCEPT in one case: I3 has a post-inc in an
2163 output operand. However, that exception can give rise to insns like
2165 which is a famous insn on the PDP-11 where the value of r3 used as the
2166 source was model-dependent. Avoid this sort of thing. */
2169 if (!(GET_CODE (PATTERN (i3)) == SET
2170 && REG_P (SET_SRC (PATTERN (i3)))
2171 && MEM_P (SET_DEST (PATTERN (i3)))
2172 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
2173 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
2174 /* It's not the exception. */
2177 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
2178 if (REG_NOTE_KIND (link) == REG_INC
2179 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
2181 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
2188 /* See if the SETs in I1 or I2 need to be kept around in the merged
2189 instruction: whenever the value set there is still needed past I3.
2190 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2192 For the SET in I1, we have two cases: If I1 and I2 independently
2193 feed into I3, the set in I1 needs to be kept around if I1DEST dies
2194 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2195 in I1 needs to be kept around unless I1DEST dies or is set in either
2196 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
2197 I1DEST. If so, we know I1 feeds into I2. */
2199 added_sets_2 = ! dead_or_set_p (i3, i2dest);
2202 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
2203 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
2205 /* If the set in I2 needs to be kept around, we must make a copy of
2206 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2207 PATTERN (I2), we are only substituting for the original I1DEST, not into
2208 an already-substituted copy. This also prevents making self-referential
2209 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2212 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
2213 ? gen_rtx_SET (VOIDmode, i2dest, i2src)
2217 i2pat = copy_rtx (i2pat);
2221 /* Substitute in the latest insn for the regs set by the earlier ones. */
2223 maxreg = max_reg_num ();
2228 /* Many machines that don't use CC0 have insns that can both perform an
2229 arithmetic operation and set the condition code. These operations will
2230 be represented as a PARALLEL with the first element of the vector
2231 being a COMPARE of an arithmetic operation with the constant zero.
2232 The second element of the vector will set some pseudo to the result
2233 of the same arithmetic operation. If we simplify the COMPARE, we won't
2234 match such a pattern and so will generate an extra insn. Here we test
2235 for this case, where both the comparison and the operation result are
2236 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2237 I2SRC. Later we will make the PARALLEL that contains I2. */
2239 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
2240 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
2241 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
2242 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
2244 #ifdef SELECT_CC_MODE
2246 enum machine_mode compare_mode;
2249 newpat = PATTERN (i3);
2250 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
2254 #ifdef SELECT_CC_MODE
2255 /* See if a COMPARE with the operand we substituted in should be done
2256 with the mode that is currently being used. If not, do the same
2257 processing we do in `subst' for a SET; namely, if the destination
2258 is used only once, try to replace it with a register of the proper
2259 mode and also replace the COMPARE. */
2260 if (undobuf.other_insn == 0
2261 && (cc_use = find_single_use (SET_DEST (newpat), i3,
2262 &undobuf.other_insn))
2263 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
2265 != GET_MODE (SET_DEST (newpat))))
2267 if (can_change_dest_mode(SET_DEST (newpat), added_sets_2,
2270 unsigned int regno = REGNO (SET_DEST (newpat));
2273 if (regno < FIRST_PSEUDO_REGISTER)
2274 new_dest = gen_rtx_REG (compare_mode, regno);
2277 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
2278 new_dest = regno_reg_rtx[regno];
2281 SUBST (SET_DEST (newpat), new_dest);
2282 SUBST (XEXP (*cc_use, 0), new_dest);
2283 SUBST (SET_SRC (newpat),
2284 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
2287 undobuf.other_insn = 0;
2294 /* It is possible that the source of I2 or I1 may be performing
2295 an unneeded operation, such as a ZERO_EXTEND of something
2296 that is known to have the high part zero. Handle that case
2297 by letting subst look at the innermost one of them.
2299 Another way to do this would be to have a function that tries
2300 to simplify a single insn instead of merging two or more
2301 insns. We don't do this because of the potential of infinite
2302 loops and because of the potential extra memory required.
2303 However, doing it the way we are is a bit of a kludge and
2304 doesn't catch all cases.
2306 But only do this if -fexpensive-optimizations since it slows
2307 things down and doesn't usually win.
2309 This is not done in the COMPARE case above because the
2310 unmodified I2PAT is used in the PARALLEL and so a pattern
2311 with a modified I2SRC would not match. */
2313 if (flag_expensive_optimizations)
2315 /* Pass pc_rtx so no substitutions are done, just
2319 subst_low_cuid = INSN_CUID (i1);
2320 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
2324 subst_low_cuid = INSN_CUID (i2);
2325 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
2329 n_occurrences = 0; /* `subst' counts here */
2331 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
2332 need to make a unique copy of I2SRC each time we substitute it
2333 to avoid self-referential rtl. */
2335 subst_low_cuid = INSN_CUID (i2);
2336 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
2337 ! i1_feeds_i3 && i1dest_in_i1src);
2340 /* Record whether i2's body now appears within i3's body. */
2341 i2_is_used = n_occurrences;
2344 /* If we already got a failure, don't try to do more. Otherwise,
2345 try to substitute in I1 if we have it. */
2347 if (i1 && GET_CODE (newpat) != CLOBBER)
2349 /* Before we can do this substitution, we must redo the test done
2350 above (see detailed comments there) that ensures that I1DEST
2351 isn't mentioned in any SETs in NEWPAT that are field assignments. */
2353 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
2361 subst_low_cuid = INSN_CUID (i1);
2362 newpat = subst (newpat, i1dest, i1src, 0, 0);
2366 /* Fail if an autoincrement side-effect has been duplicated. Be careful
2367 to count all the ways that I2SRC and I1SRC can be used. */
2368 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
2369 && i2_is_used + added_sets_2 > 1)
2370 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2371 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
2373 /* Fail if we tried to make a new register. */
2374 || max_reg_num () != maxreg
2375 /* Fail if we couldn't do something and have a CLOBBER. */
2376 || GET_CODE (newpat) == CLOBBER
2377 /* Fail if this new pattern is a MULT and we didn't have one before
2378 at the outer level. */
2379 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
2386 /* If the actions of the earlier insns must be kept
2387 in addition to substituting them into the latest one,
2388 we must make a new PARALLEL for the latest insn
2389 to hold additional the SETs. */
2391 if (added_sets_1 || added_sets_2)
2395 if (GET_CODE (newpat) == PARALLEL)
2397 rtvec old = XVEC (newpat, 0);
2398 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
2399 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2400 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
2401 sizeof (old->elem[0]) * old->num_elem);
2406 total_sets = 1 + added_sets_1 + added_sets_2;
2407 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2408 XVECEXP (newpat, 0, 0) = old;
2412 XVECEXP (newpat, 0, --total_sets)
2413 = (GET_CODE (PATTERN (i1)) == PARALLEL
2414 ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
2418 /* If there is no I1, use I2's body as is. We used to also not do
2419 the subst call below if I2 was substituted into I3,
2420 but that could lose a simplification. */
2422 XVECEXP (newpat, 0, --total_sets) = i2pat;
2424 /* See comment where i2pat is assigned. */
2425 XVECEXP (newpat, 0, --total_sets)
2426 = subst (i2pat, i1dest, i1src, 0, 0);
2430 /* We come here when we are replacing a destination in I2 with the
2431 destination of I3. */
2432 validate_replacement:
2434 /* Note which hard regs this insn has as inputs. */
2435 mark_used_regs_combine (newpat);
2437 /* If recog_for_combine fails, it strips existing clobbers. If we'll
2438 consider splitting this pattern, we might need these clobbers. */
2439 if (i1 && GET_CODE (newpat) == PARALLEL
2440 && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
2442 int len = XVECLEN (newpat, 0);
2444 newpat_vec_with_clobbers = rtvec_alloc (len);
2445 for (i = 0; i < len; i++)
2446 RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
2449 /* Is the result of combination a valid instruction? */
2450 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2452 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2453 the second SET's destination is a register that is unused and isn't
2454 marked as an instruction that might trap in an EH region. In that case,
2455 we just need the first SET. This can occur when simplifying a divmod
2456 insn. We *must* test for this case here because the code below that
2457 splits two independent SETs doesn't handle this case correctly when it
2458 updates the register status.
2460 It's pointless doing this if we originally had two sets, one from
2461 i3, and one from i2. Combining then splitting the parallel results
2462 in the original i2 again plus an invalid insn (which we delete).
2463 The net effect is only to move instructions around, which makes
2464 debug info less accurate.
2466 Also check the case where the first SET's destination is unused.
2467 That would not cause incorrect code, but does cause an unneeded
2470 if (insn_code_number < 0
2471 && !(added_sets_2 && i1 == 0)
2472 && GET_CODE (newpat) == PARALLEL
2473 && XVECLEN (newpat, 0) == 2
2474 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2475 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2476 && asm_noperands (newpat) < 0)
2478 rtx set0 = XVECEXP (newpat, 0, 0);
2479 rtx set1 = XVECEXP (newpat, 0, 1);
2482 if (((REG_P (SET_DEST (set1))
2483 && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
2484 || (GET_CODE (SET_DEST (set1)) == SUBREG
2485 && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
2486 && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2487 || INTVAL (XEXP (note, 0)) <= 0)
2488 && ! side_effects_p (SET_SRC (set1)))
2491 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2494 else if (((REG_P (SET_DEST (set0))
2495 && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
2496 || (GET_CODE (SET_DEST (set0)) == SUBREG
2497 && find_reg_note (i3, REG_UNUSED,
2498 SUBREG_REG (SET_DEST (set0)))))
2499 && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2500 || INTVAL (XEXP (note, 0)) <= 0)
2501 && ! side_effects_p (SET_SRC (set0)))
2504 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2506 if (insn_code_number >= 0)
2508 /* If we will be able to accept this, we have made a
2509 change to the destination of I3. This requires us to
2510 do a few adjustments. */
2512 PATTERN (i3) = newpat;
2513 adjust_for_new_dest (i3);
2518 /* If we were combining three insns and the result is a simple SET
2519 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2520 insns. There are two ways to do this. It can be split using a
2521 machine-specific method (like when you have an addition of a large
2522 constant) or by combine in the function find_split_point. */
2524 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2525 && asm_noperands (newpat) < 0)
2527 rtx m_split, *split;
2529 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2530 use I2DEST as a scratch register will help. In the latter case,
2531 convert I2DEST to the mode of the source of NEWPAT if we can. */
2533 m_split = split_insns (newpat, i3);
2535 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2536 inputs of NEWPAT. */
2538 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2539 possible to try that as a scratch reg. This would require adding
2540 more code to make it work though. */
2542 if (m_split == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
2544 enum machine_mode new_mode = GET_MODE (SET_DEST (newpat));
2546 /* First try to split using the original register as a
2547 scratch register. */
2548 m_split = split_insns (gen_rtx_PARALLEL
2550 gen_rtvec (2, newpat,
2551 gen_rtx_CLOBBER (VOIDmode,
2555 /* If that didn't work, try changing the mode of I2DEST if
2558 && new_mode != GET_MODE (i2dest)
2559 && new_mode != VOIDmode
2560 && can_change_dest_mode (i2dest, added_sets_2, new_mode))
2562 enum machine_mode old_mode = GET_MODE (i2dest);
2565 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
2566 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
2569 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode);
2570 ni2dest = regno_reg_rtx[REGNO (i2dest)];
2573 m_split = split_insns (gen_rtx_PARALLEL
2575 gen_rtvec (2, newpat,
2576 gen_rtx_CLOBBER (VOIDmode,
2581 && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2585 PUT_MODE (regno_reg_rtx[REGNO (i2dest)], old_mode);
2586 buf = undobuf.undos;
2587 undobuf.undos = buf->next;
2588 buf->next = undobuf.frees;
2589 undobuf.frees = buf;
2594 /* If recog_for_combine has discarded clobbers, try to use them
2595 again for the split. */
2596 if (m_split == 0 && newpat_vec_with_clobbers)
2598 = split_insns (gen_rtx_PARALLEL (VOIDmode,
2599 newpat_vec_with_clobbers), i3);
2601 if (m_split && NEXT_INSN (m_split) == NULL_RTX)
2603 m_split = PATTERN (m_split);
2604 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
2605 if (insn_code_number >= 0)
2608 else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
2609 && (next_real_insn (i2) == i3
2610 || ! use_crosses_set_p (PATTERN (m_split), INSN_CUID (i2))))
2613 rtx newi3pat = PATTERN (NEXT_INSN (m_split));
2614 newi2pat = PATTERN (m_split);
2616 i3set = single_set (NEXT_INSN (m_split));
2617 i2set = single_set (m_split);
2619 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2621 /* If I2 or I3 has multiple SETs, we won't know how to track
2622 register status, so don't use these insns. If I2's destination
2623 is used between I2 and I3, we also can't use these insns. */
2625 if (i2_code_number >= 0 && i2set && i3set
2626 && (next_real_insn (i2) == i3
2627 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
2628 insn_code_number = recog_for_combine (&newi3pat, i3,
2630 if (insn_code_number >= 0)
2633 /* It is possible that both insns now set the destination of I3.
2634 If so, we must show an extra use of it. */
2636 if (insn_code_number >= 0)
2638 rtx new_i3_dest = SET_DEST (i3set);
2639 rtx new_i2_dest = SET_DEST (i2set);
2641 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
2642 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
2643 || GET_CODE (new_i3_dest) == SUBREG)
2644 new_i3_dest = XEXP (new_i3_dest, 0);
2646 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
2647 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
2648 || GET_CODE (new_i2_dest) == SUBREG)
2649 new_i2_dest = XEXP (new_i2_dest, 0);
2651 if (REG_P (new_i3_dest)
2652 && REG_P (new_i2_dest)
2653 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
2654 REG_N_SETS (REGNO (new_i2_dest))++;
2658 /* If we can split it and use I2DEST, go ahead and see if that
2659 helps things be recognized. Verify that none of the registers
2660 are set between I2 and I3. */
2661 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
2665 /* We need I2DEST in the proper mode. If it is a hard register
2666 or the only use of a pseudo, we can change its mode.
2667 Make sure we don't change a hard register to have a mode that
2668 isn't valid for it, or change the number of registers. */
2669 && (GET_MODE (*split) == GET_MODE (i2dest)
2670 || GET_MODE (*split) == VOIDmode
2671 || can_change_dest_mode (i2dest, added_sets_2,
2673 && (next_real_insn (i2) == i3
2674 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
2675 /* We can't overwrite I2DEST if its value is still used by
2677 && ! reg_referenced_p (i2dest, newpat))
2679 rtx newdest = i2dest;
2680 enum rtx_code split_code = GET_CODE (*split);
2681 enum machine_mode split_mode = GET_MODE (*split);
2682 bool subst_done = false;
2683 newi2pat = NULL_RTX;
2685 /* Get NEWDEST as a register in the proper mode. We have already
2686 validated that we can do this. */
2687 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2689 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
2690 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
2693 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode);
2694 newdest = regno_reg_rtx[REGNO (i2dest)];
2698 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2699 an ASHIFT. This can occur if it was inside a PLUS and hence
2700 appeared to be a memory address. This is a kludge. */
2701 if (split_code == MULT
2702 && GET_CODE (XEXP (*split, 1)) == CONST_INT
2703 && INTVAL (XEXP (*split, 1)) > 0
2704 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
2706 SUBST (*split, gen_rtx_ASHIFT (split_mode,
2707 XEXP (*split, 0), GEN_INT (i)));
2708 /* Update split_code because we may not have a multiply
2710 split_code = GET_CODE (*split);
2713 #ifdef INSN_SCHEDULING
2714 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2715 be written as a ZERO_EXTEND. */
2716 if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
2718 #ifdef LOAD_EXTEND_OP
2719 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
2720 what it really is. */
2721 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
2723 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
2724 SUBREG_REG (*split)));
2727 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
2728 SUBREG_REG (*split)));
2732 /* Attempt to split binary operators using arithmetic identities. */
2733 if (BINARY_P (SET_SRC (newpat))
2734 && split_mode == GET_MODE (SET_SRC (newpat))
2735 && ! side_effects_p (SET_SRC (newpat)))
2737 rtx setsrc = SET_SRC (newpat);
2738 enum machine_mode mode = GET_MODE (setsrc);
2739 enum rtx_code code = GET_CODE (setsrc);
2740 rtx src_op0 = XEXP (setsrc, 0);
2741 rtx src_op1 = XEXP (setsrc, 1);
2743 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
2744 if (rtx_equal_p (src_op0, src_op1))
2746 newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0);
2747 SUBST (XEXP (setsrc, 0), newdest);
2748 SUBST (XEXP (setsrc, 1), newdest);
2751 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
2752 else if ((code == PLUS || code == MULT)
2753 && GET_CODE (src_op0) == code
2754 && GET_CODE (XEXP (src_op0, 0)) == code
2755 && (INTEGRAL_MODE_P (mode)
2756 || (FLOAT_MODE_P (mode)
2757 && flag_unsafe_math_optimizations)))
2759 rtx p = XEXP (XEXP (src_op0, 0), 0);
2760 rtx q = XEXP (XEXP (src_op0, 0), 1);
2761 rtx r = XEXP (src_op0, 1);
2764 /* Split both "((X op Y) op X) op Y" and
2765 "((X op Y) op Y) op X" as "T op T" where T is
2767 if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
2768 || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
2770 newi2pat = gen_rtx_SET (VOIDmode, newdest,
2772 SUBST (XEXP (setsrc, 0), newdest);
2773 SUBST (XEXP (setsrc, 1), newdest);
2776 /* Split "((X op X) op Y) op Y)" as "T op T" where
2778 else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
2780 rtx tmp = simplify_gen_binary (code, mode, p, r);
2781 newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp);
2782 SUBST (XEXP (setsrc, 0), newdest);
2783 SUBST (XEXP (setsrc, 1), newdest);
2791 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
2792 SUBST (*split, newdest);
2795 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2797 /* recog_for_combine might have added CLOBBERs to newi2pat.
2798 Make sure NEWPAT does not depend on the clobbered regs. */
2799 if (GET_CODE (newi2pat) == PARALLEL)
2800 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
2801 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
2803 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
2804 if (reg_overlap_mentioned_p (reg, newpat))
2811 /* If the split point was a MULT and we didn't have one before,
2812 don't use one now. */
2813 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
2814 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2818 /* Check for a case where we loaded from memory in a narrow mode and
2819 then sign extended it, but we need both registers. In that case,
2820 we have a PARALLEL with both loads from the same memory location.
2821 We can split this into a load from memory followed by a register-register
2822 copy. This saves at least one insn, more if register allocation can
2825 We cannot do this if the destination of the first assignment is a
2826 condition code register or cc0. We eliminate this case by making sure
2827 the SET_DEST and SET_SRC have the same mode.
2829 We cannot do this if the destination of the second assignment is
2830 a register that we have already assumed is zero-extended. Similarly
2831 for a SUBREG of such a register. */
2833 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2834 && GET_CODE (newpat) == PARALLEL
2835 && XVECLEN (newpat, 0) == 2
2836 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2837 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2838 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
2839 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
2840 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2841 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2842 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2843 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2845 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2846 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2847 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2849 && reg_stat[REGNO (temp)].nonzero_bits != 0
2850 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2851 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2852 && (reg_stat[REGNO (temp)].nonzero_bits
2853 != GET_MODE_MASK (word_mode))))
2854 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2855 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2857 && reg_stat[REGNO (temp)].nonzero_bits != 0
2858 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2859 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2860 && (reg_stat[REGNO (temp)].nonzero_bits
2861 != GET_MODE_MASK (word_mode)))))
2862 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2863 SET_SRC (XVECEXP (newpat, 0, 1)))
2864 && ! find_reg_note (i3, REG_UNUSED,
2865 SET_DEST (XVECEXP (newpat, 0, 0))))
2869 newi2pat = XVECEXP (newpat, 0, 0);
2870 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2871 newpat = XVECEXP (newpat, 0, 1);
2872 SUBST (SET_SRC (newpat),
2873 gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
2874 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2876 if (i2_code_number >= 0)
2877 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2879 if (insn_code_number >= 0)
2883 /* Similarly, check for a case where we have a PARALLEL of two independent
2884 SETs but we started with three insns. In this case, we can do the sets
2885 as two separate insns. This case occurs when some SET allows two
2886 other insns to combine, but the destination of that SET is still live. */
2888 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2889 && GET_CODE (newpat) == PARALLEL
2890 && XVECLEN (newpat, 0) == 2
2891 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2892 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2893 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2894 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2895 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2896 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2897 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2899 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2900 XVECEXP (newpat, 0, 0))
2901 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2902 XVECEXP (newpat, 0, 1))
2903 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
2904 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
2906 /* Normally, it doesn't matter which of the two is done first,
2907 but it does if one references cc0. In that case, it has to
2910 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2912 newi2pat = XVECEXP (newpat, 0, 0);
2913 newpat = XVECEXP (newpat, 0, 1);
2918 newi2pat = XVECEXP (newpat, 0, 1);
2919 newpat = XVECEXP (newpat, 0, 0);
2922 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2924 if (i2_code_number >= 0)
2925 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2928 /* If it still isn't recognized, fail and change things back the way they
2930 if ((insn_code_number < 0
2931 /* Is the result a reasonable ASM_OPERANDS? */
2932 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2938 /* If we had to change another insn, make sure it is valid also. */
2939 if (undobuf.other_insn)
2941 rtx other_pat = PATTERN (undobuf.other_insn);
2942 rtx new_other_notes;
2945 CLEAR_HARD_REG_SET (newpat_used_regs);
2947 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2950 if (other_code_number < 0 && ! check_asm_operands (other_pat))
2956 PATTERN (undobuf.other_insn) = other_pat;
2958 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2959 are still valid. Then add any non-duplicate notes added by
2960 recog_for_combine. */
2961 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2963 next = XEXP (note, 1);
2965 if (REG_NOTE_KIND (note) == REG_UNUSED
2966 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2968 if (REG_P (XEXP (note, 0)))
2969 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2971 remove_note (undobuf.other_insn, note);
2975 for (note = new_other_notes; note; note = XEXP (note, 1))
2976 if (REG_P (XEXP (note, 0)))
2977 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2979 distribute_notes (new_other_notes, undobuf.other_insn,
2980 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
2983 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
2984 they are adjacent to each other or not. */
2986 rtx p = prev_nonnote_insn (i3);
2987 if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
2988 && sets_cc0_p (newi2pat))
2996 /* Only allow this combination if insn_rtx_costs reports that the
2997 replacement instructions are cheaper than the originals. */
2998 if (!combine_validate_cost (i1, i2, i3, newpat, newi2pat))
3004 /* We now know that we can do this combination. Merge the insns and
3005 update the status of registers and LOG_LINKS. */
3013 /* I3 now uses what used to be its destination and which is now
3014 I2's destination. This requires us to do a few adjustments. */
3015 PATTERN (i3) = newpat;
3016 adjust_for_new_dest (i3);
3018 /* We need a LOG_LINK from I3 to I2. But we used to have one,
3021 However, some later insn might be using I2's dest and have
3022 a LOG_LINK pointing at I3. We must remove this link.
3023 The simplest way to remove the link is to point it at I1,
3024 which we know will be a NOTE. */
3026 /* newi2pat is usually a SET here; however, recog_for_combine might
3027 have added some clobbers. */
3028 if (GET_CODE (newi2pat) == PARALLEL)
3029 ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
3031 ni2dest = SET_DEST (newi2pat);
3033 for (insn = NEXT_INSN (i3);
3034 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3035 || insn != BB_HEAD (this_basic_block->next_bb));
3036 insn = NEXT_INSN (insn))
3038 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
3040 for (link = LOG_LINKS (insn); link;
3041 link = XEXP (link, 1))
3042 if (XEXP (link, 0) == i3)
3043 XEXP (link, 0) = i1;
3051 rtx i3notes, i2notes, i1notes = 0;
3052 rtx i3links, i2links, i1links = 0;
3055 /* Compute which registers we expect to eliminate. newi2pat may be setting
3056 either i3dest or i2dest, so we must check it. Also, i1dest may be the
3057 same as i3dest, in which case newi2pat may be setting i1dest. */
3058 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
3059 || i2dest_in_i2src || i2dest_in_i1src
3062 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
3063 || (newi2pat && reg_set_p (i1dest, newi2pat))
3067 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
3069 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
3070 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
3072 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
3074 /* Ensure that we do not have something that should not be shared but
3075 occurs multiple times in the new insns. Check this by first
3076 resetting all the `used' flags and then copying anything is shared. */
3078 reset_used_flags (i3notes);
3079 reset_used_flags (i2notes);
3080 reset_used_flags (i1notes);
3081 reset_used_flags (newpat);
3082 reset_used_flags (newi2pat);
3083 if (undobuf.other_insn)
3084 reset_used_flags (PATTERN (undobuf.other_insn));
3086 i3notes = copy_rtx_if_shared (i3notes);
3087 i2notes = copy_rtx_if_shared (i2notes);
3088 i1notes = copy_rtx_if_shared (i1notes);
3089 newpat = copy_rtx_if_shared (newpat);
3090 newi2pat = copy_rtx_if_shared (newi2pat);
3091 if (undobuf.other_insn)
3092 reset_used_flags (PATTERN (undobuf.other_insn));
3094 INSN_CODE (i3) = insn_code_number;
3095 PATTERN (i3) = newpat;
3097 if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
3099 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
3101 reset_used_flags (call_usage);
3102 call_usage = copy_rtx (call_usage);
3105 replace_rtx (call_usage, i2dest, i2src);
3108 replace_rtx (call_usage, i1dest, i1src);
3110 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
3113 if (undobuf.other_insn)
3114 INSN_CODE (undobuf.other_insn) = other_code_number;
3116 /* We had one special case above where I2 had more than one set and
3117 we replaced a destination of one of those sets with the destination
3118 of I3. In that case, we have to update LOG_LINKS of insns later
3119 in this basic block. Note that this (expensive) case is rare.
3121 Also, in this case, we must pretend that all REG_NOTEs for I2
3122 actually came from I3, so that REG_UNUSED notes from I2 will be
3123 properly handled. */
3125 if (i3_subst_into_i2)
3127 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
3128 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != USE
3129 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
3130 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
3131 && ! find_reg_note (i2, REG_UNUSED,
3132 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
3133 for (temp = NEXT_INSN (i2);
3134 temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3135 || BB_HEAD (this_basic_block) != temp);
3136 temp = NEXT_INSN (temp))
3137 if (temp != i3 && INSN_P (temp))
3138 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
3139 if (XEXP (link, 0) == i2)
3140 XEXP (link, 0) = i3;
3145 while (XEXP (link, 1))
3146 link = XEXP (link, 1);
3147 XEXP (link, 1) = i2notes;
3161 INSN_CODE (i2) = i2_code_number;
3162 PATTERN (i2) = newi2pat;
3165 SET_INSN_DELETED (i2);
3171 SET_INSN_DELETED (i1);
3174 /* Get death notes for everything that is now used in either I3 or
3175 I2 and used to die in a previous insn. If we built two new
3176 patterns, move from I1 to I2 then I2 to I3 so that we get the
3177 proper movement on registers that I2 modifies. */
3181 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
3182 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
3185 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
3188 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
3190 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
3193 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
3196 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
3199 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3202 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
3203 know these are REG_UNUSED and want them to go to the desired insn,
3204 so we always pass it as i3. We have not counted the notes in
3205 reg_n_deaths yet, so we need to do so now. */
3207 if (newi2pat && new_i2_notes)
3209 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
3210 if (REG_P (XEXP (temp, 0)))
3211 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
3213 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3218 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
3219 if (REG_P (XEXP (temp, 0)))
3220 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
3222 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
3225 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
3226 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
3227 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
3228 in that case, it might delete I2. Similarly for I2 and I1.
3229 Show an additional death due to the REG_DEAD note we make here. If
3230 we discard it in distribute_notes, we will decrement it again. */
3234 if (REG_P (i3dest_killed))
3235 REG_N_DEATHS (REGNO (i3dest_killed))++;
3237 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
3238 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
3240 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
3242 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
3244 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3248 if (i2dest_in_i2src)
3251 REG_N_DEATHS (REGNO (i2dest))++;
3253 if (newi2pat && reg_set_p (i2dest, newi2pat))
3254 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
3255 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3257 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
3258 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3259 NULL_RTX, NULL_RTX);
3262 if (i1dest_in_i1src)
3265 REG_N_DEATHS (REGNO (i1dest))++;
3267 if (newi2pat && reg_set_p (i1dest, newi2pat))
3268 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
3269 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3271 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
3272 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3273 NULL_RTX, NULL_RTX);
3276 distribute_links (i3links);
3277 distribute_links (i2links);
3278 distribute_links (i1links);
3283 rtx i2_insn = 0, i2_val = 0, set;
3285 /* The insn that used to set this register doesn't exist, and
3286 this life of the register may not exist either. See if one of
3287 I3's links points to an insn that sets I2DEST. If it does,
3288 that is now the last known value for I2DEST. If we don't update
3289 this and I2 set the register to a value that depended on its old
3290 contents, we will get confused. If this insn is used, thing
3291 will be set correctly in combine_instructions. */
3293 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3294 if ((set = single_set (XEXP (link, 0))) != 0
3295 && rtx_equal_p (i2dest, SET_DEST (set)))
3296 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
3298 record_value_for_reg (i2dest, i2_insn, i2_val);
3300 /* If the reg formerly set in I2 died only once and that was in I3,
3301 zero its use count so it won't make `reload' do any work. */
3303 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
3304 && ! i2dest_in_i2src)
3306 regno = REGNO (i2dest);
3307 REG_N_SETS (regno)--;
3311 if (i1 && REG_P (i1dest))
3314 rtx i1_insn = 0, i1_val = 0, set;
3316 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3317 if ((set = single_set (XEXP (link, 0))) != 0
3318 && rtx_equal_p (i1dest, SET_DEST (set)))
3319 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
3321 record_value_for_reg (i1dest, i1_insn, i1_val);
3323 regno = REGNO (i1dest);
3324 if (! added_sets_1 && ! i1dest_in_i1src)
3325 REG_N_SETS (regno)--;
3328 /* Update reg_stat[].nonzero_bits et al for any changes that may have
3329 been made to this insn. The order of
3330 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
3331 can affect nonzero_bits of newpat */
3333 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
3334 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
3336 /* Set new_direct_jump_p if a new return or simple jump instruction
3339 If I3 is now an unconditional jump, ensure that it has a
3340 BARRIER following it since it may have initially been a
3341 conditional jump. It may also be the last nonnote insn. */
3343 if (returnjump_p (i3) || any_uncondjump_p (i3))
3345 *new_direct_jump_p = 1;
3346 mark_jump_label (PATTERN (i3), i3, 0);
3348 if ((temp = next_nonnote_insn (i3)) == NULL_RTX
3349 || !BARRIER_P (temp))
3350 emit_barrier_after (i3);
3353 if (undobuf.other_insn != NULL_RTX
3354 && (returnjump_p (undobuf.other_insn)
3355 || any_uncondjump_p (undobuf.other_insn)))
3357 *new_direct_jump_p = 1;
3359 if ((temp = next_nonnote_insn (undobuf.other_insn)) == NULL_RTX
3360 || !BARRIER_P (temp))
3361 emit_barrier_after (undobuf.other_insn);
3364 /* An NOOP jump does not need barrier, but it does need cleaning up
3366 if (GET_CODE (newpat) == SET
3367 && SET_SRC (newpat) == pc_rtx
3368 && SET_DEST (newpat) == pc_rtx)
3369 *new_direct_jump_p = 1;
3372 combine_successes++;
3375 if (added_links_insn
3376 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
3377 && INSN_CUID (added_links_insn) < INSN_CUID (i3))
3378 return added_links_insn;
3380 return newi2pat ? i2 : i3;
3383 /* Undo all the modifications recorded in undobuf. */
3388 struct undo *undo, *next;
3390 for (undo = undobuf.undos; undo; undo = next)
3396 *undo->where.r = undo->old_contents.r;
3399 *undo->where.i = undo->old_contents.i;
3402 PUT_MODE (*undo->where.r, undo->old_contents.m);
3408 undo->next = undobuf.frees;
3409 undobuf.frees = undo;
3415 /* We've committed to accepting the changes we made. Move all
3416 of the undos to the free list. */
3421 struct undo *undo, *next;
3423 for (undo = undobuf.undos; undo; undo = next)
3426 undo->next = undobuf.frees;
3427 undobuf.frees = undo;
3433 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
3434 where we have an arithmetic expression and return that point. LOC will
3437 try_combine will call this function to see if an insn can be split into
3441 find_split_point (rtx *loc, rtx insn)
3444 enum rtx_code code = GET_CODE (x);
3446 unsigned HOST_WIDE_INT len = 0;
3447 HOST_WIDE_INT pos = 0;
3449 rtx inner = NULL_RTX;
3451 /* First special-case some codes. */
3455 #ifdef INSN_SCHEDULING
3456 /* If we are making a paradoxical SUBREG invalid, it becomes a split
3458 if (MEM_P (SUBREG_REG (x)))
3461 return find_split_point (&SUBREG_REG (x), insn);
3465 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
3466 using LO_SUM and HIGH. */
3467 if (GET_CODE (XEXP (x, 0)) == CONST
3468 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
3471 gen_rtx_LO_SUM (Pmode,
3472 gen_rtx_HIGH (Pmode, XEXP (x, 0)),
3474 return &XEXP (XEXP (x, 0), 0);
3478 /* If we have a PLUS whose second operand is a constant and the
3479 address is not valid, perhaps will can split it up using
3480 the machine-specific way to split large constants. We use
3481 the first pseudo-reg (one of the virtual regs) as a placeholder;
3482 it will not remain in the result. */
3483 if (GET_CODE (XEXP (x, 0)) == PLUS
3484 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3485 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
3487 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
3488 rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
3491 /* This should have produced two insns, each of which sets our
3492 placeholder. If the source of the second is a valid address,
3493 we can make put both sources together and make a split point
3497 && NEXT_INSN (seq) != NULL_RTX
3498 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
3499 && NONJUMP_INSN_P (seq)
3500 && GET_CODE (PATTERN (seq)) == SET
3501 && SET_DEST (PATTERN (seq)) == reg
3502 && ! reg_mentioned_p (reg,
3503 SET_SRC (PATTERN (seq)))
3504 && NONJUMP_INSN_P (NEXT_INSN (seq))
3505 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
3506 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
3507 && memory_address_p (GET_MODE (x),
3508 SET_SRC (PATTERN (NEXT_INSN (seq)))))
3510 rtx src1 = SET_SRC (PATTERN (seq));
3511 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
3513 /* Replace the placeholder in SRC2 with SRC1. If we can
3514 find where in SRC2 it was placed, that can become our
3515 split point and we can replace this address with SRC2.
3516 Just try two obvious places. */
3518 src2 = replace_rtx (src2, reg, src1);
3520 if (XEXP (src2, 0) == src1)
3521 split = &XEXP (src2, 0);
3522 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
3523 && XEXP (XEXP (src2, 0), 0) == src1)
3524 split = &XEXP (XEXP (src2, 0), 0);
3528 SUBST (XEXP (x, 0), src2);
3533 /* If that didn't work, perhaps the first operand is complex and
3534 needs to be computed separately, so make a split point there.
3535 This will occur on machines that just support REG + CONST
3536 and have a constant moved through some previous computation. */
3538 else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
3539 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
3540 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
3541 return &XEXP (XEXP (x, 0), 0);
3547 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
3548 ZERO_EXTRACT, the most likely reason why this doesn't match is that
3549 we need to put the operand into a register. So split at that
3552 if (SET_DEST (x) == cc0_rtx
3553 && GET_CODE (SET_SRC (x)) != COMPARE
3554 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
3555 && !OBJECT_P (SET_SRC (x))
3556 && ! (GET_CODE (SET_SRC (x)) == SUBREG
3557 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
3558 return &SET_SRC (x);
3561 /* See if we can split SET_SRC as it stands. */
3562 split = find_split_point (&SET_SRC (x), insn);
3563 if (split && split != &SET_SRC (x))
3566 /* See if we can split SET_DEST as it stands. */
3567 split = find_split_point (&SET_DEST (x), insn);
3568 if (split && split != &SET_DEST (x))
3571 /* See if this is a bitfield assignment with everything constant. If
3572 so, this is an IOR of an AND, so split it into that. */
3573 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
3574 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
3575 <= HOST_BITS_PER_WIDE_INT)
3576 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
3577 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
3578 && GET_CODE (SET_SRC (x)) == CONST_INT
3579 && ((INTVAL (XEXP (SET_DEST (x), 1))
3580 + INTVAL (XEXP (SET_DEST (x), 2)))
3581 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
3582 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
3584 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
3585 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
3586 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
3587 rtx dest = XEXP (SET_DEST (x), 0);
3588 enum machine_mode mode = GET_MODE (dest);
3589 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
3592 if (BITS_BIG_ENDIAN)
3593 pos = GET_MODE_BITSIZE (mode) - len - pos;
3595 or_mask = gen_int_mode (src << pos, mode);
3598 simplify_gen_binary (IOR, mode, dest, or_mask));
3601 rtx negmask = gen_int_mode (~(mask << pos), mode);
3603 simplify_gen_binary (IOR, mode,
3604 simplify_gen_binary (AND, mode,
3609 SUBST (SET_DEST (x), dest);
3611 split = find_split_point (&SET_SRC (x), insn);
3612 if (split && split != &SET_SRC (x))
3616 /* Otherwise, see if this is an operation that we can split into two.
3617 If so, try to split that. */
3618 code = GET_CODE (SET_SRC (x));
3623 /* If we are AND'ing with a large constant that is only a single
3624 bit and the result is only being used in a context where we
3625 need to know if it is zero or nonzero, replace it with a bit
3626 extraction. This will avoid the large constant, which might
3627 have taken more than one insn to make. If the constant were
3628 not a valid argument to the AND but took only one insn to make,
3629 this is no worse, but if it took more than one insn, it will
3632 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3633 && REG_P (XEXP (SET_SRC (x), 0))
3634 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
3635 && REG_P (SET_DEST (x))
3636 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
3637 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
3638 && XEXP (*split, 0) == SET_DEST (x)
3639 && XEXP (*split, 1) == const0_rtx)
3641 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
3642 XEXP (SET_SRC (x), 0),
3643 pos, NULL_RTX, 1, 1, 0, 0);
3644 if (extraction != 0)
3646 SUBST (SET_SRC (x), extraction);
3647 return find_split_point (loc, insn);
3653 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3654 is known to be on, this can be converted into a NEG of a shift. */
3655 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
3656 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
3657 && 1 <= (pos = exact_log2
3658 (nonzero_bits (XEXP (SET_SRC (x), 0),
3659 GET_MODE (XEXP (SET_SRC (x), 0))))))
3661 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
3665 gen_rtx_LSHIFTRT (mode,
3666 XEXP (SET_SRC (x), 0),
3669 split = find_split_point (&SET_SRC (x), insn);
3670 if (split && split != &SET_SRC (x))
3676 inner = XEXP (SET_SRC (x), 0);
3678 /* We can't optimize if either mode is a partial integer
3679 mode as we don't know how many bits are significant
3681 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
3682 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
3686 len = GET_MODE_BITSIZE (GET_MODE (inner));
3692 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3693 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
3695 inner = XEXP (SET_SRC (x), 0);
3696 len = INTVAL (XEXP (SET_SRC (x), 1));
3697 pos = INTVAL (XEXP (SET_SRC (x), 2));
3699 if (BITS_BIG_ENDIAN)
3700 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
3701 unsignedp = (code == ZERO_EXTRACT);
3709 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
3711 enum machine_mode mode = GET_MODE (SET_SRC (x));
3713 /* For unsigned, we have a choice of a shift followed by an
3714 AND or two shifts. Use two shifts for field sizes where the
3715 constant might be too large. We assume here that we can
3716 always at least get 8-bit constants in an AND insn, which is
3717 true for every current RISC. */
3719 if (unsignedp && len <= 8)
3724 (mode, gen_lowpart (mode, inner),
3726 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
3728 split = find_split_point (&SET_SRC (x), insn);
3729 if (split && split != &SET_SRC (x))
3736 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
3737 gen_rtx_ASHIFT (mode,
3738 gen_lowpart (mode, inner),
3739 GEN_INT (GET_MODE_BITSIZE (mode)
3741 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
3743 split = find_split_point (&SET_SRC (x), insn);
3744 if (split && split != &SET_SRC (x))
3749 /* See if this is a simple operation with a constant as the second
3750 operand. It might be that this constant is out of range and hence
3751 could be used as a split point. */
3752 if (BINARY_P (SET_SRC (x))
3753 && CONSTANT_P (XEXP (SET_SRC (x), 1))
3754 && (OBJECT_P (XEXP (SET_SRC (x), 0))
3755 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
3756 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
3757 return &XEXP (SET_SRC (x), 1);
3759 /* Finally, see if this is a simple operation with its first operand
3760 not in a register. The operation might require this operand in a
3761 register, so return it as a split point. We can always do this
3762 because if the first operand were another operation, we would have
3763 already found it as a split point. */
3764 if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
3765 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
3766 return &XEXP (SET_SRC (x), 0);
3772 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3773 it is better to write this as (not (ior A B)) so we can split it.
3774 Similarly for IOR. */
3775 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
3778 gen_rtx_NOT (GET_MODE (x),
3779 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
3781 XEXP (XEXP (x, 0), 0),
3782 XEXP (XEXP (x, 1), 0))));
3783 return find_split_point (loc, insn);
3786 /* Many RISC machines have a large set of logical insns. If the
3787 second operand is a NOT, put it first so we will try to split the
3788 other operand first. */
3789 if (GET_CODE (XEXP (x, 1)) == NOT)
3791 rtx tem = XEXP (x, 0);
3792 SUBST (XEXP (x, 0), XEXP (x, 1));
3793 SUBST (XEXP (x, 1), tem);
3801 /* Otherwise, select our actions depending on our rtx class. */
3802 switch (GET_RTX_CLASS (code))
3804 case RTX_BITFIELD_OPS: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3806 split = find_split_point (&XEXP (x, 2), insn);
3809 /* ... fall through ... */
3811 case RTX_COMM_ARITH:
3813 case RTX_COMM_COMPARE:
3814 split = find_split_point (&XEXP (x, 1), insn);
3817 /* ... fall through ... */
3819 /* Some machines have (and (shift ...) ...) insns. If X is not
3820 an AND, but XEXP (X, 0) is, use it as our split point. */
3821 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
3822 return &XEXP (x, 0);
3824 split = find_split_point (&XEXP (x, 0), insn);
3830 /* Otherwise, we don't have a split point. */
3835 /* Throughout X, replace FROM with TO, and return the result.
3836 The result is TO if X is FROM;
3837 otherwise the result is X, but its contents may have been modified.
3838 If they were modified, a record was made in undobuf so that
3839 undo_all will (among other things) return X to its original state.
3841 If the number of changes necessary is too much to record to undo,
3842 the excess changes are not made, so the result is invalid.
3843 The changes already made can still be undone.
3844 undobuf.num_undo is incremented for such changes, so by testing that
3845 the caller can tell whether the result is valid.
3847 `n_occurrences' is incremented each time FROM is replaced.
3849 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
3851 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
3852 by copying if `n_occurrences' is nonzero. */
3855 subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy)
3857 enum rtx_code code = GET_CODE (x);
3858 enum machine_mode op0_mode = VOIDmode;
3863 /* Two expressions are equal if they are identical copies of a shared
3864 RTX or if they are both registers with the same register number
3867 #define COMBINE_RTX_EQUAL_P(X,Y) \
3869 || (REG_P (X) && REG_P (Y) \
3870 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3872 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3875 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3878 /* If X and FROM are the same register but different modes, they will
3879 not have been seen as equal above. However, flow.c will make a
3880 LOG_LINKS entry for that case. If we do nothing, we will try to
3881 rerecognize our original insn and, when it succeeds, we will
3882 delete the feeding insn, which is incorrect.
3884 So force this insn not to match in this (rare) case. */
3885 if (! in_dest && code == REG && REG_P (from)
3886 && REGNO (x) == REGNO (from))
3887 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
3889 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3890 of which may contain things that can be combined. */
3891 if (code != MEM && code != LO_SUM && OBJECT_P (x))
3894 /* It is possible to have a subexpression appear twice in the insn.
3895 Suppose that FROM is a register that appears within TO.
3896 Then, after that subexpression has been scanned once by `subst',
3897 the second time it is scanned, TO may be found. If we were
3898 to scan TO here, we would find FROM within it and create a
3899 self-referent rtl structure which is completely wrong. */
3900 if (COMBINE_RTX_EQUAL_P (x, to))
3903 /* Parallel asm_operands need special attention because all of the
3904 inputs are shared across the arms. Furthermore, unsharing the
3905 rtl results in recognition failures. Failure to handle this case
3906 specially can result in circular rtl.
3908 Solve this by doing a normal pass across the first entry of the
3909 parallel, and only processing the SET_DESTs of the subsequent
3912 if (code == PARALLEL
3913 && GET_CODE (XVECEXP (x, 0, 0)) == SET
3914 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
3916 new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3918 /* If this substitution failed, this whole thing fails. */
3919 if (GET_CODE (new) == CLOBBER
3920 && XEXP (new, 0) == const0_rtx)
3923 SUBST (XVECEXP (x, 0, 0), new);
3925 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
3927 rtx dest = SET_DEST (XVECEXP (x, 0, i));
3930 && GET_CODE (dest) != CC0
3931 && GET_CODE (dest) != PC)
3933 new = subst (dest, from, to, 0, unique_copy);
3935 /* If this substitution failed, this whole thing fails. */
3936 if (GET_CODE (new) == CLOBBER
3937 && XEXP (new, 0) == const0_rtx)
3940 SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
3946 len = GET_RTX_LENGTH (code);
3947 fmt = GET_RTX_FORMAT (code);
3949 /* We don't need to process a SET_DEST that is a register, CC0,
3950 or PC, so set up to skip this common case. All other cases
3951 where we want to suppress replacing something inside a
3952 SET_SRC are handled via the IN_DEST operand. */
3954 && (REG_P (SET_DEST (x))
3955 || GET_CODE (SET_DEST (x)) == CC0
3956 || GET_CODE (SET_DEST (x)) == PC))
3959 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3962 op0_mode = GET_MODE (XEXP (x, 0));
3964 for (i = 0; i < len; i++)
3969 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3971 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3973 new = (unique_copy && n_occurrences
3974 ? copy_rtx (to) : to);
3979 new = subst (XVECEXP (x, i, j), from, to, 0,
3982 /* If this substitution failed, this whole thing
3984 if (GET_CODE (new) == CLOBBER
3985 && XEXP (new, 0) == const0_rtx)
3989 SUBST (XVECEXP (x, i, j), new);
3992 else if (fmt[i] == 'e')
3994 /* If this is a register being set, ignore it. */
3998 && (((code == SUBREG || code == ZERO_EXTRACT)
4000 || code == STRICT_LOW_PART))
4003 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
4005 /* In general, don't install a subreg involving two
4006 modes not tieable. It can worsen register
4007 allocation, and can even make invalid reload
4008 insns, since the reg inside may need to be copied
4009 from in the outside mode, and that may be invalid
4010 if it is an fp reg copied in integer mode.
4012 We allow two exceptions to this: It is valid if
4013 it is inside another SUBREG and the mode of that
4014 SUBREG and the mode of the inside of TO is
4015 tieable and it is valid if X is a SET that copies
4018 if (GET_CODE (to) == SUBREG
4019 && ! MODES_TIEABLE_P (GET_MODE (to),
4020 GET_MODE (SUBREG_REG (to)))
4021 && ! (code == SUBREG
4022 && MODES_TIEABLE_P (GET_MODE (x),
4023 GET_MODE (SUBREG_REG (to))))
4025 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
4028 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4030 #ifdef CANNOT_CHANGE_MODE_CLASS
4033 && REGNO (to) < FIRST_PSEUDO_REGISTER
4034 && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
4037 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4040 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
4044 /* If we are in a SET_DEST, suppress most cases unless we
4045 have gone inside a MEM, in which case we want to
4046 simplify the address. We assume here that things that
4047 are actually part of the destination have their inner
4048 parts in the first expression. This is true for SUBREG,
4049 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
4050 things aside from REG and MEM that should appear in a
4052 new = subst (XEXP (x, i), from, to,
4054 && (code == SUBREG || code == STRICT_LOW_PART
4055 || code == ZERO_EXTRACT))
4057 && i == 0), unique_copy);
4059 /* If we found that we will have to reject this combination,
4060 indicate that by returning the CLOBBER ourselves, rather than
4061 an expression containing it. This will speed things up as
4062 well as prevent accidents where two CLOBBERs are considered
4063 to be equal, thus producing an incorrect simplification. */
4065 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
4068 if (GET_CODE (x) == SUBREG
4069 && (GET_CODE (new) == CONST_INT
4070 || GET_CODE (new) == CONST_DOUBLE))
4072 enum machine_mode mode = GET_MODE (x);
4074 x = simplify_subreg (GET_MODE (x), new,
4075 GET_MODE (SUBREG_REG (x)),
4078 x = gen_rtx_CLOBBER (mode, const0_rtx);
4080 else if (GET_CODE (new) == CONST_INT
4081 && GET_CODE (x) == ZERO_EXTEND)
4083 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
4084 new, GET_MODE (XEXP (x, 0)));
4088 SUBST (XEXP (x, i), new);
4093 /* Try to simplify X. If the simplification changed the code, it is likely
4094 that further simplification will help, so loop, but limit the number
4095 of repetitions that will be performed. */
4097 for (i = 0; i < 4; i++)
4099 /* If X is sufficiently simple, don't bother trying to do anything
4101 if (code != CONST_INT && code != REG && code != CLOBBER)
4102 x = combine_simplify_rtx (x, op0_mode, in_dest);
4104 if (GET_CODE (x) == code)
4107 code = GET_CODE (x);
4109 /* We no longer know the original mode of operand 0 since we
4110 have changed the form of X) */
4111 op0_mode = VOIDmode;
4117 /* Simplify X, a piece of RTL. We just operate on the expression at the
4118 outer level; call `subst' to simplify recursively. Return the new
4121 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
4122 if we are inside a SET_DEST. */
4125 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest)
4127 enum rtx_code code = GET_CODE (x);
4128 enum machine_mode mode = GET_MODE (x);
4132 /* If this is a commutative operation, put a constant last and a complex
4133 expression first. We don't need to do this for comparisons here. */
4134 if (COMMUTATIVE_ARITH_P (x)
4135 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
4138 SUBST (XEXP (x, 0), XEXP (x, 1));
4139 SUBST (XEXP (x, 1), temp);
4142 /* If this is a simple operation applied to an IF_THEN_ELSE, try
4143 applying it to the arms of the IF_THEN_ELSE. This often simplifies
4144 things. Check for cases where both arms are testing the same
4147 Don't do anything if all operands are very simple. */
4150 && ((!OBJECT_P (XEXP (x, 0))
4151 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4152 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
4153 || (!OBJECT_P (XEXP (x, 1))
4154 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
4155 && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
4157 && (!OBJECT_P (XEXP (x, 0))
4158 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4159 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
4161 rtx cond, true_rtx, false_rtx;
4163 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
4165 /* If everything is a comparison, what we have is highly unlikely
4166 to be simpler, so don't use it. */
4167 && ! (COMPARISON_P (x)
4168 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
4170 rtx cop1 = const0_rtx;
4171 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
4173 if (cond_code == NE && COMPARISON_P (cond))
4176 /* Simplify the alternative arms; this may collapse the true and
4177 false arms to store-flag values. Be careful to use copy_rtx
4178 here since true_rtx or false_rtx might share RTL with x as a
4179 result of the if_then_else_cond call above. */
4180 true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0);
4181 false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0);
4183 /* If true_rtx and false_rtx are not general_operands, an if_then_else
4184 is unlikely to be simpler. */
4185 if (general_operand (true_rtx, VOIDmode)
4186 && general_operand (false_rtx, VOIDmode))
4188 enum rtx_code reversed;
4190 /* Restarting if we generate a store-flag expression will cause
4191 us to loop. Just drop through in this case. */
4193 /* If the result values are STORE_FLAG_VALUE and zero, we can
4194 just make the comparison operation. */
4195 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
4196 x = simplify_gen_relational (cond_code, mode, VOIDmode,
4198 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
4199 && ((reversed = reversed_comparison_code_parts
4200 (cond_code, cond, cop1, NULL))
4202 x = simplify_gen_relational (reversed, mode, VOIDmode,
4205 /* Likewise, we can make the negate of a comparison operation
4206 if the result values are - STORE_FLAG_VALUE and zero. */
4207 else if (GET_CODE (true_rtx) == CONST_INT
4208 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
4209 && false_rtx == const0_rtx)
4210 x = simplify_gen_unary (NEG, mode,
4211 simplify_gen_relational (cond_code,
4215 else if (GET_CODE (false_rtx) == CONST_INT
4216 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
4217 && true_rtx == const0_rtx
4218 && ((reversed = reversed_comparison_code_parts
4219 (cond_code, cond, cop1, NULL))
4221 x = simplify_gen_unary (NEG, mode,
4222 simplify_gen_relational (reversed,
4227 return gen_rtx_IF_THEN_ELSE (mode,
4228 simplify_gen_relational (cond_code,
4233 true_rtx, false_rtx);
4235 code = GET_CODE (x);
4236 op0_mode = VOIDmode;
4241 /* Try to fold this expression in case we have constants that weren't
4244 switch (GET_RTX_CLASS (code))
4247 if (op0_mode == VOIDmode)
4248 op0_mode = GET_MODE (XEXP (x, 0));
4249 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
4252 case RTX_COMM_COMPARE:
4254 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
4255 if (cmp_mode == VOIDmode)
4257 cmp_mode = GET_MODE (XEXP (x, 1));
4258 if (cmp_mode == VOIDmode)
4259 cmp_mode = op0_mode;
4261 temp = simplify_relational_operation (code, mode, cmp_mode,
4262 XEXP (x, 0), XEXP (x, 1));
4265 case RTX_COMM_ARITH:
4267 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
4269 case RTX_BITFIELD_OPS:
4271 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
4272 XEXP (x, 1), XEXP (x, 2));
4281 code = GET_CODE (temp);
4282 op0_mode = VOIDmode;
4283 mode = GET_MODE (temp);
4286 /* First see if we can apply the inverse distributive law. */
4287 if (code == PLUS || code == MINUS
4288 || code == AND || code == IOR || code == XOR)
4290 x = apply_distributive_law (x);
4291 code = GET_CODE (x);
4292 op0_mode = VOIDmode;
4295 /* If CODE is an associative operation not otherwise handled, see if we
4296 can associate some operands. This can win if they are constants or
4297 if they are logically related (i.e. (a & b) & a). */
4298 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
4299 || code == AND || code == IOR || code == XOR
4300 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
4301 && ((INTEGRAL_MODE_P (mode) && code != DIV)
4302 || (flag_unsafe_math_optimizations && FLOAT_MODE_P (mode))))
4304 if (GET_CODE (XEXP (x, 0)) == code)
4306 rtx other = XEXP (XEXP (x, 0), 0);
4307 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
4308 rtx inner_op1 = XEXP (x, 1);
4311 /* Make sure we pass the constant operand if any as the second
4312 one if this is a commutative operation. */
4313 if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
4315 rtx tem = inner_op0;
4316 inner_op0 = inner_op1;
4319 inner = simplify_binary_operation (code == MINUS ? PLUS
4320 : code == DIV ? MULT
4322 mode, inner_op0, inner_op1);
4324 /* For commutative operations, try the other pair if that one
4326 if (inner == 0 && COMMUTATIVE_ARITH_P (x))
4328 other = XEXP (XEXP (x, 0), 1);
4329 inner = simplify_binary_operation (code, mode,
4330 XEXP (XEXP (x, 0), 0),
4335 return simplify_gen_binary (code, mode, other, inner);
4339 /* A little bit of algebraic simplification here. */
4343 /* Ensure that our address has any ASHIFTs converted to MULT in case
4344 address-recognizing predicates are called later. */
4345 temp = make_compound_operation (XEXP (x, 0), MEM);
4346 SUBST (XEXP (x, 0), temp);
4350 if (op0_mode == VOIDmode)
4351 op0_mode = GET_MODE (SUBREG_REG (x));
4353 /* See if this can be moved to simplify_subreg. */
4354 if (CONSTANT_P (SUBREG_REG (x))
4355 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
4356 /* Don't call gen_lowpart if the inner mode
4357 is VOIDmode and we cannot simplify it, as SUBREG without
4358 inner mode is invalid. */
4359 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
4360 || gen_lowpart_common (mode, SUBREG_REG (x))))
4361 return gen_lowpart (mode, SUBREG_REG (x));
4363 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
4367 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
4373 /* Don't change the mode of the MEM if that would change the meaning
4375 if (MEM_P (SUBREG_REG (x))
4376 && (MEM_VOLATILE_P (SUBREG_REG (x))
4377 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
4378 return gen_rtx_CLOBBER (mode, const0_rtx);
4380 /* Note that we cannot do any narrowing for non-constants since
4381 we might have been counting on using the fact that some bits were
4382 zero. We now do this in the SET. */
4387 temp = expand_compound_operation (XEXP (x, 0));
4389 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4390 replaced by (lshiftrt X C). This will convert
4391 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
4393 if (GET_CODE (temp) == ASHIFTRT
4394 && GET_CODE (XEXP (temp, 1)) == CONST_INT
4395 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
4396 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
4397 INTVAL (XEXP (temp, 1)));
4399 /* If X has only a single bit that might be nonzero, say, bit I, convert
4400 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4401 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4402 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4403 or a SUBREG of one since we'd be making the expression more
4404 complex if it was just a register. */
4407 && ! (GET_CODE (temp) == SUBREG
4408 && REG_P (SUBREG_REG (temp)))
4409 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
4411 rtx temp1 = simplify_shift_const
4412 (NULL_RTX, ASHIFTRT, mode,
4413 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
4414 GET_MODE_BITSIZE (mode) - 1 - i),
4415 GET_MODE_BITSIZE (mode) - 1 - i);
4417 /* If all we did was surround TEMP with the two shifts, we
4418 haven't improved anything, so don't use it. Otherwise,
4419 we are better off with TEMP1. */
4420 if (GET_CODE (temp1) != ASHIFTRT
4421 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
4422 || XEXP (XEXP (temp1, 0), 0) != temp)
4428 /* We can't handle truncation to a partial integer mode here
4429 because we don't know the real bitsize of the partial
4431 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
4434 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4435 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4436 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4438 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
4439 GET_MODE_MASK (mode), 0));
4441 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
4442 whose value is a comparison can be replaced with a subreg if
4443 STORE_FLAG_VALUE permits. */
4444 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4445 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
4446 && (temp = get_last_value (XEXP (x, 0)))
4447 && COMPARISON_P (temp))
4448 return gen_lowpart (mode, XEXP (x, 0));
4453 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4454 using cc0, in which case we want to leave it as a COMPARE
4455 so we can distinguish it from a register-register-copy. */
4456 if (XEXP (x, 1) == const0_rtx)
4459 /* x - 0 is the same as x unless x's mode has signed zeros and
4460 allows rounding towards -infinity. Under those conditions,
4462 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x, 0)))
4463 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x, 0))))
4464 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4470 /* (const (const X)) can become (const X). Do it this way rather than
4471 returning the inner CONST since CONST can be shared with a
4473 if (GET_CODE (XEXP (x, 0)) == CONST)
4474 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4479 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4480 can add in an offset. find_split_point will split this address up
4481 again if it doesn't match. */
4482 if (GET_CODE (XEXP (x, 0)) == HIGH
4483 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4489 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4490 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4491 bit-field and can be replaced by either a sign_extend or a
4492 sign_extract. The `and' may be a zero_extend and the two
4493 <c>, -<c> constants may be reversed. */
4494 if (GET_CODE (XEXP (x, 0)) == XOR
4495 && GET_CODE (XEXP (x, 1)) == CONST_INT
4496 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4497 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
4498 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4499 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4500 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4501 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4502 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4503 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4504 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4505 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4506 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4507 == (unsigned int) i + 1))))
4508 return simplify_shift_const
4509 (NULL_RTX, ASHIFTRT, mode,
4510 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4511 XEXP (XEXP (XEXP (x, 0), 0), 0),
4512 GET_MODE_BITSIZE (mode) - (i + 1)),
4513 GET_MODE_BITSIZE (mode) - (i + 1));
4515 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4516 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4517 the bitsize of the mode - 1. This allows simplification of
4518 "a = (b & 8) == 0;" */
4519 if (XEXP (x, 1) == constm1_rtx
4520 && !REG_P (XEXP (x, 0))
4521 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4522 && REG_P (SUBREG_REG (XEXP (x, 0))))
4523 && nonzero_bits (XEXP (x, 0), mode) == 1)
4524 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4525 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4526 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
4527 GET_MODE_BITSIZE (mode) - 1),
4528 GET_MODE_BITSIZE (mode) - 1);
4530 /* If we are adding two things that have no bits in common, convert
4531 the addition into an IOR. This will often be further simplified,
4532 for example in cases like ((a & 1) + (a & 2)), which can
4535 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4536 && (nonzero_bits (XEXP (x, 0), mode)
4537 & nonzero_bits (XEXP (x, 1), mode)) == 0)
4539 /* Try to simplify the expression further. */
4540 rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4541 temp = combine_simplify_rtx (tor, mode, in_dest);
4543 /* If we could, great. If not, do not go ahead with the IOR
4544 replacement, since PLUS appears in many special purpose
4545 address arithmetic instructions. */
4546 if (GET_CODE (temp) != CLOBBER && temp != tor)
4552 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4553 (and <foo> (const_int pow2-1)) */
4554 if (GET_CODE (XEXP (x, 1)) == AND
4555 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4556 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4557 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4558 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4559 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4563 /* If we have (mult (plus A B) C), apply the distributive law and then
4564 the inverse distributive law to see if things simplify. This
4565 occurs mostly in addresses, often when unrolling loops. */
4567 if (GET_CODE (XEXP (x, 0)) == PLUS)
4569 rtx result = distribute_and_simplify_rtx (x, 0);
4574 /* Try simplify a*(b/c) as (a*b)/c. */
4575 if (FLOAT_MODE_P (mode) && flag_unsafe_math_optimizations
4576 && GET_CODE (XEXP (x, 0)) == DIV)
4578 rtx tem = simplify_binary_operation (MULT, mode,
4579 XEXP (XEXP (x, 0), 0),
4582 return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
4587 /* If this is a divide by a power of two, treat it as a shift if
4588 its first operand is a shift. */
4589 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4590 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4591 && (GET_CODE (XEXP (x, 0)) == ASHIFT
4592 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4593 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4594 || GET_CODE (XEXP (x, 0)) == ROTATE
4595 || GET_CODE (XEXP (x, 0)) == ROTATERT))
4596 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
4600 case GT: case GTU: case GE: case GEU:
4601 case LT: case LTU: case LE: case LEU:
4602 case UNEQ: case LTGT:
4603 case UNGT: case UNGE:
4604 case UNLT: case UNLE:
4605 case UNORDERED: case ORDERED:
4606 /* If the first operand is a condition code, we can't do anything
4608 if (GET_CODE (XEXP (x, 0)) == COMPARE
4609 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4610 && ! CC0_P (XEXP (x, 0))))
4612 rtx op0 = XEXP (x, 0);
4613 rtx op1 = XEXP (x, 1);
4614 enum rtx_code new_code;
4616 if (GET_CODE (op0) == COMPARE)
4617 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4619 /* Simplify our comparison, if possible. */
4620 new_code = simplify_comparison (code, &op0, &op1);
4622 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4623 if only the low-order bit is possibly nonzero in X (such as when
4624 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4625 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4626 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4629 Remove any ZERO_EXTRACT we made when thinking this was a
4630 comparison. It may now be simpler to use, e.g., an AND. If a
4631 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4632 the call to make_compound_operation in the SET case. */
4634 if (STORE_FLAG_VALUE == 1
4635 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4636 && op1 == const0_rtx
4637 && mode == GET_MODE (op0)
4638 && nonzero_bits (op0, mode) == 1)
4639 return gen_lowpart (mode,
4640 expand_compound_operation (op0));
4642 else if (STORE_FLAG_VALUE == 1
4643 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4644 && op1 == const0_rtx
4645 && mode == GET_MODE (op0)
4646 && (num_sign_bit_copies (op0, mode)
4647 == GET_MODE_BITSIZE (mode)))
4649 op0 = expand_compound_operation (op0);
4650 return simplify_gen_unary (NEG, mode,
4651 gen_lowpart (mode, op0),
4655 else if (STORE_FLAG_VALUE == 1
4656 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4657 && op1 == const0_rtx
4658 && mode == GET_MODE (op0)
4659 && nonzero_bits (op0, mode) == 1)
4661 op0 = expand_compound_operation (op0);
4662 return simplify_gen_binary (XOR, mode,
4663 gen_lowpart (mode, op0),
4667 else if (STORE_FLAG_VALUE == 1
4668 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4669 && op1 == const0_rtx
4670 && mode == GET_MODE (op0)
4671 && (num_sign_bit_copies (op0, mode)
4672 == GET_MODE_BITSIZE (mode)))
4674 op0 = expand_compound_operation (op0);
4675 return plus_constant (gen_lowpart (mode, op0), 1);
4678 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4680 if (STORE_FLAG_VALUE == -1
4681 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4682 && op1 == const0_rtx
4683 && (num_sign_bit_copies (op0, mode)
4684 == GET_MODE_BITSIZE (mode)))
4685 return gen_lowpart (mode,
4686 expand_compound_operation (op0));
4688 else if (STORE_FLAG_VALUE == -1
4689 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4690 && op1 == const0_rtx
4691 && mode == GET_MODE (op0)
4692 && nonzero_bits (op0, mode) == 1)
4694 op0 = expand_compound_operation (op0);
4695 return simplify_gen_unary (NEG, mode,
4696 gen_lowpart (mode, op0),
4700 else if (STORE_FLAG_VALUE == -1
4701 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4702 && op1 == const0_rtx
4703 && mode == GET_MODE (op0)
4704 && (num_sign_bit_copies (op0, mode)
4705 == GET_MODE_BITSIZE (mode)))
4707 op0 = expand_compound_operation (op0);
4708 return simplify_gen_unary (NOT, mode,
4709 gen_lowpart (mode, op0),
4713 /* If X is 0/1, (eq X 0) is X-1. */
4714 else if (STORE_FLAG_VALUE == -1
4715 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4716 && op1 == const0_rtx
4717 && mode == GET_MODE (op0)
4718 && nonzero_bits (op0, mode) == 1)
4720 op0 = expand_compound_operation (op0);
4721 return plus_constant (gen_lowpart (mode, op0), -1);
4724 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4725 one bit that might be nonzero, we can convert (ne x 0) to
4726 (ashift x c) where C puts the bit in the sign bit. Remove any
4727 AND with STORE_FLAG_VALUE when we are done, since we are only
4728 going to test the sign bit. */
4729 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4730 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4731 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4732 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
4733 && op1 == const0_rtx
4734 && mode == GET_MODE (op0)
4735 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4737 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4738 expand_compound_operation (op0),
4739 GET_MODE_BITSIZE (mode) - 1 - i);
4740 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4746 /* If the code changed, return a whole new comparison. */
4747 if (new_code != code)
4748 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
4750 /* Otherwise, keep this operation, but maybe change its operands.
4751 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4752 SUBST (XEXP (x, 0), op0);
4753 SUBST (XEXP (x, 1), op1);
4758 return simplify_if_then_else (x);
4764 /* If we are processing SET_DEST, we are done. */
4768 return expand_compound_operation (x);
4771 return simplify_set (x);
4775 return simplify_logical (x);
4782 /* If this is a shift by a constant amount, simplify it. */
4783 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4784 return simplify_shift_const (x, code, mode, XEXP (x, 0),
4785 INTVAL (XEXP (x, 1)));
4787 else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
4789 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
4791 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4803 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4806 simplify_if_then_else (rtx x)
4808 enum machine_mode mode = GET_MODE (x);
4809 rtx cond = XEXP (x, 0);
4810 rtx true_rtx = XEXP (x, 1);
4811 rtx false_rtx = XEXP (x, 2);
4812 enum rtx_code true_code = GET_CODE (cond);
4813 int comparison_p = COMPARISON_P (cond);
4816 enum rtx_code false_code;
4819 /* Simplify storing of the truth value. */
4820 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
4821 return simplify_gen_relational (true_code, mode, VOIDmode,
4822 XEXP (cond, 0), XEXP (cond, 1));
4824 /* Also when the truth value has to be reversed. */
4826 && true_rtx == const0_rtx && false_rtx == const_true_rtx
4827 && (reversed = reversed_comparison (cond, mode)))
4830 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4831 in it is being compared against certain values. Get the true and false
4832 comparisons and see if that says anything about the value of each arm. */
4835 && ((false_code = reversed_comparison_code (cond, NULL))
4837 && REG_P (XEXP (cond, 0)))
4840 rtx from = XEXP (cond, 0);
4841 rtx true_val = XEXP (cond, 1);
4842 rtx false_val = true_val;
4845 /* If FALSE_CODE is EQ, swap the codes and arms. */
4847 if (false_code == EQ)
4849 swapped = 1, true_code = EQ, false_code = NE;
4850 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4853 /* If we are comparing against zero and the expression being tested has
4854 only a single bit that might be nonzero, that is its value when it is
4855 not equal to zero. Similarly if it is known to be -1 or 0. */
4857 if (true_code == EQ && true_val == const0_rtx
4858 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4859 false_code = EQ, false_val = GEN_INT (nzb);
4860 else if (true_code == EQ && true_val == const0_rtx
4861 && (num_sign_bit_copies (from, GET_MODE (from))
4862 == GET_MODE_BITSIZE (GET_MODE (from))))
4863 false_code = EQ, false_val = constm1_rtx;
4865 /* Now simplify an arm if we know the value of the register in the
4866 branch and it is used in the arm. Be careful due to the potential
4867 of locally-shared RTL. */
4869 if (reg_mentioned_p (from, true_rtx))
4870 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
4872 pc_rtx, pc_rtx, 0, 0);
4873 if (reg_mentioned_p (from, false_rtx))
4874 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
4876 pc_rtx, pc_rtx, 0, 0);
4878 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
4879 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
4881 true_rtx = XEXP (x, 1);
4882 false_rtx = XEXP (x, 2);
4883 true_code = GET_CODE (cond);
4886 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4887 reversed, do so to avoid needing two sets of patterns for
4888 subtract-and-branch insns. Similarly if we have a constant in the true
4889 arm, the false arm is the same as the first operand of the comparison, or
4890 the false arm is more complicated than the true arm. */
4893 && reversed_comparison_code (cond, NULL) != UNKNOWN
4894 && (true_rtx == pc_rtx
4895 || (CONSTANT_P (true_rtx)
4896 && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx)
4897 || true_rtx == const0_rtx
4898 || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
4899 || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
4900 && !OBJECT_P (false_rtx))
4901 || reg_mentioned_p (true_rtx, false_rtx)
4902 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
4904 true_code = reversed_comparison_code (cond, NULL);
4905 SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
4906 SUBST (XEXP (x, 1), false_rtx);
4907 SUBST (XEXP (x, 2), true_rtx);
4909 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4912 /* It is possible that the conditional has been simplified out. */
4913 true_code = GET_CODE (cond);
4914 comparison_p = COMPARISON_P (cond);
4917 /* If the two arms are identical, we don't need the comparison. */
4919 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
4922 /* Convert a == b ? b : a to "a". */
4923 if (true_code == EQ && ! side_effects_p (cond)
4924 && !HONOR_NANS (mode)
4925 && rtx_equal_p (XEXP (cond, 0), false_rtx)
4926 && rtx_equal_p (XEXP (cond, 1), true_rtx))
4928 else if (true_code == NE && ! side_effects_p (cond)
4929 && !HONOR_NANS (mode)
4930 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4931 && rtx_equal_p (XEXP (cond, 1), false_rtx))
4934 /* Look for cases where we have (abs x) or (neg (abs X)). */
4936 if (GET_MODE_CLASS (mode) == MODE_INT
4937 && GET_CODE (false_rtx) == NEG
4938 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
4940 && rtx_equal_p (true_rtx, XEXP (cond, 0))
4941 && ! side_effects_p (true_rtx))
4946 return simplify_gen_unary (ABS, mode, true_rtx, mode);
4950 simplify_gen_unary (NEG, mode,
4951 simplify_gen_unary (ABS, mode, true_rtx, mode),
4957 /* Look for MIN or MAX. */
4959 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4961 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4962 && rtx_equal_p (XEXP (cond, 1), false_rtx)
4963 && ! side_effects_p (cond))
4968 return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
4971 return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
4974 return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
4977 return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
4982 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4983 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4984 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4985 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4986 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4987 neither 1 or -1, but it isn't worth checking for. */
4989 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4991 && GET_MODE_CLASS (mode) == MODE_INT
4992 && ! side_effects_p (x))
4994 rtx t = make_compound_operation (true_rtx, SET);
4995 rtx f = make_compound_operation (false_rtx, SET);
4996 rtx cond_op0 = XEXP (cond, 0);
4997 rtx cond_op1 = XEXP (cond, 1);
4998 enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
4999 enum machine_mode m = mode;
5000 rtx z = 0, c1 = NULL_RTX;
5002 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
5003 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
5004 || GET_CODE (t) == ASHIFT
5005 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
5006 && rtx_equal_p (XEXP (t, 0), f))
5007 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
5009 /* If an identity-zero op is commutative, check whether there
5010 would be a match if we swapped the operands. */
5011 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
5012 || GET_CODE (t) == XOR)
5013 && rtx_equal_p (XEXP (t, 1), f))
5014 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
5015 else if (GET_CODE (t) == SIGN_EXTEND
5016 && (GET_CODE (XEXP (t, 0)) == PLUS
5017 || GET_CODE (XEXP (t, 0)) == MINUS
5018 || GET_CODE (XEXP (t, 0)) == IOR
5019 || GET_CODE (XEXP (t, 0)) == XOR
5020 || GET_CODE (XEXP (t, 0)) == ASHIFT
5021 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5022 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5023 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5024 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5025 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5026 && (num_sign_bit_copies (f, GET_MODE (f))
5028 (GET_MODE_BITSIZE (mode)
5029 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
5031 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5032 extend_op = SIGN_EXTEND;
5033 m = GET_MODE (XEXP (t, 0));
5035 else if (GET_CODE (t) == SIGN_EXTEND
5036 && (GET_CODE (XEXP (t, 0)) == PLUS
5037 || GET_CODE (XEXP (t, 0)) == IOR
5038 || GET_CODE (XEXP (t, 0)) == XOR)
5039 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5040 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5041 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5042 && (num_sign_bit_copies (f, GET_MODE (f))
5044 (GET_MODE_BITSIZE (mode)
5045 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
5047 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5048 extend_op = SIGN_EXTEND;
5049 m = GET_MODE (XEXP (t, 0));
5051 else if (GET_CODE (t) == ZERO_EXTEND
5052 && (GET_CODE (XEXP (t, 0)) == PLUS
5053 || GET_CODE (XEXP (t, 0)) == MINUS
5054 || GET_CODE (XEXP (t, 0)) == IOR
5055 || GET_CODE (XEXP (t, 0)) == XOR
5056 || GET_CODE (XEXP (t, 0)) == ASHIFT
5057 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5058 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5059 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5060 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5061 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5062 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5063 && ((nonzero_bits (f, GET_MODE (f))
5064 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
5067 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5068 extend_op = ZERO_EXTEND;
5069 m = GET_MODE (XEXP (t, 0));
5071 else if (GET_CODE (t) == ZERO_EXTEND
5072 && (GET_CODE (XEXP (t, 0)) == PLUS
5073 || GET_CODE (XEXP (t, 0)) == IOR
5074 || GET_CODE (XEXP (t, 0)) == XOR)
5075 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5076 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5077 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5078 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5079 && ((nonzero_bits (f, GET_MODE (f))
5080 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
5083 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5084 extend_op = ZERO_EXTEND;
5085 m = GET_MODE (XEXP (t, 0));
5090 temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
5091 cond_op0, cond_op1),
5092 pc_rtx, pc_rtx, 0, 0);
5093 temp = simplify_gen_binary (MULT, m, temp,
5094 simplify_gen_binary (MULT, m, c1,
5096 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
5097 temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
5099 if (extend_op != UNKNOWN)
5100 temp = simplify_gen_unary (extend_op, mode, temp, m);
5106 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5107 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5108 negation of a single bit, we can convert this operation to a shift. We
5109 can actually do this more generally, but it doesn't seem worth it. */
5111 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5112 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5113 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
5114 && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
5115 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
5116 == GET_MODE_BITSIZE (mode))
5117 && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
5119 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5120 gen_lowpart (mode, XEXP (cond, 0)), i);
5122 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
5123 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5124 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5125 && GET_MODE (XEXP (cond, 0)) == mode
5126 && (INTVAL (true_rtx) & GET_MODE_MASK (mode))
5127 == nonzero_bits (XEXP (cond, 0), mode)
5128 && (i = exact_log2 (INTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
5129 return XEXP (cond, 0);
5134 /* Simplify X, a SET expression. Return the new expression. */
5137 simplify_set (rtx x)
5139 rtx src = SET_SRC (x);
5140 rtx dest = SET_DEST (x);
5141 enum machine_mode mode
5142 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
5146 /* (set (pc) (return)) gets written as (return). */
5147 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
5150 /* Now that we know for sure which bits of SRC we are using, see if we can
5151 simplify the expression for the object knowing that we only need the
5154 if (GET_MODE_CLASS (mode) == MODE_INT
5155 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5157 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, 0);
5158 SUBST (SET_SRC (x), src);
5161 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5162 the comparison result and try to simplify it unless we already have used
5163 undobuf.other_insn. */
5164 if ((GET_MODE_CLASS (mode) == MODE_CC
5165 || GET_CODE (src) == COMPARE
5167 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
5168 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
5169 && COMPARISON_P (*cc_use)
5170 && rtx_equal_p (XEXP (*cc_use, 0), dest))
5172 enum rtx_code old_code = GET_CODE (*cc_use);
5173 enum rtx_code new_code;
5175 int other_changed = 0;
5176 enum machine_mode compare_mode = GET_MODE (dest);
5178 if (GET_CODE (src) == COMPARE)
5179 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
5181 op0 = src, op1 = CONST0_RTX (GET_MODE (src));
5183 tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
5186 new_code = old_code;
5187 else if (!CONSTANT_P (tmp))
5189 new_code = GET_CODE (tmp);
5190 op0 = XEXP (tmp, 0);
5191 op1 = XEXP (tmp, 1);
5195 rtx pat = PATTERN (other_insn);
5196 undobuf.other_insn = other_insn;
5197 SUBST (*cc_use, tmp);
5199 /* Attempt to simplify CC user. */
5200 if (GET_CODE (pat) == SET)
5202 rtx new = simplify_rtx (SET_SRC (pat));
5203 if (new != NULL_RTX)
5204 SUBST (SET_SRC (pat), new);
5207 /* Convert X into a no-op move. */
5208 SUBST (SET_DEST (x), pc_rtx);
5209 SUBST (SET_SRC (x), pc_rtx);
5213 /* Simplify our comparison, if possible. */
5214 new_code = simplify_comparison (new_code, &op0, &op1);
5216 #ifdef SELECT_CC_MODE
5217 /* If this machine has CC modes other than CCmode, check to see if we
5218 need to use a different CC mode here. */
5219 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
5220 compare_mode = GET_MODE (op0);
5222 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5225 /* If the mode changed, we have to change SET_DEST, the mode in the
5226 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5227 a hard register, just build new versions with the proper mode. If it
5228 is a pseudo, we lose unless it is only time we set the pseudo, in
5229 which case we can safely change its mode. */
5230 if (compare_mode != GET_MODE (dest))
5232 if (can_change_dest_mode (dest, 0, compare_mode))
5234 unsigned int regno = REGNO (dest);
5237 if (regno < FIRST_PSEUDO_REGISTER)
5238 new_dest = gen_rtx_REG (compare_mode, regno);
5241 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
5242 new_dest = regno_reg_rtx[regno];
5245 SUBST (SET_DEST (x), new_dest);
5246 SUBST (XEXP (*cc_use, 0), new_dest);
5253 #endif /* SELECT_CC_MODE */
5255 /* If the code changed, we have to build a new comparison in
5256 undobuf.other_insn. */
5257 if (new_code != old_code)
5259 int other_changed_previously = other_changed;
5260 unsigned HOST_WIDE_INT mask;
5262 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5266 /* If the only change we made was to change an EQ into an NE or
5267 vice versa, OP0 has only one bit that might be nonzero, and OP1
5268 is zero, check if changing the user of the condition code will
5269 produce a valid insn. If it won't, we can keep the original code
5270 in that insn by surrounding our operation with an XOR. */
5272 if (((old_code == NE && new_code == EQ)
5273 || (old_code == EQ && new_code == NE))
5274 && ! other_changed_previously && op1 == const0_rtx
5275 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5276 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5278 rtx pat = PATTERN (other_insn), note = 0;
5280 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
5281 && ! check_asm_operands (pat)))
5283 PUT_CODE (*cc_use, old_code);
5286 op0 = simplify_gen_binary (XOR, GET_MODE (op0),
5287 op0, GEN_INT (mask));
5293 undobuf.other_insn = other_insn;
5296 /* If we are now comparing against zero, change our source if
5297 needed. If we do not use cc0, we always have a COMPARE. */
5298 if (op1 == const0_rtx && dest == cc0_rtx)
5300 SUBST (SET_SRC (x), op0);
5306 /* Otherwise, if we didn't previously have a COMPARE in the
5307 correct mode, we need one. */
5308 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5310 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5313 else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
5315 SUBST(SET_SRC (x), op0);
5320 /* Otherwise, update the COMPARE if needed. */
5321 SUBST (XEXP (src, 0), op0);
5322 SUBST (XEXP (src, 1), op1);
5327 /* Get SET_SRC in a form where we have placed back any
5328 compound expressions. Then do the checks below. */
5329 src = make_compound_operation (src, SET);
5330 SUBST (SET_SRC (x), src);
5333 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5334 and X being a REG or (subreg (reg)), we may be able to convert this to
5335 (set (subreg:m2 x) (op)).
5337 We can always do this if M1 is narrower than M2 because that means that
5338 we only care about the low bits of the result.
5340 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5341 perform a narrower operation than requested since the high-order bits will
5342 be undefined. On machine where it is defined, this transformation is safe
5343 as long as M1 and M2 have the same number of words. */
5345 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5346 && !OBJECT_P (SUBREG_REG (src))
5347 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5349 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5350 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5351 #ifndef WORD_REGISTER_OPERATIONS
5352 && (GET_MODE_SIZE (GET_MODE (src))
5353 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5355 #ifdef CANNOT_CHANGE_MODE_CLASS
5356 && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
5357 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
5358 GET_MODE (SUBREG_REG (src)),
5362 || (GET_CODE (dest) == SUBREG
5363 && REG_P (SUBREG_REG (dest)))))
5365 SUBST (SET_DEST (x),
5366 gen_lowpart (GET_MODE (SUBREG_REG (src)),
5368 SUBST (SET_SRC (x), SUBREG_REG (src));
5370 src = SET_SRC (x), dest = SET_DEST (x);
5374 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5377 && GET_CODE (src) == SUBREG
5378 && subreg_lowpart_p (src)
5379 && (GET_MODE_BITSIZE (GET_MODE (src))
5380 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
5382 rtx inner = SUBREG_REG (src);
5383 enum machine_mode inner_mode = GET_MODE (inner);
5385 /* Here we make sure that we don't have a sign bit on. */
5386 if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
5387 && (nonzero_bits (inner, inner_mode)
5388 < ((unsigned HOST_WIDE_INT) 1
5389 << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
5391 SUBST (SET_SRC (x), inner);
5397 #ifdef LOAD_EXTEND_OP
5398 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5399 would require a paradoxical subreg. Replace the subreg with a
5400 zero_extend to avoid the reload that would otherwise be required. */
5402 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5403 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
5404 && SUBREG_BYTE (src) == 0
5405 && (GET_MODE_SIZE (GET_MODE (src))
5406 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5407 && MEM_P (SUBREG_REG (src)))
5410 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5411 GET_MODE (src), SUBREG_REG (src)));
5417 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5418 are comparing an item known to be 0 or -1 against 0, use a logical
5419 operation instead. Check for one of the arms being an IOR of the other
5420 arm with some value. We compute three terms to be IOR'ed together. In
5421 practice, at most two will be nonzero. Then we do the IOR's. */
5423 if (GET_CODE (dest) != PC
5424 && GET_CODE (src) == IF_THEN_ELSE
5425 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5426 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5427 && XEXP (XEXP (src, 0), 1) == const0_rtx
5428 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5429 #ifdef HAVE_conditional_move
5430 && ! can_conditionally_move_p (GET_MODE (src))
5432 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5433 GET_MODE (XEXP (XEXP (src, 0), 0)))
5434 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5435 && ! side_effects_p (src))
5437 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
5438 ? XEXP (src, 1) : XEXP (src, 2));
5439 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
5440 ? XEXP (src, 2) : XEXP (src, 1));
5441 rtx term1 = const0_rtx, term2, term3;
5443 if (GET_CODE (true_rtx) == IOR
5444 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
5445 term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
5446 else if (GET_CODE (true_rtx) == IOR
5447 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
5448 term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
5449 else if (GET_CODE (false_rtx) == IOR
5450 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
5451 term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
5452 else if (GET_CODE (false_rtx) == IOR
5453 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
5454 term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
5456 term2 = simplify_gen_binary (AND, GET_MODE (src),
5457 XEXP (XEXP (src, 0), 0), true_rtx);
5458 term3 = simplify_gen_binary (AND, GET_MODE (src),
5459 simplify_gen_unary (NOT, GET_MODE (src),
5460 XEXP (XEXP (src, 0), 0),
5465 simplify_gen_binary (IOR, GET_MODE (src),
5466 simplify_gen_binary (IOR, GET_MODE (src),
5473 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5474 whole thing fail. */
5475 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5477 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5480 /* Convert this into a field assignment operation, if possible. */
5481 return make_field_assignment (x);
5484 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5488 simplify_logical (rtx x)
5490 enum machine_mode mode = GET_MODE (x);
5491 rtx op0 = XEXP (x, 0);
5492 rtx op1 = XEXP (x, 1);
5494 switch (GET_CODE (x))
5497 /* We can call simplify_and_const_int only if we don't lose
5498 any (sign) bits when converting INTVAL (op1) to
5499 "unsigned HOST_WIDE_INT". */
5500 if (GET_CODE (op1) == CONST_INT
5501 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5502 || INTVAL (op1) > 0))
5504 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5505 if (GET_CODE (x) != AND)
5512 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
5513 apply the distributive law and then the inverse distributive
5514 law to see if things simplify. */
5515 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5517 rtx result = distribute_and_simplify_rtx (x, 0);
5521 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5523 rtx result = distribute_and_simplify_rtx (x, 1);
5530 /* If we have (ior (and A B) C), apply the distributive law and then
5531 the inverse distributive law to see if things simplify. */
5533 if (GET_CODE (op0) == AND)
5535 rtx result = distribute_and_simplify_rtx (x, 0);
5540 if (GET_CODE (op1) == AND)
5542 rtx result = distribute_and_simplify_rtx (x, 1);
5555 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5556 operations" because they can be replaced with two more basic operations.
5557 ZERO_EXTEND is also considered "compound" because it can be replaced with
5558 an AND operation, which is simpler, though only one operation.
5560 The function expand_compound_operation is called with an rtx expression
5561 and will convert it to the appropriate shifts and AND operations,
5562 simplifying at each stage.
5564 The function make_compound_operation is called to convert an expression
5565 consisting of shifts and ANDs into the equivalent compound expression.
5566 It is the inverse of this function, loosely speaking. */
5569 expand_compound_operation (rtx x)
5571 unsigned HOST_WIDE_INT pos = 0, len;
5573 unsigned int modewidth;
5576 switch (GET_CODE (x))
5581 /* We can't necessarily use a const_int for a multiword mode;
5582 it depends on implicitly extending the value.
5583 Since we don't know the right way to extend it,
5584 we can't tell whether the implicit way is right.
5586 Even for a mode that is no wider than a const_int,
5587 we can't win, because we need to sign extend one of its bits through
5588 the rest of it, and we don't know which bit. */
5589 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5592 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5593 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5594 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5595 reloaded. If not for that, MEM's would very rarely be safe.
5597 Reject MODEs bigger than a word, because we might not be able
5598 to reference a two-register group starting with an arbitrary register
5599 (and currently gen_lowpart might crash for a SUBREG). */
5601 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5604 /* Reject MODEs that aren't scalar integers because turning vector
5605 or complex modes into shifts causes problems. */
5607 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5610 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5611 /* If the inner object has VOIDmode (the only way this can happen
5612 is if it is an ASM_OPERANDS), we can't do anything since we don't
5613 know how much masking to do. */
5622 /* ... fall through ... */
5625 /* If the operand is a CLOBBER, just return it. */
5626 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5629 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5630 || GET_CODE (XEXP (x, 2)) != CONST_INT
5631 || GET_MODE (XEXP (x, 0)) == VOIDmode)
5634 /* Reject MODEs that aren't scalar integers because turning vector
5635 or complex modes into shifts causes problems. */
5637 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5640 len = INTVAL (XEXP (x, 1));
5641 pos = INTVAL (XEXP (x, 2));
5643 /* This should stay within the object being extracted, fail. */
5644 gcc_assert (len + pos <= GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))));
5646 if (BITS_BIG_ENDIAN)
5647 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5654 /* Convert sign extension to zero extension, if we know that the high
5655 bit is not set, as this is easier to optimize. It will be converted
5656 back to cheaper alternative in make_extraction. */
5657 if (GET_CODE (x) == SIGN_EXTEND
5658 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5659 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
5660 & ~(((unsigned HOST_WIDE_INT)
5661 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5665 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
5666 rtx temp2 = expand_compound_operation (temp);
5668 /* Make sure this is a profitable operation. */
5669 if (rtx_cost (x, SET) > rtx_cost (temp2, SET))
5671 else if (rtx_cost (x, SET) > rtx_cost (temp, SET))
5677 /* We can optimize some special cases of ZERO_EXTEND. */
5678 if (GET_CODE (x) == ZERO_EXTEND)
5680 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5681 know that the last value didn't have any inappropriate bits
5683 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5684 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5685 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5686 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5687 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5688 return XEXP (XEXP (x, 0), 0);
5690 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5691 if (GET_CODE (XEXP (x, 0)) == SUBREG
5692 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5693 && subreg_lowpart_p (XEXP (x, 0))
5694 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5695 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5696 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5697 return SUBREG_REG (XEXP (x, 0));
5699 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5700 is a comparison and STORE_FLAG_VALUE permits. This is like
5701 the first case, but it works even when GET_MODE (x) is larger
5702 than HOST_WIDE_INT. */
5703 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5704 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5705 && COMPARISON_P (XEXP (XEXP (x, 0), 0))
5706 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5707 <= HOST_BITS_PER_WIDE_INT)
5708 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5709 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5710 return XEXP (XEXP (x, 0), 0);
5712 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5713 if (GET_CODE (XEXP (x, 0)) == SUBREG
5714 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5715 && subreg_lowpart_p (XEXP (x, 0))
5716 && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
5717 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5718 <= HOST_BITS_PER_WIDE_INT)
5719 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5720 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5721 return SUBREG_REG (XEXP (x, 0));
5725 /* If we reach here, we want to return a pair of shifts. The inner
5726 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5727 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5728 logical depending on the value of UNSIGNEDP.
5730 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5731 converted into an AND of a shift.
5733 We must check for the case where the left shift would have a negative
5734 count. This can happen in a case like (x >> 31) & 255 on machines
5735 that can't shift by a constant. On those machines, we would first
5736 combine the shift with the AND to produce a variable-position
5737 extraction. Then the constant of 31 would be substituted in to produce
5738 a such a position. */
5740 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5741 if (modewidth + len >= pos)
5742 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5744 simplify_shift_const (NULL_RTX, ASHIFT,
5747 modewidth - pos - len),
5750 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5751 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5752 simplify_shift_const (NULL_RTX, LSHIFTRT,
5755 ((HOST_WIDE_INT) 1 << len) - 1);
5757 /* Any other cases we can't handle. */
5760 /* If we couldn't do this for some reason, return the original
5762 if (GET_CODE (tem) == CLOBBER)
5768 /* X is a SET which contains an assignment of one object into
5769 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5770 or certain SUBREGS). If possible, convert it into a series of
5773 We half-heartedly support variable positions, but do not at all
5774 support variable lengths. */
5777 expand_field_assignment (rtx x)
5780 rtx pos; /* Always counts from low bit. */
5782 rtx mask, cleared, masked;
5783 enum machine_mode compute_mode;
5785 /* Loop until we find something we can't simplify. */
5788 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5789 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5791 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5792 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5793 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
5795 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5796 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5798 inner = XEXP (SET_DEST (x), 0);
5799 len = INTVAL (XEXP (SET_DEST (x), 1));
5800 pos = XEXP (SET_DEST (x), 2);
5802 /* A constant position should stay within the width of INNER. */
5803 if (GET_CODE (pos) == CONST_INT)
5804 gcc_assert (INTVAL (pos) + len
5805 <= GET_MODE_BITSIZE (GET_MODE (inner)));
5807 if (BITS_BIG_ENDIAN)
5809 if (GET_CODE (pos) == CONST_INT)
5810 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5812 else if (GET_CODE (pos) == MINUS
5813 && GET_CODE (XEXP (pos, 1)) == CONST_INT
5814 && (INTVAL (XEXP (pos, 1))
5815 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5816 /* If position is ADJUST - X, new position is X. */
5817 pos = XEXP (pos, 0);
5819 pos = simplify_gen_binary (MINUS, GET_MODE (pos),
5820 GEN_INT (GET_MODE_BITSIZE (
5827 /* A SUBREG between two modes that occupy the same numbers of words
5828 can be done by moving the SUBREG to the source. */
5829 else if (GET_CODE (SET_DEST (x)) == SUBREG
5830 /* We need SUBREGs to compute nonzero_bits properly. */
5831 && nonzero_sign_valid
5832 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5833 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5834 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5835 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5837 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
5839 (GET_MODE (SUBREG_REG (SET_DEST (x))),
5846 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5847 inner = SUBREG_REG (inner);
5849 compute_mode = GET_MODE (inner);
5851 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
5852 if (! SCALAR_INT_MODE_P (compute_mode))
5854 enum machine_mode imode;
5856 /* Don't do anything for vector or complex integral types. */
5857 if (! FLOAT_MODE_P (compute_mode))
5860 /* Try to find an integral mode to pun with. */
5861 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
5862 if (imode == BLKmode)
5865 compute_mode = imode;
5866 inner = gen_lowpart (imode, inner);
5869 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5870 if (len >= HOST_BITS_PER_WIDE_INT)
5873 /* Now compute the equivalent expression. Make a copy of INNER
5874 for the SET_DEST in case it is a MEM into which we will substitute;
5875 we don't want shared RTL in that case. */
5876 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
5877 cleared = simplify_gen_binary (AND, compute_mode,
5878 simplify_gen_unary (NOT, compute_mode,
5879 simplify_gen_binary (ASHIFT,
5884 masked = simplify_gen_binary (ASHIFT, compute_mode,
5885 simplify_gen_binary (
5887 gen_lowpart (compute_mode, SET_SRC (x)),
5891 x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
5892 simplify_gen_binary (IOR, compute_mode,
5899 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5900 it is an RTX that represents a variable starting position; otherwise,
5901 POS is the (constant) starting bit position (counted from the LSB).
5903 UNSIGNEDP is nonzero for an unsigned reference and zero for a
5906 IN_DEST is nonzero if this is a reference in the destination of a
5907 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
5908 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5911 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
5912 ZERO_EXTRACT should be built even for bits starting at bit 0.
5914 MODE is the desired mode of the result (if IN_DEST == 0).
5916 The result is an RTX for the extraction or NULL_RTX if the target
5920 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
5921 rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
5922 int in_dest, int in_compare)
5924 /* This mode describes the size of the storage area
5925 to fetch the overall value from. Within that, we
5926 ignore the POS lowest bits, etc. */
5927 enum machine_mode is_mode = GET_MODE (inner);
5928 enum machine_mode inner_mode;
5929 enum machine_mode wanted_inner_mode;
5930 enum machine_mode wanted_inner_reg_mode = word_mode;
5931 enum machine_mode pos_mode = word_mode;
5932 enum machine_mode extraction_mode = word_mode;
5933 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
5935 rtx orig_pos_rtx = pos_rtx;
5936 HOST_WIDE_INT orig_pos;
5938 if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5940 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5941 consider just the QI as the memory to extract from.
5942 The subreg adds or removes high bits; its mode is
5943 irrelevant to the meaning of this extraction,
5944 since POS and LEN count from the lsb. */
5945 if (MEM_P (SUBREG_REG (inner)))
5946 is_mode = GET_MODE (SUBREG_REG (inner));
5947 inner = SUBREG_REG (inner);
5949 else if (GET_CODE (inner) == ASHIFT
5950 && GET_CODE (XEXP (inner, 1)) == CONST_INT
5951 && pos_rtx == 0 && pos == 0
5952 && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1)))
5954 /* We're extracting the least significant bits of an rtx
5955 (ashift X (const_int C)), where LEN > C. Extract the
5956 least significant (LEN - C) bits of X, giving an rtx
5957 whose mode is MODE, then shift it left C times. */
5958 new = make_extraction (mode, XEXP (inner, 0),
5959 0, 0, len - INTVAL (XEXP (inner, 1)),
5960 unsignedp, in_dest, in_compare);
5962 return gen_rtx_ASHIFT (mode, new, XEXP (inner, 1));
5965 inner_mode = GET_MODE (inner);
5967 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
5968 pos = INTVAL (pos_rtx), pos_rtx = 0;
5970 /* See if this can be done without an extraction. We never can if the
5971 width of the field is not the same as that of some integer mode. For
5972 registers, we can only avoid the extraction if the position is at the
5973 low-order bit and this is either not in the destination or we have the
5974 appropriate STRICT_LOW_PART operation available.
5976 For MEM, we can avoid an extract if the field starts on an appropriate
5977 boundary and we can change the mode of the memory reference. */
5979 if (tmode != BLKmode
5980 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
5982 && (inner_mode == tmode
5984 || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
5985 GET_MODE_BITSIZE (inner_mode))
5986 || reg_truncated_to_mode (tmode, inner))
5989 && have_insn_for (STRICT_LOW_PART, tmode))))
5990 || (MEM_P (inner) && pos_rtx == 0
5992 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
5993 : BITS_PER_UNIT)) == 0
5994 /* We can't do this if we are widening INNER_MODE (it
5995 may not be aligned, for one thing). */
5996 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
5997 && (inner_mode == tmode
5998 || (! mode_dependent_address_p (XEXP (inner, 0))
5999 && ! MEM_VOLATILE_P (inner))))))
6001 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6002 field. If the original and current mode are the same, we need not
6003 adjust the offset. Otherwise, we do if bytes big endian.
6005 If INNER is not a MEM, get a piece consisting of just the field
6006 of interest (in this case POS % BITS_PER_WORD must be 0). */
6010 HOST_WIDE_INT offset;
6012 /* POS counts from lsb, but make OFFSET count in memory order. */
6013 if (BYTES_BIG_ENDIAN)
6014 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
6016 offset = pos / BITS_PER_UNIT;
6018 new = adjust_address_nv (inner, tmode, offset);
6020 else if (REG_P (inner))
6022 if (tmode != inner_mode)
6024 /* We can't call gen_lowpart in a DEST since we
6025 always want a SUBREG (see below) and it would sometimes
6026 return a new hard register. */
6029 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
6031 if (WORDS_BIG_ENDIAN
6032 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
6033 final_word = ((GET_MODE_SIZE (inner_mode)
6034 - GET_MODE_SIZE (tmode))
6035 / UNITS_PER_WORD) - final_word;
6037 final_word *= UNITS_PER_WORD;
6038 if (BYTES_BIG_ENDIAN &&
6039 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
6040 final_word += (GET_MODE_SIZE (inner_mode)
6041 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
6043 /* Avoid creating invalid subregs, for example when
6044 simplifying (x>>32)&255. */
6045 if (!validate_subreg (tmode, inner_mode, inner, final_word))
6048 new = gen_rtx_SUBREG (tmode, inner, final_word);
6051 new = gen_lowpart (tmode, inner);
6057 new = force_to_mode (inner, tmode,
6058 len >= HOST_BITS_PER_WIDE_INT
6059 ? ~(unsigned HOST_WIDE_INT) 0
6060 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6063 /* If this extraction is going into the destination of a SET,
6064 make a STRICT_LOW_PART unless we made a MEM. */
6067 return (MEM_P (new) ? new
6068 : (GET_CODE (new) != SUBREG
6069 ? gen_rtx_CLOBBER (tmode, const0_rtx)
6070 : gen_rtx_STRICT_LOW_PART (VOIDmode, new)));
6075 if (GET_CODE (new) == CONST_INT)
6076 return gen_int_mode (INTVAL (new), mode);
6078 /* If we know that no extraneous bits are set, and that the high
6079 bit is not set, convert the extraction to the cheaper of
6080 sign and zero extension, that are equivalent in these cases. */
6081 if (flag_expensive_optimizations
6082 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6083 && ((nonzero_bits (new, tmode)
6084 & ~(((unsigned HOST_WIDE_INT)
6085 GET_MODE_MASK (tmode))
6089 rtx temp = gen_rtx_ZERO_EXTEND (mode, new);
6090 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new);
6092 /* Prefer ZERO_EXTENSION, since it gives more information to
6094 if (rtx_cost (temp, SET) <= rtx_cost (temp1, SET))
6099 /* Otherwise, sign- or zero-extend unless we already are in the
6102 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6106 /* Unless this is a COMPARE or we have a funny memory reference,
6107 don't do anything with zero-extending field extracts starting at
6108 the low-order bit since they are simple AND operations. */
6109 if (pos_rtx == 0 && pos == 0 && ! in_dest
6110 && ! in_compare && unsignedp)
6113 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
6114 if the position is not a constant and the length is not 1. In all
6115 other cases, we would only be going outside our object in cases when
6116 an original shift would have been undefined. */
6118 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6119 || (pos_rtx != 0 && len != 1)))
6122 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6123 and the mode for the result. */
6124 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6126 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6127 pos_mode = mode_for_extraction (EP_insv, 2);
6128 extraction_mode = mode_for_extraction (EP_insv, 3);
6131 if (! in_dest && unsignedp
6132 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6134 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6135 pos_mode = mode_for_extraction (EP_extzv, 3);
6136 extraction_mode = mode_for_extraction (EP_extzv, 0);
6139 if (! in_dest && ! unsignedp
6140 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6142 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6143 pos_mode = mode_for_extraction (EP_extv, 3);
6144 extraction_mode = mode_for_extraction (EP_extv, 0);
6147 /* Never narrow an object, since that might not be safe. */
6149 if (mode != VOIDmode
6150 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6151 extraction_mode = mode;
6153 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6154 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6155 pos_mode = GET_MODE (pos_rtx);
6157 /* If this is not from memory, the desired mode is the preferred mode
6158 for an extraction pattern's first input operand, or word_mode if there
6161 wanted_inner_mode = wanted_inner_reg_mode;
6164 /* Be careful not to go beyond the extracted object and maintain the
6165 natural alignment of the memory. */
6166 wanted_inner_mode = smallest_mode_for_size (len, MODE_INT);
6167 while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len
6168 > GET_MODE_BITSIZE (wanted_inner_mode))
6170 wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode);
6171 gcc_assert (wanted_inner_mode != VOIDmode);
6174 /* If we have to change the mode of memory and cannot, the desired mode
6175 is EXTRACTION_MODE. */
6176 if (inner_mode != wanted_inner_mode
6177 && (mode_dependent_address_p (XEXP (inner, 0))
6178 || MEM_VOLATILE_P (inner)
6180 wanted_inner_mode = extraction_mode;
6185 if (BITS_BIG_ENDIAN)
6187 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6188 BITS_BIG_ENDIAN style. If position is constant, compute new
6189 position. Otherwise, build subtraction.
6190 Note that POS is relative to the mode of the original argument.
6191 If it's a MEM we need to recompute POS relative to that.
6192 However, if we're extracting from (or inserting into) a register,
6193 we want to recompute POS relative to wanted_inner_mode. */
6194 int width = (MEM_P (inner)
6195 ? GET_MODE_BITSIZE (is_mode)
6196 : GET_MODE_BITSIZE (wanted_inner_mode));
6199 pos = width - len - pos;
6202 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6203 /* POS may be less than 0 now, but we check for that below.
6204 Note that it can only be less than 0 if !MEM_P (inner). */
6207 /* If INNER has a wider mode, and this is a constant extraction, try to
6208 make it smaller and adjust the byte to point to the byte containing
6210 if (wanted_inner_mode != VOIDmode
6211 && inner_mode != wanted_inner_mode
6213 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6215 && ! mode_dependent_address_p (XEXP (inner, 0))
6216 && ! MEM_VOLATILE_P (inner))
6220 /* The computations below will be correct if the machine is big
6221 endian in both bits and bytes or little endian in bits and bytes.
6222 If it is mixed, we must adjust. */
6224 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6225 adjust OFFSET to compensate. */
6226 if (BYTES_BIG_ENDIAN
6227 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6228 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6230 /* We can now move to the desired byte. */
6231 offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode))
6232 * GET_MODE_SIZE (wanted_inner_mode);
6233 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6235 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6236 && is_mode != wanted_inner_mode)
6237 offset = (GET_MODE_SIZE (is_mode)
6238 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6240 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6243 /* If INNER is not memory, we can always get it into the proper mode. If we
6244 are changing its mode, POS must be a constant and smaller than the size
6246 else if (!MEM_P (inner))
6248 if (GET_MODE (inner) != wanted_inner_mode
6250 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6253 inner = force_to_mode (inner, wanted_inner_mode,
6255 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6256 ? ~(unsigned HOST_WIDE_INT) 0
6257 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6262 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6263 have to zero extend. Otherwise, we can just use a SUBREG. */
6265 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6267 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6269 /* If we know that no extraneous bits are set, and that the high
6270 bit is not set, convert extraction to cheaper one - either
6271 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6273 if (flag_expensive_optimizations
6274 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6275 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6276 & ~(((unsigned HOST_WIDE_INT)
6277 GET_MODE_MASK (GET_MODE (pos_rtx)))
6281 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6283 /* Prefer ZERO_EXTENSION, since it gives more information to
6285 if (rtx_cost (temp1, SET) < rtx_cost (temp, SET))
6290 else if (pos_rtx != 0
6291 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6292 pos_rtx = gen_lowpart (pos_mode, pos_rtx);
6294 /* Make POS_RTX unless we already have it and it is correct. If we don't
6295 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6297 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6298 pos_rtx = orig_pos_rtx;
6300 else if (pos_rtx == 0)
6301 pos_rtx = GEN_INT (pos);
6303 /* Make the required operation. See if we can use existing rtx. */
6304 new = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6305 extraction_mode, inner, GEN_INT (len), pos_rtx);
6307 new = gen_lowpart (mode, new);
6312 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6313 with any other operations in X. Return X without that shift if so. */
6316 extract_left_shift (rtx x, int count)
6318 enum rtx_code code = GET_CODE (x);
6319 enum machine_mode mode = GET_MODE (x);
6325 /* This is the shift itself. If it is wide enough, we will return
6326 either the value being shifted if the shift count is equal to
6327 COUNT or a shift for the difference. */
6328 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6329 && INTVAL (XEXP (x, 1)) >= count)
6330 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6331 INTVAL (XEXP (x, 1)) - count);
6335 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6336 return simplify_gen_unary (code, mode, tem, mode);
6340 case PLUS: case IOR: case XOR: case AND:
6341 /* If we can safely shift this constant and we find the inner shift,
6342 make a new operation. */
6343 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6344 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6345 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6346 return simplify_gen_binary (code, mode, tem,
6347 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6358 /* Look at the expression rooted at X. Look for expressions
6359 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6360 Form these expressions.
6362 Return the new rtx, usually just X.
6364 Also, for machines like the VAX that don't have logical shift insns,
6365 try to convert logical to arithmetic shift operations in cases where
6366 they are equivalent. This undoes the canonicalizations to logical
6367 shifts done elsewhere.
6369 We try, as much as possible, to re-use rtl expressions to save memory.
6371 IN_CODE says what kind of expression we are processing. Normally, it is
6372 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6373 being kludges), it is MEM. When processing the arguments of a comparison
6374 or a COMPARE against zero, it is COMPARE. */
6377 make_compound_operation (rtx x, enum rtx_code in_code)
6379 enum rtx_code code = GET_CODE (x);
6380 enum machine_mode mode = GET_MODE (x);
6381 int mode_width = GET_MODE_BITSIZE (mode);
6383 enum rtx_code next_code;
6389 /* Select the code to be used in recursive calls. Once we are inside an
6390 address, we stay there. If we have a comparison, set to COMPARE,
6391 but once inside, go back to our default of SET. */
6393 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6394 : ((code == COMPARE || COMPARISON_P (x))
6395 && XEXP (x, 1) == const0_rtx) ? COMPARE
6396 : in_code == COMPARE ? SET : in_code);
6398 /* Process depending on the code of this operation. If NEW is set
6399 nonzero, it will be returned. */
6404 /* Convert shifts by constants into multiplications if inside
6406 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6407 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6408 && INTVAL (XEXP (x, 1)) >= 0)
6410 new = make_compound_operation (XEXP (x, 0), next_code);
6411 new = gen_rtx_MULT (mode, new,
6412 GEN_INT ((HOST_WIDE_INT) 1
6413 << INTVAL (XEXP (x, 1))));
6418 /* If the second operand is not a constant, we can't do anything
6420 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6423 /* If the constant is a power of two minus one and the first operand
6424 is a logical right shift, make an extraction. */
6425 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6426 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6428 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6429 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6430 0, in_code == COMPARE);
6433 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6434 else if (GET_CODE (XEXP (x, 0)) == SUBREG
6435 && subreg_lowpart_p (XEXP (x, 0))
6436 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6437 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6439 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6441 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6442 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6443 0, in_code == COMPARE);
6445 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6446 else if ((GET_CODE (XEXP (x, 0)) == XOR
6447 || GET_CODE (XEXP (x, 0)) == IOR)
6448 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6449 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6450 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6452 /* Apply the distributive law, and then try to make extractions. */
6453 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
6454 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6456 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6458 new = make_compound_operation (new, in_code);
6461 /* If we are have (and (rotate X C) M) and C is larger than the number
6462 of bits in M, this is an extraction. */
6464 else if (GET_CODE (XEXP (x, 0)) == ROTATE
6465 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6466 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6467 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6469 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6470 new = make_extraction (mode, new,
6471 (GET_MODE_BITSIZE (mode)
6472 - INTVAL (XEXP (XEXP (x, 0), 1))),
6473 NULL_RTX, i, 1, 0, in_code == COMPARE);
6476 /* On machines without logical shifts, if the operand of the AND is
6477 a logical shift and our mask turns off all the propagated sign
6478 bits, we can replace the logical shift with an arithmetic shift. */
6479 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6480 && !have_insn_for (LSHIFTRT, mode)
6481 && have_insn_for (ASHIFTRT, mode)
6482 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6483 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6484 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6485 && mode_width <= HOST_BITS_PER_WIDE_INT)
6487 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6489 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6490 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6492 gen_rtx_ASHIFTRT (mode,
6493 make_compound_operation
6494 (XEXP (XEXP (x, 0), 0), next_code),
6495 XEXP (XEXP (x, 0), 1)));
6498 /* If the constant is one less than a power of two, this might be
6499 representable by an extraction even if no shift is present.
6500 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6501 we are in a COMPARE. */
6502 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6503 new = make_extraction (mode,
6504 make_compound_operation (XEXP (x, 0),
6506 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6508 /* If we are in a comparison and this is an AND with a power of two,
6509 convert this into the appropriate bit extract. */
6510 else if (in_code == COMPARE
6511 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6512 new = make_extraction (mode,
6513 make_compound_operation (XEXP (x, 0),
6515 i, NULL_RTX, 1, 1, 0, 1);
6520 /* If the sign bit is known to be zero, replace this with an
6521 arithmetic shift. */
6522 if (have_insn_for (ASHIFTRT, mode)
6523 && ! have_insn_for (LSHIFTRT, mode)
6524 && mode_width <= HOST_BITS_PER_WIDE_INT
6525 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6527 new = gen_rtx_ASHIFTRT (mode,
6528 make_compound_operation (XEXP (x, 0),
6534 /* ... fall through ... */
6540 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6541 this is a SIGN_EXTRACT. */
6542 if (GET_CODE (rhs) == CONST_INT
6543 && GET_CODE (lhs) == ASHIFT
6544 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6545 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6547 new = make_compound_operation (XEXP (lhs, 0), next_code);
6548 new = make_extraction (mode, new,
6549 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6550 NULL_RTX, mode_width - INTVAL (rhs),
6551 code == LSHIFTRT, 0, in_code == COMPARE);
6555 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6556 If so, try to merge the shifts into a SIGN_EXTEND. We could
6557 also do this for some cases of SIGN_EXTRACT, but it doesn't
6558 seem worth the effort; the case checked for occurs on Alpha. */
6561 && ! (GET_CODE (lhs) == SUBREG
6562 && (OBJECT_P (SUBREG_REG (lhs))))
6563 && GET_CODE (rhs) == CONST_INT
6564 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6565 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6566 new = make_extraction (mode, make_compound_operation (new, next_code),
6567 0, NULL_RTX, mode_width - INTVAL (rhs),
6568 code == LSHIFTRT, 0, in_code == COMPARE);
6573 /* Call ourselves recursively on the inner expression. If we are
6574 narrowing the object and it has a different RTL code from
6575 what it originally did, do this SUBREG as a force_to_mode. */
6577 tem = make_compound_operation (SUBREG_REG (x), in_code);
6581 simplified = simplify_subreg (GET_MODE (x), tem, GET_MODE (tem),
6587 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6588 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6589 && subreg_lowpart_p (x))
6591 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
6594 /* If we have something other than a SUBREG, we might have
6595 done an expansion, so rerun ourselves. */
6596 if (GET_CODE (newer) != SUBREG)
6597 newer = make_compound_operation (newer, in_code);
6613 x = gen_lowpart (mode, new);
6614 code = GET_CODE (x);
6617 /* Now recursively process each operand of this operation. */
6618 fmt = GET_RTX_FORMAT (code);
6619 for (i = 0; i < GET_RTX_LENGTH (code); i++)
6622 new = make_compound_operation (XEXP (x, i), next_code);
6623 SUBST (XEXP (x, i), new);
6626 /* If this is a commutative operation, the changes to the operands
6627 may have made it noncanonical. */
6628 if (COMMUTATIVE_ARITH_P (x)
6629 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
6632 SUBST (XEXP (x, 0), XEXP (x, 1));
6633 SUBST (XEXP (x, 1), tem);
6639 /* Given M see if it is a value that would select a field of bits
6640 within an item, but not the entire word. Return -1 if not.
6641 Otherwise, return the starting position of the field, where 0 is the
6644 *PLEN is set to the length of the field. */
6647 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
6649 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6650 int pos = exact_log2 (m & -m);
6654 /* Now shift off the low-order zero bits and see if we have a
6655 power of two minus 1. */
6656 len = exact_log2 ((m >> pos) + 1);
6665 /* If X refers to a register that equals REG in value, replace these
6666 references with REG. */
6668 canon_reg_for_combine (rtx x, rtx reg)
6675 enum rtx_code code = GET_CODE (x);
6676 switch (GET_RTX_CLASS (code))
6679 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
6680 if (op0 != XEXP (x, 0))
6681 return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
6686 case RTX_COMM_ARITH:
6687 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
6688 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
6689 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6690 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
6694 case RTX_COMM_COMPARE:
6695 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
6696 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
6697 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6698 return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
6699 GET_MODE (op0), op0, op1);
6703 case RTX_BITFIELD_OPS:
6704 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
6705 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
6706 op2 = canon_reg_for_combine (XEXP (x, 2), reg);
6707 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
6708 return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
6709 GET_MODE (op0), op0, op1, op2);
6714 if (rtx_equal_p (get_last_value (reg), x)
6715 || rtx_equal_p (reg, get_last_value (x)))
6724 fmt = GET_RTX_FORMAT (code);
6726 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6729 rtx op = canon_reg_for_combine (XEXP (x, i), reg);
6730 if (op != XEXP (x, i))
6740 else if (fmt[i] == 'E')
6743 for (j = 0; j < XVECLEN (x, i); j++)
6745 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
6746 if (op != XVECEXP (x, i, j))
6753 XVECEXP (x, i, j) = op;
6764 /* Return X converted to MODE. If the value is already truncated to
6765 MODE we can just return a subreg even though in the general case we
6766 would need an explicit truncation. */
6769 gen_lowpart_or_truncate (enum machine_mode mode, rtx x)
6771 if (GET_MODE_SIZE (GET_MODE (x)) <= GET_MODE_SIZE (mode)
6772 || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
6773 GET_MODE_BITSIZE (GET_MODE (x)))
6774 || (REG_P (x) && reg_truncated_to_mode (mode, x)))
6775 return gen_lowpart (mode, x);
6777 return gen_rtx_TRUNCATE (mode, x);
6780 /* See if X can be simplified knowing that we will only refer to it in
6781 MODE and will only refer to those bits that are nonzero in MASK.
6782 If other bits are being computed or if masking operations are done
6783 that select a superset of the bits in MASK, they can sometimes be
6786 Return a possibly simplified expression, but always convert X to
6787 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6789 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6790 are all off in X. This is used when X will be complemented, by either
6791 NOT, NEG, or XOR. */
6794 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
6797 enum rtx_code code = GET_CODE (x);
6798 int next_select = just_select || code == XOR || code == NOT || code == NEG;
6799 enum machine_mode op_mode;
6800 unsigned HOST_WIDE_INT fuller_mask, nonzero;
6803 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6804 code below will do the wrong thing since the mode of such an
6805 expression is VOIDmode.
6807 Also do nothing if X is a CLOBBER; this can happen if X was
6808 the return value from a call to gen_lowpart. */
6809 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
6812 /* We want to perform the operation is its present mode unless we know
6813 that the operation is valid in MODE, in which case we do the operation
6815 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6816 && have_insn_for (code, mode))
6817 ? mode : GET_MODE (x));
6819 /* It is not valid to do a right-shift in a narrower mode
6820 than the one it came in with. */
6821 if ((code == LSHIFTRT || code == ASHIFTRT)
6822 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6823 op_mode = GET_MODE (x);
6825 /* Truncate MASK to fit OP_MODE. */
6827 mask &= GET_MODE_MASK (op_mode);
6829 /* When we have an arithmetic operation, or a shift whose count we
6830 do not know, we need to assume that all bits up to the highest-order
6831 bit in MASK will be needed. This is how we form such a mask. */
6832 if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
6833 fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
6835 fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
6838 /* Determine what bits of X are guaranteed to be (non)zero. */
6839 nonzero = nonzero_bits (x, mode);
6841 /* If none of the bits in X are needed, return a zero. */
6842 if (! just_select && (nonzero & mask) == 0)
6845 /* If X is a CONST_INT, return a new one. Do this here since the
6846 test below will fail. */
6847 if (GET_CODE (x) == CONST_INT)
6849 if (SCALAR_INT_MODE_P (mode))
6850 return gen_int_mode (INTVAL (x) & mask, mode);
6853 x = GEN_INT (INTVAL (x) & mask);
6854 return gen_lowpart_common (mode, x);
6858 /* If X is narrower than MODE and we want all the bits in X's mode, just
6859 get X in the proper mode. */
6860 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6861 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
6862 return gen_lowpart (mode, x);
6867 /* If X is a (clobber (const_int)), return it since we know we are
6868 generating something that won't match. */
6875 x = expand_compound_operation (x);
6876 if (GET_CODE (x) != code)
6877 return force_to_mode (x, mode, mask, next_select);
6881 if (subreg_lowpart_p (x)
6882 /* We can ignore the effect of this SUBREG if it narrows the mode or
6883 if the constant masks to zero all the bits the mode doesn't
6885 && ((GET_MODE_SIZE (GET_MODE (x))
6886 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6888 & GET_MODE_MASK (GET_MODE (x))
6889 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6890 return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
6894 /* If this is an AND with a constant, convert it into an AND
6895 whose constant is the AND of that constant with MASK. If it
6896 remains an AND of MASK, delete it since it is redundant. */
6898 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6900 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6901 mask & INTVAL (XEXP (x, 1)));
6903 /* If X is still an AND, see if it is an AND with a mask that
6904 is just some low-order bits. If so, and it is MASK, we don't
6907 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6908 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
6912 /* If it remains an AND, try making another AND with the bits
6913 in the mode mask that aren't in MASK turned on. If the
6914 constant in the AND is wide enough, this might make a
6915 cheaper constant. */
6917 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6918 && GET_MODE_MASK (GET_MODE (x)) != mask
6919 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
6921 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6922 | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
6923 int width = GET_MODE_BITSIZE (GET_MODE (x));
6926 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
6927 number, sign extend it. */
6928 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6929 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6930 cval |= (HOST_WIDE_INT) -1 << width;
6932 y = simplify_gen_binary (AND, GET_MODE (x),
6933 XEXP (x, 0), GEN_INT (cval));
6934 if (rtx_cost (y, SET) < rtx_cost (x, SET))
6944 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6945 low-order bits (as in an alignment operation) and FOO is already
6946 aligned to that boundary, mask C1 to that boundary as well.
6947 This may eliminate that PLUS and, later, the AND. */
6950 unsigned int width = GET_MODE_BITSIZE (mode);
6951 unsigned HOST_WIDE_INT smask = mask;
6953 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6954 number, sign extend it. */
6956 if (width < HOST_BITS_PER_WIDE_INT
6957 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6958 smask |= (HOST_WIDE_INT) -1 << width;
6960 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6961 && exact_log2 (- smask) >= 0
6962 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
6963 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
6964 return force_to_mode (plus_constant (XEXP (x, 0),
6965 (INTVAL (XEXP (x, 1)) & smask)),
6966 mode, smask, next_select);
6969 /* ... fall through ... */
6972 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6973 most significant bit in MASK since carries from those bits will
6974 affect the bits we are interested in. */
6979 /* If X is (minus C Y) where C's least set bit is larger than any bit
6980 in the mask, then we may replace with (neg Y). */
6981 if (GET_CODE (XEXP (x, 0)) == CONST_INT
6982 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
6983 & -INTVAL (XEXP (x, 0))))
6986 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
6988 return force_to_mode (x, mode, mask, next_select);
6991 /* Similarly, if C contains every bit in the fuller_mask, then we may
6992 replace with (not Y). */
6993 if (GET_CODE (XEXP (x, 0)) == CONST_INT
6994 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask)
6995 == INTVAL (XEXP (x, 0))))
6997 x = simplify_gen_unary (NOT, GET_MODE (x),
6998 XEXP (x, 1), GET_MODE (x));
6999 return force_to_mode (x, mode, mask, next_select);
7007 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7008 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7009 operation which may be a bitfield extraction. Ensure that the
7010 constant we form is not wider than the mode of X. */
7012 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7013 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7014 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7015 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7016 && GET_CODE (XEXP (x, 1)) == CONST_INT
7017 && ((INTVAL (XEXP (XEXP (x, 0), 1))
7018 + floor_log2 (INTVAL (XEXP (x, 1))))
7019 < GET_MODE_BITSIZE (GET_MODE (x)))
7020 && (INTVAL (XEXP (x, 1))
7021 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
7023 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
7024 << INTVAL (XEXP (XEXP (x, 0), 1)));
7025 temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
7026 XEXP (XEXP (x, 0), 0), temp);
7027 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
7028 XEXP (XEXP (x, 0), 1));
7029 return force_to_mode (x, mode, mask, next_select);
7033 /* For most binary operations, just propagate into the operation and
7034 change the mode if we have an operation of that mode. */
7036 op0 = gen_lowpart_or_truncate (op_mode,
7037 force_to_mode (XEXP (x, 0), mode, mask,
7039 op1 = gen_lowpart_or_truncate (op_mode,
7040 force_to_mode (XEXP (x, 1), mode, mask,
7043 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7044 x = simplify_gen_binary (code, op_mode, op0, op1);
7048 /* For left shifts, do the same, but just for the first operand.
7049 However, we cannot do anything with shifts where we cannot
7050 guarantee that the counts are smaller than the size of the mode
7051 because such a count will have a different meaning in a
7054 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
7055 && INTVAL (XEXP (x, 1)) >= 0
7056 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
7057 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
7058 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
7059 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
7062 /* If the shift count is a constant and we can do arithmetic in
7063 the mode of the shift, refine which bits we need. Otherwise, use the
7064 conservative form of the mask. */
7065 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7066 && INTVAL (XEXP (x, 1)) >= 0
7067 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
7068 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7069 mask >>= INTVAL (XEXP (x, 1));
7073 op0 = gen_lowpart_or_truncate (op_mode,
7074 force_to_mode (XEXP (x, 0), op_mode,
7075 mask, next_select));
7077 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7078 x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
7082 /* Here we can only do something if the shift count is a constant,
7083 this shift constant is valid for the host, and we can do arithmetic
7086 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7087 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7088 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7090 rtx inner = XEXP (x, 0);
7091 unsigned HOST_WIDE_INT inner_mask;
7093 /* Select the mask of the bits we need for the shift operand. */
7094 inner_mask = mask << INTVAL (XEXP (x, 1));
7096 /* We can only change the mode of the shift if we can do arithmetic
7097 in the mode of the shift and INNER_MASK is no wider than the
7098 width of X's mode. */
7099 if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
7100 op_mode = GET_MODE (x);
7102 inner = force_to_mode (inner, op_mode, inner_mask, next_select);
7104 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
7105 x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
7108 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7109 shift and AND produces only copies of the sign bit (C2 is one less
7110 than a power of two), we can do this with just a shift. */
7112 if (GET_CODE (x) == LSHIFTRT
7113 && GET_CODE (XEXP (x, 1)) == CONST_INT
7114 /* The shift puts one of the sign bit copies in the least significant
7116 && ((INTVAL (XEXP (x, 1))
7117 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7118 >= GET_MODE_BITSIZE (GET_MODE (x)))
7119 && exact_log2 (mask + 1) >= 0
7120 /* Number of bits left after the shift must be more than the mask
7122 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7123 <= GET_MODE_BITSIZE (GET_MODE (x)))
7124 /* Must be more sign bit copies than the mask needs. */
7125 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7126 >= exact_log2 (mask + 1)))
7127 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7128 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7129 - exact_log2 (mask + 1)));
7134 /* If we are just looking for the sign bit, we don't need this shift at
7135 all, even if it has a variable count. */
7136 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7137 && (mask == ((unsigned HOST_WIDE_INT) 1
7138 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7139 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7141 /* If this is a shift by a constant, get a mask that contains those bits
7142 that are not copies of the sign bit. We then have two cases: If
7143 MASK only includes those bits, this can be a logical shift, which may
7144 allow simplifications. If MASK is a single-bit field not within
7145 those bits, we are requesting a copy of the sign bit and hence can
7146 shift the sign bit to the appropriate location. */
7148 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
7149 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7153 /* If the considered data is wider than HOST_WIDE_INT, we can't
7154 represent a mask for all its bits in a single scalar.
7155 But we only care about the lower bits, so calculate these. */
7157 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7159 nonzero = ~(HOST_WIDE_INT) 0;
7161 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7162 is the number of bits a full-width mask would have set.
7163 We need only shift if these are fewer than nonzero can
7164 hold. If not, we must keep all bits set in nonzero. */
7166 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7167 < HOST_BITS_PER_WIDE_INT)
7168 nonzero >>= INTVAL (XEXP (x, 1))
7169 + HOST_BITS_PER_WIDE_INT
7170 - GET_MODE_BITSIZE (GET_MODE (x)) ;
7174 nonzero = GET_MODE_MASK (GET_MODE (x));
7175 nonzero >>= INTVAL (XEXP (x, 1));
7178 if ((mask & ~nonzero) == 0)
7180 x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x),
7181 XEXP (x, 0), INTVAL (XEXP (x, 1)));
7182 if (GET_CODE (x) != ASHIFTRT)
7183 return force_to_mode (x, mode, mask, next_select);
7186 else if ((i = exact_log2 (mask)) >= 0)
7188 x = simplify_shift_const
7189 (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7190 GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7192 if (GET_CODE (x) != ASHIFTRT)
7193 return force_to_mode (x, mode, mask, next_select);
7197 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7198 even if the shift count isn't a constant. */
7200 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7201 XEXP (x, 0), XEXP (x, 1));
7205 /* If this is a zero- or sign-extension operation that just affects bits
7206 we don't care about, remove it. Be sure the call above returned
7207 something that is still a shift. */
7209 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7210 && GET_CODE (XEXP (x, 1)) == CONST_INT
7211 && INTVAL (XEXP (x, 1)) >= 0
7212 && (INTVAL (XEXP (x, 1))
7213 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7214 && GET_CODE (XEXP (x, 0)) == ASHIFT
7215 && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
7216 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7223 /* If the shift count is constant and we can do computations
7224 in the mode of X, compute where the bits we care about are.
7225 Otherwise, we can't do anything. Don't change the mode of
7226 the shift or propagate MODE into the shift, though. */
7227 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7228 && INTVAL (XEXP (x, 1)) >= 0)
7230 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7231 GET_MODE (x), GEN_INT (mask),
7233 if (temp && GET_CODE (temp) == CONST_INT)
7235 force_to_mode (XEXP (x, 0), GET_MODE (x),
7236 INTVAL (temp), next_select));
7241 /* If we just want the low-order bit, the NEG isn't needed since it
7242 won't change the low-order bit. */
7244 return force_to_mode (XEXP (x, 0), mode, mask, just_select);
7246 /* We need any bits less significant than the most significant bit in
7247 MASK since carries from those bits will affect the bits we are
7253 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7254 same as the XOR case above. Ensure that the constant we form is not
7255 wider than the mode of X. */
7257 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7258 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7259 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7260 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7261 < GET_MODE_BITSIZE (GET_MODE (x)))
7262 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7264 temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
7266 temp = simplify_gen_binary (XOR, GET_MODE (x),
7267 XEXP (XEXP (x, 0), 0), temp);
7268 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7269 temp, XEXP (XEXP (x, 0), 1));
7271 return force_to_mode (x, mode, mask, next_select);
7274 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7275 use the full mask inside the NOT. */
7279 op0 = gen_lowpart_or_truncate (op_mode,
7280 force_to_mode (XEXP (x, 0), mode, mask,
7282 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7283 x = simplify_gen_unary (code, op_mode, op0, op_mode);
7287 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7288 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7289 which is equal to STORE_FLAG_VALUE. */
7290 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7291 && GET_MODE (XEXP (x, 0)) == mode
7292 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7293 && (nonzero_bits (XEXP (x, 0), mode)
7294 == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
7295 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7300 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7301 written in a narrower mode. We play it safe and do not do so. */
7304 gen_lowpart_or_truncate (GET_MODE (x),
7305 force_to_mode (XEXP (x, 1), mode,
7306 mask, next_select)));
7308 gen_lowpart_or_truncate (GET_MODE (x),
7309 force_to_mode (XEXP (x, 2), mode,
7310 mask, next_select)));
7317 /* Ensure we return a value of the proper mode. */
7318 return gen_lowpart_or_truncate (mode, x);
7321 /* Return nonzero if X is an expression that has one of two values depending on
7322 whether some other value is zero or nonzero. In that case, we return the
7323 value that is being tested, *PTRUE is set to the value if the rtx being
7324 returned has a nonzero value, and *PFALSE is set to the other alternative.
7326 If we return zero, we set *PTRUE and *PFALSE to X. */
7329 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
7331 enum machine_mode mode = GET_MODE (x);
7332 enum rtx_code code = GET_CODE (x);
7333 rtx cond0, cond1, true0, true1, false0, false1;
7334 unsigned HOST_WIDE_INT nz;
7336 /* If we are comparing a value against zero, we are done. */
7337 if ((code == NE || code == EQ)
7338 && XEXP (x, 1) == const0_rtx)
7340 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7341 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7345 /* If this is a unary operation whose operand has one of two values, apply
7346 our opcode to compute those values. */
7347 else if (UNARY_P (x)
7348 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7350 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
7351 *pfalse = simplify_gen_unary (code, mode, false0,
7352 GET_MODE (XEXP (x, 0)));
7356 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7357 make can't possibly match and would suppress other optimizations. */
7358 else if (code == COMPARE)
7361 /* If this is a binary operation, see if either side has only one of two
7362 values. If either one does or if both do and they are conditional on
7363 the same value, compute the new true and false values. */
7364 else if (BINARY_P (x))
7366 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7367 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7369 if ((cond0 != 0 || cond1 != 0)
7370 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7372 /* If if_then_else_cond returned zero, then true/false are the
7373 same rtl. We must copy one of them to prevent invalid rtl
7376 true0 = copy_rtx (true0);
7377 else if (cond1 == 0)
7378 true1 = copy_rtx (true1);
7380 if (COMPARISON_P (x))
7382 *ptrue = simplify_gen_relational (code, mode, VOIDmode,
7384 *pfalse = simplify_gen_relational (code, mode, VOIDmode,
7389 *ptrue = simplify_gen_binary (code, mode, true0, true1);
7390 *pfalse = simplify_gen_binary (code, mode, false0, false1);
7393 return cond0 ? cond0 : cond1;
7396 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7397 operands is zero when the other is nonzero, and vice-versa,
7398 and STORE_FLAG_VALUE is 1 or -1. */
7400 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7401 && (code == PLUS || code == IOR || code == XOR || code == MINUS
7403 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7405 rtx op0 = XEXP (XEXP (x, 0), 1);
7406 rtx op1 = XEXP (XEXP (x, 1), 1);
7408 cond0 = XEXP (XEXP (x, 0), 0);
7409 cond1 = XEXP (XEXP (x, 1), 0);
7411 if (COMPARISON_P (cond0)
7412 && COMPARISON_P (cond1)
7413 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
7414 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7415 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7416 || ((swap_condition (GET_CODE (cond0))
7417 == reversed_comparison_code (cond1, NULL))
7418 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7419 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7420 && ! side_effects_p (x))
7422 *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
7423 *pfalse = simplify_gen_binary (MULT, mode,
7425 ? simplify_gen_unary (NEG, mode,
7433 /* Similarly for MULT, AND and UMIN, except that for these the result
7435 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7436 && (code == MULT || code == AND || code == UMIN)
7437 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7439 cond0 = XEXP (XEXP (x, 0), 0);
7440 cond1 = XEXP (XEXP (x, 1), 0);
7442 if (COMPARISON_P (cond0)
7443 && COMPARISON_P (cond1)
7444 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
7445 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7446 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7447 || ((swap_condition (GET_CODE (cond0))
7448 == reversed_comparison_code (cond1, NULL))
7449 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7450 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7451 && ! side_effects_p (x))
7453 *ptrue = *pfalse = const0_rtx;
7459 else if (code == IF_THEN_ELSE)
7461 /* If we have IF_THEN_ELSE already, extract the condition and
7462 canonicalize it if it is NE or EQ. */
7463 cond0 = XEXP (x, 0);
7464 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7465 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7466 return XEXP (cond0, 0);
7467 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7469 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7470 return XEXP (cond0, 0);
7476 /* If X is a SUBREG, we can narrow both the true and false values
7477 if the inner expression, if there is a condition. */
7478 else if (code == SUBREG
7479 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7482 true0 = simplify_gen_subreg (mode, true0,
7483 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7484 false0 = simplify_gen_subreg (mode, false0,
7485 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7486 if (true0 && false0)
7494 /* If X is a constant, this isn't special and will cause confusions
7495 if we treat it as such. Likewise if it is equivalent to a constant. */
7496 else if (CONSTANT_P (x)
7497 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7500 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7501 will be least confusing to the rest of the compiler. */
7502 else if (mode == BImode)
7504 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
7508 /* If X is known to be either 0 or -1, those are the true and
7509 false values when testing X. */
7510 else if (x == constm1_rtx || x == const0_rtx
7511 || (mode != VOIDmode
7512 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
7514 *ptrue = constm1_rtx, *pfalse = const0_rtx;
7518 /* Likewise for 0 or a single bit. */
7519 else if (SCALAR_INT_MODE_P (mode)
7520 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7521 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7523 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
7527 /* Otherwise fail; show no condition with true and false values the same. */
7528 *ptrue = *pfalse = x;
7532 /* Return the value of expression X given the fact that condition COND
7533 is known to be true when applied to REG as its first operand and VAL
7534 as its second. X is known to not be shared and so can be modified in
7537 We only handle the simplest cases, and specifically those cases that
7538 arise with IF_THEN_ELSE expressions. */
7541 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
7543 enum rtx_code code = GET_CODE (x);
7548 if (side_effects_p (x))
7551 /* If either operand of the condition is a floating point value,
7552 then we have to avoid collapsing an EQ comparison. */
7554 && rtx_equal_p (x, reg)
7555 && ! FLOAT_MODE_P (GET_MODE (x))
7556 && ! FLOAT_MODE_P (GET_MODE (val)))
7559 if (cond == UNEQ && rtx_equal_p (x, reg))
7562 /* If X is (abs REG) and we know something about REG's relationship
7563 with zero, we may be able to simplify this. */
7565 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
7568 case GE: case GT: case EQ:
7571 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
7573 GET_MODE (XEXP (x, 0)));
7578 /* The only other cases we handle are MIN, MAX, and comparisons if the
7579 operands are the same as REG and VAL. */
7581 else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
7583 if (rtx_equal_p (XEXP (x, 0), val))
7584 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
7586 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
7588 if (COMPARISON_P (x))
7590 if (comparison_dominates_p (cond, code))
7591 return const_true_rtx;
7593 code = reversed_comparison_code (x, NULL);
7595 && comparison_dominates_p (cond, code))
7600 else if (code == SMAX || code == SMIN
7601 || code == UMIN || code == UMAX)
7603 int unsignedp = (code == UMIN || code == UMAX);
7605 /* Do not reverse the condition when it is NE or EQ.
7606 This is because we cannot conclude anything about
7607 the value of 'SMAX (x, y)' when x is not equal to y,
7608 but we can when x equals y. */
7609 if ((code == SMAX || code == UMAX)
7610 && ! (cond == EQ || cond == NE))
7611 cond = reverse_condition (cond);
7616 return unsignedp ? x : XEXP (x, 1);
7618 return unsignedp ? x : XEXP (x, 0);
7620 return unsignedp ? XEXP (x, 1) : x;
7622 return unsignedp ? XEXP (x, 0) : x;
7629 else if (code == SUBREG)
7631 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
7632 rtx new, r = known_cond (SUBREG_REG (x), cond, reg, val);
7634 if (SUBREG_REG (x) != r)
7636 /* We must simplify subreg here, before we lose track of the
7637 original inner_mode. */
7638 new = simplify_subreg (GET_MODE (x), r,
7639 inner_mode, SUBREG_BYTE (x));
7643 SUBST (SUBREG_REG (x), r);
7648 /* We don't have to handle SIGN_EXTEND here, because even in the
7649 case of replacing something with a modeless CONST_INT, a
7650 CONST_INT is already (supposed to be) a valid sign extension for
7651 its narrower mode, which implies it's already properly
7652 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
7653 story is different. */
7654 else if (code == ZERO_EXTEND)
7656 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
7657 rtx new, r = known_cond (XEXP (x, 0), cond, reg, val);
7659 if (XEXP (x, 0) != r)
7661 /* We must simplify the zero_extend here, before we lose
7662 track of the original inner_mode. */
7663 new = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
7668 SUBST (XEXP (x, 0), r);
7674 fmt = GET_RTX_FORMAT (code);
7675 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7678 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7679 else if (fmt[i] == 'E')
7680 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7681 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7688 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7689 assignment as a field assignment. */
7692 rtx_equal_for_field_assignment_p (rtx x, rtx y)
7694 if (x == y || rtx_equal_p (x, y))
7697 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7700 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7701 Note that all SUBREGs of MEM are paradoxical; otherwise they
7702 would have been rewritten. */
7703 if (MEM_P (x) && GET_CODE (y) == SUBREG
7704 && MEM_P (SUBREG_REG (y))
7705 && rtx_equal_p (SUBREG_REG (y),
7706 gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
7709 if (MEM_P (y) && GET_CODE (x) == SUBREG
7710 && MEM_P (SUBREG_REG (x))
7711 && rtx_equal_p (SUBREG_REG (x),
7712 gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
7715 /* We used to see if get_last_value of X and Y were the same but that's
7716 not correct. In one direction, we'll cause the assignment to have
7717 the wrong destination and in the case, we'll import a register into this
7718 insn that might have already have been dead. So fail if none of the
7719 above cases are true. */
7723 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7724 Return that assignment if so.
7726 We only handle the most common cases. */
7729 make_field_assignment (rtx x)
7731 rtx dest = SET_DEST (x);
7732 rtx src = SET_SRC (x);
7737 unsigned HOST_WIDE_INT len;
7739 enum machine_mode mode;
7741 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7742 a clear of a one-bit field. We will have changed it to
7743 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7746 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7747 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7748 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7749 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7751 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7754 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7758 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7759 && subreg_lowpart_p (XEXP (src, 0))
7760 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7761 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7762 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7763 && GET_CODE (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == CONST_INT
7764 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7765 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7767 assign = make_extraction (VOIDmode, dest, 0,
7768 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7771 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7775 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7777 if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7778 && XEXP (XEXP (src, 0), 0) == const1_rtx
7779 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7781 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7784 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
7788 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
7789 SRC is an AND with all bits of that field set, then we can discard
7791 if (GET_CODE (dest) == ZERO_EXTRACT
7792 && GET_CODE (XEXP (dest, 1)) == CONST_INT
7793 && GET_CODE (src) == AND
7794 && GET_CODE (XEXP (src, 1)) == CONST_INT)
7796 HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
7797 unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
7798 unsigned HOST_WIDE_INT ze_mask;
7800 if (width >= HOST_BITS_PER_WIDE_INT)
7803 ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
7805 /* Complete overlap. We can remove the source AND. */
7806 if ((and_mask & ze_mask) == ze_mask)
7807 return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
7809 /* Partial overlap. We can reduce the source AND. */
7810 if ((and_mask & ze_mask) != and_mask)
7812 mode = GET_MODE (src);
7813 src = gen_rtx_AND (mode, XEXP (src, 0),
7814 gen_int_mode (and_mask & ze_mask, mode));
7815 return gen_rtx_SET (VOIDmode, dest, src);
7819 /* The other case we handle is assignments into a constant-position
7820 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7821 a mask that has all one bits except for a group of zero bits and
7822 OTHER is known to have zeros where C1 has ones, this is such an
7823 assignment. Compute the position and length from C1. Shift OTHER
7824 to the appropriate position, force it to the required mode, and
7825 make the extraction. Check for the AND in both operands. */
7827 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
7830 rhs = expand_compound_operation (XEXP (src, 0));
7831 lhs = expand_compound_operation (XEXP (src, 1));
7833 if (GET_CODE (rhs) == AND
7834 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7835 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7836 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7837 else if (GET_CODE (lhs) == AND
7838 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7839 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7840 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
7844 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
7845 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
7846 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7847 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
7850 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
7854 /* The mode to use for the source is the mode of the assignment, or of
7855 what is inside a possible STRICT_LOW_PART. */
7856 mode = (GET_CODE (assign) == STRICT_LOW_PART
7857 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
7859 /* Shift OTHER right POS places and make it the source, restricting it
7860 to the proper length and mode. */
7862 src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
7866 src = force_to_mode (src, mode,
7867 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7868 ? ~(unsigned HOST_WIDE_INT) 0
7869 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7872 /* If SRC is masked by an AND that does not make a difference in
7873 the value being stored, strip it. */
7874 if (GET_CODE (assign) == ZERO_EXTRACT
7875 && GET_CODE (XEXP (assign, 1)) == CONST_INT
7876 && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
7877 && GET_CODE (src) == AND
7878 && GET_CODE (XEXP (src, 1)) == CONST_INT
7879 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (src, 1))
7880 == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1))
7881 src = XEXP (src, 0);
7883 return gen_rtx_SET (VOIDmode, assign, src);
7886 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7890 apply_distributive_law (rtx x)
7892 enum rtx_code code = GET_CODE (x);
7893 enum rtx_code inner_code;
7894 rtx lhs, rhs, other;
7897 /* Distributivity is not true for floating point as it can change the
7898 value. So we don't do it unless -funsafe-math-optimizations. */
7899 if (FLOAT_MODE_P (GET_MODE (x))
7900 && ! flag_unsafe_math_optimizations)
7903 /* The outer operation can only be one of the following: */
7904 if (code != IOR && code != AND && code != XOR
7905 && code != PLUS && code != MINUS)
7911 /* If either operand is a primitive we can't do anything, so get out
7913 if (OBJECT_P (lhs) || OBJECT_P (rhs))
7916 lhs = expand_compound_operation (lhs);
7917 rhs = expand_compound_operation (rhs);
7918 inner_code = GET_CODE (lhs);
7919 if (inner_code != GET_CODE (rhs))
7922 /* See if the inner and outer operations distribute. */
7929 /* These all distribute except over PLUS. */
7930 if (code == PLUS || code == MINUS)
7935 if (code != PLUS && code != MINUS)
7940 /* This is also a multiply, so it distributes over everything. */
7944 /* Non-paradoxical SUBREGs distributes over all operations,
7945 provided the inner modes and byte offsets are the same, this
7946 is an extraction of a low-order part, we don't convert an fp
7947 operation to int or vice versa, this is not a vector mode,
7948 and we would not be converting a single-word operation into a
7949 multi-word operation. The latter test is not required, but
7950 it prevents generating unneeded multi-word operations. Some
7951 of the previous tests are redundant given the latter test,
7952 but are retained because they are required for correctness.
7954 We produce the result slightly differently in this case. */
7956 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7957 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
7958 || ! subreg_lowpart_p (lhs)
7959 || (GET_MODE_CLASS (GET_MODE (lhs))
7960 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
7961 || (GET_MODE_SIZE (GET_MODE (lhs))
7962 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
7963 || VECTOR_MODE_P (GET_MODE (lhs))
7964 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD
7965 /* Result might need to be truncated. Don't change mode if
7966 explicit truncation is needed. */
7967 || !TRULY_NOOP_TRUNCATION
7968 (GET_MODE_BITSIZE (GET_MODE (x)),
7969 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (lhs)))))
7972 tem = simplify_gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
7973 SUBREG_REG (lhs), SUBREG_REG (rhs));
7974 return gen_lowpart (GET_MODE (x), tem);
7980 /* Set LHS and RHS to the inner operands (A and B in the example
7981 above) and set OTHER to the common operand (C in the example).
7982 There is only one way to do this unless the inner operation is
7984 if (COMMUTATIVE_ARITH_P (lhs)
7985 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
7986 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
7987 else if (COMMUTATIVE_ARITH_P (lhs)
7988 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
7989 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
7990 else if (COMMUTATIVE_ARITH_P (lhs)
7991 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
7992 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
7993 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
7994 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
7998 /* Form the new inner operation, seeing if it simplifies first. */
7999 tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
8001 /* There is one exception to the general way of distributing:
8002 (a | c) ^ (b | c) -> (a ^ b) & ~c */
8003 if (code == XOR && inner_code == IOR)
8006 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
8009 /* We may be able to continuing distributing the result, so call
8010 ourselves recursively on the inner operation before forming the
8011 outer operation, which we return. */
8012 return simplify_gen_binary (inner_code, GET_MODE (x),
8013 apply_distributive_law (tem), other);
8016 /* See if X is of the form (* (+ A B) C), and if so convert to
8017 (+ (* A C) (* B C)) and try to simplify.
8019 Most of the time, this results in no change. However, if some of
8020 the operands are the same or inverses of each other, simplifications
8023 For example, (and (ior A B) (not B)) can occur as the result of
8024 expanding a bit field assignment. When we apply the distributive
8025 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
8026 which then simplifies to (and (A (not B))).
8028 Note that no checks happen on the validity of applying the inverse
8029 distributive law. This is pointless since we can do it in the
8030 few places where this routine is called.
8032 N is the index of the term that is decomposed (the arithmetic operation,
8033 i.e. (+ A B) in the first example above). !N is the index of the term that
8034 is distributed, i.e. of C in the first example above. */
8036 distribute_and_simplify_rtx (rtx x, int n)
8038 enum machine_mode mode;
8039 enum rtx_code outer_code, inner_code;
8040 rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
8042 decomposed = XEXP (x, n);
8043 if (!ARITHMETIC_P (decomposed))
8046 mode = GET_MODE (x);
8047 outer_code = GET_CODE (x);
8048 distributed = XEXP (x, !n);
8050 inner_code = GET_CODE (decomposed);
8051 inner_op0 = XEXP (decomposed, 0);
8052 inner_op1 = XEXP (decomposed, 1);
8054 /* Special case (and (xor B C) (not A)), which is equivalent to
8055 (xor (ior A B) (ior A C)) */
8056 if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
8058 distributed = XEXP (distributed, 0);
8064 /* Distribute the second term. */
8065 new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
8066 new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
8070 /* Distribute the first term. */
8071 new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
8072 new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
8075 tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
8077 if (GET_CODE (tmp) != outer_code
8078 && rtx_cost (tmp, SET) < rtx_cost (x, SET))
8084 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
8085 in MODE. Return an equivalent form, if different from (and VAROP
8086 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
8089 simplify_and_const_int_1 (enum machine_mode mode, rtx varop,
8090 unsigned HOST_WIDE_INT constop)
8092 unsigned HOST_WIDE_INT nonzero;
8093 unsigned HOST_WIDE_INT orig_constop;
8098 orig_constop = constop;
8099 if (GET_CODE (varop) == CLOBBER)
8102 /* Simplify VAROP knowing that we will be only looking at some of the
8105 Note by passing in CONSTOP, we guarantee that the bits not set in
8106 CONSTOP are not significant and will never be examined. We must
8107 ensure that is the case by explicitly masking out those bits
8108 before returning. */
8109 varop = force_to_mode (varop, mode, constop, 0);
8111 /* If VAROP is a CLOBBER, we will fail so return it. */
8112 if (GET_CODE (varop) == CLOBBER)
8115 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
8116 to VAROP and return the new constant. */
8117 if (GET_CODE (varop) == CONST_INT)
8118 return gen_int_mode (INTVAL (varop) & constop, mode);
8120 /* See what bits may be nonzero in VAROP. Unlike the general case of
8121 a call to nonzero_bits, here we don't care about bits outside
8124 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
8126 /* Turn off all bits in the constant that are known to already be zero.
8127 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8128 which is tested below. */
8132 /* If we don't have any bits left, return zero. */
8136 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8137 a power of two, we can replace this with an ASHIFT. */
8138 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
8139 && (i = exact_log2 (constop)) >= 0)
8140 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
8142 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8143 or XOR, then try to apply the distributive law. This may eliminate
8144 operations if either branch can be simplified because of the AND.
8145 It may also make some cases more complex, but those cases probably
8146 won't match a pattern either with or without this. */
8148 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
8152 apply_distributive_law
8153 (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
8154 simplify_and_const_int (NULL_RTX,
8158 simplify_and_const_int (NULL_RTX,
8163 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
8164 the AND and see if one of the operands simplifies to zero. If so, we
8165 may eliminate it. */
8167 if (GET_CODE (varop) == PLUS
8168 && exact_log2 (constop + 1) >= 0)
8172 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
8173 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
8174 if (o0 == const0_rtx)
8176 if (o1 == const0_rtx)
8180 /* Make a SUBREG if necessary. If we can't make it, fail. */
8181 varop = gen_lowpart (mode, varop);
8182 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
8185 /* If we are only masking insignificant bits, return VAROP. */
8186 if (constop == nonzero)
8189 if (varop == orig_varop && constop == orig_constop)
8192 /* Otherwise, return an AND. */
8193 constop = trunc_int_for_mode (constop, mode);
8194 return simplify_gen_binary (AND, mode, varop, GEN_INT (constop));
8198 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
8201 Return an equivalent form, if different from X. Otherwise, return X. If
8202 X is zero, we are to always construct the equivalent form. */
8205 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
8206 unsigned HOST_WIDE_INT constop)
8208 rtx tem = simplify_and_const_int_1 (mode, varop, constop);
8213 x = simplify_gen_binary (AND, GET_MODE (varop), varop, GEN_INT (constop));
8214 if (GET_MODE (x) != mode)
8215 x = gen_lowpart (mode, x);
8219 /* Given a REG, X, compute which bits in X can be nonzero.
8220 We don't care about bits outside of those defined in MODE.
8222 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8223 a shift, AND, or zero_extract, we can do better. */
8226 reg_nonzero_bits_for_combine (rtx x, enum machine_mode mode,
8227 rtx known_x ATTRIBUTE_UNUSED,
8228 enum machine_mode known_mode ATTRIBUTE_UNUSED,
8229 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
8230 unsigned HOST_WIDE_INT *nonzero)
8234 /* If X is a register whose nonzero bits value is current, use it.
8235 Otherwise, if X is a register whose value we can find, use that
8236 value. Otherwise, use the previously-computed global nonzero bits
8237 for this register. */
8239 if (reg_stat[REGNO (x)].last_set_value != 0
8240 && (reg_stat[REGNO (x)].last_set_mode == mode
8241 || (GET_MODE_CLASS (reg_stat[REGNO (x)].last_set_mode) == MODE_INT
8242 && GET_MODE_CLASS (mode) == MODE_INT))
8243 && (reg_stat[REGNO (x)].last_set_label == label_tick
8244 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8245 && REG_N_SETS (REGNO (x)) == 1
8246 && ! REGNO_REG_SET_P
8247 (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
8249 && INSN_CUID (reg_stat[REGNO (x)].last_set) < subst_low_cuid)
8251 *nonzero &= reg_stat[REGNO (x)].last_set_nonzero_bits;
8255 tem = get_last_value (x);
8259 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8260 /* If X is narrower than MODE and TEM is a non-negative
8261 constant that would appear negative in the mode of X,
8262 sign-extend it for use in reg_nonzero_bits because some
8263 machines (maybe most) will actually do the sign-extension
8264 and this is the conservative approach.
8266 ??? For 2.5, try to tighten up the MD files in this regard
8267 instead of this kludge. */
8269 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode)
8270 && GET_CODE (tem) == CONST_INT
8272 && 0 != (INTVAL (tem)
8273 & ((HOST_WIDE_INT) 1
8274 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8275 tem = GEN_INT (INTVAL (tem)
8276 | ((HOST_WIDE_INT) (-1)
8277 << GET_MODE_BITSIZE (GET_MODE (x))));
8281 else if (nonzero_sign_valid && reg_stat[REGNO (x)].nonzero_bits)
8283 unsigned HOST_WIDE_INT mask = reg_stat[REGNO (x)].nonzero_bits;
8285 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode))
8286 /* We don't know anything about the upper bits. */
8287 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
8294 /* Return the number of bits at the high-order end of X that are known to
8295 be equal to the sign bit. X will be used in mode MODE; if MODE is
8296 VOIDmode, X will be used in its own mode. The returned value will always
8297 be between 1 and the number of bits in MODE. */
8300 reg_num_sign_bit_copies_for_combine (rtx x, enum machine_mode mode,
8301 rtx known_x ATTRIBUTE_UNUSED,
8302 enum machine_mode known_mode
8304 unsigned int known_ret ATTRIBUTE_UNUSED,
8305 unsigned int *result)
8309 if (reg_stat[REGNO (x)].last_set_value != 0
8310 && reg_stat[REGNO (x)].last_set_mode == mode
8311 && (reg_stat[REGNO (x)].last_set_label == label_tick
8312 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8313 && REG_N_SETS (REGNO (x)) == 1
8314 && ! REGNO_REG_SET_P
8315 (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
8317 && INSN_CUID (reg_stat[REGNO (x)].last_set) < subst_low_cuid)
8319 *result = reg_stat[REGNO (x)].last_set_sign_bit_copies;
8323 tem = get_last_value (x);
8327 if (nonzero_sign_valid && reg_stat[REGNO (x)].sign_bit_copies != 0
8328 && GET_MODE_BITSIZE (GET_MODE (x)) == GET_MODE_BITSIZE (mode))
8329 *result = reg_stat[REGNO (x)].sign_bit_copies;
8334 /* Return the number of "extended" bits there are in X, when interpreted
8335 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8336 unsigned quantities, this is the number of high-order zero bits.
8337 For signed quantities, this is the number of copies of the sign bit
8338 minus 1. In both case, this function returns the number of "spare"
8339 bits. For example, if two quantities for which this function returns
8340 at least 1 are added, the addition is known not to overflow.
8342 This function will always return 0 unless called during combine, which
8343 implies that it must be called from a define_split. */
8346 extended_count (rtx x, enum machine_mode mode, int unsignedp)
8348 if (nonzero_sign_valid == 0)
8352 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8353 ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
8354 - floor_log2 (nonzero_bits (x, mode)))
8356 : num_sign_bit_copies (x, mode) - 1);
8359 /* This function is called from `simplify_shift_const' to merge two
8360 outer operations. Specifically, we have already found that we need
8361 to perform operation *POP0 with constant *PCONST0 at the outermost
8362 position. We would now like to also perform OP1 with constant CONST1
8363 (with *POP0 being done last).
8365 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8366 the resulting operation. *PCOMP_P is set to 1 if we would need to
8367 complement the innermost operand, otherwise it is unchanged.
8369 MODE is the mode in which the operation will be done. No bits outside
8370 the width of this mode matter. It is assumed that the width of this mode
8371 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8373 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
8374 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8375 result is simply *PCONST0.
8377 If the resulting operation cannot be expressed as one operation, we
8378 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8381 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
8383 enum rtx_code op0 = *pop0;
8384 HOST_WIDE_INT const0 = *pconst0;
8386 const0 &= GET_MODE_MASK (mode);
8387 const1 &= GET_MODE_MASK (mode);
8389 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8393 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
8396 if (op1 == UNKNOWN || op0 == SET)
8399 else if (op0 == UNKNOWN)
8400 op0 = op1, const0 = const1;
8402 else if (op0 == op1)
8426 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8427 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8430 /* If the two constants aren't the same, we can't do anything. The
8431 remaining six cases can all be done. */
8432 else if (const0 != const1)
8440 /* (a & b) | b == b */
8442 else /* op1 == XOR */
8443 /* (a ^ b) | b == a | b */
8449 /* (a & b) ^ b == (~a) & b */
8450 op0 = AND, *pcomp_p = 1;
8451 else /* op1 == IOR */
8452 /* (a | b) ^ b == a & ~b */
8453 op0 = AND, const0 = ~const0;
8458 /* (a | b) & b == b */
8460 else /* op1 == XOR */
8461 /* (a ^ b) & b) == (~a) & b */
8468 /* Check for NO-OP cases. */
8469 const0 &= GET_MODE_MASK (mode);
8471 && (op0 == IOR || op0 == XOR || op0 == PLUS))
8473 else if (const0 == 0 && op0 == AND)
8475 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8479 /* ??? Slightly redundant with the above mask, but not entirely.
8480 Moving this above means we'd have to sign-extend the mode mask
8481 for the final test. */
8482 const0 = trunc_int_for_mode (const0, mode);
8490 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8491 The result of the shift is RESULT_MODE. Return NULL_RTX if we cannot
8492 simplify it. Otherwise, return a simplified value.
8494 The shift is normally computed in the widest mode we find in VAROP, as
8495 long as it isn't a different number of words than RESULT_MODE. Exceptions
8496 are ASHIFTRT and ROTATE, which are always done in their original mode. */
8499 simplify_shift_const_1 (enum rtx_code code, enum machine_mode result_mode,
8500 rtx varop, int orig_count)
8502 enum rtx_code orig_code = code;
8503 rtx orig_varop = varop;
8505 enum machine_mode mode = result_mode;
8506 enum machine_mode shift_mode, tmode;
8507 unsigned int mode_words
8508 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8509 /* We form (outer_op (code varop count) (outer_const)). */
8510 enum rtx_code outer_op = UNKNOWN;
8511 HOST_WIDE_INT outer_const = 0;
8512 int complement_p = 0;
8515 /* Make sure and truncate the "natural" shift on the way in. We don't
8516 want to do this inside the loop as it makes it more difficult to
8518 if (SHIFT_COUNT_TRUNCATED)
8519 orig_count &= GET_MODE_BITSIZE (mode) - 1;
8521 /* If we were given an invalid count, don't do anything except exactly
8522 what was requested. */
8524 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
8529 /* Unless one of the branches of the `if' in this loop does a `continue',
8530 we will `break' the loop after the `if'. */
8534 /* If we have an operand of (clobber (const_int 0)), fail. */
8535 if (GET_CODE (varop) == CLOBBER)
8538 /* If we discovered we had to complement VAROP, leave. Making a NOT
8539 here would cause an infinite loop. */
8543 /* Convert ROTATERT to ROTATE. */
8544 if (code == ROTATERT)
8546 unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
8548 if (VECTOR_MODE_P (result_mode))
8549 count = bitsize / GET_MODE_NUNITS (result_mode) - count;
8551 count = bitsize - count;
8554 /* We need to determine what mode we will do the shift in. If the
8555 shift is a right shift or a ROTATE, we must always do it in the mode
8556 it was originally done in. Otherwise, we can do it in MODE, the
8557 widest mode encountered. */
8559 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8560 ? result_mode : mode);
8562 /* Handle cases where the count is greater than the size of the mode
8563 minus 1. For ASHIFT, use the size minus one as the count (this can
8564 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
8565 take the count modulo the size. For other shifts, the result is
8568 Since these shifts are being produced by the compiler by combining
8569 multiple operations, each of which are defined, we know what the
8570 result is supposed to be. */
8572 if (count > (GET_MODE_BITSIZE (shift_mode) - 1))
8574 if (code == ASHIFTRT)
8575 count = GET_MODE_BITSIZE (shift_mode) - 1;
8576 else if (code == ROTATE || code == ROTATERT)
8577 count %= GET_MODE_BITSIZE (shift_mode);
8580 /* We can't simply return zero because there may be an
8588 /* An arithmetic right shift of a quantity known to be -1 or 0
8590 if (code == ASHIFTRT
8591 && (num_sign_bit_copies (varop, shift_mode)
8592 == GET_MODE_BITSIZE (shift_mode)))
8598 /* If we are doing an arithmetic right shift and discarding all but
8599 the sign bit copies, this is equivalent to doing a shift by the
8600 bitsize minus one. Convert it into that shift because it will often
8601 allow other simplifications. */
8603 if (code == ASHIFTRT
8604 && (count + num_sign_bit_copies (varop, shift_mode)
8605 >= GET_MODE_BITSIZE (shift_mode)))
8606 count = GET_MODE_BITSIZE (shift_mode) - 1;
8608 /* We simplify the tests below and elsewhere by converting
8609 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8610 `make_compound_operation' will convert it to an ASHIFTRT for
8611 those machines (such as VAX) that don't have an LSHIFTRT. */
8612 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8614 && ((nonzero_bits (varop, shift_mode)
8615 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
8619 if (code == LSHIFTRT
8620 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8621 && !(nonzero_bits (varop, shift_mode) >> count))
8624 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8625 && !((nonzero_bits (varop, shift_mode) << count)
8626 & GET_MODE_MASK (shift_mode)))
8629 switch (GET_CODE (varop))
8635 new = expand_compound_operation (varop);
8644 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8645 minus the width of a smaller mode, we can do this with a
8646 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
8647 if ((code == ASHIFTRT || code == LSHIFTRT)
8648 && ! mode_dependent_address_p (XEXP (varop, 0))
8649 && ! MEM_VOLATILE_P (varop)
8650 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8651 MODE_INT, 1)) != BLKmode)
8653 new = adjust_address_nv (varop, tmode,
8654 BYTES_BIG_ENDIAN ? 0
8655 : count / BITS_PER_UNIT);
8657 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
8658 : ZERO_EXTEND, mode, new);
8665 /* If VAROP is a SUBREG, strip it as long as the inner operand has
8666 the same number of words as what we've seen so far. Then store
8667 the widest mode in MODE. */
8668 if (subreg_lowpart_p (varop)
8669 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8670 > GET_MODE_SIZE (GET_MODE (varop)))
8671 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8672 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
8675 varop = SUBREG_REG (varop);
8676 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
8677 mode = GET_MODE (varop);
8683 /* Some machines use MULT instead of ASHIFT because MULT
8684 is cheaper. But it is still better on those machines to
8685 merge two shifts into one. */
8686 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8687 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8690 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
8692 GEN_INT (exact_log2 (
8693 INTVAL (XEXP (varop, 1)))));
8699 /* Similar, for when divides are cheaper. */
8700 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8701 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8704 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
8706 GEN_INT (exact_log2 (
8707 INTVAL (XEXP (varop, 1)))));
8713 /* If we are extracting just the sign bit of an arithmetic
8714 right shift, that shift is not needed. However, the sign
8715 bit of a wider mode may be different from what would be
8716 interpreted as the sign bit in a narrower mode, so, if
8717 the result is narrower, don't discard the shift. */
8718 if (code == LSHIFTRT
8719 && count == (GET_MODE_BITSIZE (result_mode) - 1)
8720 && (GET_MODE_BITSIZE (result_mode)
8721 >= GET_MODE_BITSIZE (GET_MODE (varop))))
8723 varop = XEXP (varop, 0);
8727 /* ... fall through ... */
8732 /* Here we have two nested shifts. The result is usually the
8733 AND of a new shift with a mask. We compute the result below. */
8734 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8735 && INTVAL (XEXP (varop, 1)) >= 0
8736 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
8737 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8738 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
8740 enum rtx_code first_code = GET_CODE (varop);
8741 unsigned int first_count = INTVAL (XEXP (varop, 1));
8742 unsigned HOST_WIDE_INT mask;
8745 /* We have one common special case. We can't do any merging if
8746 the inner code is an ASHIFTRT of a smaller mode. However, if
8747 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
8748 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
8749 we can convert it to
8750 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
8751 This simplifies certain SIGN_EXTEND operations. */
8752 if (code == ASHIFT && first_code == ASHIFTRT
8753 && count == (GET_MODE_BITSIZE (result_mode)
8754 - GET_MODE_BITSIZE (GET_MODE (varop))))
8756 /* C3 has the low-order C1 bits zero. */
8758 mask = (GET_MODE_MASK (mode)
8759 & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
8761 varop = simplify_and_const_int (NULL_RTX, result_mode,
8762 XEXP (varop, 0), mask);
8763 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
8765 count = first_count;
8770 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
8771 than C1 high-order bits equal to the sign bit, we can convert
8772 this to either an ASHIFT or an ASHIFTRT depending on the
8775 We cannot do this if VAROP's mode is not SHIFT_MODE. */
8777 if (code == ASHIFTRT && first_code == ASHIFT
8778 && GET_MODE (varop) == shift_mode
8779 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
8782 varop = XEXP (varop, 0);
8783 count -= first_count;
8793 /* There are some cases we can't do. If CODE is ASHIFTRT,
8794 we can only do this if FIRST_CODE is also ASHIFTRT.
8796 We can't do the case when CODE is ROTATE and FIRST_CODE is
8799 If the mode of this shift is not the mode of the outer shift,
8800 we can't do this if either shift is a right shift or ROTATE.
8802 Finally, we can't do any of these if the mode is too wide
8803 unless the codes are the same.
8805 Handle the case where the shift codes are the same
8808 if (code == first_code)
8810 if (GET_MODE (varop) != result_mode
8811 && (code == ASHIFTRT || code == LSHIFTRT
8815 count += first_count;
8816 varop = XEXP (varop, 0);
8820 if (code == ASHIFTRT
8821 || (code == ROTATE && first_code == ASHIFTRT)
8822 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
8823 || (GET_MODE (varop) != result_mode
8824 && (first_code == ASHIFTRT || first_code == LSHIFTRT
8825 || first_code == ROTATE
8826 || code == ROTATE)))
8829 /* To compute the mask to apply after the shift, shift the
8830 nonzero bits of the inner shift the same way the
8831 outer shift will. */
8833 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
8836 = simplify_const_binary_operation (code, result_mode, mask_rtx,
8839 /* Give up if we can't compute an outer operation to use. */
8841 || GET_CODE (mask_rtx) != CONST_INT
8842 || ! merge_outer_ops (&outer_op, &outer_const, AND,
8844 result_mode, &complement_p))
8847 /* If the shifts are in the same direction, we add the
8848 counts. Otherwise, we subtract them. */
8849 if ((code == ASHIFTRT || code == LSHIFTRT)
8850 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
8851 count += first_count;
8853 count -= first_count;
8855 /* If COUNT is positive, the new shift is usually CODE,
8856 except for the two exceptions below, in which case it is
8857 FIRST_CODE. If the count is negative, FIRST_CODE should
8860 && ((first_code == ROTATE && code == ASHIFT)
8861 || (first_code == ASHIFTRT && code == LSHIFTRT)))
8864 code = first_code, count = -count;
8866 varop = XEXP (varop, 0);
8870 /* If we have (A << B << C) for any shift, we can convert this to
8871 (A << C << B). This wins if A is a constant. Only try this if
8872 B is not a constant. */
8874 else if (GET_CODE (varop) == code
8875 && GET_CODE (XEXP (varop, 0)) == CONST_INT
8876 && GET_CODE (XEXP (varop, 1)) != CONST_INT)
8878 rtx new = simplify_const_binary_operation (code, mode,
8881 varop = gen_rtx_fmt_ee (code, mode, new, XEXP (varop, 1));
8888 /* Make this fit the case below. */
8889 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
8890 GEN_INT (GET_MODE_MASK (mode)));
8896 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
8897 with C the size of VAROP - 1 and the shift is logical if
8898 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8899 we have an (le X 0) operation. If we have an arithmetic shift
8900 and STORE_FLAG_VALUE is 1 or we have a logical shift with
8901 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
8903 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
8904 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
8905 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8906 && (code == LSHIFTRT || code == ASHIFTRT)
8907 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
8908 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8911 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
8914 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8915 varop = gen_rtx_NEG (GET_MODE (varop), varop);
8920 /* If we have (shift (logical)), move the logical to the outside
8921 to allow it to possibly combine with another logical and the
8922 shift to combine with another shift. This also canonicalizes to
8923 what a ZERO_EXTRACT looks like. Also, some machines have
8924 (and (shift)) insns. */
8926 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8927 /* We can't do this if we have (ashiftrt (xor)) and the
8928 constant has its sign bit set in shift_mode. */
8929 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
8930 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
8932 && (new = simplify_const_binary_operation (code, result_mode,
8934 GEN_INT (count))) != 0
8935 && GET_CODE (new) == CONST_INT
8936 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
8937 INTVAL (new), result_mode, &complement_p))
8939 varop = XEXP (varop, 0);
8943 /* If we can't do that, try to simplify the shift in each arm of the
8944 logical expression, make a new logical expression, and apply
8945 the inverse distributive law. This also can't be done
8946 for some (ashiftrt (xor)). */
8947 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8948 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
8949 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
8952 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8953 XEXP (varop, 0), count);
8954 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8955 XEXP (varop, 1), count);
8957 varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
8959 varop = apply_distributive_law (varop);
8967 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
8968 says that the sign bit can be tested, FOO has mode MODE, C is
8969 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
8970 that may be nonzero. */
8971 if (code == LSHIFTRT
8972 && XEXP (varop, 1) == const0_rtx
8973 && GET_MODE (XEXP (varop, 0)) == result_mode
8974 && count == (GET_MODE_BITSIZE (result_mode) - 1)
8975 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8976 && STORE_FLAG_VALUE == -1
8977 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
8978 && merge_outer_ops (&outer_op, &outer_const, XOR,
8979 (HOST_WIDE_INT) 1, result_mode,
8982 varop = XEXP (varop, 0);
8989 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
8990 than the number of bits in the mode is equivalent to A. */
8991 if (code == LSHIFTRT
8992 && count == (GET_MODE_BITSIZE (result_mode) - 1)
8993 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
8995 varop = XEXP (varop, 0);
9000 /* NEG commutes with ASHIFT since it is multiplication. Move the
9001 NEG outside to allow shifts to combine. */
9003 && merge_outer_ops (&outer_op, &outer_const, NEG,
9004 (HOST_WIDE_INT) 0, result_mode,
9007 varop = XEXP (varop, 0);
9013 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9014 is one less than the number of bits in the mode is
9015 equivalent to (xor A 1). */
9016 if (code == LSHIFTRT
9017 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9018 && XEXP (varop, 1) == constm1_rtx
9019 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9020 && merge_outer_ops (&outer_op, &outer_const, XOR,
9021 (HOST_WIDE_INT) 1, result_mode,
9025 varop = XEXP (varop, 0);
9029 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9030 that might be nonzero in BAR are those being shifted out and those
9031 bits are known zero in FOO, we can replace the PLUS with FOO.
9032 Similarly in the other operand order. This code occurs when
9033 we are computing the size of a variable-size array. */
9035 if ((code == ASHIFTRT || code == LSHIFTRT)
9036 && count < HOST_BITS_PER_WIDE_INT
9037 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9038 && (nonzero_bits (XEXP (varop, 1), result_mode)
9039 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9041 varop = XEXP (varop, 0);
9044 else if ((code == ASHIFTRT || code == LSHIFTRT)
9045 && count < HOST_BITS_PER_WIDE_INT
9046 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9047 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9049 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9050 & nonzero_bits (XEXP (varop, 1),
9053 varop = XEXP (varop, 1);
9057 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9059 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9060 && (new = simplify_const_binary_operation (ASHIFT, result_mode,
9062 GEN_INT (count))) != 0
9063 && GET_CODE (new) == CONST_INT
9064 && merge_outer_ops (&outer_op, &outer_const, PLUS,
9065 INTVAL (new), result_mode, &complement_p))
9067 varop = XEXP (varop, 0);
9071 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
9072 signbit', and attempt to change the PLUS to an XOR and move it to
9073 the outer operation as is done above in the AND/IOR/XOR case
9074 leg for shift(logical). See details in logical handling above
9075 for reasoning in doing so. */
9076 if (code == LSHIFTRT
9077 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9078 && mode_signbit_p (result_mode, XEXP (varop, 1))
9079 && (new = simplify_const_binary_operation (code, result_mode,
9081 GEN_INT (count))) != 0
9082 && GET_CODE (new) == CONST_INT
9083 && merge_outer_ops (&outer_op, &outer_const, XOR,
9084 INTVAL (new), result_mode, &complement_p))
9086 varop = XEXP (varop, 0);
9093 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9094 with C the size of VAROP - 1 and the shift is logical if
9095 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9096 we have a (gt X 0) operation. If the shift is arithmetic with
9097 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9098 we have a (neg (gt X 0)) operation. */
9100 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9101 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9102 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9103 && (code == LSHIFTRT || code == ASHIFTRT)
9104 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9105 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
9106 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9109 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9112 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9113 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9120 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9121 if the truncate does not affect the value. */
9122 if (code == LSHIFTRT
9123 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9124 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9125 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9126 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9127 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9129 rtx varop_inner = XEXP (varop, 0);
9132 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9133 XEXP (varop_inner, 0),
9135 (count + INTVAL (XEXP (varop_inner, 1))));
9136 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9149 /* We need to determine what mode to do the shift in. If the shift is
9150 a right shift or ROTATE, we must always do it in the mode it was
9151 originally done in. Otherwise, we can do it in MODE, the widest mode
9152 encountered. The code we care about is that of the shift that will
9153 actually be done, not the shift that was originally requested. */
9155 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9156 ? result_mode : mode);
9158 /* We have now finished analyzing the shift. The result should be
9159 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9160 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
9161 to the result of the shift. OUTER_CONST is the relevant constant,
9162 but we must turn off all bits turned off in the shift. */
9164 if (outer_op == UNKNOWN
9165 && orig_code == code && orig_count == count
9166 && varop == orig_varop
9167 && shift_mode == GET_MODE (varop))
9170 /* Make a SUBREG if necessary. If we can't make it, fail. */
9171 varop = gen_lowpart (shift_mode, varop);
9172 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
9175 /* If we have an outer operation and we just made a shift, it is
9176 possible that we could have simplified the shift were it not
9177 for the outer operation. So try to do the simplification
9180 if (outer_op != UNKNOWN)
9181 x = simplify_shift_const_1 (code, shift_mode, varop, count);
9186 x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count));
9188 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9189 turn off all the bits that the shift would have turned off. */
9190 if (orig_code == LSHIFTRT && result_mode != shift_mode)
9191 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9192 GET_MODE_MASK (result_mode) >> orig_count);
9194 /* Do the remainder of the processing in RESULT_MODE. */
9195 x = gen_lowpart (result_mode, x);
9197 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9200 x = simplify_gen_unary (NOT, result_mode, x, result_mode);
9202 if (outer_op != UNKNOWN)
9204 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9205 outer_const = trunc_int_for_mode (outer_const, result_mode);
9207 if (outer_op == AND)
9208 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9209 else if (outer_op == SET)
9210 /* This means that we have determined that the result is
9211 equivalent to a constant. This should be rare. */
9212 x = GEN_INT (outer_const);
9213 else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
9214 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
9216 x = simplify_gen_binary (outer_op, result_mode, x,
9217 GEN_INT (outer_const));
9223 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9224 The result of the shift is RESULT_MODE. If we cannot simplify it,
9225 return X or, if it is NULL, synthesize the expression with
9226 simplify_gen_binary. Otherwise, return a simplified value.
9228 The shift is normally computed in the widest mode we find in VAROP, as
9229 long as it isn't a different number of words than RESULT_MODE. Exceptions
9230 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9233 simplify_shift_const (rtx x, enum rtx_code code, enum machine_mode result_mode,
9234 rtx varop, int count)
9236 rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
9241 x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count));
9242 if (GET_MODE (x) != result_mode)
9243 x = gen_lowpart (result_mode, x);
9248 /* Like recog, but we receive the address of a pointer to a new pattern.
9249 We try to match the rtx that the pointer points to.
9250 If that fails, we may try to modify or replace the pattern,
9251 storing the replacement into the same pointer object.
9253 Modifications include deletion or addition of CLOBBERs.
9255 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9256 the CLOBBERs are placed.
9258 The value is the final insn code from the pattern ultimately matched,
9262 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
9265 int insn_code_number;
9266 int num_clobbers_to_add = 0;
9269 rtx old_notes, old_pat;
9271 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9272 we use to indicate that something didn't match. If we find such a
9273 thing, force rejection. */
9274 if (GET_CODE (pat) == PARALLEL)
9275 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9276 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9277 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9280 old_pat = PATTERN (insn);
9281 old_notes = REG_NOTES (insn);
9282 PATTERN (insn) = pat;
9283 REG_NOTES (insn) = 0;
9285 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9287 /* If it isn't, there is the possibility that we previously had an insn
9288 that clobbered some register as a side effect, but the combined
9289 insn doesn't need to do that. So try once more without the clobbers
9290 unless this represents an ASM insn. */
9292 if (insn_code_number < 0 && ! check_asm_operands (pat)
9293 && GET_CODE (pat) == PARALLEL)
9297 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9298 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9301 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9305 SUBST_INT (XVECLEN (pat, 0), pos);
9308 pat = XVECEXP (pat, 0, 0);
9310 PATTERN (insn) = pat;
9311 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9313 PATTERN (insn) = old_pat;
9314 REG_NOTES (insn) = old_notes;
9316 /* Recognize all noop sets, these will be killed by followup pass. */
9317 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
9318 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
9320 /* If we had any clobbers to add, make a new pattern than contains
9321 them. Then check to make sure that all of them are dead. */
9322 if (num_clobbers_to_add)
9324 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9325 rtvec_alloc (GET_CODE (pat) == PARALLEL
9327 + num_clobbers_to_add)
9328 : num_clobbers_to_add + 1));
9330 if (GET_CODE (pat) == PARALLEL)
9331 for (i = 0; i < XVECLEN (pat, 0); i++)
9332 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9334 XVECEXP (newpat, 0, 0) = pat;
9336 add_clobbers (newpat, insn_code_number);
9338 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9339 i < XVECLEN (newpat, 0); i++)
9341 if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
9342 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9344 notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9345 XEXP (XVECEXP (newpat, 0, i), 0), notes);
9353 return insn_code_number;
9356 /* Like gen_lowpart_general but for use by combine. In combine it
9357 is not possible to create any new pseudoregs. However, it is
9358 safe to create invalid memory addresses, because combine will
9359 try to recognize them and all they will do is make the combine
9362 If for some reason this cannot do its job, an rtx
9363 (clobber (const_int 0)) is returned.
9364 An insn containing that will not be recognized. */
9367 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
9369 enum machine_mode imode = GET_MODE (x);
9370 unsigned int osize = GET_MODE_SIZE (omode);
9371 unsigned int isize = GET_MODE_SIZE (imode);
9377 /* Return identity if this is a CONST or symbolic reference. */
9379 && (GET_CODE (x) == CONST
9380 || GET_CODE (x) == SYMBOL_REF
9381 || GET_CODE (x) == LABEL_REF))
9384 /* We can only support MODE being wider than a word if X is a
9385 constant integer or has a mode the same size. */
9386 if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
9387 && ! ((imode == VOIDmode
9388 && (GET_CODE (x) == CONST_INT
9389 || GET_CODE (x) == CONST_DOUBLE))
9393 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9394 won't know what to do. So we will strip off the SUBREG here and
9395 process normally. */
9396 if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
9400 /* For use in case we fall down into the address adjustments
9401 further below, we need to adjust the known mode and size of
9402 x; imode and isize, since we just adjusted x. */
9403 imode = GET_MODE (x);
9408 isize = GET_MODE_SIZE (imode);
9411 result = gen_lowpart_common (omode, x);
9413 #ifdef CANNOT_CHANGE_MODE_CLASS
9414 if (result != 0 && GET_CODE (result) == SUBREG)
9415 record_subregs_of_mode (result);
9425 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9427 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9430 /* If we want to refer to something bigger than the original memref,
9431 generate a paradoxical subreg instead. That will force a reload
9432 of the original memref X. */
9434 return gen_rtx_SUBREG (omode, x, 0);
9436 if (WORDS_BIG_ENDIAN)
9437 offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
9439 /* Adjust the address so that the address-after-the-data is
9441 if (BYTES_BIG_ENDIAN)
9442 offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
9444 return adjust_address_nv (x, omode, offset);
9447 /* If X is a comparison operator, rewrite it in a new mode. This
9448 probably won't match, but may allow further simplifications. */
9449 else if (COMPARISON_P (x))
9450 return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
9452 /* If we couldn't simplify X any other way, just enclose it in a
9453 SUBREG. Normally, this SUBREG won't match, but some patterns may
9454 include an explicit SUBREG or we may simplify it further in combine. */
9460 offset = subreg_lowpart_offset (omode, imode);
9461 if (imode == VOIDmode)
9463 imode = int_mode_for_mode (omode);
9464 x = gen_lowpart_common (imode, x);
9468 res = simplify_gen_subreg (omode, x, imode, offset);
9474 return gen_rtx_CLOBBER (imode, const0_rtx);
9477 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9478 comparison code that will be tested.
9480 The result is a possibly different comparison code to use. *POP0 and
9481 *POP1 may be updated.
9483 It is possible that we might detect that a comparison is either always
9484 true or always false. However, we do not perform general constant
9485 folding in combine, so this knowledge isn't useful. Such tautologies
9486 should have been detected earlier. Hence we ignore all such cases. */
9488 static enum rtx_code
9489 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
9495 enum machine_mode mode, tmode;
9497 /* Try a few ways of applying the same transformation to both operands. */
9500 #ifndef WORD_REGISTER_OPERATIONS
9501 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9502 so check specially. */
9503 if (code != GTU && code != GEU && code != LTU && code != LEU
9504 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9505 && GET_CODE (XEXP (op0, 0)) == ASHIFT
9506 && GET_CODE (XEXP (op1, 0)) == ASHIFT
9507 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9508 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9509 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
9510 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
9511 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9512 && XEXP (op0, 1) == XEXP (op1, 1)
9513 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
9514 && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
9515 && (INTVAL (XEXP (op0, 1))
9516 == (GET_MODE_BITSIZE (GET_MODE (op0))
9518 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
9520 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
9521 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
9525 /* If both operands are the same constant shift, see if we can ignore the
9526 shift. We can if the shift is a rotate or if the bits shifted out of
9527 this shift are known to be zero for both inputs and if the type of
9528 comparison is compatible with the shift. */
9529 if (GET_CODE (op0) == GET_CODE (op1)
9530 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9531 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
9532 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
9533 && (code != GT && code != LT && code != GE && code != LE))
9534 || (GET_CODE (op0) == ASHIFTRT
9535 && (code != GTU && code != LTU
9536 && code != GEU && code != LEU)))
9537 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9538 && INTVAL (XEXP (op0, 1)) >= 0
9539 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9540 && XEXP (op0, 1) == XEXP (op1, 1))
9542 enum machine_mode mode = GET_MODE (op0);
9543 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9544 int shift_count = INTVAL (XEXP (op0, 1));
9546 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
9547 mask &= (mask >> shift_count) << shift_count;
9548 else if (GET_CODE (op0) == ASHIFT)
9549 mask = (mask & (mask << shift_count)) >> shift_count;
9551 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
9552 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
9553 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
9558 /* If both operands are AND's of a paradoxical SUBREG by constant, the
9559 SUBREGs are of the same mode, and, in both cases, the AND would
9560 be redundant if the comparison was done in the narrower mode,
9561 do the comparison in the narrower mode (e.g., we are AND'ing with 1
9562 and the operand's possibly nonzero bits are 0xffffff01; in that case
9563 if we only care about QImode, we don't need the AND). This case
9564 occurs if the output mode of an scc insn is not SImode and
9565 STORE_FLAG_VALUE == 1 (e.g., the 386).
9567 Similarly, check for a case where the AND's are ZERO_EXTEND
9568 operations from some narrower mode even though a SUBREG is not
9571 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
9572 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9573 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
9575 rtx inner_op0 = XEXP (op0, 0);
9576 rtx inner_op1 = XEXP (op1, 0);
9577 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
9578 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
9581 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
9582 && (GET_MODE_SIZE (GET_MODE (inner_op0))
9583 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
9584 && (GET_MODE (SUBREG_REG (inner_op0))
9585 == GET_MODE (SUBREG_REG (inner_op1)))
9586 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
9587 <= HOST_BITS_PER_WIDE_INT)
9588 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
9589 GET_MODE (SUBREG_REG (inner_op0)))))
9590 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
9591 GET_MODE (SUBREG_REG (inner_op1))))))
9593 op0 = SUBREG_REG (inner_op0);
9594 op1 = SUBREG_REG (inner_op1);
9596 /* The resulting comparison is always unsigned since we masked
9597 off the original sign bit. */
9598 code = unsigned_condition (code);
9604 for (tmode = GET_CLASS_NARROWEST_MODE
9605 (GET_MODE_CLASS (GET_MODE (op0)));
9606 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
9607 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
9609 op0 = gen_lowpart (tmode, inner_op0);
9610 op1 = gen_lowpart (tmode, inner_op1);
9611 code = unsigned_condition (code);
9620 /* If both operands are NOT, we can strip off the outer operation
9621 and adjust the comparison code for swapped operands; similarly for
9622 NEG, except that this must be an equality comparison. */
9623 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
9624 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
9625 && (code == EQ || code == NE)))
9626 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
9632 /* If the first operand is a constant, swap the operands and adjust the
9633 comparison code appropriately, but don't do this if the second operand
9634 is already a constant integer. */
9635 if (swap_commutative_operands_p (op0, op1))
9637 tem = op0, op0 = op1, op1 = tem;
9638 code = swap_condition (code);
9641 /* We now enter a loop during which we will try to simplify the comparison.
9642 For the most part, we only are concerned with comparisons with zero,
9643 but some things may really be comparisons with zero but not start
9644 out looking that way. */
9646 while (GET_CODE (op1) == CONST_INT)
9648 enum machine_mode mode = GET_MODE (op0);
9649 unsigned int mode_width = GET_MODE_BITSIZE (mode);
9650 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9651 int equality_comparison_p;
9652 int sign_bit_comparison_p;
9653 int unsigned_comparison_p;
9654 HOST_WIDE_INT const_op;
9656 /* We only want to handle integral modes. This catches VOIDmode,
9657 CCmode, and the floating-point modes. An exception is that we
9658 can handle VOIDmode if OP0 is a COMPARE or a comparison
9661 if (GET_MODE_CLASS (mode) != MODE_INT
9662 && ! (mode == VOIDmode
9663 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
9666 /* Get the constant we are comparing against and turn off all bits
9667 not on in our mode. */
9668 const_op = INTVAL (op1);
9669 if (mode != VOIDmode)
9670 const_op = trunc_int_for_mode (const_op, mode);
9671 op1 = GEN_INT (const_op);
9673 /* If we are comparing against a constant power of two and the value
9674 being compared can only have that single bit nonzero (e.g., it was
9675 `and'ed with that bit), we can replace this with a comparison
9678 && (code == EQ || code == NE || code == GE || code == GEU
9679 || code == LT || code == LTU)
9680 && mode_width <= HOST_BITS_PER_WIDE_INT
9681 && exact_log2 (const_op) >= 0
9682 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
9684 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
9685 op1 = const0_rtx, const_op = 0;
9688 /* Similarly, if we are comparing a value known to be either -1 or
9689 0 with -1, change it to the opposite comparison against zero. */
9692 && (code == EQ || code == NE || code == GT || code == LE
9693 || code == GEU || code == LTU)
9694 && num_sign_bit_copies (op0, mode) == mode_width)
9696 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
9697 op1 = const0_rtx, const_op = 0;
9700 /* Do some canonicalizations based on the comparison code. We prefer
9701 comparisons against zero and then prefer equality comparisons.
9702 If we can reduce the size of a constant, we will do that too. */
9707 /* < C is equivalent to <= (C - 1) */
9711 op1 = GEN_INT (const_op);
9713 /* ... fall through to LE case below. */
9719 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
9723 op1 = GEN_INT (const_op);
9727 /* If we are doing a <= 0 comparison on a value known to have
9728 a zero sign bit, we can replace this with == 0. */
9729 else if (const_op == 0
9730 && mode_width <= HOST_BITS_PER_WIDE_INT
9731 && (nonzero_bits (op0, mode)
9732 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9737 /* >= C is equivalent to > (C - 1). */
9741 op1 = GEN_INT (const_op);
9743 /* ... fall through to GT below. */
9749 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
9753 op1 = GEN_INT (const_op);
9757 /* If we are doing a > 0 comparison on a value known to have
9758 a zero sign bit, we can replace this with != 0. */
9759 else if (const_op == 0
9760 && mode_width <= HOST_BITS_PER_WIDE_INT
9761 && (nonzero_bits (op0, mode)
9762 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9767 /* < C is equivalent to <= (C - 1). */
9771 op1 = GEN_INT (const_op);
9773 /* ... fall through ... */
9776 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
9777 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9778 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9780 const_op = 0, op1 = const0_rtx;
9788 /* unsigned <= 0 is equivalent to == 0 */
9792 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
9793 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9794 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9796 const_op = 0, op1 = const0_rtx;
9802 /* >= C is equivalent to > (C - 1). */
9806 op1 = GEN_INT (const_op);
9808 /* ... fall through ... */
9811 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
9812 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9813 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9815 const_op = 0, op1 = const0_rtx;
9823 /* unsigned > 0 is equivalent to != 0 */
9827 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
9828 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9829 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9831 const_op = 0, op1 = const0_rtx;
9840 /* Compute some predicates to simplify code below. */
9842 equality_comparison_p = (code == EQ || code == NE);
9843 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
9844 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
9847 /* If this is a sign bit comparison and we can do arithmetic in
9848 MODE, say that we will only be needing the sign bit of OP0. */
9849 if (sign_bit_comparison_p
9850 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9851 op0 = force_to_mode (op0, mode,
9853 << (GET_MODE_BITSIZE (mode) - 1)),
9856 /* Now try cases based on the opcode of OP0. If none of the cases
9857 does a "continue", we exit this loop immediately after the
9860 switch (GET_CODE (op0))
9863 /* If we are extracting a single bit from a variable position in
9864 a constant that has only a single bit set and are comparing it
9865 with zero, we can convert this into an equality comparison
9866 between the position and the location of the single bit. */
9867 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
9868 have already reduced the shift count modulo the word size. */
9869 if (!SHIFT_COUNT_TRUNCATED
9870 && GET_CODE (XEXP (op0, 0)) == CONST_INT
9871 && XEXP (op0, 1) == const1_rtx
9872 && equality_comparison_p && const_op == 0
9873 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
9875 if (BITS_BIG_ENDIAN)
9877 enum machine_mode new_mode
9878 = mode_for_extraction (EP_extzv, 1);
9879 if (new_mode == MAX_MACHINE_MODE)
9880 i = BITS_PER_WORD - 1 - i;
9884 i = (GET_MODE_BITSIZE (mode) - 1 - i);
9888 op0 = XEXP (op0, 2);
9892 /* Result is nonzero iff shift count is equal to I. */
9893 code = reverse_condition (code);
9897 /* ... fall through ... */
9900 tem = expand_compound_operation (op0);
9909 /* If testing for equality, we can take the NOT of the constant. */
9910 if (equality_comparison_p
9911 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
9913 op0 = XEXP (op0, 0);
9918 /* If just looking at the sign bit, reverse the sense of the
9920 if (sign_bit_comparison_p)
9922 op0 = XEXP (op0, 0);
9923 code = (code == GE ? LT : GE);
9929 /* If testing for equality, we can take the NEG of the constant. */
9930 if (equality_comparison_p
9931 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
9933 op0 = XEXP (op0, 0);
9938 /* The remaining cases only apply to comparisons with zero. */
9942 /* When X is ABS or is known positive,
9943 (neg X) is < 0 if and only if X != 0. */
9945 if (sign_bit_comparison_p
9946 && (GET_CODE (XEXP (op0, 0)) == ABS
9947 || (mode_width <= HOST_BITS_PER_WIDE_INT
9948 && (nonzero_bits (XEXP (op0, 0), mode)
9949 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
9951 op0 = XEXP (op0, 0);
9952 code = (code == LT ? NE : EQ);
9956 /* If we have NEG of something whose two high-order bits are the
9957 same, we know that "(-a) < 0" is equivalent to "a > 0". */
9958 if (num_sign_bit_copies (op0, mode) >= 2)
9960 op0 = XEXP (op0, 0);
9961 code = swap_condition (code);
9967 /* If we are testing equality and our count is a constant, we
9968 can perform the inverse operation on our RHS. */
9969 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
9970 && (tem = simplify_binary_operation (ROTATERT, mode,
9971 op1, XEXP (op0, 1))) != 0)
9973 op0 = XEXP (op0, 0);
9978 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
9979 a particular bit. Convert it to an AND of a constant of that
9980 bit. This will be converted into a ZERO_EXTRACT. */
9981 if (const_op == 0 && sign_bit_comparison_p
9982 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9983 && mode_width <= HOST_BITS_PER_WIDE_INT)
9985 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
9988 - INTVAL (XEXP (op0, 1)))));
9989 code = (code == LT ? NE : EQ);
9996 /* ABS is ignorable inside an equality comparison with zero. */
9997 if (const_op == 0 && equality_comparison_p)
9999 op0 = XEXP (op0, 0);
10005 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
10006 (compare FOO CONST) if CONST fits in FOO's mode and we
10007 are either testing inequality or have an unsigned
10008 comparison with ZERO_EXTEND or a signed comparison with
10009 SIGN_EXTEND. But don't do it if we don't have a compare
10010 insn of the given mode, since we'd have to revert it
10011 later on, and then we wouldn't know whether to sign- or
10013 mode = GET_MODE (XEXP (op0, 0));
10014 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10015 && ! unsigned_comparison_p
10016 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10017 && ((unsigned HOST_WIDE_INT) const_op
10018 < (((unsigned HOST_WIDE_INT) 1
10019 << (GET_MODE_BITSIZE (mode) - 1))))
10020 && cmp_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
10022 op0 = XEXP (op0, 0);
10028 /* Check for the case where we are comparing A - C1 with C2, that is
10030 (subreg:MODE (plus (A) (-C1))) op (C2)
10032 with C1 a constant, and try to lift the SUBREG, i.e. to do the
10033 comparison in the wider mode. One of the following two conditions
10034 must be true in order for this to be valid:
10036 1. The mode extension results in the same bit pattern being added
10037 on both sides and the comparison is equality or unsigned. As
10038 C2 has been truncated to fit in MODE, the pattern can only be
10041 2. The mode extension results in the sign bit being copied on
10044 The difficulty here is that we have predicates for A but not for
10045 (A - C1) so we need to check that C1 is within proper bounds so
10046 as to perturbate A as little as possible. */
10048 if (mode_width <= HOST_BITS_PER_WIDE_INT
10049 && subreg_lowpart_p (op0)
10050 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) > mode_width
10051 && GET_CODE (SUBREG_REG (op0)) == PLUS
10052 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT)
10054 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
10055 rtx a = XEXP (SUBREG_REG (op0), 0);
10056 HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
10059 && (unsigned HOST_WIDE_INT) c1
10060 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
10061 && (equality_comparison_p || unsigned_comparison_p)
10062 /* (A - C1) zero-extends if it is positive and sign-extends
10063 if it is negative, C2 both zero- and sign-extends. */
10064 && ((0 == (nonzero_bits (a, inner_mode)
10065 & ~GET_MODE_MASK (mode))
10067 /* (A - C1) sign-extends if it is positive and 1-extends
10068 if it is negative, C2 both sign- and 1-extends. */
10069 || (num_sign_bit_copies (a, inner_mode)
10070 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10073 || ((unsigned HOST_WIDE_INT) c1
10074 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
10075 /* (A - C1) always sign-extends, like C2. */
10076 && num_sign_bit_copies (a, inner_mode)
10077 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10078 - (mode_width - 1))))
10080 op0 = SUBREG_REG (op0);
10085 /* If the inner mode is narrower and we are extracting the low part,
10086 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10087 if (subreg_lowpart_p (op0)
10088 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10089 /* Fall through */ ;
10093 /* ... fall through ... */
10096 mode = GET_MODE (XEXP (op0, 0));
10097 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10098 && (unsigned_comparison_p || equality_comparison_p)
10099 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10100 && ((unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode))
10101 && cmp_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
10103 op0 = XEXP (op0, 0);
10109 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10110 this for equality comparisons due to pathological cases involving
10112 if (equality_comparison_p
10113 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10114 op1, XEXP (op0, 1))))
10116 op0 = XEXP (op0, 0);
10121 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10122 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10123 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10125 op0 = XEXP (XEXP (op0, 0), 0);
10126 code = (code == LT ? EQ : NE);
10132 /* We used to optimize signed comparisons against zero, but that
10133 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10134 arrive here as equality comparisons, or (GEU, LTU) are
10135 optimized away. No need to special-case them. */
10137 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10138 (eq B (minus A C)), whichever simplifies. We can only do
10139 this for equality comparisons due to pathological cases involving
10141 if (equality_comparison_p
10142 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10143 XEXP (op0, 1), op1)))
10145 op0 = XEXP (op0, 0);
10150 if (equality_comparison_p
10151 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10152 XEXP (op0, 0), op1)))
10154 op0 = XEXP (op0, 1);
10159 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10160 of bits in X minus 1, is one iff X > 0. */
10161 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10162 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10163 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1))
10165 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10167 op0 = XEXP (op0, 1);
10168 code = (code == GE ? LE : GT);
10174 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10175 if C is zero or B is a constant. */
10176 if (equality_comparison_p
10177 && 0 != (tem = simplify_binary_operation (XOR, mode,
10178 XEXP (op0, 1), op1)))
10180 op0 = XEXP (op0, 0);
10187 case UNEQ: case LTGT:
10188 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
10189 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
10190 case UNORDERED: case ORDERED:
10191 /* We can't do anything if OP0 is a condition code value, rather
10192 than an actual data value. */
10194 || CC0_P (XEXP (op0, 0))
10195 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10198 /* Get the two operands being compared. */
10199 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10200 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10202 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10204 /* Check for the cases where we simply want the result of the
10205 earlier test or the opposite of that result. */
10206 if (code == NE || code == EQ
10207 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10208 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10209 && (STORE_FLAG_VALUE
10210 & (((HOST_WIDE_INT) 1
10211 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10212 && (code == LT || code == GE)))
10214 enum rtx_code new_code;
10215 if (code == LT || code == NE)
10216 new_code = GET_CODE (op0);
10218 new_code = reversed_comparison_code (op0, NULL);
10220 if (new_code != UNKNOWN)
10231 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10233 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10234 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10235 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10237 op0 = XEXP (op0, 1);
10238 code = (code == GE ? GT : LE);
10244 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10245 will be converted to a ZERO_EXTRACT later. */
10246 if (const_op == 0 && equality_comparison_p
10247 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10248 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10250 op0 = simplify_and_const_int
10251 (NULL_RTX, mode, gen_rtx_LSHIFTRT (mode,
10253 XEXP (XEXP (op0, 0), 1)),
10254 (HOST_WIDE_INT) 1);
10258 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10259 zero and X is a comparison and C1 and C2 describe only bits set
10260 in STORE_FLAG_VALUE, we can compare with X. */
10261 if (const_op == 0 && equality_comparison_p
10262 && mode_width <= HOST_BITS_PER_WIDE_INT
10263 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10264 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10265 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10266 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10267 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10269 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10270 << INTVAL (XEXP (XEXP (op0, 0), 1)));
10271 if ((~STORE_FLAG_VALUE & mask) == 0
10272 && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
10273 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10274 && COMPARISON_P (tem))))
10276 op0 = XEXP (XEXP (op0, 0), 0);
10281 /* If we are doing an equality comparison of an AND of a bit equal
10282 to the sign bit, replace this with a LT or GE comparison of
10283 the underlying value. */
10284 if (equality_comparison_p
10286 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10287 && mode_width <= HOST_BITS_PER_WIDE_INT
10288 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10289 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10291 op0 = XEXP (op0, 0);
10292 code = (code == EQ ? GE : LT);
10296 /* If this AND operation is really a ZERO_EXTEND from a narrower
10297 mode, the constant fits within that mode, and this is either an
10298 equality or unsigned comparison, try to do this comparison in
10299 the narrower mode. */
10300 if ((equality_comparison_p || unsigned_comparison_p)
10301 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10302 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10303 & GET_MODE_MASK (mode))
10305 && const_op >> i == 0
10306 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
10308 op0 = gen_lowpart (tmode, XEXP (op0, 0));
10312 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
10313 fits in both M1 and M2 and the SUBREG is either paradoxical
10314 or represents the low part, permute the SUBREG and the AND
10316 if (GET_CODE (XEXP (op0, 0)) == SUBREG)
10318 unsigned HOST_WIDE_INT c1;
10319 tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
10320 /* Require an integral mode, to avoid creating something like
10322 if (SCALAR_INT_MODE_P (tmode)
10323 /* It is unsafe to commute the AND into the SUBREG if the
10324 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
10325 not defined. As originally written the upper bits
10326 have a defined value due to the AND operation.
10327 However, if we commute the AND inside the SUBREG then
10328 they no longer have defined values and the meaning of
10329 the code has been changed. */
10331 #ifdef WORD_REGISTER_OPERATIONS
10332 || (mode_width > GET_MODE_BITSIZE (tmode)
10333 && mode_width <= BITS_PER_WORD)
10335 || (mode_width <= GET_MODE_BITSIZE (tmode)
10336 && subreg_lowpart_p (XEXP (op0, 0))))
10337 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10338 && mode_width <= HOST_BITS_PER_WIDE_INT
10339 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
10340 && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
10341 && (c1 & ~GET_MODE_MASK (tmode)) == 0
10343 && c1 != GET_MODE_MASK (tmode))
10345 op0 = simplify_gen_binary (AND, tmode,
10346 SUBREG_REG (XEXP (op0, 0)),
10347 gen_int_mode (c1, tmode));
10348 op0 = gen_lowpart (mode, op0);
10353 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
10354 if (const_op == 0 && equality_comparison_p
10355 && XEXP (op0, 1) == const1_rtx
10356 && GET_CODE (XEXP (op0, 0)) == NOT)
10358 op0 = simplify_and_const_int
10359 (NULL_RTX, mode, XEXP (XEXP (op0, 0), 0), (HOST_WIDE_INT) 1);
10360 code = (code == NE ? EQ : NE);
10364 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10365 (eq (and (lshiftrt X) 1) 0).
10366 Also handle the case where (not X) is expressed using xor. */
10367 if (const_op == 0 && equality_comparison_p
10368 && XEXP (op0, 1) == const1_rtx
10369 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
10371 rtx shift_op = XEXP (XEXP (op0, 0), 0);
10372 rtx shift_count = XEXP (XEXP (op0, 0), 1);
10374 if (GET_CODE (shift_op) == NOT
10375 || (GET_CODE (shift_op) == XOR
10376 && GET_CODE (XEXP (shift_op, 1)) == CONST_INT
10377 && GET_CODE (shift_count) == CONST_INT
10378 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
10379 && (INTVAL (XEXP (shift_op, 1))
10380 == (HOST_WIDE_INT) 1 << INTVAL (shift_count))))
10382 op0 = simplify_and_const_int
10384 gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count),
10385 (HOST_WIDE_INT) 1);
10386 code = (code == NE ? EQ : NE);
10393 /* If we have (compare (ashift FOO N) (const_int C)) and
10394 the high order N bits of FOO (N+1 if an inequality comparison)
10395 are known to be zero, we can do this by comparing FOO with C
10396 shifted right N bits so long as the low-order N bits of C are
10398 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10399 && INTVAL (XEXP (op0, 1)) >= 0
10400 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10401 < HOST_BITS_PER_WIDE_INT)
10403 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10404 && mode_width <= HOST_BITS_PER_WIDE_INT
10405 && (nonzero_bits (XEXP (op0, 0), mode)
10406 & ~(mask >> (INTVAL (XEXP (op0, 1))
10407 + ! equality_comparison_p))) == 0)
10409 /* We must perform a logical shift, not an arithmetic one,
10410 as we want the top N bits of C to be zero. */
10411 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
10413 temp >>= INTVAL (XEXP (op0, 1));
10414 op1 = gen_int_mode (temp, mode);
10415 op0 = XEXP (op0, 0);
10419 /* If we are doing a sign bit comparison, it means we are testing
10420 a particular bit. Convert it to the appropriate AND. */
10421 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10422 && mode_width <= HOST_BITS_PER_WIDE_INT)
10424 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10427 - INTVAL (XEXP (op0, 1)))));
10428 code = (code == LT ? NE : EQ);
10432 /* If this an equality comparison with zero and we are shifting
10433 the low bit to the sign bit, we can convert this to an AND of the
10435 if (const_op == 0 && equality_comparison_p
10436 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10437 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10440 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10441 (HOST_WIDE_INT) 1);
10447 /* If this is an equality comparison with zero, we can do this
10448 as a logical shift, which might be much simpler. */
10449 if (equality_comparison_p && const_op == 0
10450 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10452 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10454 INTVAL (XEXP (op0, 1)));
10458 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10459 do the comparison in a narrower mode. */
10460 if (! unsigned_comparison_p
10461 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10462 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10463 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10464 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10465 MODE_INT, 1)) != BLKmode
10466 && (((unsigned HOST_WIDE_INT) const_op
10467 + (GET_MODE_MASK (tmode) >> 1) + 1)
10468 <= GET_MODE_MASK (tmode)))
10470 op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
10474 /* Likewise if OP0 is a PLUS of a sign extension with a
10475 constant, which is usually represented with the PLUS
10476 between the shifts. */
10477 if (! unsigned_comparison_p
10478 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10479 && GET_CODE (XEXP (op0, 0)) == PLUS
10480 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10481 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
10482 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
10483 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10484 MODE_INT, 1)) != BLKmode
10485 && (((unsigned HOST_WIDE_INT) const_op
10486 + (GET_MODE_MASK (tmode) >> 1) + 1)
10487 <= GET_MODE_MASK (tmode)))
10489 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
10490 rtx add_const = XEXP (XEXP (op0, 0), 1);
10491 rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
10492 add_const, XEXP (op0, 1));
10494 op0 = simplify_gen_binary (PLUS, tmode,
10495 gen_lowpart (tmode, inner),
10500 /* ... fall through ... */
10502 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10503 the low order N bits of FOO are known to be zero, we can do this
10504 by comparing FOO with C shifted left N bits so long as no
10505 overflow occurs. */
10506 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10507 && INTVAL (XEXP (op0, 1)) >= 0
10508 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10509 && mode_width <= HOST_BITS_PER_WIDE_INT
10510 && (nonzero_bits (XEXP (op0, 0), mode)
10511 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
10512 && (((unsigned HOST_WIDE_INT) const_op
10513 + (GET_CODE (op0) != LSHIFTRT
10514 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
10517 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
10519 /* If the shift was logical, then we must make the condition
10521 if (GET_CODE (op0) == LSHIFTRT)
10522 code = unsigned_condition (code);
10524 const_op <<= INTVAL (XEXP (op0, 1));
10525 op1 = GEN_INT (const_op);
10526 op0 = XEXP (op0, 0);
10530 /* If we are using this shift to extract just the sign bit, we
10531 can replace this with an LT or GE comparison. */
10533 && (equality_comparison_p || sign_bit_comparison_p)
10534 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10535 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10538 op0 = XEXP (op0, 0);
10539 code = (code == NE || code == GT ? LT : GE);
10551 /* Now make any compound operations involved in this comparison. Then,
10552 check for an outmost SUBREG on OP0 that is not doing anything or is
10553 paradoxical. The latter transformation must only be performed when
10554 it is known that the "extra" bits will be the same in op0 and op1 or
10555 that they don't matter. There are three cases to consider:
10557 1. SUBREG_REG (op0) is a register. In this case the bits are don't
10558 care bits and we can assume they have any convenient value. So
10559 making the transformation is safe.
10561 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
10562 In this case the upper bits of op0 are undefined. We should not make
10563 the simplification in that case as we do not know the contents of
10566 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
10567 UNKNOWN. In that case we know those bits are zeros or ones. We must
10568 also be sure that they are the same as the upper bits of op1.
10570 We can never remove a SUBREG for a non-equality comparison because
10571 the sign bit is in a different place in the underlying object. */
10573 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
10574 op1 = make_compound_operation (op1, SET);
10576 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10577 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10578 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
10579 && (code == NE || code == EQ))
10581 if (GET_MODE_SIZE (GET_MODE (op0))
10582 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
10584 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
10586 if (REG_P (SUBREG_REG (op0)))
10588 op0 = SUBREG_REG (op0);
10589 op1 = gen_lowpart (GET_MODE (op0), op1);
10592 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10593 <= HOST_BITS_PER_WIDE_INT)
10594 && (nonzero_bits (SUBREG_REG (op0),
10595 GET_MODE (SUBREG_REG (op0)))
10596 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
10598 tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
10600 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
10601 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
10602 op0 = SUBREG_REG (op0), op1 = tem;
10606 /* We now do the opposite procedure: Some machines don't have compare
10607 insns in all modes. If OP0's mode is an integer mode smaller than a
10608 word and we can't do a compare in that mode, see if there is a larger
10609 mode for which we can do the compare. There are a number of cases in
10610 which we can use the wider mode. */
10612 mode = GET_MODE (op0);
10613 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10614 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
10615 && ! have_insn_for (COMPARE, mode))
10616 for (tmode = GET_MODE_WIDER_MODE (mode);
10618 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
10619 tmode = GET_MODE_WIDER_MODE (tmode))
10620 if (have_insn_for (COMPARE, tmode))
10624 /* If the only nonzero bits in OP0 and OP1 are those in the
10625 narrower mode and this is an equality or unsigned comparison,
10626 we can use the wider mode. Similarly for sign-extended
10627 values, in which case it is true for all comparisons. */
10628 zero_extended = ((code == EQ || code == NE
10629 || code == GEU || code == GTU
10630 || code == LEU || code == LTU)
10631 && (nonzero_bits (op0, tmode)
10632 & ~GET_MODE_MASK (mode)) == 0
10633 && ((GET_CODE (op1) == CONST_INT
10634 || (nonzero_bits (op1, tmode)
10635 & ~GET_MODE_MASK (mode)) == 0)));
10638 || ((num_sign_bit_copies (op0, tmode)
10639 > (unsigned int) (GET_MODE_BITSIZE (tmode)
10640 - GET_MODE_BITSIZE (mode)))
10641 && (num_sign_bit_copies (op1, tmode)
10642 > (unsigned int) (GET_MODE_BITSIZE (tmode)
10643 - GET_MODE_BITSIZE (mode)))))
10645 /* If OP0 is an AND and we don't have an AND in MODE either,
10646 make a new AND in the proper mode. */
10647 if (GET_CODE (op0) == AND
10648 && !have_insn_for (AND, mode))
10649 op0 = simplify_gen_binary (AND, tmode,
10650 gen_lowpart (tmode,
10652 gen_lowpart (tmode,
10655 op0 = gen_lowpart (tmode, op0);
10656 if (zero_extended && GET_CODE (op1) == CONST_INT)
10657 op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode));
10658 op1 = gen_lowpart (tmode, op1);
10662 /* If this is a test for negative, we can make an explicit
10663 test of the sign bit. */
10665 if (op1 == const0_rtx && (code == LT || code == GE)
10666 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10668 op0 = simplify_gen_binary (AND, tmode,
10669 gen_lowpart (tmode, op0),
10670 GEN_INT ((HOST_WIDE_INT) 1
10671 << (GET_MODE_BITSIZE (mode)
10673 code = (code == LT) ? NE : EQ;
10678 #ifdef CANONICALIZE_COMPARISON
10679 /* If this machine only supports a subset of valid comparisons, see if we
10680 can convert an unsupported one into a supported one. */
10681 CANONICALIZE_COMPARISON (code, op0, op1);
10690 /* Utility function for record_value_for_reg. Count number of
10695 enum rtx_code code = GET_CODE (x);
10699 if (GET_RTX_CLASS (code) == '2'
10700 || GET_RTX_CLASS (code) == 'c')
10702 rtx x0 = XEXP (x, 0);
10703 rtx x1 = XEXP (x, 1);
10706 return 1 + 2 * count_rtxs (x0);
10708 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
10709 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
10710 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
10711 return 2 + 2 * count_rtxs (x0)
10712 + count_rtxs (x == XEXP (x1, 0)
10713 ? XEXP (x1, 1) : XEXP (x1, 0));
10715 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
10716 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
10717 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
10718 return 2 + 2 * count_rtxs (x1)
10719 + count_rtxs (x == XEXP (x0, 0)
10720 ? XEXP (x0, 1) : XEXP (x0, 0));
10723 fmt = GET_RTX_FORMAT (code);
10724 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10726 ret += count_rtxs (XEXP (x, i));
10731 /* Utility function for following routine. Called when X is part of a value
10732 being stored into last_set_value. Sets last_set_table_tick
10733 for each register mentioned. Similar to mention_regs in cse.c */
10736 update_table_tick (rtx x)
10738 enum rtx_code code = GET_CODE (x);
10739 const char *fmt = GET_RTX_FORMAT (code);
10744 unsigned int regno = REGNO (x);
10745 unsigned int endregno
10746 = regno + (regno < FIRST_PSEUDO_REGISTER
10747 ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
10750 for (r = regno; r < endregno; r++)
10751 reg_stat[r].last_set_table_tick = label_tick;
10756 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10757 /* Note that we can't have an "E" in values stored; see
10758 get_last_value_validate. */
10761 /* Check for identical subexpressions. If x contains
10762 identical subexpression we only have to traverse one of
10764 if (i == 0 && ARITHMETIC_P (x))
10766 /* Note that at this point x1 has already been
10768 rtx x0 = XEXP (x, 0);
10769 rtx x1 = XEXP (x, 1);
10771 /* If x0 and x1 are identical then there is no need to
10776 /* If x0 is identical to a subexpression of x1 then while
10777 processing x1, x0 has already been processed. Thus we
10778 are done with x. */
10779 if (ARITHMETIC_P (x1)
10780 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
10783 /* If x1 is identical to a subexpression of x0 then we
10784 still have to process the rest of x0. */
10785 if (ARITHMETIC_P (x0)
10786 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
10788 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
10793 update_table_tick (XEXP (x, i));
10797 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
10798 are saying that the register is clobbered and we no longer know its
10799 value. If INSN is zero, don't update reg_stat[].last_set; this is
10800 only permitted with VALUE also zero and is used to invalidate the
10804 record_value_for_reg (rtx reg, rtx insn, rtx value)
10806 unsigned int regno = REGNO (reg);
10807 unsigned int endregno
10808 = regno + (regno < FIRST_PSEUDO_REGISTER
10809 ? hard_regno_nregs[regno][GET_MODE (reg)] : 1);
10812 /* If VALUE contains REG and we have a previous value for REG, substitute
10813 the previous value. */
10814 if (value && insn && reg_overlap_mentioned_p (reg, value))
10818 /* Set things up so get_last_value is allowed to see anything set up to
10820 subst_low_cuid = INSN_CUID (insn);
10821 tem = get_last_value (reg);
10823 /* If TEM is simply a binary operation with two CLOBBERs as operands,
10824 it isn't going to be useful and will take a lot of time to process,
10825 so just use the CLOBBER. */
10829 if (ARITHMETIC_P (tem)
10830 && GET_CODE (XEXP (tem, 0)) == CLOBBER
10831 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
10832 tem = XEXP (tem, 0);
10833 else if (count_occurrences (value, reg, 1) >= 2)
10835 /* If there are two or more occurrences of REG in VALUE,
10836 prevent the value from growing too much. */
10837 if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
10838 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
10841 value = replace_rtx (copy_rtx (value), reg, tem);
10845 /* For each register modified, show we don't know its value, that
10846 we don't know about its bitwise content, that its value has been
10847 updated, and that we don't know the location of the death of the
10849 for (i = regno; i < endregno; i++)
10852 reg_stat[i].last_set = insn;
10854 reg_stat[i].last_set_value = 0;
10855 reg_stat[i].last_set_mode = 0;
10856 reg_stat[i].last_set_nonzero_bits = 0;
10857 reg_stat[i].last_set_sign_bit_copies = 0;
10858 reg_stat[i].last_death = 0;
10859 reg_stat[i].truncated_to_mode = 0;
10862 /* Mark registers that are being referenced in this value. */
10864 update_table_tick (value);
10866 /* Now update the status of each register being set.
10867 If someone is using this register in this block, set this register
10868 to invalid since we will get confused between the two lives in this
10869 basic block. This makes using this register always invalid. In cse, we
10870 scan the table to invalidate all entries using this register, but this
10871 is too much work for us. */
10873 for (i = regno; i < endregno; i++)
10875 reg_stat[i].last_set_label = label_tick;
10876 if (!insn || (value && reg_stat[i].last_set_table_tick == label_tick))
10877 reg_stat[i].last_set_invalid = 1;
10879 reg_stat[i].last_set_invalid = 0;
10882 /* The value being assigned might refer to X (like in "x++;"). In that
10883 case, we must replace it with (clobber (const_int 0)) to prevent
10885 if (value && ! get_last_value_validate (&value, insn,
10886 reg_stat[regno].last_set_label, 0))
10888 value = copy_rtx (value);
10889 if (! get_last_value_validate (&value, insn,
10890 reg_stat[regno].last_set_label, 1))
10894 /* For the main register being modified, update the value, the mode, the
10895 nonzero bits, and the number of sign bit copies. */
10897 reg_stat[regno].last_set_value = value;
10901 enum machine_mode mode = GET_MODE (reg);
10902 subst_low_cuid = INSN_CUID (insn);
10903 reg_stat[regno].last_set_mode = mode;
10904 if (GET_MODE_CLASS (mode) == MODE_INT
10905 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10906 mode = nonzero_bits_mode;
10907 reg_stat[regno].last_set_nonzero_bits = nonzero_bits (value, mode);
10908 reg_stat[regno].last_set_sign_bit_copies
10909 = num_sign_bit_copies (value, GET_MODE (reg));
10913 /* Called via note_stores from record_dead_and_set_regs to handle one
10914 SET or CLOBBER in an insn. DATA is the instruction in which the
10915 set is occurring. */
10918 record_dead_and_set_regs_1 (rtx dest, rtx setter, void *data)
10920 rtx record_dead_insn = (rtx) data;
10922 if (GET_CODE (dest) == SUBREG)
10923 dest = SUBREG_REG (dest);
10925 if (!record_dead_insn)
10928 record_value_for_reg (dest, NULL_RTX, NULL_RTX);
10934 /* If we are setting the whole register, we know its value. Otherwise
10935 show that we don't know the value. We can handle SUBREG in
10937 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
10938 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
10939 else if (GET_CODE (setter) == SET
10940 && GET_CODE (SET_DEST (setter)) == SUBREG
10941 && SUBREG_REG (SET_DEST (setter)) == dest
10942 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
10943 && subreg_lowpart_p (SET_DEST (setter)))
10944 record_value_for_reg (dest, record_dead_insn,
10945 gen_lowpart (GET_MODE (dest),
10946 SET_SRC (setter)));
10948 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
10950 else if (MEM_P (dest)
10951 /* Ignore pushes, they clobber nothing. */
10952 && ! push_operand (dest, GET_MODE (dest)))
10953 mem_last_set = INSN_CUID (record_dead_insn);
10956 /* Update the records of when each REG was most recently set or killed
10957 for the things done by INSN. This is the last thing done in processing
10958 INSN in the combiner loop.
10960 We update reg_stat[], in particular fields last_set, last_set_value,
10961 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
10962 last_death, and also the similar information mem_last_set (which insn
10963 most recently modified memory) and last_call_cuid (which insn was the
10964 most recent subroutine call). */
10967 record_dead_and_set_regs (rtx insn)
10972 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
10974 if (REG_NOTE_KIND (link) == REG_DEAD
10975 && REG_P (XEXP (link, 0)))
10977 unsigned int regno = REGNO (XEXP (link, 0));
10978 unsigned int endregno
10979 = regno + (regno < FIRST_PSEUDO_REGISTER
10980 ? hard_regno_nregs[regno][GET_MODE (XEXP (link, 0))]
10983 for (i = regno; i < endregno; i++)
10984 reg_stat[i].last_death = insn;
10986 else if (REG_NOTE_KIND (link) == REG_INC)
10987 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
10992 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
10993 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
10995 reg_stat[i].last_set_value = 0;
10996 reg_stat[i].last_set_mode = 0;
10997 reg_stat[i].last_set_nonzero_bits = 0;
10998 reg_stat[i].last_set_sign_bit_copies = 0;
10999 reg_stat[i].last_death = 0;
11000 reg_stat[i].truncated_to_mode = 0;
11003 last_call_cuid = mem_last_set = INSN_CUID (insn);
11005 /* We can't combine into a call pattern. Remember, though, that
11006 the return value register is set at this CUID. We could
11007 still replace a register with the return value from the
11008 wrong subroutine call! */
11009 note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX);
11012 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11015 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11016 register present in the SUBREG, so for each such SUBREG go back and
11017 adjust nonzero and sign bit information of the registers that are
11018 known to have some zero/sign bits set.
11020 This is needed because when combine blows the SUBREGs away, the
11021 information on zero/sign bits is lost and further combines can be
11022 missed because of that. */
11025 record_promoted_value (rtx insn, rtx subreg)
11028 unsigned int regno = REGNO (SUBREG_REG (subreg));
11029 enum machine_mode mode = GET_MODE (subreg);
11031 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11034 for (links = LOG_LINKS (insn); links;)
11036 insn = XEXP (links, 0);
11037 set = single_set (insn);
11039 if (! set || !REG_P (SET_DEST (set))
11040 || REGNO (SET_DEST (set)) != regno
11041 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11043 links = XEXP (links, 1);
11047 if (reg_stat[regno].last_set == insn)
11049 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
11050 reg_stat[regno].last_set_nonzero_bits &= GET_MODE_MASK (mode);
11053 if (REG_P (SET_SRC (set)))
11055 regno = REGNO (SET_SRC (set));
11056 links = LOG_LINKS (insn);
11063 /* Check if X, a register, is known to contain a value already
11064 truncated to MODE. In this case we can use a subreg to refer to
11065 the truncated value even though in the generic case we would need
11066 an explicit truncation. */
11069 reg_truncated_to_mode (enum machine_mode mode, rtx x)
11071 enum machine_mode truncated = reg_stat[REGNO (x)].truncated_to_mode;
11073 if (truncated == 0 || reg_stat[REGNO (x)].truncation_label != label_tick)
11075 if (GET_MODE_SIZE (truncated) <= GET_MODE_SIZE (mode))
11077 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
11078 GET_MODE_BITSIZE (truncated)))
11083 /* X is a REG or a SUBREG. If X is some sort of a truncation record
11084 it. For non-TRULY_NOOP_TRUNCATION targets we might be able to turn
11085 a truncate into a subreg using this information. */
11088 record_truncated_value (rtx x)
11090 enum machine_mode truncated_mode;
11092 if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
11094 enum machine_mode original_mode = GET_MODE (SUBREG_REG (x));
11095 truncated_mode = GET_MODE (x);
11097 if (GET_MODE_SIZE (original_mode) <= GET_MODE_SIZE (truncated_mode))
11100 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (truncated_mode),
11101 GET_MODE_BITSIZE (original_mode)))
11104 x = SUBREG_REG (x);
11106 /* ??? For hard-regs we now record everthing. We might be able to
11107 optimize this using last_set_mode. */
11108 else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
11109 truncated_mode = GET_MODE (x);
11113 if (reg_stat[REGNO (x)].truncated_to_mode == 0
11114 || reg_stat[REGNO (x)].truncation_label < label_tick
11115 || (GET_MODE_SIZE (truncated_mode)
11116 < GET_MODE_SIZE (reg_stat[REGNO (x)].truncated_to_mode)))
11118 reg_stat[REGNO (x)].truncated_to_mode = truncated_mode;
11119 reg_stat[REGNO (x)].truncation_label = label_tick;
11123 /* Scan X for promoted SUBREGs and truncated REGs. For each one
11124 found, note what it implies to the registers used in it. */
11127 check_conversions (rtx insn, rtx x)
11129 if (GET_CODE (x) == SUBREG || REG_P (x))
11131 if (GET_CODE (x) == SUBREG
11132 && SUBREG_PROMOTED_VAR_P (x)
11133 && REG_P (SUBREG_REG (x)))
11134 record_promoted_value (insn, x);
11136 record_truncated_value (x);
11140 const char *format = GET_RTX_FORMAT (GET_CODE (x));
11143 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11147 check_conversions (insn, XEXP (x, i));
11151 if (XVEC (x, i) != 0)
11152 for (j = 0; j < XVECLEN (x, i); j++)
11153 check_conversions (insn, XVECEXP (x, i, j));
11159 /* Utility routine for the following function. Verify that all the registers
11160 mentioned in *LOC are valid when *LOC was part of a value set when
11161 label_tick == TICK. Return 0 if some are not.
11163 If REPLACE is nonzero, replace the invalid reference with
11164 (clobber (const_int 0)) and return 1. This replacement is useful because
11165 we often can get useful information about the form of a value (e.g., if
11166 it was produced by a shift that always produces -1 or 0) even though
11167 we don't know exactly what registers it was produced from. */
11170 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
11173 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11174 int len = GET_RTX_LENGTH (GET_CODE (x));
11179 unsigned int regno = REGNO (x);
11180 unsigned int endregno
11181 = regno + (regno < FIRST_PSEUDO_REGISTER
11182 ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
11185 for (j = regno; j < endregno; j++)
11186 if (reg_stat[j].last_set_invalid
11187 /* If this is a pseudo-register that was only set once and not
11188 live at the beginning of the function, it is always valid. */
11189 || (! (regno >= FIRST_PSEUDO_REGISTER
11190 && REG_N_SETS (regno) == 1
11191 && (! REGNO_REG_SET_P
11192 (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
11194 && reg_stat[j].last_set_label > tick))
11197 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11203 /* If this is a memory reference, make sure that there were
11204 no stores after it that might have clobbered the value. We don't
11205 have alias info, so we assume any store invalidates it. */
11206 else if (MEM_P (x) && !MEM_READONLY_P (x)
11207 && INSN_CUID (insn) <= mem_last_set)
11210 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11214 for (i = 0; i < len; i++)
11218 /* Check for identical subexpressions. If x contains
11219 identical subexpression we only have to traverse one of
11221 if (i == 1 && ARITHMETIC_P (x))
11223 /* Note that at this point x0 has already been checked
11224 and found valid. */
11225 rtx x0 = XEXP (x, 0);
11226 rtx x1 = XEXP (x, 1);
11228 /* If x0 and x1 are identical then x is also valid. */
11232 /* If x1 is identical to a subexpression of x0 then
11233 while checking x0, x1 has already been checked. Thus
11234 it is valid and so as x. */
11235 if (ARITHMETIC_P (x0)
11236 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11239 /* If x0 is identical to a subexpression of x1 then x is
11240 valid iff the rest of x1 is valid. */
11241 if (ARITHMETIC_P (x1)
11242 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11244 get_last_value_validate (&XEXP (x1,
11245 x0 == XEXP (x1, 0) ? 1 : 0),
11246 insn, tick, replace);
11249 if (get_last_value_validate (&XEXP (x, i), insn, tick,
11253 /* Don't bother with these. They shouldn't occur anyway. */
11254 else if (fmt[i] == 'E')
11258 /* If we haven't found a reason for it to be invalid, it is valid. */
11262 /* Get the last value assigned to X, if known. Some registers
11263 in the value may be replaced with (clobber (const_int 0)) if their value
11264 is known longer known reliably. */
11267 get_last_value (rtx x)
11269 unsigned int regno;
11272 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11273 then convert it to the desired mode. If this is a paradoxical SUBREG,
11274 we cannot predict what values the "extra" bits might have. */
11275 if (GET_CODE (x) == SUBREG
11276 && subreg_lowpart_p (x)
11277 && (GET_MODE_SIZE (GET_MODE (x))
11278 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11279 && (value = get_last_value (SUBREG_REG (x))) != 0)
11280 return gen_lowpart (GET_MODE (x), value);
11286 value = reg_stat[regno].last_set_value;
11288 /* If we don't have a value, or if it isn't for this basic block and
11289 it's either a hard register, set more than once, or it's a live
11290 at the beginning of the function, return 0.
11292 Because if it's not live at the beginning of the function then the reg
11293 is always set before being used (is never used without being set).
11294 And, if it's set only once, and it's always set before use, then all
11295 uses must have the same last value, even if it's not from this basic
11299 || (reg_stat[regno].last_set_label != label_tick
11300 && (regno < FIRST_PSEUDO_REGISTER
11301 || REG_N_SETS (regno) != 1
11302 || (REGNO_REG_SET_P
11303 (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
11307 /* If the value was set in a later insn than the ones we are processing,
11308 we can't use it even if the register was only set once. */
11309 if (INSN_CUID (reg_stat[regno].last_set) >= subst_low_cuid)
11312 /* If the value has all its registers valid, return it. */
11313 if (get_last_value_validate (&value, reg_stat[regno].last_set,
11314 reg_stat[regno].last_set_label, 0))
11317 /* Otherwise, make a copy and replace any invalid register with
11318 (clobber (const_int 0)). If that fails for some reason, return 0. */
11320 value = copy_rtx (value);
11321 if (get_last_value_validate (&value, reg_stat[regno].last_set,
11322 reg_stat[regno].last_set_label, 1))
11328 /* Return nonzero if expression X refers to a REG or to memory
11329 that is set in an instruction more recent than FROM_CUID. */
11332 use_crosses_set_p (rtx x, int from_cuid)
11336 enum rtx_code code = GET_CODE (x);
11340 unsigned int regno = REGNO (x);
11341 unsigned endreg = regno + (regno < FIRST_PSEUDO_REGISTER
11342 ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
11344 #ifdef PUSH_ROUNDING
11345 /* Don't allow uses of the stack pointer to be moved,
11346 because we don't know whether the move crosses a push insn. */
11347 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11350 for (; regno < endreg; regno++)
11351 if (reg_stat[regno].last_set
11352 && INSN_CUID (reg_stat[regno].last_set) > from_cuid)
11357 if (code == MEM && mem_last_set > from_cuid)
11360 fmt = GET_RTX_FORMAT (code);
11362 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11367 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11368 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
11371 else if (fmt[i] == 'e'
11372 && use_crosses_set_p (XEXP (x, i), from_cuid))
11378 /* Define three variables used for communication between the following
11381 static unsigned int reg_dead_regno, reg_dead_endregno;
11382 static int reg_dead_flag;
11384 /* Function called via note_stores from reg_dead_at_p.
11386 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11387 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11390 reg_dead_at_p_1 (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
11392 unsigned int regno, endregno;
11397 regno = REGNO (dest);
11398 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
11399 ? hard_regno_nregs[regno][GET_MODE (dest)] : 1);
11401 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11402 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11405 /* Return nonzero if REG is known to be dead at INSN.
11407 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11408 referencing REG, it is dead. If we hit a SET referencing REG, it is
11409 live. Otherwise, see if it is live or dead at the start of the basic
11410 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11411 must be assumed to be always live. */
11414 reg_dead_at_p (rtx reg, rtx insn)
11419 /* Set variables for reg_dead_at_p_1. */
11420 reg_dead_regno = REGNO (reg);
11421 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
11422 ? hard_regno_nregs[reg_dead_regno]
11428 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
11429 we allow the machine description to decide whether use-and-clobber
11430 patterns are OK. */
11431 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11433 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11434 if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
11438 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11439 beginning of function. */
11440 for (; insn && !LABEL_P (insn) && !BARRIER_P (insn);
11441 insn = prev_nonnote_insn (insn))
11443 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
11445 return reg_dead_flag == 1 ? 1 : 0;
11447 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11451 /* Get the basic block that we were in. */
11453 block = ENTRY_BLOCK_PTR->next_bb;
11456 FOR_EACH_BB (block)
11457 if (insn == BB_HEAD (block))
11460 if (block == EXIT_BLOCK_PTR)
11464 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11465 if (REGNO_REG_SET_P (block->il.rtl->global_live_at_start, i))
11471 /* Note hard registers in X that are used. This code is similar to
11472 that in flow.c, but much simpler since we don't care about pseudos. */
11475 mark_used_regs_combine (rtx x)
11477 RTX_CODE code = GET_CODE (x);
11478 unsigned int regno;
11491 case ADDR_DIFF_VEC:
11494 /* CC0 must die in the insn after it is set, so we don't need to take
11495 special note of it here. */
11501 /* If we are clobbering a MEM, mark any hard registers inside the
11502 address as used. */
11503 if (MEM_P (XEXP (x, 0)))
11504 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
11509 /* A hard reg in a wide mode may really be multiple registers.
11510 If so, mark all of them just like the first. */
11511 if (regno < FIRST_PSEUDO_REGISTER)
11513 unsigned int endregno, r;
11515 /* None of this applies to the stack, frame or arg pointers. */
11516 if (regno == STACK_POINTER_REGNUM
11517 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11518 || regno == HARD_FRAME_POINTER_REGNUM
11520 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11521 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
11523 || regno == FRAME_POINTER_REGNUM)
11526 endregno = regno + hard_regno_nregs[regno][GET_MODE (x)];
11527 for (r = regno; r < endregno; r++)
11528 SET_HARD_REG_BIT (newpat_used_regs, r);
11534 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11536 rtx testreg = SET_DEST (x);
11538 while (GET_CODE (testreg) == SUBREG
11539 || GET_CODE (testreg) == ZERO_EXTRACT
11540 || GET_CODE (testreg) == STRICT_LOW_PART)
11541 testreg = XEXP (testreg, 0);
11543 if (MEM_P (testreg))
11544 mark_used_regs_combine (XEXP (testreg, 0));
11546 mark_used_regs_combine (SET_SRC (x));
11554 /* Recursively scan the operands of this expression. */
11557 const char *fmt = GET_RTX_FORMAT (code);
11559 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11562 mark_used_regs_combine (XEXP (x, i));
11563 else if (fmt[i] == 'E')
11567 for (j = 0; j < XVECLEN (x, i); j++)
11568 mark_used_regs_combine (XVECEXP (x, i, j));
11574 /* Remove register number REGNO from the dead registers list of INSN.
11576 Return the note used to record the death, if there was one. */
11579 remove_death (unsigned int regno, rtx insn)
11581 rtx note = find_regno_note (insn, REG_DEAD, regno);
11585 REG_N_DEATHS (regno)--;
11586 remove_note (insn, note);
11592 /* For each register (hardware or pseudo) used within expression X, if its
11593 death is in an instruction with cuid between FROM_CUID (inclusive) and
11594 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11595 list headed by PNOTES.
11597 That said, don't move registers killed by maybe_kill_insn.
11599 This is done when X is being merged by combination into TO_INSN. These
11600 notes will then be distributed as needed. */
11603 move_deaths (rtx x, rtx maybe_kill_insn, int from_cuid, rtx to_insn,
11608 enum rtx_code code = GET_CODE (x);
11612 unsigned int regno = REGNO (x);
11613 rtx where_dead = reg_stat[regno].last_death;
11614 rtx before_dead, after_dead;
11616 /* Don't move the register if it gets killed in between from and to. */
11617 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
11618 && ! reg_referenced_p (x, maybe_kill_insn))
11621 /* WHERE_DEAD could be a USE insn made by combine, so first we
11622 make sure that we have insns with valid INSN_CUID values. */
11623 before_dead = where_dead;
11624 while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
11625 before_dead = PREV_INSN (before_dead);
11627 after_dead = where_dead;
11628 while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
11629 after_dead = NEXT_INSN (after_dead);
11631 if (before_dead && after_dead
11632 && INSN_CUID (before_dead) >= from_cuid
11633 && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
11634 || (where_dead != after_dead
11635 && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
11637 rtx note = remove_death (regno, where_dead);
11639 /* It is possible for the call above to return 0. This can occur
11640 when last_death points to I2 or I1 that we combined with.
11641 In that case make a new note.
11643 We must also check for the case where X is a hard register
11644 and NOTE is a death note for a range of hard registers
11645 including X. In that case, we must put REG_DEAD notes for
11646 the remaining registers in place of NOTE. */
11648 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
11649 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11650 > GET_MODE_SIZE (GET_MODE (x))))
11652 unsigned int deadregno = REGNO (XEXP (note, 0));
11653 unsigned int deadend
11654 = (deadregno + hard_regno_nregs[deadregno]
11655 [GET_MODE (XEXP (note, 0))]);
11656 unsigned int ourend
11657 = regno + hard_regno_nregs[regno][GET_MODE (x)];
11660 for (i = deadregno; i < deadend; i++)
11661 if (i < regno || i >= ourend)
11662 REG_NOTES (where_dead)
11663 = gen_rtx_EXPR_LIST (REG_DEAD,
11665 REG_NOTES (where_dead));
11668 /* If we didn't find any note, or if we found a REG_DEAD note that
11669 covers only part of the given reg, and we have a multi-reg hard
11670 register, then to be safe we must check for REG_DEAD notes
11671 for each register other than the first. They could have
11672 their own REG_DEAD notes lying around. */
11673 else if ((note == 0
11675 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11676 < GET_MODE_SIZE (GET_MODE (x)))))
11677 && regno < FIRST_PSEUDO_REGISTER
11678 && hard_regno_nregs[regno][GET_MODE (x)] > 1)
11680 unsigned int ourend
11681 = regno + hard_regno_nregs[regno][GET_MODE (x)];
11682 unsigned int i, offset;
11686 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
11690 for (i = regno + offset; i < ourend; i++)
11691 move_deaths (regno_reg_rtx[i],
11692 maybe_kill_insn, from_cuid, to_insn, &oldnotes);
11695 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
11697 XEXP (note, 1) = *pnotes;
11701 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
11703 REG_N_DEATHS (regno)++;
11709 else if (GET_CODE (x) == SET)
11711 rtx dest = SET_DEST (x);
11713 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
11715 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11716 that accesses one word of a multi-word item, some
11717 piece of everything register in the expression is used by
11718 this insn, so remove any old death. */
11719 /* ??? So why do we test for equality of the sizes? */
11721 if (GET_CODE (dest) == ZERO_EXTRACT
11722 || GET_CODE (dest) == STRICT_LOW_PART
11723 || (GET_CODE (dest) == SUBREG
11724 && (((GET_MODE_SIZE (GET_MODE (dest))
11725 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
11726 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
11727 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
11729 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
11733 /* If this is some other SUBREG, we know it replaces the entire
11734 value, so use that as the destination. */
11735 if (GET_CODE (dest) == SUBREG)
11736 dest = SUBREG_REG (dest);
11738 /* If this is a MEM, adjust deaths of anything used in the address.
11739 For a REG (the only other possibility), the entire value is
11740 being replaced so the old value is not used in this insn. */
11743 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
11748 else if (GET_CODE (x) == CLOBBER)
11751 len = GET_RTX_LENGTH (code);
11752 fmt = GET_RTX_FORMAT (code);
11754 for (i = 0; i < len; i++)
11759 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11760 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
11763 else if (fmt[i] == 'e')
11764 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
11768 /* Return 1 if X is the target of a bit-field assignment in BODY, the
11769 pattern of an insn. X must be a REG. */
11772 reg_bitfield_target_p (rtx x, rtx body)
11776 if (GET_CODE (body) == SET)
11778 rtx dest = SET_DEST (body);
11780 unsigned int regno, tregno, endregno, endtregno;
11782 if (GET_CODE (dest) == ZERO_EXTRACT)
11783 target = XEXP (dest, 0);
11784 else if (GET_CODE (dest) == STRICT_LOW_PART)
11785 target = SUBREG_REG (XEXP (dest, 0));
11789 if (GET_CODE (target) == SUBREG)
11790 target = SUBREG_REG (target);
11792 if (!REG_P (target))
11795 tregno = REGNO (target), regno = REGNO (x);
11796 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
11797 return target == x;
11799 endtregno = tregno + hard_regno_nregs[tregno][GET_MODE (target)];
11800 endregno = regno + hard_regno_nregs[regno][GET_MODE (x)];
11802 return endregno > tregno && regno < endtregno;
11805 else if (GET_CODE (body) == PARALLEL)
11806 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
11807 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
11813 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11814 as appropriate. I3 and I2 are the insns resulting from the combination
11815 insns including FROM (I2 may be zero).
11817 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
11818 not need REG_DEAD notes because they are being substituted for. This
11819 saves searching in the most common cases.
11821 Each note in the list is either ignored or placed on some insns, depending
11822 on the type of note. */
11825 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2,
11828 rtx note, next_note;
11831 for (note = notes; note; note = next_note)
11833 rtx place = 0, place2 = 0;
11835 next_note = XEXP (note, 1);
11836 switch (REG_NOTE_KIND (note))
11840 /* Doesn't matter much where we put this, as long as it's somewhere.
11841 It is preferable to keep these notes on branches, which is most
11842 likely to be i3. */
11846 case REG_VALUE_PROFILE:
11847 /* Just get rid of this note, as it is unused later anyway. */
11850 case REG_NON_LOCAL_GOTO:
11855 gcc_assert (i2 && JUMP_P (i2));
11860 case REG_EH_REGION:
11861 /* These notes must remain with the call or trapping instruction. */
11864 else if (i2 && CALL_P (i2))
11868 gcc_assert (flag_non_call_exceptions);
11869 if (may_trap_p (i3))
11871 else if (i2 && may_trap_p (i2))
11873 /* ??? Otherwise assume we've combined things such that we
11874 can now prove that the instructions can't trap. Drop the
11875 note in this case. */
11881 /* These notes must remain with the call. It should not be
11882 possible for both I2 and I3 to be a call. */
11887 gcc_assert (i2 && CALL_P (i2));
11893 /* Any clobbers for i3 may still exist, and so we must process
11894 REG_UNUSED notes from that insn.
11896 Any clobbers from i2 or i1 can only exist if they were added by
11897 recog_for_combine. In that case, recog_for_combine created the
11898 necessary REG_UNUSED notes. Trying to keep any original
11899 REG_UNUSED notes from these insns can cause incorrect output
11900 if it is for the same register as the original i3 dest.
11901 In that case, we will notice that the register is set in i3,
11902 and then add a REG_UNUSED note for the destination of i3, which
11903 is wrong. However, it is possible to have REG_UNUSED notes from
11904 i2 or i1 for register which were both used and clobbered, so
11905 we keep notes from i2 or i1 if they will turn into REG_DEAD
11908 /* If this register is set or clobbered in I3, put the note there
11909 unless there is one already. */
11910 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
11912 if (from_insn != i3)
11915 if (! (REG_P (XEXP (note, 0))
11916 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
11917 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
11920 /* Otherwise, if this register is used by I3, then this register
11921 now dies here, so we must put a REG_DEAD note here unless there
11923 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
11924 && ! (REG_P (XEXP (note, 0))
11925 ? find_regno_note (i3, REG_DEAD,
11926 REGNO (XEXP (note, 0)))
11927 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
11929 PUT_REG_NOTE_KIND (note, REG_DEAD);
11937 /* These notes say something about results of an insn. We can
11938 only support them if they used to be on I3 in which case they
11939 remain on I3. Otherwise they are ignored.
11941 If the note refers to an expression that is not a constant, we
11942 must also ignore the note since we cannot tell whether the
11943 equivalence is still true. It might be possible to do
11944 slightly better than this (we only have a problem if I2DEST
11945 or I1DEST is present in the expression), but it doesn't
11946 seem worth the trouble. */
11948 if (from_insn == i3
11949 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
11954 case REG_NO_CONFLICT:
11955 /* These notes say something about how a register is used. They must
11956 be present on any use of the register in I2 or I3. */
11957 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
11960 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
11970 /* This can show up in several ways -- either directly in the
11971 pattern, or hidden off in the constant pool with (or without?)
11972 a REG_EQUAL note. */
11973 /* ??? Ignore the without-reg_equal-note problem for now. */
11974 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
11975 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
11976 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
11977 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
11981 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
11982 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
11983 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
11984 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
11992 /* Don't attach REG_LABEL note to a JUMP_INSN. Add
11993 a JUMP_LABEL instead or decrement LABEL_NUSES. */
11994 if (place && JUMP_P (place))
11996 rtx label = JUMP_LABEL (place);
11999 JUMP_LABEL (place) = XEXP (note, 0);
12002 gcc_assert (label == XEXP (note, 0));
12003 if (LABEL_P (label))
12004 LABEL_NUSES (label)--;
12008 if (place2 && JUMP_P (place2))
12010 rtx label = JUMP_LABEL (place2);
12013 JUMP_LABEL (place2) = XEXP (note, 0);
12016 gcc_assert (label == XEXP (note, 0));
12017 if (LABEL_P (label))
12018 LABEL_NUSES (label)--;
12025 /* This note says something about the value of a register prior
12026 to the execution of an insn. It is too much trouble to see
12027 if the note is still correct in all situations. It is better
12028 to simply delete it. */
12032 /* If the insn previously containing this note still exists,
12033 put it back where it was. Otherwise move it to the previous
12034 insn. Adjust the corresponding REG_LIBCALL note. */
12035 if (!NOTE_P (from_insn))
12039 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
12040 place = prev_real_insn (from_insn);
12042 XEXP (tem, 0) = place;
12043 /* If we're deleting the last remaining instruction of a
12044 libcall sequence, don't add the notes. */
12045 else if (XEXP (note, 0) == from_insn)
12047 /* Don't add the dangling REG_RETVAL note. */
12054 /* This is handled similarly to REG_RETVAL. */
12055 if (!NOTE_P (from_insn))
12059 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
12060 place = next_real_insn (from_insn);
12062 XEXP (tem, 0) = place;
12063 /* If we're deleting the last remaining instruction of a
12064 libcall sequence, don't add the notes. */
12065 else if (XEXP (note, 0) == from_insn)
12067 /* Don't add the dangling REG_LIBCALL note. */
12074 /* If the register is used as an input in I3, it dies there.
12075 Similarly for I2, if it is nonzero and adjacent to I3.
12077 If the register is not used as an input in either I3 or I2
12078 and it is not one of the registers we were supposed to eliminate,
12079 there are two possibilities. We might have a non-adjacent I2
12080 or we might have somehow eliminated an additional register
12081 from a computation. For example, we might have had A & B where
12082 we discover that B will always be zero. In this case we will
12083 eliminate the reference to A.
12085 In both cases, we must search to see if we can find a previous
12086 use of A and put the death note there. */
12089 && CALL_P (from_insn)
12090 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12092 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12094 else if (i2 != 0 && next_nonnote_insn (i2) == i3
12095 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12099 && (rtx_equal_p (XEXP (note, 0), elim_i2)
12100 || rtx_equal_p (XEXP (note, 0), elim_i1)))
12105 basic_block bb = this_basic_block;
12107 /* You might think you could search back from FROM_INSN
12108 rather than from I3, but combine tries to split invalid
12109 combined instructions. This can result in the old I2
12110 or I1 moving later in the insn sequence. */
12111 for (tem = PREV_INSN (i3); place == 0; tem = PREV_INSN (tem))
12113 if (! INSN_P (tem))
12115 if (tem == BB_HEAD (bb))
12120 /* If the register is being set at TEM, see if that is all
12121 TEM is doing. If so, delete TEM. Otherwise, make this
12122 into a REG_UNUSED note instead. Don't delete sets to
12123 global register vars. */
12124 if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
12125 || !global_regs[REGNO (XEXP (note, 0))])
12126 && reg_set_p (XEXP (note, 0), PATTERN (tem)))
12128 rtx set = single_set (tem);
12129 rtx inner_dest = 0;
12131 rtx cc0_setter = NULL_RTX;
12135 for (inner_dest = SET_DEST (set);
12136 (GET_CODE (inner_dest) == STRICT_LOW_PART
12137 || GET_CODE (inner_dest) == SUBREG
12138 || GET_CODE (inner_dest) == ZERO_EXTRACT);
12139 inner_dest = XEXP (inner_dest, 0))
12142 /* Verify that it was the set, and not a clobber that
12143 modified the register.
12145 CC0 targets must be careful to maintain setter/user
12146 pairs. If we cannot delete the setter due to side
12147 effects, mark the user with an UNUSED note instead
12150 if (set != 0 && ! side_effects_p (SET_SRC (set))
12151 && rtx_equal_p (XEXP (note, 0), inner_dest)
12153 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12154 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12155 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12159 /* Move the notes and links of TEM elsewhere.
12160 This might delete other dead insns recursively.
12161 First set the pattern to something that won't use
12163 rtx old_notes = REG_NOTES (tem);
12165 PATTERN (tem) = pc_rtx;
12166 REG_NOTES (tem) = NULL;
12168 distribute_notes (old_notes, tem, tem, NULL_RTX,
12169 NULL_RTX, NULL_RTX);
12170 distribute_links (LOG_LINKS (tem));
12172 SET_INSN_DELETED (tem);
12175 /* Delete the setter too. */
12178 PATTERN (cc0_setter) = pc_rtx;
12179 old_notes = REG_NOTES (cc0_setter);
12180 REG_NOTES (cc0_setter) = NULL;
12182 distribute_notes (old_notes, cc0_setter,
12183 cc0_setter, NULL_RTX,
12184 NULL_RTX, NULL_RTX);
12185 distribute_links (LOG_LINKS (cc0_setter));
12187 SET_INSN_DELETED (cc0_setter);
12193 PUT_REG_NOTE_KIND (note, REG_UNUSED);
12195 /* If there isn't already a REG_UNUSED note, put one
12196 here. Do not place a REG_DEAD note, even if
12197 the register is also used here; that would not
12198 match the algorithm used in lifetime analysis
12199 and can cause the consistency check in the
12200 scheduler to fail. */
12201 if (! find_regno_note (tem, REG_UNUSED,
12202 REGNO (XEXP (note, 0))))
12207 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12209 && find_reg_fusage (tem, USE, XEXP (note, 0))))
12211 /* This may not be the correct place for the death
12212 note if FROM_INSN is before TEM, and the reg is
12213 set between FROM_INSN and TEM. The reg might
12214 die two or more times. An existing death note
12215 means we are looking at the wrong live range. */
12217 && INSN_CUID (from_insn) < INSN_CUID (tem)
12218 && find_regno_note (tem, REG_DEAD,
12219 REGNO (XEXP (note, 0))))
12222 if (tem == BB_HEAD (bb))
12229 /* If we are doing a 3->2 combination, and we have a
12230 register which formerly died in i3 and was not used
12231 by i2, which now no longer dies in i3 and is used in
12232 i2 but does not die in i2, and place is between i2
12233 and i3, then we may need to move a link from place to
12235 if (i2 && INSN_UID (place) <= max_uid_cuid
12236 && INSN_CUID (place) > INSN_CUID (i2)
12238 && INSN_CUID (from_insn) > INSN_CUID (i2)
12239 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12241 rtx links = LOG_LINKS (place);
12242 LOG_LINKS (place) = 0;
12243 distribute_links (links);
12248 if (tem == BB_HEAD (bb))
12252 /* We haven't found an insn for the death note and it
12253 is still a REG_DEAD note, but we have hit the beginning
12254 of the block. If the existing life info says the reg
12255 was dead, there's nothing left to do. Otherwise, we'll
12256 need to do a global life update after combine. */
12257 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0
12258 && REGNO_REG_SET_P (bb->il.rtl->global_live_at_start,
12259 REGNO (XEXP (note, 0))))
12260 SET_BIT (refresh_blocks, this_basic_block->index);
12263 /* If the register is set or already dead at PLACE, we needn't do
12264 anything with this note if it is still a REG_DEAD note.
12265 We check here if it is set at all, not if is it totally replaced,
12266 which is what `dead_or_set_p' checks, so also check for it being
12269 if (place && REG_NOTE_KIND (note) == REG_DEAD)
12271 unsigned int regno = REGNO (XEXP (note, 0));
12273 /* Similarly, if the instruction on which we want to place
12274 the note is a noop, we'll need do a global live update
12275 after we remove them in delete_noop_moves. */
12276 if (noop_move_p (place))
12277 SET_BIT (refresh_blocks, this_basic_block->index);
12279 if (dead_or_set_p (place, XEXP (note, 0))
12280 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12282 /* Unless the register previously died in PLACE, clear
12283 last_death. [I no longer understand why this is
12285 if (reg_stat[regno].last_death != place)
12286 reg_stat[regno].last_death = 0;
12290 reg_stat[regno].last_death = place;
12292 /* If this is a death note for a hard reg that is occupying
12293 multiple registers, ensure that we are still using all
12294 parts of the object. If we find a piece of the object
12295 that is unused, we must arrange for an appropriate REG_DEAD
12296 note to be added for it. However, we can't just emit a USE
12297 and tag the note to it, since the register might actually
12298 be dead; so we recourse, and the recursive call then finds
12299 the previous insn that used this register. */
12301 if (place && regno < FIRST_PSEUDO_REGISTER
12302 && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
12304 unsigned int endregno
12305 = regno + hard_regno_nregs[regno]
12306 [GET_MODE (XEXP (note, 0))];
12310 for (i = regno; i < endregno; i++)
12311 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12312 && ! find_regno_fusage (place, USE, i))
12313 || dead_or_set_regno_p (place, i))
12318 /* Put only REG_DEAD notes for pieces that are
12319 not already dead or set. */
12321 for (i = regno; i < endregno;
12322 i += hard_regno_nregs[i][reg_raw_mode[i]])
12324 rtx piece = regno_reg_rtx[i];
12325 basic_block bb = this_basic_block;
12327 if (! dead_or_set_p (place, piece)
12328 && ! reg_bitfield_target_p (piece,
12332 = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX);
12334 distribute_notes (new_note, place, place,
12335 NULL_RTX, NULL_RTX, NULL_RTX);
12337 else if (! refers_to_regno_p (i, i + 1,
12338 PATTERN (place), 0)
12339 && ! find_regno_fusage (place, USE, i))
12340 for (tem = PREV_INSN (place); ;
12341 tem = PREV_INSN (tem))
12343 if (! INSN_P (tem))
12345 if (tem == BB_HEAD (bb))
12347 SET_BIT (refresh_blocks,
12348 this_basic_block->index);
12353 if (dead_or_set_p (tem, piece)
12354 || reg_bitfield_target_p (piece,
12358 = gen_rtx_EXPR_LIST (REG_UNUSED, piece,
12373 /* Any other notes should not be present at this point in the
12375 gcc_unreachable ();
12380 XEXP (note, 1) = REG_NOTES (place);
12381 REG_NOTES (place) = note;
12383 else if ((REG_NOTE_KIND (note) == REG_DEAD
12384 || REG_NOTE_KIND (note) == REG_UNUSED)
12385 && REG_P (XEXP (note, 0)))
12386 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
12390 if ((REG_NOTE_KIND (note) == REG_DEAD
12391 || REG_NOTE_KIND (note) == REG_UNUSED)
12392 && REG_P (XEXP (note, 0)))
12393 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
12395 REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
12396 REG_NOTE_KIND (note),
12398 REG_NOTES (place2));
12403 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12404 I3, I2, and I1 to new locations. This is also called to add a link
12405 pointing at I3 when I3's destination is changed. */
12408 distribute_links (rtx links)
12410 rtx link, next_link;
12412 for (link = links; link; link = next_link)
12418 next_link = XEXP (link, 1);
12420 /* If the insn that this link points to is a NOTE or isn't a single
12421 set, ignore it. In the latter case, it isn't clear what we
12422 can do other than ignore the link, since we can't tell which
12423 register it was for. Such links wouldn't be used by combine
12426 It is not possible for the destination of the target of the link to
12427 have been changed by combine. The only potential of this is if we
12428 replace I3, I2, and I1 by I3 and I2. But in that case the
12429 destination of I2 also remains unchanged. */
12431 if (NOTE_P (XEXP (link, 0))
12432 || (set = single_set (XEXP (link, 0))) == 0)
12435 reg = SET_DEST (set);
12436 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12437 || GET_CODE (reg) == STRICT_LOW_PART)
12438 reg = XEXP (reg, 0);
12440 /* A LOG_LINK is defined as being placed on the first insn that uses
12441 a register and points to the insn that sets the register. Start
12442 searching at the next insn after the target of the link and stop
12443 when we reach a set of the register or the end of the basic block.
12445 Note that this correctly handles the link that used to point from
12446 I3 to I2. Also note that not much searching is typically done here
12447 since most links don't point very far away. */
12449 for (insn = NEXT_INSN (XEXP (link, 0));
12450 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
12451 || BB_HEAD (this_basic_block->next_bb) != insn));
12452 insn = NEXT_INSN (insn))
12453 if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12455 if (reg_referenced_p (reg, PATTERN (insn)))
12459 else if (CALL_P (insn)
12460 && find_reg_fusage (insn, USE, reg))
12465 else if (INSN_P (insn) && reg_set_p (reg, insn))
12468 /* If we found a place to put the link, place it there unless there
12469 is already a link to the same insn as LINK at that point. */
12475 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12476 if (XEXP (link2, 0) == XEXP (link, 0))
12481 XEXP (link, 1) = LOG_LINKS (place);
12482 LOG_LINKS (place) = link;
12484 /* Set added_links_insn to the earliest insn we added a
12486 if (added_links_insn == 0
12487 || INSN_CUID (added_links_insn) > INSN_CUID (place))
12488 added_links_insn = place;
12494 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
12495 Check whether the expression pointer to by LOC is a register or
12496 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
12497 Otherwise return zero. */
12500 unmentioned_reg_p_1 (rtx *loc, void *expr)
12505 && (REG_P (x) || MEM_P (x))
12506 && ! reg_mentioned_p (x, (rtx) expr))
12511 /* Check for any register or memory mentioned in EQUIV that is not
12512 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
12513 of EXPR where some registers may have been replaced by constants. */
12516 unmentioned_reg_p (rtx equiv, rtx expr)
12518 return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
12521 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12524 insn_cuid (rtx insn)
12526 while (insn != 0 && INSN_UID (insn) > max_uid_cuid
12527 && NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE)
12528 insn = NEXT_INSN (insn);
12530 gcc_assert (INSN_UID (insn) <= max_uid_cuid);
12532 return INSN_CUID (insn);
12536 dump_combine_stats (FILE *file)
12540 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12541 combine_attempts, combine_merges, combine_extras, combine_successes);
12545 dump_combine_total_stats (FILE *file)
12549 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12550 total_attempts, total_merges, total_extras, total_successes);
12555 gate_handle_combine (void)
12557 return (optimize > 0);
12560 /* Try combining insns through substitution. */
12562 rest_of_handle_combine (void)
12564 int rebuild_jump_labels_after_combine
12565 = combine_instructions (get_insns (), max_reg_num ());
12567 /* Combining insns may have turned an indirect jump into a
12568 direct jump. Rebuild the JUMP_LABEL fields of jumping
12570 if (rebuild_jump_labels_after_combine)
12572 timevar_push (TV_JUMP);
12573 rebuild_jump_labels (get_insns ());
12574 timevar_pop (TV_JUMP);
12576 delete_dead_jumptables ();
12577 cleanup_cfg (CLEANUP_EXPENSIVE | CLEANUP_UPDATE_LIFE);
12581 struct tree_opt_pass pass_combine =
12583 "combine", /* name */
12584 gate_handle_combine, /* gate */
12585 rest_of_handle_combine, /* execute */
12588 0, /* static_pass_number */
12589 TV_COMBINE, /* tv_id */
12590 0, /* properties_required */
12591 0, /* properties_provided */
12592 0, /* properties_destroyed */
12593 0, /* todo_flags_start */
12595 TODO_ggc_collect, /* todo_flags_finish */