1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 88, 92, 93, 94, 95, 1996 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - reg_n_refs is not adjusted in the rare case when a register is
57 no longer required in a computation
58 - there are extremely rare cases (see distribute_regnotes) when a
60 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
61 removed because there is no way to know which register it was
64 To simplify substitution, we combine only when the earlier insn(s)
65 consist of only a single assignment. To simplify updating afterward,
66 we never combine when a subroutine call appears in the middle.
68 Since we do not represent assignments to CC0 explicitly except when that
69 is all an insn does, there is no LOG_LINKS entry in an insn that uses
70 the condition code for the insn that set the condition code.
71 Fortunately, these two insns must be consecutive.
72 Therefore, every JUMP_INSN is taken to have an implicit logical link
73 to the preceding insn. This is not quite right, since non-jumps can
74 also use the condition code; but in practice such insns would not
84 /* Must precede rtl.h for FFS. */
90 #include "hard-reg-set.h"
92 #include "basic-block.h"
93 #include "insn-config.h"
94 #include "insn-flags.h"
95 #include "insn-codes.h"
96 #include "insn-attr.h"
100 /* It is not safe to use ordinary gen_lowpart in combine.
101 Use gen_lowpart_for_combine instead. See comments there. */
102 #define gen_lowpart dont_use_gen_lowpart_you_dummy
104 /* Number of attempts to combine instructions in this function. */
106 static int combine_attempts;
108 /* Number of attempts that got as far as substitution in this function. */
110 static int combine_merges;
112 /* Number of instructions combined with added SETs in this function. */
114 static int combine_extras;
116 /* Number of instructions combined in this function. */
118 static int combine_successes;
120 /* Totals over entire compilation. */
122 static int total_attempts, total_merges, total_extras, total_successes;
124 /* Define a default value for REVERSIBLE_CC_MODE.
125 We can never assume that a condition code mode is safe to reverse unless
126 the md tells us so. */
127 #ifndef REVERSIBLE_CC_MODE
128 #define REVERSIBLE_CC_MODE(MODE) 0
131 /* Vector mapping INSN_UIDs to cuids.
132 The cuids are like uids but increase monotonically always.
133 Combine always uses cuids so that it can compare them.
134 But actually renumbering the uids, which we used to do,
135 proves to be a bad idea because it makes it hard to compare
136 the dumps produced by earlier passes with those from later passes. */
138 static int *uid_cuid;
139 static int max_uid_cuid;
141 /* Get the cuid of an insn. */
143 #define INSN_CUID(INSN) \
144 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
146 /* Maximum register number, which is the size of the tables below. */
148 static int combine_max_regno;
150 /* Record last point of death of (hard or pseudo) register n. */
152 static rtx *reg_last_death;
154 /* Record last point of modification of (hard or pseudo) register n. */
156 static rtx *reg_last_set;
158 /* Record the cuid of the last insn that invalidated memory
159 (anything that writes memory, and subroutine calls, but not pushes). */
161 static int mem_last_set;
163 /* Record the cuid of the last CALL_INSN
164 so we can tell whether a potential combination crosses any calls. */
166 static int last_call_cuid;
168 /* When `subst' is called, this is the insn that is being modified
169 (by combining in a previous insn). The PATTERN of this insn
170 is still the old pattern partially modified and it should not be
171 looked at, but this may be used to examine the successors of the insn
172 to judge whether a simplification is valid. */
174 static rtx subst_insn;
176 /* This is an insn that belongs before subst_insn, but is not currently
177 on the insn chain. */
179 static rtx subst_prev_insn;
181 /* This is the lowest CUID that `subst' is currently dealing with.
182 get_last_value will not return a value if the register was set at or
183 after this CUID. If not for this mechanism, we could get confused if
184 I2 or I1 in try_combine were an insn that used the old value of a register
185 to obtain a new value. In that case, we might erroneously get the
186 new value of the register when we wanted the old one. */
188 static int subst_low_cuid;
190 /* This contains any hard registers that are used in newpat; reg_dead_at_p
191 must consider all these registers to be always live. */
193 static HARD_REG_SET newpat_used_regs;
195 /* This is an insn to which a LOG_LINKS entry has been added. If this
196 insn is the earlier than I2 or I3, combine should rescan starting at
199 static rtx added_links_insn;
201 /* Basic block number of the block in which we are performing combines. */
202 static int this_basic_block;
204 /* The next group of arrays allows the recording of the last value assigned
205 to (hard or pseudo) register n. We use this information to see if a
206 operation being processed is redundant given a prior operation performed
207 on the register. For example, an `and' with a constant is redundant if
208 all the zero bits are already known to be turned off.
210 We use an approach similar to that used by cse, but change it in the
213 (1) We do not want to reinitialize at each label.
214 (2) It is useful, but not critical, to know the actual value assigned
215 to a register. Often just its form is helpful.
217 Therefore, we maintain the following arrays:
219 reg_last_set_value the last value assigned
220 reg_last_set_label records the value of label_tick when the
221 register was assigned
222 reg_last_set_table_tick records the value of label_tick when a
223 value using the register is assigned
224 reg_last_set_invalid set to non-zero when it is not valid
225 to use the value of this register in some
228 To understand the usage of these tables, it is important to understand
229 the distinction between the value in reg_last_set_value being valid
230 and the register being validly contained in some other expression in the
233 Entry I in reg_last_set_value is valid if it is non-zero, and either
234 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
236 Register I may validly appear in any expression returned for the value
237 of another register if reg_n_sets[i] is 1. It may also appear in the
238 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
239 reg_last_set_invalid[j] is zero.
241 If an expression is found in the table containing a register which may
242 not validly appear in an expression, the register is replaced by
243 something that won't match, (clobber (const_int 0)).
245 reg_last_set_invalid[i] is set non-zero when register I is being assigned
246 to and reg_last_set_table_tick[i] == label_tick. */
248 /* Record last value assigned to (hard or pseudo) register n. */
250 static rtx *reg_last_set_value;
252 /* Record the value of label_tick when the value for register n is placed in
253 reg_last_set_value[n]. */
255 static int *reg_last_set_label;
257 /* Record the value of label_tick when an expression involving register n
258 is placed in reg_last_set_value. */
260 static int *reg_last_set_table_tick;
262 /* Set non-zero if references to register n in expressions should not be
265 static char *reg_last_set_invalid;
267 /* Incremented for each label. */
269 static int label_tick;
271 /* Some registers that are set more than once and used in more than one
272 basic block are nevertheless always set in similar ways. For example,
273 a QImode register may be loaded from memory in two places on a machine
274 where byte loads zero extend.
276 We record in the following array what we know about the nonzero
277 bits of a register, specifically which bits are known to be zero.
279 If an entry is zero, it means that we don't know anything special. */
281 static unsigned HOST_WIDE_INT *reg_nonzero_bits;
283 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
284 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
286 static enum machine_mode nonzero_bits_mode;
288 /* Nonzero if we know that a register has some leading bits that are always
289 equal to the sign bit. */
291 static char *reg_sign_bit_copies;
293 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
294 It is zero while computing them and after combine has completed. This
295 former test prevents propagating values based on previously set values,
296 which can be incorrect if a variable is modified in a loop. */
298 static int nonzero_sign_valid;
300 /* These arrays are maintained in parallel with reg_last_set_value
301 and are used to store the mode in which the register was last set,
302 the bits that were known to be zero when it was last set, and the
303 number of sign bits copies it was known to have when it was last set. */
305 static enum machine_mode *reg_last_set_mode;
306 static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits;
307 static char *reg_last_set_sign_bit_copies;
309 /* Record one modification to rtl structure
310 to be undone by storing old_contents into *where.
311 is_int is 1 if the contents are an int. */
317 union {rtx r; int i;} old_contents;
318 union {rtx *r; int *i;} where;
321 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
322 num_undo says how many are currently recorded.
324 storage is nonzero if we must undo the allocation of new storage.
325 The value of storage is what to pass to obfree.
327 other_insn is nonzero if we have modified some other insn in the process
328 of working on subst_insn. It must be verified too.
330 previous_undos is the value of undobuf.undos when we started processing
331 this substitution. This will prevent gen_rtx_combine from re-used a piece
332 from the previous expression. Doing so can produce circular rtl
340 struct undo *previous_undos;
344 static struct undobuf undobuf;
346 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
347 insn. The substitution can be undone by undo_all. If INTO is already
348 set to NEWVAL, do not record this change. Because computing NEWVAL might
349 also call SUBST, we have to compute it before we put anything into
352 #define SUBST(INTO, NEWVAL) \
353 do { rtx _new = (NEWVAL); \
357 _buf = undobuf.frees, undobuf.frees = _buf->next; \
359 _buf = (struct undo *) xmalloc (sizeof (struct undo)); \
362 _buf->where.r = &INTO; \
363 _buf->old_contents.r = INTO; \
365 if (_buf->old_contents.r == INTO) \
366 _buf->next = undobuf.frees, undobuf.frees = _buf; \
368 _buf->next = undobuf.undos, undobuf.undos = _buf; \
371 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
372 for the value of a HOST_WIDE_INT value (including CONST_INT) is
375 #define SUBST_INT(INTO, NEWVAL) \
376 do { struct undo *_buf; \
379 _buf = undobuf.frees, undobuf.frees = _buf->next; \
381 _buf = (struct undo *) xmalloc (sizeof (struct undo)); \
384 _buf->where.i = (int *) &INTO; \
385 _buf->old_contents.i = INTO; \
387 if (_buf->old_contents.i == INTO) \
388 _buf->next = undobuf.frees, undobuf.frees = _buf; \
390 _buf->next = undobuf.undos, undobuf.undos = _buf; \
393 /* Number of times the pseudo being substituted for
394 was found and replaced. */
396 static int n_occurrences;
398 static void init_reg_last_arrays PROTO((void));
399 static void setup_incoming_promotions PROTO((void));
400 static void set_nonzero_bits_and_sign_copies PROTO((rtx, rtx));
401 static int can_combine_p PROTO((rtx, rtx, rtx, rtx, rtx *, rtx *));
402 static int combinable_i3pat PROTO((rtx, rtx *, rtx, rtx, int, rtx *));
403 static rtx try_combine PROTO((rtx, rtx, rtx));
404 static void undo_all PROTO((void));
405 static rtx *find_split_point PROTO((rtx *, rtx));
406 static rtx subst PROTO((rtx, rtx, rtx, int, int));
407 static rtx simplify_rtx PROTO((rtx, enum machine_mode, int, int));
408 static rtx simplify_if_then_else PROTO((rtx));
409 static rtx simplify_set PROTO((rtx));
410 static rtx simplify_logical PROTO((rtx, int));
411 static rtx expand_compound_operation PROTO((rtx));
412 static rtx expand_field_assignment PROTO((rtx));
413 static rtx make_extraction PROTO((enum machine_mode, rtx, int, rtx, int,
415 static rtx extract_left_shift PROTO((rtx, int));
416 static rtx make_compound_operation PROTO((rtx, enum rtx_code));
417 static int get_pos_from_mask PROTO((unsigned HOST_WIDE_INT, int *));
418 static rtx force_to_mode PROTO((rtx, enum machine_mode,
419 unsigned HOST_WIDE_INT, rtx, int));
420 static rtx if_then_else_cond PROTO((rtx, rtx *, rtx *));
421 static rtx known_cond PROTO((rtx, enum rtx_code, rtx, rtx));
422 static int rtx_equal_for_field_assignment_p PROTO((rtx, rtx));
423 static rtx make_field_assignment PROTO((rtx));
424 static rtx apply_distributive_law PROTO((rtx));
425 static rtx simplify_and_const_int PROTO((rtx, enum machine_mode, rtx,
426 unsigned HOST_WIDE_INT));
427 static unsigned HOST_WIDE_INT nonzero_bits PROTO((rtx, enum machine_mode));
428 static int num_sign_bit_copies PROTO((rtx, enum machine_mode));
429 static int merge_outer_ops PROTO((enum rtx_code *, HOST_WIDE_INT *,
430 enum rtx_code, HOST_WIDE_INT,
431 enum machine_mode, int *));
432 static rtx simplify_shift_const PROTO((rtx, enum rtx_code, enum machine_mode,
434 static int recog_for_combine PROTO((rtx *, rtx, rtx *, int *));
435 static rtx gen_lowpart_for_combine PROTO((enum machine_mode, rtx));
436 static rtx gen_rtx_combine PVPROTO((enum rtx_code code, enum machine_mode mode,
438 static rtx gen_binary PROTO((enum rtx_code, enum machine_mode,
440 static rtx gen_unary PROTO((enum rtx_code, enum machine_mode,
441 enum machine_mode, rtx));
442 static enum rtx_code simplify_comparison PROTO((enum rtx_code, rtx *, rtx *));
443 static int reversible_comparison_p PROTO((rtx));
444 static void update_table_tick PROTO((rtx));
445 static void record_value_for_reg PROTO((rtx, rtx, rtx));
446 static void record_dead_and_set_regs_1 PROTO((rtx, rtx));
447 static void record_dead_and_set_regs PROTO((rtx));
448 static int get_last_value_validate PROTO((rtx *, int, int));
449 static rtx get_last_value PROTO((rtx));
450 static int use_crosses_set_p PROTO((rtx, int));
451 static void reg_dead_at_p_1 PROTO((rtx, rtx));
452 static int reg_dead_at_p PROTO((rtx, rtx));
453 static void move_deaths PROTO((rtx, rtx, int, rtx, rtx *));
454 static int reg_bitfield_target_p PROTO((rtx, rtx));
455 static void distribute_notes PROTO((rtx, rtx, rtx, rtx, rtx, rtx));
456 static void distribute_links PROTO((rtx));
457 static void mark_used_regs_combine PROTO((rtx));
458 static int insn_cuid PROTO((rtx));
460 /* Main entry point for combiner. F is the first insn of the function.
461 NREGS is the first unused pseudo-reg number. */
464 combine_instructions (f, nregs)
468 register rtx insn, next, prev;
470 register rtx links, nextlinks;
472 combine_attempts = 0;
475 combine_successes = 0;
476 undobuf.undos = undobuf.previous_undos = 0;
478 combine_max_regno = nregs;
481 = (unsigned HOST_WIDE_INT *) alloca (nregs * sizeof (HOST_WIDE_INT));
482 reg_sign_bit_copies = (char *) alloca (nregs * sizeof (char));
484 bzero ((char *) reg_nonzero_bits, nregs * sizeof (HOST_WIDE_INT));
485 bzero (reg_sign_bit_copies, nregs * sizeof (char));
487 reg_last_death = (rtx *) alloca (nregs * sizeof (rtx));
488 reg_last_set = (rtx *) alloca (nregs * sizeof (rtx));
489 reg_last_set_value = (rtx *) alloca (nregs * sizeof (rtx));
490 reg_last_set_table_tick = (int *) alloca (nregs * sizeof (int));
491 reg_last_set_label = (int *) alloca (nregs * sizeof (int));
492 reg_last_set_invalid = (char *) alloca (nregs * sizeof (char));
494 = (enum machine_mode *) alloca (nregs * sizeof (enum machine_mode));
495 reg_last_set_nonzero_bits
496 = (unsigned HOST_WIDE_INT *) alloca (nregs * sizeof (HOST_WIDE_INT));
497 reg_last_set_sign_bit_copies
498 = (char *) alloca (nregs * sizeof (char));
500 init_reg_last_arrays ();
502 init_recog_no_volatile ();
504 /* Compute maximum uid value so uid_cuid can be allocated. */
506 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
507 if (INSN_UID (insn) > i)
510 uid_cuid = (int *) alloca ((i + 1) * sizeof (int));
513 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
515 /* Don't use reg_nonzero_bits when computing it. This can cause problems
516 when, for example, we have j <<= 1 in a loop. */
518 nonzero_sign_valid = 0;
520 /* Compute the mapping from uids to cuids.
521 Cuids are numbers assigned to insns, like uids,
522 except that cuids increase monotonically through the code.
524 Scan all SETs and see if we can deduce anything about what
525 bits are known to be zero for some registers and how many copies
526 of the sign bit are known to exist for those registers.
528 Also set any known values so that we can use it while searching
529 for what bits are known to be set. */
533 /* We need to initialize it here, because record_dead_and_set_regs may call
535 subst_prev_insn = NULL_RTX;
537 setup_incoming_promotions ();
539 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
541 uid_cuid[INSN_UID (insn)] = ++i;
545 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
547 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies);
548 record_dead_and_set_regs (insn);
551 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
552 if (REG_NOTE_KIND (links) == REG_INC)
553 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX);
557 if (GET_CODE (insn) == CODE_LABEL)
561 nonzero_sign_valid = 1;
563 /* Now scan all the insns in forward order. */
565 this_basic_block = -1;
569 init_reg_last_arrays ();
570 setup_incoming_promotions ();
572 for (insn = f; insn; insn = next ? next : NEXT_INSN (insn))
576 /* If INSN starts a new basic block, update our basic block number. */
577 if (this_basic_block + 1 < n_basic_blocks
578 && basic_block_head[this_basic_block + 1] == insn)
581 if (GET_CODE (insn) == CODE_LABEL)
584 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
586 /* Try this insn with each insn it links back to. */
588 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
589 if ((next = try_combine (insn, XEXP (links, 0), NULL_RTX)) != 0)
592 /* Try each sequence of three linked insns ending with this one. */
594 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
595 for (nextlinks = LOG_LINKS (XEXP (links, 0)); nextlinks;
596 nextlinks = XEXP (nextlinks, 1))
597 if ((next = try_combine (insn, XEXP (links, 0),
598 XEXP (nextlinks, 0))) != 0)
602 /* Try to combine a jump insn that uses CC0
603 with a preceding insn that sets CC0, and maybe with its
604 logical predecessor as well.
605 This is how we make decrement-and-branch insns.
606 We need this special code because data flow connections
607 via CC0 do not get entered in LOG_LINKS. */
609 if (GET_CODE (insn) == JUMP_INSN
610 && (prev = prev_nonnote_insn (insn)) != 0
611 && GET_CODE (prev) == INSN
612 && sets_cc0_p (PATTERN (prev)))
614 if ((next = try_combine (insn, prev, NULL_RTX)) != 0)
617 for (nextlinks = LOG_LINKS (prev); nextlinks;
618 nextlinks = XEXP (nextlinks, 1))
619 if ((next = try_combine (insn, prev,
620 XEXP (nextlinks, 0))) != 0)
624 /* Do the same for an insn that explicitly references CC0. */
625 if (GET_CODE (insn) == INSN
626 && (prev = prev_nonnote_insn (insn)) != 0
627 && GET_CODE (prev) == INSN
628 && sets_cc0_p (PATTERN (prev))
629 && GET_CODE (PATTERN (insn)) == SET
630 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
632 if ((next = try_combine (insn, prev, NULL_RTX)) != 0)
635 for (nextlinks = LOG_LINKS (prev); nextlinks;
636 nextlinks = XEXP (nextlinks, 1))
637 if ((next = try_combine (insn, prev,
638 XEXP (nextlinks, 0))) != 0)
642 /* Finally, see if any of the insns that this insn links to
643 explicitly references CC0. If so, try this insn, that insn,
644 and its predecessor if it sets CC0. */
645 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
646 if (GET_CODE (XEXP (links, 0)) == INSN
647 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
648 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
649 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
650 && GET_CODE (prev) == INSN
651 && sets_cc0_p (PATTERN (prev))
652 && (next = try_combine (insn, XEXP (links, 0), prev)) != 0)
656 /* Try combining an insn with two different insns whose results it
658 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
659 for (nextlinks = XEXP (links, 1); nextlinks;
660 nextlinks = XEXP (nextlinks, 1))
661 if ((next = try_combine (insn, XEXP (links, 0),
662 XEXP (nextlinks, 0))) != 0)
665 if (GET_CODE (insn) != NOTE)
666 record_dead_and_set_regs (insn);
673 total_attempts += combine_attempts;
674 total_merges += combine_merges;
675 total_extras += combine_extras;
676 total_successes += combine_successes;
678 nonzero_sign_valid = 0;
681 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
684 init_reg_last_arrays ()
686 int nregs = combine_max_regno;
688 bzero ((char *) reg_last_death, nregs * sizeof (rtx));
689 bzero ((char *) reg_last_set, nregs * sizeof (rtx));
690 bzero ((char *) reg_last_set_value, nregs * sizeof (rtx));
691 bzero ((char *) reg_last_set_table_tick, nregs * sizeof (int));
692 bzero ((char *) reg_last_set_label, nregs * sizeof (int));
693 bzero (reg_last_set_invalid, nregs * sizeof (char));
694 bzero ((char *) reg_last_set_mode, nregs * sizeof (enum machine_mode));
695 bzero ((char *) reg_last_set_nonzero_bits, nregs * sizeof (HOST_WIDE_INT));
696 bzero (reg_last_set_sign_bit_copies, nregs * sizeof (char));
699 /* Set up any promoted values for incoming argument registers. */
702 setup_incoming_promotions ()
704 #ifdef PROMOTE_FUNCTION_ARGS
707 enum machine_mode mode;
709 rtx first = get_insns ();
711 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
712 if (FUNCTION_ARG_REGNO_P (regno)
713 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
714 record_value_for_reg (reg, first,
715 gen_rtx (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
717 gen_rtx (CLOBBER, mode, const0_rtx)));
721 /* Called via note_stores. If X is a pseudo that is narrower than
722 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
724 If we are setting only a portion of X and we can't figure out what
725 portion, assume all bits will be used since we don't know what will
728 Similarly, set how many bits of X are known to be copies of the sign bit
729 at all locations in the function. This is the smallest number implied
733 set_nonzero_bits_and_sign_copies (x, set)
739 if (GET_CODE (x) == REG
740 && REGNO (x) >= FIRST_PSEUDO_REGISTER
741 /* If this register is undefined at the start of the file, we can't
742 say what its contents were. */
743 && ! (basic_block_live_at_start[0][REGNO (x) / REGSET_ELT_BITS]
744 & ((REGSET_ELT_TYPE) 1 << (REGNO (x) % REGSET_ELT_BITS)))
745 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
747 if (set == 0 || GET_CODE (set) == CLOBBER)
749 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
750 reg_sign_bit_copies[REGNO (x)] = 1;
754 /* If this is a complex assignment, see if we can convert it into a
755 simple assignment. */
756 set = expand_field_assignment (set);
758 /* If this is a simple assignment, or we have a paradoxical SUBREG,
759 set what we know about X. */
761 if (SET_DEST (set) == x
762 || (GET_CODE (SET_DEST (set)) == SUBREG
763 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
764 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
765 && SUBREG_REG (SET_DEST (set)) == x))
767 rtx src = SET_SRC (set);
769 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
770 /* If X is narrower than a word and SRC is a non-negative
771 constant that would appear negative in the mode of X,
772 sign-extend it for use in reg_nonzero_bits because some
773 machines (maybe most) will actually do the sign-extension
774 and this is the conservative approach.
776 ??? For 2.5, try to tighten up the MD files in this regard
777 instead of this kludge. */
779 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
780 && GET_CODE (src) == CONST_INT
782 && 0 != (INTVAL (src)
784 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
785 src = GEN_INT (INTVAL (src)
786 | ((HOST_WIDE_INT) (-1)
787 << GET_MODE_BITSIZE (GET_MODE (x))));
790 reg_nonzero_bits[REGNO (x)]
791 |= nonzero_bits (src, nonzero_bits_mode);
792 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
793 if (reg_sign_bit_copies[REGNO (x)] == 0
794 || reg_sign_bit_copies[REGNO (x)] > num)
795 reg_sign_bit_copies[REGNO (x)] = num;
799 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
800 reg_sign_bit_copies[REGNO (x)] = 1;
805 /* See if INSN can be combined into I3. PRED and SUCC are optionally
806 insns that were previously combined into I3 or that will be combined
807 into the merger of INSN and I3.
809 Return 0 if the combination is not allowed for any reason.
811 If the combination is allowed, *PDEST will be set to the single
812 destination of INSN and *PSRC to the single source, and this function
816 can_combine_p (insn, i3, pred, succ, pdest, psrc)
823 rtx set = 0, src, dest;
825 int all_adjacent = (succ ? (next_active_insn (insn) == succ
826 && next_active_insn (succ) == i3)
827 : next_active_insn (insn) == i3);
829 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
830 or a PARALLEL consisting of such a SET and CLOBBERs.
832 If INSN has CLOBBER parallel parts, ignore them for our processing.
833 By definition, these happen during the execution of the insn. When it
834 is merged with another insn, all bets are off. If they are, in fact,
835 needed and aren't also supplied in I3, they may be added by
836 recog_for_combine. Otherwise, it won't match.
838 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
841 Get the source and destination of INSN. If more than one, can't
844 if (GET_CODE (PATTERN (insn)) == SET)
845 set = PATTERN (insn);
846 else if (GET_CODE (PATTERN (insn)) == PARALLEL
847 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
849 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
851 rtx elt = XVECEXP (PATTERN (insn), 0, i);
853 switch (GET_CODE (elt))
855 /* We can ignore CLOBBERs. */
860 /* Ignore SETs whose result isn't used but not those that
861 have side-effects. */
862 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
863 && ! side_effects_p (elt))
866 /* If we have already found a SET, this is a second one and
867 so we cannot combine with this insn. */
875 /* Anything else means we can't combine. */
881 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
882 so don't do anything with it. */
883 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
892 set = expand_field_assignment (set);
893 src = SET_SRC (set), dest = SET_DEST (set);
895 /* Don't eliminate a store in the stack pointer. */
896 if (dest == stack_pointer_rtx
897 /* If we couldn't eliminate a field assignment, we can't combine. */
898 || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART
899 /* Don't combine with an insn that sets a register to itself if it has
900 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
901 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
902 /* Can't merge a function call. */
903 || GET_CODE (src) == CALL
904 /* Don't eliminate a function call argument. */
905 || (GET_CODE (i3) == CALL_INSN
906 && (find_reg_fusage (i3, USE, dest)
907 || (GET_CODE (dest) == REG
908 && REGNO (dest) < FIRST_PSEUDO_REGISTER
909 && global_regs[REGNO (dest)])))
910 /* Don't substitute into an incremented register. */
911 || FIND_REG_INC_NOTE (i3, dest)
912 || (succ && FIND_REG_INC_NOTE (succ, dest))
913 /* Don't combine the end of a libcall into anything. */
914 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
915 /* Make sure that DEST is not used after SUCC but before I3. */
916 || (succ && ! all_adjacent
917 && reg_used_between_p (dest, succ, i3))
918 /* Make sure that the value that is to be substituted for the register
919 does not use any registers whose values alter in between. However,
920 If the insns are adjacent, a use can't cross a set even though we
921 think it might (this can happen for a sequence of insns each setting
922 the same destination; reg_last_set of that register might point to
923 a NOTE). If INSN has a REG_EQUIV note, the register is always
924 equivalent to the memory so the substitution is valid even if there
925 are intervening stores. Also, don't move a volatile asm or
926 UNSPEC_VOLATILE across any other insns. */
928 && (((GET_CODE (src) != MEM
929 || ! find_reg_note (insn, REG_EQUIV, src))
930 && use_crosses_set_p (src, INSN_CUID (insn)))
931 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
932 || GET_CODE (src) == UNSPEC_VOLATILE))
933 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
934 better register allocation by not doing the combine. */
935 || find_reg_note (i3, REG_NO_CONFLICT, dest)
936 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
937 /* Don't combine across a CALL_INSN, because that would possibly
938 change whether the life span of some REGs crosses calls or not,
939 and it is a pain to update that information.
940 Exception: if source is a constant, moving it later can't hurt.
941 Accept that special case, because it helps -fforce-addr a lot. */
942 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
945 /* DEST must either be a REG or CC0. */
946 if (GET_CODE (dest) == REG)
948 /* If register alignment is being enforced for multi-word items in all
949 cases except for parameters, it is possible to have a register copy
950 insn referencing a hard register that is not allowed to contain the
951 mode being copied and which would not be valid as an operand of most
952 insns. Eliminate this problem by not combining with such an insn.
954 Also, on some machines we don't want to extend the life of a hard
957 if (GET_CODE (src) == REG
958 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
959 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
960 /* Don't extend the life of a hard register unless it is
961 user variable (if we have few registers) or it can't
962 fit into the desired register (meaning something special
964 Also avoid substituting a return register into I3, because
965 reload can't handle a conflict with constraints of other
967 || (REGNO (src) < FIRST_PSEUDO_REGISTER
968 && (! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src))
969 #ifdef SMALL_REGISTER_CLASSES
970 || (SMALL_REGISTER_CLASSES
971 && ((! all_adjacent && ! REG_USERVAR_P (src))
972 || (FUNCTION_VALUE_REGNO_P (REGNO (src))
973 && ! REG_USERVAR_P (src))))
978 else if (GET_CODE (dest) != CC0)
981 /* Don't substitute for a register intended as a clobberable operand.
982 Similarly, don't substitute an expression containing a register that
983 will be clobbered in I3. */
984 if (GET_CODE (PATTERN (i3)) == PARALLEL)
985 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
986 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
987 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0),
989 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)))
992 /* If INSN contains anything volatile, or is an `asm' (whether volatile
993 or not), reject, unless nothing volatile comes between it and I3,
994 with the exception of SUCC. */
996 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
997 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
998 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
999 && p != succ && volatile_refs_p (PATTERN (p)))
1002 /* If there are any volatile insns between INSN and I3, reject, because
1003 they might affect machine state. */
1005 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1006 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
1007 && p != succ && volatile_insn_p (PATTERN (p)))
1010 /* If INSN or I2 contains an autoincrement or autodecrement,
1011 make sure that register is not used between there and I3,
1012 and not already used in I3 either.
1013 Also insist that I3 not be a jump; if it were one
1014 and the incremented register were spilled, we would lose. */
1017 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1018 if (REG_NOTE_KIND (link) == REG_INC
1019 && (GET_CODE (i3) == JUMP_INSN
1020 || reg_used_between_p (XEXP (link, 0), insn, i3)
1021 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1026 /* Don't combine an insn that follows a CC0-setting insn.
1027 An insn that uses CC0 must not be separated from the one that sets it.
1028 We do, however, allow I2 to follow a CC0-setting insn if that insn
1029 is passed as I1; in that case it will be deleted also.
1030 We also allow combining in this case if all the insns are adjacent
1031 because that would leave the two CC0 insns adjacent as well.
1032 It would be more logical to test whether CC0 occurs inside I1 or I2,
1033 but that would be much slower, and this ought to be equivalent. */
1035 p = prev_nonnote_insn (insn);
1036 if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
1041 /* If we get here, we have passed all the tests and the combination is
1050 /* LOC is the location within I3 that contains its pattern or the component
1051 of a PARALLEL of the pattern. We validate that it is valid for combining.
1053 One problem is if I3 modifies its output, as opposed to replacing it
1054 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1055 so would produce an insn that is not equivalent to the original insns.
1059 (set (reg:DI 101) (reg:DI 100))
1060 (set (subreg:SI (reg:DI 101) 0) <foo>)
1062 This is NOT equivalent to:
1064 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1065 (set (reg:DI 101) (reg:DI 100))])
1067 Not only does this modify 100 (in which case it might still be valid
1068 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1070 We can also run into a problem if I2 sets a register that I1
1071 uses and I1 gets directly substituted into I3 (not via I2). In that
1072 case, we would be getting the wrong value of I2DEST into I3, so we
1073 must reject the combination. This case occurs when I2 and I1 both
1074 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1075 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
1076 of a SET must prevent combination from occurring.
1078 On machines where SMALL_REGISTER_CLASSES is defined, we don't combine
1079 if the destination of a SET is a hard register that isn't a user
1082 Before doing the above check, we first try to expand a field assignment
1083 into a set of logical operations.
1085 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
1086 we place a register that is both set and used within I3. If more than one
1087 such register is detected, we fail.
1089 Return 1 if the combination is valid, zero otherwise. */
1092 combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed)
1098 rtx *pi3dest_killed;
1102 if (GET_CODE (x) == SET)
1104 rtx set = expand_field_assignment (x);
1105 rtx dest = SET_DEST (set);
1106 rtx src = SET_SRC (set);
1107 rtx inner_dest = dest, inner_src = src;
1111 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1112 || GET_CODE (inner_dest) == SUBREG
1113 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1114 inner_dest = XEXP (inner_dest, 0);
1116 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1119 while (GET_CODE (inner_src) == STRICT_LOW_PART
1120 || GET_CODE (inner_src) == SUBREG
1121 || GET_CODE (inner_src) == ZERO_EXTRACT)
1122 inner_src = XEXP (inner_src, 0);
1124 /* If it is better that two different modes keep two different pseudos,
1125 avoid combining them. This avoids producing the following pattern
1127 (set (subreg:SI (reg/v:QI 21) 0)
1128 (lshiftrt:SI (reg/v:SI 20)
1130 If that were made, reload could not handle the pair of
1131 reg 20/21, since it would try to get any GENERAL_REGS
1132 but some of them don't handle QImode. */
1134 if (rtx_equal_p (inner_src, i2dest)
1135 && GET_CODE (inner_dest) == REG
1136 && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest)))
1140 /* Check for the case where I3 modifies its output, as
1142 if ((inner_dest != dest
1143 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1144 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1145 /* This is the same test done in can_combine_p except that we
1146 allow a hard register with SMALL_REGISTER_CLASSES if SRC is a
1148 Moreover, we can't test all_adjacent; we don't have to, since
1149 this instruction will stay in place, thus we are not considering
1150 to increase the lifetime of INNER_DEST. */
1151 || (GET_CODE (inner_dest) == REG
1152 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1153 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1154 GET_MODE (inner_dest))
1155 #ifdef SMALL_REGISTER_CLASSES
1156 || (SMALL_REGISTER_CLASSES
1157 && GET_CODE (src) != CALL && ! REG_USERVAR_P (inner_dest)
1158 && FUNCTION_VALUE_REGNO_P (REGNO (inner_dest)))
1161 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1164 /* If DEST is used in I3, it is being killed in this insn,
1165 so record that for later.
1166 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1167 STACK_POINTER_REGNUM, since these are always considered to be
1168 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1169 if (pi3dest_killed && GET_CODE (dest) == REG
1170 && reg_referenced_p (dest, PATTERN (i3))
1171 && REGNO (dest) != FRAME_POINTER_REGNUM
1172 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1173 && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
1175 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1176 && (REGNO (dest) != ARG_POINTER_REGNUM
1177 || ! fixed_regs [REGNO (dest)])
1179 && REGNO (dest) != STACK_POINTER_REGNUM)
1181 if (*pi3dest_killed)
1184 *pi3dest_killed = dest;
1188 else if (GET_CODE (x) == PARALLEL)
1192 for (i = 0; i < XVECLEN (x, 0); i++)
1193 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1194 i1_not_in_src, pi3dest_killed))
1201 /* Try to combine the insns I1 and I2 into I3.
1202 Here I1 and I2 appear earlier than I3.
1203 I1 can be zero; then we combine just I2 into I3.
1205 It we are combining three insns and the resulting insn is not recognized,
1206 try splitting it into two insns. If that happens, I2 and I3 are retained
1207 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1210 Return 0 if the combination does not work. Then nothing is changed.
1211 If we did the combination, return the insn at which combine should
1215 try_combine (i3, i2, i1)
1216 register rtx i3, i2, i1;
1218 /* New patterns for I3 and I3, respectively. */
1219 rtx newpat, newi2pat = 0;
1220 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1221 int added_sets_1, added_sets_2;
1222 /* Total number of SETs to put into I3. */
1224 /* Nonzero is I2's body now appears in I3. */
1226 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1227 int insn_code_number, i2_code_number, other_code_number;
1228 /* Contains I3 if the destination of I3 is used in its source, which means
1229 that the old life of I3 is being killed. If that usage is placed into
1230 I2 and not in I3, a REG_DEAD note must be made. */
1231 rtx i3dest_killed = 0;
1232 /* SET_DEST and SET_SRC of I2 and I1. */
1233 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1234 /* PATTERN (I2), or a copy of it in certain cases. */
1236 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1237 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1238 int i1_feeds_i3 = 0;
1239 /* Notes that must be added to REG_NOTES in I3 and I2. */
1240 rtx new_i3_notes, new_i2_notes;
1241 /* Notes that we substituted I3 into I2 instead of the normal case. */
1242 int i3_subst_into_i2 = 0;
1243 /* Notes that I1, I2 or I3 is a MULT operation. */
1245 /* Number of clobbers of SCRATCH we had to add. */
1246 int i3_scratches = 0, i2_scratches = 0, other_scratches = 0;
1253 /* If any of I1, I2, and I3 isn't really an insn, we can't do anything.
1254 This can occur when flow deletes an insn that it has merged into an
1255 auto-increment address. We also can't do anything if I3 has a
1256 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1259 if (GET_RTX_CLASS (GET_CODE (i3)) != 'i'
1260 || GET_RTX_CLASS (GET_CODE (i2)) != 'i'
1261 || (i1 && GET_RTX_CLASS (GET_CODE (i1)) != 'i')
1262 || find_reg_note (i3, REG_LIBCALL, NULL_RTX))
1267 undobuf.undos = undobuf.previous_undos = 0;
1268 undobuf.other_insn = 0;
1270 /* Save the current high-water-mark so we can free storage if we didn't
1271 accept this combination. */
1272 undobuf.storage = (char *) oballoc (0);
1274 /* Reset the hard register usage information. */
1275 CLEAR_HARD_REG_SET (newpat_used_regs);
1277 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1278 code below, set I1 to be the earlier of the two insns. */
1279 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1280 temp = i1, i1 = i2, i2 = temp;
1282 added_links_insn = 0;
1284 /* First check for one important special-case that the code below will
1285 not handle. Namely, the case where I1 is zero, I2 has multiple sets,
1286 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1287 we may be able to replace that destination with the destination of I3.
1288 This occurs in the common code where we compute both a quotient and
1289 remainder into a structure, in which case we want to do the computation
1290 directly into the structure to avoid register-register copies.
1292 We make very conservative checks below and only try to handle the
1293 most common cases of this. For example, we only handle the case
1294 where I2 and I3 are adjacent to avoid making difficult register
1297 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1298 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1299 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1300 #ifdef SMALL_REGISTER_CLASSES
1301 && (! SMALL_REGISTER_CLASSES
1302 || GET_CODE (SET_DEST (PATTERN (i3))) != REG
1303 || REGNO (SET_DEST (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1304 || REG_USERVAR_P (SET_DEST (PATTERN (i3))))
1306 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1307 && GET_CODE (PATTERN (i2)) == PARALLEL
1308 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1309 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1310 below would need to check what is inside (and reg_overlap_mentioned_p
1311 doesn't support those codes anyway). Don't allow those destinations;
1312 the resulting insn isn't likely to be recognized anyway. */
1313 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1314 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1315 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1316 SET_DEST (PATTERN (i3)))
1317 && next_real_insn (i2) == i3)
1319 rtx p2 = PATTERN (i2);
1321 /* Make sure that the destination of I3,
1322 which we are going to substitute into one output of I2,
1323 is not used within another output of I2. We must avoid making this:
1324 (parallel [(set (mem (reg 69)) ...)
1325 (set (reg 69) ...)])
1326 which is not well-defined as to order of actions.
1327 (Besides, reload can't handle output reloads for this.)
1329 The problem can also happen if the dest of I3 is a memory ref,
1330 if another dest in I2 is an indirect memory ref. */
1331 for (i = 0; i < XVECLEN (p2, 0); i++)
1332 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1333 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1334 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1335 SET_DEST (XVECEXP (p2, 0, i))))
1338 if (i == XVECLEN (p2, 0))
1339 for (i = 0; i < XVECLEN (p2, 0); i++)
1340 if (SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1345 subst_low_cuid = INSN_CUID (i2);
1347 added_sets_2 = added_sets_1 = 0;
1348 i2dest = SET_SRC (PATTERN (i3));
1350 /* Replace the dest in I2 with our dest and make the resulting
1351 insn the new pattern for I3. Then skip to where we
1352 validate the pattern. Everything was set up above. */
1353 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1354 SET_DEST (PATTERN (i3)));
1357 i3_subst_into_i2 = 1;
1358 goto validate_replacement;
1363 /* If we have no I1 and I2 looks like:
1364 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1366 make up a dummy I1 that is
1369 (set (reg:CC X) (compare:CC Y (const_int 0)))
1371 (We can ignore any trailing CLOBBERs.)
1373 This undoes a previous combination and allows us to match a branch-and-
1376 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1377 && XVECLEN (PATTERN (i2), 0) >= 2
1378 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1379 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1381 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1382 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1383 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1384 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1385 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1386 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1388 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1389 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1394 /* We make I1 with the same INSN_UID as I2. This gives it
1395 the same INSN_CUID for value tracking. Our fake I1 will
1396 never appear in the insn stream so giving it the same INSN_UID
1397 as I2 will not cause a problem. */
1399 subst_prev_insn = i1
1400 = gen_rtx (INSN, VOIDmode, INSN_UID (i2), 0, i2,
1401 XVECEXP (PATTERN (i2), 0, 1), -1, 0, 0);
1403 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1404 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1405 SET_DEST (PATTERN (i1)));
1410 /* Verify that I2 and I1 are valid for combining. */
1411 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1412 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1418 /* Record whether I2DEST is used in I2SRC and similarly for the other
1419 cases. Knowing this will help in register status updating below. */
1420 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1421 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1422 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1424 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1426 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1428 /* Ensure that I3's pattern can be the destination of combines. */
1429 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1430 i1 && i2dest_in_i1src && i1_feeds_i3,
1437 /* See if any of the insns is a MULT operation. Unless one is, we will
1438 reject a combination that is, since it must be slower. Be conservative
1440 if (GET_CODE (i2src) == MULT
1441 || (i1 != 0 && GET_CODE (i1src) == MULT)
1442 || (GET_CODE (PATTERN (i3)) == SET
1443 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
1446 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1447 We used to do this EXCEPT in one case: I3 has a post-inc in an
1448 output operand. However, that exception can give rise to insns like
1450 which is a famous insn on the PDP-11 where the value of r3 used as the
1451 source was model-dependent. Avoid this sort of thing. */
1454 if (!(GET_CODE (PATTERN (i3)) == SET
1455 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1456 && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1457 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1458 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1459 /* It's not the exception. */
1462 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1463 if (REG_NOTE_KIND (link) == REG_INC
1464 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1466 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1473 /* See if the SETs in I1 or I2 need to be kept around in the merged
1474 instruction: whenever the value set there is still needed past I3.
1475 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1477 For the SET in I1, we have two cases: If I1 and I2 independently
1478 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1479 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1480 in I1 needs to be kept around unless I1DEST dies or is set in either
1481 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1482 I1DEST. If so, we know I1 feeds into I2. */
1484 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1487 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1488 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1490 /* If the set in I2 needs to be kept around, we must make a copy of
1491 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1492 PATTERN (I2), we are only substituting for the original I1DEST, not into
1493 an already-substituted copy. This also prevents making self-referential
1494 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1497 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1498 ? gen_rtx (SET, VOIDmode, i2dest, i2src)
1502 i2pat = copy_rtx (i2pat);
1506 /* Substitute in the latest insn for the regs set by the earlier ones. */
1508 maxreg = max_reg_num ();
1512 /* It is possible that the source of I2 or I1 may be performing an
1513 unneeded operation, such as a ZERO_EXTEND of something that is known
1514 to have the high part zero. Handle that case by letting subst look at
1515 the innermost one of them.
1517 Another way to do this would be to have a function that tries to
1518 simplify a single insn instead of merging two or more insns. We don't
1519 do this because of the potential of infinite loops and because
1520 of the potential extra memory required. However, doing it the way
1521 we are is a bit of a kludge and doesn't catch all cases.
1523 But only do this if -fexpensive-optimizations since it slows things down
1524 and doesn't usually win. */
1526 if (flag_expensive_optimizations)
1528 /* Pass pc_rtx so no substitutions are done, just simplifications.
1529 The cases that we are interested in here do not involve the few
1530 cases were is_replaced is checked. */
1533 subst_low_cuid = INSN_CUID (i1);
1534 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1538 subst_low_cuid = INSN_CUID (i2);
1539 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1542 undobuf.previous_undos = undobuf.undos;
1546 /* Many machines that don't use CC0 have insns that can both perform an
1547 arithmetic operation and set the condition code. These operations will
1548 be represented as a PARALLEL with the first element of the vector
1549 being a COMPARE of an arithmetic operation with the constant zero.
1550 The second element of the vector will set some pseudo to the result
1551 of the same arithmetic operation. If we simplify the COMPARE, we won't
1552 match such a pattern and so will generate an extra insn. Here we test
1553 for this case, where both the comparison and the operation result are
1554 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1555 I2SRC. Later we will make the PARALLEL that contains I2. */
1557 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1558 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1559 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1560 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1563 enum machine_mode compare_mode;
1565 newpat = PATTERN (i3);
1566 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1570 #ifdef EXTRA_CC_MODES
1571 /* See if a COMPARE with the operand we substituted in should be done
1572 with the mode that is currently being used. If not, do the same
1573 processing we do in `subst' for a SET; namely, if the destination
1574 is used only once, try to replace it with a register of the proper
1575 mode and also replace the COMPARE. */
1576 if (undobuf.other_insn == 0
1577 && (cc_use = find_single_use (SET_DEST (newpat), i3,
1578 &undobuf.other_insn))
1579 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
1581 != GET_MODE (SET_DEST (newpat))))
1583 int regno = REGNO (SET_DEST (newpat));
1584 rtx new_dest = gen_rtx (REG, compare_mode, regno);
1586 if (regno < FIRST_PSEUDO_REGISTER
1587 || (reg_n_sets[regno] == 1 && ! added_sets_2
1588 && ! REG_USERVAR_P (SET_DEST (newpat))))
1590 if (regno >= FIRST_PSEUDO_REGISTER)
1591 SUBST (regno_reg_rtx[regno], new_dest);
1593 SUBST (SET_DEST (newpat), new_dest);
1594 SUBST (XEXP (*cc_use, 0), new_dest);
1595 SUBST (SET_SRC (newpat),
1596 gen_rtx_combine (COMPARE, compare_mode,
1597 i2src, const0_rtx));
1600 undobuf.other_insn = 0;
1607 n_occurrences = 0; /* `subst' counts here */
1609 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1610 need to make a unique copy of I2SRC each time we substitute it
1611 to avoid self-referential rtl. */
1613 subst_low_cuid = INSN_CUID (i2);
1614 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1615 ! i1_feeds_i3 && i1dest_in_i1src);
1616 undobuf.previous_undos = undobuf.undos;
1618 /* Record whether i2's body now appears within i3's body. */
1619 i2_is_used = n_occurrences;
1622 /* If we already got a failure, don't try to do more. Otherwise,
1623 try to substitute in I1 if we have it. */
1625 if (i1 && GET_CODE (newpat) != CLOBBER)
1627 /* Before we can do this substitution, we must redo the test done
1628 above (see detailed comments there) that ensures that I1DEST
1629 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1631 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
1639 subst_low_cuid = INSN_CUID (i1);
1640 newpat = subst (newpat, i1dest, i1src, 0, 0);
1641 undobuf.previous_undos = undobuf.undos;
1644 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1645 to count all the ways that I2SRC and I1SRC can be used. */
1646 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
1647 && i2_is_used + added_sets_2 > 1)
1648 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
1649 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
1651 /* Fail if we tried to make a new register (we used to abort, but there's
1652 really no reason to). */
1653 || max_reg_num () != maxreg
1654 /* Fail if we couldn't do something and have a CLOBBER. */
1655 || GET_CODE (newpat) == CLOBBER
1656 /* Fail if this new pattern is a MULT and we didn't have one before
1657 at the outer level. */
1658 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
1665 /* If the actions of the earlier insns must be kept
1666 in addition to substituting them into the latest one,
1667 we must make a new PARALLEL for the latest insn
1668 to hold additional the SETs. */
1670 if (added_sets_1 || added_sets_2)
1674 if (GET_CODE (newpat) == PARALLEL)
1676 rtvec old = XVEC (newpat, 0);
1677 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
1678 newpat = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (total_sets));
1679 bcopy ((char *) &old->elem[0], (char *) XVEC (newpat, 0)->elem,
1680 sizeof (old->elem[0]) * old->num_elem);
1685 total_sets = 1 + added_sets_1 + added_sets_2;
1686 newpat = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (total_sets));
1687 XVECEXP (newpat, 0, 0) = old;
1691 XVECEXP (newpat, 0, --total_sets)
1692 = (GET_CODE (PATTERN (i1)) == PARALLEL
1693 ? gen_rtx (SET, VOIDmode, i1dest, i1src) : PATTERN (i1));
1697 /* If there is no I1, use I2's body as is. We used to also not do
1698 the subst call below if I2 was substituted into I3,
1699 but that could lose a simplification. */
1701 XVECEXP (newpat, 0, --total_sets) = i2pat;
1703 /* See comment where i2pat is assigned. */
1704 XVECEXP (newpat, 0, --total_sets)
1705 = subst (i2pat, i1dest, i1src, 0, 0);
1709 /* We come here when we are replacing a destination in I2 with the
1710 destination of I3. */
1711 validate_replacement:
1713 /* Note which hard regs this insn has as inputs. */
1714 mark_used_regs_combine (newpat);
1716 /* Is the result of combination a valid instruction? */
1718 = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
1720 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
1721 the second SET's destination is a register that is unused. In that case,
1722 we just need the first SET. This can occur when simplifying a divmod
1723 insn. We *must* test for this case here because the code below that
1724 splits two independent SETs doesn't handle this case correctly when it
1725 updates the register status. Also check the case where the first
1726 SET's destination is unused. That would not cause incorrect code, but
1727 does cause an unneeded insn to remain. */
1729 if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1730 && XVECLEN (newpat, 0) == 2
1731 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1732 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1733 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
1734 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
1735 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
1736 && asm_noperands (newpat) < 0)
1738 newpat = XVECEXP (newpat, 0, 0);
1740 = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
1743 else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1744 && XVECLEN (newpat, 0) == 2
1745 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1746 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1747 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
1748 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
1749 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
1750 && asm_noperands (newpat) < 0)
1752 newpat = XVECEXP (newpat, 0, 1);
1754 = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
1757 /* If we were combining three insns and the result is a simple SET
1758 with no ASM_OPERANDS that wasn't recognized, try to split it into two
1759 insns. There are two ways to do this. It can be split using a
1760 machine-specific method (like when you have an addition of a large
1761 constant) or by combine in the function find_split_point. */
1763 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
1764 && asm_noperands (newpat) < 0)
1766 rtx m_split, *split;
1767 rtx ni2dest = i2dest;
1769 /* See if the MD file can split NEWPAT. If it can't, see if letting it
1770 use I2DEST as a scratch register will help. In the latter case,
1771 convert I2DEST to the mode of the source of NEWPAT if we can. */
1773 m_split = split_insns (newpat, i3);
1775 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
1776 inputs of NEWPAT. */
1778 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
1779 possible to try that as a scratch reg. This would require adding
1780 more code to make it work though. */
1782 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
1784 /* If I2DEST is a hard register or the only use of a pseudo,
1785 we can change its mode. */
1786 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
1787 && GET_MODE (SET_DEST (newpat)) != VOIDmode
1788 && GET_CODE (i2dest) == REG
1789 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
1790 || (reg_n_sets[REGNO (i2dest)] == 1 && ! added_sets_2
1791 && ! REG_USERVAR_P (i2dest))))
1792 ni2dest = gen_rtx (REG, GET_MODE (SET_DEST (newpat)),
1795 m_split = split_insns (gen_rtx (PARALLEL, VOIDmode,
1796 gen_rtvec (2, newpat,
1803 if (m_split && GET_CODE (m_split) == SEQUENCE
1804 && XVECLEN (m_split, 0) == 2
1805 && (next_real_insn (i2) == i3
1806 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split, 0, 0)),
1810 rtx newi3pat = PATTERN (XVECEXP (m_split, 0, 1));
1811 newi2pat = PATTERN (XVECEXP (m_split, 0, 0));
1813 i3set = single_set (XVECEXP (m_split, 0, 1));
1814 i2set = single_set (XVECEXP (m_split, 0, 0));
1816 /* In case we changed the mode of I2DEST, replace it in the
1817 pseudo-register table here. We can't do it above in case this
1818 code doesn't get executed and we do a split the other way. */
1820 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
1821 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
1823 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes,
1826 /* If I2 or I3 has multiple SETs, we won't know how to track
1827 register status, so don't use these insns. If I2's destination
1828 is used between I2 and I3, we also can't use these insns. */
1830 if (i2_code_number >= 0 && i2set && i3set
1831 && (next_real_insn (i2) == i3
1832 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
1833 insn_code_number = recog_for_combine (&newi3pat, i3, &new_i3_notes,
1835 if (insn_code_number >= 0)
1838 /* It is possible that both insns now set the destination of I3.
1839 If so, we must show an extra use of it. */
1841 if (insn_code_number >= 0)
1843 rtx new_i3_dest = SET_DEST (i3set);
1844 rtx new_i2_dest = SET_DEST (i2set);
1846 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
1847 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
1848 || GET_CODE (new_i3_dest) == SUBREG)
1849 new_i3_dest = XEXP (new_i3_dest, 0);
1851 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
1852 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
1853 || GET_CODE (new_i2_dest) == SUBREG)
1854 new_i2_dest = XEXP (new_i2_dest, 0);
1856 if (GET_CODE (new_i3_dest) == REG
1857 && GET_CODE (new_i2_dest) == REG
1858 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
1859 reg_n_sets[REGNO (new_i2_dest)]++;
1863 /* If we can split it and use I2DEST, go ahead and see if that
1864 helps things be recognized. Verify that none of the registers
1865 are set between I2 and I3. */
1866 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
1868 && GET_CODE (i2dest) == REG
1870 /* We need I2DEST in the proper mode. If it is a hard register
1871 or the only use of a pseudo, we can change its mode. */
1872 && (GET_MODE (*split) == GET_MODE (i2dest)
1873 || GET_MODE (*split) == VOIDmode
1874 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
1875 || (reg_n_sets[REGNO (i2dest)] == 1 && ! added_sets_2
1876 && ! REG_USERVAR_P (i2dest)))
1877 && (next_real_insn (i2) == i3
1878 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
1879 /* We can't overwrite I2DEST if its value is still used by
1881 && ! reg_referenced_p (i2dest, newpat))
1883 rtx newdest = i2dest;
1884 enum rtx_code split_code = GET_CODE (*split);
1885 enum machine_mode split_mode = GET_MODE (*split);
1887 /* Get NEWDEST as a register in the proper mode. We have already
1888 validated that we can do this. */
1889 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
1891 newdest = gen_rtx (REG, split_mode, REGNO (i2dest));
1893 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
1894 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
1897 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
1898 an ASHIFT. This can occur if it was inside a PLUS and hence
1899 appeared to be a memory address. This is a kludge. */
1900 if (split_code == MULT
1901 && GET_CODE (XEXP (*split, 1)) == CONST_INT
1902 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
1904 SUBST (*split, gen_rtx_combine (ASHIFT, split_mode,
1905 XEXP (*split, 0), GEN_INT (i)));
1906 /* Update split_code because we may not have a multiply
1908 split_code = GET_CODE (*split);
1911 #ifdef INSN_SCHEDULING
1912 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
1913 be written as a ZERO_EXTEND. */
1914 if (split_code == SUBREG && GET_CODE (SUBREG_REG (*split)) == MEM)
1915 SUBST (*split, gen_rtx_combine (ZERO_EXTEND, split_mode,
1919 newi2pat = gen_rtx_combine (SET, VOIDmode, newdest, *split);
1920 SUBST (*split, newdest);
1922 = recog_for_combine (&newi2pat, i2, &new_i2_notes, &i2_scratches);
1924 /* If the split point was a MULT and we didn't have one before,
1925 don't use one now. */
1926 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
1928 = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
1932 /* Check for a case where we loaded from memory in a narrow mode and
1933 then sign extended it, but we need both registers. In that case,
1934 we have a PARALLEL with both loads from the same memory location.
1935 We can split this into a load from memory followed by a register-register
1936 copy. This saves at least one insn, more if register allocation can
1939 We cannot do this if the destination of the second assignment is
1940 a register that we have already assumed is zero-extended. Similarly
1941 for a SUBREG of such a register. */
1943 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
1944 && GET_CODE (newpat) == PARALLEL
1945 && XVECLEN (newpat, 0) == 2
1946 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1947 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
1948 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1949 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
1950 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
1951 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
1953 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
1954 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
1955 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
1956 (GET_CODE (temp) == REG
1957 && reg_nonzero_bits[REGNO (temp)] != 0
1958 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
1959 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
1960 && (reg_nonzero_bits[REGNO (temp)]
1961 != GET_MODE_MASK (word_mode))))
1962 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
1963 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
1964 (GET_CODE (temp) == REG
1965 && reg_nonzero_bits[REGNO (temp)] != 0
1966 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
1967 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
1968 && (reg_nonzero_bits[REGNO (temp)]
1969 != GET_MODE_MASK (word_mode)))))
1970 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
1971 SET_SRC (XVECEXP (newpat, 0, 1)))
1972 && ! find_reg_note (i3, REG_UNUSED,
1973 SET_DEST (XVECEXP (newpat, 0, 0))))
1977 newi2pat = XVECEXP (newpat, 0, 0);
1978 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
1979 newpat = XVECEXP (newpat, 0, 1);
1980 SUBST (SET_SRC (newpat),
1981 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest));
1983 = recog_for_combine (&newi2pat, i2, &new_i2_notes, &i2_scratches);
1985 if (i2_code_number >= 0)
1987 = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
1989 if (insn_code_number >= 0)
1994 /* If we will be able to accept this, we have made a change to the
1995 destination of I3. This can invalidate a LOG_LINKS pointing
1996 to I3. No other part of combine.c makes such a transformation.
1998 The new I3 will have a destination that was previously the
1999 destination of I1 or I2 and which was used in i2 or I3. Call
2000 distribute_links to make a LOG_LINK from the next use of
2001 that destination. */
2003 PATTERN (i3) = newpat;
2004 distribute_links (gen_rtx (INSN_LIST, VOIDmode, i3, NULL_RTX));
2006 /* I3 now uses what used to be its destination and which is
2007 now I2's destination. That means we need a LOG_LINK from
2008 I3 to I2. But we used to have one, so we still will.
2010 However, some later insn might be using I2's dest and have
2011 a LOG_LINK pointing at I3. We must remove this link.
2012 The simplest way to remove the link is to point it at I1,
2013 which we know will be a NOTE. */
2015 for (insn = NEXT_INSN (i3);
2016 insn && (this_basic_block == n_basic_blocks - 1
2017 || insn != basic_block_head[this_basic_block + 1]);
2018 insn = NEXT_INSN (insn))
2020 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
2021 && reg_referenced_p (ni2dest, PATTERN (insn)))
2023 for (link = LOG_LINKS (insn); link;
2024 link = XEXP (link, 1))
2025 if (XEXP (link, 0) == i3)
2026 XEXP (link, 0) = i1;
2034 /* Similarly, check for a case where we have a PARALLEL of two independent
2035 SETs but we started with three insns. In this case, we can do the sets
2036 as two separate insns. This case occurs when some SET allows two
2037 other insns to combine, but the destination of that SET is still live. */
2039 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2040 && GET_CODE (newpat) == PARALLEL
2041 && XVECLEN (newpat, 0) == 2
2042 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2043 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2044 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2045 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2046 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2047 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2048 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2050 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2051 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2052 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2053 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2054 XVECEXP (newpat, 0, 0))
2055 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2056 XVECEXP (newpat, 0, 1)))
2058 newi2pat = XVECEXP (newpat, 0, 1);
2059 newpat = XVECEXP (newpat, 0, 0);
2062 = recog_for_combine (&newi2pat, i2, &new_i2_notes, &i2_scratches);
2064 if (i2_code_number >= 0)
2066 = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
2069 /* If it still isn't recognized, fail and change things back the way they
2071 if ((insn_code_number < 0
2072 /* Is the result a reasonable ASM_OPERANDS? */
2073 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2079 /* If we had to change another insn, make sure it is valid also. */
2080 if (undobuf.other_insn)
2082 rtx other_pat = PATTERN (undobuf.other_insn);
2083 rtx new_other_notes;
2086 CLEAR_HARD_REG_SET (newpat_used_regs);
2089 = recog_for_combine (&other_pat, undobuf.other_insn,
2090 &new_other_notes, &other_scratches);
2092 if (other_code_number < 0 && ! check_asm_operands (other_pat))
2098 PATTERN (undobuf.other_insn) = other_pat;
2100 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2101 are still valid. Then add any non-duplicate notes added by
2102 recog_for_combine. */
2103 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2105 next = XEXP (note, 1);
2107 if (REG_NOTE_KIND (note) == REG_UNUSED
2108 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2110 if (GET_CODE (XEXP (note, 0)) == REG)
2111 reg_n_deaths[REGNO (XEXP (note, 0))]--;
2113 remove_note (undobuf.other_insn, note);
2117 for (note = new_other_notes; note; note = XEXP (note, 1))
2118 if (GET_CODE (XEXP (note, 0)) == REG)
2119 reg_n_deaths[REGNO (XEXP (note, 0))]++;
2121 distribute_notes (new_other_notes, undobuf.other_insn,
2122 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
2125 /* We now know that we can do this combination. Merge the insns and
2126 update the status of registers and LOG_LINKS. */
2129 rtx i3notes, i2notes, i1notes = 0;
2130 rtx i3links, i2links, i1links = 0;
2133 /* Compute which registers we expect to eliminate. */
2134 rtx elim_i2 = (newi2pat || i2dest_in_i2src || i2dest_in_i1src
2136 rtx elim_i1 = i1 == 0 || i1dest_in_i1src ? 0 : i1dest;
2138 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2140 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2141 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2143 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2145 /* Ensure that we do not have something that should not be shared but
2146 occurs multiple times in the new insns. Check this by first
2147 resetting all the `used' flags and then copying anything is shared. */
2149 reset_used_flags (i3notes);
2150 reset_used_flags (i2notes);
2151 reset_used_flags (i1notes);
2152 reset_used_flags (newpat);
2153 reset_used_flags (newi2pat);
2154 if (undobuf.other_insn)
2155 reset_used_flags (PATTERN (undobuf.other_insn));
2157 i3notes = copy_rtx_if_shared (i3notes);
2158 i2notes = copy_rtx_if_shared (i2notes);
2159 i1notes = copy_rtx_if_shared (i1notes);
2160 newpat = copy_rtx_if_shared (newpat);
2161 newi2pat = copy_rtx_if_shared (newi2pat);
2162 if (undobuf.other_insn)
2163 reset_used_flags (PATTERN (undobuf.other_insn));
2165 INSN_CODE (i3) = insn_code_number;
2166 PATTERN (i3) = newpat;
2167 if (undobuf.other_insn)
2168 INSN_CODE (undobuf.other_insn) = other_code_number;
2170 /* We had one special case above where I2 had more than one set and
2171 we replaced a destination of one of those sets with the destination
2172 of I3. In that case, we have to update LOG_LINKS of insns later
2173 in this basic block. Note that this (expensive) case is rare.
2175 Also, in this case, we must pretend that all REG_NOTEs for I2
2176 actually came from I3, so that REG_UNUSED notes from I2 will be
2177 properly handled. */
2179 if (i3_subst_into_i2)
2181 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2182 if (GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
2183 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2184 && ! find_reg_note (i2, REG_UNUSED,
2185 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2186 for (temp = NEXT_INSN (i2);
2187 temp && (this_basic_block == n_basic_blocks - 1
2188 || basic_block_head[this_basic_block] != temp);
2189 temp = NEXT_INSN (temp))
2190 if (temp != i3 && GET_RTX_CLASS (GET_CODE (temp)) == 'i')
2191 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2192 if (XEXP (link, 0) == i2)
2193 XEXP (link, 0) = i3;
2198 while (XEXP (link, 1))
2199 link = XEXP (link, 1);
2200 XEXP (link, 1) = i2notes;
2214 INSN_CODE (i2) = i2_code_number;
2215 PATTERN (i2) = newi2pat;
2219 PUT_CODE (i2, NOTE);
2220 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
2221 NOTE_SOURCE_FILE (i2) = 0;
2228 PUT_CODE (i1, NOTE);
2229 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
2230 NOTE_SOURCE_FILE (i1) = 0;
2233 /* Get death notes for everything that is now used in either I3 or
2234 I2 and used to die in a previous insn. If we built two new
2235 patterns, move from I1 to I2 then I2 to I3 so that we get the
2236 proper movement on registers that I2 modifies. */
2240 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
2241 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
2244 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
2247 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2249 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
2252 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
2255 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
2258 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2261 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2262 know these are REG_UNUSED and want them to go to the desired insn,
2263 so we always pass it as i3. We have not counted the notes in
2264 reg_n_deaths yet, so we need to do so now. */
2266 if (newi2pat && new_i2_notes)
2268 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2269 if (GET_CODE (XEXP (temp, 0)) == REG)
2270 reg_n_deaths[REGNO (XEXP (temp, 0))]++;
2272 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2277 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2278 if (GET_CODE (XEXP (temp, 0)) == REG)
2279 reg_n_deaths[REGNO (XEXP (temp, 0))]++;
2281 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
2284 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2285 put a REG_DEAD note for it somewhere. Similarly for I2 and I1.
2286 Show an additional death due to the REG_DEAD note we make here. If
2287 we discard it in distribute_notes, we will decrement it again. */
2291 if (GET_CODE (i3dest_killed) == REG)
2292 reg_n_deaths[REGNO (i3dest_killed)]++;
2294 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i3dest_killed,
2296 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2297 NULL_RTX, NULL_RTX);
2300 /* For I2 and I1, we have to be careful. If NEWI2PAT exists and sets
2301 I2DEST or I1DEST, the death must be somewhere before I2, not I3. If
2302 we passed I3 in that case, it might delete I2. */
2304 if (i2dest_in_i2src)
2306 if (GET_CODE (i2dest) == REG)
2307 reg_n_deaths[REGNO (i2dest)]++;
2309 if (newi2pat && reg_set_p (i2dest, newi2pat))
2310 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i2dest, NULL_RTX),
2311 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2313 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i2dest, NULL_RTX),
2314 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2315 NULL_RTX, NULL_RTX);
2318 if (i1dest_in_i1src)
2320 if (GET_CODE (i1dest) == REG)
2321 reg_n_deaths[REGNO (i1dest)]++;
2323 if (newi2pat && reg_set_p (i1dest, newi2pat))
2324 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i1dest, NULL_RTX),
2325 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2327 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i1dest, NULL_RTX),
2328 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2329 NULL_RTX, NULL_RTX);
2332 distribute_links (i3links);
2333 distribute_links (i2links);
2334 distribute_links (i1links);
2336 if (GET_CODE (i2dest) == REG)
2339 rtx i2_insn = 0, i2_val = 0, set;
2341 /* The insn that used to set this register doesn't exist, and
2342 this life of the register may not exist either. See if one of
2343 I3's links points to an insn that sets I2DEST. If it does,
2344 that is now the last known value for I2DEST. If we don't update
2345 this and I2 set the register to a value that depended on its old
2346 contents, we will get confused. If this insn is used, thing
2347 will be set correctly in combine_instructions. */
2349 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2350 if ((set = single_set (XEXP (link, 0))) != 0
2351 && rtx_equal_p (i2dest, SET_DEST (set)))
2352 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2354 record_value_for_reg (i2dest, i2_insn, i2_val);
2356 /* If the reg formerly set in I2 died only once and that was in I3,
2357 zero its use count so it won't make `reload' do any work. */
2358 if (! added_sets_2 && newi2pat == 0 && ! i2dest_in_i2src)
2360 regno = REGNO (i2dest);
2361 reg_n_sets[regno]--;
2362 if (reg_n_sets[regno] == 0
2363 && ! (basic_block_live_at_start[0][regno / REGSET_ELT_BITS]
2364 & ((REGSET_ELT_TYPE) 1 << (regno % REGSET_ELT_BITS))))
2365 reg_n_refs[regno] = 0;
2369 if (i1 && GET_CODE (i1dest) == REG)
2372 rtx i1_insn = 0, i1_val = 0, set;
2374 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2375 if ((set = single_set (XEXP (link, 0))) != 0
2376 && rtx_equal_p (i1dest, SET_DEST (set)))
2377 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2379 record_value_for_reg (i1dest, i1_insn, i1_val);
2381 regno = REGNO (i1dest);
2382 if (! added_sets_1 && ! i1dest_in_i1src)
2384 reg_n_sets[regno]--;
2385 if (reg_n_sets[regno] == 0
2386 && ! (basic_block_live_at_start[0][regno / REGSET_ELT_BITS]
2387 & ((REGSET_ELT_TYPE) 1 << (regno % REGSET_ELT_BITS))))
2388 reg_n_refs[regno] = 0;
2392 /* Update reg_nonzero_bits et al for any changes that may have been made
2395 note_stores (newpat, set_nonzero_bits_and_sign_copies);
2397 note_stores (newi2pat, set_nonzero_bits_and_sign_copies);
2399 /* If we added any (clobber (scratch)), add them to the max for a
2400 block. This is a very pessimistic calculation, since we might
2401 have had them already and this might not be the worst block, but
2402 it's not worth doing any better. */
2403 max_scratch += i3_scratches + i2_scratches + other_scratches;
2405 /* If I3 is now an unconditional jump, ensure that it has a
2406 BARRIER following it since it may have initially been a
2407 conditional jump. It may also be the last nonnote insn. */
2409 if ((GET_CODE (newpat) == RETURN || simplejump_p (i3))
2410 && ((temp = next_nonnote_insn (i3)) == NULL_RTX
2411 || GET_CODE (temp) != BARRIER))
2412 emit_barrier_after (i3);
2415 combine_successes++;
2417 /* Clear this here, so that subsequent get_last_value calls are not
2419 subst_prev_insn = NULL_RTX;
2421 if (added_links_insn
2422 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
2423 && INSN_CUID (added_links_insn) < INSN_CUID (i3))
2424 return added_links_insn;
2426 return newi2pat ? i2 : i3;
2429 /* Undo all the modifications recorded in undobuf. */
2434 struct undo *undo, *next;
2436 for (undo = undobuf.undos; undo; undo = next)
2440 *undo->where.i = undo->old_contents.i;
2442 *undo->where.r = undo->old_contents.r;
2444 undo->next = undobuf.frees;
2445 undobuf.frees = undo;
2448 obfree (undobuf.storage);
2449 undobuf.undos = undobuf.previous_undos = 0;
2451 /* Clear this here, so that subsequent get_last_value calls are not
2453 subst_prev_insn = NULL_RTX;
2456 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2457 where we have an arithmetic expression and return that point. LOC will
2460 try_combine will call this function to see if an insn can be split into
2464 find_split_point (loc, insn)
2469 enum rtx_code code = GET_CODE (x);
2471 int len = 0, pos, unsignedp;
2474 /* First special-case some codes. */
2478 #ifdef INSN_SCHEDULING
2479 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2481 if (GET_CODE (SUBREG_REG (x)) == MEM)
2484 return find_split_point (&SUBREG_REG (x), insn);
2488 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2489 using LO_SUM and HIGH. */
2490 if (GET_CODE (XEXP (x, 0)) == CONST
2491 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
2494 gen_rtx_combine (LO_SUM, Pmode,
2495 gen_rtx_combine (HIGH, Pmode, XEXP (x, 0)),
2497 return &XEXP (XEXP (x, 0), 0);
2501 /* If we have a PLUS whose second operand is a constant and the
2502 address is not valid, perhaps will can split it up using
2503 the machine-specific way to split large constants. We use
2504 the first pseudo-reg (one of the virtual regs) as a placeholder;
2505 it will not remain in the result. */
2506 if (GET_CODE (XEXP (x, 0)) == PLUS
2507 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2508 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
2510 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
2511 rtx seq = split_insns (gen_rtx (SET, VOIDmode, reg, XEXP (x, 0)),
2514 /* This should have produced two insns, each of which sets our
2515 placeholder. If the source of the second is a valid address,
2516 we can make put both sources together and make a split point
2519 if (seq && XVECLEN (seq, 0) == 2
2520 && GET_CODE (XVECEXP (seq, 0, 0)) == INSN
2521 && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) == SET
2522 && SET_DEST (PATTERN (XVECEXP (seq, 0, 0))) == reg
2523 && ! reg_mentioned_p (reg,
2524 SET_SRC (PATTERN (XVECEXP (seq, 0, 0))))
2525 && GET_CODE (XVECEXP (seq, 0, 1)) == INSN
2526 && GET_CODE (PATTERN (XVECEXP (seq, 0, 1))) == SET
2527 && SET_DEST (PATTERN (XVECEXP (seq, 0, 1))) == reg
2528 && memory_address_p (GET_MODE (x),
2529 SET_SRC (PATTERN (XVECEXP (seq, 0, 1)))))
2531 rtx src1 = SET_SRC (PATTERN (XVECEXP (seq, 0, 0)));
2532 rtx src2 = SET_SRC (PATTERN (XVECEXP (seq, 0, 1)));
2534 /* Replace the placeholder in SRC2 with SRC1. If we can
2535 find where in SRC2 it was placed, that can become our
2536 split point and we can replace this address with SRC2.
2537 Just try two obvious places. */
2539 src2 = replace_rtx (src2, reg, src1);
2541 if (XEXP (src2, 0) == src1)
2542 split = &XEXP (src2, 0);
2543 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
2544 && XEXP (XEXP (src2, 0), 0) == src1)
2545 split = &XEXP (XEXP (src2, 0), 0);
2549 SUBST (XEXP (x, 0), src2);
2554 /* If that didn't work, perhaps the first operand is complex and
2555 needs to be computed separately, so make a split point there.
2556 This will occur on machines that just support REG + CONST
2557 and have a constant moved through some previous computation. */
2559 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o'
2560 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
2561 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0))))
2563 return &XEXP (XEXP (x, 0), 0);
2569 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2570 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2571 we need to put the operand into a register. So split at that
2574 if (SET_DEST (x) == cc0_rtx
2575 && GET_CODE (SET_SRC (x)) != COMPARE
2576 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
2577 && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
2578 && ! (GET_CODE (SET_SRC (x)) == SUBREG
2579 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
2580 return &SET_SRC (x);
2583 /* See if we can split SET_SRC as it stands. */
2584 split = find_split_point (&SET_SRC (x), insn);
2585 if (split && split != &SET_SRC (x))
2588 /* See if we can split SET_DEST as it stands. */
2589 split = find_split_point (&SET_DEST (x), insn);
2590 if (split && split != &SET_DEST (x))
2593 /* See if this is a bitfield assignment with everything constant. If
2594 so, this is an IOR of an AND, so split it into that. */
2595 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
2596 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
2597 <= HOST_BITS_PER_WIDE_INT)
2598 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
2599 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
2600 && GET_CODE (SET_SRC (x)) == CONST_INT
2601 && ((INTVAL (XEXP (SET_DEST (x), 1))
2602 + INTVAL (XEXP (SET_DEST (x), 2)))
2603 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
2604 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
2606 int pos = INTVAL (XEXP (SET_DEST (x), 2));
2607 int len = INTVAL (XEXP (SET_DEST (x), 1));
2608 int src = INTVAL (SET_SRC (x));
2609 rtx dest = XEXP (SET_DEST (x), 0);
2610 enum machine_mode mode = GET_MODE (dest);
2611 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
2613 if (BITS_BIG_ENDIAN)
2614 pos = GET_MODE_BITSIZE (mode) - len - pos;
2618 gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
2621 gen_binary (IOR, mode,
2622 gen_binary (AND, mode, dest,
2623 GEN_INT (~ (mask << pos)
2624 & GET_MODE_MASK (mode))),
2625 GEN_INT (src << pos)));
2627 SUBST (SET_DEST (x), dest);
2629 split = find_split_point (&SET_SRC (x), insn);
2630 if (split && split != &SET_SRC (x))
2634 /* Otherwise, see if this is an operation that we can split into two.
2635 If so, try to split that. */
2636 code = GET_CODE (SET_SRC (x));
2641 /* If we are AND'ing with a large constant that is only a single
2642 bit and the result is only being used in a context where we
2643 need to know if it is zero or non-zero, replace it with a bit
2644 extraction. This will avoid the large constant, which might
2645 have taken more than one insn to make. If the constant were
2646 not a valid argument to the AND but took only one insn to make,
2647 this is no worse, but if it took more than one insn, it will
2650 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2651 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
2652 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
2653 && GET_CODE (SET_DEST (x)) == REG
2654 && (split = find_single_use (SET_DEST (x), insn, NULL_PTR)) != 0
2655 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
2656 && XEXP (*split, 0) == SET_DEST (x)
2657 && XEXP (*split, 1) == const0_rtx)
2659 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
2660 XEXP (SET_SRC (x), 0),
2661 pos, NULL_RTX, 1, 1, 0, 0);
2662 if (extraction != 0)
2664 SUBST (SET_SRC (x), extraction);
2665 return find_split_point (loc, insn);
2671 inner = XEXP (SET_SRC (x), 0);
2673 len = GET_MODE_BITSIZE (GET_MODE (inner));
2679 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2680 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
2682 inner = XEXP (SET_SRC (x), 0);
2683 len = INTVAL (XEXP (SET_SRC (x), 1));
2684 pos = INTVAL (XEXP (SET_SRC (x), 2));
2686 if (BITS_BIG_ENDIAN)
2687 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
2688 unsignedp = (code == ZERO_EXTRACT);
2693 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
2695 enum machine_mode mode = GET_MODE (SET_SRC (x));
2697 /* For unsigned, we have a choice of a shift followed by an
2698 AND or two shifts. Use two shifts for field sizes where the
2699 constant might be too large. We assume here that we can
2700 always at least get 8-bit constants in an AND insn, which is
2701 true for every current RISC. */
2703 if (unsignedp && len <= 8)
2708 gen_rtx_combine (LSHIFTRT, mode,
2709 gen_lowpart_for_combine (mode, inner),
2711 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
2713 split = find_split_point (&SET_SRC (x), insn);
2714 if (split && split != &SET_SRC (x))
2721 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
2722 gen_rtx_combine (ASHIFT, mode,
2723 gen_lowpart_for_combine (mode, inner),
2724 GEN_INT (GET_MODE_BITSIZE (mode)
2726 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
2728 split = find_split_point (&SET_SRC (x), insn);
2729 if (split && split != &SET_SRC (x))
2734 /* See if this is a simple operation with a constant as the second
2735 operand. It might be that this constant is out of range and hence
2736 could be used as a split point. */
2737 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2738 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2739 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
2740 && CONSTANT_P (XEXP (SET_SRC (x), 1))
2741 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
2742 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
2743 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
2745 return &XEXP (SET_SRC (x), 1);
2747 /* Finally, see if this is a simple operation with its first operand
2748 not in a register. The operation might require this operand in a
2749 register, so return it as a split point. We can always do this
2750 because if the first operand were another operation, we would have
2751 already found it as a split point. */
2752 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2753 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2754 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
2755 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
2756 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
2757 return &XEXP (SET_SRC (x), 0);
2763 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
2764 it is better to write this as (not (ior A B)) so we can split it.
2765 Similarly for IOR. */
2766 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
2769 gen_rtx_combine (NOT, GET_MODE (x),
2770 gen_rtx_combine (code == IOR ? AND : IOR,
2772 XEXP (XEXP (x, 0), 0),
2773 XEXP (XEXP (x, 1), 0))));
2774 return find_split_point (loc, insn);
2777 /* Many RISC machines have a large set of logical insns. If the
2778 second operand is a NOT, put it first so we will try to split the
2779 other operand first. */
2780 if (GET_CODE (XEXP (x, 1)) == NOT)
2782 rtx tem = XEXP (x, 0);
2783 SUBST (XEXP (x, 0), XEXP (x, 1));
2784 SUBST (XEXP (x, 1), tem);
2789 /* Otherwise, select our actions depending on our rtx class. */
2790 switch (GET_RTX_CLASS (code))
2792 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
2794 split = find_split_point (&XEXP (x, 2), insn);
2797 /* ... fall through ... */
2801 split = find_split_point (&XEXP (x, 1), insn);
2804 /* ... fall through ... */
2806 /* Some machines have (and (shift ...) ...) insns. If X is not
2807 an AND, but XEXP (X, 0) is, use it as our split point. */
2808 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
2809 return &XEXP (x, 0);
2811 split = find_split_point (&XEXP (x, 0), insn);
2817 /* Otherwise, we don't have a split point. */
2821 /* Throughout X, replace FROM with TO, and return the result.
2822 The result is TO if X is FROM;
2823 otherwise the result is X, but its contents may have been modified.
2824 If they were modified, a record was made in undobuf so that
2825 undo_all will (among other things) return X to its original state.
2827 If the number of changes necessary is too much to record to undo,
2828 the excess changes are not made, so the result is invalid.
2829 The changes already made can still be undone.
2830 undobuf.num_undo is incremented for such changes, so by testing that
2831 the caller can tell whether the result is valid.
2833 `n_occurrences' is incremented each time FROM is replaced.
2835 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
2837 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
2838 by copying if `n_occurrences' is non-zero. */
2841 subst (x, from, to, in_dest, unique_copy)
2842 register rtx x, from, to;
2846 register enum rtx_code code = GET_CODE (x);
2847 enum machine_mode op0_mode = VOIDmode;
2849 register int len, i;
2852 /* Two expressions are equal if they are identical copies of a shared
2853 RTX or if they are both registers with the same register number
2856 #define COMBINE_RTX_EQUAL_P(X,Y) \
2858 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
2859 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
2861 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
2864 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
2867 /* If X and FROM are the same register but different modes, they will
2868 not have been seen as equal above. However, flow.c will make a
2869 LOG_LINKS entry for that case. If we do nothing, we will try to
2870 rerecognize our original insn and, when it succeeds, we will
2871 delete the feeding insn, which is incorrect.
2873 So force this insn not to match in this (rare) case. */
2874 if (! in_dest && code == REG && GET_CODE (from) == REG
2875 && REGNO (x) == REGNO (from))
2876 return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
2878 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
2879 of which may contain things that can be combined. */
2880 if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
2883 /* It is possible to have a subexpression appear twice in the insn.
2884 Suppose that FROM is a register that appears within TO.
2885 Then, after that subexpression has been scanned once by `subst',
2886 the second time it is scanned, TO may be found. If we were
2887 to scan TO here, we would find FROM within it and create a
2888 self-referent rtl structure which is completely wrong. */
2889 if (COMBINE_RTX_EQUAL_P (x, to))
2892 len = GET_RTX_LENGTH (code);
2893 fmt = GET_RTX_FORMAT (code);
2895 /* We don't need to process a SET_DEST that is a register, CC0, or PC, so
2896 set up to skip this common case. All other cases where we want to
2897 suppress replacing something inside a SET_SRC are handled via the
2900 && (GET_CODE (SET_DEST (x)) == REG
2901 || GET_CODE (SET_DEST (x)) == CC0
2902 || GET_CODE (SET_DEST (x)) == PC))
2905 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
2908 op0_mode = GET_MODE (XEXP (x, 0));
2910 for (i = 0; i < len; i++)
2915 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2917 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
2919 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
2924 new = subst (XVECEXP (x, i, j), from, to, 0, unique_copy);
2926 /* If this substitution failed, this whole thing fails. */
2927 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
2931 SUBST (XVECEXP (x, i, j), new);
2934 else if (fmt[i] == 'e')
2936 if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
2938 /* In general, don't install a subreg involving two modes not
2939 tieable. It can worsen register allocation, and can even
2940 make invalid reload insns, since the reg inside may need to
2941 be copied from in the outside mode, and that may be invalid
2942 if it is an fp reg copied in integer mode.
2944 We allow two exceptions to this: It is valid if it is inside
2945 another SUBREG and the mode of that SUBREG and the mode of
2946 the inside of TO is tieable and it is valid if X is a SET
2947 that copies FROM to CC0. */
2948 if (GET_CODE (to) == SUBREG
2949 && ! MODES_TIEABLE_P (GET_MODE (to),
2950 GET_MODE (SUBREG_REG (to)))
2951 && ! (code == SUBREG
2952 && MODES_TIEABLE_P (GET_MODE (x),
2953 GET_MODE (SUBREG_REG (to))))
2955 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
2958 return gen_rtx (CLOBBER, VOIDmode, const0_rtx);
2960 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
2964 /* If we are in a SET_DEST, suppress most cases unless we
2965 have gone inside a MEM, in which case we want to
2966 simplify the address. We assume here that things that
2967 are actually part of the destination have their inner
2968 parts in the first expression. This is true for SUBREG,
2969 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
2970 things aside from REG and MEM that should appear in a
2972 new = subst (XEXP (x, i), from, to,
2974 && (code == SUBREG || code == STRICT_LOW_PART
2975 || code == ZERO_EXTRACT))
2977 && i == 0), unique_copy);
2979 /* If we found that we will have to reject this combination,
2980 indicate that by returning the CLOBBER ourselves, rather than
2981 an expression containing it. This will speed things up as
2982 well as prevent accidents where two CLOBBERs are considered
2983 to be equal, thus producing an incorrect simplification. */
2985 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
2988 SUBST (XEXP (x, i), new);
2992 /* Try to simplify X. If the simplification changed the code, it is likely
2993 that further simplification will help, so loop, but limit the number
2994 of repetitions that will be performed. */
2996 for (i = 0; i < 4; i++)
2998 /* If X is sufficiently simple, don't bother trying to do anything
3000 if (code != CONST_INT && code != REG && code != CLOBBER)
3001 x = simplify_rtx (x, op0_mode, i == 3, in_dest);
3003 if (GET_CODE (x) == code)
3006 code = GET_CODE (x);
3008 /* We no longer know the original mode of operand 0 since we
3009 have changed the form of X) */
3010 op0_mode = VOIDmode;
3016 /* Simplify X, a piece of RTL. We just operate on the expression at the
3017 outer level; call `subst' to simplify recursively. Return the new
3020 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3021 will be the iteration even if an expression with a code different from
3022 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3025 simplify_rtx (x, op0_mode, last, in_dest)
3027 enum machine_mode op0_mode;
3031 enum rtx_code code = GET_CODE (x);
3032 enum machine_mode mode = GET_MODE (x);
3036 /* If this is a commutative operation, put a constant last and a complex
3037 expression first. We don't need to do this for comparisons here. */
3038 if (GET_RTX_CLASS (code) == 'c'
3039 && ((CONSTANT_P (XEXP (x, 0)) && GET_CODE (XEXP (x, 1)) != CONST_INT)
3040 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == 'o'
3041 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')
3042 || (GET_CODE (XEXP (x, 0)) == SUBREG
3043 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == 'o'
3044 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')))
3047 SUBST (XEXP (x, 0), XEXP (x, 1));
3048 SUBST (XEXP (x, 1), temp);
3051 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3052 sign extension of a PLUS with a constant, reverse the order of the sign
3053 extension and the addition. Note that this not the same as the original
3054 code, but overflow is undefined for signed values. Also note that the
3055 PLUS will have been partially moved "inside" the sign-extension, so that
3056 the first operand of X will really look like:
3057 (ashiftrt (plus (ashift A C4) C5) C4).
3059 (plus (ashiftrt (ashift A C4) C2) C4)
3060 and replace the first operand of X with that expression. Later parts
3061 of this function may simplify the expression further.
3063 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3064 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3065 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3067 We do this to simplify address expressions. */
3069 if ((code == PLUS || code == MINUS || code == MULT)
3070 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3071 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
3072 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
3073 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
3074 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3075 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
3076 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3077 && (temp = simplify_binary_operation (ASHIFTRT, mode,
3078 XEXP (XEXP (XEXP (x, 0), 0), 1),
3079 XEXP (XEXP (x, 0), 1))) != 0)
3082 = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3083 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
3084 INTVAL (XEXP (XEXP (x, 0), 1)));
3086 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
3087 INTVAL (XEXP (XEXP (x, 0), 1)));
3089 SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
3092 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3093 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3094 things. Check for cases where both arms are testing the same
3097 Don't do anything if all operands are very simple. */
3099 if (((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c'
3100 || GET_RTX_CLASS (code) == '<')
3101 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3102 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3103 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3105 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o'
3106 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3107 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 1))))
3109 || (GET_RTX_CLASS (code) == '1'
3110 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3111 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3112 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3115 rtx cond, true, false;
3117 cond = if_then_else_cond (x, &true, &false);
3120 rtx cop1 = const0_rtx;
3121 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3123 if (cond_code == NE && GET_RTX_CLASS (GET_CODE (cond)) == '<')
3126 /* Simplify the alternative arms; this may collapse the true and
3127 false arms to store-flag values. */
3128 true = subst (true, pc_rtx, pc_rtx, 0, 0);
3129 false = subst (false, pc_rtx, pc_rtx, 0, 0);
3131 /* Restarting if we generate a store-flag expression will cause
3132 us to loop. Just drop through in this case. */
3134 /* If the result values are STORE_FLAG_VALUE and zero, we can
3135 just make the comparison operation. */
3136 if (true == const_true_rtx && false == const0_rtx)
3137 x = gen_binary (cond_code, mode, cond, cop1);
3138 else if (true == const0_rtx && false == const_true_rtx)
3139 x = gen_binary (reverse_condition (cond_code), mode, cond, cop1);
3141 /* Likewise, we can make the negate of a comparison operation
3142 if the result values are - STORE_FLAG_VALUE and zero. */
3143 else if (GET_CODE (true) == CONST_INT
3144 && INTVAL (true) == - STORE_FLAG_VALUE
3145 && false == const0_rtx)
3146 x = gen_unary (NEG, mode, mode,
3147 gen_binary (cond_code, mode, cond, cop1));
3148 else if (GET_CODE (false) == CONST_INT
3149 && INTVAL (false) == - STORE_FLAG_VALUE
3150 && true == const0_rtx)
3151 x = gen_unary (NEG, mode, mode,
3152 gen_binary (reverse_condition (cond_code),
3155 return gen_rtx (IF_THEN_ELSE, mode,
3156 gen_binary (cond_code, VOIDmode, cond, cop1),
3159 code = GET_CODE (x);
3160 op0_mode = VOIDmode;
3164 /* Try to fold this expression in case we have constants that weren't
3167 switch (GET_RTX_CLASS (code))
3170 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
3173 temp = simplify_relational_operation (code, op0_mode,
3174 XEXP (x, 0), XEXP (x, 1));
3175 #ifdef FLOAT_STORE_FLAG_VALUE
3176 if (temp != 0 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
3177 temp = ((temp == const0_rtx) ? CONST0_RTX (GET_MODE (x))
3178 : immed_real_const_1 (FLOAT_STORE_FLAG_VALUE, GET_MODE (x)));
3183 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3187 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
3188 XEXP (x, 1), XEXP (x, 2));
3193 x = temp, code = GET_CODE (temp);
3195 /* First see if we can apply the inverse distributive law. */
3196 if (code == PLUS || code == MINUS
3197 || code == AND || code == IOR || code == XOR)
3199 x = apply_distributive_law (x);
3200 code = GET_CODE (x);
3203 /* If CODE is an associative operation not otherwise handled, see if we
3204 can associate some operands. This can win if they are constants or
3205 if they are logically related (i.e. (a & b) & a. */
3206 if ((code == PLUS || code == MINUS
3207 || code == MULT || code == AND || code == IOR || code == XOR
3208 || code == DIV || code == UDIV
3209 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
3210 && INTEGRAL_MODE_P (mode))
3212 if (GET_CODE (XEXP (x, 0)) == code)
3214 rtx other = XEXP (XEXP (x, 0), 0);
3215 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
3216 rtx inner_op1 = XEXP (x, 1);
3219 /* Make sure we pass the constant operand if any as the second
3220 one if this is a commutative operation. */
3221 if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
3223 rtx tem = inner_op0;
3224 inner_op0 = inner_op1;
3227 inner = simplify_binary_operation (code == MINUS ? PLUS
3228 : code == DIV ? MULT
3229 : code == UDIV ? MULT
3231 mode, inner_op0, inner_op1);
3233 /* For commutative operations, try the other pair if that one
3235 if (inner == 0 && GET_RTX_CLASS (code) == 'c')
3237 other = XEXP (XEXP (x, 0), 1);
3238 inner = simplify_binary_operation (code, mode,
3239 XEXP (XEXP (x, 0), 0),
3244 return gen_binary (code, mode, other, inner);
3248 /* A little bit of algebraic simplification here. */
3252 /* Ensure that our address has any ASHIFTs converted to MULT in case
3253 address-recognizing predicates are called later. */
3254 temp = make_compound_operation (XEXP (x, 0), MEM);
3255 SUBST (XEXP (x, 0), temp);
3259 /* (subreg:A (mem:B X) N) becomes a modified MEM unless the SUBREG
3260 is paradoxical. If we can't do that safely, then it becomes
3261 something nonsensical so that this combination won't take place. */
3263 if (GET_CODE (SUBREG_REG (x)) == MEM
3264 && (GET_MODE_SIZE (mode)
3265 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
3267 rtx inner = SUBREG_REG (x);
3268 int endian_offset = 0;
3269 /* Don't change the mode of the MEM
3270 if that would change the meaning of the address. */
3271 if (MEM_VOLATILE_P (SUBREG_REG (x))
3272 || mode_dependent_address_p (XEXP (inner, 0)))
3273 return gen_rtx (CLOBBER, mode, const0_rtx);
3275 if (BYTES_BIG_ENDIAN)
3277 if (GET_MODE_SIZE (mode) < UNITS_PER_WORD)
3278 endian_offset += UNITS_PER_WORD - GET_MODE_SIZE (mode);
3279 if (GET_MODE_SIZE (GET_MODE (inner)) < UNITS_PER_WORD)
3280 endian_offset -= (UNITS_PER_WORD
3281 - GET_MODE_SIZE (GET_MODE (inner)));
3283 /* Note if the plus_constant doesn't make a valid address
3284 then this combination won't be accepted. */
3285 x = gen_rtx (MEM, mode,
3286 plus_constant (XEXP (inner, 0),
3287 (SUBREG_WORD (x) * UNITS_PER_WORD
3289 MEM_VOLATILE_P (x) = MEM_VOLATILE_P (inner);
3290 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (inner);
3291 MEM_IN_STRUCT_P (x) = MEM_IN_STRUCT_P (inner);
3295 /* If we are in a SET_DEST, these other cases can't apply. */
3299 /* Changing mode twice with SUBREG => just change it once,
3300 or not at all if changing back to starting mode. */
3301 if (GET_CODE (SUBREG_REG (x)) == SUBREG)
3303 if (mode == GET_MODE (SUBREG_REG (SUBREG_REG (x)))
3304 && SUBREG_WORD (x) == 0 && SUBREG_WORD (SUBREG_REG (x)) == 0)
3305 return SUBREG_REG (SUBREG_REG (x));
3307 SUBST_INT (SUBREG_WORD (x),
3308 SUBREG_WORD (x) + SUBREG_WORD (SUBREG_REG (x)));
3309 SUBST (SUBREG_REG (x), SUBREG_REG (SUBREG_REG (x)));
3312 /* SUBREG of a hard register => just change the register number
3313 and/or mode. If the hard register is not valid in that mode,
3314 suppress this combination. If the hard register is the stack,
3315 frame, or argument pointer, leave this as a SUBREG. */
3317 if (GET_CODE (SUBREG_REG (x)) == REG
3318 && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER
3319 && REGNO (SUBREG_REG (x)) != FRAME_POINTER_REGNUM
3320 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3321 && REGNO (SUBREG_REG (x)) != HARD_FRAME_POINTER_REGNUM
3323 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3324 && REGNO (SUBREG_REG (x)) != ARG_POINTER_REGNUM
3326 && REGNO (SUBREG_REG (x)) != STACK_POINTER_REGNUM)
3328 if (HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (x)) + SUBREG_WORD (x),
3330 return gen_rtx (REG, mode,
3331 REGNO (SUBREG_REG (x)) + SUBREG_WORD (x));
3333 return gen_rtx (CLOBBER, mode, const0_rtx);
3336 /* For a constant, try to pick up the part we want. Handle a full
3337 word and low-order part. Only do this if we are narrowing
3338 the constant; if it is being widened, we have no idea what
3339 the extra bits will have been set to. */
3341 if (CONSTANT_P (SUBREG_REG (x)) && op0_mode != VOIDmode
3342 && GET_MODE_SIZE (mode) == UNITS_PER_WORD
3343 && GET_MODE_SIZE (op0_mode) < UNITS_PER_WORD
3344 && GET_MODE_CLASS (mode) == MODE_INT)
3346 temp = operand_subword (SUBREG_REG (x), SUBREG_WORD (x),
3352 /* If we want a subreg of a constant, at offset 0,
3353 take the low bits. On a little-endian machine, that's
3354 always valid. On a big-endian machine, it's valid
3355 only if the constant's mode fits in one word. */
3356 if (CONSTANT_P (SUBREG_REG (x)) && subreg_lowpart_p (x)
3357 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (op0_mode)
3358 && (! WORDS_BIG_ENDIAN
3359 || GET_MODE_BITSIZE (op0_mode) <= BITS_PER_WORD))
3360 return gen_lowpart_for_combine (mode, SUBREG_REG (x));
3362 /* A paradoxical SUBREG of a VOIDmode constant is the same constant,
3363 since we are saying that the high bits don't matter. */
3364 if (CONSTANT_P (SUBREG_REG (x)) && GET_MODE (SUBREG_REG (x)) == VOIDmode
3365 && GET_MODE_SIZE (mode) > GET_MODE_SIZE (op0_mode))
3366 return SUBREG_REG (x);
3368 /* Note that we cannot do any narrowing for non-constants since
3369 we might have been counting on using the fact that some bits were
3370 zero. We now do this in the SET. */
3375 /* (not (plus X -1)) can become (neg X). */
3376 if (GET_CODE (XEXP (x, 0)) == PLUS
3377 && XEXP (XEXP (x, 0), 1) == constm1_rtx)
3378 return gen_rtx_combine (NEG, mode, XEXP (XEXP (x, 0), 0));
3380 /* Similarly, (not (neg X)) is (plus X -1). */
3381 if (GET_CODE (XEXP (x, 0)) == NEG)
3382 return gen_rtx_combine (PLUS, mode, XEXP (XEXP (x, 0), 0),
3385 /* (not (xor X C)) for C constant is (xor X D) with D = ~ C. */
3386 if (GET_CODE (XEXP (x, 0)) == XOR
3387 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3388 && (temp = simplify_unary_operation (NOT, mode,
3389 XEXP (XEXP (x, 0), 1),
3391 return gen_binary (XOR, mode, XEXP (XEXP (x, 0), 0), temp);
3393 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3394 other than 1, but that is not valid. We could do a similar
3395 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3396 but this doesn't seem common enough to bother with. */
3397 if (GET_CODE (XEXP (x, 0)) == ASHIFT
3398 && XEXP (XEXP (x, 0), 0) == const1_rtx)
3399 return gen_rtx (ROTATE, mode, gen_unary (NOT, mode, mode, const1_rtx),
3400 XEXP (XEXP (x, 0), 1));
3402 if (GET_CODE (XEXP (x, 0)) == SUBREG
3403 && subreg_lowpart_p (XEXP (x, 0))
3404 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3405 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
3406 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
3407 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3409 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3411 x = gen_rtx (ROTATE, inner_mode,
3412 gen_unary (NOT, inner_mode, inner_mode, const1_rtx),
3413 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
3414 return gen_lowpart_for_combine (mode, x);
3417 #if STORE_FLAG_VALUE == -1
3418 /* (not (comparison foo bar)) can be done by reversing the comparison
3420 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3421 && reversible_comparison_p (XEXP (x, 0)))
3422 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
3423 mode, XEXP (XEXP (x, 0), 0),
3424 XEXP (XEXP (x, 0), 1));
3426 /* (ashiftrt foo C) where C is the number of bits in FOO minus 1
3427 is (lt foo (const_int 0)), so we can perform the above
3430 if (XEXP (x, 1) == const1_rtx
3431 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3432 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3433 && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
3434 return gen_rtx_combine (GE, mode, XEXP (XEXP (x, 0), 0), const0_rtx);
3437 /* Apply De Morgan's laws to reduce number of patterns for machines
3438 with negating logical insns (and-not, nand, etc.). If result has
3439 only one NOT, put it first, since that is how the patterns are
3442 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
3444 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
3446 if (GET_CODE (in1) == NOT)
3447 in1 = XEXP (in1, 0);
3449 in1 = gen_rtx_combine (NOT, GET_MODE (in1), in1);
3451 if (GET_CODE (in2) == NOT)
3452 in2 = XEXP (in2, 0);
3453 else if (GET_CODE (in2) == CONST_INT
3454 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3455 in2 = GEN_INT (GET_MODE_MASK (mode) & ~ INTVAL (in2));
3457 in2 = gen_rtx_combine (NOT, GET_MODE (in2), in2);
3459 if (GET_CODE (in2) == NOT)
3462 in2 = in1; in1 = tem;
3465 return gen_rtx_combine (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
3471 /* (neg (plus X 1)) can become (not X). */
3472 if (GET_CODE (XEXP (x, 0)) == PLUS
3473 && XEXP (XEXP (x, 0), 1) == const1_rtx)
3474 return gen_rtx_combine (NOT, mode, XEXP (XEXP (x, 0), 0));
3476 /* Similarly, (neg (not X)) is (plus X 1). */
3477 if (GET_CODE (XEXP (x, 0)) == NOT)
3478 return plus_constant (XEXP (XEXP (x, 0), 0), 1);
3480 /* (neg (minus X Y)) can become (minus Y X). */
3481 if (GET_CODE (XEXP (x, 0)) == MINUS
3482 && (! FLOAT_MODE_P (mode)
3483 /* x-y != -(y-x) with IEEE floating point. */
3484 || TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
3486 return gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
3487 XEXP (XEXP (x, 0), 0));
3489 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
3490 if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx
3491 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
3492 return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3494 /* NEG commutes with ASHIFT since it is multiplication. Only do this
3495 if we can then eliminate the NEG (e.g.,
3496 if the operand is a constant). */
3498 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
3500 temp = simplify_unary_operation (NEG, mode,
3501 XEXP (XEXP (x, 0), 0), mode);
3504 SUBST (XEXP (XEXP (x, 0), 0), temp);
3509 temp = expand_compound_operation (XEXP (x, 0));
3511 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3512 replaced by (lshiftrt X C). This will convert
3513 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
3515 if (GET_CODE (temp) == ASHIFTRT
3516 && GET_CODE (XEXP (temp, 1)) == CONST_INT
3517 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
3518 return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
3519 INTVAL (XEXP (temp, 1)));
3521 /* If X has only a single bit that might be nonzero, say, bit I, convert
3522 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
3523 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
3524 (sign_extract X 1 Y). But only do this if TEMP isn't a register
3525 or a SUBREG of one since we'd be making the expression more
3526 complex if it was just a register. */
3528 if (GET_CODE (temp) != REG
3529 && ! (GET_CODE (temp) == SUBREG
3530 && GET_CODE (SUBREG_REG (temp)) == REG)
3531 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
3533 rtx temp1 = simplify_shift_const
3534 (NULL_RTX, ASHIFTRT, mode,
3535 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
3536 GET_MODE_BITSIZE (mode) - 1 - i),
3537 GET_MODE_BITSIZE (mode) - 1 - i);
3539 /* If all we did was surround TEMP with the two shifts, we
3540 haven't improved anything, so don't use it. Otherwise,
3541 we are better off with TEMP1. */
3542 if (GET_CODE (temp1) != ASHIFTRT
3543 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
3544 || XEXP (XEXP (temp1, 0), 0) != temp)
3550 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3552 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
3553 GET_MODE_MASK (mode), NULL_RTX, 0));
3555 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
3556 if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
3557 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
3558 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
3559 return XEXP (XEXP (x, 0), 0);
3561 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
3562 (OP:SI foo:SI) if OP is NEG or ABS. */
3563 if ((GET_CODE (XEXP (x, 0)) == ABS
3564 || GET_CODE (XEXP (x, 0)) == NEG)
3565 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
3566 || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
3567 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
3568 return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode,
3569 XEXP (XEXP (XEXP (x, 0), 0), 0));
3571 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
3573 if (GET_CODE (XEXP (x, 0)) == SUBREG
3574 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE
3575 && subreg_lowpart_p (XEXP (x, 0)))
3576 return SUBREG_REG (XEXP (x, 0));
3578 /* If we know that the value is already truncated, we can
3579 replace the TRUNCATE with a SUBREG. */
3580 if (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) <= HOST_BITS_PER_WIDE_INT
3581 && (nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
3582 &~ GET_MODE_MASK (mode)) == 0)
3583 return gen_lowpart_for_combine (mode, XEXP (x, 0));
3585 /* A truncate of a comparison can be replaced with a subreg if
3586 STORE_FLAG_VALUE permits. This is like the previous test,
3587 but it works even if the comparison is done in a mode larger
3588 than HOST_BITS_PER_WIDE_INT. */
3589 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3590 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3591 && ((HOST_WIDE_INT) STORE_FLAG_VALUE &~ GET_MODE_MASK (mode)) == 0)
3592 return gen_lowpart_for_combine (mode, XEXP (x, 0));
3594 /* Similarly, a truncate of a register whose value is a
3595 comparison can be replaced with a subreg if STORE_FLAG_VALUE
3597 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3598 && ((HOST_WIDE_INT) STORE_FLAG_VALUE &~ GET_MODE_MASK (mode)) == 0
3599 && (temp = get_last_value (XEXP (x, 0)))
3600 && GET_RTX_CLASS (GET_CODE (temp)) == '<')
3601 return gen_lowpart_for_combine (mode, XEXP (x, 0));
3605 case FLOAT_TRUNCATE:
3606 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
3607 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
3608 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
3609 return XEXP (XEXP (x, 0), 0);
3611 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
3612 (OP:SF foo:SF) if OP is NEG or ABS. */
3613 if ((GET_CODE (XEXP (x, 0)) == ABS
3614 || GET_CODE (XEXP (x, 0)) == NEG)
3615 && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
3616 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
3617 return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode,
3618 XEXP (XEXP (XEXP (x, 0), 0), 0));
3620 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
3621 is (float_truncate:SF x). */
3622 if (GET_CODE (XEXP (x, 0)) == SUBREG
3623 && subreg_lowpart_p (XEXP (x, 0))
3624 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
3625 return SUBREG_REG (XEXP (x, 0));
3630 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
3631 using cc0, in which case we want to leave it as a COMPARE
3632 so we can distinguish it from a register-register-copy. */
3633 if (XEXP (x, 1) == const0_rtx)
3636 /* In IEEE floating point, x-0 is not the same as x. */
3637 if ((TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
3638 || ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0)))
3640 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
3646 /* (const (const X)) can become (const X). Do it this way rather than
3647 returning the inner CONST since CONST can be shared with a
3649 if (GET_CODE (XEXP (x, 0)) == CONST)
3650 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
3655 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
3656 can add in an offset. find_split_point will split this address up
3657 again if it doesn't match. */
3658 if (GET_CODE (XEXP (x, 0)) == HIGH
3659 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
3665 /* If we have (plus (plus (A const) B)), associate it so that CONST is
3666 outermost. That's because that's the way indexed addresses are
3667 supposed to appear. This code used to check many more cases, but
3668 they are now checked elsewhere. */
3669 if (GET_CODE (XEXP (x, 0)) == PLUS
3670 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
3671 return gen_binary (PLUS, mode,
3672 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
3674 XEXP (XEXP (x, 0), 1));
3676 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
3677 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
3678 bit-field and can be replaced by either a sign_extend or a
3679 sign_extract. The `and' may be a zero_extend. */
3680 if (GET_CODE (XEXP (x, 0)) == XOR
3681 && GET_CODE (XEXP (x, 1)) == CONST_INT
3682 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3683 && INTVAL (XEXP (x, 1)) == - INTVAL (XEXP (XEXP (x, 0), 1))
3684 && (i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
3685 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3686 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
3687 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3688 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
3689 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
3690 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
3691 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
3693 return simplify_shift_const
3694 (NULL_RTX, ASHIFTRT, mode,
3695 simplify_shift_const (NULL_RTX, ASHIFT, mode,
3696 XEXP (XEXP (XEXP (x, 0), 0), 0),
3697 GET_MODE_BITSIZE (mode) - (i + 1)),
3698 GET_MODE_BITSIZE (mode) - (i + 1));
3700 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
3701 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
3702 is 1. This produces better code than the alternative immediately
3704 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3705 && reversible_comparison_p (XEXP (x, 0))
3706 && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
3707 || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx)))
3709 gen_unary (NEG, mode, mode,
3710 gen_binary (reverse_condition (GET_CODE (XEXP (x, 0))),
3711 mode, XEXP (XEXP (x, 0), 0),
3712 XEXP (XEXP (x, 0), 1)));
3714 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
3715 can become (ashiftrt (ashift (xor x 1) C) C) where C is
3716 the bitsize of the mode - 1. This allows simplification of
3717 "a = (b & 8) == 0;" */
3718 if (XEXP (x, 1) == constm1_rtx
3719 && GET_CODE (XEXP (x, 0)) != REG
3720 && ! (GET_CODE (XEXP (x,0)) == SUBREG
3721 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
3722 && nonzero_bits (XEXP (x, 0), mode) == 1)
3723 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
3724 simplify_shift_const (NULL_RTX, ASHIFT, mode,
3725 gen_rtx_combine (XOR, mode,
3726 XEXP (x, 0), const1_rtx),
3727 GET_MODE_BITSIZE (mode) - 1),
3728 GET_MODE_BITSIZE (mode) - 1);
3730 /* If we are adding two things that have no bits in common, convert
3731 the addition into an IOR. This will often be further simplified,
3732 for example in cases like ((a & 1) + (a & 2)), which can
3735 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3736 && (nonzero_bits (XEXP (x, 0), mode)
3737 & nonzero_bits (XEXP (x, 1), mode)) == 0)
3738 return gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
3742 #if STORE_FLAG_VALUE == 1
3743 /* (minus 1 (comparison foo bar)) can be done by reversing the comparison
3745 if (XEXP (x, 0) == const1_rtx
3746 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<'
3747 && reversible_comparison_p (XEXP (x, 1)))
3748 return gen_binary (reverse_condition (GET_CODE (XEXP (x, 1))),
3749 mode, XEXP (XEXP (x, 1), 0),
3750 XEXP (XEXP (x, 1), 1));
3753 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
3754 (and <foo> (const_int pow2-1)) */
3755 if (GET_CODE (XEXP (x, 1)) == AND
3756 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
3757 && exact_log2 (- INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
3758 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
3759 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
3760 - INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
3762 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
3764 if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
3765 return gen_binary (MINUS, mode,
3766 gen_binary (MINUS, mode, XEXP (x, 0),
3767 XEXP (XEXP (x, 1), 0)),
3768 XEXP (XEXP (x, 1), 1));
3772 /* If we have (mult (plus A B) C), apply the distributive law and then
3773 the inverse distributive law to see if things simplify. This
3774 occurs mostly in addresses, often when unrolling loops. */
3776 if (GET_CODE (XEXP (x, 0)) == PLUS)
3778 x = apply_distributive_law
3779 (gen_binary (PLUS, mode,
3780 gen_binary (MULT, mode,
3781 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
3782 gen_binary (MULT, mode,
3783 XEXP (XEXP (x, 0), 1), XEXP (x, 1))));
3785 if (GET_CODE (x) != MULT)
3791 /* If this is a divide by a power of two, treat it as a shift if
3792 its first operand is a shift. */
3793 if (GET_CODE (XEXP (x, 1)) == CONST_INT
3794 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
3795 && (GET_CODE (XEXP (x, 0)) == ASHIFT
3796 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
3797 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
3798 || GET_CODE (XEXP (x, 0)) == ROTATE
3799 || GET_CODE (XEXP (x, 0)) == ROTATERT))
3800 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
3804 case GT: case GTU: case GE: case GEU:
3805 case LT: case LTU: case LE: case LEU:
3806 /* If the first operand is a condition code, we can't do anything
3808 if (GET_CODE (XEXP (x, 0)) == COMPARE
3809 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
3811 && XEXP (x, 0) != cc0_rtx
3815 rtx op0 = XEXP (x, 0);
3816 rtx op1 = XEXP (x, 1);
3817 enum rtx_code new_code;
3819 if (GET_CODE (op0) == COMPARE)
3820 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
3822 /* Simplify our comparison, if possible. */
3823 new_code = simplify_comparison (code, &op0, &op1);
3825 #if STORE_FLAG_VALUE == 1
3826 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
3827 if only the low-order bit is possibly nonzero in X (such as when
3828 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
3829 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
3830 known to be either 0 or -1, NE becomes a NEG and EQ becomes
3833 Remove any ZERO_EXTRACT we made when thinking this was a
3834 comparison. It may now be simpler to use, e.g., an AND. If a
3835 ZERO_EXTRACT is indeed appropriate, it will be placed back by
3836 the call to make_compound_operation in the SET case. */
3838 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3839 && op1 == const0_rtx
3840 && nonzero_bits (op0, mode) == 1)
3841 return gen_lowpart_for_combine (mode,
3842 expand_compound_operation (op0));
3844 else if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3845 && op1 == const0_rtx
3846 && (num_sign_bit_copies (op0, mode)
3847 == GET_MODE_BITSIZE (mode)))
3849 op0 = expand_compound_operation (op0);
3850 return gen_unary (NEG, mode, mode,
3851 gen_lowpart_for_combine (mode, op0));
3854 else if (new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
3855 && op1 == const0_rtx
3856 && nonzero_bits (op0, mode) == 1)
3858 op0 = expand_compound_operation (op0);
3859 return gen_binary (XOR, mode,
3860 gen_lowpart_for_combine (mode, op0),
3864 else if (new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
3865 && op1 == const0_rtx
3866 && (num_sign_bit_copies (op0, mode)
3867 == GET_MODE_BITSIZE (mode)))
3869 op0 = expand_compound_operation (op0);
3870 return plus_constant (gen_lowpart_for_combine (mode, op0), 1);
3874 #if STORE_FLAG_VALUE == -1
3875 /* If STORE_FLAG_VALUE is -1, we have cases similar to
3877 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3878 && op1 == const0_rtx
3879 && (num_sign_bit_copies (op0, mode)
3880 == GET_MODE_BITSIZE (mode)))
3881 return gen_lowpart_for_combine (mode,
3882 expand_compound_operation (op0));
3884 else if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3885 && op1 == const0_rtx
3886 && nonzero_bits (op0, mode) == 1)
3888 op0 = expand_compound_operation (op0);
3889 return gen_unary (NEG, mode, mode,
3890 gen_lowpart_for_combine (mode, op0));
3893 else if (new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
3894 && op1 == const0_rtx
3895 && (num_sign_bit_copies (op0, mode)
3896 == GET_MODE_BITSIZE (mode)))
3898 op0 = expand_compound_operation (op0);
3899 return gen_unary (NOT, mode, mode,
3900 gen_lowpart_for_combine (mode, op0));
3903 /* If X is 0/1, (eq X 0) is X-1. */
3904 else if (new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
3905 && op1 == const0_rtx
3906 && nonzero_bits (op0, mode) == 1)
3908 op0 = expand_compound_operation (op0);
3909 return plus_constant (gen_lowpart_for_combine (mode, op0), -1);
3913 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
3914 one bit that might be nonzero, we can convert (ne x 0) to
3915 (ashift x c) where C puts the bit in the sign bit. Remove any
3916 AND with STORE_FLAG_VALUE when we are done, since we are only
3917 going to test the sign bit. */
3918 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3919 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3920 && (STORE_FLAG_VALUE
3921 == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
3922 && op1 == const0_rtx
3923 && mode == GET_MODE (op0)
3924 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
3926 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3927 expand_compound_operation (op0),
3928 GET_MODE_BITSIZE (mode) - 1 - i);
3929 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
3935 /* If the code changed, return a whole new comparison. */
3936 if (new_code != code)
3937 return gen_rtx_combine (new_code, mode, op0, op1);
3939 /* Otherwise, keep this operation, but maybe change its operands.
3940 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
3941 SUBST (XEXP (x, 0), op0);
3942 SUBST (XEXP (x, 1), op1);
3947 return simplify_if_then_else (x);
3953 /* If we are processing SET_DEST, we are done. */
3957 return expand_compound_operation (x);
3960 return simplify_set (x);
3965 return simplify_logical (x, last);
3968 /* (abs (neg <foo>)) -> (abs <foo>) */
3969 if (GET_CODE (XEXP (x, 0)) == NEG)
3970 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
3972 /* If operand is something known to be positive, ignore the ABS. */
3973 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
3974 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
3975 <= HOST_BITS_PER_WIDE_INT)
3976 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
3977 & ((HOST_WIDE_INT) 1
3978 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
3983 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
3984 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
3985 return gen_rtx_combine (NEG, mode, XEXP (x, 0));
3990 /* (ffs (*_extend <X>)) = (ffs <X>) */
3991 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
3992 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
3993 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
3997 /* (float (sign_extend <X>)) = (float <X>). */
3998 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
3999 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4007 /* If this is a shift by a constant amount, simplify it. */
4008 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4009 return simplify_shift_const (x, code, mode, XEXP (x, 0),
4010 INTVAL (XEXP (x, 1)));
4012 #ifdef SHIFT_COUNT_TRUNCATED
4013 else if (SHIFT_COUNT_TRUNCATED && GET_CODE (XEXP (x, 1)) != REG)
4015 force_to_mode (XEXP (x, 1), GET_MODE (x),
4017 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4028 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4031 simplify_if_then_else (x)
4034 enum machine_mode mode = GET_MODE (x);
4035 rtx cond = XEXP (x, 0);
4036 rtx true = XEXP (x, 1);
4037 rtx false = XEXP (x, 2);
4038 enum rtx_code true_code = GET_CODE (cond);
4039 int comparison_p = GET_RTX_CLASS (true_code) == '<';
4043 /* Simplify storing of the truth value. */
4044 if (comparison_p && true == const_true_rtx && false == const0_rtx)
4045 return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1));
4047 /* Also when the truth value has to be reversed. */
4048 if (comparison_p && reversible_comparison_p (cond)
4049 && true == const0_rtx && false == const_true_rtx)
4050 return gen_binary (reverse_condition (true_code),
4051 mode, XEXP (cond, 0), XEXP (cond, 1));
4053 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4054 in it is being compared against certain values. Get the true and false
4055 comparisons and see if that says anything about the value of each arm. */
4057 if (comparison_p && reversible_comparison_p (cond)
4058 && GET_CODE (XEXP (cond, 0)) == REG)
4061 rtx from = XEXP (cond, 0);
4062 enum rtx_code false_code = reverse_condition (true_code);
4063 rtx true_val = XEXP (cond, 1);
4064 rtx false_val = true_val;
4067 /* If FALSE_CODE is EQ, swap the codes and arms. */
4069 if (false_code == EQ)
4071 swapped = 1, true_code = EQ, false_code = NE;
4072 temp = true, true = false, false = temp;
4075 /* If we are comparing against zero and the expression being tested has
4076 only a single bit that might be nonzero, that is its value when it is
4077 not equal to zero. Similarly if it is known to be -1 or 0. */
4079 if (true_code == EQ && true_val == const0_rtx
4080 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4081 false_code = EQ, false_val = GEN_INT (nzb);
4082 else if (true_code == EQ && true_val == const0_rtx
4083 && (num_sign_bit_copies (from, GET_MODE (from))
4084 == GET_MODE_BITSIZE (GET_MODE (from))))
4085 false_code = EQ, false_val = constm1_rtx;
4087 /* Now simplify an arm if we know the value of the register in the
4088 branch and it is used in the arm. Be careful due to the potential
4089 of locally-shared RTL. */
4091 if (reg_mentioned_p (from, true))
4092 true = subst (known_cond (copy_rtx (true), true_code, from, true_val),
4093 pc_rtx, pc_rtx, 0, 0);
4094 if (reg_mentioned_p (from, false))
4095 false = subst (known_cond (copy_rtx (false), false_code,
4097 pc_rtx, pc_rtx, 0, 0);
4099 SUBST (XEXP (x, 1), swapped ? false : true);
4100 SUBST (XEXP (x, 2), swapped ? true : false);
4102 true = XEXP (x, 1), false = XEXP (x, 2), true_code = GET_CODE (cond);
4105 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4106 reversed, do so to avoid needing two sets of patterns for
4107 subtract-and-branch insns. Similarly if we have a constant in the true
4108 arm, the false arm is the same as the first operand of the comparison, or
4109 the false arm is more complicated than the true arm. */
4111 if (comparison_p && reversible_comparison_p (cond)
4113 || (CONSTANT_P (true)
4114 && GET_CODE (false) != CONST_INT && false != pc_rtx)
4115 || true == const0_rtx
4116 || (GET_RTX_CLASS (GET_CODE (true)) == 'o'
4117 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4118 || (GET_CODE (true) == SUBREG
4119 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true))) == 'o'
4120 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4121 || reg_mentioned_p (true, false)
4122 || rtx_equal_p (false, XEXP (cond, 0))))
4124 true_code = reverse_condition (true_code);
4126 gen_binary (true_code, GET_MODE (cond), XEXP (cond, 0),
4129 SUBST (XEXP (x, 1), false);
4130 SUBST (XEXP (x, 2), true);
4132 temp = true, true = false, false = temp, cond = XEXP (x, 0);
4134 /* It is possible that the conditional has been simplified out. */
4135 true_code = GET_CODE (cond);
4136 comparison_p = GET_RTX_CLASS (true_code) == '<';
4139 /* If the two arms are identical, we don't need the comparison. */
4141 if (rtx_equal_p (true, false) && ! side_effects_p (cond))
4144 /* Convert a == b ? b : a to "a". */
4145 if (true_code == EQ && ! side_effects_p (cond)
4146 && rtx_equal_p (XEXP (cond, 0), false)
4147 && rtx_equal_p (XEXP (cond, 1), true))
4149 else if (true_code == NE && ! side_effects_p (cond)
4150 && rtx_equal_p (XEXP (cond, 0), true)
4151 && rtx_equal_p (XEXP (cond, 1), false))
4154 /* Look for cases where we have (abs x) or (neg (abs X)). */
4156 if (GET_MODE_CLASS (mode) == MODE_INT
4157 && GET_CODE (false) == NEG
4158 && rtx_equal_p (true, XEXP (false, 0))
4160 && rtx_equal_p (true, XEXP (cond, 0))
4161 && ! side_effects_p (true))
4166 return gen_unary (ABS, mode, mode, true);
4169 return gen_unary (NEG, mode, mode, gen_unary (ABS, mode, mode, true));
4172 /* Look for MIN or MAX. */
4174 if ((! FLOAT_MODE_P (mode) || flag_fast_math)
4176 && rtx_equal_p (XEXP (cond, 0), true)
4177 && rtx_equal_p (XEXP (cond, 1), false)
4178 && ! side_effects_p (cond))
4183 return gen_binary (SMAX, mode, true, false);
4186 return gen_binary (SMIN, mode, true, false);
4189 return gen_binary (UMAX, mode, true, false);
4192 return gen_binary (UMIN, mode, true, false);
4195 #if STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1
4197 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4198 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4199 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4200 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4201 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4202 neither of the above, but it isn't worth checking for. */
4204 if (comparison_p && mode != VOIDmode && ! side_effects_p (x))
4206 rtx t = make_compound_operation (true, SET);
4207 rtx f = make_compound_operation (false, SET);
4208 rtx cond_op0 = XEXP (cond, 0);
4209 rtx cond_op1 = XEXP (cond, 1);
4210 enum rtx_code op, extend_op = NIL;
4211 enum machine_mode m = mode;
4214 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4215 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4216 || GET_CODE (t) == ASHIFT
4217 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4218 && rtx_equal_p (XEXP (t, 0), f))
4219 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4221 /* If an identity-zero op is commutative, check whether there
4222 would be a match if we swapped the operands. */
4223 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4224 || GET_CODE (t) == XOR)
4225 && rtx_equal_p (XEXP (t, 1), f))
4226 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4227 else if (GET_CODE (t) == SIGN_EXTEND
4228 && (GET_CODE (XEXP (t, 0)) == PLUS
4229 || GET_CODE (XEXP (t, 0)) == MINUS
4230 || GET_CODE (XEXP (t, 0)) == IOR
4231 || GET_CODE (XEXP (t, 0)) == XOR
4232 || GET_CODE (XEXP (t, 0)) == ASHIFT
4233 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4234 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4235 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4236 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4237 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4238 && (num_sign_bit_copies (f, GET_MODE (f))
4239 > (GET_MODE_BITSIZE (mode)
4240 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
4242 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4243 extend_op = SIGN_EXTEND;
4244 m = GET_MODE (XEXP (t, 0));
4246 else if (GET_CODE (t) == SIGN_EXTEND
4247 && (GET_CODE (XEXP (t, 0)) == PLUS
4248 || GET_CODE (XEXP (t, 0)) == IOR
4249 || GET_CODE (XEXP (t, 0)) == XOR)
4250 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4251 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4252 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4253 && (num_sign_bit_copies (f, GET_MODE (f))
4254 > (GET_MODE_BITSIZE (mode)
4255 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
4257 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4258 extend_op = SIGN_EXTEND;
4259 m = GET_MODE (XEXP (t, 0));
4261 else if (GET_CODE (t) == ZERO_EXTEND
4262 && (GET_CODE (XEXP (t, 0)) == PLUS
4263 || GET_CODE (XEXP (t, 0)) == MINUS
4264 || GET_CODE (XEXP (t, 0)) == IOR
4265 || GET_CODE (XEXP (t, 0)) == XOR
4266 || GET_CODE (XEXP (t, 0)) == ASHIFT
4267 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4268 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4269 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4270 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4271 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4272 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4273 && ((nonzero_bits (f, GET_MODE (f))
4274 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
4277 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4278 extend_op = ZERO_EXTEND;
4279 m = GET_MODE (XEXP (t, 0));
4281 else if (GET_CODE (t) == ZERO_EXTEND
4282 && (GET_CODE (XEXP (t, 0)) == PLUS
4283 || GET_CODE (XEXP (t, 0)) == IOR
4284 || GET_CODE (XEXP (t, 0)) == XOR)
4285 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4286 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4287 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4288 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4289 && ((nonzero_bits (f, GET_MODE (f))
4290 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
4293 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4294 extend_op = ZERO_EXTEND;
4295 m = GET_MODE (XEXP (t, 0));
4300 temp = subst (gen_binary (true_code, m, cond_op0, cond_op1),
4301 pc_rtx, pc_rtx, 0, 0);
4302 temp = gen_binary (MULT, m, temp,
4303 gen_binary (MULT, m, c1, const_true_rtx));
4304 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
4305 temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp);
4307 if (extend_op != NIL)
4308 temp = gen_unary (extend_op, mode, m, temp);
4315 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4316 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4317 negation of a single bit, we can convert this operation to a shift. We
4318 can actually do this more generally, but it doesn't seem worth it. */
4320 if (true_code == NE && XEXP (cond, 1) == const0_rtx
4321 && false == const0_rtx && GET_CODE (true) == CONST_INT
4322 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
4323 && (i = exact_log2 (INTVAL (true))) >= 0)
4324 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
4325 == GET_MODE_BITSIZE (mode))
4326 && (i = exact_log2 (- INTVAL (true))) >= 0)))
4328 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4329 gen_lowpart_for_combine (mode, XEXP (cond, 0)), i);
4334 /* Simplify X, a SET expression. Return the new expression. */
4340 rtx src = SET_SRC (x);
4341 rtx dest = SET_DEST (x);
4342 enum machine_mode mode
4343 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
4347 /* (set (pc) (return)) gets written as (return). */
4348 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
4351 /* Now that we know for sure which bits of SRC we are using, see if we can
4352 simplify the expression for the object knowing that we only need the
4355 if (GET_MODE_CLASS (mode) == MODE_INT)
4356 src = force_to_mode (src, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
4358 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4359 the comparison result and try to simplify it unless we already have used
4360 undobuf.other_insn. */
4361 if ((GET_CODE (src) == COMPARE
4366 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
4367 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
4368 && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
4369 && rtx_equal_p (XEXP (*cc_use, 0), dest))
4371 enum rtx_code old_code = GET_CODE (*cc_use);
4372 enum rtx_code new_code;
4374 int other_changed = 0;
4375 enum machine_mode compare_mode = GET_MODE (dest);
4377 if (GET_CODE (src) == COMPARE)
4378 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
4380 op0 = src, op1 = const0_rtx;
4382 /* Simplify our comparison, if possible. */
4383 new_code = simplify_comparison (old_code, &op0, &op1);
4385 #ifdef EXTRA_CC_MODES
4386 /* If this machine has CC modes other than CCmode, check to see if we
4387 need to use a different CC mode here. */
4388 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
4389 #endif /* EXTRA_CC_MODES */
4391 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
4392 /* If the mode changed, we have to change SET_DEST, the mode in the
4393 compare, and the mode in the place SET_DEST is used. If SET_DEST is
4394 a hard register, just build new versions with the proper mode. If it
4395 is a pseudo, we lose unless it is only time we set the pseudo, in
4396 which case we can safely change its mode. */
4397 if (compare_mode != GET_MODE (dest))
4399 int regno = REGNO (dest);
4400 rtx new_dest = gen_rtx (REG, compare_mode, regno);
4402 if (regno < FIRST_PSEUDO_REGISTER
4403 || (reg_n_sets[regno] == 1 && ! REG_USERVAR_P (dest)))
4405 if (regno >= FIRST_PSEUDO_REGISTER)
4406 SUBST (regno_reg_rtx[regno], new_dest);
4408 SUBST (SET_DEST (x), new_dest);
4409 SUBST (XEXP (*cc_use, 0), new_dest);
4417 /* If the code changed, we have to build a new comparison in
4418 undobuf.other_insn. */
4419 if (new_code != old_code)
4421 unsigned HOST_WIDE_INT mask;
4423 SUBST (*cc_use, gen_rtx_combine (new_code, GET_MODE (*cc_use),
4426 /* If the only change we made was to change an EQ into an NE or
4427 vice versa, OP0 has only one bit that might be nonzero, and OP1
4428 is zero, check if changing the user of the condition code will
4429 produce a valid insn. If it won't, we can keep the original code
4430 in that insn by surrounding our operation with an XOR. */
4432 if (((old_code == NE && new_code == EQ)
4433 || (old_code == EQ && new_code == NE))
4434 && ! other_changed && op1 == const0_rtx
4435 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
4436 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
4438 rtx pat = PATTERN (other_insn), note = 0;
4441 if ((recog_for_combine (&pat, other_insn, ¬e, &scratches) < 0
4442 && ! check_asm_operands (pat)))
4444 PUT_CODE (*cc_use, old_code);
4447 op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask));
4455 undobuf.other_insn = other_insn;
4458 /* If we are now comparing against zero, change our source if
4459 needed. If we do not use cc0, we always have a COMPARE. */
4460 if (op1 == const0_rtx && dest == cc0_rtx)
4462 SUBST (SET_SRC (x), op0);
4468 /* Otherwise, if we didn't previously have a COMPARE in the
4469 correct mode, we need one. */
4470 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
4473 gen_rtx_combine (COMPARE, compare_mode, op0, op1));
4478 /* Otherwise, update the COMPARE if needed. */
4479 SUBST (XEXP (src, 0), op0);
4480 SUBST (XEXP (src, 1), op1);
4485 /* Get SET_SRC in a form where we have placed back any
4486 compound expressions. Then do the checks below. */
4487 src = make_compound_operation (src, SET);
4488 SUBST (SET_SRC (x), src);
4491 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
4492 and X being a REG or (subreg (reg)), we may be able to convert this to
4493 (set (subreg:m2 x) (op)).
4495 We can always do this if M1 is narrower than M2 because that means that
4496 we only care about the low bits of the result.
4498 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
4499 perform a narrower operation that requested since the high-order bits will
4500 be undefined. On machine where it is defined, this transformation is safe
4501 as long as M1 and M2 have the same number of words. */
4503 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
4504 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src))) != 'o'
4505 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
4507 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
4508 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
4509 #ifndef WORD_REGISTER_OPERATIONS
4510 && (GET_MODE_SIZE (GET_MODE (src))
4511 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
4513 #ifdef CLASS_CANNOT_CHANGE_SIZE
4514 && ! (GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER
4515 && (TEST_HARD_REG_BIT
4516 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE],
4518 && (GET_MODE_SIZE (GET_MODE (src))
4519 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))))
4521 && (GET_CODE (dest) == REG
4522 || (GET_CODE (dest) == SUBREG
4523 && GET_CODE (SUBREG_REG (dest)) == REG)))
4525 SUBST (SET_DEST (x),
4526 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src)),
4528 SUBST (SET_SRC (x), SUBREG_REG (src));
4530 src = SET_SRC (x), dest = SET_DEST (x);
4533 #ifdef LOAD_EXTEND_OP
4534 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
4535 would require a paradoxical subreg. Replace the subreg with a
4536 zero_extend to avoid the reload that would otherwise be required. */
4538 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
4539 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL
4540 && SUBREG_WORD (src) == 0
4541 && (GET_MODE_SIZE (GET_MODE (src))
4542 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
4543 && GET_CODE (SUBREG_REG (src)) == MEM)
4546 gen_rtx_combine (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
4547 GET_MODE (src), XEXP (src, 0)));
4553 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
4554 are comparing an item known to be 0 or -1 against 0, use a logical
4555 operation instead. Check for one of the arms being an IOR of the other
4556 arm with some value. We compute three terms to be IOR'ed together. In
4557 practice, at most two will be nonzero. Then we do the IOR's. */
4559 if (GET_CODE (dest) != PC
4560 && GET_CODE (src) == IF_THEN_ELSE
4561 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
4562 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
4563 && XEXP (XEXP (src, 0), 1) == const0_rtx
4564 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
4565 #ifdef HAVE_conditional_move
4566 && ! can_conditionally_move_p (GET_MODE (src))
4568 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
4569 GET_MODE (XEXP (XEXP (src, 0), 0)))
4570 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
4571 && ! side_effects_p (src))
4573 rtx true = (GET_CODE (XEXP (src, 0)) == NE
4574 ? XEXP (src, 1) : XEXP (src, 2));
4575 rtx false = (GET_CODE (XEXP (src, 0)) == NE
4576 ? XEXP (src, 2) : XEXP (src, 1));
4577 rtx term1 = const0_rtx, term2, term3;
4579 if (GET_CODE (true) == IOR && rtx_equal_p (XEXP (true, 0), false))
4580 term1 = false, true = XEXP (true, 1), false = const0_rtx;
4581 else if (GET_CODE (true) == IOR
4582 && rtx_equal_p (XEXP (true, 1), false))
4583 term1 = false, true = XEXP (true, 0), false = const0_rtx;
4584 else if (GET_CODE (false) == IOR
4585 && rtx_equal_p (XEXP (false, 0), true))
4586 term1 = true, false = XEXP (false, 1), true = const0_rtx;
4587 else if (GET_CODE (false) == IOR
4588 && rtx_equal_p (XEXP (false, 1), true))
4589 term1 = true, false = XEXP (false, 0), true = const0_rtx;
4591 term2 = gen_binary (AND, GET_MODE (src), XEXP (XEXP (src, 0), 0), true);
4592 term3 = gen_binary (AND, GET_MODE (src),
4593 gen_unary (NOT, GET_MODE (src), GET_MODE (src),
4594 XEXP (XEXP (src, 0), 0)),
4598 gen_binary (IOR, GET_MODE (src),
4599 gen_binary (IOR, GET_MODE (src), term1, term2),
4605 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
4606 whole thing fail. */
4607 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
4609 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
4612 /* Convert this into a field assignment operation, if possible. */
4613 return make_field_assignment (x);
4616 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
4617 result. LAST is nonzero if this is the last retry. */
4620 simplify_logical (x, last)
4624 enum machine_mode mode = GET_MODE (x);
4625 rtx op0 = XEXP (x, 0);
4626 rtx op1 = XEXP (x, 1);
4628 switch (GET_CODE (x))
4631 /* Convert (A ^ B) & A to A & (~ B) since the latter is often a single
4632 insn (and may simplify more). */
4633 if (GET_CODE (op0) == XOR
4634 && rtx_equal_p (XEXP (op0, 0), op1)
4635 && ! side_effects_p (op1))
4636 x = gen_binary (AND, mode,
4637 gen_unary (NOT, mode, mode, XEXP (op0, 1)), op1);
4639 if (GET_CODE (op0) == XOR
4640 && rtx_equal_p (XEXP (op0, 1), op1)
4641 && ! side_effects_p (op1))
4642 x = gen_binary (AND, mode,
4643 gen_unary (NOT, mode, mode, XEXP (op0, 0)), op1);
4645 /* Similarly for (~ (A ^ B)) & A. */
4646 if (GET_CODE (op0) == NOT
4647 && GET_CODE (XEXP (op0, 0)) == XOR
4648 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
4649 && ! side_effects_p (op1))
4650 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
4652 if (GET_CODE (op0) == NOT
4653 && GET_CODE (XEXP (op0, 0)) == XOR
4654 && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
4655 && ! side_effects_p (op1))
4656 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
4658 if (GET_CODE (op1) == CONST_INT)
4660 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
4662 /* If we have (ior (and (X C1) C2)) and the next restart would be
4663 the last, simplify this by making C1 as small as possible
4666 && GET_CODE (x) == IOR && GET_CODE (op0) == AND
4667 && GET_CODE (XEXP (op0, 1)) == CONST_INT
4668 && GET_CODE (op1) == CONST_INT)
4669 return gen_binary (IOR, mode,
4670 gen_binary (AND, mode, XEXP (op0, 0),
4671 GEN_INT (INTVAL (XEXP (op0, 1))
4672 & ~ INTVAL (op1))), op1);
4674 if (GET_CODE (x) != AND)
4677 if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
4678 || GET_RTX_CLASS (GET_CODE (x)) == '2')
4679 op0 = XEXP (x, 0), op1 = XEXP (x, 1);
4682 /* Convert (A | B) & A to A. */
4683 if (GET_CODE (op0) == IOR
4684 && (rtx_equal_p (XEXP (op0, 0), op1)
4685 || rtx_equal_p (XEXP (op0, 1), op1))
4686 && ! side_effects_p (XEXP (op0, 0))
4687 && ! side_effects_p (XEXP (op0, 1)))
4690 /* In the following group of tests (and those in case IOR below),
4691 we start with some combination of logical operations and apply
4692 the distributive law followed by the inverse distributive law.
4693 Most of the time, this results in no change. However, if some of
4694 the operands are the same or inverses of each other, simplifications
4697 For example, (and (ior A B) (not B)) can occur as the result of
4698 expanding a bit field assignment. When we apply the distributive
4699 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
4700 which then simplifies to (and (A (not B))).
4702 If we have (and (ior A B) C), apply the distributive law and then
4703 the inverse distributive law to see if things simplify. */
4705 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
4707 x = apply_distributive_law
4708 (gen_binary (GET_CODE (op0), mode,
4709 gen_binary (AND, mode, XEXP (op0, 0), op1),
4710 gen_binary (AND, mode, XEXP (op0, 1), op1)));
4711 if (GET_CODE (x) != AND)
4715 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
4716 return apply_distributive_law
4717 (gen_binary (GET_CODE (op1), mode,
4718 gen_binary (AND, mode, XEXP (op1, 0), op0),
4719 gen_binary (AND, mode, XEXP (op1, 1), op0)));
4721 /* Similarly, taking advantage of the fact that
4722 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
4724 if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR)
4725 return apply_distributive_law
4726 (gen_binary (XOR, mode,
4727 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)),
4728 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 1))));
4730 else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR)
4731 return apply_distributive_law
4732 (gen_binary (XOR, mode,
4733 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)),
4734 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 1))));
4738 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
4739 if (GET_CODE (op1) == CONST_INT
4740 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4741 && (nonzero_bits (op0, mode) & ~ INTVAL (op1)) == 0)
4744 /* Convert (A & B) | A to A. */
4745 if (GET_CODE (op0) == AND
4746 && (rtx_equal_p (XEXP (op0, 0), op1)
4747 || rtx_equal_p (XEXP (op0, 1), op1))
4748 && ! side_effects_p (XEXP (op0, 0))
4749 && ! side_effects_p (XEXP (op0, 1)))
4752 /* If we have (ior (and A B) C), apply the distributive law and then
4753 the inverse distributive law to see if things simplify. */
4755 if (GET_CODE (op0) == AND)
4757 x = apply_distributive_law
4758 (gen_binary (AND, mode,
4759 gen_binary (IOR, mode, XEXP (op0, 0), op1),
4760 gen_binary (IOR, mode, XEXP (op0, 1), op1)));
4762 if (GET_CODE (x) != IOR)
4766 if (GET_CODE (op1) == AND)
4768 x = apply_distributive_law
4769 (gen_binary (AND, mode,
4770 gen_binary (IOR, mode, XEXP (op1, 0), op0),
4771 gen_binary (IOR, mode, XEXP (op1, 1), op0)));
4773 if (GET_CODE (x) != IOR)
4777 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
4778 mode size to (rotate A CX). */
4780 if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
4781 || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
4782 && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
4783 && GET_CODE (XEXP (op0, 1)) == CONST_INT
4784 && GET_CODE (XEXP (op1, 1)) == CONST_INT
4785 && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
4786 == GET_MODE_BITSIZE (mode)))
4787 return gen_rtx (ROTATE, mode, XEXP (op0, 0),
4788 (GET_CODE (op0) == ASHIFT
4789 ? XEXP (op0, 1) : XEXP (op1, 1)));
4791 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
4792 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
4793 does not affect any of the bits in OP1, it can really be done
4794 as a PLUS and we can associate. We do this by seeing if OP1
4795 can be safely shifted left C bits. */
4796 if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
4797 && GET_CODE (XEXP (op0, 0)) == PLUS
4798 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
4799 && GET_CODE (XEXP (op0, 1)) == CONST_INT
4800 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
4802 int count = INTVAL (XEXP (op0, 1));
4803 HOST_WIDE_INT mask = INTVAL (op1) << count;
4805 if (mask >> count == INTVAL (op1)
4806 && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
4808 SUBST (XEXP (XEXP (op0, 0), 1),
4809 GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
4816 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
4817 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
4820 int num_negated = 0;
4822 if (GET_CODE (op0) == NOT)
4823 num_negated++, op0 = XEXP (op0, 0);
4824 if (GET_CODE (op1) == NOT)
4825 num_negated++, op1 = XEXP (op1, 0);
4827 if (num_negated == 2)
4829 SUBST (XEXP (x, 0), op0);
4830 SUBST (XEXP (x, 1), op1);
4832 else if (num_negated == 1)
4833 return gen_unary (NOT, mode, mode, gen_binary (XOR, mode, op0, op1));
4836 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
4837 correspond to a machine insn or result in further simplifications
4838 if B is a constant. */
4840 if (GET_CODE (op0) == AND
4841 && rtx_equal_p (XEXP (op0, 1), op1)
4842 && ! side_effects_p (op1))
4843 return gen_binary (AND, mode,
4844 gen_unary (NOT, mode, mode, XEXP (op0, 0)),
4847 else if (GET_CODE (op0) == AND
4848 && rtx_equal_p (XEXP (op0, 0), op1)
4849 && ! side_effects_p (op1))
4850 return gen_binary (AND, mode,
4851 gen_unary (NOT, mode, mode, XEXP (op0, 1)),
4854 #if STORE_FLAG_VALUE == 1
4855 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
4857 if (op1 == const1_rtx
4858 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
4859 && reversible_comparison_p (op0))
4860 return gen_rtx_combine (reverse_condition (GET_CODE (op0)),
4861 mode, XEXP (op0, 0), XEXP (op0, 1));
4863 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
4864 is (lt foo (const_int 0)), so we can perform the above
4867 if (op1 == const1_rtx
4868 && GET_CODE (op0) == LSHIFTRT
4869 && GET_CODE (XEXP (op0, 1)) == CONST_INT
4870 && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
4871 return gen_rtx_combine (GE, mode, XEXP (op0, 0), const0_rtx);
4874 /* (xor (comparison foo bar) (const_int sign-bit))
4875 when STORE_FLAG_VALUE is the sign bit. */
4876 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4877 && (STORE_FLAG_VALUE
4878 == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
4879 && op1 == const_true_rtx
4880 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
4881 && reversible_comparison_p (op0))
4882 return gen_rtx_combine (reverse_condition (GET_CODE (op0)),
4883 mode, XEXP (op0, 0), XEXP (op0, 1));
4890 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
4891 operations" because they can be replaced with two more basic operations.
4892 ZERO_EXTEND is also considered "compound" because it can be replaced with
4893 an AND operation, which is simpler, though only one operation.
4895 The function expand_compound_operation is called with an rtx expression
4896 and will convert it to the appropriate shifts and AND operations,
4897 simplifying at each stage.
4899 The function make_compound_operation is called to convert an expression
4900 consisting of shifts and ANDs into the equivalent compound expression.
4901 It is the inverse of this function, loosely speaking. */
4904 expand_compound_operation (x)
4912 switch (GET_CODE (x))
4917 /* We can't necessarily use a const_int for a multiword mode;
4918 it depends on implicitly extending the value.
4919 Since we don't know the right way to extend it,
4920 we can't tell whether the implicit way is right.
4922 Even for a mode that is no wider than a const_int,
4923 we can't win, because we need to sign extend one of its bits through
4924 the rest of it, and we don't know which bit. */
4925 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
4928 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
4929 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
4930 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
4931 reloaded. If not for that, MEM's would very rarely be safe.
4933 Reject MODEs bigger than a word, because we might not be able
4934 to reference a two-register group starting with an arbitrary register
4935 (and currently gen_lowpart might crash for a SUBREG). */
4937 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
4940 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
4941 /* If the inner object has VOIDmode (the only way this can happen
4942 is if it is a ASM_OPERANDS), we can't do anything since we don't
4943 know how much masking to do. */
4952 /* If the operand is a CLOBBER, just return it. */
4953 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
4956 if (GET_CODE (XEXP (x, 1)) != CONST_INT
4957 || GET_CODE (XEXP (x, 2)) != CONST_INT
4958 || GET_MODE (XEXP (x, 0)) == VOIDmode)
4961 len = INTVAL (XEXP (x, 1));
4962 pos = INTVAL (XEXP (x, 2));
4964 /* If this goes outside the object being extracted, replace the object
4965 with a (use (mem ...)) construct that only combine understands
4966 and is used only for this purpose. */
4967 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
4968 SUBST (XEXP (x, 0), gen_rtx (USE, GET_MODE (x), XEXP (x, 0)));
4970 if (BITS_BIG_ENDIAN)
4971 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
4979 /* We can optimize some special cases of ZERO_EXTEND. */
4980 if (GET_CODE (x) == ZERO_EXTEND)
4982 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
4983 know that the last value didn't have any inappropriate bits
4985 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
4986 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
4987 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
4988 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
4989 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
4990 return XEXP (XEXP (x, 0), 0);
4992 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
4993 if (GET_CODE (XEXP (x, 0)) == SUBREG
4994 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
4995 && subreg_lowpart_p (XEXP (x, 0))
4996 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
4997 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
4998 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))) == 0)
4999 return SUBREG_REG (XEXP (x, 0));
5001 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5002 is a comparison and STORE_FLAG_VALUE permits. This is like
5003 the first case, but it works even when GET_MODE (x) is larger
5004 than HOST_WIDE_INT. */
5005 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5006 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5007 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) == '<'
5008 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5009 <= HOST_BITS_PER_WIDE_INT)
5010 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5011 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5012 return XEXP (XEXP (x, 0), 0);
5014 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5015 if (GET_CODE (XEXP (x, 0)) == SUBREG
5016 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5017 && subreg_lowpart_p (XEXP (x, 0))
5018 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == '<'
5019 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5020 <= HOST_BITS_PER_WIDE_INT)
5021 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5022 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5023 return SUBREG_REG (XEXP (x, 0));
5025 /* If sign extension is cheaper than zero extension, then use it
5026 if we know that no extraneous bits are set, and that the high
5028 if (flag_expensive_optimizations
5029 && ((GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5030 && ((nonzero_bits (XEXP (x, 0), GET_MODE (x))
5031 & ~ (((unsigned HOST_WIDE_INT)
5032 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5035 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
5036 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5037 <= HOST_BITS_PER_WIDE_INT)
5038 && (((HOST_WIDE_INT) STORE_FLAG_VALUE
5039 & ~ (((unsigned HOST_WIDE_INT)
5040 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5044 rtx temp = gen_rtx (SIGN_EXTEND, GET_MODE (x), XEXP (x, 0));
5046 if (rtx_cost (temp, SET) < rtx_cost (x, SET))
5047 return expand_compound_operation (temp);
5051 /* If we reach here, we want to return a pair of shifts. The inner
5052 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5053 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5054 logical depending on the value of UNSIGNEDP.
5056 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5057 converted into an AND of a shift.
5059 We must check for the case where the left shift would have a negative
5060 count. This can happen in a case like (x >> 31) & 255 on machines
5061 that can't shift by a constant. On those machines, we would first
5062 combine the shift with the AND to produce a variable-position
5063 extraction. Then the constant of 31 would be substituted in to produce
5064 a such a position. */
5066 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5067 if (modewidth >= pos - len)
5068 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5070 simplify_shift_const (NULL_RTX, ASHIFT,
5073 modewidth - pos - len),
5076 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5077 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5078 simplify_shift_const (NULL_RTX, LSHIFTRT,
5081 ((HOST_WIDE_INT) 1 << len) - 1);
5083 /* Any other cases we can't handle. */
5087 /* If we couldn't do this for some reason, return the original
5089 if (GET_CODE (tem) == CLOBBER)
5095 /* X is a SET which contains an assignment of one object into
5096 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5097 or certain SUBREGS). If possible, convert it into a series of
5100 We half-heartedly support variable positions, but do not at all
5101 support variable lengths. */
5104 expand_field_assignment (x)
5108 rtx pos; /* Always counts from low bit. */
5111 enum machine_mode compute_mode;
5113 /* Loop until we find something we can't simplify. */
5116 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5117 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5119 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5120 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5121 pos = GEN_INT (BITS_PER_WORD * SUBREG_WORD (XEXP (SET_DEST (x), 0)));
5123 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5124 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5126 inner = XEXP (SET_DEST (x), 0);
5127 len = INTVAL (XEXP (SET_DEST (x), 1));
5128 pos = XEXP (SET_DEST (x), 2);
5130 /* If the position is constant and spans the width of INNER,
5131 surround INNER with a USE to indicate this. */
5132 if (GET_CODE (pos) == CONST_INT
5133 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5134 inner = gen_rtx (USE, GET_MODE (SET_DEST (x)), inner);
5136 if (BITS_BIG_ENDIAN)
5138 if (GET_CODE (pos) == CONST_INT)
5139 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5141 else if (GET_CODE (pos) == MINUS
5142 && GET_CODE (XEXP (pos, 1)) == CONST_INT
5143 && (INTVAL (XEXP (pos, 1))
5144 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5145 /* If position is ADJUST - X, new position is X. */
5146 pos = XEXP (pos, 0);
5148 pos = gen_binary (MINUS, GET_MODE (pos),
5149 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
5155 /* A SUBREG between two modes that occupy the same numbers of words
5156 can be done by moving the SUBREG to the source. */
5157 else if (GET_CODE (SET_DEST (x)) == SUBREG
5158 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5159 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5160 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5161 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5163 x = gen_rtx (SET, VOIDmode, SUBREG_REG (SET_DEST (x)),
5164 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (SET_DEST (x))),
5171 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5172 inner = SUBREG_REG (inner);
5174 compute_mode = GET_MODE (inner);
5176 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5177 if (len < HOST_BITS_PER_WIDE_INT)
5178 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
5182 /* Now compute the equivalent expression. Make a copy of INNER
5183 for the SET_DEST in case it is a MEM into which we will substitute;
5184 we don't want shared RTL in that case. */
5185 x = gen_rtx (SET, VOIDmode, copy_rtx (inner),
5186 gen_binary (IOR, compute_mode,
5187 gen_binary (AND, compute_mode,
5188 gen_unary (NOT, compute_mode,
5194 gen_binary (ASHIFT, compute_mode,
5195 gen_binary (AND, compute_mode,
5196 gen_lowpart_for_combine
5206 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5207 it is an RTX that represents a variable starting position; otherwise,
5208 POS is the (constant) starting bit position (counted from the LSB).
5210 INNER may be a USE. This will occur when we started with a bitfield
5211 that went outside the boundary of the object in memory, which is
5212 allowed on most machines. To isolate this case, we produce a USE
5213 whose mode is wide enough and surround the MEM with it. The only
5214 code that understands the USE is this routine. If it is not removed,
5215 it will cause the resulting insn not to match.
5217 UNSIGNEDP is non-zero for an unsigned reference and zero for a
5220 IN_DEST is non-zero if this is a reference in the destination of a
5221 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
5222 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5225 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
5226 ZERO_EXTRACT should be built even for bits starting at bit 0.
5228 MODE is the desired mode of the result (if IN_DEST == 0).
5230 The result is an RTX for the extraction or NULL_RTX if the target
5234 make_extraction (mode, inner, pos, pos_rtx, len,
5235 unsignedp, in_dest, in_compare)
5236 enum machine_mode mode;
5242 int in_dest, in_compare;
5244 /* This mode describes the size of the storage area
5245 to fetch the overall value from. Within that, we
5246 ignore the POS lowest bits, etc. */
5247 enum machine_mode is_mode = GET_MODE (inner);
5248 enum machine_mode inner_mode;
5249 enum machine_mode wanted_inner_mode = byte_mode;
5250 enum machine_mode wanted_inner_reg_mode = word_mode;
5251 enum machine_mode pos_mode = word_mode;
5252 enum machine_mode extraction_mode = word_mode;
5253 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
5256 rtx orig_pos_rtx = pos_rtx;
5259 /* Get some information about INNER and get the innermost object. */
5260 if (GET_CODE (inner) == USE)
5261 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
5262 /* We don't need to adjust the position because we set up the USE
5263 to pretend that it was a full-word object. */
5264 spans_byte = 1, inner = XEXP (inner, 0);
5265 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5267 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5268 consider just the QI as the memory to extract from.
5269 The subreg adds or removes high bits; its mode is
5270 irrelevant to the meaning of this extraction,
5271 since POS and LEN count from the lsb. */
5272 if (GET_CODE (SUBREG_REG (inner)) == MEM)
5273 is_mode = GET_MODE (SUBREG_REG (inner));
5274 inner = SUBREG_REG (inner);
5277 inner_mode = GET_MODE (inner);
5279 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
5280 pos = INTVAL (pos_rtx), pos_rtx = 0;
5282 /* See if this can be done without an extraction. We never can if the
5283 width of the field is not the same as that of some integer mode. For
5284 registers, we can only avoid the extraction if the position is at the
5285 low-order bit and this is either not in the destination or we have the
5286 appropriate STRICT_LOW_PART operation available.
5288 For MEM, we can avoid an extract if the field starts on an appropriate
5289 boundary and we can change the mode of the memory reference. However,
5290 we cannot directly access the MEM if we have a USE and the underlying
5291 MEM is not TMODE. This combination means that MEM was being used in a
5292 context where bits outside its mode were being referenced; that is only
5293 valid in bit-field insns. */
5295 if (tmode != BLKmode
5296 && ! (spans_byte && inner_mode != tmode)
5297 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
5298 && GET_CODE (inner) != MEM
5300 || (GET_CODE (inner) == REG
5301 && (movstrict_optab->handlers[(int) tmode].insn_code
5302 != CODE_FOR_nothing))))
5303 || (GET_CODE (inner) == MEM && pos_rtx == 0
5305 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
5306 : BITS_PER_UNIT)) == 0
5307 /* We can't do this if we are widening INNER_MODE (it
5308 may not be aligned, for one thing). */
5309 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
5310 && (inner_mode == tmode
5311 || (! mode_dependent_address_p (XEXP (inner, 0))
5312 && ! MEM_VOLATILE_P (inner))))))
5314 /* If INNER is a MEM, make a new MEM that encompasses just the desired
5315 field. If the original and current mode are the same, we need not
5316 adjust the offset. Otherwise, we do if bytes big endian.
5318 If INNER is not a MEM, get a piece consisting of just the field
5319 of interest (in this case POS % BITS_PER_WORD must be 0). */
5321 if (GET_CODE (inner) == MEM)
5324 /* POS counts from lsb, but make OFFSET count in memory order. */
5325 if (BYTES_BIG_ENDIAN)
5326 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
5328 offset = pos / BITS_PER_UNIT;
5330 new = gen_rtx (MEM, tmode, plus_constant (XEXP (inner, 0), offset));
5331 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (inner);
5332 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (inner);
5333 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (inner);
5335 else if (GET_CODE (inner) == REG)
5337 /* We can't call gen_lowpart_for_combine here since we always want
5338 a SUBREG and it would sometimes return a new hard register. */
5339 if (tmode != inner_mode)
5340 new = gen_rtx (SUBREG, tmode, inner,
5342 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD
5343 ? (((GET_MODE_SIZE (inner_mode)
5344 - GET_MODE_SIZE (tmode))
5346 - pos / BITS_PER_WORD)
5347 : pos / BITS_PER_WORD));
5352 new = force_to_mode (inner, tmode,
5353 len >= HOST_BITS_PER_WIDE_INT
5354 ? GET_MODE_MASK (tmode)
5355 : ((HOST_WIDE_INT) 1 << len) - 1,
5358 /* If this extraction is going into the destination of a SET,
5359 make a STRICT_LOW_PART unless we made a MEM. */
5362 return (GET_CODE (new) == MEM ? new
5363 : (GET_CODE (new) != SUBREG
5364 ? gen_rtx (CLOBBER, tmode, const0_rtx)
5365 : gen_rtx_combine (STRICT_LOW_PART, VOIDmode, new)));
5367 /* Otherwise, sign- or zero-extend unless we already are in the
5370 return (mode == tmode ? new
5371 : gen_rtx_combine (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
5375 /* Unless this is a COMPARE or we have a funny memory reference,
5376 don't do anything with zero-extending field extracts starting at
5377 the low-order bit since they are simple AND operations. */
5378 if (pos_rtx == 0 && pos == 0 && ! in_dest
5379 && ! in_compare && ! spans_byte && unsignedp)
5382 /* Unless we are allowed to span bytes, reject this if we would be
5383 spanning bytes or if the position is not a constant and the length
5384 is not 1. In all other cases, we would only be going outside
5385 out object in cases when an original shift would have been
5388 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
5389 || (pos_rtx != 0 && len != 1)))
5392 /* Get the mode to use should INNER not be a MEM, the mode for the position,
5393 and the mode for the result. */
5397 wanted_inner_reg_mode = insn_operand_mode[(int) CODE_FOR_insv][0];
5398 pos_mode = insn_operand_mode[(int) CODE_FOR_insv][2];
5399 extraction_mode = insn_operand_mode[(int) CODE_FOR_insv][3];
5404 if (! in_dest && unsignedp)
5406 wanted_inner_reg_mode = insn_operand_mode[(int) CODE_FOR_extzv][1];
5407 pos_mode = insn_operand_mode[(int) CODE_FOR_extzv][3];
5408 extraction_mode = insn_operand_mode[(int) CODE_FOR_extzv][0];
5413 if (! in_dest && ! unsignedp)
5415 wanted_inner_reg_mode = insn_operand_mode[(int) CODE_FOR_extv][1];
5416 pos_mode = insn_operand_mode[(int) CODE_FOR_extv][3];
5417 extraction_mode = insn_operand_mode[(int) CODE_FOR_extv][0];
5421 /* Never narrow an object, since that might not be safe. */
5423 if (mode != VOIDmode
5424 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
5425 extraction_mode = mode;
5427 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
5428 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
5429 pos_mode = GET_MODE (pos_rtx);
5431 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
5432 if we have to change the mode of memory and cannot, the desired mode is
5434 if (GET_CODE (inner) != MEM)
5435 wanted_inner_mode = wanted_inner_reg_mode;
5436 else if (inner_mode != wanted_inner_mode
5437 && (mode_dependent_address_p (XEXP (inner, 0))
5438 || MEM_VOLATILE_P (inner)))
5439 wanted_inner_mode = extraction_mode;
5443 if (BITS_BIG_ENDIAN)
5445 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
5446 BITS_BIG_ENDIAN style. If position is constant, compute new
5447 position. Otherwise, build subtraction.
5448 Note that POS is relative to the mode of the original argument.
5449 If it's a MEM we need to recompute POS relative to that.
5450 However, if we're extracting from (or inserting into) a register,
5451 we want to recompute POS relative to wanted_inner_mode. */
5452 int width = (GET_CODE (inner) == MEM
5453 ? GET_MODE_BITSIZE (is_mode)
5454 : GET_MODE_BITSIZE (wanted_inner_mode));
5457 pos = width - len - pos;
5460 = gen_rtx_combine (MINUS, GET_MODE (pos_rtx),
5461 GEN_INT (width - len), pos_rtx);
5462 /* POS may be less than 0 now, but we check for that below.
5463 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
5466 /* If INNER has a wider mode, make it smaller. If this is a constant
5467 extract, try to adjust the byte to point to the byte containing
5469 if (wanted_inner_mode != VOIDmode
5470 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
5471 && ((GET_CODE (inner) == MEM
5472 && (inner_mode == wanted_inner_mode
5473 || (! mode_dependent_address_p (XEXP (inner, 0))
5474 && ! MEM_VOLATILE_P (inner))))))
5478 /* The computations below will be correct if the machine is big
5479 endian in both bits and bytes or little endian in bits and bytes.
5480 If it is mixed, we must adjust. */
5482 /* If bytes are big endian and we had a paradoxical SUBREG, we must
5483 adjust OFFSET to compensate. */
5484 if (BYTES_BIG_ENDIAN
5486 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
5487 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
5489 /* If this is a constant position, we can move to the desired byte. */
5492 offset += pos / BITS_PER_UNIT;
5493 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
5496 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
5498 && is_mode != wanted_inner_mode)
5499 offset = (GET_MODE_SIZE (is_mode)
5500 - GET_MODE_SIZE (wanted_inner_mode) - offset);
5502 if (offset != 0 || inner_mode != wanted_inner_mode)
5504 rtx newmem = gen_rtx (MEM, wanted_inner_mode,
5505 plus_constant (XEXP (inner, 0), offset));
5506 RTX_UNCHANGING_P (newmem) = RTX_UNCHANGING_P (inner);
5507 MEM_VOLATILE_P (newmem) = MEM_VOLATILE_P (inner);
5508 MEM_IN_STRUCT_P (newmem) = MEM_IN_STRUCT_P (inner);
5513 /* If INNER is not memory, we can always get it into the proper mode. If we
5514 are changing its mode, POS must be a constant and smaller than the size
5516 else if (GET_CODE (inner) != MEM)
5518 if (GET_MODE (inner) != wanted_inner_mode
5520 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
5523 inner = force_to_mode (inner, wanted_inner_mode,
5525 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
5526 ? GET_MODE_MASK (wanted_inner_mode)
5527 : (((HOST_WIDE_INT) 1 << len) - 1) << orig_pos,
5531 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
5532 have to zero extend. Otherwise, we can just use a SUBREG. */
5534 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
5535 pos_rtx = gen_rtx_combine (ZERO_EXTEND, pos_mode, pos_rtx);
5536 else if (pos_rtx != 0
5537 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
5538 pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
5540 /* Make POS_RTX unless we already have it and it is correct. If we don't
5541 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
5543 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
5544 pos_rtx = orig_pos_rtx;
5546 else if (pos_rtx == 0)
5547 pos_rtx = GEN_INT (pos);
5549 /* Make the required operation. See if we can use existing rtx. */
5550 new = gen_rtx_combine (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
5551 extraction_mode, inner, GEN_INT (len), pos_rtx);
5553 new = gen_lowpart_for_combine (mode, new);
5558 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
5559 with any other operations in X. Return X without that shift if so. */
5562 extract_left_shift (x, count)
5566 enum rtx_code code = GET_CODE (x);
5567 enum machine_mode mode = GET_MODE (x);
5573 /* This is the shift itself. If it is wide enough, we will return
5574 either the value being shifted if the shift count is equal to
5575 COUNT or a shift for the difference. */
5576 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5577 && INTVAL (XEXP (x, 1)) >= count)
5578 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
5579 INTVAL (XEXP (x, 1)) - count);
5583 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
5584 return gen_unary (code, mode, mode, tem);
5588 case PLUS: case IOR: case XOR: case AND:
5589 /* If we can safely shift this constant and we find the inner shift,
5590 make a new operation. */
5591 if (GET_CODE (XEXP (x,1)) == CONST_INT
5592 && (INTVAL (XEXP (x, 1)) & (((HOST_WIDE_INT) 1 << count)) - 1) == 0
5593 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
5594 return gen_binary (code, mode, tem,
5595 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
5603 /* Look at the expression rooted at X. Look for expressions
5604 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
5605 Form these expressions.
5607 Return the new rtx, usually just X.
5609 Also, for machines like the Vax that don't have logical shift insns,
5610 try to convert logical to arithmetic shift operations in cases where
5611 they are equivalent. This undoes the canonicalizations to logical
5612 shifts done elsewhere.
5614 We try, as much as possible, to re-use rtl expressions to save memory.
5616 IN_CODE says what kind of expression we are processing. Normally, it is
5617 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
5618 being kludges), it is MEM. When processing the arguments of a comparison
5619 or a COMPARE against zero, it is COMPARE. */
5622 make_compound_operation (x, in_code)
5624 enum rtx_code in_code;
5626 enum rtx_code code = GET_CODE (x);
5627 enum machine_mode mode = GET_MODE (x);
5628 int mode_width = GET_MODE_BITSIZE (mode);
5630 enum rtx_code next_code;
5636 /* Select the code to be used in recursive calls. Once we are inside an
5637 address, we stay there. If we have a comparison, set to COMPARE,
5638 but once inside, go back to our default of SET. */
5640 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
5641 : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
5642 && XEXP (x, 1) == const0_rtx) ? COMPARE
5643 : in_code == COMPARE ? SET : in_code);
5645 /* Process depending on the code of this operation. If NEW is set
5646 non-zero, it will be returned. */
5651 /* Convert shifts by constants into multiplications if inside
5653 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
5654 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
5655 && INTVAL (XEXP (x, 1)) >= 0)
5657 new = make_compound_operation (XEXP (x, 0), next_code);
5658 new = gen_rtx_combine (MULT, mode, new,
5659 GEN_INT ((HOST_WIDE_INT) 1
5660 << INTVAL (XEXP (x, 1))));
5665 /* If the second operand is not a constant, we can't do anything
5667 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
5670 /* If the constant is a power of two minus one and the first operand
5671 is a logical right shift, make an extraction. */
5672 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
5673 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5675 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
5676 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
5677 0, in_code == COMPARE);
5680 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
5681 else if (GET_CODE (XEXP (x, 0)) == SUBREG
5682 && subreg_lowpart_p (XEXP (x, 0))
5683 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
5684 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5686 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
5688 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
5689 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
5690 0, in_code == COMPARE);
5692 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
5693 else if ((GET_CODE (XEXP (x, 0)) == XOR
5694 || GET_CODE (XEXP (x, 0)) == IOR)
5695 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
5696 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
5697 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5699 /* Apply the distributive law, and then try to make extractions. */
5700 new = gen_rtx_combine (GET_CODE (XEXP (x, 0)), mode,
5701 gen_rtx (AND, mode, XEXP (XEXP (x, 0), 0),
5703 gen_rtx (AND, mode, XEXP (XEXP (x, 0), 1),
5705 new = make_compound_operation (new, in_code);
5708 /* If we are have (and (rotate X C) M) and C is larger than the number
5709 of bits in M, this is an extraction. */
5711 else if (GET_CODE (XEXP (x, 0)) == ROTATE
5712 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5713 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
5714 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
5716 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
5717 new = make_extraction (mode, new,
5718 (GET_MODE_BITSIZE (mode)
5719 - INTVAL (XEXP (XEXP (x, 0), 1))),
5720 NULL_RTX, i, 1, 0, in_code == COMPARE);
5723 /* On machines without logical shifts, if the operand of the AND is
5724 a logical shift and our mask turns off all the propagated sign
5725 bits, we can replace the logical shift with an arithmetic shift. */
5726 else if (ashr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
5727 && (lshr_optab->handlers[(int) mode].insn_code
5728 == CODE_FOR_nothing)
5729 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
5730 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5731 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
5732 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
5733 && mode_width <= HOST_BITS_PER_WIDE_INT)
5735 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
5737 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
5738 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
5740 gen_rtx_combine (ASHIFTRT, mode,
5741 make_compound_operation (XEXP (XEXP (x, 0), 0),
5743 XEXP (XEXP (x, 0), 1)));
5746 /* If the constant is one less than a power of two, this might be
5747 representable by an extraction even if no shift is present.
5748 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
5749 we are in a COMPARE. */
5750 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5751 new = make_extraction (mode,
5752 make_compound_operation (XEXP (x, 0),
5754 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
5756 /* If we are in a comparison and this is an AND with a power of two,
5757 convert this into the appropriate bit extract. */
5758 else if (in_code == COMPARE
5759 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
5760 new = make_extraction (mode,
5761 make_compound_operation (XEXP (x, 0),
5763 i, NULL_RTX, 1, 1, 0, 1);
5768 /* If the sign bit is known to be zero, replace this with an
5769 arithmetic shift. */
5770 if (ashr_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing
5771 && lshr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
5772 && mode_width <= HOST_BITS_PER_WIDE_INT
5773 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
5775 new = gen_rtx_combine (ASHIFTRT, mode,
5776 make_compound_operation (XEXP (x, 0),
5782 /* ... fall through ... */
5788 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
5789 this is a SIGN_EXTRACT. */
5790 if (GET_CODE (rhs) == CONST_INT
5791 && GET_CODE (lhs) == ASHIFT
5792 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
5793 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
5795 new = make_compound_operation (XEXP (lhs, 0), next_code);
5796 new = make_extraction (mode, new,
5797 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
5798 NULL_RTX, mode_width - INTVAL (rhs),
5799 code == LSHIFTRT, 0, in_code == COMPARE);
5802 /* See if we have operations between an ASHIFTRT and an ASHIFT.
5803 If so, try to merge the shifts into a SIGN_EXTEND. We could
5804 also do this for some cases of SIGN_EXTRACT, but it doesn't
5805 seem worth the effort; the case checked for occurs on Alpha. */
5807 if (GET_RTX_CLASS (GET_CODE (lhs)) != 'o'
5808 && ! (GET_CODE (lhs) == SUBREG
5809 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs))) == 'o'))
5810 && GET_CODE (rhs) == CONST_INT
5811 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
5812 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
5813 new = make_extraction (mode, make_compound_operation (new, next_code),
5814 0, NULL_RTX, mode_width - INTVAL (rhs),
5815 code == LSHIFTRT, 0, in_code == COMPARE);
5820 /* Call ourselves recursively on the inner expression. If we are
5821 narrowing the object and it has a different RTL code from
5822 what it originally did, do this SUBREG as a force_to_mode. */
5824 tem = make_compound_operation (SUBREG_REG (x), in_code);
5825 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
5826 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
5827 && subreg_lowpart_p (x))
5829 rtx newer = force_to_mode (tem, mode,
5830 GET_MODE_MASK (mode), NULL_RTX, 0);
5832 /* If we have something other than a SUBREG, we might have
5833 done an expansion, so rerun outselves. */
5834 if (GET_CODE (newer) != SUBREG)
5835 newer = make_compound_operation (newer, in_code);
5843 x = gen_lowpart_for_combine (mode, new);
5844 code = GET_CODE (x);
5847 /* Now recursively process each operand of this operation. */
5848 fmt = GET_RTX_FORMAT (code);
5849 for (i = 0; i < GET_RTX_LENGTH (code); i++)
5852 new = make_compound_operation (XEXP (x, i), next_code);
5853 SUBST (XEXP (x, i), new);
5859 /* Given M see if it is a value that would select a field of bits
5860 within an item, but not the entire word. Return -1 if not.
5861 Otherwise, return the starting position of the field, where 0 is the
5864 *PLEN is set to the length of the field. */
5867 get_pos_from_mask (m, plen)
5868 unsigned HOST_WIDE_INT m;
5871 /* Get the bit number of the first 1 bit from the right, -1 if none. */
5872 int pos = exact_log2 (m & - m);
5877 /* Now shift off the low-order zero bits and see if we have a power of
5879 *plen = exact_log2 ((m >> pos) + 1);
5887 /* See if X can be simplified knowing that we will only refer to it in
5888 MODE and will only refer to those bits that are nonzero in MASK.
5889 If other bits are being computed or if masking operations are done
5890 that select a superset of the bits in MASK, they can sometimes be
5893 Return a possibly simplified expression, but always convert X to
5894 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
5896 Also, if REG is non-zero and X is a register equal in value to REG,
5899 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
5900 are all off in X. This is used when X will be complemented, by either
5901 NOT, NEG, or XOR. */
5904 force_to_mode (x, mode, mask, reg, just_select)
5906 enum machine_mode mode;
5907 unsigned HOST_WIDE_INT mask;
5911 enum rtx_code code = GET_CODE (x);
5912 int next_select = just_select || code == XOR || code == NOT || code == NEG;
5913 enum machine_mode op_mode;
5914 unsigned HOST_WIDE_INT fuller_mask, nonzero;
5917 /* If this is a CALL, don't do anything. Some of the code below
5918 will do the wrong thing since the mode of a CALL is VOIDmode. */
5922 /* We want to perform the operation is its present mode unless we know
5923 that the operation is valid in MODE, in which case we do the operation
5925 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
5926 && code_to_optab[(int) code] != 0
5927 && (code_to_optab[(int) code]->handlers[(int) mode].insn_code
5928 != CODE_FOR_nothing))
5929 ? mode : GET_MODE (x));
5931 /* It is not valid to do a right-shift in a narrower mode
5932 than the one it came in with. */
5933 if ((code == LSHIFTRT || code == ASHIFTRT)
5934 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
5935 op_mode = GET_MODE (x);
5937 /* Truncate MASK to fit OP_MODE. */
5939 mask &= GET_MODE_MASK (op_mode);
5941 /* When we have an arithmetic operation, or a shift whose count we
5942 do not know, we need to assume that all bit the up to the highest-order
5943 bit in MASK will be needed. This is how we form such a mask. */
5945 fuller_mask = (GET_MODE_BITSIZE (op_mode) >= HOST_BITS_PER_WIDE_INT
5946 ? GET_MODE_MASK (op_mode)
5947 : ((HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1)) - 1);
5949 fuller_mask = ~ (HOST_WIDE_INT) 0;
5951 /* Determine what bits of X are guaranteed to be (non)zero. */
5952 nonzero = nonzero_bits (x, mode);
5954 /* If none of the bits in X are needed, return a zero. */
5955 if (! just_select && (nonzero & mask) == 0)
5958 /* If X is a CONST_INT, return a new one. Do this here since the
5959 test below will fail. */
5960 if (GET_CODE (x) == CONST_INT)
5962 HOST_WIDE_INT cval = INTVAL (x) & mask;
5963 int width = GET_MODE_BITSIZE (mode);
5965 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
5966 number, sign extend it. */
5967 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
5968 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
5969 cval |= (HOST_WIDE_INT) -1 << width;
5971 return GEN_INT (cval);
5974 /* If X is narrower than MODE and we want all the bits in X's mode, just
5975 get X in the proper mode. */
5976 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
5977 && (GET_MODE_MASK (GET_MODE (x)) & ~ mask) == 0)
5978 return gen_lowpart_for_combine (mode, x);
5980 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
5981 MASK are already known to be zero in X, we need not do anything. */
5982 if (GET_MODE (x) == mode && code != SUBREG && (~ mask & nonzero) == 0)
5988 /* If X is a (clobber (const_int)), return it since we know we are
5989 generating something that won't match. */
5993 /* X is a (use (mem ..)) that was made from a bit-field extraction that
5994 spanned the boundary of the MEM. If we are now masking so it is
5995 within that boundary, we don't need the USE any more. */
5996 if (! BITS_BIG_ENDIAN
5997 && (mask & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5998 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6005 x = expand_compound_operation (x);
6006 if (GET_CODE (x) != code)
6007 return force_to_mode (x, mode, mask, reg, next_select);
6011 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
6012 || rtx_equal_p (reg, get_last_value (x))))
6017 if (subreg_lowpart_p (x)
6018 /* We can ignore the effect of this SUBREG if it narrows the mode or
6019 if the constant masks to zero all the bits the mode doesn't
6021 && ((GET_MODE_SIZE (GET_MODE (x))
6022 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6024 & GET_MODE_MASK (GET_MODE (x))
6025 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6026 return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
6030 /* If this is an AND with a constant, convert it into an AND
6031 whose constant is the AND of that constant with MASK. If it
6032 remains an AND of MASK, delete it since it is redundant. */
6034 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6036 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6037 mask & INTVAL (XEXP (x, 1)));
6039 /* If X is still an AND, see if it is an AND with a mask that
6040 is just some low-order bits. If so, and it is MASK, we don't
6043 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6044 && INTVAL (XEXP (x, 1)) == mask)
6047 /* If it remains an AND, try making another AND with the bits
6048 in the mode mask that aren't in MASK turned on. If the
6049 constant in the AND is wide enough, this might make a
6050 cheaper constant. */
6052 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6053 && GET_MODE_MASK (GET_MODE (x)) != mask
6054 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
6056 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6057 | (GET_MODE_MASK (GET_MODE (x)) & ~ mask));
6058 int width = GET_MODE_BITSIZE (GET_MODE (x));
6061 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6062 number, sign extend it. */
6063 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6064 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6065 cval |= (HOST_WIDE_INT) -1 << width;
6067 y = gen_binary (AND, GET_MODE (x), XEXP (x, 0), GEN_INT (cval));
6068 if (rtx_cost (y, SET) < rtx_cost (x, SET))
6078 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6079 low-order bits (as in an alignment operation) and FOO is already
6080 aligned to that boundary, mask C1 to that boundary as well.
6081 This may eliminate that PLUS and, later, the AND. */
6084 int width = GET_MODE_BITSIZE (mode);
6085 unsigned HOST_WIDE_INT smask = mask;
6087 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6088 number, sign extend it. */
6090 if (width < HOST_BITS_PER_WIDE_INT
6091 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6092 smask |= (HOST_WIDE_INT) -1 << width;
6094 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6095 && exact_log2 (- smask) >= 0
6096 && (nonzero_bits (XEXP (x, 0), mode) & ~ mask) == 0
6097 && (INTVAL (XEXP (x, 1)) & ~ mask) != 0)
6098 return force_to_mode (plus_constant (XEXP (x, 0),
6099 INTVAL (XEXP (x, 1)) & mask),
6100 mode, mask, reg, next_select);
6103 /* ... fall through ... */
6107 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6108 most significant bit in MASK since carries from those bits will
6109 affect the bits we are interested in. */
6115 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6116 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6117 operation which may be a bitfield extraction. Ensure that the
6118 constant we form is not wider than the mode of X. */
6120 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6121 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6122 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6123 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6124 && GET_CODE (XEXP (x, 1)) == CONST_INT
6125 && ((INTVAL (XEXP (XEXP (x, 0), 1))
6126 + floor_log2 (INTVAL (XEXP (x, 1))))
6127 < GET_MODE_BITSIZE (GET_MODE (x)))
6128 && (INTVAL (XEXP (x, 1))
6129 & ~ nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
6131 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
6132 << INTVAL (XEXP (XEXP (x, 0), 1)));
6133 temp = gen_binary (GET_CODE (x), GET_MODE (x),
6134 XEXP (XEXP (x, 0), 0), temp);
6135 x = gen_binary (LSHIFTRT, GET_MODE (x), temp,
6136 XEXP (XEXP (x, 0), 1));
6137 return force_to_mode (x, mode, mask, reg, next_select);
6141 /* For most binary operations, just propagate into the operation and
6142 change the mode if we have an operation of that mode. */
6144 op0 = gen_lowpart_for_combine (op_mode,
6145 force_to_mode (XEXP (x, 0), mode, mask,
6147 op1 = gen_lowpart_for_combine (op_mode,
6148 force_to_mode (XEXP (x, 1), mode, mask,
6151 /* If OP1 is a CONST_INT and X is an IOR or XOR, clear bits outside
6152 MASK since OP1 might have been sign-extended but we never want
6153 to turn on extra bits, since combine might have previously relied
6154 on them being off. */
6155 if (GET_CODE (op1) == CONST_INT && (code == IOR || code == XOR)
6156 && (INTVAL (op1) & mask) != 0)
6157 op1 = GEN_INT (INTVAL (op1) & mask);
6159 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6160 x = gen_binary (code, op_mode, op0, op1);
6164 /* For left shifts, do the same, but just for the first operand.
6165 However, we cannot do anything with shifts where we cannot
6166 guarantee that the counts are smaller than the size of the mode
6167 because such a count will have a different meaning in a
6170 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
6171 && INTVAL (XEXP (x, 1)) >= 0
6172 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
6173 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
6174 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
6175 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
6178 /* If the shift count is a constant and we can do arithmetic in
6179 the mode of the shift, refine which bits we need. Otherwise, use the
6180 conservative form of the mask. */
6181 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6182 && INTVAL (XEXP (x, 1)) >= 0
6183 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
6184 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6185 mask >>= INTVAL (XEXP (x, 1));
6189 op0 = gen_lowpart_for_combine (op_mode,
6190 force_to_mode (XEXP (x, 0), op_mode,
6191 mask, reg, next_select));
6193 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
6194 x = gen_binary (code, op_mode, op0, XEXP (x, 1));
6198 /* Here we can only do something if the shift count is a constant,
6199 this shift constant is valid for the host, and we can do arithmetic
6202 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6203 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6204 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6206 rtx inner = XEXP (x, 0);
6208 /* Select the mask of the bits we need for the shift operand. */
6209 mask <<= INTVAL (XEXP (x, 1));
6211 /* We can only change the mode of the shift if we can do arithmetic
6212 in the mode of the shift and MASK is no wider than the width of
6214 if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT
6215 || (mask & ~ GET_MODE_MASK (op_mode)) != 0)
6216 op_mode = GET_MODE (x);
6218 inner = force_to_mode (inner, op_mode, mask, reg, next_select);
6220 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
6221 x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
6224 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
6225 shift and AND produces only copies of the sign bit (C2 is one less
6226 than a power of two), we can do this with just a shift. */
6228 if (GET_CODE (x) == LSHIFTRT
6229 && GET_CODE (XEXP (x, 1)) == CONST_INT
6230 && ((INTVAL (XEXP (x, 1))
6231 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
6232 >= GET_MODE_BITSIZE (GET_MODE (x)))
6233 && exact_log2 (mask + 1) >= 0
6234 && (num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6235 >= exact_log2 (mask + 1)))
6236 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
6237 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
6238 - exact_log2 (mask + 1)));
6242 /* If we are just looking for the sign bit, we don't need this shift at
6243 all, even if it has a variable count. */
6244 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6245 && (mask == ((HOST_WIDE_INT) 1
6246 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
6247 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6249 /* If this is a shift by a constant, get a mask that contains those bits
6250 that are not copies of the sign bit. We then have two cases: If
6251 MASK only includes those bits, this can be a logical shift, which may
6252 allow simplifications. If MASK is a single-bit field not within
6253 those bits, we are requesting a copy of the sign bit and hence can
6254 shift the sign bit to the appropriate location. */
6256 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
6257 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
6261 /* If the considered data is wider then HOST_WIDE_INT, we can't
6262 represent a mask for all its bits in a single scalar.
6263 But we only care about the lower bits, so calculate these. */
6265 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
6267 nonzero = ~ (HOST_WIDE_INT) 0;
6269 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6270 is the number of bits a full-width mask would have set.
6271 We need only shift if these are fewer than nonzero can
6272 hold. If not, we must keep all bits set in nonzero. */
6274 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6275 < HOST_BITS_PER_WIDE_INT)
6276 nonzero >>= INTVAL (XEXP (x, 1))
6277 + HOST_BITS_PER_WIDE_INT
6278 - GET_MODE_BITSIZE (GET_MODE (x)) ;
6282 nonzero = GET_MODE_MASK (GET_MODE (x));
6283 nonzero >>= INTVAL (XEXP (x, 1));
6286 if ((mask & ~ nonzero) == 0
6287 || (i = exact_log2 (mask)) >= 0)
6289 x = simplify_shift_const
6290 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
6291 i < 0 ? INTVAL (XEXP (x, 1))
6292 : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
6294 if (GET_CODE (x) != ASHIFTRT)
6295 return force_to_mode (x, mode, mask, reg, next_select);
6299 /* If MASK is 1, convert this to a LSHIFTRT. This can be done
6300 even if the shift count isn't a constant. */
6302 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1));
6304 /* If this is a sign-extension operation that just affects bits
6305 we don't care about, remove it. Be sure the call above returned
6306 something that is still a shift. */
6308 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
6309 && GET_CODE (XEXP (x, 1)) == CONST_INT
6310 && INTVAL (XEXP (x, 1)) >= 0
6311 && (INTVAL (XEXP (x, 1))
6312 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
6313 && GET_CODE (XEXP (x, 0)) == ASHIFT
6314 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6315 && INTVAL (XEXP (XEXP (x, 0), 1)) == INTVAL (XEXP (x, 1)))
6316 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
6323 /* If the shift count is constant and we can do computations
6324 in the mode of X, compute where the bits we care about are.
6325 Otherwise, we can't do anything. Don't change the mode of
6326 the shift or propagate MODE into the shift, though. */
6327 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6328 && INTVAL (XEXP (x, 1)) >= 0)
6330 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
6331 GET_MODE (x), GEN_INT (mask),
6333 if (temp && GET_CODE(temp) == CONST_INT)
6335 force_to_mode (XEXP (x, 0), GET_MODE (x),
6336 INTVAL (temp), reg, next_select));
6341 /* If we just want the low-order bit, the NEG isn't needed since it
6342 won't change the low-order bit. */
6344 return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
6346 /* We need any bits less significant than the most significant bit in
6347 MASK since carries from those bits will affect the bits we are
6353 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
6354 same as the XOR case above. Ensure that the constant we form is not
6355 wider than the mode of X. */
6357 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6358 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6359 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6360 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
6361 < GET_MODE_BITSIZE (GET_MODE (x)))
6362 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
6364 temp = GEN_INT (mask << INTVAL (XEXP (XEXP (x, 0), 1)));
6365 temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp);
6366 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1));
6368 return force_to_mode (x, mode, mask, reg, next_select);
6371 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
6372 use the full mask inside the NOT. */
6376 op0 = gen_lowpart_for_combine (op_mode,
6377 force_to_mode (XEXP (x, 0), mode, mask,
6379 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
6380 x = gen_unary (code, op_mode, op_mode, op0);
6384 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
6385 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
6386 which is in CONST. */
6387 if ((mask & ~ STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
6388 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
6389 && (nonzero_bits (XEXP (x, 0), mode) & ~ mask) == 0)
6390 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6395 /* We have no way of knowing if the IF_THEN_ELSE can itself be
6396 written in a narrower mode. We play it safe and do not do so. */
6399 gen_lowpart_for_combine (GET_MODE (x),
6400 force_to_mode (XEXP (x, 1), mode,
6401 mask, reg, next_select)));
6403 gen_lowpart_for_combine (GET_MODE (x),
6404 force_to_mode (XEXP (x, 2), mode,
6405 mask, reg,next_select)));
6409 /* Ensure we return a value of the proper mode. */
6410 return gen_lowpart_for_combine (mode, x);
6413 /* Return nonzero if X is an expression that has one of two values depending on
6414 whether some other value is zero or nonzero. In that case, we return the
6415 value that is being tested, *PTRUE is set to the value if the rtx being
6416 returned has a nonzero value, and *PFALSE is set to the other alternative.
6418 If we return zero, we set *PTRUE and *PFALSE to X. */
6421 if_then_else_cond (x, ptrue, pfalse)
6423 rtx *ptrue, *pfalse;
6425 enum machine_mode mode = GET_MODE (x);
6426 enum rtx_code code = GET_CODE (x);
6427 int size = GET_MODE_BITSIZE (mode);
6428 rtx cond0, cond1, true0, true1, false0, false1;
6429 unsigned HOST_WIDE_INT nz;
6431 /* If this is a unary operation whose operand has one of two values, apply
6432 our opcode to compute those values. */
6433 if (GET_RTX_CLASS (code) == '1'
6434 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
6436 *ptrue = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), true0);
6437 *pfalse = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), false0);
6441 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
6442 make can't possibly match and would suppress other optimizations. */
6443 else if (code == COMPARE)
6446 /* If this is a binary operation, see if either side has only one of two
6447 values. If either one does or if both do and they are conditional on
6448 the same value, compute the new true and false values. */
6449 else if (GET_RTX_CLASS (code) == 'c' || GET_RTX_CLASS (code) == '2'
6450 || GET_RTX_CLASS (code) == '<')
6452 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
6453 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
6455 if ((cond0 != 0 || cond1 != 0)
6456 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
6458 *ptrue = gen_binary (code, mode, true0, true1);
6459 *pfalse = gen_binary (code, mode, false0, false1);
6460 return cond0 ? cond0 : cond1;
6463 #if STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1
6465 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
6466 operands is zero when the other is non-zero, and vice-versa. */
6468 if ((code == PLUS || code == IOR || code == XOR || code == MINUS
6470 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
6472 rtx op0 = XEXP (XEXP (x, 0), 1);
6473 rtx op1 = XEXP (XEXP (x, 1), 1);
6475 cond0 = XEXP (XEXP (x, 0), 0);
6476 cond1 = XEXP (XEXP (x, 1), 0);
6478 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
6479 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
6480 && reversible_comparison_p (cond1)
6481 && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1))
6482 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
6483 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
6484 || ((swap_condition (GET_CODE (cond0))
6485 == reverse_condition (GET_CODE (cond1)))
6486 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
6487 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
6488 && ! side_effects_p (x))
6490 *ptrue = gen_binary (MULT, mode, op0, const_true_rtx);
6491 *pfalse = gen_binary (MULT, mode,
6493 ? gen_unary (NEG, mode, mode, op1) : op1),
6499 /* Similarly for MULT, AND and UMIN, execpt that for these the result
6501 if ((code == MULT || code == AND || code == UMIN)
6502 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
6504 cond0 = XEXP (XEXP (x, 0), 0);
6505 cond1 = XEXP (XEXP (x, 1), 0);
6507 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
6508 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
6509 && reversible_comparison_p (cond1)
6510 && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1))
6511 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
6512 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
6513 || ((swap_condition (GET_CODE (cond0))
6514 == reverse_condition (GET_CODE (cond1)))
6515 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
6516 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
6517 && ! side_effects_p (x))
6519 *ptrue = *pfalse = const0_rtx;
6526 else if (code == IF_THEN_ELSE)
6528 /* If we have IF_THEN_ELSE already, extract the condition and
6529 canonicalize it if it is NE or EQ. */
6530 cond0 = XEXP (x, 0);
6531 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
6532 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
6533 return XEXP (cond0, 0);
6534 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
6536 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
6537 return XEXP (cond0, 0);
6543 /* If X is a normal SUBREG with both inner and outer modes integral,
6544 we can narrow both the true and false values of the inner expression,
6545 if there is a condition. */
6546 else if (code == SUBREG && GET_MODE_CLASS (mode) == MODE_INT
6547 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_INT
6548 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))
6549 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
6552 *ptrue = force_to_mode (true0, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
6554 = force_to_mode (false0, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
6559 /* If X is a constant, this isn't special and will cause confusions
6560 if we treat it as such. Likewise if it is equivalent to a constant. */
6561 else if (CONSTANT_P (x)
6562 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
6565 /* If X is known to be either 0 or -1, those are the true and
6566 false values when testing X. */
6567 else if (num_sign_bit_copies (x, mode) == size)
6569 *ptrue = constm1_rtx, *pfalse = const0_rtx;
6573 /* Likewise for 0 or a single bit. */
6574 else if (exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
6576 *ptrue = GEN_INT (nz), *pfalse = const0_rtx;
6580 /* Otherwise fail; show no condition with true and false values the same. */
6581 *ptrue = *pfalse = x;
6585 /* Return the value of expression X given the fact that condition COND
6586 is known to be true when applied to REG as its first operand and VAL
6587 as its second. X is known to not be shared and so can be modified in
6590 We only handle the simplest cases, and specifically those cases that
6591 arise with IF_THEN_ELSE expressions. */
6594 known_cond (x, cond, reg, val)
6599 enum rtx_code code = GET_CODE (x);
6604 if (side_effects_p (x))
6607 if (cond == EQ && rtx_equal_p (x, reg))
6610 /* If X is (abs REG) and we know something about REG's relationship
6611 with zero, we may be able to simplify this. */
6613 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
6616 case GE: case GT: case EQ:
6619 return gen_unary (NEG, GET_MODE (XEXP (x, 0)), GET_MODE (XEXP (x, 0)),
6623 /* The only other cases we handle are MIN, MAX, and comparisons if the
6624 operands are the same as REG and VAL. */
6626 else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
6628 if (rtx_equal_p (XEXP (x, 0), val))
6629 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
6631 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
6633 if (GET_RTX_CLASS (code) == '<')
6634 return (comparison_dominates_p (cond, code) ? const_true_rtx
6635 : (comparison_dominates_p (cond,
6636 reverse_condition (code))
6639 else if (code == SMAX || code == SMIN
6640 || code == UMIN || code == UMAX)
6642 int unsignedp = (code == UMIN || code == UMAX);
6644 if (code == SMAX || code == UMAX)
6645 cond = reverse_condition (cond);
6650 return unsignedp ? x : XEXP (x, 1);
6652 return unsignedp ? x : XEXP (x, 0);
6654 return unsignedp ? XEXP (x, 1) : x;
6656 return unsignedp ? XEXP (x, 0) : x;
6662 fmt = GET_RTX_FORMAT (code);
6663 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6666 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
6667 else if (fmt[i] == 'E')
6668 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
6669 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
6676 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
6677 assignment as a field assignment. */
6680 rtx_equal_for_field_assignment_p (x, y)
6686 if (x == y || rtx_equal_p (x, y))
6689 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
6692 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
6693 Note that all SUBREGs of MEM are paradoxical; otherwise they
6694 would have been rewritten. */
6695 if (GET_CODE (x) == MEM && GET_CODE (y) == SUBREG
6696 && GET_CODE (SUBREG_REG (y)) == MEM
6697 && rtx_equal_p (SUBREG_REG (y),
6698 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y)), x)))
6701 if (GET_CODE (y) == MEM && GET_CODE (x) == SUBREG
6702 && GET_CODE (SUBREG_REG (x)) == MEM
6703 && rtx_equal_p (SUBREG_REG (x),
6704 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x)), y)))
6707 last_x = get_last_value (x);
6708 last_y = get_last_value (y);
6710 return ((last_x != 0
6711 && GET_CODE (last_x) != CLOBBER
6712 && rtx_equal_for_field_assignment_p (last_x, y))
6714 && GET_CODE (last_y) != CLOBBER
6715 && rtx_equal_for_field_assignment_p (x, last_y))
6716 || (last_x != 0 && last_y != 0
6717 && GET_CODE (last_x) != CLOBBER
6718 && GET_CODE (last_y) != CLOBBER
6719 && rtx_equal_for_field_assignment_p (last_x, last_y)));
6722 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
6723 Return that assignment if so.
6725 We only handle the most common cases. */
6728 make_field_assignment (x)
6731 rtx dest = SET_DEST (x);
6732 rtx src = SET_SRC (x);
6738 enum machine_mode mode;
6740 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
6741 a clear of a one-bit field. We will have changed it to
6742 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
6745 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
6746 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
6747 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
6748 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
6750 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
6753 return gen_rtx (SET, VOIDmode, assign, const0_rtx);
6757 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
6758 && subreg_lowpart_p (XEXP (src, 0))
6759 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
6760 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
6761 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
6762 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
6763 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
6765 assign = make_extraction (VOIDmode, dest, 0,
6766 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
6769 return gen_rtx (SET, VOIDmode, assign, const0_rtx);
6773 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
6775 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
6776 && XEXP (XEXP (src, 0), 0) == const1_rtx
6777 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
6779 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
6782 return gen_rtx (SET, VOIDmode, assign, const1_rtx);
6786 /* The other case we handle is assignments into a constant-position
6787 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
6788 a mask that has all one bits except for a group of zero bits and
6789 OTHER is known to have zeros where C1 has ones, this is such an
6790 assignment. Compute the position and length from C1. Shift OTHER
6791 to the appropriate position, force it to the required mode, and
6792 make the extraction. Check for the AND in both operands. */
6794 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
6797 rhs = expand_compound_operation (XEXP (src, 0));
6798 lhs = expand_compound_operation (XEXP (src, 1));
6800 if (GET_CODE (rhs) == AND
6801 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
6802 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
6803 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
6804 else if (GET_CODE (lhs) == AND
6805 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6806 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
6807 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
6811 pos = get_pos_from_mask ((~ c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
6812 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
6813 || (GET_MODE_BITSIZE (GET_MODE (other)) <= HOST_BITS_PER_WIDE_INT
6814 && (c1 & nonzero_bits (other, GET_MODE (other))) != 0))
6817 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
6821 /* The mode to use for the source is the mode of the assignment, or of
6822 what is inside a possible STRICT_LOW_PART. */
6823 mode = (GET_CODE (assign) == STRICT_LOW_PART
6824 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
6826 /* Shift OTHER right POS places and make it the source, restricting it
6827 to the proper length and mode. */
6829 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
6830 GET_MODE (src), other, pos),
6832 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
6833 ? GET_MODE_MASK (mode)
6834 : ((HOST_WIDE_INT) 1 << len) - 1,
6837 return gen_rtx_combine (SET, VOIDmode, assign, src);
6840 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
6844 apply_distributive_law (x)
6847 enum rtx_code code = GET_CODE (x);
6848 rtx lhs, rhs, other;
6850 enum rtx_code inner_code;
6852 /* Distributivity is not true for floating point.
6853 It can change the value. So don't do it.
6854 -- rms and moshier@world.std.com. */
6855 if (FLOAT_MODE_P (GET_MODE (x)))
6858 /* The outer operation can only be one of the following: */
6859 if (code != IOR && code != AND && code != XOR
6860 && code != PLUS && code != MINUS)
6863 lhs = XEXP (x, 0), rhs = XEXP (x, 1);
6865 /* If either operand is a primitive we can't do anything, so get out
6867 if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
6868 || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
6871 lhs = expand_compound_operation (lhs);
6872 rhs = expand_compound_operation (rhs);
6873 inner_code = GET_CODE (lhs);
6874 if (inner_code != GET_CODE (rhs))
6877 /* See if the inner and outer operations distribute. */
6884 /* These all distribute except over PLUS. */
6885 if (code == PLUS || code == MINUS)
6890 if (code != PLUS && code != MINUS)
6895 /* This is also a multiply, so it distributes over everything. */
6899 /* Non-paradoxical SUBREGs distributes over all operations, provided
6900 the inner modes and word numbers are the same, this is an extraction
6901 of a low-order part, we don't convert an fp operation to int or
6902 vice versa, and we would not be converting a single-word
6903 operation into a multi-word operation. The latter test is not
6904 required, but it prevents generating unneeded multi-word operations.
6905 Some of the previous tests are redundant given the latter test, but
6906 are retained because they are required for correctness.
6908 We produce the result slightly differently in this case. */
6910 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
6911 || SUBREG_WORD (lhs) != SUBREG_WORD (rhs)
6912 || ! subreg_lowpart_p (lhs)
6913 || (GET_MODE_CLASS (GET_MODE (lhs))
6914 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
6915 || (GET_MODE_SIZE (GET_MODE (lhs))
6916 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
6917 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
6920 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
6921 SUBREG_REG (lhs), SUBREG_REG (rhs));
6922 return gen_lowpart_for_combine (GET_MODE (x), tem);
6928 /* Set LHS and RHS to the inner operands (A and B in the example
6929 above) and set OTHER to the common operand (C in the example).
6930 These is only one way to do this unless the inner operation is
6932 if (GET_RTX_CLASS (inner_code) == 'c'
6933 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
6934 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
6935 else if (GET_RTX_CLASS (inner_code) == 'c'
6936 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
6937 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
6938 else if (GET_RTX_CLASS (inner_code) == 'c'
6939 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
6940 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
6941 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
6942 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
6946 /* Form the new inner operation, seeing if it simplifies first. */
6947 tem = gen_binary (code, GET_MODE (x), lhs, rhs);
6949 /* There is one exception to the general way of distributing:
6950 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
6951 if (code == XOR && inner_code == IOR)
6954 other = gen_unary (NOT, GET_MODE (x), GET_MODE (x), other);
6957 /* We may be able to continuing distributing the result, so call
6958 ourselves recursively on the inner operation before forming the
6959 outer operation, which we return. */
6960 return gen_binary (inner_code, GET_MODE (x),
6961 apply_distributive_law (tem), other);
6964 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
6967 Return an equivalent form, if different from X. Otherwise, return X. If
6968 X is zero, we are to always construct the equivalent form. */
6971 simplify_and_const_int (x, mode, varop, constop)
6973 enum machine_mode mode;
6975 unsigned HOST_WIDE_INT constop;
6977 unsigned HOST_WIDE_INT nonzero;
6978 int width = GET_MODE_BITSIZE (mode);
6981 /* Simplify VAROP knowing that we will be only looking at some of the
6983 varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
6985 /* If VAROP is a CLOBBER, we will fail so return it; if it is a
6986 CONST_INT, we are done. */
6987 if (GET_CODE (varop) == CLOBBER || GET_CODE (varop) == CONST_INT)
6990 /* See what bits may be nonzero in VAROP. Unlike the general case of
6991 a call to nonzero_bits, here we don't care about bits outside
6994 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
6996 /* If this would be an entire word for the target, but is not for
6997 the host, then sign-extend on the host so that the number will look
6998 the same way on the host that it would on the target.
7000 For example, when building a 64 bit alpha hosted 32 bit sparc
7001 targeted compiler, then we want the 32 bit unsigned value -1 to be
7002 represented as a 64 bit value -1, and not as 0x00000000ffffffff.
7003 The later confuses the sparc backend. */
7005 if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT && BITS_PER_WORD == width
7006 && (nonzero & ((HOST_WIDE_INT) 1 << (width - 1))))
7007 nonzero |= ((HOST_WIDE_INT) (-1) << width);
7009 /* Turn off all bits in the constant that are known to already be zero.
7010 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7011 which is tested below. */
7015 /* If we don't have any bits left, return zero. */
7019 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7020 a power of two, we can replace this with a ASHIFT. */
7021 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
7022 && (i = exact_log2 (constop)) >= 0)
7023 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
7025 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7026 or XOR, then try to apply the distributive law. This may eliminate
7027 operations if either branch can be simplified because of the AND.
7028 It may also make some cases more complex, but those cases probably
7029 won't match a pattern either with or without this. */
7031 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
7033 gen_lowpart_for_combine
7035 apply_distributive_law
7036 (gen_binary (GET_CODE (varop), GET_MODE (varop),
7037 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7038 XEXP (varop, 0), constop),
7039 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7040 XEXP (varop, 1), constop))));
7042 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
7043 if we already had one (just check for the simplest cases). */
7044 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
7045 && GET_MODE (XEXP (x, 0)) == mode
7046 && SUBREG_REG (XEXP (x, 0)) == varop)
7047 varop = XEXP (x, 0);
7049 varop = gen_lowpart_for_combine (mode, varop);
7051 /* If we can't make the SUBREG, try to return what we were given. */
7052 if (GET_CODE (varop) == CLOBBER)
7053 return x ? x : varop;
7055 /* If we are only masking insignificant bits, return VAROP. */
7056 if (constop == nonzero)
7059 /* Otherwise, return an AND. See how much, if any, of X we can use. */
7060 else if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
7061 x = gen_binary (AND, mode, varop, GEN_INT (constop));
7065 if (GET_CODE (XEXP (x, 1)) != CONST_INT
7066 || INTVAL (XEXP (x, 1)) != constop)
7067 SUBST (XEXP (x, 1), GEN_INT (constop));
7069 SUBST (XEXP (x, 0), varop);
7075 /* Given an expression, X, compute which bits in X can be non-zero.
7076 We don't care about bits outside of those defined in MODE.
7078 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
7079 a shift, AND, or zero_extract, we can do better. */
7081 static unsigned HOST_WIDE_INT
7082 nonzero_bits (x, mode)
7084 enum machine_mode mode;
7086 unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);
7087 unsigned HOST_WIDE_INT inner_nz;
7089 int mode_width = GET_MODE_BITSIZE (mode);
7092 /* For floating-point values, assume all bits are needed. */
7093 if (FLOAT_MODE_P (GET_MODE (x)) || FLOAT_MODE_P (mode))
7096 /* If X is wider than MODE, use its mode instead. */
7097 if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
7099 mode = GET_MODE (x);
7100 nonzero = GET_MODE_MASK (mode);
7101 mode_width = GET_MODE_BITSIZE (mode);
7104 if (mode_width > HOST_BITS_PER_WIDE_INT)
7105 /* Our only callers in this case look for single bit values. So
7106 just return the mode mask. Those tests will then be false. */
7109 #ifndef WORD_REGISTER_OPERATIONS
7110 /* If MODE is wider than X, but both are a single word for both the host
7111 and target machines, we can compute this from which bits of the
7112 object might be nonzero in its own mode, taking into account the fact
7113 that on many CISC machines, accessing an object in a wider mode
7114 causes the high-order bits to become undefined. So they are
7115 not known to be zero. */
7117 if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode
7118 && GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD
7119 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7120 && GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (GET_MODE (x)))
7122 nonzero &= nonzero_bits (x, GET_MODE (x));
7123 nonzero |= GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x));
7128 code = GET_CODE (x);
7132 #ifdef POINTERS_EXTEND_UNSIGNED
7133 /* If pointers extend unsigned and this is a pointer in Pmode, say that
7134 all the bits above ptr_mode are known to be zero. */
7135 if (POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
7136 && REGNO_POINTER_FLAG (REGNO (x)))
7137 nonzero &= GET_MODE_MASK (ptr_mode);
7140 #ifdef STACK_BOUNDARY
7141 /* If this is the stack pointer, we may know something about its
7142 alignment. If PUSH_ROUNDING is defined, it is possible for the
7143 stack to be momentarily aligned only to that amount, so we pick
7144 the least alignment. */
7146 /* We can't check for arg_pointer_rtx here, because it is not
7147 guaranteed to have as much alignment as the stack pointer.
7148 In particular, in the Irix6 n64 ABI, the stack has 128 bit
7149 alignment but the argument pointer has only 64 bit alignment. */
7151 if (x == stack_pointer_rtx || x == frame_pointer_rtx
7152 || x == hard_frame_pointer_rtx
7153 || (REGNO (x) >= FIRST_VIRTUAL_REGISTER
7154 && REGNO (x) <= LAST_VIRTUAL_REGISTER))
7156 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
7158 #ifdef PUSH_ROUNDING
7159 if (REGNO (x) == STACK_POINTER_REGNUM)
7160 sp_alignment = MIN (PUSH_ROUNDING (1), sp_alignment);
7163 /* We must return here, otherwise we may get a worse result from
7164 one of the choices below. There is nothing useful below as
7165 far as the stack pointer is concerned. */
7166 return nonzero &= ~ (sp_alignment - 1);
7170 /* If X is a register whose nonzero bits value is current, use it.
7171 Otherwise, if X is a register whose value we can find, use that
7172 value. Otherwise, use the previously-computed global nonzero bits
7173 for this register. */
7175 if (reg_last_set_value[REGNO (x)] != 0
7176 && reg_last_set_mode[REGNO (x)] == mode
7177 && (reg_n_sets[REGNO (x)] == 1
7178 || reg_last_set_label[REGNO (x)] == label_tick)
7179 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
7180 return reg_last_set_nonzero_bits[REGNO (x)];
7182 tem = get_last_value (x);
7186 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7187 /* If X is narrower than MODE and TEM is a non-negative
7188 constant that would appear negative in the mode of X,
7189 sign-extend it for use in reg_nonzero_bits because some
7190 machines (maybe most) will actually do the sign-extension
7191 and this is the conservative approach.
7193 ??? For 2.5, try to tighten up the MD files in this regard
7194 instead of this kludge. */
7196 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width
7197 && GET_CODE (tem) == CONST_INT
7199 && 0 != (INTVAL (tem)
7200 & ((HOST_WIDE_INT) 1
7201 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7202 tem = GEN_INT (INTVAL (tem)
7203 | ((HOST_WIDE_INT) (-1)
7204 << GET_MODE_BITSIZE (GET_MODE (x))));
7206 return nonzero_bits (tem, mode);
7208 else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)])
7209 return reg_nonzero_bits[REGNO (x)] & nonzero;
7214 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7215 /* If X is negative in MODE, sign-extend the value. */
7216 if (INTVAL (x) > 0 && mode_width < BITS_PER_WORD
7217 && 0 != (INTVAL (x) & ((HOST_WIDE_INT) 1 << (mode_width - 1))))
7218 return (INTVAL (x) | ((HOST_WIDE_INT) (-1) << mode_width));
7224 #ifdef LOAD_EXTEND_OP
7225 /* In many, if not most, RISC machines, reading a byte from memory
7226 zeros the rest of the register. Noticing that fact saves a lot
7227 of extra zero-extends. */
7228 if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND)
7229 nonzero &= GET_MODE_MASK (GET_MODE (x));
7239 /* If this produces an integer result, we know which bits are set.
7240 Code here used to clear bits outside the mode of X, but that is
7243 if (GET_MODE_CLASS (mode) == MODE_INT
7244 && mode_width <= HOST_BITS_PER_WIDE_INT)
7245 nonzero = STORE_FLAG_VALUE;
7249 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
7250 == GET_MODE_BITSIZE (GET_MODE (x)))
7253 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
7254 nonzero |= (GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x)));
7258 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
7259 == GET_MODE_BITSIZE (GET_MODE (x)))
7264 nonzero &= (nonzero_bits (XEXP (x, 0), mode) & GET_MODE_MASK (mode));
7268 nonzero &= nonzero_bits (XEXP (x, 0), mode);
7269 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
7270 nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
7274 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
7275 Otherwise, show all the bits in the outer mode but not the inner
7277 inner_nz = nonzero_bits (XEXP (x, 0), mode);
7278 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
7280 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
7283 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
7284 inner_nz |= (GET_MODE_MASK (mode)
7285 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
7288 nonzero &= inner_nz;
7292 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
7293 & nonzero_bits (XEXP (x, 1), mode));
7297 case UMIN: case UMAX: case SMIN: case SMAX:
7298 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
7299 | nonzero_bits (XEXP (x, 1), mode));
7302 case PLUS: case MINUS:
7304 case DIV: case UDIV:
7305 case MOD: case UMOD:
7306 /* We can apply the rules of arithmetic to compute the number of
7307 high- and low-order zero bits of these operations. We start by
7308 computing the width (position of the highest-order non-zero bit)
7309 and the number of low-order zero bits for each value. */
7311 unsigned HOST_WIDE_INT nz0 = nonzero_bits (XEXP (x, 0), mode);
7312 unsigned HOST_WIDE_INT nz1 = nonzero_bits (XEXP (x, 1), mode);
7313 int width0 = floor_log2 (nz0) + 1;
7314 int width1 = floor_log2 (nz1) + 1;
7315 int low0 = floor_log2 (nz0 & -nz0);
7316 int low1 = floor_log2 (nz1 & -nz1);
7317 HOST_WIDE_INT op0_maybe_minusp
7318 = (nz0 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
7319 HOST_WIDE_INT op1_maybe_minusp
7320 = (nz1 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
7321 int result_width = mode_width;
7327 result_width = MAX (width0, width1) + 1;
7328 result_low = MIN (low0, low1);
7331 result_low = MIN (low0, low1);
7334 result_width = width0 + width1;
7335 result_low = low0 + low1;
7338 if (! op0_maybe_minusp && ! op1_maybe_minusp)
7339 result_width = width0;
7342 result_width = width0;
7345 if (! op0_maybe_minusp && ! op1_maybe_minusp)
7346 result_width = MIN (width0, width1);
7347 result_low = MIN (low0, low1);
7350 result_width = MIN (width0, width1);
7351 result_low = MIN (low0, low1);
7355 if (result_width < mode_width)
7356 nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1;
7359 nonzero &= ~ (((HOST_WIDE_INT) 1 << result_low) - 1);
7364 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7365 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7366 nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1;
7370 /* If this is a SUBREG formed for a promoted variable that has
7371 been zero-extended, we know that at least the high-order bits
7372 are zero, though others might be too. */
7374 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x))
7375 nonzero = (GET_MODE_MASK (GET_MODE (x))
7376 & nonzero_bits (SUBREG_REG (x), GET_MODE (x)));
7378 /* If the inner mode is a single word for both the host and target
7379 machines, we can compute this from which bits of the inner
7380 object might be nonzero. */
7381 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
7382 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
7383 <= HOST_BITS_PER_WIDE_INT))
7385 nonzero &= nonzero_bits (SUBREG_REG (x), mode);
7387 #ifndef WORD_REGISTER_OPERATIONS
7388 /* On many CISC machines, accessing an object in a wider mode
7389 causes the high-order bits to become undefined. So they are
7390 not known to be zero. */
7391 if (GET_MODE_SIZE (GET_MODE (x))
7392 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7393 nonzero |= (GET_MODE_MASK (GET_MODE (x))
7394 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
7403 /* The nonzero bits are in two classes: any bits within MODE
7404 that aren't in GET_MODE (x) are always significant. The rest of the
7405 nonzero bits are those that are significant in the operand of
7406 the shift when shifted the appropriate number of bits. This
7407 shows that high-order bits are cleared by the right shift and
7408 low-order bits by left shifts. */
7409 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7410 && INTVAL (XEXP (x, 1)) >= 0
7411 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7413 enum machine_mode inner_mode = GET_MODE (x);
7414 int width = GET_MODE_BITSIZE (inner_mode);
7415 int count = INTVAL (XEXP (x, 1));
7416 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
7417 unsigned HOST_WIDE_INT op_nonzero = nonzero_bits (XEXP (x, 0), mode);
7418 unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask;
7419 unsigned HOST_WIDE_INT outer = 0;
7421 if (mode_width > width)
7422 outer = (op_nonzero & nonzero & ~ mode_mask);
7424 if (code == LSHIFTRT)
7426 else if (code == ASHIFTRT)
7430 /* If the sign bit may have been nonzero before the shift, we
7431 need to mark all the places it could have been copied to
7432 by the shift as possibly nonzero. */
7433 if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count)))
7434 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count);
7436 else if (code == ASHIFT)
7439 inner = ((inner << (count % width)
7440 | (inner >> (width - (count % width)))) & mode_mask);
7442 nonzero &= (outer | inner);
7447 /* This is at most the number of bits in the mode. */
7448 nonzero = ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width) + 1)) - 1;
7452 nonzero &= (nonzero_bits (XEXP (x, 1), mode)
7453 | nonzero_bits (XEXP (x, 2), mode));
7460 /* Return the number of bits at the high-order end of X that are known to
7461 be equal to the sign bit. X will be used in mode MODE; if MODE is
7462 VOIDmode, X will be used in its own mode. The returned value will always
7463 be between 1 and the number of bits in MODE. */
7466 num_sign_bit_copies (x, mode)
7468 enum machine_mode mode;
7470 enum rtx_code code = GET_CODE (x);
7472 int num0, num1, result;
7473 unsigned HOST_WIDE_INT nonzero;
7476 /* If we weren't given a mode, use the mode of X. If the mode is still
7477 VOIDmode, we don't know anything. Likewise if one of the modes is
7480 if (mode == VOIDmode)
7481 mode = GET_MODE (x);
7483 if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x)))
7486 bitwidth = GET_MODE_BITSIZE (mode);
7488 /* For a smaller object, just ignore the high bits. */
7489 if (bitwidth < GET_MODE_BITSIZE (GET_MODE (x)))
7490 return MAX (1, (num_sign_bit_copies (x, GET_MODE (x))
7491 - (GET_MODE_BITSIZE (GET_MODE (x)) - bitwidth)));
7493 #ifndef WORD_REGISTER_OPERATIONS
7494 /* If this machine does not do all register operations on the entire
7495 register and MODE is wider than the mode of X, we can say nothing
7496 at all about the high-order bits. */
7497 if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_BITSIZE (GET_MODE (x)))
7505 #ifdef POINTERS_EXTEND_UNSIGNED
7506 /* If pointers extend signed and this is a pointer in Pmode, say that
7507 all the bits above ptr_mode are known to be sign bit copies. */
7508 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode && mode == Pmode
7509 && REGNO_POINTER_FLAG (REGNO (x)))
7510 return GET_MODE_BITSIZE (Pmode) - GET_MODE_BITSIZE (ptr_mode) + 1;
7513 if (reg_last_set_value[REGNO (x)] != 0
7514 && reg_last_set_mode[REGNO (x)] == mode
7515 && (reg_n_sets[REGNO (x)] == 1
7516 || reg_last_set_label[REGNO (x)] == label_tick)
7517 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
7518 return reg_last_set_sign_bit_copies[REGNO (x)];
7520 tem = get_last_value (x);
7522 return num_sign_bit_copies (tem, mode);
7524 if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0)
7525 return reg_sign_bit_copies[REGNO (x)];
7529 #ifdef LOAD_EXTEND_OP
7530 /* Some RISC machines sign-extend all loads of smaller than a word. */
7531 if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND)
7532 return MAX (1, bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1);
7537 /* If the constant is negative, take its 1's complement and remask.
7538 Then see how many zero bits we have. */
7539 nonzero = INTVAL (x) & GET_MODE_MASK (mode);
7540 if (bitwidth <= HOST_BITS_PER_WIDE_INT
7541 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
7542 nonzero = (~ nonzero) & GET_MODE_MASK (mode);
7544 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
7547 /* If this is a SUBREG for a promoted object that is sign-extended
7548 and we are looking at it in a wider mode, we know that at least the
7549 high-order bits are known to be sign bit copies. */
7551 if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
7552 return MAX (bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1,
7553 num_sign_bit_copies (SUBREG_REG (x), mode));
7555 /* For a smaller object, just ignore the high bits. */
7556 if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
7558 num0 = num_sign_bit_copies (SUBREG_REG (x), VOIDmode);
7559 return MAX (1, (num0
7560 - (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
7564 #ifdef WORD_REGISTER_OPERATIONS
7565 #ifdef LOAD_EXTEND_OP
7566 /* For paradoxical SUBREGs on machines where all register operations
7567 affect the entire register, just look inside. Note that we are
7568 passing MODE to the recursive call, so the number of sign bit copies
7569 will remain relative to that mode, not the inner mode. */
7571 /* This works only if loads sign extend. Otherwise, if we get a
7572 reload for the inner part, it may be loaded from the stack, and
7573 then we lose all sign bit copies that existed before the store
7576 if ((GET_MODE_SIZE (GET_MODE (x))
7577 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7578 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND)
7579 return num_sign_bit_copies (SUBREG_REG (x), mode);
7585 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
7586 return MAX (1, bitwidth - INTVAL (XEXP (x, 1)));
7590 return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
7591 + num_sign_bit_copies (XEXP (x, 0), VOIDmode));
7594 /* For a smaller object, just ignore the high bits. */
7595 num0 = num_sign_bit_copies (XEXP (x, 0), VOIDmode);
7596 return MAX (1, (num0 - (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
7600 return num_sign_bit_copies (XEXP (x, 0), mode);
7602 case ROTATE: case ROTATERT:
7603 /* If we are rotating left by a number of bits less than the number
7604 of sign bit copies, we can just subtract that amount from the
7606 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7607 && INTVAL (XEXP (x, 1)) >= 0 && INTVAL (XEXP (x, 1)) < bitwidth)
7609 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7610 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
7611 : bitwidth - INTVAL (XEXP (x, 1))));
7616 /* In general, this subtracts one sign bit copy. But if the value
7617 is known to be positive, the number of sign bit copies is the
7618 same as that of the input. Finally, if the input has just one bit
7619 that might be nonzero, all the bits are copies of the sign bit. */
7620 nonzero = nonzero_bits (XEXP (x, 0), mode);
7624 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7626 && bitwidth <= HOST_BITS_PER_WIDE_INT
7627 && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero))
7632 case IOR: case AND: case XOR:
7633 case SMIN: case SMAX: case UMIN: case UMAX:
7634 /* Logical operations will preserve the number of sign-bit copies.
7635 MIN and MAX operations always return one of the operands. */
7636 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7637 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
7638 return MIN (num0, num1);
7640 case PLUS: case MINUS:
7641 /* For addition and subtraction, we can have a 1-bit carry. However,
7642 if we are subtracting 1 from a positive number, there will not
7643 be such a carry. Furthermore, if the positive number is known to
7644 be 0 or 1, we know the result is either -1 or 0. */
7646 if (code == PLUS && XEXP (x, 1) == constm1_rtx
7647 && bitwidth <= HOST_BITS_PER_WIDE_INT)
7649 nonzero = nonzero_bits (XEXP (x, 0), mode);
7650 if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0)
7651 return (nonzero == 1 || nonzero == 0 ? bitwidth
7652 : bitwidth - floor_log2 (nonzero) - 1);
7655 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7656 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
7657 return MAX (1, MIN (num0, num1) - 1);
7660 /* The number of bits of the product is the sum of the number of
7661 bits of both terms. However, unless one of the terms if known
7662 to be positive, we must allow for an additional bit since negating
7663 a negative number can remove one sign bit copy. */
7665 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7666 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
7668 result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
7670 && bitwidth <= HOST_BITS_PER_WIDE_INT
7671 && ((nonzero_bits (XEXP (x, 0), mode)
7672 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
7673 && ((nonzero_bits (XEXP (x, 1), mode)
7674 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
7677 return MAX (1, result);
7680 /* The result must be <= the first operand. */
7681 return num_sign_bit_copies (XEXP (x, 0), mode);
7684 /* The result must be <= the scond operand. */
7685 return num_sign_bit_copies (XEXP (x, 1), mode);
7688 /* Similar to unsigned division, except that we have to worry about
7689 the case where the divisor is negative, in which case we have
7691 result = num_sign_bit_copies (XEXP (x, 0), mode);
7693 && bitwidth <= HOST_BITS_PER_WIDE_INT
7694 && (nonzero_bits (XEXP (x, 1), mode)
7695 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
7701 result = num_sign_bit_copies (XEXP (x, 1), mode);
7703 && bitwidth <= HOST_BITS_PER_WIDE_INT
7704 && (nonzero_bits (XEXP (x, 1), mode)
7705 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
7711 /* Shifts by a constant add to the number of bits equal to the
7713 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7714 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7715 && INTVAL (XEXP (x, 1)) > 0)
7716 num0 = MIN (bitwidth, num0 + INTVAL (XEXP (x, 1)));
7721 /* Left shifts destroy copies. */
7722 if (GET_CODE (XEXP (x, 1)) != CONST_INT
7723 || INTVAL (XEXP (x, 1)) < 0
7724 || INTVAL (XEXP (x, 1)) >= bitwidth)
7727 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7728 return MAX (1, num0 - INTVAL (XEXP (x, 1)));
7731 num0 = num_sign_bit_copies (XEXP (x, 1), mode);
7732 num1 = num_sign_bit_copies (XEXP (x, 2), mode);
7733 return MIN (num0, num1);
7735 #if STORE_FLAG_VALUE == -1
7736 case EQ: case NE: case GE: case GT: case LE: case LT:
7737 case GEU: case GTU: case LEU: case LTU:
7742 /* If we haven't been able to figure it out by one of the above rules,
7743 see if some of the high-order bits are known to be zero. If so,
7744 count those bits and return one less than that amount. If we can't
7745 safely compute the mask for this mode, always return BITWIDTH. */
7747 if (bitwidth > HOST_BITS_PER_WIDE_INT)
7750 nonzero = nonzero_bits (x, mode);
7751 return (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))
7752 ? 1 : bitwidth - floor_log2 (nonzero) - 1);
7755 /* Return the number of "extended" bits there are in X, when interpreted
7756 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
7757 unsigned quantities, this is the number of high-order zero bits.
7758 For signed quantities, this is the number of copies of the sign bit
7759 minus 1. In both case, this function returns the number of "spare"
7760 bits. For example, if two quantities for which this function returns
7761 at least 1 are added, the addition is known not to overflow.
7763 This function will always return 0 unless called during combine, which
7764 implies that it must be called from a define_split. */
7767 extended_count (x, mode, unsignedp)
7769 enum machine_mode mode;
7772 if (nonzero_sign_valid == 0)
7776 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7777 && (GET_MODE_BITSIZE (mode) - 1
7778 - floor_log2 (nonzero_bits (x, mode))))
7779 : num_sign_bit_copies (x, mode) - 1);
7782 /* This function is called from `simplify_shift_const' to merge two
7783 outer operations. Specifically, we have already found that we need
7784 to perform operation *POP0 with constant *PCONST0 at the outermost
7785 position. We would now like to also perform OP1 with constant CONST1
7786 (with *POP0 being done last).
7788 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
7789 the resulting operation. *PCOMP_P is set to 1 if we would need to
7790 complement the innermost operand, otherwise it is unchanged.
7792 MODE is the mode in which the operation will be done. No bits outside
7793 the width of this mode matter. It is assumed that the width of this mode
7794 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
7796 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
7797 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
7798 result is simply *PCONST0.
7800 If the resulting operation cannot be expressed as one operation, we
7801 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
7804 merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p)
7805 enum rtx_code *pop0;
7806 HOST_WIDE_INT *pconst0;
7808 HOST_WIDE_INT const1;
7809 enum machine_mode mode;
7812 enum rtx_code op0 = *pop0;
7813 HOST_WIDE_INT const0 = *pconst0;
7814 int width = GET_MODE_BITSIZE (mode);
7816 const0 &= GET_MODE_MASK (mode);
7817 const1 &= GET_MODE_MASK (mode);
7819 /* If OP0 is an AND, clear unimportant bits in CONST1. */
7823 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
7826 if (op1 == NIL || op0 == SET)
7829 else if (op0 == NIL)
7830 op0 = op1, const0 = const1;
7832 else if (op0 == op1)
7854 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
7855 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
7858 /* If the two constants aren't the same, we can't do anything. The
7859 remaining six cases can all be done. */
7860 else if (const0 != const1)
7868 /* (a & b) | b == b */
7870 else /* op1 == XOR */
7871 /* (a ^ b) | b == a | b */
7877 /* (a & b) ^ b == (~a) & b */
7878 op0 = AND, *pcomp_p = 1;
7879 else /* op1 == IOR */
7880 /* (a | b) ^ b == a & ~b */
7881 op0 = AND, *pconst0 = ~ const0;
7886 /* (a | b) & b == b */
7888 else /* op1 == XOR */
7889 /* (a ^ b) & b) == (~a) & b */
7894 /* Check for NO-OP cases. */
7895 const0 &= GET_MODE_MASK (mode);
7897 && (op0 == IOR || op0 == XOR || op0 == PLUS))
7899 else if (const0 == 0 && op0 == AND)
7901 else if (const0 == GET_MODE_MASK (mode) && op0 == AND)
7904 /* If this would be an entire word for the target, but is not for
7905 the host, then sign-extend on the host so that the number will look
7906 the same way on the host that it would on the target.
7908 For example, when building a 64 bit alpha hosted 32 bit sparc
7909 targeted compiler, then we want the 32 bit unsigned value -1 to be
7910 represented as a 64 bit value -1, and not as 0x00000000ffffffff.
7911 The later confuses the sparc backend. */
7913 if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT && BITS_PER_WORD == width
7914 && (const0 & ((HOST_WIDE_INT) 1 << (width - 1))))
7915 const0 |= ((HOST_WIDE_INT) (-1) << width);
7923 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
7924 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
7925 that we started with.
7927 The shift is normally computed in the widest mode we find in VAROP, as
7928 long as it isn't a different number of words than RESULT_MODE. Exceptions
7929 are ASHIFTRT and ROTATE, which are always done in their original mode, */
7932 simplify_shift_const (x, code, result_mode, varop, count)
7935 enum machine_mode result_mode;
7939 enum rtx_code orig_code = code;
7940 int orig_count = count;
7941 enum machine_mode mode = result_mode;
7942 enum machine_mode shift_mode, tmode;
7944 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
7945 /* We form (outer_op (code varop count) (outer_const)). */
7946 enum rtx_code outer_op = NIL;
7947 HOST_WIDE_INT outer_const = 0;
7949 int complement_p = 0;
7952 /* If we were given an invalid count, don't do anything except exactly
7953 what was requested. */
7955 if (count < 0 || count > GET_MODE_BITSIZE (mode))
7960 return gen_rtx (code, mode, varop, GEN_INT (count));
7963 /* Unless one of the branches of the `if' in this loop does a `continue',
7964 we will `break' the loop after the `if'. */
7968 /* If we have an operand of (clobber (const_int 0)), just return that
7970 if (GET_CODE (varop) == CLOBBER)
7973 /* If we discovered we had to complement VAROP, leave. Making a NOT
7974 here would cause an infinite loop. */
7978 /* Convert ROTATERT to ROTATE. */
7979 if (code == ROTATERT)
7980 code = ROTATE, count = GET_MODE_BITSIZE (result_mode) - count;
7982 /* We need to determine what mode we will do the shift in. If the
7983 shift is a right shift or a ROTATE, we must always do it in the mode
7984 it was originally done in. Otherwise, we can do it in MODE, the
7985 widest mode encountered. */
7987 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
7988 ? result_mode : mode);
7990 /* Handle cases where the count is greater than the size of the mode
7991 minus 1. For ASHIFT, use the size minus one as the count (this can
7992 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
7993 take the count modulo the size. For other shifts, the result is
7996 Since these shifts are being produced by the compiler by combining
7997 multiple operations, each of which are defined, we know what the
7998 result is supposed to be. */
8000 if (count > GET_MODE_BITSIZE (shift_mode) - 1)
8002 if (code == ASHIFTRT)
8003 count = GET_MODE_BITSIZE (shift_mode) - 1;
8004 else if (code == ROTATE || code == ROTATERT)
8005 count %= GET_MODE_BITSIZE (shift_mode);
8008 /* We can't simply return zero because there may be an
8016 /* Negative counts are invalid and should not have been made (a
8017 programmer-specified negative count should have been handled
8022 /* An arithmetic right shift of a quantity known to be -1 or 0
8024 if (code == ASHIFTRT
8025 && (num_sign_bit_copies (varop, shift_mode)
8026 == GET_MODE_BITSIZE (shift_mode)))
8032 /* If we are doing an arithmetic right shift and discarding all but
8033 the sign bit copies, this is equivalent to doing a shift by the
8034 bitsize minus one. Convert it into that shift because it will often
8035 allow other simplifications. */
8037 if (code == ASHIFTRT
8038 && (count + num_sign_bit_copies (varop, shift_mode)
8039 >= GET_MODE_BITSIZE (shift_mode)))
8040 count = GET_MODE_BITSIZE (shift_mode) - 1;
8042 /* We simplify the tests below and elsewhere by converting
8043 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8044 `make_compound_operation' will convert it to a ASHIFTRT for
8045 those machines (such as Vax) that don't have a LSHIFTRT. */
8046 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8048 && ((nonzero_bits (varop, shift_mode)
8049 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
8053 switch (GET_CODE (varop))
8059 new = expand_compound_operation (varop);
8068 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8069 minus the width of a smaller mode, we can do this with a
8070 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
8071 if ((code == ASHIFTRT || code == LSHIFTRT)
8072 && ! mode_dependent_address_p (XEXP (varop, 0))
8073 && ! MEM_VOLATILE_P (varop)
8074 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8075 MODE_INT, 1)) != BLKmode)
8077 if (BYTES_BIG_ENDIAN)
8078 new = gen_rtx (MEM, tmode, XEXP (varop, 0));
8080 new = gen_rtx (MEM, tmode,
8081 plus_constant (XEXP (varop, 0),
8082 count / BITS_PER_UNIT));
8083 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (varop);
8084 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (varop);
8085 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (varop);
8086 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
8087 : ZERO_EXTEND, mode, new);
8094 /* Similar to the case above, except that we can only do this if
8095 the resulting mode is the same as that of the underlying
8096 MEM and adjust the address depending on the *bits* endianness
8097 because of the way that bit-field extract insns are defined. */
8098 if ((code == ASHIFTRT || code == LSHIFTRT)
8099 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8100 MODE_INT, 1)) != BLKmode
8101 && tmode == GET_MODE (XEXP (varop, 0)))
8103 if (BITS_BIG_ENDIAN)
8104 new = XEXP (varop, 0);
8107 new = copy_rtx (XEXP (varop, 0));
8108 SUBST (XEXP (new, 0),
8109 plus_constant (XEXP (new, 0),
8110 count / BITS_PER_UNIT));
8113 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
8114 : ZERO_EXTEND, mode, new);
8121 /* If VAROP is a SUBREG, strip it as long as the inner operand has
8122 the same number of words as what we've seen so far. Then store
8123 the widest mode in MODE. */
8124 if (subreg_lowpart_p (varop)
8125 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8126 > GET_MODE_SIZE (GET_MODE (varop)))
8127 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8128 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
8131 varop = SUBREG_REG (varop);
8132 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
8133 mode = GET_MODE (varop);
8139 /* Some machines use MULT instead of ASHIFT because MULT
8140 is cheaper. But it is still better on those machines to
8141 merge two shifts into one. */
8142 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8143 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8145 varop = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
8146 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));;
8152 /* Similar, for when divides are cheaper. */
8153 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8154 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8156 varop = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
8157 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
8163 /* If we are extracting just the sign bit of an arithmetic right
8164 shift, that shift is not needed. */
8165 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1)
8167 varop = XEXP (varop, 0);
8171 /* ... fall through ... */
8176 /* Here we have two nested shifts. The result is usually the
8177 AND of a new shift with a mask. We compute the result below. */
8178 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8179 && INTVAL (XEXP (varop, 1)) >= 0
8180 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
8181 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8182 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
8184 enum rtx_code first_code = GET_CODE (varop);
8185 int first_count = INTVAL (XEXP (varop, 1));
8186 unsigned HOST_WIDE_INT mask;
8189 /* We have one common special case. We can't do any merging if
8190 the inner code is an ASHIFTRT of a smaller mode. However, if
8191 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
8192 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
8193 we can convert it to
8194 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
8195 This simplifies certain SIGN_EXTEND operations. */
8196 if (code == ASHIFT && first_code == ASHIFTRT
8197 && (GET_MODE_BITSIZE (result_mode)
8198 - GET_MODE_BITSIZE (GET_MODE (varop))) == count)
8200 /* C3 has the low-order C1 bits zero. */
8202 mask = (GET_MODE_MASK (mode)
8203 & ~ (((HOST_WIDE_INT) 1 << first_count) - 1));
8205 varop = simplify_and_const_int (NULL_RTX, result_mode,
8206 XEXP (varop, 0), mask);
8207 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
8209 count = first_count;
8214 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
8215 than C1 high-order bits equal to the sign bit, we can convert
8216 this to either an ASHIFT or a ASHIFTRT depending on the
8219 We cannot do this if VAROP's mode is not SHIFT_MODE. */
8221 if (code == ASHIFTRT && first_code == ASHIFT
8222 && GET_MODE (varop) == shift_mode
8223 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
8226 count -= first_count;
8228 count = - count, code = ASHIFT;
8229 varop = XEXP (varop, 0);
8233 /* There are some cases we can't do. If CODE is ASHIFTRT,
8234 we can only do this if FIRST_CODE is also ASHIFTRT.
8236 We can't do the case when CODE is ROTATE and FIRST_CODE is
8239 If the mode of this shift is not the mode of the outer shift,
8240 we can't do this if either shift is a right shift or ROTATE.
8242 Finally, we can't do any of these if the mode is too wide
8243 unless the codes are the same.
8245 Handle the case where the shift codes are the same
8248 if (code == first_code)
8250 if (GET_MODE (varop) != result_mode
8251 && (code == ASHIFTRT || code == LSHIFTRT
8255 count += first_count;
8256 varop = XEXP (varop, 0);
8260 if (code == ASHIFTRT
8261 || (code == ROTATE && first_code == ASHIFTRT)
8262 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
8263 || (GET_MODE (varop) != result_mode
8264 && (first_code == ASHIFTRT || first_code == LSHIFTRT
8265 || first_code == ROTATE
8266 || code == ROTATE)))
8269 /* To compute the mask to apply after the shift, shift the
8270 nonzero bits of the inner shift the same way the
8271 outer shift will. */
8273 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
8276 = simplify_binary_operation (code, result_mode, mask_rtx,
8279 /* Give up if we can't compute an outer operation to use. */
8281 || GET_CODE (mask_rtx) != CONST_INT
8282 || ! merge_outer_ops (&outer_op, &outer_const, AND,
8284 result_mode, &complement_p))
8287 /* If the shifts are in the same direction, we add the
8288 counts. Otherwise, we subtract them. */
8289 if ((code == ASHIFTRT || code == LSHIFTRT)
8290 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
8291 count += first_count;
8293 count -= first_count;
8295 /* If COUNT is positive, the new shift is usually CODE,
8296 except for the two exceptions below, in which case it is
8297 FIRST_CODE. If the count is negative, FIRST_CODE should
8300 && ((first_code == ROTATE && code == ASHIFT)
8301 || (first_code == ASHIFTRT && code == LSHIFTRT)))
8304 code = first_code, count = - count;
8306 varop = XEXP (varop, 0);
8310 /* If we have (A << B << C) for any shift, we can convert this to
8311 (A << C << B). This wins if A is a constant. Only try this if
8312 B is not a constant. */
8314 else if (GET_CODE (varop) == code
8315 && GET_CODE (XEXP (varop, 1)) != CONST_INT
8317 = simplify_binary_operation (code, mode,
8321 varop = gen_rtx_combine (code, mode, new, XEXP (varop, 1));
8328 /* Make this fit the case below. */
8329 varop = gen_rtx_combine (XOR, mode, XEXP (varop, 0),
8330 GEN_INT (GET_MODE_MASK (mode)));
8336 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
8337 with C the size of VAROP - 1 and the shift is logical if
8338 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8339 we have an (le X 0) operation. If we have an arithmetic shift
8340 and STORE_FLAG_VALUE is 1 or we have a logical shift with
8341 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
8343 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
8344 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
8345 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8346 && (code == LSHIFTRT || code == ASHIFTRT)
8347 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
8348 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8351 varop = gen_rtx_combine (LE, GET_MODE (varop), XEXP (varop, 1),
8354 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8355 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
8360 /* If we have (shift (logical)), move the logical to the outside
8361 to allow it to possibly combine with another logical and the
8362 shift to combine with another shift. This also canonicalizes to
8363 what a ZERO_EXTRACT looks like. Also, some machines have
8364 (and (shift)) insns. */
8366 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8367 && (new = simplify_binary_operation (code, result_mode,
8369 GEN_INT (count))) != 0
8370 && GET_CODE(new) == CONST_INT
8371 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
8372 INTVAL (new), result_mode, &complement_p))
8374 varop = XEXP (varop, 0);
8378 /* If we can't do that, try to simplify the shift in each arm of the
8379 logical expression, make a new logical expression, and apply
8380 the inverse distributive law. */
8382 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8383 XEXP (varop, 0), count);
8384 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8385 XEXP (varop, 1), count);
8387 varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs);
8388 varop = apply_distributive_law (varop);
8395 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
8396 says that the sign bit can be tested, FOO has mode MODE, C is
8397 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
8398 that may be nonzero. */
8399 if (code == LSHIFTRT
8400 && XEXP (varop, 1) == const0_rtx
8401 && GET_MODE (XEXP (varop, 0)) == result_mode
8402 && count == GET_MODE_BITSIZE (result_mode) - 1
8403 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8404 && ((STORE_FLAG_VALUE
8405 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (result_mode) - 1))))
8406 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
8407 && merge_outer_ops (&outer_op, &outer_const, XOR,
8408 (HOST_WIDE_INT) 1, result_mode,
8411 varop = XEXP (varop, 0);
8418 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
8419 than the number of bits in the mode is equivalent to A. */
8420 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
8421 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
8423 varop = XEXP (varop, 0);
8428 /* NEG commutes with ASHIFT since it is multiplication. Move the
8429 NEG outside to allow shifts to combine. */
8431 && merge_outer_ops (&outer_op, &outer_const, NEG,
8432 (HOST_WIDE_INT) 0, result_mode,
8435 varop = XEXP (varop, 0);
8441 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
8442 is one less than the number of bits in the mode is
8443 equivalent to (xor A 1). */
8444 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
8445 && XEXP (varop, 1) == constm1_rtx
8446 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
8447 && merge_outer_ops (&outer_op, &outer_const, XOR,
8448 (HOST_WIDE_INT) 1, result_mode,
8452 varop = XEXP (varop, 0);
8456 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
8457 that might be nonzero in BAR are those being shifted out and those
8458 bits are known zero in FOO, we can replace the PLUS with FOO.
8459 Similarly in the other operand order. This code occurs when
8460 we are computing the size of a variable-size array. */
8462 if ((code == ASHIFTRT || code == LSHIFTRT)
8463 && count < HOST_BITS_PER_WIDE_INT
8464 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
8465 && (nonzero_bits (XEXP (varop, 1), result_mode)
8466 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
8468 varop = XEXP (varop, 0);
8471 else if ((code == ASHIFTRT || code == LSHIFTRT)
8472 && count < HOST_BITS_PER_WIDE_INT
8473 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8474 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
8476 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
8477 & nonzero_bits (XEXP (varop, 1),
8480 varop = XEXP (varop, 1);
8484 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
8486 && GET_CODE (XEXP (varop, 1)) == CONST_INT
8487 && (new = simplify_binary_operation (ASHIFT, result_mode,
8489 GEN_INT (count))) != 0
8490 && GET_CODE(new) == CONST_INT
8491 && merge_outer_ops (&outer_op, &outer_const, PLUS,
8492 INTVAL (new), result_mode, &complement_p))
8494 varop = XEXP (varop, 0);
8500 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
8501 with C the size of VAROP - 1 and the shift is logical if
8502 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8503 we have a (gt X 0) operation. If the shift is arithmetic with
8504 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
8505 we have a (neg (gt X 0)) operation. */
8507 if (GET_CODE (XEXP (varop, 0)) == ASHIFTRT
8508 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
8509 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8510 && (code == LSHIFTRT || code == ASHIFTRT)
8511 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
8512 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
8513 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8516 varop = gen_rtx_combine (GT, GET_MODE (varop), XEXP (varop, 1),
8519 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8520 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
8530 /* We need to determine what mode to do the shift in. If the shift is
8531 a right shift or ROTATE, we must always do it in the mode it was
8532 originally done in. Otherwise, we can do it in MODE, the widest mode
8533 encountered. The code we care about is that of the shift that will
8534 actually be done, not the shift that was originally requested. */
8536 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8537 ? result_mode : mode);
8539 /* We have now finished analyzing the shift. The result should be
8540 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
8541 OUTER_OP is non-NIL, it is an operation that needs to be applied
8542 to the result of the shift. OUTER_CONST is the relevant constant,
8543 but we must turn off all bits turned off in the shift.
8545 If we were passed a value for X, see if we can use any pieces of
8546 it. If not, make new rtx. */
8548 if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
8549 && GET_CODE (XEXP (x, 1)) == CONST_INT
8550 && INTVAL (XEXP (x, 1)) == count)
8551 const_rtx = XEXP (x, 1);
8553 const_rtx = GEN_INT (count);
8555 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
8556 && GET_MODE (XEXP (x, 0)) == shift_mode
8557 && SUBREG_REG (XEXP (x, 0)) == varop)
8558 varop = XEXP (x, 0);
8559 else if (GET_MODE (varop) != shift_mode)
8560 varop = gen_lowpart_for_combine (shift_mode, varop);
8562 /* If we can't make the SUBREG, try to return what we were given. */
8563 if (GET_CODE (varop) == CLOBBER)
8564 return x ? x : varop;
8566 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
8571 if (x == 0 || GET_CODE (x) != code || GET_MODE (x) != shift_mode)
8572 x = gen_rtx_combine (code, shift_mode, varop, const_rtx);
8574 SUBST (XEXP (x, 0), varop);
8575 SUBST (XEXP (x, 1), const_rtx);
8578 /* If we have an outer operation and we just made a shift, it is
8579 possible that we could have simplified the shift were it not
8580 for the outer operation. So try to do the simplification
8583 if (outer_op != NIL && GET_CODE (x) == code
8584 && GET_CODE (XEXP (x, 1)) == CONST_INT)
8585 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
8586 INTVAL (XEXP (x, 1)));
8588 /* If we were doing a LSHIFTRT in a wider mode than it was originally,
8589 turn off all the bits that the shift would have turned off. */
8590 if (orig_code == LSHIFTRT && result_mode != shift_mode)
8591 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
8592 GET_MODE_MASK (result_mode) >> orig_count);
8594 /* Do the remainder of the processing in RESULT_MODE. */
8595 x = gen_lowpart_for_combine (result_mode, x);
8597 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
8600 x = gen_unary (NOT, result_mode, result_mode, x);
8602 if (outer_op != NIL)
8604 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
8606 int width = GET_MODE_BITSIZE (result_mode);
8608 outer_const &= GET_MODE_MASK (result_mode);
8610 /* If this would be an entire word for the target, but is not for
8611 the host, then sign-extend on the host so that the number will
8612 look the same way on the host that it would on the target.
8614 For example, when building a 64 bit alpha hosted 32 bit sparc
8615 targeted compiler, then we want the 32 bit unsigned value -1 to be
8616 represented as a 64 bit value -1, and not as 0x00000000ffffffff.
8617 The later confuses the sparc backend. */
8619 if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT && BITS_PER_WORD == width
8620 && (outer_const & ((HOST_WIDE_INT) 1 << (width - 1))))
8621 outer_const |= ((HOST_WIDE_INT) (-1) << width);
8624 if (outer_op == AND)
8625 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
8626 else if (outer_op == SET)
8627 /* This means that we have determined that the result is
8628 equivalent to a constant. This should be rare. */
8629 x = GEN_INT (outer_const);
8630 else if (GET_RTX_CLASS (outer_op) == '1')
8631 x = gen_unary (outer_op, result_mode, result_mode, x);
8633 x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
8639 /* Like recog, but we receive the address of a pointer to a new pattern.
8640 We try to match the rtx that the pointer points to.
8641 If that fails, we may try to modify or replace the pattern,
8642 storing the replacement into the same pointer object.
8644 Modifications include deletion or addition of CLOBBERs.
8646 PNOTES is a pointer to a location where any REG_UNUSED notes added for
8647 the CLOBBERs are placed.
8649 PADDED_SCRATCHES is set to the number of (clobber (scratch)) patterns
8652 The value is the final insn code from the pattern ultimately matched,
8656 recog_for_combine (pnewpat, insn, pnotes, padded_scratches)
8660 int *padded_scratches;
8662 register rtx pat = *pnewpat;
8663 int insn_code_number;
8664 int num_clobbers_to_add = 0;
8668 *padded_scratches = 0;
8670 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
8671 we use to indicate that something didn't match. If we find such a
8672 thing, force rejection. */
8673 if (GET_CODE (pat) == PARALLEL)
8674 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
8675 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
8676 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
8679 /* Is the result of combination a valid instruction? */
8680 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
8682 /* If it isn't, there is the possibility that we previously had an insn
8683 that clobbered some register as a side effect, but the combined
8684 insn doesn't need to do that. So try once more without the clobbers
8685 unless this represents an ASM insn. */
8687 if (insn_code_number < 0 && ! check_asm_operands (pat)
8688 && GET_CODE (pat) == PARALLEL)
8692 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
8693 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
8696 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
8700 SUBST_INT (XVECLEN (pat, 0), pos);
8703 pat = XVECEXP (pat, 0, 0);
8705 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
8708 /* If we had any clobbers to add, make a new pattern than contains
8709 them. Then check to make sure that all of them are dead. */
8710 if (num_clobbers_to_add)
8712 rtx newpat = gen_rtx (PARALLEL, VOIDmode,
8713 gen_rtvec (GET_CODE (pat) == PARALLEL
8714 ? XVECLEN (pat, 0) + num_clobbers_to_add
8715 : num_clobbers_to_add + 1));
8717 if (GET_CODE (pat) == PARALLEL)
8718 for (i = 0; i < XVECLEN (pat, 0); i++)
8719 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
8721 XVECEXP (newpat, 0, 0) = pat;
8723 add_clobbers (newpat, insn_code_number);
8725 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
8726 i < XVECLEN (newpat, 0); i++)
8728 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
8729 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
8731 else if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == SCRATCH)
8732 (*padded_scratches)++;
8733 notes = gen_rtx (EXPR_LIST, REG_UNUSED,
8734 XEXP (XVECEXP (newpat, 0, i), 0), notes);
8742 return insn_code_number;
8745 /* Like gen_lowpart but for use by combine. In combine it is not possible
8746 to create any new pseudoregs. However, it is safe to create
8747 invalid memory addresses, because combine will try to recognize
8748 them and all they will do is make the combine attempt fail.
8750 If for some reason this cannot do its job, an rtx
8751 (clobber (const_int 0)) is returned.
8752 An insn containing that will not be recognized. */
8757 gen_lowpart_for_combine (mode, x)
8758 enum machine_mode mode;
8763 if (GET_MODE (x) == mode)
8766 /* We can only support MODE being wider than a word if X is a
8767 constant integer or has a mode the same size. */
8769 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
8770 && ! ((GET_MODE (x) == VOIDmode
8771 && (GET_CODE (x) == CONST_INT
8772 || GET_CODE (x) == CONST_DOUBLE))
8773 || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
8774 return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
8776 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
8777 won't know what to do. So we will strip off the SUBREG here and
8778 process normally. */
8779 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
8782 if (GET_MODE (x) == mode)
8786 result = gen_lowpart_common (mode, x);
8788 && GET_CODE (result) == SUBREG
8789 && GET_CODE (SUBREG_REG (result)) == REG
8790 && REGNO (SUBREG_REG (result)) >= FIRST_PSEUDO_REGISTER
8791 && (GET_MODE_SIZE (GET_MODE (result))
8792 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (result)))))
8793 reg_changes_size[REGNO (SUBREG_REG (result))] = 1;
8798 if (GET_CODE (x) == MEM)
8800 register int offset = 0;
8803 /* Refuse to work on a volatile memory ref or one with a mode-dependent
8805 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
8806 return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
8808 /* If we want to refer to something bigger than the original memref,
8809 generate a perverse subreg instead. That will force a reload
8810 of the original memref X. */
8811 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
8812 return gen_rtx (SUBREG, mode, x, 0);
8814 if (WORDS_BIG_ENDIAN)
8815 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
8816 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
8817 if (BYTES_BIG_ENDIAN)
8819 /* Adjust the address so that the address-after-the-data is
8821 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
8822 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
8824 new = gen_rtx (MEM, mode, plus_constant (XEXP (x, 0), offset));
8825 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (x);
8826 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (x);
8827 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (x);
8831 /* If X is a comparison operator, rewrite it in a new mode. This
8832 probably won't match, but may allow further simplifications. */
8833 else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
8834 return gen_rtx_combine (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
8836 /* If we couldn't simplify X any other way, just enclose it in a
8837 SUBREG. Normally, this SUBREG won't match, but some patterns may
8838 include an explicit SUBREG or we may simplify it further in combine. */
8843 if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
8844 word = ((GET_MODE_SIZE (GET_MODE (x))
8845 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
8847 return gen_rtx (SUBREG, mode, x, word);
8851 /* Make an rtx expression. This is a subset of gen_rtx and only supports
8852 expressions of 1, 2, or 3 operands, each of which are rtx expressions.
8854 If the identical expression was previously in the insn (in the undobuf),
8855 it will be returned. Only if it is not found will a new expression
8860 gen_rtx_combine VPROTO((enum rtx_code code, enum machine_mode mode, ...))
8864 enum machine_mode mode;
8877 code = va_arg (p, enum rtx_code);
8878 mode = va_arg (p, enum machine_mode);
8881 n_args = GET_RTX_LENGTH (code);
8882 fmt = GET_RTX_FORMAT (code);
8884 if (n_args == 0 || n_args > 3)
8887 /* Get each arg and verify that it is supposed to be an expression. */
8888 for (j = 0; j < n_args; j++)
8893 args[j] = va_arg (p, rtx);
8896 /* See if this is in undobuf. Be sure we don't use objects that came
8897 from another insn; this could produce circular rtl structures. */
8899 for (undo = undobuf.undos; undo != undobuf.previous_undos; undo = undo->next)
8901 && GET_CODE (undo->old_contents.r) == code
8902 && GET_MODE (undo->old_contents.r) == mode)
8904 for (j = 0; j < n_args; j++)
8905 if (XEXP (undo->old_contents.r, j) != args[j])
8909 return undo->old_contents.r;
8912 /* Otherwise make a new rtx. We know we have 1, 2, or 3 args.
8913 Use rtx_alloc instead of gen_rtx because it's faster on RISC. */
8914 rt = rtx_alloc (code);
8915 PUT_MODE (rt, mode);
8916 XEXP (rt, 0) = args[0];
8919 XEXP (rt, 1) = args[1];
8921 XEXP (rt, 2) = args[2];
8926 /* These routines make binary and unary operations by first seeing if they
8927 fold; if not, a new expression is allocated. */
8930 gen_binary (code, mode, op0, op1)
8932 enum machine_mode mode;
8938 if (GET_RTX_CLASS (code) == 'c'
8939 && (GET_CODE (op0) == CONST_INT
8940 || (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)))
8941 tem = op0, op0 = op1, op1 = tem;
8943 if (GET_RTX_CLASS (code) == '<')
8945 enum machine_mode op_mode = GET_MODE (op0);
8947 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
8948 just (REL_OP X Y). */
8949 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
8951 op1 = XEXP (op0, 1);
8952 op0 = XEXP (op0, 0);
8953 op_mode = GET_MODE (op0);
8956 if (op_mode == VOIDmode)
8957 op_mode = GET_MODE (op1);
8958 result = simplify_relational_operation (code, op_mode, op0, op1);
8961 result = simplify_binary_operation (code, mode, op0, op1);
8966 /* Put complex operands first and constants second. */
8967 if (GET_RTX_CLASS (code) == 'c'
8968 && ((CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
8969 || (GET_RTX_CLASS (GET_CODE (op0)) == 'o'
8970 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')
8971 || (GET_CODE (op0) == SUBREG
8972 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (op0))) == 'o'
8973 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')))
8974 return gen_rtx_combine (code, mode, op1, op0);
8976 return gen_rtx_combine (code, mode, op0, op1);
8980 gen_unary (code, mode, op0_mode, op0)
8982 enum machine_mode mode, op0_mode;
8985 rtx result = simplify_unary_operation (code, mode, op0, op0_mode);
8990 return gen_rtx_combine (code, mode, op0);
8993 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
8994 comparison code that will be tested.
8996 The result is a possibly different comparison code to use. *POP0 and
8997 *POP1 may be updated.
8999 It is possible that we might detect that a comparison is either always
9000 true or always false. However, we do not perform general constant
9001 folding in combine, so this knowledge isn't useful. Such tautologies
9002 should have been detected earlier. Hence we ignore all such cases. */
9004 static enum rtx_code
9005 simplify_comparison (code, pop0, pop1)
9014 enum machine_mode mode, tmode;
9016 /* Try a few ways of applying the same transformation to both operands. */
9019 #ifndef WORD_REGISTER_OPERATIONS
9020 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9021 so check specially. */
9022 if (code != GTU && code != GEU && code != LTU && code != LEU
9023 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9024 && GET_CODE (XEXP (op0, 0)) == ASHIFT
9025 && GET_CODE (XEXP (op1, 0)) == ASHIFT
9026 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9027 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9028 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
9029 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
9030 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9031 && GET_CODE (XEXP (op1, 1)) == CONST_INT
9032 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
9033 && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT
9034 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (op1, 1))
9035 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op0, 0), 1))
9036 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op1, 0), 1))
9037 && (INTVAL (XEXP (op0, 1))
9038 == (GET_MODE_BITSIZE (GET_MODE (op0))
9040 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
9042 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
9043 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
9047 /* If both operands are the same constant shift, see if we can ignore the
9048 shift. We can if the shift is a rotate or if the bits shifted out of
9049 this shift are known to be zero for both inputs and if the type of
9050 comparison is compatible with the shift. */
9051 if (GET_CODE (op0) == GET_CODE (op1)
9052 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9053 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
9054 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
9055 && (code != GT && code != LT && code != GE && code != LE))
9056 || (GET_CODE (op0) == ASHIFTRT
9057 && (code != GTU && code != LTU
9058 && code != GEU && code != GEU)))
9059 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9060 && INTVAL (XEXP (op0, 1)) >= 0
9061 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9062 && XEXP (op0, 1) == XEXP (op1, 1))
9064 enum machine_mode mode = GET_MODE (op0);
9065 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9066 int shift_count = INTVAL (XEXP (op0, 1));
9068 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
9069 mask &= (mask >> shift_count) << shift_count;
9070 else if (GET_CODE (op0) == ASHIFT)
9071 mask = (mask & (mask << shift_count)) >> shift_count;
9073 if ((nonzero_bits (XEXP (op0, 0), mode) & ~ mask) == 0
9074 && (nonzero_bits (XEXP (op1, 0), mode) & ~ mask) == 0)
9075 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
9080 /* If both operands are AND's of a paradoxical SUBREG by constant, the
9081 SUBREGs are of the same mode, and, in both cases, the AND would
9082 be redundant if the comparison was done in the narrower mode,
9083 do the comparison in the narrower mode (e.g., we are AND'ing with 1
9084 and the operand's possibly nonzero bits are 0xffffff01; in that case
9085 if we only care about QImode, we don't need the AND). This case
9086 occurs if the output mode of an scc insn is not SImode and
9087 STORE_FLAG_VALUE == 1 (e.g., the 386).
9089 Similarly, check for a case where the AND's are ZERO_EXTEND
9090 operations from some narrower mode even though a SUBREG is not
9093 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
9094 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9095 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
9097 rtx inner_op0 = XEXP (op0, 0);
9098 rtx inner_op1 = XEXP (op1, 0);
9099 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
9100 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
9103 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
9104 && (GET_MODE_SIZE (GET_MODE (inner_op0))
9105 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
9106 && (GET_MODE (SUBREG_REG (inner_op0))
9107 == GET_MODE (SUBREG_REG (inner_op1)))
9108 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
9109 <= HOST_BITS_PER_WIDE_INT)
9110 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
9111 GET_MODE (SUBREG_REG (op0)))))
9112 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
9113 GET_MODE (SUBREG_REG (inner_op1))))))
9115 op0 = SUBREG_REG (inner_op0);
9116 op1 = SUBREG_REG (inner_op1);
9118 /* The resulting comparison is always unsigned since we masked
9119 off the original sign bit. */
9120 code = unsigned_condition (code);
9126 for (tmode = GET_CLASS_NARROWEST_MODE
9127 (GET_MODE_CLASS (GET_MODE (op0)));
9128 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
9129 if (c0 == GET_MODE_MASK (tmode))
9131 op0 = gen_lowpart_for_combine (tmode, inner_op0);
9132 op1 = gen_lowpart_for_combine (tmode, inner_op1);
9133 code = unsigned_condition (code);
9142 /* If both operands are NOT, we can strip off the outer operation
9143 and adjust the comparison code for swapped operands; similarly for
9144 NEG, except that this must be an equality comparison. */
9145 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
9146 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
9147 && (code == EQ || code == NE)))
9148 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
9154 /* If the first operand is a constant, swap the operands and adjust the
9155 comparison code appropriately, but don't do this if the second operand
9156 is already a constant integer. */
9157 if (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
9159 tem = op0, op0 = op1, op1 = tem;
9160 code = swap_condition (code);
9163 /* We now enter a loop during which we will try to simplify the comparison.
9164 For the most part, we only are concerned with comparisons with zero,
9165 but some things may really be comparisons with zero but not start
9166 out looking that way. */
9168 while (GET_CODE (op1) == CONST_INT)
9170 enum machine_mode mode = GET_MODE (op0);
9171 int mode_width = GET_MODE_BITSIZE (mode);
9172 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9173 int equality_comparison_p;
9174 int sign_bit_comparison_p;
9175 int unsigned_comparison_p;
9176 HOST_WIDE_INT const_op;
9178 /* We only want to handle integral modes. This catches VOIDmode,
9179 CCmode, and the floating-point modes. An exception is that we
9180 can handle VOIDmode if OP0 is a COMPARE or a comparison
9183 if (GET_MODE_CLASS (mode) != MODE_INT
9184 && ! (mode == VOIDmode
9185 && (GET_CODE (op0) == COMPARE
9186 || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
9189 /* Get the constant we are comparing against and turn off all bits
9190 not on in our mode. */
9191 const_op = INTVAL (op1);
9192 if (mode_width <= HOST_BITS_PER_WIDE_INT)
9195 /* If we are comparing against a constant power of two and the value
9196 being compared can only have that single bit nonzero (e.g., it was
9197 `and'ed with that bit), we can replace this with a comparison
9200 && (code == EQ || code == NE || code == GE || code == GEU
9201 || code == LT || code == LTU)
9202 && mode_width <= HOST_BITS_PER_WIDE_INT
9203 && exact_log2 (const_op) >= 0
9204 && nonzero_bits (op0, mode) == const_op)
9206 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
9207 op1 = const0_rtx, const_op = 0;
9210 /* Similarly, if we are comparing a value known to be either -1 or
9211 0 with -1, change it to the opposite comparison against zero. */
9214 && (code == EQ || code == NE || code == GT || code == LE
9215 || code == GEU || code == LTU)
9216 && num_sign_bit_copies (op0, mode) == mode_width)
9218 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
9219 op1 = const0_rtx, const_op = 0;
9222 /* Do some canonicalizations based on the comparison code. We prefer
9223 comparisons against zero and then prefer equality comparisons.
9224 If we can reduce the size of a constant, we will do that too. */
9229 /* < C is equivalent to <= (C - 1) */
9233 op1 = GEN_INT (const_op);
9235 /* ... fall through to LE case below. */
9241 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
9245 op1 = GEN_INT (const_op);
9249 /* If we are doing a <= 0 comparison on a value known to have
9250 a zero sign bit, we can replace this with == 0. */
9251 else if (const_op == 0
9252 && mode_width <= HOST_BITS_PER_WIDE_INT
9253 && (nonzero_bits (op0, mode)
9254 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9259 /* >= C is equivalent to > (C - 1). */
9263 op1 = GEN_INT (const_op);
9265 /* ... fall through to GT below. */
9271 /* > C is equivalent to >= (C + 1); we do this for C < 0*/
9275 op1 = GEN_INT (const_op);
9279 /* If we are doing a > 0 comparison on a value known to have
9280 a zero sign bit, we can replace this with != 0. */
9281 else if (const_op == 0
9282 && mode_width <= HOST_BITS_PER_WIDE_INT
9283 && (nonzero_bits (op0, mode)
9284 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9289 /* < C is equivalent to <= (C - 1). */
9293 op1 = GEN_INT (const_op);
9295 /* ... fall through ... */
9298 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
9299 else if (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1))
9301 const_op = 0, op1 = const0_rtx;
9309 /* unsigned <= 0 is equivalent to == 0 */
9313 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
9314 else if (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
9316 const_op = 0, op1 = const0_rtx;
9322 /* >= C is equivalent to < (C - 1). */
9326 op1 = GEN_INT (const_op);
9328 /* ... fall through ... */
9331 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
9332 else if (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1))
9334 const_op = 0, op1 = const0_rtx;
9342 /* unsigned > 0 is equivalent to != 0 */
9346 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
9347 else if (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
9349 const_op = 0, op1 = const0_rtx;
9355 /* Compute some predicates to simplify code below. */
9357 equality_comparison_p = (code == EQ || code == NE);
9358 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
9359 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
9362 /* If this is a sign bit comparison and we can do arithmetic in
9363 MODE, say that we will only be needing the sign bit of OP0. */
9364 if (sign_bit_comparison_p
9365 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9366 op0 = force_to_mode (op0, mode,
9368 << (GET_MODE_BITSIZE (mode) - 1)),
9371 /* Now try cases based on the opcode of OP0. If none of the cases
9372 does a "continue", we exit this loop immediately after the
9375 switch (GET_CODE (op0))
9378 /* If we are extracting a single bit from a variable position in
9379 a constant that has only a single bit set and are comparing it
9380 with zero, we can convert this into an equality comparison
9381 between the position and the location of the single bit. */
9383 if (GET_CODE (XEXP (op0, 0)) == CONST_INT
9384 && XEXP (op0, 1) == const1_rtx
9385 && equality_comparison_p && const_op == 0
9386 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
9388 if (BITS_BIG_ENDIAN)
9390 i = (GET_MODE_BITSIZE
9391 (insn_operand_mode[(int) CODE_FOR_extzv][1]) - 1 - i);
9393 i = BITS_PER_WORD - 1 - i;
9396 op0 = XEXP (op0, 2);
9400 /* Result is nonzero iff shift count is equal to I. */
9401 code = reverse_condition (code);
9405 /* ... fall through ... */
9408 tem = expand_compound_operation (op0);
9417 /* If testing for equality, we can take the NOT of the constant. */
9418 if (equality_comparison_p
9419 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
9421 op0 = XEXP (op0, 0);
9426 /* If just looking at the sign bit, reverse the sense of the
9428 if (sign_bit_comparison_p)
9430 op0 = XEXP (op0, 0);
9431 code = (code == GE ? LT : GE);
9437 /* If testing for equality, we can take the NEG of the constant. */
9438 if (equality_comparison_p
9439 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
9441 op0 = XEXP (op0, 0);
9446 /* The remaining cases only apply to comparisons with zero. */
9450 /* When X is ABS or is known positive,
9451 (neg X) is < 0 if and only if X != 0. */
9453 if (sign_bit_comparison_p
9454 && (GET_CODE (XEXP (op0, 0)) == ABS
9455 || (mode_width <= HOST_BITS_PER_WIDE_INT
9456 && (nonzero_bits (XEXP (op0, 0), mode)
9457 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
9459 op0 = XEXP (op0, 0);
9460 code = (code == LT ? NE : EQ);
9464 /* If we have NEG of something whose two high-order bits are the
9465 same, we know that "(-a) < 0" is equivalent to "a > 0". */
9466 if (num_sign_bit_copies (op0, mode) >= 2)
9468 op0 = XEXP (op0, 0);
9469 code = swap_condition (code);
9475 /* If we are testing equality and our count is a constant, we
9476 can perform the inverse operation on our RHS. */
9477 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
9478 && (tem = simplify_binary_operation (ROTATERT, mode,
9479 op1, XEXP (op0, 1))) != 0)
9481 op0 = XEXP (op0, 0);
9486 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
9487 a particular bit. Convert it to an AND of a constant of that
9488 bit. This will be converted into a ZERO_EXTRACT. */
9489 if (const_op == 0 && sign_bit_comparison_p
9490 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9491 && mode_width <= HOST_BITS_PER_WIDE_INT)
9493 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
9496 - INTVAL (XEXP (op0, 1)))));
9497 code = (code == LT ? NE : EQ);
9501 /* ... fall through ... */
9504 /* ABS is ignorable inside an equality comparison with zero. */
9505 if (const_op == 0 && equality_comparison_p)
9507 op0 = XEXP (op0, 0);
9514 /* Can simplify (compare (zero/sign_extend FOO) CONST)
9515 to (compare FOO CONST) if CONST fits in FOO's mode and we
9516 are either testing inequality or have an unsigned comparison
9517 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
9518 if (! unsigned_comparison_p
9519 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
9520 <= HOST_BITS_PER_WIDE_INT)
9521 && ((unsigned HOST_WIDE_INT) const_op
9522 < (((HOST_WIDE_INT) 1
9523 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
9525 op0 = XEXP (op0, 0);
9531 /* Check for the case where we are comparing A - C1 with C2,
9532 both constants are smaller than 1/2 the maximum positive
9533 value in MODE, and the comparison is equality or unsigned.
9534 In that case, if A is either zero-extended to MODE or has
9535 sufficient sign bits so that the high-order bit in MODE
9536 is a copy of the sign in the inner mode, we can prove that it is
9537 safe to do the operation in the wider mode. This simplifies
9538 many range checks. */
9540 if (mode_width <= HOST_BITS_PER_WIDE_INT
9541 && subreg_lowpart_p (op0)
9542 && GET_CODE (SUBREG_REG (op0)) == PLUS
9543 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
9544 && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
9545 && (- INTVAL (XEXP (SUBREG_REG (op0), 1))
9546 < GET_MODE_MASK (mode) / 2)
9547 && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2
9548 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0),
9549 GET_MODE (SUBREG_REG (op0)))
9550 & ~ GET_MODE_MASK (mode))
9551 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
9552 GET_MODE (SUBREG_REG (op0)))
9553 > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
9554 - GET_MODE_BITSIZE (mode)))))
9556 op0 = SUBREG_REG (op0);
9560 /* If the inner mode is narrower and we are extracting the low part,
9561 we can treat the SUBREG as if it were a ZERO_EXTEND. */
9562 if (subreg_lowpart_p (op0)
9563 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
9564 /* Fall through */ ;
9568 /* ... fall through ... */
9571 if ((unsigned_comparison_p || equality_comparison_p)
9572 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
9573 <= HOST_BITS_PER_WIDE_INT)
9574 && ((unsigned HOST_WIDE_INT) const_op
9575 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
9577 op0 = XEXP (op0, 0);
9583 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
9584 this for equality comparisons due to pathological cases involving
9586 if (equality_comparison_p
9587 && 0 != (tem = simplify_binary_operation (MINUS, mode,
9588 op1, XEXP (op0, 1))))
9590 op0 = XEXP (op0, 0);
9595 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
9596 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
9597 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
9599 op0 = XEXP (XEXP (op0, 0), 0);
9600 code = (code == LT ? EQ : NE);
9606 /* (eq (minus A B) C) -> (eq A (plus B C)) or
9607 (eq B (minus A C)), whichever simplifies. We can only do
9608 this for equality comparisons due to pathological cases involving
9610 if (equality_comparison_p
9611 && 0 != (tem = simplify_binary_operation (PLUS, mode,
9612 XEXP (op0, 1), op1)))
9614 op0 = XEXP (op0, 0);
9619 if (equality_comparison_p
9620 && 0 != (tem = simplify_binary_operation (MINUS, mode,
9621 XEXP (op0, 0), op1)))
9623 op0 = XEXP (op0, 1);
9628 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
9629 of bits in X minus 1, is one iff X > 0. */
9630 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
9631 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
9632 && INTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
9633 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
9635 op0 = XEXP (op0, 1);
9636 code = (code == GE ? LE : GT);
9642 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
9643 if C is zero or B is a constant. */
9644 if (equality_comparison_p
9645 && 0 != (tem = simplify_binary_operation (XOR, mode,
9646 XEXP (op0, 1), op1)))
9648 op0 = XEXP (op0, 0);
9655 case LT: case LTU: case LE: case LEU:
9656 case GT: case GTU: case GE: case GEU:
9657 /* We can't do anything if OP0 is a condition code value, rather
9658 than an actual data value. */
9661 || XEXP (op0, 0) == cc0_rtx
9663 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
9666 /* Get the two operands being compared. */
9667 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
9668 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
9670 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
9672 /* Check for the cases where we simply want the result of the
9673 earlier test or the opposite of that result. */
9675 || (code == EQ && reversible_comparison_p (op0))
9676 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9677 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
9678 && (STORE_FLAG_VALUE
9679 & (((HOST_WIDE_INT) 1
9680 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
9682 || (code == GE && reversible_comparison_p (op0)))))
9684 code = (code == LT || code == NE
9685 ? GET_CODE (op0) : reverse_condition (GET_CODE (op0)));
9686 op0 = tem, op1 = tem1;
9692 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
9694 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
9695 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
9696 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
9698 op0 = XEXP (op0, 1);
9699 code = (code == GE ? GT : LE);
9705 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
9706 will be converted to a ZERO_EXTRACT later. */
9707 if (const_op == 0 && equality_comparison_p
9708 && GET_CODE (XEXP (op0, 0)) == ASHIFT
9709 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
9711 op0 = simplify_and_const_int
9712 (op0, mode, gen_rtx_combine (LSHIFTRT, mode,
9714 XEXP (XEXP (op0, 0), 1)),
9719 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
9720 zero and X is a comparison and C1 and C2 describe only bits set
9721 in STORE_FLAG_VALUE, we can compare with X. */
9722 if (const_op == 0 && equality_comparison_p
9723 && mode_width <= HOST_BITS_PER_WIDE_INT
9724 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9725 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
9726 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
9727 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
9728 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
9730 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
9731 << INTVAL (XEXP (XEXP (op0, 0), 1)));
9732 if ((~ STORE_FLAG_VALUE & mask) == 0
9733 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
9734 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
9735 && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
9737 op0 = XEXP (XEXP (op0, 0), 0);
9742 /* If we are doing an equality comparison of an AND of a bit equal
9743 to the sign bit, replace this with a LT or GE comparison of
9744 the underlying value. */
9745 if (equality_comparison_p
9747 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9748 && mode_width <= HOST_BITS_PER_WIDE_INT
9749 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
9750 == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9752 op0 = XEXP (op0, 0);
9753 code = (code == EQ ? GE : LT);
9757 /* If this AND operation is really a ZERO_EXTEND from a narrower
9758 mode, the constant fits within that mode, and this is either an
9759 equality or unsigned comparison, try to do this comparison in
9760 the narrower mode. */
9761 if ((equality_comparison_p || unsigned_comparison_p)
9762 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9763 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
9764 & GET_MODE_MASK (mode))
9766 && const_op >> i == 0
9767 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
9769 op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
9775 /* If we have (compare (ashift FOO N) (const_int C)) and
9776 the high order N bits of FOO (N+1 if an inequality comparison)
9777 are known to be zero, we can do this by comparing FOO with C
9778 shifted right N bits so long as the low-order N bits of C are
9780 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
9781 && INTVAL (XEXP (op0, 1)) >= 0
9782 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
9783 < HOST_BITS_PER_WIDE_INT)
9785 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
9786 && mode_width <= HOST_BITS_PER_WIDE_INT
9787 && (nonzero_bits (XEXP (op0, 0), mode)
9788 & ~ (mask >> (INTVAL (XEXP (op0, 1))
9789 + ! equality_comparison_p))) == 0)
9791 const_op >>= INTVAL (XEXP (op0, 1));
9792 op1 = GEN_INT (const_op);
9793 op0 = XEXP (op0, 0);
9797 /* If we are doing a sign bit comparison, it means we are testing
9798 a particular bit. Convert it to the appropriate AND. */
9799 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
9800 && mode_width <= HOST_BITS_PER_WIDE_INT)
9802 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
9805 - INTVAL (XEXP (op0, 1)))));
9806 code = (code == LT ? NE : EQ);
9810 /* If this an equality comparison with zero and we are shifting
9811 the low bit to the sign bit, we can convert this to an AND of the
9813 if (const_op == 0 && equality_comparison_p
9814 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9815 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
9817 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
9824 /* If this is an equality comparison with zero, we can do this
9825 as a logical shift, which might be much simpler. */
9826 if (equality_comparison_p && const_op == 0
9827 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
9829 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
9831 INTVAL (XEXP (op0, 1)));
9835 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
9836 do the comparison in a narrower mode. */
9837 if (! unsigned_comparison_p
9838 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9839 && GET_CODE (XEXP (op0, 0)) == ASHIFT
9840 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
9841 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
9842 MODE_INT, 1)) != BLKmode
9843 && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode)
9844 || ((unsigned HOST_WIDE_INT) - const_op
9845 <= GET_MODE_MASK (tmode))))
9847 op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
9851 /* ... fall through ... */
9853 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
9854 the low order N bits of FOO are known to be zero, we can do this
9855 by comparing FOO with C shifted left N bits so long as no
9857 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
9858 && INTVAL (XEXP (op0, 1)) >= 0
9859 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9860 && mode_width <= HOST_BITS_PER_WIDE_INT
9861 && (nonzero_bits (XEXP (op0, 0), mode)
9862 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
9864 || (floor_log2 (const_op) + INTVAL (XEXP (op0, 1))
9867 const_op <<= INTVAL (XEXP (op0, 1));
9868 op1 = GEN_INT (const_op);
9869 op0 = XEXP (op0, 0);
9873 /* If we are using this shift to extract just the sign bit, we
9874 can replace this with an LT or GE comparison. */
9876 && (equality_comparison_p || sign_bit_comparison_p)
9877 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9878 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
9880 op0 = XEXP (op0, 0);
9881 code = (code == NE || code == GT ? LT : GE);
9890 /* Now make any compound operations involved in this comparison. Then,
9891 check for an outmost SUBREG on OP0 that isn't doing anything or is
9892 paradoxical. The latter case can only occur when it is known that the
9893 "extra" bits will be zero. Therefore, it is safe to remove the SUBREG.
9894 We can never remove a SUBREG for a non-equality comparison because the
9895 sign bit is in a different place in the underlying object. */
9897 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
9898 op1 = make_compound_operation (op1, SET);
9900 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
9901 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
9902 && (code == NE || code == EQ)
9903 && ((GET_MODE_SIZE (GET_MODE (op0))
9904 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))))
9906 op0 = SUBREG_REG (op0);
9907 op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
9910 else if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
9911 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
9912 && (code == NE || code == EQ)
9913 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
9914 <= HOST_BITS_PER_WIDE_INT)
9915 && (nonzero_bits (SUBREG_REG (op0), GET_MODE (SUBREG_REG (op0)))
9916 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0
9917 && (tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)),
9919 (nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
9920 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0))
9921 op0 = SUBREG_REG (op0), op1 = tem;
9923 /* We now do the opposite procedure: Some machines don't have compare
9924 insns in all modes. If OP0's mode is an integer mode smaller than a
9925 word and we can't do a compare in that mode, see if there is a larger
9926 mode for which we can do the compare. There are a number of cases in
9927 which we can use the wider mode. */
9929 mode = GET_MODE (op0);
9930 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
9931 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
9932 && cmp_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
9933 for (tmode = GET_MODE_WIDER_MODE (mode);
9935 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
9936 tmode = GET_MODE_WIDER_MODE (tmode))
9937 if (cmp_optab->handlers[(int) tmode].insn_code != CODE_FOR_nothing)
9939 /* If the only nonzero bits in OP0 and OP1 are those in the
9940 narrower mode and this is an equality or unsigned comparison,
9941 we can use the wider mode. Similarly for sign-extended
9942 values, in which case it is true for all comparisons. */
9943 if (((code == EQ || code == NE
9944 || code == GEU || code == GTU || code == LEU || code == LTU)
9945 && (nonzero_bits (op0, tmode) & ~ GET_MODE_MASK (mode)) == 0
9946 && (nonzero_bits (op1, tmode) & ~ GET_MODE_MASK (mode)) == 0)
9947 || ((num_sign_bit_copies (op0, tmode)
9948 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))
9949 && (num_sign_bit_copies (op1, tmode)
9950 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))))
9952 op0 = gen_lowpart_for_combine (tmode, op0);
9953 op1 = gen_lowpart_for_combine (tmode, op1);
9957 /* If this is a test for negative, we can make an explicit
9958 test of the sign bit. */
9960 if (op1 == const0_rtx && (code == LT || code == GE)
9961 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9963 op0 = gen_binary (AND, tmode,
9964 gen_lowpart_for_combine (tmode, op0),
9965 GEN_INT ((HOST_WIDE_INT) 1
9966 << (GET_MODE_BITSIZE (mode) - 1)));
9967 code = (code == LT) ? NE : EQ;
9972 #ifdef CANONICALIZE_COMPARISON
9973 /* If this machine only supports a subset of valid comparisons, see if we
9974 can convert an unsupported one into a supported one. */
9975 CANONICALIZE_COMPARISON (code, op0, op1);
9984 /* Return 1 if we know that X, a comparison operation, is not operating
9985 on a floating-point value or is EQ or NE, meaning that we can safely
9989 reversible_comparison_p (x)
9992 if (TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
9994 || GET_CODE (x) == NE || GET_CODE (x) == EQ)
9997 switch (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))))
10000 case MODE_PARTIAL_INT:
10001 case MODE_COMPLEX_INT:
10005 /* If the mode of the condition codes tells us that this is safe,
10006 we need look no further. */
10007 if (REVERSIBLE_CC_MODE (GET_MODE (XEXP (x, 0))))
10010 /* Otherwise try and find where the condition codes were last set and
10012 x = get_last_value (XEXP (x, 0));
10013 return (x && GET_CODE (x) == COMPARE
10014 && ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0))));
10020 /* Utility function for following routine. Called when X is part of a value
10021 being stored into reg_last_set_value. Sets reg_last_set_table_tick
10022 for each register mentioned. Similar to mention_regs in cse.c */
10025 update_table_tick (x)
10028 register enum rtx_code code = GET_CODE (x);
10029 register char *fmt = GET_RTX_FORMAT (code);
10034 int regno = REGNO (x);
10035 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10036 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10038 for (i = regno; i < endregno; i++)
10039 reg_last_set_table_tick[i] = label_tick;
10044 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10045 /* Note that we can't have an "E" in values stored; see
10046 get_last_value_validate. */
10048 update_table_tick (XEXP (x, i));
10051 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
10052 are saying that the register is clobbered and we no longer know its
10053 value. If INSN is zero, don't update reg_last_set; this is only permitted
10054 with VALUE also zero and is used to invalidate the register. */
10057 record_value_for_reg (reg, insn, value)
10062 int regno = REGNO (reg);
10063 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10064 ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
10067 /* If VALUE contains REG and we have a previous value for REG, substitute
10068 the previous value. */
10069 if (value && insn && reg_overlap_mentioned_p (reg, value))
10073 /* Set things up so get_last_value is allowed to see anything set up to
10075 subst_low_cuid = INSN_CUID (insn);
10076 tem = get_last_value (reg);
10079 value = replace_rtx (copy_rtx (value), reg, tem);
10082 /* For each register modified, show we don't know its value, that
10083 we don't know about its bitwise content, that its value has been
10084 updated, and that we don't know the location of the death of the
10086 for (i = regno; i < endregno; i ++)
10089 reg_last_set[i] = insn;
10090 reg_last_set_value[i] = 0;
10091 reg_last_set_mode[i] = 0;
10092 reg_last_set_nonzero_bits[i] = 0;
10093 reg_last_set_sign_bit_copies[i] = 0;
10094 reg_last_death[i] = 0;
10097 /* Mark registers that are being referenced in this value. */
10099 update_table_tick (value);
10101 /* Now update the status of each register being set.
10102 If someone is using this register in this block, set this register
10103 to invalid since we will get confused between the two lives in this
10104 basic block. This makes using this register always invalid. In cse, we
10105 scan the table to invalidate all entries using this register, but this
10106 is too much work for us. */
10108 for (i = regno; i < endregno; i++)
10110 reg_last_set_label[i] = label_tick;
10111 if (value && reg_last_set_table_tick[i] == label_tick)
10112 reg_last_set_invalid[i] = 1;
10114 reg_last_set_invalid[i] = 0;
10117 /* The value being assigned might refer to X (like in "x++;"). In that
10118 case, we must replace it with (clobber (const_int 0)) to prevent
10120 if (value && ! get_last_value_validate (&value,
10121 reg_last_set_label[regno], 0))
10123 value = copy_rtx (value);
10124 if (! get_last_value_validate (&value, reg_last_set_label[regno], 1))
10128 /* For the main register being modified, update the value, the mode, the
10129 nonzero bits, and the number of sign bit copies. */
10131 reg_last_set_value[regno] = value;
10135 subst_low_cuid = INSN_CUID (insn);
10136 reg_last_set_mode[regno] = GET_MODE (reg);
10137 reg_last_set_nonzero_bits[regno] = nonzero_bits (value, GET_MODE (reg));
10138 reg_last_set_sign_bit_copies[regno]
10139 = num_sign_bit_copies (value, GET_MODE (reg));
10143 /* Used for communication between the following two routines. */
10144 static rtx record_dead_insn;
10146 /* Called via note_stores from record_dead_and_set_regs to handle one
10147 SET or CLOBBER in an insn. */
10150 record_dead_and_set_regs_1 (dest, setter)
10153 if (GET_CODE (dest) == SUBREG)
10154 dest = SUBREG_REG (dest);
10156 if (GET_CODE (dest) == REG)
10158 /* If we are setting the whole register, we know its value. Otherwise
10159 show that we don't know the value. We can handle SUBREG in
10161 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
10162 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
10163 else if (GET_CODE (setter) == SET
10164 && GET_CODE (SET_DEST (setter)) == SUBREG
10165 && SUBREG_REG (SET_DEST (setter)) == dest
10166 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
10167 && subreg_lowpart_p (SET_DEST (setter)))
10168 record_value_for_reg (dest, record_dead_insn,
10169 gen_lowpart_for_combine (GET_MODE (dest),
10170 SET_SRC (setter)));
10172 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
10174 else if (GET_CODE (dest) == MEM
10175 /* Ignore pushes, they clobber nothing. */
10176 && ! push_operand (dest, GET_MODE (dest)))
10177 mem_last_set = INSN_CUID (record_dead_insn);
10180 /* Update the records of when each REG was most recently set or killed
10181 for the things done by INSN. This is the last thing done in processing
10182 INSN in the combiner loop.
10184 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
10185 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
10186 and also the similar information mem_last_set (which insn most recently
10187 modified memory) and last_call_cuid (which insn was the most recent
10188 subroutine call). */
10191 record_dead_and_set_regs (insn)
10197 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
10199 if (REG_NOTE_KIND (link) == REG_DEAD
10200 && GET_CODE (XEXP (link, 0)) == REG)
10202 int regno = REGNO (XEXP (link, 0));
10204 = regno + (regno < FIRST_PSEUDO_REGISTER
10205 ? HARD_REGNO_NREGS (regno, GET_MODE (XEXP (link, 0)))
10208 for (i = regno; i < endregno; i++)
10209 reg_last_death[i] = insn;
10211 else if (REG_NOTE_KIND (link) == REG_INC)
10212 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
10215 if (GET_CODE (insn) == CALL_INSN)
10217 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
10218 if (call_used_regs[i])
10220 reg_last_set_value[i] = 0;
10221 reg_last_set_mode[i] = 0;
10222 reg_last_set_nonzero_bits[i] = 0;
10223 reg_last_set_sign_bit_copies[i] = 0;
10224 reg_last_death[i] = 0;
10227 last_call_cuid = mem_last_set = INSN_CUID (insn);
10230 record_dead_insn = insn;
10231 note_stores (PATTERN (insn), record_dead_and_set_regs_1);
10234 /* Utility routine for the following function. Verify that all the registers
10235 mentioned in *LOC are valid when *LOC was part of a value set when
10236 label_tick == TICK. Return 0 if some are not.
10238 If REPLACE is non-zero, replace the invalid reference with
10239 (clobber (const_int 0)) and return 1. This replacement is useful because
10240 we often can get useful information about the form of a value (e.g., if
10241 it was produced by a shift that always produces -1 or 0) even though
10242 we don't know exactly what registers it was produced from. */
10245 get_last_value_validate (loc, tick, replace)
10251 char *fmt = GET_RTX_FORMAT (GET_CODE (x));
10252 int len = GET_RTX_LENGTH (GET_CODE (x));
10255 if (GET_CODE (x) == REG)
10257 int regno = REGNO (x);
10258 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10259 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10262 for (j = regno; j < endregno; j++)
10263 if (reg_last_set_invalid[j]
10264 /* If this is a pseudo-register that was only set once, it is
10266 || (! (regno >= FIRST_PSEUDO_REGISTER && reg_n_sets[regno] == 1)
10267 && reg_last_set_label[j] > tick))
10270 *loc = gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
10277 for (i = 0; i < len; i++)
10279 && get_last_value_validate (&XEXP (x, i), tick, replace) == 0)
10280 /* Don't bother with these. They shouldn't occur anyway. */
10284 /* If we haven't found a reason for it to be invalid, it is valid. */
10288 /* Get the last value assigned to X, if known. Some registers
10289 in the value may be replaced with (clobber (const_int 0)) if their value
10290 is known longer known reliably. */
10299 /* If this is a non-paradoxical SUBREG, get the value of its operand and
10300 then convert it to the desired mode. If this is a paradoxical SUBREG,
10301 we cannot predict what values the "extra" bits might have. */
10302 if (GET_CODE (x) == SUBREG
10303 && subreg_lowpart_p (x)
10304 && (GET_MODE_SIZE (GET_MODE (x))
10305 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
10306 && (value = get_last_value (SUBREG_REG (x))) != 0)
10307 return gen_lowpart_for_combine (GET_MODE (x), value);
10309 if (GET_CODE (x) != REG)
10313 value = reg_last_set_value[regno];
10315 /* If we don't have a value or if it isn't for this basic block,
10319 || (reg_n_sets[regno] != 1
10320 && reg_last_set_label[regno] != label_tick))
10323 /* If the value was set in a later insn than the ones we are processing,
10324 we can't use it even if the register was only set once, but make a quick
10325 check to see if the previous insn set it to something. This is commonly
10326 the case when the same pseudo is used by repeated insns.
10328 This does not work if there exists an instruction which is temporarily
10329 not on the insn chain. */
10331 if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)
10335 /* We can not do anything useful in this case, because there is
10336 an instruction which is not on the insn chain. */
10337 if (subst_prev_insn)
10340 /* Skip over USE insns. They are not useful here, and they may have
10341 been made by combine, in which case they do not have a INSN_CUID
10342 value. We can't use prev_real_insn, because that would incorrectly
10343 take us backwards across labels. Skip over BARRIERs also, since
10344 they could have been made by combine. If we see one, we must be
10345 optimizing dead code, so it doesn't matter what we do. */
10346 for (insn = prev_nonnote_insn (subst_insn);
10347 insn && ((GET_CODE (insn) == INSN
10348 && GET_CODE (PATTERN (insn)) == USE)
10349 || GET_CODE (insn) == BARRIER
10350 || INSN_CUID (insn) >= subst_low_cuid);
10351 insn = prev_nonnote_insn (insn))
10355 && (set = single_set (insn)) != 0
10356 && rtx_equal_p (SET_DEST (set), x))
10358 value = SET_SRC (set);
10360 /* Make sure that VALUE doesn't reference X. Replace any
10361 explicit references with a CLOBBER. If there are any remaining
10362 references (rare), don't use the value. */
10364 if (reg_mentioned_p (x, value))
10365 value = replace_rtx (copy_rtx (value), x,
10366 gen_rtx (CLOBBER, GET_MODE (x), const0_rtx));
10368 if (reg_overlap_mentioned_p (x, value))
10375 /* If the value has all its registers valid, return it. */
10376 if (get_last_value_validate (&value, reg_last_set_label[regno], 0))
10379 /* Otherwise, make a copy and replace any invalid register with
10380 (clobber (const_int 0)). If that fails for some reason, return 0. */
10382 value = copy_rtx (value);
10383 if (get_last_value_validate (&value, reg_last_set_label[regno], 1))
10389 /* Return nonzero if expression X refers to a REG or to memory
10390 that is set in an instruction more recent than FROM_CUID. */
10393 use_crosses_set_p (x, from_cuid)
10397 register char *fmt;
10399 register enum rtx_code code = GET_CODE (x);
10403 register int regno = REGNO (x);
10404 int endreg = regno + (regno < FIRST_PSEUDO_REGISTER
10405 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10407 #ifdef PUSH_ROUNDING
10408 /* Don't allow uses of the stack pointer to be moved,
10409 because we don't know whether the move crosses a push insn. */
10410 if (regno == STACK_POINTER_REGNUM)
10413 for (;regno < endreg; regno++)
10414 if (reg_last_set[regno]
10415 && INSN_CUID (reg_last_set[regno]) > from_cuid)
10420 if (code == MEM && mem_last_set > from_cuid)
10423 fmt = GET_RTX_FORMAT (code);
10425 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10430 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
10431 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
10434 else if (fmt[i] == 'e'
10435 && use_crosses_set_p (XEXP (x, i), from_cuid))
10441 /* Define three variables used for communication between the following
10444 static int reg_dead_regno, reg_dead_endregno;
10445 static int reg_dead_flag;
10447 /* Function called via note_stores from reg_dead_at_p.
10449 If DEST is within [reg_dead_regno, reg_dead_endregno), set
10450 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
10453 reg_dead_at_p_1 (dest, x)
10457 int regno, endregno;
10459 if (GET_CODE (dest) != REG)
10462 regno = REGNO (dest);
10463 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10464 ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
10466 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
10467 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
10470 /* Return non-zero if REG is known to be dead at INSN.
10472 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
10473 referencing REG, it is dead. If we hit a SET referencing REG, it is
10474 live. Otherwise, see if it is live or dead at the start of the basic
10475 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
10476 must be assumed to be always live. */
10479 reg_dead_at_p (reg, insn)
10485 /* Set variables for reg_dead_at_p_1. */
10486 reg_dead_regno = REGNO (reg);
10487 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
10488 ? HARD_REGNO_NREGS (reg_dead_regno,
10494 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
10495 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
10497 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
10498 if (TEST_HARD_REG_BIT (newpat_used_regs, i))
10502 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
10503 beginning of function. */
10504 for (; insn && GET_CODE (insn) != CODE_LABEL && GET_CODE (insn) != BARRIER;
10505 insn = prev_nonnote_insn (insn))
10507 note_stores (PATTERN (insn), reg_dead_at_p_1);
10509 return reg_dead_flag == 1 ? 1 : 0;
10511 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
10515 /* Get the basic block number that we were in. */
10520 for (block = 0; block < n_basic_blocks; block++)
10521 if (insn == basic_block_head[block])
10524 if (block == n_basic_blocks)
10528 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
10529 if (basic_block_live_at_start[block][i / REGSET_ELT_BITS]
10530 & ((REGSET_ELT_TYPE) 1 << (i % REGSET_ELT_BITS)))
10536 /* Note hard registers in X that are used. This code is similar to
10537 that in flow.c, but much simpler since we don't care about pseudos. */
10540 mark_used_regs_combine (x)
10543 register RTX_CODE code = GET_CODE (x);
10544 register int regno;
10556 case ADDR_DIFF_VEC:
10559 /* CC0 must die in the insn after it is set, so we don't need to take
10560 special note of it here. */
10566 /* If we are clobbering a MEM, mark any hard registers inside the
10567 address as used. */
10568 if (GET_CODE (XEXP (x, 0)) == MEM)
10569 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
10574 /* A hard reg in a wide mode may really be multiple registers.
10575 If so, mark all of them just like the first. */
10576 if (regno < FIRST_PSEUDO_REGISTER)
10578 /* None of this applies to the stack, frame or arg pointers */
10579 if (regno == STACK_POINTER_REGNUM
10580 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
10581 || regno == HARD_FRAME_POINTER_REGNUM
10583 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
10584 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
10586 || regno == FRAME_POINTER_REGNUM)
10589 i = HARD_REGNO_NREGS (regno, GET_MODE (x));
10591 SET_HARD_REG_BIT (newpat_used_regs, regno + i);
10597 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
10599 register rtx testreg = SET_DEST (x);
10601 while (GET_CODE (testreg) == SUBREG
10602 || GET_CODE (testreg) == ZERO_EXTRACT
10603 || GET_CODE (testreg) == SIGN_EXTRACT
10604 || GET_CODE (testreg) == STRICT_LOW_PART)
10605 testreg = XEXP (testreg, 0);
10607 if (GET_CODE (testreg) == MEM)
10608 mark_used_regs_combine (XEXP (testreg, 0));
10610 mark_used_regs_combine (SET_SRC (x));
10615 /* Recursively scan the operands of this expression. */
10618 register char *fmt = GET_RTX_FORMAT (code);
10620 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10623 mark_used_regs_combine (XEXP (x, i));
10624 else if (fmt[i] == 'E')
10628 for (j = 0; j < XVECLEN (x, i); j++)
10629 mark_used_regs_combine (XVECEXP (x, i, j));
10636 /* Remove register number REGNO from the dead registers list of INSN.
10638 Return the note used to record the death, if there was one. */
10641 remove_death (regno, insn)
10645 register rtx note = find_regno_note (insn, REG_DEAD, regno);
10649 reg_n_deaths[regno]--;
10650 remove_note (insn, note);
10656 /* For each register (hardware or pseudo) used within expression X, if its
10657 death is in an instruction with cuid between FROM_CUID (inclusive) and
10658 TO_INSN (exclusive), put a REG_DEAD note for that register in the
10659 list headed by PNOTES.
10661 That said, don't move registers killed by maybe_kill_insn.
10663 This is done when X is being merged by combination into TO_INSN. These
10664 notes will then be distributed as needed. */
10667 move_deaths (x, maybe_kill_insn, from_cuid, to_insn, pnotes)
10669 rtx maybe_kill_insn;
10674 register char *fmt;
10675 register int len, i;
10676 register enum rtx_code code = GET_CODE (x);
10680 register int regno = REGNO (x);
10681 register rtx where_dead = reg_last_death[regno];
10682 register rtx before_dead, after_dead;
10684 /* Don't move the register if it gets killed in between from and to */
10685 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
10686 && !reg_referenced_p (x, maybe_kill_insn))
10689 /* WHERE_DEAD could be a USE insn made by combine, so first we
10690 make sure that we have insns with valid INSN_CUID values. */
10691 before_dead = where_dead;
10692 while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
10693 before_dead = PREV_INSN (before_dead);
10694 after_dead = where_dead;
10695 while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
10696 after_dead = NEXT_INSN (after_dead);
10698 if (before_dead && after_dead
10699 && INSN_CUID (before_dead) >= from_cuid
10700 && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
10701 || (where_dead != after_dead
10702 && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
10704 rtx note = remove_death (regno, where_dead);
10706 /* It is possible for the call above to return 0. This can occur
10707 when reg_last_death points to I2 or I1 that we combined with.
10708 In that case make a new note.
10710 We must also check for the case where X is a hard register
10711 and NOTE is a death note for a range of hard registers
10712 including X. In that case, we must put REG_DEAD notes for
10713 the remaining registers in place of NOTE. */
10715 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
10716 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
10717 != GET_MODE_SIZE (GET_MODE (x))))
10719 int deadregno = REGNO (XEXP (note, 0));
10721 = (deadregno + HARD_REGNO_NREGS (deadregno,
10722 GET_MODE (XEXP (note, 0))));
10723 int ourend = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
10726 for (i = deadregno; i < deadend; i++)
10727 if (i < regno || i >= ourend)
10728 REG_NOTES (where_dead)
10729 = gen_rtx (EXPR_LIST, REG_DEAD,
10730 gen_rtx (REG, reg_raw_mode[i], i),
10731 REG_NOTES (where_dead));
10733 /* If we didn't find any note, and we have a multi-reg hard
10734 register, then to be safe we must check for REG_DEAD notes
10735 for each register other than the first. They could have
10736 their own REG_DEAD notes lying around. */
10737 else if (note == 0 && regno < FIRST_PSEUDO_REGISTER
10738 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
10740 int ourend = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
10744 for (i = regno + 1; i < ourend; i++)
10745 move_deaths (gen_rtx (REG, reg_raw_mode[i], i),
10746 maybe_kill_insn, from_cuid, to_insn, &oldnotes);
10749 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
10751 XEXP (note, 1) = *pnotes;
10755 *pnotes = gen_rtx (EXPR_LIST, REG_DEAD, x, *pnotes);
10757 reg_n_deaths[regno]++;
10763 else if (GET_CODE (x) == SET)
10765 rtx dest = SET_DEST (x);
10767 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
10769 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
10770 that accesses one word of a multi-word item, some
10771 piece of everything register in the expression is used by
10772 this insn, so remove any old death. */
10774 if (GET_CODE (dest) == ZERO_EXTRACT
10775 || GET_CODE (dest) == STRICT_LOW_PART
10776 || (GET_CODE (dest) == SUBREG
10777 && (((GET_MODE_SIZE (GET_MODE (dest))
10778 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
10779 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
10780 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
10782 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
10786 /* If this is some other SUBREG, we know it replaces the entire
10787 value, so use that as the destination. */
10788 if (GET_CODE (dest) == SUBREG)
10789 dest = SUBREG_REG (dest);
10791 /* If this is a MEM, adjust deaths of anything used in the address.
10792 For a REG (the only other possibility), the entire value is
10793 being replaced so the old value is not used in this insn. */
10795 if (GET_CODE (dest) == MEM)
10796 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
10801 else if (GET_CODE (x) == CLOBBER)
10804 len = GET_RTX_LENGTH (code);
10805 fmt = GET_RTX_FORMAT (code);
10807 for (i = 0; i < len; i++)
10812 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
10813 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
10816 else if (fmt[i] == 'e')
10817 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
10821 /* Return 1 if X is the target of a bit-field assignment in BODY, the
10822 pattern of an insn. X must be a REG. */
10825 reg_bitfield_target_p (x, body)
10831 if (GET_CODE (body) == SET)
10833 rtx dest = SET_DEST (body);
10835 int regno, tregno, endregno, endtregno;
10837 if (GET_CODE (dest) == ZERO_EXTRACT)
10838 target = XEXP (dest, 0);
10839 else if (GET_CODE (dest) == STRICT_LOW_PART)
10840 target = SUBREG_REG (XEXP (dest, 0));
10844 if (GET_CODE (target) == SUBREG)
10845 target = SUBREG_REG (target);
10847 if (GET_CODE (target) != REG)
10850 tregno = REGNO (target), regno = REGNO (x);
10851 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
10852 return target == x;
10854 endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target));
10855 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
10857 return endregno > tregno && regno < endtregno;
10860 else if (GET_CODE (body) == PARALLEL)
10861 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
10862 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
10868 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
10869 as appropriate. I3 and I2 are the insns resulting from the combination
10870 insns including FROM (I2 may be zero).
10872 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
10873 not need REG_DEAD notes because they are being substituted for. This
10874 saves searching in the most common cases.
10876 Each note in the list is either ignored or placed on some insns, depending
10877 on the type of note. */
10880 distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1)
10884 rtx elim_i2, elim_i1;
10886 rtx note, next_note;
10889 for (note = notes; note; note = next_note)
10891 rtx place = 0, place2 = 0;
10893 /* If this NOTE references a pseudo register, ensure it references
10894 the latest copy of that register. */
10895 if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
10896 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
10897 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
10899 next_note = XEXP (note, 1);
10900 switch (REG_NOTE_KIND (note))
10903 /* Any clobbers for i3 may still exist, and so we must process
10904 REG_UNUSED notes from that insn.
10906 Any clobbers from i2 or i1 can only exist if they were added by
10907 recog_for_combine. In that case, recog_for_combine created the
10908 necessary REG_UNUSED notes. Trying to keep any original
10909 REG_UNUSED notes from these insns can cause incorrect output
10910 if it is for the same register as the original i3 dest.
10911 In that case, we will notice that the register is set in i3,
10912 and then add a REG_UNUSED note for the destination of i3, which
10913 is wrong. However, it is possible to have REG_UNUSED notes from
10914 i2 or i1 for register which were both used and clobbered, so
10915 we keep notes from i2 or i1 if they will turn into REG_DEAD
10918 /* If this register is set or clobbered in I3, put the note there
10919 unless there is one already. */
10920 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
10922 if (from_insn != i3)
10925 if (! (GET_CODE (XEXP (note, 0)) == REG
10926 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
10927 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
10930 /* Otherwise, if this register is used by I3, then this register
10931 now dies here, so we must put a REG_DEAD note here unless there
10933 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
10934 && ! (GET_CODE (XEXP (note, 0)) == REG
10935 ? find_regno_note (i3, REG_DEAD, REGNO (XEXP (note, 0)))
10936 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
10938 PUT_REG_NOTE_KIND (note, REG_DEAD);
10946 /* These notes say something about results of an insn. We can
10947 only support them if they used to be on I3 in which case they
10948 remain on I3. Otherwise they are ignored.
10950 If the note refers to an expression that is not a constant, we
10951 must also ignore the note since we cannot tell whether the
10952 equivalence is still true. It might be possible to do
10953 slightly better than this (we only have a problem if I2DEST
10954 or I1DEST is present in the expression), but it doesn't
10955 seem worth the trouble. */
10957 if (from_insn == i3
10958 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
10963 case REG_NO_CONFLICT:
10965 /* These notes say something about how a register is used. They must
10966 be present on any use of the register in I2 or I3. */
10967 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
10970 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
10980 /* It is too much trouble to try to see if this note is still
10981 correct in all situations. It is better to simply delete it. */
10985 /* If the insn previously containing this note still exists,
10986 put it back where it was. Otherwise move it to the previous
10987 insn. Adjust the corresponding REG_LIBCALL note. */
10988 if (GET_CODE (from_insn) != NOTE)
10992 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
10993 place = prev_real_insn (from_insn);
10995 XEXP (tem, 0) = place;
11000 /* This is handled similarly to REG_RETVAL. */
11001 if (GET_CODE (from_insn) != NOTE)
11005 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
11006 place = next_real_insn (from_insn);
11008 XEXP (tem, 0) = place;
11013 /* If the register is used as an input in I3, it dies there.
11014 Similarly for I2, if it is non-zero and adjacent to I3.
11016 If the register is not used as an input in either I3 or I2
11017 and it is not one of the registers we were supposed to eliminate,
11018 there are two possibilities. We might have a non-adjacent I2
11019 or we might have somehow eliminated an additional register
11020 from a computation. For example, we might have had A & B where
11021 we discover that B will always be zero. In this case we will
11022 eliminate the reference to A.
11024 In both cases, we must search to see if we can find a previous
11025 use of A and put the death note there. */
11028 && GET_CODE (from_insn) == CALL_INSN
11029 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
11031 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
11033 else if (i2 != 0 && next_nonnote_insn (i2) == i3
11034 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
11037 if (XEXP (note, 0) == elim_i2 || XEXP (note, 0) == elim_i1)
11040 /* If the register is used in both I2 and I3 and it dies in I3,
11041 we might have added another reference to it. If reg_n_refs
11042 was 2, bump it to 3. This has to be correct since the
11043 register must have been set somewhere. The reason this is
11044 done is because local-alloc.c treats 2 references as a
11047 if (place == i3 && i2 != 0 && GET_CODE (XEXP (note, 0)) == REG
11048 && reg_n_refs[REGNO (XEXP (note, 0))]== 2
11049 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
11050 reg_n_refs[REGNO (XEXP (note, 0))] = 3;
11054 for (tem = prev_nonnote_insn (i3);
11056 && (GET_CODE (tem) == INSN || GET_CODE (tem) == CALL_INSN);
11057 tem = prev_nonnote_insn (tem))
11059 /* If the register is being set at TEM, see if that is all
11060 TEM is doing. If so, delete TEM. Otherwise, make this
11061 into a REG_UNUSED note instead. */
11062 if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
11064 rtx set = single_set (tem);
11066 /* Verify that it was the set, and not a clobber that
11067 modified the register. */
11069 if (set != 0 && ! side_effects_p (SET_SRC (set))
11070 && (rtx_equal_p (XEXP (note, 0), SET_DEST (set))
11071 || (GET_CODE (SET_DEST (set)) == SUBREG
11072 && rtx_equal_p (XEXP (note, 0),
11073 XEXP (SET_DEST (set), 0)))))
11075 /* Move the notes and links of TEM elsewhere.
11076 This might delete other dead insns recursively.
11077 First set the pattern to something that won't use
11080 PATTERN (tem) = pc_rtx;
11082 distribute_notes (REG_NOTES (tem), tem, tem,
11083 NULL_RTX, NULL_RTX, NULL_RTX);
11084 distribute_links (LOG_LINKS (tem));
11086 PUT_CODE (tem, NOTE);
11087 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
11088 NOTE_SOURCE_FILE (tem) = 0;
11092 PUT_REG_NOTE_KIND (note, REG_UNUSED);
11094 /* If there isn't already a REG_UNUSED note, put one
11096 if (! find_regno_note (tem, REG_UNUSED,
11097 REGNO (XEXP (note, 0))))
11102 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
11103 || (GET_CODE (tem) == CALL_INSN
11104 && find_reg_fusage (tem, USE, XEXP (note, 0))))
11108 /* If we are doing a 3->2 combination, and we have a
11109 register which formerly died in i3 and was not used
11110 by i2, which now no longer dies in i3 and is used in
11111 i2 but does not die in i2, and place is between i2
11112 and i3, then we may need to move a link from place to
11114 if (i2 && INSN_UID (place) <= max_uid_cuid
11115 && INSN_CUID (place) > INSN_CUID (i2)
11116 && from_insn && INSN_CUID (from_insn) > INSN_CUID (i2)
11117 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
11119 rtx links = LOG_LINKS (place);
11120 LOG_LINKS (place) = 0;
11121 distribute_links (links);
11127 /* If we haven't found an insn for the death note and it
11128 is still a REG_DEAD note, but we have hit a CODE_LABEL,
11129 insert a USE insn for the register at that label and
11130 put the death node there. This prevents problems with
11131 call-state tracking in caller-save.c. */
11132 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0 && tem != 0)
11135 = emit_insn_after (gen_rtx (USE, VOIDmode, XEXP (note, 0)),
11138 /* If this insn was emitted between blocks, then update
11139 basic_block_head of the current block to include it. */
11140 if (basic_block_end[this_basic_block - 1] == tem)
11141 basic_block_head[this_basic_block] = place;
11145 /* If the register is set or already dead at PLACE, we needn't do
11146 anything with this note if it is still a REG_DEAD note.
11148 Note that we cannot use just `dead_or_set_p' here since we can
11149 convert an assignment to a register into a bit-field assignment.
11150 Therefore, we must also omit the note if the register is the
11151 target of a bitfield assignment. */
11153 if (place && REG_NOTE_KIND (note) == REG_DEAD)
11155 int regno = REGNO (XEXP (note, 0));
11157 if (dead_or_set_p (place, XEXP (note, 0))
11158 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
11160 /* Unless the register previously died in PLACE, clear
11161 reg_last_death. [I no longer understand why this is
11163 if (reg_last_death[regno] != place)
11164 reg_last_death[regno] = 0;
11168 reg_last_death[regno] = place;
11170 /* If this is a death note for a hard reg that is occupying
11171 multiple registers, ensure that we are still using all
11172 parts of the object. If we find a piece of the object
11173 that is unused, we must add a USE for that piece before
11174 PLACE and put the appropriate REG_DEAD note on it.
11176 An alternative would be to put a REG_UNUSED for the pieces
11177 on the insn that set the register, but that can't be done if
11178 it is not in the same block. It is simpler, though less
11179 efficient, to add the USE insns. */
11181 if (place && regno < FIRST_PSEUDO_REGISTER
11182 && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
11185 = regno + HARD_REGNO_NREGS (regno,
11186 GET_MODE (XEXP (note, 0)));
11190 for (i = regno; i < endregno; i++)
11191 if (! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
11192 && ! find_regno_fusage (place, USE, i))
11194 rtx piece = gen_rtx (REG, reg_raw_mode[i], i);
11197 /* See if we already placed a USE note for this
11198 register in front of PLACE. */
11200 GET_CODE (PREV_INSN (p)) == INSN
11201 && GET_CODE (PATTERN (PREV_INSN (p))) == USE;
11203 if (rtx_equal_p (piece,
11204 XEXP (PATTERN (PREV_INSN (p)), 0)))
11213 = emit_insn_before (gen_rtx (USE, VOIDmode,
11216 REG_NOTES (use_insn)
11217 = gen_rtx (EXPR_LIST, REG_DEAD, piece,
11218 REG_NOTES (use_insn));
11224 /* Check for the case where the register dying partially
11225 overlaps the register set by this insn. */
11227 for (i = regno; i < endregno; i++)
11228 if (dead_or_set_regno_p (place, i))
11236 /* Put only REG_DEAD notes for pieces that are
11237 still used and that are not already dead or set. */
11239 for (i = regno; i < endregno; i++)
11241 rtx piece = gen_rtx (REG, reg_raw_mode[i], i);
11243 if ((reg_referenced_p (piece, PATTERN (place))
11244 || (GET_CODE (place) == CALL_INSN
11245 && find_reg_fusage (place, USE, piece)))
11246 && ! dead_or_set_p (place, piece)
11247 && ! reg_bitfield_target_p (piece,
11249 REG_NOTES (place) = gen_rtx (EXPR_LIST, REG_DEAD,
11251 REG_NOTES (place));
11261 /* Any other notes should not be present at this point in the
11268 XEXP (note, 1) = REG_NOTES (place);
11269 REG_NOTES (place) = note;
11271 else if ((REG_NOTE_KIND (note) == REG_DEAD
11272 || REG_NOTE_KIND (note) == REG_UNUSED)
11273 && GET_CODE (XEXP (note, 0)) == REG)
11274 reg_n_deaths[REGNO (XEXP (note, 0))]--;
11278 if ((REG_NOTE_KIND (note) == REG_DEAD
11279 || REG_NOTE_KIND (note) == REG_UNUSED)
11280 && GET_CODE (XEXP (note, 0)) == REG)
11281 reg_n_deaths[REGNO (XEXP (note, 0))]++;
11283 REG_NOTES (place2) = gen_rtx (GET_CODE (note), REG_NOTE_KIND (note),
11284 XEXP (note, 0), REG_NOTES (place2));
11289 /* Similarly to above, distribute the LOG_LINKS that used to be present on
11290 I3, I2, and I1 to new locations. This is also called in one case to
11291 add a link pointing at I3 when I3's destination is changed. */
11294 distribute_links (links)
11297 rtx link, next_link;
11299 for (link = links; link; link = next_link)
11305 next_link = XEXP (link, 1);
11307 /* If the insn that this link points to is a NOTE or isn't a single
11308 set, ignore it. In the latter case, it isn't clear what we
11309 can do other than ignore the link, since we can't tell which
11310 register it was for. Such links wouldn't be used by combine
11313 It is not possible for the destination of the target of the link to
11314 have been changed by combine. The only potential of this is if we
11315 replace I3, I2, and I1 by I3 and I2. But in that case the
11316 destination of I2 also remains unchanged. */
11318 if (GET_CODE (XEXP (link, 0)) == NOTE
11319 || (set = single_set (XEXP (link, 0))) == 0)
11322 reg = SET_DEST (set);
11323 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
11324 || GET_CODE (reg) == SIGN_EXTRACT
11325 || GET_CODE (reg) == STRICT_LOW_PART)
11326 reg = XEXP (reg, 0);
11328 /* A LOG_LINK is defined as being placed on the first insn that uses
11329 a register and points to the insn that sets the register. Start
11330 searching at the next insn after the target of the link and stop
11331 when we reach a set of the register or the end of the basic block.
11333 Note that this correctly handles the link that used to point from
11334 I3 to I2. Also note that not much searching is typically done here
11335 since most links don't point very far away. */
11337 for (insn = NEXT_INSN (XEXP (link, 0));
11338 (insn && (this_basic_block == n_basic_blocks - 1
11339 || basic_block_head[this_basic_block + 1] != insn));
11340 insn = NEXT_INSN (insn))
11341 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
11342 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
11344 if (reg_referenced_p (reg, PATTERN (insn)))
11348 else if (GET_CODE (insn) == CALL_INSN
11349 && find_reg_fusage (insn, USE, reg))
11355 /* If we found a place to put the link, place it there unless there
11356 is already a link to the same insn as LINK at that point. */
11362 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
11363 if (XEXP (link2, 0) == XEXP (link, 0))
11368 XEXP (link, 1) = LOG_LINKS (place);
11369 LOG_LINKS (place) = link;
11371 /* Set added_links_insn to the earliest insn we added a
11373 if (added_links_insn == 0
11374 || INSN_CUID (added_links_insn) > INSN_CUID (place))
11375 added_links_insn = place;
11381 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
11387 while (insn != 0 && INSN_UID (insn) > max_uid_cuid
11388 && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE)
11389 insn = NEXT_INSN (insn);
11391 if (INSN_UID (insn) > max_uid_cuid)
11394 return INSN_CUID (insn);
11398 dump_combine_stats (file)
11403 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
11404 combine_attempts, combine_merges, combine_extras, combine_successes);
11408 dump_combine_total_stats (file)
11413 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
11414 total_attempts, total_merges, total_extras, total_successes);
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