1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - reg_n_refs is not adjusted in the rare case when a register is
57 no longer required in a computation
58 - there are extremely rare cases (see distribute_notes) when a
60 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
61 removed because there is no way to know which register it was
64 To simplify substitution, we combine only when the earlier insn(s)
65 consist of only a single assignment. To simplify updating afterward,
66 we never combine when a subroutine call appears in the middle.
68 Since we do not represent assignments to CC0 explicitly except when that
69 is all an insn does, there is no LOG_LINKS entry in an insn that uses
70 the condition code for the insn that set the condition code.
71 Fortunately, these two insns must be consecutive.
72 Therefore, every JUMP_INSN is taken to have an implicit logical link
73 to the preceding insn. This is not quite right, since non-jumps can
74 also use the condition code; but in practice such insns would not
79 #include "coretypes.h"
86 #include "hard-reg-set.h"
87 #include "basic-block.h"
88 #include "insn-config.h"
90 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
92 #include "insn-attr.h"
98 #include "insn-codes.h"
99 #include "rtlhooks-def.h"
100 /* Include output.h for dump_file. */
104 #include "tree-pass.h"
106 /* Number of attempts to combine instructions in this function. */
108 static int combine_attempts;
110 /* Number of attempts that got as far as substitution in this function. */
112 static int combine_merges;
114 /* Number of instructions combined with added SETs in this function. */
116 static int combine_extras;
118 /* Number of instructions combined in this function. */
120 static int combine_successes;
122 /* Totals over entire compilation. */
124 static int total_attempts, total_merges, total_extras, total_successes;
127 /* Vector mapping INSN_UIDs to cuids.
128 The cuids are like uids but increase monotonically always.
129 Combine always uses cuids so that it can compare them.
130 But actually renumbering the uids, which we used to do,
131 proves to be a bad idea because it makes it hard to compare
132 the dumps produced by earlier passes with those from later passes. */
134 static int *uid_cuid;
135 static int max_uid_cuid;
137 /* Get the cuid of an insn. */
139 #define INSN_CUID(INSN) \
140 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
142 /* Maximum register number, which is the size of the tables below. */
144 static unsigned int combine_max_regno;
147 /* Record last point of death of (hard or pseudo) register n. */
150 /* Record last point of modification of (hard or pseudo) register n. */
153 /* The next group of fields allows the recording of the last value assigned
154 to (hard or pseudo) register n. We use this information to see if an
155 operation being processed is redundant given a prior operation performed
156 on the register. For example, an `and' with a constant is redundant if
157 all the zero bits are already known to be turned off.
159 We use an approach similar to that used by cse, but change it in the
162 (1) We do not want to reinitialize at each label.
163 (2) It is useful, but not critical, to know the actual value assigned
164 to a register. Often just its form is helpful.
166 Therefore, we maintain the following fields:
168 last_set_value the last value assigned
169 last_set_label records the value of label_tick when the
170 register was assigned
171 last_set_table_tick records the value of label_tick when a
172 value using the register is assigned
173 last_set_invalid set to nonzero when it is not valid
174 to use the value of this register in some
177 To understand the usage of these tables, it is important to understand
178 the distinction between the value in last_set_value being valid and
179 the register being validly contained in some other expression in the
182 (The next two parameters are out of date).
184 reg_stat[i].last_set_value is valid if it is nonzero, and either
185 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
187 Register I may validly appear in any expression returned for the value
188 of another register if reg_n_sets[i] is 1. It may also appear in the
189 value for register J if reg_stat[j].last_set_invalid is zero, or
190 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
192 If an expression is found in the table containing a register which may
193 not validly appear in an expression, the register is replaced by
194 something that won't match, (clobber (const_int 0)). */
196 /* Record last value assigned to (hard or pseudo) register n. */
200 /* Record the value of label_tick when an expression involving register n
201 is placed in last_set_value. */
203 int last_set_table_tick;
205 /* Record the value of label_tick when the value for register n is placed in
210 /* These fields are maintained in parallel with last_set_value and are
211 used to store the mode in which the register was last set, the bits
212 that were known to be zero when it was last set, and the number of
213 sign bits copies it was known to have when it was last set. */
215 unsigned HOST_WIDE_INT last_set_nonzero_bits;
216 char last_set_sign_bit_copies;
217 ENUM_BITFIELD(machine_mode) last_set_mode : 8;
219 /* Set nonzero if references to register n in expressions should not be
220 used. last_set_invalid is set nonzero when this register is being
221 assigned to and last_set_table_tick == label_tick. */
223 char last_set_invalid;
225 /* Some registers that are set more than once and used in more than one
226 basic block are nevertheless always set in similar ways. For example,
227 a QImode register may be loaded from memory in two places on a machine
228 where byte loads zero extend.
230 We record in the following fields if a register has some leading bits
231 that are always equal to the sign bit, and what we know about the
232 nonzero bits of a register, specifically which bits are known to be
235 If an entry is zero, it means that we don't know anything special. */
237 unsigned char sign_bit_copies;
239 unsigned HOST_WIDE_INT nonzero_bits;
241 /* Record the value of the label_tick when the last truncation
242 happened. The field truncated_to_mode is only valid if
243 truncation_label == label_tick. */
245 int truncation_label;
247 /* Record the last truncation seen for this register. If truncation
248 is not a nop to this mode we might be able to save an explicit
249 truncation if we know that value already contains a truncated
252 ENUM_BITFIELD(machine_mode) truncated_to_mode : 8;
255 static struct reg_stat *reg_stat;
257 /* Record the cuid of the last insn that invalidated memory
258 (anything that writes memory, and subroutine calls, but not pushes). */
260 static int mem_last_set;
262 /* Record the cuid of the last CALL_INSN
263 so we can tell whether a potential combination crosses any calls. */
265 static int last_call_cuid;
267 /* When `subst' is called, this is the insn that is being modified
268 (by combining in a previous insn). The PATTERN of this insn
269 is still the old pattern partially modified and it should not be
270 looked at, but this may be used to examine the successors of the insn
271 to judge whether a simplification is valid. */
273 static rtx subst_insn;
275 /* This is the lowest CUID that `subst' is currently dealing with.
276 get_last_value will not return a value if the register was set at or
277 after this CUID. If not for this mechanism, we could get confused if
278 I2 or I1 in try_combine were an insn that used the old value of a register
279 to obtain a new value. In that case, we might erroneously get the
280 new value of the register when we wanted the old one. */
282 static int subst_low_cuid;
284 /* This contains any hard registers that are used in newpat; reg_dead_at_p
285 must consider all these registers to be always live. */
287 static HARD_REG_SET newpat_used_regs;
289 /* This is an insn to which a LOG_LINKS entry has been added. If this
290 insn is the earlier than I2 or I3, combine should rescan starting at
293 static rtx added_links_insn;
295 /* Basic block in which we are performing combines. */
296 static basic_block this_basic_block;
298 /* A bitmap indicating which blocks had registers go dead at entry.
299 After combine, we'll need to re-do global life analysis with
300 those blocks as starting points. */
301 static sbitmap refresh_blocks;
303 /* The following array records the insn_rtx_cost for every insn
304 in the instruction stream. */
306 static int *uid_insn_cost;
308 /* Length of the currently allocated uid_insn_cost array. */
310 static int last_insn_cost;
312 /* Incremented for each label. */
314 static int label_tick;
316 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
317 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
319 static enum machine_mode nonzero_bits_mode;
321 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
322 be safely used. It is zero while computing them and after combine has
323 completed. This former test prevents propagating values based on
324 previously set values, which can be incorrect if a variable is modified
327 static int nonzero_sign_valid;
330 /* Record one modification to rtl structure
331 to be undone by storing old_contents into *where. */
336 enum { UNDO_RTX, UNDO_INT, UNDO_MODE } kind;
337 union { rtx r; int i; enum machine_mode m; } old_contents;
338 union { rtx *r; int *i; } where;
341 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
342 num_undo says how many are currently recorded.
344 other_insn is nonzero if we have modified some other insn in the process
345 of working on subst_insn. It must be verified too. */
354 static struct undobuf undobuf;
356 /* Number of times the pseudo being substituted for
357 was found and replaced. */
359 static int n_occurrences;
361 static rtx reg_nonzero_bits_for_combine (rtx, enum machine_mode, rtx,
363 unsigned HOST_WIDE_INT,
364 unsigned HOST_WIDE_INT *);
365 static rtx reg_num_sign_bit_copies_for_combine (rtx, enum machine_mode, rtx,
367 unsigned int, unsigned int *);
368 static void do_SUBST (rtx *, rtx);
369 static void do_SUBST_INT (int *, int);
370 static void init_reg_last (void);
371 static void setup_incoming_promotions (void);
372 static void set_nonzero_bits_and_sign_copies (rtx, rtx, void *);
373 static int cant_combine_insn_p (rtx);
374 static int can_combine_p (rtx, rtx, rtx, rtx, rtx *, rtx *);
375 static int combinable_i3pat (rtx, rtx *, rtx, rtx, int, rtx *);
376 static int contains_muldiv (rtx);
377 static rtx try_combine (rtx, rtx, rtx, int *);
378 static void undo_all (void);
379 static void undo_commit (void);
380 static rtx *find_split_point (rtx *, rtx);
381 static rtx subst (rtx, rtx, rtx, int, int);
382 static rtx combine_simplify_rtx (rtx, enum machine_mode, int);
383 static rtx simplify_if_then_else (rtx);
384 static rtx simplify_set (rtx);
385 static rtx simplify_logical (rtx);
386 static rtx expand_compound_operation (rtx);
387 static rtx expand_field_assignment (rtx);
388 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
389 rtx, unsigned HOST_WIDE_INT, int, int, int);
390 static rtx extract_left_shift (rtx, int);
391 static rtx make_compound_operation (rtx, enum rtx_code);
392 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
393 unsigned HOST_WIDE_INT *);
394 static rtx canon_reg_for_combine (rtx, rtx);
395 static rtx force_to_mode (rtx, enum machine_mode,
396 unsigned HOST_WIDE_INT, int);
397 static rtx if_then_else_cond (rtx, rtx *, rtx *);
398 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
399 static int rtx_equal_for_field_assignment_p (rtx, rtx);
400 static rtx make_field_assignment (rtx);
401 static rtx apply_distributive_law (rtx);
402 static rtx distribute_and_simplify_rtx (rtx, int);
403 static rtx simplify_and_const_int_1 (enum machine_mode, rtx,
404 unsigned HOST_WIDE_INT);
405 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
406 unsigned HOST_WIDE_INT);
407 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
408 HOST_WIDE_INT, enum machine_mode, int *);
409 static rtx simplify_shift_const_1 (enum rtx_code, enum machine_mode, rtx, int);
410 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
412 static int recog_for_combine (rtx *, rtx, rtx *);
413 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
414 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
415 static void update_table_tick (rtx);
416 static void record_value_for_reg (rtx, rtx, rtx);
417 static void check_conversions (rtx, rtx);
418 static void record_dead_and_set_regs_1 (rtx, rtx, void *);
419 static void record_dead_and_set_regs (rtx);
420 static int get_last_value_validate (rtx *, rtx, int, int);
421 static rtx get_last_value (rtx);
422 static int use_crosses_set_p (rtx, int);
423 static void reg_dead_at_p_1 (rtx, rtx, void *);
424 static int reg_dead_at_p (rtx, rtx);
425 static void move_deaths (rtx, rtx, int, rtx, rtx *);
426 static int reg_bitfield_target_p (rtx, rtx);
427 static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx);
428 static void distribute_links (rtx);
429 static void mark_used_regs_combine (rtx);
430 static int insn_cuid (rtx);
431 static void record_promoted_value (rtx, rtx);
432 static int unmentioned_reg_p_1 (rtx *, void *);
433 static bool unmentioned_reg_p (rtx, rtx);
434 static void record_truncated_value (rtx);
435 static bool reg_truncated_to_mode (enum machine_mode, rtx);
436 static rtx gen_lowpart_or_truncate (enum machine_mode, rtx);
439 /* It is not safe to use ordinary gen_lowpart in combine.
440 See comments in gen_lowpart_for_combine. */
441 #undef RTL_HOOKS_GEN_LOWPART
442 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
444 /* Our implementation of gen_lowpart never emits a new pseudo. */
445 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
446 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
448 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
449 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
451 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
452 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
454 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
455 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
457 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
460 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
461 insn. The substitution can be undone by undo_all. If INTO is already
462 set to NEWVAL, do not record this change. Because computing NEWVAL might
463 also call SUBST, we have to compute it before we put anything into
467 do_SUBST (rtx *into, rtx newval)
472 if (oldval == newval)
475 /* We'd like to catch as many invalid transformations here as
476 possible. Unfortunately, there are way too many mode changes
477 that are perfectly valid, so we'd waste too much effort for
478 little gain doing the checks here. Focus on catching invalid
479 transformations involving integer constants. */
480 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
481 && GET_CODE (newval) == CONST_INT)
483 /* Sanity check that we're replacing oldval with a CONST_INT
484 that is a valid sign-extension for the original mode. */
485 gcc_assert (INTVAL (newval)
486 == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
488 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
489 CONST_INT is not valid, because after the replacement, the
490 original mode would be gone. Unfortunately, we can't tell
491 when do_SUBST is called to replace the operand thereof, so we
492 perform this test on oldval instead, checking whether an
493 invalid replacement took place before we got here. */
494 gcc_assert (!(GET_CODE (oldval) == SUBREG
495 && GET_CODE (SUBREG_REG (oldval)) == CONST_INT));
496 gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
497 && GET_CODE (XEXP (oldval, 0)) == CONST_INT));
501 buf = undobuf.frees, undobuf.frees = buf->next;
503 buf = XNEW (struct undo);
505 buf->kind = UNDO_RTX;
507 buf->old_contents.r = oldval;
510 buf->next = undobuf.undos, undobuf.undos = buf;
513 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
515 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
516 for the value of a HOST_WIDE_INT value (including CONST_INT) is
520 do_SUBST_INT (int *into, int newval)
525 if (oldval == newval)
529 buf = undobuf.frees, undobuf.frees = buf->next;
531 buf = XNEW (struct undo);
533 buf->kind = UNDO_INT;
535 buf->old_contents.i = oldval;
538 buf->next = undobuf.undos, undobuf.undos = buf;
541 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
543 /* Similar to SUBST, but just substitute the mode. This is used when
544 changing the mode of a pseudo-register, so that any other
545 references to the entry in the regno_reg_rtx array will change as
549 do_SUBST_MODE (rtx *into, enum machine_mode newval)
552 enum machine_mode oldval = GET_MODE (*into);
554 if (oldval == newval)
558 buf = undobuf.frees, undobuf.frees = buf->next;
560 buf = XNEW (struct undo);
562 buf->kind = UNDO_MODE;
564 buf->old_contents.m = oldval;
565 PUT_MODE (*into, newval);
567 buf->next = undobuf.undos, undobuf.undos = buf;
570 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE(&(INTO), (NEWVAL))
572 /* Subroutine of try_combine. Determine whether the combine replacement
573 patterns NEWPAT and NEWI2PAT are cheaper according to insn_rtx_cost
574 that the original instruction sequence I1, I2 and I3. Note that I1
575 and/or NEWI2PAT may be NULL_RTX. This function returns false, if the
576 costs of all instructions can be estimated, and the replacements are
577 more expensive than the original sequence. */
580 combine_validate_cost (rtx i1, rtx i2, rtx i3, rtx newpat, rtx newi2pat)
582 int i1_cost, i2_cost, i3_cost;
583 int new_i2_cost, new_i3_cost;
584 int old_cost, new_cost;
586 /* Lookup the original insn_rtx_costs. */
587 i2_cost = INSN_UID (i2) <= last_insn_cost
588 ? uid_insn_cost[INSN_UID (i2)] : 0;
589 i3_cost = INSN_UID (i3) <= last_insn_cost
590 ? uid_insn_cost[INSN_UID (i3)] : 0;
594 i1_cost = INSN_UID (i1) <= last_insn_cost
595 ? uid_insn_cost[INSN_UID (i1)] : 0;
596 old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0)
597 ? i1_cost + i2_cost + i3_cost : 0;
601 old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
605 /* Calculate the replacement insn_rtx_costs. */
606 new_i3_cost = insn_rtx_cost (newpat);
609 new_i2_cost = insn_rtx_cost (newi2pat);
610 new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
611 ? new_i2_cost + new_i3_cost : 0;
615 new_cost = new_i3_cost;
619 if (undobuf.other_insn)
621 int old_other_cost, new_other_cost;
623 old_other_cost = (INSN_UID (undobuf.other_insn) <= last_insn_cost
624 ? uid_insn_cost[INSN_UID (undobuf.other_insn)] : 0);
625 new_other_cost = insn_rtx_cost (PATTERN (undobuf.other_insn));
626 if (old_other_cost > 0 && new_other_cost > 0)
628 old_cost += old_other_cost;
629 new_cost += new_other_cost;
635 /* Disallow this recombination if both new_cost and old_cost are
636 greater than zero, and new_cost is greater than old cost. */
638 && new_cost > old_cost)
645 "rejecting combination of insns %d, %d and %d\n",
646 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
647 fprintf (dump_file, "original costs %d + %d + %d = %d\n",
648 i1_cost, i2_cost, i3_cost, old_cost);
653 "rejecting combination of insns %d and %d\n",
654 INSN_UID (i2), INSN_UID (i3));
655 fprintf (dump_file, "original costs %d + %d = %d\n",
656 i2_cost, i3_cost, old_cost);
661 fprintf (dump_file, "replacement costs %d + %d = %d\n",
662 new_i2_cost, new_i3_cost, new_cost);
665 fprintf (dump_file, "replacement cost %d\n", new_cost);
671 /* Update the uid_insn_cost array with the replacement costs. */
672 uid_insn_cost[INSN_UID (i2)] = new_i2_cost;
673 uid_insn_cost[INSN_UID (i3)] = new_i3_cost;
675 uid_insn_cost[INSN_UID (i1)] = 0;
680 /* Main entry point for combiner. F is the first insn of the function.
681 NREGS is the first unused pseudo-reg number.
683 Return nonzero if the combiner has turned an indirect jump
684 instruction into a direct jump. */
686 combine_instructions (rtx f, unsigned int nregs)
694 rtx links, nextlinks;
695 sbitmap_iterator sbi;
697 int new_direct_jump_p = 0;
699 combine_attempts = 0;
702 combine_successes = 0;
704 combine_max_regno = nregs;
706 rtl_hooks = combine_rtl_hooks;
708 reg_stat = XCNEWVEC (struct reg_stat, nregs);
710 init_recog_no_volatile ();
712 /* Compute maximum uid value so uid_cuid can be allocated. */
714 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
715 if (INSN_UID (insn) > i)
718 uid_cuid = XNEWVEC (int, i + 1);
721 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
723 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
724 problems when, for example, we have j <<= 1 in a loop. */
726 nonzero_sign_valid = 0;
728 /* Compute the mapping from uids to cuids.
729 Cuids are numbers assigned to insns, like uids,
730 except that cuids increase monotonically through the code.
732 Scan all SETs and see if we can deduce anything about what
733 bits are known to be zero for some registers and how many copies
734 of the sign bit are known to exist for those registers.
736 Also set any known values so that we can use it while searching
737 for what bits are known to be set. */
741 setup_incoming_promotions ();
743 refresh_blocks = sbitmap_alloc (last_basic_block);
744 sbitmap_zero (refresh_blocks);
746 /* Allocate array of current insn_rtx_costs. */
747 uid_insn_cost = XCNEWVEC (int, max_uid_cuid + 1);
748 last_insn_cost = max_uid_cuid;
750 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
752 uid_cuid[INSN_UID (insn)] = ++i;
758 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
760 record_dead_and_set_regs (insn);
763 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
764 if (REG_NOTE_KIND (links) == REG_INC)
765 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
769 /* Record the current insn_rtx_cost of this instruction. */
770 if (NONJUMP_INSN_P (insn))
771 uid_insn_cost[INSN_UID (insn)] = insn_rtx_cost (PATTERN (insn));
773 fprintf(dump_file, "insn_cost %d: %d\n",
774 INSN_UID (insn), uid_insn_cost[INSN_UID (insn)]);
781 nonzero_sign_valid = 1;
783 /* Now scan all the insns in forward order. */
789 setup_incoming_promotions ();
791 FOR_EACH_BB (this_basic_block)
793 for (insn = BB_HEAD (this_basic_block);
794 insn != NEXT_INSN (BB_END (this_basic_block));
795 insn = next ? next : NEXT_INSN (insn))
802 else if (INSN_P (insn))
804 /* See if we know about function return values before this
805 insn based upon SUBREG flags. */
806 check_conversions (insn, PATTERN (insn));
808 /* Try this insn with each insn it links back to. */
810 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
811 if ((next = try_combine (insn, XEXP (links, 0),
812 NULL_RTX, &new_direct_jump_p)) != 0)
815 /* Try each sequence of three linked insns ending with this one. */
817 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
819 rtx link = XEXP (links, 0);
821 /* If the linked insn has been replaced by a note, then there
822 is no point in pursuing this chain any further. */
826 for (nextlinks = LOG_LINKS (link);
828 nextlinks = XEXP (nextlinks, 1))
829 if ((next = try_combine (insn, link,
831 &new_direct_jump_p)) != 0)
836 /* Try to combine a jump insn that uses CC0
837 with a preceding insn that sets CC0, and maybe with its
838 logical predecessor as well.
839 This is how we make decrement-and-branch insns.
840 We need this special code because data flow connections
841 via CC0 do not get entered in LOG_LINKS. */
844 && (prev = prev_nonnote_insn (insn)) != 0
845 && NONJUMP_INSN_P (prev)
846 && sets_cc0_p (PATTERN (prev)))
848 if ((next = try_combine (insn, prev,
849 NULL_RTX, &new_direct_jump_p)) != 0)
852 for (nextlinks = LOG_LINKS (prev); nextlinks;
853 nextlinks = XEXP (nextlinks, 1))
854 if ((next = try_combine (insn, prev,
856 &new_direct_jump_p)) != 0)
860 /* Do the same for an insn that explicitly references CC0. */
861 if (NONJUMP_INSN_P (insn)
862 && (prev = prev_nonnote_insn (insn)) != 0
863 && NONJUMP_INSN_P (prev)
864 && sets_cc0_p (PATTERN (prev))
865 && GET_CODE (PATTERN (insn)) == SET
866 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
868 if ((next = try_combine (insn, prev,
869 NULL_RTX, &new_direct_jump_p)) != 0)
872 for (nextlinks = LOG_LINKS (prev); nextlinks;
873 nextlinks = XEXP (nextlinks, 1))
874 if ((next = try_combine (insn, prev,
876 &new_direct_jump_p)) != 0)
880 /* Finally, see if any of the insns that this insn links to
881 explicitly references CC0. If so, try this insn, that insn,
882 and its predecessor if it sets CC0. */
883 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
884 if (NONJUMP_INSN_P (XEXP (links, 0))
885 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
886 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
887 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
888 && NONJUMP_INSN_P (prev)
889 && sets_cc0_p (PATTERN (prev))
890 && (next = try_combine (insn, XEXP (links, 0),
891 prev, &new_direct_jump_p)) != 0)
895 /* Try combining an insn with two different insns whose results it
897 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
898 for (nextlinks = XEXP (links, 1); nextlinks;
899 nextlinks = XEXP (nextlinks, 1))
900 if ((next = try_combine (insn, XEXP (links, 0),
902 &new_direct_jump_p)) != 0)
905 /* Try this insn with each REG_EQUAL note it links back to. */
906 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
909 rtx temp = XEXP (links, 0);
910 if ((set = single_set (temp)) != 0
911 && (note = find_reg_equal_equiv_note (temp)) != 0
912 && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
913 /* Avoid using a register that may already been marked
914 dead by an earlier instruction. */
915 && ! unmentioned_reg_p (note, SET_SRC (set))
916 && (GET_MODE (note) == VOIDmode
917 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
918 : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
920 /* Temporarily replace the set's source with the
921 contents of the REG_EQUAL note. The insn will
922 be deleted or recognized by try_combine. */
923 rtx orig = SET_SRC (set);
924 SET_SRC (set) = note;
925 next = try_combine (insn, temp, NULL_RTX,
929 SET_SRC (set) = orig;
934 record_dead_and_set_regs (insn);
943 EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks, 0, j, sbi)
944 BASIC_BLOCK (j)->flags |= BB_DIRTY;
945 new_direct_jump_p |= purge_all_dead_edges ();
946 delete_noop_moves ();
948 update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES,
949 PROP_DEATH_NOTES | PROP_SCAN_DEAD_CODE
950 | PROP_KILL_DEAD_CODE);
953 sbitmap_free (refresh_blocks);
954 free (uid_insn_cost);
959 struct undo *undo, *next;
960 for (undo = undobuf.frees; undo; undo = next)
968 total_attempts += combine_attempts;
969 total_merges += combine_merges;
970 total_extras += combine_extras;
971 total_successes += combine_successes;
973 nonzero_sign_valid = 0;
974 rtl_hooks = general_rtl_hooks;
976 /* Make recognizer allow volatile MEMs again. */
979 return new_direct_jump_p;
982 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
988 for (i = 0; i < combine_max_regno; i++)
989 memset (reg_stat + i, 0, offsetof (struct reg_stat, sign_bit_copies));
992 /* Set up any promoted values for incoming argument registers. */
995 setup_incoming_promotions (void)
999 enum machine_mode mode;
1001 rtx first = get_insns ();
1003 if (targetm.calls.promote_function_args (TREE_TYPE (cfun->decl)))
1005 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
1006 /* Check whether this register can hold an incoming pointer
1007 argument. FUNCTION_ARG_REGNO_P tests outgoing register
1008 numbers, so translate if necessary due to register windows. */
1009 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno))
1010 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
1012 record_value_for_reg
1013 (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
1016 gen_rtx_CLOBBER (mode, const0_rtx)));
1021 /* Called via note_stores. If X is a pseudo that is narrower than
1022 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1024 If we are setting only a portion of X and we can't figure out what
1025 portion, assume all bits will be used since we don't know what will
1028 Similarly, set how many bits of X are known to be copies of the sign bit
1029 at all locations in the function. This is the smallest number implied
1033 set_nonzero_bits_and_sign_copies (rtx x, rtx set,
1034 void *data ATTRIBUTE_UNUSED)
1039 && REGNO (x) >= FIRST_PSEUDO_REGISTER
1040 /* If this register is undefined at the start of the file, we can't
1041 say what its contents were. */
1042 && ! REGNO_REG_SET_P
1043 (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start, REGNO (x))
1044 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
1046 if (set == 0 || GET_CODE (set) == CLOBBER)
1048 reg_stat[REGNO (x)].nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1049 reg_stat[REGNO (x)].sign_bit_copies = 1;
1053 /* If this is a complex assignment, see if we can convert it into a
1054 simple assignment. */
1055 set = expand_field_assignment (set);
1057 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1058 set what we know about X. */
1060 if (SET_DEST (set) == x
1061 || (GET_CODE (SET_DEST (set)) == SUBREG
1062 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
1063 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
1064 && SUBREG_REG (SET_DEST (set)) == x))
1066 rtx src = SET_SRC (set);
1068 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1069 /* If X is narrower than a word and SRC is a non-negative
1070 constant that would appear negative in the mode of X,
1071 sign-extend it for use in reg_stat[].nonzero_bits because some
1072 machines (maybe most) will actually do the sign-extension
1073 and this is the conservative approach.
1075 ??? For 2.5, try to tighten up the MD files in this regard
1076 instead of this kludge. */
1078 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
1079 && GET_CODE (src) == CONST_INT
1081 && 0 != (INTVAL (src)
1082 & ((HOST_WIDE_INT) 1
1083 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
1084 src = GEN_INT (INTVAL (src)
1085 | ((HOST_WIDE_INT) (-1)
1086 << GET_MODE_BITSIZE (GET_MODE (x))));
1089 /* Don't call nonzero_bits if it cannot change anything. */
1090 if (reg_stat[REGNO (x)].nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1091 reg_stat[REGNO (x)].nonzero_bits
1092 |= nonzero_bits (src, nonzero_bits_mode);
1093 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1094 if (reg_stat[REGNO (x)].sign_bit_copies == 0
1095 || reg_stat[REGNO (x)].sign_bit_copies > num)
1096 reg_stat[REGNO (x)].sign_bit_copies = num;
1100 reg_stat[REGNO (x)].nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1101 reg_stat[REGNO (x)].sign_bit_copies = 1;
1106 /* See if INSN can be combined into I3. PRED and SUCC are optionally
1107 insns that were previously combined into I3 or that will be combined
1108 into the merger of INSN and I3.
1110 Return 0 if the combination is not allowed for any reason.
1112 If the combination is allowed, *PDEST will be set to the single
1113 destination of INSN and *PSRC to the single source, and this function
1117 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED, rtx succ,
1118 rtx *pdest, rtx *psrc)
1121 rtx set = 0, src, dest;
1126 int all_adjacent = (succ ? (next_active_insn (insn) == succ
1127 && next_active_insn (succ) == i3)
1128 : next_active_insn (insn) == i3);
1130 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1131 or a PARALLEL consisting of such a SET and CLOBBERs.
1133 If INSN has CLOBBER parallel parts, ignore them for our processing.
1134 By definition, these happen during the execution of the insn. When it
1135 is merged with another insn, all bets are off. If they are, in fact,
1136 needed and aren't also supplied in I3, they may be added by
1137 recog_for_combine. Otherwise, it won't match.
1139 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1142 Get the source and destination of INSN. If more than one, can't
1145 if (GET_CODE (PATTERN (insn)) == SET)
1146 set = PATTERN (insn);
1147 else if (GET_CODE (PATTERN (insn)) == PARALLEL
1148 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1150 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1152 rtx elt = XVECEXP (PATTERN (insn), 0, i);
1155 switch (GET_CODE (elt))
1157 /* This is important to combine floating point insns
1158 for the SH4 port. */
1160 /* Combining an isolated USE doesn't make sense.
1161 We depend here on combinable_i3pat to reject them. */
1162 /* The code below this loop only verifies that the inputs of
1163 the SET in INSN do not change. We call reg_set_between_p
1164 to verify that the REG in the USE does not change between
1166 If the USE in INSN was for a pseudo register, the matching
1167 insn pattern will likely match any register; combining this
1168 with any other USE would only be safe if we knew that the
1169 used registers have identical values, or if there was
1170 something to tell them apart, e.g. different modes. For
1171 now, we forgo such complicated tests and simply disallow
1172 combining of USES of pseudo registers with any other USE. */
1173 if (REG_P (XEXP (elt, 0))
1174 && GET_CODE (PATTERN (i3)) == PARALLEL)
1176 rtx i3pat = PATTERN (i3);
1177 int i = XVECLEN (i3pat, 0) - 1;
1178 unsigned int regno = REGNO (XEXP (elt, 0));
1182 rtx i3elt = XVECEXP (i3pat, 0, i);
1184 if (GET_CODE (i3elt) == USE
1185 && REG_P (XEXP (i3elt, 0))
1186 && (REGNO (XEXP (i3elt, 0)) == regno
1187 ? reg_set_between_p (XEXP (elt, 0),
1188 PREV_INSN (insn), i3)
1189 : regno >= FIRST_PSEUDO_REGISTER))
1196 /* We can ignore CLOBBERs. */
1201 /* Ignore SETs whose result isn't used but not those that
1202 have side-effects. */
1203 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1204 && (!(note = find_reg_note (insn, REG_EH_REGION, NULL_RTX))
1205 || INTVAL (XEXP (note, 0)) <= 0)
1206 && ! side_effects_p (elt))
1209 /* If we have already found a SET, this is a second one and
1210 so we cannot combine with this insn. */
1218 /* Anything else means we can't combine. */
1224 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1225 so don't do anything with it. */
1226 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1235 set = expand_field_assignment (set);
1236 src = SET_SRC (set), dest = SET_DEST (set);
1238 /* Don't eliminate a store in the stack pointer. */
1239 if (dest == stack_pointer_rtx
1240 /* Don't combine with an insn that sets a register to itself if it has
1241 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1242 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1243 /* Can't merge an ASM_OPERANDS. */
1244 || GET_CODE (src) == ASM_OPERANDS
1245 /* Can't merge a function call. */
1246 || GET_CODE (src) == CALL
1247 /* Don't eliminate a function call argument. */
1249 && (find_reg_fusage (i3, USE, dest)
1251 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1252 && global_regs[REGNO (dest)])))
1253 /* Don't substitute into an incremented register. */
1254 || FIND_REG_INC_NOTE (i3, dest)
1255 || (succ && FIND_REG_INC_NOTE (succ, dest))
1256 /* Don't substitute into a non-local goto, this confuses CFG. */
1257 || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1259 /* Don't combine the end of a libcall into anything. */
1260 /* ??? This gives worse code, and appears to be unnecessary, since no
1261 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1262 use REG_RETVAL notes for noconflict blocks, but other code here
1263 makes sure that those insns don't disappear. */
1264 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
1266 /* Make sure that DEST is not used after SUCC but before I3. */
1267 || (succ && ! all_adjacent
1268 && reg_used_between_p (dest, succ, i3))
1269 /* Make sure that the value that is to be substituted for the register
1270 does not use any registers whose values alter in between. However,
1271 If the insns are adjacent, a use can't cross a set even though we
1272 think it might (this can happen for a sequence of insns each setting
1273 the same destination; last_set of that register might point to
1274 a NOTE). If INSN has a REG_EQUIV note, the register is always
1275 equivalent to the memory so the substitution is valid even if there
1276 are intervening stores. Also, don't move a volatile asm or
1277 UNSPEC_VOLATILE across any other insns. */
1280 || ! find_reg_note (insn, REG_EQUIV, src))
1281 && use_crosses_set_p (src, INSN_CUID (insn)))
1282 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1283 || GET_CODE (src) == UNSPEC_VOLATILE))
1284 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1285 better register allocation by not doing the combine. */
1286 || find_reg_note (i3, REG_NO_CONFLICT, dest)
1287 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
1288 /* Don't combine across a CALL_INSN, because that would possibly
1289 change whether the life span of some REGs crosses calls or not,
1290 and it is a pain to update that information.
1291 Exception: if source is a constant, moving it later can't hurt.
1292 Accept that special case, because it helps -fforce-addr a lot. */
1293 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
1296 /* DEST must either be a REG or CC0. */
1299 /* If register alignment is being enforced for multi-word items in all
1300 cases except for parameters, it is possible to have a register copy
1301 insn referencing a hard register that is not allowed to contain the
1302 mode being copied and which would not be valid as an operand of most
1303 insns. Eliminate this problem by not combining with such an insn.
1305 Also, on some machines we don't want to extend the life of a hard
1309 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1310 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1311 /* Don't extend the life of a hard register unless it is
1312 user variable (if we have few registers) or it can't
1313 fit into the desired register (meaning something special
1315 Also avoid substituting a return register into I3, because
1316 reload can't handle a conflict with constraints of other
1318 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1319 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1322 else if (GET_CODE (dest) != CC0)
1326 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1327 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1328 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1330 /* Don't substitute for a register intended as a clobberable
1332 rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1333 if (rtx_equal_p (reg, dest))
1336 /* If the clobber represents an earlyclobber operand, we must not
1337 substitute an expression containing the clobbered register.
1338 As we do not analyze the constraint strings here, we have to
1339 make the conservative assumption. However, if the register is
1340 a fixed hard reg, the clobber cannot represent any operand;
1341 we leave it up to the machine description to either accept or
1342 reject use-and-clobber patterns. */
1344 || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1345 || !fixed_regs[REGNO (reg)])
1346 if (reg_overlap_mentioned_p (reg, src))
1350 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1351 or not), reject, unless nothing volatile comes between it and I3 */
1353 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1355 /* Make sure succ doesn't contain a volatile reference. */
1356 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1359 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1360 if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1364 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1365 to be an explicit register variable, and was chosen for a reason. */
1367 if (GET_CODE (src) == ASM_OPERANDS
1368 && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1371 /* If there are any volatile insns between INSN and I3, reject, because
1372 they might affect machine state. */
1374 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1375 if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1378 /* If INSN contains an autoincrement or autodecrement, make sure that
1379 register is not used between there and I3, and not already used in
1380 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1381 Also insist that I3 not be a jump; if it were one
1382 and the incremented register were spilled, we would lose. */
1385 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1386 if (REG_NOTE_KIND (link) == REG_INC
1388 || reg_used_between_p (XEXP (link, 0), insn, i3)
1389 || (pred != NULL_RTX
1390 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
1391 || (succ != NULL_RTX
1392 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
1393 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1398 /* Don't combine an insn that follows a CC0-setting insn.
1399 An insn that uses CC0 must not be separated from the one that sets it.
1400 We do, however, allow I2 to follow a CC0-setting insn if that insn
1401 is passed as I1; in that case it will be deleted also.
1402 We also allow combining in this case if all the insns are adjacent
1403 because that would leave the two CC0 insns adjacent as well.
1404 It would be more logical to test whether CC0 occurs inside I1 or I2,
1405 but that would be much slower, and this ought to be equivalent. */
1407 p = prev_nonnote_insn (insn);
1408 if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
1413 /* If we get here, we have passed all the tests and the combination is
1422 /* LOC is the location within I3 that contains its pattern or the component
1423 of a PARALLEL of the pattern. We validate that it is valid for combining.
1425 One problem is if I3 modifies its output, as opposed to replacing it
1426 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1427 so would produce an insn that is not equivalent to the original insns.
1431 (set (reg:DI 101) (reg:DI 100))
1432 (set (subreg:SI (reg:DI 101) 0) <foo>)
1434 This is NOT equivalent to:
1436 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1437 (set (reg:DI 101) (reg:DI 100))])
1439 Not only does this modify 100 (in which case it might still be valid
1440 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1442 We can also run into a problem if I2 sets a register that I1
1443 uses and I1 gets directly substituted into I3 (not via I2). In that
1444 case, we would be getting the wrong value of I2DEST into I3, so we
1445 must reject the combination. This case occurs when I2 and I1 both
1446 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1447 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1448 of a SET must prevent combination from occurring.
1450 Before doing the above check, we first try to expand a field assignment
1451 into a set of logical operations.
1453 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1454 we place a register that is both set and used within I3. If more than one
1455 such register is detected, we fail.
1457 Return 1 if the combination is valid, zero otherwise. */
1460 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest,
1461 int i1_not_in_src, rtx *pi3dest_killed)
1465 if (GET_CODE (x) == SET)
1468 rtx dest = SET_DEST (set);
1469 rtx src = SET_SRC (set);
1470 rtx inner_dest = dest;
1473 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1474 || GET_CODE (inner_dest) == SUBREG
1475 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1476 inner_dest = XEXP (inner_dest, 0);
1478 /* Check for the case where I3 modifies its output, as discussed
1479 above. We don't want to prevent pseudos from being combined
1480 into the address of a MEM, so only prevent the combination if
1481 i1 or i2 set the same MEM. */
1482 if ((inner_dest != dest &&
1483 (!MEM_P (inner_dest)
1484 || rtx_equal_p (i2dest, inner_dest)
1485 || (i1dest && rtx_equal_p (i1dest, inner_dest)))
1486 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1487 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1489 /* This is the same test done in can_combine_p except we can't test
1490 all_adjacent; we don't have to, since this instruction will stay
1491 in place, thus we are not considering increasing the lifetime of
1494 Also, if this insn sets a function argument, combining it with
1495 something that might need a spill could clobber a previous
1496 function argument; the all_adjacent test in can_combine_p also
1497 checks this; here, we do a more specific test for this case. */
1499 || (REG_P (inner_dest)
1500 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1501 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1502 GET_MODE (inner_dest))))
1503 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1506 /* If DEST is used in I3, it is being killed in this insn, so
1507 record that for later. We have to consider paradoxical
1508 subregs here, since they kill the whole register, but we
1509 ignore partial subregs, STRICT_LOW_PART, etc.
1510 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1511 STACK_POINTER_REGNUM, since these are always considered to be
1512 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1514 if (GET_CODE (subdest) == SUBREG
1515 && (GET_MODE_SIZE (GET_MODE (subdest))
1516 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
1517 subdest = SUBREG_REG (subdest);
1520 && reg_referenced_p (subdest, PATTERN (i3))
1521 && REGNO (subdest) != FRAME_POINTER_REGNUM
1522 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1523 && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
1525 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1526 && (REGNO (subdest) != ARG_POINTER_REGNUM
1527 || ! fixed_regs [REGNO (subdest)])
1529 && REGNO (subdest) != STACK_POINTER_REGNUM)
1531 if (*pi3dest_killed)
1534 *pi3dest_killed = subdest;
1538 else if (GET_CODE (x) == PARALLEL)
1542 for (i = 0; i < XVECLEN (x, 0); i++)
1543 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1544 i1_not_in_src, pi3dest_killed))
1551 /* Return 1 if X is an arithmetic expression that contains a multiplication
1552 and division. We don't count multiplications by powers of two here. */
1555 contains_muldiv (rtx x)
1557 switch (GET_CODE (x))
1559 case MOD: case DIV: case UMOD: case UDIV:
1563 return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1564 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1567 return contains_muldiv (XEXP (x, 0))
1568 || contains_muldiv (XEXP (x, 1));
1571 return contains_muldiv (XEXP (x, 0));
1577 /* Determine whether INSN can be used in a combination. Return nonzero if
1578 not. This is used in try_combine to detect early some cases where we
1579 can't perform combinations. */
1582 cant_combine_insn_p (rtx insn)
1587 /* If this isn't really an insn, we can't do anything.
1588 This can occur when flow deletes an insn that it has merged into an
1589 auto-increment address. */
1590 if (! INSN_P (insn))
1593 /* Never combine loads and stores involving hard regs that are likely
1594 to be spilled. The register allocator can usually handle such
1595 reg-reg moves by tying. If we allow the combiner to make
1596 substitutions of likely-spilled regs, reload might die.
1597 As an exception, we allow combinations involving fixed regs; these are
1598 not available to the register allocator so there's no risk involved. */
1600 set = single_set (insn);
1603 src = SET_SRC (set);
1604 dest = SET_DEST (set);
1605 if (GET_CODE (src) == SUBREG)
1606 src = SUBREG_REG (src);
1607 if (GET_CODE (dest) == SUBREG)
1608 dest = SUBREG_REG (dest);
1609 if (REG_P (src) && REG_P (dest)
1610 && ((REGNO (src) < FIRST_PSEUDO_REGISTER
1611 && ! fixed_regs[REGNO (src)]
1612 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src))))
1613 || (REGNO (dest) < FIRST_PSEUDO_REGISTER
1614 && ! fixed_regs[REGNO (dest)]
1615 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest))))))
1621 struct likely_spilled_retval_info
1623 unsigned regno, nregs;
1627 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
1628 hard registers that are known to be written to / clobbered in full. */
1630 likely_spilled_retval_1 (rtx x, rtx set, void *data)
1632 struct likely_spilled_retval_info *info = data;
1633 unsigned regno, nregs;
1636 if (!REG_P (XEXP (set, 0)))
1639 if (regno >= info->regno + info->nregs)
1641 nregs = hard_regno_nregs[regno][GET_MODE (x)];
1642 if (regno + nregs <= info->regno)
1644 new_mask = (2U << (nregs - 1)) - 1;
1645 if (regno < info->regno)
1646 new_mask >>= info->regno - regno;
1648 new_mask <<= regno - info->regno;
1649 info->mask &= new_mask;
1652 /* Return nonzero iff part of the return value is live during INSN, and
1653 it is likely spilled. This can happen when more than one insn is needed
1654 to copy the return value, e.g. when we consider to combine into the
1655 second copy insn for a complex value. */
1658 likely_spilled_retval_p (rtx insn)
1660 rtx use = BB_END (this_basic_block);
1662 unsigned regno, nregs;
1663 /* We assume here that no machine mode needs more than
1664 32 hard registers when the value overlaps with a register
1665 for which FUNCTION_VALUE_REGNO_P is true. */
1667 struct likely_spilled_retval_info info;
1669 if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
1671 reg = XEXP (PATTERN (use), 0);
1672 if (!REG_P (reg) || !FUNCTION_VALUE_REGNO_P (REGNO (reg)))
1674 regno = REGNO (reg);
1675 nregs = hard_regno_nregs[regno][GET_MODE (reg)];
1678 mask = (2U << (nregs - 1)) - 1;
1680 /* Disregard parts of the return value that are set later. */
1684 for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
1685 note_stores (PATTERN (insn), likely_spilled_retval_1, &info);
1688 /* Check if any of the (probably) live return value registers is
1693 if ((mask & 1 << nregs)
1694 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (regno + nregs)))
1700 /* Adjust INSN after we made a change to its destination.
1702 Changing the destination can invalidate notes that say something about
1703 the results of the insn and a LOG_LINK pointing to the insn. */
1706 adjust_for_new_dest (rtx insn)
1710 /* For notes, be conservative and simply remove them. */
1711 loc = ®_NOTES (insn);
1714 enum reg_note kind = REG_NOTE_KIND (*loc);
1715 if (kind == REG_EQUAL || kind == REG_EQUIV)
1716 *loc = XEXP (*loc, 1);
1718 loc = &XEXP (*loc, 1);
1721 /* The new insn will have a destination that was previously the destination
1722 of an insn just above it. Call distribute_links to make a LOG_LINK from
1723 the next use of that destination. */
1724 distribute_links (gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX));
1727 /* Return TRUE if combine can reuse reg X in mode MODE.
1728 ADDED_SETS is nonzero if the original set is still required. */
1730 can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode)
1738 /* Allow hard registers if the new mode is legal, and occupies no more
1739 registers than the old mode. */
1740 if (regno < FIRST_PSEUDO_REGISTER)
1741 return (HARD_REGNO_MODE_OK (regno, mode)
1742 && (hard_regno_nregs[regno][GET_MODE (x)]
1743 >= hard_regno_nregs[regno][mode]));
1745 /* Or a pseudo that is only used once. */
1746 return (REG_N_SETS (regno) == 1 && !added_sets
1747 && !REG_USERVAR_P (x));
1751 /* Check whether X, the destination of a set, refers to part of
1752 the register specified by REG. */
1755 reg_subword_p (rtx x, rtx reg)
1757 /* Check that reg is an integer mode register. */
1758 if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
1761 if (GET_CODE (x) == STRICT_LOW_PART
1762 || GET_CODE (x) == ZERO_EXTRACT)
1765 return GET_CODE (x) == SUBREG
1766 && SUBREG_REG (x) == reg
1767 && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
1771 /* Try to combine the insns I1 and I2 into I3.
1772 Here I1 and I2 appear earlier than I3.
1773 I1 can be zero; then we combine just I2 into I3.
1775 If we are combining three insns and the resulting insn is not recognized,
1776 try splitting it into two insns. If that happens, I2 and I3 are retained
1777 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1780 Return 0 if the combination does not work. Then nothing is changed.
1781 If we did the combination, return the insn at which combine should
1784 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
1785 new direct jump instruction. */
1788 try_combine (rtx i3, rtx i2, rtx i1, int *new_direct_jump_p)
1790 /* New patterns for I3 and I2, respectively. */
1791 rtx newpat, newi2pat = 0;
1792 rtvec newpat_vec_with_clobbers = 0;
1793 int substed_i2 = 0, substed_i1 = 0;
1794 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1795 int added_sets_1, added_sets_2;
1796 /* Total number of SETs to put into I3. */
1798 /* Nonzero if I2's body now appears in I3. */
1800 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1801 int insn_code_number, i2_code_number = 0, other_code_number = 0;
1802 /* Contains I3 if the destination of I3 is used in its source, which means
1803 that the old life of I3 is being killed. If that usage is placed into
1804 I2 and not in I3, a REG_DEAD note must be made. */
1805 rtx i3dest_killed = 0;
1806 /* SET_DEST and SET_SRC of I2 and I1. */
1807 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1808 /* PATTERN (I2), or a copy of it in certain cases. */
1810 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1811 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1812 int i2dest_killed = 0, i1dest_killed = 0;
1813 int i1_feeds_i3 = 0;
1814 /* Notes that must be added to REG_NOTES in I3 and I2. */
1815 rtx new_i3_notes, new_i2_notes;
1816 /* Notes that we substituted I3 into I2 instead of the normal case. */
1817 int i3_subst_into_i2 = 0;
1818 /* Notes that I1, I2 or I3 is a MULT operation. */
1827 /* Exit early if one of the insns involved can't be used for
1829 if (cant_combine_insn_p (i3)
1830 || cant_combine_insn_p (i2)
1831 || (i1 && cant_combine_insn_p (i1))
1832 || likely_spilled_retval_p (i3)
1833 /* We also can't do anything if I3 has a
1834 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1837 /* ??? This gives worse code, and appears to be unnecessary, since no
1838 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1839 || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1845 undobuf.other_insn = 0;
1847 /* Reset the hard register usage information. */
1848 CLEAR_HARD_REG_SET (newpat_used_regs);
1850 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1851 code below, set I1 to be the earlier of the two insns. */
1852 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1853 temp = i1, i1 = i2, i2 = temp;
1855 added_links_insn = 0;
1857 /* First check for one important special-case that the code below will
1858 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1859 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1860 we may be able to replace that destination with the destination of I3.
1861 This occurs in the common code where we compute both a quotient and
1862 remainder into a structure, in which case we want to do the computation
1863 directly into the structure to avoid register-register copies.
1865 Note that this case handles both multiple sets in I2 and also
1866 cases where I2 has a number of CLOBBER or PARALLELs.
1868 We make very conservative checks below and only try to handle the
1869 most common cases of this. For example, we only handle the case
1870 where I2 and I3 are adjacent to avoid making difficult register
1873 if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
1874 && REG_P (SET_SRC (PATTERN (i3)))
1875 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1876 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1877 && GET_CODE (PATTERN (i2)) == PARALLEL
1878 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1879 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1880 below would need to check what is inside (and reg_overlap_mentioned_p
1881 doesn't support those codes anyway). Don't allow those destinations;
1882 the resulting insn isn't likely to be recognized anyway. */
1883 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1884 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1885 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1886 SET_DEST (PATTERN (i3)))
1887 && next_real_insn (i2) == i3)
1889 rtx p2 = PATTERN (i2);
1891 /* Make sure that the destination of I3,
1892 which we are going to substitute into one output of I2,
1893 is not used within another output of I2. We must avoid making this:
1894 (parallel [(set (mem (reg 69)) ...)
1895 (set (reg 69) ...)])
1896 which is not well-defined as to order of actions.
1897 (Besides, reload can't handle output reloads for this.)
1899 The problem can also happen if the dest of I3 is a memory ref,
1900 if another dest in I2 is an indirect memory ref. */
1901 for (i = 0; i < XVECLEN (p2, 0); i++)
1902 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1903 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1904 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1905 SET_DEST (XVECEXP (p2, 0, i))))
1908 if (i == XVECLEN (p2, 0))
1909 for (i = 0; i < XVECLEN (p2, 0); i++)
1910 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1911 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1912 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1917 subst_low_cuid = INSN_CUID (i2);
1919 added_sets_2 = added_sets_1 = 0;
1920 i2dest = SET_SRC (PATTERN (i3));
1921 i2dest_killed = dead_or_set_p (i2, i2dest);
1923 /* Replace the dest in I2 with our dest and make the resulting
1924 insn the new pattern for I3. Then skip to where we
1925 validate the pattern. Everything was set up above. */
1926 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1927 SET_DEST (PATTERN (i3)));
1930 i3_subst_into_i2 = 1;
1931 goto validate_replacement;
1935 /* If I2 is setting a pseudo to a constant and I3 is setting some
1936 sub-part of it to another constant, merge them by making a new
1939 && (temp = single_set (i2)) != 0
1940 && (GET_CODE (SET_SRC (temp)) == CONST_INT
1941 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
1942 && GET_CODE (PATTERN (i3)) == SET
1943 && (GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT
1944 || GET_CODE (SET_SRC (PATTERN (i3))) == CONST_DOUBLE)
1945 && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp)))
1947 rtx dest = SET_DEST (PATTERN (i3));
1951 if (GET_CODE (dest) == ZERO_EXTRACT)
1953 if (GET_CODE (XEXP (dest, 1)) == CONST_INT
1954 && GET_CODE (XEXP (dest, 2)) == CONST_INT)
1956 width = INTVAL (XEXP (dest, 1));
1957 offset = INTVAL (XEXP (dest, 2));
1958 dest = XEXP (dest, 0);
1959 if (BITS_BIG_ENDIAN)
1960 offset = GET_MODE_BITSIZE (GET_MODE (dest)) - width - offset;
1965 if (GET_CODE (dest) == STRICT_LOW_PART)
1966 dest = XEXP (dest, 0);
1967 width = GET_MODE_BITSIZE (GET_MODE (dest));
1973 /* If this is the low part, we're done. */
1974 if (subreg_lowpart_p (dest))
1976 /* Handle the case where inner is twice the size of outer. */
1977 else if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
1978 == 2 * GET_MODE_BITSIZE (GET_MODE (dest)))
1979 offset += GET_MODE_BITSIZE (GET_MODE (dest));
1980 /* Otherwise give up for now. */
1987 HOST_WIDE_INT mhi, ohi, ihi;
1988 HOST_WIDE_INT mlo, olo, ilo;
1989 rtx inner = SET_SRC (PATTERN (i3));
1990 rtx outer = SET_SRC (temp);
1992 if (GET_CODE (outer) == CONST_INT)
1994 olo = INTVAL (outer);
1995 ohi = olo < 0 ? -1 : 0;
1999 olo = CONST_DOUBLE_LOW (outer);
2000 ohi = CONST_DOUBLE_HIGH (outer);
2003 if (GET_CODE (inner) == CONST_INT)
2005 ilo = INTVAL (inner);
2006 ihi = ilo < 0 ? -1 : 0;
2010 ilo = CONST_DOUBLE_LOW (inner);
2011 ihi = CONST_DOUBLE_HIGH (inner);
2014 if (width < HOST_BITS_PER_WIDE_INT)
2016 mlo = ((unsigned HOST_WIDE_INT) 1 << width) - 1;
2019 else if (width < HOST_BITS_PER_WIDE_INT * 2)
2021 mhi = ((unsigned HOST_WIDE_INT) 1
2022 << (width - HOST_BITS_PER_WIDE_INT)) - 1;
2034 if (offset >= HOST_BITS_PER_WIDE_INT)
2036 mhi = mlo << (offset - HOST_BITS_PER_WIDE_INT);
2038 ihi = ilo << (offset - HOST_BITS_PER_WIDE_INT);
2041 else if (offset > 0)
2043 mhi = (mhi << offset) | ((unsigned HOST_WIDE_INT) mlo
2044 >> (HOST_BITS_PER_WIDE_INT - offset));
2045 mlo = mlo << offset;
2046 ihi = (ihi << offset) | ((unsigned HOST_WIDE_INT) ilo
2047 >> (HOST_BITS_PER_WIDE_INT - offset));
2048 ilo = ilo << offset;
2051 olo = (olo & ~mlo) | ilo;
2052 ohi = (ohi & ~mhi) | ihi;
2056 subst_low_cuid = INSN_CUID (i2);
2057 added_sets_2 = added_sets_1 = 0;
2058 i2dest = SET_DEST (temp);
2059 i2dest_killed = dead_or_set_p (i2, i2dest);
2061 SUBST (SET_SRC (temp),
2062 immed_double_const (olo, ohi, GET_MODE (SET_DEST (temp))));
2064 newpat = PATTERN (i2);
2065 goto validate_replacement;
2070 /* If we have no I1 and I2 looks like:
2071 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2073 make up a dummy I1 that is
2076 (set (reg:CC X) (compare:CC Y (const_int 0)))
2078 (We can ignore any trailing CLOBBERs.)
2080 This undoes a previous combination and allows us to match a branch-and-
2083 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
2084 && XVECLEN (PATTERN (i2), 0) >= 2
2085 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
2086 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2088 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2089 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2090 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
2091 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
2092 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2093 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
2095 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
2096 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
2101 /* We make I1 with the same INSN_UID as I2. This gives it
2102 the same INSN_CUID for value tracking. Our fake I1 will
2103 never appear in the insn stream so giving it the same INSN_UID
2104 as I2 will not cause a problem. */
2106 i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
2107 BLOCK_FOR_INSN (i2), INSN_LOCATOR (i2),
2108 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
2111 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2112 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2113 SET_DEST (PATTERN (i1)));
2118 /* Verify that I2 and I1 are valid for combining. */
2119 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
2120 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
2126 /* Record whether I2DEST is used in I2SRC and similarly for the other
2127 cases. Knowing this will help in register status updating below. */
2128 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2129 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2130 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2131 i2dest_killed = dead_or_set_p (i2, i2dest);
2132 i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2134 /* See if I1 directly feeds into I3. It does if I1DEST is not used
2136 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
2138 /* Ensure that I3's pattern can be the destination of combines. */
2139 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
2140 i1 && i2dest_in_i1src && i1_feeds_i3,
2147 /* See if any of the insns is a MULT operation. Unless one is, we will
2148 reject a combination that is, since it must be slower. Be conservative
2150 if (GET_CODE (i2src) == MULT
2151 || (i1 != 0 && GET_CODE (i1src) == MULT)
2152 || (GET_CODE (PATTERN (i3)) == SET
2153 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
2156 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2157 We used to do this EXCEPT in one case: I3 has a post-inc in an
2158 output operand. However, that exception can give rise to insns like
2160 which is a famous insn on the PDP-11 where the value of r3 used as the
2161 source was model-dependent. Avoid this sort of thing. */
2164 if (!(GET_CODE (PATTERN (i3)) == SET
2165 && REG_P (SET_SRC (PATTERN (i3)))
2166 && MEM_P (SET_DEST (PATTERN (i3)))
2167 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
2168 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
2169 /* It's not the exception. */
2172 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
2173 if (REG_NOTE_KIND (link) == REG_INC
2174 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
2176 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
2183 /* See if the SETs in I1 or I2 need to be kept around in the merged
2184 instruction: whenever the value set there is still needed past I3.
2185 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2187 For the SET in I1, we have two cases: If I1 and I2 independently
2188 feed into I3, the set in I1 needs to be kept around if I1DEST dies
2189 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2190 in I1 needs to be kept around unless I1DEST dies or is set in either
2191 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
2192 I1DEST. If so, we know I1 feeds into I2. */
2194 added_sets_2 = ! dead_or_set_p (i3, i2dest);
2197 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
2198 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
2200 /* If the set in I2 needs to be kept around, we must make a copy of
2201 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2202 PATTERN (I2), we are only substituting for the original I1DEST, not into
2203 an already-substituted copy. This also prevents making self-referential
2204 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2207 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
2208 ? gen_rtx_SET (VOIDmode, i2dest, i2src)
2212 i2pat = copy_rtx (i2pat);
2216 /* Substitute in the latest insn for the regs set by the earlier ones. */
2218 maxreg = max_reg_num ();
2223 /* Many machines that don't use CC0 have insns that can both perform an
2224 arithmetic operation and set the condition code. These operations will
2225 be represented as a PARALLEL with the first element of the vector
2226 being a COMPARE of an arithmetic operation with the constant zero.
2227 The second element of the vector will set some pseudo to the result
2228 of the same arithmetic operation. If we simplify the COMPARE, we won't
2229 match such a pattern and so will generate an extra insn. Here we test
2230 for this case, where both the comparison and the operation result are
2231 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2232 I2SRC. Later we will make the PARALLEL that contains I2. */
2234 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
2235 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
2236 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
2237 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
2239 #ifdef SELECT_CC_MODE
2241 enum machine_mode compare_mode;
2244 newpat = PATTERN (i3);
2245 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
2249 #ifdef SELECT_CC_MODE
2250 /* See if a COMPARE with the operand we substituted in should be done
2251 with the mode that is currently being used. If not, do the same
2252 processing we do in `subst' for a SET; namely, if the destination
2253 is used only once, try to replace it with a register of the proper
2254 mode and also replace the COMPARE. */
2255 if (undobuf.other_insn == 0
2256 && (cc_use = find_single_use (SET_DEST (newpat), i3,
2257 &undobuf.other_insn))
2258 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
2260 != GET_MODE (SET_DEST (newpat))))
2262 if (can_change_dest_mode(SET_DEST (newpat), added_sets_2,
2265 unsigned int regno = REGNO (SET_DEST (newpat));
2268 if (regno < FIRST_PSEUDO_REGISTER)
2269 new_dest = gen_rtx_REG (compare_mode, regno);
2272 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
2273 new_dest = regno_reg_rtx[regno];
2276 SUBST (SET_DEST (newpat), new_dest);
2277 SUBST (XEXP (*cc_use, 0), new_dest);
2278 SUBST (SET_SRC (newpat),
2279 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
2282 undobuf.other_insn = 0;
2289 /* It is possible that the source of I2 or I1 may be performing
2290 an unneeded operation, such as a ZERO_EXTEND of something
2291 that is known to have the high part zero. Handle that case
2292 by letting subst look at the innermost one of them.
2294 Another way to do this would be to have a function that tries
2295 to simplify a single insn instead of merging two or more
2296 insns. We don't do this because of the potential of infinite
2297 loops and because of the potential extra memory required.
2298 However, doing it the way we are is a bit of a kludge and
2299 doesn't catch all cases.
2301 But only do this if -fexpensive-optimizations since it slows
2302 things down and doesn't usually win.
2304 This is not done in the COMPARE case above because the
2305 unmodified I2PAT is used in the PARALLEL and so a pattern
2306 with a modified I2SRC would not match. */
2308 if (flag_expensive_optimizations)
2310 /* Pass pc_rtx so no substitutions are done, just
2314 subst_low_cuid = INSN_CUID (i1);
2315 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
2319 subst_low_cuid = INSN_CUID (i2);
2320 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
2324 n_occurrences = 0; /* `subst' counts here */
2326 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
2327 need to make a unique copy of I2SRC each time we substitute it
2328 to avoid self-referential rtl. */
2330 subst_low_cuid = INSN_CUID (i2);
2331 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
2332 ! i1_feeds_i3 && i1dest_in_i1src);
2335 /* Record whether i2's body now appears within i3's body. */
2336 i2_is_used = n_occurrences;
2339 /* If we already got a failure, don't try to do more. Otherwise,
2340 try to substitute in I1 if we have it. */
2342 if (i1 && GET_CODE (newpat) != CLOBBER)
2344 /* Before we can do this substitution, we must redo the test done
2345 above (see detailed comments there) that ensures that I1DEST
2346 isn't mentioned in any SETs in NEWPAT that are field assignments. */
2348 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
2356 subst_low_cuid = INSN_CUID (i1);
2357 newpat = subst (newpat, i1dest, i1src, 0, 0);
2361 /* Fail if an autoincrement side-effect has been duplicated. Be careful
2362 to count all the ways that I2SRC and I1SRC can be used. */
2363 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
2364 && i2_is_used + added_sets_2 > 1)
2365 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2366 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
2368 /* Fail if we tried to make a new register. */
2369 || max_reg_num () != maxreg
2370 /* Fail if we couldn't do something and have a CLOBBER. */
2371 || GET_CODE (newpat) == CLOBBER
2372 /* Fail if this new pattern is a MULT and we didn't have one before
2373 at the outer level. */
2374 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
2381 /* If the actions of the earlier insns must be kept
2382 in addition to substituting them into the latest one,
2383 we must make a new PARALLEL for the latest insn
2384 to hold additional the SETs. */
2386 if (added_sets_1 || added_sets_2)
2390 if (GET_CODE (newpat) == PARALLEL)
2392 rtvec old = XVEC (newpat, 0);
2393 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
2394 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2395 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
2396 sizeof (old->elem[0]) * old->num_elem);
2401 total_sets = 1 + added_sets_1 + added_sets_2;
2402 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2403 XVECEXP (newpat, 0, 0) = old;
2407 XVECEXP (newpat, 0, --total_sets)
2408 = (GET_CODE (PATTERN (i1)) == PARALLEL
2409 ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
2413 /* If there is no I1, use I2's body as is. We used to also not do
2414 the subst call below if I2 was substituted into I3,
2415 but that could lose a simplification. */
2417 XVECEXP (newpat, 0, --total_sets) = i2pat;
2419 /* See comment where i2pat is assigned. */
2420 XVECEXP (newpat, 0, --total_sets)
2421 = subst (i2pat, i1dest, i1src, 0, 0);
2425 /* We come here when we are replacing a destination in I2 with the
2426 destination of I3. */
2427 validate_replacement:
2429 /* Note which hard regs this insn has as inputs. */
2430 mark_used_regs_combine (newpat);
2432 /* If recog_for_combine fails, it strips existing clobbers. If we'll
2433 consider splitting this pattern, we might need these clobbers. */
2434 if (i1 && GET_CODE (newpat) == PARALLEL
2435 && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
2437 int len = XVECLEN (newpat, 0);
2439 newpat_vec_with_clobbers = rtvec_alloc (len);
2440 for (i = 0; i < len; i++)
2441 RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
2444 /* Is the result of combination a valid instruction? */
2445 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2447 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2448 the second SET's destination is a register that is unused and isn't
2449 marked as an instruction that might trap in an EH region. In that case,
2450 we just need the first SET. This can occur when simplifying a divmod
2451 insn. We *must* test for this case here because the code below that
2452 splits two independent SETs doesn't handle this case correctly when it
2453 updates the register status.
2455 It's pointless doing this if we originally had two sets, one from
2456 i3, and one from i2. Combining then splitting the parallel results
2457 in the original i2 again plus an invalid insn (which we delete).
2458 The net effect is only to move instructions around, which makes
2459 debug info less accurate.
2461 Also check the case where the first SET's destination is unused.
2462 That would not cause incorrect code, but does cause an unneeded
2465 if (insn_code_number < 0
2466 && !(added_sets_2 && i1 == 0)
2467 && GET_CODE (newpat) == PARALLEL
2468 && XVECLEN (newpat, 0) == 2
2469 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2470 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2471 && asm_noperands (newpat) < 0)
2473 rtx set0 = XVECEXP (newpat, 0, 0);
2474 rtx set1 = XVECEXP (newpat, 0, 1);
2477 if (((REG_P (SET_DEST (set1))
2478 && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
2479 || (GET_CODE (SET_DEST (set1)) == SUBREG
2480 && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
2481 && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2482 || INTVAL (XEXP (note, 0)) <= 0)
2483 && ! side_effects_p (SET_SRC (set1)))
2486 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2489 else if (((REG_P (SET_DEST (set0))
2490 && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
2491 || (GET_CODE (SET_DEST (set0)) == SUBREG
2492 && find_reg_note (i3, REG_UNUSED,
2493 SUBREG_REG (SET_DEST (set0)))))
2494 && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2495 || INTVAL (XEXP (note, 0)) <= 0)
2496 && ! side_effects_p (SET_SRC (set0)))
2499 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2501 if (insn_code_number >= 0)
2503 /* If we will be able to accept this, we have made a
2504 change to the destination of I3. This requires us to
2505 do a few adjustments. */
2507 PATTERN (i3) = newpat;
2508 adjust_for_new_dest (i3);
2513 /* If we were combining three insns and the result is a simple SET
2514 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2515 insns. There are two ways to do this. It can be split using a
2516 machine-specific method (like when you have an addition of a large
2517 constant) or by combine in the function find_split_point. */
2519 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2520 && asm_noperands (newpat) < 0)
2522 rtx m_split, *split;
2524 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2525 use I2DEST as a scratch register will help. In the latter case,
2526 convert I2DEST to the mode of the source of NEWPAT if we can. */
2528 m_split = split_insns (newpat, i3);
2530 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2531 inputs of NEWPAT. */
2533 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2534 possible to try that as a scratch reg. This would require adding
2535 more code to make it work though. */
2537 if (m_split == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
2539 enum machine_mode new_mode = GET_MODE (SET_DEST (newpat));
2541 /* First try to split using the original register as a
2542 scratch register. */
2543 m_split = split_insns (gen_rtx_PARALLEL
2545 gen_rtvec (2, newpat,
2546 gen_rtx_CLOBBER (VOIDmode,
2550 /* If that didn't work, try changing the mode of I2DEST if
2553 && new_mode != GET_MODE (i2dest)
2554 && new_mode != VOIDmode
2555 && can_change_dest_mode (i2dest, added_sets_2, new_mode))
2557 enum machine_mode old_mode = GET_MODE (i2dest);
2560 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
2561 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
2564 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode);
2565 ni2dest = regno_reg_rtx[REGNO (i2dest)];
2568 m_split = split_insns (gen_rtx_PARALLEL
2570 gen_rtvec (2, newpat,
2571 gen_rtx_CLOBBER (VOIDmode,
2576 && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2580 PUT_MODE (regno_reg_rtx[REGNO (i2dest)], old_mode);
2581 buf = undobuf.undos;
2582 undobuf.undos = buf->next;
2583 buf->next = undobuf.frees;
2584 undobuf.frees = buf;
2589 /* If recog_for_combine has discarded clobbers, try to use them
2590 again for the split. */
2591 if (m_split == 0 && newpat_vec_with_clobbers)
2593 = split_insns (gen_rtx_PARALLEL (VOIDmode,
2594 newpat_vec_with_clobbers), i3);
2596 if (m_split && NEXT_INSN (m_split) == NULL_RTX)
2598 m_split = PATTERN (m_split);
2599 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
2600 if (insn_code_number >= 0)
2603 else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
2604 && (next_real_insn (i2) == i3
2605 || ! use_crosses_set_p (PATTERN (m_split), INSN_CUID (i2))))
2608 rtx newi3pat = PATTERN (NEXT_INSN (m_split));
2609 newi2pat = PATTERN (m_split);
2611 i3set = single_set (NEXT_INSN (m_split));
2612 i2set = single_set (m_split);
2614 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2616 /* If I2 or I3 has multiple SETs, we won't know how to track
2617 register status, so don't use these insns. If I2's destination
2618 is used between I2 and I3, we also can't use these insns. */
2620 if (i2_code_number >= 0 && i2set && i3set
2621 && (next_real_insn (i2) == i3
2622 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
2623 insn_code_number = recog_for_combine (&newi3pat, i3,
2625 if (insn_code_number >= 0)
2628 /* It is possible that both insns now set the destination of I3.
2629 If so, we must show an extra use of it. */
2631 if (insn_code_number >= 0)
2633 rtx new_i3_dest = SET_DEST (i3set);
2634 rtx new_i2_dest = SET_DEST (i2set);
2636 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
2637 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
2638 || GET_CODE (new_i3_dest) == SUBREG)
2639 new_i3_dest = XEXP (new_i3_dest, 0);
2641 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
2642 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
2643 || GET_CODE (new_i2_dest) == SUBREG)
2644 new_i2_dest = XEXP (new_i2_dest, 0);
2646 if (REG_P (new_i3_dest)
2647 && REG_P (new_i2_dest)
2648 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
2649 REG_N_SETS (REGNO (new_i2_dest))++;
2653 /* If we can split it and use I2DEST, go ahead and see if that
2654 helps things be recognized. Verify that none of the registers
2655 are set between I2 and I3. */
2656 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
2660 /* We need I2DEST in the proper mode. If it is a hard register
2661 or the only use of a pseudo, we can change its mode.
2662 Make sure we don't change a hard register to have a mode that
2663 isn't valid for it, or change the number of registers. */
2664 && (GET_MODE (*split) == GET_MODE (i2dest)
2665 || GET_MODE (*split) == VOIDmode
2666 || can_change_dest_mode (i2dest, added_sets_2,
2668 && (next_real_insn (i2) == i3
2669 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
2670 /* We can't overwrite I2DEST if its value is still used by
2672 && ! reg_referenced_p (i2dest, newpat))
2674 rtx newdest = i2dest;
2675 enum rtx_code split_code = GET_CODE (*split);
2676 enum machine_mode split_mode = GET_MODE (*split);
2677 bool subst_done = false;
2678 newi2pat = NULL_RTX;
2680 /* Get NEWDEST as a register in the proper mode. We have already
2681 validated that we can do this. */
2682 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2684 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
2685 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
2688 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode);
2689 newdest = regno_reg_rtx[REGNO (i2dest)];
2693 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2694 an ASHIFT. This can occur if it was inside a PLUS and hence
2695 appeared to be a memory address. This is a kludge. */
2696 if (split_code == MULT
2697 && GET_CODE (XEXP (*split, 1)) == CONST_INT
2698 && INTVAL (XEXP (*split, 1)) > 0
2699 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
2701 SUBST (*split, gen_rtx_ASHIFT (split_mode,
2702 XEXP (*split, 0), GEN_INT (i)));
2703 /* Update split_code because we may not have a multiply
2705 split_code = GET_CODE (*split);
2708 #ifdef INSN_SCHEDULING
2709 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2710 be written as a ZERO_EXTEND. */
2711 if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
2713 #ifdef LOAD_EXTEND_OP
2714 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
2715 what it really is. */
2716 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
2718 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
2719 SUBREG_REG (*split)));
2722 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
2723 SUBREG_REG (*split)));
2727 /* Attempt to split binary operators using arithmetic identities. */
2728 if (BINARY_P (SET_SRC (newpat))
2729 && split_mode == GET_MODE (SET_SRC (newpat))
2730 && ! side_effects_p (SET_SRC (newpat)))
2732 rtx setsrc = SET_SRC (newpat);
2733 enum machine_mode mode = GET_MODE (setsrc);
2734 enum rtx_code code = GET_CODE (setsrc);
2735 rtx src_op0 = XEXP (setsrc, 0);
2736 rtx src_op1 = XEXP (setsrc, 1);
2738 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
2739 if (rtx_equal_p (src_op0, src_op1))
2741 newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0);
2742 SUBST (XEXP (setsrc, 0), newdest);
2743 SUBST (XEXP (setsrc, 1), newdest);
2746 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
2747 else if ((code == PLUS || code == MULT)
2748 && GET_CODE (src_op0) == code
2749 && GET_CODE (XEXP (src_op0, 0)) == code
2750 && (INTEGRAL_MODE_P (mode)
2751 || (FLOAT_MODE_P (mode)
2752 && flag_unsafe_math_optimizations)))
2754 rtx p = XEXP (XEXP (src_op0, 0), 0);
2755 rtx q = XEXP (XEXP (src_op0, 0), 1);
2756 rtx r = XEXP (src_op0, 1);
2759 /* Split both "((X op Y) op X) op Y" and
2760 "((X op Y) op Y) op X" as "T op T" where T is
2762 if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
2763 || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
2765 newi2pat = gen_rtx_SET (VOIDmode, newdest,
2767 SUBST (XEXP (setsrc, 0), newdest);
2768 SUBST (XEXP (setsrc, 1), newdest);
2771 /* Split "((X op X) op Y) op Y)" as "T op T" where
2773 else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
2775 rtx tmp = simplify_gen_binary (code, mode, p, r);
2776 newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp);
2777 SUBST (XEXP (setsrc, 0), newdest);
2778 SUBST (XEXP (setsrc, 1), newdest);
2786 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
2787 SUBST (*split, newdest);
2790 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2792 /* recog_for_combine might have added CLOBBERs to newi2pat.
2793 Make sure NEWPAT does not depend on the clobbered regs. */
2794 if (GET_CODE (newi2pat) == PARALLEL)
2795 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
2796 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
2798 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
2799 if (reg_overlap_mentioned_p (reg, newpat))
2806 /* If the split point was a MULT and we didn't have one before,
2807 don't use one now. */
2808 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
2809 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2813 /* Check for a case where we loaded from memory in a narrow mode and
2814 then sign extended it, but we need both registers. In that case,
2815 we have a PARALLEL with both loads from the same memory location.
2816 We can split this into a load from memory followed by a register-register
2817 copy. This saves at least one insn, more if register allocation can
2820 We cannot do this if the destination of the first assignment is a
2821 condition code register or cc0. We eliminate this case by making sure
2822 the SET_DEST and SET_SRC have the same mode.
2824 We cannot do this if the destination of the second assignment is
2825 a register that we have already assumed is zero-extended. Similarly
2826 for a SUBREG of such a register. */
2828 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2829 && GET_CODE (newpat) == PARALLEL
2830 && XVECLEN (newpat, 0) == 2
2831 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2832 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2833 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
2834 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
2835 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2836 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2837 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2838 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2840 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2841 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2842 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2844 && reg_stat[REGNO (temp)].nonzero_bits != 0
2845 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2846 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2847 && (reg_stat[REGNO (temp)].nonzero_bits
2848 != GET_MODE_MASK (word_mode))))
2849 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2850 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2852 && reg_stat[REGNO (temp)].nonzero_bits != 0
2853 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2854 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2855 && (reg_stat[REGNO (temp)].nonzero_bits
2856 != GET_MODE_MASK (word_mode)))))
2857 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2858 SET_SRC (XVECEXP (newpat, 0, 1)))
2859 && ! find_reg_note (i3, REG_UNUSED,
2860 SET_DEST (XVECEXP (newpat, 0, 0))))
2864 newi2pat = XVECEXP (newpat, 0, 0);
2865 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2866 newpat = XVECEXP (newpat, 0, 1);
2867 SUBST (SET_SRC (newpat),
2868 gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
2869 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2871 if (i2_code_number >= 0)
2872 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2874 if (insn_code_number >= 0)
2878 /* Similarly, check for a case where we have a PARALLEL of two independent
2879 SETs but we started with three insns. In this case, we can do the sets
2880 as two separate insns. This case occurs when some SET allows two
2881 other insns to combine, but the destination of that SET is still live. */
2883 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2884 && GET_CODE (newpat) == PARALLEL
2885 && XVECLEN (newpat, 0) == 2
2886 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2887 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2888 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2889 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2890 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2891 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2892 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2894 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2895 XVECEXP (newpat, 0, 0))
2896 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2897 XVECEXP (newpat, 0, 1))
2898 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
2899 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1))))
2901 /* We cannot split the parallel into two sets if both sets
2903 && ! (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0))
2904 && reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 1)))
2908 /* Normally, it doesn't matter which of the two is done first,
2909 but it does if one references cc0. In that case, it has to
2912 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2914 newi2pat = XVECEXP (newpat, 0, 0);
2915 newpat = XVECEXP (newpat, 0, 1);
2920 newi2pat = XVECEXP (newpat, 0, 1);
2921 newpat = XVECEXP (newpat, 0, 0);
2924 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2926 if (i2_code_number >= 0)
2927 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2930 /* If it still isn't recognized, fail and change things back the way they
2932 if ((insn_code_number < 0
2933 /* Is the result a reasonable ASM_OPERANDS? */
2934 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2940 /* If we had to change another insn, make sure it is valid also. */
2941 if (undobuf.other_insn)
2943 rtx other_pat = PATTERN (undobuf.other_insn);
2944 rtx new_other_notes;
2947 CLEAR_HARD_REG_SET (newpat_used_regs);
2949 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2952 if (other_code_number < 0 && ! check_asm_operands (other_pat))
2958 PATTERN (undobuf.other_insn) = other_pat;
2960 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2961 are still valid. Then add any non-duplicate notes added by
2962 recog_for_combine. */
2963 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2965 next = XEXP (note, 1);
2967 if (REG_NOTE_KIND (note) == REG_UNUSED
2968 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2970 if (REG_P (XEXP (note, 0)))
2971 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2973 remove_note (undobuf.other_insn, note);
2977 for (note = new_other_notes; note; note = XEXP (note, 1))
2978 if (REG_P (XEXP (note, 0)))
2979 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2981 distribute_notes (new_other_notes, undobuf.other_insn,
2982 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
2985 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
2986 they are adjacent to each other or not. */
2988 rtx p = prev_nonnote_insn (i3);
2989 if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
2990 && sets_cc0_p (newi2pat))
2998 /* Only allow this combination if insn_rtx_costs reports that the
2999 replacement instructions are cheaper than the originals. */
3000 if (!combine_validate_cost (i1, i2, i3, newpat, newi2pat))
3006 /* We now know that we can do this combination. Merge the insns and
3007 update the status of registers and LOG_LINKS. */
3015 /* I3 now uses what used to be its destination and which is now
3016 I2's destination. This requires us to do a few adjustments. */
3017 PATTERN (i3) = newpat;
3018 adjust_for_new_dest (i3);
3020 /* We need a LOG_LINK from I3 to I2. But we used to have one,
3023 However, some later insn might be using I2's dest and have
3024 a LOG_LINK pointing at I3. We must remove this link.
3025 The simplest way to remove the link is to point it at I1,
3026 which we know will be a NOTE. */
3028 /* newi2pat is usually a SET here; however, recog_for_combine might
3029 have added some clobbers. */
3030 if (GET_CODE (newi2pat) == PARALLEL)
3031 ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
3033 ni2dest = SET_DEST (newi2pat);
3035 for (insn = NEXT_INSN (i3);
3036 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3037 || insn != BB_HEAD (this_basic_block->next_bb));
3038 insn = NEXT_INSN (insn))
3040 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
3042 for (link = LOG_LINKS (insn); link;
3043 link = XEXP (link, 1))
3044 if (XEXP (link, 0) == i3)
3045 XEXP (link, 0) = i1;
3053 rtx i3notes, i2notes, i1notes = 0;
3054 rtx i3links, i2links, i1links = 0;
3057 /* Compute which registers we expect to eliminate. newi2pat may be setting
3058 either i3dest or i2dest, so we must check it. Also, i1dest may be the
3059 same as i3dest, in which case newi2pat may be setting i1dest. */
3060 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
3061 || i2dest_in_i2src || i2dest_in_i1src
3064 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
3065 || (newi2pat && reg_set_p (i1dest, newi2pat))
3069 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
3071 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
3072 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
3074 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
3076 /* Ensure that we do not have something that should not be shared but
3077 occurs multiple times in the new insns. Check this by first
3078 resetting all the `used' flags and then copying anything is shared. */
3080 reset_used_flags (i3notes);
3081 reset_used_flags (i2notes);
3082 reset_used_flags (i1notes);
3083 reset_used_flags (newpat);
3084 reset_used_flags (newi2pat);
3085 if (undobuf.other_insn)
3086 reset_used_flags (PATTERN (undobuf.other_insn));
3088 i3notes = copy_rtx_if_shared (i3notes);
3089 i2notes = copy_rtx_if_shared (i2notes);
3090 i1notes = copy_rtx_if_shared (i1notes);
3091 newpat = copy_rtx_if_shared (newpat);
3092 newi2pat = copy_rtx_if_shared (newi2pat);
3093 if (undobuf.other_insn)
3094 reset_used_flags (PATTERN (undobuf.other_insn));
3096 INSN_CODE (i3) = insn_code_number;
3097 PATTERN (i3) = newpat;
3099 if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
3101 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
3103 reset_used_flags (call_usage);
3104 call_usage = copy_rtx (call_usage);
3107 replace_rtx (call_usage, i2dest, i2src);
3110 replace_rtx (call_usage, i1dest, i1src);
3112 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
3115 if (undobuf.other_insn)
3116 INSN_CODE (undobuf.other_insn) = other_code_number;
3118 /* We had one special case above where I2 had more than one set and
3119 we replaced a destination of one of those sets with the destination
3120 of I3. In that case, we have to update LOG_LINKS of insns later
3121 in this basic block. Note that this (expensive) case is rare.
3123 Also, in this case, we must pretend that all REG_NOTEs for I2
3124 actually came from I3, so that REG_UNUSED notes from I2 will be
3125 properly handled. */
3127 if (i3_subst_into_i2)
3129 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
3130 if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET
3131 || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER)
3132 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
3133 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
3134 && ! find_reg_note (i2, REG_UNUSED,
3135 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
3136 for (temp = NEXT_INSN (i2);
3137 temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3138 || BB_HEAD (this_basic_block) != temp);
3139 temp = NEXT_INSN (temp))
3140 if (temp != i3 && INSN_P (temp))
3141 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
3142 if (XEXP (link, 0) == i2)
3143 XEXP (link, 0) = i3;
3148 while (XEXP (link, 1))
3149 link = XEXP (link, 1);
3150 XEXP (link, 1) = i2notes;
3164 INSN_CODE (i2) = i2_code_number;
3165 PATTERN (i2) = newi2pat;
3168 SET_INSN_DELETED (i2);
3174 SET_INSN_DELETED (i1);
3177 /* Get death notes for everything that is now used in either I3 or
3178 I2 and used to die in a previous insn. If we built two new
3179 patterns, move from I1 to I2 then I2 to I3 so that we get the
3180 proper movement on registers that I2 modifies. */
3184 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
3185 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
3188 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
3191 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
3193 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
3196 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
3199 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
3202 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3205 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
3206 know these are REG_UNUSED and want them to go to the desired insn,
3207 so we always pass it as i3. We have not counted the notes in
3208 reg_n_deaths yet, so we need to do so now. */
3210 if (newi2pat && new_i2_notes)
3212 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
3213 if (REG_P (XEXP (temp, 0)))
3214 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
3216 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3221 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
3222 if (REG_P (XEXP (temp, 0)))
3223 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
3225 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
3228 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
3229 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
3230 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
3231 in that case, it might delete I2. Similarly for I2 and I1.
3232 Show an additional death due to the REG_DEAD note we make here. If
3233 we discard it in distribute_notes, we will decrement it again. */
3237 if (REG_P (i3dest_killed))
3238 REG_N_DEATHS (REGNO (i3dest_killed))++;
3240 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
3241 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
3243 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
3245 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
3247 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3251 if (i2dest_in_i2src)
3254 REG_N_DEATHS (REGNO (i2dest))++;
3256 if (newi2pat && reg_set_p (i2dest, newi2pat))
3257 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
3258 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3260 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
3261 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3262 NULL_RTX, NULL_RTX);
3265 if (i1dest_in_i1src)
3268 REG_N_DEATHS (REGNO (i1dest))++;
3270 if (newi2pat && reg_set_p (i1dest, newi2pat))
3271 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
3272 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3274 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
3275 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3276 NULL_RTX, NULL_RTX);
3279 distribute_links (i3links);
3280 distribute_links (i2links);
3281 distribute_links (i1links);
3286 rtx i2_insn = 0, i2_val = 0, set;
3288 /* The insn that used to set this register doesn't exist, and
3289 this life of the register may not exist either. See if one of
3290 I3's links points to an insn that sets I2DEST. If it does,
3291 that is now the last known value for I2DEST. If we don't update
3292 this and I2 set the register to a value that depended on its old
3293 contents, we will get confused. If this insn is used, thing
3294 will be set correctly in combine_instructions. */
3296 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3297 if ((set = single_set (XEXP (link, 0))) != 0
3298 && rtx_equal_p (i2dest, SET_DEST (set)))
3299 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
3301 record_value_for_reg (i2dest, i2_insn, i2_val);
3303 /* If the reg formerly set in I2 died only once and that was in I3,
3304 zero its use count so it won't make `reload' do any work. */
3306 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
3307 && ! i2dest_in_i2src)
3309 regno = REGNO (i2dest);
3310 REG_N_SETS (regno)--;
3314 if (i1 && REG_P (i1dest))
3317 rtx i1_insn = 0, i1_val = 0, set;
3319 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3320 if ((set = single_set (XEXP (link, 0))) != 0
3321 && rtx_equal_p (i1dest, SET_DEST (set)))
3322 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
3324 record_value_for_reg (i1dest, i1_insn, i1_val);
3326 regno = REGNO (i1dest);
3327 if (! added_sets_1 && ! i1dest_in_i1src)
3328 REG_N_SETS (regno)--;
3331 /* Update reg_stat[].nonzero_bits et al for any changes that may have
3332 been made to this insn. The order of
3333 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
3334 can affect nonzero_bits of newpat */
3336 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
3337 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
3339 /* Set new_direct_jump_p if a new return or simple jump instruction
3342 If I3 is now an unconditional jump, ensure that it has a
3343 BARRIER following it since it may have initially been a
3344 conditional jump. It may also be the last nonnote insn. */
3346 if (returnjump_p (i3) || any_uncondjump_p (i3))
3348 *new_direct_jump_p = 1;
3349 mark_jump_label (PATTERN (i3), i3, 0);
3351 if ((temp = next_nonnote_insn (i3)) == NULL_RTX
3352 || !BARRIER_P (temp))
3353 emit_barrier_after (i3);
3356 if (undobuf.other_insn != NULL_RTX
3357 && (returnjump_p (undobuf.other_insn)
3358 || any_uncondjump_p (undobuf.other_insn)))
3360 *new_direct_jump_p = 1;
3362 if ((temp = next_nonnote_insn (undobuf.other_insn)) == NULL_RTX
3363 || !BARRIER_P (temp))
3364 emit_barrier_after (undobuf.other_insn);
3367 /* An NOOP jump does not need barrier, but it does need cleaning up
3369 if (GET_CODE (newpat) == SET
3370 && SET_SRC (newpat) == pc_rtx
3371 && SET_DEST (newpat) == pc_rtx)
3372 *new_direct_jump_p = 1;
3375 combine_successes++;
3378 if (added_links_insn
3379 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
3380 && INSN_CUID (added_links_insn) < INSN_CUID (i3))
3381 return added_links_insn;
3383 return newi2pat ? i2 : i3;
3386 /* Undo all the modifications recorded in undobuf. */
3391 struct undo *undo, *next;
3393 for (undo = undobuf.undos; undo; undo = next)
3399 *undo->where.r = undo->old_contents.r;
3402 *undo->where.i = undo->old_contents.i;
3405 PUT_MODE (*undo->where.r, undo->old_contents.m);
3411 undo->next = undobuf.frees;
3412 undobuf.frees = undo;
3418 /* We've committed to accepting the changes we made. Move all
3419 of the undos to the free list. */
3424 struct undo *undo, *next;
3426 for (undo = undobuf.undos; undo; undo = next)
3429 undo->next = undobuf.frees;
3430 undobuf.frees = undo;
3435 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
3436 where we have an arithmetic expression and return that point. LOC will
3439 try_combine will call this function to see if an insn can be split into
3443 find_split_point (rtx *loc, rtx insn)
3446 enum rtx_code code = GET_CODE (x);
3448 unsigned HOST_WIDE_INT len = 0;
3449 HOST_WIDE_INT pos = 0;
3451 rtx inner = NULL_RTX;
3453 /* First special-case some codes. */
3457 #ifdef INSN_SCHEDULING
3458 /* If we are making a paradoxical SUBREG invalid, it becomes a split
3460 if (MEM_P (SUBREG_REG (x)))
3463 return find_split_point (&SUBREG_REG (x), insn);
3467 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
3468 using LO_SUM and HIGH. */
3469 if (GET_CODE (XEXP (x, 0)) == CONST
3470 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
3473 gen_rtx_LO_SUM (Pmode,
3474 gen_rtx_HIGH (Pmode, XEXP (x, 0)),
3476 return &XEXP (XEXP (x, 0), 0);
3480 /* If we have a PLUS whose second operand is a constant and the
3481 address is not valid, perhaps will can split it up using
3482 the machine-specific way to split large constants. We use
3483 the first pseudo-reg (one of the virtual regs) as a placeholder;
3484 it will not remain in the result. */
3485 if (GET_CODE (XEXP (x, 0)) == PLUS
3486 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3487 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
3489 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
3490 rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
3493 /* This should have produced two insns, each of which sets our
3494 placeholder. If the source of the second is a valid address,
3495 we can make put both sources together and make a split point
3499 && NEXT_INSN (seq) != NULL_RTX
3500 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
3501 && NONJUMP_INSN_P (seq)
3502 && GET_CODE (PATTERN (seq)) == SET
3503 && SET_DEST (PATTERN (seq)) == reg
3504 && ! reg_mentioned_p (reg,
3505 SET_SRC (PATTERN (seq)))
3506 && NONJUMP_INSN_P (NEXT_INSN (seq))
3507 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
3508 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
3509 && memory_address_p (GET_MODE (x),
3510 SET_SRC (PATTERN (NEXT_INSN (seq)))))
3512 rtx src1 = SET_SRC (PATTERN (seq));
3513 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
3515 /* Replace the placeholder in SRC2 with SRC1. If we can
3516 find where in SRC2 it was placed, that can become our
3517 split point and we can replace this address with SRC2.
3518 Just try two obvious places. */
3520 src2 = replace_rtx (src2, reg, src1);
3522 if (XEXP (src2, 0) == src1)
3523 split = &XEXP (src2, 0);
3524 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
3525 && XEXP (XEXP (src2, 0), 0) == src1)
3526 split = &XEXP (XEXP (src2, 0), 0);
3530 SUBST (XEXP (x, 0), src2);
3535 /* If that didn't work, perhaps the first operand is complex and
3536 needs to be computed separately, so make a split point there.
3537 This will occur on machines that just support REG + CONST
3538 and have a constant moved through some previous computation. */
3540 else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
3541 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
3542 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
3543 return &XEXP (XEXP (x, 0), 0);
3549 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
3550 ZERO_EXTRACT, the most likely reason why this doesn't match is that
3551 we need to put the operand into a register. So split at that
3554 if (SET_DEST (x) == cc0_rtx
3555 && GET_CODE (SET_SRC (x)) != COMPARE
3556 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
3557 && !OBJECT_P (SET_SRC (x))
3558 && ! (GET_CODE (SET_SRC (x)) == SUBREG
3559 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
3560 return &SET_SRC (x);
3563 /* See if we can split SET_SRC as it stands. */
3564 split = find_split_point (&SET_SRC (x), insn);
3565 if (split && split != &SET_SRC (x))
3568 /* See if we can split SET_DEST as it stands. */
3569 split = find_split_point (&SET_DEST (x), insn);
3570 if (split && split != &SET_DEST (x))
3573 /* See if this is a bitfield assignment with everything constant. If
3574 so, this is an IOR of an AND, so split it into that. */
3575 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
3576 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
3577 <= HOST_BITS_PER_WIDE_INT)
3578 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
3579 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
3580 && GET_CODE (SET_SRC (x)) == CONST_INT
3581 && ((INTVAL (XEXP (SET_DEST (x), 1))
3582 + INTVAL (XEXP (SET_DEST (x), 2)))
3583 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
3584 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
3586 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
3587 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
3588 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
3589 rtx dest = XEXP (SET_DEST (x), 0);
3590 enum machine_mode mode = GET_MODE (dest);
3591 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
3594 if (BITS_BIG_ENDIAN)
3595 pos = GET_MODE_BITSIZE (mode) - len - pos;
3597 or_mask = gen_int_mode (src << pos, mode);
3600 simplify_gen_binary (IOR, mode, dest, or_mask));
3603 rtx negmask = gen_int_mode (~(mask << pos), mode);
3605 simplify_gen_binary (IOR, mode,
3606 simplify_gen_binary (AND, mode,
3611 SUBST (SET_DEST (x), dest);
3613 split = find_split_point (&SET_SRC (x), insn);
3614 if (split && split != &SET_SRC (x))
3618 /* Otherwise, see if this is an operation that we can split into two.
3619 If so, try to split that. */
3620 code = GET_CODE (SET_SRC (x));
3625 /* If we are AND'ing with a large constant that is only a single
3626 bit and the result is only being used in a context where we
3627 need to know if it is zero or nonzero, replace it with a bit
3628 extraction. This will avoid the large constant, which might
3629 have taken more than one insn to make. If the constant were
3630 not a valid argument to the AND but took only one insn to make,
3631 this is no worse, but if it took more than one insn, it will
3634 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3635 && REG_P (XEXP (SET_SRC (x), 0))
3636 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
3637 && REG_P (SET_DEST (x))
3638 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
3639 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
3640 && XEXP (*split, 0) == SET_DEST (x)
3641 && XEXP (*split, 1) == const0_rtx)
3643 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
3644 XEXP (SET_SRC (x), 0),
3645 pos, NULL_RTX, 1, 1, 0, 0);
3646 if (extraction != 0)
3648 SUBST (SET_SRC (x), extraction);
3649 return find_split_point (loc, insn);
3655 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3656 is known to be on, this can be converted into a NEG of a shift. */
3657 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
3658 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
3659 && 1 <= (pos = exact_log2
3660 (nonzero_bits (XEXP (SET_SRC (x), 0),
3661 GET_MODE (XEXP (SET_SRC (x), 0))))))
3663 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
3667 gen_rtx_LSHIFTRT (mode,
3668 XEXP (SET_SRC (x), 0),
3671 split = find_split_point (&SET_SRC (x), insn);
3672 if (split && split != &SET_SRC (x))
3678 inner = XEXP (SET_SRC (x), 0);
3680 /* We can't optimize if either mode is a partial integer
3681 mode as we don't know how many bits are significant
3683 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
3684 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
3688 len = GET_MODE_BITSIZE (GET_MODE (inner));
3694 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3695 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
3697 inner = XEXP (SET_SRC (x), 0);
3698 len = INTVAL (XEXP (SET_SRC (x), 1));
3699 pos = INTVAL (XEXP (SET_SRC (x), 2));
3701 if (BITS_BIG_ENDIAN)
3702 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
3703 unsignedp = (code == ZERO_EXTRACT);
3711 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
3713 enum machine_mode mode = GET_MODE (SET_SRC (x));
3715 /* For unsigned, we have a choice of a shift followed by an
3716 AND or two shifts. Use two shifts for field sizes where the
3717 constant might be too large. We assume here that we can
3718 always at least get 8-bit constants in an AND insn, which is
3719 true for every current RISC. */
3721 if (unsignedp && len <= 8)
3726 (mode, gen_lowpart (mode, inner),
3728 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
3730 split = find_split_point (&SET_SRC (x), insn);
3731 if (split && split != &SET_SRC (x))
3738 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
3739 gen_rtx_ASHIFT (mode,
3740 gen_lowpart (mode, inner),
3741 GEN_INT (GET_MODE_BITSIZE (mode)
3743 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
3745 split = find_split_point (&SET_SRC (x), insn);
3746 if (split && split != &SET_SRC (x))
3751 /* See if this is a simple operation with a constant as the second
3752 operand. It might be that this constant is out of range and hence
3753 could be used as a split point. */
3754 if (BINARY_P (SET_SRC (x))
3755 && CONSTANT_P (XEXP (SET_SRC (x), 1))
3756 && (OBJECT_P (XEXP (SET_SRC (x), 0))
3757 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
3758 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
3759 return &XEXP (SET_SRC (x), 1);
3761 /* Finally, see if this is a simple operation with its first operand
3762 not in a register. The operation might require this operand in a
3763 register, so return it as a split point. We can always do this
3764 because if the first operand were another operation, we would have
3765 already found it as a split point. */
3766 if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
3767 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
3768 return &XEXP (SET_SRC (x), 0);
3774 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3775 it is better to write this as (not (ior A B)) so we can split it.
3776 Similarly for IOR. */
3777 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
3780 gen_rtx_NOT (GET_MODE (x),
3781 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
3783 XEXP (XEXP (x, 0), 0),
3784 XEXP (XEXP (x, 1), 0))));
3785 return find_split_point (loc, insn);
3788 /* Many RISC machines have a large set of logical insns. If the
3789 second operand is a NOT, put it first so we will try to split the
3790 other operand first. */
3791 if (GET_CODE (XEXP (x, 1)) == NOT)
3793 rtx tem = XEXP (x, 0);
3794 SUBST (XEXP (x, 0), XEXP (x, 1));
3795 SUBST (XEXP (x, 1), tem);
3803 /* Otherwise, select our actions depending on our rtx class. */
3804 switch (GET_RTX_CLASS (code))
3806 case RTX_BITFIELD_OPS: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3808 split = find_split_point (&XEXP (x, 2), insn);
3811 /* ... fall through ... */
3813 case RTX_COMM_ARITH:
3815 case RTX_COMM_COMPARE:
3816 split = find_split_point (&XEXP (x, 1), insn);
3819 /* ... fall through ... */
3821 /* Some machines have (and (shift ...) ...) insns. If X is not
3822 an AND, but XEXP (X, 0) is, use it as our split point. */
3823 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
3824 return &XEXP (x, 0);
3826 split = find_split_point (&XEXP (x, 0), insn);
3832 /* Otherwise, we don't have a split point. */
3837 /* Throughout X, replace FROM with TO, and return the result.
3838 The result is TO if X is FROM;
3839 otherwise the result is X, but its contents may have been modified.
3840 If they were modified, a record was made in undobuf so that
3841 undo_all will (among other things) return X to its original state.
3843 If the number of changes necessary is too much to record to undo,
3844 the excess changes are not made, so the result is invalid.
3845 The changes already made can still be undone.
3846 undobuf.num_undo is incremented for such changes, so by testing that
3847 the caller can tell whether the result is valid.
3849 `n_occurrences' is incremented each time FROM is replaced.
3851 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
3853 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
3854 by copying if `n_occurrences' is nonzero. */
3857 subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy)
3859 enum rtx_code code = GET_CODE (x);
3860 enum machine_mode op0_mode = VOIDmode;
3865 /* Two expressions are equal if they are identical copies of a shared
3866 RTX or if they are both registers with the same register number
3869 #define COMBINE_RTX_EQUAL_P(X,Y) \
3871 || (REG_P (X) && REG_P (Y) \
3872 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3874 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3877 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3880 /* If X and FROM are the same register but different modes, they will
3881 not have been seen as equal above. However, flow.c will make a
3882 LOG_LINKS entry for that case. If we do nothing, we will try to
3883 rerecognize our original insn and, when it succeeds, we will
3884 delete the feeding insn, which is incorrect.
3886 So force this insn not to match in this (rare) case. */
3887 if (! in_dest && code == REG && REG_P (from)
3888 && REGNO (x) == REGNO (from))
3889 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
3891 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3892 of which may contain things that can be combined. */
3893 if (code != MEM && code != LO_SUM && OBJECT_P (x))
3896 /* It is possible to have a subexpression appear twice in the insn.
3897 Suppose that FROM is a register that appears within TO.
3898 Then, after that subexpression has been scanned once by `subst',
3899 the second time it is scanned, TO may be found. If we were
3900 to scan TO here, we would find FROM within it and create a
3901 self-referent rtl structure which is completely wrong. */
3902 if (COMBINE_RTX_EQUAL_P (x, to))
3905 /* Parallel asm_operands need special attention because all of the
3906 inputs are shared across the arms. Furthermore, unsharing the
3907 rtl results in recognition failures. Failure to handle this case
3908 specially can result in circular rtl.
3910 Solve this by doing a normal pass across the first entry of the
3911 parallel, and only processing the SET_DESTs of the subsequent
3914 if (code == PARALLEL
3915 && GET_CODE (XVECEXP (x, 0, 0)) == SET
3916 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
3918 new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3920 /* If this substitution failed, this whole thing fails. */
3921 if (GET_CODE (new) == CLOBBER
3922 && XEXP (new, 0) == const0_rtx)
3925 SUBST (XVECEXP (x, 0, 0), new);
3927 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
3929 rtx dest = SET_DEST (XVECEXP (x, 0, i));
3932 && GET_CODE (dest) != CC0
3933 && GET_CODE (dest) != PC)
3935 new = subst (dest, from, to, 0, unique_copy);
3937 /* If this substitution failed, this whole thing fails. */
3938 if (GET_CODE (new) == CLOBBER
3939 && XEXP (new, 0) == const0_rtx)
3942 SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
3948 len = GET_RTX_LENGTH (code);
3949 fmt = GET_RTX_FORMAT (code);
3951 /* We don't need to process a SET_DEST that is a register, CC0,
3952 or PC, so set up to skip this common case. All other cases
3953 where we want to suppress replacing something inside a
3954 SET_SRC are handled via the IN_DEST operand. */
3956 && (REG_P (SET_DEST (x))
3957 || GET_CODE (SET_DEST (x)) == CC0
3958 || GET_CODE (SET_DEST (x)) == PC))
3961 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3964 op0_mode = GET_MODE (XEXP (x, 0));
3966 for (i = 0; i < len; i++)
3971 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3973 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3975 new = (unique_copy && n_occurrences
3976 ? copy_rtx (to) : to);
3981 new = subst (XVECEXP (x, i, j), from, to, 0,
3984 /* If this substitution failed, this whole thing
3986 if (GET_CODE (new) == CLOBBER
3987 && XEXP (new, 0) == const0_rtx)
3991 SUBST (XVECEXP (x, i, j), new);
3994 else if (fmt[i] == 'e')
3996 /* If this is a register being set, ignore it. */
4000 && (((code == SUBREG || code == ZERO_EXTRACT)
4002 || code == STRICT_LOW_PART))
4005 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
4007 /* In general, don't install a subreg involving two
4008 modes not tieable. It can worsen register
4009 allocation, and can even make invalid reload
4010 insns, since the reg inside may need to be copied
4011 from in the outside mode, and that may be invalid
4012 if it is an fp reg copied in integer mode.
4014 We allow two exceptions to this: It is valid if
4015 it is inside another SUBREG and the mode of that
4016 SUBREG and the mode of the inside of TO is
4017 tieable and it is valid if X is a SET that copies
4020 if (GET_CODE (to) == SUBREG
4021 && ! MODES_TIEABLE_P (GET_MODE (to),
4022 GET_MODE (SUBREG_REG (to)))
4023 && ! (code == SUBREG
4024 && MODES_TIEABLE_P (GET_MODE (x),
4025 GET_MODE (SUBREG_REG (to))))
4027 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
4030 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4032 #ifdef CANNOT_CHANGE_MODE_CLASS
4035 && REGNO (to) < FIRST_PSEUDO_REGISTER
4036 && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
4039 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4042 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
4046 /* If we are in a SET_DEST, suppress most cases unless we
4047 have gone inside a MEM, in which case we want to
4048 simplify the address. We assume here that things that
4049 are actually part of the destination have their inner
4050 parts in the first expression. This is true for SUBREG,
4051 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
4052 things aside from REG and MEM that should appear in a
4054 new = subst (XEXP (x, i), from, to,
4056 && (code == SUBREG || code == STRICT_LOW_PART
4057 || code == ZERO_EXTRACT))
4059 && i == 0), unique_copy);
4061 /* If we found that we will have to reject this combination,
4062 indicate that by returning the CLOBBER ourselves, rather than
4063 an expression containing it. This will speed things up as
4064 well as prevent accidents where two CLOBBERs are considered
4065 to be equal, thus producing an incorrect simplification. */
4067 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
4070 if (GET_CODE (x) == SUBREG
4071 && (GET_CODE (new) == CONST_INT
4072 || GET_CODE (new) == CONST_DOUBLE))
4074 enum machine_mode mode = GET_MODE (x);
4076 x = simplify_subreg (GET_MODE (x), new,
4077 GET_MODE (SUBREG_REG (x)),
4080 x = gen_rtx_CLOBBER (mode, const0_rtx);
4082 else if (GET_CODE (new) == CONST_INT
4083 && GET_CODE (x) == ZERO_EXTEND)
4085 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
4086 new, GET_MODE (XEXP (x, 0)));
4090 SUBST (XEXP (x, i), new);
4095 /* Try to simplify X. If the simplification changed the code, it is likely
4096 that further simplification will help, so loop, but limit the number
4097 of repetitions that will be performed. */
4099 for (i = 0; i < 4; i++)
4101 /* If X is sufficiently simple, don't bother trying to do anything
4103 if (code != CONST_INT && code != REG && code != CLOBBER)
4104 x = combine_simplify_rtx (x, op0_mode, in_dest);
4106 if (GET_CODE (x) == code)
4109 code = GET_CODE (x);
4111 /* We no longer know the original mode of operand 0 since we
4112 have changed the form of X) */
4113 op0_mode = VOIDmode;
4119 /* Simplify X, a piece of RTL. We just operate on the expression at the
4120 outer level; call `subst' to simplify recursively. Return the new
4123 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
4124 if we are inside a SET_DEST. */
4127 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest)
4129 enum rtx_code code = GET_CODE (x);
4130 enum machine_mode mode = GET_MODE (x);
4134 /* If this is a commutative operation, put a constant last and a complex
4135 expression first. We don't need to do this for comparisons here. */
4136 if (COMMUTATIVE_ARITH_P (x)
4137 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
4140 SUBST (XEXP (x, 0), XEXP (x, 1));
4141 SUBST (XEXP (x, 1), temp);
4144 /* If this is a simple operation applied to an IF_THEN_ELSE, try
4145 applying it to the arms of the IF_THEN_ELSE. This often simplifies
4146 things. Check for cases where both arms are testing the same
4149 Don't do anything if all operands are very simple. */
4152 && ((!OBJECT_P (XEXP (x, 0))
4153 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4154 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
4155 || (!OBJECT_P (XEXP (x, 1))
4156 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
4157 && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
4159 && (!OBJECT_P (XEXP (x, 0))
4160 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4161 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
4163 rtx cond, true_rtx, false_rtx;
4165 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
4167 /* If everything is a comparison, what we have is highly unlikely
4168 to be simpler, so don't use it. */
4169 && ! (COMPARISON_P (x)
4170 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
4172 rtx cop1 = const0_rtx;
4173 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
4175 if (cond_code == NE && COMPARISON_P (cond))
4178 /* Simplify the alternative arms; this may collapse the true and
4179 false arms to store-flag values. Be careful to use copy_rtx
4180 here since true_rtx or false_rtx might share RTL with x as a
4181 result of the if_then_else_cond call above. */
4182 true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0);
4183 false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0);
4185 /* If true_rtx and false_rtx are not general_operands, an if_then_else
4186 is unlikely to be simpler. */
4187 if (general_operand (true_rtx, VOIDmode)
4188 && general_operand (false_rtx, VOIDmode))
4190 enum rtx_code reversed;
4192 /* Restarting if we generate a store-flag expression will cause
4193 us to loop. Just drop through in this case. */
4195 /* If the result values are STORE_FLAG_VALUE and zero, we can
4196 just make the comparison operation. */
4197 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
4198 x = simplify_gen_relational (cond_code, mode, VOIDmode,
4200 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
4201 && ((reversed = reversed_comparison_code_parts
4202 (cond_code, cond, cop1, NULL))
4204 x = simplify_gen_relational (reversed, mode, VOIDmode,
4207 /* Likewise, we can make the negate of a comparison operation
4208 if the result values are - STORE_FLAG_VALUE and zero. */
4209 else if (GET_CODE (true_rtx) == CONST_INT
4210 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
4211 && false_rtx == const0_rtx)
4212 x = simplify_gen_unary (NEG, mode,
4213 simplify_gen_relational (cond_code,
4217 else if (GET_CODE (false_rtx) == CONST_INT
4218 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
4219 && true_rtx == const0_rtx
4220 && ((reversed = reversed_comparison_code_parts
4221 (cond_code, cond, cop1, NULL))
4223 x = simplify_gen_unary (NEG, mode,
4224 simplify_gen_relational (reversed,
4229 return gen_rtx_IF_THEN_ELSE (mode,
4230 simplify_gen_relational (cond_code,
4235 true_rtx, false_rtx);
4237 code = GET_CODE (x);
4238 op0_mode = VOIDmode;
4243 /* Try to fold this expression in case we have constants that weren't
4246 switch (GET_RTX_CLASS (code))
4249 if (op0_mode == VOIDmode)
4250 op0_mode = GET_MODE (XEXP (x, 0));
4251 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
4254 case RTX_COMM_COMPARE:
4256 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
4257 if (cmp_mode == VOIDmode)
4259 cmp_mode = GET_MODE (XEXP (x, 1));
4260 if (cmp_mode == VOIDmode)
4261 cmp_mode = op0_mode;
4263 temp = simplify_relational_operation (code, mode, cmp_mode,
4264 XEXP (x, 0), XEXP (x, 1));
4267 case RTX_COMM_ARITH:
4269 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
4271 case RTX_BITFIELD_OPS:
4273 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
4274 XEXP (x, 1), XEXP (x, 2));
4283 code = GET_CODE (temp);
4284 op0_mode = VOIDmode;
4285 mode = GET_MODE (temp);
4288 /* First see if we can apply the inverse distributive law. */
4289 if (code == PLUS || code == MINUS
4290 || code == AND || code == IOR || code == XOR)
4292 x = apply_distributive_law (x);
4293 code = GET_CODE (x);
4294 op0_mode = VOIDmode;
4297 /* If CODE is an associative operation not otherwise handled, see if we
4298 can associate some operands. This can win if they are constants or
4299 if they are logically related (i.e. (a & b) & a). */
4300 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
4301 || code == AND || code == IOR || code == XOR
4302 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
4303 && ((INTEGRAL_MODE_P (mode) && code != DIV)
4304 || (flag_unsafe_math_optimizations && FLOAT_MODE_P (mode))))
4306 if (GET_CODE (XEXP (x, 0)) == code)
4308 rtx other = XEXP (XEXP (x, 0), 0);
4309 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
4310 rtx inner_op1 = XEXP (x, 1);
4313 /* Make sure we pass the constant operand if any as the second
4314 one if this is a commutative operation. */
4315 if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
4317 rtx tem = inner_op0;
4318 inner_op0 = inner_op1;
4321 inner = simplify_binary_operation (code == MINUS ? PLUS
4322 : code == DIV ? MULT
4324 mode, inner_op0, inner_op1);
4326 /* For commutative operations, try the other pair if that one
4328 if (inner == 0 && COMMUTATIVE_ARITH_P (x))
4330 other = XEXP (XEXP (x, 0), 1);
4331 inner = simplify_binary_operation (code, mode,
4332 XEXP (XEXP (x, 0), 0),
4337 return simplify_gen_binary (code, mode, other, inner);
4341 /* A little bit of algebraic simplification here. */
4345 /* Ensure that our address has any ASHIFTs converted to MULT in case
4346 address-recognizing predicates are called later. */
4347 temp = make_compound_operation (XEXP (x, 0), MEM);
4348 SUBST (XEXP (x, 0), temp);
4352 if (op0_mode == VOIDmode)
4353 op0_mode = GET_MODE (SUBREG_REG (x));
4355 /* See if this can be moved to simplify_subreg. */
4356 if (CONSTANT_P (SUBREG_REG (x))
4357 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
4358 /* Don't call gen_lowpart if the inner mode
4359 is VOIDmode and we cannot simplify it, as SUBREG without
4360 inner mode is invalid. */
4361 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
4362 || gen_lowpart_common (mode, SUBREG_REG (x))))
4363 return gen_lowpart (mode, SUBREG_REG (x));
4365 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
4369 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
4375 /* Don't change the mode of the MEM if that would change the meaning
4377 if (MEM_P (SUBREG_REG (x))
4378 && (MEM_VOLATILE_P (SUBREG_REG (x))
4379 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
4380 return gen_rtx_CLOBBER (mode, const0_rtx);
4382 /* Note that we cannot do any narrowing for non-constants since
4383 we might have been counting on using the fact that some bits were
4384 zero. We now do this in the SET. */
4389 temp = expand_compound_operation (XEXP (x, 0));
4391 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4392 replaced by (lshiftrt X C). This will convert
4393 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
4395 if (GET_CODE (temp) == ASHIFTRT
4396 && GET_CODE (XEXP (temp, 1)) == CONST_INT
4397 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
4398 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
4399 INTVAL (XEXP (temp, 1)));
4401 /* If X has only a single bit that might be nonzero, say, bit I, convert
4402 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4403 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4404 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4405 or a SUBREG of one since we'd be making the expression more
4406 complex if it was just a register. */
4409 && ! (GET_CODE (temp) == SUBREG
4410 && REG_P (SUBREG_REG (temp)))
4411 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
4413 rtx temp1 = simplify_shift_const
4414 (NULL_RTX, ASHIFTRT, mode,
4415 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
4416 GET_MODE_BITSIZE (mode) - 1 - i),
4417 GET_MODE_BITSIZE (mode) - 1 - i);
4419 /* If all we did was surround TEMP with the two shifts, we
4420 haven't improved anything, so don't use it. Otherwise,
4421 we are better off with TEMP1. */
4422 if (GET_CODE (temp1) != ASHIFTRT
4423 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
4424 || XEXP (XEXP (temp1, 0), 0) != temp)
4430 /* We can't handle truncation to a partial integer mode here
4431 because we don't know the real bitsize of the partial
4433 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
4436 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4437 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4438 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4440 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
4441 GET_MODE_MASK (mode), 0));
4443 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
4444 whose value is a comparison can be replaced with a subreg if
4445 STORE_FLAG_VALUE permits. */
4446 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4447 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
4448 && (temp = get_last_value (XEXP (x, 0)))
4449 && COMPARISON_P (temp))
4450 return gen_lowpart (mode, XEXP (x, 0));
4455 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4456 using cc0, in which case we want to leave it as a COMPARE
4457 so we can distinguish it from a register-register-copy. */
4458 if (XEXP (x, 1) == const0_rtx)
4461 /* x - 0 is the same as x unless x's mode has signed zeros and
4462 allows rounding towards -infinity. Under those conditions,
4464 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x, 0)))
4465 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x, 0))))
4466 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4472 /* (const (const X)) can become (const X). Do it this way rather than
4473 returning the inner CONST since CONST can be shared with a
4475 if (GET_CODE (XEXP (x, 0)) == CONST)
4476 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4481 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4482 can add in an offset. find_split_point will split this address up
4483 again if it doesn't match. */
4484 if (GET_CODE (XEXP (x, 0)) == HIGH
4485 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4491 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4492 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4493 bit-field and can be replaced by either a sign_extend or a
4494 sign_extract. The `and' may be a zero_extend and the two
4495 <c>, -<c> constants may be reversed. */
4496 if (GET_CODE (XEXP (x, 0)) == XOR
4497 && GET_CODE (XEXP (x, 1)) == CONST_INT
4498 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4499 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
4500 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4501 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4502 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4503 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4504 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4505 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4506 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4507 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4508 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4509 == (unsigned int) i + 1))))
4510 return simplify_shift_const
4511 (NULL_RTX, ASHIFTRT, mode,
4512 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4513 XEXP (XEXP (XEXP (x, 0), 0), 0),
4514 GET_MODE_BITSIZE (mode) - (i + 1)),
4515 GET_MODE_BITSIZE (mode) - (i + 1));
4517 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4518 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4519 the bitsize of the mode - 1. This allows simplification of
4520 "a = (b & 8) == 0;" */
4521 if (XEXP (x, 1) == constm1_rtx
4522 && !REG_P (XEXP (x, 0))
4523 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4524 && REG_P (SUBREG_REG (XEXP (x, 0))))
4525 && nonzero_bits (XEXP (x, 0), mode) == 1)
4526 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4527 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4528 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
4529 GET_MODE_BITSIZE (mode) - 1),
4530 GET_MODE_BITSIZE (mode) - 1);
4532 /* If we are adding two things that have no bits in common, convert
4533 the addition into an IOR. This will often be further simplified,
4534 for example in cases like ((a & 1) + (a & 2)), which can
4537 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4538 && (nonzero_bits (XEXP (x, 0), mode)
4539 & nonzero_bits (XEXP (x, 1), mode)) == 0)
4541 /* Try to simplify the expression further. */
4542 rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4543 temp = combine_simplify_rtx (tor, mode, in_dest);
4545 /* If we could, great. If not, do not go ahead with the IOR
4546 replacement, since PLUS appears in many special purpose
4547 address arithmetic instructions. */
4548 if (GET_CODE (temp) != CLOBBER && temp != tor)
4554 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4555 (and <foo> (const_int pow2-1)) */
4556 if (GET_CODE (XEXP (x, 1)) == AND
4557 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4558 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4559 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4560 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4561 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4565 /* If we have (mult (plus A B) C), apply the distributive law and then
4566 the inverse distributive law to see if things simplify. This
4567 occurs mostly in addresses, often when unrolling loops. */
4569 if (GET_CODE (XEXP (x, 0)) == PLUS)
4571 rtx result = distribute_and_simplify_rtx (x, 0);
4576 /* Try simplify a*(b/c) as (a*b)/c. */
4577 if (FLOAT_MODE_P (mode) && flag_unsafe_math_optimizations
4578 && GET_CODE (XEXP (x, 0)) == DIV)
4580 rtx tem = simplify_binary_operation (MULT, mode,
4581 XEXP (XEXP (x, 0), 0),
4584 return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
4589 /* If this is a divide by a power of two, treat it as a shift if
4590 its first operand is a shift. */
4591 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4592 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4593 && (GET_CODE (XEXP (x, 0)) == ASHIFT
4594 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4595 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4596 || GET_CODE (XEXP (x, 0)) == ROTATE
4597 || GET_CODE (XEXP (x, 0)) == ROTATERT))
4598 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
4602 case GT: case GTU: case GE: case GEU:
4603 case LT: case LTU: case LE: case LEU:
4604 case UNEQ: case LTGT:
4605 case UNGT: case UNGE:
4606 case UNLT: case UNLE:
4607 case UNORDERED: case ORDERED:
4608 /* If the first operand is a condition code, we can't do anything
4610 if (GET_CODE (XEXP (x, 0)) == COMPARE
4611 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4612 && ! CC0_P (XEXP (x, 0))))
4614 rtx op0 = XEXP (x, 0);
4615 rtx op1 = XEXP (x, 1);
4616 enum rtx_code new_code;
4618 if (GET_CODE (op0) == COMPARE)
4619 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4621 /* Simplify our comparison, if possible. */
4622 new_code = simplify_comparison (code, &op0, &op1);
4624 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4625 if only the low-order bit is possibly nonzero in X (such as when
4626 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4627 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4628 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4631 Remove any ZERO_EXTRACT we made when thinking this was a
4632 comparison. It may now be simpler to use, e.g., an AND. If a
4633 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4634 the call to make_compound_operation in the SET case. */
4636 if (STORE_FLAG_VALUE == 1
4637 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4638 && op1 == const0_rtx
4639 && mode == GET_MODE (op0)
4640 && nonzero_bits (op0, mode) == 1)
4641 return gen_lowpart (mode,
4642 expand_compound_operation (op0));
4644 else if (STORE_FLAG_VALUE == 1
4645 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4646 && op1 == const0_rtx
4647 && mode == GET_MODE (op0)
4648 && (num_sign_bit_copies (op0, mode)
4649 == GET_MODE_BITSIZE (mode)))
4651 op0 = expand_compound_operation (op0);
4652 return simplify_gen_unary (NEG, mode,
4653 gen_lowpart (mode, op0),
4657 else if (STORE_FLAG_VALUE == 1
4658 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4659 && op1 == const0_rtx
4660 && mode == GET_MODE (op0)
4661 && nonzero_bits (op0, mode) == 1)
4663 op0 = expand_compound_operation (op0);
4664 return simplify_gen_binary (XOR, mode,
4665 gen_lowpart (mode, op0),
4669 else if (STORE_FLAG_VALUE == 1
4670 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4671 && op1 == const0_rtx
4672 && mode == GET_MODE (op0)
4673 && (num_sign_bit_copies (op0, mode)
4674 == GET_MODE_BITSIZE (mode)))
4676 op0 = expand_compound_operation (op0);
4677 return plus_constant (gen_lowpart (mode, op0), 1);
4680 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4682 if (STORE_FLAG_VALUE == -1
4683 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4684 && op1 == const0_rtx
4685 && (num_sign_bit_copies (op0, mode)
4686 == GET_MODE_BITSIZE (mode)))
4687 return gen_lowpart (mode,
4688 expand_compound_operation (op0));
4690 else if (STORE_FLAG_VALUE == -1
4691 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4692 && op1 == const0_rtx
4693 && mode == GET_MODE (op0)
4694 && nonzero_bits (op0, mode) == 1)
4696 op0 = expand_compound_operation (op0);
4697 return simplify_gen_unary (NEG, mode,
4698 gen_lowpart (mode, op0),
4702 else if (STORE_FLAG_VALUE == -1
4703 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4704 && op1 == const0_rtx
4705 && mode == GET_MODE (op0)
4706 && (num_sign_bit_copies (op0, mode)
4707 == GET_MODE_BITSIZE (mode)))
4709 op0 = expand_compound_operation (op0);
4710 return simplify_gen_unary (NOT, mode,
4711 gen_lowpart (mode, op0),
4715 /* If X is 0/1, (eq X 0) is X-1. */
4716 else if (STORE_FLAG_VALUE == -1
4717 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4718 && op1 == const0_rtx
4719 && mode == GET_MODE (op0)
4720 && nonzero_bits (op0, mode) == 1)
4722 op0 = expand_compound_operation (op0);
4723 return plus_constant (gen_lowpart (mode, op0), -1);
4726 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4727 one bit that might be nonzero, we can convert (ne x 0) to
4728 (ashift x c) where C puts the bit in the sign bit. Remove any
4729 AND with STORE_FLAG_VALUE when we are done, since we are only
4730 going to test the sign bit. */
4731 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4732 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4733 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4734 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
4735 && op1 == const0_rtx
4736 && mode == GET_MODE (op0)
4737 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4739 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4740 expand_compound_operation (op0),
4741 GET_MODE_BITSIZE (mode) - 1 - i);
4742 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4748 /* If the code changed, return a whole new comparison. */
4749 if (new_code != code)
4750 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
4752 /* Otherwise, keep this operation, but maybe change its operands.
4753 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4754 SUBST (XEXP (x, 0), op0);
4755 SUBST (XEXP (x, 1), op1);
4760 return simplify_if_then_else (x);
4766 /* If we are processing SET_DEST, we are done. */
4770 return expand_compound_operation (x);
4773 return simplify_set (x);
4777 return simplify_logical (x);
4784 /* If this is a shift by a constant amount, simplify it. */
4785 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4786 return simplify_shift_const (x, code, mode, XEXP (x, 0),
4787 INTVAL (XEXP (x, 1)));
4789 else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
4791 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
4793 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4805 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4808 simplify_if_then_else (rtx x)
4810 enum machine_mode mode = GET_MODE (x);
4811 rtx cond = XEXP (x, 0);
4812 rtx true_rtx = XEXP (x, 1);
4813 rtx false_rtx = XEXP (x, 2);
4814 enum rtx_code true_code = GET_CODE (cond);
4815 int comparison_p = COMPARISON_P (cond);
4818 enum rtx_code false_code;
4821 /* Simplify storing of the truth value. */
4822 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
4823 return simplify_gen_relational (true_code, mode, VOIDmode,
4824 XEXP (cond, 0), XEXP (cond, 1));
4826 /* Also when the truth value has to be reversed. */
4828 && true_rtx == const0_rtx && false_rtx == const_true_rtx
4829 && (reversed = reversed_comparison (cond, mode)))
4832 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4833 in it is being compared against certain values. Get the true and false
4834 comparisons and see if that says anything about the value of each arm. */
4837 && ((false_code = reversed_comparison_code (cond, NULL))
4839 && REG_P (XEXP (cond, 0)))
4842 rtx from = XEXP (cond, 0);
4843 rtx true_val = XEXP (cond, 1);
4844 rtx false_val = true_val;
4847 /* If FALSE_CODE is EQ, swap the codes and arms. */
4849 if (false_code == EQ)
4851 swapped = 1, true_code = EQ, false_code = NE;
4852 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4855 /* If we are comparing against zero and the expression being tested has
4856 only a single bit that might be nonzero, that is its value when it is
4857 not equal to zero. Similarly if it is known to be -1 or 0. */
4859 if (true_code == EQ && true_val == const0_rtx
4860 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4861 false_code = EQ, false_val = GEN_INT (nzb);
4862 else if (true_code == EQ && true_val == const0_rtx
4863 && (num_sign_bit_copies (from, GET_MODE (from))
4864 == GET_MODE_BITSIZE (GET_MODE (from))))
4865 false_code = EQ, false_val = constm1_rtx;
4867 /* Now simplify an arm if we know the value of the register in the
4868 branch and it is used in the arm. Be careful due to the potential
4869 of locally-shared RTL. */
4871 if (reg_mentioned_p (from, true_rtx))
4872 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
4874 pc_rtx, pc_rtx, 0, 0);
4875 if (reg_mentioned_p (from, false_rtx))
4876 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
4878 pc_rtx, pc_rtx, 0, 0);
4880 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
4881 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
4883 true_rtx = XEXP (x, 1);
4884 false_rtx = XEXP (x, 2);
4885 true_code = GET_CODE (cond);
4888 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4889 reversed, do so to avoid needing two sets of patterns for
4890 subtract-and-branch insns. Similarly if we have a constant in the true
4891 arm, the false arm is the same as the first operand of the comparison, or
4892 the false arm is more complicated than the true arm. */
4895 && reversed_comparison_code (cond, NULL) != UNKNOWN
4896 && (true_rtx == pc_rtx
4897 || (CONSTANT_P (true_rtx)
4898 && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx)
4899 || true_rtx == const0_rtx
4900 || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
4901 || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
4902 && !OBJECT_P (false_rtx))
4903 || reg_mentioned_p (true_rtx, false_rtx)
4904 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
4906 true_code = reversed_comparison_code (cond, NULL);
4907 SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
4908 SUBST (XEXP (x, 1), false_rtx);
4909 SUBST (XEXP (x, 2), true_rtx);
4911 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4914 /* It is possible that the conditional has been simplified out. */
4915 true_code = GET_CODE (cond);
4916 comparison_p = COMPARISON_P (cond);
4919 /* If the two arms are identical, we don't need the comparison. */
4921 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
4924 /* Convert a == b ? b : a to "a". */
4925 if (true_code == EQ && ! side_effects_p (cond)
4926 && !HONOR_NANS (mode)
4927 && rtx_equal_p (XEXP (cond, 0), false_rtx)
4928 && rtx_equal_p (XEXP (cond, 1), true_rtx))
4930 else if (true_code == NE && ! side_effects_p (cond)
4931 && !HONOR_NANS (mode)
4932 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4933 && rtx_equal_p (XEXP (cond, 1), false_rtx))
4936 /* Look for cases where we have (abs x) or (neg (abs X)). */
4938 if (GET_MODE_CLASS (mode) == MODE_INT
4939 && GET_CODE (false_rtx) == NEG
4940 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
4942 && rtx_equal_p (true_rtx, XEXP (cond, 0))
4943 && ! side_effects_p (true_rtx))
4948 return simplify_gen_unary (ABS, mode, true_rtx, mode);
4952 simplify_gen_unary (NEG, mode,
4953 simplify_gen_unary (ABS, mode, true_rtx, mode),
4959 /* Look for MIN or MAX. */
4961 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4963 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4964 && rtx_equal_p (XEXP (cond, 1), false_rtx)
4965 && ! side_effects_p (cond))
4970 return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
4973 return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
4976 return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
4979 return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
4984 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4985 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4986 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4987 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4988 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4989 neither 1 or -1, but it isn't worth checking for. */
4991 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4993 && GET_MODE_CLASS (mode) == MODE_INT
4994 && ! side_effects_p (x))
4996 rtx t = make_compound_operation (true_rtx, SET);
4997 rtx f = make_compound_operation (false_rtx, SET);
4998 rtx cond_op0 = XEXP (cond, 0);
4999 rtx cond_op1 = XEXP (cond, 1);
5000 enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
5001 enum machine_mode m = mode;
5002 rtx z = 0, c1 = NULL_RTX;
5004 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
5005 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
5006 || GET_CODE (t) == ASHIFT
5007 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
5008 && rtx_equal_p (XEXP (t, 0), f))
5009 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
5011 /* If an identity-zero op is commutative, check whether there
5012 would be a match if we swapped the operands. */
5013 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
5014 || GET_CODE (t) == XOR)
5015 && rtx_equal_p (XEXP (t, 1), f))
5016 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
5017 else if (GET_CODE (t) == SIGN_EXTEND
5018 && (GET_CODE (XEXP (t, 0)) == PLUS
5019 || GET_CODE (XEXP (t, 0)) == MINUS
5020 || GET_CODE (XEXP (t, 0)) == IOR
5021 || GET_CODE (XEXP (t, 0)) == XOR
5022 || GET_CODE (XEXP (t, 0)) == ASHIFT
5023 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5024 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5025 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5026 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5027 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5028 && (num_sign_bit_copies (f, GET_MODE (f))
5030 (GET_MODE_BITSIZE (mode)
5031 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
5033 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5034 extend_op = SIGN_EXTEND;
5035 m = GET_MODE (XEXP (t, 0));
5037 else if (GET_CODE (t) == SIGN_EXTEND
5038 && (GET_CODE (XEXP (t, 0)) == PLUS
5039 || GET_CODE (XEXP (t, 0)) == IOR
5040 || GET_CODE (XEXP (t, 0)) == XOR)
5041 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5042 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5043 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5044 && (num_sign_bit_copies (f, GET_MODE (f))
5046 (GET_MODE_BITSIZE (mode)
5047 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
5049 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5050 extend_op = SIGN_EXTEND;
5051 m = GET_MODE (XEXP (t, 0));
5053 else if (GET_CODE (t) == ZERO_EXTEND
5054 && (GET_CODE (XEXP (t, 0)) == PLUS
5055 || GET_CODE (XEXP (t, 0)) == MINUS
5056 || GET_CODE (XEXP (t, 0)) == IOR
5057 || GET_CODE (XEXP (t, 0)) == XOR
5058 || GET_CODE (XEXP (t, 0)) == ASHIFT
5059 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5060 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5061 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5062 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5063 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5064 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5065 && ((nonzero_bits (f, GET_MODE (f))
5066 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
5069 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5070 extend_op = ZERO_EXTEND;
5071 m = GET_MODE (XEXP (t, 0));
5073 else if (GET_CODE (t) == ZERO_EXTEND
5074 && (GET_CODE (XEXP (t, 0)) == PLUS
5075 || GET_CODE (XEXP (t, 0)) == IOR
5076 || GET_CODE (XEXP (t, 0)) == XOR)
5077 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5078 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5079 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5080 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5081 && ((nonzero_bits (f, GET_MODE (f))
5082 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
5085 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5086 extend_op = ZERO_EXTEND;
5087 m = GET_MODE (XEXP (t, 0));
5092 temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
5093 cond_op0, cond_op1),
5094 pc_rtx, pc_rtx, 0, 0);
5095 temp = simplify_gen_binary (MULT, m, temp,
5096 simplify_gen_binary (MULT, m, c1,
5098 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
5099 temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
5101 if (extend_op != UNKNOWN)
5102 temp = simplify_gen_unary (extend_op, mode, temp, m);
5108 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5109 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5110 negation of a single bit, we can convert this operation to a shift. We
5111 can actually do this more generally, but it doesn't seem worth it. */
5113 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5114 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5115 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
5116 && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
5117 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
5118 == GET_MODE_BITSIZE (mode))
5119 && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
5121 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5122 gen_lowpart (mode, XEXP (cond, 0)), i);
5124 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
5125 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5126 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5127 && GET_MODE (XEXP (cond, 0)) == mode
5128 && (INTVAL (true_rtx) & GET_MODE_MASK (mode))
5129 == nonzero_bits (XEXP (cond, 0), mode)
5130 && (i = exact_log2 (INTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
5131 return XEXP (cond, 0);
5136 /* Simplify X, a SET expression. Return the new expression. */
5139 simplify_set (rtx x)
5141 rtx src = SET_SRC (x);
5142 rtx dest = SET_DEST (x);
5143 enum machine_mode mode
5144 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
5148 /* (set (pc) (return)) gets written as (return). */
5149 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
5152 /* Now that we know for sure which bits of SRC we are using, see if we can
5153 simplify the expression for the object knowing that we only need the
5156 if (GET_MODE_CLASS (mode) == MODE_INT
5157 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5159 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, 0);
5160 SUBST (SET_SRC (x), src);
5163 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5164 the comparison result and try to simplify it unless we already have used
5165 undobuf.other_insn. */
5166 if ((GET_MODE_CLASS (mode) == MODE_CC
5167 || GET_CODE (src) == COMPARE
5169 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
5170 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
5171 && COMPARISON_P (*cc_use)
5172 && rtx_equal_p (XEXP (*cc_use, 0), dest))
5174 enum rtx_code old_code = GET_CODE (*cc_use);
5175 enum rtx_code new_code;
5177 int other_changed = 0;
5178 enum machine_mode compare_mode = GET_MODE (dest);
5180 if (GET_CODE (src) == COMPARE)
5181 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
5183 op0 = src, op1 = CONST0_RTX (GET_MODE (src));
5185 tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
5188 new_code = old_code;
5189 else if (!CONSTANT_P (tmp))
5191 new_code = GET_CODE (tmp);
5192 op0 = XEXP (tmp, 0);
5193 op1 = XEXP (tmp, 1);
5197 rtx pat = PATTERN (other_insn);
5198 undobuf.other_insn = other_insn;
5199 SUBST (*cc_use, tmp);
5201 /* Attempt to simplify CC user. */
5202 if (GET_CODE (pat) == SET)
5204 rtx new = simplify_rtx (SET_SRC (pat));
5205 if (new != NULL_RTX)
5206 SUBST (SET_SRC (pat), new);
5209 /* Convert X into a no-op move. */
5210 SUBST (SET_DEST (x), pc_rtx);
5211 SUBST (SET_SRC (x), pc_rtx);
5215 /* Simplify our comparison, if possible. */
5216 new_code = simplify_comparison (new_code, &op0, &op1);
5218 #ifdef SELECT_CC_MODE
5219 /* If this machine has CC modes other than CCmode, check to see if we
5220 need to use a different CC mode here. */
5221 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
5222 compare_mode = GET_MODE (op0);
5224 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5227 /* If the mode changed, we have to change SET_DEST, the mode in the
5228 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5229 a hard register, just build new versions with the proper mode. If it
5230 is a pseudo, we lose unless it is only time we set the pseudo, in
5231 which case we can safely change its mode. */
5232 if (compare_mode != GET_MODE (dest))
5234 if (can_change_dest_mode (dest, 0, compare_mode))
5236 unsigned int regno = REGNO (dest);
5239 if (regno < FIRST_PSEUDO_REGISTER)
5240 new_dest = gen_rtx_REG (compare_mode, regno);
5243 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
5244 new_dest = regno_reg_rtx[regno];
5247 SUBST (SET_DEST (x), new_dest);
5248 SUBST (XEXP (*cc_use, 0), new_dest);
5255 #endif /* SELECT_CC_MODE */
5257 /* If the code changed, we have to build a new comparison in
5258 undobuf.other_insn. */
5259 if (new_code != old_code)
5261 int other_changed_previously = other_changed;
5262 unsigned HOST_WIDE_INT mask;
5264 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5268 /* If the only change we made was to change an EQ into an NE or
5269 vice versa, OP0 has only one bit that might be nonzero, and OP1
5270 is zero, check if changing the user of the condition code will
5271 produce a valid insn. If it won't, we can keep the original code
5272 in that insn by surrounding our operation with an XOR. */
5274 if (((old_code == NE && new_code == EQ)
5275 || (old_code == EQ && new_code == NE))
5276 && ! other_changed_previously && op1 == const0_rtx
5277 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5278 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5280 rtx pat = PATTERN (other_insn), note = 0;
5282 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
5283 && ! check_asm_operands (pat)))
5285 PUT_CODE (*cc_use, old_code);
5288 op0 = simplify_gen_binary (XOR, GET_MODE (op0),
5289 op0, GEN_INT (mask));
5295 undobuf.other_insn = other_insn;
5298 /* If we are now comparing against zero, change our source if
5299 needed. If we do not use cc0, we always have a COMPARE. */
5300 if (op1 == const0_rtx && dest == cc0_rtx)
5302 SUBST (SET_SRC (x), op0);
5308 /* Otherwise, if we didn't previously have a COMPARE in the
5309 correct mode, we need one. */
5310 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5312 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5315 else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
5317 SUBST(SET_SRC (x), op0);
5322 /* Otherwise, update the COMPARE if needed. */
5323 SUBST (XEXP (src, 0), op0);
5324 SUBST (XEXP (src, 1), op1);
5329 /* Get SET_SRC in a form where we have placed back any
5330 compound expressions. Then do the checks below. */
5331 src = make_compound_operation (src, SET);
5332 SUBST (SET_SRC (x), src);
5335 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5336 and X being a REG or (subreg (reg)), we may be able to convert this to
5337 (set (subreg:m2 x) (op)).
5339 We can always do this if M1 is narrower than M2 because that means that
5340 we only care about the low bits of the result.
5342 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5343 perform a narrower operation than requested since the high-order bits will
5344 be undefined. On machine where it is defined, this transformation is safe
5345 as long as M1 and M2 have the same number of words. */
5347 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5348 && !OBJECT_P (SUBREG_REG (src))
5349 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5351 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5352 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5353 #ifndef WORD_REGISTER_OPERATIONS
5354 && (GET_MODE_SIZE (GET_MODE (src))
5355 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5357 #ifdef CANNOT_CHANGE_MODE_CLASS
5358 && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
5359 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
5360 GET_MODE (SUBREG_REG (src)),
5364 || (GET_CODE (dest) == SUBREG
5365 && REG_P (SUBREG_REG (dest)))))
5367 SUBST (SET_DEST (x),
5368 gen_lowpart (GET_MODE (SUBREG_REG (src)),
5370 SUBST (SET_SRC (x), SUBREG_REG (src));
5372 src = SET_SRC (x), dest = SET_DEST (x);
5376 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5379 && GET_CODE (src) == SUBREG
5380 && subreg_lowpart_p (src)
5381 && (GET_MODE_BITSIZE (GET_MODE (src))
5382 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
5384 rtx inner = SUBREG_REG (src);
5385 enum machine_mode inner_mode = GET_MODE (inner);
5387 /* Here we make sure that we don't have a sign bit on. */
5388 if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
5389 && (nonzero_bits (inner, inner_mode)
5390 < ((unsigned HOST_WIDE_INT) 1
5391 << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
5393 SUBST (SET_SRC (x), inner);
5399 #ifdef LOAD_EXTEND_OP
5400 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5401 would require a paradoxical subreg. Replace the subreg with a
5402 zero_extend to avoid the reload that would otherwise be required. */
5404 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5405 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
5406 && SUBREG_BYTE (src) == 0
5407 && (GET_MODE_SIZE (GET_MODE (src))
5408 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5409 && MEM_P (SUBREG_REG (src)))
5412 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5413 GET_MODE (src), SUBREG_REG (src)));
5419 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5420 are comparing an item known to be 0 or -1 against 0, use a logical
5421 operation instead. Check for one of the arms being an IOR of the other
5422 arm with some value. We compute three terms to be IOR'ed together. In
5423 practice, at most two will be nonzero. Then we do the IOR's. */
5425 if (GET_CODE (dest) != PC
5426 && GET_CODE (src) == IF_THEN_ELSE
5427 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5428 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5429 && XEXP (XEXP (src, 0), 1) == const0_rtx
5430 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5431 #ifdef HAVE_conditional_move
5432 && ! can_conditionally_move_p (GET_MODE (src))
5434 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5435 GET_MODE (XEXP (XEXP (src, 0), 0)))
5436 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5437 && ! side_effects_p (src))
5439 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
5440 ? XEXP (src, 1) : XEXP (src, 2));
5441 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
5442 ? XEXP (src, 2) : XEXP (src, 1));
5443 rtx term1 = const0_rtx, term2, term3;
5445 if (GET_CODE (true_rtx) == IOR
5446 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
5447 term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
5448 else if (GET_CODE (true_rtx) == IOR
5449 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
5450 term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
5451 else if (GET_CODE (false_rtx) == IOR
5452 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
5453 term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
5454 else if (GET_CODE (false_rtx) == IOR
5455 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
5456 term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
5458 term2 = simplify_gen_binary (AND, GET_MODE (src),
5459 XEXP (XEXP (src, 0), 0), true_rtx);
5460 term3 = simplify_gen_binary (AND, GET_MODE (src),
5461 simplify_gen_unary (NOT, GET_MODE (src),
5462 XEXP (XEXP (src, 0), 0),
5467 simplify_gen_binary (IOR, GET_MODE (src),
5468 simplify_gen_binary (IOR, GET_MODE (src),
5475 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5476 whole thing fail. */
5477 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5479 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5482 /* Convert this into a field assignment operation, if possible. */
5483 return make_field_assignment (x);
5486 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5490 simplify_logical (rtx x)
5492 enum machine_mode mode = GET_MODE (x);
5493 rtx op0 = XEXP (x, 0);
5494 rtx op1 = XEXP (x, 1);
5496 switch (GET_CODE (x))
5499 /* We can call simplify_and_const_int only if we don't lose
5500 any (sign) bits when converting INTVAL (op1) to
5501 "unsigned HOST_WIDE_INT". */
5502 if (GET_CODE (op1) == CONST_INT
5503 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5504 || INTVAL (op1) > 0))
5506 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5507 if (GET_CODE (x) != AND)
5514 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
5515 apply the distributive law and then the inverse distributive
5516 law to see if things simplify. */
5517 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5519 rtx result = distribute_and_simplify_rtx (x, 0);
5523 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5525 rtx result = distribute_and_simplify_rtx (x, 1);
5532 /* If we have (ior (and A B) C), apply the distributive law and then
5533 the inverse distributive law to see if things simplify. */
5535 if (GET_CODE (op0) == AND)
5537 rtx result = distribute_and_simplify_rtx (x, 0);
5542 if (GET_CODE (op1) == AND)
5544 rtx result = distribute_and_simplify_rtx (x, 1);
5557 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5558 operations" because they can be replaced with two more basic operations.
5559 ZERO_EXTEND is also considered "compound" because it can be replaced with
5560 an AND operation, which is simpler, though only one operation.
5562 The function expand_compound_operation is called with an rtx expression
5563 and will convert it to the appropriate shifts and AND operations,
5564 simplifying at each stage.
5566 The function make_compound_operation is called to convert an expression
5567 consisting of shifts and ANDs into the equivalent compound expression.
5568 It is the inverse of this function, loosely speaking. */
5571 expand_compound_operation (rtx x)
5573 unsigned HOST_WIDE_INT pos = 0, len;
5575 unsigned int modewidth;
5578 switch (GET_CODE (x))
5583 /* We can't necessarily use a const_int for a multiword mode;
5584 it depends on implicitly extending the value.
5585 Since we don't know the right way to extend it,
5586 we can't tell whether the implicit way is right.
5588 Even for a mode that is no wider than a const_int,
5589 we can't win, because we need to sign extend one of its bits through
5590 the rest of it, and we don't know which bit. */
5591 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5594 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5595 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5596 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5597 reloaded. If not for that, MEM's would very rarely be safe.
5599 Reject MODEs bigger than a word, because we might not be able
5600 to reference a two-register group starting with an arbitrary register
5601 (and currently gen_lowpart might crash for a SUBREG). */
5603 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5606 /* Reject MODEs that aren't scalar integers because turning vector
5607 or complex modes into shifts causes problems. */
5609 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5612 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5613 /* If the inner object has VOIDmode (the only way this can happen
5614 is if it is an ASM_OPERANDS), we can't do anything since we don't
5615 know how much masking to do. */
5624 /* ... fall through ... */
5627 /* If the operand is a CLOBBER, just return it. */
5628 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5631 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5632 || GET_CODE (XEXP (x, 2)) != CONST_INT
5633 || GET_MODE (XEXP (x, 0)) == VOIDmode)
5636 /* Reject MODEs that aren't scalar integers because turning vector
5637 or complex modes into shifts causes problems. */
5639 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5642 len = INTVAL (XEXP (x, 1));
5643 pos = INTVAL (XEXP (x, 2));
5645 /* This should stay within the object being extracted, fail otherwise. */
5646 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5649 if (BITS_BIG_ENDIAN)
5650 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5657 /* Convert sign extension to zero extension, if we know that the high
5658 bit is not set, as this is easier to optimize. It will be converted
5659 back to cheaper alternative in make_extraction. */
5660 if (GET_CODE (x) == SIGN_EXTEND
5661 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5662 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
5663 & ~(((unsigned HOST_WIDE_INT)
5664 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5668 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
5669 rtx temp2 = expand_compound_operation (temp);
5671 /* Make sure this is a profitable operation. */
5672 if (rtx_cost (x, SET) > rtx_cost (temp2, SET))
5674 else if (rtx_cost (x, SET) > rtx_cost (temp, SET))
5680 /* We can optimize some special cases of ZERO_EXTEND. */
5681 if (GET_CODE (x) == ZERO_EXTEND)
5683 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5684 know that the last value didn't have any inappropriate bits
5686 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5687 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5688 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5689 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5690 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5691 return XEXP (XEXP (x, 0), 0);
5693 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5694 if (GET_CODE (XEXP (x, 0)) == SUBREG
5695 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5696 && subreg_lowpart_p (XEXP (x, 0))
5697 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5698 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5699 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5700 return SUBREG_REG (XEXP (x, 0));
5702 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5703 is a comparison and STORE_FLAG_VALUE permits. This is like
5704 the first case, but it works even when GET_MODE (x) is larger
5705 than HOST_WIDE_INT. */
5706 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5707 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5708 && COMPARISON_P (XEXP (XEXP (x, 0), 0))
5709 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5710 <= HOST_BITS_PER_WIDE_INT)
5711 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5712 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5713 return XEXP (XEXP (x, 0), 0);
5715 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5716 if (GET_CODE (XEXP (x, 0)) == SUBREG
5717 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5718 && subreg_lowpart_p (XEXP (x, 0))
5719 && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
5720 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5721 <= HOST_BITS_PER_WIDE_INT)
5722 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5723 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5724 return SUBREG_REG (XEXP (x, 0));
5728 /* If we reach here, we want to return a pair of shifts. The inner
5729 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5730 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5731 logical depending on the value of UNSIGNEDP.
5733 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5734 converted into an AND of a shift.
5736 We must check for the case where the left shift would have a negative
5737 count. This can happen in a case like (x >> 31) & 255 on machines
5738 that can't shift by a constant. On those machines, we would first
5739 combine the shift with the AND to produce a variable-position
5740 extraction. Then the constant of 31 would be substituted in to produce
5741 a such a position. */
5743 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5744 if (modewidth + len >= pos)
5746 enum machine_mode mode = GET_MODE (x);
5747 tem = gen_lowpart (mode, XEXP (x, 0));
5748 if (!tem || GET_CODE (tem) == CLOBBER)
5750 tem = simplify_shift_const (NULL_RTX, ASHIFT, mode,
5751 tem, modewidth - pos - len);
5752 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5753 mode, tem, modewidth - len);
5755 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5756 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5757 simplify_shift_const (NULL_RTX, LSHIFTRT,
5760 ((HOST_WIDE_INT) 1 << len) - 1);
5762 /* Any other cases we can't handle. */
5765 /* If we couldn't do this for some reason, return the original
5767 if (GET_CODE (tem) == CLOBBER)
5773 /* X is a SET which contains an assignment of one object into
5774 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5775 or certain SUBREGS). If possible, convert it into a series of
5778 We half-heartedly support variable positions, but do not at all
5779 support variable lengths. */
5782 expand_field_assignment (rtx x)
5785 rtx pos; /* Always counts from low bit. */
5787 rtx mask, cleared, masked;
5788 enum machine_mode compute_mode;
5790 /* Loop until we find something we can't simplify. */
5793 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5794 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5796 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5797 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5798 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
5800 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5801 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5803 inner = XEXP (SET_DEST (x), 0);
5804 len = INTVAL (XEXP (SET_DEST (x), 1));
5805 pos = XEXP (SET_DEST (x), 2);
5807 /* A constant position should stay within the width of INNER. */
5808 if (GET_CODE (pos) == CONST_INT
5809 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5812 if (BITS_BIG_ENDIAN)
5814 if (GET_CODE (pos) == CONST_INT)
5815 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5817 else if (GET_CODE (pos) == MINUS
5818 && GET_CODE (XEXP (pos, 1)) == CONST_INT
5819 && (INTVAL (XEXP (pos, 1))
5820 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5821 /* If position is ADJUST - X, new position is X. */
5822 pos = XEXP (pos, 0);
5824 pos = simplify_gen_binary (MINUS, GET_MODE (pos),
5825 GEN_INT (GET_MODE_BITSIZE (
5832 /* A SUBREG between two modes that occupy the same numbers of words
5833 can be done by moving the SUBREG to the source. */
5834 else if (GET_CODE (SET_DEST (x)) == SUBREG
5835 /* We need SUBREGs to compute nonzero_bits properly. */
5836 && nonzero_sign_valid
5837 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5838 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5839 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5840 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5842 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
5844 (GET_MODE (SUBREG_REG (SET_DEST (x))),
5851 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5852 inner = SUBREG_REG (inner);
5854 compute_mode = GET_MODE (inner);
5856 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
5857 if (! SCALAR_INT_MODE_P (compute_mode))
5859 enum machine_mode imode;
5861 /* Don't do anything for vector or complex integral types. */
5862 if (! FLOAT_MODE_P (compute_mode))
5865 /* Try to find an integral mode to pun with. */
5866 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
5867 if (imode == BLKmode)
5870 compute_mode = imode;
5871 inner = gen_lowpart (imode, inner);
5874 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5875 if (len >= HOST_BITS_PER_WIDE_INT)
5878 /* Now compute the equivalent expression. Make a copy of INNER
5879 for the SET_DEST in case it is a MEM into which we will substitute;
5880 we don't want shared RTL in that case. */
5881 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
5882 cleared = simplify_gen_binary (AND, compute_mode,
5883 simplify_gen_unary (NOT, compute_mode,
5884 simplify_gen_binary (ASHIFT,
5889 masked = simplify_gen_binary (ASHIFT, compute_mode,
5890 simplify_gen_binary (
5892 gen_lowpart (compute_mode, SET_SRC (x)),
5896 x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
5897 simplify_gen_binary (IOR, compute_mode,
5904 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5905 it is an RTX that represents a variable starting position; otherwise,
5906 POS is the (constant) starting bit position (counted from the LSB).
5908 UNSIGNEDP is nonzero for an unsigned reference and zero for a
5911 IN_DEST is nonzero if this is a reference in the destination of a
5912 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
5913 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5916 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
5917 ZERO_EXTRACT should be built even for bits starting at bit 0.
5919 MODE is the desired mode of the result (if IN_DEST == 0).
5921 The result is an RTX for the extraction or NULL_RTX if the target
5925 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
5926 rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
5927 int in_dest, int in_compare)
5929 /* This mode describes the size of the storage area
5930 to fetch the overall value from. Within that, we
5931 ignore the POS lowest bits, etc. */
5932 enum machine_mode is_mode = GET_MODE (inner);
5933 enum machine_mode inner_mode;
5934 enum machine_mode wanted_inner_mode;
5935 enum machine_mode wanted_inner_reg_mode = word_mode;
5936 enum machine_mode pos_mode = word_mode;
5937 enum machine_mode extraction_mode = word_mode;
5938 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
5940 rtx orig_pos_rtx = pos_rtx;
5941 HOST_WIDE_INT orig_pos;
5943 if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5945 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5946 consider just the QI as the memory to extract from.
5947 The subreg adds or removes high bits; its mode is
5948 irrelevant to the meaning of this extraction,
5949 since POS and LEN count from the lsb. */
5950 if (MEM_P (SUBREG_REG (inner)))
5951 is_mode = GET_MODE (SUBREG_REG (inner));
5952 inner = SUBREG_REG (inner);
5954 else if (GET_CODE (inner) == ASHIFT
5955 && GET_CODE (XEXP (inner, 1)) == CONST_INT
5956 && pos_rtx == 0 && pos == 0
5957 && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1)))
5959 /* We're extracting the least significant bits of an rtx
5960 (ashift X (const_int C)), where LEN > C. Extract the
5961 least significant (LEN - C) bits of X, giving an rtx
5962 whose mode is MODE, then shift it left C times. */
5963 new = make_extraction (mode, XEXP (inner, 0),
5964 0, 0, len - INTVAL (XEXP (inner, 1)),
5965 unsignedp, in_dest, in_compare);
5967 return gen_rtx_ASHIFT (mode, new, XEXP (inner, 1));
5970 inner_mode = GET_MODE (inner);
5972 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
5973 pos = INTVAL (pos_rtx), pos_rtx = 0;
5975 /* See if this can be done without an extraction. We never can if the
5976 width of the field is not the same as that of some integer mode. For
5977 registers, we can only avoid the extraction if the position is at the
5978 low-order bit and this is either not in the destination or we have the
5979 appropriate STRICT_LOW_PART operation available.
5981 For MEM, we can avoid an extract if the field starts on an appropriate
5982 boundary and we can change the mode of the memory reference. */
5984 if (tmode != BLKmode
5985 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
5987 && (inner_mode == tmode
5989 || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
5990 GET_MODE_BITSIZE (inner_mode))
5991 || reg_truncated_to_mode (tmode, inner))
5994 && have_insn_for (STRICT_LOW_PART, tmode))))
5995 || (MEM_P (inner) && pos_rtx == 0
5997 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
5998 : BITS_PER_UNIT)) == 0
5999 /* We can't do this if we are widening INNER_MODE (it
6000 may not be aligned, for one thing). */
6001 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
6002 && (inner_mode == tmode
6003 || (! mode_dependent_address_p (XEXP (inner, 0))
6004 && ! MEM_VOLATILE_P (inner))))))
6006 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6007 field. If the original and current mode are the same, we need not
6008 adjust the offset. Otherwise, we do if bytes big endian.
6010 If INNER is not a MEM, get a piece consisting of just the field
6011 of interest (in this case POS % BITS_PER_WORD must be 0). */
6015 HOST_WIDE_INT offset;
6017 /* POS counts from lsb, but make OFFSET count in memory order. */
6018 if (BYTES_BIG_ENDIAN)
6019 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
6021 offset = pos / BITS_PER_UNIT;
6023 new = adjust_address_nv (inner, tmode, offset);
6025 else if (REG_P (inner))
6027 if (tmode != inner_mode)
6029 /* We can't call gen_lowpart in a DEST since we
6030 always want a SUBREG (see below) and it would sometimes
6031 return a new hard register. */
6034 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
6036 if (WORDS_BIG_ENDIAN
6037 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
6038 final_word = ((GET_MODE_SIZE (inner_mode)
6039 - GET_MODE_SIZE (tmode))
6040 / UNITS_PER_WORD) - final_word;
6042 final_word *= UNITS_PER_WORD;
6043 if (BYTES_BIG_ENDIAN &&
6044 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
6045 final_word += (GET_MODE_SIZE (inner_mode)
6046 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
6048 /* Avoid creating invalid subregs, for example when
6049 simplifying (x>>32)&255. */
6050 if (!validate_subreg (tmode, inner_mode, inner, final_word))
6053 new = gen_rtx_SUBREG (tmode, inner, final_word);
6056 new = gen_lowpart (tmode, inner);
6062 new = force_to_mode (inner, tmode,
6063 len >= HOST_BITS_PER_WIDE_INT
6064 ? ~(unsigned HOST_WIDE_INT) 0
6065 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6068 /* If this extraction is going into the destination of a SET,
6069 make a STRICT_LOW_PART unless we made a MEM. */
6072 return (MEM_P (new) ? new
6073 : (GET_CODE (new) != SUBREG
6074 ? gen_rtx_CLOBBER (tmode, const0_rtx)
6075 : gen_rtx_STRICT_LOW_PART (VOIDmode, new)));
6080 if (GET_CODE (new) == CONST_INT)
6081 return gen_int_mode (INTVAL (new), mode);
6083 /* If we know that no extraneous bits are set, and that the high
6084 bit is not set, convert the extraction to the cheaper of
6085 sign and zero extension, that are equivalent in these cases. */
6086 if (flag_expensive_optimizations
6087 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6088 && ((nonzero_bits (new, tmode)
6089 & ~(((unsigned HOST_WIDE_INT)
6090 GET_MODE_MASK (tmode))
6094 rtx temp = gen_rtx_ZERO_EXTEND (mode, new);
6095 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new);
6097 /* Prefer ZERO_EXTENSION, since it gives more information to
6099 if (rtx_cost (temp, SET) <= rtx_cost (temp1, SET))
6104 /* Otherwise, sign- or zero-extend unless we already are in the
6107 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6111 /* Unless this is a COMPARE or we have a funny memory reference,
6112 don't do anything with zero-extending field extracts starting at
6113 the low-order bit since they are simple AND operations. */
6114 if (pos_rtx == 0 && pos == 0 && ! in_dest
6115 && ! in_compare && unsignedp)
6118 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
6119 if the position is not a constant and the length is not 1. In all
6120 other cases, we would only be going outside our object in cases when
6121 an original shift would have been undefined. */
6123 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6124 || (pos_rtx != 0 && len != 1)))
6127 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6128 and the mode for the result. */
6129 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6131 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6132 pos_mode = mode_for_extraction (EP_insv, 2);
6133 extraction_mode = mode_for_extraction (EP_insv, 3);
6136 if (! in_dest && unsignedp
6137 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6139 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6140 pos_mode = mode_for_extraction (EP_extzv, 3);
6141 extraction_mode = mode_for_extraction (EP_extzv, 0);
6144 if (! in_dest && ! unsignedp
6145 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6147 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6148 pos_mode = mode_for_extraction (EP_extv, 3);
6149 extraction_mode = mode_for_extraction (EP_extv, 0);
6152 /* Never narrow an object, since that might not be safe. */
6154 if (mode != VOIDmode
6155 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6156 extraction_mode = mode;
6158 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6159 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6160 pos_mode = GET_MODE (pos_rtx);
6162 /* If this is not from memory, the desired mode is the preferred mode
6163 for an extraction pattern's first input operand, or word_mode if there
6166 wanted_inner_mode = wanted_inner_reg_mode;
6169 /* Be careful not to go beyond the extracted object and maintain the
6170 natural alignment of the memory. */
6171 wanted_inner_mode = smallest_mode_for_size (len, MODE_INT);
6172 while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len
6173 > GET_MODE_BITSIZE (wanted_inner_mode))
6175 wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode);
6176 gcc_assert (wanted_inner_mode != VOIDmode);
6179 /* If we have to change the mode of memory and cannot, the desired mode
6180 is EXTRACTION_MODE. */
6181 if (inner_mode != wanted_inner_mode
6182 && (mode_dependent_address_p (XEXP (inner, 0))
6183 || MEM_VOLATILE_P (inner)
6185 wanted_inner_mode = extraction_mode;
6190 if (BITS_BIG_ENDIAN)
6192 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6193 BITS_BIG_ENDIAN style. If position is constant, compute new
6194 position. Otherwise, build subtraction.
6195 Note that POS is relative to the mode of the original argument.
6196 If it's a MEM we need to recompute POS relative to that.
6197 However, if we're extracting from (or inserting into) a register,
6198 we want to recompute POS relative to wanted_inner_mode. */
6199 int width = (MEM_P (inner)
6200 ? GET_MODE_BITSIZE (is_mode)
6201 : GET_MODE_BITSIZE (wanted_inner_mode));
6204 pos = width - len - pos;
6207 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6208 /* POS may be less than 0 now, but we check for that below.
6209 Note that it can only be less than 0 if !MEM_P (inner). */
6212 /* If INNER has a wider mode, and this is a constant extraction, try to
6213 make it smaller and adjust the byte to point to the byte containing
6215 if (wanted_inner_mode != VOIDmode
6216 && inner_mode != wanted_inner_mode
6218 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6220 && ! mode_dependent_address_p (XEXP (inner, 0))
6221 && ! MEM_VOLATILE_P (inner))
6225 /* The computations below will be correct if the machine is big
6226 endian in both bits and bytes or little endian in bits and bytes.
6227 If it is mixed, we must adjust. */
6229 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6230 adjust OFFSET to compensate. */
6231 if (BYTES_BIG_ENDIAN
6232 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6233 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6235 /* We can now move to the desired byte. */
6236 offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode))
6237 * GET_MODE_SIZE (wanted_inner_mode);
6238 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6240 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6241 && is_mode != wanted_inner_mode)
6242 offset = (GET_MODE_SIZE (is_mode)
6243 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6245 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6248 /* If INNER is not memory, we can always get it into the proper mode. If we
6249 are changing its mode, POS must be a constant and smaller than the size
6251 else if (!MEM_P (inner))
6253 if (GET_MODE (inner) != wanted_inner_mode
6255 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6261 inner = force_to_mode (inner, wanted_inner_mode,
6263 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6264 ? ~(unsigned HOST_WIDE_INT) 0
6265 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6270 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6271 have to zero extend. Otherwise, we can just use a SUBREG. */
6273 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6275 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6277 /* If we know that no extraneous bits are set, and that the high
6278 bit is not set, convert extraction to cheaper one - either
6279 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6281 if (flag_expensive_optimizations
6282 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6283 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6284 & ~(((unsigned HOST_WIDE_INT)
6285 GET_MODE_MASK (GET_MODE (pos_rtx)))
6289 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6291 /* Prefer ZERO_EXTENSION, since it gives more information to
6293 if (rtx_cost (temp1, SET) < rtx_cost (temp, SET))
6298 else if (pos_rtx != 0
6299 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6300 pos_rtx = gen_lowpart (pos_mode, pos_rtx);
6302 /* Make POS_RTX unless we already have it and it is correct. If we don't
6303 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6305 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6306 pos_rtx = orig_pos_rtx;
6308 else if (pos_rtx == 0)
6309 pos_rtx = GEN_INT (pos);
6311 /* Make the required operation. See if we can use existing rtx. */
6312 new = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6313 extraction_mode, inner, GEN_INT (len), pos_rtx);
6315 new = gen_lowpart (mode, new);
6320 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6321 with any other operations in X. Return X without that shift if so. */
6324 extract_left_shift (rtx x, int count)
6326 enum rtx_code code = GET_CODE (x);
6327 enum machine_mode mode = GET_MODE (x);
6333 /* This is the shift itself. If it is wide enough, we will return
6334 either the value being shifted if the shift count is equal to
6335 COUNT or a shift for the difference. */
6336 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6337 && INTVAL (XEXP (x, 1)) >= count)
6338 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6339 INTVAL (XEXP (x, 1)) - count);
6343 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6344 return simplify_gen_unary (code, mode, tem, mode);
6348 case PLUS: case IOR: case XOR: case AND:
6349 /* If we can safely shift this constant and we find the inner shift,
6350 make a new operation. */
6351 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6352 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6353 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6354 return simplify_gen_binary (code, mode, tem,
6355 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6366 /* Look at the expression rooted at X. Look for expressions
6367 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6368 Form these expressions.
6370 Return the new rtx, usually just X.
6372 Also, for machines like the VAX that don't have logical shift insns,
6373 try to convert logical to arithmetic shift operations in cases where
6374 they are equivalent. This undoes the canonicalizations to logical
6375 shifts done elsewhere.
6377 We try, as much as possible, to re-use rtl expressions to save memory.
6379 IN_CODE says what kind of expression we are processing. Normally, it is
6380 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6381 being kludges), it is MEM. When processing the arguments of a comparison
6382 or a COMPARE against zero, it is COMPARE. */
6385 make_compound_operation (rtx x, enum rtx_code in_code)
6387 enum rtx_code code = GET_CODE (x);
6388 enum machine_mode mode = GET_MODE (x);
6389 int mode_width = GET_MODE_BITSIZE (mode);
6391 enum rtx_code next_code;
6397 /* Select the code to be used in recursive calls. Once we are inside an
6398 address, we stay there. If we have a comparison, set to COMPARE,
6399 but once inside, go back to our default of SET. */
6401 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6402 : ((code == COMPARE || COMPARISON_P (x))
6403 && XEXP (x, 1) == const0_rtx) ? COMPARE
6404 : in_code == COMPARE ? SET : in_code);
6406 /* Process depending on the code of this operation. If NEW is set
6407 nonzero, it will be returned. */
6412 /* Convert shifts by constants into multiplications if inside
6414 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6415 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6416 && INTVAL (XEXP (x, 1)) >= 0)
6418 new = make_compound_operation (XEXP (x, 0), next_code);
6419 new = gen_rtx_MULT (mode, new,
6420 GEN_INT ((HOST_WIDE_INT) 1
6421 << INTVAL (XEXP (x, 1))));
6426 /* If the second operand is not a constant, we can't do anything
6428 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6431 /* If the constant is a power of two minus one and the first operand
6432 is a logical right shift, make an extraction. */
6433 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6434 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6436 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6437 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6438 0, in_code == COMPARE);
6441 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6442 else if (GET_CODE (XEXP (x, 0)) == SUBREG
6443 && subreg_lowpart_p (XEXP (x, 0))
6444 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6445 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6447 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6449 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6450 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6451 0, in_code == COMPARE);
6453 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6454 else if ((GET_CODE (XEXP (x, 0)) == XOR
6455 || GET_CODE (XEXP (x, 0)) == IOR)
6456 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6457 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6458 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6460 /* Apply the distributive law, and then try to make extractions. */
6461 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
6462 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6464 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6466 new = make_compound_operation (new, in_code);
6469 /* If we are have (and (rotate X C) M) and C is larger than the number
6470 of bits in M, this is an extraction. */
6472 else if (GET_CODE (XEXP (x, 0)) == ROTATE
6473 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6474 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6475 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6477 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6478 new = make_extraction (mode, new,
6479 (GET_MODE_BITSIZE (mode)
6480 - INTVAL (XEXP (XEXP (x, 0), 1))),
6481 NULL_RTX, i, 1, 0, in_code == COMPARE);
6484 /* On machines without logical shifts, if the operand of the AND is
6485 a logical shift and our mask turns off all the propagated sign
6486 bits, we can replace the logical shift with an arithmetic shift. */
6487 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6488 && !have_insn_for (LSHIFTRT, mode)
6489 && have_insn_for (ASHIFTRT, mode)
6490 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6491 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6492 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6493 && mode_width <= HOST_BITS_PER_WIDE_INT)
6495 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6497 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6498 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6500 gen_rtx_ASHIFTRT (mode,
6501 make_compound_operation
6502 (XEXP (XEXP (x, 0), 0), next_code),
6503 XEXP (XEXP (x, 0), 1)));
6506 /* If the constant is one less than a power of two, this might be
6507 representable by an extraction even if no shift is present.
6508 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6509 we are in a COMPARE. */
6510 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6511 new = make_extraction (mode,
6512 make_compound_operation (XEXP (x, 0),
6514 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6516 /* If we are in a comparison and this is an AND with a power of two,
6517 convert this into the appropriate bit extract. */
6518 else if (in_code == COMPARE
6519 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6520 new = make_extraction (mode,
6521 make_compound_operation (XEXP (x, 0),
6523 i, NULL_RTX, 1, 1, 0, 1);
6528 /* If the sign bit is known to be zero, replace this with an
6529 arithmetic shift. */
6530 if (have_insn_for (ASHIFTRT, mode)
6531 && ! have_insn_for (LSHIFTRT, mode)
6532 && mode_width <= HOST_BITS_PER_WIDE_INT
6533 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6535 new = gen_rtx_ASHIFTRT (mode,
6536 make_compound_operation (XEXP (x, 0),
6542 /* ... fall through ... */
6548 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6549 this is a SIGN_EXTRACT. */
6550 if (GET_CODE (rhs) == CONST_INT
6551 && GET_CODE (lhs) == ASHIFT
6552 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6553 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6555 new = make_compound_operation (XEXP (lhs, 0), next_code);
6556 new = make_extraction (mode, new,
6557 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6558 NULL_RTX, mode_width - INTVAL (rhs),
6559 code == LSHIFTRT, 0, in_code == COMPARE);
6563 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6564 If so, try to merge the shifts into a SIGN_EXTEND. We could
6565 also do this for some cases of SIGN_EXTRACT, but it doesn't
6566 seem worth the effort; the case checked for occurs on Alpha. */
6569 && ! (GET_CODE (lhs) == SUBREG
6570 && (OBJECT_P (SUBREG_REG (lhs))))
6571 && GET_CODE (rhs) == CONST_INT
6572 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6573 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6574 new = make_extraction (mode, make_compound_operation (new, next_code),
6575 0, NULL_RTX, mode_width - INTVAL (rhs),
6576 code == LSHIFTRT, 0, in_code == COMPARE);
6581 /* Call ourselves recursively on the inner expression. If we are
6582 narrowing the object and it has a different RTL code from
6583 what it originally did, do this SUBREG as a force_to_mode. */
6585 tem = make_compound_operation (SUBREG_REG (x), in_code);
6589 simplified = simplify_subreg (GET_MODE (x), tem, GET_MODE (tem),
6595 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6596 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6597 && subreg_lowpart_p (x))
6599 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
6602 /* If we have something other than a SUBREG, we might have
6603 done an expansion, so rerun ourselves. */
6604 if (GET_CODE (newer) != SUBREG)
6605 newer = make_compound_operation (newer, in_code);
6621 x = gen_lowpart (mode, new);
6622 code = GET_CODE (x);
6625 /* Now recursively process each operand of this operation. */
6626 fmt = GET_RTX_FORMAT (code);
6627 for (i = 0; i < GET_RTX_LENGTH (code); i++)
6630 new = make_compound_operation (XEXP (x, i), next_code);
6631 SUBST (XEXP (x, i), new);
6634 /* If this is a commutative operation, the changes to the operands
6635 may have made it noncanonical. */
6636 if (COMMUTATIVE_ARITH_P (x)
6637 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
6640 SUBST (XEXP (x, 0), XEXP (x, 1));
6641 SUBST (XEXP (x, 1), tem);
6647 /* Given M see if it is a value that would select a field of bits
6648 within an item, but not the entire word. Return -1 if not.
6649 Otherwise, return the starting position of the field, where 0 is the
6652 *PLEN is set to the length of the field. */
6655 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
6657 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6658 int pos = exact_log2 (m & -m);
6662 /* Now shift off the low-order zero bits and see if we have a
6663 power of two minus 1. */
6664 len = exact_log2 ((m >> pos) + 1);
6673 /* If X refers to a register that equals REG in value, replace these
6674 references with REG. */
6676 canon_reg_for_combine (rtx x, rtx reg)
6683 enum rtx_code code = GET_CODE (x);
6684 switch (GET_RTX_CLASS (code))
6687 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
6688 if (op0 != XEXP (x, 0))
6689 return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
6694 case RTX_COMM_ARITH:
6695 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
6696 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
6697 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6698 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
6702 case RTX_COMM_COMPARE:
6703 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
6704 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
6705 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6706 return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
6707 GET_MODE (op0), op0, op1);
6711 case RTX_BITFIELD_OPS:
6712 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
6713 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
6714 op2 = canon_reg_for_combine (XEXP (x, 2), reg);
6715 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
6716 return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
6717 GET_MODE (op0), op0, op1, op2);
6722 if (rtx_equal_p (get_last_value (reg), x)
6723 || rtx_equal_p (reg, get_last_value (x)))
6732 fmt = GET_RTX_FORMAT (code);
6734 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6737 rtx op = canon_reg_for_combine (XEXP (x, i), reg);
6738 if (op != XEXP (x, i))
6748 else if (fmt[i] == 'E')
6751 for (j = 0; j < XVECLEN (x, i); j++)
6753 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
6754 if (op != XVECEXP (x, i, j))
6761 XVECEXP (x, i, j) = op;
6772 /* Return X converted to MODE. If the value is already truncated to
6773 MODE we can just return a subreg even though in the general case we
6774 would need an explicit truncation. */
6777 gen_lowpart_or_truncate (enum machine_mode mode, rtx x)
6779 if (GET_MODE_SIZE (GET_MODE (x)) <= GET_MODE_SIZE (mode)
6780 || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
6781 GET_MODE_BITSIZE (GET_MODE (x)))
6782 || (REG_P (x) && reg_truncated_to_mode (mode, x)))
6783 return gen_lowpart (mode, x);
6785 return simplify_gen_unary (TRUNCATE, mode, x, GET_MODE (x));
6788 /* See if X can be simplified knowing that we will only refer to it in
6789 MODE and will only refer to those bits that are nonzero in MASK.
6790 If other bits are being computed or if masking operations are done
6791 that select a superset of the bits in MASK, they can sometimes be
6794 Return a possibly simplified expression, but always convert X to
6795 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6797 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6798 are all off in X. This is used when X will be complemented, by either
6799 NOT, NEG, or XOR. */
6802 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
6805 enum rtx_code code = GET_CODE (x);
6806 int next_select = just_select || code == XOR || code == NOT || code == NEG;
6807 enum machine_mode op_mode;
6808 unsigned HOST_WIDE_INT fuller_mask, nonzero;
6811 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6812 code below will do the wrong thing since the mode of such an
6813 expression is VOIDmode.
6815 Also do nothing if X is a CLOBBER; this can happen if X was
6816 the return value from a call to gen_lowpart. */
6817 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
6820 /* We want to perform the operation is its present mode unless we know
6821 that the operation is valid in MODE, in which case we do the operation
6823 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6824 && have_insn_for (code, mode))
6825 ? mode : GET_MODE (x));
6827 /* It is not valid to do a right-shift in a narrower mode
6828 than the one it came in with. */
6829 if ((code == LSHIFTRT || code == ASHIFTRT)
6830 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6831 op_mode = GET_MODE (x);
6833 /* Truncate MASK to fit OP_MODE. */
6835 mask &= GET_MODE_MASK (op_mode);
6837 /* When we have an arithmetic operation, or a shift whose count we
6838 do not know, we need to assume that all bits up to the highest-order
6839 bit in MASK will be needed. This is how we form such a mask. */
6840 if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
6841 fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
6843 fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
6846 /* Determine what bits of X are guaranteed to be (non)zero. */
6847 nonzero = nonzero_bits (x, mode);
6849 /* If none of the bits in X are needed, return a zero. */
6850 if (! just_select && (nonzero & mask) == 0)
6853 /* If X is a CONST_INT, return a new one. Do this here since the
6854 test below will fail. */
6855 if (GET_CODE (x) == CONST_INT)
6857 if (SCALAR_INT_MODE_P (mode))
6858 return gen_int_mode (INTVAL (x) & mask, mode);
6861 x = GEN_INT (INTVAL (x) & mask);
6862 return gen_lowpart_common (mode, x);
6866 /* If X is narrower than MODE and we want all the bits in X's mode, just
6867 get X in the proper mode. */
6868 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6869 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
6870 return gen_lowpart (mode, x);
6875 /* If X is a (clobber (const_int)), return it since we know we are
6876 generating something that won't match. */
6883 x = expand_compound_operation (x);
6884 if (GET_CODE (x) != code)
6885 return force_to_mode (x, mode, mask, next_select);
6889 if (subreg_lowpart_p (x)
6890 /* We can ignore the effect of this SUBREG if it narrows the mode or
6891 if the constant masks to zero all the bits the mode doesn't
6893 && ((GET_MODE_SIZE (GET_MODE (x))
6894 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6896 & GET_MODE_MASK (GET_MODE (x))
6897 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6898 return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
6902 /* If this is an AND with a constant, convert it into an AND
6903 whose constant is the AND of that constant with MASK. If it
6904 remains an AND of MASK, delete it since it is redundant. */
6906 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6908 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6909 mask & INTVAL (XEXP (x, 1)));
6911 /* If X is still an AND, see if it is an AND with a mask that
6912 is just some low-order bits. If so, and it is MASK, we don't
6915 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6916 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
6920 /* If it remains an AND, try making another AND with the bits
6921 in the mode mask that aren't in MASK turned on. If the
6922 constant in the AND is wide enough, this might make a
6923 cheaper constant. */
6925 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6926 && GET_MODE_MASK (GET_MODE (x)) != mask
6927 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
6929 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6930 | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
6931 int width = GET_MODE_BITSIZE (GET_MODE (x));
6934 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
6935 number, sign extend it. */
6936 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6937 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6938 cval |= (HOST_WIDE_INT) -1 << width;
6940 y = simplify_gen_binary (AND, GET_MODE (x),
6941 XEXP (x, 0), GEN_INT (cval));
6942 if (rtx_cost (y, SET) < rtx_cost (x, SET))
6952 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6953 low-order bits (as in an alignment operation) and FOO is already
6954 aligned to that boundary, mask C1 to that boundary as well.
6955 This may eliminate that PLUS and, later, the AND. */
6958 unsigned int width = GET_MODE_BITSIZE (mode);
6959 unsigned HOST_WIDE_INT smask = mask;
6961 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6962 number, sign extend it. */
6964 if (width < HOST_BITS_PER_WIDE_INT
6965 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6966 smask |= (HOST_WIDE_INT) -1 << width;
6968 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6969 && exact_log2 (- smask) >= 0
6970 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
6971 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
6972 return force_to_mode (plus_constant (XEXP (x, 0),
6973 (INTVAL (XEXP (x, 1)) & smask)),
6974 mode, smask, next_select);
6977 /* ... fall through ... */
6980 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6981 most significant bit in MASK since carries from those bits will
6982 affect the bits we are interested in. */
6987 /* If X is (minus C Y) where C's least set bit is larger than any bit
6988 in the mask, then we may replace with (neg Y). */
6989 if (GET_CODE (XEXP (x, 0)) == CONST_INT
6990 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
6991 & -INTVAL (XEXP (x, 0))))
6994 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
6996 return force_to_mode (x, mode, mask, next_select);
6999 /* Similarly, if C contains every bit in the fuller_mask, then we may
7000 replace with (not Y). */
7001 if (GET_CODE (XEXP (x, 0)) == CONST_INT
7002 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask)
7003 == INTVAL (XEXP (x, 0))))
7005 x = simplify_gen_unary (NOT, GET_MODE (x),
7006 XEXP (x, 1), GET_MODE (x));
7007 return force_to_mode (x, mode, mask, next_select);
7015 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7016 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7017 operation which may be a bitfield extraction. Ensure that the
7018 constant we form is not wider than the mode of X. */
7020 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7021 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7022 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7023 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7024 && GET_CODE (XEXP (x, 1)) == CONST_INT
7025 && ((INTVAL (XEXP (XEXP (x, 0), 1))
7026 + floor_log2 (INTVAL (XEXP (x, 1))))
7027 < GET_MODE_BITSIZE (GET_MODE (x)))
7028 && (INTVAL (XEXP (x, 1))
7029 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
7031 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
7032 << INTVAL (XEXP (XEXP (x, 0), 1)));
7033 temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
7034 XEXP (XEXP (x, 0), 0), temp);
7035 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
7036 XEXP (XEXP (x, 0), 1));
7037 return force_to_mode (x, mode, mask, next_select);
7041 /* For most binary operations, just propagate into the operation and
7042 change the mode if we have an operation of that mode. */
7044 op0 = gen_lowpart_or_truncate (op_mode,
7045 force_to_mode (XEXP (x, 0), mode, mask,
7047 op1 = gen_lowpart_or_truncate (op_mode,
7048 force_to_mode (XEXP (x, 1), mode, mask,
7051 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7052 x = simplify_gen_binary (code, op_mode, op0, op1);
7056 /* For left shifts, do the same, but just for the first operand.
7057 However, we cannot do anything with shifts where we cannot
7058 guarantee that the counts are smaller than the size of the mode
7059 because such a count will have a different meaning in a
7062 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
7063 && INTVAL (XEXP (x, 1)) >= 0
7064 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
7065 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
7066 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
7067 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
7070 /* If the shift count is a constant and we can do arithmetic in
7071 the mode of the shift, refine which bits we need. Otherwise, use the
7072 conservative form of the mask. */
7073 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7074 && INTVAL (XEXP (x, 1)) >= 0
7075 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
7076 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7077 mask >>= INTVAL (XEXP (x, 1));
7081 op0 = gen_lowpart_or_truncate (op_mode,
7082 force_to_mode (XEXP (x, 0), op_mode,
7083 mask, next_select));
7085 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7086 x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
7090 /* Here we can only do something if the shift count is a constant,
7091 this shift constant is valid for the host, and we can do arithmetic
7094 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7095 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7096 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7098 rtx inner = XEXP (x, 0);
7099 unsigned HOST_WIDE_INT inner_mask;
7101 /* Select the mask of the bits we need for the shift operand. */
7102 inner_mask = mask << INTVAL (XEXP (x, 1));
7104 /* We can only change the mode of the shift if we can do arithmetic
7105 in the mode of the shift and INNER_MASK is no wider than the
7106 width of X's mode. */
7107 if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
7108 op_mode = GET_MODE (x);
7110 inner = force_to_mode (inner, op_mode, inner_mask, next_select);
7112 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
7113 x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
7116 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7117 shift and AND produces only copies of the sign bit (C2 is one less
7118 than a power of two), we can do this with just a shift. */
7120 if (GET_CODE (x) == LSHIFTRT
7121 && GET_CODE (XEXP (x, 1)) == CONST_INT
7122 /* The shift puts one of the sign bit copies in the least significant
7124 && ((INTVAL (XEXP (x, 1))
7125 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7126 >= GET_MODE_BITSIZE (GET_MODE (x)))
7127 && exact_log2 (mask + 1) >= 0
7128 /* Number of bits left after the shift must be more than the mask
7130 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7131 <= GET_MODE_BITSIZE (GET_MODE (x)))
7132 /* Must be more sign bit copies than the mask needs. */
7133 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7134 >= exact_log2 (mask + 1)))
7135 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7136 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7137 - exact_log2 (mask + 1)));
7142 /* If we are just looking for the sign bit, we don't need this shift at
7143 all, even if it has a variable count. */
7144 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7145 && (mask == ((unsigned HOST_WIDE_INT) 1
7146 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7147 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7149 /* If this is a shift by a constant, get a mask that contains those bits
7150 that are not copies of the sign bit. We then have two cases: If
7151 MASK only includes those bits, this can be a logical shift, which may
7152 allow simplifications. If MASK is a single-bit field not within
7153 those bits, we are requesting a copy of the sign bit and hence can
7154 shift the sign bit to the appropriate location. */
7156 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
7157 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7161 /* If the considered data is wider than HOST_WIDE_INT, we can't
7162 represent a mask for all its bits in a single scalar.
7163 But we only care about the lower bits, so calculate these. */
7165 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7167 nonzero = ~(HOST_WIDE_INT) 0;
7169 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7170 is the number of bits a full-width mask would have set.
7171 We need only shift if these are fewer than nonzero can
7172 hold. If not, we must keep all bits set in nonzero. */
7174 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7175 < HOST_BITS_PER_WIDE_INT)
7176 nonzero >>= INTVAL (XEXP (x, 1))
7177 + HOST_BITS_PER_WIDE_INT
7178 - GET_MODE_BITSIZE (GET_MODE (x)) ;
7182 nonzero = GET_MODE_MASK (GET_MODE (x));
7183 nonzero >>= INTVAL (XEXP (x, 1));
7186 if ((mask & ~nonzero) == 0)
7188 x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x),
7189 XEXP (x, 0), INTVAL (XEXP (x, 1)));
7190 if (GET_CODE (x) != ASHIFTRT)
7191 return force_to_mode (x, mode, mask, next_select);
7194 else if ((i = exact_log2 (mask)) >= 0)
7196 x = simplify_shift_const
7197 (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7198 GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7200 if (GET_CODE (x) != ASHIFTRT)
7201 return force_to_mode (x, mode, mask, next_select);
7205 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7206 even if the shift count isn't a constant. */
7208 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7209 XEXP (x, 0), XEXP (x, 1));
7213 /* If this is a zero- or sign-extension operation that just affects bits
7214 we don't care about, remove it. Be sure the call above returned
7215 something that is still a shift. */
7217 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7218 && GET_CODE (XEXP (x, 1)) == CONST_INT
7219 && INTVAL (XEXP (x, 1)) >= 0
7220 && (INTVAL (XEXP (x, 1))
7221 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7222 && GET_CODE (XEXP (x, 0)) == ASHIFT
7223 && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
7224 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7231 /* If the shift count is constant and we can do computations
7232 in the mode of X, compute where the bits we care about are.
7233 Otherwise, we can't do anything. Don't change the mode of
7234 the shift or propagate MODE into the shift, though. */
7235 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7236 && INTVAL (XEXP (x, 1)) >= 0)
7238 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7239 GET_MODE (x), GEN_INT (mask),
7241 if (temp && GET_CODE (temp) == CONST_INT)
7243 force_to_mode (XEXP (x, 0), GET_MODE (x),
7244 INTVAL (temp), next_select));
7249 /* If we just want the low-order bit, the NEG isn't needed since it
7250 won't change the low-order bit. */
7252 return force_to_mode (XEXP (x, 0), mode, mask, just_select);
7254 /* We need any bits less significant than the most significant bit in
7255 MASK since carries from those bits will affect the bits we are
7261 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7262 same as the XOR case above. Ensure that the constant we form is not
7263 wider than the mode of X. */
7265 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7266 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7267 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7268 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7269 < GET_MODE_BITSIZE (GET_MODE (x)))
7270 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7272 temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
7274 temp = simplify_gen_binary (XOR, GET_MODE (x),
7275 XEXP (XEXP (x, 0), 0), temp);
7276 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7277 temp, XEXP (XEXP (x, 0), 1));
7279 return force_to_mode (x, mode, mask, next_select);
7282 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7283 use the full mask inside the NOT. */
7287 op0 = gen_lowpart_or_truncate (op_mode,
7288 force_to_mode (XEXP (x, 0), mode, mask,
7290 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7291 x = simplify_gen_unary (code, op_mode, op0, op_mode);
7295 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7296 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7297 which is equal to STORE_FLAG_VALUE. */
7298 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7299 && GET_MODE (XEXP (x, 0)) == mode
7300 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7301 && (nonzero_bits (XEXP (x, 0), mode)
7302 == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
7303 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7308 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7309 written in a narrower mode. We play it safe and do not do so. */
7312 gen_lowpart_or_truncate (GET_MODE (x),
7313 force_to_mode (XEXP (x, 1), mode,
7314 mask, next_select)));
7316 gen_lowpart_or_truncate (GET_MODE (x),
7317 force_to_mode (XEXP (x, 2), mode,
7318 mask, next_select)));
7325 /* Ensure we return a value of the proper mode. */
7326 return gen_lowpart_or_truncate (mode, x);
7329 /* Return nonzero if X is an expression that has one of two values depending on
7330 whether some other value is zero or nonzero. In that case, we return the
7331 value that is being tested, *PTRUE is set to the value if the rtx being
7332 returned has a nonzero value, and *PFALSE is set to the other alternative.
7334 If we return zero, we set *PTRUE and *PFALSE to X. */
7337 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
7339 enum machine_mode mode = GET_MODE (x);
7340 enum rtx_code code = GET_CODE (x);
7341 rtx cond0, cond1, true0, true1, false0, false1;
7342 unsigned HOST_WIDE_INT nz;
7344 /* If we are comparing a value against zero, we are done. */
7345 if ((code == NE || code == EQ)
7346 && XEXP (x, 1) == const0_rtx)
7348 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7349 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7353 /* If this is a unary operation whose operand has one of two values, apply
7354 our opcode to compute those values. */
7355 else if (UNARY_P (x)
7356 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7358 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
7359 *pfalse = simplify_gen_unary (code, mode, false0,
7360 GET_MODE (XEXP (x, 0)));
7364 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7365 make can't possibly match and would suppress other optimizations. */
7366 else if (code == COMPARE)
7369 /* If this is a binary operation, see if either side has only one of two
7370 values. If either one does or if both do and they are conditional on
7371 the same value, compute the new true and false values. */
7372 else if (BINARY_P (x))
7374 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7375 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7377 if ((cond0 != 0 || cond1 != 0)
7378 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7380 /* If if_then_else_cond returned zero, then true/false are the
7381 same rtl. We must copy one of them to prevent invalid rtl
7384 true0 = copy_rtx (true0);
7385 else if (cond1 == 0)
7386 true1 = copy_rtx (true1);
7388 if (COMPARISON_P (x))
7390 *ptrue = simplify_gen_relational (code, mode, VOIDmode,
7392 *pfalse = simplify_gen_relational (code, mode, VOIDmode,
7397 *ptrue = simplify_gen_binary (code, mode, true0, true1);
7398 *pfalse = simplify_gen_binary (code, mode, false0, false1);
7401 return cond0 ? cond0 : cond1;
7404 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7405 operands is zero when the other is nonzero, and vice-versa,
7406 and STORE_FLAG_VALUE is 1 or -1. */
7408 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7409 && (code == PLUS || code == IOR || code == XOR || code == MINUS
7411 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7413 rtx op0 = XEXP (XEXP (x, 0), 1);
7414 rtx op1 = XEXP (XEXP (x, 1), 1);
7416 cond0 = XEXP (XEXP (x, 0), 0);
7417 cond1 = XEXP (XEXP (x, 1), 0);
7419 if (COMPARISON_P (cond0)
7420 && COMPARISON_P (cond1)
7421 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
7422 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7423 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7424 || ((swap_condition (GET_CODE (cond0))
7425 == reversed_comparison_code (cond1, NULL))
7426 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7427 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7428 && ! side_effects_p (x))
7430 *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
7431 *pfalse = simplify_gen_binary (MULT, mode,
7433 ? simplify_gen_unary (NEG, mode,
7441 /* Similarly for MULT, AND and UMIN, except that for these the result
7443 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7444 && (code == MULT || code == AND || code == UMIN)
7445 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7447 cond0 = XEXP (XEXP (x, 0), 0);
7448 cond1 = XEXP (XEXP (x, 1), 0);
7450 if (COMPARISON_P (cond0)
7451 && COMPARISON_P (cond1)
7452 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
7453 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7454 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7455 || ((swap_condition (GET_CODE (cond0))
7456 == reversed_comparison_code (cond1, NULL))
7457 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7458 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7459 && ! side_effects_p (x))
7461 *ptrue = *pfalse = const0_rtx;
7467 else if (code == IF_THEN_ELSE)
7469 /* If we have IF_THEN_ELSE already, extract the condition and
7470 canonicalize it if it is NE or EQ. */
7471 cond0 = XEXP (x, 0);
7472 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7473 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7474 return XEXP (cond0, 0);
7475 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7477 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7478 return XEXP (cond0, 0);
7484 /* If X is a SUBREG, we can narrow both the true and false values
7485 if the inner expression, if there is a condition. */
7486 else if (code == SUBREG
7487 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7490 true0 = simplify_gen_subreg (mode, true0,
7491 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7492 false0 = simplify_gen_subreg (mode, false0,
7493 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7494 if (true0 && false0)
7502 /* If X is a constant, this isn't special and will cause confusions
7503 if we treat it as such. Likewise if it is equivalent to a constant. */
7504 else if (CONSTANT_P (x)
7505 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7508 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7509 will be least confusing to the rest of the compiler. */
7510 else if (mode == BImode)
7512 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
7516 /* If X is known to be either 0 or -1, those are the true and
7517 false values when testing X. */
7518 else if (x == constm1_rtx || x == const0_rtx
7519 || (mode != VOIDmode
7520 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
7522 *ptrue = constm1_rtx, *pfalse = const0_rtx;
7526 /* Likewise for 0 or a single bit. */
7527 else if (SCALAR_INT_MODE_P (mode)
7528 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7529 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7531 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
7535 /* Otherwise fail; show no condition with true and false values the same. */
7536 *ptrue = *pfalse = x;
7540 /* Return the value of expression X given the fact that condition COND
7541 is known to be true when applied to REG as its first operand and VAL
7542 as its second. X is known to not be shared and so can be modified in
7545 We only handle the simplest cases, and specifically those cases that
7546 arise with IF_THEN_ELSE expressions. */
7549 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
7551 enum rtx_code code = GET_CODE (x);
7556 if (side_effects_p (x))
7559 /* If either operand of the condition is a floating point value,
7560 then we have to avoid collapsing an EQ comparison. */
7562 && rtx_equal_p (x, reg)
7563 && ! FLOAT_MODE_P (GET_MODE (x))
7564 && ! FLOAT_MODE_P (GET_MODE (val)))
7567 if (cond == UNEQ && rtx_equal_p (x, reg))
7570 /* If X is (abs REG) and we know something about REG's relationship
7571 with zero, we may be able to simplify this. */
7573 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
7576 case GE: case GT: case EQ:
7579 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
7581 GET_MODE (XEXP (x, 0)));
7586 /* The only other cases we handle are MIN, MAX, and comparisons if the
7587 operands are the same as REG and VAL. */
7589 else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
7591 if (rtx_equal_p (XEXP (x, 0), val))
7592 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
7594 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
7596 if (COMPARISON_P (x))
7598 if (comparison_dominates_p (cond, code))
7599 return const_true_rtx;
7601 code = reversed_comparison_code (x, NULL);
7603 && comparison_dominates_p (cond, code))
7608 else if (code == SMAX || code == SMIN
7609 || code == UMIN || code == UMAX)
7611 int unsignedp = (code == UMIN || code == UMAX);
7613 /* Do not reverse the condition when it is NE or EQ.
7614 This is because we cannot conclude anything about
7615 the value of 'SMAX (x, y)' when x is not equal to y,
7616 but we can when x equals y. */
7617 if ((code == SMAX || code == UMAX)
7618 && ! (cond == EQ || cond == NE))
7619 cond = reverse_condition (cond);
7624 return unsignedp ? x : XEXP (x, 1);
7626 return unsignedp ? x : XEXP (x, 0);
7628 return unsignedp ? XEXP (x, 1) : x;
7630 return unsignedp ? XEXP (x, 0) : x;
7637 else if (code == SUBREG)
7639 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
7640 rtx new, r = known_cond (SUBREG_REG (x), cond, reg, val);
7642 if (SUBREG_REG (x) != r)
7644 /* We must simplify subreg here, before we lose track of the
7645 original inner_mode. */
7646 new = simplify_subreg (GET_MODE (x), r,
7647 inner_mode, SUBREG_BYTE (x));
7651 SUBST (SUBREG_REG (x), r);
7656 /* We don't have to handle SIGN_EXTEND here, because even in the
7657 case of replacing something with a modeless CONST_INT, a
7658 CONST_INT is already (supposed to be) a valid sign extension for
7659 its narrower mode, which implies it's already properly
7660 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
7661 story is different. */
7662 else if (code == ZERO_EXTEND)
7664 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
7665 rtx new, r = known_cond (XEXP (x, 0), cond, reg, val);
7667 if (XEXP (x, 0) != r)
7669 /* We must simplify the zero_extend here, before we lose
7670 track of the original inner_mode. */
7671 new = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
7676 SUBST (XEXP (x, 0), r);
7682 fmt = GET_RTX_FORMAT (code);
7683 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7686 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7687 else if (fmt[i] == 'E')
7688 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7689 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7696 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7697 assignment as a field assignment. */
7700 rtx_equal_for_field_assignment_p (rtx x, rtx y)
7702 if (x == y || rtx_equal_p (x, y))
7705 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7708 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7709 Note that all SUBREGs of MEM are paradoxical; otherwise they
7710 would have been rewritten. */
7711 if (MEM_P (x) && GET_CODE (y) == SUBREG
7712 && MEM_P (SUBREG_REG (y))
7713 && rtx_equal_p (SUBREG_REG (y),
7714 gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
7717 if (MEM_P (y) && GET_CODE (x) == SUBREG
7718 && MEM_P (SUBREG_REG (x))
7719 && rtx_equal_p (SUBREG_REG (x),
7720 gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
7723 /* We used to see if get_last_value of X and Y were the same but that's
7724 not correct. In one direction, we'll cause the assignment to have
7725 the wrong destination and in the case, we'll import a register into this
7726 insn that might have already have been dead. So fail if none of the
7727 above cases are true. */
7731 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7732 Return that assignment if so.
7734 We only handle the most common cases. */
7737 make_field_assignment (rtx x)
7739 rtx dest = SET_DEST (x);
7740 rtx src = SET_SRC (x);
7745 unsigned HOST_WIDE_INT len;
7747 enum machine_mode mode;
7749 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7750 a clear of a one-bit field. We will have changed it to
7751 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7754 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7755 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7756 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7757 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7759 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7762 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7766 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7767 && subreg_lowpart_p (XEXP (src, 0))
7768 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7769 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7770 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7771 && GET_CODE (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == CONST_INT
7772 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7773 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7775 assign = make_extraction (VOIDmode, dest, 0,
7776 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7779 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7783 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7785 if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7786 && XEXP (XEXP (src, 0), 0) == const1_rtx
7787 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7789 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7792 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
7796 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
7797 SRC is an AND with all bits of that field set, then we can discard
7799 if (GET_CODE (dest) == ZERO_EXTRACT
7800 && GET_CODE (XEXP (dest, 1)) == CONST_INT
7801 && GET_CODE (src) == AND
7802 && GET_CODE (XEXP (src, 1)) == CONST_INT)
7804 HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
7805 unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
7806 unsigned HOST_WIDE_INT ze_mask;
7808 if (width >= HOST_BITS_PER_WIDE_INT)
7811 ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
7813 /* Complete overlap. We can remove the source AND. */
7814 if ((and_mask & ze_mask) == ze_mask)
7815 return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
7817 /* Partial overlap. We can reduce the source AND. */
7818 if ((and_mask & ze_mask) != and_mask)
7820 mode = GET_MODE (src);
7821 src = gen_rtx_AND (mode, XEXP (src, 0),
7822 gen_int_mode (and_mask & ze_mask, mode));
7823 return gen_rtx_SET (VOIDmode, dest, src);
7827 /* The other case we handle is assignments into a constant-position
7828 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7829 a mask that has all one bits except for a group of zero bits and
7830 OTHER is known to have zeros where C1 has ones, this is such an
7831 assignment. Compute the position and length from C1. Shift OTHER
7832 to the appropriate position, force it to the required mode, and
7833 make the extraction. Check for the AND in both operands. */
7835 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
7838 rhs = expand_compound_operation (XEXP (src, 0));
7839 lhs = expand_compound_operation (XEXP (src, 1));
7841 if (GET_CODE (rhs) == AND
7842 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7843 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7844 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7845 else if (GET_CODE (lhs) == AND
7846 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7847 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7848 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
7852 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
7853 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
7854 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7855 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
7858 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
7862 /* The mode to use for the source is the mode of the assignment, or of
7863 what is inside a possible STRICT_LOW_PART. */
7864 mode = (GET_CODE (assign) == STRICT_LOW_PART
7865 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
7867 /* Shift OTHER right POS places and make it the source, restricting it
7868 to the proper length and mode. */
7870 src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
7874 src = force_to_mode (src, mode,
7875 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7876 ? ~(unsigned HOST_WIDE_INT) 0
7877 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7880 /* If SRC is masked by an AND that does not make a difference in
7881 the value being stored, strip it. */
7882 if (GET_CODE (assign) == ZERO_EXTRACT
7883 && GET_CODE (XEXP (assign, 1)) == CONST_INT
7884 && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
7885 && GET_CODE (src) == AND
7886 && GET_CODE (XEXP (src, 1)) == CONST_INT
7887 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (src, 1))
7888 == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1))
7889 src = XEXP (src, 0);
7891 return gen_rtx_SET (VOIDmode, assign, src);
7894 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7898 apply_distributive_law (rtx x)
7900 enum rtx_code code = GET_CODE (x);
7901 enum rtx_code inner_code;
7902 rtx lhs, rhs, other;
7905 /* Distributivity is not true for floating point as it can change the
7906 value. So we don't do it unless -funsafe-math-optimizations. */
7907 if (FLOAT_MODE_P (GET_MODE (x))
7908 && ! flag_unsafe_math_optimizations)
7911 /* The outer operation can only be one of the following: */
7912 if (code != IOR && code != AND && code != XOR
7913 && code != PLUS && code != MINUS)
7919 /* If either operand is a primitive we can't do anything, so get out
7921 if (OBJECT_P (lhs) || OBJECT_P (rhs))
7924 lhs = expand_compound_operation (lhs);
7925 rhs = expand_compound_operation (rhs);
7926 inner_code = GET_CODE (lhs);
7927 if (inner_code != GET_CODE (rhs))
7930 /* See if the inner and outer operations distribute. */
7937 /* These all distribute except over PLUS. */
7938 if (code == PLUS || code == MINUS)
7943 if (code != PLUS && code != MINUS)
7948 /* This is also a multiply, so it distributes over everything. */
7952 /* Non-paradoxical SUBREGs distributes over all operations,
7953 provided the inner modes and byte offsets are the same, this
7954 is an extraction of a low-order part, we don't convert an fp
7955 operation to int or vice versa, this is not a vector mode,
7956 and we would not be converting a single-word operation into a
7957 multi-word operation. The latter test is not required, but
7958 it prevents generating unneeded multi-word operations. Some
7959 of the previous tests are redundant given the latter test,
7960 but are retained because they are required for correctness.
7962 We produce the result slightly differently in this case. */
7964 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7965 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
7966 || ! subreg_lowpart_p (lhs)
7967 || (GET_MODE_CLASS (GET_MODE (lhs))
7968 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
7969 || (GET_MODE_SIZE (GET_MODE (lhs))
7970 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
7971 || VECTOR_MODE_P (GET_MODE (lhs))
7972 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD
7973 /* Result might need to be truncated. Don't change mode if
7974 explicit truncation is needed. */
7975 || !TRULY_NOOP_TRUNCATION
7976 (GET_MODE_BITSIZE (GET_MODE (x)),
7977 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (lhs)))))
7980 tem = simplify_gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
7981 SUBREG_REG (lhs), SUBREG_REG (rhs));
7982 return gen_lowpart (GET_MODE (x), tem);
7988 /* Set LHS and RHS to the inner operands (A and B in the example
7989 above) and set OTHER to the common operand (C in the example).
7990 There is only one way to do this unless the inner operation is
7992 if (COMMUTATIVE_ARITH_P (lhs)
7993 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
7994 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
7995 else if (COMMUTATIVE_ARITH_P (lhs)
7996 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
7997 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
7998 else if (COMMUTATIVE_ARITH_P (lhs)
7999 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
8000 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
8001 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
8002 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
8006 /* Form the new inner operation, seeing if it simplifies first. */
8007 tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
8009 /* There is one exception to the general way of distributing:
8010 (a | c) ^ (b | c) -> (a ^ b) & ~c */
8011 if (code == XOR && inner_code == IOR)
8014 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
8017 /* We may be able to continuing distributing the result, so call
8018 ourselves recursively on the inner operation before forming the
8019 outer operation, which we return. */
8020 return simplify_gen_binary (inner_code, GET_MODE (x),
8021 apply_distributive_law (tem), other);
8024 /* See if X is of the form (* (+ A B) C), and if so convert to
8025 (+ (* A C) (* B C)) and try to simplify.
8027 Most of the time, this results in no change. However, if some of
8028 the operands are the same or inverses of each other, simplifications
8031 For example, (and (ior A B) (not B)) can occur as the result of
8032 expanding a bit field assignment. When we apply the distributive
8033 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
8034 which then simplifies to (and (A (not B))).
8036 Note that no checks happen on the validity of applying the inverse
8037 distributive law. This is pointless since we can do it in the
8038 few places where this routine is called.
8040 N is the index of the term that is decomposed (the arithmetic operation,
8041 i.e. (+ A B) in the first example above). !N is the index of the term that
8042 is distributed, i.e. of C in the first example above. */
8044 distribute_and_simplify_rtx (rtx x, int n)
8046 enum machine_mode mode;
8047 enum rtx_code outer_code, inner_code;
8048 rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
8050 decomposed = XEXP (x, n);
8051 if (!ARITHMETIC_P (decomposed))
8054 mode = GET_MODE (x);
8055 outer_code = GET_CODE (x);
8056 distributed = XEXP (x, !n);
8058 inner_code = GET_CODE (decomposed);
8059 inner_op0 = XEXP (decomposed, 0);
8060 inner_op1 = XEXP (decomposed, 1);
8062 /* Special case (and (xor B C) (not A)), which is equivalent to
8063 (xor (ior A B) (ior A C)) */
8064 if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
8066 distributed = XEXP (distributed, 0);
8072 /* Distribute the second term. */
8073 new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
8074 new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
8078 /* Distribute the first term. */
8079 new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
8080 new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
8083 tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
8085 if (GET_CODE (tmp) != outer_code
8086 && rtx_cost (tmp, SET) < rtx_cost (x, SET))
8092 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
8093 in MODE. Return an equivalent form, if different from (and VAROP
8094 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
8097 simplify_and_const_int_1 (enum machine_mode mode, rtx varop,
8098 unsigned HOST_WIDE_INT constop)
8100 unsigned HOST_WIDE_INT nonzero;
8101 unsigned HOST_WIDE_INT orig_constop;
8106 orig_constop = constop;
8107 if (GET_CODE (varop) == CLOBBER)
8110 /* Simplify VAROP knowing that we will be only looking at some of the
8113 Note by passing in CONSTOP, we guarantee that the bits not set in
8114 CONSTOP are not significant and will never be examined. We must
8115 ensure that is the case by explicitly masking out those bits
8116 before returning. */
8117 varop = force_to_mode (varop, mode, constop, 0);
8119 /* If VAROP is a CLOBBER, we will fail so return it. */
8120 if (GET_CODE (varop) == CLOBBER)
8123 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
8124 to VAROP and return the new constant. */
8125 if (GET_CODE (varop) == CONST_INT)
8126 return gen_int_mode (INTVAL (varop) & constop, mode);
8128 /* See what bits may be nonzero in VAROP. Unlike the general case of
8129 a call to nonzero_bits, here we don't care about bits outside
8132 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
8134 /* Turn off all bits in the constant that are known to already be zero.
8135 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8136 which is tested below. */
8140 /* If we don't have any bits left, return zero. */
8144 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8145 a power of two, we can replace this with an ASHIFT. */
8146 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
8147 && (i = exact_log2 (constop)) >= 0)
8148 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
8150 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8151 or XOR, then try to apply the distributive law. This may eliminate
8152 operations if either branch can be simplified because of the AND.
8153 It may also make some cases more complex, but those cases probably
8154 won't match a pattern either with or without this. */
8156 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
8160 apply_distributive_law
8161 (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
8162 simplify_and_const_int (NULL_RTX,
8166 simplify_and_const_int (NULL_RTX,
8171 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
8172 the AND and see if one of the operands simplifies to zero. If so, we
8173 may eliminate it. */
8175 if (GET_CODE (varop) == PLUS
8176 && exact_log2 (constop + 1) >= 0)
8180 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
8181 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
8182 if (o0 == const0_rtx)
8184 if (o1 == const0_rtx)
8188 /* Make a SUBREG if necessary. If we can't make it, fail. */
8189 varop = gen_lowpart (mode, varop);
8190 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
8193 /* If we are only masking insignificant bits, return VAROP. */
8194 if (constop == nonzero)
8197 if (varop == orig_varop && constop == orig_constop)
8200 /* Otherwise, return an AND. */
8201 return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode));
8205 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
8208 Return an equivalent form, if different from X. Otherwise, return X. If
8209 X is zero, we are to always construct the equivalent form. */
8212 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
8213 unsigned HOST_WIDE_INT constop)
8215 rtx tem = simplify_and_const_int_1 (mode, varop, constop);
8220 x = simplify_gen_binary (AND, GET_MODE (varop), varop,
8221 gen_int_mode (constop, mode));
8222 if (GET_MODE (x) != mode)
8223 x = gen_lowpart (mode, x);
8227 /* Given a REG, X, compute which bits in X can be nonzero.
8228 We don't care about bits outside of those defined in MODE.
8230 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8231 a shift, AND, or zero_extract, we can do better. */
8234 reg_nonzero_bits_for_combine (rtx x, enum machine_mode mode,
8235 rtx known_x ATTRIBUTE_UNUSED,
8236 enum machine_mode known_mode ATTRIBUTE_UNUSED,
8237 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
8238 unsigned HOST_WIDE_INT *nonzero)
8242 /* If X is a register whose nonzero bits value is current, use it.
8243 Otherwise, if X is a register whose value we can find, use that
8244 value. Otherwise, use the previously-computed global nonzero bits
8245 for this register. */
8247 if (reg_stat[REGNO (x)].last_set_value != 0
8248 && (reg_stat[REGNO (x)].last_set_mode == mode
8249 || (GET_MODE_CLASS (reg_stat[REGNO (x)].last_set_mode) == MODE_INT
8250 && GET_MODE_CLASS (mode) == MODE_INT))
8251 && (reg_stat[REGNO (x)].last_set_label == label_tick
8252 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8253 && REG_N_SETS (REGNO (x)) == 1
8254 && ! REGNO_REG_SET_P
8255 (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
8257 && INSN_CUID (reg_stat[REGNO (x)].last_set) < subst_low_cuid)
8259 *nonzero &= reg_stat[REGNO (x)].last_set_nonzero_bits;
8263 tem = get_last_value (x);
8267 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8268 /* If X is narrower than MODE and TEM is a non-negative
8269 constant that would appear negative in the mode of X,
8270 sign-extend it for use in reg_nonzero_bits because some
8271 machines (maybe most) will actually do the sign-extension
8272 and this is the conservative approach.
8274 ??? For 2.5, try to tighten up the MD files in this regard
8275 instead of this kludge. */
8277 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode)
8278 && GET_CODE (tem) == CONST_INT
8280 && 0 != (INTVAL (tem)
8281 & ((HOST_WIDE_INT) 1
8282 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8283 tem = GEN_INT (INTVAL (tem)
8284 | ((HOST_WIDE_INT) (-1)
8285 << GET_MODE_BITSIZE (GET_MODE (x))));
8289 else if (nonzero_sign_valid && reg_stat[REGNO (x)].nonzero_bits)
8291 unsigned HOST_WIDE_INT mask = reg_stat[REGNO (x)].nonzero_bits;
8293 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode))
8294 /* We don't know anything about the upper bits. */
8295 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
8302 /* Return the number of bits at the high-order end of X that are known to
8303 be equal to the sign bit. X will be used in mode MODE; if MODE is
8304 VOIDmode, X will be used in its own mode. The returned value will always
8305 be between 1 and the number of bits in MODE. */
8308 reg_num_sign_bit_copies_for_combine (rtx x, enum machine_mode mode,
8309 rtx known_x ATTRIBUTE_UNUSED,
8310 enum machine_mode known_mode
8312 unsigned int known_ret ATTRIBUTE_UNUSED,
8313 unsigned int *result)
8317 if (reg_stat[REGNO (x)].last_set_value != 0
8318 && reg_stat[REGNO (x)].last_set_mode == mode
8319 && (reg_stat[REGNO (x)].last_set_label == label_tick
8320 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8321 && REG_N_SETS (REGNO (x)) == 1
8322 && ! REGNO_REG_SET_P
8323 (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
8325 && INSN_CUID (reg_stat[REGNO (x)].last_set) < subst_low_cuid)
8327 *result = reg_stat[REGNO (x)].last_set_sign_bit_copies;
8331 tem = get_last_value (x);
8335 if (nonzero_sign_valid && reg_stat[REGNO (x)].sign_bit_copies != 0
8336 && GET_MODE_BITSIZE (GET_MODE (x)) == GET_MODE_BITSIZE (mode))
8337 *result = reg_stat[REGNO (x)].sign_bit_copies;
8342 /* Return the number of "extended" bits there are in X, when interpreted
8343 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8344 unsigned quantities, this is the number of high-order zero bits.
8345 For signed quantities, this is the number of copies of the sign bit
8346 minus 1. In both case, this function returns the number of "spare"
8347 bits. For example, if two quantities for which this function returns
8348 at least 1 are added, the addition is known not to overflow.
8350 This function will always return 0 unless called during combine, which
8351 implies that it must be called from a define_split. */
8354 extended_count (rtx x, enum machine_mode mode, int unsignedp)
8356 if (nonzero_sign_valid == 0)
8360 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8361 ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
8362 - floor_log2 (nonzero_bits (x, mode)))
8364 : num_sign_bit_copies (x, mode) - 1);
8367 /* This function is called from `simplify_shift_const' to merge two
8368 outer operations. Specifically, we have already found that we need
8369 to perform operation *POP0 with constant *PCONST0 at the outermost
8370 position. We would now like to also perform OP1 with constant CONST1
8371 (with *POP0 being done last).
8373 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8374 the resulting operation. *PCOMP_P is set to 1 if we would need to
8375 complement the innermost operand, otherwise it is unchanged.
8377 MODE is the mode in which the operation will be done. No bits outside
8378 the width of this mode matter. It is assumed that the width of this mode
8379 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8381 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
8382 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8383 result is simply *PCONST0.
8385 If the resulting operation cannot be expressed as one operation, we
8386 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8389 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
8391 enum rtx_code op0 = *pop0;
8392 HOST_WIDE_INT const0 = *pconst0;
8394 const0 &= GET_MODE_MASK (mode);
8395 const1 &= GET_MODE_MASK (mode);
8397 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8401 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
8404 if (op1 == UNKNOWN || op0 == SET)
8407 else if (op0 == UNKNOWN)
8408 op0 = op1, const0 = const1;
8410 else if (op0 == op1)
8434 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8435 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8438 /* If the two constants aren't the same, we can't do anything. The
8439 remaining six cases can all be done. */
8440 else if (const0 != const1)
8448 /* (a & b) | b == b */
8450 else /* op1 == XOR */
8451 /* (a ^ b) | b == a | b */
8457 /* (a & b) ^ b == (~a) & b */
8458 op0 = AND, *pcomp_p = 1;
8459 else /* op1 == IOR */
8460 /* (a | b) ^ b == a & ~b */
8461 op0 = AND, const0 = ~const0;
8466 /* (a | b) & b == b */
8468 else /* op1 == XOR */
8469 /* (a ^ b) & b) == (~a) & b */
8476 /* Check for NO-OP cases. */
8477 const0 &= GET_MODE_MASK (mode);
8479 && (op0 == IOR || op0 == XOR || op0 == PLUS))
8481 else if (const0 == 0 && op0 == AND)
8483 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8487 /* ??? Slightly redundant with the above mask, but not entirely.
8488 Moving this above means we'd have to sign-extend the mode mask
8489 for the final test. */
8490 const0 = trunc_int_for_mode (const0, mode);
8498 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8499 The result of the shift is RESULT_MODE. Return NULL_RTX if we cannot
8500 simplify it. Otherwise, return a simplified value.
8502 The shift is normally computed in the widest mode we find in VAROP, as
8503 long as it isn't a different number of words than RESULT_MODE. Exceptions
8504 are ASHIFTRT and ROTATE, which are always done in their original mode. */
8507 simplify_shift_const_1 (enum rtx_code code, enum machine_mode result_mode,
8508 rtx varop, int orig_count)
8510 enum rtx_code orig_code = code;
8511 rtx orig_varop = varop;
8513 enum machine_mode mode = result_mode;
8514 enum machine_mode shift_mode, tmode;
8515 unsigned int mode_words
8516 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8517 /* We form (outer_op (code varop count) (outer_const)). */
8518 enum rtx_code outer_op = UNKNOWN;
8519 HOST_WIDE_INT outer_const = 0;
8520 int complement_p = 0;
8523 /* Make sure and truncate the "natural" shift on the way in. We don't
8524 want to do this inside the loop as it makes it more difficult to
8526 if (SHIFT_COUNT_TRUNCATED)
8527 orig_count &= GET_MODE_BITSIZE (mode) - 1;
8529 /* If we were given an invalid count, don't do anything except exactly
8530 what was requested. */
8532 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
8537 /* Unless one of the branches of the `if' in this loop does a `continue',
8538 we will `break' the loop after the `if'. */
8542 /* If we have an operand of (clobber (const_int 0)), fail. */
8543 if (GET_CODE (varop) == CLOBBER)
8546 /* If we discovered we had to complement VAROP, leave. Making a NOT
8547 here would cause an infinite loop. */
8551 /* Convert ROTATERT to ROTATE. */
8552 if (code == ROTATERT)
8554 unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
8556 if (VECTOR_MODE_P (result_mode))
8557 count = bitsize / GET_MODE_NUNITS (result_mode) - count;
8559 count = bitsize - count;
8562 /* We need to determine what mode we will do the shift in. If the
8563 shift is a right shift or a ROTATE, we must always do it in the mode
8564 it was originally done in. Otherwise, we can do it in MODE, the
8565 widest mode encountered. */
8567 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8568 ? result_mode : mode);
8570 /* Handle cases where the count is greater than the size of the mode
8571 minus 1. For ASHIFT, use the size minus one as the count (this can
8572 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
8573 take the count modulo the size. For other shifts, the result is
8576 Since these shifts are being produced by the compiler by combining
8577 multiple operations, each of which are defined, we know what the
8578 result is supposed to be. */
8580 if (count > (GET_MODE_BITSIZE (shift_mode) - 1))
8582 if (code == ASHIFTRT)
8583 count = GET_MODE_BITSIZE (shift_mode) - 1;
8584 else if (code == ROTATE || code == ROTATERT)
8585 count %= GET_MODE_BITSIZE (shift_mode);
8588 /* We can't simply return zero because there may be an
8596 /* An arithmetic right shift of a quantity known to be -1 or 0
8598 if (code == ASHIFTRT
8599 && (num_sign_bit_copies (varop, shift_mode)
8600 == GET_MODE_BITSIZE (shift_mode)))
8606 /* If we are doing an arithmetic right shift and discarding all but
8607 the sign bit copies, this is equivalent to doing a shift by the
8608 bitsize minus one. Convert it into that shift because it will often
8609 allow other simplifications. */
8611 if (code == ASHIFTRT
8612 && (count + num_sign_bit_copies (varop, shift_mode)
8613 >= GET_MODE_BITSIZE (shift_mode)))
8614 count = GET_MODE_BITSIZE (shift_mode) - 1;
8616 /* We simplify the tests below and elsewhere by converting
8617 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8618 `make_compound_operation' will convert it to an ASHIFTRT for
8619 those machines (such as VAX) that don't have an LSHIFTRT. */
8620 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8622 && ((nonzero_bits (varop, shift_mode)
8623 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
8627 if (code == LSHIFTRT
8628 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8629 && !(nonzero_bits (varop, shift_mode) >> count))
8632 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8633 && !((nonzero_bits (varop, shift_mode) << count)
8634 & GET_MODE_MASK (shift_mode)))
8637 switch (GET_CODE (varop))
8643 new = expand_compound_operation (varop);
8652 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8653 minus the width of a smaller mode, we can do this with a
8654 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
8655 if ((code == ASHIFTRT || code == LSHIFTRT)
8656 && ! mode_dependent_address_p (XEXP (varop, 0))
8657 && ! MEM_VOLATILE_P (varop)
8658 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8659 MODE_INT, 1)) != BLKmode)
8661 new = adjust_address_nv (varop, tmode,
8662 BYTES_BIG_ENDIAN ? 0
8663 : count / BITS_PER_UNIT);
8665 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
8666 : ZERO_EXTEND, mode, new);
8673 /* If VAROP is a SUBREG, strip it as long as the inner operand has
8674 the same number of words as what we've seen so far. Then store
8675 the widest mode in MODE. */
8676 if (subreg_lowpart_p (varop)
8677 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8678 > GET_MODE_SIZE (GET_MODE (varop)))
8679 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8680 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
8683 varop = SUBREG_REG (varop);
8684 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
8685 mode = GET_MODE (varop);
8691 /* Some machines use MULT instead of ASHIFT because MULT
8692 is cheaper. But it is still better on those machines to
8693 merge two shifts into one. */
8694 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8695 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8698 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
8700 GEN_INT (exact_log2 (
8701 INTVAL (XEXP (varop, 1)))));
8707 /* Similar, for when divides are cheaper. */
8708 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8709 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8712 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
8714 GEN_INT (exact_log2 (
8715 INTVAL (XEXP (varop, 1)))));
8721 /* If we are extracting just the sign bit of an arithmetic
8722 right shift, that shift is not needed. However, the sign
8723 bit of a wider mode may be different from what would be
8724 interpreted as the sign bit in a narrower mode, so, if
8725 the result is narrower, don't discard the shift. */
8726 if (code == LSHIFTRT
8727 && count == (GET_MODE_BITSIZE (result_mode) - 1)
8728 && (GET_MODE_BITSIZE (result_mode)
8729 >= GET_MODE_BITSIZE (GET_MODE (varop))))
8731 varop = XEXP (varop, 0);
8735 /* ... fall through ... */
8740 /* Here we have two nested shifts. The result is usually the
8741 AND of a new shift with a mask. We compute the result below. */
8742 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8743 && INTVAL (XEXP (varop, 1)) >= 0
8744 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
8745 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8746 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8747 && !VECTOR_MODE_P (result_mode))
8749 enum rtx_code first_code = GET_CODE (varop);
8750 unsigned int first_count = INTVAL (XEXP (varop, 1));
8751 unsigned HOST_WIDE_INT mask;
8754 /* We have one common special case. We can't do any merging if
8755 the inner code is an ASHIFTRT of a smaller mode. However, if
8756 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
8757 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
8758 we can convert it to
8759 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
8760 This simplifies certain SIGN_EXTEND operations. */
8761 if (code == ASHIFT && first_code == ASHIFTRT
8762 && count == (GET_MODE_BITSIZE (result_mode)
8763 - GET_MODE_BITSIZE (GET_MODE (varop))))
8765 /* C3 has the low-order C1 bits zero. */
8767 mask = (GET_MODE_MASK (mode)
8768 & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
8770 varop = simplify_and_const_int (NULL_RTX, result_mode,
8771 XEXP (varop, 0), mask);
8772 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
8774 count = first_count;
8779 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
8780 than C1 high-order bits equal to the sign bit, we can convert
8781 this to either an ASHIFT or an ASHIFTRT depending on the
8784 We cannot do this if VAROP's mode is not SHIFT_MODE. */
8786 if (code == ASHIFTRT && first_code == ASHIFT
8787 && GET_MODE (varop) == shift_mode
8788 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
8791 varop = XEXP (varop, 0);
8792 count -= first_count;
8802 /* There are some cases we can't do. If CODE is ASHIFTRT,
8803 we can only do this if FIRST_CODE is also ASHIFTRT.
8805 We can't do the case when CODE is ROTATE and FIRST_CODE is
8808 If the mode of this shift is not the mode of the outer shift,
8809 we can't do this if either shift is a right shift or ROTATE.
8811 Finally, we can't do any of these if the mode is too wide
8812 unless the codes are the same.
8814 Handle the case where the shift codes are the same
8817 if (code == first_code)
8819 if (GET_MODE (varop) != result_mode
8820 && (code == ASHIFTRT || code == LSHIFTRT
8824 count += first_count;
8825 varop = XEXP (varop, 0);
8829 if (code == ASHIFTRT
8830 || (code == ROTATE && first_code == ASHIFTRT)
8831 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
8832 || (GET_MODE (varop) != result_mode
8833 && (first_code == ASHIFTRT || first_code == LSHIFTRT
8834 || first_code == ROTATE
8835 || code == ROTATE)))
8838 /* To compute the mask to apply after the shift, shift the
8839 nonzero bits of the inner shift the same way the
8840 outer shift will. */
8842 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
8845 = simplify_const_binary_operation (code, result_mode, mask_rtx,
8848 /* Give up if we can't compute an outer operation to use. */
8850 || GET_CODE (mask_rtx) != CONST_INT
8851 || ! merge_outer_ops (&outer_op, &outer_const, AND,
8853 result_mode, &complement_p))
8856 /* If the shifts are in the same direction, we add the
8857 counts. Otherwise, we subtract them. */
8858 if ((code == ASHIFTRT || code == LSHIFTRT)
8859 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
8860 count += first_count;
8862 count -= first_count;
8864 /* If COUNT is positive, the new shift is usually CODE,
8865 except for the two exceptions below, in which case it is
8866 FIRST_CODE. If the count is negative, FIRST_CODE should
8869 && ((first_code == ROTATE && code == ASHIFT)
8870 || (first_code == ASHIFTRT && code == LSHIFTRT)))
8873 code = first_code, count = -count;
8875 varop = XEXP (varop, 0);
8879 /* If we have (A << B << C) for any shift, we can convert this to
8880 (A << C << B). This wins if A is a constant. Only try this if
8881 B is not a constant. */
8883 else if (GET_CODE (varop) == code
8884 && GET_CODE (XEXP (varop, 0)) == CONST_INT
8885 && GET_CODE (XEXP (varop, 1)) != CONST_INT)
8887 rtx new = simplify_const_binary_operation (code, mode,
8890 varop = gen_rtx_fmt_ee (code, mode, new, XEXP (varop, 1));
8897 /* Make this fit the case below. */
8898 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
8899 GEN_INT (GET_MODE_MASK (mode)));
8905 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
8906 with C the size of VAROP - 1 and the shift is logical if
8907 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8908 we have an (le X 0) operation. If we have an arithmetic shift
8909 and STORE_FLAG_VALUE is 1 or we have a logical shift with
8910 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
8912 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
8913 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
8914 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8915 && (code == LSHIFTRT || code == ASHIFTRT)
8916 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
8917 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8920 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
8923 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8924 varop = gen_rtx_NEG (GET_MODE (varop), varop);
8929 /* If we have (shift (logical)), move the logical to the outside
8930 to allow it to possibly combine with another logical and the
8931 shift to combine with another shift. This also canonicalizes to
8932 what a ZERO_EXTRACT looks like. Also, some machines have
8933 (and (shift)) insns. */
8935 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8936 /* We can't do this if we have (ashiftrt (xor)) and the
8937 constant has its sign bit set in shift_mode. */
8938 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
8939 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
8941 && (new = simplify_const_binary_operation (code, result_mode,
8943 GEN_INT (count))) != 0
8944 && GET_CODE (new) == CONST_INT
8945 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
8946 INTVAL (new), result_mode, &complement_p))
8948 varop = XEXP (varop, 0);
8952 /* If we can't do that, try to simplify the shift in each arm of the
8953 logical expression, make a new logical expression, and apply
8954 the inverse distributive law. This also can't be done
8955 for some (ashiftrt (xor)). */
8956 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8957 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
8958 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
8961 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8962 XEXP (varop, 0), count);
8963 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8964 XEXP (varop, 1), count);
8966 varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
8968 varop = apply_distributive_law (varop);
8976 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
8977 says that the sign bit can be tested, FOO has mode MODE, C is
8978 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
8979 that may be nonzero. */
8980 if (code == LSHIFTRT
8981 && XEXP (varop, 1) == const0_rtx
8982 && GET_MODE (XEXP (varop, 0)) == result_mode
8983 && count == (GET_MODE_BITSIZE (result_mode) - 1)
8984 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8985 && STORE_FLAG_VALUE == -1
8986 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
8987 && merge_outer_ops (&outer_op, &outer_const, XOR,
8988 (HOST_WIDE_INT) 1, result_mode,
8991 varop = XEXP (varop, 0);
8998 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
8999 than the number of bits in the mode is equivalent to A. */
9000 if (code == LSHIFTRT
9001 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9002 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9004 varop = XEXP (varop, 0);
9009 /* NEG commutes with ASHIFT since it is multiplication. Move the
9010 NEG outside to allow shifts to combine. */
9012 && merge_outer_ops (&outer_op, &outer_const, NEG,
9013 (HOST_WIDE_INT) 0, result_mode,
9016 varop = XEXP (varop, 0);
9022 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9023 is one less than the number of bits in the mode is
9024 equivalent to (xor A 1). */
9025 if (code == LSHIFTRT
9026 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9027 && XEXP (varop, 1) == constm1_rtx
9028 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9029 && merge_outer_ops (&outer_op, &outer_const, XOR,
9030 (HOST_WIDE_INT) 1, result_mode,
9034 varop = XEXP (varop, 0);
9038 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9039 that might be nonzero in BAR are those being shifted out and those
9040 bits are known zero in FOO, we can replace the PLUS with FOO.
9041 Similarly in the other operand order. This code occurs when
9042 we are computing the size of a variable-size array. */
9044 if ((code == ASHIFTRT || code == LSHIFTRT)
9045 && count < HOST_BITS_PER_WIDE_INT
9046 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9047 && (nonzero_bits (XEXP (varop, 1), result_mode)
9048 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9050 varop = XEXP (varop, 0);
9053 else if ((code == ASHIFTRT || code == LSHIFTRT)
9054 && count < HOST_BITS_PER_WIDE_INT
9055 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9056 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9058 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9059 & nonzero_bits (XEXP (varop, 1),
9062 varop = XEXP (varop, 1);
9066 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9068 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9069 && (new = simplify_const_binary_operation (ASHIFT, result_mode,
9071 GEN_INT (count))) != 0
9072 && GET_CODE (new) == CONST_INT
9073 && merge_outer_ops (&outer_op, &outer_const, PLUS,
9074 INTVAL (new), result_mode, &complement_p))
9076 varop = XEXP (varop, 0);
9080 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
9081 signbit', and attempt to change the PLUS to an XOR and move it to
9082 the outer operation as is done above in the AND/IOR/XOR case
9083 leg for shift(logical). See details in logical handling above
9084 for reasoning in doing so. */
9085 if (code == LSHIFTRT
9086 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9087 && mode_signbit_p (result_mode, XEXP (varop, 1))
9088 && (new = simplify_const_binary_operation (code, result_mode,
9090 GEN_INT (count))) != 0
9091 && GET_CODE (new) == CONST_INT
9092 && merge_outer_ops (&outer_op, &outer_const, XOR,
9093 INTVAL (new), result_mode, &complement_p))
9095 varop = XEXP (varop, 0);
9102 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9103 with C the size of VAROP - 1 and the shift is logical if
9104 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9105 we have a (gt X 0) operation. If the shift is arithmetic with
9106 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9107 we have a (neg (gt X 0)) operation. */
9109 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9110 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9111 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9112 && (code == LSHIFTRT || code == ASHIFTRT)
9113 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9114 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
9115 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9118 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9121 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9122 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9129 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9130 if the truncate does not affect the value. */
9131 if (code == LSHIFTRT
9132 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9133 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9134 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9135 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9136 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9138 rtx varop_inner = XEXP (varop, 0);
9141 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9142 XEXP (varop_inner, 0),
9144 (count + INTVAL (XEXP (varop_inner, 1))));
9145 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9158 /* We need to determine what mode to do the shift in. If the shift is
9159 a right shift or ROTATE, we must always do it in the mode it was
9160 originally done in. Otherwise, we can do it in MODE, the widest mode
9161 encountered. The code we care about is that of the shift that will
9162 actually be done, not the shift that was originally requested. */
9164 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9165 ? result_mode : mode);
9167 /* We have now finished analyzing the shift. The result should be
9168 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9169 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
9170 to the result of the shift. OUTER_CONST is the relevant constant,
9171 but we must turn off all bits turned off in the shift. */
9173 if (outer_op == UNKNOWN
9174 && orig_code == code && orig_count == count
9175 && varop == orig_varop
9176 && shift_mode == GET_MODE (varop))
9179 /* Make a SUBREG if necessary. If we can't make it, fail. */
9180 varop = gen_lowpart (shift_mode, varop);
9181 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
9184 /* If we have an outer operation and we just made a shift, it is
9185 possible that we could have simplified the shift were it not
9186 for the outer operation. So try to do the simplification
9189 if (outer_op != UNKNOWN)
9190 x = simplify_shift_const_1 (code, shift_mode, varop, count);
9195 x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count));
9197 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9198 turn off all the bits that the shift would have turned off. */
9199 if (orig_code == LSHIFTRT && result_mode != shift_mode)
9200 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9201 GET_MODE_MASK (result_mode) >> orig_count);
9203 /* Do the remainder of the processing in RESULT_MODE. */
9204 x = gen_lowpart_or_truncate (result_mode, x);
9206 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9209 x = simplify_gen_unary (NOT, result_mode, x, result_mode);
9211 if (outer_op != UNKNOWN)
9213 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9214 outer_const = trunc_int_for_mode (outer_const, result_mode);
9216 if (outer_op == AND)
9217 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9218 else if (outer_op == SET)
9219 /* This means that we have determined that the result is
9220 equivalent to a constant. This should be rare. */
9221 x = GEN_INT (outer_const);
9222 else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
9223 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
9225 x = simplify_gen_binary (outer_op, result_mode, x,
9226 GEN_INT (outer_const));
9232 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9233 The result of the shift is RESULT_MODE. If we cannot simplify it,
9234 return X or, if it is NULL, synthesize the expression with
9235 simplify_gen_binary. Otherwise, return a simplified value.
9237 The shift is normally computed in the widest mode we find in VAROP, as
9238 long as it isn't a different number of words than RESULT_MODE. Exceptions
9239 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9242 simplify_shift_const (rtx x, enum rtx_code code, enum machine_mode result_mode,
9243 rtx varop, int count)
9245 rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
9250 x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count));
9251 if (GET_MODE (x) != result_mode)
9252 x = gen_lowpart (result_mode, x);
9257 /* Like recog, but we receive the address of a pointer to a new pattern.
9258 We try to match the rtx that the pointer points to.
9259 If that fails, we may try to modify or replace the pattern,
9260 storing the replacement into the same pointer object.
9262 Modifications include deletion or addition of CLOBBERs.
9264 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9265 the CLOBBERs are placed.
9267 The value is the final insn code from the pattern ultimately matched,
9271 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
9274 int insn_code_number;
9275 int num_clobbers_to_add = 0;
9278 rtx old_notes, old_pat;
9280 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9281 we use to indicate that something didn't match. If we find such a
9282 thing, force rejection. */
9283 if (GET_CODE (pat) == PARALLEL)
9284 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9285 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9286 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9289 old_pat = PATTERN (insn);
9290 old_notes = REG_NOTES (insn);
9291 PATTERN (insn) = pat;
9292 REG_NOTES (insn) = 0;
9294 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9296 /* If it isn't, there is the possibility that we previously had an insn
9297 that clobbered some register as a side effect, but the combined
9298 insn doesn't need to do that. So try once more without the clobbers
9299 unless this represents an ASM insn. */
9301 if (insn_code_number < 0 && ! check_asm_operands (pat)
9302 && GET_CODE (pat) == PARALLEL)
9306 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9307 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9310 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9314 SUBST_INT (XVECLEN (pat, 0), pos);
9317 pat = XVECEXP (pat, 0, 0);
9319 PATTERN (insn) = pat;
9320 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9322 PATTERN (insn) = old_pat;
9323 REG_NOTES (insn) = old_notes;
9325 /* Recognize all noop sets, these will be killed by followup pass. */
9326 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
9327 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
9329 /* If we had any clobbers to add, make a new pattern than contains
9330 them. Then check to make sure that all of them are dead. */
9331 if (num_clobbers_to_add)
9333 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9334 rtvec_alloc (GET_CODE (pat) == PARALLEL
9336 + num_clobbers_to_add)
9337 : num_clobbers_to_add + 1));
9339 if (GET_CODE (pat) == PARALLEL)
9340 for (i = 0; i < XVECLEN (pat, 0); i++)
9341 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9343 XVECEXP (newpat, 0, 0) = pat;
9345 add_clobbers (newpat, insn_code_number);
9347 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9348 i < XVECLEN (newpat, 0); i++)
9350 if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
9351 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9353 notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9354 XEXP (XVECEXP (newpat, 0, i), 0), notes);
9362 return insn_code_number;
9365 /* Like gen_lowpart_general but for use by combine. In combine it
9366 is not possible to create any new pseudoregs. However, it is
9367 safe to create invalid memory addresses, because combine will
9368 try to recognize them and all they will do is make the combine
9371 If for some reason this cannot do its job, an rtx
9372 (clobber (const_int 0)) is returned.
9373 An insn containing that will not be recognized. */
9376 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
9378 enum machine_mode imode = GET_MODE (x);
9379 unsigned int osize = GET_MODE_SIZE (omode);
9380 unsigned int isize = GET_MODE_SIZE (imode);
9386 /* Return identity if this is a CONST or symbolic reference. */
9388 && (GET_CODE (x) == CONST
9389 || GET_CODE (x) == SYMBOL_REF
9390 || GET_CODE (x) == LABEL_REF))
9393 /* We can only support MODE being wider than a word if X is a
9394 constant integer or has a mode the same size. */
9395 if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
9396 && ! ((imode == VOIDmode
9397 && (GET_CODE (x) == CONST_INT
9398 || GET_CODE (x) == CONST_DOUBLE))
9402 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9403 won't know what to do. So we will strip off the SUBREG here and
9404 process normally. */
9405 if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
9409 /* For use in case we fall down into the address adjustments
9410 further below, we need to adjust the known mode and size of
9411 x; imode and isize, since we just adjusted x. */
9412 imode = GET_MODE (x);
9417 isize = GET_MODE_SIZE (imode);
9420 result = gen_lowpart_common (omode, x);
9422 #ifdef CANNOT_CHANGE_MODE_CLASS
9423 if (result != 0 && GET_CODE (result) == SUBREG)
9424 record_subregs_of_mode (result);
9434 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9436 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9439 /* If we want to refer to something bigger than the original memref,
9440 generate a paradoxical subreg instead. That will force a reload
9441 of the original memref X. */
9443 return gen_rtx_SUBREG (omode, x, 0);
9445 if (WORDS_BIG_ENDIAN)
9446 offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
9448 /* Adjust the address so that the address-after-the-data is
9450 if (BYTES_BIG_ENDIAN)
9451 offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
9453 return adjust_address_nv (x, omode, offset);
9456 /* If X is a comparison operator, rewrite it in a new mode. This
9457 probably won't match, but may allow further simplifications. */
9458 else if (COMPARISON_P (x))
9459 return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
9461 /* If we couldn't simplify X any other way, just enclose it in a
9462 SUBREG. Normally, this SUBREG won't match, but some patterns may
9463 include an explicit SUBREG or we may simplify it further in combine. */
9469 offset = subreg_lowpart_offset (omode, imode);
9470 if (imode == VOIDmode)
9472 imode = int_mode_for_mode (omode);
9473 x = gen_lowpart_common (imode, x);
9477 res = simplify_gen_subreg (omode, x, imode, offset);
9483 return gen_rtx_CLOBBER (imode, const0_rtx);
9486 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9487 comparison code that will be tested.
9489 The result is a possibly different comparison code to use. *POP0 and
9490 *POP1 may be updated.
9492 It is possible that we might detect that a comparison is either always
9493 true or always false. However, we do not perform general constant
9494 folding in combine, so this knowledge isn't useful. Such tautologies
9495 should have been detected earlier. Hence we ignore all such cases. */
9497 static enum rtx_code
9498 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
9504 enum machine_mode mode, tmode;
9506 /* Try a few ways of applying the same transformation to both operands. */
9509 #ifndef WORD_REGISTER_OPERATIONS
9510 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9511 so check specially. */
9512 if (code != GTU && code != GEU && code != LTU && code != LEU
9513 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9514 && GET_CODE (XEXP (op0, 0)) == ASHIFT
9515 && GET_CODE (XEXP (op1, 0)) == ASHIFT
9516 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9517 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9518 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
9519 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
9520 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9521 && XEXP (op0, 1) == XEXP (op1, 1)
9522 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
9523 && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
9524 && (INTVAL (XEXP (op0, 1))
9525 == (GET_MODE_BITSIZE (GET_MODE (op0))
9527 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
9529 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
9530 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
9534 /* If both operands are the same constant shift, see if we can ignore the
9535 shift. We can if the shift is a rotate or if the bits shifted out of
9536 this shift are known to be zero for both inputs and if the type of
9537 comparison is compatible with the shift. */
9538 if (GET_CODE (op0) == GET_CODE (op1)
9539 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9540 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
9541 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
9542 && (code != GT && code != LT && code != GE && code != LE))
9543 || (GET_CODE (op0) == ASHIFTRT
9544 && (code != GTU && code != LTU
9545 && code != GEU && code != LEU)))
9546 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9547 && INTVAL (XEXP (op0, 1)) >= 0
9548 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9549 && XEXP (op0, 1) == XEXP (op1, 1))
9551 enum machine_mode mode = GET_MODE (op0);
9552 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9553 int shift_count = INTVAL (XEXP (op0, 1));
9555 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
9556 mask &= (mask >> shift_count) << shift_count;
9557 else if (GET_CODE (op0) == ASHIFT)
9558 mask = (mask & (mask << shift_count)) >> shift_count;
9560 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
9561 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
9562 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
9567 /* If both operands are AND's of a paradoxical SUBREG by constant, the
9568 SUBREGs are of the same mode, and, in both cases, the AND would
9569 be redundant if the comparison was done in the narrower mode,
9570 do the comparison in the narrower mode (e.g., we are AND'ing with 1
9571 and the operand's possibly nonzero bits are 0xffffff01; in that case
9572 if we only care about QImode, we don't need the AND). This case
9573 occurs if the output mode of an scc insn is not SImode and
9574 STORE_FLAG_VALUE == 1 (e.g., the 386).
9576 Similarly, check for a case where the AND's are ZERO_EXTEND
9577 operations from some narrower mode even though a SUBREG is not
9580 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
9581 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9582 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
9584 rtx inner_op0 = XEXP (op0, 0);
9585 rtx inner_op1 = XEXP (op1, 0);
9586 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
9587 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
9590 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
9591 && (GET_MODE_SIZE (GET_MODE (inner_op0))
9592 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
9593 && (GET_MODE (SUBREG_REG (inner_op0))
9594 == GET_MODE (SUBREG_REG (inner_op1)))
9595 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
9596 <= HOST_BITS_PER_WIDE_INT)
9597 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
9598 GET_MODE (SUBREG_REG (inner_op0)))))
9599 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
9600 GET_MODE (SUBREG_REG (inner_op1))))))
9602 op0 = SUBREG_REG (inner_op0);
9603 op1 = SUBREG_REG (inner_op1);
9605 /* The resulting comparison is always unsigned since we masked
9606 off the original sign bit. */
9607 code = unsigned_condition (code);
9613 for (tmode = GET_CLASS_NARROWEST_MODE
9614 (GET_MODE_CLASS (GET_MODE (op0)));
9615 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
9616 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
9618 op0 = gen_lowpart (tmode, inner_op0);
9619 op1 = gen_lowpart (tmode, inner_op1);
9620 code = unsigned_condition (code);
9629 /* If both operands are NOT, we can strip off the outer operation
9630 and adjust the comparison code for swapped operands; similarly for
9631 NEG, except that this must be an equality comparison. */
9632 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
9633 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
9634 && (code == EQ || code == NE)))
9635 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
9641 /* If the first operand is a constant, swap the operands and adjust the
9642 comparison code appropriately, but don't do this if the second operand
9643 is already a constant integer. */
9644 if (swap_commutative_operands_p (op0, op1))
9646 tem = op0, op0 = op1, op1 = tem;
9647 code = swap_condition (code);
9650 /* We now enter a loop during which we will try to simplify the comparison.
9651 For the most part, we only are concerned with comparisons with zero,
9652 but some things may really be comparisons with zero but not start
9653 out looking that way. */
9655 while (GET_CODE (op1) == CONST_INT)
9657 enum machine_mode mode = GET_MODE (op0);
9658 unsigned int mode_width = GET_MODE_BITSIZE (mode);
9659 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9660 int equality_comparison_p;
9661 int sign_bit_comparison_p;
9662 int unsigned_comparison_p;
9663 HOST_WIDE_INT const_op;
9665 /* We only want to handle integral modes. This catches VOIDmode,
9666 CCmode, and the floating-point modes. An exception is that we
9667 can handle VOIDmode if OP0 is a COMPARE or a comparison
9670 if (GET_MODE_CLASS (mode) != MODE_INT
9671 && ! (mode == VOIDmode
9672 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
9675 /* Get the constant we are comparing against and turn off all bits
9676 not on in our mode. */
9677 const_op = INTVAL (op1);
9678 if (mode != VOIDmode)
9679 const_op = trunc_int_for_mode (const_op, mode);
9680 op1 = GEN_INT (const_op);
9682 /* If we are comparing against a constant power of two and the value
9683 being compared can only have that single bit nonzero (e.g., it was
9684 `and'ed with that bit), we can replace this with a comparison
9687 && (code == EQ || code == NE || code == GE || code == GEU
9688 || code == LT || code == LTU)
9689 && mode_width <= HOST_BITS_PER_WIDE_INT
9690 && exact_log2 (const_op) >= 0
9691 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
9693 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
9694 op1 = const0_rtx, const_op = 0;
9697 /* Similarly, if we are comparing a value known to be either -1 or
9698 0 with -1, change it to the opposite comparison against zero. */
9701 && (code == EQ || code == NE || code == GT || code == LE
9702 || code == GEU || code == LTU)
9703 && num_sign_bit_copies (op0, mode) == mode_width)
9705 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
9706 op1 = const0_rtx, const_op = 0;
9709 /* Do some canonicalizations based on the comparison code. We prefer
9710 comparisons against zero and then prefer equality comparisons.
9711 If we can reduce the size of a constant, we will do that too. */
9716 /* < C is equivalent to <= (C - 1) */
9720 op1 = GEN_INT (const_op);
9722 /* ... fall through to LE case below. */
9728 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
9732 op1 = GEN_INT (const_op);
9736 /* If we are doing a <= 0 comparison on a value known to have
9737 a zero sign bit, we can replace this with == 0. */
9738 else if (const_op == 0
9739 && mode_width <= HOST_BITS_PER_WIDE_INT
9740 && (nonzero_bits (op0, mode)
9741 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9746 /* >= C is equivalent to > (C - 1). */
9750 op1 = GEN_INT (const_op);
9752 /* ... fall through to GT below. */
9758 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
9762 op1 = GEN_INT (const_op);
9766 /* If we are doing a > 0 comparison on a value known to have
9767 a zero sign bit, we can replace this with != 0. */
9768 else if (const_op == 0
9769 && mode_width <= HOST_BITS_PER_WIDE_INT
9770 && (nonzero_bits (op0, mode)
9771 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9776 /* < C is equivalent to <= (C - 1). */
9780 op1 = GEN_INT (const_op);
9782 /* ... fall through ... */
9785 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
9786 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9787 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9789 const_op = 0, op1 = const0_rtx;
9797 /* unsigned <= 0 is equivalent to == 0 */
9801 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
9802 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9803 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9805 const_op = 0, op1 = const0_rtx;
9811 /* >= C is equivalent to > (C - 1). */
9815 op1 = GEN_INT (const_op);
9817 /* ... fall through ... */
9820 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
9821 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9822 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9824 const_op = 0, op1 = const0_rtx;
9832 /* unsigned > 0 is equivalent to != 0 */
9836 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
9837 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9838 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9840 const_op = 0, op1 = const0_rtx;
9849 /* Compute some predicates to simplify code below. */
9851 equality_comparison_p = (code == EQ || code == NE);
9852 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
9853 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
9856 /* If this is a sign bit comparison and we can do arithmetic in
9857 MODE, say that we will only be needing the sign bit of OP0. */
9858 if (sign_bit_comparison_p
9859 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9860 op0 = force_to_mode (op0, mode,
9862 << (GET_MODE_BITSIZE (mode) - 1)),
9865 /* Now try cases based on the opcode of OP0. If none of the cases
9866 does a "continue", we exit this loop immediately after the
9869 switch (GET_CODE (op0))
9872 /* If we are extracting a single bit from a variable position in
9873 a constant that has only a single bit set and are comparing it
9874 with zero, we can convert this into an equality comparison
9875 between the position and the location of the single bit. */
9876 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
9877 have already reduced the shift count modulo the word size. */
9878 if (!SHIFT_COUNT_TRUNCATED
9879 && GET_CODE (XEXP (op0, 0)) == CONST_INT
9880 && XEXP (op0, 1) == const1_rtx
9881 && equality_comparison_p && const_op == 0
9882 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
9884 if (BITS_BIG_ENDIAN)
9886 enum machine_mode new_mode
9887 = mode_for_extraction (EP_extzv, 1);
9888 if (new_mode == MAX_MACHINE_MODE)
9889 i = BITS_PER_WORD - 1 - i;
9893 i = (GET_MODE_BITSIZE (mode) - 1 - i);
9897 op0 = XEXP (op0, 2);
9901 /* Result is nonzero iff shift count is equal to I. */
9902 code = reverse_condition (code);
9906 /* ... fall through ... */
9909 tem = expand_compound_operation (op0);
9918 /* If testing for equality, we can take the NOT of the constant. */
9919 if (equality_comparison_p
9920 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
9922 op0 = XEXP (op0, 0);
9927 /* If just looking at the sign bit, reverse the sense of the
9929 if (sign_bit_comparison_p)
9931 op0 = XEXP (op0, 0);
9932 code = (code == GE ? LT : GE);
9938 /* If testing for equality, we can take the NEG of the constant. */
9939 if (equality_comparison_p
9940 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
9942 op0 = XEXP (op0, 0);
9947 /* The remaining cases only apply to comparisons with zero. */
9951 /* When X is ABS or is known positive,
9952 (neg X) is < 0 if and only if X != 0. */
9954 if (sign_bit_comparison_p
9955 && (GET_CODE (XEXP (op0, 0)) == ABS
9956 || (mode_width <= HOST_BITS_PER_WIDE_INT
9957 && (nonzero_bits (XEXP (op0, 0), mode)
9958 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
9960 op0 = XEXP (op0, 0);
9961 code = (code == LT ? NE : EQ);
9965 /* If we have NEG of something whose two high-order bits are the
9966 same, we know that "(-a) < 0" is equivalent to "a > 0". */
9967 if (num_sign_bit_copies (op0, mode) >= 2)
9969 op0 = XEXP (op0, 0);
9970 code = swap_condition (code);
9976 /* If we are testing equality and our count is a constant, we
9977 can perform the inverse operation on our RHS. */
9978 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
9979 && (tem = simplify_binary_operation (ROTATERT, mode,
9980 op1, XEXP (op0, 1))) != 0)
9982 op0 = XEXP (op0, 0);
9987 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
9988 a particular bit. Convert it to an AND of a constant of that
9989 bit. This will be converted into a ZERO_EXTRACT. */
9990 if (const_op == 0 && sign_bit_comparison_p
9991 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9992 && mode_width <= HOST_BITS_PER_WIDE_INT)
9994 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
9997 - INTVAL (XEXP (op0, 1)))));
9998 code = (code == LT ? NE : EQ);
10002 /* Fall through. */
10005 /* ABS is ignorable inside an equality comparison with zero. */
10006 if (const_op == 0 && equality_comparison_p)
10008 op0 = XEXP (op0, 0);
10014 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
10015 (compare FOO CONST) if CONST fits in FOO's mode and we
10016 are either testing inequality or have an unsigned
10017 comparison with ZERO_EXTEND or a signed comparison with
10018 SIGN_EXTEND. But don't do it if we don't have a compare
10019 insn of the given mode, since we'd have to revert it
10020 later on, and then we wouldn't know whether to sign- or
10022 mode = GET_MODE (XEXP (op0, 0));
10023 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10024 && ! unsigned_comparison_p
10025 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10026 && ((unsigned HOST_WIDE_INT) const_op
10027 < (((unsigned HOST_WIDE_INT) 1
10028 << (GET_MODE_BITSIZE (mode) - 1))))
10029 && cmp_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
10031 op0 = XEXP (op0, 0);
10037 /* Check for the case where we are comparing A - C1 with C2, that is
10039 (subreg:MODE (plus (A) (-C1))) op (C2)
10041 with C1 a constant, and try to lift the SUBREG, i.e. to do the
10042 comparison in the wider mode. One of the following two conditions
10043 must be true in order for this to be valid:
10045 1. The mode extension results in the same bit pattern being added
10046 on both sides and the comparison is equality or unsigned. As
10047 C2 has been truncated to fit in MODE, the pattern can only be
10050 2. The mode extension results in the sign bit being copied on
10053 The difficulty here is that we have predicates for A but not for
10054 (A - C1) so we need to check that C1 is within proper bounds so
10055 as to perturbate A as little as possible. */
10057 if (mode_width <= HOST_BITS_PER_WIDE_INT
10058 && subreg_lowpart_p (op0)
10059 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) > mode_width
10060 && GET_CODE (SUBREG_REG (op0)) == PLUS
10061 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT)
10063 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
10064 rtx a = XEXP (SUBREG_REG (op0), 0);
10065 HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
10068 && (unsigned HOST_WIDE_INT) c1
10069 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
10070 && (equality_comparison_p || unsigned_comparison_p)
10071 /* (A - C1) zero-extends if it is positive and sign-extends
10072 if it is negative, C2 both zero- and sign-extends. */
10073 && ((0 == (nonzero_bits (a, inner_mode)
10074 & ~GET_MODE_MASK (mode))
10076 /* (A - C1) sign-extends if it is positive and 1-extends
10077 if it is negative, C2 both sign- and 1-extends. */
10078 || (num_sign_bit_copies (a, inner_mode)
10079 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10082 || ((unsigned HOST_WIDE_INT) c1
10083 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
10084 /* (A - C1) always sign-extends, like C2. */
10085 && num_sign_bit_copies (a, inner_mode)
10086 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10087 - (mode_width - 1))))
10089 op0 = SUBREG_REG (op0);
10094 /* If the inner mode is narrower and we are extracting the low part,
10095 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10096 if (subreg_lowpart_p (op0)
10097 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10098 /* Fall through */ ;
10102 /* ... fall through ... */
10105 mode = GET_MODE (XEXP (op0, 0));
10106 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10107 && (unsigned_comparison_p || equality_comparison_p)
10108 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10109 && ((unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode))
10110 && cmp_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
10112 op0 = XEXP (op0, 0);
10118 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10119 this for equality comparisons due to pathological cases involving
10121 if (equality_comparison_p
10122 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10123 op1, XEXP (op0, 1))))
10125 op0 = XEXP (op0, 0);
10130 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10131 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10132 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10134 op0 = XEXP (XEXP (op0, 0), 0);
10135 code = (code == LT ? EQ : NE);
10141 /* We used to optimize signed comparisons against zero, but that
10142 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10143 arrive here as equality comparisons, or (GEU, LTU) are
10144 optimized away. No need to special-case them. */
10146 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10147 (eq B (minus A C)), whichever simplifies. We can only do
10148 this for equality comparisons due to pathological cases involving
10150 if (equality_comparison_p
10151 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10152 XEXP (op0, 1), op1)))
10154 op0 = XEXP (op0, 0);
10159 if (equality_comparison_p
10160 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10161 XEXP (op0, 0), op1)))
10163 op0 = XEXP (op0, 1);
10168 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10169 of bits in X minus 1, is one iff X > 0. */
10170 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10171 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10172 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1))
10174 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10176 op0 = XEXP (op0, 1);
10177 code = (code == GE ? LE : GT);
10183 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10184 if C is zero or B is a constant. */
10185 if (equality_comparison_p
10186 && 0 != (tem = simplify_binary_operation (XOR, mode,
10187 XEXP (op0, 1), op1)))
10189 op0 = XEXP (op0, 0);
10196 case UNEQ: case LTGT:
10197 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
10198 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
10199 case UNORDERED: case ORDERED:
10200 /* We can't do anything if OP0 is a condition code value, rather
10201 than an actual data value. */
10203 || CC0_P (XEXP (op0, 0))
10204 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10207 /* Get the two operands being compared. */
10208 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10209 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10211 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10213 /* Check for the cases where we simply want the result of the
10214 earlier test or the opposite of that result. */
10215 if (code == NE || code == EQ
10216 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10217 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10218 && (STORE_FLAG_VALUE
10219 & (((HOST_WIDE_INT) 1
10220 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10221 && (code == LT || code == GE)))
10223 enum rtx_code new_code;
10224 if (code == LT || code == NE)
10225 new_code = GET_CODE (op0);
10227 new_code = reversed_comparison_code (op0, NULL);
10229 if (new_code != UNKNOWN)
10240 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10242 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10243 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10244 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10246 op0 = XEXP (op0, 1);
10247 code = (code == GE ? GT : LE);
10253 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10254 will be converted to a ZERO_EXTRACT later. */
10255 if (const_op == 0 && equality_comparison_p
10256 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10257 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10259 op0 = simplify_and_const_int
10260 (NULL_RTX, mode, gen_rtx_LSHIFTRT (mode,
10262 XEXP (XEXP (op0, 0), 1)),
10263 (HOST_WIDE_INT) 1);
10267 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10268 zero and X is a comparison and C1 and C2 describe only bits set
10269 in STORE_FLAG_VALUE, we can compare with X. */
10270 if (const_op == 0 && equality_comparison_p
10271 && mode_width <= HOST_BITS_PER_WIDE_INT
10272 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10273 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10274 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10275 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10276 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10278 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10279 << INTVAL (XEXP (XEXP (op0, 0), 1)));
10280 if ((~STORE_FLAG_VALUE & mask) == 0
10281 && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
10282 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10283 && COMPARISON_P (tem))))
10285 op0 = XEXP (XEXP (op0, 0), 0);
10290 /* If we are doing an equality comparison of an AND of a bit equal
10291 to the sign bit, replace this with a LT or GE comparison of
10292 the underlying value. */
10293 if (equality_comparison_p
10295 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10296 && mode_width <= HOST_BITS_PER_WIDE_INT
10297 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10298 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10300 op0 = XEXP (op0, 0);
10301 code = (code == EQ ? GE : LT);
10305 /* If this AND operation is really a ZERO_EXTEND from a narrower
10306 mode, the constant fits within that mode, and this is either an
10307 equality or unsigned comparison, try to do this comparison in
10312 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
10313 -> (ne:DI (reg:SI 4) (const_int 0))
10315 unless TRULY_NOOP_TRUNCATION allows it or the register is
10316 known to hold a value of the required mode the
10317 transformation is invalid. */
10318 if ((equality_comparison_p || unsigned_comparison_p)
10319 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10320 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10321 & GET_MODE_MASK (mode))
10323 && const_op >> i == 0
10324 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode
10325 && (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
10326 GET_MODE_BITSIZE (GET_MODE (op0)))
10327 || (REG_P (XEXP (op0, 0))
10328 && reg_truncated_to_mode (tmode, XEXP (op0, 0)))))
10330 op0 = gen_lowpart (tmode, XEXP (op0, 0));
10334 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
10335 fits in both M1 and M2 and the SUBREG is either paradoxical
10336 or represents the low part, permute the SUBREG and the AND
10338 if (GET_CODE (XEXP (op0, 0)) == SUBREG)
10340 unsigned HOST_WIDE_INT c1;
10341 tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
10342 /* Require an integral mode, to avoid creating something like
10344 if (SCALAR_INT_MODE_P (tmode)
10345 /* It is unsafe to commute the AND into the SUBREG if the
10346 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
10347 not defined. As originally written the upper bits
10348 have a defined value due to the AND operation.
10349 However, if we commute the AND inside the SUBREG then
10350 they no longer have defined values and the meaning of
10351 the code has been changed. */
10353 #ifdef WORD_REGISTER_OPERATIONS
10354 || (mode_width > GET_MODE_BITSIZE (tmode)
10355 && mode_width <= BITS_PER_WORD)
10357 || (mode_width <= GET_MODE_BITSIZE (tmode)
10358 && subreg_lowpart_p (XEXP (op0, 0))))
10359 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10360 && mode_width <= HOST_BITS_PER_WIDE_INT
10361 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
10362 && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
10363 && (c1 & ~GET_MODE_MASK (tmode)) == 0
10365 && c1 != GET_MODE_MASK (tmode))
10367 op0 = simplify_gen_binary (AND, tmode,
10368 SUBREG_REG (XEXP (op0, 0)),
10369 gen_int_mode (c1, tmode));
10370 op0 = gen_lowpart (mode, op0);
10375 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
10376 if (const_op == 0 && equality_comparison_p
10377 && XEXP (op0, 1) == const1_rtx
10378 && GET_CODE (XEXP (op0, 0)) == NOT)
10380 op0 = simplify_and_const_int
10381 (NULL_RTX, mode, XEXP (XEXP (op0, 0), 0), (HOST_WIDE_INT) 1);
10382 code = (code == NE ? EQ : NE);
10386 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10387 (eq (and (lshiftrt X) 1) 0).
10388 Also handle the case where (not X) is expressed using xor. */
10389 if (const_op == 0 && equality_comparison_p
10390 && XEXP (op0, 1) == const1_rtx
10391 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
10393 rtx shift_op = XEXP (XEXP (op0, 0), 0);
10394 rtx shift_count = XEXP (XEXP (op0, 0), 1);
10396 if (GET_CODE (shift_op) == NOT
10397 || (GET_CODE (shift_op) == XOR
10398 && GET_CODE (XEXP (shift_op, 1)) == CONST_INT
10399 && GET_CODE (shift_count) == CONST_INT
10400 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
10401 && (INTVAL (XEXP (shift_op, 1))
10402 == (HOST_WIDE_INT) 1 << INTVAL (shift_count))))
10404 op0 = simplify_and_const_int
10406 gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count),
10407 (HOST_WIDE_INT) 1);
10408 code = (code == NE ? EQ : NE);
10415 /* If we have (compare (ashift FOO N) (const_int C)) and
10416 the high order N bits of FOO (N+1 if an inequality comparison)
10417 are known to be zero, we can do this by comparing FOO with C
10418 shifted right N bits so long as the low-order N bits of C are
10420 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10421 && INTVAL (XEXP (op0, 1)) >= 0
10422 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10423 < HOST_BITS_PER_WIDE_INT)
10425 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10426 && mode_width <= HOST_BITS_PER_WIDE_INT
10427 && (nonzero_bits (XEXP (op0, 0), mode)
10428 & ~(mask >> (INTVAL (XEXP (op0, 1))
10429 + ! equality_comparison_p))) == 0)
10431 /* We must perform a logical shift, not an arithmetic one,
10432 as we want the top N bits of C to be zero. */
10433 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
10435 temp >>= INTVAL (XEXP (op0, 1));
10436 op1 = gen_int_mode (temp, mode);
10437 op0 = XEXP (op0, 0);
10441 /* If we are doing a sign bit comparison, it means we are testing
10442 a particular bit. Convert it to the appropriate AND. */
10443 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10444 && mode_width <= HOST_BITS_PER_WIDE_INT)
10446 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10449 - INTVAL (XEXP (op0, 1)))));
10450 code = (code == LT ? NE : EQ);
10454 /* If this an equality comparison with zero and we are shifting
10455 the low bit to the sign bit, we can convert this to an AND of the
10457 if (const_op == 0 && equality_comparison_p
10458 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10459 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10462 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10463 (HOST_WIDE_INT) 1);
10469 /* If this is an equality comparison with zero, we can do this
10470 as a logical shift, which might be much simpler. */
10471 if (equality_comparison_p && const_op == 0
10472 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10474 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10476 INTVAL (XEXP (op0, 1)));
10480 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10481 do the comparison in a narrower mode. */
10482 if (! unsigned_comparison_p
10483 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10484 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10485 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10486 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10487 MODE_INT, 1)) != BLKmode
10488 && (((unsigned HOST_WIDE_INT) const_op
10489 + (GET_MODE_MASK (tmode) >> 1) + 1)
10490 <= GET_MODE_MASK (tmode)))
10492 op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
10496 /* Likewise if OP0 is a PLUS of a sign extension with a
10497 constant, which is usually represented with the PLUS
10498 between the shifts. */
10499 if (! unsigned_comparison_p
10500 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10501 && GET_CODE (XEXP (op0, 0)) == PLUS
10502 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10503 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
10504 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
10505 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10506 MODE_INT, 1)) != BLKmode
10507 && (((unsigned HOST_WIDE_INT) const_op
10508 + (GET_MODE_MASK (tmode) >> 1) + 1)
10509 <= GET_MODE_MASK (tmode)))
10511 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
10512 rtx add_const = XEXP (XEXP (op0, 0), 1);
10513 rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
10514 add_const, XEXP (op0, 1));
10516 op0 = simplify_gen_binary (PLUS, tmode,
10517 gen_lowpart (tmode, inner),
10522 /* ... fall through ... */
10524 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10525 the low order N bits of FOO are known to be zero, we can do this
10526 by comparing FOO with C shifted left N bits so long as no
10527 overflow occurs. */
10528 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10529 && INTVAL (XEXP (op0, 1)) >= 0
10530 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10531 && mode_width <= HOST_BITS_PER_WIDE_INT
10532 && (nonzero_bits (XEXP (op0, 0), mode)
10533 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
10534 && (((unsigned HOST_WIDE_INT) const_op
10535 + (GET_CODE (op0) != LSHIFTRT
10536 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
10539 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
10541 /* If the shift was logical, then we must make the condition
10543 if (GET_CODE (op0) == LSHIFTRT)
10544 code = unsigned_condition (code);
10546 const_op <<= INTVAL (XEXP (op0, 1));
10547 op1 = GEN_INT (const_op);
10548 op0 = XEXP (op0, 0);
10552 /* If we are using this shift to extract just the sign bit, we
10553 can replace this with an LT or GE comparison. */
10555 && (equality_comparison_p || sign_bit_comparison_p)
10556 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10557 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10560 op0 = XEXP (op0, 0);
10561 code = (code == NE || code == GT ? LT : GE);
10573 /* Now make any compound operations involved in this comparison. Then,
10574 check for an outmost SUBREG on OP0 that is not doing anything or is
10575 paradoxical. The latter transformation must only be performed when
10576 it is known that the "extra" bits will be the same in op0 and op1 or
10577 that they don't matter. There are three cases to consider:
10579 1. SUBREG_REG (op0) is a register. In this case the bits are don't
10580 care bits and we can assume they have any convenient value. So
10581 making the transformation is safe.
10583 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
10584 In this case the upper bits of op0 are undefined. We should not make
10585 the simplification in that case as we do not know the contents of
10588 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
10589 UNKNOWN. In that case we know those bits are zeros or ones. We must
10590 also be sure that they are the same as the upper bits of op1.
10592 We can never remove a SUBREG for a non-equality comparison because
10593 the sign bit is in a different place in the underlying object. */
10595 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
10596 op1 = make_compound_operation (op1, SET);
10598 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10599 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10600 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
10601 && (code == NE || code == EQ))
10603 if (GET_MODE_SIZE (GET_MODE (op0))
10604 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
10606 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
10608 if (REG_P (SUBREG_REG (op0)))
10610 op0 = SUBREG_REG (op0);
10611 op1 = gen_lowpart (GET_MODE (op0), op1);
10614 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10615 <= HOST_BITS_PER_WIDE_INT)
10616 && (nonzero_bits (SUBREG_REG (op0),
10617 GET_MODE (SUBREG_REG (op0)))
10618 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
10620 tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
10622 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
10623 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
10624 op0 = SUBREG_REG (op0), op1 = tem;
10628 /* We now do the opposite procedure: Some machines don't have compare
10629 insns in all modes. If OP0's mode is an integer mode smaller than a
10630 word and we can't do a compare in that mode, see if there is a larger
10631 mode for which we can do the compare. There are a number of cases in
10632 which we can use the wider mode. */
10634 mode = GET_MODE (op0);
10635 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10636 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
10637 && ! have_insn_for (COMPARE, mode))
10638 for (tmode = GET_MODE_WIDER_MODE (mode);
10640 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
10641 tmode = GET_MODE_WIDER_MODE (tmode))
10642 if (have_insn_for (COMPARE, tmode))
10646 /* If the only nonzero bits in OP0 and OP1 are those in the
10647 narrower mode and this is an equality or unsigned comparison,
10648 we can use the wider mode. Similarly for sign-extended
10649 values, in which case it is true for all comparisons. */
10650 zero_extended = ((code == EQ || code == NE
10651 || code == GEU || code == GTU
10652 || code == LEU || code == LTU)
10653 && (nonzero_bits (op0, tmode)
10654 & ~GET_MODE_MASK (mode)) == 0
10655 && ((GET_CODE (op1) == CONST_INT
10656 || (nonzero_bits (op1, tmode)
10657 & ~GET_MODE_MASK (mode)) == 0)));
10660 || ((num_sign_bit_copies (op0, tmode)
10661 > (unsigned int) (GET_MODE_BITSIZE (tmode)
10662 - GET_MODE_BITSIZE (mode)))
10663 && (num_sign_bit_copies (op1, tmode)
10664 > (unsigned int) (GET_MODE_BITSIZE (tmode)
10665 - GET_MODE_BITSIZE (mode)))))
10667 /* If OP0 is an AND and we don't have an AND in MODE either,
10668 make a new AND in the proper mode. */
10669 if (GET_CODE (op0) == AND
10670 && !have_insn_for (AND, mode))
10671 op0 = simplify_gen_binary (AND, tmode,
10672 gen_lowpart (tmode,
10674 gen_lowpart (tmode,
10677 op0 = gen_lowpart (tmode, op0);
10678 if (zero_extended && GET_CODE (op1) == CONST_INT)
10679 op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode));
10680 op1 = gen_lowpart (tmode, op1);
10684 /* If this is a test for negative, we can make an explicit
10685 test of the sign bit. */
10687 if (op1 == const0_rtx && (code == LT || code == GE)
10688 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10690 op0 = simplify_gen_binary (AND, tmode,
10691 gen_lowpart (tmode, op0),
10692 GEN_INT ((HOST_WIDE_INT) 1
10693 << (GET_MODE_BITSIZE (mode)
10695 code = (code == LT) ? NE : EQ;
10700 #ifdef CANONICALIZE_COMPARISON
10701 /* If this machine only supports a subset of valid comparisons, see if we
10702 can convert an unsupported one into a supported one. */
10703 CANONICALIZE_COMPARISON (code, op0, op1);
10712 /* Utility function for record_value_for_reg. Count number of
10717 enum rtx_code code = GET_CODE (x);
10721 if (GET_RTX_CLASS (code) == '2'
10722 || GET_RTX_CLASS (code) == 'c')
10724 rtx x0 = XEXP (x, 0);
10725 rtx x1 = XEXP (x, 1);
10728 return 1 + 2 * count_rtxs (x0);
10730 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
10731 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
10732 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
10733 return 2 + 2 * count_rtxs (x0)
10734 + count_rtxs (x == XEXP (x1, 0)
10735 ? XEXP (x1, 1) : XEXP (x1, 0));
10737 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
10738 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
10739 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
10740 return 2 + 2 * count_rtxs (x1)
10741 + count_rtxs (x == XEXP (x0, 0)
10742 ? XEXP (x0, 1) : XEXP (x0, 0));
10745 fmt = GET_RTX_FORMAT (code);
10746 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10748 ret += count_rtxs (XEXP (x, i));
10753 /* Utility function for following routine. Called when X is part of a value
10754 being stored into last_set_value. Sets last_set_table_tick
10755 for each register mentioned. Similar to mention_regs in cse.c */
10758 update_table_tick (rtx x)
10760 enum rtx_code code = GET_CODE (x);
10761 const char *fmt = GET_RTX_FORMAT (code);
10766 unsigned int regno = REGNO (x);
10767 unsigned int endregno
10768 = regno + (regno < FIRST_PSEUDO_REGISTER
10769 ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
10772 for (r = regno; r < endregno; r++)
10773 reg_stat[r].last_set_table_tick = label_tick;
10778 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10779 /* Note that we can't have an "E" in values stored; see
10780 get_last_value_validate. */
10783 /* Check for identical subexpressions. If x contains
10784 identical subexpression we only have to traverse one of
10786 if (i == 0 && ARITHMETIC_P (x))
10788 /* Note that at this point x1 has already been
10790 rtx x0 = XEXP (x, 0);
10791 rtx x1 = XEXP (x, 1);
10793 /* If x0 and x1 are identical then there is no need to
10798 /* If x0 is identical to a subexpression of x1 then while
10799 processing x1, x0 has already been processed. Thus we
10800 are done with x. */
10801 if (ARITHMETIC_P (x1)
10802 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
10805 /* If x1 is identical to a subexpression of x0 then we
10806 still have to process the rest of x0. */
10807 if (ARITHMETIC_P (x0)
10808 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
10810 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
10815 update_table_tick (XEXP (x, i));
10819 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
10820 are saying that the register is clobbered and we no longer know its
10821 value. If INSN is zero, don't update reg_stat[].last_set; this is
10822 only permitted with VALUE also zero and is used to invalidate the
10826 record_value_for_reg (rtx reg, rtx insn, rtx value)
10828 unsigned int regno = REGNO (reg);
10829 unsigned int endregno
10830 = regno + (regno < FIRST_PSEUDO_REGISTER
10831 ? hard_regno_nregs[regno][GET_MODE (reg)] : 1);
10834 /* If VALUE contains REG and we have a previous value for REG, substitute
10835 the previous value. */
10836 if (value && insn && reg_overlap_mentioned_p (reg, value))
10840 /* Set things up so get_last_value is allowed to see anything set up to
10842 subst_low_cuid = INSN_CUID (insn);
10843 tem = get_last_value (reg);
10845 /* If TEM is simply a binary operation with two CLOBBERs as operands,
10846 it isn't going to be useful and will take a lot of time to process,
10847 so just use the CLOBBER. */
10851 if (ARITHMETIC_P (tem)
10852 && GET_CODE (XEXP (tem, 0)) == CLOBBER
10853 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
10854 tem = XEXP (tem, 0);
10855 else if (count_occurrences (value, reg, 1) >= 2)
10857 /* If there are two or more occurrences of REG in VALUE,
10858 prevent the value from growing too much. */
10859 if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
10860 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
10863 value = replace_rtx (copy_rtx (value), reg, tem);
10867 /* For each register modified, show we don't know its value, that
10868 we don't know about its bitwise content, that its value has been
10869 updated, and that we don't know the location of the death of the
10871 for (i = regno; i < endregno; i++)
10874 reg_stat[i].last_set = insn;
10876 reg_stat[i].last_set_value = 0;
10877 reg_stat[i].last_set_mode = 0;
10878 reg_stat[i].last_set_nonzero_bits = 0;
10879 reg_stat[i].last_set_sign_bit_copies = 0;
10880 reg_stat[i].last_death = 0;
10881 reg_stat[i].truncated_to_mode = 0;
10884 /* Mark registers that are being referenced in this value. */
10886 update_table_tick (value);
10888 /* Now update the status of each register being set.
10889 If someone is using this register in this block, set this register
10890 to invalid since we will get confused between the two lives in this
10891 basic block. This makes using this register always invalid. In cse, we
10892 scan the table to invalidate all entries using this register, but this
10893 is too much work for us. */
10895 for (i = regno; i < endregno; i++)
10897 reg_stat[i].last_set_label = label_tick;
10898 if (!insn || (value && reg_stat[i].last_set_table_tick == label_tick))
10899 reg_stat[i].last_set_invalid = 1;
10901 reg_stat[i].last_set_invalid = 0;
10904 /* The value being assigned might refer to X (like in "x++;"). In that
10905 case, we must replace it with (clobber (const_int 0)) to prevent
10907 if (value && ! get_last_value_validate (&value, insn,
10908 reg_stat[regno].last_set_label, 0))
10910 value = copy_rtx (value);
10911 if (! get_last_value_validate (&value, insn,
10912 reg_stat[regno].last_set_label, 1))
10916 /* For the main register being modified, update the value, the mode, the
10917 nonzero bits, and the number of sign bit copies. */
10919 reg_stat[regno].last_set_value = value;
10923 enum machine_mode mode = GET_MODE (reg);
10924 subst_low_cuid = INSN_CUID (insn);
10925 reg_stat[regno].last_set_mode = mode;
10926 if (GET_MODE_CLASS (mode) == MODE_INT
10927 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10928 mode = nonzero_bits_mode;
10929 reg_stat[regno].last_set_nonzero_bits = nonzero_bits (value, mode);
10930 reg_stat[regno].last_set_sign_bit_copies
10931 = num_sign_bit_copies (value, GET_MODE (reg));
10935 /* Called via note_stores from record_dead_and_set_regs to handle one
10936 SET or CLOBBER in an insn. DATA is the instruction in which the
10937 set is occurring. */
10940 record_dead_and_set_regs_1 (rtx dest, rtx setter, void *data)
10942 rtx record_dead_insn = (rtx) data;
10944 if (GET_CODE (dest) == SUBREG)
10945 dest = SUBREG_REG (dest);
10947 if (!record_dead_insn)
10950 record_value_for_reg (dest, NULL_RTX, NULL_RTX);
10956 /* If we are setting the whole register, we know its value. Otherwise
10957 show that we don't know the value. We can handle SUBREG in
10959 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
10960 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
10961 else if (GET_CODE (setter) == SET
10962 && GET_CODE (SET_DEST (setter)) == SUBREG
10963 && SUBREG_REG (SET_DEST (setter)) == dest
10964 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
10965 && subreg_lowpart_p (SET_DEST (setter)))
10966 record_value_for_reg (dest, record_dead_insn,
10967 gen_lowpart (GET_MODE (dest),
10968 SET_SRC (setter)));
10970 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
10972 else if (MEM_P (dest)
10973 /* Ignore pushes, they clobber nothing. */
10974 && ! push_operand (dest, GET_MODE (dest)))
10975 mem_last_set = INSN_CUID (record_dead_insn);
10978 /* Update the records of when each REG was most recently set or killed
10979 for the things done by INSN. This is the last thing done in processing
10980 INSN in the combiner loop.
10982 We update reg_stat[], in particular fields last_set, last_set_value,
10983 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
10984 last_death, and also the similar information mem_last_set (which insn
10985 most recently modified memory) and last_call_cuid (which insn was the
10986 most recent subroutine call). */
10989 record_dead_and_set_regs (rtx insn)
10994 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
10996 if (REG_NOTE_KIND (link) == REG_DEAD
10997 && REG_P (XEXP (link, 0)))
10999 unsigned int regno = REGNO (XEXP (link, 0));
11000 unsigned int endregno
11001 = regno + (regno < FIRST_PSEUDO_REGISTER
11002 ? hard_regno_nregs[regno][GET_MODE (XEXP (link, 0))]
11005 for (i = regno; i < endregno; i++)
11006 reg_stat[i].last_death = insn;
11008 else if (REG_NOTE_KIND (link) == REG_INC)
11009 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11014 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11015 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
11017 reg_stat[i].last_set_value = 0;
11018 reg_stat[i].last_set_mode = 0;
11019 reg_stat[i].last_set_nonzero_bits = 0;
11020 reg_stat[i].last_set_sign_bit_copies = 0;
11021 reg_stat[i].last_death = 0;
11022 reg_stat[i].truncated_to_mode = 0;
11025 last_call_cuid = mem_last_set = INSN_CUID (insn);
11027 /* We can't combine into a call pattern. Remember, though, that
11028 the return value register is set at this CUID. We could
11029 still replace a register with the return value from the
11030 wrong subroutine call! */
11031 note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX);
11034 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11037 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11038 register present in the SUBREG, so for each such SUBREG go back and
11039 adjust nonzero and sign bit information of the registers that are
11040 known to have some zero/sign bits set.
11042 This is needed because when combine blows the SUBREGs away, the
11043 information on zero/sign bits is lost and further combines can be
11044 missed because of that. */
11047 record_promoted_value (rtx insn, rtx subreg)
11050 unsigned int regno = REGNO (SUBREG_REG (subreg));
11051 enum machine_mode mode = GET_MODE (subreg);
11053 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11056 for (links = LOG_LINKS (insn); links;)
11058 insn = XEXP (links, 0);
11059 set = single_set (insn);
11061 if (! set || !REG_P (SET_DEST (set))
11062 || REGNO (SET_DEST (set)) != regno
11063 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11065 links = XEXP (links, 1);
11069 if (reg_stat[regno].last_set == insn)
11071 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
11072 reg_stat[regno].last_set_nonzero_bits &= GET_MODE_MASK (mode);
11075 if (REG_P (SET_SRC (set)))
11077 regno = REGNO (SET_SRC (set));
11078 links = LOG_LINKS (insn);
11085 /* Check if X, a register, is known to contain a value already
11086 truncated to MODE. In this case we can use a subreg to refer to
11087 the truncated value even though in the generic case we would need
11088 an explicit truncation. */
11091 reg_truncated_to_mode (enum machine_mode mode, rtx x)
11093 enum machine_mode truncated = reg_stat[REGNO (x)].truncated_to_mode;
11095 if (truncated == 0 || reg_stat[REGNO (x)].truncation_label != label_tick)
11097 if (GET_MODE_SIZE (truncated) <= GET_MODE_SIZE (mode))
11099 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
11100 GET_MODE_BITSIZE (truncated)))
11105 /* X is a REG or a SUBREG. If X is some sort of a truncation record
11106 it. For non-TRULY_NOOP_TRUNCATION targets we might be able to turn
11107 a truncate into a subreg using this information. */
11110 record_truncated_value (rtx x)
11112 enum machine_mode truncated_mode;
11114 if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
11116 enum machine_mode original_mode = GET_MODE (SUBREG_REG (x));
11117 truncated_mode = GET_MODE (x);
11119 if (GET_MODE_SIZE (original_mode) <= GET_MODE_SIZE (truncated_mode))
11122 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (truncated_mode),
11123 GET_MODE_BITSIZE (original_mode)))
11126 x = SUBREG_REG (x);
11128 /* ??? For hard-regs we now record everything. We might be able to
11129 optimize this using last_set_mode. */
11130 else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
11131 truncated_mode = GET_MODE (x);
11135 if (reg_stat[REGNO (x)].truncated_to_mode == 0
11136 || reg_stat[REGNO (x)].truncation_label < label_tick
11137 || (GET_MODE_SIZE (truncated_mode)
11138 < GET_MODE_SIZE (reg_stat[REGNO (x)].truncated_to_mode)))
11140 reg_stat[REGNO (x)].truncated_to_mode = truncated_mode;
11141 reg_stat[REGNO (x)].truncation_label = label_tick;
11145 /* Scan X for promoted SUBREGs and truncated REGs. For each one
11146 found, note what it implies to the registers used in it. */
11149 check_conversions (rtx insn, rtx x)
11151 if (GET_CODE (x) == SUBREG || REG_P (x))
11153 if (GET_CODE (x) == SUBREG
11154 && SUBREG_PROMOTED_VAR_P (x)
11155 && REG_P (SUBREG_REG (x)))
11156 record_promoted_value (insn, x);
11158 record_truncated_value (x);
11162 const char *format = GET_RTX_FORMAT (GET_CODE (x));
11165 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11169 check_conversions (insn, XEXP (x, i));
11173 if (XVEC (x, i) != 0)
11174 for (j = 0; j < XVECLEN (x, i); j++)
11175 check_conversions (insn, XVECEXP (x, i, j));
11181 /* Utility routine for the following function. Verify that all the registers
11182 mentioned in *LOC are valid when *LOC was part of a value set when
11183 label_tick == TICK. Return 0 if some are not.
11185 If REPLACE is nonzero, replace the invalid reference with
11186 (clobber (const_int 0)) and return 1. This replacement is useful because
11187 we often can get useful information about the form of a value (e.g., if
11188 it was produced by a shift that always produces -1 or 0) even though
11189 we don't know exactly what registers it was produced from. */
11192 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
11195 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11196 int len = GET_RTX_LENGTH (GET_CODE (x));
11201 unsigned int regno = REGNO (x);
11202 unsigned int endregno
11203 = regno + (regno < FIRST_PSEUDO_REGISTER
11204 ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
11207 for (j = regno; j < endregno; j++)
11208 if (reg_stat[j].last_set_invalid
11209 /* If this is a pseudo-register that was only set once and not
11210 live at the beginning of the function, it is always valid. */
11211 || (! (regno >= FIRST_PSEUDO_REGISTER
11212 && REG_N_SETS (regno) == 1
11213 && (! REGNO_REG_SET_P
11214 (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
11216 && reg_stat[j].last_set_label > tick))
11219 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11225 /* If this is a memory reference, make sure that there were
11226 no stores after it that might have clobbered the value. We don't
11227 have alias info, so we assume any store invalidates it. */
11228 else if (MEM_P (x) && !MEM_READONLY_P (x)
11229 && INSN_CUID (insn) <= mem_last_set)
11232 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11236 for (i = 0; i < len; i++)
11240 /* Check for identical subexpressions. If x contains
11241 identical subexpression we only have to traverse one of
11243 if (i == 1 && ARITHMETIC_P (x))
11245 /* Note that at this point x0 has already been checked
11246 and found valid. */
11247 rtx x0 = XEXP (x, 0);
11248 rtx x1 = XEXP (x, 1);
11250 /* If x0 and x1 are identical then x is also valid. */
11254 /* If x1 is identical to a subexpression of x0 then
11255 while checking x0, x1 has already been checked. Thus
11256 it is valid and so as x. */
11257 if (ARITHMETIC_P (x0)
11258 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11261 /* If x0 is identical to a subexpression of x1 then x is
11262 valid iff the rest of x1 is valid. */
11263 if (ARITHMETIC_P (x1)
11264 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11266 get_last_value_validate (&XEXP (x1,
11267 x0 == XEXP (x1, 0) ? 1 : 0),
11268 insn, tick, replace);
11271 if (get_last_value_validate (&XEXP (x, i), insn, tick,
11275 /* Don't bother with these. They shouldn't occur anyway. */
11276 else if (fmt[i] == 'E')
11280 /* If we haven't found a reason for it to be invalid, it is valid. */
11284 /* Get the last value assigned to X, if known. Some registers
11285 in the value may be replaced with (clobber (const_int 0)) if their value
11286 is known longer known reliably. */
11289 get_last_value (rtx x)
11291 unsigned int regno;
11294 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11295 then convert it to the desired mode. If this is a paradoxical SUBREG,
11296 we cannot predict what values the "extra" bits might have. */
11297 if (GET_CODE (x) == SUBREG
11298 && subreg_lowpart_p (x)
11299 && (GET_MODE_SIZE (GET_MODE (x))
11300 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11301 && (value = get_last_value (SUBREG_REG (x))) != 0)
11302 return gen_lowpart (GET_MODE (x), value);
11308 value = reg_stat[regno].last_set_value;
11310 /* If we don't have a value, or if it isn't for this basic block and
11311 it's either a hard register, set more than once, or it's a live
11312 at the beginning of the function, return 0.
11314 Because if it's not live at the beginning of the function then the reg
11315 is always set before being used (is never used without being set).
11316 And, if it's set only once, and it's always set before use, then all
11317 uses must have the same last value, even if it's not from this basic
11321 || (reg_stat[regno].last_set_label != label_tick
11322 && (regno < FIRST_PSEUDO_REGISTER
11323 || REG_N_SETS (regno) != 1
11324 || (REGNO_REG_SET_P
11325 (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
11329 /* If the value was set in a later insn than the ones we are processing,
11330 we can't use it even if the register was only set once. */
11331 if (INSN_CUID (reg_stat[regno].last_set) >= subst_low_cuid)
11334 /* If the value has all its registers valid, return it. */
11335 if (get_last_value_validate (&value, reg_stat[regno].last_set,
11336 reg_stat[regno].last_set_label, 0))
11339 /* Otherwise, make a copy and replace any invalid register with
11340 (clobber (const_int 0)). If that fails for some reason, return 0. */
11342 value = copy_rtx (value);
11343 if (get_last_value_validate (&value, reg_stat[regno].last_set,
11344 reg_stat[regno].last_set_label, 1))
11350 /* Return nonzero if expression X refers to a REG or to memory
11351 that is set in an instruction more recent than FROM_CUID. */
11354 use_crosses_set_p (rtx x, int from_cuid)
11358 enum rtx_code code = GET_CODE (x);
11362 unsigned int regno = REGNO (x);
11363 unsigned endreg = regno + (regno < FIRST_PSEUDO_REGISTER
11364 ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
11366 #ifdef PUSH_ROUNDING
11367 /* Don't allow uses of the stack pointer to be moved,
11368 because we don't know whether the move crosses a push insn. */
11369 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11372 for (; regno < endreg; regno++)
11373 if (reg_stat[regno].last_set
11374 && INSN_CUID (reg_stat[regno].last_set) > from_cuid)
11379 if (code == MEM && mem_last_set > from_cuid)
11382 fmt = GET_RTX_FORMAT (code);
11384 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11389 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11390 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
11393 else if (fmt[i] == 'e'
11394 && use_crosses_set_p (XEXP (x, i), from_cuid))
11400 /* Define three variables used for communication between the following
11403 static unsigned int reg_dead_regno, reg_dead_endregno;
11404 static int reg_dead_flag;
11406 /* Function called via note_stores from reg_dead_at_p.
11408 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11409 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11412 reg_dead_at_p_1 (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
11414 unsigned int regno, endregno;
11419 regno = REGNO (dest);
11420 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
11421 ? hard_regno_nregs[regno][GET_MODE (dest)] : 1);
11423 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11424 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11427 /* Return nonzero if REG is known to be dead at INSN.
11429 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11430 referencing REG, it is dead. If we hit a SET referencing REG, it is
11431 live. Otherwise, see if it is live or dead at the start of the basic
11432 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11433 must be assumed to be always live. */
11436 reg_dead_at_p (rtx reg, rtx insn)
11441 /* Set variables for reg_dead_at_p_1. */
11442 reg_dead_regno = REGNO (reg);
11443 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
11444 ? hard_regno_nregs[reg_dead_regno]
11450 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
11451 we allow the machine description to decide whether use-and-clobber
11452 patterns are OK. */
11453 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11455 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11456 if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
11460 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11461 beginning of function. */
11462 for (; insn && !LABEL_P (insn) && !BARRIER_P (insn);
11463 insn = prev_nonnote_insn (insn))
11465 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
11467 return reg_dead_flag == 1 ? 1 : 0;
11469 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11473 /* Get the basic block that we were in. */
11475 block = ENTRY_BLOCK_PTR->next_bb;
11478 FOR_EACH_BB (block)
11479 if (insn == BB_HEAD (block))
11482 if (block == EXIT_BLOCK_PTR)
11486 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11487 if (REGNO_REG_SET_P (block->il.rtl->global_live_at_start, i))
11493 /* Note hard registers in X that are used. This code is similar to
11494 that in flow.c, but much simpler since we don't care about pseudos. */
11497 mark_used_regs_combine (rtx x)
11499 RTX_CODE code = GET_CODE (x);
11500 unsigned int regno;
11513 case ADDR_DIFF_VEC:
11516 /* CC0 must die in the insn after it is set, so we don't need to take
11517 special note of it here. */
11523 /* If we are clobbering a MEM, mark any hard registers inside the
11524 address as used. */
11525 if (MEM_P (XEXP (x, 0)))
11526 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
11531 /* A hard reg in a wide mode may really be multiple registers.
11532 If so, mark all of them just like the first. */
11533 if (regno < FIRST_PSEUDO_REGISTER)
11535 unsigned int endregno, r;
11537 /* None of this applies to the stack, frame or arg pointers. */
11538 if (regno == STACK_POINTER_REGNUM
11539 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11540 || regno == HARD_FRAME_POINTER_REGNUM
11542 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11543 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
11545 || regno == FRAME_POINTER_REGNUM)
11548 endregno = regno + hard_regno_nregs[regno][GET_MODE (x)];
11549 for (r = regno; r < endregno; r++)
11550 SET_HARD_REG_BIT (newpat_used_regs, r);
11556 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11558 rtx testreg = SET_DEST (x);
11560 while (GET_CODE (testreg) == SUBREG
11561 || GET_CODE (testreg) == ZERO_EXTRACT
11562 || GET_CODE (testreg) == STRICT_LOW_PART)
11563 testreg = XEXP (testreg, 0);
11565 if (MEM_P (testreg))
11566 mark_used_regs_combine (XEXP (testreg, 0));
11568 mark_used_regs_combine (SET_SRC (x));
11576 /* Recursively scan the operands of this expression. */
11579 const char *fmt = GET_RTX_FORMAT (code);
11581 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11584 mark_used_regs_combine (XEXP (x, i));
11585 else if (fmt[i] == 'E')
11589 for (j = 0; j < XVECLEN (x, i); j++)
11590 mark_used_regs_combine (XVECEXP (x, i, j));
11596 /* Remove register number REGNO from the dead registers list of INSN.
11598 Return the note used to record the death, if there was one. */
11601 remove_death (unsigned int regno, rtx insn)
11603 rtx note = find_regno_note (insn, REG_DEAD, regno);
11607 REG_N_DEATHS (regno)--;
11608 remove_note (insn, note);
11614 /* For each register (hardware or pseudo) used within expression X, if its
11615 death is in an instruction with cuid between FROM_CUID (inclusive) and
11616 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11617 list headed by PNOTES.
11619 That said, don't move registers killed by maybe_kill_insn.
11621 This is done when X is being merged by combination into TO_INSN. These
11622 notes will then be distributed as needed. */
11625 move_deaths (rtx x, rtx maybe_kill_insn, int from_cuid, rtx to_insn,
11630 enum rtx_code code = GET_CODE (x);
11634 unsigned int regno = REGNO (x);
11635 rtx where_dead = reg_stat[regno].last_death;
11636 rtx before_dead, after_dead;
11638 /* Don't move the register if it gets killed in between from and to. */
11639 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
11640 && ! reg_referenced_p (x, maybe_kill_insn))
11643 /* WHERE_DEAD could be a USE insn made by combine, so first we
11644 make sure that we have insns with valid INSN_CUID values. */
11645 before_dead = where_dead;
11646 while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
11647 before_dead = PREV_INSN (before_dead);
11649 after_dead = where_dead;
11650 while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
11651 after_dead = NEXT_INSN (after_dead);
11653 if (before_dead && after_dead
11654 && INSN_CUID (before_dead) >= from_cuid
11655 && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
11656 || (where_dead != after_dead
11657 && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
11659 rtx note = remove_death (regno, where_dead);
11661 /* It is possible for the call above to return 0. This can occur
11662 when last_death points to I2 or I1 that we combined with.
11663 In that case make a new note.
11665 We must also check for the case where X is a hard register
11666 and NOTE is a death note for a range of hard registers
11667 including X. In that case, we must put REG_DEAD notes for
11668 the remaining registers in place of NOTE. */
11670 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
11671 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11672 > GET_MODE_SIZE (GET_MODE (x))))
11674 unsigned int deadregno = REGNO (XEXP (note, 0));
11675 unsigned int deadend
11676 = (deadregno + hard_regno_nregs[deadregno]
11677 [GET_MODE (XEXP (note, 0))]);
11678 unsigned int ourend
11679 = regno + hard_regno_nregs[regno][GET_MODE (x)];
11682 for (i = deadregno; i < deadend; i++)
11683 if (i < regno || i >= ourend)
11684 REG_NOTES (where_dead)
11685 = gen_rtx_EXPR_LIST (REG_DEAD,
11687 REG_NOTES (where_dead));
11690 /* If we didn't find any note, or if we found a REG_DEAD note that
11691 covers only part of the given reg, and we have a multi-reg hard
11692 register, then to be safe we must check for REG_DEAD notes
11693 for each register other than the first. They could have
11694 their own REG_DEAD notes lying around. */
11695 else if ((note == 0
11697 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11698 < GET_MODE_SIZE (GET_MODE (x)))))
11699 && regno < FIRST_PSEUDO_REGISTER
11700 && hard_regno_nregs[regno][GET_MODE (x)] > 1)
11702 unsigned int ourend
11703 = regno + hard_regno_nregs[regno][GET_MODE (x)];
11704 unsigned int i, offset;
11708 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
11712 for (i = regno + offset; i < ourend; i++)
11713 move_deaths (regno_reg_rtx[i],
11714 maybe_kill_insn, from_cuid, to_insn, &oldnotes);
11717 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
11719 XEXP (note, 1) = *pnotes;
11723 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
11725 REG_N_DEATHS (regno)++;
11731 else if (GET_CODE (x) == SET)
11733 rtx dest = SET_DEST (x);
11735 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
11737 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11738 that accesses one word of a multi-word item, some
11739 piece of everything register in the expression is used by
11740 this insn, so remove any old death. */
11741 /* ??? So why do we test for equality of the sizes? */
11743 if (GET_CODE (dest) == ZERO_EXTRACT
11744 || GET_CODE (dest) == STRICT_LOW_PART
11745 || (GET_CODE (dest) == SUBREG
11746 && (((GET_MODE_SIZE (GET_MODE (dest))
11747 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
11748 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
11749 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
11751 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
11755 /* If this is some other SUBREG, we know it replaces the entire
11756 value, so use that as the destination. */
11757 if (GET_CODE (dest) == SUBREG)
11758 dest = SUBREG_REG (dest);
11760 /* If this is a MEM, adjust deaths of anything used in the address.
11761 For a REG (the only other possibility), the entire value is
11762 being replaced so the old value is not used in this insn. */
11765 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
11770 else if (GET_CODE (x) == CLOBBER)
11773 len = GET_RTX_LENGTH (code);
11774 fmt = GET_RTX_FORMAT (code);
11776 for (i = 0; i < len; i++)
11781 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11782 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
11785 else if (fmt[i] == 'e')
11786 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
11790 /* Return 1 if X is the target of a bit-field assignment in BODY, the
11791 pattern of an insn. X must be a REG. */
11794 reg_bitfield_target_p (rtx x, rtx body)
11798 if (GET_CODE (body) == SET)
11800 rtx dest = SET_DEST (body);
11802 unsigned int regno, tregno, endregno, endtregno;
11804 if (GET_CODE (dest) == ZERO_EXTRACT)
11805 target = XEXP (dest, 0);
11806 else if (GET_CODE (dest) == STRICT_LOW_PART)
11807 target = SUBREG_REG (XEXP (dest, 0));
11811 if (GET_CODE (target) == SUBREG)
11812 target = SUBREG_REG (target);
11814 if (!REG_P (target))
11817 tregno = REGNO (target), regno = REGNO (x);
11818 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
11819 return target == x;
11821 endtregno = tregno + hard_regno_nregs[tregno][GET_MODE (target)];
11822 endregno = regno + hard_regno_nregs[regno][GET_MODE (x)];
11824 return endregno > tregno && regno < endtregno;
11827 else if (GET_CODE (body) == PARALLEL)
11828 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
11829 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
11835 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11836 as appropriate. I3 and I2 are the insns resulting from the combination
11837 insns including FROM (I2 may be zero).
11839 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
11840 not need REG_DEAD notes because they are being substituted for. This
11841 saves searching in the most common cases.
11843 Each note in the list is either ignored or placed on some insns, depending
11844 on the type of note. */
11847 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2,
11850 rtx note, next_note;
11853 for (note = notes; note; note = next_note)
11855 rtx place = 0, place2 = 0;
11857 next_note = XEXP (note, 1);
11858 switch (REG_NOTE_KIND (note))
11862 /* Doesn't matter much where we put this, as long as it's somewhere.
11863 It is preferable to keep these notes on branches, which is most
11864 likely to be i3. */
11868 case REG_VALUE_PROFILE:
11869 /* Just get rid of this note, as it is unused later anyway. */
11872 case REG_NON_LOCAL_GOTO:
11877 gcc_assert (i2 && JUMP_P (i2));
11882 case REG_EH_REGION:
11883 /* These notes must remain with the call or trapping instruction. */
11886 else if (i2 && CALL_P (i2))
11890 gcc_assert (flag_non_call_exceptions);
11891 if (may_trap_p (i3))
11893 else if (i2 && may_trap_p (i2))
11895 /* ??? Otherwise assume we've combined things such that we
11896 can now prove that the instructions can't trap. Drop the
11897 note in this case. */
11903 /* These notes must remain with the call. It should not be
11904 possible for both I2 and I3 to be a call. */
11909 gcc_assert (i2 && CALL_P (i2));
11915 /* Any clobbers for i3 may still exist, and so we must process
11916 REG_UNUSED notes from that insn.
11918 Any clobbers from i2 or i1 can only exist if they were added by
11919 recog_for_combine. In that case, recog_for_combine created the
11920 necessary REG_UNUSED notes. Trying to keep any original
11921 REG_UNUSED notes from these insns can cause incorrect output
11922 if it is for the same register as the original i3 dest.
11923 In that case, we will notice that the register is set in i3,
11924 and then add a REG_UNUSED note for the destination of i3, which
11925 is wrong. However, it is possible to have REG_UNUSED notes from
11926 i2 or i1 for register which were both used and clobbered, so
11927 we keep notes from i2 or i1 if they will turn into REG_DEAD
11930 /* If this register is set or clobbered in I3, put the note there
11931 unless there is one already. */
11932 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
11934 if (from_insn != i3)
11937 if (! (REG_P (XEXP (note, 0))
11938 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
11939 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
11942 /* Otherwise, if this register is used by I3, then this register
11943 now dies here, so we must put a REG_DEAD note here unless there
11945 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
11946 && ! (REG_P (XEXP (note, 0))
11947 ? find_regno_note (i3, REG_DEAD,
11948 REGNO (XEXP (note, 0)))
11949 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
11951 PUT_REG_NOTE_KIND (note, REG_DEAD);
11959 /* These notes say something about results of an insn. We can
11960 only support them if they used to be on I3 in which case they
11961 remain on I3. Otherwise they are ignored.
11963 If the note refers to an expression that is not a constant, we
11964 must also ignore the note since we cannot tell whether the
11965 equivalence is still true. It might be possible to do
11966 slightly better than this (we only have a problem if I2DEST
11967 or I1DEST is present in the expression), but it doesn't
11968 seem worth the trouble. */
11970 if (from_insn == i3
11971 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
11976 case REG_NO_CONFLICT:
11977 /* These notes say something about how a register is used. They must
11978 be present on any use of the register in I2 or I3. */
11979 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
11982 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
11992 /* This can show up in several ways -- either directly in the
11993 pattern, or hidden off in the constant pool with (or without?)
11994 a REG_EQUAL note. */
11995 /* ??? Ignore the without-reg_equal-note problem for now. */
11996 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
11997 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
11998 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
11999 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
12003 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
12004 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
12005 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12006 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12014 /* Don't attach REG_LABEL note to a JUMP_INSN. Add
12015 a JUMP_LABEL instead or decrement LABEL_NUSES. */
12016 if (place && JUMP_P (place))
12018 rtx label = JUMP_LABEL (place);
12021 JUMP_LABEL (place) = XEXP (note, 0);
12024 gcc_assert (label == XEXP (note, 0));
12025 if (LABEL_P (label))
12026 LABEL_NUSES (label)--;
12030 if (place2 && JUMP_P (place2))
12032 rtx label = JUMP_LABEL (place2);
12035 JUMP_LABEL (place2) = XEXP (note, 0);
12038 gcc_assert (label == XEXP (note, 0));
12039 if (LABEL_P (label))
12040 LABEL_NUSES (label)--;
12047 /* This note says something about the value of a register prior
12048 to the execution of an insn. It is too much trouble to see
12049 if the note is still correct in all situations. It is better
12050 to simply delete it. */
12054 /* If the insn previously containing this note still exists,
12055 put it back where it was. Otherwise move it to the previous
12056 insn. Adjust the corresponding REG_LIBCALL note. */
12057 if (!NOTE_P (from_insn))
12061 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
12062 place = prev_real_insn (from_insn);
12064 XEXP (tem, 0) = place;
12065 /* If we're deleting the last remaining instruction of a
12066 libcall sequence, don't add the notes. */
12067 else if (XEXP (note, 0) == from_insn)
12069 /* Don't add the dangling REG_RETVAL note. */
12076 /* This is handled similarly to REG_RETVAL. */
12077 if (!NOTE_P (from_insn))
12081 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
12082 place = next_real_insn (from_insn);
12084 XEXP (tem, 0) = place;
12085 /* If we're deleting the last remaining instruction of a
12086 libcall sequence, don't add the notes. */
12087 else if (XEXP (note, 0) == from_insn)
12089 /* Don't add the dangling REG_LIBCALL note. */
12096 /* If the register is used as an input in I3, it dies there.
12097 Similarly for I2, if it is nonzero and adjacent to I3.
12099 If the register is not used as an input in either I3 or I2
12100 and it is not one of the registers we were supposed to eliminate,
12101 there are two possibilities. We might have a non-adjacent I2
12102 or we might have somehow eliminated an additional register
12103 from a computation. For example, we might have had A & B where
12104 we discover that B will always be zero. In this case we will
12105 eliminate the reference to A.
12107 In both cases, we must search to see if we can find a previous
12108 use of A and put the death note there. */
12111 && CALL_P (from_insn)
12112 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12114 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12116 else if (i2 != 0 && next_nonnote_insn (i2) == i3
12117 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12121 && (rtx_equal_p (XEXP (note, 0), elim_i2)
12122 || rtx_equal_p (XEXP (note, 0), elim_i1)))
12127 basic_block bb = this_basic_block;
12129 /* You might think you could search back from FROM_INSN
12130 rather than from I3, but combine tries to split invalid
12131 combined instructions. This can result in the old I2
12132 or I1 moving later in the insn sequence. */
12133 for (tem = PREV_INSN (i3); place == 0; tem = PREV_INSN (tem))
12135 if (! INSN_P (tem))
12137 if (tem == BB_HEAD (bb))
12142 /* If the register is being set at TEM, see if that is all
12143 TEM is doing. If so, delete TEM. Otherwise, make this
12144 into a REG_UNUSED note instead. Don't delete sets to
12145 global register vars. */
12146 if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
12147 || !global_regs[REGNO (XEXP (note, 0))])
12148 && reg_set_p (XEXP (note, 0), PATTERN (tem)))
12150 rtx set = single_set (tem);
12151 rtx inner_dest = 0;
12153 rtx cc0_setter = NULL_RTX;
12157 for (inner_dest = SET_DEST (set);
12158 (GET_CODE (inner_dest) == STRICT_LOW_PART
12159 || GET_CODE (inner_dest) == SUBREG
12160 || GET_CODE (inner_dest) == ZERO_EXTRACT);
12161 inner_dest = XEXP (inner_dest, 0))
12164 /* Verify that it was the set, and not a clobber that
12165 modified the register.
12167 CC0 targets must be careful to maintain setter/user
12168 pairs. If we cannot delete the setter due to side
12169 effects, mark the user with an UNUSED note instead
12172 if (set != 0 && ! side_effects_p (SET_SRC (set))
12173 && rtx_equal_p (XEXP (note, 0), inner_dest)
12175 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12176 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12177 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12181 /* Move the notes and links of TEM elsewhere.
12182 This might delete other dead insns recursively.
12183 First set the pattern to something that won't use
12185 rtx old_notes = REG_NOTES (tem);
12187 PATTERN (tem) = pc_rtx;
12188 REG_NOTES (tem) = NULL;
12190 distribute_notes (old_notes, tem, tem, NULL_RTX,
12191 NULL_RTX, NULL_RTX);
12192 distribute_links (LOG_LINKS (tem));
12194 SET_INSN_DELETED (tem);
12197 /* Delete the setter too. */
12200 PATTERN (cc0_setter) = pc_rtx;
12201 old_notes = REG_NOTES (cc0_setter);
12202 REG_NOTES (cc0_setter) = NULL;
12204 distribute_notes (old_notes, cc0_setter,
12205 cc0_setter, NULL_RTX,
12206 NULL_RTX, NULL_RTX);
12207 distribute_links (LOG_LINKS (cc0_setter));
12209 SET_INSN_DELETED (cc0_setter);
12215 PUT_REG_NOTE_KIND (note, REG_UNUSED);
12217 /* If there isn't already a REG_UNUSED note, put one
12218 here. Do not place a REG_DEAD note, even if
12219 the register is also used here; that would not
12220 match the algorithm used in lifetime analysis
12221 and can cause the consistency check in the
12222 scheduler to fail. */
12223 if (! find_regno_note (tem, REG_UNUSED,
12224 REGNO (XEXP (note, 0))))
12229 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12231 && find_reg_fusage (tem, USE, XEXP (note, 0))))
12233 /* This may not be the correct place for the death
12234 note if FROM_INSN is before TEM, and the reg is
12235 set between FROM_INSN and TEM. The reg might
12236 die two or more times. An existing death note
12237 means we are looking at the wrong live range. */
12239 && INSN_CUID (from_insn) < INSN_CUID (tem)
12240 && find_regno_note (tem, REG_DEAD,
12241 REGNO (XEXP (note, 0))))
12244 if (tem == BB_HEAD (bb))
12251 /* If we are doing a 3->2 combination, and we have a
12252 register which formerly died in i3 and was not used
12253 by i2, which now no longer dies in i3 and is used in
12254 i2 but does not die in i2, and place is between i2
12255 and i3, then we may need to move a link from place to
12257 if (i2 && INSN_UID (place) <= max_uid_cuid
12258 && INSN_CUID (place) > INSN_CUID (i2)
12260 && INSN_CUID (from_insn) > INSN_CUID (i2)
12261 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12263 rtx links = LOG_LINKS (place);
12264 LOG_LINKS (place) = 0;
12265 distribute_links (links);
12270 if (tem == BB_HEAD (bb))
12274 /* We haven't found an insn for the death note and it
12275 is still a REG_DEAD note, but we have hit the beginning
12276 of the block. If the existing life info says the reg
12277 was dead, there's nothing left to do. Otherwise, we'll
12278 need to do a global life update after combine. */
12279 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0
12280 && REGNO_REG_SET_P (bb->il.rtl->global_live_at_start,
12281 REGNO (XEXP (note, 0))))
12282 SET_BIT (refresh_blocks, this_basic_block->index);
12285 /* If the register is set or already dead at PLACE, we needn't do
12286 anything with this note if it is still a REG_DEAD note.
12287 We check here if it is set at all, not if is it totally replaced,
12288 which is what `dead_or_set_p' checks, so also check for it being
12291 if (place && REG_NOTE_KIND (note) == REG_DEAD)
12293 unsigned int regno = REGNO (XEXP (note, 0));
12295 /* Similarly, if the instruction on which we want to place
12296 the note is a noop, we'll need do a global live update
12297 after we remove them in delete_noop_moves. */
12298 if (noop_move_p (place))
12299 SET_BIT (refresh_blocks, this_basic_block->index);
12301 if (dead_or_set_p (place, XEXP (note, 0))
12302 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12304 /* Unless the register previously died in PLACE, clear
12305 last_death. [I no longer understand why this is
12307 if (reg_stat[regno].last_death != place)
12308 reg_stat[regno].last_death = 0;
12312 reg_stat[regno].last_death = place;
12314 /* If this is a death note for a hard reg that is occupying
12315 multiple registers, ensure that we are still using all
12316 parts of the object. If we find a piece of the object
12317 that is unused, we must arrange for an appropriate REG_DEAD
12318 note to be added for it. However, we can't just emit a USE
12319 and tag the note to it, since the register might actually
12320 be dead; so we recourse, and the recursive call then finds
12321 the previous insn that used this register. */
12323 if (place && regno < FIRST_PSEUDO_REGISTER
12324 && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
12326 unsigned int endregno
12327 = regno + hard_regno_nregs[regno]
12328 [GET_MODE (XEXP (note, 0))];
12332 for (i = regno; i < endregno; i++)
12333 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12334 && ! find_regno_fusage (place, USE, i))
12335 || dead_or_set_regno_p (place, i))
12340 /* Put only REG_DEAD notes for pieces that are
12341 not already dead or set. */
12343 for (i = regno; i < endregno;
12344 i += hard_regno_nregs[i][reg_raw_mode[i]])
12346 rtx piece = regno_reg_rtx[i];
12347 basic_block bb = this_basic_block;
12349 if (! dead_or_set_p (place, piece)
12350 && ! reg_bitfield_target_p (piece,
12354 = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX);
12356 distribute_notes (new_note, place, place,
12357 NULL_RTX, NULL_RTX, NULL_RTX);
12359 else if (! refers_to_regno_p (i, i + 1,
12360 PATTERN (place), 0)
12361 && ! find_regno_fusage (place, USE, i))
12362 for (tem = PREV_INSN (place); ;
12363 tem = PREV_INSN (tem))
12365 if (! INSN_P (tem))
12367 if (tem == BB_HEAD (bb))
12369 SET_BIT (refresh_blocks,
12370 this_basic_block->index);
12375 if (dead_or_set_p (tem, piece)
12376 || reg_bitfield_target_p (piece,
12380 = gen_rtx_EXPR_LIST (REG_UNUSED, piece,
12395 /* Any other notes should not be present at this point in the
12397 gcc_unreachable ();
12402 XEXP (note, 1) = REG_NOTES (place);
12403 REG_NOTES (place) = note;
12405 else if ((REG_NOTE_KIND (note) == REG_DEAD
12406 || REG_NOTE_KIND (note) == REG_UNUSED)
12407 && REG_P (XEXP (note, 0)))
12408 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
12412 if ((REG_NOTE_KIND (note) == REG_DEAD
12413 || REG_NOTE_KIND (note) == REG_UNUSED)
12414 && REG_P (XEXP (note, 0)))
12415 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
12417 REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
12418 REG_NOTE_KIND (note),
12420 REG_NOTES (place2));
12425 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12426 I3, I2, and I1 to new locations. This is also called to add a link
12427 pointing at I3 when I3's destination is changed. */
12430 distribute_links (rtx links)
12432 rtx link, next_link;
12434 for (link = links; link; link = next_link)
12440 next_link = XEXP (link, 1);
12442 /* If the insn that this link points to is a NOTE or isn't a single
12443 set, ignore it. In the latter case, it isn't clear what we
12444 can do other than ignore the link, since we can't tell which
12445 register it was for. Such links wouldn't be used by combine
12448 It is not possible for the destination of the target of the link to
12449 have been changed by combine. The only potential of this is if we
12450 replace I3, I2, and I1 by I3 and I2. But in that case the
12451 destination of I2 also remains unchanged. */
12453 if (NOTE_P (XEXP (link, 0))
12454 || (set = single_set (XEXP (link, 0))) == 0)
12457 reg = SET_DEST (set);
12458 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12459 || GET_CODE (reg) == STRICT_LOW_PART)
12460 reg = XEXP (reg, 0);
12462 /* A LOG_LINK is defined as being placed on the first insn that uses
12463 a register and points to the insn that sets the register. Start
12464 searching at the next insn after the target of the link and stop
12465 when we reach a set of the register or the end of the basic block.
12467 Note that this correctly handles the link that used to point from
12468 I3 to I2. Also note that not much searching is typically done here
12469 since most links don't point very far away. */
12471 for (insn = NEXT_INSN (XEXP (link, 0));
12472 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
12473 || BB_HEAD (this_basic_block->next_bb) != insn));
12474 insn = NEXT_INSN (insn))
12475 if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12477 if (reg_referenced_p (reg, PATTERN (insn)))
12481 else if (CALL_P (insn)
12482 && find_reg_fusage (insn, USE, reg))
12487 else if (INSN_P (insn) && reg_set_p (reg, insn))
12490 /* If we found a place to put the link, place it there unless there
12491 is already a link to the same insn as LINK at that point. */
12497 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12498 if (XEXP (link2, 0) == XEXP (link, 0))
12503 XEXP (link, 1) = LOG_LINKS (place);
12504 LOG_LINKS (place) = link;
12506 /* Set added_links_insn to the earliest insn we added a
12508 if (added_links_insn == 0
12509 || INSN_CUID (added_links_insn) > INSN_CUID (place))
12510 added_links_insn = place;
12516 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
12517 Check whether the expression pointer to by LOC is a register or
12518 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
12519 Otherwise return zero. */
12522 unmentioned_reg_p_1 (rtx *loc, void *expr)
12527 && (REG_P (x) || MEM_P (x))
12528 && ! reg_mentioned_p (x, (rtx) expr))
12533 /* Check for any register or memory mentioned in EQUIV that is not
12534 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
12535 of EXPR where some registers may have been replaced by constants. */
12538 unmentioned_reg_p (rtx equiv, rtx expr)
12540 return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
12543 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12546 insn_cuid (rtx insn)
12548 while (insn != 0 && INSN_UID (insn) > max_uid_cuid
12549 && NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE)
12550 insn = NEXT_INSN (insn);
12552 gcc_assert (INSN_UID (insn) <= max_uid_cuid);
12554 return INSN_CUID (insn);
12558 dump_combine_stats (FILE *file)
12562 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12563 combine_attempts, combine_merges, combine_extras, combine_successes);
12567 dump_combine_total_stats (FILE *file)
12571 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12572 total_attempts, total_merges, total_extras, total_successes);
12577 gate_handle_combine (void)
12579 return (optimize > 0);
12582 /* Try combining insns through substitution. */
12583 static unsigned int
12584 rest_of_handle_combine (void)
12586 int rebuild_jump_labels_after_combine
12587 = combine_instructions (get_insns (), max_reg_num ());
12589 /* Combining insns may have turned an indirect jump into a
12590 direct jump. Rebuild the JUMP_LABEL fields of jumping
12592 if (rebuild_jump_labels_after_combine)
12594 timevar_push (TV_JUMP);
12595 rebuild_jump_labels (get_insns ());
12596 timevar_pop (TV_JUMP);
12598 delete_dead_jumptables ();
12599 cleanup_cfg (CLEANUP_EXPENSIVE | CLEANUP_UPDATE_LIFE);
12604 struct tree_opt_pass pass_combine =
12606 "combine", /* name */
12607 gate_handle_combine, /* gate */
12608 rest_of_handle_combine, /* execute */
12611 0, /* static_pass_number */
12612 TV_COMBINE, /* tv_id */
12613 0, /* properties_required */
12614 0, /* properties_provided */
12615 0, /* properties_destroyed */
12616 0, /* todo_flags_start */
12618 TODO_ggc_collect, /* todo_flags_finish */