\r
#ifndef AT91SAM7S256_H\r
# define AT91SAM7S256_H\r
-\rtypedef volatile unsigned int AT91_REG; // Hardware register definition\r
-
+\r
+typedef volatile unsigned int AT91_REG; // Hardware register definition\r
+\r
\r
// *****************************************************************************\r
// SOFTWARE API DEFINITION FOR System Peripherals\r
// *****************************************************************************\r
- typedef struct _AT91S_SYS {
- \rAT91_REG AIC_SMR[32]; // Source Mode Register\r
+ typedef struct _AT91S_SYS {\r
+ \r
+AT91_REG AIC_SMR[32]; // Source Mode Register\r
AT91_REG AIC_SVR[32]; // Source Vector Register\r
AT91_REG AIC_IVR; // IRQ Vector Register\r
AT91_REG AIC_FVR; // FIQ Vector Register\r
AT91_REG WDTC_WDSR; // Watchdog Status Register\r
AT91_REG Reserved20[5]; //\r
AT91_REG VREG_MR; // Voltage Regulator Mode Register\r
-} AT91S_SYS, *AT91PS_SYS;
-
-\r\r\r
+} AT91S_SYS, *AT91PS_SYS;\r
+\r
+\r
+\r
+\r
// *****************************************************************************\r
// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller\r
// *****************************************************************************\r
- typedef struct _AT91S_AIC {
- \rAT91_REG AIC_SMR[32]; // Source Mode Register\r
+ typedef struct _AT91S_AIC {\r
+ \r
+AT91_REG AIC_SMR[32]; // Source Mode Register\r
AT91_REG AIC_SVR[32]; // Source Vector Register\r
AT91_REG AIC_IVR; // IRQ Vector Register\r
AT91_REG AIC_FVR; // FIQ Vector Register\r
AT91_REG AIC_FFER; // Fast Forcing Enable Register\r
AT91_REG AIC_FFDR; // Fast Forcing Disable Register\r
AT91_REG AIC_FFSR; // Fast Forcing Status Register\r
-} AT91S_AIC, *AT91PS_AIC;
-
-\r\r
+} AT91S_AIC, *AT91PS_AIC;\r
+\r
+\r
+\r
// -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------\r
# define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level\r
# define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level\r
// *****************************************************************************\r
// SOFTWARE API DEFINITION FOR Peripheral DMA Controller\r
// *****************************************************************************\r
- typedef struct _AT91S_PDC {
- \rAT91_REG PDC_RPR; // Receive Pointer Register\r
+ typedef struct _AT91S_PDC {\r
+ \r
+AT91_REG PDC_RPR; // Receive Pointer Register\r
AT91_REG PDC_RCR; // Receive Counter Register\r
AT91_REG PDC_TPR; // Transmit Pointer Register\r
AT91_REG PDC_TCR; // Transmit Counter Register\r
AT91_REG PDC_TNCR; // Transmit Next Counter Register\r
AT91_REG PDC_PTCR; // PDC Transfer Control Register\r
AT91_REG PDC_PTSR; // PDC Transfer Status Register\r
-} AT91S_PDC, *AT91PS_PDC;
-
-\r\r
+} AT91S_PDC, *AT91PS_PDC;\r
+\r
+\r
+\r
// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------\r
# define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable\r
# define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable\r
// *****************************************************************************\r
// SOFTWARE API DEFINITION FOR Debug Unit\r
// *****************************************************************************\r
- typedef struct _AT91S_DBGU {
- \rAT91_REG DBGU_CR; // Control Register\r
+ typedef struct _AT91S_DBGU {\r
+ \r
+AT91_REG DBGU_CR; // Control Register\r
AT91_REG DBGU_MR; // Mode Register\r
AT91_REG DBGU_IER; // Interrupt Enable Register\r
AT91_REG DBGU_IDR; // Interrupt Disable Register\r
AT91_REG DBGU_TNCR; // Transmit Next Counter Register\r
AT91_REG DBGU_PTCR; // PDC Transfer Control Register\r
AT91_REG DBGU_PTSR; // PDC Transfer Status Register\r
-} AT91S_DBGU, *AT91PS_DBGU;
-
-\r\r
+} AT91S_DBGU, *AT91PS_DBGU;\r
+\r
+\r
+\r
// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------\r
# define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver\r
# define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter\r
// *****************************************************************************\r
// SOFTWARE API DEFINITION FOR Parallel Input Output Controler\r
// *****************************************************************************\r
- typedef struct _AT91S_PIO {
- \rAT91_REG PIO_PER; // PIO Enable Register\r
+ typedef struct _AT91S_PIO {\r
+ \r
+AT91_REG PIO_PER; // PIO Enable Register\r
AT91_REG PIO_PDR; // PIO Disable Register\r
AT91_REG PIO_PSR; // PIO Status Register\r
AT91_REG Reserved0[1]; //\r
AT91_REG PIO_OWER; // Output Write Enable Register\r
AT91_REG PIO_OWDR; // Output Write Disable Register\r
AT91_REG PIO_OWSR; // Output Write Status Register\r
-} AT91S_PIO, *AT91PS_PIO;
-
-\r\r\r
+} AT91S_PIO, *AT91PS_PIO;\r
+\r
+\r
+\r
+\r
// *****************************************************************************\r
// SOFTWARE API DEFINITION FOR Clock Generator Controler\r
// *****************************************************************************\r
- typedef struct _AT91S_CKGR {
- \rAT91_REG CKGR_MOR; // Main Oscillator Register\r
+ typedef struct _AT91S_CKGR {\r
+ \r
+AT91_REG CKGR_MOR; // Main Oscillator Register\r
AT91_REG CKGR_MCFR; // Main Clock Frequency Register\r
AT91_REG Reserved0[1]; //\r
AT91_REG CKGR_PLLR; // PLL Register\r
-} AT91S_CKGR, *AT91PS_CKGR;
-
-\r\r
+} AT91S_CKGR, *AT91PS_CKGR;\r
+\r
+\r
+\r
// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------\r
# define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable\r
# define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass\r
// *****************************************************************************\r
// SOFTWARE API DEFINITION FOR Power Management Controler\r
// *****************************************************************************\r
- typedef struct _AT91S_PMC {
- \rAT91_REG PMC_SCER; // System Clock Enable Register\r
+ typedef struct _AT91S_PMC {\r
+ \r
+AT91_REG PMC_SCER; // System Clock Enable Register\r
AT91_REG PMC_SCDR; // System Clock Disable Register\r
AT91_REG PMC_SCSR; // System Clock Status Register\r
AT91_REG Reserved0[1]; //\r
AT91_REG PMC_IDR; // Interrupt Disable Register\r
AT91_REG PMC_SR; // Status Register\r
AT91_REG PMC_IMR; // Interrupt Mask Register\r
-} AT91S_PMC, *AT91PS_PMC;
-
-\r\r
+} AT91S_PMC, *AT91PS_PMC;\r
+\r
+\r
+\r
// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------\r
# define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock\r
# define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock\r
// *****************************************************************************\r
// SOFTWARE API DEFINITION FOR Reset Controller Interface\r
// *****************************************************************************\r
- typedef struct _AT91S_RSTC {
- \rAT91_REG RSTC_RCR; // Reset Control Register\r
+ typedef struct _AT91S_RSTC {\r
+ \r
+AT91_REG RSTC_RCR; // Reset Control Register\r
AT91_REG RSTC_RSR; // Reset Status Register\r
AT91_REG RSTC_RMR; // Reset Mode Register\r
-} AT91S_RSTC, *AT91PS_RSTC;
-
-\r\r
+} AT91S_RSTC, *AT91PS_RSTC;\r
+\r
+\r
+\r
// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------\r
# define AT91C_RSTC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset\r
# define AT91C_RSTC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset\r
// *****************************************************************************\r
// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface\r
// *****************************************************************************\r
- typedef struct _AT91S_RTTC {
- \rAT91_REG RTTC_RTMR; // Real-time Mode Register\r
+ typedef struct _AT91S_RTTC {\r
+ \r
+AT91_REG RTTC_RTMR; // Real-time Mode Register\r
AT91_REG RTTC_RTAR; // Real-time Alarm Register\r
AT91_REG RTTC_RTVR; // Real-time Value Register\r
AT91_REG RTTC_RTSR; // Real-time Status Register\r
-} AT91S_RTTC, *AT91PS_RTTC;
-
-\r\r
+} AT91S_RTTC, *AT91PS_RTTC;\r
+\r
+\r
+\r
// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------\r
# define AT91C_RTTC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value\r
# define AT91C_RTTC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable\r
// *****************************************************************************\r
// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface\r
// *****************************************************************************\r
- typedef struct _AT91S_PITC {
- \rAT91_REG PITC_PIMR; // Period Interval Mode Register\r
+ typedef struct _AT91S_PITC {\r
+ \r
+AT91_REG PITC_PIMR; // Period Interval Mode Register\r
AT91_REG PITC_PISR; // Period Interval Status Register\r
AT91_REG PITC_PIVR; // Period Interval Value Register\r
AT91_REG PITC_PIIR; // Period Interval Image Register\r
-} AT91S_PITC, *AT91PS_PITC;
-
-\r\r
+} AT91S_PITC, *AT91PS_PITC;\r
+\r
+\r
+\r
// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------\r
# define AT91C_PITC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value\r
# define AT91C_PITC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled\r
// *****************************************************************************\r
// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface\r
// *****************************************************************************\r
- typedef struct _AT91S_WDTC {
- \rAT91_REG WDTC_WDCR; // Watchdog Control Register\r
+ typedef struct _AT91S_WDTC {\r
+ \r
+AT91_REG WDTC_WDCR; // Watchdog Control Register\r
AT91_REG WDTC_WDMR; // Watchdog Mode Register\r
AT91_REG WDTC_WDSR; // Watchdog Status Register\r
-} AT91S_WDTC, *AT91PS_WDTC;
-
-\r\r
+} AT91S_WDTC, *AT91PS_WDTC;\r
+\r
+\r
+\r
// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------\r
# define AT91C_WDTC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart\r
# define AT91C_WDTC_KEY ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password\r
// *****************************************************************************\r
// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface\r
// *****************************************************************************\r
- typedef struct _AT91S_VREG {
- \rAT91_REG VREG_MR; // Voltage Regulator Mode Register\r
-} AT91S_VREG, *AT91PS_VREG;
-
-\r\r
+ typedef struct _AT91S_VREG {\r
+ \r
+AT91_REG VREG_MR; // Voltage Regulator Mode Register\r
+} AT91S_VREG, *AT91PS_VREG;\r
+\r
+\r
+\r
// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register --------\r
# define AT91C_VREG_PSTDBY ((unsigned int) 0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode\r
\r
// *****************************************************************************\r
// SOFTWARE API DEFINITION FOR Memory Controller Interface\r
// *****************************************************************************\r
- typedef struct _AT91S_MC {
- \rAT91_REG MC_RCR; // MC Remap Control Register\r
+ typedef struct _AT91S_MC {\r
+ \r
+AT91_REG MC_RCR; // MC Remap Control Register\r
AT91_REG MC_ASR; // MC Abort Status Register\r
AT91_REG MC_AASR; // MC Abort Address Status Register\r
AT91_REG Reserved0[21]; //\r
AT91_REG MC_FMR; // MC Flash Mode Register\r
AT91_REG MC_FCR; // MC Flash Command Register\r
AT91_REG MC_FSR; // MC Flash Status Register\r
-} AT91S_MC, *AT91PS_MC;
-
-\r\r
+} AT91S_MC, *AT91PS_MC;\r
+\r
+\r
+\r
// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------\r
# define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit\r
// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------\r
// *****************************************************************************\r
// SOFTWARE API DEFINITION FOR Serial Parallel Interface\r
// *****************************************************************************\r
- typedef struct _AT91S_SPI {
- \rAT91_REG SPI_CR; // Control Register\r
+ typedef struct _AT91S_SPI {\r
+ \r
+AT91_REG SPI_CR; // Control Register\r
AT91_REG SPI_MR; // Mode Register\r
AT91_REG SPI_RDR; // Receive Data Register\r
AT91_REG SPI_TDR; // Transmit Data Register\r
AT91_REG SPI_TNCR; // Transmit Next Counter Register\r
AT91_REG SPI_PTCR; // PDC Transfer Control Register\r
AT91_REG SPI_PTSR; // PDC Transfer Status Register\r
-} AT91S_SPI, *AT91PS_SPI;
-
-\r\r
+} AT91S_SPI, *AT91PS_SPI;\r
+\r
+\r
+\r
// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------\r
# define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable\r
# define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable\r
// *****************************************************************************\r
// SOFTWARE API DEFINITION FOR Analog to Digital Convertor\r
// *****************************************************************************\r
- typedef struct _AT91S_ADC {
- \rAT91_REG ADC_CR; // ADC Control Register\r
+ typedef struct _AT91S_ADC {\r
+ \r
+AT91_REG ADC_CR; // ADC Control Register\r
AT91_REG ADC_MR; // ADC Mode Register\r
AT91_REG Reserved0[2]; //\r
AT91_REG ADC_CHER; // ADC Channel Enable Register\r
AT91_REG ADC_TNCR; // Transmit Next Counter Register\r
AT91_REG ADC_PTCR; // PDC Transfer Control Register\r
AT91_REG ADC_PTSR; // PDC Transfer Status Register\r
-} AT91S_ADC, *AT91PS_ADC;
-
-\r\r
+} AT91S_ADC, *AT91PS_ADC;\r
+\r
+\r
+\r
// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------\r
# define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset\r
# define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion\r
// *****************************************************************************\r
// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface\r
// *****************************************************************************\r
- typedef struct _AT91S_SSC {
- \rAT91_REG SSC_CR; // Control Register\r
+ typedef struct _AT91S_SSC {\r
+ \r
+AT91_REG SSC_CR; // Control Register\r
AT91_REG SSC_CMR; // Clock Mode Register\r
AT91_REG Reserved0[2]; //\r
AT91_REG SSC_RCMR; // Receive Clock ModeRegister\r
AT91_REG SSC_TNCR; // Transmit Next Counter Register\r
AT91_REG SSC_PTCR; // PDC Transfer Control Register\r
AT91_REG SSC_PTSR; // PDC Transfer Status Register\r
-} AT91S_SSC, *AT91PS_SSC;
-
-\r\r
+} AT91S_SSC, *AT91PS_SSC;\r
+\r
+\r
+\r
// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------\r
# define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable\r
# define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable\r
// *****************************************************************************\r
// SOFTWARE API DEFINITION FOR Usart\r
// *****************************************************************************\r
- typedef struct _AT91S_USART {
- \rAT91_REG US_CR; // Control Register\r
+ typedef struct _AT91S_USART {\r
+ \r
+AT91_REG US_CR; // Control Register\r
AT91_REG US_MR; // Mode Register\r
AT91_REG US_IER; // Interrupt Enable Register\r
AT91_REG US_IDR; // Interrupt Disable Register\r
AT91_REG US_TNCR; // Transmit Next Counter Register\r
AT91_REG US_PTCR; // PDC Transfer Control Register\r
AT91_REG US_PTSR; // PDC Transfer Status Register\r
-} AT91S_USART, *AT91PS_USART;
-
-\r\r
+} AT91S_USART, *AT91PS_USART;\r
+\r
+\r
+\r
// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------\r
# define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break\r
# define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break\r
// *****************************************************************************\r
// SOFTWARE API DEFINITION FOR Two-wire Interface\r
// *****************************************************************************\r
- typedef struct _AT91S_TWI {
- \rAT91_REG TWI_CR; // Control Register\r
+ typedef struct _AT91S_TWI {\r
+ \r
+AT91_REG TWI_CR; // Control Register\r
AT91_REG TWI_MMR; // Master Mode Register\r
AT91_REG Reserved0[1]; //\r
AT91_REG TWI_IADR; // Internal Address Register\r
AT91_REG TWI_IMR; // Interrupt Mask Register\r
AT91_REG TWI_RHR; // Receive Holding Register\r
AT91_REG TWI_THR; // Transmit Holding Register\r
-} AT91S_TWI, *AT91PS_TWI;
-
-\r\r
+} AT91S_TWI, *AT91PS_TWI;\r
+\r
+\r
+\r
// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------\r
# define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition\r
# define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition\r
// *****************************************************************************\r
// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface\r
// *****************************************************************************\r
- typedef struct _AT91S_TC {
- \rAT91_REG TC_CCR; // Channel Control Register\r
+ typedef struct _AT91S_TC {\r
+ \r
+AT91_REG TC_CCR; // Channel Control Register\r
AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode)\r
AT91_REG Reserved0[2]; //\r
AT91_REG TC_CV; // Counter Value\r
AT91_REG TC_IER; // Interrupt Enable Register\r
AT91_REG TC_IDR; // Interrupt Disable Register\r
AT91_REG TC_IMR; // Interrupt Mask Register\r
-} AT91S_TC, *AT91PS_TC;
-
-\r\r
+} AT91S_TC, *AT91PS_TC;\r
+\r
+\r
+\r
// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------\r
# define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command\r
# define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command\r
// *****************************************************************************\r
// SOFTWARE API DEFINITION FOR Timer Counter Interface\r
// *****************************************************************************\r
- typedef struct _AT91S_TCB {
- \rAT91S_TC TCB_TC0; // TC Channel 0\r
+ typedef struct _AT91S_TCB {\r
+ \r
+AT91S_TC TCB_TC0; // TC Channel 0\r
AT91_REG Reserved0[4]; //\r
AT91S_TC TCB_TC1; // TC Channel 1\r
AT91_REG Reserved1[4]; //\r
AT91_REG Reserved2[4]; //\r
AT91_REG TCB_BCR; // TC Block Control Register\r
AT91_REG TCB_BMR; // TC Block Mode Register\r
-} AT91S_TCB, *AT91PS_TCB;
-
-\r\r
+} AT91S_TCB, *AT91PS_TCB;\r
+\r
+\r
+\r
// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------\r
# define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command\r
// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------\r
// *****************************************************************************\r
// SOFTWARE API DEFINITION FOR PWMC Channel Interface\r
// *****************************************************************************\r
- typedef struct _AT91S_PWMC_CH {
- \rAT91_REG PWMC_CMR; // Channel Mode Register\r
+ typedef struct _AT91S_PWMC_CH {\r
+ \r
+AT91_REG PWMC_CMR; // Channel Mode Register\r
AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register\r
AT91_REG PWMC_CPRDR; // Channel Period Register\r
AT91_REG PWMC_CCNTR; // Channel Counter Register\r
AT91_REG PWMC_CUPDR; // Channel Update Register\r
AT91_REG PWMC_Reserved[3]; // Reserved\r
-} AT91S_PWMC_CH, *AT91PS_PWMC_CH;
-
-\r\r
+} AT91S_PWMC_CH, *AT91PS_PWMC_CH;\r
+\r
+\r
+\r
// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register --------\r
# define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx\r
# define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH)\r
// *****************************************************************************\r
// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface\r
// *****************************************************************************\r
- typedef struct _AT91S_PWMC {
- \rAT91_REG PWMC_MR; // PWMC Mode Register\r
+ typedef struct _AT91S_PWMC {\r
+ \r
+AT91_REG PWMC_MR; // PWMC Mode Register\r
AT91_REG PWMC_ENA; // PWMC Enable Register\r
AT91_REG PWMC_DIS; // PWMC Disable Register\r
AT91_REG PWMC_SR; // PWMC Status Register\r
AT91_REG PWMC_VR; // PWMC Version Register\r
AT91_REG Reserved1[64]; //\r
AT91S_PWMC_CH PWMC_CH[32]; // PWMC Channel 0\r
-} AT91S_PWMC, *AT91PS_PWMC;
-
-\r\r
+} AT91S_PWMC, *AT91PS_PWMC;\r
+\r
+\r
+\r
// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register --------\r
# define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor.\r
# define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A\r
// *****************************************************************************\r
// SOFTWARE API DEFINITION FOR USB Device Interface\r
// *****************************************************************************\r
- typedef struct _AT91S_UDP {
- \rAT91_REG UDP_NUM; // Frame Number Register\r
+ typedef struct _AT91S_UDP {\r
+ \r
+AT91_REG UDP_NUM; // Frame Number Register\r
AT91_REG UDP_GLBSTATE; // Global State Register\r
AT91_REG UDP_FADDR; // Function Address Register\r
AT91_REG Reserved0[1]; //\r
AT91_REG UDP_FDR[8]; // Endpoint FIFO Data Register\r
AT91_REG Reserved3[1]; //\r
AT91_REG UDP_TXVC; // Transceiver Control Register\r
-} AT91S_UDP, *AT91PS_UDP;
-
-\r\r
+} AT91S_UDP, *AT91PS_UDP;\r
+\r
+\r
+\r
// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------\r
# define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats\r
# define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error\r
// *****************************************************************************\r
// ========== Register definition for SYS peripheral ==========\r
// ========== Register definition for AIC peripheral ==========\r
-# define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100)
+# define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100)\r
// (AIC) IRQ Vector Register\r
-# define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000)
+# define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000)\r
// (AIC) Source Mode Register\r
-# define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104)
+# define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104)\r
// (AIC) FIQ Vector Register\r
-# define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138)
+# define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138)\r
// (AIC) Debug Control Register (Protect)\r
-# define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130)
+# define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130)\r
// (AIC) End of Interrupt Command Register\r
-# define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080)
+# define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080)\r
// (AIC) Source Vector Register\r
-# define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148)
+# define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148)\r
// (AIC) Fast Forcing Status Register\r
-# define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128)
+# define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128)\r
// (AIC) Interrupt Clear Command Register\r
-# define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108)
+# define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108)\r
// (AIC) Interrupt Status Register\r
-# define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110)
+# define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110)\r
// (AIC) Interrupt Mask Register\r
-# define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C)
+# define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C)\r
// (AIC) Interrupt Pending Register\r
-# define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140)
+# define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140)\r
// (AIC) Fast Forcing Enable Register\r
-# define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120)
+# define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120)\r
// (AIC) Interrupt Enable Command Register\r
-# define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C)
+# define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C)\r
// (AIC) Interrupt Set Command Register\r
-# define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144)
+# define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144)\r
// (AIC) Fast Forcing Disable Register\r
-# define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114)
+# define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114)\r
// (AIC) Core Interrupt Status Register\r
-# define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124)
+# define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124)\r
// (AIC) Interrupt Disable Command Register\r
-# define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134)
+# define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134)\r
// (AIC) Spurious Vector Register\r
// ========== Register definition for PDC_DBGU peripheral ==========\r
-# define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C)
+# define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C)\r
// (PDC_DBGU) Transmit Counter Register\r
-# define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310)
+# define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310)\r
// (PDC_DBGU) Receive Next Pointer Register\r
-# define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318)
+# define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318)\r
// (PDC_DBGU) Transmit Next Pointer Register\r
-# define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308)
+# define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308)\r
// (PDC_DBGU) Transmit Pointer Register\r
-# define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300)
+# define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300)\r
// (PDC_DBGU) Receive Pointer Register\r
-# define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304)
+# define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304)\r
// (PDC_DBGU) Receive Counter Register\r
-# define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314)
+# define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314)\r
// (PDC_DBGU) Receive Next Counter Register\r
-# define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320)
+# define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320)\r
// (PDC_DBGU) PDC Transfer Control Register\r
-# define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324)
+# define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324)\r
// (PDC_DBGU) PDC Transfer Status Register\r
-# define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C)
+# define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C)\r
// (PDC_DBGU) Transmit Next Counter Register\r
// ========== Register definition for DBGU peripheral ==========\r
-# define AT91C_DBGU_EXID ((AT91_REG *) 0xFFFFF244)
+# define AT91C_DBGU_EXID ((AT91_REG *) 0xFFFFF244)\r
// (DBGU) Chip ID Extension Register\r
-# define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220)
+# define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220)\r
// (DBGU) Baud Rate Generator Register\r
-# define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C)
+# define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C)\r
// (DBGU) Interrupt Disable Register\r
-# define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214)
+# define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214)\r
// (DBGU) Channel Status Register\r
-# define AT91C_DBGU_CIDR ((AT91_REG *) 0xFFFFF240)
+# define AT91C_DBGU_CIDR ((AT91_REG *) 0xFFFFF240)\r
// (DBGU) Chip ID Register\r
-# define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204)
+# define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204)\r
// (DBGU) Mode Register\r
-# define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210)
+# define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210)\r
// (DBGU) Interrupt Mask Register\r
-# define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200)
+# define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200)\r
// (DBGU) Control Register\r
-# define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248)
+# define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248)\r
// (DBGU) Force NTRST Register\r
-# define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C)
+# define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C)\r
// (DBGU) Transmitter Holding Register\r
-# define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218)
+# define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218)\r
// (DBGU) Receiver Holding Register\r
-# define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208)
+# define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208)\r
// (DBGU) Interrupt Enable Register\r
// ========== Register definition for PIOA peripheral ==========\r
-# define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414)
+# define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414)\r
// (PIOA) Output Disable Registerr\r
-# define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430)
+# define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430)\r
// (PIOA) Set Output Data Register\r
-# define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C)
+# define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C)\r
// (PIOA) Interrupt Status Register\r
-# define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478)
+# define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478)\r
// (PIOA) AB Select Status Register\r
-# define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440)
+# define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440)\r
// (PIOA) Interrupt Enable Register\r
-# define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460)
+# define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460)\r
// (PIOA) Pull-up Disable Register\r
-# define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448)
+# define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448)\r
// (PIOA) Interrupt Mask Register\r
-# define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400)
+# define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400)\r
// (PIOA) PIO Enable Register\r
-# define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424)
+# define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424)\r
// (PIOA) Input Filter Disable Register\r
-# define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4)
+# define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4)\r
// (PIOA) Output Write Disable Register\r
-# define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458)
+# define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458)\r
// (PIOA) Multi-driver Status Register\r
-# define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444)
+# define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444)\r
// (PIOA) Interrupt Disable Register\r
-# define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438)
+# define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438)\r
// (PIOA) Output Data Status Register\r
-# define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468)
+# define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468)\r
// (PIOA) Pull-up Status Register\r
-# define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8)
+# define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8)\r
// (PIOA) Output Write Status Register\r
-# define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474)
+# define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474)\r
// (PIOA) Select B Register\r
-# define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0)
+# define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0)\r
// (PIOA) Output Write Enable Register\r
-# define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420)
+# define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420)\r
// (PIOA) Input Filter Enable Register\r
-# define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C)
+# define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C)\r
// (PIOA) Pin Data Status Register\r
-# define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464)
+# define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464)\r
// (PIOA) Pull-up Enable Register\r
-# define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418)
+# define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418)\r
// (PIOA) Output Status Register\r
-# define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470)
+# define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470)\r
// (PIOA) Select A Register\r
-# define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454)
+# define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454)\r
// (PIOA) Multi-driver Disable Register\r
-# define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434)
+# define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434)\r
// (PIOA) Clear Output Data Register\r
-# define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450)
+# define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450)\r
// (PIOA) Multi-driver Enable Register\r
-# define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404)
+# define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404)\r
// (PIOA) PIO Disable Register\r
-# define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428)
+# define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428)\r
// (PIOA) Input Filter Status Register\r
-# define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410)
+# define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410)\r
// (PIOA) Output Enable Register\r
-# define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408)
+# define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408)\r
// (PIOA) PIO Status Register\r
// ========== Register definition for CKGR peripheral ==========\r
-# define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20)
+# define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20)\r
// (CKGR) Main Oscillator Register\r
-# define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C)
+# define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C)\r
// (CKGR) PLL Register\r
-# define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24)
+# define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24)\r
// (CKGR) Main Clock Frequency Register\r
// ========== Register definition for PMC peripheral ==========\r
-# define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64)
+# define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64)\r
// (PMC) Interrupt Disable Register\r
-# define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20)
+# define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20)\r
// (PMC) Main Oscillator Register\r
-# define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C)
+# define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C)\r
// (PMC) PLL Register\r
-# define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10)
+# define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10)\r
// (PMC) Peripheral Clock Enable Register\r
-# define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40)
+# define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40)\r
// (PMC) Programmable Clock Register\r
-# define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30)
+# define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30)\r
// (PMC) Master Clock Register\r
-# define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04)
+# define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04)\r
// (PMC) System Clock Disable Register\r
-# define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14)
+# define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14)\r
// (PMC) Peripheral Clock Disable Register\r
-# define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08)
+# define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08)\r
// (PMC) System Clock Status Register\r
-# define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18)
+# define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18)\r
// (PMC) Peripheral Clock Status Register\r
-# define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24)
+# define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24)\r
// (PMC) Main Clock Frequency Register\r
-# define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00)
+# define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00)\r
// (PMC) System Clock Enable Register\r
-# define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C)
+# define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C)\r
// (PMC) Interrupt Mask Register\r
-# define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60)
+# define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60)\r
// (PMC) Interrupt Enable Register\r
-# define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68)
+# define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68)\r
// (PMC) Status Register\r
// ========== Register definition for RSTC peripheral ==========\r
-# define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00)
+# define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00)\r
// (RSTC) Reset Control Register\r
-# define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08)
+# define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08)\r
// (RSTC) Reset Mode Register\r
-# define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04)
+# define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04)\r
// (RSTC) Reset Status Register\r
// ========== Register definition for RTTC peripheral ==========\r
-# define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C)
+# define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C)\r
// (RTTC) Real-time Status Register\r
-# define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20)
+# define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20)\r
// (RTTC) Real-time Mode Register\r
-# define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28)
+# define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28)\r
// (RTTC) Real-time Value Register\r
-# define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24)
+# define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24)\r
// (RTTC) Real-time Alarm Register\r
// ========== Register definition for PITC peripheral ==========\r
-# define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38)
+# define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38)\r
// (PITC) Period Interval Value Register\r
-# define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34)
+# define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34)\r
// (PITC) Period Interval Status Register\r
-# define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C)
+# define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C)\r
// (PITC) Period Interval Image Register\r
-# define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30)
+# define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30)\r
// (PITC) Period Interval Mode Register\r
// ========== Register definition for WDTC peripheral ==========\r
-# define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40)
+# define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40)\r
// (WDTC) Watchdog Control Register\r
-# define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48)
+# define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48)\r
// (WDTC) Watchdog Status Register\r
-# define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44)
+# define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44)\r
// (WDTC) Watchdog Mode Register\r
// ========== Register definition for VREG peripheral ==========\r
-# define AT91C_VREG_MR ((AT91_REG *) 0xFFFFFD60)
+# define AT91C_VREG_MR ((AT91_REG *) 0xFFFFFD60)\r
// (VREG) Voltage Regulator Mode Register\r
// ========== Register definition for MC peripheral ==========\r
-# define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04)
+# define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04)\r
// (MC) MC Abort Status Register\r
-# define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00)
+# define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00)\r
// (MC) MC Remap Control Register\r
-# define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64)
+# define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64)\r
// (MC) MC Flash Command Register\r
-# define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08)
+# define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08)\r
// (MC) MC Abort Address Status Register\r
-# define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68)
+# define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68)\r
// (MC) MC Flash Status Register\r
-# define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60)
+# define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60)\r
// (MC) MC Flash Mode Register\r
// ========== Register definition for PDC_SPI peripheral ==========\r
-# define AT91C_SPI_PTCR ((AT91_REG *) 0xFFFE0120)
+# define AT91C_SPI_PTCR ((AT91_REG *) 0xFFFE0120)\r
// (PDC_SPI) PDC Transfer Control Register\r
-# define AT91C_SPI_TPR ((AT91_REG *) 0xFFFE0108)
+# define AT91C_SPI_TPR ((AT91_REG *) 0xFFFE0108)\r
// (PDC_SPI) Transmit Pointer Register\r
-# define AT91C_SPI_TCR ((AT91_REG *) 0xFFFE010C)
+# define AT91C_SPI_TCR ((AT91_REG *) 0xFFFE010C)\r
// (PDC_SPI) Transmit Counter Register\r
-# define AT91C_SPI_RCR ((AT91_REG *) 0xFFFE0104)
+# define AT91C_SPI_RCR ((AT91_REG *) 0xFFFE0104)\r
// (PDC_SPI) Receive Counter Register\r
-# define AT91C_SPI_PTSR ((AT91_REG *) 0xFFFE0124)
+# define AT91C_SPI_PTSR ((AT91_REG *) 0xFFFE0124)\r
// (PDC_SPI) PDC Transfer Status Register\r
-# define AT91C_SPI_RNPR ((AT91_REG *) 0xFFFE0110)
+# define AT91C_SPI_RNPR ((AT91_REG *) 0xFFFE0110)\r
// (PDC_SPI) Receive Next Pointer Register\r
-# define AT91C_SPI_RPR ((AT91_REG *) 0xFFFE0100)
+# define AT91C_SPI_RPR ((AT91_REG *) 0xFFFE0100)\r
// (PDC_SPI) Receive Pointer Register\r
-# define AT91C_SPI_TNCR ((AT91_REG *) 0xFFFE011C)
+# define AT91C_SPI_TNCR ((AT91_REG *) 0xFFFE011C)\r
// (PDC_SPI) Transmit Next Counter Register\r
-# define AT91C_SPI_RNCR ((AT91_REG *) 0xFFFE0114)
+# define AT91C_SPI_RNCR ((AT91_REG *) 0xFFFE0114)\r
// (PDC_SPI) Receive Next Counter Register\r
-# define AT91C_SPI_TNPR ((AT91_REG *) 0xFFFE0118)
+# define AT91C_SPI_TNPR ((AT91_REG *) 0xFFFE0118)\r
// (PDC_SPI) Transmit Next Pointer Register\r
// ========== Register definition for SPI peripheral ==========\r
-# define AT91C_SPI_IER ((AT91_REG *) 0xFFFE0014)
+# define AT91C_SPI_IER ((AT91_REG *) 0xFFFE0014)\r
// (SPI) Interrupt Enable Register\r
-# define AT91C_SPI_SR ((AT91_REG *) 0xFFFE0010)
+# define AT91C_SPI_SR ((AT91_REG *) 0xFFFE0010)\r
// (SPI) Status Register\r
-# define AT91C_SPI_IDR ((AT91_REG *) 0xFFFE0018)
+# define AT91C_SPI_IDR ((AT91_REG *) 0xFFFE0018)\r
// (SPI) Interrupt Disable Register\r
-# define AT91C_SPI_CR ((AT91_REG *) 0xFFFE0000)
+# define AT91C_SPI_CR ((AT91_REG *) 0xFFFE0000)\r
// (SPI) Control Register\r
-# define AT91C_SPI_MR ((AT91_REG *) 0xFFFE0004)
+# define AT91C_SPI_MR ((AT91_REG *) 0xFFFE0004)\r
// (SPI) Mode Register\r
-# define AT91C_SPI_IMR ((AT91_REG *) 0xFFFE001C)
+# define AT91C_SPI_IMR ((AT91_REG *) 0xFFFE001C)\r
// (SPI) Interrupt Mask Register\r
-# define AT91C_SPI_TDR ((AT91_REG *) 0xFFFE000C)
+# define AT91C_SPI_TDR ((AT91_REG *) 0xFFFE000C)\r
// (SPI) Transmit Data Register\r
-# define AT91C_SPI_RDR ((AT91_REG *) 0xFFFE0008)
+# define AT91C_SPI_RDR ((AT91_REG *) 0xFFFE0008)\r
// (SPI) Receive Data Register\r
-# define AT91C_SPI_CSR ((AT91_REG *) 0xFFFE0030)
+# define AT91C_SPI_CSR ((AT91_REG *) 0xFFFE0030)\r
// (SPI) Chip Select Register\r
// ========== Register definition for PDC_ADC peripheral ==========\r
-# define AT91C_ADC_PTSR ((AT91_REG *) 0xFFFD8124)
+# define AT91C_ADC_PTSR ((AT91_REG *) 0xFFFD8124)\r
// (PDC_ADC) PDC Transfer Status Register\r
-# define AT91C_ADC_PTCR ((AT91_REG *) 0xFFFD8120)
+# define AT91C_ADC_PTCR ((AT91_REG *) 0xFFFD8120)\r
// (PDC_ADC) PDC Transfer Control Register\r
-# define AT91C_ADC_TNPR ((AT91_REG *) 0xFFFD8118)
+# define AT91C_ADC_TNPR ((AT91_REG *) 0xFFFD8118)\r
// (PDC_ADC) Transmit Next Pointer Register\r
-# define AT91C_ADC_TNCR ((AT91_REG *) 0xFFFD811C)
+# define AT91C_ADC_TNCR ((AT91_REG *) 0xFFFD811C)\r
// (PDC_ADC) Transmit Next Counter Register\r
-# define AT91C_ADC_RNPR ((AT91_REG *) 0xFFFD8110)
+# define AT91C_ADC_RNPR ((AT91_REG *) 0xFFFD8110)\r
// (PDC_ADC) Receive Next Pointer Register\r
-# define AT91C_ADC_RNCR ((AT91_REG *) 0xFFFD8114)
+# define AT91C_ADC_RNCR ((AT91_REG *) 0xFFFD8114)\r
// (PDC_ADC) Receive Next Counter Register\r
-# define AT91C_ADC_RPR ((AT91_REG *) 0xFFFD8100)
+# define AT91C_ADC_RPR ((AT91_REG *) 0xFFFD8100)\r
// (PDC_ADC) Receive Pointer Register\r
-# define AT91C_ADC_TCR ((AT91_REG *) 0xFFFD810C)
+# define AT91C_ADC_TCR ((AT91_REG *) 0xFFFD810C)\r
// (PDC_ADC) Transmit Counter Register\r
-# define AT91C_ADC_TPR ((AT91_REG *) 0xFFFD8108)
+# define AT91C_ADC_TPR ((AT91_REG *) 0xFFFD8108)\r
// (PDC_ADC) Transmit Pointer Register\r
-# define AT91C_ADC_RCR ((AT91_REG *) 0xFFFD8104)
+# define AT91C_ADC_RCR ((AT91_REG *) 0xFFFD8104)\r
// (PDC_ADC) Receive Counter Register\r
// ========== Register definition for ADC peripheral ==========\r
-# define AT91C_ADC_CDR2 ((AT91_REG *) 0xFFFD8038)
+# define AT91C_ADC_CDR2 ((AT91_REG *) 0xFFFD8038)\r
// (ADC) ADC Channel Data Register 2\r
-# define AT91C_ADC_CDR3 ((AT91_REG *) 0xFFFD803C)
+# define AT91C_ADC_CDR3 ((AT91_REG *) 0xFFFD803C)\r
// (ADC) ADC Channel Data Register 3\r
-# define AT91C_ADC_CDR0 ((AT91_REG *) 0xFFFD8030)
+# define AT91C_ADC_CDR0 ((AT91_REG *) 0xFFFD8030)\r
// (ADC) ADC Channel Data Register 0\r
-# define AT91C_ADC_CDR5 ((AT91_REG *) 0xFFFD8044)
+# define AT91C_ADC_CDR5 ((AT91_REG *) 0xFFFD8044)\r
// (ADC) ADC Channel Data Register 5\r
-# define AT91C_ADC_CHDR ((AT91_REG *) 0xFFFD8014)
+# define AT91C_ADC_CHDR ((AT91_REG *) 0xFFFD8014)\r
// (ADC) ADC Channel Disable Register\r
-# define AT91C_ADC_SR ((AT91_REG *) 0xFFFD801C)
+# define AT91C_ADC_SR ((AT91_REG *) 0xFFFD801C)\r
// (ADC) ADC Status Register\r
-# define AT91C_ADC_CDR4 ((AT91_REG *) 0xFFFD8040)
+# define AT91C_ADC_CDR4 ((AT91_REG *) 0xFFFD8040)\r
// (ADC) ADC Channel Data Register 4\r
-# define AT91C_ADC_CDR1 ((AT91_REG *) 0xFFFD8034)
+# define AT91C_ADC_CDR1 ((AT91_REG *) 0xFFFD8034)\r
// (ADC) ADC Channel Data Register 1\r
-# define AT91C_ADC_LCDR ((AT91_REG *) 0xFFFD8020)
+# define AT91C_ADC_LCDR ((AT91_REG *) 0xFFFD8020)\r
// (ADC) ADC Last Converted Data Register\r
-# define AT91C_ADC_IDR ((AT91_REG *) 0xFFFD8028)
+# define AT91C_ADC_IDR ((AT91_REG *) 0xFFFD8028)\r
// (ADC) ADC Interrupt Disable Register\r
-# define AT91C_ADC_CR ((AT91_REG *) 0xFFFD8000)
+# define AT91C_ADC_CR ((AT91_REG *) 0xFFFD8000)\r
// (ADC) ADC Control Register\r
-# define AT91C_ADC_CDR7 ((AT91_REG *) 0xFFFD804C)
+# define AT91C_ADC_CDR7 ((AT91_REG *) 0xFFFD804C)\r
// (ADC) ADC Channel Data Register 7\r
-# define AT91C_ADC_CDR6 ((AT91_REG *) 0xFFFD8048)
+# define AT91C_ADC_CDR6 ((AT91_REG *) 0xFFFD8048)\r
// (ADC) ADC Channel Data Register 6\r
-# define AT91C_ADC_IER ((AT91_REG *) 0xFFFD8024)
+# define AT91C_ADC_IER ((AT91_REG *) 0xFFFD8024)\r
// (ADC) ADC Interrupt Enable Register\r
-# define AT91C_ADC_CHER ((AT91_REG *) 0xFFFD8010)
+# define AT91C_ADC_CHER ((AT91_REG *) 0xFFFD8010)\r
// (ADC) ADC Channel Enable Register\r
-# define AT91C_ADC_CHSR ((AT91_REG *) 0xFFFD8018)
+# define AT91C_ADC_CHSR ((AT91_REG *) 0xFFFD8018)\r
// (ADC) ADC Channel Status Register\r
-# define AT91C_ADC_MR ((AT91_REG *) 0xFFFD8004)
+# define AT91C_ADC_MR ((AT91_REG *) 0xFFFD8004)\r
// (ADC) ADC Mode Register\r
-# define AT91C_ADC_IMR ((AT91_REG *) 0xFFFD802C)
+# define AT91C_ADC_IMR ((AT91_REG *) 0xFFFD802C)\r
// (ADC) ADC Interrupt Mask Register\r
// ========== Register definition for PDC_SSC peripheral ==========\r
-# define AT91C_SSC_TNCR ((AT91_REG *) 0xFFFD411C)
+# define AT91C_SSC_TNCR ((AT91_REG *) 0xFFFD411C)\r
// (PDC_SSC) Transmit Next Counter Register\r
-# define AT91C_SSC_RPR ((AT91_REG *) 0xFFFD4100)
+# define AT91C_SSC_RPR ((AT91_REG *) 0xFFFD4100)\r
// (PDC_SSC) Receive Pointer Register\r
-# define AT91C_SSC_RNCR ((AT91_REG *) 0xFFFD4114)
+# define AT91C_SSC_RNCR ((AT91_REG *) 0xFFFD4114)\r
// (PDC_SSC) Receive Next Counter Register\r
-# define AT91C_SSC_TPR ((AT91_REG *) 0xFFFD4108)
+# define AT91C_SSC_TPR ((AT91_REG *) 0xFFFD4108)\r
// (PDC_SSC) Transmit Pointer Register\r
-# define AT91C_SSC_PTCR ((AT91_REG *) 0xFFFD4120)
+# define AT91C_SSC_PTCR ((AT91_REG *) 0xFFFD4120)\r
// (PDC_SSC) PDC Transfer Control Register\r
-# define AT91C_SSC_TCR ((AT91_REG *) 0xFFFD410C)
+# define AT91C_SSC_TCR ((AT91_REG *) 0xFFFD410C)\r
// (PDC_SSC) Transmit Counter Register\r
-# define AT91C_SSC_RCR ((AT91_REG *) 0xFFFD4104)
+# define AT91C_SSC_RCR ((AT91_REG *) 0xFFFD4104)\r
// (PDC_SSC) Receive Counter Register\r
-# define AT91C_SSC_RNPR ((AT91_REG *) 0xFFFD4110)
+# define AT91C_SSC_RNPR ((AT91_REG *) 0xFFFD4110)\r
// (PDC_SSC) Receive Next Pointer Register\r
-# define AT91C_SSC_TNPR ((AT91_REG *) 0xFFFD4118)
+# define AT91C_SSC_TNPR ((AT91_REG *) 0xFFFD4118)\r
// (PDC_SSC) Transmit Next Pointer Register\r
-# define AT91C_SSC_PTSR ((AT91_REG *) 0xFFFD4124)
+# define AT91C_SSC_PTSR ((AT91_REG *) 0xFFFD4124)\r
// (PDC_SSC) PDC Transfer Status Register\r
// ========== Register definition for SSC peripheral ==========\r
-# define AT91C_SSC_RHR ((AT91_REG *) 0xFFFD4020)
+# define AT91C_SSC_RHR ((AT91_REG *) 0xFFFD4020)\r
// (SSC) Receive Holding Register\r
-# define AT91C_SSC_RSHR ((AT91_REG *) 0xFFFD4030)
+# define AT91C_SSC_RSHR ((AT91_REG *) 0xFFFD4030)\r
// (SSC) Receive Sync Holding Register\r
-# define AT91C_SSC_TFMR ((AT91_REG *) 0xFFFD401C)
+# define AT91C_SSC_TFMR ((AT91_REG *) 0xFFFD401C)\r
// (SSC) Transmit Frame Mode Register\r
-# define AT91C_SSC_IDR ((AT91_REG *) 0xFFFD4048)
+# define AT91C_SSC_IDR ((AT91_REG *) 0xFFFD4048)\r
// (SSC) Interrupt Disable Register\r
-# define AT91C_SSC_THR ((AT91_REG *) 0xFFFD4024)
+# define AT91C_SSC_THR ((AT91_REG *) 0xFFFD4024)\r
// (SSC) Transmit Holding Register\r
-# define AT91C_SSC_RCMR ((AT91_REG *) 0xFFFD4010)
+# define AT91C_SSC_RCMR ((AT91_REG *) 0xFFFD4010)\r
// (SSC) Receive Clock ModeRegister\r
-# define AT91C_SSC_IER ((AT91_REG *) 0xFFFD4044)
+# define AT91C_SSC_IER ((AT91_REG *) 0xFFFD4044)\r
// (SSC) Interrupt Enable Register\r
-# define AT91C_SSC_TSHR ((AT91_REG *) 0xFFFD4034)
+# define AT91C_SSC_TSHR ((AT91_REG *) 0xFFFD4034)\r
// (SSC) Transmit Sync Holding Register\r
-# define AT91C_SSC_SR ((AT91_REG *) 0xFFFD4040)
+# define AT91C_SSC_SR ((AT91_REG *) 0xFFFD4040)\r
// (SSC) Status Register\r
-# define AT91C_SSC_CMR ((AT91_REG *) 0xFFFD4004)
+# define AT91C_SSC_CMR ((AT91_REG *) 0xFFFD4004)\r
// (SSC) Clock Mode Register\r
-# define AT91C_SSC_TCMR ((AT91_REG *) 0xFFFD4018)
+# define AT91C_SSC_TCMR ((AT91_REG *) 0xFFFD4018)\r
// (SSC) Transmit Clock Mode Register\r
-# define AT91C_SSC_CR ((AT91_REG *) 0xFFFD4000)
+# define AT91C_SSC_CR ((AT91_REG *) 0xFFFD4000)\r
// (SSC) Control Register\r
-# define AT91C_SSC_IMR ((AT91_REG *) 0xFFFD404C)
+# define AT91C_SSC_IMR ((AT91_REG *) 0xFFFD404C)\r
// (SSC) Interrupt Mask Register\r
-# define AT91C_SSC_RFMR ((AT91_REG *) 0xFFFD4014)
+# define AT91C_SSC_RFMR ((AT91_REG *) 0xFFFD4014)\r
// (SSC) Receive Frame Mode Register\r
// ========== Register definition for PDC_US1 peripheral ==========\r
-# define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114)
+# define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114)\r
// (PDC_US1) Receive Next Counter Register\r
-# define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120)
+# define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120)\r
// (PDC_US1) PDC Transfer Control Register\r
-# define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C)
+# define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C)\r
// (PDC_US1) Transmit Counter Register\r
-# define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124)
+# define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124)\r
// (PDC_US1) PDC Transfer Status Register\r
-# define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118)
+# define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118)\r
// (PDC_US1) Transmit Next Pointer Register\r
-# define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104)
+# define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104)\r
// (PDC_US1) Receive Counter Register\r
-# define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110)
+# define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110)\r
// (PDC_US1) Receive Next Pointer Register\r
-# define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100)
+# define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100)\r
// (PDC_US1) Receive Pointer Register\r
-# define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C)
+# define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C)\r
// (PDC_US1) Transmit Next Counter Register\r
-# define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108)
+# define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108)\r
// (PDC_US1) Transmit Pointer Register\r
// ========== Register definition for US1 peripheral ==========\r
-# define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C)
+# define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C)\r
// (US1) IRDA_FILTER Register\r
-# define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044)
+# define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044)\r
// (US1) Nb Errors Register\r
-# define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024)
+# define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024)\r
// (US1) Receiver Time-out Register\r
-# define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014)
+# define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014)\r
// (US1) Channel Status Register\r
-# define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C)
+# define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C)\r
// (US1) Interrupt Disable Register\r
-# define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008)
+# define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008)\r
// (US1) Interrupt Enable Register\r
-# define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C)
+# define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C)\r
// (US1) Transmitter Holding Register\r
-# define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028)
+# define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028)\r
// (US1) Transmitter Time-guard Register\r
-# define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018)
+# define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018)\r
// (US1) Receiver Holding Register\r
-# define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020)
+# define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020)\r
// (US1) Baud Rate Generator Register\r
-# define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010)
+# define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010)\r
// (US1) Interrupt Mask Register\r
-# define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040)
+# define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040)\r
// (US1) FI_DI_Ratio Register\r
-# define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000)
+# define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000)\r
// (US1) Control Register\r
-# define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004)
+# define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004)\r
// (US1) Mode Register\r
// ========== Register definition for PDC_US0 peripheral ==========\r
-# define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118)
+# define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118)\r
// (PDC_US0) Transmit Next Pointer Register\r
-# define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110)
+# define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110)\r
// (PDC_US0) Receive Next Pointer Register\r
-# define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C)
+# define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C)\r
// (PDC_US0) Transmit Counter Register\r
-# define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120)
+# define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120)\r
// (PDC_US0) PDC Transfer Control Register\r
-# define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124)
+# define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124)\r
// (PDC_US0) PDC Transfer Status Register\r
-# define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C)
+# define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C)\r
// (PDC_US0) Transmit Next Counter Register\r
-# define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108)
+# define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108)\r
// (PDC_US0) Transmit Pointer Register\r
-# define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104)
+# define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104)\r
// (PDC_US0) Receive Counter Register\r
-# define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100)
+# define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100)\r
// (PDC_US0) Receive Pointer Register\r
-# define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114)
+# define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114)\r
// (PDC_US0) Receive Next Counter Register\r
// ========== Register definition for US0 peripheral ==========\r
-# define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020)
+# define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020)\r
// (US0) Baud Rate Generator Register\r
-# define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044)
+# define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044)\r
// (US0) Nb Errors Register\r
-# define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000)
+# define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000)\r
// (US0) Control Register\r
-# define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010)
+# define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010)\r
// (US0) Interrupt Mask Register\r
-# define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040)
+# define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040)\r
// (US0) FI_DI_Ratio Register\r
-# define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028)
+# define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028)\r
// (US0) Transmitter Time-guard Register\r
-# define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004)
+# define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004)\r
// (US0) Mode Register\r
-# define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024)
+# define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024)\r
// (US0) Receiver Time-out Register\r
-# define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014)
+# define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014)\r
// (US0) Channel Status Register\r
-# define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018)
+# define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018)\r
// (US0) Receiver Holding Register\r
-# define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C)
+# define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C)\r
// (US0) Interrupt Disable Register\r
-# define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C)
+# define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C)\r
// (US0) Transmitter Holding Register\r
-# define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C)
+# define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C)\r
// (US0) IRDA_FILTER Register\r
-# define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008)
+# define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008)\r
// (US0) Interrupt Enable Register\r
// ========== Register definition for TWI peripheral ==========\r
-# define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024)
+# define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024)\r
// (TWI) Interrupt Enable Register\r
-# define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000)
+# define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000)\r
// (TWI) Control Register\r
-# define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020)
+# define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020)\r
// (TWI) Status Register\r
-# define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C)
+# define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C)\r
// (TWI) Interrupt Mask Register\r
-# define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034)
+# define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034)\r
// (TWI) Transmit Holding Register\r
-# define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028)
+# define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028)\r
// (TWI) Interrupt Disable Register\r
-# define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C)
+# define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C)\r
// (TWI) Internal Address Register\r
-# define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004)
+# define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004)\r
// (TWI) Master Mode Register\r
-# define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010)
+# define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010)\r
// (TWI) Clock Waveform Generator Register\r
-# define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030)
+# define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030)\r
// (TWI) Receive Holding Register\r
// ========== Register definition for TC0 peripheral ==========\r
-# define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020)
+# define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020)\r
// (TC0) Status Register\r
-# define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C)
+# define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C)\r
// (TC0) Register C\r
-# define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018)
+# define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018)\r
// (TC0) Register B\r
-# define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000)
+# define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000)\r
// (TC0) Channel Control Register\r
-# define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004)
+# define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004)\r
// (TC0) Channel Mode Register (Capture Mode / Waveform Mode)\r
-# define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024)
+# define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024)\r
// (TC0) Interrupt Enable Register\r
-# define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014)
+# define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014)\r
// (TC0) Register A\r
-# define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028)
+# define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028)\r
// (TC0) Interrupt Disable Register\r
-# define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010)
+# define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010)\r
// (TC0) Counter Value\r
-# define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C)
+# define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C)\r
// (TC0) Interrupt Mask Register\r
// ========== Register definition for TC1 peripheral ==========\r
-# define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058)
+# define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058)\r
// (TC1) Register B\r
-# define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040)
+# define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040)\r
// (TC1) Channel Control Register\r
-# define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064)
+# define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064)\r
// (TC1) Interrupt Enable Register\r
-# define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068)
+# define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068)\r
// (TC1) Interrupt Disable Register\r
-# define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060)
+# define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060)\r
// (TC1) Status Register\r
-# define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044)
+# define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044)\r
// (TC1) Channel Mode Register (Capture Mode / Waveform Mode)\r
-# define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054)
+# define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054)\r
// (TC1) Register A\r
-# define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C)
+# define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C)\r
// (TC1) Register C\r
-# define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C)
+# define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C)\r
// (TC1) Interrupt Mask Register\r
-# define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050)
+# define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050)\r
// (TC1) Counter Value\r
// ========== Register definition for TC2 peripheral ==========\r
-# define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084)
+# define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084)\r
// (TC2) Channel Mode Register (Capture Mode / Waveform Mode)\r
-# define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080)
+# define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080)\r
// (TC2) Channel Control Register\r
-# define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090)
+# define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090)\r
// (TC2) Counter Value\r
-# define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094)
+# define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094)\r
// (TC2) Register A\r
-# define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098)
+# define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098)\r
// (TC2) Register B\r
-# define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8)
+# define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8)\r
// (TC2) Interrupt Disable Register\r
-# define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC)
+# define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC)\r
// (TC2) Interrupt Mask Register\r
-# define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C)
+# define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C)\r
// (TC2) Register C\r
-# define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4)
+# define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4)\r
// (TC2) Interrupt Enable Register\r
-# define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0)
+# define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0)\r
// (TC2) Status Register\r
// ========== Register definition for TCB peripheral ==========\r
-# define AT91C_TCB_BMR ((AT91_REG *) 0xFFFA00C4)
+# define AT91C_TCB_BMR ((AT91_REG *) 0xFFFA00C4)\r
// (TCB) TC Block Mode Register\r
-# define AT91C_TCB_BCR ((AT91_REG *) 0xFFFA00C0)
+# define AT91C_TCB_BCR ((AT91_REG *) 0xFFFA00C0)\r
// (TCB) TC Block Control Register\r
// ========== Register definition for PWMC_CH3 peripheral ==========\r
# define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register\r
-# define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 0xFFFCC274)
+# define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 0xFFFCC274)\r
// (PWMC_CH3) Reserved\r
# define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register\r
# define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register\r
# define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register\r
# define AT91C_PWMC_CH3_CMR ((AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register\r
// ========== Register definition for PWMC_CH2 peripheral ==========\r
-# define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 0xFFFCC254)
+# define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 0xFFFCC254)\r
// (PWMC_CH2) Reserved\r
# define AT91C_PWMC_CH2_CMR ((AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register\r
# define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register\r
# define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register\r
# define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register\r
// ========== Register definition for PWMC_CH1 peripheral ==========\r
-# define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 0xFFFCC234)
+# define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 0xFFFCC234)\r
// (PWMC_CH1) Reserved\r
# define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register\r
# define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register\r
# define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register\r
# define AT91C_PWMC_CH1_CMR ((AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register\r
// ========== Register definition for PWMC_CH0 peripheral ==========\r
-# define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 0xFFFCC214)
+# define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 0xFFFCC214)\r
// (PWMC_CH0) Reserved\r
# define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register\r
# define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register\r
# define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register\r
# define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register\r
// ========== Register definition for PWMC peripheral ==========\r
-# define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014)
+# define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014)\r
// (PWMC) PWMC Interrupt Disable Register\r
-# define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008)
+# define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008)\r
// (PWMC) PWMC Disable Register\r
-# define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010)
+# define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010)\r
// (PWMC) PWMC Interrupt Enable Register\r
-# define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC)
+# define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC)\r
// (PWMC) PWMC Version Register\r
-# define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C)
+# define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C)\r
// (PWMC) PWMC Interrupt Status Register\r
-# define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C)
+# define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C)\r
// (PWMC) PWMC Status Register\r
-# define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018)
+# define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018)\r
// (PWMC) PWMC Interrupt Mask Register\r
-# define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000)
+# define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000)\r
// (PWMC) PWMC Mode Register\r
-# define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004)
+# define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004)\r
// (PWMC) PWMC Enable Register\r
// ========== Register definition for UDP peripheral ==========\r
-# define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018)
+# define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018)\r
// (UDP) Interrupt Mask Register\r
-# define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008)
+# define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008)\r
// (UDP) Function Address Register\r
-# define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000)
+# define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000)\r
// (UDP) Frame Number Register\r
-# define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050)
+# define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050)\r
// (UDP) Endpoint FIFO Data Register\r
-# define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C)
+# define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C)\r
// (UDP) Interrupt Status Register\r
-# define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030)
+# define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030)\r
// (UDP) Endpoint Control and Status Register\r
-# define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014)
+# define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014)\r
// (UDP) Interrupt Disable Register\r
-# define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020)
+# define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020)\r
// (UDP) Interrupt Clear Register\r
-# define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028)
+# define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028)\r
// (UDP) Reset Endpoint Register\r
-# define AT91C_UDP_TXVC ((AT91_REG *) 0xFFFB0074)
+# define AT91C_UDP_TXVC ((AT91_REG *) 0xFFFB0074)\r
// (UDP) Transceiver Control Register\r
# define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register\r
-# define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010)
+# define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010)\r
// (UDP) Interrupt Enable Register\r
\r
// *****************************************************************************\r
# define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ)\r
# define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral\r
# define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller\r
-# define AT91C_ID_3_Reserved ((unsigned int) 3)
+# define AT91C_ID_3_Reserved ((unsigned int) 3)\r
// Reserved\r
# define AT91C_ID_ADC ((unsigned int) 4) // Analog-to-Digital Converter\r
# define AT91C_ID_SPI ((unsigned int) 5) // Serial Peripheral Interface\r
# define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address\r
# define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address\r
# define AT91C_BASE_TCB ((AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address\r
-# define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260)
+# define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260)\r
// (PWMC_CH3) Base Address\r
-# define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240)
+# define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240)\r
// (PWMC_CH2) Base Address\r
-# define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220)
+# define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220)\r
// (PWMC_CH1) Base Address\r
-# define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200)
+# define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200)\r
// (PWMC_CH0) Base Address\r
# define AT91C_BASE_PWMC ((AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address\r
# define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address\r
-
+/**
+ * USB support for jeJOS.
+ * We use a mixture of interrupt driven and directly driven I/O. Interrupts
+ * are used for handling the configuration/enumeration phases, which allows
+ * us to respond quickly to events. For actual data transfer we drive the
+ * process directly thus removing the need top have data buffers available at
+ * interrupt time. As with other leJOS drivers we implement only a minimal
+ * set of functions in the firmware with as much as possible being done in
+ * Java. In the case of USB there are strict timing requirements so we
+ * perform all of the configuration and enumeration here.
+ * The leJOS implementation uses the standard Lego identifiers (and so can
+ * be used from the PC side applications that work with the standard Lego
+ * firmware).
+ */
+#include "types.h"
#include "mytypes.h"
#include "udp.h"
#include "interrupts.h"
-#include "at91sam7s256.h"
+#include "AT91SAM7.h"
#include "aic.h"
#include "systick.h"
#include "display.h"
+#include <string.h>
+//#include "rconsole.h"
-#define EP_OUT 1
-#define EP_IN 2
+#define MAX_BUF 64
+#define EP_OUT 1
+#define EP_IN 2
-#define AT91C_PERIPHERAL_ID_UDP 11
+#define AT91C_PERIPHERAL_ID_UDP 11
#define AT91C_UDP_CSR0 ((AT91_REG *) 0xFFFB0030)
#define AT91C_UDP_CSR1 ((AT91_REG *) 0xFFFB0034)
#define AT91C_UDP_FDR2 ((AT91_REG *) 0xFFFB0058)
#define AT91C_UDP_FDR3 ((AT91_REG *) 0xFFFB005C)
+// The following functions are used to set/clear bits in the control
+// register. This must be synchronized against the actual hardware.
+// Care must also be taken to avoid clearing bits that may have been
+// set by the hardware during the operation. The actual code comes
+// from the Atmel sample drivers.
+/// Bitmap for all status bits in CSR.
+#define AT91C_UDP_STALLSENT AT91C_UDP_ISOERROR
+#define REG_NO_EFFECT_1_ALL AT91C_UDP_RX_DATA_BK0 | AT91C_UDP_RX_DATA_BK1 \
+ |AT91C_UDP_STALLSENT | AT91C_UDP_RXSETUP \
+ |AT91C_UDP_TXCOMP
+
+/// Sets the specified bit(s) in the UDP_CSR register.
+/// \param endpoint The endpoint number of the CSR to process.
+/// \param flags The bitmap to set to 1.
+#define UDP_SETEPFLAGS(csr, flags) \
+ { \
+ volatile unsigned int reg; \
+ reg = (csr) ; \
+ reg |= REG_NO_EFFECT_1_ALL; \
+ reg |= (flags); \
+ do (csr) = reg; \
+ while ( ((csr) & (flags)) != (flags)); \
+ }
+
+/// Clears the specified bit(s) in the UDP_CSR register.
+/// \param endpoint The endpoint number of the CSR to process.
+/// \param flags The bitmap to clear to 0.
+#define UDP_CLEAREPFLAGS(csr, flags) \
+ { \
+ volatile unsigned int reg; \
+ reg = (csr); \
+ reg |= REG_NO_EFFECT_1_ALL; \
+ reg &= ~(flags); \
+ do (csr) = reg; \
+ while ( ((csr) & (flags)) != 0); \
+ }
+
+#define MIN(a, b) ((a) < (b) ? (a) : (b))
+
+// USB States
+#define USB_READY 0
+#define USB_CONFIGURED 1
+#define USB_SUSPENDED 2
+
+#define USB_DISABLED 0x8000
+#define USB_NEEDRESET 0x4000
+#define USB_WRITEABLE 0x100000
+#define USB_READABLE 0x200000
+
+// Critical section macros. Disable and enable interrupts
+#define ENTER() (*AT91C_UDP_IDR = (AT91C_UDP_EPINT0 | AT91C_UDP_RXSUSP | AT91C_UDP_RXRSM))
+#define LEAVE() (*AT91C_UDP_IER = (AT91C_UDP_EPINT0 | AT91C_UDP_RXSUSP | AT91C_UDP_RXRSM))
+
static U8 currentConfig;
-static unsigned currentConnection;
+static U32 currentFeatures;
static unsigned currentRxBank;
-static unsigned usbTimeOut;
-
+static int configured = (USB_DISABLED|USB_NEEDRESET);
+static int newAddress;
+static U8 *outPtr;
+static U32 outCnt;
+static U8 delayedEnable = 0;
+static U32 intCnt = 0;
+#if REMOTE_CONSOLE
+static U8 rConsole = 0;
+#endif
// Device descriptor
static const U8 dd[] = {
0x12,
// Serial Number Descriptor
static U8 snd[] =
{
- 0x1A,
- 0x03,
+ 0x1A, // Descriptor length
+ 0x03, // Descriptor type 3 == string
0x31, 0x00, // MSD of Lap (Lap[2,3]) in UNICode
0x32, 0x00, // Lap[4,5]
0x33, 0x00, // Lap[6,7]
0x30, 0x00 // LSD of Uap in UNICode
};
+// Name descriptor, we allow up to 16 unicode characters
+static U8 named[] =
+{
+ 0x08, // Descriptor length
+ 0x03, // Descriptor type 3 == string
+ 0x6e, 0x00, // n
+ 0x78, 0x00, // x
+ 0x74, 0x00, // t
+ 0x00, 0x00,
+ 0x00, 0x00,
+ 0x00, 0x00,
+ 0x00, 0x00,
+ 0x00, 0x00,
+ 0x00, 0x00,
+ 0x00, 0x00,
+ 0x00, 0x00,
+ 0x00, 0x00,
+ 0x00, 0x00,
+ 0x00, 0x00,
+ 0x00, 0x00,
+ 0x00, 0x00
+};
+
static const U8 ld[] = {0x04,0x03,0x09,0x04}; // Language descriptor
extern void udp_isr_entry(void);
-static int configured = 0;
-//static char x4[5];
-//static char* hexchars = "0123456789abcdef";
-
-/* supress a warning by GCC
+static char x4[5];
+static char* hexchars = "0123456789abcdef";
+
static char *
hex4(int i)
{
x4[4] = 0;
return x4;
}
-*/
+static
void
-udp_isr_C(void)
+reset()
{
+ // setup config state.
+ currentConfig = 0;
+ currentRxBank = AT91C_UDP_RX_DATA_BK0;
+ configured = (configured & USB_DISABLED) | USB_READY;
+ currentFeatures = 0;
+ newAddress = -1;
+ outCnt = 0;
+ delayedEnable = 0;
}
+
-void
-udp_check_interrupt()
+int
+udp_init(void)
{
- if (*AT91C_UDP_ISR & END_OF_BUS_RESET)
- {
- //display_goto_xy(0,0);
- //display_string("Bus Reset");
- //display_update();
- *AT91C_UDP_ICR = END_OF_BUS_RESET;
- *AT91C_UDP_ICR = SUSPEND_RESUME;
- *AT91C_UDP_ICR = WAKEUP;
- configured = 0;
- currentConfig = 0;
- *AT91C_UDP_RSTEP = 0xFFFFFFFF;
- *AT91C_UDP_RSTEP = 0x0;
- currentRxBank = AT91C_UDP_RX_DATA_BK0;
- *AT91C_UDP_FADDR = AT91C_UDP_FEN;
- *AT91C_UDP_CSR0 = (AT91C_UDP_EPEDS | AT91C_UDP_EPTYPE_CTRL);
- }
- else if (*AT91C_UDP_ISR & SUSPEND_INT)
- {
- //display_goto_xy(0,0);
- //display_string("Suspend");
- //display_update();
- if (configured == 1) configured = 2;
- else configured = 0;
- *AT91C_UDP_ICR = SUSPEND_INT;
- currentRxBank = AT91C_UDP_RX_DATA_BK0;
- }
- else if (*AT91C_UDP_ISR & SUSPEND_RESUME)
- {
- //display_goto_xy(0,0);
- //display_string("Resume");
- //display_update();
- if (configured == 2) configured = 1;
- else configured = 0;
- *AT91C_UDP_ICR = WAKEUP;
- *AT91C_UDP_ICR = SUSPEND_RESUME;
- }
- else if (*AT91C_UDP_ISR & AT91C_UDP_EPINT0)
- {
- *AT91C_UDP_ICR = AT91C_UDP_EPINT0;
- udp_enumerate();
- }
+ udp_disable();
+ configured = (USB_DISABLED|USB_NEEDRESET);
+ return 1;
}
-int
-udp_init(void)
+void
+udp_reset()
{
- //int i_state;
+ int i_state;
+
+ // We must be enabled
+ if (configured & USB_DISABLED) return;
+ // Take the hardware off line
+ *AT91C_PIOA_PER = (1 << 16);
+ *AT91C_PIOA_OER = (1 << 16);
+ *AT91C_PIOA_SODR = (1 << 16);
+ *AT91C_PMC_SCDR = AT91C_PMC_UDP;
+ *AT91C_PMC_PCDR = (1 << AT91C_ID_UDP);
+ systick_wait_ms(2);
+ // now bring it back online
+ i_state = interrupts_get_and_disable();
/* Make sure the USB PLL and clock are set up */
*AT91C_CKGR_PLLR |= AT91C_CKGR_USBDIV_1;
*AT91C_PMC_SCER = AT91C_PMC_UDP;
*AT91C_PMC_PCER = (1 << AT91C_ID_UDP);
+ *AT91C_UDP_FADDR = 0;
+ *AT91C_UDP_GLBSTATE = 0;
/* Enable the UDP pull up by outputting a zero on PA.16 */
*AT91C_PIOA_PER = (1 << 16);
*AT91C_PIOA_OER = (1 << 16);
*AT91C_PIOA_CODR = (1 << 16);
+ *AT91C_UDP_IDR = ~0;
/* Set up default state */
+ reset();
- currentConfig = 0;
- currentConnection = 0;
- currentRxBank = AT91C_UDP_RX_DATA_BK0;
-
- /*i_state = interrupts_get_and_disable();
-
- aic_mask_off(AT91C_PERIPHERAL_ID_UDP);
- aic_set_vector(AT91C_PERIPHERAL_ID_UDP, AIC_INT_LEVEL_NORMAL,
- (U32) udp_isr_entry);
- aic_mask_on(AT91C_PERIPHERAL_ID_UDP);
+ *AT91C_UDP_IER = (AT91C_UDP_EPINT0 | AT91C_UDP_RXSUSP | AT91C_UDP_RXRSM);
if (i_state)
- interrupts_enable(); */
-
- return 1;
-}
-
-void
-udp_close(U32 u)
-{
- /* Nothing */
-}
-
-void
-udp_disable()
-{
- *AT91C_PIOA_PER = (1 << 16);
- *AT91C_PIOA_OER = (1 << 16);
- *AT91C_PIOA_SODR = (1 << 16);
-}
-
-void
-udp_reset()
-{
- udp_disable();
- systick_wait_ms(1);
- udp_init();
-}
-
-int
-udp_short_timed_out()
-{
- return (USB_TIMEOUT <
- ((((*AT91C_PITC_PIIR) & AT91C_PITC_CPIV)
- - usbTimeOut) & AT91C_PITC_CPIV));
-}
-
-static int timeout_counter = 0;
-
-int
-udp_timed_out()
-{
- if(udp_short_timed_out())
- {
- timeout_counter++;
- udp_short_reset_timeout();
- }
- return (timeout_counter > 500);
-}
-
-void
-udp_reset_timeout()
-{
- timeout_counter = 0;
- udp_short_reset_timeout();
-}
-
-void
-udp_short_reset_timeout()
-{
- usbTimeOut = ((*AT91C_PITC_PIIR) & AT91C_PITC_CPIV);
+ interrupts_enable();
}
int
-udp_read(U8* buf, int len)
+udp_read(U8* buf, int off, int len)
{
+ /* Perform a non-blocking read operation. We use double buffering (ping-pong)
+ * operation to provide better throughput.
+ */
int packetSize = 0, i;
- if (udp_configured() != 1) return 0;
-
+ if (len == 0) return 0;
if ((*AT91C_UDP_CSR1) & currentRxBank) // data to read
{
- packetSize = (*AT91C_UDP_CSR1) >> 16;
- if (packetSize > len) packetSize = len;
-
- for(i=0;i<packetSize;i++) buf[i] = *AT91C_UDP_FDR1;
-
- *AT91C_UDP_CSR1 &= ~(currentRxBank);
-
- if (currentRxBank == AT91C_UDP_RX_DATA_BK0) {
+ packetSize = ((*AT91C_UDP_CSR1) & AT91C_UDP_RXBYTECNT) >> 16;
+ if (packetSize > len) packetSize = len;
+ // Transfer the data
+ for(i=0;i<packetSize;i++) buf[off+i] = *AT91C_UDP_FDR1;
+
+ // Flip bank
+ ENTER();
+ UDP_CLEAREPFLAGS(*AT91C_UDP_CSR1, currentRxBank);
+ if (currentRxBank == AT91C_UDP_RX_DATA_BK0) {
currentRxBank = AT91C_UDP_RX_DATA_BK1;
} else {
currentRxBank = AT91C_UDP_RX_DATA_BK0;
}
+ // We may have an enable/reset pending do it now if there is no data
+ // in the buffers.
+ if (delayedEnable && ((*AT91C_UDP_CSR1) & AT91C_UDP_RXBYTECNT) == 0)
+ {
+ delayedEnable = 0;
+ UDP_CLEAREPFLAGS(*AT91C_UDP_CSR1, AT91C_UDP_FORCESTALL);
+ (*AT91C_UDP_RSTEP) |= AT91C_UDP_EP1;
+ (*AT91C_UDP_RSTEP) &= ~AT91C_UDP_EP1;
+ }
+ LEAVE();
+
+ // use special case for a real zero length packet so we can use it to
+ // indicate EOF
+ if (packetSize == 0) return -2;
+ return packetSize;
}
- return packetSize;
+ if (configured != USB_CONFIGURED) return -1;
+ return 0;
}
-void
-udp_write(U8* buf, int len)
+int
+udp_write(U8* buf, int off, int len)
{
+ /* Perform a non-blocking write. Return the number of bytes actually
+ * written.
+ */
int i;
- if (configured != 1) return;
-
- for(i=0;i<len;i++) *AT91C_UDP_FDR2 = buf[i];
-
- *AT91C_UDP_CSR2 |= AT91C_UDP_TXPKTRDY;
-
- udp_reset_timeout();
+ if (configured != USB_CONFIGURED) return -1;
+ // Can we write ?
+ if ((*AT91C_UDP_CSR2 & AT91C_UDP_TXPKTRDY) != 0) return 0;
+ // Limit to max transfer size
+ if (len > MAX_BUF) len = MAX_BUF;
+ for(i=0;i<len;i++) *AT91C_UDP_FDR2 = buf[off+i];
- while ( !((*AT91C_UDP_CSR2) & AT91C_UDP_TXCOMP) )
- if (udp_configured() != 1 || udp_timed_out()) return;
-
- (*AT91C_UDP_CSR2) &= ~(AT91C_UDP_TXCOMP);
-
- while ((*AT91C_UDP_CSR2) & AT91C_UDP_TXCOMP);
+ ENTER();
+ UDP_SETEPFLAGS(*AT91C_UDP_CSR2, AT91C_UDP_TXPKTRDY);
+ UDP_CLEAREPFLAGS(*AT91C_UDP_CSR2, AT91C_UDP_TXCOMP);
+ LEAVE();
+ return len;
}
+static
void
udp_send_null()
{
- (*AT91C_UDP_CSR0) |= AT91C_UDP_TXPKTRDY;
-
- udp_reset_timeout();
-
- while ( !((*AT91C_UDP_CSR0) & AT91C_UDP_TXCOMP) && !udp_timed_out());
-
- (*AT91C_UDP_CSR0) &= ~(AT91C_UDP_TXCOMP);
- while ((*AT91C_UDP_CSR0) & AT91C_UDP_TXCOMP);
+ UDP_SETEPFLAGS(*AT91C_UDP_CSR0, AT91C_UDP_TXPKTRDY);
}
-void udp_send_stall()
+static void udp_send_stall()
{
- (*AT91C_UDP_CSR0) |= AT91C_UDP_FORCESTALL;
- while ( !((*AT91C_UDP_CSR0) & AT91C_UDP_ISOERROR) );
-
- (*AT91C_UDP_CSR0) &= ~(AT91C_UDP_FORCESTALL | AT91C_UDP_ISOERROR);
- while ((*AT91C_UDP_CSR0) & (AT91C_UDP_FORCESTALL | AT91C_UDP_ISOERROR));
-}
-
-void udp_send_control(U8* p, int len, int send_null)
-{
- int i = 0, j, tmp;
-
- do
- {
- // send 8 bytes or less
-
- for(j=0;j<8 && i<len;j++)
- {
- *AT91C_UDP_FDR0 = p[i++];
- }
-
- // Packet ready to send
-
- (*AT91C_UDP_CSR0) |= AT91C_UDP_TXPKTRDY;
- udp_reset_timeout();
-
- do
- {
- tmp = (*AT91C_UDP_CSR0);
-
- if (tmp & AT91C_UDP_RX_DATA_BK0)
- {
-
- (*AT91C_UDP_CSR0) &= ~(AT91C_UDP_TXPKTRDY);
-
- (*AT91C_UDP_CSR0) &= ~(AT91C_UDP_RX_DATA_BK0);
- return;
- }
- }
- while (!(tmp & AT91C_UDP_TXCOMP) && !udp_timed_out());
-
- (*AT91C_UDP_CSR0) &= ~(AT91C_UDP_TXCOMP);
-
- while ((*AT91C_UDP_CSR0) & AT91C_UDP_TXCOMP);
-
- }
- while (i < len);
- // If needed send the null terminating data
- if (send_null) udp_send_null();
- udp_reset_timeout();
-
- while(!((*AT91C_UDP_CSR0) & AT91C_UDP_RX_DATA_BK0) && !udp_timed_out());
-
- (*AT91C_UDP_CSR0) &= ~(AT91C_UDP_RX_DATA_BK0);
-
+ UDP_SETEPFLAGS(*AT91C_UDP_CSR0, AT91C_UDP_FORCESTALL);
}
-int
-udp_configured()
+static void udp_send_control(U8* p, int len)
{
- udp_check_interrupt();
- /*display_goto_xy(0,7);
- display_int(configured,1);
- display_update();*/
- return configured;
+ outPtr = p;
+ outCnt = len;
+ int i;
+ // Start sending the first part of the data...
+ for(i=0;i<8 && i<outCnt;i++)
+ *AT91C_UDP_FDR0 = outPtr[i];
+ UDP_SETEPFLAGS(*AT91C_UDP_CSR0, AT91C_UDP_TXPKTRDY);
}
-
+
+static
void
udp_enumerate()
{
U8 bt, br;
int req, len, ind, val;
short status;
+ //display_goto_xy(8,3);
+ //display_string(hex4(*AT91C_UDP_CSR0));
+ //display_goto_xy(12,3);
+ //display_string(" ");
+ // First we deal with any completion states.
+ if ((*AT91C_UDP_CSR0) & AT91C_UDP_TXCOMP)
+ {
+ // Write operation has completed.
+ // Send config data if needed. Send a zero length packet to mark the
+ // end of the data if an exact multiple of 8.
+ if (outCnt >= 8)
+ {
+ outCnt -= 8;
+ outPtr += 8;
+ int i;
+ // Send next part of the data
+ for(i=0;i<8 && i<outCnt;i++)
+ *AT91C_UDP_FDR0 = outPtr[i];
+ UDP_SETEPFLAGS(*AT91C_UDP_CSR0, AT91C_UDP_TXPKTRDY);
+ }
+ else
+ outCnt = 0;
+
+
+ // Clear the state
+ UDP_CLEAREPFLAGS(*AT91C_UDP_CSR0, AT91C_UDP_TXCOMP);
+ if (newAddress >= 0)
+ {
+ // Set new address
+ *AT91C_UDP_FADDR = (AT91C_UDP_FEN | newAddress);
+ *AT91C_UDP_GLBSTATE = (newAddress) ? AT91C_UDP_FADDEN : 0;
+ newAddress = -1;
+ }
+ }
+ if ((*AT91C_UDP_CSR0) & (AT91C_UDP_RX_DATA_BK0))
+ {
+ // Got Transfer complete ack
+ // Clear the state
+ UDP_CLEAREPFLAGS(*AT91C_UDP_CSR0, AT91C_UDP_RX_DATA_BK0);
+ }
+ if (*AT91C_UDP_CSR0 & AT91C_UDP_ISOERROR)
+ {
+ // Clear the state
+ UDP_CLEAREPFLAGS(*AT91C_UDP_CSR0, (AT91C_UDP_ISOERROR|AT91C_UDP_FORCESTALL));
+ }
+
+ //display_goto_xy(12,3);
+ //display_string("E1");
+
if (!((*AT91C_UDP_CSR0) & AT91C_UDP_RXSETUP)) return;
bt = *AT91C_UDP_FDR0;
if (bt & 0x80)
{
- *AT91C_UDP_CSR0 |= AT91C_UDP_DIR;
- while ( !((*AT91C_UDP_CSR0) & AT91C_UDP_DIR) );
+ UDP_SETEPFLAGS(*AT91C_UDP_CSR0, AT91C_UDP_DIR);
}
- *AT91C_UDP_CSR0 &= ~AT91C_UDP_RXSETUP;
- while ( ((*AT91C_UDP_CSR0) & AT91C_UDP_RXSETUP) );
+ UDP_CLEAREPFLAGS(*AT91C_UDP_CSR0, AT91C_UDP_RXSETUP);
req = br << 8 | bt;
-
- /*
+ /*
if (1) {
- display_goto_xy(0,0);
+
+ display_goto_xy(0,1);
display_string(hex4(req));
- display_goto_xy(4,0);
+ display_goto_xy(4,1);
display_string(hex4(val));
- display_goto_xy(8,0);
+ display_goto_xy(8,1);
display_string(hex4(ind));
- display_goto_xy(12,0);
+ display_goto_xy(12,1);
display_string(hex4(len));
- display_goto_xy(0,1);
- display_string(" ");
display_update();
+ }*/
+ // If we are disabled we respond to requests with a stall
+ if (configured & USB_DISABLED)
+ {
+ udp_send_stall();
+ return;
}
- */
-
switch(req)
{
case STD_GET_DESCRIPTOR:
if (val == 0x100) // Get device descriptor
{
- udp_send_control((U8 *)dd, sizeof(dd), 0);
+ udp_send_control((U8 *)dd, MIN(sizeof(dd), len));
}
else if (val == 0x200) // Configuration descriptor
{
- udp_send_control((U8 *)cfd, (len < sizeof(cfd) ? len : sizeof(cfd)), (len > sizeof(cfd) ? 1 : 0));
+ udp_send_control((U8 *)cfd, MIN(sizeof(cfd), len));
//if (len > sizeof(cfd)) udp_send_null();
- }
+ }
else if ((val & 0xF00) == 0x300)
{
switch(val & 0xFF)
{
case 0x00:
- udp_send_control((U8 *)ld, sizeof(ld), 0);
+ udp_send_control((U8 *)ld, MIN(sizeof(ld), len));
break;
case 0x01:
- udp_send_control(snd, sizeof(snd), 0);
+ udp_send_control(snd, MIN(sizeof(snd), len));
break;
default:
- udp_send_stall();
+ udp_send_stall();
}
}
else
break;
case STD_SET_ADDRESS:
-
- (*AT91C_UDP_CSR0) |= AT91C_UDP_TXPKTRDY;
-
- udp_reset_timeout();
-
- while(((*AT91C_UDP_CSR0) & AT91C_UDP_TXPKTRDY) && !udp_timed_out());
-
- *AT91C_UDP_FADDR = (AT91C_UDP_FEN | val);
-
- *AT91C_UDP_GLBSTATE = (val) ? AT91C_UDP_FADDEN : 0;
-
+ newAddress = val;
+ udp_send_null();
break;
case STD_SET_CONFIGURATION:
- configured = 1;
currentConfig = val;
+ if (val)
+ {
+ configured = USB_CONFIGURED;
+ *AT91C_UDP_GLBSTATE = AT91C_UDP_CONFG;
+ delayedEnable = 0;
+ // Make sure we are not stalled
+ UDP_CLEAREPFLAGS(*AT91C_UDP_CSR1, AT91C_UDP_FORCESTALL);
+ UDP_CLEAREPFLAGS(*AT91C_UDP_CSR2, AT91C_UDP_FORCESTALL);
+ UDP_CLEAREPFLAGS(*AT91C_UDP_CSR3, AT91C_UDP_FORCESTALL);
+ // Now enable the endpoints
+ UDP_SETEPFLAGS(*AT91C_UDP_CSR1, (AT91C_UDP_EPEDS | AT91C_UDP_EPTYPE_BULK_OUT));
+ UDP_SETEPFLAGS(*AT91C_UDP_CSR2, (AT91C_UDP_EPEDS | AT91C_UDP_EPTYPE_BULK_IN));
+ UDP_SETEPFLAGS(*AT91C_UDP_CSR3, AT91C_UDP_EPTYPE_INT_IN);
+ // and reset them...
+ (*AT91C_UDP_RSTEP) |= (AT91C_UDP_EP1|AT91C_UDP_EP2|AT91C_UDP_EP3);
+ (*AT91C_UDP_RSTEP) &= ~(AT91C_UDP_EP1|AT91C_UDP_EP2|AT91C_UDP_EP3);
+ }
+ else
+ {
+ configured = USB_READY;
+ *AT91C_UDP_GLBSTATE = AT91C_UDP_FADDEN;
+ delayedEnable = 0;
+ UDP_CLEAREPFLAGS(*AT91C_UDP_CSR1, AT91C_UDP_EPEDS|AT91C_UDP_FORCESTALL);
+ UDP_CLEAREPFLAGS(*AT91C_UDP_CSR2, AT91C_UDP_EPEDS|AT91C_UDP_FORCESTALL);
+ *AT91C_UDP_CSR3 = 0;
+ }
udp_send_null();
- *AT91C_UDP_GLBSTATE = (val) ? AT91C_UDP_CONFG : AT91C_UDP_FADDEN;
-
- *AT91C_UDP_CSR1 = (val) ? (AT91C_UDP_EPEDS | AT91C_UDP_EPTYPE_BULK_OUT) : 0;
- *AT91C_UDP_CSR2 = (val) ? (AT91C_UDP_EPEDS | AT91C_UDP_EPTYPE_BULK_IN) : 0;
- *AT91C_UDP_CSR3 = (val) ? (AT91C_UDP_EPTYPE_INT_IN) : 0;
break;
{
switch (ind)
{
- case 1:
- (*AT91C_UDP_CSR1) = 0;
+ case 1:
+ UDP_SETEPFLAGS(*AT91C_UDP_CSR1, AT91C_UDP_FORCESTALL);
+ delayedEnable = 0;
break;
case 2:
- (*AT91C_UDP_CSR2) = 0;
+ UDP_SETEPFLAGS(*AT91C_UDP_CSR2, AT91C_UDP_FORCESTALL);
break;
case 3:
- (*AT91C_UDP_CSR3) = 0;
+ UDP_SETEPFLAGS(*AT91C_UDP_CSR3, AT91C_UDP_FORCESTALL);
break;
}
udp_send_null();
ind &= 0x0F;
if ((val == 0) && ind && (ind <= 3))
- {
- if (ind == 1) {
- (*AT91C_UDP_CSR1) = (AT91C_UDP_EPEDS | AT91C_UDP_EPTYPE_BULK_OUT);
- (*AT91C_UDP_RSTEP) |= AT91C_UDP_EP1;
- (*AT91C_UDP_RSTEP) &= ~AT91C_UDP_EP1;
- } else if (ind == 2) {
- (*AT91C_UDP_CSR2) = (AT91C_UDP_EPEDS | AT91C_UDP_EPTYPE_BULK_IN);
- (*AT91C_UDP_RSTEP) |= AT91C_UDP_EP2;
- (*AT91C_UDP_RSTEP) &= ~AT91C_UDP_EP2;
- } else if (ind == 3) {
- (*AT91C_UDP_CSR3) = (AT91C_UDP_EPEDS | AT91C_UDP_EPTYPE_INT_IN);
- (*AT91C_UDP_RSTEP) |= AT91C_UDP_EP3;
- (*AT91C_UDP_RSTEP) &= ~AT91C_UDP_EP3;
+ {
+ // Enable and reset the end point
+ int res = 0;
+ switch (ind)
+ {
+ case 1:
+ // We need to take special care for the input end point because
+ // we may have data in the hardware buffer. If we do then the reset
+ // will cause this to be lost. To prevent this loss we delay the
+ // enable until the data has been read.
+ if ((*AT91C_UDP_CSR1) & currentRxBank)
+ {
+ UDP_SETEPFLAGS(*AT91C_UDP_CSR1, AT91C_UDP_FORCESTALL);
+ delayedEnable = 1;
+ }
+ else
+ {
+ UDP_CLEAREPFLAGS(*AT91C_UDP_CSR1, AT91C_UDP_FORCESTALL);
+ delayedEnable = 0;
+ res = AT91C_UDP_EP1;
+ }
+ break;
+ case 2:
+ UDP_CLEAREPFLAGS(*AT91C_UDP_CSR2, AT91C_UDP_FORCESTALL);
+ res = AT91C_UDP_EP2;
+ break;
+ case 3:
+ UDP_CLEAREPFLAGS(*AT91C_UDP_CSR3, AT91C_UDP_FORCESTALL);
+ res = AT91C_UDP_EP3;
+ break;
}
+ (*AT91C_UDP_RSTEP) |= res;
+ (*AT91C_UDP_RSTEP) &= ~res;
udp_send_null();
}
else udp_send_stall();
case STD_GET_CONFIGURATION:
- udp_send_control((U8 *) &(currentConfig), sizeof(currentConfig), 0);
+ udp_send_control((U8 *) &(currentConfig), MIN(sizeof(currentConfig), len));
break;
case STD_GET_STATUS_ZERO:
status = 0x01;
- udp_send_control((U8 *) &status, sizeof(status), 0);
+ udp_send_control((U8 *) &status, MIN(sizeof(status), len));
break;
case STD_GET_STATUS_INTERFACE:
status = 0;
- udp_send_control((U8 *) &status, sizeof(status), 0);
+ udp_send_control((U8 *) &status, MIN(sizeof(status), len));
break;
case STD_GET_STATUS_ENDPOINT:
switch (ind)
{
case 1:
- status = ((*AT91C_UDP_CSR1) & AT91C_UDP_EPEDS) ? 0 : 1;
+ status = ((*AT91C_UDP_CSR1) & AT91C_UDP_FORCESTALL) ? 1 : 0;
break;
case 2:
- status = ((*AT91C_UDP_CSR2) & AT91C_UDP_EPEDS) ? 0 : 1;
+ status = ((*AT91C_UDP_CSR2) & AT91C_UDP_FORCESTALL) ? 1 : 0;
break;
case 3:
- status = ((*AT91C_UDP_CSR3) & AT91C_UDP_EPEDS) ? 0 : 1;
+ status = ((*AT91C_UDP_CSR3) & AT91C_UDP_FORCESTALL) ? 1 : 0;
break;
}
- udp_send_control((U8 *) &status, sizeof(status), 0);
+ udp_send_control((U8 *) &status, MIN(sizeof(status), len));
}
else if (((*AT91C_UDP_GLBSTATE) & AT91C_UDP_FADDEN) && (ind == 0))
{
status = ((*AT91C_UDP_CSR0) & AT91C_UDP_EPEDS) ? 0 : 1;
- udp_send_control((U8 *) &status, sizeof(status), 0);
+ udp_send_control((U8 *) &status, MIN(sizeof(status), len));
}
else udp_send_stall(); // Illegal request :-(
break;
+ case VENDOR_SET_FEATURE_INTERFACE:
+ ind &= 0xf;
+ currentFeatures |= (1 << ind);
+ udp_send_null();
+ break;
+ case VENDOR_CLEAR_FEATURE_INTERFACE:
+ ind &= 0xf;
+ currentFeatures &= ~(1 << ind);
+ udp_send_null();
+ break;
+ case VENDOR_GET_DESCRIPTOR:
+ udp_send_control((U8 *)named, MIN(named[0], len));
+ break;
+
case STD_SET_FEATURE_INTERFACE:
case STD_CLEAR_FEATURE_INTERFACE:
udp_send_null();
break;
-
case STD_SET_INTERFACE:
case STD_SET_FEATURE_ZERO:
case STD_CLEAR_FEATURE_ZERO:
default:
udp_send_stall();
}
+ //display_goto_xy(14,3);
+ //display_string("E2");
+}
+
+void
+udp_isr_C(void)
+{
+ /* Process interrupts. We mainly use these during the configuration and
+ * enumeration stages.
+ */
+/*display_goto_xy(0,3);
+display_string(hex4(*AT91C_UDP_ISR));
+display_goto_xy(4,3);
+display_string(hex4(intCnt++));*/
+
+ if (*AT91C_UDP_ISR & END_OF_BUS_RESET)
+ {
+ //display_goto_xy(0,2);
+ //display_string("Bus Reset ");
+ //display_update();
+ *AT91C_UDP_ICR = END_OF_BUS_RESET;
+ *AT91C_UDP_ICR = SUSPEND_RESUME;
+ *AT91C_UDP_ICR = WAKEUP;
+ *AT91C_UDP_RSTEP = 0xFFFFFFFF;
+ *AT91C_UDP_RSTEP = 0x0;
+ *AT91C_UDP_FADDR = AT91C_UDP_FEN;
+ reset();
+ UDP_SETEPFLAGS(*AT91C_UDP_CSR0,(AT91C_UDP_EPEDS | AT91C_UDP_EPTYPE_CTRL));
+ *AT91C_UDP_IER = (AT91C_UDP_EPINT0 | AT91C_UDP_RXSUSP | AT91C_UDP_RXRSM);
+ //display_goto_xy(12,2);
+ //display_string("IE1");
+ return;
+ }
+ if (*AT91C_UDP_ISR & SUSPEND_INT)
+ {
+ //display_goto_xy(0,2);
+ //display_string("Suspend ");
+ //display_update();
+ if ((configured & ~USB_DISABLED) == USB_CONFIGURED)
+ configured = (configured & USB_DISABLED) | USB_SUSPENDED;
+ else
+ configured = (configured & USB_DISABLED) | USB_READY;
+ *AT91C_UDP_ICR = SUSPEND_INT;
+ currentRxBank = AT91C_UDP_RX_DATA_BK0;
+ }
+ if (*AT91C_UDP_ISR & SUSPEND_RESUME)
+ {
+ //display_goto_xy(0,2);
+ //display_string("Resume ");
+ //display_update();
+ if ((configured & ~USB_DISABLED) == USB_SUSPENDED)
+ configured = (configured & USB_DISABLED) | USB_CONFIGURED;
+ else
+ configured = (configured & USB_DISABLED) | USB_READY;
+ *AT91C_UDP_ICR = WAKEUP;
+ *AT91C_UDP_ICR = SUSPEND_RESUME;
+ }
+ if (*AT91C_UDP_ISR & AT91C_UDP_EPINT0)
+ {
+ //display_goto_xy(0,2);
+ //display_string("Data ");
+ //display_update();
+ *AT91C_UDP_ICR = AT91C_UDP_EPINT0;
+ udp_enumerate();
+ }
+ //display_goto_xy(12,2);
+ //display_string("IE2");
+}
+
+int
+udp_status()
+{
+ /* Return the current status of the USB connection. This information
+ * can be used to determine if the connection can be used. We return
+ * the connected state, the currently selected configuration and
+ * the currenly active features. This latter item is used by co-operating
+ * software on the PC and nxt to indicate the start and end of a stream
+ * connection.
+ */
+ int ret = (configured << 28) | (currentConfig << 24) | (currentFeatures & 0xffff);
+
+ if (configured == USB_CONFIGURED)
+ {
+ if ((*AT91C_UDP_CSR1) & currentRxBank) ret |= USB_READABLE;
+ if ((*AT91C_UDP_CSR2 & AT91C_UDP_TXPKTRDY) == 0) ret |= USB_WRITEABLE;
+ }
+ return ret;
}
+void
+udp_enable(int reset)
+{
+ /* Enable the processing of USB requests. */
+ /* Initialise the interrupt handler. We use a very low priority becuase
+ * some of the USB operations can run for a relatively long time...
+ */
+ if (reset & 0x2)
+ {
+#if REMOTE_CONSOLE
+ rConsole = 1;
+ printf("Firmware output enabled\n");
+#endif
+ return;
+ }
+
+ int i_state = interrupts_get_and_disable();
+ aic_mask_off(AT91C_PERIPHERAL_ID_UDP);
+ aic_set_vector(AT91C_PERIPHERAL_ID_UDP, AIC_INT_LEVEL_LOWEST,
+ (U32) udp_isr_entry);
+ aic_mask_on(AT91C_PERIPHERAL_ID_UDP);
+ *AT91C_UDP_IER = (AT91C_UDP_EPINT0 | AT91C_UDP_RXSUSP | AT91C_UDP_RXRSM);
+ reset = reset || (configured & USB_NEEDRESET);
+ configured &= ~USB_DISABLED;
+ if (i_state)
+ interrupts_enable();
+ if (reset)
+ udp_reset();
+}
+void
+udp_disable()
+{
+ /* Disable processing of USB requests */
+ U8 buf[MAX_BUF];
+ // Discard any input
+ while (udp_read(buf, 0, sizeof(buf)) > 0)
+ ;
+ int i_state = interrupts_get_and_disable();
+ configured |= USB_DISABLED;
+ currentFeatures = 0;
+ if (i_state)
+ interrupts_enable();
+#if REMOTE_CONSOLE
+ rConsole = 0;
+#endif
+}
+void
+udp_set_serialno(U8 *serNo, int len)
+{
+ /* Set the USB serial number. serNo should point to a 12 character
+ * Unicode string, containing the USB serial number.
+ */
+ if (len == (sizeof(snd)-2)/2)
+ memcpy(snd+2, serNo, len*2);
+}
+void
+udp_set_name(U8 *name, int len)
+{
+ if (len <= (sizeof(named)-2)/2)
+ {
+ memcpy(named+2, name, len*2);
+ named[0] = len*2 + 2;
+ }
+}
+#if REMOTE_CONSOLE
+void
+udp_rconsole(U8 *buf, int cnt)
+{
+ if (!rConsole) return;
+ while (udp_write(buf, 0, cnt) == 0)
+ ;
+}
+#endif
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