From edc7838532f50719bbdbf3b69b7cea7fd5962409 Mon Sep 17 00:00:00 2001 From: rsandifo Date: Mon, 15 Dec 2008 21:10:00 +0000 Subject: [PATCH] gcc/ * config/mips/mips.md (move_doubleword_fpr): Use TARGET_FLOAT64 && !TARGET_64BIT to detect the mxhc1 case. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@142769 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog | 5 +++++ gcc/config/mips/mips.md | 6 +++--- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index a5314980c24..aeed7051e48 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2008-12-15 Richard Sandiford + + * config/mips/mips.md (move_doubleword_fpr): Use + TARGET_FLOAT64 && !TARGET_64BIT to detect the mxhc1 case. + 2008-12-15 Hariharan Sandanagobalane * config/picochip/picochip.c (picochip_override_options): Disable CFI diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 1b26f029853..5a06cdc7e71 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -4521,8 +4521,8 @@ rtx low = mips_subword (operands[1], 0); rtx high = mips_subword (operands[1], 1); emit_insn (gen_load_low (operands[0], low)); - if (ISA_HAS_MXHC1 && reg_or_0_operand (high, mode)) - emit_insn (gen_mthc1 (operands[0], high, operands[0])); + if (TARGET_FLOAT64 && !TARGET_64BIT) + emit_insn (gen_mthc1 (operands[0], high, operands[0])); else emit_insn (gen_load_high (operands[0], high, operands[0])); } @@ -4531,7 +4531,7 @@ rtx low = mips_subword (operands[0], 0); rtx high = mips_subword (operands[0], 1); emit_insn (gen_store_word (low, operands[1], const0_rtx)); - if (ISA_HAS_MXHC1 && register_operand (high, mode)) + if (TARGET_FLOAT64 && !TARGET_64BIT) emit_insn (gen_mfhc1 (high, operands[1])); else emit_insn (gen_store_word (high, operands[1], const1_rtx)); -- 2.11.0