From 2ae7d678ca3f0abb2d4e49bff730cca5e5f24b9d Mon Sep 17 00:00:00 2001
From: hubicka <hubicka@138bc75d-0d04-0410-961f-82ee72b054a4>
Date: Tue, 27 Jun 2000 10:24:38 +0000
Subject: [PATCH] 	* genattrtab.c (write_attr_value): Do not abort for
 CONST_INT operands. 	* i386.c (ix86_attr_length_default): Kill. 
 (ix86_attr_length_immediate_default, ix86_attr_length_address_default): 
 New. 	* i386-protos.h (ix86_attr_length_default): Kill 
 (ix86_attr_length_immediate_default, ix86_attr_length_address_default): 
 Add prototype 	* i386.md (attribute type): Add "test". 	(attribute
 length_prefix): Kill. 	(attribute length_opcode): Kill. 	(attribute
 i387, mode, length_immediate, length_address, prefix_data16, 	prefix_rep,
 prefix_0f, modrm): New. 	(attribute length): Compute using the new
 attributes. 	(attribute pent_prefix): New. 	(attribute pent_pair): Compute
 using pent_prefix. 	(all insn patterns): Set mode,modrm and
 immediate_length attributes where 	needed. 	(cmpsi patterns):
 Compute sizes propertly for test instruction. 	(movsi, movhi patterns):
 Compute sizes propertly for eax shortcuts. 	(movstricthi_xor,
 movstrictqi_xor): New patterns. 	(andsi/andhi): Use splitters to
 generate xor instructions. 	(xorqi_ext_1): New pattern. 
 (movstricthi->movstricthi_xor peep2): New.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@34731 138bc75d-0d04-0410-961f-82ee72b054a4
---
 gcc/ChangeLog                 |   26 +
 gcc/config/i386/i386-protos.h |    3 +-
 gcc/config/i386/i386.c        |  142 ++---
 gcc/config/i386/i386.md       | 1338 +++++++++++++++++++++++++++--------------
 gcc/genattrtab.c              |    4 +
 5 files changed, 958 insertions(+), 555 deletions(-)

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 58d5b60cec9..748c5f1d572 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,29 @@
+Tue Jun 27 12:14:12 MET DST 2000  Jan Hubicka  <jh@suse.cz>
+
+	* genattrtab.c (write_attr_value): Do not abort for CONST_INT operands.
+	* i386.c (ix86_attr_length_default): Kill.
+	(ix86_attr_length_immediate_default, ix86_attr_length_address_default):
+	New.
+	* i386-protos.h (ix86_attr_length_default): Kill
+	(ix86_attr_length_immediate_default, ix86_attr_length_address_default):
+	Add prototype
+	* i386.md (attribute type): Add "test".
+	(attribute length_prefix): Kill.
+	(attribute length_opcode): Kill.
+	(attribute i387, mode, length_immediate, length_address, prefix_data16,
+	prefix_rep, prefix_0f, modrm): New.
+	(attribute length): Compute using the new attributes.
+	(attribute pent_prefix): New.
+	(attribute pent_pair): Compute using pent_prefix.
+	(all insn patterns): Set mode,modrm and immediate_length attributes where
+	needed.
+	(cmpsi patterns): Compute sizes propertly for test instruction.
+	(movsi, movhi patterns): Compute sizes propertly for eax shortcuts.
+	(movstricthi_xor, movstrictqi_xor): New patterns.
+	(andsi/andhi): Use splitters to generate xor instructions.
+	(xorqi_ext_1): New pattern.
+	(movstricthi->movstricthi_xor peep2): New.
+
 Tue Jun 27 12:03:03 MET DST 2000  Jan Hubicka  <jh@suse.cz>
 
 	* i386.md (addqi_low_1): Remove.
diff --git a/gcc/config/i386/i386-protos.h b/gcc/config/i386/i386-protos.h
index 65e3df908ef..18b258bb362 100644
--- a/gcc/config/i386/i386-protos.h
+++ b/gcc/config/i386/i386-protos.h
@@ -113,7 +113,8 @@ extern void ix86_expand_strlensi_unroll_1 PARAMS ((rtx, rtx, rtx));
 extern int ix86_address_cost PARAMS ((rtx));
 
 extern rtx assign_386_stack_local PARAMS ((enum machine_mode, int));
-extern int ix86_attr_length_default PARAMS ((rtx));
+extern int ix86_attr_length_immediate_default PARAMS ((rtx, int));
+extern int ix86_attr_length_address_default PARAMS ((rtx));
 
 extern int ix86_issue_rate PARAMS ((void));
 extern int ix86_adjust_cost PARAMS ((rtx, rtx, rtx, int));
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 0eb9d95303b..061d693c0fb 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -6156,119 +6156,59 @@ memory_address_length (addr)
   return len;
 }
 
+/* Compute default value for "length_immediate" attribute.  When SHORTFORM is set
+   expect that insn have 8bit immediate alternative.  */
 int
-ix86_attr_length_default (insn)
+ix86_attr_length_immediate_default (insn, shortform)
      rtx insn;
+     int shortform;
 {
-  enum attr_type type;
-  int len = 0, i;
-
-  type = get_attr_type (insn);
+  int len = 0;
+  int i;
   extract_insn (insn);
-  switch (type)
-    {
-    case TYPE_INCDEC:
-    case TYPE_SETCC:
-    case TYPE_ICMOV:
-    case TYPE_FMOV:
-    case TYPE_FOP:
-    case TYPE_FCMP:
-    case TYPE_FOP1:
-    case TYPE_FMUL:
-    case TYPE_FDIV:
-    case TYPE_FSGN:
-    case TYPE_FPSPC:
-    case TYPE_FCMOV:
-    case TYPE_IBR:
-      break;
-    case TYPE_STR:
-    case TYPE_CLD:
-      len = 0;
-
-    case TYPE_ALU1:
-    case TYPE_NEGNOT:
-    case TYPE_ALU:
-    case TYPE_ICMP:
-    case TYPE_IMOVX:
-    case TYPE_ISHIFT:
-    case TYPE_IMUL:
-    case TYPE_IDIV:
-    case TYPE_PUSH:
-    case TYPE_POP:
-      for (i = recog_data.n_operands - 1; i >= 0; --i)
-        if (CONSTANT_P (recog_data.operand[i]))
-	  {
-	    if (GET_CODE (recog_data.operand[i]) == CONST_INT
-		&& CONST_OK_FOR_LETTER_P (INTVAL (recog_data.operand[i]), 'K'))
-	      len += 1;
-	    else
-	      len += GET_MODE_SIZE (GET_MODE (recog_data.operand[0]));
-	  }
-      break;
-
-    case TYPE_IMOV:
-      if (CONSTANT_P (recog_data.operand[1]))
-        len += GET_MODE_SIZE (GET_MODE (recog_data.operand[0]));
-      break;
-
-    case TYPE_CALL:
-      if (constant_call_address_operand (recog_data.operand[0],
-					 GET_MODE (recog_data.operand[0])))
-	return 5;
-      break;
-
-    case TYPE_CALLV:
-      if (constant_call_address_operand (recog_data.operand[1],
-					 GET_MODE (recog_data.operand[1])))
-	return 5;
-      break;
-
-    case TYPE_LEA:
+  for (i = recog_data.n_operands - 1; i >= 0; --i)
+    if (CONSTANT_P (recog_data.operand[i]))
       {
-        /* Irritatingly, single_set doesn't work with REG_UNUSED present,
-	   as we'll get from running life_analysis during reg-stack when
-	   not optimizing.  Not that it matters anyway, now that
-	   pro_epilogue_adjust_stack uses lea, and is by design not
-	   single_set. */
-        rtx set = PATTERN (insn);
-        if (GET_CODE (set) == SET)
-	  ;
-	else if (GET_CODE (set) == PARALLEL
-		 && GET_CODE (XVECEXP (set, 0, 0)) == SET)
-	  set = XVECEXP (set, 0, 0);
-	else
+	if (len)
 	  abort ();
-
-	len += memory_address_length (SET_SRC (set));
-	goto just_opcode;
+	if (shortform
+	    && GET_CODE (recog_data.operand[i]) == CONST_INT
+	    && CONST_OK_FOR_LETTER_P (INTVAL (recog_data.operand[i]), 'K'))
+	  len = 1;
+	else
+	  {
+	    switch (get_attr_mode (insn))
+	      {
+		case MODE_QI:
+		  len+=1;
+		  break;
+		case MODE_HI:
+		  len+=2;
+		  break;
+		case MODE_SI:
+		  len+=4;
+		  break;
+		default:
+		  fatal_insn ("Unknown insn mode", insn);
+	      }
+	  }
       }
-
-    case TYPE_OTHER: 
-    case TYPE_MULTI:
-      return 15;
-
-    case TYPE_FXCH:
-      if (STACK_TOP_P (recog_data.operand[0]))
-	return 2 + (REGNO (recog_data.operand[1]) != FIRST_STACK_REG + 1);
-      else
-	return 2 + (REGNO (recog_data.operand[0]) != FIRST_STACK_REG + 1);
-
-    default:
-      abort ();
-    }
-
+  return len;
+}
+/* Compute default value for "length_address" attribute.  */
+int
+ix86_attr_length_address_default (insn)
+     rtx insn;
+{
+  int i;
+  extract_insn (insn);
   for (i = recog_data.n_operands - 1; i >= 0; --i)
     if (GET_CODE (recog_data.operand[i]) == MEM)
       {
-	len += memory_address_length (XEXP (recog_data.operand[i], 0));
+	return memory_address_length (XEXP (recog_data.operand[i], 0));
 	break;
       }
-
-just_opcode:
-  len += get_attr_length_opcode (insn);
-  len += get_attr_length_prefix (insn);
-
-  return len;
+  return 0;
 }
 
 /* Return the maximum number of instructions a cpu can issue.  */
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 7bb4a6b6a4c..f0846450294 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -84,46 +84,111 @@
 ;; A basic instruction type.  Refinements due to arguments to be
 ;; provided in other attributes.
 (define_attr "type"
-  "other,multi,alu1,negnot,alu,icmp,imov,imovx,lea,incdec,ishift,imul,idiv,ibr,setcc,push,pop,call,callv,icmov,fmov,fop,fop1,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,str,cld"
+  "other,multi,alu1,negnot,alu,icmp,test,imov,imovx,lea,incdec,ishift,imul,idiv,ibr,setcc,push,pop,call,callv,icmov,fmov,fop,fop1,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,str,cld"
   (const_string "other"))
 
-;; The (bounding maximum) length of an instruction in bytes.
-(define_attr "length" ""
-  (symbol_ref "ix86_attr_length_default(insn)"))
+;; Main data type used by the insn
+(define_attr "mode" "unknown,none,QI,HI,SI,DI,unknownfp,SF,DF,XF"
+  (const_string "unknown"))
+
+;; Set for i387 operations.
+(define_attr "i387" ""
+  (if_then_else (eq_attr "type" "fmov,fop,fop1,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch")
+    (const_int 1)
+    (const_int 0)))
+
+;; The (bounding maximum) length of an instruction immediate.
+(define_attr "length_immediate" ""
+  (cond [(eq_attr "type" "incdec,setcc,icmov,ibr,str,cld,lea,other,multi,idiv")
+	   (const_int 0)
+	 (eq_attr "i387" "1")
+	   (const_int 0)
+	 (eq_attr "type" "alu1,negnot,alu,icmp,imovx,ishift,imul,push,pop")
+	   (symbol_ref "ix86_attr_length_immediate_default(insn,1)")
+	 (eq_attr "type" "imov,test")
+	   (symbol_ref "ix86_attr_length_immediate_default(insn,0)")
+	 (eq_attr "type" "call")
+	   (if_then_else (match_operand 0 "constant_call_address_operand" "")
+	     (const_int 4)
+	     (const_int 0))
+	 (eq_attr "type" "callv")
+	   (if_then_else (match_operand 1 "constant_call_address_operand" "")
+	     (const_int 4)
+	     (const_int 0))
+	 (eq_attr "type" "ibr")
+	   (if_then_else (and (ge (minus (match_dup 0) (pc))
+				  (const_int -128))
+			      (lt (minus (match_dup 0) (pc))
+				  (const_int 124)))
+	     (const_int 1)
+	     (const_int 4))
+	 ]
+	 (symbol_ref "/* Update immediate_length and other attributes! */ abort(),1")))
 
-;; Supporting: number of prefix bytes
-(define_attr "length_prefix" ""
-  (cond [(and (eq_attr "type" "alu,alu1,negnot,icmp,imovx,incdec,ishift,imul,idiv,imov,pop")
-	      (match_operand:HI 0 "general_operand" ""))
-	   (const_int 1)
-	 (and (eq_attr "type" "push")
-	      (match_operand:HI 1 "general_operand" ""))
-	   (const_int 1)
-	]
-	(const_int 0)))
-
-;; Supporting: bytes in the opcode+modrm.
-(define_attr "length_opcode" ""
-  (cond [(eq_attr "type" "imovx,setcc,icmov")
-	   (const_int 3)
-	 (eq_attr "type" "str,cld")
-	   (const_int 1)
+;; The (bounding maximum) length of an instruction address.
+(define_attr "length_address" ""
+  (cond [(eq_attr "type" "str,cld,other,multi,fxch")
+	   (const_int 0)
+	 (and (eq_attr "type" "call")
+	      (match_operand 1 "constant_call_address_operand" ""))
+	     (const_int 0)
+	 (and (eq_attr "type" "callv")
+	      (match_operand 1 "constant_call_address_operand" ""))
+	     (const_int 0)
+	 ]
+	 (symbol_ref "ix86_attr_length_address_default (insn)")))
+
+;; Set when length prefix is used.
+(define_attr "prefix_data16" ""
+  (if_then_else (eq_attr "mode" "HI")
+    (const_int 1)
+    (const_int 0)))
+
+;; Set when string REP prefix is used.
+(define_attr "prefix_rep" "" (const_int 0))
+
+;; Set when 0f opcode prefix is used.
+(define_attr "prefix_0f" ""
+  (if_then_else (eq_attr "type" "imovx,setcc,icmov")
+    (const_int 1)
+    (const_int 0)))
+
+;; Set when modrm byte is used.
+(define_attr "modrm" ""
+  (cond [(eq_attr "type" "str,cld")
+	   (const_int 0)
+	 (eq_attr "i387" "1")
+	   (const_int 0)
          (and (eq_attr "type" "incdec")
 	      (ior (match_operand:SI 1 "register_operand" "")
 		   (match_operand:HI 1 "register_operand" "")))
-	   (const_int 1)
+	   (const_int 0)
 	 (and (eq_attr "type" "push")
 	      (not (match_operand 1 "memory_operand" "")))
-	   (const_int 1)
+	   (const_int 0)
 	 (and (eq_attr "type" "pop")
 	      (not (match_operand 0 "memory_operand" "")))
-	   (const_int 1)
+	   (const_int 0)
 	 (and (eq_attr "type" "imov")
 	      (and (match_operand 0 "register_operand" "")
 	           (match_operand 1 "immediate_operand" "")))
-	   (const_int 1)
+	   (const_int 0)
 	 ]
-	 (const_int 2)))
+	 (const_int 1)))
+
+;; The (bounding maximum) length of an instruction in bytes.
+(define_attr "length" ""
+  (cond [(eq_attr "type" "other,multi")
+	   (const_int 16)
+	 ]
+	 (plus (plus (attr "modrm")
+		     (plus (attr "prefix_0f")
+			   (plus (attr "i387")
+				 (const_int 1))))
+	       (plus (attr "prefix_rep")
+		     (plus (attr "prefix_data16")
+			   (plus (attr "length_immediate")
+				 (attr "length_address")))))))
 
 ;; The `memory' attribute is `none' if no memory is referenced, `load' or
 ;; `store' if there is a simple memory reference therein, or `unknown'
@@ -142,7 +207,7 @@
 	   (if_then_else (match_operand 0 "memory_operand" "")
 	     (const_string "both")
 	     (const_string "load"))
-	 (eq_attr "type" "icmp")
+	 (eq_attr "type" "icmp,test")
 	   (if_then_else (ior (match_operand 0 "memory_operand" "")
 			      (match_operand 1 "memory_operand" ""))
 	     (const_string "load")
@@ -169,7 +234,7 @@
 	   (const_string "store")
 	 (match_operand 1 "memory_operand" "")
 	   (const_string "load")
-	 (and (eq_attr "type" "!icmp,alu1,negnot,fop1,fsgn,imov,imovx,fmov,fcmp")
+	 (and (eq_attr "type" "!icmp,test,alu1,negnot,fop1,fsgn,imov,imovx,fmov,fcmp")
 	      (match_operand 2 "memory_operand" ""))
 	   (const_string "load")
 	 (and (eq_attr "type" "icmov")
@@ -183,7 +248,7 @@
 (define_attr "imm_disp" "false,true,unknown"
   (cond [(eq_attr "type" "other,multi")
 	   (const_string "unknown")
-	 (and (eq_attr "type" "icmp,imov")
+	 (and (eq_attr "type" "icmp,test,imov")
 	      (and (match_operand 0 "memory_displacement_operand" "")
 		   (match_operand 1 "immediate_operand" "")))
 	   (const_string "true")
@@ -208,6 +273,14 @@
 ;;
 ;; The Pentium is an in-order core with two integer pipelines.
 
+;; True for insns that behave like prefixed insns on the Pentium.
+(define_attr "pent_prefix" "false,true"
+  (if_then_else (ior (eq_attr "prefix_0f" "1")
+  		     (ior (eq_attr "prefix_data16" "1")
+			  (eq_attr "prefix_rep" "1")))
+    (const_string "true")
+    (const_string "false")))
+
 ;; Categorize how an instruction slots.
 
 ;; The non-MMX Pentium slots an instruction with prefixes on U pipe only,
@@ -219,8 +292,10 @@
 (define_attr "pent_pair" "uv,pu,pv,np"
   (cond [(eq_attr "imm_disp" "true")
 	   (const_string "np")
-	 (eq_attr "type" "alu1,alu,imov,icmp,lea,incdec")
-	   (if_then_else (eq_attr "length_prefix" "1")
+	 (ior (eq_attr "type" "alu1,alu,imov,icmp,test,lea,incdec")
+	      (and (eq_attr "type" "pop,push")
+		   (eq_attr "memory" "!both")))
+	   (if_then_else (eq_attr "pent_prefix" "true")
 	     (const_string "pu")
 	     (const_string "uv"))
 	 (eq_attr "type" "ibr")
@@ -228,11 +303,6 @@
 	 (and (eq_attr "type" "ishift")
 	      (match_operand 2 "const_int_operand" ""))
 	   (const_string "pu")
-	 (and (eq_attr "type" "pop,push")
-	      (eq_attr "memory" "!both"))
-	   (if_then_else (eq_attr "length_prefix" "1")
-	     (const_string "pu")
-	     (const_string "uv"))
 	 (and (eq_attr "type" "call")
 	      (match_operand 0 "constant_call_address_operand" ""))
 	   (const_string "pv")
@@ -631,13 +701,13 @@
 ;; The QI mode arithmetic is issued to X pipe only.
 (define_function_unit "k6_alux" 1 0
   (and (eq_attr "cpu" "k6")
-       (and (eq_attr "type" "alu,alu1,negnot,icmp,imovx,incdec")
+       (and (eq_attr "type" "alu,alu1,negnot,icmp,test,imovx,incdec")
 	    (match_operand:QI 0 "general_operand" "")))
   1 1)
 
 (define_function_unit "k6_alu" 2 0
   (and (eq_attr "cpu" "k6")
-       (eq_attr "type" "ishift,alu1,negnot,alu,icmp,imovx,incdec,setcc,lea"))
+       (eq_attr "type" "ishift,alu1,negnot,alu,icmp,test,imovx,incdec,setcc,lea"))
   1 1)
 
 (define_function_unit "k6_alu" 2 0
@@ -766,7 +836,7 @@
 
 (define_function_unit "athlon_ieu" 3 0
   (and (eq_attr "cpu" "athlon")
-       (eq_attr "type" "alu1,negnot,alu,icmp,imov,imovx,lea,incdec,ishift,ibr,call,callv,icmov,cld,pop,setcc,push,pop"))
+       (eq_attr "type" "alu1,negnot,alu,icmp,test,imov,imovx,lea,incdec,ishift,ibr,call,callv,icmov,cld,pop,setcc,push,pop"))
   1 1)
 
 (define_function_unit "athlon_ieu" 3 0
@@ -981,7 +1051,9 @@
   "@
    test{l}\\t{%0, %0|%0, %0}
    cmp{l}\\t{%1, %0|%0, %1}"
-  [(set_attr "type" "icmp")])
+  [(set_attr "type" "test,icmp")
+   (set_attr "length_immediate" "0,1")
+   (set_attr "mode" "SI")])
 
 (define_insn "cmpsi_ccno_1"
   [(set (reg:CCNO 17)
@@ -991,7 +1063,9 @@
   "@
    test{l}\\t{%0, %0|%0, %0}
    cmp{l}\\t{%1, %0|%0, %1}"
-  [(set_attr "type" "icmp")])
+  [(set_attr "type" "test,icmp")
+   (set_attr "length_immediate" "0,1")
+   (set_attr "mode" "SI")])
 
 (define_insn "cmpsi_1"
   [(set (reg:CC 17)
@@ -999,7 +1073,8 @@
 		    (match_operand:SI 1 "general_operand" "ri,mr")))]
   "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
   "cmp{l}\\t{%1, %0|%0, %1}"
-  [(set_attr "type" "icmp")])
+  [(set_attr "type" "icmp")
+   (set_attr "mode" "SI")])
 
 (define_insn "*cmphi_0"
   [(set (reg 17)
@@ -1009,7 +1084,9 @@
   "@
    test{w}\\t{%0, %0|%0, %0}
    cmp{w}\\t{%1, %0|%0, %1}"
-  [(set_attr "type" "icmp")])
+  [(set_attr "type" "test,icmp")
+   (set_attr "length_immediate" "0,1")
+   (set_attr "mode" "HI")])
 
 (define_insn "*cmphi_1"
   [(set (reg:CC 17)
@@ -1017,7 +1094,8 @@
 		    (match_operand:HI 1 "general_operand" "ri,mr")))]
   "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
   "cmp{w}\\t{%1, %0|%0, %1}"
-  [(set_attr "type" "icmp")])
+  [(set_attr "type" "icmp")
+   (set_attr "mode" "HI")])
 
 (define_insn "cmpqi_ccz_1"
   [(set (reg:CCZ 17)
@@ -1027,7 +1105,9 @@
   "@
    test{b}\\t{%0, %0|%0, %0}
    cmp{b}\\t{$0, %0|%0, 0}"
-  [(set_attr "type" "icmp")])
+  [(set_attr "type" "test,icmp")
+   (set_attr "length_immediate" "0,1")
+   (set_attr "mode" "QI")])
 
 (define_insn "*cmpqi_ccno_1"
   [(set (reg:CCNO 17)
@@ -1037,7 +1117,9 @@
   "@
    test{b}\\t{%0, %0|%0, %0}
    cmp{b}\\t{$0, %0|%0, 0}"
-  [(set_attr "type" "icmp")])
+  [(set_attr "type" "test,icmp")
+   (set_attr "length_immediate" "0,1")
+   (set_attr "mode" "QI")])
 
 (define_insn "*cmpqi_1"
   [(set (reg:CC 17)
@@ -1045,7 +1127,8 @@
 		    (match_operand:QI 1 "general_operand" "qi,mq")))]
   "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
   "cmp{b}\\t{%1, %0|%0, %1}"
-  [(set_attr "type" "icmp")])
+  [(set_attr "type" "icmp")
+   (set_attr "mode" "QI")])
 
 (define_insn "*cmpqi_ext_1"
   [(set (reg:CC 17)
@@ -1058,7 +1141,8 @@
 	      (const_int 8)) 0)))]
   ""
   "cmp{b}\\t{%h1, %0|%0, %h1}"
-  [(set_attr "type" "icmp")])
+  [(set_attr "type" "icmp")
+   (set_attr "mode" "QI")])
 
 (define_insn "*cmpqi_ext_2"
   [(set (reg 17)
@@ -1071,7 +1155,9 @@
 	  (match_operand:QI 1 "const0_operand" "n")))]
   "ix86_match_ccmode (insn, CCNOmode)"
   "test{b}\\t%h0, %h0"
-  [(set_attr "type" "icmp")])
+  [(set_attr "type" "test")
+   (set_attr "length_immediate" "0")
+   (set_attr "mode" "QI")])
 
 (define_insn "cmpqi_ext_3"
   [(set (reg:CC 17)
@@ -1084,7 +1170,8 @@
 	  (match_operand:QI 1 "general_operand" "qmn")))]
   ""
   "cmp{b}\\t{%1, %h0|%h0, %1}"
-  [(set_attr "type" "icmp")])
+  [(set_attr "type" "icmp")
+   (set_attr "mode" "QI")])
 
 (define_insn "*cmpqi_ext_4"
   [(set (reg:CC 17)
@@ -1101,7 +1188,8 @@
 	      (const_int 8)) 0)))]
   ""
   "cmp{b}\\t{%h1, %h0|%h0, %h1}"
-  [(set_attr "type" "icmp")])
+  [(set_attr "type" "icmp")
+   (set_attr "mode" "QI")])
 
 ;; These implement float point compares.
 ;; %%% See if we can get away with VOIDmode operands on the actual insns,
@@ -1177,7 +1265,8 @@
   else
     return \"ftst\;fnstsw\\t%0\";
 }"
-  [(set_attr "type" "multi")])
+  [(set_attr "type" "multi")
+   (set_attr "mode" "unknownfp")])
 
 ;; We may not use "#" to split and emit these, since the REG_DEAD notes
 ;; used to manage the reg stack popping would not be preserved.
@@ -1189,7 +1278,8 @@
 	  (match_operand:SF 1 "nonimmediate_operand" "fm")))]
   "TARGET_80387"
   "* return output_fp_compare (insn, operands, 0, 0);"
-  [(set_attr "type" "fcmp")])
+  [(set_attr "type" "fcmp")
+   (set_attr "mode" "SF")])
 
 (define_insn "*cmpfp_2_sf_1"
   [(set (match_operand:HI 0 "register_operand" "=a")
@@ -1199,7 +1289,8 @@
 	     (match_operand:SF 2 "nonimmediate_operand" "fm"))] 9))]
   "TARGET_80387"
   "* return output_fp_compare (insn, operands, 2, 0);"
-  [(set_attr "type" "fcmp")])
+  [(set_attr "type" "fcmp")
+   (set_attr "mode" "SF")])
 
 (define_insn "*cmpfp_2_df"
   [(set (reg:CCFP 18)
@@ -1208,7 +1299,8 @@
 	  (match_operand:DF 1 "nonimmediate_operand" "fm")))]
   "TARGET_80387"
   "* return output_fp_compare (insn, operands, 0, 0);"
-  [(set_attr "type" "fcmp")])
+  [(set_attr "type" "fcmp")
+   (set_attr "mode" "DF")])
 
 (define_insn "*cmpfp_2_df_1"
   [(set (match_operand:HI 0 "register_operand" "=a")
@@ -1218,7 +1310,8 @@
 	     (match_operand:DF 2 "nonimmediate_operand" "fm"))] 9))]
   "TARGET_80387"
   "* return output_fp_compare (insn, operands, 2, 0);"
-  [(set_attr "type" "multi")])
+  [(set_attr "type" "multi")
+   (set_attr "mode" "DF")])
 
 (define_insn "*cmpfp_2_xf"
   [(set (reg:CCFP 18)
@@ -1227,7 +1320,8 @@
 	  (match_operand:XF 1 "register_operand" "f")))]
   "TARGET_80387"
   "* return output_fp_compare (insn, operands, 0, 0);"
-  [(set_attr "type" "fcmp")])
+  [(set_attr "type" "fcmp")
+   (set_attr "mode" "XF")])
 
 (define_insn "*cmpfp_2_xf_1"
   [(set (match_operand:HI 0 "register_operand" "=a")
@@ -1237,7 +1331,8 @@
 	     (match_operand:XF 2 "register_operand" "f"))] 9))]
   "TARGET_80387"
   "* return output_fp_compare (insn, operands, 2, 0);"
-  [(set_attr "type" "multi")])
+  [(set_attr "type" "multi")
+   (set_attr "mode" "XF")])
 
 (define_insn "*cmpfp_2u"
   [(set (reg:CCFPU 18)
@@ -1248,7 +1343,8 @@
    && FLOAT_MODE_P (GET_MODE (operands[0]))
    && GET_MODE (operands[0]) == GET_MODE (operands[1])"
   "* return output_fp_compare (insn, operands, 0, 1);"
-  [(set_attr "type" "fcmp")])
+  [(set_attr "type" "fcmp")
+   (set_attr "mode" "unknownfp")])
 
 (define_insn "*cmpfp_2u_1"
   [(set (match_operand:HI 0 "register_operand" "=a")
@@ -1260,7 +1356,8 @@
    && FLOAT_MODE_P (GET_MODE (operands[1]))
    && GET_MODE (operands[1]) == GET_MODE (operands[2])"
   "* return output_fp_compare (insn, operands, 2, 1);"
-  [(set_attr "type" "multi")])
+  [(set_attr "type" "multi")
+   (set_attr "mode" "unknownfp")])
 
 ;; Patterns to match the SImode-in-memory ficom instructions.
 ;;
@@ -1306,6 +1403,8 @@
   "TARGET_80387"
   "fnstsw\\t%0"
   [(set_attr "length" "2")
+   (set_attr "mode" "SI")
+   (set_attr "i387" "1")
    (set_attr "ppro_uops" "few")])
 
 ;; FP compares, step 3
@@ -1318,6 +1417,7 @@
   "sahf"
   [(set_attr "length" "1")
    (set_attr "athlon_decode" "vector")
+   (set_attr "mode" "SI")
    (set_attr "ppro_uops" "one")])
 
 ;; Pentium Pro can do steps 1 through 3 in one go.
@@ -1331,6 +1431,7 @@
    && GET_MODE (operands[0]) == GET_MODE (operands[0])"
   "* return output_fp_compare (insn, operands, 1, 0);"
   [(set_attr "type" "fcmp")
+   (set_attr "mode" "unknownfp")
    (set_attr "athlon_decode" "vector")])
 
 (define_insn "*cmpfp_iu"
@@ -1342,6 +1443,7 @@
    && GET_MODE (operands[0]) == GET_MODE (operands[1])"
   "* return output_fp_compare (insn, operands, 1, 1);"
   [(set_attr "type" "fcmp")
+   (set_attr "mode" "unknownfp")
    (set_attr "athlon_decode" "vector")])
 
 ;; Move instructions.
@@ -1368,7 +1470,8 @@
 	(match_operand:SI 1 "general_no_elim_operand" "ri*m"))]
   ""
   "push{l}\\t%1"
-  [(set_attr "type" "push")])
+  [(set_attr "type" "push")
+   (set_attr "mode" "SI")])
 
 (define_insn "*pushsi2_prologue"
   [(set (match_operand:SI 0 "push_operand" "=<")
@@ -1376,7 +1479,8 @@
    (set (reg:SI 6) (reg:SI 6))]
   ""
   "push{l}\\t%1"
-  [(set_attr "type" "push")])
+  [(set_attr "type" "push")
+   (set_attr "mode" "SI")])
 
 (define_insn "*popsi1_epilogue"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=r*m")
@@ -1386,7 +1490,8 @@
    (set (reg:SI 6) (reg:SI 6))]
   ""
   "pop{l}\\t%0"
-  [(set_attr "type" "pop")])
+  [(set_attr "type" "pop")
+   (set_attr "mode" "SI")])
 
 (define_insn "popsi1"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=r*m")
@@ -1395,7 +1500,8 @@
 	(plus:SI (reg:SI 7) (const_int 4)))]
   ""
   "pop{l}\\t%0"
-  [(set_attr "type" "pop")])
+  [(set_attr "type" "pop")
+   (set_attr "mode" "SI")])
 
 (define_insn "*movsi_xor"
   [(set (match_operand:SI 0 "register_operand" "=r")
@@ -1404,7 +1510,8 @@
   "reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
   "xor{l}\\t{%0, %0|%0, %0}"
   [(set_attr "type" "alu1")
-   (set_attr "length" "2")])
+   (set_attr "mode" "SI")
+   (set_attr "length_immediate" "0")])
 
 (define_insn "*movsi_or"
   [(set (match_operand:SI 0 "register_operand" "=r")
@@ -1419,11 +1526,12 @@
   return \"or{l}\\t{%1, %0|%1, %0}\";
 }"
   [(set_attr "type" "alu1")
-   (set_attr "length" "3")])
+   (set_attr "mode" "SI")
+   (set_attr "length_immediate" "1")])
 
 (define_insn "*movsi_1"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=r,m")
-	(match_operand:SI 1 "general_operand" "rinm,rin"))]
+  [(set (match_operand:SI 0 "nonimmediate_operand" "=*a,r,*a,m")
+	(match_operand:SI 1 "general_operand" "im,rinm,rinm,rin"))]
   "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
   "*
 {
@@ -1442,7 +1550,9 @@
 		 (match_operand:SI 1 "symbolic_operand" ""))
 	      (const_string "lea")
 	   ]
-	   (const_string "imov")))])
+	   (const_string "imov")))
+   (set_attr "modrm" "0,*,0,*")
+   (set_attr "mode" "SI")])
 
 (define_insn "*swapsi"
   [(set (match_operand:SI 0 "register_operand" "+r")
@@ -1454,6 +1564,8 @@
   [(set_attr "type" "imov")
    (set_attr "pent_pair" "np")
    (set_attr "athlon_decode" "vector")
+   (set_attr "mode" "SI")
+   (set_attr "modrm" "0")
    (set_attr "ppro_uops" "few")])
 
 (define_expand "movhi"
@@ -1469,7 +1581,8 @@
   "@
    push{w}\\t{|WORD PTR }%1
    push{w}\\t%1"
-  [(set_attr "type" "push")])
+  [(set_attr "type" "push")
+   (set_attr "mode" "HI")])
 
 (define_insn "pophi1"
   [(set (match_operand:HI 0 "nonimmediate_operand" "=r*m")
@@ -1478,11 +1591,12 @@
 	(plus:SI (reg:SI 7) (const_int 2)))]
   ""
   "pop{w}\\t%0"
-  [(set_attr "type" "pop")])
+  [(set_attr "type" "pop")
+   (set_attr "mode" "HI")])
 
 (define_insn "*movhi_1"
-  [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
-	(match_operand:HI 1 "general_operand" "r,rn,rm,rn"))]
+  [(set (match_operand:HI 0 "nonimmediate_operand" "=*a,r,r,*a,r,m")
+	(match_operand:HI 1 "general_operand" "i,r,rn,rm,rm,rn"))]
   "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
   "*
 {
@@ -1493,50 +1607,43 @@
 	 though not as fast as an aligned movl.  */
       return \"movz{wl|x}\\t{%1, %k0|%k0, %1}\";
     default:
-      if (get_attr_length_prefix (insn) == 0)
+      if (get_attr_mode (insn) == MODE_SI)
         return \"mov{l}\\t{%k1, %k0|%k0, %k1}\";
       else
         return \"mov{w}\\t{%1, %0|%0, %1}\";
     }
 }"
   [(set (attr "type")
-     (cond [(and (eq_attr "alternative" "0")
+     (cond [(and (eq_attr "alternative" "0,1")
 		 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
 			  (const_int 0))
 		      (eq (symbol_ref "TARGET_HIMODE_MATH")
 			  (const_int 0))))
 	      (const_string "imov")
-	    (and (eq_attr "alternative" "1,2")
+	    (and (eq_attr "alternative" "2,3,4")
 		 (match_operand:HI 1 "aligned_operand" ""))
 	      (const_string "imov")
 	    (and (ne (symbol_ref "TARGET_MOVX")
 		     (const_int 0))
-		 (eq_attr "alternative" "0,2"))
+		 (eq_attr "alternative" "0,1,3,4"))
 	      (const_string "imovx")
 	   ]
 	   (const_string "imov")))
-    (set (attr "length_prefix")
+    (set (attr "mode")
       (cond [(eq_attr "type" "imovx")
-	       (const_string "0")
-	     (and (eq_attr "alternative" "1,2")
+	       (const_string "SI")
+	     (and (eq_attr "alternative" "2,3,4")
 		  (match_operand:HI 1 "aligned_operand" ""))
-	       (const_string "0")
-	     (and (eq_attr "alternative" "0")
+	       (const_string "SI")
+	     (and (eq_attr "alternative" "0,1")
 		  (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
 			   (const_int 0))
 		       (eq (symbol_ref "TARGET_HIMODE_MATH")
 			   (const_int 0))))
-	       (const_string "0")
-	    ]
-	    (const_string "1")))
-    ; There's no place to override just the immediate length
-    (set (attr "length")
-      (cond [(and (eq_attr "type" "imov")
-		  (and (eq_attr "length_prefix" "0")
-		       (match_operand:HI 1 "immediate_operand" "")))
-	       (const_string "5")
+	       (const_string "SI")
 	    ]
-	    (const_string "*")))])
+	    (const_string "HI")))
+   (set_attr "modrm" "0,*,*,0,*,*")])
 
 (define_insn "*swaphi_1"
   [(set (match_operand:HI 0 "register_operand" "+r")
@@ -1547,6 +1654,8 @@
   "xchg{w}\\t%1, %0"
   [(set_attr "type" "imov")
    (set_attr "pent_pair" "np")
+   (set_attr "mode" "HI")
+   (set_attr "modrm" "0")
    (set_attr "ppro_uops" "few")])
 
 (define_insn "*swaphi_2"
@@ -1557,8 +1666,9 @@
   "! TARGET_PARTIAL_REG_STALL"
   "xchg{l}\\t%k1, %k0"
   [(set_attr "type" "imov")
-   (set_attr "length_prefix" "0")
    (set_attr "pent_pair" "np")
+   (set_attr "mode" "SI")
+   (set_attr "modrm" "0")
    (set_attr "ppro_uops" "few")])
 
 (define_expand "movstricthi"
@@ -1578,7 +1688,18 @@
   "! TARGET_PARTIAL_REG_STALL
    && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
   "mov{w}\\t{%1, %0|%0, %1}"
-  [(set_attr "type" "imov")])
+  [(set_attr "type" "imov")
+   (set_attr "mode" "HI")])
+
+(define_insn "*movstricthi_xor"
+  [(set (strict_low_part (match_operand:HI 0 "register_operand" "=r"))
+	(match_operand:HI 1 "const0_operand" "i"))
+   (clobber (reg:CC 17))]
+  "reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
+  "xor{w}\\t{%0, %0|%0, %0}"
+  [(set_attr "type" "alu1")
+   (set_attr "mode" "HI")
+   (set_attr "length_immediate" "0")])
 
 (define_expand "movqi"
   [(set (match_operand:QI 0 "nonimmediate_operand" "")
@@ -1598,12 +1719,7 @@
    push{w}\\t{|word ptr }%1
    push{w}\\t%w1"
   [(set_attr "type" "push")
-   (set_attr "length_prefix" "1")
-    ; There's no place to override just the immediate length
-    (set (attr "length")
-      (if_then_else (eq_attr "length_prefix" "0")
-	(const_string "4")
-	(const_string "*")))])
+   (set_attr "mode" "HI")])
 
 (define_insn "popqi1"
   [(set (match_operand:QI 0 "nonimmediate_operand" "=r*m")
@@ -1613,7 +1729,7 @@
   ""
   "pop{w}\\t%0"
   [(set_attr "type" "pop")
-   (set_attr "length_prefix" "1")])
+   (set_attr "mode" "HI")])
 
 ;; Situation is quite tricky about when to choose full sized (SImode) move
 ;; over QImode moves.  For Q_REG -> Q_REG move we use full size only for
@@ -1638,11 +1754,7 @@
 	abort ();
       return \"movz{bl|x}\\t{%1, %k0|%k0, %1}\";
     default:
-      if (which_alternative == 4 || which_alternative == 3
-	  || (which_alternative == 1 && get_attr_length (insn) == 5)
-	  || (which_alternative == 0
-	      && ((TARGET_PARTIAL_REG_STALL && !TARGET_QIMODE_MATH)
-		  || TARGET_PARTIAL_REG_DEPENDENCY)))
+      if (get_attr_mode (insn) == MODE_SI)
         return \"mov{l}\\t{%k1, %k0|%k0, %k1}\";
       else
         return \"mov{b}\\t{%1, %0|%0, %1}\";
@@ -1663,28 +1775,28 @@
 	      (const_string "imovx")
 	   ]
 	   (const_string "imov")))
-    ; There's no place to override just the immediate length
-    (set (attr "length")
-      (cond [(and (eq_attr "type" "imov")
-		  (and (match_operand:HI 1 "immediate_operand" "")
-		       (eq_attr "alternative" "4")))
-	       (const_string "5")
-	     ;; Avoid extra dependency on partial register.
+   (set (attr "mode")
+      (cond [(eq_attr "alternative" "3,4,5")
+	       (const_string "SI")
+	     (eq_attr "alternative" "6")
+	       (const_string "QI")
+	     (eq_attr "type" "imovx")
+	       (const_string "SI")
 	     (and (eq_attr "type" "imov")
-		  (and (eq_attr "alternative" "1")
+		  (and (eq_attr "alternative" "0,1,2")
 		       (ne (symbol_ref "TARGET_PARTIAL_REG_DEPENDENCY")
 			   (const_int 0))))
-	       (const_string "5")
+	       (const_string "SI")
 	     ;; Avoid partial register stalls when not using QImode arithmetic
 	     (and (eq_attr "type" "imov")
-		  (and (eq_attr "alternative" "1")
+		  (and (eq_attr "alternative" "0,1,2")
 		       (and (ne (symbol_ref "TARGET_PARTIAL_REG_STALL")
 				(const_int 0))
 			    (eq (symbol_ref "TARGET_QIMODE_MATH")
 				(const_int 0)))))
-	       (const_string "5")
-	    ]
-	    (const_string "*")))])
+	       (const_string "SI")
+	   ]
+	   (const_string "QI")))])
 
 (define_expand "reload_outqi"
   [(parallel [(match_operand:QI 0 "" "=m")
@@ -1716,6 +1828,8 @@
   "xchg{b}\\t%1, %0"
   [(set_attr "type" "imov")
    (set_attr "pent_pair" "np")
+   (set_attr "mode" "QI")
+   (set_attr "modrm" "0")
    (set_attr "ppro_uops" "few")])
 
 (define_expand "movstrictqi"
@@ -1735,7 +1849,18 @@
   "! TARGET_PARTIAL_REG_STALL
    && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
   "mov{b}\\t{%1, %0|%0, %1}"
-  [(set_attr "type" "imov")])
+  [(set_attr "type" "imov")
+   (set_attr "mode" "QI")])
+
+(define_insn "*movstrictqi_xor"
+  [(set (strict_low_part (match_operand:QI 0 "register_operand" "=r"))
+	(match_operand:QI 1 "const0_operand" "i"))
+   (clobber (reg:CC 17))]
+  "reload_completed && (!TARGET_USE_MOV0 || optimize_size)"
+  "xor{b}\\t{%0, %0|%0, %0}"
+  [(set_attr "type" "alu1")
+   (set_attr "mode" "QI")
+   (set_attr "length_immediate" "0")])
 
 (define_insn "*movsi_extv_1"
   [(set (match_operand:SI 0 "register_operand" "=r")
@@ -1744,7 +1869,8 @@
 			 (const_int 8)))]
   ""
   "movs{bl|x}\\t{%h1, %0|%0, %h1}"
-  [(set_attr "type" "imovx")])
+  [(set_attr "type" "imovx")
+   (set_attr "mode" "SI")])
 
 (define_insn "*movhi_extv_1"
   [(set (match_operand:HI 0 "register_operand" "=r")
@@ -1753,7 +1879,8 @@
 			 (const_int 8)))]
   ""
   "movs{bl|x}\\t{%h1, %k0|%k0, %h1}"
-  [(set_attr "type" "imovx")])
+  [(set_attr "type" "imovx")
+   (set_attr "mode" "SI")])
 
 (define_insn "*movqi_extv_1"
   [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,?r")
@@ -1777,7 +1904,11 @@
 			     (ne (symbol_ref "TARGET_MOVX")
 				 (const_int 0))))
 	(const_string "imovx")
-	(const_string "imov")))])
+	(const_string "imov")))
+   (set (attr "mode")
+     (if_then_else (eq_attr "type" "imovx")
+	(const_string "SI")
+	(const_string "QI")))])
 
 (define_insn "*movsi_extzv_1"
   [(set (match_operand:SI 0 "register_operand" "=r")
@@ -1786,7 +1917,8 @@
 			 (const_int 8)))]
   ""
   "movz{bl|x}\\t{%h1, %0|%0, %h1}"
-  [(set_attr "type" "imovx")])
+  [(set_attr "type" "imovx")
+   (set_attr "mode" "SI")])
 
 (define_insn "*movqi_extzv_1"
   [(set (match_operand:QI 0 "nonimmediate_operand" "=qm,?r")
@@ -1810,7 +1942,11 @@
 			     (ne (symbol_ref "TARGET_MOVX")
 				 (const_int 0))))
 	(const_string "imovx")
-	(const_string "imov")))])
+	(const_string "imov")))
+   (set (attr "mode")
+     (if_then_else (eq_attr "type" "imovx")
+	(const_string "SI")
+	(const_string "QI")))])
 
 (define_insn "*movsi_insv_1"
   [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+q")
@@ -1819,7 +1955,8 @@
 	(match_operand:SI 1 "nonimmediate_operand" "qm"))]
   ""
   "mov{b}\\t{%b1, %h0|%h0, %b1}"
-  [(set_attr "type" "imov")])
+  [(set_attr "type" "imov")
+   (set_attr "mode" "QI")])
 
 (define_insn "*movqi_insv_2"
   [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+q")
@@ -1830,7 +1967,8 @@
 		(const_int 255)))]
   ""
   "mov{b}\\t{%h1, %h0|%h0, %h1}"
-  [(set_attr "type" "imov")])
+  [(set_attr "type" "imov")
+   (set_attr "mode" "QI")])
 
 (define_expand "movdi"
   [(set (match_operand:DI 0 "nonimmediate_operand" "")
@@ -1897,7 +2035,8 @@
       abort ();
     }
 }"
-  [(set_attr "type" "multi,push")])
+  [(set_attr "type" "multi,push")
+   (set_attr "mode" "SF,SI")])
 
 (define_split
   [(set (match_operand:SF 0 "push_operand" "")
@@ -1963,7 +2102,8 @@
       abort();
     }
 }"
-  [(set_attr "type" "fmov,fmov,fmov,imov,imov")])
+  [(set_attr "type" "fmov,fmov,fmov,imov,imov")
+   (set_attr "mode" "SF,SF,SF,SI,SI")])
 
 (define_split
   [(set (match_operand:SF 0 "nonimmediate_operand" "")
@@ -1993,7 +2133,8 @@
   else
     return \"fxch\\t%0\";
 }"
-  [(set_attr "type" "fxch")])
+  [(set_attr "type" "fxch")
+   (set_attr "mode" "SF")])
 
 (define_expand "movdf"
   [(set (match_operand:DF 0 "nonimmediate_operand" "")
@@ -2032,7 +2173,8 @@
       abort ();
     }
 }"
-  [(set_attr "type" "multi")])
+  [(set_attr "type" "multi")
+   (set_attr "mode" "DF,SI,SI")])
 
 (define_insn "*pushdf_integer"
   [(set (match_operand:DF 0 "push_operand" "=<,<")
@@ -2059,7 +2201,8 @@
       abort ();
     }
 }"
-  [(set_attr "type" "multi")])
+  [(set_attr "type" "multi")
+   (set_attr "mode" "DF,SI")])
 
 ;; %%% Kill this when call knows how to work this out.
 (define_split
@@ -2126,7 +2269,8 @@
       abort();
     }
 }"
-  [(set_attr "type" "fmov,fmov,fmov,multi,multi")])
+  [(set_attr "type" "fmov,fmov,fmov,multi,multi")
+   (set_attr "mode" "DF,DF,DF,SI,SI")])
 
 (define_insn "*movdf_integer"
   [(set (match_operand:DF 0 "nonimmediate_operand" "=f#r,m,f#r,r#f,o")
@@ -2173,7 +2317,8 @@
       abort();
     }
 }"
-  [(set_attr "type" "fmov,fmov,fmov,multi,multi")])
+  [(set_attr "type" "fmov,fmov,fmov,multi,multi")
+   (set_attr "mode" "DF,DF,DF,SI,SI")])
 
 (define_split
   [(set (match_operand:DF 0 "nonimmediate_operand" "")
@@ -2215,7 +2360,8 @@
   else
     return \"fxch\\t%0\";
 }"
-  [(set_attr "type" "fxch")])
+  [(set_attr "type" "fxch")
+   (set_attr "mode" "DF")])
 
 (define_expand "movxf"
   [(set (match_operand:XF 0 "nonimmediate_operand" "")
@@ -2256,7 +2402,8 @@
       abort ();
     }
 }"
-  [(set_attr "type" "multi")])
+  [(set_attr "type" "multi")
+   (set_attr "mode" "XF,SI,SI")])
 
 (define_insn "*pushxf_integer"
   [(set (match_operand:XF 0 "push_operand" "=<,<")
@@ -2283,7 +2430,8 @@
       abort ();
     }
 }"
-  [(set_attr "type" "multi")])
+  [(set_attr "type" "multi")
+   (set_attr "mode" "XF,SI")])
 
 (define_split
   [(set (match_operand:XF 0 "push_operand" "")
@@ -2345,7 +2493,8 @@
     }
   abort();
 }"
-  [(set_attr "type" "fmov,fmov,fmov,multi,multi")])
+  [(set_attr "type" "fmov,fmov,fmov,multi,multi")
+   (set_attr "mode" "XF,XF,XF,SI,SI")])
 
 (define_insn "*movxf_integer"
   [(set (match_operand:XF 0 "nonimmediate_operand" "=f#r,m,f#r,r#f,o")
@@ -2391,7 +2540,8 @@
     }
   abort();
 }"
-  [(set_attr "type" "fmov,fmov,fmov,multi,multi")])
+  [(set_attr "type" "fmov,fmov,fmov,multi,multi")
+   (set_attr "mode" "XF,XF,XF,SI,SI")])
 
 (define_split
   [(set (match_operand:XF 0 "nonimmediate_operand" "")
@@ -2435,7 +2585,7 @@
     return \"fxch\\t%0\";
 }"
   [(set_attr "type" "fxch")
-   (set_attr "athlon_decode" "vector")])
+   (set_attr "mode" "XF")])
 
 ;; Zero extension instructions
 
@@ -2459,7 +2609,8 @@
    (clobber (reg:CC 17))]
   "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
   "#"
-  [(set_attr "type" "alu1")])
+  [(set_attr "type" "alu1")
+   (set_attr "mode" "SI")])
 
 (define_split
   [(set (match_operand:SI 0 "register_operand" "")
@@ -2475,7 +2626,8 @@
      (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
   "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
   "movz{wl|x}\\t{%1, %0|%0, %1}"
-  [(set_attr "type" "imovx")])
+  [(set_attr "type" "imovx")
+   (set_attr "mode" "SI")])
 
 (define_expand "zero_extendqihi2"
   [(parallel
@@ -2491,7 +2643,8 @@
    (clobber (reg:CC 17))]
   "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
   "#"
-  [(set_attr "type" "alu1")])
+  [(set_attr "type" "alu1")
+   (set_attr "mode" "HI")])
 
 (define_insn "*zero_extendqihi2_movzbw_and"
   [(set (match_operand:HI 0 "register_operand" "=r,r")
@@ -2499,14 +2652,16 @@
    (clobber (reg:CC 17))]
   "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
   "#"
-  [(set_attr "type" "imovx,alu1")])
+  [(set_attr "type" "imovx,alu1")
+   (set_attr "mode" "HI")])
 
 (define_insn "*zero_extendqihi2_movzbw"
   [(set (match_operand:HI 0 "register_operand" "=r")
      (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
   "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed"
   "movz{bw|x}\\t{%1, %0|%0, %1}"
-  [(set_attr "type" "imovx")])
+  [(set_attr "type" "imovx")
+   (set_attr "mode" "HI")])
 
 ;; For the movzbw case strip only the clobber
 (define_split
@@ -2558,7 +2713,8 @@
    (clobber (reg:CC 17))]
   "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
   "#"
-  [(set_attr "type" "alu1")])
+  [(set_attr "type" "alu1")
+   (set_attr "mode" "SI")])
 
 (define_insn "*zero_extendqisi2_movzbw_and"
   [(set (match_operand:SI 0 "register_operand" "=r,r")
@@ -2566,14 +2722,16 @@
    (clobber (reg:CC 17))]
   "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
   "#"
-  [(set_attr "type" "imovx,alu1")])
+  [(set_attr "type" "imovx,alu1")
+   (set_attr "mode" "SI")])
 
 (define_insn "*zero_extendqisi2_movzbw"
   [(set (match_operand:SI 0 "register_operand" "=r")
      (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
   "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed"
   "movz{bl|x}\\t{%1, %0|%0, %1}"
-  [(set_attr "type" "imovx")])
+  [(set_attr "type" "imovx")
+   (set_attr "mode" "SI")])
 
 ;; For the movzbl case strip only the clobber
 (define_split
@@ -2618,7 +2776,8 @@
 	(zero_extend:DI (match_operand:SI 1 "general_operand" "0,rm,r")))
    (clobber (reg:CC 17))]
   ""
-  "#")
+  "#"
+  [(set_attr "mode" "SI")])
 
 (define_split 
   [(set (match_operand:DI 0 "register_operand" "")
@@ -2729,22 +2888,26 @@
   ""
   "*
 {
-  switch (get_attr_length (insn))
+  switch (get_attr_prefix_0f (insn))
     {
-    case 1:
+    case 0:
       return \"{cwtl|cwde}\";
     default:
       return \"movs{wl|x}\\t{%1,%0|%0, %1}\";
     }
 }"
   [(set_attr "type" "imovx")
-    (set (attr "length")
-      ;; movsx is short decodable while cwtl is vector decoded.
-      (cond [(and (eq_attr "cpu" "!k6")
-		  (eq_attr "alternative" "0"))
-	       (const_string "1")
-	    ]
-	    (const_string "*")))])
+   (set_attr "mode" "SI")
+   (set (attr "prefix_0f")
+     ;; movsx is short decodable while cwtl is vector decoded.
+     (if_then_else (and (eq_attr "cpu" "!k6")
+			(eq_attr "alternative" "0"))
+	(const_string "0")
+	(const_string "1")))
+   (set (attr "modrm")
+     (if_then_else (eq_attr "prefix_0f" "0")
+	(const_string "0")
+	(const_string "1")))])
 
 (define_insn "extendqihi2"
   [(set (match_operand:HI 0 "register_operand" "=*a,r")
@@ -2752,29 +2915,34 @@
   ""
   "*
 {
-  switch (get_attr_length (insn))
+  switch (get_attr_prefix_0f (insn))
     {
-    case 1:
+    case 0:
       return \"{cbtw|cbw}\";
     default:
       return \"movs{bw|x}\\t{%1,%0|%0, %1}\";
     }
 }"
   [(set_attr "type" "imovx")
-    (set (attr "length")
-      ;; movsx is short decodable while cwtl is vector decoded.
-      (cond [(and (eq_attr "cpu" "!k6")
-		  (eq_attr "alternative" "0"))
-	       (const_string "1")
-	    ]
-	    (const_string "*")))])
+   (set_attr "mode" "HI")
+   (set (attr "prefix_0f")
+     ;; movsx is short decodable while cwtl is vector decoded.
+     (if_then_else (and (eq_attr "cpu" "!k6")
+			(eq_attr "alternative" "0"))
+	(const_string "0")
+	(const_string "1")))
+   (set (attr "modrm")
+     (if_then_else (eq_attr "prefix_0f" "0")
+	(const_string "0")
+	(const_string "1")))])
 
 (define_insn "extendqisi2"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
   ""
   "movs{bl|x}\\t{%1,%0|%0, %1}"
-   [(set_attr "type" "imovx")])
+   [(set_attr "type" "imovx")
+    (set_attr "mode" "SI")])
 
 ;; Conversions between float and double.
 
@@ -2860,7 +3028,8 @@
       abort ();
     }
 }"
-  [(set_attr "type" "fmov")])
+  [(set_attr "type" "fmov")
+   (set_attr "mode" "SF,XF")])
 
 (define_expand "extendsfxf2"
   [(set (match_operand:XF 0 "nonimmediate_operand" "")
@@ -2902,7 +3071,8 @@
       abort ();
     }
 }"
-  [(set_attr "type" "fmov")])
+  [(set_attr "type" "fmov")
+   (set_attr "mode" "SF,XF")])
 
 (define_expand "extenddfxf2"
   [(set (match_operand:XF 0 "nonimmediate_operand" "")
@@ -2944,7 +3114,8 @@
       abort ();
     }
 }"
-  [(set_attr "type" "fmov")])
+  [(set_attr "type" "fmov")
+   (set_attr "mode" "DF,XF")])
 
 ;; %%% This seems bad bad news.
 ;; This cannot output into an f-reg because there is no way to be sure
@@ -2980,7 +3151,8 @@
     }
   abort ();
 }"
-  [(set_attr "type" "fmov,multi")])
+  [(set_attr "type" "fmov,multi")
+   (set_attr "mode" "SF")])
 
 (define_insn "*truncdfsf2_2"
   [(set (match_operand:SF 0 "memory_operand" "=m")
@@ -2994,7 +3166,8 @@
   else
     return \"fst%z0\\t%y0\";
 }"
-  [(set_attr "type" "fmov")])
+  [(set_attr "type" "fmov")
+   (set_attr "mode" "SF")])
 
 (define_split
   [(set (match_operand:SF 0 "memory_operand" "")
@@ -3043,7 +3216,8 @@
     }
   abort ();
 }"
-  [(set_attr "type" "fmov,multi")])
+  [(set_attr "type" "fmov,multi")
+   (set_attr "mode" "SF")])
 
 (define_insn "*truncxfsf2_2"
   [(set (match_operand:SF 0 "nonimmediate_operand" "=m")
@@ -3057,7 +3231,8 @@
   else
     return \"fst%z0\\t%y0\";
 }"
-  [(set_attr "type" "fmov")])
+  [(set_attr "type" "fmov")
+   (set_attr "mode" "SF")])
 
 (define_split
   [(set (match_operand:SF 0 "memory_operand" "")
@@ -3106,7 +3281,8 @@
     }
   abort ();
 }"
-  [(set_attr "type" "fmov,multi")])
+  [(set_attr "type" "fmov,multi")
+   (set_attr "mode" "DF")])
 
 (define_insn "*truncxfdf2_2"
   [(set (match_operand:DF 0 "memory_operand" "=m")
@@ -3120,7 +3296,8 @@
   else
     return \"fst%z0\\t%y0\";
 }"
-  [(set_attr "type" "fmov")])
+  [(set_attr "type" "fmov")
+   (set_attr "mode" "DF")])
 
 (define_split
   [(set (match_operand:DF 0 "memory_operand" "")
@@ -3324,7 +3501,9 @@
 	(unspec:HI [(reg:HI 18)] 11))]
   "TARGET_80387"
   "fnstcw\\t%0"
-  [(set_attr "length_opcode" "2")
+  [(set_attr "length" "2")
+   (set_attr "mode" "HI")
+   (set_attr "i387" "1")
    (set_attr "ppro_uops" "few")])
 
 (define_insn "x86_fldcw_1"
@@ -3332,7 +3511,9 @@
 	(unspec:HI [(match_operand:HI 0 "memory_operand" "m")] 12))]
   "TARGET_80387"
   "fldcw\\t%0"
-  [(set_attr "length_opcode" "2")
+  [(set_attr "length" "2")
+   (set_attr "mode" "HI")
+   (set_attr "i387" "1")
    (set_attr "athlon_decode" "vector")
    (set_attr "ppro_uops" "few")])
 
@@ -3349,6 +3530,7 @@
    fild%z1\\t%1
    #"
   [(set_attr "type" "fmov,multi")
+   (set_attr "mode" "SF")
    (set_attr "fp_int_src" "true")])
 
 (define_insn "floatsisf2"
@@ -3359,6 +3541,7 @@
    fild%z1\\t%1
    #"
   [(set_attr "type" "fmov,multi")
+   (set_attr "mode" "SF")
    (set_attr "fp_int_src" "true")])
 
 (define_insn "floatdisf2"
@@ -3369,6 +3552,7 @@
    fild%z1\\t%1
    #"
   [(set_attr "type" "fmov,multi")
+   (set_attr "mode" "SF")
    (set_attr "fp_int_src" "true")])
 
 (define_insn "floathidf2"
@@ -3379,6 +3563,7 @@
    fild%z1\\t%1
    #"
   [(set_attr "type" "fmov,multi")
+   (set_attr "mode" "DF")
    (set_attr "fp_int_src" "true")])
 
 (define_insn "floatsidf2"
@@ -3389,6 +3574,7 @@
    fild%z1\\t%1
    #"
   [(set_attr "type" "fmov,multi")
+   (set_attr "mode" "DF")
    (set_attr "fp_int_src" "true")])
 
 (define_insn "floatdidf2"
@@ -3399,6 +3585,7 @@
    fild%z1\\t%1
    #"
   [(set_attr "type" "fmov,multi")
+   (set_attr "mode" "DF")
    (set_attr "fp_int_src" "true")])
 
 (define_insn "floathixf2"
@@ -3409,6 +3596,7 @@
    fild%z1\\t%1
    #"
   [(set_attr "type" "fmov,multi")
+   (set_attr "mode" "XF")
    (set_attr "fp_int_src" "true")])
 
 (define_insn "floatsixf2"
@@ -3419,6 +3607,7 @@
    fild%z1\\t%1
    #"
   [(set_attr "type" "fmov,multi")
+   (set_attr "mode" "XF")
    (set_attr "fp_int_src" "true")])
 
 (define_insn "floatdixf2"
@@ -3429,6 +3618,7 @@
    fild%z1\\t%1
    #"
   [(set_attr "type" "fmov,multi")
+   (set_attr "mode" "XF")
    (set_attr "fp_int_src" "true")])
 
 ;; %%% Kill these when reload knows how to do it.
@@ -3508,7 +3698,8 @@
 	(plus:SI (match_dup 1) (match_dup 2)))]
   "ix86_binary_operator_ok (PLUS, SImode, operands)"
   "add{l}\\t{%2, %0|%0, %2}"
-  [(set_attr "type" "alu")])
+  [(set_attr "type" "alu")
+   (set_attr "mode" "SI")])
 
 (define_insn "addqi3_cc"
   [(set (reg:CC 17) (plus:CC (match_operand:QI 1 "nonimmediate_operand" "%0,0")
@@ -3517,7 +3708,8 @@
 	(plus:QI (match_dup 1) (match_dup 2)))]
   "ix86_binary_operator_ok (PLUS, QImode, operands)"
   "add{b}\\t{%2, %0|%0, %2}"
-  [(set_attr "type" "alu")])
+  [(set_attr "type" "alu")
+   (set_attr "mode" "QI")])
 
 (define_insn "*addsi3_carry"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
@@ -3529,6 +3721,7 @@
   "adc{l}\\t{%2, %0|%0, %2}"
   [(set_attr "type" "alu")
    (set_attr "pent_pair" "pu")
+   (set_attr "mode" "SI")
    (set_attr "ppro_uops" "few")])
 
 (define_expand "addsi3"
@@ -3544,7 +3737,8 @@
 	(match_operand:SI 1 "address_operand" "p"))]
   ""
   "lea{l}\\t{%a1, %0|%0, %a1}"
-  [(set_attr "type" "lea")])
+  [(set_attr "type" "lea")
+   (set_attr "mode" "SI")])
 
 (define_insn "*addsi_1"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=r,rm,r")
@@ -3597,7 +3791,8 @@
 	    (match_operand:SI 2 "incdec_operand" "")
 	      (const_string "incdec")
 	   ]
-	   (const_string "alu")))])
+	   (const_string "alu")))
+   (set_attr "mode" "SI")])
 
 ;; Convert lea to the lea pattern to avoid flags dependency.
 (define_split
@@ -3658,7 +3853,8 @@
   [(set (attr "type")
      (if_then_else (match_operand:SI 2 "incdec_operand" "")
 	(const_string "incdec")
-	(const_string "alu")))])
+	(const_string "alu")))
+   (set_attr "mode" "SI")])
 
 (define_insn "*addsi_3"
   [(set (reg:CC 17)
@@ -3672,7 +3868,8 @@
       ought but a memory context. */
    && ! pic_symbolic_operand (operands[2], VOIDmode)"
   "add{l}\\t{%2, %0|%0, %2}"
-  [(set_attr "type" "alu")])
+  [(set_attr "type" "alu")
+   (set_attr "mode" "SI")])
 
 (define_expand "addhi3"
   [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
@@ -3722,7 +3919,8 @@
   [(set (attr "type")
      (if_then_else (match_operand:HI 2 "incdec_operand" "")
 	(const_string "incdec")
-	(const_string "alu")))])
+	(const_string "alu")))
+   (set_attr "mode" "HI")])
 
 (define_insn "*addhi_2"
   [(set (reg 17)
@@ -3764,7 +3962,8 @@
   [(set (attr "type")
      (if_then_else (match_operand:HI 2 "incdec_operand" "")
 	(const_string "incdec")
-	(const_string "alu")))])
+	(const_string "alu")))
+   (set_attr "mode" "HI")])
 
 (define_insn "*addhi_3"
   [(set (reg:CC 17)
@@ -3775,7 +3974,8 @@
 	(plus:HI (match_dup 1) (match_dup 2)))]
   "ix86_binary_operator_ok (PLUS, HImode, operands)"
   "add{w}\\t{%2, %0|%0, %2}"
-  [(set_attr "type" "alu")])
+  [(set_attr "type" "alu")
+   (set_attr "mode" "HI")])
 
 (define_expand "addqi3"
   [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
@@ -3829,7 +4029,8 @@
   [(set (attr "type")
      (if_then_else (match_operand:QI 2 "incdec_operand" "")
 	(const_string "incdec")
-	(const_string "alu")))])
+	(const_string "alu")))
+   (set_attr "mode" "QI,QI,SI")])
 
 (define_insn "*addqi_2"
   [(set (reg 17)
@@ -3868,7 +4069,8 @@
   [(set (attr "type")
      (if_then_else (match_operand:QI 2 "incdec_operand" "")
 	(const_string "incdec")
-	(const_string "alu")))])
+	(const_string "alu")))
+   (set_attr "mode" "QI")])
 
 (define_insn "*addqi_3"
   [(set (reg:CC 17)
@@ -3879,7 +4081,8 @@
 	(plus:QI (match_dup 1) (match_dup 2)))]
   "ix86_binary_operator_ok (PLUS, QImode, operands)"
   "add{b}\\t{%2, %0|%0, %2}"
-  [(set_attr "type" "alu")])
+  [(set_attr "type" "alu")
+   (set_attr "mode" "QI")])
 
 
 (define_insn "addqi_ext_1"
@@ -3914,7 +4117,8 @@
   [(set (attr "type")
      (if_then_else (match_operand:QI 2 "incdec_operand" "")
 	(const_string "incdec")
-	(const_string "alu")))])
+	(const_string "alu")))
+   (set_attr "mode" "QI")])
 
 (define_insn "*addqi_ext_2"
   [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=q")
@@ -3932,7 +4136,8 @@
    (clobber (reg:CC 17))]
   ""
   "add{b}\\t{%h2, %h0|%h0, %h2}"
-  [(set_attr "type" "alu")])
+  [(set_attr "type" "alu")
+   (set_attr "mode" "QI")])
 
 ;; The patterns that match these are at the end of this file.
 
@@ -3994,7 +4199,8 @@
 	(minus:SI (match_dup 1) (match_dup 2)))]
   "ix86_binary_operator_ok (MINUS, SImode, operands)"
   "sub{l}\\t{%2, %0|%0, %2}"
-  [(set_attr "type" "alu")])
+  [(set_attr "type" "alu")
+   (set_attr "mode" "SI")])
 
 (define_insn "subsi3_carry"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
@@ -4006,7 +4212,8 @@
   "sbb{l}\\t{%2, %0|%0, %2}"
   [(set_attr "type" "alu")
    (set_attr "pent_pair" "pu")
-   (set_attr "ppro_uops" "few")])
+   (set_attr "ppro_uops" "few")
+   (set_attr "mode" "SI")])
 
 (define_expand "subsi3"
   [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "")
@@ -4023,7 +4230,8 @@
    (clobber (reg:CC 17))]
   "ix86_binary_operator_ok (MINUS, SImode, operands)"
   "sub{l}\\t{%2, %0|%0, %2}"
-  [(set_attr "type" "alu")])
+  [(set_attr "type" "alu")
+   (set_attr "mode" "SI")])
 
 (define_insn "*subsi_2"
   [(set (reg 17)
@@ -4036,7 +4244,8 @@
   "ix86_match_ccmode (insn, CCmode)
    && ix86_binary_operator_ok (MINUS, SImode, operands)"
   "sub{l}\\t{%2, %0|%0, %2}"
-  [(set_attr "type" "alu")])
+  [(set_attr "type" "alu")
+   (set_attr "mode" "SI")])
 
 (define_expand "subhi3"
   [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
@@ -4053,7 +4262,8 @@
    (clobber (reg:CC 17))]
   "ix86_binary_operator_ok (MINUS, HImode, operands)"
   "sub{w}\\t{%2, %0|%0, %2}"
-  [(set_attr "type" "alu")])
+  [(set_attr "type" "alu")
+   (set_attr "mode" "HI")])
 
 (define_insn "*subhi_2"
   [(set (reg 17)
@@ -4066,7 +4276,8 @@
   "ix86_match_ccmode (insn, CCmode)
    && ix86_binary_operator_ok (MINUS, HImode, operands)"
   "sub{w}\\t{%2, %0|%0, %2}"
-  [(set_attr "type" "alu")])
+  [(set_attr "type" "alu")
+   (set_attr "mode" "HI")])
 
 (define_expand "subqi3"
   [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
@@ -4083,7 +4294,8 @@
    (clobber (reg:CC 17))]
   "ix86_binary_operator_ok (MINUS, QImode, operands)"
   "sub{b}\\t{%2, %0|%0, %2}"
-  [(set_attr "type" "alu")])
+  [(set_attr "type" "alu")
+   (set_attr "mode" "QI")])
 
 (define_insn "*subqi_2"
   [(set (reg 17)
@@ -4096,7 +4308,8 @@
   "ix86_match_ccmode (insn, CCmode)
    && ix86_binary_operator_ok (MINUS, QImode, operands)"
   "sub{b}\\t{%2, %0|%0, %2}"
-  [(set_attr "type" "alu")])
+  [(set_attr "type" "alu")
+   (set_attr "mode" "QI")])
 
 ;; The patterns that match these are at the end of this file.
 
@@ -4154,7 +4367,8 @@
    imul{l}\\t{%2, %1, %0|%0, %1, %2}
    imul{l}\\t{%2, %0|%0, %2}"
   [(set_attr "type" "imul")
-   (set_attr "length" "2,3,2")])
+   (set_attr "prefix_0f" "0,0,1")
+   (set_attr "mode" "SI")])
 
 (define_expand "mulhi3"
   [(parallel [(set (match_operand:HI 0 "register_operand" "")
@@ -4165,17 +4379,20 @@
   "")
 
 (define_insn "*mulhi3_1"
-  [(set (match_operand:HI 0 "register_operand" "=r,r")
-	(mult:HI (match_operand:HI 1 "nonimmediate_operand" "%rm,0")
-		 (match_operand:HI 2 "general_operand" "K,g")))
+  [(set (match_operand:HI 0 "register_operand" "=r,r,r")
+	(mult:HI (match_operand:HI 1 "nonimmediate_operand" "%rm,0,0")
+		 (match_operand:HI 2 "general_operand" "K,i,mr")))
    (clobber (reg:CC 17))]
   "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM"
   ; %%% There was a note about "Assembler has weird restrictions",
   ; concerning alternative 1 when op1 == op0.  True?
   "@
    imul{w}\\t{%2, %1, %0|%0, %1, %2}
+   imul{w}\\t{%2, %1, %0|%0, %1, %2}
    imul{w}\\t{%2, %0|%0, %2}"
-  [(set_attr "type" "imul")])
+  [(set_attr "type" "imul")
+   (set_attr "prefix_0f" "0,0,1")
+   (set_attr "mode" "HI")])
 
 (define_insn "mulqi3"
   [(set (match_operand:QI 0 "register_operand" "=a")
@@ -4184,7 +4401,9 @@
    (clobber (reg:CC 17))]
   "TARGET_QIMODE_MATH"
   "mul{b}\\t%2"
-  [(set_attr "type" "imul")])
+  [(set_attr "type" "imul")
+   (set_attr "length_immediate" "0")
+   (set_attr "mode" "QI")])
 
 (define_insn "umulqihi3"
   [(set (match_operand:HI 0 "register_operand" "=a")
@@ -4193,7 +4412,9 @@
    (clobber (reg:CC 17))]
   "TARGET_QIMODE_MATH"
   "mul{b}\\t%2"
-  [(set_attr "type" "imul")])
+  [(set_attr "type" "imul")
+   (set_attr "length_immediate" "0")
+   (set_attr "mode" "QI")])
 
 (define_insn "mulqihi3"
   [(set (match_operand:HI 0 "register_operand" "=a")
@@ -4202,7 +4423,9 @@
    (clobber (reg:CC 17))]
   "TARGET_QIMODE_MATH"
   "imul{b}\\t%2"
-  [(set_attr "type" "imul")])
+  [(set_attr "type" "imul")
+   (set_attr "length_immediate" "0")
+   (set_attr "mode" "QI")])
 
 (define_insn "umulsidi3"
   [(set (match_operand:DI 0 "register_operand" "=A")
@@ -4212,7 +4435,9 @@
   ""
   "mul{l}\\t%2"
   [(set_attr "type" "imul")
-   (set_attr "ppro_uops" "few")])
+   (set_attr "ppro_uops" "few")
+   (set_attr "length_immediate" "0")
+   (set_attr "mode" "SI")])
 
 (define_insn "mulsidi3"
   [(set (match_operand:DI 0 "register_operand" "=A")
@@ -4221,7 +4446,9 @@
    (clobber (reg:CC 17))]
   ""
   "imul{l}\\t%2"
-  [(set_attr "type" "imul")])
+  [(set_attr "type" "imul")
+   (set_attr "length_immediate" "0")
+   (set_attr "mode" "SI")])
 
 (define_insn "umulsi3_highpart"
   [(set (match_operand:SI 0 "register_operand" "=d")
@@ -4237,7 +4464,9 @@
   ""
   "mul{l}\\t%2"
   [(set_attr "type" "imul")
-   (set_attr "ppro_uops" "few")])
+   (set_attr "ppro_uops" "few")
+   (set_attr "length_immediate" "0")
+   (set_attr "mode" "SI")])
 
 (define_insn "smulsi3_highpart"
   [(set (match_operand:SI 0 "register_operand" "=d")
@@ -4253,7 +4482,8 @@
   ""
   "imul{l}\\t%2"
   [(set_attr "type" "imul")
-   (set_attr "ppro_uops" "few")])
+   (set_attr "ppro_uops" "few")
+   (set_attr "mode" "SI")])
 
 ;; The patterns that match these are at the end of this file.
 
@@ -4288,6 +4518,7 @@
   "TARGET_QIMODE_MATH"
   "idiv{b}\\t%2"
   [(set_attr "type" "idiv")
+   (set_attr "mode" "QI")
    (set_attr "ppro_uops" "few")])
 
 (define_insn "udivqi3"
@@ -4298,6 +4529,7 @@
   "TARGET_QIMODE_MATH"
   "div{b}\\t%2"
   [(set_attr "type" "idiv")
+   (set_attr "mode" "QI")
    (set_attr "ppro_uops" "few")])
 
 ;; The patterns that match these are at the end of this file.
@@ -4370,6 +4602,7 @@
   ""
   "idiv{l}\\t%2"
   [(set_attr "type" "idiv")
+   (set_attr "mode" "SI")
    (set_attr "ppro_uops" "few")])
 
 (define_split
@@ -4417,7 +4650,9 @@
    (clobber (reg:CC 17))]
   "TARGET_HIMODE_MATH"
   "cwtd\;idiv{w}\\t%2"
-  [(set_attr "type" "multi")])
+  [(set_attr "type" "multi")
+   (set_attr "length_immediate" "0")
+   (set_attr "mode" "SI")])
 
 (define_insn "udivmodsi4"
   [(set (match_operand:SI 0 "register_operand" "=a")
@@ -4428,7 +4663,9 @@
    (clobber (reg:CC 17))]
   ""
   "xor{l}\\t%3, %3\;div{l}\\t%2"
-  [(set_attr "type" "multi")])
+  [(set_attr "type" "multi")
+   (set_attr "length_immediate" "0")
+   (set_attr "mode" "SI")])
 
 (define_insn "*udivmodsi4_noext"
   [(set (match_operand:SI 0 "register_operand" "=a")
@@ -4441,7 +4678,8 @@
   ""
   "div{l}\\t%2"
   [(set_attr "type" "idiv")
-   (set_attr "ppro_uops" "few")])
+   (set_attr "ppro_uops" "few")
+   (set_attr "mode" "SI")])
 
 (define_split
   [(set (match_operand:SI 0 "register_operand" "")
@@ -4483,6 +4721,7 @@
   ""
   "div{w}\\t%2"
   [(set_attr "type" "idiv")
+   (set_attr "mode" "HI")
    (set_attr "ppro_uops" "few")])
 
 ;; We can not use div/idiv for double division, because it causes
@@ -4518,7 +4757,9 @@
 	  (const_int 0)))]
   ""
   "test{l}\\t{%1, %0|%0, %1}"
-  [(set_attr "type" "icmp")
+  [(set_attr "type" "test")
+   (set_attr "modrm" "0,1,1")
+   (set_attr "mode" "SI")
    (set_attr "pent_pair" "uv,np,uv")])
 
 (define_insn "testsi_ccno_1"
@@ -4529,7 +4770,9 @@
 	  (const_int 0)))]
   ""
   "test{l}\\t{%1, %0|%0, %1}"
-  [(set_attr "type" "icmp")
+  [(set_attr "type" "test")
+   (set_attr "modrm" "0,1,1")
+   (set_attr "mode" "SI")
    (set_attr "pent_pair" "uv,np,uv")])
 
 (define_insn "*testhi_1"
@@ -4539,7 +4782,9 @@
 		 (const_int 0)))]
   "ix86_match_ccmode (insn, CCNOmode)"
   "test{w}\\t{%1, %0|%0, %1}"
-  [(set_attr "type" "icmp")
+  [(set_attr "type" "test")
+   (set_attr "modrm" "0,1,1")
+   (set_attr "mode" "HI")
    (set_attr "pent_pair" "uv,np,uv")])
 
 (define_insn "testqi_ccz_1"
@@ -4550,18 +4795,25 @@
 	  (const_int 0)))]
   ""
   "test{b}\\t{%1, %0|%0, %1}"
-  [(set_attr "type" "icmp")
+  [(set_attr "type" "test")
+   (set_attr "modrm" "0,1,1")
+   (set_attr "mode" "QI")
    (set_attr "pent_pair" "uv,np,uv")])
 
 (define_insn "testqi_ccno_1"
   [(set (reg:CCNO 17)
-        (compare:CCNO (and:QI (match_operand:QI 0 "nonimmediate_operand" "%*a,q,qm")
-			      (match_operand:QI 1 "nonmemory_operand" "n,n,qn"))
+        (compare:CCNO (and:QI (match_operand:QI 0 "nonimmediate_operand" "%*a,q,qm,r")
+			      (match_operand:QI 1 "nonmemory_operand" "n,n,qn,n"))
 		      (const_int 0)))]
   ""
-  "test{b}\\t{%1, %0|%0, %1}"
-  [(set_attr "type" "icmp")
-   (set_attr "pent_pair" "uv,np,uv")])
+  "test{b}\\t{%1, %0|%0, %1} 
+   test{b}\\t{%1, %0|%0, %1} 
+   test{b}\\t{%1, %0|%0, %1} 
+   test{l}\\t{%1, %0|%0, %1}"
+  [(set_attr "type" "test")
+   (set_attr "modrm" "0,1,1,1")
+   (set_attr "mode" "QI,QI,QI,SI")
+   (set_attr "pent_pair" "uv,np,uv,np")])
 
 (define_insn "*testqi_ext_ccz_0"
   [(set (reg:CCZ 17)
@@ -4575,7 +4827,9 @@
 	  (const_int 0)))]
   "(unsigned HOST_WIDE_INT) INTVAL (operands[1]) <= 0xff"
   "test{b}\\t{%1, %h0|%h0, %1}"
-  [(set_attr "type" "icmp")
+  [(set_attr "type" "test")
+   (set_attr "mode" "QI")
+   (set_attr "length_immediate" "1")
    (set_attr "pent_pair" "np")])
 
 (define_insn "testqi_ext_ccno_0"
@@ -4590,7 +4844,9 @@
 	  (const_int 0)))]
   "(unsigned HOST_WIDE_INT) INTVAL (operands[1]) <= 0xff"
   "test{b}\\t{%1, %h0|%h0, %1}"
-  [(set_attr "type" "icmp")
+  [(set_attr "type" "test")
+   (set_attr "mode" "QI")
+   (set_attr "length_immediate" "1")
    (set_attr "pent_pair" "np")])
 
 (define_insn "*testqi_ext_1"
@@ -4606,7 +4862,8 @@
 	  (const_int 0)))]
   "ix86_match_ccmode (insn, CCNOmode)"
   "test{b}\\t{%1, %h0|%h0, %1}"
-  [(set_attr "type" "icmp")])
+  [(set_attr "type" "test")
+   (set_attr "mode" "QI")])
 
 (define_insn "*testqi_ext_2"
   [(set (reg 17)
@@ -4623,7 +4880,8 @@
 	  (const_int 0)))]
   "ix86_match_ccmode (insn, CCNOmode)"
   "test{b}\\t{%h1, %h0|%h0, %h1}"
-  [(set_attr "type" "icmp")])
+  [(set_attr "type" "test")
+   (set_attr "mode" "QI")])
 
 ;; Combine likes to form bit extractions for some tests.  Humor it.
 (define_insn "*testqi_ext_3"
@@ -4724,30 +4982,51 @@
     default:
       if (! rtx_equal_p (operands[0], operands[1]))
 	abort ();
-
-      /* If operands[2] is an immediate, we may be able to use xor.
-	 Walk through the cases to figure out which subword we are
-	 supposed to clear.  */
-      if (REG_P (operands[0])
-	  && GET_CODE (operands[2]) == CONST_INT
-	  && (optimize_size
-	      || ! TARGET_PARTIAL_REG_STALL))
-	{
-	  if (INTVAL (operands[2]) == (HOST_WIDE_INT) 0xffff0000
-	      && optimize_size)
-	    return \"xor{w}\\t{%w0, %w0|%w0, %w0}\";
-	  if (QI_REG_P (operands[0]))
-	    {
-	      if (INTVAL (operands[2]) == (HOST_WIDE_INT) 0xffffff00)
-	        return \"xor{b}\\t{%b0, %b0|%b0, %b0}\";
-	      if (INTVAL (operands[2]) == (HOST_WIDE_INT) 0xffff00ff)
-	        return \"xor{b}\\t{%h0, %h0|%h0, %h0}\";
-	    }
-	}
       return \"and{l}\\t{%2, %0|%0, %2}\";
     }
 }"
-  [(set_attr "type" "alu,alu,imovx")])
+  [(set_attr "type" "alu,alu,imovx")
+   (set_attr "length_immediate" "*,*,0")
+   (set_attr "mode" "SI")])
+
+(define_split
+  [(set (match_operand:SI 0 "register_operand" "")
+	(and:SI (match_dup 0)
+		(const_int -65536)))
+   (clobber (reg:CC 17))]
+  "optimize_size"
+  [(set (strict_low_part (match_dup 1)) (const_int 0))]
+  "operands[1] = gen_lowpart (HImode, operands[0]);")
+
+(define_split
+  [(set (match_operand:SI 0 "register_operand" "")
+	(and:SI (match_dup 0)
+		(const_int -256)))
+   (clobber (reg:CC 17))]
+  "(optimize_size || !TARGET_PARTIAL_REG_STALL)
+   && (GET_MODE (operands[0]) == SImode || GET_MODE (operands[0]) == HImode)"
+  [(set (strict_low_part (match_dup 1)) (const_int 0))]
+  "operands[1] = gen_lowpart (QImode, operands[0]);")
+
+(define_split
+  [(set (match_operand 0 "register_operand" "")
+	(and (match_dup 0)
+	     (const_int -65281)))
+   (clobber (reg:CC 17))]
+  "(optimize_size || !TARGET_PARTIAL_REG_STALL)
+   && (GET_MODE (operands[0]) == SImode || GET_MODE (operands[0]) == HImode)"
+  [(parallel [(set (zero_extract:SI (match_dup 0)
+				    (const_int 8)
+				    (const_int 8))
+		   (xor:SI 
+		     (zero_extract:SI (match_dup 0)
+				      (const_int 8)
+				      (const_int 8))
+		     (zero_extract:SI (match_dup 0)
+				      (const_int 8)
+				      (const_int 8))))
+	      (clobber (reg:CC 17))])]
+  "operands[0] = gen_lowpart (SImode, operands[0]);")
 
 (define_insn "*andsi_2"
   [(set (reg 17)
@@ -4759,7 +5038,8 @@
   "ix86_match_ccmode (insn, CCNOmode)
    && ix86_binary_operator_ok (AND, SImode, operands)"
   "and{l}\\t{%2, %0|%0, %2}"
-  [(set_attr "type" "alu")])
+  [(set_attr "type" "alu")
+   (set_attr "mode" "SI")])
 
 (define_expand "andhi3"
   [(set (match_operand:HI 0 "nonimmediate_operand" "")
@@ -4790,25 +5070,12 @@
       if (! rtx_equal_p (operands[0], operands[1]))
 	abort ();
 
-      /* If operands[2] is an immediate, we may be able to use xor.
-	 Walk through the cases to figure out which subword we are
-	 supposed to clear.  */
-      /* %%% Do these as splits.  They get length_prefix wrong.  */
-      if (GET_CODE (operands[2]) == CONST_INT
-	  && QI_REG_P (operands[0])
-	  && (optimize_size 
-	      || ! TARGET_PARTIAL_REG_STALL))
-	{
-	  if ((INTVAL (operands[2]) & 0xffff) == 0xff00)
-	    return \"xor{b}\\t{%b0, %b0|%b0, %b0}\";
-	  if ((INTVAL (operands[2]) & 0xffff) == 0x00ff)
-	    return \"xor{b}\\t{%h0, %h0|%h0, %h0}\";
-	}
-
       return \"and{w}\\t{%2, %0|%0, %2}\";
     }
 }"
-  [(set_attr "type" "alu,alu,imovx")])
+  [(set_attr "type" "alu,alu,imovx")
+   (set_attr "length_immediate" "*,*,0")
+   (set_attr "mode" "HI,HI,SI")])
 
 (define_insn "*andhi_2"
   [(set (reg 17)
@@ -4820,7 +5087,8 @@
   "ix86_match_ccmode (insn, CCNOmode)
    && ix86_binary_operator_ok (AND, HImode, operands)"
   "and{w}\\t{%2, %0|%0, %2}"
-  [(set_attr "type" "alu")])
+  [(set_attr "type" "alu")
+   (set_attr "mode" "HI")])
 
 (define_expand "andqi3"
   [(set (match_operand:QI 0 "nonimmediate_operand" "")
@@ -4841,7 +5109,8 @@
    and{b}\\t{%2, %0|%0, %2}
    and{b}\\t{%2, %0|%0, %2}
    and{l}\\t{%k2, %k0|%k0, %k2}"
-  [(set_attr "type" "alu")])
+  [(set_attr "type" "alu")
+   (set_attr "mode" "QI,QI,SI")])
 
 (define_insn "*andqi_2"
   [(set (reg 17)
@@ -4857,7 +5126,8 @@
    and{b}\\t{%2, %0|%0, %2}
    and{b}\\t{%2, %0|%0, %2}
    and{l}\\t{%2, %k0|%k0, %2}"
-  [(set_attr "type" "alu")])
+  [(set_attr "type" "alu")
+   (set_attr "mode" "QI,QI,SI")])
 
 ;; ??? A bug in recog prevents it from recognizing a const_int as an
 ;; operand to zero_extend in andqi_ext_1.  It was checking explicitly
@@ -4876,7 +5146,9 @@
    (clobber (reg:CC 17))]
   "(unsigned HOST_WIDE_INT)INTVAL (operands[2]) <= 0xff"
   "and{b}\\t{%2, %h0|%h0, %2}"
-  [(set_attr "type" "alu")])
+  [(set_attr "type" "alu")
+   (set_attr "length_immediate" "1")
+   (set_attr "mode" "QI")])
 
 ;; Generated by peephole translating test to and.  This shows up
 ;; often in fp comparisons.
@@ -4903,7 +5175,9 @@
   "ix86_match_ccmode (insn, CCNOmode)
    && (unsigned HOST_WIDE_INT)INTVAL (operands[2]) <= 0xff"
   "and{b}\\t{%2, %h0|%h0, %2}"
-  [(set_attr "type" "alu")])
+  [(set_attr "type" "alu")
+   (set_attr "length_immediate" "1")
+   (set_attr "mode" "QI")])
 
 (define_insn "*andqi_ext_1"
   [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=q")
@@ -4919,7 +5193,9 @@
    (clobber (reg:CC 17))]
   ""
   "and{b}\\t{%2, %h0|%h0, %2}"
-  [(set_attr "type" "alu")])
+  [(set_attr "type" "alu")
+   (set_attr "length_immediate" "0")
+   (set_attr "mode" "QI")])
 
 (define_insn "*andqi_ext_2"
   [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=q")
@@ -4937,7 +5213,9 @@
    (clobber (reg:CC 17))]
   ""
   "and{b}\\t{%h2, %h0|%h0, %h2}"
-  [(set_attr "type" "alu")])
+  [(set_attr "type" "alu")
+   (set_attr "length_immediate" "0")
+   (set_attr "mode" "QI")])
 
 ;; Logical inclusive OR instructions
 
@@ -4959,7 +5237,8 @@
    (clobber (reg:CC 17))]
   "ix86_binary_operator_ok (IOR, SImode, operands)"
   "or{l}\\t{%2, %0|%0, %2}"
-  [(set_attr "type" "alu")])
+  [(set_attr "type" "alu")
+   (set_attr "mode" "SI")])
 
 (define_insn "*iorsi_2"
   [(set (reg 17)
@@ -4971,7 +5250,8 @@
   "ix86_match_ccmode (insn, CCNOmode)
    && ix86_binary_operator_ok (IOR, SImode, operands)"
   "or{l}\\t{%2, %0|%0, %2}"
-  [(set_attr "type" "alu")])
+  [(set_attr "type" "alu")
+   (set_attr "mode" "SI")])
 
 (define_expand "iorhi3"
   [(set (match_operand:HI 0 "nonimmediate_operand" "")
@@ -4988,7 +5268,8 @@
    (clobber (reg:CC 17))]
   "ix86_binary_operator_ok (IOR, HImode, operands)"
   "or{w}\\t{%2, %0|%0, %2}"
-  [(set_attr "type" "alu")])
+  [(set_attr "type" "alu")
+   (set_attr "mode" "HI")])
 
 (define_insn "*iorhi_2"
   [(set (reg 17)
@@ -5000,7 +5281,8 @@
   "ix86_match_ccmode (insn, CCNOmode)
    && ix86_binary_operator_ok (IOR, HImode, operands)"
   "or{w}\\t{%2, %0|%0, %2}"
-  [(set_attr "type" "alu")])
+  [(set_attr "type" "alu")
+   (set_attr "mode" "HI")])
 
 (define_expand "iorqi3"
   [(set (match_operand:QI 0 "nonimmediate_operand" "")
@@ -5021,7 +5303,8 @@
    or{b}\\t{%2, %0|%0, %2}
    or{b}\\t{%2, %0|%0, %2}
    or{l}\\t{%k2, %k0|%k0, %k2}"
-  [(set_attr "type" "alu")])
+  [(set_attr "type" "alu")
+   (set_attr "mode" "QI")])
 
 (define_insn "*iorqi_2"
   [(set (reg 17)
@@ -5033,7 +5316,8 @@
   "ix86_match_ccmode (insn, CCNOmode)
    && ix86_binary_operator_ok (IOR, QImode, operands)"
   "or{b}\\t{%2, %0|%0, %2}"
-  [(set_attr "type" "alu")])
+  [(set_attr "type" "alu")
+   (set_attr "mode" "QI")])
 
 ;; Logical XOR instructions
 
@@ -5055,7 +5339,8 @@
    (clobber (reg:CC 17))]
   "ix86_binary_operator_ok (XOR, SImode, operands)"
   "xor{l}\\t{%2, %0|%0, %2}"
-  [(set_attr "type" "alu")])
+  [(set_attr "type" "alu")
+   (set_attr "mode" "SI")])
 
 (define_insn "*xorsi_2"
   [(set (reg 17)
@@ -5067,7 +5352,8 @@
   "ix86_match_ccmode (insn, CCNOmode)
    && ix86_binary_operator_ok (XOR, SImode, operands)"
   "xor{l}\\t{%2, %0|%0, %2}"
-  [(set_attr "type" "alu")])
+  [(set_attr "type" "alu")
+   (set_attr "mode" "SI")])
 
 (define_expand "xorhi3"
   [(set (match_operand:HI 0 "nonimmediate_operand" "")
@@ -5084,7 +5370,8 @@
    (clobber (reg:CC 17))]
   "ix86_binary_operator_ok (XOR, HImode, operands)"
   "xor{w}\\t{%2, %0|%0, %2}"
-  [(set_attr "type" "alu")])
+  [(set_attr "type" "alu")
+   (set_attr "mode" "HI")])
 
 (define_insn "*xorhi_2"
   [(set (reg 17)
@@ -5096,7 +5383,8 @@
   "ix86_match_ccmode (insn, CCNOmode)
    && ix86_binary_operator_ok (XOR, HImode, operands)"
   "xor{w}\\t{%2, %0|%0, %2}"
-  [(set_attr "type" "alu")])
+  [(set_attr "type" "alu")
+   (set_attr "mode" "HI")])
 
 (define_expand "xorqi3"
   [(set (match_operand:QI 0 "nonimmediate_operand" "")
@@ -5117,7 +5405,26 @@
    xor{b}\\t{%2, %0|%0, %2}
    xor{b}\\t{%2, %0|%0, %2}
    xor{l}\\t{%k2, %k0|%k0, %k2}"
-  [(set_attr "type" "alu")])
+  [(set_attr "type" "alu")
+   (set_attr "mode" "QI,QI,SI")])
+
+(define_insn "xorqi_ext_1"
+  [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=q")
+			 (const_int 8)
+			 (const_int 8))
+	(xor:SI 
+	  (zero_extract:SI (match_operand 1 "ext_register_operand" "0")
+	  		   (const_int 8)
+			   (const_int 8))
+	  (zero_extract:SI (match_operand 2 "ext_register_operand" "q")
+	  		   (const_int 8)
+			   (const_int 8))))
+   (clobber (reg:CC 17))]
+  ""
+  "xor{b}\\t{%h2, %h0|%h0, %h2}"
+  [(set_attr "type" "alu")
+   (set_attr "length_immediate" "0")
+   (set_attr "mode" "QI")])
 
 (define_insn "*xorqi_cc_1"
   [(set (reg 17)
@@ -5130,7 +5437,8 @@
   "ix86_match_ccmode (insn, CCNOmode)
    && ix86_binary_operator_ok (XOR, QImode, operands)"
   "xor{b}\\t{%2, %0|%0, %2}"
-  [(set_attr "type" "alu")])
+  [(set_attr "type" "alu")
+   (set_attr "mode" "QI")])
 
 (define_insn "xorqi_cc_ext_1"
   [(set (reg:CCNO 17)
@@ -5150,7 +5458,8 @@
 	  (match_dup 2)))]
   ""
   "xor{b}\\t{%2, %h0|%h0, %2}"
-  [(set_attr "type" "alu")])
+  [(set_attr "type" "alu")
+   (set_attr "mode" "QI")])
 
 ;; Negation instructions
 
@@ -5205,7 +5514,8 @@
    (clobber (reg:CC 17))]
   "ix86_unary_operator_ok (NEG, SImode, operands)"
   "neg{l}\\t%0"
-  [(set_attr "type" "negnot")])
+  [(set_attr "type" "negnot")
+   (set_attr "mode" "SI")])
 
 ;; The problem with neg is that it does not perform (compare x 0),
 ;; it really performs (compare 0 x), which leaves us with the zero
@@ -5219,7 +5529,8 @@
 	(neg:SI (match_dup 1)))]
   "ix86_unary_operator_ok (NEG, SImode, operands)"
   "neg{l}\\t%0"
-  [(set_attr "type" "negnot")])
+  [(set_attr "type" "negnot")
+   (set_attr "mode" "SI")])
 
 (define_expand "neghi2"
   [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
@@ -5234,7 +5545,8 @@
    (clobber (reg:CC 17))]
   "ix86_unary_operator_ok (NEG, HImode, operands)"
   "neg{w}\\t%0"
-  [(set_attr "type" "negnot")])
+  [(set_attr "type" "negnot")
+   (set_attr "mode" "HI")])
 
 (define_insn "*neghi2_cmpz"
   [(set (reg:CCZ 17)
@@ -5244,7 +5556,8 @@
 	(neg:HI (match_dup 1)))]
   "ix86_unary_operator_ok (NEG, HImode, operands)"
   "neg{w}\\t%0"
-  [(set_attr "type" "negnot")])
+  [(set_attr "type" "negnot")
+   (set_attr "mode" "HI")])
 
 (define_expand "negqi2"
   [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
@@ -5259,7 +5572,8 @@
    (clobber (reg:CC 17))]
   "ix86_unary_operator_ok (NEG, QImode, operands)"
   "neg{b}\\t%0"
-  [(set_attr "type" "negnot")])
+  [(set_attr "type" "negnot")
+   (set_attr "mode" "QI")])
 
 (define_insn "*negqi2_cmpz"
   [(set (reg:CCZ 17)
@@ -5269,7 +5583,8 @@
 	(neg:QI (match_dup 1)))]
   "ix86_unary_operator_ok (NEG, QImode, operands)"
   "neg{b}\\t%0"
-  [(set_attr "type" "negnot")])
+  [(set_attr "type" "negnot")
+   (set_attr "mode" "QI")])
 
 ;; Changing of sign for FP values is doable using integer unit too.
 
@@ -5409,6 +5724,7 @@
   "TARGET_80387 && reload_completed"
   "fchs"
   [(set_attr "type" "fsgn")
+   (set_attr "mode" "SF")
    (set_attr "ppro_uops" "few")])
 
 (define_insn "*negdf2_1"
@@ -5417,6 +5733,7 @@
   "TARGET_80387 && reload_completed"
   "fchs"
   [(set_attr "type" "fsgn")
+   (set_attr "mode" "DF")
    (set_attr "ppro_uops" "few")])
 
 (define_insn "*negextendsfdf2"
@@ -5426,6 +5743,7 @@
   "TARGET_80387"
   "fchs"
   [(set_attr "type" "fsgn")
+   (set_attr "mode" "DF")
    (set_attr "ppro_uops" "few")])
 
 (define_insn "*negxf2_1"
@@ -5434,6 +5752,7 @@
   "TARGET_80387 && reload_completed"
   "fchs"
   [(set_attr "type" "fsgn")
+   (set_attr "mode" "XF")
    (set_attr "ppro_uops" "few")])
 
 (define_insn "*negextenddfxf2"
@@ -5443,6 +5762,7 @@
   "TARGET_80387"
   "fchs"
   [(set_attr "type" "fsgn")
+   (set_attr "mode" "XF")
    (set_attr "ppro_uops" "few")])
 
 (define_insn "*negextendsfxf2"
@@ -5452,6 +5772,7 @@
   "TARGET_80387"
   "fchs"
   [(set_attr "type" "fsgn")
+   (set_attr "mode" "XF")
    (set_attr "ppro_uops" "few")])
 
 ;; Absolute value instructions
@@ -5588,14 +5909,16 @@
 	(abs:SF (match_operand:SF 1 "register_operand" "0")))]
   "TARGET_80387 && reload_completed"
   "fabs"
-  [(set_attr "type" "fsgn")])
+  [(set_attr "type" "fsgn")
+   (set_attr "mode" "SF")])
 
 (define_insn "*absdf2_1"
   [(set (match_operand:DF 0 "register_operand" "=f")
 	(abs:DF (match_operand:DF 1 "register_operand" "0")))]
   "TARGET_80387 && reload_completed"
   "fabs"
-  [(set_attr "type" "fsgn")])
+  [(set_attr "type" "fsgn")
+   (set_attr "mode" "DF")])
 
 (define_insn "*absextendsfdf2"
   [(set (match_operand:DF 0 "register_operand" "=f")
@@ -5603,14 +5926,16 @@
 		  (match_operand:SF 1 "register_operand" "0"))))]
   "TARGET_80387"
   "fabs"
-  [(set_attr "type" "fsgn")])
+  [(set_attr "type" "fsgn")
+   (set_attr "mode" "DF")])
 
 (define_insn "*absxf2_1"
   [(set (match_operand:XF 0 "register_operand" "=f")
 	(abs:XF (match_operand:XF 1 "register_operand" "0")))]
   "TARGET_80387 && reload_completed"
   "fabs"
-  [(set_attr "type" "fsgn")])
+  [(set_attr "type" "fsgn")
+   (set_attr "mode" "DF")])
 
 (define_insn "*absextenddfxf2"
   [(set (match_operand:XF 0 "register_operand" "=f")
@@ -5618,7 +5943,8 @@
 	  (match_operand:DF 1 "register_operand" "0"))))]
   "TARGET_80387"
   "fabs"
-  [(set_attr "type" "fsgn")])
+  [(set_attr "type" "fsgn")
+   (set_attr "mode" "XF")])
 
 (define_insn "*absextendsfxf2"
   [(set (match_operand:XF 0 "register_operand" "=f")
@@ -5626,7 +5952,8 @@
 	  (match_operand:SF 1 "register_operand" "0"))))]
   "TARGET_80387"
   "fabs"
-  [(set_attr "type" "fsgn")])
+  [(set_attr "type" "fsgn")
+   (set_attr "mode" "XF")])
 
 ;; One complement instructions
 
@@ -5641,7 +5968,8 @@
 	(not:SI (match_operand:SI 1 "nonimmediate_operand" "0")))]
   "ix86_unary_operator_ok (NOT, SImode, operands)"
   "not{l}\\t%0"
-  [(set_attr "type" "negnot")])
+  [(set_attr "type" "negnot")
+   (set_attr "mode" "SI")])
 
 (define_insn "*one_cmplsi2_2"
   [(set (reg 17)
@@ -5652,7 +5980,8 @@
   "ix86_match_ccmode (insn, CCNOmode)
    && ix86_unary_operator_ok (NOT, SImode, operands)"
   "#"
-  [(set_attr "type" "alu1")])
+  [(set_attr "type" "alu1")
+   (set_attr "mode" "SI")])
 
 (define_split
   [(set (reg 17)
@@ -5679,7 +6008,8 @@
 	(not:HI (match_operand:HI 1 "nonimmediate_operand" "0")))]
   "ix86_unary_operator_ok (NOT, HImode, operands)"
   "not{w}\\t%0"
-  [(set_attr "type" "negnot")])
+  [(set_attr "type" "negnot")
+   (set_attr "mode" "HI")])
 
 (define_insn "*one_cmplhi2_2"
   [(set (reg 17)
@@ -5690,7 +6020,8 @@
   "ix86_match_ccmode (insn, CCNOmode)
    && ix86_unary_operator_ok (NEG, HImode, operands)"
   "#"
-  [(set_attr "type" "alu1")])
+  [(set_attr "type" "alu1")
+   (set_attr "mode" "HI")])
 
 (define_split
   [(set (reg 17)
@@ -5720,7 +6051,8 @@
   "@
    not{b}\\t%0
    not{l}\\t%k0"
-  [(set_attr "type" "negnot")])
+  [(set_attr "type" "negnot")
+   (set_attr "mode" "QI,SI")])
 
 (define_insn "*one_cmplqi2_2"
   [(set (reg 17)
@@ -5731,7 +6063,8 @@
   "ix86_match_ccmode (insn, CCNOmode)
    && ix86_unary_operator_ok (NOT, QImode, operands)"
   "#"
-  [(set_attr "type" "alu1")])
+  [(set_attr "type" "alu1")
+   (set_attr "mode" "QI")])
 
 (define_split
   [(set (reg 17)
@@ -5836,7 +6169,8 @@
    shld{l}\\t{%2, %1, %0|%0, %1, %2}
    shld{l}\\t{%s2%1, %0|%0, %1, %2}"
   [(set_attr "type" "ishift")
-   (set_attr "length_opcode" "3")
+   (set_attr "prefix_0f" "1")
+   (set_attr "mode" "SI")
    (set_attr "pent_pair" "np")
    (set_attr "athlon_decode" "vector")
    (set_attr "ppro_uops" "few")])
@@ -5939,7 +6273,8 @@
 		 (match_operand 2 "const1_operand" ""))
 	      (const_string "alu")
 	   ]
-	   (const_string "ishift")))])
+	   (const_string "ishift")))
+   (set_attr "mode" "SI")])
 
 ;; Convert lea to the lea pattern to avoid flags dependency.
 (define_split
@@ -5994,7 +6329,8 @@
 		 (match_operand 2 "const1_operand" ""))
 	      (const_string "alu")
 	   ]
-	   (const_string "ishift")))])
+	   (const_string "ishift")))
+   (set_attr "mode" "SI")])
 
 (define_expand "ashlhi3"
   [(set (match_operand:HI 0 "nonimmediate_operand" "")
@@ -6037,7 +6373,8 @@
 		 (match_operand 2 "const1_operand" ""))
 	      (const_string "alu")
 	   ]
-	   (const_string "ishift")))])
+	   (const_string "ishift")))
+   (set_attr "mode" "HI")])
 
 ;; This pattern can't accept a variable shift count, since shifts by
 ;; zero don't affect the flags.  We assume that shifts by constant
@@ -6079,7 +6416,8 @@
 		 (match_operand 2 "const1_operand" ""))
 	      (const_string "alu")
 	   ]
-	   (const_string "ishift")))])
+	   (const_string "ishift")))
+   (set_attr "mode" "HI")])
 
 (define_expand "ashlqi3"
   [(set (match_operand:QI 0 "nonimmediate_operand" "")
@@ -6141,7 +6479,8 @@
 		 (match_operand 2 "const1_operand" ""))
 	      (const_string "alu")
 	   ]
-	   (const_string "ishift")))])
+	   (const_string "ishift")))
+   (set_attr "mode" "QI,SI")])
 
 ;; This pattern can't accept a variable shift count, since shifts by
 ;; zero don't affect the flags.  We assume that shifts by constant
@@ -6183,7 +6522,8 @@
 		 (match_operand 2 "const1_operand" ""))
 	      (const_string "alu")
 	   ]
-	   (const_string "ishift")))])
+	   (const_string "ishift")))
+   (set_attr "mode" "QI")])
 
 ;; See comment above `ashldi3' about how this works.
 
@@ -6252,9 +6592,10 @@
    shrd{l}\\t{%2, %1, %0|%0, %1, %2}
    shrd{l}\\t{%s2%1, %0|%0, %1, %2}"
   [(set_attr "type" "ishift")
-   (set_attr "length_opcode" "3")
+   (set_attr "prefix_0f" "1")
    (set_attr "pent_pair" "np")
-   (set_attr "ppro_uops" "few")])
+   (set_attr "ppro_uops" "few")
+   (set_attr "mode" "SI")])
 
 (define_expand "x86_shift_adj_3"
   [(use (match_operand:SI 0 "register_operand" ""))
@@ -6295,8 +6636,11 @@
   "@
    {cltd|cdq}
    sar{l}\\t{%2, %0|%0, %2}"
-   [(set_attr "type" "imovx,ishift")
-    (set_attr "length" "1,*")])
+  [(set_attr "type" "imovx,ishift")
+   (set_attr "prefix_0f" "0,*")
+   (set_attr "length_immediate" "0,*")
+   (set_attr "modrm" "0,1")
+   (set_attr "mode" "SI")])
 
 (define_expand "ashrsi3"
   [(set (match_operand:SI 0 "nonimmediate_operand" "")
@@ -6329,7 +6673,8 @@
   "@
    sar{l}\\t{%2, %0|%0, %2}
    sar{l}\\t{%b2, %0|%0, %b2}"
-  [(set_attr "type" "ishift")])
+  [(set_attr "type" "ishift")
+   (set_attr "mode" "SI")])
 
 ;; This pattern can't accept a variable shift count, since shifts by
 ;; zero don't affect the flags.  We assume that shifts by constant
@@ -6367,7 +6712,8 @@
    && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
   "@
    sar{l}\\t{%2, %0|%0, %2}"
-  [(set_attr "type" "ishift")])
+  [(set_attr "type" "ishift")
+   (set_attr "mode" "SI")])
 
 (define_expand "ashrhi3"
   [(set (match_operand:HI 0 "nonimmediate_operand" "")
@@ -6400,7 +6746,8 @@
   "@
    sar{w}\\t{%2, %0|%0, %2}
    sar{w}\\t{%b2, %0|%0, %b2}"
-  [(set_attr "type" "ishift")])
+  [(set_attr "type" "ishift")
+   (set_attr "mode" "HI")])
 
 ;; This pattern can't accept a variable shift count, since shifts by
 ;; zero don't affect the flags.  We assume that shifts by constant
@@ -6438,7 +6785,8 @@
    && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
   "@
    sar{w}\\t{%2, %0|%0, %2}"
-  [(set_attr "type" "ishift")])
+  [(set_attr "type" "ishift")
+   (set_attr "mode" "HI")])
 
 (define_expand "ashrqi3"
   [(set (match_operand:QI 0 "nonimmediate_operand" "")
@@ -6471,7 +6819,8 @@
   "@
    sar{b}\\t{%2, %0|%0, %2}
    sar{b}\\t{%b2, %0|%0, %b2}"
-  [(set_attr "type" "ishift")])
+  [(set_attr "type" "ishift")
+   (set_attr "mode" "QI")])
 
 ;; This pattern can't accept a variable shift count, since shifts by
 ;; zero don't affect the flags.  We assume that shifts by constant
@@ -6509,7 +6858,8 @@
    && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
   "@
    sar{b}\\t{%2, %0|%0, %2}"
-  [(set_attr "type" "ishift")])
+  [(set_attr "type" "ishift")
+   (set_attr "mode" "QI")])
 
 ;; Logical shift instructions
 
@@ -6599,7 +6949,8 @@
   "@
    shr{l}\\t{%2, %0|%0, %2}
    shr{l}\\t{%b2, %0|%0, %b2}"
-  [(set_attr "type" "ishift")])
+  [(set_attr "type" "ishift")
+   (set_attr "mode" "SI")])
 
 ;; This pattern can't accept a variable shift count, since shifts by
 ;; zero don't affect the flags.  We assume that shifts by constant
@@ -6637,7 +6988,8 @@
    && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
   "@
    shr{l}\\t{%2, %0|%0, %2}"
-  [(set_attr "type" "ishift")])
+  [(set_attr "type" "ishift")
+   (set_attr "mode" "SI")])
 
 (define_expand "lshrhi3"
   [(set (match_operand:HI 0 "nonimmediate_operand" "")
@@ -6670,7 +7022,8 @@
   "@
    shr{w}\\t{%2, %0|%0, %2}
    shr{w}\\t{%b2, %0|%0, %b2}"
-  [(set_attr "type" "ishift")])
+  [(set_attr "type" "ishift")
+   (set_attr "mode" "HI")])
 
 ;; This pattern can't accept a variable shift count, since shifts by
 ;; zero don't affect the flags.  We assume that shifts by constant
@@ -6708,7 +7061,8 @@
    && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
   "@
    shr{w}\\t{%2, %0|%0, %2}"
-  [(set_attr "type" "ishift")])
+  [(set_attr "type" "ishift")
+   (set_attr "mode" "HI")])
 
 (define_expand "lshrqi3"
   [(set (match_operand:QI 0 "nonimmediate_operand" "")
@@ -6741,7 +7095,8 @@
   "@
    shr{b}\\t{%2, %0|%0, %2}
    shr{b}\\t{%b2, %0|%0, %b2}"
-  [(set_attr "type" "ishift")])
+  [(set_attr "type" "ishift")
+   (set_attr "mode" "QI")])
 
 ;; This pattern can't accept a variable shift count, since shifts by
 ;; zero don't affect the flags.  We assume that shifts by constant
@@ -6778,7 +7133,8 @@
   "ix86_match_ccmode (insn, CCNOmode)
    && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
   "shr{b}\\t{%2, %0|%0, %2}"
-  [(set_attr "type" "ishift")])
+  [(set_attr "type" "ishift")
+   (set_attr "mode" "QI")])
 
 ;; Rotate instructions
 
@@ -6813,7 +7169,8 @@
   "@
    rol{l}\\t{%2, %0|%0, %2}
    rol{l}\\t{%b2, %0|%0, %b2}"
-  [(set_attr "type" "ishift")])
+  [(set_attr "type" "ishift")
+   (set_attr "mode" "SI")])
 
 (define_expand "rotlhi3"
   [(set (match_operand:HI 0 "nonimmediate_operand" "")
@@ -6846,7 +7203,8 @@
   "@
    rol{w}\\t{%2, %0|%0, %2}
    rol{w}\\t{%b2, %0|%0, %b2}"
-  [(set_attr "type" "ishift")])
+  [(set_attr "type" "ishift")
+   (set_attr "mode" "HI")])
 
 (define_expand "rotlqi3"
   [(set (match_operand:QI 0 "nonimmediate_operand" "")
@@ -6879,7 +7237,8 @@
   "@
    rol{b}\\t{%2, %0|%0, %2}
    rol{b}\\t{%b2, %0|%0, %b2}"
-  [(set_attr "type" "ishift")])
+  [(set_attr "type" "ishift")
+   (set_attr "mode" "QI")])
 
 (define_expand "rotrsi3"
   [(set (match_operand:SI 0 "nonimmediate_operand" "")
@@ -6912,7 +7271,8 @@
   "@
    ror{l}\\t{%2, %0|%0, %2}
    ror{l}\\t{%b2, %0|%0, %b2}"
-  [(set_attr "type" "ishift")])
+  [(set_attr "type" "ishift")
+   (set_attr "mode" "SI")])
 
 (define_expand "rotrhi3"
   [(set (match_operand:HI 0 "nonimmediate_operand" "")
@@ -6945,7 +7305,8 @@
   "@
    ror{w}\\t{%2, %0|%0, %2}
    ror{w}\\t{%b2, %0|%0, %b2}"
-  [(set_attr "type" "ishift")])
+  [(set_attr "type" "ishift")
+   (set_attr "mode" "HI")])
 
 (define_expand "rotrqi3"
   [(set (match_operand:QI 0 "nonimmediate_operand" "")
@@ -6978,7 +7339,8 @@
   "@
    ror{b}\\t{%2, %0|%0, %2}
    ror{b}\\t{%b2, %0|%0, %b2}"
-  [(set_attr "type" "ishift")])
+  [(set_attr "type" "ishift")
+   (set_attr "mode" "QI")])
 
 ;; Bit set / bit test instructions
 
@@ -7161,7 +7523,8 @@
 	  [(reg 17) (const_int 0)]))]
   ""
   "set%C1\\t%0"
-  [(set_attr "type" "setcc")])
+  [(set_attr "type" "setcc")
+   (set_attr "mode" "QI")])
 
 (define_insn "*setcc_2"
   [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
@@ -7169,7 +7532,8 @@
 	  [(reg 17) (const_int 0)]))]
   ""
   "set%C1\\t%0"
-  [(set_attr "type" "setcc")])
+  [(set_attr "type" "setcc")
+   (set_attr "mode" "QI")])
 
 (define_insn "*setcc_3"
   [(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
@@ -7177,7 +7541,8 @@
 	  [(reg:CC 17) (const_int 0)]))]
   ""
   "set%C1\\t%0"
-  [(set_attr "type" "setcc")])
+  [(set_attr "type" "setcc")
+   (set_attr "mode" "QI")])
 
 (define_insn "*setcc_4"
   [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm"))
@@ -7185,7 +7550,8 @@
 	  [(reg:CC 17) (const_int 0)]))]
   ""
   "set%C1\\t%0"
-  [(set_attr "type" "setcc")])
+  [(set_attr "type" "setcc")
+   (set_attr "mode" "QI")])
 
 ;; Basic conditional jump instructions.
 ;; We ignore the overflow flag for signed branch instructions.
@@ -7339,71 +7705,71 @@
 
 (define_insn "*jcc_1"
   [(set (pc)
-	(if_then_else (match_operator 0 "no_comparison_operator"
+	(if_then_else (match_operator 1 "no_comparison_operator"
 				      [(reg 17) (const_int 0)])
-		      (label_ref (match_operand 1 "" ""))
+		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "j%C0\\t%l1"
+  "j%C1\\t%l0"
   [(set_attr "type" "ibr")
-   (set (attr "length")
-	(if_then_else (and (ge (minus (match_dup 1) (pc))
-			       (const_int -128))
-			   (lt (minus (match_dup 1) (pc))
-			       (const_int 124)))
-	  (const_int 2)
-	  (const_int 6)))])
+   (set (attr "prefix_0f")
+	   (if_then_else (and (ge (minus (match_dup 0) (pc))
+				  (const_int -128))
+			      (lt (minus (match_dup 0) (pc))
+				  (const_int 124)))
+	     (const_int 0)
+	     (const_int 1)))])
 
 (define_insn "*jcc_2"
   [(set (pc)
-	(if_then_else (match_operator 0 "no_comparison_operator"
+	(if_then_else (match_operator 1 "no_comparison_operator"
 				      [(reg 17) (const_int 0)])
 		      (pc)
-		      (label_ref (match_operand 1 "" ""))))]
+		      (label_ref (match_operand 0 "" ""))))]
   ""
-  "j%c0\\t%l1"
+  "j%c1\\t%l0"
   [(set_attr "type" "ibr")
-   (set (attr "length")
-	(if_then_else (and (ge (minus (match_dup 1) (pc))
-			       (const_int -128))
-			   (lt (minus (match_dup 1) (pc))
-			       (const_int 124)))
-	  (const_int 2)
-	  (const_int 6)))])
+   (set (attr "prefix_0f")
+	   (if_then_else (and (ge (minus (match_dup 0) (pc))
+				  (const_int -128))
+			      (lt (minus (match_dup 0) (pc))
+				  (const_int 124)))
+	     (const_int 0)
+	     (const_int 1)))])
 
 (define_insn "*jcc_3"
   [(set (pc)
-	(if_then_else (match_operator 0 "uno_comparison_operator"
+	(if_then_else (match_operator 1 "uno_comparison_operator"
 				      [(reg:CC 17) (const_int 0)])
-		      (label_ref (match_operand 1 "" ""))
+		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "j%C0\\t%l1"
+  "j%C1\\t%l0"
   [(set_attr "type" "ibr")
-   (set (attr "length")
-	(if_then_else (and (ge (minus (match_dup 1) (pc))
-			       (const_int -128))
-			   (lt (minus (match_dup 1) (pc))
-			       (const_int 124)))
-	  (const_int 2)
-	  (const_int 6)))])
+   (set (attr "prefix_0f")
+	   (if_then_else (and (ge (minus (match_dup 0) (pc))
+				  (const_int -128))
+			      (lt (minus (match_dup 0) (pc))
+				  (const_int 124)))
+	     (const_int 0)
+	     (const_int 1)))])
 
 (define_insn "*jcc_4"
   [(set (pc)
-	(if_then_else (match_operator 0 "uno_comparison_operator"
+	(if_then_else (match_operator 1 "uno_comparison_operator"
 				      [(reg:CC 17) (const_int 0)])
 		      (pc)
-		      (label_ref (match_operand 1 "" ""))))]
+		      (label_ref (match_operand 0 "" ""))))]
   ""
-  "j%c0\\t%l1"
+  "j%c1\\t%l0"
   [(set_attr "type" "ibr")
-   (set (attr "length")
-	(if_then_else (and (ge (minus (match_dup 1) (pc))
-			       (const_int -128))
-			   (lt (minus (match_dup 1) (pc))
-			       (const_int 124)))
-	  (const_int 2)
-	  (const_int 6)))])
+   (set (attr "prefix_0f")
+	   (if_then_else (and (ge (minus (match_dup 0) (pc))
+				  (const_int -128))
+			      (lt (minus (match_dup 0) (pc))
+				  (const_int 124)))
+	     (const_int 0)
+	     (const_int 1)))])
 
 ;; Define combination compare-and-branch fp compare instructions to use
 ;; during early optimization.  Splitting the operation apart early makes
@@ -7547,27 +7913,22 @@
 	(label_ref (match_operand 0 "" "")))]
   ""
   "jmp\\t%l0"
-  [(set_attr "type" "ibr")
-   (set (attr "length")
-	(if_then_else (and (ge (minus (match_dup 0) (pc))
-			       (const_int -128))
-			   (lt (minus (match_dup 0) (pc))
-			       (const_int 124)))
-	  (const_int 2)
-	  (const_int 5)))])
+  [(set_attr "type" "ibr")])
 
 (define_insn "indirect_jump"
   [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))]
   ""
   "jmp\\t%*%0"
-  [(set_attr "type" "ibr")])
+  [(set_attr "type" "ibr")
+   (set_attr "length_immediate" "0")])
 
 (define_insn "tablejump"
   [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))
    (use (label_ref (match_operand 1 "" "")))]
   "! flag_pic"
   "jmp\\t%*%0"
-  [(set_attr "type" "ibr")])
+  [(set_attr "type" "ibr")
+   (set_attr "length_immediate" "0")])
 
 ;; Implement switch statements when generating PIC code.  Switches are
 ;; implemented by `tablejump' when not using -fpic.
@@ -7640,7 +8001,8 @@
    (use (label_ref (match_operand 1 "" "")))]
   ""
   "jmp\\t%*%0"
-  [(set_attr "type" "ibr")])
+  [(set_attr "type" "ibr")
+   (set_attr "length_immediate" "0")])
 
 ;; Loop instruction
 ;;
@@ -7682,16 +8044,15 @@
   else
     return \"dec{l}\\t%1\;jne\\t%l0\";
 }"
-  [(set_attr "type" "ibr")
-   (set_attr "ppro_uops" "many")
-   (set (attr "length")
+  [(set_attr "ppro_uops" "many")
+   (set (attr "type")
 	(if_then_else (and (eq_attr "alternative" "0")
 			   (and (ge (minus (match_dup 0) (pc))
 			            (const_int -128))
 			        (lt (minus (match_dup 0) (pc))
 			            (const_int 124))))
-		      (const_int 2)
-		      (const_int 16)))])
+		      (const_string "ibr")
+		      (const_string "multi")))])
 
 (define_insn "*dbra_ge"
   [(set (pc)
@@ -7714,16 +8075,15 @@
   else
     return \"dec{l}\\t%1\;jne\\t%l0\";
 }"
-  [(set_attr "type" "ibr")
-   (set_attr "ppro_uops" "many")
-   (set (attr "length")
+  [(set (attr "type")
 	(if_then_else (and (eq_attr "alternative" "0")
 			   (and (ge (minus (match_dup 0) (pc))
 			            (const_int -128))
 			        (lt (minus (match_dup 0) (pc))
 			            (const_int 124))))
-		      (const_int 2)
-		      (const_int 16)))])
+		      (const_string "ibr")
+		      (const_string "multi")))
+   (set_attr "ppro_uops" "many")])
 
 (define_split
   [(set (pc)
@@ -8047,20 +8407,26 @@
   [(return)]
   "reload_completed"
   "ret"
-  [(set_attr "length" "1")])
+  [(set_attr "length" "1")
+   (set_attr "length_immediate" "0")
+   (set_attr "modrm" "0")])
 
 (define_insn "return_pop_internal"
   [(return)
    (use (match_operand:SI 0 "const_int_operand" ""))]
   "reload_completed"
   "ret\\t%0"
-  [(set_attr "length" "3")])
+  [(set_attr "length" "3")
+   (set_attr "length_immediate" "2")
+   (set_attr "modrm" "0")])
 
 (define_insn "nop"
   [(const_int 0)]
   ""
   "nop"
   [(set_attr "length" "1")
+   (set_attr "length_immediate" "0")
+   (set_attr "modrm" "0")
    (set_attr "ppro_uops" "one")])
 
 (define_expand "prologue"
@@ -8085,7 +8451,8 @@
   else  
     return \"add{l}\\t{%1+[.-%X2], %0|%0, %a1+(.-%X2)}\";
 }"
-  [(set_attr "type" "alu")])
+  [(set_attr "type" "alu")
+   (set_attr "mode" "SI")])
 
 (define_insn "prologue_get_pc"
   [(set (match_operand:SI 0 "register_operand" "=r")
@@ -8120,7 +8487,10 @@
    (set (reg:SI 6) (mem:SI (pre_dec:SI (reg:SI 7))))]
   ""
   "leave"
-  [(set_attr "length" "1")
+  [(set_attr "length_immediate" "0")
+   (set_attr "length" "1")
+   (set_attr "modrm" "0")
+   (set_attr "modrm" "0")
    (set_attr "athlon_decode" "vector")
    (set_attr "ppro_uops" "few")])
 
@@ -8219,7 +8589,7 @@
 	(unspec:SI [(match_dup 1)] 5))]
   ""
   "bsf{l}\\t{%1, %0|%0, %1}"
-  [(set_attr "length_opcode" "3")
+  [(set_attr "prefix_0f" "1")
    (set_attr "ppro_uops" "few")])
 
 ;; ffshi2 is not useful -- 4 word prefix ops are needed, which is larger
@@ -8245,7 +8615,8 @@
   [(set (attr "type") 
         (if_then_else (match_operand:SF 3 "mult_operator" "") 
            (const_string "fmul")
-           (const_string "fop")))])
+           (const_string "fop")))
+   (set_attr "mode" "SF")])
 
 (define_insn "*fop_df_comm"
   [(set (match_operand:DF 0 "register_operand" "=f")
@@ -8257,7 +8628,8 @@
   [(set (attr "type") 
         (if_then_else (match_operand:DF 3 "mult_operator" "") 
            (const_string "fmul")
-           (const_string "fop")))])
+           (const_string "fop")))
+   (set_attr "mode" "DF")])
 
 (define_insn "*fop_xf_comm"
   [(set (match_operand:XF 0 "register_operand" "=f")
@@ -8269,7 +8641,8 @@
   [(set (attr "type") 
         (if_then_else (match_operand:XF 3 "mult_operator" "") 
            (const_string "fmul")
-           (const_string "fop")))])
+           (const_string "fop")))
+   (set_attr "mode" "XF")])
 
 (define_insn "*fop_sf_1"
   [(set (match_operand:SF 0 "register_operand" "=f,f")
@@ -8286,7 +8659,8 @@
                (match_operand:SF 3 "div_operator" "") 
                  (const_string "fdiv")
               ]
-              (const_string "fop")))])
+              (const_string "fop")))
+   (set_attr "mode" "SF")])
 
 (define_insn "*fop_sf_2"
   [(set (match_operand:SF 0 "register_operand" "=f,f")
@@ -8303,7 +8677,8 @@
               ]
               (const_string "fop")))
    (set_attr "fp_int_src" "true")
-   (set_attr "ppro_uops" "many")])
+   (set_attr "ppro_uops" "many")
+   (set_attr "mode" "SI")])
 
 (define_insn "*fop_sf_3"
   [(set (match_operand:SF 0 "register_operand" "=f,f")
@@ -8320,7 +8695,8 @@
               ]
               (const_string "fop")))
    (set_attr "fp_int_src" "true")
-   (set_attr "ppro_uops" "many")])
+   (set_attr "ppro_uops" "many")
+   (set_attr "mode" "SI")])
 
 (define_insn "*fop_df_1"
   [(set (match_operand:DF 0 "register_operand" "=f,f")
@@ -8337,7 +8713,8 @@
                (match_operand:DF 3 "div_operator" "") 
                  (const_string "fdiv")
               ]
-              (const_string "fop")))])
+              (const_string "fop")))
+   (set_attr "mode" "DF")])
 
 (define_insn "*fop_df_2"
   [(set (match_operand:DF 0 "register_operand" "=f,f")
@@ -8354,7 +8731,8 @@
               ]
               (const_string "fop")))
    (set_attr "fp_int_src" "true")
-   (set_attr "ppro_uops" "many")])
+   (set_attr "ppro_uops" "many")
+   (set_attr "mode" "SI")])
 
 (define_insn "*fop_df_3"
   [(set (match_operand:DF 0 "register_operand" "=f,f")
@@ -8371,7 +8749,8 @@
               ]
               (const_string "fop")))
    (set_attr "fp_int_src" "true")
-   (set_attr "ppro_uops" "many")])
+   (set_attr "ppro_uops" "many")
+   (set_attr "mode" "SI")])
 
 (define_insn "*fop_df_4"
   [(set (match_operand:DF 0 "register_operand" "=f,f")
@@ -8387,7 +8766,8 @@
                (match_operand:DF 3 "div_operator" "") 
                  (const_string "fdiv")
               ]
-              (const_string "fop")))])
+              (const_string "fop")))
+   (set_attr "mode" "SF")])
 
 (define_insn "*fop_df_5"
   [(set (match_operand:DF 0 "register_operand" "=f,f")
@@ -8403,7 +8783,8 @@
                (match_operand:DF 3 "div_operator" "") 
                  (const_string "fdiv")
               ]
-              (const_string "fop")))])
+              (const_string "fop")))
+   (set_attr "mode" "SF")])
 
 (define_insn "*fop_xf_1"
   [(set (match_operand:XF 0 "register_operand" "=f,f")
@@ -8419,7 +8800,8 @@
                (match_operand:XF 3 "div_operator" "") 
                  (const_string "fdiv")
               ]
-              (const_string "fop")))])
+              (const_string "fop")))
+   (set_attr "mode" "XF")])
 
 (define_insn "*fop_xf_2"
   [(set (match_operand:XF 0 "register_operand" "=f,f")
@@ -8436,6 +8818,7 @@
               ]
               (const_string "fop")))
    (set_attr "fp_int_src" "true")
+   (set_attr "mode" "SI")
    (set_attr "ppro_uops" "many")])
 
 (define_insn "*fop_xf_3"
@@ -8453,6 +8836,7 @@
               ]
               (const_string "fop")))
    (set_attr "fp_int_src" "true")
+   (set_attr "mode" "SI")
    (set_attr "ppro_uops" "many")])
 
 (define_insn "*fop_xf_4"
@@ -8468,7 +8852,8 @@
                (match_operand:XF 3 "div_operator" "") 
                  (const_string "fdiv")
               ]
-              (const_string "fop")))])
+              (const_string "fop")))
+   (set_attr "mode" "SF")])
 
 (define_insn "*fop_xf_5"
   [(set (match_operand:XF 0 "register_operand" "=f,f")
@@ -8484,7 +8869,8 @@
                (match_operand:XF 3 "div_operator" "") 
                  (const_string "fdiv")
               ]
-              (const_string "fop")))])
+              (const_string "fop")))
+   (set_attr "mode" "SF")])
 
 (define_insn "*fop_xf_6"
   [(set (match_operand:XF 0 "register_operand" "=f,f")
@@ -8499,7 +8885,8 @@
                (match_operand:XF 3 "div_operator" "") 
                  (const_string "fdiv")
               ]
-              (const_string "fop")))])
+              (const_string "fop")))
+   (set_attr "mode" "DF")])
 
 (define_insn "*fop_xf_7"
   [(set (match_operand:XF 0 "register_operand" "=f,f")
@@ -8515,7 +8902,8 @@
                (match_operand:XF 3 "div_operator" "") 
                  (const_string "fdiv")
               ]
-              (const_string "fop")))])
+              (const_string "fop")))
+   (set_attr "mode" "DF")])
 
 (define_split
   [(set (match_operand 0 "register_operand" "")
@@ -8555,6 +8943,7 @@
   "! TARGET_NO_FANCY_MATH_387 && TARGET_80387"
   "fsqrt"
   [(set_attr "type" "fpspc")
+   (set_attr "mode" "SF")
    (set_attr "athlon_decode" "direct")])
 
 (define_insn "sqrtdf2"
@@ -8564,6 +8953,7 @@
    && (TARGET_IEEE_FP || flag_fast_math) "
   "fsqrt"
   [(set_attr "type" "fpspc")
+   (set_attr "mode" "DF")
    (set_attr "athlon_decode" "direct")])
 
 (define_insn "*sqrtextendsfdf2"
@@ -8573,6 +8963,7 @@
   "! TARGET_NO_FANCY_MATH_387 && TARGET_80387"
   "fsqrt"
   [(set_attr "type" "fpspc")
+   (set_attr "mode" "DF")
    (set_attr "athlon_decode" "direct")])
 
 (define_insn "sqrtxf2"
@@ -8582,6 +8973,7 @@
    && (TARGET_IEEE_FP || flag_fast_math) "
   "fsqrt"
   [(set_attr "type" "fpspc")
+   (set_attr "mode" "XF")
    (set_attr "athlon_decode" "direct")])
 
 (define_insn "*sqrtextenddfxf2"
@@ -8591,6 +8983,7 @@
   "! TARGET_NO_FANCY_MATH_387 && TARGET_80387"
   "fsqrt"
   [(set_attr "type" "fpspc")
+   (set_attr "mode" "XF")
    (set_attr "athlon_decode" "direct")])
 
 (define_insn "*sqrtextendsfxf2"
@@ -8600,6 +8993,7 @@
   "! TARGET_NO_FANCY_MATH_387 && TARGET_80387"
   "fsqrt"
   [(set_attr "type" "fpspc")
+   (set_attr "mode" "XF")
    (set_attr "athlon_decode" "direct")])
 
 (define_insn "sindf2"
@@ -8607,14 +9001,16 @@
 	(unspec:DF [(match_operand:DF 1 "register_operand" "0")] 1))]
   "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && flag_fast_math"
   "fsin"
-  [(set_attr "type" "fpspc")])
+  [(set_attr "type" "fpspc")
+   (set_attr "mode" "DF")])
 
 (define_insn "sinsf2"
   [(set (match_operand:SF 0 "register_operand" "=f")
 	(unspec:SF [(match_operand:SF 1 "register_operand" "0")] 1))]
   "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && flag_fast_math"
   "fsin"
-  [(set_attr "type" "fpspc")])
+  [(set_attr "type" "fpspc")
+   (set_attr "mode" "SF")])
 
 (define_insn "*sinextendsfdf2"
   [(set (match_operand:DF 0 "register_operand" "=f")
@@ -8622,28 +9018,32 @@
 		     (match_operand:SF 1 "register_operand" "0"))] 1))]
   "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && flag_fast_math"
   "fsin"
-  [(set_attr "type" "fpspc")])
+  [(set_attr "type" "fpspc")
+   (set_attr "mode" "DF")])
 
 (define_insn "sinxf2"
   [(set (match_operand:XF 0 "register_operand" "=f")
 	(unspec:XF [(match_operand:XF 1 "register_operand" "0")] 1))]
   "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && flag_fast_math"
   "fsin"
-  [(set_attr "type" "fpspc")])
+  [(set_attr "type" "fpspc")
+   (set_attr "mode" "XF")])
 
 (define_insn "cosdf2"
   [(set (match_operand:DF 0 "register_operand" "=f")
 	(unspec:DF [(match_operand:DF 1 "register_operand" "0")] 2))]
   "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && flag_fast_math"
   "fcos"
-  [(set_attr "type" "fpspc")])
+  [(set_attr "type" "fpspc")
+   (set_attr "mode" "DF")])
 
 (define_insn "cossf2"
   [(set (match_operand:SF 0 "register_operand" "=f")
 	(unspec:SF [(match_operand:SF 1 "register_operand" "0")] 2))]
   "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && flag_fast_math"
   "fcos"
-  [(set_attr "type" "fpspc")])
+  [(set_attr "type" "fpspc")
+   (set_attr "mode" "SF")])
 
 (define_insn "*cosextendsfdf2"
   [(set (match_operand:DF 0 "register_operand" "=f")
@@ -8651,14 +9051,16 @@
 		     (match_operand:SF 1 "register_operand" "0"))] 2))]
   "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && flag_fast_math"
   "fcos"
-  [(set_attr "type" "fpspc")])
+  [(set_attr "type" "fpspc")
+   (set_attr "mode" "DF")])
 
 (define_insn "cosxf2"
   [(set (match_operand:XF 0 "register_operand" "=f")
 	(unspec:XF [(match_operand:XF 1 "register_operand" "0")] 2))]
   "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && flag_fast_math"
   "fcos"
-  [(set_attr "type" "fpspc")])
+  [(set_attr "type" "fpspc")
+   (set_attr "mode" "XF")])
 
 ;; Block operation instructions
 
@@ -8930,6 +9332,7 @@
   "TARGET_SINGLE_STRINGOP || optimize_size"
   "movsl"
   [(set_attr "type" "str")
+   (set_attr "mode" "SI")
    (set_attr "memory" "both")])
 
 (define_insn "strmovhi_1"
@@ -8946,7 +9349,7 @@
   "movsw"
   [(set_attr "type" "str")
    (set_attr "memory" "both")
-   (set_attr "length_prefix" "1")])
+   (set_attr "mode" "HI")])
 
 (define_insn "strmovqi_1"
   [(set (mem:QI (match_operand:SI 2 "register_operand" "0"))
@@ -8961,7 +9364,8 @@
   "TARGET_SINGLE_STRINGOP || optimize_size"
   "movsb"
   [(set_attr "type" "str")
-   (set_attr "memory" "both")])
+   (set_attr "memory" "both")
+   (set_attr "mode" "QI")])
 
 ;; It might seem that operands 3 & 4 could use predicate register_operand.
 ;; But strength reduction might offset the MEM expression.  So we let
@@ -8982,8 +9386,9 @@
   ""
   "rep\;movsl|rep movsd"
   [(set_attr "type" "str")
-   (set_attr "length_prefix" "1")
-   (set_attr "memory" "both")])
+   (set_attr "prefix_rep" "1")
+   (set_attr "memory" "both")
+   (set_attr "mode" "SI")])
 
 (define_insn "rep_movqi"
   [(set (match_operand:SI 2 "register_operand" "=c") (const_int 0))
@@ -8998,8 +9403,9 @@
   ""
   "rep\;movsb|rep movsb"
   [(set_attr "type" "str")
-   (set_attr "length_prefix" "1")
-   (set_attr "memory" "both")])
+   (set_attr "prefix_rep" "1")
+   (set_attr "memory" "both")
+   (set_attr "mode" "SI")])
 
 (define_expand "clrstrsi"
    [(use (match_operand:BLK 0 "memory_operand" ""))
@@ -9227,7 +9633,8 @@
   "TARGET_SINGLE_STRINGOP || optimize_size"
   "stosl"
   [(set_attr "type" "str")
-   (set_attr "memory" "store")])
+   (set_attr "memory" "store")
+   (set_attr "mode" "SI")])
 
 (define_insn "strsethi_1"
   [(set (mem:HI (match_operand:SI 1 "register_operand" "0"))
@@ -9240,7 +9647,7 @@
   "stosw"
   [(set_attr "type" "str")
    (set_attr "memory" "store")
-   (set_attr "length_prefix" "1")])
+   (set_attr "mode" "HI")])
 
 (define_insn "strsetqi_1"
   [(set (mem:QI (match_operand:SI 1 "register_operand" "0"))
@@ -9252,7 +9659,8 @@
   "TARGET_SINGLE_STRINGOP || optimize_size"
   "stosb"
   [(set_attr "type" "str")
-   (set_attr "memory" "store")])
+   (set_attr "memory" "store")
+   (set_attr "mode" "QI")])
 
 ;; It might seem that operand 0 could use predicate register_operand.
 ;; But strength reduction might offset the MEM expression.  So we let
@@ -9271,8 +9679,9 @@
   ""
   "rep\;stosl|rep stosd"
   [(set_attr "type" "str")
-   (set_attr "length_prefix" "1")
-   (set_attr "memory" "store")])
+   (set_attr "prefix_rep" "1")
+   (set_attr "memory" "store")
+   (set_attr "mode" "SI")])
 
 (define_insn "rep_stosqi"
   [(set (match_operand:SI 1 "register_operand" "=c") (const_int 0))
@@ -9286,8 +9695,9 @@
   ""
   "rep\;stosb|rep stosb"
   [(set_attr "type" "str")
-   (set_attr "length_prefix" "1")
-   (set_attr "memory" "store")])
+   (set_attr "prefix_rep" "1")
+   (set_attr "memory" "store")
+   (set_attr "mode" "QI")])
 
 (define_expand "cmpstrsi"
   [(set (match_operand:SI 0 "register_operand" "")
@@ -9376,7 +9786,8 @@
   ""
   "repz{\;| }cmpsb"
   [(set_attr "type" "str")
-   (set_attr "length_prefix" "1")])
+   (set_attr "mode" "QI")
+   (set_attr "prefix_rep" "1")])
 
 ;; The same, but the count is not known to not be zero.
 
@@ -9396,7 +9807,8 @@
   ""
   "repz{\;| }cmpsb"
   [(set_attr "type" "str")
-   (set_attr "length_prefix" "1")])
+   (set_attr "mode" "QI")
+   (set_attr "prefix_rep" "1")])
 
 (define_expand "strlensi"
   [(set (match_operand:SI 0 "register_operand" "")
@@ -9478,7 +9890,8 @@
   ""
   "repnz{\;| }scasb"
   [(set_attr "type" "str")
-   (set_attr "length_prefix" "1")])
+   (set_attr "mode" "QI")
+   (set_attr "prefix_rep" "1")])
 
 ;; Conditional move instructions.
 
@@ -9507,7 +9920,8 @@
   [(set_attr "type" "alu")
    (set_attr "memory" "none")
    (set_attr "imm_disp" "false")
-   (set_attr "length" "2")])
+   (set_attr "mode" "SI")
+   (set_attr "length_immediate" "0")])
 
 (define_insn "*movsicc_noc"
   [(set (match_operand:SI 0 "register_operand" "=r,r")
@@ -9520,7 +9934,8 @@
   "@
    cmov%C1\\t{%2, %0|%0, %2}
    cmov%c1\\t{%3, %0|%0, %3}"
-  [(set_attr "type" "icmov")])
+  [(set_attr "type" "icmov")
+   (set_attr "mode" "SI")])
 
 (define_insn "*movsicc_c"
   [(set (match_operand:SI 0 "register_operand" "=r,r")
@@ -9533,7 +9948,8 @@
   "@
    cmov%C1\\t{%2, %0|%0, %2}
    cmov%c1\\t{%3, %0|%0, %3}"
-  [(set_attr "type" "icmov")])
+  [(set_attr "type" "icmov")
+   (set_attr "mode" "SI")])
 
 (define_expand "movhicc"
   [(set (match_operand:HI 0 "register_operand" "")
@@ -9554,7 +9970,8 @@
   "@
    cmov%C1\\t{%2, %0|%0, %2}
    cmov%c1\\t{%3, %0|%0, %3}"
-  [(set_attr "type" "icmov")])
+  [(set_attr "type" "icmov")
+   (set_attr "mode" "HI")])
 
 (define_insn "*movhicc_c"
   [(set (match_operand:HI 0 "register_operand" "=r,r")
@@ -9567,7 +9984,8 @@
   "@
    cmov%C1\\t{%2, %0|%0, %2}
    cmov%c1\\t{%3, %0|%0, %3}"
-  [(set_attr "type" "icmov")])
+  [(set_attr "type" "icmov")
+   (set_attr "mode" "HI")])
 
 (define_expand "movsfcc"
   [(set (match_operand:SF 0 "register_operand" "")
@@ -9587,7 +10005,8 @@
   "@
    fcmov%F1\\t{%2, %0|%0, %2}
    fcmov%f1\\t{%3, %0|%0, %3}"
-  [(set_attr "type" "fcmov")])
+  [(set_attr "type" "fcmov")
+   (set_attr "mode" "SF")])
 
 (define_expand "movdfcc"
   [(set (match_operand:DF 0 "register_operand" "")
@@ -9607,7 +10026,8 @@
   "@
    fcmov%F1\\t{%2, %0|%0, %2}
    fcmov%f1\\t{%3, %0|%0, %3}"
-  [(set_attr "type" "fcmov")])
+  [(set_attr "type" "fcmov")
+   (set_attr "mode" "DF")])
 
 (define_expand "movxfcc"
   [(set (match_operand:XF 0 "register_operand" "")
@@ -9627,7 +10047,8 @@
   "@
    fcmov%F1\\t{%2, %0|%0, %2}
    fcmov%f1\\t{%3, %0|%0, %3}"
-  [(set_attr "type" "fcmov")])
+  [(set_attr "type" "fcmov")
+   (set_attr "mode" "XF")])
 
 ;; Misc patterns (?)
 
@@ -9681,7 +10102,8 @@
 	       (match_operand:SI 2 "const0_operand" "")
 		 (const_string "imov")
 	      ]
-	      (const_string "lea")))])
+	      (const_string "lea")))
+   (set_attr "mode" "SI")])
 
 (define_insn "allocate_stack_worker"
   [(unspec:SI [(match_operand:SI 0 "register_operand" "a")] 3)
@@ -10180,6 +10602,16 @@
 	      (clobber (reg:CC 17))])]
   "operands[0] = gen_rtx_REG (SImode, true_regnum (operands[0]));")
 
+(define_peephole2
+  [(set (strict_low_part (match_operand 0 "register_operand" ""))
+	(const_int 0))]
+  "(GET_MODE (operands[0]) == QImode
+    || GET_MODE (operands[0]) == HImode)
+   && (! TARGET_USE_MOV0 || optimize_size)
+   && peep2_regno_dead_p (0, FLAGS_REG)"
+  [(parallel [(set (strict_low_part (match_dup 0)) (const_int 0))
+	      (clobber (reg:CC 17))])])
+
 ;; For HI and SI modes, or $-1,reg is smaller than mov $-1,reg.
 (define_peephole2
   [(set (match_operand 0 "register_operand" "")
diff --git a/gcc/genattrtab.c b/gcc/genattrtab.c
index db4634d9863..5b4d656d0b1 100644
--- a/gcc/genattrtab.c
+++ b/gcc/genattrtab.c
@@ -5310,6 +5310,10 @@ write_attr_value (attr, value)
       write_attr_valueq (attr, XSTR (value, 0));
       break;
 
+    case CONST_INT:
+      printf (HOST_WIDE_INT_PRINT_DEC, INTVAL (value));
+      break;
+
     case SYMBOL_REF:
       fputs (XSTR (value, 0), stdout);
       break;
-- 
2.11.0